From 4ded097bed1663b307f353a0dd6ad931e345834e Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Fri, 20 Oct 2017 11:41:17 +1100 Subject: constify more dcache.h inlined helpers. const struct pointers in commit f0d3b3ded999 ("constify dcache.c inlined helpers where possible"). This patch allows 'const' in a couple that were added since then. Signed-off-by: NeilBrown Signed-off-by: Al Viro --- include/linux/dcache.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/dcache.h b/include/linux/dcache.h index ed1a7cf6923a..4cc3d891ea03 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h @@ -358,7 +358,7 @@ static inline void dont_mount(struct dentry *dentry) extern void __d_lookup_done(struct dentry *); -static inline int d_in_lookup(struct dentry *dentry) +static inline int d_in_lookup(const struct dentry *dentry) { return dentry->d_flags & DCACHE_PAR_LOOKUP; } @@ -486,7 +486,7 @@ static inline bool d_really_is_positive(const struct dentry *dentry) return dentry->d_inode != NULL; } -static inline int simple_positive(struct dentry *dentry) +static inline int simple_positive(const struct dentry *dentry) { return d_really_is_positive(dentry) && !d_unhashed(dentry); } -- cgit v1.2.3 From 6909e29fdefbb7aa643021279daef6ed10c81528 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 12 Oct 2017 16:06:11 +0200 Subject: kdb: use __ktime_get_real_seconds instead of __current_kernel_time kdb is the only user of the __current_kernel_time() interface, which is not y2038 safe and should be removed at some point. The kdb code also goes to great lengths to print the time in a human-readable format from 'struct timespec', again using a non-y2038-safe re-implementation of the generic time_to_tm() code. Using __current_kernel_time() here is necessary since the regular accessors that require a sequence lock might hang when called during the xtime update. However, this is safe in the particular case since kdb is only interested in the tv_sec field that is updated atomically. In order to make this y2038-safe, I'm converting the code to the generic time64_to_tm helper, but that introduces the problem that we have no interface like __current_kernel_time() that provides a 64-bit timestamp in a lockless, safe and architecture-independent way. I have multiple ideas for how to solve that: - __ktime_get_real_seconds() is lockless, but can return incorrect results on 32-bit architectures in the special case that we are in the process of changing the time across the epoch, either during the timer tick that overflows the seconds in 2038, or while calling settimeofday. - ktime_get_real_fast_ns() would work in this context, but does require a call into the clocksource driver to return a high-resolution timestamp. This may have undesired side-effects in the debugger, since we want to limit the interactions with the rest of the kernel. - Adding a ktime_get_real_fast_seconds() based on tk_fast_mono plus tkr->base_real without the tk_clock_read() delta. Not sure about the value of adding yet another interface here. - Changing the existing ktime_get_real_seconds() to use tk_fast_mono on 32-bit architectures rather than xtime_sec. I think this could work, but am not entirely sure if this is an improvement. I picked the first of those for simplicity here. It's technically not correct but probably good enough as the time is only used for the debugging output and the race will likely never be hit in practice. Another downside is having to move the declaration into a public header file. Let me know if anyone has a different preference. Cc: Andy Shevchenko Link: https://patchwork.kernel.org/patch/9775309/ Signed-off-by: Arnd Bergmann Signed-off-by: Jason Wessel --- include/linux/timekeeping.h | 1 + kernel/debug/kdb/kdb_main.c | 45 +++++--------------------------------- kernel/time/timekeeping_internal.h | 2 -- 3 files changed, 6 insertions(+), 42 deletions(-) (limited to 'include/linux') diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index b17bcce58bc4..588a0e4b1ab9 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -31,6 +31,7 @@ struct timespec64 get_monotonic_coarse64(void); extern void getrawmonotonic64(struct timespec64 *ts); extern void ktime_get_ts64(struct timespec64 *ts); extern time64_t ktime_get_seconds(void); +extern time64_t __ktime_get_real_seconds(void); extern time64_t ktime_get_real_seconds(void); extern int __getnstimeofday64(struct timespec64 *tv); diff --git a/kernel/debug/kdb/kdb_main.c b/kernel/debug/kdb/kdb_main.c index c8146d53ca67..69e70f4021fe 100644 --- a/kernel/debug/kdb/kdb_main.c +++ b/kernel/debug/kdb/kdb_main.c @@ -2479,41 +2479,6 @@ static int kdb_kill(int argc, const char **argv) return 0; } -struct kdb_tm { - int tm_sec; /* seconds */ - int tm_min; /* minutes */ - int tm_hour; /* hours */ - int tm_mday; /* day of the month */ - int tm_mon; /* month */ - int tm_year; /* year */ -}; - -static void kdb_gmtime(struct timespec *tv, struct kdb_tm *tm) -{ - /* This will work from 1970-2099, 2100 is not a leap year */ - static int mon_day[] = { 31, 29, 31, 30, 31, 30, 31, - 31, 30, 31, 30, 31 }; - memset(tm, 0, sizeof(*tm)); - tm->tm_sec = tv->tv_sec % (24 * 60 * 60); - tm->tm_mday = tv->tv_sec / (24 * 60 * 60) + - (2 * 365 + 1); /* shift base from 1970 to 1968 */ - tm->tm_min = tm->tm_sec / 60 % 60; - tm->tm_hour = tm->tm_sec / 60 / 60; - tm->tm_sec = tm->tm_sec % 60; - tm->tm_year = 68 + 4*(tm->tm_mday / (4*365+1)); - tm->tm_mday %= (4*365+1); - mon_day[1] = 29; - while (tm->tm_mday >= mon_day[tm->tm_mon]) { - tm->tm_mday -= mon_day[tm->tm_mon]; - if (++tm->tm_mon == 12) { - tm->tm_mon = 0; - ++tm->tm_year; - mon_day[1] = 28; - } - } - ++tm->tm_mday; -} - /* * Most of this code has been lifted from kernel/timer.c::sys_sysinfo(). * I cannot call that code directly from kdb, it has an unconditional @@ -2539,8 +2504,8 @@ static void kdb_sysinfo(struct sysinfo *val) */ static int kdb_summary(int argc, const char **argv) { - struct timespec now; - struct kdb_tm tm; + time64_t now; + struct tm tm; struct sysinfo val; if (argc) @@ -2554,9 +2519,9 @@ static int kdb_summary(int argc, const char **argv) kdb_printf("domainname %s\n", init_uts_ns.name.domainname); kdb_printf("ccversion %s\n", __stringify(CCVERSION)); - now = __current_kernel_time(); - kdb_gmtime(&now, &tm); - kdb_printf("date %04d-%02d-%02d %02d:%02d:%02d " + now = __ktime_get_real_seconds(); + time64_to_tm(now, 0, &tm); + kdb_printf("date %04ld-%02d-%02d %02d:%02d:%02d " "tz_minuteswest %d\n", 1900+tm.tm_year, tm.tm_mon+1, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec, diff --git a/kernel/time/timekeeping_internal.h b/kernel/time/timekeeping_internal.h index fdbeeb02dde9..cf5c0828ee31 100644 --- a/kernel/time/timekeeping_internal.h +++ b/kernel/time/timekeeping_internal.h @@ -31,6 +31,4 @@ static inline u64 clocksource_delta(u64 now, u64 last, u64 mask) } #endif -extern time64_t __ktime_get_real_seconds(void); - #endif /* _TIMEKEEPING_INTERNAL_H */ -- cgit v1.2.3 From 5b698be0497d8be986e2050e9b1c145b2e0603c2 Mon Sep 17 00:00:00 2001 From: Meghana Madhyastha Date: Wed, 24 Jan 2018 16:34:07 +0000 Subject: video: backlight: Add helpers to enable and disable backlight MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add helper functions backlight_enable and backlight_disable to enable/disable a backlight device. These helper functions can then be used by different drm and tinydrm drivers to avoid repetition of code and also to enforce a uniform and consistent way to enable/disable a backlight device. Acked-by: Daniel Thompson Reviewed-by: Noralf Trønnes Reviewed-by: Sean Paul Signed-off-by: Meghana Madhyastha Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/39b5bf0a02008a8072d910bdf8231c431e9ef504.1516810725.git.meghana.madhyastha@gmail.com --- include/linux/backlight.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'include/linux') diff --git a/include/linux/backlight.h b/include/linux/backlight.h index af7003548593..ace825e2ca2d 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -130,6 +130,38 @@ static inline int backlight_update_status(struct backlight_device *bd) return ret; } +/** + * backlight_enable - Enable backlight + * @bd: the backlight device to enable + */ +static inline int backlight_enable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + bd->props.state &= ~BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + +/** + * backlight_disable - Disable backlight + * @bd: the backlight device to disable + */ +static inline int backlight_disable(struct backlight_device *bd) +{ + if (!bd) + return 0; + + bd->props.power = FB_BLANK_POWERDOWN; + bd->props.fb_blank = FB_BLANK_POWERDOWN; + bd->props.state |= BL_CORE_FBBLANK; + + return backlight_update_status(bd); +} + extern struct backlight_device *backlight_device_register(const char *name, struct device *dev, void *devdata, const struct backlight_ops *ops, const struct backlight_properties *props); -- cgit v1.2.3 From c2adda27d202fa8f70a5d6e8b0c12b449c8868b8 Mon Sep 17 00:00:00 2001 From: Meghana Madhyastha Date: Wed, 24 Jan 2018 16:35:30 +0000 Subject: video: backlight: Add of_find_backlight helper in backlight.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add of_find_backlight, a helper function which is a generic version of tinydrm_of_find_backlight that can be used by other drivers to avoid repetition of code and simplify things. Acked-by: Daniel Thompson Reviewed-by: Noralf Trønnes Reviewed-by: Sean Paul Reviewed-by: Thierry Reding Signed-off-by: Meghana Madhyastha Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/116d160ba78be2e6dcbdcb6855622bce67da9472.1516810725.git.meghana.madhyastha@gmail.com --- drivers/video/backlight/backlight.c | 43 +++++++++++++++++++++++++++++++++++++ include/linux/backlight.h | 19 ++++++++++++++++ 2 files changed, 62 insertions(+) (limited to 'include/linux') diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c index 8049e7656daa..553bf5c4807c 100644 --- a/drivers/video/backlight/backlight.c +++ b/drivers/video/backlight/backlight.c @@ -580,6 +580,49 @@ struct backlight_device *of_find_backlight_by_node(struct device_node *node) EXPORT_SYMBOL(of_find_backlight_by_node); #endif +/** + * of_find_backlight - Get backlight device + * @dev: Device + * + * This function looks for a property named 'backlight' on the DT node + * connected to @dev and looks up the backlight device. + * + * Call backlight_put() to drop the reference on the backlight device. + * + * Returns: + * A pointer to the backlight device if found. + * Error pointer -EPROBE_DEFER if the DT property is set, but no backlight + * device is found. + * NULL if there's no backlight property. + */ +struct backlight_device *of_find_backlight(struct device *dev) +{ + struct backlight_device *bd = NULL; + struct device_node *np; + + if (!dev) + return NULL; + + if (IS_ENABLED(CONFIG_OF) && dev->of_node) { + np = of_parse_phandle(dev->of_node, "backlight", 0); + if (np) { + bd = of_find_backlight_by_node(np); + of_node_put(np); + if (!bd) + return ERR_PTR(-EPROBE_DEFER); + /* + * Note: gpio_backlight uses brightness as + * power state during probe + */ + if (!bd->props.brightness) + bd->props.brightness = bd->props.max_brightness; + } + } + + return bd; +} +EXPORT_SYMBOL(of_find_backlight); + static void __exit backlight_class_exit(void) { class_destroy(backlight_class); diff --git a/include/linux/backlight.h b/include/linux/backlight.h index ace825e2ca2d..ddc9bade4fb2 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -162,6 +162,16 @@ static inline int backlight_disable(struct backlight_device *bd) return backlight_update_status(bd); } +/** + * backlight_put - Drop backlight reference + * @bd: the backlight device to put + */ +static inline void backlight_put(struct backlight_device *bd) +{ + if (bd) + put_device(&bd->dev); +} + extern struct backlight_device *backlight_device_register(const char *name, struct device *dev, void *devdata, const struct backlight_ops *ops, const struct backlight_properties *props); @@ -205,4 +215,13 @@ of_find_backlight_by_node(struct device_node *node) } #endif +#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) +struct backlight_device *of_find_backlight(struct device *dev); +#else +static inline struct backlight_device *of_find_backlight(struct device *dev) +{ + return NULL; +} +#endif + #endif -- cgit v1.2.3 From 2e4ef3347b4a4eb65c4fd950d94bbd75fed4d798 Mon Sep 17 00:00:00 2001 From: Meghana Madhyastha Date: Wed, 24 Jan 2018 16:37:23 +0000 Subject: video: backlight: Add devres versions of of_find_backlight MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devm_of_find_backlight and the corresponding release function because some drivers use devres versions of functions for acquiring device resources. Acked-by: Daniel Thompson Reviewed-by: Noralf Trønnes Reviewed-by: Sean Paul Signed-off-by: Meghana Madhyastha Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/021f8fecfa3f374dc5dcb70fb07a6f6b019bea7b.1516810725.git.meghana.madhyastha@gmail.com --- drivers/video/backlight/backlight.c | 30 ++++++++++++++++++++++++++++++ include/linux/backlight.h | 7 +++++++ 2 files changed, 37 insertions(+) (limited to 'include/linux') diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c index 553bf5c4807c..deb824bef6e2 100644 --- a/drivers/video/backlight/backlight.c +++ b/drivers/video/backlight/backlight.c @@ -623,6 +623,36 @@ struct backlight_device *of_find_backlight(struct device *dev) } EXPORT_SYMBOL(of_find_backlight); +static void devm_backlight_release(void *data) +{ + backlight_put(data); +} + +/** + * devm_of_find_backlight - Resource-managed of_find_backlight() + * @dev: Device + * + * Device managed version of of_find_backlight(). + * The reference on the backlight device is automatically + * dropped on driver detach. + */ +struct backlight_device *devm_of_find_backlight(struct device *dev) +{ + struct backlight_device *bd; + int ret; + + bd = of_find_backlight(dev); + if (IS_ERR_OR_NULL(bd)) + return bd; + ret = devm_add_action(dev, devm_backlight_release, bd); + if (ret) { + backlight_put(bd); + return ERR_PTR(ret); + } + return bd; +} +EXPORT_SYMBOL(devm_of_find_backlight); + static void __exit backlight_class_exit(void) { class_destroy(backlight_class); diff --git a/include/linux/backlight.h b/include/linux/backlight.h index ddc9bade4fb2..2baab6f3861d 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -217,11 +217,18 @@ of_find_backlight_by_node(struct device_node *node) #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) struct backlight_device *of_find_backlight(struct device *dev); +struct backlight_device *devm_of_find_backlight(struct device *dev); #else static inline struct backlight_device *of_find_backlight(struct device *dev) { return NULL; } + +static inline struct backlight_device * +devm_of_find_backlight(struct device *dev) +{ + return NULL; +} #endif #endif -- cgit v1.2.3 From 1a3f6755649dd419d9e01cbc38e116e2c70acb73 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 15 Jan 2018 11:33:41 +0100 Subject: iio: adc: axp20x_adc: add support for AXP813 ADC The X-Powers AXP813 PMIC is really close to what is already done for AXP20X/AXP22X. There are two pairs of bits to set the rate (one for Voltage and Current measurements and one for TS/GPIO0 voltage measurements) instead of one. The register to set the ADC rates is different from the one for AXP20X/AXP22X. GPIO0 can be used as an ADC (measuring Volts) unlike for AXP22X. The scales to apply to the different inputs are unlike the ones from AXP20X and AXP22X. Signed-off-by: Quentin Schulz Acked-by: Jonathan Cameron Signed-off-by: Jonathan Cameron --- drivers/iio/adc/axp20x_adc.c | 123 +++++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/axp20x.h | 2 + 2 files changed, 125 insertions(+) (limited to 'include/linux') diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c index 39680539a701..7cdb8bc8cde6 100644 --- a/drivers/iio/adc/axp20x_adc.c +++ b/drivers/iio/adc/axp20x_adc.c @@ -35,8 +35,13 @@ #define AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1) #define AXP20X_ADC_RATE_MASK GENMASK(7, 6) +#define AXP813_V_I_ADC_RATE_MASK GENMASK(5, 4) +#define AXP813_ADC_RATE_MASK (AXP20X_ADC_RATE_MASK | AXP813_V_I_ADC_RATE_MASK) #define AXP20X_ADC_RATE_HZ(x) ((ilog2((x) / 25) << 6) & AXP20X_ADC_RATE_MASK) #define AXP22X_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 6) & AXP20X_ADC_RATE_MASK) +#define AXP813_TS_GPIO0_ADC_RATE_HZ(x) AXP20X_ADC_RATE_HZ(x) +#define AXP813_V_I_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK) +#define AXP813_ADC_RATE_HZ(x) (AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x)) #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \ { \ @@ -95,6 +100,12 @@ enum axp22x_adc_channel_i { AXP22X_BATT_DISCHRG_I, }; +enum axp813_adc_channel_v { + AXP813_TS_IN = 0, + AXP813_GPIO0_V, + AXP813_BATT_V, +}; + static struct iio_map axp20x_maps[] = { { .consumer_dev_name = "axp20x-usb-power-supply", @@ -197,6 +208,25 @@ static const struct iio_chan_spec axp22x_adc_channels[] = { AXP20X_BATT_DISCHRG_I_H), }; +static const struct iio_chan_spec axp813_adc_channels[] = { + { + .type = IIO_TEMP, + .address = AXP22X_PMIC_TEMP_H, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .datasheet_name = "pmic_temp", + }, + AXP20X_ADC_CHANNEL(AXP813_GPIO0_V, "gpio0_v", IIO_VOLTAGE, + AXP288_GP_ADC_H), + AXP20X_ADC_CHANNEL(AXP813_BATT_V, "batt_v", IIO_VOLTAGE, + AXP20X_BATT_V_H), + AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT, + AXP20X_BATT_CHRG_I_H), + AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT, + AXP20X_BATT_DISCHRG_I_H), +}; + static int axp20x_adc_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { @@ -243,6 +273,18 @@ static int axp22x_adc_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } +static int axp813_adc_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + struct axp20x_adc_iio *info = iio_priv(indio_dev); + + *val = axp20x_read_variable_width(info->regmap, chan->address, 12); + if (*val < 0) + return *val; + + return IIO_VAL_INT; +} + static int axp20x_adc_scale_voltage(int channel, int *val, int *val2) { switch (channel) { @@ -273,6 +315,24 @@ static int axp20x_adc_scale_voltage(int channel, int *val, int *val2) } } +static int axp813_adc_scale_voltage(int channel, int *val, int *val2) +{ + switch (channel) { + case AXP813_GPIO0_V: + *val = 0; + *val2 = 800000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP813_BATT_V: + *val = 1; + *val2 = 100000; + return IIO_VAL_INT_PLUS_MICRO; + + default: + return -EINVAL; + } +} + static int axp20x_adc_scale_current(int channel, int *val, int *val2) { switch (channel) { @@ -342,6 +402,26 @@ static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val, } } +static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val, + int *val2) +{ + switch (chan->type) { + case IIO_VOLTAGE: + return axp813_adc_scale_voltage(chan->channel, val, val2); + + case IIO_CURRENT: + *val = 1; + return IIO_VAL_INT; + + case IIO_TEMP: + *val = 100; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel, int *val) { @@ -425,6 +505,26 @@ static int axp22x_read_raw(struct iio_dev *indio_dev, } } +static int axp813_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_OFFSET: + *val = -2667; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + return axp813_adc_scale(chan, val, val2); + + case IIO_CHAN_INFO_RAW: + return axp813_adc_raw(indio_dev, chan, val); + + default: + return -EINVAL; + } +} + static int axp20x_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) @@ -470,6 +570,10 @@ static const struct iio_info axp22x_adc_iio_info = { .read_raw = axp22x_read_raw, }; +static const struct iio_info axp813_adc_iio_info = { + .read_raw = axp813_read_raw, +}; + static int axp20x_adc_rate(struct axp20x_adc_iio *info, int rate) { return regmap_update_bits(info->regmap, AXP20X_ADC_RATE, @@ -484,6 +588,13 @@ static int axp22x_adc_rate(struct axp20x_adc_iio *info, int rate) AXP22X_ADC_RATE_HZ(rate)); } +static int axp813_adc_rate(struct axp20x_adc_iio *info, int rate) +{ + return regmap_update_bits(info->regmap, AXP813_ADC_RATE, + AXP813_ADC_RATE_MASK, + AXP813_ADC_RATE_HZ(rate)); +} + struct axp_data { const struct iio_info *iio_info; int num_channels; @@ -515,9 +626,20 @@ static const struct axp_data axp22x_data = { .maps = axp22x_maps, }; +static const struct axp_data axp813_data = { + .iio_info = &axp813_adc_iio_info, + .num_channels = ARRAY_SIZE(axp813_adc_channels), + .channels = axp813_adc_channels, + .adc_en1_mask = AXP22X_ADC_EN1_MASK, + .adc_rate = axp813_adc_rate, + .adc_en2 = false, + .maps = axp22x_maps, +}; + static const struct of_device_id axp20x_adc_of_match[] = { { .compatible = "x-powers,axp209-adc", .data = (void *)&axp20x_data, }, { .compatible = "x-powers,axp221-adc", .data = (void *)&axp22x_data, }, + { .compatible = "x-powers,axp813-adc", .data = (void *)&axp813_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, axp20x_adc_of_match); @@ -525,6 +647,7 @@ MODULE_DEVICE_TABLE(of, axp20x_adc_of_match); static const struct platform_device_id axp20x_adc_id_match[] = { { .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, }, { .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, }, + { .name = "axp813-adc", .driver_data = (kernel_ulong_t)&axp813_data, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(platform, axp20x_adc_id_match); diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 78dc85365c4f..ff95414c8316 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -266,6 +266,8 @@ enum axp20x_variants { #define AXP288_RT_BATT_V_H 0xa0 #define AXP288_RT_BATT_V_L 0xa1 +#define AXP813_ADC_RATE 0x85 + /* Fuel Gauge */ #define AXP288_FG_RDC1_REG 0xba #define AXP288_FG_RDC0_REG 0xbb -- cgit v1.2.3 From b28bad65c1fec47076ebee88b51b0dafa31f5065 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 4 Jan 2018 10:58:48 -0800 Subject: Input: libps2 - use u8 for byte data Instead of using unsigned char for the byte data switch to using u8. Also use unsigned int for the command codes and timeouts, and have ps2_handle_ack() and ps2_handle_response() return bool instead of int, as they do not return error codes but rather signal whether a byte was handled or not handled. ps2_is_keyboard_id() now returns bool as well. Signed-off-by: Dmitry Torokhov --- drivers/input/serio/libps2.c | 31 ++++++++++++++++--------------- include/linux/libps2.h | 23 +++++++++++++---------- 2 files changed, 29 insertions(+), 25 deletions(-) (limited to 'include/linux') diff --git a/drivers/input/serio/libps2.c b/drivers/input/serio/libps2.c index 21aea5169a99..c3712f0a47b5 100644 --- a/drivers/input/serio/libps2.c +++ b/drivers/input/serio/libps2.c @@ -34,7 +34,7 @@ MODULE_LICENSE("GPL"); * ps2_sendbyte() can only be called from a process context. */ -int ps2_sendbyte(struct ps2dev *ps2dev, unsigned char byte, int timeout) +int ps2_sendbyte(struct ps2dev *ps2dev, u8 byte, unsigned int timeout) { serio_pause_rx(ps2dev->serio); ps2dev->nak = 1; @@ -75,7 +75,7 @@ EXPORT_SYMBOL(ps2_end_command); * and discards them. */ -void ps2_drain(struct ps2dev *ps2dev, int maxbytes, int timeout) +void ps2_drain(struct ps2dev *ps2dev, size_t maxbytes, unsigned int timeout) { if (maxbytes > sizeof(ps2dev->cmdbuf)) { WARN_ON(1); @@ -102,9 +102,9 @@ EXPORT_SYMBOL(ps2_drain); * known keyboard IDs. */ -int ps2_is_keyboard_id(char id_byte) +bool ps2_is_keyboard_id(u8 id_byte) { - static const char keyboard_ids[] = { + static const u8 keyboard_ids[] = { 0xab, /* Regular keyboards */ 0xac, /* NCD Sun keyboard */ 0x2b, /* Trust keyboard, translated */ @@ -123,7 +123,8 @@ EXPORT_SYMBOL(ps2_is_keyboard_id); * completion. */ -static int ps2_adjust_timeout(struct ps2dev *ps2dev, int command, int timeout) +static int ps2_adjust_timeout(struct ps2dev *ps2dev, + unsigned int command, unsigned int timeout) { switch (command) { case PS2_CMD_RESET_BAT: @@ -178,11 +179,11 @@ static int ps2_adjust_timeout(struct ps2dev *ps2dev, int command, int timeout) * ps2_command() can only be called from a process context */ -int __ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command) +int __ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command) { - int timeout; - int send = (command >> 12) & 0xf; - int receive = (command >> 8) & 0xf; + unsigned int timeout; + unsigned int send = (command >> 12) & 0xf; + unsigned int receive = (command >> 8) & 0xf; int rc = -1; int i; @@ -256,7 +257,7 @@ int __ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command) } EXPORT_SYMBOL(__ps2_command); -int ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command) +int ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command) { int rc; @@ -286,7 +287,7 @@ EXPORT_SYMBOL(ps2_init); * to properly process ACK/NAK of a command from a PS/2 device. */ -int ps2_handle_ack(struct ps2dev *ps2dev, unsigned char data) +bool ps2_handle_ack(struct ps2dev *ps2dev, u8 data) { switch (data) { case PS2_RET_ACK: @@ -318,7 +319,7 @@ int ps2_handle_ack(struct ps2dev *ps2dev, unsigned char data) } /* Fall through */ default: - return 0; + return false; } if (!ps2dev->nak) { @@ -333,7 +334,7 @@ int ps2_handle_ack(struct ps2dev *ps2dev, unsigned char data) if (data != PS2_RET_ACK) ps2_handle_response(ps2dev, data); - return 1; + return true; } EXPORT_SYMBOL(ps2_handle_ack); @@ -343,7 +344,7 @@ EXPORT_SYMBOL(ps2_handle_ack); * waiting for completion of the command. */ -int ps2_handle_response(struct ps2dev *ps2dev, unsigned char data) +bool ps2_handle_response(struct ps2dev *ps2dev, u8 data) { if (ps2dev->cmdcnt) ps2dev->cmdbuf[--ps2dev->cmdcnt] = data; @@ -359,7 +360,7 @@ int ps2_handle_response(struct ps2dev *ps2dev, unsigned char data) wake_up(&ps2dev->wait); } - return 1; + return true; } EXPORT_SYMBOL(ps2_handle_response); diff --git a/include/linux/libps2.h b/include/linux/libps2.h index 4ad06e824f76..04a5750f1e4e 100644 --- a/include/linux/libps2.h +++ b/include/linux/libps2.h @@ -10,6 +10,9 @@ * the Free Software Foundation. */ +#include +#include +#include #define PS2_CMD_GETID 0x02f2 #define PS2_CMD_RESET_BAT 0x02ff @@ -36,21 +39,21 @@ struct ps2dev { wait_queue_head_t wait; unsigned long flags; - unsigned char cmdbuf[8]; - unsigned char cmdcnt; - unsigned char nak; + u8 cmdbuf[8]; + u8 cmdcnt; + u8 nak; }; void ps2_init(struct ps2dev *ps2dev, struct serio *serio); -int ps2_sendbyte(struct ps2dev *ps2dev, unsigned char byte, int timeout); -void ps2_drain(struct ps2dev *ps2dev, int maxbytes, int timeout); +int ps2_sendbyte(struct ps2dev *ps2dev, u8 byte, unsigned int timeout); +void ps2_drain(struct ps2dev *ps2dev, size_t maxbytes, unsigned int timeout); void ps2_begin_command(struct ps2dev *ps2dev); void ps2_end_command(struct ps2dev *ps2dev); -int __ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command); -int ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command); -int ps2_handle_ack(struct ps2dev *ps2dev, unsigned char data); -int ps2_handle_response(struct ps2dev *ps2dev, unsigned char data); +int __ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command); +int ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command); +bool ps2_handle_ack(struct ps2dev *ps2dev, u8 data); +bool ps2_handle_response(struct ps2dev *ps2dev, u8 data); void ps2_cmd_aborted(struct ps2dev *ps2dev); -int ps2_is_keyboard_id(char id); +bool ps2_is_keyboard_id(u8 id); #endif /* _LIBPS2_H */ -- cgit v1.2.3 From 3a92dd331f90a33e0f0962b981577eb5078419c4 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 4 Jan 2018 11:27:05 -0800 Subject: Input: libps2 - use BIT() for bitmask constants Let's explicitly document bit numbers with BIT() macro. Signed-off-by: Dmitry Torokhov --- include/linux/libps2.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/libps2.h b/include/linux/libps2.h index 04a5750f1e4e..646b581fea56 100644 --- a/include/linux/libps2.h +++ b/include/linux/libps2.h @@ -10,6 +10,7 @@ * the Free Software Foundation. */ +#include #include #include #include @@ -23,11 +24,11 @@ #define PS2_RET_NAK 0xfe #define PS2_RET_ERR 0xfc -#define PS2_FLAG_ACK 1 /* Waiting for ACK/NAK */ -#define PS2_FLAG_CMD 2 /* Waiting for command to finish */ -#define PS2_FLAG_CMD1 4 /* Waiting for the first byte of command response */ -#define PS2_FLAG_WAITID 8 /* Command execiting is GET ID */ -#define PS2_FLAG_NAK 16 /* Last transmission was NAKed */ +#define PS2_FLAG_ACK BIT(0) /* Waiting for ACK/NAK */ +#define PS2_FLAG_CMD BIT(1) /* Waiting for a command to finish */ +#define PS2_FLAG_CMD1 BIT(2) /* Waiting for the first byte of command response */ +#define PS2_FLAG_WAITID BIT(3) /* Command executing is GET ID */ +#define PS2_FLAG_NAK BIT(4) /* Last transmission was NAKed */ struct ps2dev { struct serio *serio; -- cgit v1.2.3 From 08be954b7a7de6742d3d47e4dc20e3b086410761 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 2 Jan 2018 12:03:02 -0800 Subject: Input: psmouse - move sliced command implementation to libps2 In preparation to adding some debugging statements to PS/2 control sequences let's move psmouse_sliced_command() into libps2 and rename it to ps2_sliced_command(). Signed-off-by: Dmitry Torokhov --- drivers/input/mouse/elantech.c | 12 ++++++------ drivers/input/mouse/logips2pp.c | 2 +- drivers/input/mouse/psmouse-base.c | 26 -------------------------- drivers/input/mouse/psmouse.h | 1 - drivers/input/mouse/synaptics.c | 8 ++++---- drivers/input/serio/libps2.c | 32 ++++++++++++++++++++++++++++++++ include/linux/libps2.h | 3 +++ 7 files changed, 46 insertions(+), 38 deletions(-) (limited to 'include/linux') diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c index af7fc17c14d9..db47a5e1d114 100644 --- a/drivers/input/mouse/elantech.c +++ b/drivers/input/mouse/elantech.c @@ -35,7 +35,7 @@ static int synaptics_send_cmd(struct psmouse *psmouse, unsigned char c, unsigned char *param) { - if (psmouse_sliced_command(psmouse, c) || + if (ps2_sliced_command(&psmouse->ps2dev, c) || ps2_command(&psmouse->ps2dev, param, PSMOUSE_CMD_GETINFO)) { psmouse_err(psmouse, "%s query 0x%02x failed.\n", __func__, c); return -1; @@ -107,8 +107,8 @@ static int elantech_read_reg(struct psmouse *psmouse, unsigned char reg, switch (etd->hw_version) { case 1: - if (psmouse_sliced_command(psmouse, ETP_REGISTER_READ) || - psmouse_sliced_command(psmouse, reg) || + if (ps2_sliced_command(&psmouse->ps2dev, ETP_REGISTER_READ) || + ps2_sliced_command(&psmouse->ps2dev, reg) || ps2_command(&psmouse->ps2dev, param, PSMOUSE_CMD_GETINFO)) { rc = -1; } @@ -162,9 +162,9 @@ static int elantech_write_reg(struct psmouse *psmouse, unsigned char reg, switch (etd->hw_version) { case 1: - if (psmouse_sliced_command(psmouse, ETP_REGISTER_WRITE) || - psmouse_sliced_command(psmouse, reg) || - psmouse_sliced_command(psmouse, val) || + if (ps2_sliced_command(&psmouse->ps2dev, ETP_REGISTER_WRITE) || + ps2_sliced_command(&psmouse->ps2dev, reg) || + ps2_sliced_command(&psmouse->ps2dev, val) || ps2_command(&psmouse->ps2dev, NULL, PSMOUSE_CMD_SETSCALE11)) { rc = -1; } diff --git a/drivers/input/mouse/logips2pp.c b/drivers/input/mouse/logips2pp.c index 3c8d7051ef5e..3d5637e6fa5f 100644 --- a/drivers/input/mouse/logips2pp.c +++ b/drivers/input/mouse/logips2pp.c @@ -117,7 +117,7 @@ static int ps2pp_cmd(struct psmouse *psmouse, u8 *param, u8 command) { int error; - error = psmouse_sliced_command(psmouse, command); + error = ps2_sliced_command(&psmouse->ps2dev, command); if (error) return error; diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c index f0b16eb4a32a..4f9f438e2653 100644 --- a/drivers/input/mouse/psmouse-base.c +++ b/drivers/input/mouse/psmouse-base.c @@ -431,32 +431,6 @@ static irqreturn_t psmouse_interrupt(struct serio *serio, return IRQ_HANDLED; } -/* - * psmouse_sliced_command() sends an extended PS/2 command to the mouse - * using sliced syntax, understood by advanced devices, such as Logitech - * or Synaptics touchpads. The command is encoded as: - * 0xE6 0xE8 rr 0xE8 ss 0xE8 tt 0xE8 uu where (rr*64)+(ss*16)+(tt*4)+uu - * is the command. - */ -int psmouse_sliced_command(struct psmouse *psmouse, u8 command) -{ - int i; - int error; - - error = ps2_command(&psmouse->ps2dev, NULL, PSMOUSE_CMD_SETSCALE11); - if (error) - return error; - - for (i = 6; i >= 0; i -= 2) { - u8 d = (command >> i) & 3; - error = ps2_command(&psmouse->ps2dev, &d, PSMOUSE_CMD_SETRES); - if (error) - return error; - } - - return 0; -} - /* * psmouse_reset() resets the mouse into power-on state. */ diff --git a/drivers/input/mouse/psmouse.h b/drivers/input/mouse/psmouse.h index 8bc99691494e..71ac50082c8b 100644 --- a/drivers/input/mouse/psmouse.h +++ b/drivers/input/mouse/psmouse.h @@ -131,7 +131,6 @@ struct psmouse { void psmouse_queue_work(struct psmouse *psmouse, struct delayed_work *work, unsigned long delay); -int psmouse_sliced_command(struct psmouse *psmouse, unsigned char command); int psmouse_reset(struct psmouse *psmouse); void psmouse_set_state(struct psmouse *psmouse, enum psmouse_state new_state); void psmouse_set_resolution(struct psmouse *psmouse, unsigned int resolution); diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c index cd9f61cb3fc6..89ab77a211b5 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -84,7 +84,7 @@ static int synaptics_mode_cmd(struct psmouse *psmouse, u8 mode) u8 param[1]; int error; - error = psmouse_sliced_command(psmouse, mode); + error = ps2_sliced_command(&psmouse->ps2dev, mode); if (error) return error; @@ -190,7 +190,7 @@ static int synaptics_send_cmd(struct psmouse *psmouse, u8 cmd, u8 *param) { int error; - error = psmouse_sliced_command(psmouse, cmd); + error = ps2_sliced_command(&psmouse->ps2dev, cmd); if (error) return error; @@ -547,7 +547,7 @@ static int synaptics_set_advanced_gesture_mode(struct psmouse *psmouse) static u8 param = 0xc8; int error; - error = psmouse_sliced_command(psmouse, SYN_QUE_MODEL); + error = ps2_sliced_command(&psmouse->ps2dev, SYN_QUE_MODEL); if (error) return error; @@ -614,7 +614,7 @@ static int synaptics_pt_write(struct serio *serio, u8 c) u8 rate_param = SYN_PS_CLIENT_CMD; /* indicates that we want pass-through port */ int error; - error = psmouse_sliced_command(parent, c); + error = ps2_sliced_command(&parent->ps2dev, c); if (error) return error; diff --git a/drivers/input/serio/libps2.c b/drivers/input/serio/libps2.c index c3712f0a47b5..e96ae477f0b5 100644 --- a/drivers/input/serio/libps2.c +++ b/drivers/input/serio/libps2.c @@ -269,6 +269,38 @@ int ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command) } EXPORT_SYMBOL(ps2_command); +/* + * ps2_sliced_command() sends an extended PS/2 command to the mouse + * using sliced syntax, understood by advanced devices, such as Logitech + * or Synaptics touchpads. The command is encoded as: + * 0xE6 0xE8 rr 0xE8 ss 0xE8 tt 0xE8 uu where (rr*64)+(ss*16)+(tt*4)+uu + * is the command. + */ + +int ps2_sliced_command(struct ps2dev *ps2dev, u8 command) +{ + int i; + int retval; + + ps2_begin_command(ps2dev); + + retval = __ps2_command(ps2dev, NULL, PS2_CMD_SETSCALE11); + if (retval) + goto out; + + for (i = 6; i >= 0; i -= 2) { + u8 d = (command >> i) & 3; + retval = __ps2_command(ps2dev, &d, PS2_CMD_SETRES); + if (retval) + break; + } + +out: + ps2_end_command(ps2dev); + return retval; +} +EXPORT_SYMBOL(ps2_sliced_command); + /* * ps2_init() initializes ps2dev structure */ diff --git a/include/linux/libps2.h b/include/linux/libps2.h index 646b581fea56..3c69cd796f48 100644 --- a/include/linux/libps2.h +++ b/include/linux/libps2.h @@ -15,6 +15,8 @@ #include #include +#define PS2_CMD_SETSCALE11 0x00e6 +#define PS2_CMD_SETRES 0x10e8 #define PS2_CMD_GETID 0x02f2 #define PS2_CMD_RESET_BAT 0x02ff @@ -52,6 +54,7 @@ void ps2_begin_command(struct ps2dev *ps2dev); void ps2_end_command(struct ps2dev *ps2dev); int __ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command); int ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command); +int ps2_sliced_command(struct ps2dev *ps2dev, u8 command); bool ps2_handle_ack(struct ps2dev *ps2dev, u8 data); bool ps2_handle_response(struct ps2dev *ps2dev, u8 data); void ps2_cmd_aborted(struct ps2dev *ps2dev); -- cgit v1.2.3 From 29acc42e8e10a4721757af9ed8aec569d30ce39b Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 17 Jan 2018 12:00:24 -0800 Subject: Input: libps2 - relax command byte ACK handling When we probe PS/2 devices we first issue "Get ID" command and only if we receive what we consider a valid keyboard or mouse ID we disable the device and continue with protocol detection. That means that the device may be transmitting motion or keystroke data, while we expect ACK response. Instead of signaling failure if we see anything but ACK/NAK let's ignore "garbage" response until we see ACK for the command byte (first byte). The checks for subsequent ACKs of command parameters will continue be strict. Signed-off-by: Dmitry Torokhov --- drivers/input/serio/libps2.c | 25 ++++++++++++++++++++++--- include/linux/libps2.h | 1 + 2 files changed, 23 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/input/serio/libps2.c b/drivers/input/serio/libps2.c index f05c407b31f3..e6a07e68d1ff 100644 --- a/drivers/input/serio/libps2.c +++ b/drivers/input/serio/libps2.c @@ -256,16 +256,23 @@ int __ps2_command(struct ps2dev *ps2dev, u8 *param, unsigned int command) for (i = 0; i < receive; i++) ps2dev->cmdbuf[(receive - 1) - i] = param[i]; + /* Signal that we are sending the command byte */ + ps2dev->flags |= PS2_FLAG_ACK_CMD; + /* * Some devices (Synaptics) peform the reset before * ACKing the reset command, and so it can take a long * time before the ACK arrives. */ - rc = ps2_do_sendbyte(ps2dev, command & 0xff, - command == PS2_CMD_RESET_BAT ? 1000 : 200, 2); + timeout = command == PS2_CMD_RESET_BAT ? 1000 : 200; + + rc = ps2_do_sendbyte(ps2dev, command & 0xff, timeout, 2); if (rc) goto out_reset_flags; + /* Now we are sending command parameters, if any */ + ps2dev->flags &= ~PS2_FLAG_ACK_CMD; + for (i = 0; i < send; i++) { rc = ps2_do_sendbyte(ps2dev, param[i], 200, 2); if (rc) @@ -416,7 +423,19 @@ bool ps2_handle_ack(struct ps2dev *ps2dev, u8 data) } /* Fall through */ default: - return false; + /* + * Do not signal errors if we get unexpected reply while + * waiting for an ACK to the initial (first) command byte: + * the device might not be quiesced yet and continue + * delivering data. + * Note that we reset PS2_FLAG_WAITID flag, so the workaround + * for mice not acknowledging the Get ID command only triggers + * on the 1st byte; if device spews data we really want to see + * a real ACK from it. + */ + dev_dbg(&ps2dev->serio->dev, "unexpected %#02x\n", data); + ps2dev->flags &= ~PS2_FLAG_WAITID; + return ps2dev->flags & PS2_FLAG_ACK_CMD; } if (!ps2dev->nak) { diff --git a/include/linux/libps2.h b/include/linux/libps2.h index 3c69cd796f48..5f18fe02ae37 100644 --- a/include/linux/libps2.h +++ b/include/linux/libps2.h @@ -31,6 +31,7 @@ #define PS2_FLAG_CMD1 BIT(2) /* Waiting for the first byte of command response */ #define PS2_FLAG_WAITID BIT(3) /* Command executing is GET ID */ #define PS2_FLAG_NAK BIT(4) /* Last transmission was NAKed */ +#define PS2_FLAG_ACK_CMD BIT(5) /* Waiting to ACK the command (first) byte */ struct ps2dev { struct serio *serio; -- cgit v1.2.3 From 47a361634821dc66cefbfa70b9d10a91269d7f7d Mon Sep 17 00:00:00 2001 From: Crt Mori Date: Thu, 11 Jan 2018 11:19:57 +0100 Subject: lib: Add strongly typed 64bit int_sqrt There is no option to perform 64bit integer sqrt on 32bit platform. Added stronger typed int_sqrt64 enables the 64bit calculations to be performed on 32bit platforms. Using same algorithm as int_sqrt() with strong typing provides enough precision also on 32bit platforms, but it sacrifices some performance. In case values are smaller than ULONG_MAX the standard int_sqrt is used for calculation to maximize the performance due to more native calculations. Signed-off-by: Crt Mori Acked-by: Joe Perches Signed-off-by: Jonathan Cameron --- include/linux/kernel.h | 9 +++++++++ lib/int_sqrt.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) (limited to 'include/linux') diff --git a/include/linux/kernel.h b/include/linux/kernel.h index ce51455e2adf..2da80e079d56 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -479,6 +479,15 @@ extern int func_ptr_is_kernel_text(void *ptr); unsigned long int_sqrt(unsigned long); +#if BITS_PER_LONG < 64 +u32 int_sqrt64(u64 x); +#else +static inline u32 int_sqrt64(u64 x) +{ + return (u32)int_sqrt(x); +} +#endif + extern void bust_spinlocks(int yes); extern int oops_in_progress; /* If set, an oops, panic(), BUG() or die() is in progress */ extern int panic_timeout; diff --git a/lib/int_sqrt.c b/lib/int_sqrt.c index e2d329099bf7..14436f4ca6bd 100644 --- a/lib/int_sqrt.c +++ b/lib/int_sqrt.c @@ -38,3 +38,33 @@ unsigned long int_sqrt(unsigned long x) return y; } EXPORT_SYMBOL(int_sqrt); + +#if BITS_PER_LONG < 64 +/** + * int_sqrt64 - strongly typed int_sqrt function when minimum 64 bit input + * is expected. + * @x: 64bit integer of which to calculate the sqrt + */ +u32 int_sqrt64(u64 x) +{ + u64 b, m, y = 0; + + if (x <= ULONG_MAX) + return int_sqrt((unsigned long) x); + + m = 1ULL << (fls64(x) & ~1ULL); + while (m != 0) { + b = y + m; + y >>= 1; + + if (x >= b) { + x -= b; + y += m; + } + m >>= 2; + } + + return y; +} +EXPORT_SYMBOL(int_sqrt64); +#endif -- cgit v1.2.3 From e12f03d7031a977356e3d7b75a68c2185ff8d155 Mon Sep 17 00:00:00 2001 From: Song Liu Date: Wed, 6 Dec 2017 14:45:15 -0800 Subject: perf/core: Implement the 'perf_kprobe' PMU A new PMU type, perf_kprobe is added. Based on attr from perf_event_open(), perf_kprobe creates a kprobe (or kretprobe) for the perf_event. This kprobe is private to this perf_event, and thus not added to global lists, and not available in tracefs. Two functions, create_local_trace_kprobe() and destroy_local_trace_kprobe() are added to created and destroy these local trace_kprobe. Signed-off-by: Song Liu Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Yonghong Song Reviewed-by: Josef Bacik Cc: Cc: Cc: Cc: Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20171206224518.3598254-6-songliubraving@fb.com Signed-off-by: Ingo Molnar --- include/linux/trace_events.h | 4 ++ kernel/events/core.c | 142 ++++++++++++++++++++++++++++++---------- kernel/trace/trace_event_perf.c | 49 ++++++++++++++ kernel/trace/trace_kprobe.c | 91 ++++++++++++++++++++++--- kernel/trace/trace_probe.h | 7 ++ 5 files changed, 250 insertions(+), 43 deletions(-) (limited to 'include/linux') diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h index af44e7c2d577..21c5d43a21af 100644 --- a/include/linux/trace_events.h +++ b/include/linux/trace_events.h @@ -533,6 +533,10 @@ extern int perf_trace_init(struct perf_event *event); extern void perf_trace_destroy(struct perf_event *event); extern int perf_trace_add(struct perf_event *event, int flags); extern void perf_trace_del(struct perf_event *event, int flags); +#ifdef CONFIG_KPROBE_EVENTS +extern int perf_kprobe_init(struct perf_event *event, bool is_retprobe); +extern void perf_kprobe_destroy(struct perf_event *event); +#endif extern int ftrace_profile_set_filter(struct perf_event *event, int event_id, char *filter_str); extern void ftrace_profile_free_filter(struct perf_event *event); diff --git a/kernel/events/core.c b/kernel/events/core.c index d99fe3fdec8a..333735531968 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -7992,9 +7992,77 @@ static struct pmu perf_tracepoint = { .read = perf_swevent_read, }; +#ifdef CONFIG_KPROBE_EVENTS +/* + * Flags in config, used by dynamic PMU kprobe and uprobe + * The flags should match following PMU_FORMAT_ATTR(). + * + * PERF_PROBE_CONFIG_IS_RETPROBE if set, create kretprobe/uretprobe + * if not set, create kprobe/uprobe + */ +enum perf_probe_config { + PERF_PROBE_CONFIG_IS_RETPROBE = 1U << 0, /* [k,u]retprobe */ +}; + +PMU_FORMAT_ATTR(retprobe, "config:0"); + +static struct attribute *probe_attrs[] = { + &format_attr_retprobe.attr, + NULL, +}; + +static struct attribute_group probe_format_group = { + .name = "format", + .attrs = probe_attrs, +}; + +static const struct attribute_group *probe_attr_groups[] = { + &probe_format_group, + NULL, +}; + +static int perf_kprobe_event_init(struct perf_event *event); +static struct pmu perf_kprobe = { + .task_ctx_nr = perf_sw_context, + .event_init = perf_kprobe_event_init, + .add = perf_trace_add, + .del = perf_trace_del, + .start = perf_swevent_start, + .stop = perf_swevent_stop, + .read = perf_swevent_read, + .attr_groups = probe_attr_groups, +}; + +static int perf_kprobe_event_init(struct perf_event *event) +{ + int err; + bool is_retprobe; + + if (event->attr.type != perf_kprobe.type) + return -ENOENT; + /* + * no branch sampling for probe events + */ + if (has_branch_stack(event)) + return -EOPNOTSUPP; + + is_retprobe = event->attr.config & PERF_PROBE_CONFIG_IS_RETPROBE; + err = perf_kprobe_init(event, is_retprobe); + if (err) + return err; + + event->destroy = perf_kprobe_destroy; + + return 0; +} +#endif /* CONFIG_KPROBE_EVENTS */ + static inline void perf_tp_register(void) { perf_pmu_register(&perf_tracepoint, "tracepoint", PERF_TYPE_TRACEPOINT); +#ifdef CONFIG_KPROBE_EVENTS + perf_pmu_register(&perf_kprobe, "kprobe", -1); +#endif } static void perf_event_free_filter(struct perf_event *event) @@ -8071,13 +8139,28 @@ static void perf_event_free_bpf_handler(struct perf_event *event) } #endif +/* + * returns true if the event is a tracepoint, or a kprobe/upprobe created + * with perf_event_open() + */ +static inline bool perf_event_is_tracing(struct perf_event *event) +{ + if (event->pmu == &perf_tracepoint) + return true; +#ifdef CONFIG_KPROBE_EVENTS + if (event->pmu == &perf_kprobe) + return true; +#endif + return false; +} + static int perf_event_set_bpf_prog(struct perf_event *event, u32 prog_fd) { bool is_kprobe, is_tracepoint, is_syscall_tp; struct bpf_prog *prog; int ret; - if (event->attr.type != PERF_TYPE_TRACEPOINT) + if (!perf_event_is_tracing(event)) return perf_event_set_bpf_handler(event, prog_fd); is_kprobe = event->tp_event->flags & TRACE_EVENT_FL_UKPROBE; @@ -8116,7 +8199,7 @@ static int perf_event_set_bpf_prog(struct perf_event *event, u32 prog_fd) static void perf_event_free_bpf_prog(struct perf_event *event) { - if (event->attr.type != PERF_TYPE_TRACEPOINT) { + if (!perf_event_is_tracing(event)) { perf_event_free_bpf_handler(event); return; } @@ -8535,47 +8618,36 @@ fail_clear_files: return ret; } -static int -perf_tracepoint_set_filter(struct perf_event *event, char *filter_str) -{ - struct perf_event_context *ctx = event->ctx; - int ret; - - /* - * Beware, here be dragons!! - * - * the tracepoint muck will deadlock against ctx->mutex, but the tracepoint - * stuff does not actually need it. So temporarily drop ctx->mutex. As per - * perf_event_ctx_lock() we already have a reference on ctx. - * - * This can result in event getting moved to a different ctx, but that - * does not affect the tracepoint state. - */ - mutex_unlock(&ctx->mutex); - ret = ftrace_profile_set_filter(event, event->attr.config, filter_str); - mutex_lock(&ctx->mutex); - - return ret; -} - static int perf_event_set_filter(struct perf_event *event, void __user *arg) { - char *filter_str; int ret = -EINVAL; - - if ((event->attr.type != PERF_TYPE_TRACEPOINT || - !IS_ENABLED(CONFIG_EVENT_TRACING)) && - !has_addr_filter(event)) - return -EINVAL; + char *filter_str; filter_str = strndup_user(arg, PAGE_SIZE); if (IS_ERR(filter_str)) return PTR_ERR(filter_str); - if (IS_ENABLED(CONFIG_EVENT_TRACING) && - event->attr.type == PERF_TYPE_TRACEPOINT) - ret = perf_tracepoint_set_filter(event, filter_str); - else if (has_addr_filter(event)) +#ifdef CONFIG_EVENT_TRACING + if (perf_event_is_tracing(event)) { + struct perf_event_context *ctx = event->ctx; + + /* + * Beware, here be dragons!! + * + * the tracepoint muck will deadlock against ctx->mutex, but + * the tracepoint stuff does not actually need it. So + * temporarily drop ctx->mutex. As per perf_event_ctx_lock() we + * already have a reference on ctx. + * + * This can result in event getting moved to a different ctx, + * but that does not affect the tracepoint state. + */ + mutex_unlock(&ctx->mutex); + ret = ftrace_profile_set_filter(event, event->attr.config, filter_str); + mutex_lock(&ctx->mutex); + } else +#endif + if (has_addr_filter(event)) ret = perf_event_set_addr_filter(event, filter_str); kfree(filter_str); diff --git a/kernel/trace/trace_event_perf.c b/kernel/trace/trace_event_perf.c index 55d6dff37daf..779baade9114 100644 --- a/kernel/trace/trace_event_perf.c +++ b/kernel/trace/trace_event_perf.c @@ -8,6 +8,7 @@ #include #include #include "trace.h" +#include "trace_probe.h" static char __percpu *perf_trace_buf[PERF_NR_CONTEXTS]; @@ -237,6 +238,54 @@ void perf_trace_destroy(struct perf_event *p_event) mutex_unlock(&event_mutex); } +#ifdef CONFIG_KPROBE_EVENTS +int perf_kprobe_init(struct perf_event *p_event, bool is_retprobe) +{ + int ret; + char *func = NULL; + struct trace_event_call *tp_event; + + if (p_event->attr.kprobe_func) { + func = kzalloc(KSYM_NAME_LEN, GFP_KERNEL); + if (!func) + return -ENOMEM; + ret = strncpy_from_user( + func, u64_to_user_ptr(p_event->attr.kprobe_func), + KSYM_NAME_LEN); + if (ret < 0) + goto out; + + if (func[0] == '\0') { + kfree(func); + func = NULL; + } + } + + tp_event = create_local_trace_kprobe( + func, (void *)(unsigned long)(p_event->attr.kprobe_addr), + p_event->attr.probe_offset, is_retprobe); + if (IS_ERR(tp_event)) { + ret = PTR_ERR(tp_event); + goto out; + } + + ret = perf_trace_event_init(tp_event, p_event); + if (ret) + destroy_local_trace_kprobe(tp_event); +out: + kfree(func); + return ret; +} + +void perf_kprobe_destroy(struct perf_event *p_event) +{ + perf_trace_event_close(p_event); + perf_trace_event_unreg(p_event); + + destroy_local_trace_kprobe(p_event->tp_event); +} +#endif /* CONFIG_KPROBE_EVENTS */ + int perf_trace_add(struct perf_event *p_event, int flags) { struct trace_event_call *tp_event = p_event->tp_event; diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c index 492700c5fb4d..246c786c851c 100644 --- a/kernel/trace/trace_kprobe.c +++ b/kernel/trace/trace_kprobe.c @@ -438,6 +438,14 @@ disable_trace_kprobe(struct trace_kprobe *tk, struct trace_event_file *file) disable_kprobe(&tk->rp.kp); wait = 1; } + + /* + * if tk is not added to any list, it must be a local trace_kprobe + * created with perf_event_open. We don't need to wait for these + * trace_kprobes + */ + if (list_empty(&tk->list)) + wait = 0; out: if (wait) { /* @@ -1313,12 +1321,9 @@ static struct trace_event_functions kprobe_funcs = { .trace = print_kprobe_event }; -static int register_kprobe_event(struct trace_kprobe *tk) +static inline void init_trace_event_call(struct trace_kprobe *tk, + struct trace_event_call *call) { - struct trace_event_call *call = &tk->tp.call; - int ret; - - /* Initialize trace_event_call */ INIT_LIST_HEAD(&call->class->fields); if (trace_kprobe_is_return(tk)) { call->event.funcs = &kretprobe_funcs; @@ -1327,6 +1332,19 @@ static int register_kprobe_event(struct trace_kprobe *tk) call->event.funcs = &kprobe_funcs; call->class->define_fields = kprobe_event_define_fields; } + + call->flags = TRACE_EVENT_FL_KPROBE; + call->class->reg = kprobe_register; + call->data = tk; +} + +static int register_kprobe_event(struct trace_kprobe *tk) +{ + struct trace_event_call *call = &tk->tp.call; + int ret = 0; + + init_trace_event_call(tk, call); + if (set_print_fmt(&tk->tp, trace_kprobe_is_return(tk)) < 0) return -ENOMEM; ret = register_trace_event(&call->event); @@ -1334,9 +1352,6 @@ static int register_kprobe_event(struct trace_kprobe *tk) kfree(call->print_fmt); return -ENODEV; } - call->flags = TRACE_EVENT_FL_KPROBE; - call->class->reg = kprobe_register; - call->data = tk; ret = trace_add_event_call(call); if (ret) { pr_info("Failed to register kprobe event: %s\n", @@ -1358,6 +1373,66 @@ static int unregister_kprobe_event(struct trace_kprobe *tk) return ret; } +#ifdef CONFIG_PERF_EVENTS +/* create a trace_kprobe, but don't add it to global lists */ +struct trace_event_call * +create_local_trace_kprobe(char *func, void *addr, unsigned long offs, + bool is_return) +{ + struct trace_kprobe *tk; + int ret; + char *event; + + /* + * local trace_kprobes are not added to probe_list, so they are never + * searched in find_trace_kprobe(). Therefore, there is no concern of + * duplicated name here. + */ + event = func ? func : "DUMMY_EVENT"; + + tk = alloc_trace_kprobe(KPROBE_EVENT_SYSTEM, event, (void *)addr, func, + offs, 0 /* maxactive */, 0 /* nargs */, + is_return); + + if (IS_ERR(tk)) { + pr_info("Failed to allocate trace_probe.(%d)\n", + (int)PTR_ERR(tk)); + return ERR_CAST(tk); + } + + init_trace_event_call(tk, &tk->tp.call); + + if (set_print_fmt(&tk->tp, trace_kprobe_is_return(tk)) < 0) { + ret = -ENOMEM; + goto error; + } + + ret = __register_trace_kprobe(tk); + if (ret < 0) + goto error; + + return &tk->tp.call; +error: + free_trace_kprobe(tk); + return ERR_PTR(ret); +} + +void destroy_local_trace_kprobe(struct trace_event_call *event_call) +{ + struct trace_kprobe *tk; + + tk = container_of(event_call, struct trace_kprobe, tp.call); + + if (trace_probe_is_enabled(&tk->tp)) { + WARN_ON(1); + return; + } + + __unregister_trace_kprobe(tk); + free_trace_kprobe(tk); +} +#endif /* CONFIG_PERF_EVENTS */ + /* Make a tracefs interface for controlling probe points */ static __init int init_kprobe_trace(void) { diff --git a/kernel/trace/trace_probe.h b/kernel/trace/trace_probe.h index fb66e3eaa192..e3d940a49dcd 100644 --- a/kernel/trace/trace_probe.h +++ b/kernel/trace/trace_probe.h @@ -404,3 +404,10 @@ store_trace_args(int ent_size, struct trace_probe *tp, struct pt_regs *regs, } extern int set_print_fmt(struct trace_probe *tp, bool is_return); + +#ifdef CONFIG_PERF_EVENTS +extern struct trace_event_call * +create_local_trace_kprobe(char *func, void *addr, unsigned long offs, + bool is_return); +extern void destroy_local_trace_kprobe(struct trace_event_call *event_call); +#endif -- cgit v1.2.3 From 33ea4b24277b06dbc55d7f5772a46f029600255e Mon Sep 17 00:00:00 2001 From: Song Liu Date: Wed, 6 Dec 2017 14:45:16 -0800 Subject: perf/core: Implement the 'perf_uprobe' PMU This patch adds perf_uprobe support with similar pattern as previous patch (for kprobe). Two functions, create_local_trace_uprobe() and destroy_local_trace_uprobe(), are created so a uprobe can be created and attached to the file descriptor created by perf_event_open(). Signed-off-by: Song Liu Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Yonghong Song Reviewed-by: Josef Bacik Cc: Cc: Cc: Cc: Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20171206224518.3598254-7-songliubraving@fb.com Signed-off-by: Ingo Molnar --- include/linux/trace_events.h | 4 ++ kernel/events/core.c | 48 ++++++++++++++++++++++- kernel/trace/trace_event_perf.c | 53 +++++++++++++++++++++++++ kernel/trace/trace_probe.h | 4 ++ kernel/trace/trace_uprobe.c | 86 +++++++++++++++++++++++++++++++++++++---- 5 files changed, 186 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h index 21c5d43a21af..0d9d6cb454b1 100644 --- a/include/linux/trace_events.h +++ b/include/linux/trace_events.h @@ -537,6 +537,10 @@ extern void perf_trace_del(struct perf_event *event, int flags); extern int perf_kprobe_init(struct perf_event *event, bool is_retprobe); extern void perf_kprobe_destroy(struct perf_event *event); #endif +#ifdef CONFIG_UPROBE_EVENTS +extern int perf_uprobe_init(struct perf_event *event, bool is_retprobe); +extern void perf_uprobe_destroy(struct perf_event *event); +#endif extern int ftrace_profile_set_filter(struct perf_event *event, int event_id, char *filter_str); extern void ftrace_profile_free_filter(struct perf_event *event); diff --git a/kernel/events/core.c b/kernel/events/core.c index 333735531968..5a54630db86b 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -7992,7 +7992,7 @@ static struct pmu perf_tracepoint = { .read = perf_swevent_read, }; -#ifdef CONFIG_KPROBE_EVENTS +#if defined(CONFIG_KPROBE_EVENTS) || defined(CONFIG_UPROBE_EVENTS) /* * Flags in config, used by dynamic PMU kprobe and uprobe * The flags should match following PMU_FORMAT_ATTR(). @@ -8020,7 +8020,9 @@ static const struct attribute_group *probe_attr_groups[] = { &probe_format_group, NULL, }; +#endif +#ifdef CONFIG_KPROBE_EVENTS static int perf_kprobe_event_init(struct perf_event *event); static struct pmu perf_kprobe = { .task_ctx_nr = perf_sw_context, @@ -8057,12 +8059,52 @@ static int perf_kprobe_event_init(struct perf_event *event) } #endif /* CONFIG_KPROBE_EVENTS */ +#ifdef CONFIG_UPROBE_EVENTS +static int perf_uprobe_event_init(struct perf_event *event); +static struct pmu perf_uprobe = { + .task_ctx_nr = perf_sw_context, + .event_init = perf_uprobe_event_init, + .add = perf_trace_add, + .del = perf_trace_del, + .start = perf_swevent_start, + .stop = perf_swevent_stop, + .read = perf_swevent_read, + .attr_groups = probe_attr_groups, +}; + +static int perf_uprobe_event_init(struct perf_event *event) +{ + int err; + bool is_retprobe; + + if (event->attr.type != perf_uprobe.type) + return -ENOENT; + /* + * no branch sampling for probe events + */ + if (has_branch_stack(event)) + return -EOPNOTSUPP; + + is_retprobe = event->attr.config & PERF_PROBE_CONFIG_IS_RETPROBE; + err = perf_uprobe_init(event, is_retprobe); + if (err) + return err; + + event->destroy = perf_uprobe_destroy; + + return 0; +} +#endif /* CONFIG_UPROBE_EVENTS */ + static inline void perf_tp_register(void) { perf_pmu_register(&perf_tracepoint, "tracepoint", PERF_TYPE_TRACEPOINT); #ifdef CONFIG_KPROBE_EVENTS perf_pmu_register(&perf_kprobe, "kprobe", -1); #endif +#ifdef CONFIG_UPROBE_EVENTS + perf_pmu_register(&perf_uprobe, "uprobe", -1); +#endif } static void perf_event_free_filter(struct perf_event *event) @@ -8150,6 +8192,10 @@ static inline bool perf_event_is_tracing(struct perf_event *event) #ifdef CONFIG_KPROBE_EVENTS if (event->pmu == &perf_kprobe) return true; +#endif +#ifdef CONFIG_UPROBE_EVENTS + if (event->pmu == &perf_uprobe) + return true; #endif return false; } diff --git a/kernel/trace/trace_event_perf.c b/kernel/trace/trace_event_perf.c index 779baade9114..2c416509b834 100644 --- a/kernel/trace/trace_event_perf.c +++ b/kernel/trace/trace_event_perf.c @@ -286,6 +286,59 @@ void perf_kprobe_destroy(struct perf_event *p_event) } #endif /* CONFIG_KPROBE_EVENTS */ +#ifdef CONFIG_UPROBE_EVENTS +int perf_uprobe_init(struct perf_event *p_event, bool is_retprobe) +{ + int ret; + char *path = NULL; + struct trace_event_call *tp_event; + + if (!p_event->attr.uprobe_path) + return -EINVAL; + path = kzalloc(PATH_MAX, GFP_KERNEL); + if (!path) + return -ENOMEM; + ret = strncpy_from_user( + path, u64_to_user_ptr(p_event->attr.uprobe_path), PATH_MAX); + if (ret < 0) + goto out; + if (path[0] == '\0') { + ret = -EINVAL; + goto out; + } + + tp_event = create_local_trace_uprobe( + path, p_event->attr.probe_offset, is_retprobe); + if (IS_ERR(tp_event)) { + ret = PTR_ERR(tp_event); + goto out; + } + + /* + * local trace_uprobe need to hold event_mutex to call + * uprobe_buffer_enable() and uprobe_buffer_disable(). + * event_mutex is not required for local trace_kprobes. + */ + mutex_lock(&event_mutex); + ret = perf_trace_event_init(tp_event, p_event); + if (ret) + destroy_local_trace_uprobe(tp_event); + mutex_unlock(&event_mutex); +out: + kfree(path); + return ret; +} + +void perf_uprobe_destroy(struct perf_event *p_event) +{ + mutex_lock(&event_mutex); + perf_trace_event_close(p_event); + perf_trace_event_unreg(p_event); + mutex_unlock(&event_mutex); + destroy_local_trace_uprobe(p_event->tp_event); +} +#endif /* CONFIG_UPROBE_EVENTS */ + int perf_trace_add(struct perf_event *p_event, int flags) { struct trace_event_call *tp_event = p_event->tp_event; diff --git a/kernel/trace/trace_probe.h b/kernel/trace/trace_probe.h index e3d940a49dcd..27de3174050a 100644 --- a/kernel/trace/trace_probe.h +++ b/kernel/trace/trace_probe.h @@ -410,4 +410,8 @@ extern struct trace_event_call * create_local_trace_kprobe(char *func, void *addr, unsigned long offs, bool is_return); extern void destroy_local_trace_kprobe(struct trace_event_call *event_call); + +extern struct trace_event_call * +create_local_trace_uprobe(char *name, unsigned long offs, bool is_return); +extern void destroy_local_trace_uprobe(struct trace_event_call *event_call); #endif diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c index 40592e7b3568..e3cbae702a53 100644 --- a/kernel/trace/trace_uprobe.c +++ b/kernel/trace/trace_uprobe.c @@ -1292,16 +1292,25 @@ static struct trace_event_functions uprobe_funcs = { .trace = print_uprobe_event }; -static int register_uprobe_event(struct trace_uprobe *tu) +static inline void init_trace_event_call(struct trace_uprobe *tu, + struct trace_event_call *call) { - struct trace_event_call *call = &tu->tp.call; - int ret; - - /* Initialize trace_event_call */ INIT_LIST_HEAD(&call->class->fields); call->event.funcs = &uprobe_funcs; call->class->define_fields = uprobe_event_define_fields; + call->flags = TRACE_EVENT_FL_UPROBE; + call->class->reg = trace_uprobe_register; + call->data = tu; +} + +static int register_uprobe_event(struct trace_uprobe *tu) +{ + struct trace_event_call *call = &tu->tp.call; + int ret = 0; + + init_trace_event_call(tu, call); + if (set_print_fmt(&tu->tp, is_ret_probe(tu)) < 0) return -ENOMEM; @@ -1311,9 +1320,6 @@ static int register_uprobe_event(struct trace_uprobe *tu) return -ENODEV; } - call->flags = TRACE_EVENT_FL_UPROBE; - call->class->reg = trace_uprobe_register; - call->data = tu; ret = trace_add_event_call(call); if (ret) { @@ -1339,6 +1345,70 @@ static int unregister_uprobe_event(struct trace_uprobe *tu) return 0; } +#ifdef CONFIG_PERF_EVENTS +struct trace_event_call * +create_local_trace_uprobe(char *name, unsigned long offs, bool is_return) +{ + struct trace_uprobe *tu; + struct inode *inode; + struct path path; + int ret; + + ret = kern_path(name, LOOKUP_FOLLOW, &path); + if (ret) + return ERR_PTR(ret); + + inode = igrab(d_inode(path.dentry)); + path_put(&path); + + if (!inode || !S_ISREG(inode->i_mode)) { + iput(inode); + return ERR_PTR(-EINVAL); + } + + /* + * local trace_kprobes are not added to probe_list, so they are never + * searched in find_trace_kprobe(). Therefore, there is no concern of + * duplicated name "DUMMY_EVENT" here. + */ + tu = alloc_trace_uprobe(UPROBE_EVENT_SYSTEM, "DUMMY_EVENT", 0, + is_return); + + if (IS_ERR(tu)) { + pr_info("Failed to allocate trace_uprobe.(%d)\n", + (int)PTR_ERR(tu)); + return ERR_CAST(tu); + } + + tu->offset = offs; + tu->inode = inode; + tu->filename = kstrdup(name, GFP_KERNEL); + init_trace_event_call(tu, &tu->tp.call); + + if (set_print_fmt(&tu->tp, is_ret_probe(tu)) < 0) { + ret = -ENOMEM; + goto error; + } + + return &tu->tp.call; +error: + free_trace_uprobe(tu); + return ERR_PTR(ret); +} + +void destroy_local_trace_uprobe(struct trace_event_call *event_call) +{ + struct trace_uprobe *tu; + + tu = container_of(event_call, struct trace_uprobe, tp.call); + + kfree(tu->tp.call.print_fmt); + tu->tp.call.print_fmt = NULL; + + free_trace_uprobe(tu); +} +#endif /* CONFIG_PERF_EVENTS */ + /* Make a trace interface for controling probe points */ static __init int init_uprobe_trace(void) { -- cgit v1.2.3 From 0c0eb4caf03bb6d3d92c70560e0530c8fdf62284 Mon Sep 17 00:00:00 2001 From: Zi Yan Date: Mon, 8 Jan 2018 10:50:50 -0500 Subject: dmaengine: avoid map_cnt overflow with CONFIG_DMA_ENGINE_RAID When CONFIG_DMA_ENGINE_RAID is enabled, unmap pool size can reach to 256. But in struct dmaengine_unmap_data, map_cnt is only u8, wrapping to 0, if the unmap pool is maximally used. This triggers BUG() when struct dmaengine_unmap_data is freed. Use u16 to fix the problem. Signed-off-by: Zi Yan Signed-off-by: Vinod Koul --- include/linux/dmaengine.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux') diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index f838764993eb..861be5cab1df 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -470,7 +470,11 @@ typedef void (*dma_async_tx_callback_result)(void *dma_async_param, const struct dmaengine_result *result); struct dmaengine_unmap_data { +#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) + u16 map_cnt; +#else u8 map_cnt; +#endif u8 to_cnt; u8 from_cnt; u8 bidi_cnt; -- cgit v1.2.3 From bd6f2fd5a1d52198468c5cdc3c2472362dff5aaa Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 30 Jan 2018 18:36:16 -0800 Subject: of: Support parsing phandle argument lists through a nexus node Platforms like 96boards have a standardized connector/expansion slot that exposes signals like GPIOs to expansion boards in an SoC agnostic way. We'd like the DT overlays for the expansion boards to be written once without knowledge of the SoC on the other side of the connector. This avoids the unscalable combinatorial explosion of a different DT overlay for each expansion board and SoC pair. We need a way to describe the GPIOs routed through the connector in an SoC agnostic way. Let's introduce nexus property parsing into the OF core to do this. This is largely based on the interrupt nexus support we already have. This allows us to remap a phandle list in a consumer node (e.g. reset-gpios) through a connector in a generic way (e.g. via gpio-map). Do this in a generic routine so that we can remap any sort of variable length phandle list. Taking GPIOs as an example, the connector would be a GPIO nexus, supporting the remapping of a GPIO specifier space to multiple GPIO providers on the SoC. DT would look as shown below, where 'soc_gpio1' and 'soc_gpio2' are inside the SoC, 'connector' is an expansion port where boards can be plugged in, and 'expansion_device' is a device on the expansion board. soc { soc_gpio1: gpio-controller1 { #gpio-cells = <2>; }; soc_gpio2: gpio-controller2 { #gpio-cells = <2>; }; }; connector: connector { #gpio-cells = <2>; gpio-map = <0 0 &soc_gpio1 1 0>, <1 0 &soc_gpio2 4 0>, <2 0 &soc_gpio1 3 0>, <3 0 &soc_gpio2 2 0>; gpio-map-mask = <0xf 0x0>; gpio-map-pass-thru = <0x0 0x1> }; expansion_device { reset-gpios = <&connector 2 GPIO_ACTIVE_LOW>; }; The GPIO core would use of_parse_phandle_with_args_map() instead of of_parse_phandle_with_args() and arrive at the same type of result, a phandle and argument list. The difference is that the phandle and arguments will be remapped through the nexus node to the underlying SoC GPIO controller node. In the example above, we would remap 'reset-gpios' from <&connector 2 GPIO_ACTIVE_LOW> to <&soc_gpio1 3 GPIO_ACTIVE_LOW>. Cc: Pantelis Antoniou Cc: Linus Walleij Cc: Mark Brown Signed-off-by: Stephen Boyd Signed-off-by: Rob Herring --- drivers/of/base.c | 184 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/of.h | 12 ++++ 2 files changed, 196 insertions(+) (limited to 'include/linux') diff --git a/drivers/of/base.c b/drivers/of/base.c index ad28de96e13f..091aa9449c3a 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -1283,6 +1283,190 @@ int of_parse_phandle_with_args(const struct device_node *np, const char *list_na } EXPORT_SYMBOL(of_parse_phandle_with_args); +/** + * of_parse_phandle_with_args_map() - Find a node pointed by phandle in a list and remap it + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @stem_name: stem of property names that specify phandles' arguments count + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate errno + * value. The difference between this function and of_parse_phandle_with_args() + * is that this API remaps a phandle if the node the phandle points to has + * a <@stem_name>-map property. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * phandle1: node1 { + * #list-cells = <2>; + * } + * + * phandle2: node2 { + * #list-cells = <1>; + * } + * + * phandle3: node3 { + * #list-cells = <1>; + * list-map = <0 &phandle2 3>, + * <1 &phandle2 2>, + * <2 &phandle1 5 1>; + * list-map-mask = <0x3>; + * }; + * + * node4 { + * list = <&phandle1 1 2 &phandle3 0>; + * } + * + * To get a device_node of the `node2' node you may call this: + * of_parse_phandle_with_args(node4, "list", "list", 1, &args); + */ +int of_parse_phandle_with_args_map(const struct device_node *np, + const char *list_name, + const char *stem_name, + int index, struct of_phandle_args *out_args) +{ + char *cells_name, *map_name = NULL, *mask_name = NULL; + char *pass_name = NULL; + struct device_node *cur, *new = NULL; + const __be32 *map, *mask, *pass; + static const __be32 dummy_mask[] = { [0 ... MAX_PHANDLE_ARGS] = ~0 }; + static const __be32 dummy_pass[] = { [0 ... MAX_PHANDLE_ARGS] = 0 }; + __be32 initial_match_array[MAX_PHANDLE_ARGS]; + const __be32 *match_array = initial_match_array; + int i, ret, map_len, match; + u32 list_size, new_size; + + if (index < 0) + return -EINVAL; + + cells_name = kasprintf(GFP_KERNEL, "#%s-cells", stem_name); + if (!cells_name) + return -ENOMEM; + + ret = -ENOMEM; + map_name = kasprintf(GFP_KERNEL, "%s-map", stem_name); + if (!map_name) + goto free; + + mask_name = kasprintf(GFP_KERNEL, "%s-map-mask", stem_name); + if (!mask_name) + goto free; + + pass_name = kasprintf(GFP_KERNEL, "%s-map-pass-thru", stem_name); + if (!pass_name) + goto free; + + ret = __of_parse_phandle_with_args(np, list_name, cells_name, 0, index, + out_args); + if (ret) + goto free; + + /* Get the #-cells property */ + cur = out_args->np; + ret = of_property_read_u32(cur, cells_name, &list_size); + if (ret < 0) + goto put; + + /* Precalculate the match array - this simplifies match loop */ + for (i = 0; i < list_size; i++) + initial_match_array[i] = cpu_to_be32(out_args->args[i]); + + ret = -EINVAL; + while (cur) { + /* Get the -map property */ + map = of_get_property(cur, map_name, &map_len); + if (!map) { + ret = 0; + goto free; + } + map_len /= sizeof(u32); + + /* Get the -map-mask property (optional) */ + mask = of_get_property(cur, mask_name, NULL); + if (!mask) + mask = dummy_mask; + /* Iterate through -map property */ + match = 0; + while (map_len > (list_size + 1) && !match) { + /* Compare specifiers */ + match = 1; + for (i = 0; i < list_size; i++, map_len--) + match &= !((match_array[i] ^ *map++) & mask[i]); + + of_node_put(new); + new = of_find_node_by_phandle(be32_to_cpup(map)); + map++; + map_len--; + + /* Check if not found */ + if (!new) + goto put; + + if (!of_device_is_available(new)) + match = 0; + + ret = of_property_read_u32(new, cells_name, &new_size); + if (ret) + goto put; + + /* Check for malformed properties */ + if (WARN_ON(new_size > MAX_PHANDLE_ARGS)) + goto put; + if (map_len < new_size) + goto put; + + /* Move forward by new node's #-cells amount */ + map += new_size; + map_len -= new_size; + } + if (!match) + goto put; + + /* Get the -map-pass-thru property (optional) */ + pass = of_get_property(cur, pass_name, NULL); + if (!pass) + pass = dummy_pass; + + /* + * Successfully parsed a -map translation; copy new + * specifier into the out_args structure, keeping the + * bits specified in -map-pass-thru. + */ + match_array = map - new_size; + for (i = 0; i < new_size; i++) { + __be32 val = *(map - new_size + i); + + if (i < list_size) { + val &= ~pass[i]; + val |= cpu_to_be32(out_args->args[i]) & pass[i]; + } + + out_args->args[i] = be32_to_cpu(val); + } + out_args->args_count = list_size = new_size; + /* Iterate again with new provider */ + out_args->np = new; + of_node_put(cur); + cur = new; + } +put: + of_node_put(cur); + of_node_put(new); +free: + kfree(mask_name); + kfree(map_name); + kfree(cells_name); + kfree(pass_name); + + return ret; +} +EXPORT_SYMBOL(of_parse_phandle_with_args_map); + /** * of_parse_phandle_with_fixed_args() - Find a node pointed by phandle in a list * @np: pointer to a device tree node containing a list diff --git a/include/linux/of.h b/include/linux/of.h index da1ee95241c1..7258bbc85e4e 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -363,6 +363,9 @@ extern struct device_node *of_parse_phandle(const struct device_node *np, extern int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, int index, struct of_phandle_args *out_args); +extern int of_parse_phandle_with_args_map(const struct device_node *np, + const char *list_name, const char *stem_name, int index, + struct of_phandle_args *out_args); extern int of_parse_phandle_with_fixed_args(const struct device_node *np, const char *list_name, int cells_count, int index, struct of_phandle_args *out_args); @@ -815,6 +818,15 @@ static inline int of_parse_phandle_with_args(const struct device_node *np, return -ENOSYS; } +static inline int of_parse_phandle_with_args_map(const struct device_node *np, + const char *list_name, + const char *stem_name, + int index, + struct of_phandle_args *out_args) +{ + return -ENOSYS; +} + static inline int of_parse_phandle_with_fixed_args(const struct device_node *np, const char *list_name, int cells_count, int index, struct of_phandle_args *out_args) -- cgit v1.2.3 From 34e81f7a720d8a638f46b18b35678712dbafb42d Mon Sep 17 00:00:00 2001 From: Hannes Reinecke Date: Wed, 24 Jan 2018 09:07:58 +0100 Subject: scsi: raid_class: Add 'JBOD' RAID level Not a real RAID level, but some HBAs support JBOD in addition to the 'classical' RAID levels. Signed-off-by: Hannes Reinecke Signed-off-by: Martin K. Petersen --- drivers/scsi/raid_class.c | 1 + include/linux/raid_class.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include/linux') diff --git a/drivers/scsi/raid_class.c b/drivers/scsi/raid_class.c index 2c146b44d95f..ea88906d2cc5 100644 --- a/drivers/scsi/raid_class.c +++ b/drivers/scsi/raid_class.c @@ -157,6 +157,7 @@ static struct { { RAID_LEVEL_5, "raid5" }, { RAID_LEVEL_50, "raid50" }, { RAID_LEVEL_6, "raid6" }, + { RAID_LEVEL_JBOD, "jbod" }, }; static const char *raid_level_name(enum raid_level level) diff --git a/include/linux/raid_class.h b/include/linux/raid_class.h index 31e1ff69efc8..ec8655514283 100644 --- a/include/linux/raid_class.h +++ b/include/linux/raid_class.h @@ -38,6 +38,7 @@ enum raid_level { RAID_LEVEL_5, RAID_LEVEL_50, RAID_LEVEL_6, + RAID_LEVEL_JBOD, }; struct raid_data { -- cgit v1.2.3 From f947153f92afcd957476b765dc4ac75d2680b17b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Jan 2018 19:29:54 +0100 Subject: ARM: EXYNOS: Add SPDX license identifiers Replace GPL license statements with SPDX GPL-2.0 and GPL-2.0+ license identifiers. Signed-off-by: Krzysztof Kozlowski --- arch/arm/include/debug/exynos.S | 7 ++----- arch/arm/include/debug/samsung.S | 10 +++------- include/linux/serial_s3c.h | 17 ++--------------- 3 files changed, 7 insertions(+), 27 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/include/debug/exynos.S b/arch/arm/include/debug/exynos.S index 60bf3c23200d..74b56769f9cb 100644 --- a/arch/arm/include/debug/exynos.S +++ b/arch/arm/include/debug/exynos.S @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ /* pull in the relevant register and map files. */ diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S index f4eeed2a1981..69201d7fb48f 100644 --- a/arch/arm/include/debug/samsung.S +++ b/arch/arm/include/debug/samsung.S @@ -1,13 +1,9 @@ -/* arch/arm/plat-samsung/include/plat/debug-macro.S - * +/* SPDX-License-Identifier: GPL-2.0 */ +/* * Copyright 2005, 2007 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #include diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index a7f004a3c177..463ed28d2b27 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Internal header file for Samsung S3C2410 serial ports (UART0-2) * @@ -10,21 +11,7 @@ * Internal header file for MX1ADS serial ports (UART1 & 2) * * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ + */ #ifndef __ASM_ARM_REGS_SERIAL_H #define __ASM_ARM_REGS_SERIAL_H -- cgit v1.2.3 From bcb41a53b0b075600cb821302e7177ca5ab62efd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Jan 2018 19:29:56 +0100 Subject: soc: samsung: Add SPDX license identifiers to headers Replace GPL license statements with SPDX GPL-2.0 license identifiers. Signed-off-by: Krzysztof Kozlowski --- include/linux/soc/samsung/exynos-pmu.h | 5 +---- include/linux/soc/samsung/exynos-regs-pmu.h | 6 +----- 2 files changed, 2 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/include/linux/soc/samsung/exynos-pmu.h b/include/linux/soc/samsung/exynos-pmu.h index e57eb4b6cc5a..fc0b445bb36b 100644 --- a/include/linux/soc/samsung/exynos-pmu.h +++ b/include/linux/soc/samsung/exynos-pmu.h @@ -1,12 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Header for EXYNOS PMU Driver support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __LINUX_SOC_EXYNOS_PMU_H diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index bebdde5dccd6..66dcb9ec273a 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1,14 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2010-2015 Samsung Electronics Co., Ltd. * http://www.samsung.com * * EXYNOS - Power management unit definition * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * * Notice: * This is not a list of all Exynos Power Management Unit SFRs. * There are too many of them, not mentioning subtle differences -- cgit v1.2.3 From 2666ca9197e3d352f43b02d7dfb7c6dd72e7c614 Mon Sep 17 00:00:00 2001 From: Sarangdhar Joshi Date: Fri, 5 Jan 2018 16:04:17 -0800 Subject: remoteproc: Add remote processor coredump support As the remoteproc framework restarts the remote processor after a fatal event, it's useful to be able to acquire a coredump of the remote processor's state, for post mortem debugging. This patch introduces a mechanism for extracting the memory contents after the remote has stopped and before the restart sequence has begun in the recovery path. The remoteproc framework builds the core dump in memory and use devcoredump to expose this to user space. Signed-off-by: Sarangdhar Joshi [bjorn: Use vmalloc instead of composing the ELF on the fly] Signed-off-by: Bjorn Andersson --- drivers/remoteproc/Kconfig | 1 + drivers/remoteproc/remoteproc_core.c | 128 +++++++++++++++++++++++++++++++++++ include/linux/remoteproc.h | 18 +++++ 3 files changed, 147 insertions(+) (limited to 'include/linux') diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index b609e1d3654b..3e4bca77188d 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -6,6 +6,7 @@ config REMOTEPROC select CRC32 select FW_LOADER select VIRTIO + select WANT_DEV_COREDUMP help Support for remote processors (such as DSP coprocessors). These are mainly used on embedded systems. diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c index 4170dfbd93bd..5af7547b9d8d 100644 --- a/drivers/remoteproc/remoteproc_core.c +++ b/drivers/remoteproc/remoteproc_core.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -801,6 +802,20 @@ static void rproc_remove_subdevices(struct rproc *rproc) subdev->remove(subdev); } +/** + * rproc_coredump_cleanup() - clean up dump_segments list + * @rproc: the remote processor handle + */ +static void rproc_coredump_cleanup(struct rproc *rproc) +{ + struct rproc_dump_segment *entry, *tmp; + + list_for_each_entry_safe(entry, tmp, &rproc->dump_segments, node) { + list_del(&entry->node); + kfree(entry); + } +} + /** * rproc_resource_cleanup() - clean up and free all acquired resources * @rproc: rproc handle @@ -848,6 +863,8 @@ static void rproc_resource_cleanup(struct rproc *rproc) /* clean up remote vdev entries */ list_for_each_entry_safe(rvdev, rvtmp, &rproc->rvdevs, node) kref_put(&rvdev->refcount, rproc_vdev_release); + + rproc_coredump_cleanup(rproc); } static int rproc_start(struct rproc *rproc, const struct firmware *fw) @@ -1017,6 +1034,113 @@ static int rproc_stop(struct rproc *rproc) return 0; } +/** + * rproc_coredump_add_segment() - add segment of device memory to coredump + * @rproc: handle of a remote processor + * @da: device address + * @size: size of segment + * + * Add device memory to the list of segments to be included in a coredump for + * the remoteproc. + * + * Return: 0 on success, negative errno on error. + */ +int rproc_coredump_add_segment(struct rproc *rproc, dma_addr_t da, size_t size) +{ + struct rproc_dump_segment *segment; + + segment = kzalloc(sizeof(*segment), GFP_KERNEL); + if (!segment) + return -ENOMEM; + + segment->da = da; + segment->size = size; + + list_add_tail(&segment->node, &rproc->dump_segments); + + return 0; +} +EXPORT_SYMBOL(rproc_coredump_add_segment); + +/** + * rproc_coredump() - perform coredump + * @rproc: rproc handle + * + * This function will generate an ELF header for the registered segments + * and create a devcoredump device associated with rproc. + */ +static void rproc_coredump(struct rproc *rproc) +{ + struct rproc_dump_segment *segment; + struct elf32_phdr *phdr; + struct elf32_hdr *ehdr; + size_t data_size; + size_t offset; + void *data; + void *ptr; + int phnum = 0; + + if (list_empty(&rproc->dump_segments)) + return; + + data_size = sizeof(*ehdr); + list_for_each_entry(segment, &rproc->dump_segments, node) { + data_size += sizeof(*phdr) + segment->size; + + phnum++; + } + + data = vmalloc(data_size); + if (!data) + return; + + ehdr = data; + + memset(ehdr, 0, sizeof(*ehdr)); + memcpy(ehdr->e_ident, ELFMAG, SELFMAG); + ehdr->e_ident[EI_CLASS] = ELFCLASS32; + ehdr->e_ident[EI_DATA] = ELFDATA2LSB; + ehdr->e_ident[EI_VERSION] = EV_CURRENT; + ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE; + ehdr->e_type = ET_CORE; + ehdr->e_machine = EM_NONE; + ehdr->e_version = EV_CURRENT; + ehdr->e_entry = rproc->bootaddr; + ehdr->e_phoff = sizeof(*ehdr); + ehdr->e_ehsize = sizeof(*ehdr); + ehdr->e_phentsize = sizeof(*phdr); + ehdr->e_phnum = phnum; + + phdr = data + ehdr->e_phoff; + offset = ehdr->e_phoff + sizeof(*phdr) * ehdr->e_phnum; + list_for_each_entry(segment, &rproc->dump_segments, node) { + memset(phdr, 0, sizeof(*phdr)); + phdr->p_type = PT_LOAD; + phdr->p_offset = offset; + phdr->p_vaddr = segment->da; + phdr->p_paddr = segment->da; + phdr->p_filesz = segment->size; + phdr->p_memsz = segment->size; + phdr->p_flags = PF_R | PF_W | PF_X; + phdr->p_align = 0; + + ptr = rproc_da_to_va(rproc, segment->da, segment->size); + if (!ptr) { + dev_err(&rproc->dev, + "invalid coredump segment (%pad, %zu)\n", + &segment->da, segment->size); + memset(data + offset, 0xff, segment->size); + } else { + memcpy(data + offset, ptr, segment->size); + } + + offset += phdr->p_filesz; + phdr++; + } + + dev_coredumpv(&rproc->dev, data, data_size, GFP_KERNEL); +} + /** * rproc_trigger_recovery() - recover a remoteproc * @rproc: the remote processor @@ -1043,6 +1167,9 @@ int rproc_trigger_recovery(struct rproc *rproc) if (ret) goto unlock_mutex; + /* generate coredump */ + rproc_coredump(rproc); + /* load firmware */ ret = request_firmware(&firmware_p, rproc->firmware, dev); if (ret < 0) { @@ -1443,6 +1570,7 @@ struct rproc *rproc_alloc(struct device *dev, const char *name, INIT_LIST_HEAD(&rproc->traces); INIT_LIST_HEAD(&rproc->rvdevs); INIT_LIST_HEAD(&rproc->subdevs); + INIT_LIST_HEAD(&rproc->dump_segments); INIT_WORK(&rproc->crash_handler, rproc_crash_handler_work); diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index 728d421fffe9..b60c3a31b75d 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -394,6 +394,21 @@ enum rproc_crash_type { RPROC_FATAL_ERROR, }; +/** + * struct rproc_dump_segment - segment info from ELF header + * @node: list node related to the rproc segment list + * @da: device address of the segment + * @size: size of the segment + */ +struct rproc_dump_segment { + struct list_head node; + + dma_addr_t da; + size_t size; + + loff_t offset; +}; + /** * struct rproc - represents a physical remote processor device * @node: list node of this rproc object @@ -424,6 +439,7 @@ enum rproc_crash_type { * @cached_table: copy of the resource table * @table_sz: size of @cached_table * @has_iommu: flag to indicate if remote processor is behind an MMU + * @dump_segments: list of segments in the firmware */ struct rproc { struct list_head node; @@ -455,6 +471,7 @@ struct rproc { size_t table_sz; bool has_iommu; bool auto_boot; + struct list_head dump_segments; }; /** @@ -534,6 +551,7 @@ void rproc_free(struct rproc *rproc); int rproc_boot(struct rproc *rproc); void rproc_shutdown(struct rproc *rproc); void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type); +int rproc_coredump_add_segment(struct rproc *rproc, dma_addr_t da, size_t size); static inline struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev) { -- cgit v1.2.3 From c1d35c1ab4242464a0e5953ae69de8aa78156c6c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 5 Jan 2018 16:04:18 -0800 Subject: remoteproc: Rename "load_rsc_table" to "parse_fw" The resource table is just one possible source of information that can be extracted from the firmware file. Generalize this interface to allow drivers to override this with parsers of other types of information. Signed-off-by: Bjorn Andersson --- drivers/remoteproc/remoteproc_core.c | 6 +++--- drivers/remoteproc/remoteproc_internal.h | 7 +++---- include/linux/remoteproc.h | 2 +- 3 files changed, 7 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c index 5af7547b9d8d..fd257607a578 100644 --- a/drivers/remoteproc/remoteproc_core.c +++ b/drivers/remoteproc/remoteproc_core.c @@ -944,8 +944,8 @@ static int rproc_fw_boot(struct rproc *rproc, const struct firmware *fw) rproc->bootaddr = rproc_get_boot_addr(rproc, fw); - /* load resource table */ - ret = rproc_load_rsc_table(rproc, fw); + /* Load resource table, core dump segment list etc from the firmware */ + ret = rproc_parse_fw(rproc, fw); if (ret) goto disable_iommu; @@ -1555,7 +1555,7 @@ struct rproc *rproc_alloc(struct device *dev, const char *name, /* Default to ELF loader if no load function is specified */ if (!rproc->ops->load) { rproc->ops->load = rproc_elf_load_segments; - rproc->ops->load_rsc_table = rproc_elf_load_rsc_table; + rproc->ops->parse_fw = rproc_elf_load_rsc_table; rproc->ops->find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table; rproc->ops->sanity_check = rproc_elf_sanity_check; rproc->ops->get_boot_addr = rproc_elf_get_boot_addr; diff --git a/drivers/remoteproc/remoteproc_internal.h b/drivers/remoteproc/remoteproc_internal.h index 55a2950c5cb7..7570beb035b5 100644 --- a/drivers/remoteproc/remoteproc_internal.h +++ b/drivers/remoteproc/remoteproc_internal.h @@ -88,11 +88,10 @@ int rproc_load_segments(struct rproc *rproc, const struct firmware *fw) return -EINVAL; } -static inline int rproc_load_rsc_table(struct rproc *rproc, - const struct firmware *fw) +static inline int rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) { - if (rproc->ops->load_rsc_table) - return rproc->ops->load_rsc_table(rproc, fw); + if (rproc->ops->parse_fw) + return rproc->ops->parse_fw(rproc, fw); return 0; } diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index b60c3a31b75d..f16864acedad 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -344,7 +344,7 @@ struct rproc_ops { int (*stop)(struct rproc *rproc); void (*kick)(struct rproc *rproc, int vqid); void * (*da_to_va)(struct rproc *rproc, u64 da, int len); - int (*load_rsc_table)(struct rproc *rproc, const struct firmware *fw); + int (*parse_fw)(struct rproc *rproc, const struct firmware *fw); struct resource_table *(*find_loaded_rsc_table)( struct rproc *rproc, const struct firmware *fw); int (*load)(struct rproc *rproc, const struct firmware *fw); -- cgit v1.2.3 From 4dd27f544c84c4d079049dd716beee192fcc7e03 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 5 Jan 2018 16:04:19 -0800 Subject: soc: qcom: mdt-loader: Return relocation base In order to implement support for grabbing core dumps in remoteproc it's necessary to know the relocated base of the image, as the offsets from the virtual memory base might not be based on the physical address. Return the adjusted physical base address to the caller. Acked-by: Andy Gross Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- drivers/media/platform/qcom/venus/firmware.c | 2 +- drivers/remoteproc/qcom_adsp_pil.c | 4 +++- drivers/remoteproc/qcom_wcnss.c | 3 ++- drivers/soc/qcom/mdt_loader.c | 7 ++++++- include/linux/soc/qcom/mdt_loader.h | 3 ++- 6 files changed, 16 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 7e09d44e4a15..8676fa9a9f49 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -89,14 +89,14 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname) */ if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { ret = qcom_mdt_load(dev, fw, fwname, GPU_PAS_ID, - mem_region, mem_phys, mem_size); + mem_region, mem_phys, mem_size, NULL); } else { char newname[strlen("qcom/") + strlen(fwname) + 1]; sprintf(newname, "qcom/%s", fwname); ret = qcom_mdt_load(dev, fw, newname, GPU_PAS_ID, - mem_region, mem_phys, mem_size); + mem_region, mem_phys, mem_size, NULL); } if (ret) goto out; diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c index 521d4b36c090..c4a577848dd7 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -76,7 +76,7 @@ int venus_boot(struct device *dev, const char *fwname) } ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID, mem_va, mem_phys, - mem_size); + mem_size, NULL); release_firmware(mdt); diff --git a/drivers/remoteproc/qcom_adsp_pil.c b/drivers/remoteproc/qcom_adsp_pil.c index 4a2ee6c5816c..ca2bda9bc71d 100644 --- a/drivers/remoteproc/qcom_adsp_pil.c +++ b/drivers/remoteproc/qcom_adsp_pil.c @@ -82,7 +82,9 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw) struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id, - adsp->mem_region, adsp->mem_phys, adsp->mem_size); + adsp->mem_region, adsp->mem_phys, adsp->mem_size, + &adsp->mem_reloc); + } static int adsp_start(struct rproc *rproc) diff --git a/drivers/remoteproc/qcom_wcnss.c b/drivers/remoteproc/qcom_wcnss.c index 043f3d3dea7d..f1ae5ecbc392 100644 --- a/drivers/remoteproc/qcom_wcnss.c +++ b/drivers/remoteproc/qcom_wcnss.c @@ -153,7 +153,8 @@ static int wcnss_load(struct rproc *rproc, const struct firmware *fw) struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID, - wcnss->mem_region, wcnss->mem_phys, wcnss->mem_size); + wcnss->mem_region, wcnss->mem_phys, + wcnss->mem_size, &wcnss->mem_reloc); } static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss) diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 08bd8549242a..17b314d9a148 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -83,12 +83,14 @@ EXPORT_SYMBOL_GPL(qcom_mdt_get_size); * @mem_region: allocated memory region to load firmware into * @mem_phys: physical address of allocated memory region * @mem_size: size of the allocated memory region + * @reloc_base: adjusted physical address after relocation * * Returns 0 on success, negative errno otherwise. */ int qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *firmware, int pas_id, void *mem_region, - phys_addr_t mem_phys, size_t mem_size) + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; @@ -192,6 +194,9 @@ int qcom_mdt_load(struct device *dev, const struct firmware *fw, memset(ptr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz); } + if (reloc_base) + *reloc_base = mem_reloc; + out: kfree(fw_name); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/mdt_loader.h index bd8e0864b059..5b98bbdabc25 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -14,6 +14,7 @@ struct firmware; ssize_t qcom_mdt_get_size(const struct firmware *fw); int qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, - phys_addr_t mem_phys, size_t mem_size); + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base); #endif -- cgit v1.2.3 From 9b2c45d479d0fb8647c9e83359df69162b5fbe5f Mon Sep 17 00:00:00 2001 From: Denys Vlasenko Date: Mon, 12 Feb 2018 20:00:20 +0100 Subject: net: make getname() functions return length rather than use int* parameter Changes since v1: Added changes in these files: drivers/infiniband/hw/usnic/usnic_transport.c drivers/staging/lustre/lnet/lnet/lib-socket.c drivers/target/iscsi/iscsi_target_login.c drivers/vhost/net.c fs/dlm/lowcomms.c fs/ocfs2/cluster/tcp.c security/tomoyo/network.c Before: All these functions either return a negative error indicator, or store length of sockaddr into "int *socklen" parameter and return zero on success. "int *socklen" parameter is awkward. For example, if caller does not care, it still needs to provide on-stack storage for the value it does not need. None of the many FOO_getname() functions of various protocols ever used old value of *socklen. They always just overwrite it. This change drops this parameter, and makes all these functions, on success, return length of sockaddr. It's always >= 0 and can be differentiated from an error. Tests in callers are changed from "if (err)" to "if (err < 0)", where needed. rpc_sockname() lost "int buflen" parameter, since its only use was to be passed to kernel_getsockname() as &buflen and subsequently not used in any way. Userspace API is not changed. text data bss dec hex filename 30108430 2633624 873672 33615726 200ef6e vmlinux.before.o 30108109 2633612 873672 33615393 200ee21 vmlinux.o Signed-off-by: Denys Vlasenko CC: David S. Miller CC: linux-kernel@vger.kernel.org CC: netdev@vger.kernel.org CC: linux-bluetooth@vger.kernel.org CC: linux-decnet-user@lists.sourceforge.net CC: linux-wireless@vger.kernel.org CC: linux-rdma@vger.kernel.org CC: linux-sctp@vger.kernel.org CC: linux-nfs@vger.kernel.org CC: linux-x25@vger.kernel.org Signed-off-by: David S. Miller --- drivers/infiniband/hw/usnic/usnic_transport.c | 5 ++-- drivers/isdn/mISDN/socket.c | 5 ++-- drivers/net/ppp/pppoe.c | 6 ++--- drivers/net/ppp/pptp.c | 6 ++--- drivers/scsi/iscsi_tcp.c | 14 +++++------ drivers/soc/qcom/qmi_interface.c | 3 +-- drivers/staging/ipx/af_ipx.c | 6 ++--- drivers/staging/irda/net/af_irda.c | 8 +++--- drivers/staging/lustre/lnet/lnet/lib-socket.c | 7 +++--- drivers/target/iscsi/iscsi_target_login.c | 18 +++++++------- drivers/vhost/net.c | 7 +++--- fs/dlm/lowcomms.c | 7 +++--- fs/ocfs2/cluster/tcp.c | 6 ++--- include/linux/net.h | 8 +++--- include/net/inet_common.h | 2 +- include/net/ipv6.h | 2 +- include/net/sock.h | 2 +- net/appletalk/ddp.c | 5 ++-- net/atm/pvc.c | 5 ++-- net/atm/svc.c | 5 ++-- net/ax25/af_ax25.c | 4 +-- net/bluetooth/hci_sock.c | 4 +-- net/bluetooth/l2cap_sock.c | 5 ++-- net/bluetooth/rfcomm/sock.c | 5 ++-- net/bluetooth/sco.c | 5 ++-- net/can/raw.c | 6 ++--- net/core/sock.c | 5 ++-- net/decnet/af_decnet.c | 6 ++--- net/ipv4/af_inet.c | 5 ++-- net/ipv6/af_inet6.c | 5 ++-- net/iucv/af_iucv.c | 5 ++-- net/l2tp/l2tp_ip.c | 5 ++-- net/l2tp/l2tp_ip6.c | 5 ++-- net/l2tp/l2tp_ppp.c | 5 ++-- net/llc/af_llc.c | 5 ++-- net/netlink/af_netlink.c | 5 ++-- net/netrom/af_netrom.c | 9 ++++--- net/nfc/llcp_sock.c | 5 ++-- net/packet/af_packet.c | 10 +++----- net/phonet/socket.c | 5 ++-- net/qrtr/qrtr.c | 5 ++-- net/rds/af_rds.c | 5 ++-- net/rds/tcp.c | 7 ++---- net/rose/af_rose.c | 5 ++-- net/sctp/ipv6.c | 8 +++--- net/smc/af_smc.c | 11 ++++----- net/socket.c | 35 +++++++++++++-------------- net/sunrpc/clnt.c | 6 ++--- net/sunrpc/svcsock.c | 13 ++++++---- net/sunrpc/xprtsock.c | 3 +-- net/tipc/socket.c | 5 ++-- net/unix/af_unix.c | 10 ++++---- net/vmw_vsock/af_vsock.c | 4 +-- net/x25/af_x25.c | 4 +-- security/tomoyo/network.c | 5 ++-- 55 files changed, 159 insertions(+), 203 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/usnic/usnic_transport.c b/drivers/infiniband/hw/usnic/usnic_transport.c index de318389a301..67de94343cb4 100644 --- a/drivers/infiniband/hw/usnic/usnic_transport.c +++ b/drivers/infiniband/hw/usnic/usnic_transport.c @@ -174,14 +174,13 @@ void usnic_transport_put_socket(struct socket *sock) int usnic_transport_sock_get_addr(struct socket *sock, int *proto, uint32_t *addr, uint16_t *port) { - int len; int err; struct sockaddr_in sock_addr; err = sock->ops->getname(sock, (struct sockaddr *)&sock_addr, - &len, 0); - if (err) + 0); + if (err < 0) return err; if (sock_addr.sin_family != AF_INET) diff --git a/drivers/isdn/mISDN/socket.c b/drivers/isdn/mISDN/socket.c index c5603d1a07d6..1f8f489b4167 100644 --- a/drivers/isdn/mISDN/socket.c +++ b/drivers/isdn/mISDN/socket.c @@ -560,7 +560,7 @@ done: static int data_sock_getname(struct socket *sock, struct sockaddr *addr, - int *addr_len, int peer) + int peer) { struct sockaddr_mISDN *maddr = (struct sockaddr_mISDN *) addr; struct sock *sk = sock->sk; @@ -570,14 +570,13 @@ data_sock_getname(struct socket *sock, struct sockaddr *addr, lock_sock(sk); - *addr_len = sizeof(*maddr); maddr->family = AF_ISDN; maddr->dev = _pms(sk)->dev->id; maddr->channel = _pms(sk)->ch.nr; maddr->sapi = _pms(sk)->ch.addr & 0xff; maddr->tei = (_pms(sk)->ch.addr >> 8) & 0xff; release_sock(sk); - return 0; + return sizeof(*maddr); } static const struct proto_ops data_sock_ops = { diff --git a/drivers/net/ppp/pppoe.c b/drivers/net/ppp/pppoe.c index 5aa59f41bf8c..bd89d1c559ce 100644 --- a/drivers/net/ppp/pppoe.c +++ b/drivers/net/ppp/pppoe.c @@ -714,7 +714,7 @@ err_put: } static int pppoe_getname(struct socket *sock, struct sockaddr *uaddr, - int *usockaddr_len, int peer) + int peer) { int len = sizeof(struct sockaddr_pppox); struct sockaddr_pppox sp; @@ -726,9 +726,7 @@ static int pppoe_getname(struct socket *sock, struct sockaddr *uaddr, memcpy(uaddr, &sp, len); - *usockaddr_len = len; - - return 0; + return len; } static int pppoe_ioctl(struct socket *sock, unsigned int cmd, diff --git a/drivers/net/ppp/pptp.c b/drivers/net/ppp/pptp.c index 6dde9a0cfe76..8249d46a7844 100644 --- a/drivers/net/ppp/pptp.c +++ b/drivers/net/ppp/pptp.c @@ -483,7 +483,7 @@ static int pptp_connect(struct socket *sock, struct sockaddr *uservaddr, } static int pptp_getname(struct socket *sock, struct sockaddr *uaddr, - int *usockaddr_len, int peer) + int peer) { int len = sizeof(struct sockaddr_pppox); struct sockaddr_pppox sp; @@ -496,9 +496,7 @@ static int pptp_getname(struct socket *sock, struct sockaddr *uaddr, memcpy(uaddr, &sp, len); - *usockaddr_len = len; - - return 0; + return len; } static int pptp_release(struct socket *sock) diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 6198559abbd8..0ad00dbf912d 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -732,7 +732,7 @@ static int iscsi_sw_tcp_conn_get_param(struct iscsi_cls_conn *cls_conn, struct iscsi_tcp_conn *tcp_conn = conn->dd_data; struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data; struct sockaddr_in6 addr; - int rc, len; + int rc; switch(param) { case ISCSI_PARAM_CONN_PORT: @@ -745,12 +745,12 @@ static int iscsi_sw_tcp_conn_get_param(struct iscsi_cls_conn *cls_conn, } if (param == ISCSI_PARAM_LOCAL_PORT) rc = kernel_getsockname(tcp_sw_conn->sock, - (struct sockaddr *)&addr, &len); + (struct sockaddr *)&addr); else rc = kernel_getpeername(tcp_sw_conn->sock, - (struct sockaddr *)&addr, &len); + (struct sockaddr *)&addr); spin_unlock_bh(&conn->session->frwd_lock); - if (rc) + if (rc < 0) return rc; return iscsi_conn_get_addr_param((struct sockaddr_storage *) @@ -771,7 +771,7 @@ static int iscsi_sw_tcp_host_get_param(struct Scsi_Host *shost, struct iscsi_tcp_conn *tcp_conn; struct iscsi_sw_tcp_conn *tcp_sw_conn; struct sockaddr_in6 addr; - int rc, len; + int rc; switch (param) { case ISCSI_HOST_PARAM_IPADDRESS: @@ -793,9 +793,9 @@ static int iscsi_sw_tcp_host_get_param(struct Scsi_Host *shost, } rc = kernel_getsockname(tcp_sw_conn->sock, - (struct sockaddr *)&addr, &len); + (struct sockaddr *)&addr); spin_unlock_bh(&session->frwd_lock); - if (rc) + if (rc < 0) return rc; return iscsi_conn_get_addr_param((struct sockaddr_storage *) diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index 877611d5c42b..321982277697 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -586,7 +586,6 @@ static struct socket *qmi_sock_create(struct qmi_handle *qmi, struct sockaddr_qrtr *sq) { struct socket *sock; - int sl = sizeof(*sq); int ret; ret = sock_create_kern(&init_net, AF_QIPCRTR, SOCK_DGRAM, @@ -594,7 +593,7 @@ static struct socket *qmi_sock_create(struct qmi_handle *qmi, if (ret < 0) return ERR_PTR(ret); - ret = kernel_getsockname(sock, (struct sockaddr *)sq, &sl); + ret = kernel_getsockname(sock, (struct sockaddr *)sq); if (ret < 0) { sock_release(sock); return ERR_PTR(ret); diff --git a/drivers/staging/ipx/af_ipx.c b/drivers/staging/ipx/af_ipx.c index d21a9d128d3e..5703dd176787 100644 --- a/drivers/staging/ipx/af_ipx.c +++ b/drivers/staging/ipx/af_ipx.c @@ -1577,7 +1577,7 @@ out: static int ipx_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct ipx_address *addr; struct sockaddr_ipx sipx; @@ -1585,8 +1585,6 @@ static int ipx_getname(struct socket *sock, struct sockaddr *uaddr, struct ipx_sock *ipxs = ipx_sk(sk); int rc; - *uaddr_len = sizeof(struct sockaddr_ipx); - lock_sock(sk); if (peer) { rc = -ENOTCONN; @@ -1620,7 +1618,7 @@ static int ipx_getname(struct socket *sock, struct sockaddr *uaddr, sipx.sipx_zero = 0; memcpy(uaddr, &sipx, sizeof(sipx)); - rc = 0; + rc = sizeof(struct sockaddr_ipx); out: release_sock(sk); return rc; diff --git a/drivers/staging/irda/net/af_irda.c b/drivers/staging/irda/net/af_irda.c index 2f1e9ab3d6d0..c13553a9ee11 100644 --- a/drivers/staging/irda/net/af_irda.c +++ b/drivers/staging/irda/net/af_irda.c @@ -697,7 +697,7 @@ static int irda_discover_daddr_and_lsap_sel(struct irda_sock *self, char *name) * */ static int irda_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sockaddr_irda saddr; struct sock *sk = sock->sk; @@ -720,11 +720,9 @@ static int irda_getname(struct socket *sock, struct sockaddr *uaddr, pr_debug("%s(), tsap_sel = %#x\n", __func__, saddr.sir_lsap_sel); pr_debug("%s(), addr = %08x\n", __func__, saddr.sir_addr); - /* uaddr_len come to us uninitialised */ - *uaddr_len = sizeof (struct sockaddr_irda); - memcpy(uaddr, &saddr, *uaddr_len); + memcpy(uaddr, &saddr, sizeof (struct sockaddr_irda)); - return 0; + return sizeof (struct sockaddr_irda); } /* diff --git a/drivers/staging/lustre/lnet/lnet/lib-socket.c b/drivers/staging/lustre/lnet/lnet/lib-socket.c index ce93806eefca..1bee667802b0 100644 --- a/drivers/staging/lustre/lnet/lnet/lib-socket.c +++ b/drivers/staging/lustre/lnet/lnet/lib-socket.c @@ -448,14 +448,13 @@ int lnet_sock_getaddr(struct socket *sock, bool remote, __u32 *ip, int *port) { struct sockaddr_in sin; - int len = sizeof(sin); int rc; if (remote) - rc = kernel_getpeername(sock, (struct sockaddr *)&sin, &len); + rc = kernel_getpeername(sock, (struct sockaddr *)&sin); else - rc = kernel_getsockname(sock, (struct sockaddr *)&sin, &len); - if (rc) { + rc = kernel_getsockname(sock, (struct sockaddr *)&sin); + if (rc < 0) { CERROR("Error %d getting sock %s IP/port\n", rc, remote ? "peer" : "local"); return rc; diff --git a/drivers/target/iscsi/iscsi_target_login.c b/drivers/target/iscsi/iscsi_target_login.c index 64c5a57b92e4..99501785cdc1 100644 --- a/drivers/target/iscsi/iscsi_target_login.c +++ b/drivers/target/iscsi/iscsi_target_login.c @@ -1020,7 +1020,7 @@ int iscsit_accept_np(struct iscsi_np *np, struct iscsi_conn *conn) struct socket *new_sock, *sock = np->np_socket; struct sockaddr_in sock_in; struct sockaddr_in6 sock_in6; - int rc, err; + int rc; rc = kernel_accept(sock, &new_sock, 0); if (rc < 0) @@ -1033,8 +1033,8 @@ int iscsit_accept_np(struct iscsi_np *np, struct iscsi_conn *conn) memset(&sock_in6, 0, sizeof(struct sockaddr_in6)); rc = conn->sock->ops->getname(conn->sock, - (struct sockaddr *)&sock_in6, &err, 1); - if (!rc) { + (struct sockaddr *)&sock_in6, 1); + if (rc >= 0) { if (!ipv6_addr_v4mapped(&sock_in6.sin6_addr)) { memcpy(&conn->login_sockaddr, &sock_in6, sizeof(sock_in6)); } else { @@ -1047,8 +1047,8 @@ int iscsit_accept_np(struct iscsi_np *np, struct iscsi_conn *conn) } rc = conn->sock->ops->getname(conn->sock, - (struct sockaddr *)&sock_in6, &err, 0); - if (!rc) { + (struct sockaddr *)&sock_in6, 0); + if (rc >= 0) { if (!ipv6_addr_v4mapped(&sock_in6.sin6_addr)) { memcpy(&conn->local_sockaddr, &sock_in6, sizeof(sock_in6)); } else { @@ -1063,13 +1063,13 @@ int iscsit_accept_np(struct iscsi_np *np, struct iscsi_conn *conn) memset(&sock_in, 0, sizeof(struct sockaddr_in)); rc = conn->sock->ops->getname(conn->sock, - (struct sockaddr *)&sock_in, &err, 1); - if (!rc) + (struct sockaddr *)&sock_in, 1); + if (rc >= 0) memcpy(&conn->login_sockaddr, &sock_in, sizeof(sock_in)); rc = conn->sock->ops->getname(conn->sock, - (struct sockaddr *)&sock_in, &err, 0); - if (!rc) + (struct sockaddr *)&sock_in, 0); + if (rc >= 0) memcpy(&conn->local_sockaddr, &sock_in, sizeof(sock_in)); } diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c index 610cba276d47..b5fb56b822fd 100644 --- a/drivers/vhost/net.c +++ b/drivers/vhost/net.c @@ -1038,7 +1038,7 @@ static struct socket *get_raw_socket(int fd) struct sockaddr_ll sa; char buf[MAX_ADDR_LEN]; } uaddr; - int uaddr_len = sizeof uaddr, r; + int r; struct socket *sock = sockfd_lookup(fd, &r); if (!sock) @@ -1050,9 +1050,8 @@ static struct socket *get_raw_socket(int fd) goto err; } - r = sock->ops->getname(sock, (struct sockaddr *)&uaddr.sa, - &uaddr_len, 0); - if (r) + r = sock->ops->getname(sock, (struct sockaddr *)&uaddr.sa, 0); + if (r < 0) goto err; if (uaddr.sa.sll_family != AF_PACKET) { diff --git a/fs/dlm/lowcomms.c b/fs/dlm/lowcomms.c index cff79ea0c01d..5243989a60cc 100644 --- a/fs/dlm/lowcomms.c +++ b/fs/dlm/lowcomms.c @@ -482,7 +482,6 @@ static void lowcomms_error_report(struct sock *sk) { struct connection *con; struct sockaddr_storage saddr; - int buflen; void (*orig_report)(struct sock *) = NULL; read_lock_bh(&sk->sk_callback_lock); @@ -492,7 +491,7 @@ static void lowcomms_error_report(struct sock *sk) orig_report = listen_sock.sk_error_report; if (con->sock == NULL || - kernel_getpeername(con->sock, (struct sockaddr *)&saddr, &buflen)) { + kernel_getpeername(con->sock, (struct sockaddr *)&saddr) < 0) { printk_ratelimited(KERN_ERR "dlm: node %d: socket error " "sending to node %d, port %d, " "sk_err=%d/%d\n", dlm_our_nodeid(), @@ -757,8 +756,8 @@ static int tcp_accept_from_sock(struct connection *con) /* Get the connected socket's peer */ memset(&peeraddr, 0, sizeof(peeraddr)); - if (newsock->ops->getname(newsock, (struct sockaddr *)&peeraddr, - &len, 2)) { + len = newsock->ops->getname(newsock, (struct sockaddr *)&peeraddr, 2); + if (len < 0) { result = -ECONNABORTED; goto accept_err; } diff --git a/fs/ocfs2/cluster/tcp.c b/fs/ocfs2/cluster/tcp.c index eac5140aac47..e5076185cc1e 100644 --- a/fs/ocfs2/cluster/tcp.c +++ b/fs/ocfs2/cluster/tcp.c @@ -1819,7 +1819,7 @@ int o2net_register_hb_callbacks(void) static int o2net_accept_one(struct socket *sock, int *more) { - int ret, slen; + int ret; struct sockaddr_in sin; struct socket *new_sock = NULL; struct o2nm_node *node = NULL; @@ -1864,9 +1864,7 @@ static int o2net_accept_one(struct socket *sock, int *more) goto out; } - slen = sizeof(sin); - ret = new_sock->ops->getname(new_sock, (struct sockaddr *) &sin, - &slen, 1); + ret = new_sock->ops->getname(new_sock, (struct sockaddr *) &sin, 1); if (ret < 0) goto out; diff --git a/include/linux/net.h b/include/linux/net.h index 91216b16feb7..000d1aada74f 100644 --- a/include/linux/net.h +++ b/include/linux/net.h @@ -146,7 +146,7 @@ struct proto_ops { struct socket *newsock, int flags, bool kern); int (*getname) (struct socket *sock, struct sockaddr *addr, - int *sockaddr_len, int peer); + int peer); __poll_t (*poll) (struct file *file, struct socket *sock, struct poll_table_struct *wait); int (*ioctl) (struct socket *sock, unsigned int cmd, @@ -294,10 +294,8 @@ int kernel_listen(struct socket *sock, int backlog); int kernel_accept(struct socket *sock, struct socket **newsock, int flags); int kernel_connect(struct socket *sock, struct sockaddr *addr, int addrlen, int flags); -int kernel_getsockname(struct socket *sock, struct sockaddr *addr, - int *addrlen); -int kernel_getpeername(struct socket *sock, struct sockaddr *addr, - int *addrlen); +int kernel_getsockname(struct socket *sock, struct sockaddr *addr); +int kernel_getpeername(struct socket *sock, struct sockaddr *addr); int kernel_getsockopt(struct socket *sock, int level, int optname, char *optval, int *optlen); int kernel_setsockopt(struct socket *sock, int level, int optname, char *optval, diff --git a/include/net/inet_common.h b/include/net/inet_common.h index 5a54c9570977..500f81375200 100644 --- a/include/net/inet_common.h +++ b/include/net/inet_common.h @@ -32,7 +32,7 @@ int inet_shutdown(struct socket *sock, int how); int inet_listen(struct socket *sock, int backlog); void inet_sock_destruct(struct sock *sk); int inet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len); -int inet_getname(struct socket *sock, struct sockaddr *uaddr, int *uaddr_len, +int inet_getname(struct socket *sock, struct sockaddr *uaddr, int peer); int inet_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg); int inet_ctl_sock_create(struct sock **sk, unsigned short family, diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 8606c9113d3f..7a98cd583c73 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -1056,7 +1056,7 @@ void ipv6_local_rxpmtu(struct sock *sk, struct flowi6 *fl6, u32 mtu); int inet6_release(struct socket *sock); int inet6_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len); -int inet6_getname(struct socket *sock, struct sockaddr *uaddr, int *uaddr_len, +int inet6_getname(struct socket *sock, struct sockaddr *uaddr, int peer); int inet6_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg); diff --git a/include/net/sock.h b/include/net/sock.h index 169c92afcafa..3aa7b7d6e6c7 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1584,7 +1584,7 @@ int sock_no_bind(struct socket *, struct sockaddr *, int); int sock_no_connect(struct socket *, struct sockaddr *, int, int); int sock_no_socketpair(struct socket *, struct socket *); int sock_no_accept(struct socket *, struct socket *, int, bool); -int sock_no_getname(struct socket *, struct sockaddr *, int *, int); +int sock_no_getname(struct socket *, struct sockaddr *, int); __poll_t sock_no_poll(struct file *, struct socket *, struct poll_table_struct *); int sock_no_ioctl(struct socket *, unsigned int, unsigned long); diff --git a/net/appletalk/ddp.c b/net/appletalk/ddp.c index 03a9fc0771c0..9b6bc5abe946 100644 --- a/net/appletalk/ddp.c +++ b/net/appletalk/ddp.c @@ -1238,7 +1238,7 @@ out: * fields into the sockaddr. */ static int atalk_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sockaddr_at sat; struct sock *sk = sock->sk; @@ -1251,7 +1251,6 @@ static int atalk_getname(struct socket *sock, struct sockaddr *uaddr, if (atalk_autobind(sk) < 0) goto out; - *uaddr_len = sizeof(struct sockaddr_at); memset(&sat, 0, sizeof(sat)); if (peer) { @@ -1268,9 +1267,9 @@ static int atalk_getname(struct socket *sock, struct sockaddr *uaddr, sat.sat_port = at->src_port; } - err = 0; sat.sat_family = AF_APPLETALK; memcpy(uaddr, &sat, sizeof(sat)); + err = sizeof(struct sockaddr_at); out: release_sock(sk); diff --git a/net/atm/pvc.c b/net/atm/pvc.c index e1140b3bdcaa..2cb10af16afc 100644 --- a/net/atm/pvc.c +++ b/net/atm/pvc.c @@ -87,21 +87,20 @@ static int pvc_getsockopt(struct socket *sock, int level, int optname, } static int pvc_getname(struct socket *sock, struct sockaddr *sockaddr, - int *sockaddr_len, int peer) + int peer) { struct sockaddr_atmpvc *addr; struct atm_vcc *vcc = ATM_SD(sock); if (!vcc->dev || !test_bit(ATM_VF_ADDR, &vcc->flags)) return -ENOTCONN; - *sockaddr_len = sizeof(struct sockaddr_atmpvc); addr = (struct sockaddr_atmpvc *)sockaddr; memset(addr, 0, sizeof(*addr)); addr->sap_family = AF_ATMPVC; addr->sap_addr.itf = vcc->dev->number; addr->sap_addr.vpi = vcc->vpi; addr->sap_addr.vci = vcc->vci; - return 0; + return sizeof(struct sockaddr_atmpvc); } static const struct proto_ops pvc_proto_ops = { diff --git a/net/atm/svc.c b/net/atm/svc.c index c458adcbc177..2f91b766ac42 100644 --- a/net/atm/svc.c +++ b/net/atm/svc.c @@ -419,15 +419,14 @@ out: } static int svc_getname(struct socket *sock, struct sockaddr *sockaddr, - int *sockaddr_len, int peer) + int peer) { struct sockaddr_atmsvc *addr; - *sockaddr_len = sizeof(struct sockaddr_atmsvc); addr = (struct sockaddr_atmsvc *) sockaddr; memcpy(addr, peer ? &ATM_SD(sock)->remote : &ATM_SD(sock)->local, sizeof(struct sockaddr_atmsvc)); - return 0; + return sizeof(struct sockaddr_atmsvc); } int svc_change_qos(struct atm_vcc *vcc, struct atm_qos *qos) diff --git a/net/ax25/af_ax25.c b/net/ax25/af_ax25.c index 47fdd399626b..c8319ed48485 100644 --- a/net/ax25/af_ax25.c +++ b/net/ax25/af_ax25.c @@ -1388,7 +1388,7 @@ out: } static int ax25_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct full_sockaddr_ax25 *fsa = (struct full_sockaddr_ax25 *)uaddr; struct sock *sk = sock->sk; @@ -1427,7 +1427,7 @@ static int ax25_getname(struct socket *sock, struct sockaddr *uaddr, fsa->fsa_digipeater[0] = null_ax25_address; } } - *uaddr_len = sizeof (struct full_sockaddr_ax25); + err = sizeof (struct full_sockaddr_ax25); out: release_sock(sk); diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c index 923e9a271872..1506e1632394 100644 --- a/net/bluetooth/hci_sock.c +++ b/net/bluetooth/hci_sock.c @@ -1340,7 +1340,7 @@ done: } static int hci_sock_getname(struct socket *sock, struct sockaddr *addr, - int *addr_len, int peer) + int peer) { struct sockaddr_hci *haddr = (struct sockaddr_hci *)addr; struct sock *sk = sock->sk; @@ -1360,10 +1360,10 @@ static int hci_sock_getname(struct socket *sock, struct sockaddr *addr, goto done; } - *addr_len = sizeof(*haddr); haddr->hci_family = AF_BLUETOOTH; haddr->hci_dev = hdev->id; haddr->hci_channel= hci_pi(sk)->channel; + err = sizeof(*haddr); done: release_sock(sk); diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c index 67a8642f57ea..686bdc6b35b0 100644 --- a/net/bluetooth/l2cap_sock.c +++ b/net/bluetooth/l2cap_sock.c @@ -358,7 +358,7 @@ done: } static int l2cap_sock_getname(struct socket *sock, struct sockaddr *addr, - int *len, int peer) + int peer) { struct sockaddr_l2 *la = (struct sockaddr_l2 *) addr; struct sock *sk = sock->sk; @@ -373,7 +373,6 @@ static int l2cap_sock_getname(struct socket *sock, struct sockaddr *addr, memset(la, 0, sizeof(struct sockaddr_l2)); addr->sa_family = AF_BLUETOOTH; - *len = sizeof(struct sockaddr_l2); la->l2_psm = chan->psm; @@ -387,7 +386,7 @@ static int l2cap_sock_getname(struct socket *sock, struct sockaddr *addr, la->l2_bdaddr_type = chan->src_type; } - return 0; + return sizeof(struct sockaddr_l2); } static int l2cap_sock_getsockopt_old(struct socket *sock, int optname, diff --git a/net/bluetooth/rfcomm/sock.c b/net/bluetooth/rfcomm/sock.c index 1aaccf637479..93a3b219db09 100644 --- a/net/bluetooth/rfcomm/sock.c +++ b/net/bluetooth/rfcomm/sock.c @@ -533,7 +533,7 @@ done: return err; } -static int rfcomm_sock_getname(struct socket *sock, struct sockaddr *addr, int *len, int peer) +static int rfcomm_sock_getname(struct socket *sock, struct sockaddr *addr, int peer) { struct sockaddr_rc *sa = (struct sockaddr_rc *) addr; struct sock *sk = sock->sk; @@ -552,8 +552,7 @@ static int rfcomm_sock_getname(struct socket *sock, struct sockaddr *addr, int * else bacpy(&sa->rc_bdaddr, &rfcomm_pi(sk)->src); - *len = sizeof(struct sockaddr_rc); - return 0; + return sizeof(struct sockaddr_rc); } static int rfcomm_sock_sendmsg(struct socket *sock, struct msghdr *msg, diff --git a/net/bluetooth/sco.c b/net/bluetooth/sco.c index 08df57665e1f..413b8ee49fec 100644 --- a/net/bluetooth/sco.c +++ b/net/bluetooth/sco.c @@ -680,7 +680,7 @@ done: } static int sco_sock_getname(struct socket *sock, struct sockaddr *addr, - int *len, int peer) + int peer) { struct sockaddr_sco *sa = (struct sockaddr_sco *) addr; struct sock *sk = sock->sk; @@ -688,14 +688,13 @@ static int sco_sock_getname(struct socket *sock, struct sockaddr *addr, BT_DBG("sock %p, sk %p", sock, sk); addr->sa_family = AF_BLUETOOTH; - *len = sizeof(struct sockaddr_sco); if (peer) bacpy(&sa->sco_bdaddr, &sco_pi(sk)->dst); else bacpy(&sa->sco_bdaddr, &sco_pi(sk)->src); - return 0; + return sizeof(struct sockaddr_sco); } static int sco_sock_sendmsg(struct socket *sock, struct msghdr *msg, diff --git a/net/can/raw.c b/net/can/raw.c index f2ecc43376a1..1051eee82581 100644 --- a/net/can/raw.c +++ b/net/can/raw.c @@ -470,7 +470,7 @@ static int raw_bind(struct socket *sock, struct sockaddr *uaddr, int len) } static int raw_getname(struct socket *sock, struct sockaddr *uaddr, - int *len, int peer) + int peer) { struct sockaddr_can *addr = (struct sockaddr_can *)uaddr; struct sock *sk = sock->sk; @@ -483,9 +483,7 @@ static int raw_getname(struct socket *sock, struct sockaddr *uaddr, addr->can_family = AF_CAN; addr->can_ifindex = ro->ifindex; - *len = sizeof(*addr); - - return 0; + return sizeof(*addr); } static int raw_setsockopt(struct socket *sock, int level, int optname, diff --git a/net/core/sock.c b/net/core/sock.c index c501499a04fe..04e5e27c9b81 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -1274,7 +1274,8 @@ int sock_getsockopt(struct socket *sock, int level, int optname, { char address[128]; - if (sock->ops->getname(sock, (struct sockaddr *)address, &lv, 2)) + lv = sock->ops->getname(sock, (struct sockaddr *)address, 2); + if (lv < 0) return -ENOTCONN; if (lv < len) return -EINVAL; @@ -2497,7 +2498,7 @@ int sock_no_accept(struct socket *sock, struct socket *newsock, int flags, EXPORT_SYMBOL(sock_no_accept); int sock_no_getname(struct socket *sock, struct sockaddr *saddr, - int *len, int peer) + int peer) { return -EOPNOTSUPP; } diff --git a/net/decnet/af_decnet.c b/net/decnet/af_decnet.c index 91dd09f79808..45cb5bea884b 100644 --- a/net/decnet/af_decnet.c +++ b/net/decnet/af_decnet.c @@ -1180,14 +1180,12 @@ static int dn_accept(struct socket *sock, struct socket *newsock, int flags, } -static int dn_getname(struct socket *sock, struct sockaddr *uaddr,int *uaddr_len,int peer) +static int dn_getname(struct socket *sock, struct sockaddr *uaddr,int peer) { struct sockaddr_dn *sa = (struct sockaddr_dn *)uaddr; struct sock *sk = sock->sk; struct dn_scp *scp = DN_SK(sk); - *uaddr_len = sizeof(struct sockaddr_dn); - lock_sock(sk); if (peer) { @@ -1205,7 +1203,7 @@ static int dn_getname(struct socket *sock, struct sockaddr *uaddr,int *uaddr_len release_sock(sk); - return 0; + return sizeof(struct sockaddr_dn); } diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index e4329e161943..f98e2f0db841 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -723,7 +723,7 @@ EXPORT_SYMBOL(inet_accept); * This does both peername and sockname. */ int inet_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sock *sk = sock->sk; struct inet_sock *inet = inet_sk(sk); @@ -745,8 +745,7 @@ int inet_getname(struct socket *sock, struct sockaddr *uaddr, sin->sin_addr.s_addr = addr; } memset(sin->sin_zero, 0, sizeof(sin->sin_zero)); - *uaddr_len = sizeof(*sin); - return 0; + return sizeof(*sin); } EXPORT_SYMBOL(inet_getname); diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index 416917719a6f..c1e292db04db 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -470,7 +470,7 @@ EXPORT_SYMBOL_GPL(inet6_destroy_sock); */ int inet6_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sockaddr_in6 *sin = (struct sockaddr_in6 *)uaddr; struct sock *sk = sock->sk; @@ -500,8 +500,7 @@ int inet6_getname(struct socket *sock, struct sockaddr *uaddr, } sin->sin6_scope_id = ipv6_iface_scope_id(&sin->sin6_addr, sk->sk_bound_dev_if); - *uaddr_len = sizeof(*sin); - return 0; + return sizeof(*sin); } EXPORT_SYMBOL(inet6_getname); diff --git a/net/iucv/af_iucv.c b/net/iucv/af_iucv.c index 1e8cc7bcbca3..81ce15ffb878 100644 --- a/net/iucv/af_iucv.c +++ b/net/iucv/af_iucv.c @@ -989,14 +989,13 @@ done: } static int iucv_sock_getname(struct socket *sock, struct sockaddr *addr, - int *len, int peer) + int peer) { struct sockaddr_iucv *siucv = (struct sockaddr_iucv *) addr; struct sock *sk = sock->sk; struct iucv_sock *iucv = iucv_sk(sk); addr->sa_family = AF_IUCV; - *len = sizeof(struct sockaddr_iucv); if (peer) { memcpy(siucv->siucv_user_id, iucv->dst_user_id, 8); @@ -1009,7 +1008,7 @@ static int iucv_sock_getname(struct socket *sock, struct sockaddr *addr, memset(&siucv->siucv_addr, 0, sizeof(siucv->siucv_addr)); memset(&siucv->siucv_nodeid, 0, sizeof(siucv->siucv_nodeid)); - return 0; + return sizeof(struct sockaddr_iucv); } /** diff --git a/net/l2tp/l2tp_ip.c b/net/l2tp/l2tp_ip.c index ff61124fdf59..4614585e1720 100644 --- a/net/l2tp/l2tp_ip.c +++ b/net/l2tp/l2tp_ip.c @@ -349,7 +349,7 @@ static int l2tp_ip_disconnect(struct sock *sk, int flags) } static int l2tp_ip_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sock *sk = sock->sk; struct inet_sock *inet = inet_sk(sk); @@ -370,8 +370,7 @@ static int l2tp_ip_getname(struct socket *sock, struct sockaddr *uaddr, lsa->l2tp_conn_id = lsk->conn_id; lsa->l2tp_addr.s_addr = addr; } - *uaddr_len = sizeof(*lsa); - return 0; + return sizeof(*lsa); } static int l2tp_ip_backlog_recv(struct sock *sk, struct sk_buff *skb) diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c index 192344688c06..efea58b66295 100644 --- a/net/l2tp/l2tp_ip6.c +++ b/net/l2tp/l2tp_ip6.c @@ -421,7 +421,7 @@ static int l2tp_ip6_disconnect(struct sock *sk, int flags) } static int l2tp_ip6_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sockaddr_l2tpip6 *lsa = (struct sockaddr_l2tpip6 *)uaddr; struct sock *sk = sock->sk; @@ -449,8 +449,7 @@ static int l2tp_ip6_getname(struct socket *sock, struct sockaddr *uaddr, } if (ipv6_addr_type(&lsa->l2tp_addr) & IPV6_ADDR_LINKLOCAL) lsa->l2tp_scope_id = sk->sk_bound_dev_if; - *uaddr_len = sizeof(*lsa); - return 0; + return sizeof(*lsa); } static int l2tp_ip6_backlog_recv(struct sock *sk, struct sk_buff *skb) diff --git a/net/l2tp/l2tp_ppp.c b/net/l2tp/l2tp_ppp.c index 59f246d7b290..99a03c72db4f 100644 --- a/net/l2tp/l2tp_ppp.c +++ b/net/l2tp/l2tp_ppp.c @@ -870,7 +870,7 @@ err: /* getname() support. */ static int pppol2tp_getname(struct socket *sock, struct sockaddr *uaddr, - int *usockaddr_len, int peer) + int peer) { int len = 0; int error = 0; @@ -969,8 +969,7 @@ static int pppol2tp_getname(struct socket *sock, struct sockaddr *uaddr, memcpy(uaddr, &sp, len); } - *usockaddr_len = len; - error = 0; + error = len; sock_put(sk); end: diff --git a/net/llc/af_llc.c b/net/llc/af_llc.c index c38d16f22d2a..01dcc0823d1f 100644 --- a/net/llc/af_llc.c +++ b/net/llc/af_llc.c @@ -971,7 +971,7 @@ release: * Return the address information of a socket. */ static int llc_ui_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddrlen, int peer) + int peer) { struct sockaddr_llc sllc; struct sock *sk = sock->sk; @@ -982,7 +982,6 @@ static int llc_ui_getname(struct socket *sock, struct sockaddr *uaddr, lock_sock(sk); if (sock_flag(sk, SOCK_ZAPPED)) goto out; - *uaddrlen = sizeof(sllc); if (peer) { rc = -ENOTCONN; if (sk->sk_state != TCP_ESTABLISHED) @@ -1003,9 +1002,9 @@ static int llc_ui_getname(struct socket *sock, struct sockaddr *uaddr, IFHWADDRLEN); } } - rc = 0; sllc.sllc_family = AF_LLC; memcpy(uaddr, &sllc, sizeof(sllc)); + rc = sizeof(sllc); out: release_sock(sk); return rc; diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 2ad445c1d27c..3c8af14330b5 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -1105,7 +1105,7 @@ static int netlink_connect(struct socket *sock, struct sockaddr *addr, } static int netlink_getname(struct socket *sock, struct sockaddr *addr, - int *addr_len, int peer) + int peer) { struct sock *sk = sock->sk; struct netlink_sock *nlk = nlk_sk(sk); @@ -1113,7 +1113,6 @@ static int netlink_getname(struct socket *sock, struct sockaddr *addr, nladdr->nl_family = AF_NETLINK; nladdr->nl_pad = 0; - *addr_len = sizeof(*nladdr); if (peer) { nladdr->nl_pid = nlk->dst_portid; @@ -1124,7 +1123,7 @@ static int netlink_getname(struct socket *sock, struct sockaddr *addr, nladdr->nl_groups = nlk->groups ? nlk->groups[0] : 0; netlink_unlock_table(); } - return 0; + return sizeof(*nladdr); } static int netlink_ioctl(struct socket *sock, unsigned int cmd, diff --git a/net/netrom/af_netrom.c b/net/netrom/af_netrom.c index 9ba30c63be3d..35bb6807927f 100644 --- a/net/netrom/af_netrom.c +++ b/net/netrom/af_netrom.c @@ -829,11 +829,12 @@ out_release: } static int nr_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct full_sockaddr_ax25 *sax = (struct full_sockaddr_ax25 *)uaddr; struct sock *sk = sock->sk; struct nr_sock *nr = nr_sk(sk); + int uaddr_len; memset(&sax->fsa_ax25, 0, sizeof(struct sockaddr_ax25)); @@ -848,16 +849,16 @@ static int nr_getname(struct socket *sock, struct sockaddr *uaddr, sax->fsa_ax25.sax25_call = nr->user_addr; memset(sax->fsa_digipeater, 0, sizeof(sax->fsa_digipeater)); sax->fsa_digipeater[0] = nr->dest_addr; - *uaddr_len = sizeof(struct full_sockaddr_ax25); + uaddr_len = sizeof(struct full_sockaddr_ax25); } else { sax->fsa_ax25.sax25_family = AF_NETROM; sax->fsa_ax25.sax25_ndigis = 0; sax->fsa_ax25.sax25_call = nr->source_addr; - *uaddr_len = sizeof(struct sockaddr_ax25); + uaddr_len = sizeof(struct sockaddr_ax25); } release_sock(sk); - return 0; + return uaddr_len; } int nr_rx_frame(struct sk_buff *skb, struct net_device *dev) diff --git a/net/nfc/llcp_sock.c b/net/nfc/llcp_sock.c index 376040092142..ea0c0c6f1874 100644 --- a/net/nfc/llcp_sock.c +++ b/net/nfc/llcp_sock.c @@ -497,7 +497,7 @@ error: } static int llcp_sock_getname(struct socket *sock, struct sockaddr *uaddr, - int *len, int peer) + int peer) { struct sock *sk = sock->sk; struct nfc_llcp_sock *llcp_sock = nfc_llcp_sock(sk); @@ -510,7 +510,6 @@ static int llcp_sock_getname(struct socket *sock, struct sockaddr *uaddr, llcp_sock->dsap, llcp_sock->ssap); memset(llcp_addr, 0, sizeof(*llcp_addr)); - *len = sizeof(struct sockaddr_nfc_llcp); lock_sock(sk); if (!llcp_sock->dev) { @@ -528,7 +527,7 @@ static int llcp_sock_getname(struct socket *sock, struct sockaddr *uaddr, llcp_addr->service_name_len); release_sock(sk); - return 0; + return sizeof(struct sockaddr_nfc_llcp); } static inline __poll_t llcp_accept_poll(struct sock *parent) diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index e0f3f4aeeb4f..616cb9c18f88 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -3409,7 +3409,7 @@ out: } static int packet_getname_spkt(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct net_device *dev; struct sock *sk = sock->sk; @@ -3424,13 +3424,12 @@ static int packet_getname_spkt(struct socket *sock, struct sockaddr *uaddr, if (dev) strlcpy(uaddr->sa_data, dev->name, sizeof(uaddr->sa_data)); rcu_read_unlock(); - *uaddr_len = sizeof(*uaddr); - return 0; + return sizeof(*uaddr); } static int packet_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct net_device *dev; struct sock *sk = sock->sk; @@ -3455,9 +3454,8 @@ static int packet_getname(struct socket *sock, struct sockaddr *uaddr, sll->sll_halen = 0; } rcu_read_unlock(); - *uaddr_len = offsetof(struct sockaddr_ll, sll_addr) + sll->sll_halen; - return 0; + return offsetof(struct sockaddr_ll, sll_addr) + sll->sll_halen; } static int packet_dev_mc(struct net_device *dev, struct packet_mclist *i, diff --git a/net/phonet/socket.c b/net/phonet/socket.c index fffcd69f63ff..f9b40e6a18a5 100644 --- a/net/phonet/socket.c +++ b/net/phonet/socket.c @@ -326,7 +326,7 @@ static int pn_socket_accept(struct socket *sock, struct socket *newsock, } static int pn_socket_getname(struct socket *sock, struct sockaddr *addr, - int *sockaddr_len, int peer) + int peer) { struct sock *sk = sock->sk; struct pn_sock *pn = pn_sk(sk); @@ -337,8 +337,7 @@ static int pn_socket_getname(struct socket *sock, struct sockaddr *addr, pn_sockaddr_set_object((struct sockaddr_pn *)addr, pn->sobject); - *sockaddr_len = sizeof(struct sockaddr_pn); - return 0; + return sizeof(struct sockaddr_pn); } static __poll_t pn_socket_poll(struct file *file, struct socket *sock, diff --git a/net/qrtr/qrtr.c b/net/qrtr/qrtr.c index 5fb3929e3d7d..b33e5aeb4c06 100644 --- a/net/qrtr/qrtr.c +++ b/net/qrtr/qrtr.c @@ -893,7 +893,7 @@ static int qrtr_connect(struct socket *sock, struct sockaddr *saddr, } static int qrtr_getname(struct socket *sock, struct sockaddr *saddr, - int *len, int peer) + int peer) { struct qrtr_sock *ipc = qrtr_sk(sock->sk); struct sockaddr_qrtr qaddr; @@ -912,12 +912,11 @@ static int qrtr_getname(struct socket *sock, struct sockaddr *saddr, } release_sock(sk); - *len = sizeof(qaddr); qaddr.sq_family = AF_QIPCRTR; memcpy(saddr, &qaddr, sizeof(qaddr)); - return 0; + return sizeof(qaddr); } static int qrtr_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) diff --git a/net/rds/af_rds.c b/net/rds/af_rds.c index 744c637c86b0..0a8eefd256b3 100644 --- a/net/rds/af_rds.c +++ b/net/rds/af_rds.c @@ -110,7 +110,7 @@ void rds_wake_sk_sleep(struct rds_sock *rs) } static int rds_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sockaddr_in *sin = (struct sockaddr_in *)uaddr; struct rds_sock *rs = rds_sk_to_rs(sock->sk); @@ -131,8 +131,7 @@ static int rds_getname(struct socket *sock, struct sockaddr *uaddr, sin->sin_family = AF_INET; - *uaddr_len = sizeof(*sin); - return 0; + return sizeof(*sin); } /* diff --git a/net/rds/tcp.c b/net/rds/tcp.c index 44c4652721af..08230a145042 100644 --- a/net/rds/tcp.c +++ b/net/rds/tcp.c @@ -227,7 +227,6 @@ static void rds_tcp_tc_info(struct socket *rds_sock, unsigned int len, struct rds_tcp_connection *tc; unsigned long flags; struct sockaddr_in sin; - int sinlen; struct socket *sock; spin_lock_irqsave(&rds_tcp_tc_list_lock, flags); @@ -239,12 +238,10 @@ static void rds_tcp_tc_info(struct socket *rds_sock, unsigned int len, sock = tc->t_sock; if (sock) { - sock->ops->getname(sock, (struct sockaddr *)&sin, - &sinlen, 0); + sock->ops->getname(sock, (struct sockaddr *)&sin, 0); tsinfo.local_addr = sin.sin_addr.s_addr; tsinfo.local_port = sin.sin_port; - sock->ops->getname(sock, (struct sockaddr *)&sin, - &sinlen, 1); + sock->ops->getname(sock, (struct sockaddr *)&sin, 1); tsinfo.peer_addr = sin.sin_addr.s_addr; tsinfo.peer_port = sin.sin_port; } diff --git a/net/rose/af_rose.c b/net/rose/af_rose.c index 083bd251406f..5170373b797c 100644 --- a/net/rose/af_rose.c +++ b/net/rose/af_rose.c @@ -938,7 +938,7 @@ out_release: } static int rose_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct full_sockaddr_rose *srose = (struct full_sockaddr_rose *)uaddr; struct sock *sk = sock->sk; @@ -964,8 +964,7 @@ static int rose_getname(struct socket *sock, struct sockaddr *uaddr, srose->srose_digis[n] = rose->source_digis[n]; } - *uaddr_len = sizeof(struct full_sockaddr_rose); - return 0; + return sizeof(struct full_sockaddr_rose); } int rose_rx_call_request(struct sk_buff *skb, struct net_device *dev, struct rose_neigh *neigh, unsigned int lci) diff --git a/net/sctp/ipv6.c b/net/sctp/ipv6.c index e35d4f73d2df..0d873c58e516 100644 --- a/net/sctp/ipv6.c +++ b/net/sctp/ipv6.c @@ -952,16 +952,16 @@ static int sctp_inet6_supported_addrs(const struct sctp_sock *opt, /* Handle SCTP_I_WANT_MAPPED_V4_ADDR for getpeername() and getsockname() */ static int sctp_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { int rc; - rc = inet6_getname(sock, uaddr, uaddr_len, peer); + rc = inet6_getname(sock, uaddr, peer); - if (rc != 0) + if (rc < 0) return rc; - *uaddr_len = sctp_v6_addr_to_user(sctp_sk(sock->sk), + rc = sctp_v6_addr_to_user(sctp_sk(sock->sk), (union sctp_addr *)uaddr); return rc; diff --git a/net/smc/af_smc.c b/net/smc/af_smc.c index da1a5cdefd13..38ae22b65e77 100644 --- a/net/smc/af_smc.c +++ b/net/smc/af_smc.c @@ -281,7 +281,6 @@ int smc_netinfo_by_tcpsk(struct socket *clcsock, struct in_device *in_dev; struct sockaddr_in addr; int rc = -ENOENT; - int len; if (!dst) { rc = -ENOTCONN; @@ -293,7 +292,7 @@ int smc_netinfo_by_tcpsk(struct socket *clcsock, } /* get address to which the internal TCP socket is bound */ - kernel_getsockname(clcsock, (struct sockaddr *)&addr, &len); + kernel_getsockname(clcsock, (struct sockaddr *)&addr); /* analyze IPv4 specific data of net_device belonging to TCP socket */ rcu_read_lock(); in_dev = __in_dev_get_rcu(dst->dev); @@ -771,7 +770,7 @@ static void smc_listen_work(struct work_struct *work) u8 buf[SMC_CLC_MAX_LEN]; struct smc_link *link; int reason_code = 0; - int rc = 0, len; + int rc = 0; __be32 subnet; u8 prefix_len; u8 ibport; @@ -824,7 +823,7 @@ static void smc_listen_work(struct work_struct *work) } /* get address of the peer connected to the internal TCP socket */ - kernel_getpeername(newclcsock, (struct sockaddr *)&peeraddr, &len); + kernel_getpeername(newclcsock, (struct sockaddr *)&peeraddr); /* allocate connection / link group */ mutex_lock(&smc_create_lgr_pending); @@ -1075,7 +1074,7 @@ out: } static int smc_getname(struct socket *sock, struct sockaddr *addr, - int *len, int peer) + int peer) { struct smc_sock *smc; @@ -1085,7 +1084,7 @@ static int smc_getname(struct socket *sock, struct sockaddr *addr, smc = smc_sk(sock->sk); - return smc->clcsock->ops->getname(smc->clcsock, addr, len, peer); + return smc->clcsock->ops->getname(smc->clcsock, addr, peer); } static int smc_sendmsg(struct socket *sock, struct msghdr *msg, size_t len) diff --git a/net/socket.c b/net/socket.c index a93c99b518ca..fac8246a8ae8 100644 --- a/net/socket.c +++ b/net/socket.c @@ -1573,8 +1573,9 @@ SYSCALL_DEFINE4(accept4, int, fd, struct sockaddr __user *, upeer_sockaddr, goto out_fd; if (upeer_sockaddr) { - if (newsock->ops->getname(newsock, (struct sockaddr *)&address, - &len, 2) < 0) { + len = newsock->ops->getname(newsock, + (struct sockaddr *)&address, 2); + if (len < 0) { err = -ECONNABORTED; goto out_fd; } @@ -1654,7 +1655,7 @@ SYSCALL_DEFINE3(getsockname, int, fd, struct sockaddr __user *, usockaddr, { struct socket *sock; struct sockaddr_storage address; - int len, err, fput_needed; + int err, fput_needed; sock = sockfd_lookup_light(fd, &err, &fput_needed); if (!sock) @@ -1664,10 +1665,11 @@ SYSCALL_DEFINE3(getsockname, int, fd, struct sockaddr __user *, usockaddr, if (err) goto out_put; - err = sock->ops->getname(sock, (struct sockaddr *)&address, &len, 0); - if (err) + err = sock->ops->getname(sock, (struct sockaddr *)&address, 0); + if (err < 0) goto out_put; - err = move_addr_to_user(&address, len, usockaddr, usockaddr_len); + /* "err" is actually length in this case */ + err = move_addr_to_user(&address, err, usockaddr, usockaddr_len); out_put: fput_light(sock->file, fput_needed); @@ -1685,7 +1687,7 @@ SYSCALL_DEFINE3(getpeername, int, fd, struct sockaddr __user *, usockaddr, { struct socket *sock; struct sockaddr_storage address; - int len, err, fput_needed; + int err, fput_needed; sock = sockfd_lookup_light(fd, &err, &fput_needed); if (sock != NULL) { @@ -1695,11 +1697,10 @@ SYSCALL_DEFINE3(getpeername, int, fd, struct sockaddr __user *, usockaddr, return err; } - err = - sock->ops->getname(sock, (struct sockaddr *)&address, &len, - 1); - if (!err) - err = move_addr_to_user(&address, len, usockaddr, + err = sock->ops->getname(sock, (struct sockaddr *)&address, 1); + if (err >= 0) + /* "err" is actually length in this case */ + err = move_addr_to_user(&address, err, usockaddr, usockaddr_len); fput_light(sock->file, fput_needed); } @@ -3166,17 +3167,15 @@ int kernel_connect(struct socket *sock, struct sockaddr *addr, int addrlen, } EXPORT_SYMBOL(kernel_connect); -int kernel_getsockname(struct socket *sock, struct sockaddr *addr, - int *addrlen) +int kernel_getsockname(struct socket *sock, struct sockaddr *addr) { - return sock->ops->getname(sock, addr, addrlen, 0); + return sock->ops->getname(sock, addr, 0); } EXPORT_SYMBOL(kernel_getsockname); -int kernel_getpeername(struct socket *sock, struct sockaddr *addr, - int *addrlen) +int kernel_getpeername(struct socket *sock, struct sockaddr *addr) { - return sock->ops->getname(sock, addr, addrlen, 1); + return sock->ops->getname(sock, addr, 1); } EXPORT_SYMBOL(kernel_getpeername); diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c index 6e432ecd7f99..806395687bb6 100644 --- a/net/sunrpc/clnt.c +++ b/net/sunrpc/clnt.c @@ -1231,7 +1231,7 @@ static const struct sockaddr_in6 rpc_in6addr_loopback = { * negative errno is returned. */ static int rpc_sockname(struct net *net, struct sockaddr *sap, size_t salen, - struct sockaddr *buf, int buflen) + struct sockaddr *buf) { struct socket *sock; int err; @@ -1269,7 +1269,7 @@ static int rpc_sockname(struct net *net, struct sockaddr *sap, size_t salen, goto out_release; } - err = kernel_getsockname(sock, buf, &buflen); + err = kernel_getsockname(sock, buf); if (err < 0) { dprintk("RPC: getsockname failed (%d)\n", err); goto out_release; @@ -1353,7 +1353,7 @@ int rpc_localaddr(struct rpc_clnt *clnt, struct sockaddr *buf, size_t buflen) rcu_read_unlock(); rpc_set_port(sap, 0); - err = rpc_sockname(net, sap, salen, buf, buflen); + err = rpc_sockname(net, sap, salen, buf); put_net(net); if (err != 0) /* Couldn't discover local address, return ANYADDR */ diff --git a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c index 943f2a745cd5..08cd951aaeea 100644 --- a/net/sunrpc/svcsock.c +++ b/net/sunrpc/svcsock.c @@ -832,12 +832,13 @@ static struct svc_xprt *svc_tcp_accept(struct svc_xprt *xprt) } set_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags); - err = kernel_getpeername(newsock, sin, &slen); + err = kernel_getpeername(newsock, sin); if (err < 0) { net_warn_ratelimited("%s: peername failed (err %d)!\n", serv->sv_name, -err); goto failed; /* aborted connection or whatever */ } + slen = err; /* Ideally, we would want to reject connections from unauthorized * hosts here, but when we get encryption, the IP of the host won't @@ -866,7 +867,8 @@ static struct svc_xprt *svc_tcp_accept(struct svc_xprt *xprt) if (IS_ERR(newsvsk)) goto failed; svc_xprt_set_remote(&newsvsk->sk_xprt, sin, slen); - err = kernel_getsockname(newsock, sin, &slen); + err = kernel_getsockname(newsock, sin); + slen = err; if (unlikely(err < 0)) { dprintk("svc_tcp_accept: kernel_getsockname error %d\n", -err); slen = offsetof(struct sockaddr, sa_data); @@ -1465,7 +1467,8 @@ int svc_addsock(struct svc_serv *serv, const int fd, char *name_return, err = PTR_ERR(svsk); goto out; } - if (kernel_getsockname(svsk->sk_sock, sin, &salen) == 0) + salen = kernel_getsockname(svsk->sk_sock, sin); + if (salen >= 0) svc_xprt_set_local(&svsk->sk_xprt, sin, salen); svc_add_new_perm_xprt(serv, &svsk->sk_xprt); return svc_one_sock_name(svsk, name_return, len); @@ -1539,10 +1542,10 @@ static struct svc_xprt *svc_create_socket(struct svc_serv *serv, if (error < 0) goto bummer; - newlen = len; - error = kernel_getsockname(sock, newsin, &newlen); + error = kernel_getsockname(sock, newsin); if (error < 0) goto bummer; + newlen = error; if (protocol == IPPROTO_TCP) { if ((error = kernel_listen(sock, 64)) < 0) diff --git a/net/sunrpc/xprtsock.c b/net/sunrpc/xprtsock.c index a6b8c1f8f92a..956e29c1438d 100644 --- a/net/sunrpc/xprtsock.c +++ b/net/sunrpc/xprtsock.c @@ -1794,10 +1794,9 @@ static void xs_sock_set_reuseport(struct socket *sock) static unsigned short xs_sock_getport(struct socket *sock) { struct sockaddr_storage buf; - int buflen; unsigned short port = 0; - if (kernel_getsockname(sock, (struct sockaddr *)&buf, &buflen) < 0) + if (kernel_getsockname(sock, (struct sockaddr *)&buf) < 0) goto out; switch (buf.ss_family) { case AF_INET6: diff --git a/net/tipc/socket.c b/net/tipc/socket.c index b0323ec7971e..f93477187a90 100644 --- a/net/tipc/socket.c +++ b/net/tipc/socket.c @@ -665,7 +665,7 @@ exit: * a completely predictable manner). */ static int tipc_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sockaddr_tipc *addr = (struct sockaddr_tipc *)uaddr; struct sock *sk = sock->sk; @@ -684,13 +684,12 @@ static int tipc_getname(struct socket *sock, struct sockaddr *uaddr, addr->addr.id.node = tn->own_addr; } - *uaddr_len = sizeof(*addr); addr->addrtype = TIPC_ADDR_ID; addr->family = AF_TIPC; addr->scope = 0; addr->addr.name.domain = 0; - return 0; + return sizeof(*addr); } /** diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index d545e1d0dea2..723698416242 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -637,7 +637,7 @@ static int unix_stream_connect(struct socket *, struct sockaddr *, int addr_len, int flags); static int unix_socketpair(struct socket *, struct socket *); static int unix_accept(struct socket *, struct socket *, int, bool); -static int unix_getname(struct socket *, struct sockaddr *, int *, int); +static int unix_getname(struct socket *, struct sockaddr *, int); static __poll_t unix_poll(struct file *, struct socket *, poll_table *); static __poll_t unix_dgram_poll(struct file *, struct socket *, poll_table *); @@ -1453,7 +1453,7 @@ out: } -static int unix_getname(struct socket *sock, struct sockaddr *uaddr, int *uaddr_len, int peer) +static int unix_getname(struct socket *sock, struct sockaddr *uaddr, int peer) { struct sock *sk = sock->sk; struct unix_sock *u; @@ -1476,12 +1476,12 @@ static int unix_getname(struct socket *sock, struct sockaddr *uaddr, int *uaddr_ if (!u->addr) { sunaddr->sun_family = AF_UNIX; sunaddr->sun_path[0] = 0; - *uaddr_len = sizeof(short); + err = sizeof(short); } else { struct unix_address *addr = u->addr; - *uaddr_len = addr->len; - memcpy(sunaddr, addr->name, *uaddr_len); + err = addr->len; + memcpy(sunaddr, addr->name, addr->len); } unix_state_unlock(sk); sock_put(sk); diff --git a/net/vmw_vsock/af_vsock.c b/net/vmw_vsock/af_vsock.c index e0fc84daed94..aac9b8f6552e 100644 --- a/net/vmw_vsock/af_vsock.c +++ b/net/vmw_vsock/af_vsock.c @@ -759,7 +759,7 @@ vsock_bind(struct socket *sock, struct sockaddr *addr, int addr_len) } static int vsock_getname(struct socket *sock, - struct sockaddr *addr, int *addr_len, int peer) + struct sockaddr *addr, int peer) { int err; struct sock *sk; @@ -794,7 +794,7 @@ static int vsock_getname(struct socket *sock, */ BUILD_BUG_ON(sizeof(*vm_addr) > 128); memcpy(addr, vm_addr, sizeof(*vm_addr)); - *addr_len = sizeof(*vm_addr); + err = sizeof(*vm_addr); out: release_sock(sk); diff --git a/net/x25/af_x25.c b/net/x25/af_x25.c index 562cc11131f6..d49aa79b7997 100644 --- a/net/x25/af_x25.c +++ b/net/x25/af_x25.c @@ -896,7 +896,7 @@ out: } static int x25_getname(struct socket *sock, struct sockaddr *uaddr, - int *uaddr_len, int peer) + int peer) { struct sockaddr_x25 *sx25 = (struct sockaddr_x25 *)uaddr; struct sock *sk = sock->sk; @@ -913,7 +913,7 @@ static int x25_getname(struct socket *sock, struct sockaddr *uaddr, sx25->sx25_addr = x25->source_addr; sx25->sx25_family = AF_X25; - *uaddr_len = sizeof(*sx25); + rc = sizeof(*sx25); out: return rc; diff --git a/security/tomoyo/network.c b/security/tomoyo/network.c index cd6932e5225c..9094f4b3b367 100644 --- a/security/tomoyo/network.c +++ b/security/tomoyo/network.c @@ -655,10 +655,11 @@ int tomoyo_socket_listen_permission(struct socket *sock) return 0; { const int error = sock->ops->getname(sock, (struct sockaddr *) - &addr, &addr_len, 0); + &addr, 0); - if (error) + if (error < 0) return error; + addr_len = error; } address.protocol = type; address.operation = TOMOYO_NETWORK_LISTEN; -- cgit v1.2.3 From 880f5b388252fedb26c70bb80ad1d7c8abbc0607 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 30 Oct 2017 23:11:14 -0700 Subject: remoteproc: Pass type of shutdown to subdev remove remoteproc instances can be stopped either by invoking shutdown or by an attempt to recover from a crash. For some subdev types it's expected to clean up gracefully during a shutdown, but are unable to do so during a crash - so pass this information to the subdev remove functions. Acked-By: Chris Lew Signed-off-by: Bjorn Andersson --- drivers/remoteproc/qcom_common.c | 6 +++--- drivers/remoteproc/remoteproc_core.c | 18 +++++++++--------- include/linux/remoteproc.h | 7 ++++--- 3 files changed, 16 insertions(+), 15 deletions(-) (limited to 'include/linux') diff --git a/drivers/remoteproc/qcom_common.c b/drivers/remoteproc/qcom_common.c index b7d53a9cf21f..9e47a147c131 100644 --- a/drivers/remoteproc/qcom_common.c +++ b/drivers/remoteproc/qcom_common.c @@ -42,7 +42,7 @@ static int glink_subdev_probe(struct rproc_subdev *subdev) return PTR_ERR_OR_ZERO(glink->edge); } -static void glink_subdev_remove(struct rproc_subdev *subdev) +static void glink_subdev_remove(struct rproc_subdev *subdev, bool crashed) { struct qcom_rproc_glink *glink = to_glink_subdev(subdev); @@ -132,7 +132,7 @@ static int smd_subdev_probe(struct rproc_subdev *subdev) return PTR_ERR_OR_ZERO(smd->edge); } -static void smd_subdev_remove(struct rproc_subdev *subdev) +static void smd_subdev_remove(struct rproc_subdev *subdev, bool crashed) { struct qcom_rproc_subdev *smd = to_smd_subdev(subdev); @@ -201,7 +201,7 @@ static int ssr_notify_start(struct rproc_subdev *subdev) return 0; } -static void ssr_notify_stop(struct rproc_subdev *subdev) +static void ssr_notify_stop(struct rproc_subdev *subdev, bool crashed) { struct qcom_rproc_ssr *ssr = to_ssr_subdev(subdev); diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c index fd257607a578..6d9c5832ce47 100644 --- a/drivers/remoteproc/remoteproc_core.c +++ b/drivers/remoteproc/remoteproc_core.c @@ -308,7 +308,7 @@ static int rproc_vdev_do_probe(struct rproc_subdev *subdev) return rproc_add_virtio_dev(rvdev, rvdev->id); } -static void rproc_vdev_do_remove(struct rproc_subdev *subdev) +static void rproc_vdev_do_remove(struct rproc_subdev *subdev, bool crashed) { struct rproc_vdev *rvdev = container_of(subdev, struct rproc_vdev, subdev); @@ -789,17 +789,17 @@ static int rproc_probe_subdevices(struct rproc *rproc) unroll_registration: list_for_each_entry_continue_reverse(subdev, &rproc->subdevs, node) - subdev->remove(subdev); + subdev->remove(subdev, true); return ret; } -static void rproc_remove_subdevices(struct rproc *rproc) +static void rproc_remove_subdevices(struct rproc *rproc, bool crashed) { struct rproc_subdev *subdev; list_for_each_entry_reverse(subdev, &rproc->subdevs, node) - subdev->remove(subdev); + subdev->remove(subdev, crashed); } /** @@ -1009,13 +1009,13 @@ static int rproc_trigger_auto_boot(struct rproc *rproc) return ret; } -static int rproc_stop(struct rproc *rproc) +static int rproc_stop(struct rproc *rproc, bool crashed) { struct device *dev = &rproc->dev; int ret; /* remove any subdevices for the remote processor */ - rproc_remove_subdevices(rproc); + rproc_remove_subdevices(rproc, crashed); /* the installed resource table is no longer accessible */ rproc->table_ptr = rproc->cached_table; @@ -1163,7 +1163,7 @@ int rproc_trigger_recovery(struct rproc *rproc) if (ret) return ret; - ret = rproc_stop(rproc); + ret = rproc_stop(rproc, false); if (ret) goto unlock_mutex; @@ -1316,7 +1316,7 @@ void rproc_shutdown(struct rproc *rproc) if (!atomic_dec_and_test(&rproc->power)) goto out; - ret = rproc_stop(rproc); + ret = rproc_stop(rproc, true); if (ret) { atomic_inc(&rproc->power); goto out; @@ -1663,7 +1663,7 @@ EXPORT_SYMBOL(rproc_del); void rproc_add_subdev(struct rproc *rproc, struct rproc_subdev *subdev, int (*probe)(struct rproc_subdev *subdev), - void (*remove)(struct rproc_subdev *subdev)) + void (*remove)(struct rproc_subdev *subdev, bool crashed)) { subdev->probe = probe; subdev->remove = remove; diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index f16864acedad..d09a9c7af109 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -478,13 +478,14 @@ struct rproc { * struct rproc_subdev - subdevice tied to a remoteproc * @node: list node related to the rproc subdevs list * @probe: probe function, called as the rproc is started - * @remove: remove function, called as the rproc is stopped + * @remove: remove function, called as the rproc is being stopped, the @crashed + * parameter indicates if this originates from the a recovery */ struct rproc_subdev { struct list_head node; int (*probe)(struct rproc_subdev *subdev); - void (*remove)(struct rproc_subdev *subdev); + void (*remove)(struct rproc_subdev *subdev, bool crashed); }; /* we currently support only two vrings per rvdev */ @@ -568,7 +569,7 @@ static inline struct rproc *vdev_to_rproc(struct virtio_device *vdev) void rproc_add_subdev(struct rproc *rproc, struct rproc_subdev *subdev, int (*probe)(struct rproc_subdev *subdev), - void (*remove)(struct rproc_subdev *subdev)); + void (*remove)(struct rproc_subdev *subdev, bool graceful)); void rproc_remove_subdev(struct rproc *rproc, struct rproc_subdev *subdev); -- cgit v1.2.3 From 1a57feb847c56d6193f67d0e892c24e71f9e3ab1 Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Tue, 13 Feb 2018 12:26:23 +0300 Subject: net: Introduce net_sem for protection of pernet_list Currently, the mutex is mostly used to protect pernet operations list. It orders setup_net() and cleanup_net() with parallel {un,}register_pernet_operations() calls, so ->exit{,batch} methods of the same pernet operations are executed for a dying net, as were used to call ->init methods, even after the net namespace is unlinked from net_namespace_list in cleanup_net(). But there are several problems with scalability. The first one is that more than one net can't be created or destroyed at the same moment on the node. For big machines with many cpus running many containers it's very sensitive. The second one is that it's need to synchronize_rcu() after net is removed from net_namespace_list(): Destroy net_ns: cleanup_net() mutex_lock(&net_mutex) list_del_rcu(&net->list) synchronize_rcu() <--- Sleep there for ages list_for_each_entry_reverse(ops, &pernet_list, list) ops_exit_list(ops, &net_exit_list) list_for_each_entry_reverse(ops, &pernet_list, list) ops_free_list(ops, &net_exit_list) mutex_unlock(&net_mutex) This primitive is not fast, especially on the systems with many processors and/or when preemptible RCU is enabled in config. So, all the time, while cleanup_net() is waiting for RCU grace period, creation of new net namespaces is not possible, the tasks, who makes it, are sleeping on the same mutex: Create net_ns: copy_net_ns() mutex_lock_killable(&net_mutex) <--- Sleep there for ages I observed 20-30 seconds hangs of "unshare -n" on ordinary 8-cpu laptop with preemptible RCU enabled after CRIU tests round is finished. The solution is to convert net_mutex to the rw_semaphore and add fine grain locks to really small number of pernet_operations, what really need them. Then, pernet_operations::init/::exit methods, modifying the net-related data, will require down_read() locking only, while down_write() will be used for changing pernet_list (i.e., when modules are being loaded and unloaded). This gives signify performance increase, after all patch set is applied, like you may see here: %for i in {1..10000}; do unshare -n bash -c exit; done *before* real 1m40,377s user 0m9,672s sys 0m19,928s *after* real 0m17,007s user 0m5,311s sys 0m11,779 (5.8 times faster) This patch starts replacing net_mutex to net_sem. It adds rw_semaphore, describes the variables it protects, and makes to use, where appropriate. net_mutex is still present, and next patches will kick it out step-by-step. Signed-off-by: Kirill Tkhai Acked-by: Andrei Vagin Signed-off-by: David S. Miller --- include/linux/rtnetlink.h | 1 + net/core/net_namespace.c | 39 ++++++++++++++++++++++++++------------- net/core/rtnetlink.c | 4 ++-- 3 files changed, 29 insertions(+), 15 deletions(-) (limited to 'include/linux') diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 1fdcde96eb65..e9ee9ad0a681 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -36,6 +36,7 @@ extern int rtnl_is_locked(void); extern wait_queue_head_t netdev_unregistering_wq; extern struct mutex net_mutex; +extern struct rw_semaphore net_sem; #ifdef CONFIG_PROVE_LOCKING extern bool lockdep_rtnl_is_held(void); diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c index 81384386f91b..e89b2b7abd36 100644 --- a/net/core/net_namespace.c +++ b/net/core/net_namespace.c @@ -41,6 +41,11 @@ struct net init_net = { EXPORT_SYMBOL(init_net); static bool init_net_initialized; +/* + * net_sem: protects: pernet_list, net_generic_ids, + * init_net_initialized and first_device pointer. + */ +DECLARE_RWSEM(net_sem); #define MIN_PERNET_OPS_ID \ ((sizeof(struct net_generic) + sizeof(void *) - 1) / sizeof(void *)) @@ -286,7 +291,7 @@ struct net *get_net_ns_by_id(struct net *net, int id) */ static __net_init int setup_net(struct net *net, struct user_namespace *user_ns) { - /* Must be called with net_mutex held */ + /* Must be called with net_sem held */ const struct pernet_operations *ops, *saved_ops; int error = 0; LIST_HEAD(net_exit_list); @@ -418,12 +423,16 @@ struct net *copy_net_ns(unsigned long flags, net->ucounts = ucounts; get_user_ns(user_ns); - rv = mutex_lock_killable(&net_mutex); + rv = down_read_killable(&net_sem); if (rv < 0) goto put_userns; - + rv = mutex_lock_killable(&net_mutex); + if (rv < 0) + goto up_read; rv = setup_net(net, user_ns); mutex_unlock(&net_mutex); +up_read: + up_read(&net_sem); if (rv < 0) { put_userns: put_user_ns(user_ns); @@ -477,6 +486,7 @@ static void cleanup_net(struct work_struct *work) list_replace_init(&cleanup_list, &net_kill_list); spin_unlock_irq(&cleanup_list_lock); + down_read(&net_sem); mutex_lock(&net_mutex); /* Don't let anyone else find us. */ @@ -517,6 +527,7 @@ static void cleanup_net(struct work_struct *work) ops_free_list(ops, &net_exit_list); mutex_unlock(&net_mutex); + up_read(&net_sem); /* Ensure there are no outstanding rcu callbacks using this * network namespace. @@ -543,8 +554,10 @@ static void cleanup_net(struct work_struct *work) */ void net_ns_barrier(void) { + down_write(&net_sem); mutex_lock(&net_mutex); mutex_unlock(&net_mutex); + up_write(&net_sem); } EXPORT_SYMBOL(net_ns_barrier); @@ -871,12 +884,12 @@ static int __init net_ns_init(void) rcu_assign_pointer(init_net.gen, ng); - mutex_lock(&net_mutex); + down_write(&net_sem); if (setup_net(&init_net, &init_user_ns)) panic("Could not setup the initial network namespace"); init_net_initialized = true; - mutex_unlock(&net_mutex); + up_write(&net_sem); register_pernet_subsys(&net_ns_ops); @@ -1016,9 +1029,9 @@ static void unregister_pernet_operations(struct pernet_operations *ops) int register_pernet_subsys(struct pernet_operations *ops) { int error; - mutex_lock(&net_mutex); + down_write(&net_sem); error = register_pernet_operations(first_device, ops); - mutex_unlock(&net_mutex); + up_write(&net_sem); return error; } EXPORT_SYMBOL_GPL(register_pernet_subsys); @@ -1034,9 +1047,9 @@ EXPORT_SYMBOL_GPL(register_pernet_subsys); */ void unregister_pernet_subsys(struct pernet_operations *ops) { - mutex_lock(&net_mutex); + down_write(&net_sem); unregister_pernet_operations(ops); - mutex_unlock(&net_mutex); + up_write(&net_sem); } EXPORT_SYMBOL_GPL(unregister_pernet_subsys); @@ -1062,11 +1075,11 @@ EXPORT_SYMBOL_GPL(unregister_pernet_subsys); int register_pernet_device(struct pernet_operations *ops) { int error; - mutex_lock(&net_mutex); + down_write(&net_sem); error = register_pernet_operations(&pernet_list, ops); if (!error && (first_device == &pernet_list)) first_device = &ops->list; - mutex_unlock(&net_mutex); + up_write(&net_sem); return error; } EXPORT_SYMBOL_GPL(register_pernet_device); @@ -1082,11 +1095,11 @@ EXPORT_SYMBOL_GPL(register_pernet_device); */ void unregister_pernet_device(struct pernet_operations *ops) { - mutex_lock(&net_mutex); + down_write(&net_sem); if (&ops->list == first_device) first_device = first_device->next; unregister_pernet_operations(ops); - mutex_unlock(&net_mutex); + up_write(&net_sem); } EXPORT_SYMBOL_GPL(unregister_pernet_device); diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index bc290413a49d..257e7bbaffba 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -454,11 +454,11 @@ static void rtnl_lock_unregistering_all(void) void rtnl_link_unregister(struct rtnl_link_ops *ops) { /* Close the race with cleanup_net() */ - mutex_lock(&net_mutex); + down_write(&net_sem); rtnl_lock_unregistering_all(); __rtnl_link_unregister(ops); rtnl_unlock(); - mutex_unlock(&net_mutex); + up_write(&net_sem); } EXPORT_SYMBOL_GPL(rtnl_link_unregister); -- cgit v1.2.3 From b1d03c1d12abbfa7de127772f281b309cf1650c3 Mon Sep 17 00:00:00 2001 From: Dmitry Safonov Date: Mon, 12 Feb 2018 16:48:21 +0000 Subject: iommu/vt-d: Clean/document fault status flags So one could decode them without opening the specification. Signed-off-by: Dmitry Safonov Signed-off-by: Joerg Roedel --- include/linux/intel-iommu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 8dad3dd26eae..ef169d67df92 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -209,12 +209,12 @@ #define DMA_FECTL_IM (((u32)1) << 31) /* FSTS_REG */ -#define DMA_FSTS_PPF ((u32)2) -#define DMA_FSTS_PFO ((u32)1) -#define DMA_FSTS_IQE (1 << 4) -#define DMA_FSTS_ICE (1 << 5) -#define DMA_FSTS_ITE (1 << 6) -#define DMA_FSTS_PRO (1 << 7) +#define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */ +#define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */ +#define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */ +#define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */ +#define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */ +#define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */ #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) /* FRCD_REG, 32 bits access */ -- cgit v1.2.3 From c5611a8751e67595e4e7d3feaff3c900b92094b9 Mon Sep 17 00:00:00 2001 From: Suravee Suthikulpanit Date: Mon, 5 Feb 2018 05:45:53 -0500 Subject: iommu: Do not return error code for APIs with size_t return type Currently, iommu_unmap, iommu_unmap_fast and iommu_map_sg return size_t. However, some of the return values are error codes (< 0), which can be misinterpreted as large size. Therefore, returning size 0 instead to signify failure to map/unmap. Cc: Joerg Roedel Cc: Alex Williamson Signed-off-by: Suravee Suthikulpanit Signed-off-by: Joerg Roedel --- drivers/iommu/amd_iommu.c | 2 +- drivers/iommu/iommu.c | 6 +++--- include/linux/iommu.h | 14 +++++++------- 3 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include/linux') diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 74788fdeb773..ecdeb045deef 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -3050,7 +3050,7 @@ static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, size_t unmap_size; if (domain->mode == PAGE_MODE_NONE) - return -EINVAL; + return 0; mutex_lock(&domain->api_lock); unmap_size = iommu_unmap_page(domain, iova, page_size); diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 69fef991c651..d2aa23202bb9 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1573,10 +1573,10 @@ static size_t __iommu_unmap(struct iommu_domain *domain, if (unlikely(ops->unmap == NULL || domain->pgsize_bitmap == 0UL)) - return -ENODEV; + return 0; if (unlikely(!(domain->type & __IOMMU_DOMAIN_PAGING))) - return -EINVAL; + return 0; /* find out the minimum page size supported */ min_pagesz = 1 << __ffs(domain->pgsize_bitmap); @@ -1589,7 +1589,7 @@ static size_t __iommu_unmap(struct iommu_domain *domain, if (!IS_ALIGNED(iova | size, min_pagesz)) { pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n", iova, size, min_pagesz); - return -EINVAL; + return 0; } pr_debug("unmap this: iova 0x%lx size 0x%zx\n", iova, size); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 41b8c5757859..19938ee6eb31 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -465,23 +465,23 @@ static inline int iommu_map(struct iommu_domain *domain, unsigned long iova, return -ENODEV; } -static inline int iommu_unmap(struct iommu_domain *domain, unsigned long iova, - size_t size) +static inline size_t iommu_unmap(struct iommu_domain *domain, + unsigned long iova, size_t size) { - return -ENODEV; + return 0; } -static inline int iommu_unmap_fast(struct iommu_domain *domain, unsigned long iova, - int gfp_order) +static inline size_t iommu_unmap_fast(struct iommu_domain *domain, + unsigned long iova, int gfp_order) { - return -ENODEV; + return 0; } static inline size_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova, struct scatterlist *sg, unsigned int nents, int prot) { - return -ENODEV; + return 0; } static inline void iommu_flush_tlb_all(struct iommu_domain *domain) -- cgit v1.2.3 From 297dd12cb104151797fd649433a2157b585f1718 Mon Sep 17 00:00:00 2001 From: Jesper Dangaard Brouer Date: Tue, 13 Feb 2018 14:15:36 +0100 Subject: net: avoid including xdp.h in filter.h If is sufficient with a forward declaration of struct xdp_rxq_info in linux/filter.h, which avoids including net/xdp.h. This was originally suggested by John Fastabend during the review phase, but wasn't included in the final patchset revision. Thus, this followup. Suggested-by: John Fastabend Signed-off-by: Jesper Dangaard Brouer Signed-off-by: Alexei Starovoitov --- include/linux/filter.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/filter.h b/include/linux/filter.h index 276932d75975..fdb691b520c0 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -20,7 +20,6 @@ #include #include -#include #include #include @@ -30,6 +29,7 @@ struct sk_buff; struct sock; struct seccomp_data; struct bpf_prog_aux; +struct xdp_rxq_info; /* ArgX, context and stack frame pointer register positions. Note, * Arg1, Arg2, Arg3, etc are used as argument mappings of function -- cgit v1.2.3 From c65e774fb3f6af212641538694b9778ff9ab4300 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Wed, 14 Feb 2018 14:16:53 +0300 Subject: x86/mm: Make PGDIR_SHIFT and PTRS_PER_P4D variable For boot-time switching between 4- and 5-level paging we need to be able to fold p4d page table level at runtime. It requires variable PGDIR_SHIFT and PTRS_PER_P4D. The change doesn't affect the kernel image size much: text data bss dec hex filename 8628091 4734304 1368064 14730459 e0c4db vmlinux.before 8628393 4734340 1368064 14730797 e0c62d vmlinux.after Signed-off-by: Kirill A. Shutemov Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20180214111656.88514-7-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar --- arch/x86/boot/compressed/kaslr.c | 2 ++ arch/x86/include/asm/pgtable_32.h | 2 ++ arch/x86/include/asm/pgtable_64_types.h | 19 ++++++++++++------- arch/x86/kernel/cpu/mcheck/mce.c | 18 ++++++------------ arch/x86/kernel/head64.c | 6 +++++- arch/x86/mm/dump_pagetables.c | 12 +++++------- arch/x86/mm/init_64.c | 2 +- arch/x86/mm/kasan_init_64.c | 2 +- arch/x86/platform/efi/efi_64.c | 4 ++-- include/asm-generic/5level-fixup.h | 1 + include/asm-generic/pgtable-nop4d.h | 9 +++++---- include/linux/kasan.h | 2 +- mm/kasan/kasan_init.c | 2 +- 13 files changed, 44 insertions(+), 37 deletions(-) (limited to 'include/linux') diff --git a/arch/x86/boot/compressed/kaslr.c b/arch/x86/boot/compressed/kaslr.c index bd69e1830fbe..b18e8f9512de 100644 --- a/arch/x86/boot/compressed/kaslr.c +++ b/arch/x86/boot/compressed/kaslr.c @@ -48,6 +48,8 @@ #ifdef CONFIG_X86_5LEVEL unsigned int pgtable_l5_enabled __ro_after_init = 1; +unsigned int pgdir_shift __ro_after_init = 48; +unsigned int ptrs_per_p4d __ro_after_init = 512; #endif extern unsigned long get_cmd_line_ptr(void); diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h index e67c0620aec2..d829360e26bd 100644 --- a/arch/x86/include/asm/pgtable_32.h +++ b/arch/x86/include/asm/pgtable_32.h @@ -33,6 +33,8 @@ static inline void pgtable_cache_init(void) { } static inline void check_pgt_cache(void) { } void paging_init(void); +static inline int pgd_large(pgd_t pgd) { return 0; } + /* * Define this if things work differently on an i386 and an i486: * it will (on an i486) warn about kernel memory accesses that are diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h index 903e4d054bcb..0c48d80e11d4 100644 --- a/arch/x86/include/asm/pgtable_64_types.h +++ b/arch/x86/include/asm/pgtable_64_types.h @@ -26,6 +26,9 @@ extern unsigned int pgtable_l5_enabled; #define pgtable_l5_enabled 0 #endif +extern unsigned int pgdir_shift; +extern unsigned int ptrs_per_p4d; + #endif /* !__ASSEMBLY__ */ #define SHARED_KERNEL_PMD 0 @@ -35,16 +38,17 @@ extern unsigned int pgtable_l5_enabled; /* * PGDIR_SHIFT determines what a top-level page table entry can map */ -#define PGDIR_SHIFT 48 +#define PGDIR_SHIFT pgdir_shift #define PTRS_PER_PGD 512 /* * 4th level page in 5-level paging case */ -#define P4D_SHIFT 39 -#define PTRS_PER_P4D 512 -#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT) -#define P4D_MASK (~(P4D_SIZE - 1)) +#define P4D_SHIFT 39 +#define MAX_PTRS_PER_P4D 512 +#define PTRS_PER_P4D ptrs_per_p4d +#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT) +#define P4D_MASK (~(P4D_SIZE - 1)) #define MAX_POSSIBLE_PHYSMEM_BITS 52 @@ -53,8 +57,9 @@ extern unsigned int pgtable_l5_enabled; /* * PGDIR_SHIFT determines what a top-level page table entry can map */ -#define PGDIR_SHIFT 39 -#define PTRS_PER_PGD 512 +#define PGDIR_SHIFT 39 +#define PTRS_PER_PGD 512 +#define MAX_PTRS_PER_P4D 1 #endif /* CONFIG_X86_5LEVEL */ diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 3a8e88a611eb..cbb3af721291 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1082,19 +1082,7 @@ void arch_unmap_kpfn(unsigned long pfn) * a legal address. */ -/* - * Build time check to see if we have a spare virtual bit. Don't want - * to leave this until run time because most developers don't have a - * system that can exercise this code path. This will only become a - * problem if/when we move beyond 5-level page tables. - * - * Hard code "9" here because cpp doesn't grok ilog2(PTRS_PER_PGD) - */ -#if PGDIR_SHIFT + 9 < 63 decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63)); -#else -#error "no unused virtual bit available" -#endif if (set_memory_np(decoy_addr, 1)) pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn); @@ -2328,6 +2316,12 @@ static __init int mcheck_init_device(void) { int err; + /* + * Check if we have a spare virtual bit. This will only become + * a problem if/when we move beyond 5-level page tables. + */ + MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); + if (!mce_available(&boot_cpu_data)) { err = -EIO; goto err_out; diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 17d00d1886de..98b0ff49b220 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -42,6 +42,10 @@ pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX); #ifdef CONFIG_X86_5LEVEL unsigned int pgtable_l5_enabled __ro_after_init = 1; EXPORT_SYMBOL(pgtable_l5_enabled); +unsigned int pgdir_shift __ro_after_init = 48; +EXPORT_SYMBOL(pgdir_shift); +unsigned int ptrs_per_p4d __ro_after_init = 512; +EXPORT_SYMBOL(ptrs_per_p4d); #endif #ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT @@ -336,7 +340,7 @@ asmlinkage __visible void __init x86_64_start_kernel(char * real_mode_data) BUILD_BUG_ON((__START_KERNEL_map & ~PMD_MASK) != 0); BUILD_BUG_ON((MODULES_VADDR & ~PMD_MASK) != 0); BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL)); - BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) == + MAYBE_BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) == (__START_KERNEL & PGDIR_MASK))); BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) <= MODULES_END); diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c index a89f2dbc3531..420058b05d39 100644 --- a/arch/x86/mm/dump_pagetables.c +++ b/arch/x86/mm/dump_pagetables.c @@ -428,14 +428,15 @@ static void walk_pud_level(struct seq_file *m, struct pg_state *st, p4d_t addr, #define p4d_none(a) pud_none(__pud(p4d_val(a))) #endif -#if PTRS_PER_P4D > 1 - static void walk_p4d_level(struct seq_file *m, struct pg_state *st, pgd_t addr, unsigned long P) { int i; p4d_t *start, *p4d_start; pgprotval_t prot; + if (PTRS_PER_P4D == 1) + return walk_pud_level(m, st, __p4d(pgd_val(addr)), P); + p4d_start = start = (p4d_t *)pgd_page_vaddr(addr); for (i = 0; i < PTRS_PER_P4D; i++) { @@ -455,11 +456,8 @@ static void walk_p4d_level(struct seq_file *m, struct pg_state *st, pgd_t addr, } } -#else -#define walk_p4d_level(m,s,a,p) walk_pud_level(m,s,__p4d(pgd_val(a)),p) -#define pgd_large(a) p4d_large(__p4d(pgd_val(a))) -#define pgd_none(a) p4d_none(__p4d(pgd_val(a))) -#endif +#define pgd_large(a) (pgtable_l5_enabled ? pgd_large(a) : p4d_large(__p4d(pgd_val(a)))) +#define pgd_none(a) (pgtable_l5_enabled ? pgd_none(a) : p4d_none(__p4d(pgd_val(a)))) static inline bool is_hypervisor_range(int idx) { diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 1ab42c852069..6a4b20bc7527 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -143,7 +143,7 @@ void sync_global_pgds(unsigned long start, unsigned long end) * With folded p4d, pgd_none() is always false, we need to * handle synchonization on p4d level. */ - BUILD_BUG_ON(pgd_none(*pgd_ref)); + MAYBE_BUILD_BUG_ON(pgd_none(*pgd_ref)); p4d_ref = p4d_offset(pgd_ref, addr); if (p4d_none(*p4d_ref)) diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasan_init_64.c index af6f2f9c6a26..12ec90f62457 100644 --- a/arch/x86/mm/kasan_init_64.c +++ b/arch/x86/mm/kasan_init_64.c @@ -19,7 +19,7 @@ extern struct range pfn_mapped[E820_MAX_ENTRIES]; -static p4d_t tmp_p4d_table[PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE); +static p4d_t tmp_p4d_table[MAX_PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE); static __init void *early_alloc(size_t size, int nid, bool panic) { diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c index 780460aa5ea5..d52aaa7dc088 100644 --- a/arch/x86/platform/efi/efi_64.c +++ b/arch/x86/platform/efi/efi_64.c @@ -257,8 +257,8 @@ void efi_sync_low_kernel_mappings(void) * only span a single PGD entry and that the entry also maps * other important kernel regions. */ - BUILD_BUG_ON(pgd_index(EFI_VA_END) != pgd_index(MODULES_END)); - BUILD_BUG_ON((EFI_VA_START & PGDIR_MASK) != + MAYBE_BUILD_BUG_ON(pgd_index(EFI_VA_END) != pgd_index(MODULES_END)); + MAYBE_BUILD_BUG_ON((EFI_VA_START & PGDIR_MASK) != (EFI_VA_END & PGDIR_MASK)); pgd_efi = efi_pgd + pgd_index(PAGE_OFFSET); diff --git a/include/asm-generic/5level-fixup.h b/include/asm-generic/5level-fixup.h index dfbd9d990637..9c2e0708eb82 100644 --- a/include/asm-generic/5level-fixup.h +++ b/include/asm-generic/5level-fixup.h @@ -8,6 +8,7 @@ #define P4D_SHIFT PGDIR_SHIFT #define P4D_SIZE PGDIR_SIZE #define P4D_MASK PGDIR_MASK +#define MAX_PTRS_PER_P4D 1 #define PTRS_PER_P4D 1 #define p4d_t pgd_t diff --git a/include/asm-generic/pgtable-nop4d.h b/include/asm-generic/pgtable-nop4d.h index 8f22f55de17a..1a29b2a0282b 100644 --- a/include/asm-generic/pgtable-nop4d.h +++ b/include/asm-generic/pgtable-nop4d.h @@ -8,10 +8,11 @@ typedef struct { pgd_t pgd; } p4d_t; -#define P4D_SHIFT PGDIR_SHIFT -#define PTRS_PER_P4D 1 -#define P4D_SIZE (1UL << P4D_SHIFT) -#define P4D_MASK (~(P4D_SIZE-1)) +#define P4D_SHIFT PGDIR_SHIFT +#define MAX_PTRS_PER_P4D 1 +#define PTRS_PER_P4D 1 +#define P4D_SIZE (1UL << P4D_SHIFT) +#define P4D_MASK (~(P4D_SIZE-1)) /* * The "pgd_xxx()" functions here are trivial for a folded two-level diff --git a/include/linux/kasan.h b/include/linux/kasan.h index adc13474a53b..d6459bd1376d 100644 --- a/include/linux/kasan.h +++ b/include/linux/kasan.h @@ -18,7 +18,7 @@ extern unsigned char kasan_zero_page[PAGE_SIZE]; extern pte_t kasan_zero_pte[PTRS_PER_PTE]; extern pmd_t kasan_zero_pmd[PTRS_PER_PMD]; extern pud_t kasan_zero_pud[PTRS_PER_PUD]; -extern p4d_t kasan_zero_p4d[PTRS_PER_P4D]; +extern p4d_t kasan_zero_p4d[MAX_PTRS_PER_P4D]; void kasan_populate_zero_shadow(const void *shadow_start, const void *shadow_end); diff --git a/mm/kasan/kasan_init.c b/mm/kasan/kasan_init.c index 554e4c0f23a2..f436246ccc79 100644 --- a/mm/kasan/kasan_init.c +++ b/mm/kasan/kasan_init.c @@ -31,7 +31,7 @@ unsigned char kasan_zero_page[PAGE_SIZE] __page_aligned_bss; #if CONFIG_PGTABLE_LEVELS > 4 -p4d_t kasan_zero_p4d[PTRS_PER_P4D] __page_aligned_bss; +p4d_t kasan_zero_p4d[MAX_PTRS_PER_P4D] __page_aligned_bss; #endif #if CONFIG_PGTABLE_LEVELS > 3 pud_t kasan_zero_pud[PTRS_PER_PUD] __page_aligned_bss; -- cgit v1.2.3 From 8b4282e6b8e239d8ce68ab884c89335cc6fdd7c7 Mon Sep 17 00:00:00 2001 From: Shameer Kolothum Date: Tue, 13 Feb 2018 15:20:50 +0000 Subject: ACPI/IORT: Add msi address regions reservation helper On some platforms msi parent address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves ITS address regions - the msi parent - through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. The function checks for the smmu model number and only applies the msi reservation if the platform requires it. Signed-off-by: Shameer Kolothum Reviewed-by: Lorenzo Pieralisi [For the ITS part] Reviewed-by: Marc Zyngier Signed-off-by: Joerg Roedel --- drivers/acpi/arm64/iort.c | 111 +++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 3 files changed, 116 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 95255ecfae7c..e2f7bddf5522 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -39,6 +39,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -161,14 +162,16 @@ static LIST_HEAD(iort_msi_chip_list); static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -178,6 +181,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -581,6 +585,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + int ret = -ENODEV; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + ret = 0; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return ret; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -766,6 +788,24 @@ static inline bool iort_iommu_driver_enabled(u8 type) } #ifdef CONFIG_IOMMU_API +static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) +{ + struct acpi_iort_node *iommu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; + + iommu = iort_get_iort_node(fwspec->iommu_fwnode); + + if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) { + struct acpi_iort_smmu_v3 *smmu; + + smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data; + if (smmu->model == ACPI_IORT_SMMU_V3_HISILICON_HI161X) + return iommu; + } + + return NULL; +} + static inline const struct iommu_ops *iort_fwspec_iommu_ops( struct iommu_fwspec *fwspec) { @@ -782,6 +822,69 @@ static inline int iort_add_device_replay(const struct iommu_ops *ops, return err; } + +/** + * iort_iommu_msi_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @head: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of msi reserved regions on success (0 if platform + * doesn't require the reservation or no associated msi regions), + * appropriate error value otherwise. The ITS interrupt translation + * spaces (ITS_base + SZ_64K, SZ_64K) associated with the device + * are the msi reserved regions. + */ +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct acpi_iort_its_group *its; + struct acpi_iort_node *iommu_node, *its_node = NULL; + int i, resv = 0; + + iommu_node = iort_get_msi_resv_iommu(dev); + if (!iommu_node) + return 0; + + /* + * Current logic to reserve ITS regions relies on HW topologies + * where a given PCI or named component maps its IDs to only one + * ITS group; if a PCI or named component can map its IDs to + * different ITS groups through IORT mappings this function has + * to be reworked to ensure we reserve regions for all ITS groups + * a given PCI or named component may map IDs to. + */ + + for (i = 0; i < dev->iommu_fwspec->num_ids; i++) { + its_node = iort_node_map_id(iommu_node, + dev->iommu_fwspec->ids[i], + NULL, IORT_MSI_TYPE); + if (its_node) + break; + } + + if (!its_node) + return 0; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)its_node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K, + prot, IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } + + return (resv == its->its_count) ? resv : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops( struct iommu_fwspec *fwspec) @@ -789,6 +892,8 @@ static inline const struct iommu_ops *iort_fwspec_iommu_ops( static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return 0; } #endif static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 06f025fd5726..ab99d1bd7087 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3450,7 +3450,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 2f7a29242b87..38cd77b39a64 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -38,6 +39,7 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id); /* IOMMU interface */ void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id) @@ -52,6 +54,9 @@ static inline void iort_dma_setup(struct device *dev, u64 *dma_addr, static inline const struct iommu_ops *iort_iommu_configure( struct device *dev) { return NULL; } +static inline +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return 0; } #endif #endif /* __ACPI_IORT_H__ */ -- cgit v1.2.3 From 9b00bc7b901ff672a9252002d3810fdf9489bc64 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 12 Feb 2018 13:45:30 +0100 Subject: spi: spi-gpio: Rewrite to use GPIO descriptors This converts the bit-banged GPIO SPI driver to looking up and using GPIO descriptors to get a handle on GPIO lines for SCK, MOSI, MISO and all CS lines. All existing board files are converted in one go to keep it all consistent. With these conversions I rarely find any interrim steps that makes any sense. Device tree probing and GPIO handling should work like before also after this patch. For board files, we stop using controller data to pass the GPIO line for chip select, instead we pass this as a GPIO descriptor lookup like everything else. In some s3c24xx machines the names of the SPI devices were set to "spi-gpio" rather than "spi_gpio" which can never have worked, I fixed it working (I guess) as part of this patch set. Sometimes I wonder how this code got upstream in the first place, it obviously is not tested. mach-s3c64xx/mach-smartq.c has the same problem and additionally defines the *same* GPIO line for MOSI and MISO which is not going to be accepted by gpiolib. As the lines were number 1,2,2 I assumed it was a typo and use lines 1,2,3. A comment gives awat that line 0 is chip select though no actual SPI device is provided for the LCD supposed to be on this bit-banged SPI bus. I left it intact instead of just deleting the bus though. Kill off board file code that try to initialize the SPI lines to the same values that they will later be set by the spi_gpio driver anyways. Given the huge number of weird things in these board files I do not think this code is very tested or put in with much afterthought anyways. In order to assert that we do not get performance regressions on this crucial bing-banged driver, a ran a script like this dumping the Ilitek ILI9322 regmap 10000 times (it has no caching obviously) on an otherwise idle system in two iterations before and after the patches: #!/bin/sh for run in `seq 10000` do cat /debug/regmap/spi0.0/registers > /dev/null done Before the patch: time test.sh real 3m 41.03s user 0m 29.41s sys 3m 7.22s time test.sh real 3m 44.24s user 0m 32.31s sys 3m 7.60s After the patch: time test.sh real 3m 41.32s user 0m 28.92s sys 3m 8.08s time test.sh real 3m 39.92s user 0m 30.20s sys 3m 5.56s So any performance differences seems to be in the error margin. Signed-off-by: Linus Walleij Acked-by: Olof Johansson Reviewed-by: Andy Shevchenko Signed-off-by: Mark Brown --- arch/arm/mach-pxa/cm-x300.c | 21 ++- arch/arm/mach-pxa/raumfeld.c | 26 +++- arch/arm/mach-s3c24xx/mach-jive.c | 55 ++++--- arch/arm/mach-s3c24xx/mach-qt2410.c | 26 +++- arch/arm/mach-s3c64xx/mach-smartq.c | 22 ++- arch/mips/alchemy/devboards/db1000.c | 24 ++- arch/mips/jz4740/board-qi_lb60.c | 26 +++- drivers/misc/eeprom/digsy_mtc_eeprom.c | 29 +++- drivers/spi/spi-gpio.c | 270 +++++++++++---------------------- include/linux/spi/spi_gpio.h | 49 +----- 10 files changed, 262 insertions(+), 286 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index c487401b6fdb..69d7f48a4183 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -343,9 +344,6 @@ static inline void cm_x300_init_bl(void) {} #define LCD_SPI_BUS_NUM (1) static struct spi_gpio_platform_data cm_x300_spi_gpio_pdata = { - .sck = GPIO_LCD_SCL, - .mosi = GPIO_LCD_DIN, - .miso = GPIO_LCD_DOUT, .num_chipselect = 1, }; @@ -357,6 +355,21 @@ static struct platform_device cm_x300_spi_gpio = { }, }; +static struct gpiod_lookup_table cm_x300_spi_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("gpio-pxa", GPIO_LCD_SCL, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DIN, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", GPIO_LCD_DOUT, + "miso", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-pxa", GPIO_LCD_CS, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; + static struct tdo24m_platform_data cm_x300_tdo24m_pdata = { .model = TDO35S, }; @@ -367,7 +380,6 @@ static struct spi_board_info cm_x300_spi_devices[] __initdata = { .max_speed_hz = 1000000, .bus_num = LCD_SPI_BUS_NUM, .chip_select = 0, - .controller_data = (void *) GPIO_LCD_CS, .platform_data = &cm_x300_tdo24m_pdata, }, }; @@ -376,6 +388,7 @@ static void __init cm_x300_init_spi(void) { spi_register_board_info(cm_x300_spi_devices, ARRAY_SIZE(cm_x300_spi_devices)); + gpiod_add_lookup_table(&cm_x300_spi_gpiod_table); platform_device_register(&cm_x300_spi_gpio); } #else diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 4d5d05cf87d6..e7ac7dcb95e9 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -646,9 +646,6 @@ static void __init raumfeld_lcd_init(void) */ static struct spi_gpio_platform_data raumfeld_spi_platform_data = { - .sck = GPIO_SPI_CLK, - .mosi = GPIO_SPI_MOSI, - .miso = GPIO_SPI_MISO, .num_chipselect = 3, }; @@ -660,6 +657,25 @@ static struct platform_device raumfeld_spi_device = { } }; +static struct gpiod_lookup_table raumfeld_spi_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("gpio-0", GPIO_SPI_CLK, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-0", GPIO_SPI_MOSI, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio-0", GPIO_SPI_MISO, + "miso", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-0", GPIO_SPDIF_CS, + "cs", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-0", GPIO_ACCEL_CS, + "cs", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-0", GPIO_MCLK_DAC_CS, + "cs", 2, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static struct lis3lv02d_platform_data lis3_pdata = { .click_flags = LIS3_CLICK_SINGLE_X | LIS3_CLICK_SINGLE_Y | @@ -680,7 +696,6 @@ static struct lis3lv02d_platform_data lis3_pdata = { .max_speed_hz = 10000, \ .bus_num = 0, \ .chip_select = 0, \ - .controller_data = (void *) GPIO_SPDIF_CS, \ } #define SPI_LIS3 \ @@ -689,7 +704,6 @@ static struct lis3lv02d_platform_data lis3_pdata = { .max_speed_hz = 1000000, \ .bus_num = 0, \ .chip_select = 1, \ - .controller_data = (void *) GPIO_ACCEL_CS, \ .platform_data = &lis3_pdata, \ .irq = PXA_GPIO_TO_IRQ(GPIO_ACCEL_IRQ), \ } @@ -700,7 +714,6 @@ static struct lis3lv02d_platform_data lis3_pdata = { .max_speed_hz = 1000000, \ .bus_num = 0, \ .chip_select = 2, \ - .controller_data = (void *) GPIO_MCLK_DAC_CS, \ } static struct spi_board_info connector_spi_devices[] __initdata = { @@ -1066,6 +1079,7 @@ static void __init raumfeld_common_init(void) else gpio_direction_output(GPIO_SHUTDOWN_SUPPLY, 0); + gpiod_add_lookup_table(&raumfeld_spi_gpiod_table); platform_add_devices(ARRAY_AND_SIZE(raumfeld_common_devices)); i2c_register_board_info(1, &raumfeld_pwri2c_board_info, 1); } diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c index a3ddbbbd6d92..59589a4a0d4b 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c24xx/mach-jive.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -388,32 +389,53 @@ static struct ili9320_platdata jive_lcm_config = { /* LCD SPI support */ static struct spi_gpio_platform_data jive_lcd_spi = { - .sck = S3C2410_GPG(8), - .mosi = S3C2410_GPB(8), - .miso = SPI_GPIO_NO_MISO, + .num_chipselect = 1, }; static struct platform_device jive_device_lcdspi = { - .name = "spi-gpio", + .name = "spi_gpio", .id = 1, .dev.platform_data = &jive_lcd_spi, }; +static struct gpiod_lookup_table jive_lcdspi_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("GPIOG", 8, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOB", 8, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOB", 7, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; /* WM8750 audio code SPI definition */ static struct spi_gpio_platform_data jive_wm8750_spi = { - .sck = S3C2410_GPB(4), - .mosi = S3C2410_GPB(9), - .miso = SPI_GPIO_NO_MISO, + .num_chipselect = 1, }; static struct platform_device jive_device_wm8750 = { - .name = "spi-gpio", + .name = "spi_gpio", .id = 2, .dev.platform_data = &jive_wm8750_spi, }; +static struct gpiod_lookup_table jive_wm8750_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("GPIOB", 4, + "gpio-sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOB", 9, + "gpio-mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOH", 10, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; + /* JIVE SPI devices. */ static struct spi_board_info __initdata jive_spi_devs[] = { @@ -424,14 +446,12 @@ static struct spi_board_info __initdata jive_spi_devs[] = { .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */ .max_speed_hz = 100000, .platform_data = &jive_lcm_config, - .controller_data = (void *)S3C2410_GPB(7), }, { .modalias = "WM8750", .bus_num = 2, .chip_select = 0, .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */ .max_speed_hz = 100000, - .controller_data = (void *)S3C2410_GPH(10), }, }; @@ -619,25 +639,12 @@ static void __init jive_machine_init(void) /** TODO - check that this is after the cmdline option! */ s3c_nand_set_platdata(&jive_nand_info); - /* initialise the spi */ - gpio_request(S3C2410_GPG(13), "lcm reset"); gpio_direction_output(S3C2410_GPG(13), 0); - gpio_request(S3C2410_GPB(7), "jive spi"); - gpio_direction_output(S3C2410_GPB(7), 1); - gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL); gpio_free(S3C2410_GPB(6)); - gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL); - gpio_free(S3C2410_GPG(8)); - - /* initialise the WM8750 spi */ - - gpio_request(S3C2410_GPH(10), "jive wm8750 spi"); - gpio_direction_output(S3C2410_GPH(10), 1); - /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ @@ -655,6 +662,8 @@ static void __init jive_machine_init(void) pm_power_off = jive_power_off; + gpiod_add_lookup_table(&jive_lcdspi_gpiod_table); + gpiod_add_lookup_table(&jive_wm8750_gpiod_table); platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices)); } diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index 9c8373b8d9c3..5d48e5b6e738 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -194,17 +195,30 @@ static struct platform_device qt2410_led = { /* SPI */ static struct spi_gpio_platform_data spi_gpio_cfg = { - .sck = S3C2410_GPG(7), - .mosi = S3C2410_GPG(6), - .miso = S3C2410_GPG(5), + .num_chipselect = 1, }; static struct platform_device qt2410_spi = { - .name = "spi-gpio", + .name = "spi_gpio", .id = 1, .dev.platform_data = &spi_gpio_cfg, }; +static struct gpiod_lookup_table qt2410_spi_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("GPIOG", 7, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOG", 6, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOG", 5, + "miso", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOB", 5, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; + /* Board devices */ static struct platform_device *qt2410_devices[] __initdata = { @@ -323,9 +337,7 @@ static void __init qt2410_machine_init(void) s3c24xx_udc_set_platdata(&qt2410_udc_cfg); s3c_i2c0_set_platdata(NULL); - WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs")); - gpio_direction_output(S3C2410_GPB(5), 1); - + gpiod_add_lookup_table(&qt2410_spi_gpiod_table); platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); s3c_pm_init(); } diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index 5655fe968b1f..951208f168e7 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -206,17 +206,30 @@ static int __init smartq_lcd_setup_gpio(void) /* GPM0 -> CS */ static struct spi_gpio_platform_data smartq_lcd_control = { - .sck = S3C64XX_GPM(1), - .mosi = S3C64XX_GPM(2), - .miso = S3C64XX_GPM(2), + .num_chipselect = 1, }; static struct platform_device smartq_lcd_control_device = { - .name = "spi-gpio", + .name = "spi_gpio", .id = 1, .dev.platform_data = &smartq_lcd_control, }; +static struct gpiod_lookup_table smartq_lcd_control_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("GPIOM", 1, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOM", 2, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOM", 3, + "miso", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOM", 0, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; + static void smartq_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) { gpio_direction_output(S3C64XX_GPM(3), power); @@ -404,6 +417,7 @@ void __init smartq_machine_init(void) WARN_ON(smartq_wifi_init()); pwm_add_table(smartq_pwm_lookup, ARRAY_SIZE(smartq_pwm_lookup)); + gpiod_add_lookup_table(&smartq_lcd_control_gpiod_table); platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); gpiod_add_lookup_table(&smartq_audio_gpios); diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 433c4b9a9f0a..13e3c84859fe 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -447,9 +448,6 @@ static struct ads7846_platform_data db1100_touch_pd = { }; static struct spi_gpio_platform_data db1100_spictl_pd = { - .sck = 209, - .mosi = 208, - .miso = 207, .num_chipselect = 1, }; @@ -462,7 +460,6 @@ static struct spi_board_info db1100_spi_info[] __initdata = { .mode = 0, .irq = AU1100_GPIO21_INT, .platform_data = &db1100_touch_pd, - .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */ }, }; @@ -474,6 +471,24 @@ static struct platform_device db1100_spi_dev = { }, }; +/* + * Alchemy GPIO 2 has its base at 200 so the GPIO lines + * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip. + */ +static struct gpiod_lookup_table db1100_spi_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("alchemy-gpio2", 9, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("alchemy-gpio2", 8, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("alchemy-gpio2", 7, + "miso", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("alchemy-gpio2", 10, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; static struct platform_device *db1x00_devs[] = { &db1x00_codec_dev, @@ -541,6 +556,7 @@ int __init db1000_dev_setup(void) clk_put(p); platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); + gpiod_add_lookup_table(&db1100_spi_gpiod_table); platform_device_register(&db1100_spi_dev); } else if (board == BCSR_WHOAMI_DB1000) { c0 = AU1000_GPIO2_INT; diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 6d7f97552200..60f0767507c6 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -313,25 +313,34 @@ static struct jz4740_fb_platform_data qi_lb60_fb_pdata = { .pixclk_falling_edge = 1, }; -struct spi_gpio_platform_data spigpio_platform_data = { - .sck = JZ_GPIO_PORTC(23), - .mosi = JZ_GPIO_PORTC(22), - .miso = -1, +struct spi_gpio_platform_data qi_lb60_spigpio_platform_data = { .num_chipselect = 1, }; -static struct platform_device spigpio_device = { +static struct platform_device qi_lb60_spigpio_device = { .name = "spi_gpio", .id = 1, .dev = { - .platform_data = &spigpio_platform_data, + .platform_data = &qi_lb60_spigpio_platform_data, + }, +}; + +static struct gpiod_lookup_table qi_lb60_spigpio_gpio_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("GPIOC", 23, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOC", 22, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOC", 21, + "cs", GPIO_ACTIVE_HIGH), + { }, }, }; static struct spi_board_info qi_lb60_spi_board_info[] = { { .modalias = "ili8960", - .controller_data = (void *)JZ_GPIO_PORTC(21), .chip_select = 0, .bus_num = 1, .max_speed_hz = 30 * 1000, @@ -435,7 +444,7 @@ static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_mmc_device, &jz4740_nand_device, &qi_lb60_keypad, - &spigpio_device, + &qi_lb60_spigpio_device, &jz4740_framebuffer_device, &jz4740_pcm_device, &jz4740_i2s_device, @@ -489,6 +498,7 @@ static int __init qi_lb60_init_platform_devices(void) gpiod_add_lookup_table(&qi_lb60_audio_gpio_table); gpiod_add_lookup_table(&qi_lb60_nand_gpio_table); + gpiod_add_lookup_table(&qi_lb60_spigpio_gpio_table); spi_register_board_info(qi_lb60_spi_board_info, ARRAY_SIZE(qi_lb60_spi_board_info)); diff --git a/drivers/misc/eeprom/digsy_mtc_eeprom.c b/drivers/misc/eeprom/digsy_mtc_eeprom.c index 66d9e1baeae5..fbde2516c04f 100644 --- a/drivers/misc/eeprom/digsy_mtc_eeprom.c +++ b/drivers/misc/eeprom/digsy_mtc_eeprom.c @@ -7,9 +7,18 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. + * + * FIXME: this driver is used on a device-tree probed platform: it + * should be defined as a bit-banged SPI device and probed from the device + * tree and not like this with static grabbing of a few numbered GPIO + * lines at random. + * + * Add proper SPI and EEPROM in arch/powerpc/boot/dts/digsy_mtc.dts + * and delete this driver. */ #include +#include #include #include #include @@ -42,9 +51,6 @@ struct eeprom_93xx46_platform_data digsy_mtc_eeprom_data = { }; static struct spi_gpio_platform_data eeprom_spi_gpio_data = { - .sck = GPIO_EEPROM_CLK, - .mosi = GPIO_EEPROM_DI, - .miso = GPIO_EEPROM_DO, .num_chipselect = 1, }; @@ -56,6 +62,21 @@ static struct platform_device digsy_mtc_eeprom = { }, }; +static struct gpiod_lookup_table eeprom_spi_gpiod_table = { + .dev_id = "spi_gpio", + .table = { + GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_CLK, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_DI, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_DO, + "miso", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio@b00", GPIO_EEPROM_CS, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; + static struct spi_board_info digsy_mtc_eeprom_info[] __initdata = { { .modalias = "93xx46", @@ -63,7 +84,6 @@ static struct spi_board_info digsy_mtc_eeprom_info[] __initdata = { .bus_num = EE_SPI_BUS_NUM, .chip_select = 0, .mode = SPI_MODE_0, - .controller_data = (void *)GPIO_EEPROM_CS, .platform_data = &digsy_mtc_eeprom_data, }, }; @@ -78,6 +98,7 @@ static int __init digsy_mtc_eeprom_devices_init(void) pr_err("can't request gpio %d\n", GPIO_EEPROM_OE); return ret; } + gpiod_add_lookup_table(&eeprom_spi_gpiod_table); spi_register_board_info(digsy_mtc_eeprom_info, ARRAY_SIZE(digsy_mtc_eeprom_info)); return platform_device_register(&digsy_mtc_eeprom); diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index 1c34c9314c8a..b85a93cad44a 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c @@ -2,6 +2,7 @@ * SPI master driver using generic bitbanged GPIO * * Copyright (C) 2006,2008 David Brownell + * Copyright (C) 2017 Linus Walleij * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,10 +17,9 @@ #include #include #include -#include +#include #include #include -#include #include #include @@ -44,7 +44,11 @@ struct spi_gpio { struct spi_bitbang bitbang; struct spi_gpio_platform_data pdata; struct platform_device *pdev; - unsigned long cs_gpios[0]; + struct gpio_desc *sck; + struct gpio_desc *miso; + struct gpio_desc *mosi; + struct gpio_desc **cs_gpios; + bool has_cs; }; /*----------------------------------------------------------------------*/ @@ -77,13 +81,6 @@ struct spi_gpio { #define GENERIC_BITBANG /* vs tight inlines */ -/* all functions referencing these symbols must define pdata */ -#define SPI_MISO_GPIO ((pdata)->miso) -#define SPI_MOSI_GPIO ((pdata)->mosi) -#define SPI_SCK_GPIO ((pdata)->sck) - -#define SPI_N_CHIPSEL ((pdata)->num_chipselect) - #endif /*----------------------------------------------------------------------*/ @@ -105,25 +102,27 @@ spi_to_pdata(const struct spi_device *spi) return &spi_to_spi_gpio(spi)->pdata; } -/* this is #defined to avoid unused-variable warnings when inlining */ -#define pdata spi_to_pdata(spi) - +/* These helpers are in turn called by the bitbang inlines */ static inline void setsck(const struct spi_device *spi, int is_on) { - gpio_set_value_cansleep(SPI_SCK_GPIO, is_on); + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + gpiod_set_value_cansleep(spi_gpio->sck, is_on); } static inline void setmosi(const struct spi_device *spi, int is_on) { - gpio_set_value_cansleep(SPI_MOSI_GPIO, is_on); + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + gpiod_set_value_cansleep(spi_gpio->mosi, is_on); } static inline int getmiso(const struct spi_device *spi) { - return !!gpio_get_value_cansleep(SPI_MISO_GPIO); -} + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); -#undef pdata + return !!gpiod_get_value_cansleep(spi_gpio->miso); +} /* * NOTE: this clocks "as fast as we can". It "should" be a function of the @@ -216,123 +215,89 @@ static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi, static void spi_gpio_chipselect(struct spi_device *spi, int is_active) { struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); - unsigned long cs = spi_gpio->cs_gpios[spi->chip_select]; - /* set initial clock polarity */ + /* set initial clock line level */ if (is_active) - setsck(spi, spi->mode & SPI_CPOL); + gpiod_set_value_cansleep(spi_gpio->sck, spi->mode & SPI_CPOL); + + /* Drive chip select line, if we have one */ + if (spi_gpio->has_cs) { + struct gpio_desc *cs = spi_gpio->cs_gpios[spi->chip_select]; - if (cs != SPI_GPIO_NO_CHIPSELECT) { - /* SPI is normally active-low */ - gpio_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); + /* SPI chip selects are normally active-low */ + gpiod_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); } } static int spi_gpio_setup(struct spi_device *spi) { - unsigned long cs; + struct gpio_desc *cs; int status = 0; struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); - struct device_node *np = spi->master->dev.of_node; - - if (np) { - /* - * In DT environments, the CS GPIOs have already been - * initialized from the "cs-gpios" property of the node. - */ - cs = spi_gpio->cs_gpios[spi->chip_select]; - } else { - /* - * ... otherwise, take it from spi->controller_data - */ - cs = (uintptr_t) spi->controller_data; - } - if (!spi->controller_state) { - if (cs != SPI_GPIO_NO_CHIPSELECT) { - status = gpio_request(cs, dev_name(&spi->dev)); - if (status) - return status; - status = gpio_direction_output(cs, - !(spi->mode & SPI_CS_HIGH)); - } - } - if (!status) { - /* in case it was initialized from static board data */ - spi_gpio->cs_gpios[spi->chip_select] = cs; + /* + * The CS GPIOs have already been + * initialized from the descriptor lookup. + */ + cs = spi_gpio->cs_gpios[spi->chip_select]; + if (!spi->controller_state && cs) + status = gpiod_direction_output(cs, + !(spi->mode & SPI_CS_HIGH)); + + if (!status) status = spi_bitbang_setup(spi); - } - if (status) { - if (!spi->controller_state && cs != SPI_GPIO_NO_CHIPSELECT) - gpio_free(cs); - } return status; } static void spi_gpio_cleanup(struct spi_device *spi) { - struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); - unsigned long cs = spi_gpio->cs_gpios[spi->chip_select]; - - if (cs != SPI_GPIO_NO_CHIPSELECT) - gpio_free(cs); spi_bitbang_cleanup(spi); } -static int spi_gpio_alloc(unsigned pin, const char *label, bool is_in) -{ - int value; - - value = gpio_request(pin, label); - if (value == 0) { - if (is_in) - value = gpio_direction_input(pin); - else - value = gpio_direction_output(pin, 0); - } - return value; -} - -static int spi_gpio_request(struct spi_gpio_platform_data *pdata, - const char *label, u16 *res_flags) +/* + * It can be convenient to use this driver with pins that have alternate + * functions associated with a "native" SPI controller if a driver for that + * controller is not available, or is missing important functionality. + * + * On platforms which can do so, configure MISO with a weak pullup unless + * there's an external pullup on that signal. That saves power by avoiding + * floating signals. (A weak pulldown would save power too, but many + * drivers expect to see all-ones data as the no slave "response".) + */ +static int spi_gpio_request(struct device *dev, + struct spi_gpio *spi_gpio, + unsigned int num_chipselects, + u16 *mflags) { - int value; - - /* NOTE: SPI_*_GPIO symbols may reference "pdata" */ + int i; - if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI) { - value = spi_gpio_alloc(SPI_MOSI_GPIO, label, false); - if (value) - goto done; - } else { + spi_gpio->mosi = devm_gpiod_get_optional(dev, "mosi", GPIOD_OUT_LOW); + if (IS_ERR(spi_gpio->mosi)) + return PTR_ERR(spi_gpio->mosi); + if (!spi_gpio->mosi) /* HW configuration without MOSI pin */ - *res_flags |= SPI_MASTER_NO_TX; - } + *mflags |= SPI_MASTER_NO_TX; - if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) { - value = spi_gpio_alloc(SPI_MISO_GPIO, label, true); - if (value) - goto free_mosi; - } else { + spi_gpio->miso = devm_gpiod_get_optional(dev, "miso", GPIOD_IN); + if (IS_ERR(spi_gpio->miso)) + return PTR_ERR(spi_gpio->miso); + if (!spi_gpio->miso) /* HW configuration without MISO pin */ - *res_flags |= SPI_MASTER_NO_RX; - } + *mflags |= SPI_MASTER_NO_RX; - value = spi_gpio_alloc(SPI_SCK_GPIO, label, false); - if (value) - goto free_miso; + spi_gpio->sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW); + if (IS_ERR(spi_gpio->mosi)) + return PTR_ERR(spi_gpio->mosi); - goto done; + for (i = 0; i < num_chipselects; i++) { + spi_gpio->cs_gpios[i] = devm_gpiod_get_index(dev, "cs", + i, GPIOD_OUT_HIGH); + if (IS_ERR(spi_gpio->cs_gpios[i])) + return PTR_ERR(spi_gpio->cs_gpios[i]); + } -free_miso: - if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) - gpio_free(SPI_MISO_GPIO); -free_mosi: - if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI) - gpio_free(SPI_MOSI_GPIO); -done: - return value; + return 0; } #ifdef CONFIG_OF @@ -358,26 +323,6 @@ static int spi_gpio_probe_dt(struct platform_device *pdev) if (!pdata) return -ENOMEM; - ret = of_get_named_gpio(np, "gpio-sck", 0); - if (ret < 0) { - dev_err(&pdev->dev, "gpio-sck property not found\n"); - goto error_free; - } - pdata->sck = ret; - - ret = of_get_named_gpio(np, "gpio-miso", 0); - if (ret < 0) { - dev_info(&pdev->dev, "gpio-miso property not found, switching to no-rx mode\n"); - pdata->miso = SPI_GPIO_NO_MISO; - } else - pdata->miso = ret; - - ret = of_get_named_gpio(np, "gpio-mosi", 0); - if (ret < 0) { - dev_info(&pdev->dev, "gpio-mosi property not found, switching to no-tx mode\n"); - pdata->mosi = SPI_GPIO_NO_MOSI; - } else - pdata->mosi = ret; ret = of_property_read_u32(np, "num-chipselects", &tmp); if (ret < 0) { @@ -409,7 +354,6 @@ static int spi_gpio_probe(struct platform_device *pdev) struct spi_gpio_platform_data *pdata; u16 master_flags = 0; bool use_of = 0; - int num_devices; status = spi_gpio_probe_dt(pdev); if (status < 0) @@ -423,59 +367,41 @@ static int spi_gpio_probe(struct platform_device *pdev) return -ENODEV; #endif - if (use_of && !SPI_N_CHIPSEL) - num_devices = 1; - else - num_devices = SPI_N_CHIPSEL; - - status = spi_gpio_request(pdata, dev_name(&pdev->dev), &master_flags); - if (status < 0) - return status; + master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio)); + if (!master) + return -ENOMEM; - master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio) + - (sizeof(unsigned long) * num_devices)); - if (!master) { - status = -ENOMEM; - goto gpio_free; - } spi_gpio = spi_master_get_devdata(master); + + spi_gpio->cs_gpios = devm_kzalloc(&pdev->dev, + pdata->num_chipselect * sizeof(*spi_gpio->cs_gpios), + GFP_KERNEL); + if (!spi_gpio->cs_gpios) + return -ENOMEM; + platform_set_drvdata(pdev, spi_gpio); + /* Determine if we have chip selects connected */ + spi_gpio->has_cs = !!pdata->num_chipselect; + spi_gpio->pdev = pdev; if (pdata) spi_gpio->pdata = *pdata; + status = spi_gpio_request(&pdev->dev, spi_gpio, + pdata->num_chipselect, &master_flags); + if (status) + return status; + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); master->flags = master_flags; master->bus_num = pdev->id; - master->num_chipselect = num_devices; + /* The master needs to think there is a chipselect even if not connected */ + master->num_chipselect = spi_gpio->has_cs ? pdata->num_chipselect : 1; master->setup = spi_gpio_setup; master->cleanup = spi_gpio_cleanup; #ifdef CONFIG_OF master->dev.of_node = pdev->dev.of_node; - - if (use_of) { - int i; - struct device_node *np = pdev->dev.of_node; - - /* - * In DT environments, take the CS GPIO from the "cs-gpios" - * property of the node. - */ - - if (!SPI_N_CHIPSEL) - spi_gpio->cs_gpios[0] = SPI_GPIO_NO_CHIPSELECT; - else - for (i = 0; i < SPI_N_CHIPSEL; i++) { - status = of_get_named_gpio(np, "cs-gpios", i); - if (status < 0) { - dev_err(&pdev->dev, - "invalid cs-gpios property\n"); - goto gpio_free; - } - spi_gpio->cs_gpios[i] = status; - } - } #endif spi_gpio->bitbang.master = master; @@ -496,15 +422,8 @@ static int spi_gpio_probe(struct platform_device *pdev) spi_gpio->bitbang.flags = SPI_CS_HIGH; status = spi_bitbang_start(&spi_gpio->bitbang); - if (status < 0) { -gpio_free: - if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) - gpio_free(SPI_MISO_GPIO); - if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI) - gpio_free(SPI_MOSI_GPIO); - gpio_free(SPI_SCK_GPIO); + if (status) spi_master_put(master); - } return status; } @@ -520,11 +439,6 @@ static int spi_gpio_remove(struct platform_device *pdev) /* stop() unregisters child devices too */ spi_bitbang_stop(&spi_gpio->bitbang); - if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) - gpio_free(SPI_MISO_GPIO); - if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI) - gpio_free(SPI_MOSI_GPIO); - gpio_free(SPI_SCK_GPIO); spi_master_put(spi_gpio->bitbang.master); return 0; diff --git a/include/linux/spi/spi_gpio.h b/include/linux/spi/spi_gpio.h index e7bd89a59cd1..9e7e83d8645b 100644 --- a/include/linux/spi/spi_gpio.h +++ b/include/linux/spi/spi_gpio.h @@ -8,64 +8,17 @@ * - id the same as the SPI bus number it implements * - dev.platform data pointing to a struct spi_gpio_platform_data * - * Or, see the driver code for information about speedups that are - * possible on platforms that support inlined access for GPIOs (no - * spi_gpio_platform_data is used). - * - * Use spi_board_info with these busses in the usual way, being sure - * that the controller_data being the GPIO used for each device's - * chipselect: - * - * static struct spi_board_info ... [] = { - * ... - * // this slave uses GPIO 42 for its chipselect - * .controller_data = (void *) 42, - * ... - * // this one uses GPIO 86 for its chipselect - * .controller_data = (void *) 86, - * ... - * }; - * - * If chipselect is not used (there's only one device on the bus), assign - * SPI_GPIO_NO_CHIPSELECT to the controller_data: - * .controller_data = (void *) SPI_GPIO_NO_CHIPSELECT; - * - * If the MISO or MOSI pin is not available then it should be set to - * SPI_GPIO_NO_MISO or SPI_GPIO_NO_MOSI. + * Use spi_board_info with these busses in the usual way. * * If the bitbanged bus is later switched to a "native" controller, * that platform_device and controller_data should be removed. */ -#define SPI_GPIO_NO_CHIPSELECT ((unsigned long)-1l) -#define SPI_GPIO_NO_MISO ((unsigned long)-1l) -#define SPI_GPIO_NO_MOSI ((unsigned long)-1l) - /** * struct spi_gpio_platform_data - parameter for bitbanged SPI master - * @sck: number of the GPIO used for clock output - * @mosi: number of the GPIO used for Master Output, Slave In (MOSI) data - * @miso: number of the GPIO used for Master Input, Slave Output (MISO) data * @num_chipselect: how many slaves to allow - * - * All GPIO signals used with the SPI bus managed through this driver - * (chipselects, MOSI, MISO, SCK) must be configured as GPIOs, instead - * of some alternate function. - * - * It can be convenient to use this driver with pins that have alternate - * functions associated with a "native" SPI controller if a driver for that - * controller is not available, or is missing important functionality. - * - * On platforms which can do so, configure MISO with a weak pullup unless - * there's an external pullup on that signal. That saves power by avoiding - * floating signals. (A weak pulldown would save power too, but many - * drivers expect to see all-ones data as the no slave "response".) */ struct spi_gpio_platform_data { - unsigned sck; - unsigned long mosi; - unsigned long miso; - u16 num_chipselect; }; -- cgit v1.2.3 From 330c7272c40e965b8ab510d1022acd6e6a32e9c8 Mon Sep 17 00:00:00 2001 From: David Ahern Date: Tue, 13 Feb 2018 08:52:00 -0800 Subject: net: Make dn_ptr depend on CONFIG_DECNET Signed-off-by: David Ahern Signed-off-by: David S. Miller --- include/linux/netdevice.h | 2 ++ net/core/dev.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 5eef6c8e2741..d2ef35e00626 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1800,7 +1800,9 @@ struct net_device { #endif void *atalk_ptr; struct in_device __rcu *ip_ptr; +#if IS_ENABLED(CONFIG_DECNET) struct dn_dev __rcu *dn_ptr; +#endif struct inet6_dev __rcu *ip6_ptr; void *ax25_ptr; struct wireless_dev *ieee80211_ptr; diff --git a/net/core/dev.c b/net/core/dev.c index df5241c8eda1..4bd4ad7ffda4 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -8134,8 +8134,9 @@ void netdev_run_todo(void) BUG_ON(!list_empty(&dev->ptype_specific)); WARN_ON(rcu_access_pointer(dev->ip_ptr)); WARN_ON(rcu_access_pointer(dev->ip6_ptr)); +#if IS_ENABLED(CONFIG_DECNET) WARN_ON(dev->dn_ptr); - +#endif if (dev->priv_destructor) dev->priv_destructor(dev); if (dev->needs_free_netdev) -- cgit v1.2.3 From 19ff13f2a411d99af67d8e51867d54b86e1bf017 Mon Sep 17 00:00:00 2001 From: David Ahern Date: Tue, 13 Feb 2018 08:52:01 -0800 Subject: net: Make ax25_ptr depend on CONFIG_AX25 Signed-off-by: David Ahern Signed-off-by: David S. Miller --- include/linux/netdevice.h | 2 ++ include/net/ax25.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include/linux') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index d2ef35e00626..936dc2c9dca1 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1804,7 +1804,9 @@ struct net_device { struct dn_dev __rcu *dn_ptr; #endif struct inet6_dev __rcu *ip6_ptr; +#if IS_ENABLED(CONFIG_AX25) void *ax25_ptr; +#endif struct wireless_dev *ieee80211_ptr; struct wpan_dev *ieee802154_ptr; #if IS_ENABLED(CONFIG_MPLS_ROUTING) diff --git a/include/net/ax25.h b/include/net/ax25.h index 76fb39c272a7..c91bc87931c7 100644 --- a/include/net/ax25.h +++ b/include/net/ax25.h @@ -318,10 +318,12 @@ void ax25_digi_invert(const ax25_digi *, ax25_digi *); extern ax25_dev *ax25_dev_list; extern spinlock_t ax25_dev_lock; +#if IS_ENABLED(CONFIG_AX25) static inline ax25_dev *ax25_dev_ax25dev(struct net_device *dev) { return dev->ax25_ptr; } +#endif ax25_dev *ax25_addr_ax25dev(ax25_address *); void ax25_dev_device_up(struct net_device *); -- cgit v1.2.3 From 89e58148fbf2e4cbd84006e263061c19a2b47adf Mon Sep 17 00:00:00 2001 From: David Ahern Date: Tue, 13 Feb 2018 08:52:02 -0800 Subject: net: Make atalk_ptr depend on ATALK or IRDA Signed-off-by: David Ahern Signed-off-by: David S. Miller --- include/linux/atalk.h | 2 ++ include/linux/netdevice.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include/linux') diff --git a/include/linux/atalk.h b/include/linux/atalk.h index 4d356e168692..40373920ea58 100644 --- a/include/linux/atalk.h +++ b/include/linux/atalk.h @@ -113,10 +113,12 @@ extern void aarp_proto_init(void); /* Inter module exports */ /* Give a device find its atif control structure */ +#if IS_ENABLED(CONFIG_IRDA) || IS_ENABLED(CONFIG_ATALK) static inline struct atalk_iface *atalk_find_dev(struct net_device *dev) { return dev->atalk_ptr; } +#endif extern struct atalk_addr *atalk_find_dev_addr(struct net_device *dev); extern struct net_device *atrtr_get_dev(struct atalk_addr *sa); diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 936dc2c9dca1..dbe6344b727a 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1798,7 +1798,9 @@ struct net_device { #if IS_ENABLED(CONFIG_TIPC) struct tipc_bearer __rcu *tipc_ptr; #endif +#if IS_ENABLED(CONFIG_IRDA) || IS_ENABLED(CONFIG_ATALK) void *atalk_ptr; +#endif struct in_device __rcu *ip_ptr; #if IS_ENABLED(CONFIG_DECNET) struct dn_dev __rcu *dn_ptr; -- cgit v1.2.3 From eb09f1feb8e5999390a6f149307cb88354232680 Mon Sep 17 00:00:00 2001 From: Harshitha Ramamurthy Date: Tue, 23 Jan 2018 08:50:56 -0800 Subject: virtchnl: Add virtchl structures to support queue channels This patch defines new structs in support of the virtchannel message that the VF sends to the PF to create a queue channel specified by the user via tc tool. Signed-off-by: Harshitha Ramamurthy Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher --- include/linux/avf/virtchnl.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'include/linux') diff --git a/include/linux/avf/virtchnl.h b/include/linux/avf/virtchnl.h index 3ce61342fa31..1f652ceecf35 100644 --- a/include/linux/avf/virtchnl.h +++ b/include/linux/avf/virtchnl.h @@ -136,6 +136,8 @@ enum virtchnl_ops { VIRTCHNL_OP_ENABLE_VLAN_STRIPPING = 27, VIRTCHNL_OP_DISABLE_VLAN_STRIPPING = 28, VIRTCHNL_OP_REQUEST_QUEUES = 29, + VIRTCHNL_OP_ENABLE_CHANNELS = 30, + VIRTCHNL_OP_DISABLE_CHANNELS = 31, }; /* This macro is used to generate a compilation error if a structure @@ -244,6 +246,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource); #define VIRTCHNL_VF_OFFLOAD_ENCAP 0X00100000 #define VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM 0X00200000 #define VIRTCHNL_VF_OFFLOAD_RX_ENCAP_CSUM 0X00400000 +#define VIRTCHNL_VF_OFFLOAD_ADQ 0X00800000 #define VF_BASE_MODE_OFFLOADS (VIRTCHNL_VF_OFFLOAD_L2 | \ VIRTCHNL_VF_OFFLOAD_VLAN | \ @@ -496,6 +499,30 @@ struct virtchnl_rss_hena { VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_rss_hena); +/* VIRTCHNL_OP_ENABLE_CHANNELS + * VIRTCHNL_OP_DISABLE_CHANNELS + * VF sends these messages to enable or disable channels based on + * the user specified queue count and queue offset for each traffic class. + * This struct encompasses all the information that the PF needs from + * VF to create a channel. + */ +struct virtchnl_channel_info { + u16 count; /* number of queues in a channel */ + u16 offset; /* queues in a channel start from 'offset' */ + u32 pad; + u64 max_tx_rate; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_channel_info); + +struct virtchnl_tc_info { + u32 num_tc; + u32 pad; + struct virtchnl_channel_info list[1]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_tc_info); + /* VIRTCHNL_OP_EVENT * PF sends this message to inform the VF driver of events that may affect it. * No direct response is expected from the VF, though it may generate other @@ -711,6 +738,19 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, case VIRTCHNL_OP_REQUEST_QUEUES: valid_len = sizeof(struct virtchnl_vf_res_request); break; + case VIRTCHNL_OP_ENABLE_CHANNELS: + valid_len = sizeof(struct virtchnl_tc_info); + if (msglen >= valid_len) { + struct virtchnl_tc_info *vti = + (struct virtchnl_tc_info *)msg; + valid_len += vti->num_tc * + sizeof(struct virtchnl_channel_info); + if (vti->num_tc == 0) + err_msg_format = true; + } + break; + case VIRTCHNL_OP_DISABLE_CHANNELS: + break; /* These are always errors coming from the VF. */ case VIRTCHNL_OP_EVENT: case VIRTCHNL_OP_UNKNOWN: -- cgit v1.2.3 From 0718e560a330599d15fddc37651d693c7a09e49e Mon Sep 17 00:00:00 2001 From: Harshitha Ramamurthy Date: Tue, 23 Jan 2018 08:51:03 -0800 Subject: virtchnl: Add a macro to check the size of a union This patch adds a macro to check if the size of a union is correct. It throws a divide by zero error if the union is not of the correct size. Signed-off-by: Harshitha Ramamurthy Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher --- include/linux/avf/virtchnl.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/avf/virtchnl.h b/include/linux/avf/virtchnl.h index 1f652ceecf35..6fe630ebbf23 100644 --- a/include/linux/avf/virtchnl.h +++ b/include/linux/avf/virtchnl.h @@ -140,13 +140,15 @@ enum virtchnl_ops { VIRTCHNL_OP_DISABLE_CHANNELS = 31, }; -/* This macro is used to generate a compilation error if a structure +/* These macros are used to generate compilation errors if a structure/union * is not exactly the correct length. It gives a divide by zero error if the - * structure is not of the correct size, otherwise it creates an enum that is - * never used. + * structure/union is not of the correct size, otherwise it creates an enum + * that is never used. */ #define VIRTCHNL_CHECK_STRUCT_LEN(n, X) enum virtchnl_static_assert_enum_##X \ { virtchnl_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } +#define VIRTCHNL_CHECK_UNION_LEN(n, X) enum virtchnl_static_asset_enum_##X \ + { virtchnl_static_assert_##X = (n)/((sizeof(union X) == (n)) ? 1 : 0) } /* Virtual channel message descriptor. This overlays the admin queue * descriptor. All other data is passed in external buffers. -- cgit v1.2.3 From 3872c8d44c2e489bcce0c743e808a4135e8da228 Mon Sep 17 00:00:00 2001 From: Harshitha Ramamurthy Date: Tue, 23 Jan 2018 08:51:04 -0800 Subject: virtchnl: Add filter data structures This patch adds infrastructure to send virtchnl messages to the PF to configure filters on the VF. The patch adds a struct called virtchnl_filter which contains information about the fields in the user-specified tc filter. Signed-off-by: Harshitha Ramamurthy Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher --- include/linux/avf/virtchnl.h | 59 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'include/linux') diff --git a/include/linux/avf/virtchnl.h b/include/linux/avf/virtchnl.h index 6fe630ebbf23..b0a7f315bfbe 100644 --- a/include/linux/avf/virtchnl.h +++ b/include/linux/avf/virtchnl.h @@ -138,6 +138,8 @@ enum virtchnl_ops { VIRTCHNL_OP_REQUEST_QUEUES = 29, VIRTCHNL_OP_ENABLE_CHANNELS = 30, VIRTCHNL_OP_DISABLE_CHANNELS = 31, + VIRTCHNL_OP_ADD_CLOUD_FILTER = 32, + VIRTCHNL_OP_DEL_CLOUD_FILTER = 33, }; /* These macros are used to generate compilation errors if a structure/union @@ -525,6 +527,57 @@ struct virtchnl_tc_info { VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_tc_info); +/* VIRTCHNL_ADD_CLOUD_FILTER + * VIRTCHNL_DEL_CLOUD_FILTER + * VF sends these messages to add or delete a cloud filter based on the + * user specified match and action filters. These structures encompass + * all the information that the PF needs from the VF to add/delete a + * cloud filter. + */ + +struct virtchnl_l4_spec { + u8 src_mac[ETH_ALEN]; + u8 dst_mac[ETH_ALEN]; + __be16 vlan_id; + __be16 pad; /* reserved for future use */ + __be32 src_ip[4]; + __be32 dst_ip[4]; + __be16 src_port; + __be16 dst_port; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(52, virtchnl_l4_spec); + +union virtchnl_flow_spec { + struct virtchnl_l4_spec tcp_spec; + u8 buffer[128]; /* reserved for future use */ +}; + +VIRTCHNL_CHECK_UNION_LEN(128, virtchnl_flow_spec); + +enum virtchnl_action { + /* action types */ + VIRTCHNL_ACTION_DROP = 0, + VIRTCHNL_ACTION_TC_REDIRECT, +}; + +enum virtchnl_flow_type { + /* flow types */ + VIRTCHNL_TCP_V4_FLOW = 0, + VIRTCHNL_TCP_V6_FLOW, +}; + +struct virtchnl_filter { + union virtchnl_flow_spec data; + union virtchnl_flow_spec mask; + enum virtchnl_flow_type flow_type; + enum virtchnl_action action; + u32 action_meta; + __u8 field_flags; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(272, virtchnl_filter); + /* VIRTCHNL_OP_EVENT * PF sends this message to inform the VF driver of events that may affect it. * No direct response is expected from the VF, though it may generate other @@ -753,6 +806,12 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, break; case VIRTCHNL_OP_DISABLE_CHANNELS: break; + case VIRTCHNL_OP_ADD_CLOUD_FILTER: + valid_len = sizeof(struct virtchnl_filter); + break; + case VIRTCHNL_OP_DEL_CLOUD_FILTER: + valid_len = sizeof(struct virtchnl_filter); + break; /* These are always errors coming from the VF. */ case VIRTCHNL_OP_EVENT: case VIRTCHNL_OP_UNKNOWN: -- cgit v1.2.3 From a0e37da2a542acb6069b9e10d8aba3be4e5204d7 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 12 Feb 2018 19:32:37 -0600 Subject: ARM: OMAP2+: Cleanup omap_gpio_dev_attr usage The omap_gpio_dev_attr data was used to supply instance-specific data for legacy non-DT devices. The GPIO legacy device support has been cleaned up in commit 14944934f8ac ("ARM: OMAP2+: Remove legacy gpio code") a while ago and this data is therefore no longer needed. So, cleanup the structure and all the associated data in various hwmod data files. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 13 +------------ arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 1 - arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 9 --------- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 13 ------------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 4 ---- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 13 ------------- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 15 --------------- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 15 --------------- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 8 -------- arch/arm/mach-omap2/omap_hwmod_common_data.h | 1 - include/linux/platform_data/gpio-omap.h | 5 ----- 13 files changed, 1 insertion(+), 99 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 013b26b305d2..1f696bec9962 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -134,7 +134,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { }, }, .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, }; /* dma attributes */ diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 4f0a1d4dd7fa..e1a6ebe3a8ac 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -10,9 +10,8 @@ */ #include - -#include #include + #include #include @@ -570,12 +569,6 @@ struct omap_hwmod omap2xxx_dss_venc_hwmod = { .flags = HWMOD_NO_IDLEST, }; -/* gpio dev_attr */ -struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = false, -}; - /* gpio1 */ struct omap_hwmod omap2xxx_gpio1_hwmod = { .name = "gpio1", @@ -589,7 +582,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = { }, }, .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, }; /* gpio2 */ @@ -605,7 +597,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = { }, }, .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, }; /* gpio3 */ @@ -621,7 +612,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = { }, }, .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, }; /* gpio4 */ @@ -637,7 +627,6 @@ struct omap_hwmod omap2xxx_gpio4_hwmod = { }, }, .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &omap2xxx_gpio_dev_attr, }; /* mcspi1 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index 434bd1a77229..bbda6887388b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -139,7 +139,6 @@ extern struct omap_hwmod_class am33xx_epwmss_hwmod_class; extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class; extern struct omap_hwmod_class am33xx_spi_hwmod_class; -extern struct omap_gpio_dev_attr gpio_dev_attr; extern struct omap2_mcspi_dev_attr mcspi_attrib; void omap_hwmod_am33xx_reg(void); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 4161e369d216..db8cd550a5bd 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -16,7 +16,6 @@ #include -#include #include #include #include "omap_hwmod.h" @@ -539,11 +538,6 @@ struct omap_hwmod_class am33xx_gpio_hwmod_class = { .rev = 2, }; -struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, -}; - /* gpio1 */ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, @@ -562,7 +556,6 @@ struct omap_hwmod am33xx_gpio1_hwmod = { }, .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio2 */ @@ -583,7 +576,6 @@ struct omap_hwmod am33xx_gpio2_hwmod = { }, .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio3 */ @@ -604,7 +596,6 @@ struct omap_hwmod am33xx_gpio3_hwmod = { }, .opt_clks = gpio3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpmc */ diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 4d16b15bb0cf..232d03045c6d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -17,7 +17,6 @@ #include #include "omap_hwmod.h" -#include #include #include "omap_hwmod_common_data.h" @@ -252,7 +251,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = { }, .opt_clks = gpio0_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* lcdc */ diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 1a2f2242e31b..c7ff7560f47a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,7 +17,6 @@ #include #include -#include #include #include @@ -769,12 +768,6 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { .rev = 1, }; -/* gpio_dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, -}; - /* gpio1 */ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbck", }, @@ -794,7 +787,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = { }, }, .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, }; /* gpio2 */ @@ -816,7 +808,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = { }, }, .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, }; /* gpio3 */ @@ -838,7 +829,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = { }, }, .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, }; /* gpio4 */ @@ -860,7 +850,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { }, }, .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, }; /* gpio5 */ @@ -883,7 +872,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { }, }, .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, }; /* gpio6 */ @@ -906,7 +894,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { }, }, .class = &omap3xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, }; /* dma attributes */ diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index afbce1f6f641..4f31ce899869 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include "omap_hwmod.h" #include "omap_hwmod_33xx_43xx_common_data.h" @@ -107,7 +106,6 @@ static struct omap_hwmod am43xx_gpio0_hwmod = { }, .opt_clks = gpio0_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), - .dev_attr = &gpio_dev_attr, }; static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = { @@ -288,7 +286,6 @@ static struct omap_hwmod am43xx_gpio4_hwmod = { }, .opt_clks = gpio4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), - .dev_attr = &gpio_dev_attr, }; static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { @@ -309,7 +306,6 @@ static struct omap_hwmod am43xx_gpio5_hwmod = { }, .opt_clks = gpio5_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), - .dev_attr = &gpio_dev_attr, }; static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index a1901c22a0f0..3afb7333b800 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -21,7 +21,6 @@ */ #include -#include #include #include #include @@ -1083,12 +1082,6 @@ static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { .rev = 2, }; -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, -}; - /* gpio1 */ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, @@ -1108,7 +1101,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { }, .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio2 */ @@ -1131,7 +1123,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { }, .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio3 */ @@ -1154,7 +1145,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { }, .opt_clks = gpio3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio4 */ @@ -1177,7 +1167,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { }, .opt_clks = gpio4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio5 */ @@ -1200,7 +1189,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { }, .opt_clks = gpio5_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio6 */ @@ -1223,7 +1211,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { }, .opt_clks = gpio6_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 988e7eaa1330..593b4bc92d99 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -18,7 +18,6 @@ */ #include -#include #include #include #include @@ -627,12 +626,6 @@ static struct omap_hwmod_class omap54xx_gpio_hwmod_class = { .rev = 2, }; -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, -}; - /* gpio1 */ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, @@ -652,7 +645,6 @@ static struct omap_hwmod omap54xx_gpio1_hwmod = { }, .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio2 */ @@ -675,7 +667,6 @@ static struct omap_hwmod omap54xx_gpio2_hwmod = { }, .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio3 */ @@ -698,7 +689,6 @@ static struct omap_hwmod omap54xx_gpio3_hwmod = { }, .opt_clks = gpio3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio4 */ @@ -721,7 +711,6 @@ static struct omap_hwmod omap54xx_gpio4_hwmod = { }, .opt_clks = gpio4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio5 */ @@ -744,7 +733,6 @@ static struct omap_hwmod omap54xx_gpio5_hwmod = { }, .opt_clks = gpio5_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio6 */ @@ -767,7 +755,6 @@ static struct omap_hwmod omap54xx_gpio6_hwmod = { }, .opt_clks = gpio6_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio7 */ @@ -790,7 +777,6 @@ static struct omap_hwmod omap54xx_gpio7_hwmod = { }, .opt_clks = gpio7_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio8 */ @@ -813,7 +799,6 @@ static struct omap_hwmod omap54xx_gpio8_hwmod = { }, .opt_clks = gpio8_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 4c2a05b1bd19..523e89498fd3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -18,7 +18,6 @@ */ #include -#include #include #include #include @@ -818,12 +817,6 @@ static struct omap_hwmod_class dra7xx_gpio_hwmod_class = { .rev = 2, }; -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, -}; - /* gpio1 */ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, @@ -844,7 +837,6 @@ static struct omap_hwmod dra7xx_gpio1_hwmod = { }, .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio2 */ @@ -867,7 +859,6 @@ static struct omap_hwmod dra7xx_gpio2_hwmod = { }, .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio3 */ @@ -890,7 +881,6 @@ static struct omap_hwmod dra7xx_gpio3_hwmod = { }, .opt_clks = gpio3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio4 */ @@ -913,7 +903,6 @@ static struct omap_hwmod dra7xx_gpio4_hwmod = { }, .opt_clks = gpio4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio5 */ @@ -936,7 +925,6 @@ static struct omap_hwmod dra7xx_gpio5_hwmod = { }, .opt_clks = gpio5_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio6 */ @@ -959,7 +947,6 @@ static struct omap_hwmod dra7xx_gpio6_hwmod = { }, .opt_clks = gpio6_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio7 */ @@ -982,7 +969,6 @@ static struct omap_hwmod dra7xx_gpio7_hwmod = { }, .opt_clks = gpio7_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* gpio8 */ @@ -1005,7 +991,6 @@ static struct omap_hwmod dra7xx_gpio8_hwmod = { }, .opt_clks = gpio8_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), - .dev_attr = &gpio_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 64c5a1299003..d1f4dc47a3ae 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -17,7 +17,6 @@ #include -#include #include #include #include @@ -490,11 +489,6 @@ static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { .rev = 2, }; -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, -}; - static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "sysclk18_ck" }, }; @@ -512,7 +506,6 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = { }, .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), - .dev_attr = &gpio_dev_attr, }; static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { @@ -539,7 +532,6 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = { }, .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .dev_attr = &gpio_dev_attr, }; static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 29a52df2de26..56dbaca9a728 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -19,7 +19,6 @@ #include "display.h" /* Common IP block data across OMAP2xxx */ -extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; extern struct omap_hwmod omap2xxx_l3_main_hwmod; extern struct omap_hwmod omap2xxx_l4_core_hwmod; extern struct omap_hwmod omap2xxx_l4_wkup_hwmod; diff --git a/include/linux/platform_data/gpio-omap.h b/include/linux/platform_data/gpio-omap.h index cb2618147c34..8612855691b2 100644 --- a/include/linux/platform_data/gpio-omap.h +++ b/include/linux/platform_data/gpio-omap.h @@ -157,11 +157,6 @@ #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) -struct omap_gpio_dev_attr { - int bank_width; /* GPIO bank width */ - bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ -}; - struct omap_gpio_reg_offs { u16 revision; u16 direction; -- cgit v1.2.3 From 1cddc364584e76c16354d34326c671aac2a23e4f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 12 Feb 2018 19:32:40 -0600 Subject: ARM: OMAP2+: Cleanup omap2_spi_dev_attr and other legacy data The omap2_spi_dev_attr data was used to supply instance-specific data for legacy non-DT devices. The SPI legacy device support including the usage of the hwmod class revision data has been dropped in commit 6f3ab009a178 ("ARM: OMAP2+: Remove unused legacy code for device init") and this data is therefore no longer needed. So, cleanup the structure and all the associated data in various hwmod data files. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_2430_data.c | 6 ----- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 13 ----------- .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 2 -- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 7 ------ arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 26 ---------------------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 4 ---- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 22 ------------------ arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 26 ---------------------- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 26 ---------------------- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 7 ------ include/linux/platform_data/spi-omap2-mcspi.h | 8 ------- 13 files changed, 150 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 9f16b1b8d882..fe66cf247874 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -14,7 +14,6 @@ */ #include -#include #include #include "omap_hwmod.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 409f0e634707..cdbd09b21168 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include "omap_hwmod.h" @@ -157,10 +156,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { }; /* mcspi3 */ -static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap2430_mcspi3_hwmod = { .name = "mcspi3", .main_clk = "mcspi3_fck", @@ -172,7 +167,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { }, }, .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi3_dev_attr, }; /* usbhsotg */ diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 00a5ae5df82d..5345919a81f8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -12,8 +12,6 @@ #include #include -#include - #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm-regbits-24xx.h" @@ -159,7 +157,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = { struct omap_hwmod_class omap2xxx_mcspi_class = { .name = "mcspi", .sysc = &omap2xxx_mcspi_sysc, - .rev = OMAP2_MCSPI_REV, }; /* @@ -593,10 +590,6 @@ struct omap_hwmod omap2xxx_gpio4_hwmod = { }; /* mcspi1 */ -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - struct omap_hwmod omap2xxx_mcspi1_hwmod = { .name = "mcspi1", .main_clk = "mcspi1_fck", @@ -608,14 +601,9 @@ struct omap_hwmod omap2xxx_mcspi1_hwmod = { }, }, .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - struct omap_hwmod omap2xxx_mcspi2_hwmod = { .name = "mcspi2", .main_clk = "mcspi2_fck", @@ -627,7 +615,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { }, }, .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, }; static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index bbda6887388b..6f81d7a4fec1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -139,8 +139,6 @@ extern struct omap_hwmod_class am33xx_epwmss_hwmod_class; extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class; extern struct omap_hwmod_class am33xx_spi_hwmod_class; -extern struct omap2_mcspi_dev_attr mcspi_attrib; - void omap_hwmod_am33xx_reg(void); void omap_hwmod_am43xx_reg(void); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index b1118b1124d9..5efe91c6e95b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -17,7 +17,6 @@ #include #include -#include #include "omap_hwmod.h" #include "i2c.h" #include "wd_timer.h" @@ -879,13 +878,9 @@ static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { struct omap_hwmod_class am33xx_spi_hwmod_class = { .name = "mcspi", .sysc = &am33xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* spi0 */ -struct omap2_mcspi_dev_attr mcspi_attrib = { - .num_chipselect = 2, -}; struct omap_hwmod am33xx_spi0_hwmod = { .name = "spi0", .class = &am33xx_spi_hwmod_class, @@ -896,7 +891,6 @@ struct omap_hwmod am33xx_spi0_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; /* spi1 */ @@ -910,7 +904,6 @@ struct omap_hwmod am33xx_spi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 232d03045c6d..53e1ac3724f2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -17,8 +17,6 @@ #include #include "omap_hwmod.h" -#include - #include "omap_hwmod_common_data.h" #include "control.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 7515119cab64..23008cb35140 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -23,7 +23,6 @@ #include "l3_3xxx.h" #include "l4_3xxx.h" #include -#include #include "soc.h" #include "omap_hwmod.h" @@ -1189,14 +1188,9 @@ static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { static struct omap_hwmod_class omap34xx_mcspi_class = { .name = "mcspi", .sysc = &omap34xx_mcspi_sysc, - .rev = OMAP3_MCSPI_REV, }; /* mcspi1 */ -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod omap34xx_mcspi1 = { .name = "mcspi1", .main_clk = "mcspi1_fck", @@ -1208,14 +1202,9 @@ static struct omap_hwmod omap34xx_mcspi1 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap34xx_mcspi2 = { .name = "mcspi2", .main_clk = "mcspi2_fck", @@ -1227,16 +1216,9 @@ static struct omap_hwmod omap34xx_mcspi2 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, }; /* mcspi3 */ - - -static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap34xx_mcspi3 = { .name = "mcspi3", .main_clk = "mcspi3_fck", @@ -1248,16 +1230,9 @@ static struct omap_hwmod omap34xx_mcspi3 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi3_dev_attr, }; /* mcspi4 */ - - -static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod omap34xx_mcspi4 = { .name = "mcspi4", .main_clk = "mcspi4_fck", @@ -1269,7 +1244,6 @@ static struct omap_hwmod omap34xx_mcspi4 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi4_dev_attr, }; /* usbhsotg */ diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 4f31ce899869..5f73b730d4fc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include "omap_hwmod.h" #include "omap_hwmod_33xx_43xx_common_data.h" #include "prcm43xx.h" @@ -237,7 +236,6 @@ static struct omap_hwmod am43xx_spi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; static struct omap_hwmod am43xx_spi3_hwmod = { @@ -251,7 +249,6 @@ static struct omap_hwmod am43xx_spi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; static struct omap_hwmod am43xx_spi4_hwmod = { @@ -265,7 +262,6 @@ static struct omap_hwmod am43xx_spi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 70eb826d5f65..5a313483b3b8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -27,7 +27,6 @@ #include -#include #include #include "omap_hwmod.h" @@ -1838,14 +1837,9 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { .name = "mcspi", .sysc = &omap44xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* mcspi1 */ -static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod omap44xx_mcspi1_hwmod = { .name = "mcspi1", .class = &omap44xx_mcspi_hwmod_class, @@ -1858,14 +1852,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap44xx_mcspi2_hwmod = { .name = "mcspi2", .class = &omap44xx_mcspi_hwmod_class, @@ -1878,14 +1867,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi2_dev_attr, }; /* mcspi3 */ -static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap44xx_mcspi3_hwmod = { .name = "mcspi3", .class = &omap44xx_mcspi_hwmod_class, @@ -1898,14 +1882,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi3_dev_attr, }; /* mcspi4 */ -static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod omap44xx_mcspi4_hwmod = { .name = "mcspi4", .class = &omap44xx_mcspi_hwmod_class, @@ -1918,7 +1897,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi4_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 2275789854dc..f901b17bd73a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include #include "omap_hwmod.h" @@ -1123,15 +1122,9 @@ static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = { static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = { .name = "mcspi", .sysc = &omap54xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* mcspi1 */ -/* mcspi1 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod omap54xx_mcspi1_hwmod = { .name = "mcspi1", .class = &omap54xx_mcspi_hwmod_class, @@ -1144,15 +1137,9 @@ static struct omap_hwmod omap54xx_mcspi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi1_dev_attr, }; /* mcspi2 */ -/* mcspi2 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap54xx_mcspi2_hwmod = { .name = "mcspi2", .class = &omap54xx_mcspi_hwmod_class, @@ -1165,15 +1152,9 @@ static struct omap_hwmod omap54xx_mcspi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi2_dev_attr, }; /* mcspi3 */ -/* mcspi3 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap54xx_mcspi3_hwmod = { .name = "mcspi3", .class = &omap54xx_mcspi_hwmod_class, @@ -1186,15 +1167,9 @@ static struct omap_hwmod omap54xx_mcspi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi3_dev_attr, }; /* mcspi4 */ -/* mcspi4 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod omap54xx_mcspi4_hwmod = { .name = "mcspi4", .class = &omap54xx_mcspi_hwmod_class, @@ -1207,7 +1182,6 @@ static struct omap_hwmod omap54xx_mcspi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi4_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index d0f1fd65d01f..d66dc806425d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include #include "omap_hwmod.h" @@ -1375,15 +1374,9 @@ static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = { static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = { .name = "mcspi", .sysc = &dra7xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* mcspi1 */ -/* mcspi1 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod dra7xx_mcspi1_hwmod = { .name = "mcspi1", .class = &dra7xx_mcspi_hwmod_class, @@ -1396,15 +1389,9 @@ static struct omap_hwmod dra7xx_mcspi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi1_dev_attr, }; /* mcspi2 */ -/* mcspi2 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod dra7xx_mcspi2_hwmod = { .name = "mcspi2", .class = &dra7xx_mcspi_hwmod_class, @@ -1417,15 +1404,9 @@ static struct omap_hwmod dra7xx_mcspi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi2_dev_attr, }; /* mcspi3 */ -/* mcspi3 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod dra7xx_mcspi3_hwmod = { .name = "mcspi3", .class = &dra7xx_mcspi_hwmod_class, @@ -1438,15 +1419,9 @@ static struct omap_hwmod dra7xx_mcspi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi3_dev_attr, }; /* mcspi4 */ -/* mcspi4 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod dra7xx_mcspi4_hwmod = { .name = "mcspi4", .class = &dra7xx_mcspi_hwmod_class, @@ -1459,7 +1434,6 @@ static struct omap_hwmod dra7xx_mcspi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi4_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 333a896c0c9a..686655f884c1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -18,7 +18,6 @@ #include #include -#include #include "omap_hwmod_common_data.h" #include "cm81xx.h" @@ -1118,11 +1117,6 @@ static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { static struct omap_hwmod_class dm816x_mcspi_class = { .name = "mcspi", .sysc = &dm816x_mcspi_sysc, - .rev = OMAP3_MCSPI_REV, -}; - -static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { - .num_chipselect = 4, }; static struct omap_hwmod dm81xx_mcspi1_hwmod = { @@ -1136,7 +1130,6 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = { }, }, .class = &dm816x_mcspi_class, - .dev_attr = &dm816x_mcspi1_dev_attr, }; static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { diff --git a/include/linux/platform_data/spi-omap2-mcspi.h b/include/linux/platform_data/spi-omap2-mcspi.h index 13c83a25958a..0bf9fddb8306 100644 --- a/include/linux/platform_data/spi-omap2-mcspi.h +++ b/include/linux/platform_data/spi-omap2-mcspi.h @@ -2,10 +2,6 @@ #ifndef _OMAP2_MCSPI_H #define _OMAP2_MCSPI_H -#define OMAP2_MCSPI_REV 0 -#define OMAP3_MCSPI_REV 1 -#define OMAP4_MCSPI_REV 2 - #define OMAP4_MCSPI_REG_OFFSET 0x100 #define MCSPI_PINDIR_D0_IN_D1_OUT 0 @@ -17,10 +13,6 @@ struct omap2_mcspi_platform_config { unsigned int pin_dir:1; }; -struct omap2_mcspi_dev_attr { - unsigned short num_chipselect; -}; - struct omap2_mcspi_device_config { unsigned turbo_mode:1; -- cgit v1.2.3 From 0693036ca800ab471e8f28caeb3a9ac4d77af810 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 12 Feb 2018 19:32:41 -0600 Subject: ARM: OMAP2+: Cleanup omap_mcbsp_dev_attr and other legacy data The omap_mcbsp_dev_attr data was used to supply instance-specific data for legacy non-DT devices. The legacy McBSP device support including the usage of the hwmod class revision data has been dropped in commit 48f6693790aa ("ARM: OMAP2+: Remove unused legacy code for McBSP") and this data is therefore no longer needed. So, cleanup the structure and all the associated data in various hwmod data files. Cc: Peter Ujfalusi Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 21 --------------------- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 3 --- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 1 - include/linux/platform_data/asoc-ti-mcbsp.h | 12 ------------ 6 files changed, 41 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index cdbd09b21168..74eefd30518c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -14,7 +14,6 @@ */ #include -#include #include #include @@ -223,7 +222,6 @@ static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap2430_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE2, }; static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 23008cb35140..23336b6c7125 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -22,7 +22,6 @@ #include #include "l3_3xxx.h" #include "l4_3xxx.h" -#include #include "soc.h" #include "omap_hwmod.h" @@ -896,7 +895,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap3xxx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE3, }; /* McBSP functional clock mapping */ @@ -911,7 +909,6 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { }; /* mcbsp1 */ - static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap3xxx_mcbsp_hwmod_class, @@ -928,11 +925,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { }; /* mcbsp2 */ - -static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { - .sidetone = "mcbsp2_sidetone", -}; - static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap3xxx_mcbsp_hwmod_class, @@ -946,15 +938,9 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { }, .opt_clks = mcbsp234_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), - .dev_attr = &omap34xx_mcbsp2_dev_attr, }; /* mcbsp3 */ - -static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { - .sidetone = "mcbsp3_sidetone", -}; - static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap3xxx_mcbsp_hwmod_class, @@ -968,12 +954,9 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { }, .opt_clks = mcbsp234_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), - .dev_attr = &omap34xx_mcbsp3_dev_attr, }; /* mcbsp4 */ - - static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap3xxx_mcbsp_hwmod_class, @@ -990,8 +973,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { }; /* mcbsp5 */ - - static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap3xxx_mcbsp_hwmod_class, @@ -1020,7 +1001,6 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { }; /* mcbsp2_sidetone */ - static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { .name = "mcbsp2_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, @@ -1029,7 +1009,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { }; /* mcbsp3_sidetone */ - static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { .name = "mcbsp3_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 5a313483b3b8..e4f8ae9cd637 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -27,8 +27,6 @@ #include -#include - #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm1_44xx.h" @@ -1679,7 +1677,6 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap44xx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE4, }; /* mcbsp1 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index f901b17bd73a..c72cd84b07ec 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" @@ -985,7 +984,6 @@ static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = { static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap54xx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE4, }; /* mcbsp1 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index d66dc806425d..62352d1e6361 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" diff --git a/include/linux/platform_data/asoc-ti-mcbsp.h b/include/linux/platform_data/asoc-ti-mcbsp.h index e684543254f3..e319d0a2ec82 100644 --- a/include/linux/platform_data/asoc-ti-mcbsp.h +++ b/include/linux/platform_data/asoc-ti-mcbsp.h @@ -25,10 +25,6 @@ #include #include -#define MCBSP_CONFIG_TYPE2 0x2 -#define MCBSP_CONFIG_TYPE3 0x3 -#define MCBSP_CONFIG_TYPE4 0x4 - /* Platform specific configuration */ struct omap_mcbsp_ops { void (*request)(unsigned int); @@ -47,14 +43,6 @@ struct omap_mcbsp_platform_data { int (*force_ick_on)(struct clk *clk, bool force_on); }; -/** - * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod - * @sidetone: name of the sidetone device - */ -struct omap_mcbsp_dev_attr { - const char *sidetone; -}; - void omap3_mcbsp_init_pdata_callback(struct omap_mcbsp_platform_data *pdata); #endif -- cgit v1.2.3 From 052fddfb3c4e5f3d413d3f6b8dffe1b7192026af Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 14 Feb 2018 01:07:42 +0100 Subject: net: ptp: Add stub for ptp_classify_raw() When NET_PTP_CLASSIFY is disabled, a stub function is required in order that the drivers compile. Signed-off-by: Andrew Lunn Acked-by: Richard Cochran Signed-off-by: David S. Miller --- include/linux/ptp_classify.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux') diff --git a/include/linux/ptp_classify.h b/include/linux/ptp_classify.h index a079656b614c..059242030631 100644 --- a/include/linux/ptp_classify.h +++ b/include/linux/ptp_classify.h @@ -75,5 +75,9 @@ void __init ptp_classifier_init(void); static inline void ptp_classifier_init(void) { } +static inline unsigned int ptp_classify_raw(struct sk_buff *skb) +{ + return PTP_CLASS_NONE; +} #endif #endif /* _PTP_CLASSIFY_H_ */ -- cgit v1.2.3 From 02d92f7903647119e125b24f5470f96cee0d4b4b Mon Sep 17 00:00:00 2001 From: Saeed Mahameed Date: Fri, 19 Jan 2018 16:13:01 -0800 Subject: net/mlx5: CQ Database per EQ Before this patch the driver had one CQ database protected via one spinlock, this spinlock is meant to synchronize between CQ adding/removing and CQ IRQ interrupt handling. On a system with large number of CPUs and on a work load that requires lots of interrupts, this global spinlock becomes a very nasty hotspot and introduces a contention between the active cores, which will significantly hurt performance and becomes a bottleneck that prevents seamless cpu scaling. To solve this we simply move the CQ database and its spinlock to be per EQ (IRQ), thus per core. Tested with: system: 2 sockets, 14 cores per socket, hyperthreading, 2x14x2=56 cores netperf command: ./super_netperf 200 -P 0 -t TCP_RR -H -l 30 -- -r 300,300 -o -s 1M,1M -S 1M,1M WITHOUT THIS PATCH: Average: CPU %usr %nice %sys %iowait %irq %soft %steal %guest %gnice %idle Average: all 4.32 0.00 36.15 0.09 0.00 34.02 0.00 0.00 0.00 25.41 Samples: 2M of event 'cycles:pp', Event count (approx.): 1554616897271 Overhead Command Shared Object Symbol + 14.28% swapper [kernel.vmlinux] [k] intel_idle + 12.25% swapper [kernel.vmlinux] [k] queued_spin_lock_slowpath + 10.29% netserver [kernel.vmlinux] [k] queued_spin_lock_slowpath + 1.32% netserver [kernel.vmlinux] [k] mlx5e_xmit WITH THIS PATCH: Average: CPU %usr %nice %sys %iowait %irq %soft %steal %guest %gnice %idle Average: all 4.27 0.00 34.31 0.01 0.00 18.71 0.00 0.00 0.00 42.69 Samples: 2M of event 'cycles:pp', Event count (approx.): 1498132937483 Overhead Command Shared Object Symbol + 23.33% swapper [kernel.vmlinux] [k] intel_idle + 1.69% netserver [kernel.vmlinux] [k] mlx5e_xmit Tested-by: Song Liu Signed-off-by: Saeed Mahameed Reviewed-by: Gal Pressman --- drivers/net/ethernet/mellanox/mlx5/core/cq.c | 69 +++++++++++++++----------- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 10 +++- drivers/net/ethernet/mellanox/mlx5/core/main.c | 8 +-- include/linux/mlx5/cq.h | 3 +- include/linux/mlx5/driver.h | 22 ++++---- 5 files changed, 62 insertions(+), 50 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cq.c b/drivers/net/ethernet/mellanox/mlx5/core/cq.c index 1016e05c7ec7..dfbeeaa43276 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cq.c @@ -86,10 +86,10 @@ static void mlx5_add_cq_to_tasklet(struct mlx5_core_cq *cq) spin_unlock_irqrestore(&tasklet_ctx->lock, flags); } -void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn) +void mlx5_cq_completion(struct mlx5_eq *eq, u32 cqn) { + struct mlx5_cq_table *table = &eq->cq_table; struct mlx5_core_cq *cq; - struct mlx5_cq_table *table = &dev->priv.cq_table; spin_lock(&table->lock); cq = radix_tree_lookup(&table->tree, cqn); @@ -98,7 +98,7 @@ void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn) spin_unlock(&table->lock); if (!cq) { - mlx5_core_warn(dev, "Completion event for bogus CQ 0x%x\n", cqn); + mlx5_core_warn(eq->dev, "Completion event for bogus CQ 0x%x\n", cqn); return; } @@ -110,9 +110,9 @@ void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn) complete(&cq->free); } -void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type) +void mlx5_cq_event(struct mlx5_eq *eq, u32 cqn, int event_type) { - struct mlx5_cq_table *table = &dev->priv.cq_table; + struct mlx5_cq_table *table = &eq->cq_table; struct mlx5_core_cq *cq; spin_lock(&table->lock); @@ -124,7 +124,7 @@ void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type) spin_unlock(&table->lock); if (!cq) { - mlx5_core_warn(dev, "Async event for bogus CQ 0x%x\n", cqn); + mlx5_core_warn(eq->dev, "Async event for bogus CQ 0x%x\n", cqn); return; } @@ -137,19 +137,22 @@ void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type) int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, u32 *in, int inlen) { - struct mlx5_cq_table *table = &dev->priv.cq_table; u32 out[MLX5_ST_SZ_DW(create_cq_out)]; u32 din[MLX5_ST_SZ_DW(destroy_cq_in)]; u32 dout[MLX5_ST_SZ_DW(destroy_cq_out)]; int eqn = MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), c_eqn); - struct mlx5_eq *eq; + struct mlx5_eq *eq, *async_eq; + struct mlx5_cq_table *table; int err; + async_eq = &dev->priv.eq_table.async_eq; eq = mlx5_eqn2eq(dev, eqn); if (IS_ERR(eq)) return PTR_ERR(eq); + table = &eq->cq_table; + memset(out, 0, sizeof(out)); MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); @@ -159,6 +162,7 @@ int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, cq->cqn = MLX5_GET(create_cq_out, out, cqn); cq->cons_index = 0; cq->arm_sn = 0; + cq->eq = eq; refcount_set(&cq->refcount, 1); init_completion(&cq->free); if (!cq->comp) @@ -167,12 +171,20 @@ int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, cq->tasklet_ctx.priv = &eq->tasklet_ctx; INIT_LIST_HEAD(&cq->tasklet_ctx.list); + /* Add to comp EQ CQ tree to recv comp events */ spin_lock_irq(&table->lock); err = radix_tree_insert(&table->tree, cq->cqn, cq); spin_unlock_irq(&table->lock); if (err) goto err_cmd; + /* Add to async EQ CQ tree to recv Async events */ + spin_lock_irq(&async_eq->cq_table.lock); + err = radix_tree_insert(&async_eq->cq_table.tree, cq->cqn, cq); + spin_unlock_irq(&async_eq->cq_table.lock); + if (err) + goto err_cq_table; + cq->pid = current->pid; err = mlx5_debug_cq_add(dev, cq); if (err) @@ -183,6 +195,10 @@ int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, return 0; +err_cq_table: + spin_lock_irq(&table->lock); + radix_tree_delete(&table->tree, cq->cqn); + spin_unlock_irq(&table->lock); err_cmd: memset(din, 0, sizeof(din)); memset(dout, 0, sizeof(dout)); @@ -195,21 +211,34 @@ EXPORT_SYMBOL(mlx5_core_create_cq); int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq) { - struct mlx5_cq_table *table = &dev->priv.cq_table; + struct mlx5_cq_table *asyn_eq_cq_table = &dev->priv.eq_table.async_eq.cq_table; + struct mlx5_cq_table *table = &cq->eq->cq_table; u32 out[MLX5_ST_SZ_DW(destroy_cq_out)] = {0}; u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {0}; struct mlx5_core_cq *tmp; int err; + spin_lock_irq(&asyn_eq_cq_table->lock); + tmp = radix_tree_delete(&asyn_eq_cq_table->tree, cq->cqn); + spin_unlock_irq(&asyn_eq_cq_table->lock); + if (!tmp) { + mlx5_core_warn(dev, "cq 0x%x not found in async eq cq tree\n", cq->cqn); + return -EINVAL; + } + if (tmp != cq) { + mlx5_core_warn(dev, "corruption on cqn 0x%x in async eq cq tree\n", cq->cqn); + return -EINVAL; + } + spin_lock_irq(&table->lock); tmp = radix_tree_delete(&table->tree, cq->cqn); spin_unlock_irq(&table->lock); if (!tmp) { - mlx5_core_warn(dev, "cq 0x%x not found in tree\n", cq->cqn); + mlx5_core_warn(dev, "cq 0x%x not found in comp eq cq tree\n", cq->cqn); return -EINVAL; } if (tmp != cq) { - mlx5_core_warn(dev, "corruption on srqn 0x%x\n", cq->cqn); + mlx5_core_warn(dev, "corruption on cqn 0x%x in comp eq cq tree\n", cq->cqn); return -EINVAL; } @@ -270,21 +299,3 @@ int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev, return mlx5_core_modify_cq(dev, cq, in, sizeof(in)); } EXPORT_SYMBOL(mlx5_core_modify_cq_moderation); - -int mlx5_init_cq_table(struct mlx5_core_dev *dev) -{ - struct mlx5_cq_table *table = &dev->priv.cq_table; - int err; - - memset(table, 0, sizeof(*table)); - spin_lock_init(&table->lock); - INIT_RADIX_TREE(&table->tree, GFP_ATOMIC); - err = mlx5_cq_debugfs_init(dev); - - return err; -} - -void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev) -{ - mlx5_cq_debugfs_cleanup(dev); -} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 25106e996a96..328403ebf2f5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -415,7 +415,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) switch (eqe->type) { case MLX5_EVENT_TYPE_COMP: cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; - mlx5_cq_completion(dev, cqn); + mlx5_cq_completion(eq, cqn); break; case MLX5_EVENT_TYPE_DCT_DRAINED: rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; @@ -472,7 +472,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrome 0x%x\n", cqn, eqe->data.cq_err.syndrome); - mlx5_cq_event(dev, cqn, eqe->type); + mlx5_cq_event(eq, cqn, eqe->type); break; case MLX5_EVENT_TYPE_PAGE_REQUEST: @@ -567,6 +567,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, int nent, u64 mask, const char *name, enum mlx5_eq_type type) { + struct mlx5_cq_table *cq_table = &eq->cq_table; u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; struct mlx5_priv *priv = &dev->priv; irq_handler_t handler; @@ -576,6 +577,11 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, u32 *in; int err; + /* Init CQ table */ + memset(cq_table, 0, sizeof(*cq_table)); + spin_lock_init(&cq_table->lock); + INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC); + eq->type = type; eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); eq->cons_index = 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 2ef641c91c26..8cc22bf80c87 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -942,9 +942,9 @@ static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) goto out; } - err = mlx5_init_cq_table(dev); + err = mlx5_cq_debugfs_init(dev); if (err) { - dev_err(&pdev->dev, "failed to initialize cq table\n"); + dev_err(&pdev->dev, "failed to initialize cq debugfs\n"); goto err_eq_cleanup; } @@ -1002,7 +1002,7 @@ err_tables_cleanup: mlx5_cleanup_mkey_table(dev); mlx5_cleanup_srq_table(dev); mlx5_cleanup_qp_table(dev); - mlx5_cleanup_cq_table(dev); + mlx5_cq_debugfs_cleanup(dev); err_eq_cleanup: mlx5_eq_cleanup(dev); @@ -1023,7 +1023,7 @@ static void mlx5_cleanup_once(struct mlx5_core_dev *dev) mlx5_cleanup_mkey_table(dev); mlx5_cleanup_srq_table(dev); mlx5_cleanup_qp_table(dev); - mlx5_cleanup_cq_table(dev); + mlx5_cq_debugfs_cleanup(dev); mlx5_eq_cleanup(dev); } diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h index 48c181a2acc9..06ba425a6ad7 100644 --- a/include/linux/mlx5/cq.h +++ b/include/linux/mlx5/cq.h @@ -60,6 +60,7 @@ struct mlx5_core_cq { } tasklet_ctx; int reset_notify_added; struct list_head reset_notify; + struct mlx5_eq *eq; }; @@ -171,8 +172,6 @@ static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd, mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, NULL); } -int mlx5_init_cq_table(struct mlx5_core_dev *dev); -void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev); int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, u32 *in, int inlen); int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 6ed79a8a8318..96e003db2bcd 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -375,8 +375,15 @@ struct mlx5_eq_pagefault { mempool_t *pool; }; +struct mlx5_cq_table { + /* protect radix tree */ + spinlock_t lock; + struct radix_tree_root tree; +}; + struct mlx5_eq { struct mlx5_core_dev *dev; + struct mlx5_cq_table cq_table; __be32 __iomem *doorbell; u32 cons_index; struct mlx5_buf buf; @@ -526,13 +533,6 @@ struct mlx5_core_health { struct delayed_work recover_work; }; -struct mlx5_cq_table { - /* protect radix tree - */ - spinlock_t lock; - struct radix_tree_root tree; -}; - struct mlx5_qp_table { /* protect radix tree */ @@ -654,10 +654,6 @@ struct mlx5_priv { struct dentry *cmdif_debugfs; /* end: qp staff */ - /* start: cq staff */ - struct mlx5_cq_table cq_table; - /* end: cq staff */ - /* start: mkey staff */ struct mlx5_mkey_table mkey_table; /* end: mkey staff */ @@ -1053,12 +1049,12 @@ int mlx5_eq_init(struct mlx5_core_dev *dev); void mlx5_eq_cleanup(struct mlx5_core_dev *dev); void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); -void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); +void mlx5_cq_completion(struct mlx5_eq *eq, u32 cqn); void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); -void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); +void mlx5_cq_event(struct mlx5_eq *eq, u32 cqn, int event_type); int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, int nent, u64 mask, const char *name, enum mlx5_eq_type type); -- cgit v1.2.3 From f105b45bf77ced96e516e1cd771c41bb7e8c830b Mon Sep 17 00:00:00 2001 From: Saeed Mahameed Date: Thu, 1 Feb 2018 03:32:00 -0800 Subject: net/mlx5: CQ hold/put API Now as the CQ table is per EQ, add an API to hold/put CQ to be used from eq.c in downstream patch. Signed-off-by: Saeed Mahameed Reviewed-by: Gal Pressman --- drivers/net/ethernet/mellanox/mlx5/core/cq.c | 42 +++++++++++++--------------- include/linux/mlx5/cq.h | 11 ++++++++ 2 files changed, 30 insertions(+), 23 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cq.c b/drivers/net/ethernet/mellanox/mlx5/core/cq.c index f6e478d05ecc..06dc7bd302ed 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cq.c @@ -58,8 +58,7 @@ void mlx5_cq_tasklet_cb(unsigned long data) tasklet_ctx.list) { list_del_init(&mcq->tasklet_ctx.list); mcq->tasklet_ctx.comp(mcq); - if (refcount_dec_and_test(&mcq->refcount)) - complete(&mcq->free); + mlx5_cq_put(mcq); if (time_after(jiffies, end)) break; } @@ -80,23 +79,31 @@ static void mlx5_add_cq_to_tasklet(struct mlx5_core_cq *cq) * still arrive. */ if (list_empty_careful(&cq->tasklet_ctx.list)) { - refcount_inc(&cq->refcount); + mlx5_cq_hold(cq); list_add_tail(&cq->tasklet_ctx.list, &tasklet_ctx->list); } spin_unlock_irqrestore(&tasklet_ctx->lock, flags); } -void mlx5_cq_completion(struct mlx5_eq *eq, u32 cqn) +/* caller must eventually call mlx5_cq_put on the returned cq */ +static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn) { struct mlx5_cq_table *table = &eq->cq_table; - struct mlx5_core_cq *cq; + struct mlx5_core_cq *cq = NULL; spin_lock(&table->lock); cq = radix_tree_lookup(&table->tree, cqn); if (likely(cq)) - refcount_inc(&cq->refcount); + mlx5_cq_hold(cq); spin_unlock(&table->lock); + return cq; +} + +void mlx5_cq_completion(struct mlx5_eq *eq, u32 cqn) +{ + struct mlx5_core_cq *cq = mlx5_eq_cq_get(eq, cqn); + if (unlikely(!cq)) { mlx5_core_warn(eq->dev, "Completion event for bogus CQ 0x%x\n", cqn); return; @@ -106,22 +113,12 @@ void mlx5_cq_completion(struct mlx5_eq *eq, u32 cqn) cq->comp(cq); - if (refcount_dec_and_test(&cq->refcount)) - complete(&cq->free); + mlx5_cq_put(cq); } void mlx5_cq_event(struct mlx5_eq *eq, u32 cqn, int event_type) { - struct mlx5_cq_table *table = &eq->cq_table; - struct mlx5_core_cq *cq; - - spin_lock(&table->lock); - - cq = radix_tree_lookup(&table->tree, cqn); - if (likely(cq)) - refcount_inc(&cq->refcount); - - spin_unlock(&table->lock); + struct mlx5_core_cq *cq = mlx5_eq_cq_get(eq, cqn); if (unlikely(!cq)) { mlx5_core_warn(eq->dev, "Async event for bogus CQ 0x%x\n", cqn); @@ -130,8 +127,7 @@ void mlx5_cq_event(struct mlx5_eq *eq, u32 cqn, int event_type) cq->event(cq, event_type); - if (refcount_dec_and_test(&cq->refcount)) - complete(&cq->free); + mlx5_cq_put(cq); } int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, @@ -158,7 +154,8 @@ int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, cq->cons_index = 0; cq->arm_sn = 0; cq->eq = eq; - refcount_set(&cq->refcount, 1); + refcount_set(&cq->refcount, 0); + mlx5_cq_hold(cq); init_completion(&cq->free); if (!cq->comp) cq->comp = mlx5_add_cq_to_tasklet; @@ -221,8 +218,7 @@ int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq) synchronize_irq(cq->irqn); mlx5_debug_cq_remove(dev, cq); - if (refcount_dec_and_test(&cq->refcount)) - complete(&cq->free); + mlx5_cq_put(cq); wait_for_completion(&cq->free); return 0; diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h index 06ba425a6ad7..445ad194e0fe 100644 --- a/include/linux/mlx5/cq.h +++ b/include/linux/mlx5/cq.h @@ -172,6 +172,17 @@ static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd, mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, NULL); } +static inline void mlx5_cq_hold(struct mlx5_core_cq *cq) +{ + refcount_inc(&cq->refcount); +} + +static inline void mlx5_cq_put(struct mlx5_core_cq *cq) +{ + if (refcount_dec_and_test(&cq->refcount)) + complete(&cq->free); +} + int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, u32 *in, int inlen); int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); -- cgit v1.2.3 From 3ac7afdbcf243d6c79c1569d9e29aef0096e4743 Mon Sep 17 00:00:00 2001 From: Saeed Mahameed Date: Thu, 1 Feb 2018 04:37:07 -0800 Subject: net/mlx5: Move CQ completion and event forwarding logic to eq.c Since CQ tree is now per EQ, CQ completion and event forwarding became specific implementation of EQ logic, this patch moves that logic to eq.c and makes those functions static. Signed-off-by: Saeed Mahameed Reviewed-by: Gal Pressman --- drivers/net/ethernet/mellanox/mlx5/core/cq.c | 45 ------------------------- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 49 ++++++++++++++++++++++++++-- include/linux/mlx5/driver.h | 2 -- 3 files changed, 47 insertions(+), 49 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cq.c b/drivers/net/ethernet/mellanox/mlx5/core/cq.c index 06dc7bd302ed..669ed16938b3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cq.c @@ -85,51 +85,6 @@ static void mlx5_add_cq_to_tasklet(struct mlx5_core_cq *cq) spin_unlock_irqrestore(&tasklet_ctx->lock, flags); } -/* caller must eventually call mlx5_cq_put on the returned cq */ -static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn) -{ - struct mlx5_cq_table *table = &eq->cq_table; - struct mlx5_core_cq *cq = NULL; - - spin_lock(&table->lock); - cq = radix_tree_lookup(&table->tree, cqn); - if (likely(cq)) - mlx5_cq_hold(cq); - spin_unlock(&table->lock); - - return cq; -} - -void mlx5_cq_completion(struct mlx5_eq *eq, u32 cqn) -{ - struct mlx5_core_cq *cq = mlx5_eq_cq_get(eq, cqn); - - if (unlikely(!cq)) { - mlx5_core_warn(eq->dev, "Completion event for bogus CQ 0x%x\n", cqn); - return; - } - - ++cq->arm_sn; - - cq->comp(cq); - - mlx5_cq_put(cq); -} - -void mlx5_cq_event(struct mlx5_eq *eq, u32 cqn, int event_type) -{ - struct mlx5_core_cq *cq = mlx5_eq_cq_get(eq, cqn); - - if (unlikely(!cq)) { - mlx5_core_warn(eq->dev, "Async event for bogus CQ 0x%x\n", cqn); - return; - } - - cq->event(cq, event_type); - - mlx5_cq_put(cq); -} - int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, u32 *in, int inlen) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index c1f0468e95bd..7e442b38a8ca 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -393,6 +393,51 @@ static void general_event_handler(struct mlx5_core_dev *dev, } } +/* caller must eventually call mlx5_cq_put on the returned cq */ +static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn) +{ + struct mlx5_cq_table *table = &eq->cq_table; + struct mlx5_core_cq *cq = NULL; + + spin_lock(&table->lock); + cq = radix_tree_lookup(&table->tree, cqn); + if (likely(cq)) + mlx5_cq_hold(cq); + spin_unlock(&table->lock); + + return cq; +} + +static void mlx5_eq_cq_completion(struct mlx5_eq *eq, u32 cqn) +{ + struct mlx5_core_cq *cq = mlx5_eq_cq_get(eq, cqn); + + if (unlikely(!cq)) { + mlx5_core_warn(eq->dev, "Completion event for bogus CQ 0x%x\n", cqn); + return; + } + + ++cq->arm_sn; + + cq->comp(cq); + + mlx5_cq_put(cq); +} + +static void mlx5_eq_cq_event(struct mlx5_eq *eq, u32 cqn, int event_type) +{ + struct mlx5_core_cq *cq = mlx5_eq_cq_get(eq, cqn); + + if (unlikely(!cq)) { + mlx5_core_warn(eq->dev, "Async event for bogus CQ 0x%x\n", cqn); + return; + } + + cq->event(cq, event_type); + + mlx5_cq_put(cq); +} + static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) { struct mlx5_eq *eq = eq_ptr; @@ -415,7 +460,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) switch (eqe->type) { case MLX5_EVENT_TYPE_COMP: cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; - mlx5_cq_completion(eq, cqn); + mlx5_eq_cq_completion(eq, cqn); break; case MLX5_EVENT_TYPE_DCT_DRAINED: rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; @@ -472,7 +517,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrome 0x%x\n", cqn, eqe->data.cq_err.syndrome); - mlx5_cq_event(eq, cqn, eqe->type); + mlx5_eq_cq_event(eq, cqn, eqe->type); break; case MLX5_EVENT_TYPE_PAGE_REQUEST: diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 96e003db2bcd..09e2f3e8753c 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1049,12 +1049,10 @@ int mlx5_eq_init(struct mlx5_core_dev *dev); void mlx5_eq_cleanup(struct mlx5_core_dev *dev); void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); -void mlx5_cq_completion(struct mlx5_eq *eq, u32 cqn); void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); -void mlx5_cq_event(struct mlx5_eq *eq, u32 cqn, int event_type); int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, int nent, u64 mask, const char *name, enum mlx5_eq_type type); -- cgit v1.2.3 From 3ec5693b17314b58977ba3c8d720d1f9cfef39f8 Mon Sep 17 00:00:00 2001 From: Saeed Mahameed Date: Thu, 1 Feb 2018 05:42:06 -0800 Subject: net/mlx5: Remove redundant EQ API exports EQ structure and API is private to mlx5_core driver only, external drivers should not have access or the means to manipulate EQ objects. Remove redundant exports and move API functions out of the linux/mlx5 include directory into the driver's mlx5_core.h private include file. Signed-off-by: Saeed Mahameed Reviewed-by: Gal Pressman --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 3 --- drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 17 +++++++++++++++++ include/linux/mlx5/driver.h | 17 ----------------- 3 files changed, 17 insertions(+), 20 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 7e442b38a8ca..c1c94974e16b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -720,7 +720,6 @@ err_buf: mlx5_buf_free(dev, &eq->buf); return err; } -EXPORT_SYMBOL_GPL(mlx5_create_map_eq); int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) { @@ -747,7 +746,6 @@ int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) return err; } -EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq) { @@ -925,4 +923,3 @@ int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, MLX5_SET(query_eq_in, in, eq_number, eq->eqn); return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); } -EXPORT_SYMBOL_GPL(mlx5_core_eq_query); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index 54a1cbfb1b5a..23e17ac0cba5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -117,11 +117,28 @@ int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, int mlx5_wait_for_vf_pages(struct mlx5_core_dev *dev); u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev); +int mlx5_eq_init(struct mlx5_core_dev *dev); +void mlx5_eq_cleanup(struct mlx5_core_dev *dev); +int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, + int nent, u64 mask, const char *name, + enum mlx5_eq_type type); +int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq); int mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq); +int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, + u32 *out, int outlen); +int mlx5_start_eqs(struct mlx5_core_dev *dev); +void mlx5_stop_eqs(struct mlx5_core_dev *dev); struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn); u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq *eq); void mlx5_cq_tasklet_cb(unsigned long data); +void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); +int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); +void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); +int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); +void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); +int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); +void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, u8 access_reg_group); diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 09e2f3e8753c..2860a253275b 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1045,20 +1045,11 @@ int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); void mlx5_register_debugfs(void); void mlx5_unregister_debugfs(void); -int mlx5_eq_init(struct mlx5_core_dev *dev); -void mlx5_eq_cleanup(struct mlx5_core_dev *dev); void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); -void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); -int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, - int nent, u64 mask, const char *name, - enum mlx5_eq_type type); -int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); -int mlx5_start_eqs(struct mlx5_core_dev *dev); -void mlx5_stop_eqs(struct mlx5_core_dev *dev); int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, unsigned int *irqn); int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); @@ -1070,14 +1061,6 @@ int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in, void *data_out, int size_out, u16 reg_num, int arg, int write); -int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); -void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); -int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, - u32 *out, int outlen); -int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); -void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); -int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); -void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, int node); -- cgit v1.2.3 From 388ca8be00370db132464e27f745b8a0add19fcb Mon Sep 17 00:00:00 2001 From: Yonatan Cohen Date: Tue, 2 Jan 2018 16:08:06 +0200 Subject: IB/mlx5: Implement fragmented completion queue (CQ) The current implementation of create CQ requires contiguous memory, such requirement is problematic once the memory is fragmented or the system is low in memory, it causes for failures in dma_zalloc_coherent(). This patch implements new scheme of fragmented CQ to overcome this issue by introducing new type: 'struct mlx5_frag_buf_ctrl' to allocate fragmented buffers, rather than contiguous ones. Base the Completion Queues (CQs) on this new fragmented buffer. It fixes following crashes: kworker/29:0: page allocation failure: order:6, mode:0x80d0 CPU: 29 PID: 8374 Comm: kworker/29:0 Tainted: G OE 3.10.0 Workqueue: ib_cm cm_work_handler [ib_cm] Call Trace: [<>] dump_stack+0x19/0x1b [<>] warn_alloc_failed+0x110/0x180 [<>] __alloc_pages_slowpath+0x6b7/0x725 [<>] __alloc_pages_nodemask+0x405/0x420 [<>] dma_generic_alloc_coherent+0x8f/0x140 [<>] x86_swiotlb_alloc_coherent+0x21/0x50 [<>] mlx5_dma_zalloc_coherent_node+0xad/0x110 [mlx5_core] [<>] ? mlx5_db_alloc_node+0x69/0x1b0 [mlx5_core] [<>] mlx5_buf_alloc_node+0x3e/0xa0 [mlx5_core] [<>] mlx5_buf_alloc+0x14/0x20 [mlx5_core] [<>] create_cq_kernel+0x90/0x1f0 [mlx5_ib] [<>] mlx5_ib_create_cq+0x3b0/0x4e0 [mlx5_ib] Signed-off-by: Yonatan Cohen Reviewed-by: Tariq Toukan Signed-off-by: Leon Romanovsky Signed-off-by: Saeed Mahameed --- drivers/infiniband/hw/mlx5/cq.c | 64 +++++++++++++++---------- drivers/infiniband/hw/mlx5/mlx5_ib.h | 6 +-- drivers/net/ethernet/mellanox/mlx5/core/alloc.c | 37 +++++++++----- drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 11 +++-- drivers/net/ethernet/mellanox/mlx5/core/wq.c | 18 +++---- drivers/net/ethernet/mellanox/mlx5/core/wq.h | 22 +++------ include/linux/mlx5/driver.h | 51 ++++++++++++++------ 7 files changed, 124 insertions(+), 85 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c index 5b974fb97611..c4c7b82f4ac1 100644 --- a/drivers/infiniband/hw/mlx5/cq.c +++ b/drivers/infiniband/hw/mlx5/cq.c @@ -64,14 +64,9 @@ static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type) } } -static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size) -{ - return mlx5_buf_offset(&buf->buf, n * size); -} - static void *get_cqe(struct mlx5_ib_cq *cq, int n) { - return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz); + return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n); } static u8 sw_ownership_bit(int n, int nent) @@ -403,7 +398,7 @@ static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64, static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf) { - mlx5_buf_free(dev->mdev, &buf->buf); + mlx5_frag_buf_free(dev->mdev, &buf->fbc.frag_buf); } static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe, @@ -724,12 +719,25 @@ int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) return ret; } -static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf, - int nent, int cqe_size) +static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev, + struct mlx5_ib_cq_buf *buf, + int nent, + int cqe_size) { + struct mlx5_frag_buf_ctrl *c = &buf->fbc; + struct mlx5_frag_buf *frag_buf = &c->frag_buf; + u32 cqc_buff[MLX5_ST_SZ_DW(cqc)] = {0}; int err; - err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf); + MLX5_SET(cqc, cqc_buff, log_cq_size, ilog2(cqe_size)); + MLX5_SET(cqc, cqc_buff, cqe_sz, (cqe_size == 128) ? 1 : 0); + + mlx5_core_init_cq_frag_buf(&buf->fbc, cqc_buff); + + err = mlx5_frag_buf_alloc_node(dev->mdev, + nent * cqe_size, + frag_buf, + dev->mdev->priv.numa_node); if (err) return err; @@ -862,14 +870,15 @@ static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context) ib_umem_release(cq->buf.umem); } -static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf) +static void init_cq_frag_buf(struct mlx5_ib_cq *cq, + struct mlx5_ib_cq_buf *buf) { int i; void *cqe; struct mlx5_cqe64 *cqe64; for (i = 0; i < buf->nent; i++) { - cqe = get_cqe_from_buf(buf, i, buf->cqe_size); + cqe = get_cqe(cq, i); cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; cqe64->op_own = MLX5_CQE_INVALID << 4; } @@ -891,14 +900,15 @@ static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, cq->mcq.arm_db = cq->db.db + 1; cq->mcq.cqe_sz = cqe_size; - err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size); + err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size); if (err) goto err_db; - init_cq_buf(cq, &cq->buf); + init_cq_frag_buf(cq, &cq->buf); *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + - MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * cq->buf.buf.npages; + MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * + cq->buf.fbc.frag_buf.npages; *cqb = kvzalloc(*inlen, GFP_KERNEL); if (!*cqb) { err = -ENOMEM; @@ -906,11 +916,12 @@ static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, } pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); - mlx5_fill_page_array(&cq->buf.buf, pas); + mlx5_fill_page_frag_array(&cq->buf.fbc.frag_buf, pas); cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); MLX5_SET(cqc, cqc, log_page_size, - cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); + cq->buf.fbc.frag_buf.page_shift - + MLX5_ADAPTER_PAGE_SHIFT); *index = dev->mdev->priv.uar->index; @@ -1207,11 +1218,11 @@ static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, if (!cq->resize_buf) return -ENOMEM; - err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size); + err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size); if (err) goto ex; - init_cq_buf(cq, cq->resize_buf); + init_cq_frag_buf(cq, cq->resize_buf); return 0; @@ -1256,9 +1267,8 @@ static int copy_resize_cqes(struct mlx5_ib_cq *cq) } while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) { - dcqe = get_cqe_from_buf(cq->resize_buf, - (i + 1) & (cq->resize_buf->nent), - dsize); + dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc, + (i + 1) & cq->resize_buf->nent); dcqe64 = dsize == 64 ? dcqe : dcqe + 64; sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent); memcpy(dcqe, scqe, dsize); @@ -1324,8 +1334,11 @@ int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) cqe_size = 64; err = resize_kernel(dev, cq, entries, cqe_size); if (!err) { - npas = cq->resize_buf->buf.npages; - page_shift = cq->resize_buf->buf.page_shift; + struct mlx5_frag_buf_ctrl *c; + + c = &cq->resize_buf->fbc; + npas = c->frag_buf.npages; + page_shift = c->frag_buf.page_shift; } } @@ -1346,7 +1359,8 @@ int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift, pas, 0); else - mlx5_fill_page_array(&cq->resize_buf->buf, pas); + mlx5_fill_page_frag_array(&cq->resize_buf->fbc.frag_buf, + pas); MLX5_SET(modify_cq_in, in, modify_field_select_resize_field_select.resize_field_select.resize_field_select, diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h index 139385129973..eafb9751daf6 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -371,7 +371,7 @@ struct mlx5_ib_qp { struct mlx5_ib_rss_qp rss_qp; struct mlx5_ib_dct dct; }; - struct mlx5_buf buf; + struct mlx5_frag_buf buf; struct mlx5_db db; struct mlx5_ib_wq rq; @@ -413,7 +413,7 @@ struct mlx5_ib_qp { }; struct mlx5_ib_cq_buf { - struct mlx5_buf buf; + struct mlx5_frag_buf_ctrl fbc; struct ib_umem *umem; int cqe_size; int nent; @@ -495,7 +495,7 @@ struct mlx5_ib_wc { struct mlx5_ib_srq { struct ib_srq ibsrq; struct mlx5_core_srq msrq; - struct mlx5_buf buf; + struct mlx5_frag_buf buf; struct mlx5_db db; u64 *wrid; /* protect SRQ hanlding diff --git a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c b/drivers/net/ethernet/mellanox/mlx5/core/alloc.c index 47239bf7bf43..323ffe8bf7e4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/alloc.c @@ -71,19 +71,24 @@ static void *mlx5_dma_zalloc_coherent_node(struct mlx5_core_dev *dev, } int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, - struct mlx5_buf *buf, int node) + struct mlx5_frag_buf *buf, int node) { dma_addr_t t; buf->size = size; buf->npages = 1; buf->page_shift = (u8)get_order(size) + PAGE_SHIFT; - buf->direct.buf = mlx5_dma_zalloc_coherent_node(dev, size, - &t, node); - if (!buf->direct.buf) + + buf->frags = kzalloc(sizeof(*buf->frags), GFP_KERNEL); + if (!buf->frags) return -ENOMEM; - buf->direct.map = t; + buf->frags->buf = mlx5_dma_zalloc_coherent_node(dev, size, + &t, node); + if (!buf->frags->buf) + goto err_out; + + buf->frags->map = t; while (t & ((1 << buf->page_shift) - 1)) { --buf->page_shift; @@ -91,18 +96,24 @@ int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, } return 0; +err_out: + kfree(buf->frags); + return -ENOMEM; } -int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf) +int mlx5_buf_alloc(struct mlx5_core_dev *dev, + int size, struct mlx5_frag_buf *buf) { return mlx5_buf_alloc_node(dev, size, buf, dev->priv.numa_node); } -EXPORT_SYMBOL_GPL(mlx5_buf_alloc); +EXPORT_SYMBOL(mlx5_buf_alloc); -void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf) +void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf) { - dma_free_coherent(&dev->pdev->dev, buf->size, buf->direct.buf, - buf->direct.map); + dma_free_coherent(&dev->pdev->dev, buf->size, buf->frags->buf, + buf->frags->map); + + kfree(buf->frags); } EXPORT_SYMBOL_GPL(mlx5_buf_free); @@ -147,6 +158,7 @@ err_free_buf: err_out: return -ENOMEM; } +EXPORT_SYMBOL_GPL(mlx5_frag_buf_alloc_node); void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf) { @@ -162,6 +174,7 @@ void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf) } kfree(buf->frags); } +EXPORT_SYMBOL_GPL(mlx5_frag_buf_free); static struct mlx5_db_pgdir *mlx5_alloc_db_pgdir(struct mlx5_core_dev *dev, int node) @@ -275,13 +288,13 @@ void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db) } EXPORT_SYMBOL_GPL(mlx5_db_free); -void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas) +void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas) { u64 addr; int i; for (i = 0; i < buf->npages; i++) { - addr = buf->direct.map + (i << buf->page_shift); + addr = buf->frags->map + (i << buf->page_shift); pas[i] = cpu_to_be64(addr); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 0d4bb0688faa..80b84f6af2a1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -52,7 +52,7 @@ static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, void *data) { - u32 ci = cqcc & cq->wq.sz_m1; + u32 ci = cqcc & cq->wq.fbc.sz_m1; memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); } @@ -74,9 +74,10 @@ static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) { - u8 op_own = (cqcc >> cq->wq.log_sz) & 1; - u32 wq_sz = 1 << cq->wq.log_sz; - u32 ci = cqcc & cq->wq.sz_m1; + struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc; + u8 op_own = (cqcc >> fbc->log_sz) & 1; + u32 wq_sz = 1 << fbc->log_sz; + u32 ci = cqcc & fbc->sz_m1; u32 ci_top = min_t(u32, wq_sz, ci + n); for (; ci < ci_top; ci++, n--) { @@ -101,7 +102,7 @@ static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; cq->title.op_own &= 0xf0; - cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); + cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz); cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/wq.c b/drivers/net/ethernet/mellanox/mlx5/core/wq.c index 6bcfc25350f5..ea66448ba365 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/wq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/wq.c @@ -41,7 +41,7 @@ u32 mlx5_wq_cyc_get_size(struct mlx5_wq_cyc *wq) u32 mlx5_cqwq_get_size(struct mlx5_cqwq *wq) { - return wq->sz_m1 + 1; + return wq->fbc.sz_m1 + 1; } u32 mlx5_wq_ll_get_size(struct mlx5_wq_ll *wq) @@ -62,7 +62,7 @@ static u32 mlx5_wq_qp_get_byte_size(struct mlx5_wq_qp *wq) static u32 mlx5_cqwq_get_byte_size(struct mlx5_cqwq *wq) { - return mlx5_cqwq_get_size(wq) << wq->log_stride; + return mlx5_cqwq_get_size(wq) << wq->fbc.log_stride; } static u32 mlx5_wq_ll_get_byte_size(struct mlx5_wq_ll *wq) @@ -92,7 +92,7 @@ int mlx5_wq_cyc_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param, goto err_db_free; } - wq->buf = wq_ctrl->buf.direct.buf; + wq->buf = wq_ctrl->buf.frags->buf; wq->db = wq_ctrl->db.db; wq_ctrl->mdev = mdev; @@ -130,7 +130,7 @@ int mlx5_wq_qp_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param, goto err_db_free; } - wq->rq.buf = wq_ctrl->buf.direct.buf; + wq->rq.buf = wq_ctrl->buf.frags->buf; wq->sq.buf = wq->rq.buf + mlx5_wq_cyc_get_byte_size(&wq->rq); wq->rq.db = &wq_ctrl->db.db[MLX5_RCV_DBR]; wq->sq.db = &wq_ctrl->db.db[MLX5_SND_DBR]; @@ -151,11 +151,7 @@ int mlx5_cqwq_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param, { int err; - wq->log_stride = 6 + MLX5_GET(cqc, cqc, cqe_sz); - wq->log_sz = MLX5_GET(cqc, cqc, log_cq_size); - wq->sz_m1 = (1 << wq->log_sz) - 1; - wq->log_frag_strides = PAGE_SHIFT - wq->log_stride; - wq->frag_sz_m1 = (1 << wq->log_frag_strides) - 1; + mlx5_core_init_cq_frag_buf(&wq->fbc, cqc); err = mlx5_db_alloc_node(mdev, &wq_ctrl->db, param->db_numa_node); if (err) { @@ -172,7 +168,7 @@ int mlx5_cqwq_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param, goto err_db_free; } - wq->frag_buf = wq_ctrl->frag_buf; + wq->fbc.frag_buf = wq_ctrl->frag_buf; wq->db = wq_ctrl->db.db; wq_ctrl->mdev = mdev; @@ -209,7 +205,7 @@ int mlx5_wq_ll_create(struct mlx5_core_dev *mdev, struct mlx5_wq_param *param, goto err_db_free; } - wq->buf = wq_ctrl->buf.direct.buf; + wq->buf = wq_ctrl->buf.frags->buf; wq->db = wq_ctrl->db.db; for (i = 0; i < wq->sz_m1; i++) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/wq.h b/drivers/net/ethernet/mellanox/mlx5/core/wq.h index 718589d0cec2..fca90b94596d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/wq.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/wq.h @@ -45,7 +45,7 @@ struct mlx5_wq_param { struct mlx5_wq_ctrl { struct mlx5_core_dev *mdev; - struct mlx5_buf buf; + struct mlx5_frag_buf buf; struct mlx5_db db; }; @@ -68,14 +68,9 @@ struct mlx5_wq_qp { }; struct mlx5_cqwq { - struct mlx5_frag_buf frag_buf; - __be32 *db; - u32 sz_m1; - u32 frag_sz_m1; - u32 cc; /* consumer counter */ - u8 log_sz; - u8 log_stride; - u8 log_frag_strides; + struct mlx5_frag_buf_ctrl fbc; + __be32 *db; + u32 cc; /* consumer counter */ }; struct mlx5_wq_ll { @@ -131,20 +126,17 @@ static inline int mlx5_wq_cyc_cc_bigger(u16 cc1, u16 cc2) static inline u32 mlx5_cqwq_get_ci(struct mlx5_cqwq *wq) { - return wq->cc & wq->sz_m1; + return wq->cc & wq->fbc.sz_m1; } static inline void *mlx5_cqwq_get_wqe(struct mlx5_cqwq *wq, u32 ix) { - unsigned int frag = (ix >> wq->log_frag_strides); - - return wq->frag_buf.frags[frag].buf + - ((wq->frag_sz_m1 & ix) << wq->log_stride); + return mlx5_frag_buf_get_wqe(&wq->fbc, ix); } static inline u32 mlx5_cqwq_get_wrap_cnt(struct mlx5_cqwq *wq) { - return wq->cc >> wq->log_sz; + return wq->cc >> wq->fbc.log_sz; } static inline void mlx5_cqwq_pop(struct mlx5_cqwq *wq) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 2860a253275b..bfea26af6de5 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -345,13 +345,6 @@ struct mlx5_buf_list { dma_addr_t map; }; -struct mlx5_buf { - struct mlx5_buf_list direct; - int npages; - int size; - u8 page_shift; -}; - struct mlx5_frag_buf { struct mlx5_buf_list *frags; int npages; @@ -359,6 +352,15 @@ struct mlx5_frag_buf { u8 page_shift; }; +struct mlx5_frag_buf_ctrl { + struct mlx5_frag_buf frag_buf; + u32 sz_m1; + u32 frag_sz_m1; + u8 log_sz; + u8 log_stride; + u8 log_frag_strides; +}; + struct mlx5_eq_tasklet { struct list_head list; struct list_head process_list; @@ -386,7 +388,7 @@ struct mlx5_eq { struct mlx5_cq_table cq_table; __be32 __iomem *doorbell; u32 cons_index; - struct mlx5_buf buf; + struct mlx5_frag_buf buf; int size; unsigned int irqn; u8 eqn; @@ -932,9 +934,9 @@ struct mlx5_hca_vport_context { bool grh_required; }; -static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) +static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) { - return buf->direct.buf + offset; + return buf->frags->buf + offset; } #define STRUCT_FIELD(header, field) \ @@ -973,6 +975,25 @@ static inline u32 mlx5_base_mkey(const u32 key) return key & 0xffffff00u; } +static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc, + void *cqc) +{ + fbc->log_stride = 6 + MLX5_GET(cqc, cqc, cqe_sz); + fbc->log_sz = MLX5_GET(cqc, cqc, log_cq_size); + fbc->sz_m1 = (1 << fbc->log_sz) - 1; + fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; + fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; +} + +static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, + u32 ix) +{ + unsigned int frag = (ix >> fbc->log_frag_strides); + + return fbc->frag_buf.frags[frag].buf + + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); +} + int mlx5_cmd_init(struct mlx5_core_dev *dev); void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); void mlx5_cmd_use_events(struct mlx5_core_dev *dev); @@ -998,9 +1019,10 @@ void mlx5_drain_health_wq(struct mlx5_core_dev *dev); void mlx5_trigger_health_work(struct mlx5_core_dev *dev); void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, - struct mlx5_buf *buf, int node); -int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); -void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); + struct mlx5_frag_buf *buf, int node); +int mlx5_buf_alloc(struct mlx5_core_dev *dev, + int size, struct mlx5_frag_buf *buf); +void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, struct mlx5_frag_buf *buf, int node); void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); @@ -1045,7 +1067,8 @@ int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); void mlx5_register_debugfs(void); void mlx5_unregister_debugfs(void); -void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); + +void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); -- cgit v1.2.3 From d8d211a2a0c37755a8660dc69f97b7c70bf210b1 Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Wed, 14 Feb 2018 16:39:56 +0300 Subject: net: Make extern and export get_net_ns() This function will be used to obtain net of tun device. Signed-off-by: Kirill Tkhai Signed-off-by: David S. Miller --- include/linux/socket.h | 2 ++ net/socket.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/socket.h b/include/linux/socket.h index 9286a5a8c60c..1ce1f768a58c 100644 --- a/include/linux/socket.h +++ b/include/linux/socket.h @@ -353,4 +353,6 @@ extern int __sys_recvmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen unsigned int flags, struct timespec *timeout); extern int __sys_sendmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen, unsigned int flags); + +extern struct ns_common *get_net_ns(struct ns_common *ns); #endif /* _LINUX_SOCKET_H */ diff --git a/net/socket.c b/net/socket.c index d83e804d5e65..ab58e57c09ca 100644 --- a/net/socket.c +++ b/net/socket.c @@ -990,10 +990,11 @@ static long sock_do_ioctl(struct net *net, struct socket *sock, * what to do with it - that's up to the protocol still. */ -static struct ns_common *get_net_ns(struct ns_common *ns) +struct ns_common *get_net_ns(struct ns_common *ns) { return &get_net(container_of(ns, struct net, ns))->ns; } +EXPORT_SYMBOL_GPL(get_net_ns); static long sock_ioctl(struct file *file, unsigned cmd, unsigned long arg) { -- cgit v1.2.3 From 562c45d635ecd5c0648ceb4d4aff9bdc1ad91252 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 15 Feb 2018 16:49:45 -0800 Subject: headers: Drop two #included headers from It seems that does not need nor . 8 kernels builds are successful without these 2 headers (allmodconfig, allyesconfig, allnoconfig, and tinyconfig on both i386 and x86_64). is #included 3875 times in 4.16-rc1, so this reduces #include processing of these 2 files by a total of 7750 times. Since I only tested x86 builds, this needs to be tested on other $ARCHes as well. Signed-off-by: Randy Dunlap Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-arch@vger.kernel.org Link: http://lkml.kernel.org/r/b24b9ec8-4970-65f5-759a-911d4ba2fcf0@infradead.org Signed-off-by: Ingo Molnar --- include/linux/interrupt.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index 69c238210325..5426627f9c55 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -4,9 +4,7 @@ #define _LINUX_INTERRUPT_H #include -#include #include -#include #include #include #include -- cgit v1.2.3 From 43a0a45abc4ab386f3ba978c877a2b68a0cad448 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 5 Feb 2018 23:01:59 +0100 Subject: mtd: nand: Get rid of comments giving the file path inside the file itself Some files add a comment giving the path of the file inside the Linux tree, which is pretty useless since the reader had to find the file to open it. Getting rid of these comments will also allow us to easily move these files around when needed. Signed-off-by: Boris Brezillon --- drivers/mtd/nand/Makefile | 3 --- drivers/mtd/nand/ams-delta.c | 2 -- drivers/mtd/nand/au1550nd.c | 2 -- drivers/mtd/nand/bf5xx_nand.c | 3 +-- drivers/mtd/nand/cmx270_nand.c | 2 -- drivers/mtd/nand/cs553x_nand.c | 2 -- drivers/mtd/nand/diskonchip.c | 2 -- drivers/mtd/nand/fsmc_nand.c | 2 -- drivers/mtd/nand/gpio.c | 2 -- drivers/mtd/nand/nand_ecc.c | 2 -- drivers/mtd/nand/orion_nand.c | 2 -- drivers/mtd/nand/pxa3xx_nand.c | 2 -- drivers/mtd/nand/s3c2410.c | 3 +-- drivers/mtd/nand/sharpsl.c | 2 -- drivers/mtd/nand/socrates_nand.c | 2 -- include/linux/mtd/bbm.h | 2 -- include/linux/mtd/nand_ecc.h | 2 -- include/linux/mtd/ndfc.h | 2 -- 18 files changed, 2 insertions(+), 37 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 921634ba400c..4e0982476267 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -1,7 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -# -# linux/drivers/nand/Makefile -# obj-$(CONFIG_MTD_NAND) += nand.o obj-$(CONFIG_MTD_NAND_ECC) += nand_ecc.o diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c index d60ada45c549..e15991d81a20 100644 --- a/drivers/mtd/nand/ams-delta.c +++ b/drivers/mtd/nand/ams-delta.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/ams-delta.c - * * Copyright (C) 2006 Jonathan McDowell * * Derived from drivers/mtd/toto.c diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 8ab827edf94e..df0ef1f1e2f5 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/au1550nd.c - * * Copyright (C) 2004 Embedded Edge, LLC * * This program is free software; you can redistribute it and/or modify diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c index 87bbd177b3e5..4a5f56f76efd 100644 --- a/drivers/mtd/nand/bf5xx_nand.c +++ b/drivers/mtd/nand/bf5xx_nand.c @@ -1,5 +1,4 @@ -/* linux/drivers/mtd/nand/bf5xx_nand.c - * +/* * Copyright 2006-2008 Analog Devices Inc. * http://blackfin.uclinux.org/ * Bryan Wu diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c index b01c9804590e..66749ade9654 100644 --- a/drivers/mtd/nand/cmx270_nand.c +++ b/drivers/mtd/nand/cmx270_nand.c @@ -1,6 +1,4 @@ /* - * linux/drivers/mtd/nand/cmx270-nand.c - * * Copyright (C) 2006 Compulab, Ltd. * Mike Rapoport * diff --git a/drivers/mtd/nand/cs553x_nand.c b/drivers/mtd/nand/cs553x_nand.c index d48877540f14..be1f28fc7363 100644 --- a/drivers/mtd/nand/cs553x_nand.c +++ b/drivers/mtd/nand/cs553x_nand.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/cs553x_nand.c - * * (C) 2005, 2006 Red Hat Inc. * * Author: David Woodhouse diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c index 6bc93ea66f50..1af77f798fe5 100644 --- a/drivers/mtd/nand/diskonchip.c +++ b/drivers/mtd/nand/diskonchip.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/diskonchip.c - * * (C) 2003 Red Hat, Inc. * (C) 2004 Dan Brown * (C) 2004 Kalev Lember diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index f49ed46fa770..e763161a7c82 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/fsmc_nand.c - * * ST Microelectronics * Flexible Static Memory Controller (FSMC) * Driver for NAND portions diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c index a8bde6665c24..2780af26d9ab 100644 --- a/drivers/mtd/nand/gpio.c +++ b/drivers/mtd/nand/gpio.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/gpio.c - * * Updated, and converted to generic GPIO based driver by Russell King. * * Written by Ben Dooks diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c index 7613a0388044..3630f0fe8fa4 100644 --- a/drivers/mtd/nand/nand_ecc.c +++ b/drivers/mtd/nand/nand_ecc.c @@ -2,8 +2,6 @@ * This file contains an ECC algorithm that detects and corrects 1 bit * errors in a 256 byte block of data. * - * drivers/mtd/nand/nand_ecc.c - * * Copyright © 2008 Koninklijke Philips Electronics NV. * Author: Frans Meulenbroeks * diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index 5a5aa1f07d07..7825fd3ce66b 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/orion_nand.c - * * NAND support for Marvell Orion SoC platforms * * Tzachi Perelstein diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index d1979c7dbe7e..d75f30263d21 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/pxa3xx_nand.c - * * Copyright © 2005 Intel Corporation * Copyright © 2006 Marvell International Ltd. * diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 4c383eeec6f6..b5bc5f106c09 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -1,5 +1,4 @@ -/* linux/drivers/mtd/nand/s3c2410.c - * +/* * Copyright © 2004-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c index f59c455d9f51..e93df02c825e 100644 --- a/drivers/mtd/nand/sharpsl.c +++ b/drivers/mtd/nand/sharpsl.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/sharpsl.c - * * Copyright (C) 2004 Richard Purdie * Copyright (C) 2008 Dmitry Baryshkov * diff --git a/drivers/mtd/nand/socrates_nand.c b/drivers/mtd/nand/socrates_nand.c index 575997d0ef8a..9824a9923583 100644 --- a/drivers/mtd/nand/socrates_nand.c +++ b/drivers/mtd/nand/socrates_nand.c @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand/socrates_nand.c - * * Copyright © 2008 Ilya Yanok, Emcraft Systems * * diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h index 3bf8f954b642..3102bd754d18 100644 --- a/include/linux/mtd/bbm.h +++ b/include/linux/mtd/bbm.h @@ -1,6 +1,4 @@ /* - * linux/include/linux/mtd/bbm.h - * * NAND family Bad Block Management (BBM) header file * - Bad Block Table (BBT) implementation * diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h index 4d8406c81652..8a2decf7462c 100644 --- a/include/linux/mtd/nand_ecc.h +++ b/include/linux/mtd/nand_ecc.h @@ -1,6 +1,4 @@ /* - * drivers/mtd/nand_ecc.h - * * Copyright (C) 2000-2010 Steven J. Hill * David Woodhouse * Thomas Gleixner diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h index d0558a982628..357e88b3263a 100644 --- a/include/linux/mtd/ndfc.h +++ b/include/linux/mtd/ndfc.h @@ -1,6 +1,4 @@ /* - * linux/include/linux/mtd/ndfc.h - * * Copyright (c) 2006 Thomas Gleixner * * This program is free software; you can redistribute it and/or modify -- cgit v1.2.3 From 9c3736a3de21d916a6af0594418b85a112f4bef6 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 5 Feb 2018 23:02:05 +0100 Subject: mtd: nand: Add core infrastructure to deal with NAND devices Add an intermediate layer to abstract NAND device interface so that some logic can be shared between SPI NANDs, parallel/raw NANDs, OneNANDs, ... Signed-off-by: Boris Brezillon --- drivers/mtd/nand/Kconfig | 3 + drivers/mtd/nand/Makefile | 3 + drivers/mtd/nand/bbt.c | 130 +++++++++ drivers/mtd/nand/core.c | 244 ++++++++++++++++ include/linux/mtd/nand.h | 731 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 1111 insertions(+) create mode 100644 drivers/mtd/nand/bbt.c create mode 100644 drivers/mtd/nand/core.c create mode 100644 include/linux/mtd/nand.h (limited to 'include/linux') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 6d5373471809..1c1a1f487e20 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -1 +1,4 @@ +config MTD_NAND_CORE + tristate + source "drivers/mtd/nand/raw/Kconfig" diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 32af7168c5ba..a72d3cb0f325 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +nandcore-objs := core.o bbt.o +obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o + obj-y += raw/ diff --git a/drivers/mtd/nand/bbt.c b/drivers/mtd/nand/bbt.c new file mode 100644 index 000000000000..56cde38b92c0 --- /dev/null +++ b/drivers/mtd/nand/bbt.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017 Free Electrons + * + * Authors: + * Boris Brezillon + * Peter Pan + */ + +#define pr_fmt(fmt) "nand-bbt: " fmt + +#include +#include + +/** + * nanddev_bbt_init() - Initialize the BBT (Bad Block Table) + * @nand: NAND device + * + * Initialize the in-memory BBT. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int nanddev_bbt_init(struct nand_device *nand) +{ + unsigned int bits_per_block = fls(NAND_BBT_BLOCK_NUM_STATUS); + unsigned int nblocks = nanddev_neraseblocks(nand); + unsigned int nwords = DIV_ROUND_UP(nblocks * bits_per_block, + BITS_PER_LONG); + + nand->bbt.cache = kzalloc(nwords, GFP_KERNEL); + if (!nand->bbt.cache) + return -ENOMEM; + + return 0; +} +EXPORT_SYMBOL_GPL(nanddev_bbt_init); + +/** + * nanddev_bbt_cleanup() - Cleanup the BBT (Bad Block Table) + * @nand: NAND device + * + * Undoes what has been done in nanddev_bbt_init() + */ +void nanddev_bbt_cleanup(struct nand_device *nand) +{ + kfree(nand->bbt.cache); +} +EXPORT_SYMBOL_GPL(nanddev_bbt_cleanup); + +/** + * nanddev_bbt_update() - Update a BBT + * @nand: nand device + * + * Update the BBT. Currently a NOP function since on-flash bbt is not yet + * supported. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int nanddev_bbt_update(struct nand_device *nand) +{ + return 0; +} +EXPORT_SYMBOL_GPL(nanddev_bbt_update); + +/** + * nanddev_bbt_get_block_status() - Return the status of an eraseblock + * @nand: nand device + * @entry: the BBT entry + * + * Return: a positive number nand_bbt_block_status status or -%ERANGE if @entry + * is bigger than the BBT size. + */ +int nanddev_bbt_get_block_status(const struct nand_device *nand, + unsigned int entry) +{ + unsigned int bits_per_block = fls(NAND_BBT_BLOCK_NUM_STATUS); + unsigned long *pos = nand->bbt.cache + + ((entry * bits_per_block) / BITS_PER_LONG); + unsigned int offs = (entry * bits_per_block) % BITS_PER_LONG; + unsigned long status; + + if (entry >= nanddev_neraseblocks(nand)) + return -ERANGE; + + status = pos[0] >> offs; + if (bits_per_block + offs > BITS_PER_LONG) + status |= pos[1] << (BITS_PER_LONG - offs); + + return status & GENMASK(bits_per_block - 1, 0); +} +EXPORT_SYMBOL_GPL(nanddev_bbt_get_block_status); + +/** + * nanddev_bbt_set_block_status() - Update the status of an eraseblock in the + * in-memory BBT + * @nand: nand device + * @entry: the BBT entry to update + * @status: the new status + * + * Update an entry of the in-memory BBT. If you want to push the updated BBT + * the NAND you should call nanddev_bbt_update(). + * + * Return: 0 in case of success or -%ERANGE if @entry is bigger than the BBT + * size. + */ +int nanddev_bbt_set_block_status(struct nand_device *nand, unsigned int entry, + enum nand_bbt_block_status status) +{ + unsigned int bits_per_block = fls(NAND_BBT_BLOCK_NUM_STATUS); + unsigned long *pos = nand->bbt.cache + + ((entry * bits_per_block) / BITS_PER_LONG); + unsigned int offs = (entry * bits_per_block) % BITS_PER_LONG; + unsigned long val = status & GENMASK(bits_per_block - 1, 0); + + if (entry >= nanddev_neraseblocks(nand)) + return -ERANGE; + + pos[0] &= ~GENMASK(offs + bits_per_block - 1, offs); + pos[0] |= val << offs; + + if (bits_per_block + offs > BITS_PER_LONG) { + unsigned int rbits = bits_per_block + offs - BITS_PER_LONG; + + pos[1] &= ~GENMASK(rbits - 1, 0); + pos[1] |= val >> rbits; + } + + return 0; +} +EXPORT_SYMBOL_GPL(nanddev_bbt_set_block_status); diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c new file mode 100644 index 000000000000..f237a688f8e9 --- /dev/null +++ b/drivers/mtd/nand/core.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017 Free Electrons + * + * Authors: + * Boris Brezillon + * Peter Pan + */ + +#define pr_fmt(fmt) "nand: " fmt + +#include +#include + +/** + * nanddev_isbad() - Check if a block is bad + * @nand: NAND device + * @pos: position pointing to the block we want to check + * + * Return: true if the block is bad, false otherwise. + */ +bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) +{ + if (nanddev_bbt_is_initialized(nand)) { + unsigned int entry; + int status; + + entry = nanddev_bbt_pos_to_entry(nand, pos); + status = nanddev_bbt_get_block_status(nand, entry); + /* Lazy block status retrieval */ + if (status == NAND_BBT_BLOCK_STATUS_UNKNOWN) { + if (nand->ops->isbad(nand, pos)) + status = NAND_BBT_BLOCK_FACTORY_BAD; + else + status = NAND_BBT_BLOCK_GOOD; + + nanddev_bbt_set_block_status(nand, entry, status); + } + + if (status == NAND_BBT_BLOCK_WORN || + status == NAND_BBT_BLOCK_FACTORY_BAD) + return true; + + return false; + } + + return nand->ops->isbad(nand, pos); +} +EXPORT_SYMBOL_GPL(nanddev_isbad); + +/** + * nanddev_markbad() - Mark a block as bad + * @nand: NAND device + * @block: block to mark bad + * + * Mark a block bad. This function is updating the BBT if available and + * calls the low-level markbad hook (nand->ops->markbad()). + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos) +{ + struct mtd_info *mtd = nanddev_to_mtd(nand); + unsigned int entry; + int ret = 0; + + if (nanddev_isbad(nand, pos)) + return 0; + + ret = nand->ops->markbad(nand, pos); + if (ret) + pr_warn("failed to write BBM to block @%llx (err = %d)\n", + nanddev_pos_to_offs(nand, pos), ret); + + if (!nanddev_bbt_is_initialized(nand)) + goto out; + + entry = nanddev_bbt_pos_to_entry(nand, pos); + ret = nanddev_bbt_set_block_status(nand, entry, NAND_BBT_BLOCK_WORN); + if (ret) + goto out; + + ret = nanddev_bbt_update(nand); + +out: + if (!ret) + mtd->ecc_stats.badblocks++; + + return ret; +} +EXPORT_SYMBOL_GPL(nanddev_markbad); + +/** + * nanddev_isreserved() - Check whether an eraseblock is reserved or not + * @nand: NAND device + * @pos: NAND position to test + * + * Checks whether the eraseblock pointed by @pos is reserved or not. + * + * Return: true if the eraseblock is reserved, false otherwise. + */ +bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos) +{ + unsigned int entry; + int status; + + if (!nanddev_bbt_is_initialized(nand)) + return false; + + /* Return info from the table */ + entry = nanddev_bbt_pos_to_entry(nand, pos); + status = nanddev_bbt_get_block_status(nand, entry); + return status == NAND_BBT_BLOCK_RESERVED; +} +EXPORT_SYMBOL_GPL(nanddev_isreserved); + +/** + * nanddev_erase() - Erase a NAND portion + * @nand: NAND device + * @block: eraseblock to erase + * + * Erases @block if it's not bad. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) +{ + if (nanddev_isbad(nand, pos) || nanddev_isreserved(nand, pos)) { + pr_warn("attempt to erase a bad/reserved block @%llx\n", + nanddev_pos_to_offs(nand, pos)); + return -EIO; + } + + return nand->ops->erase(nand, pos); +} +EXPORT_SYMBOL_GPL(nanddev_erase); + +/** + * nanddev_mtd_erase() - Generic mtd->_erase() implementation for NAND devices + * @mtd: MTD device + * @einfo: erase request + * + * This is a simple mtd->_erase() implementation iterating over all blocks + * concerned by @einfo and calling nand->ops->erase() on each of them. + * + * Note that mtd->_erase should not be directly assigned to this helper, + * because there's no locking here. NAND specialized layers should instead + * implement there own wrapper around nanddev_mtd_erase() taking the + * appropriate lock before calling nanddev_mtd_erase(). + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo) +{ + struct nand_device *nand = mtd_to_nanddev(mtd); + struct nand_pos pos, last; + int ret; + + nanddev_offs_to_pos(nand, einfo->addr, &pos); + nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1, &last); + while (nanddev_pos_cmp(&pos, &last) <= 0) { + ret = nanddev_erase(nand, &pos); + if (ret) { + einfo->fail_addr = nanddev_pos_to_offs(nand, &pos); + einfo->state = MTD_ERASE_FAILED; + + return ret; + } + + nanddev_pos_next_eraseblock(nand, &pos); + } + + einfo->state = MTD_ERASE_DONE; + + return 0; +} +EXPORT_SYMBOL_GPL(nanddev_mtd_erase); + +/** + * nanddev_init() - Initialize a NAND device + * @nand: NAND device + * @memorg: NAND memory organization descriptor + * @ops: NAND device operations + * + * Initializes a NAND device object. Consistency checks are done on @memorg and + * @ops. Also takes care of initializing the BBT. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int nanddev_init(struct nand_device *nand, const struct nand_ops *ops, + struct module *owner) +{ + struct mtd_info *mtd = nanddev_to_mtd(nand); + struct nand_memory_organization *memorg = nanddev_get_memorg(nand); + + if (!nand || !ops) + return -EINVAL; + + if (!ops->erase || !ops->markbad || !ops->isbad) + return -EINVAL; + + if (!memorg->bits_per_cell || !memorg->pagesize || + !memorg->pages_per_eraseblock || !memorg->eraseblocks_per_lun || + !memorg->planes_per_lun || !memorg->luns_per_target || + !memorg->ntargets) + return -EINVAL; + + nand->rowconv.eraseblock_addr_shift = + fls(memorg->pages_per_eraseblock - 1); + nand->rowconv.lun_addr_shift = fls(memorg->eraseblocks_per_lun - 1) + + nand->rowconv.eraseblock_addr_shift; + + nand->ops = ops; + + mtd->type = memorg->bits_per_cell == 1 ? + MTD_NANDFLASH : MTD_MLCNANDFLASH; + mtd->flags = MTD_CAP_NANDFLASH; + mtd->erasesize = memorg->pagesize * memorg->pages_per_eraseblock; + mtd->writesize = memorg->pagesize; + mtd->writebufsize = memorg->pagesize; + mtd->oobsize = memorg->oobsize; + mtd->size = nanddev_size(nand); + mtd->owner = owner; + + return nanddev_bbt_init(nand); +} +EXPORT_SYMBOL_GPL(nanddev_init); + +/** + * nanddev_cleanup() - Release resources allocated in nanddev_init() + * @nand: NAND device + * + * Basically undoes what has been done in nanddev_init(). + */ +void nanddev_cleanup(struct nand_device *nand) +{ + if (nanddev_bbt_is_initialized(nand)) + nanddev_bbt_cleanup(nand); +} +EXPORT_SYMBOL_GPL(nanddev_cleanup); + +MODULE_DESCRIPTION("Generic NAND framework"); +MODULE_AUTHOR("Boris Brezillon "); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h new file mode 100644 index 000000000000..792ea5c26329 --- /dev/null +++ b/include/linux/mtd/nand.h @@ -0,0 +1,731 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 - Free Electrons + * + * Authors: + * Boris Brezillon + * Peter Pan + */ + +#ifndef __LINUX_MTD_NAND_H +#define __LINUX_MTD_NAND_H + +#include + +/** + * struct nand_memory_organization - Memory organization structure + * @bits_per_cell: number of bits per NAND cell + * @pagesize: page size + * @oobsize: OOB area size + * @pages_per_eraseblock: number of pages per eraseblock + * @eraseblocks_per_lun: number of eraseblocks per LUN (Logical Unit Number) + * @planes_per_lun: number of planes per LUN + * @luns_per_target: number of LUN per target (target is a synonym for die) + * @ntargets: total number of targets exposed by the NAND device + */ +struct nand_memory_organization { + unsigned int bits_per_cell; + unsigned int pagesize; + unsigned int oobsize; + unsigned int pages_per_eraseblock; + unsigned int eraseblocks_per_lun; + unsigned int planes_per_lun; + unsigned int luns_per_target; + unsigned int ntargets; +}; + +#define NAND_MEMORG(bpc, ps, os, ppe, epl, ppl, lpt, nt) \ + { \ + .bits_per_cell = (bpc), \ + .pagesize = (ps), \ + .oobsize = (os), \ + .pages_per_eraseblock = (ppe), \ + .eraseblocks_per_lun = (epl), \ + .planes_per_lun = (ppl), \ + .luns_per_target = (lpt), \ + .ntargets = (nt), \ + } + +/** + * struct nand_row_converter - Information needed to convert an absolute offset + * into a row address + * @lun_addr_shift: position of the LUN identifier in the row address + * @eraseblock_addr_shift: position of the eraseblock identifier in the row + * address + */ +struct nand_row_converter { + unsigned int lun_addr_shift; + unsigned int eraseblock_addr_shift; +}; + +/** + * struct nand_pos - NAND position object + * @target: the NAND target/die + * @lun: the LUN identifier + * @plane: the plane within the LUN + * @eraseblock: the eraseblock within the LUN + * @page: the page within the LUN + * + * These information are usually used by specific sub-layers to select the + * appropriate target/die and generate a row address to pass to the device. + */ +struct nand_pos { + unsigned int target; + unsigned int lun; + unsigned int plane; + unsigned int eraseblock; + unsigned int page; +}; + +/** + * struct nand_page_io_req - NAND I/O request object + * @pos: the position this I/O request is targeting + * @dataoffs: the offset within the page + * @datalen: number of data bytes to read from/write to this page + * @databuf: buffer to store data in or get data from + * @ooboffs: the OOB offset within the page + * @ooblen: the number of OOB bytes to read from/write to this page + * @oobbuf: buffer to store OOB data in or get OOB data from + * + * This object is used to pass per-page I/O requests to NAND sub-layers. This + * way all useful information are already formatted in a useful way and + * specific NAND layers can focus on translating these information into + * specific commands/operations. + */ +struct nand_page_io_req { + struct nand_pos pos; + unsigned int dataoffs; + unsigned int datalen; + union { + const void *out; + void *in; + } databuf; + unsigned int ooboffs; + unsigned int ooblen; + union { + const void *out; + void *in; + } oobbuf; +}; + +/** + * struct nand_ecc_req - NAND ECC requirements + * @strength: ECC strength + * @step_size: ECC step/block size + */ +struct nand_ecc_req { + unsigned int strength; + unsigned int step_size; +}; + +#define NAND_ECCREQ(str, stp) { .strength = (str), .step_size = (stp) } + +/** + * struct nand_bbt - bad block table object + * @cache: in memory BBT cache + */ +struct nand_bbt { + unsigned long *cache; +}; + +struct nand_device; + +/** + * struct nand_ops - NAND operations + * @erase: erase a specific block. No need to check if the block is bad before + * erasing, this has been taken care of by the generic NAND layer + * @markbad: mark a specific block bad. No need to check if the block is + * already marked bad, this has been taken care of by the generic + * NAND layer. This method should just write the BBM (Bad Block + * Marker) so that future call to struct_nand_ops->isbad() return + * true + * @isbad: check whether a block is bad or not. This method should just read + * the BBM and return whether the block is bad or not based on what it + * reads + * + * These are all low level operations that should be implemented by specialized + * NAND layers (SPI NAND, raw NAND, ...). + */ +struct nand_ops { + int (*erase)(struct nand_device *nand, const struct nand_pos *pos); + int (*markbad)(struct nand_device *nand, const struct nand_pos *pos); + bool (*isbad)(struct nand_device *nand, const struct nand_pos *pos); +}; + +/** + * struct nand_device - NAND device + * @mtd: MTD instance attached to the NAND device + * @memorg: memory layout + * @eccreq: ECC requirements + * @rowconv: position to row address converter + * @bbt: bad block table info + * @ops: NAND operations attached to the NAND device + * + * Generic NAND object. Specialized NAND layers (raw NAND, SPI NAND, OneNAND) + * should declare their own NAND object embedding a nand_device struct (that's + * how inheritance is done). + * struct_nand_device->memorg and struct_nand_device->eccreq should be filled + * at device detection time to reflect the NAND device + * capabilities/requirements. Once this is done nanddev_init() can be called. + * It will take care of converting NAND information into MTD ones, which means + * the specialized NAND layers should never manually tweak + * struct_nand_device->mtd except for the ->_read/write() hooks. + */ +struct nand_device { + struct mtd_info mtd; + struct nand_memory_organization memorg; + struct nand_ecc_req eccreq; + struct nand_row_converter rowconv; + struct nand_bbt bbt; + const struct nand_ops *ops; +}; + +/** + * struct nand_io_iter - NAND I/O iterator + * @req: current I/O request + * @oobbytes_per_page: maximum number of OOB bytes per page + * @dataleft: remaining number of data bytes to read/write + * @oobleft: remaining number of OOB bytes to read/write + * + * Can be used by specialized NAND layers to iterate over all pages covered + * by an MTD I/O request, which should greatly simplifies the boiler-plate + * code needed to read/write data from/to a NAND device. + */ +struct nand_io_iter { + struct nand_page_io_req req; + unsigned int oobbytes_per_page; + unsigned int dataleft; + unsigned int oobleft; +}; + +/** + * mtd_to_nanddev() - Get the NAND device attached to the MTD instance + * @mtd: MTD instance + * + * Return: the NAND device embedding @mtd. + */ +static inline struct nand_device *mtd_to_nanddev(struct mtd_info *mtd) +{ + return container_of(mtd, struct nand_device, mtd); +} + +/** + * nanddev_to_mtd() - Get the MTD device attached to a NAND device + * @nand: NAND device + * + * Return: the MTD device embedded in @nand. + */ +static inline struct mtd_info *nanddev_to_mtd(struct nand_device *nand) +{ + return &nand->mtd; +} + +/* + * nanddev_bits_per_cell() - Get the number of bits per cell + * @nand: NAND device + * + * Return: the number of bits per cell. + */ +static inline unsigned int nanddev_bits_per_cell(const struct nand_device *nand) +{ + return nand->memorg.bits_per_cell; +} + +/** + * nanddev_page_size() - Get NAND page size + * @nand: NAND device + * + * Return: the page size. + */ +static inline size_t nanddev_page_size(const struct nand_device *nand) +{ + return nand->memorg.pagesize; +} + +/** + * nanddev_per_page_oobsize() - Get NAND OOB size + * @nand: NAND device + * + * Return: the OOB size. + */ +static inline unsigned int +nanddev_per_page_oobsize(const struct nand_device *nand) +{ + return nand->memorg.oobsize; +} + +/** + * nanddev_pages_per_eraseblock() - Get the number of pages per eraseblock + * @nand: NAND device + * + * Return: the number of pages per eraseblock. + */ +static inline unsigned int +nanddev_pages_per_eraseblock(const struct nand_device *nand) +{ + return nand->memorg.pages_per_eraseblock; +} + +/** + * nanddev_per_page_oobsize() - Get NAND erase block size + * @nand: NAND device + * + * Return: the eraseblock size. + */ +static inline size_t nanddev_eraseblock_size(const struct nand_device *nand) +{ + return nand->memorg.pagesize * nand->memorg.pages_per_eraseblock; +} + +/** + * nanddev_eraseblocks_per_lun() - Get the number of eraseblocks per LUN + * @nand: NAND device + * + * Return: the number of eraseblocks per LUN. + */ +static inline unsigned int +nanddev_eraseblocks_per_lun(const struct nand_device *nand) +{ + return nand->memorg.eraseblocks_per_lun; +} + +/** + * nanddev_target_size() - Get the total size provided by a single target/die + * @nand: NAND device + * + * Return: the total size exposed by a single target/die in bytes. + */ +static inline u64 nanddev_target_size(const struct nand_device *nand) +{ + return (u64)nand->memorg.luns_per_target * + nand->memorg.eraseblocks_per_lun * + nand->memorg.pages_per_eraseblock * + nand->memorg.pagesize; +} + +/** + * nanddev_ntarget() - Get the total of targets + * @nand: NAND device + * + * Return: the number of targets/dies exposed by @nand. + */ +static inline unsigned int nanddev_ntargets(const struct nand_device *nand) +{ + return nand->memorg.ntargets; +} + +/** + * nanddev_neraseblocks() - Get the total number of erasablocks + * @nand: NAND device + * + * Return: the total number of eraseblocks exposed by @nand. + */ +static inline unsigned int nanddev_neraseblocks(const struct nand_device *nand) +{ + return (u64)nand->memorg.luns_per_target * + nand->memorg.eraseblocks_per_lun * + nand->memorg.pages_per_eraseblock; +} + +/** + * nanddev_size() - Get NAND size + * @nand: NAND device + * + * Return: the total size (in bytes) exposed by @nand. + */ +static inline u64 nanddev_size(const struct nand_device *nand) +{ + return nanddev_target_size(nand) * nanddev_ntargets(nand); +} + +/** + * nanddev_get_memorg() - Extract memory organization info from a NAND device + * @nand: NAND device + * + * This can be used by the upper layer to fill the memorg info before calling + * nanddev_init(). + * + * Return: the memorg object embedded in the NAND device. + */ +static inline struct nand_memory_organization * +nanddev_get_memorg(struct nand_device *nand) +{ + return &nand->memorg; +} + +int nanddev_init(struct nand_device *nand, const struct nand_ops *ops, + struct module *owner); +void nanddev_cleanup(struct nand_device *nand); + +/** + * nanddev_register() - Register a NAND device + * @nand: NAND device + * + * Register a NAND device. + * This function is just a wrapper around mtd_device_register() + * registering the MTD device embedded in @nand. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +static inline int nanddev_register(struct nand_device *nand) +{ + return mtd_device_register(&nand->mtd, NULL, 0); +} + +/** + * nanddev_unregister() - Unregister a NAND device + * @nand: NAND device + * + * Unregister a NAND device. + * This function is just a wrapper around mtd_device_unregister() + * unregistering the MTD device embedded in @nand. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +static inline int nanddev_unregister(struct nand_device *nand) +{ + return mtd_device_unregister(&nand->mtd); +} + +/** + * nanddev_set_of_node() - Attach a DT node to a NAND device + * @nand: NAND device + * @np: DT node + * + * Attach a DT node to a NAND device. + */ +static inline void nanddev_set_of_node(struct nand_device *nand, + struct device_node *np) +{ + mtd_set_of_node(&nand->mtd, np); +} + +/** + * nanddev_get_of_node() - Retrieve the DT node attached to a NAND device + * @nand: NAND device + * + * Return: the DT node attached to @nand. + */ +static inline struct device_node *nanddev_get_of_node(struct nand_device *nand) +{ + return mtd_get_of_node(&nand->mtd); +} + +/** + * nanddev_offs_to_pos() - Convert an absolute NAND offset into a NAND position + * @nand: NAND device + * @offs: absolute NAND offset (usually passed by the MTD layer) + * @pos: a NAND position object to fill in + * + * Converts @offs into a nand_pos representation. + * + * Return: the offset within the NAND page pointed by @pos. + */ +static inline unsigned int nanddev_offs_to_pos(struct nand_device *nand, + loff_t offs, + struct nand_pos *pos) +{ + unsigned int pageoffs; + u64 tmp = offs; + + pageoffs = do_div(tmp, nand->memorg.pagesize); + pos->page = do_div(tmp, nand->memorg.pages_per_eraseblock); + pos->eraseblock = do_div(tmp, nand->memorg.eraseblocks_per_lun); + pos->plane = pos->eraseblock % nand->memorg.planes_per_lun; + pos->lun = do_div(tmp, nand->memorg.luns_per_target); + pos->target = tmp; + + return pageoffs; +} + +/** + * nanddev_pos_cmp() - Compare two NAND positions + * @a: First NAND position + * @b: Second NAND position + * + * Compares two NAND positions. + * + * Return: -1 if @a < @b, 0 if @a == @b and 1 if @a > @b. + */ +static inline int nanddev_pos_cmp(const struct nand_pos *a, + const struct nand_pos *b) +{ + if (a->target != b->target) + return a->target < b->target ? -1 : 1; + + if (a->lun != b->lun) + return a->lun < b->lun ? -1 : 1; + + if (a->eraseblock != b->eraseblock) + return a->eraseblock < b->eraseblock ? -1 : 1; + + if (a->page != b->page) + return a->page < b->page ? -1 : 1; + + return 0; +} + +/** + * nanddev_pos_to_offs() - Convert a NAND position into an absolute offset + * @nand: NAND device + * @pos: the NAND position to convert + * + * Converts @pos NAND position into an absolute offset. + * + * Return: the absolute offset. Note that @pos points to the beginning of a + * page, if one wants to point to a specific offset within this page + * the returned offset has to be adjusted manually. + */ +static inline loff_t nanddev_pos_to_offs(struct nand_device *nand, + const struct nand_pos *pos) +{ + unsigned int npages; + + npages = pos->page + + ((pos->eraseblock + + (pos->lun + + (pos->target * nand->memorg.luns_per_target)) * + nand->memorg.eraseblocks_per_lun) * + nand->memorg.pages_per_eraseblock); + + return (loff_t)npages * nand->memorg.pagesize; +} + +/** + * nanddev_pos_to_row() - Extract a row address from a NAND position + * @nand: NAND device + * @pos: the position to convert + * + * Converts a NAND position into a row address that can then be passed to the + * device. + * + * Return: the row address extracted from @pos. + */ +static inline unsigned int nanddev_pos_to_row(struct nand_device *nand, + const struct nand_pos *pos) +{ + return (pos->lun << nand->rowconv.lun_addr_shift) | + (pos->eraseblock << nand->rowconv.eraseblock_addr_shift) | + pos->page; +} + +/** + * nanddev_pos_next_target() - Move a position to the next target/die + * @nand: NAND device + * @pos: the position to update + * + * Updates @pos to point to the start of the next target/die. Useful when you + * want to iterate over all targets/dies of a NAND device. + */ +static inline void nanddev_pos_next_target(struct nand_device *nand, + struct nand_pos *pos) +{ + pos->page = 0; + pos->plane = 0; + pos->eraseblock = 0; + pos->lun = 0; + pos->target++; +} + +/** + * nanddev_pos_next_lun() - Move a position to the next LUN + * @nand: NAND device + * @pos: the position to update + * + * Updates @pos to point to the start of the next LUN. Useful when you want to + * iterate over all LUNs of a NAND device. + */ +static inline void nanddev_pos_next_lun(struct nand_device *nand, + struct nand_pos *pos) +{ + if (pos->lun >= nand->memorg.luns_per_target - 1) + return nanddev_pos_next_target(nand, pos); + + pos->lun++; + pos->page = 0; + pos->plane = 0; + pos->eraseblock = 0; +} + +/** + * nanddev_pos_next_eraseblock() - Move a position to the next eraseblock + * @nand: NAND device + * @pos: the position to update + * + * Updates @pos to point to the start of the next eraseblock. Useful when you + * want to iterate over all eraseblocks of a NAND device. + */ +static inline void nanddev_pos_next_eraseblock(struct nand_device *nand, + struct nand_pos *pos) +{ + if (pos->eraseblock >= nand->memorg.eraseblocks_per_lun - 1) + return nanddev_pos_next_lun(nand, pos); + + pos->eraseblock++; + pos->page = 0; + pos->plane = pos->eraseblock % nand->memorg.planes_per_lun; +} + +/** + * nanddev_pos_next_eraseblock() - Move a position to the next page + * @nand: NAND device + * @pos: the position to update + * + * Updates @pos to point to the start of the next page. Useful when you want to + * iterate over all pages of a NAND device. + */ +static inline void nanddev_pos_next_page(struct nand_device *nand, + struct nand_pos *pos) +{ + if (pos->page >= nand->memorg.pages_per_eraseblock - 1) + return nanddev_pos_next_eraseblock(nand, pos); + + pos->page++; +} + +/** + * nand_io_iter_init - Initialize a NAND I/O iterator + * @nand: NAND device + * @offs: absolute offset + * @req: MTD request + * @iter: NAND I/O iterator + * + * Initializes a NAND iterator based on the information passed by the MTD + * layer. + */ +static inline void nanddev_io_iter_init(struct nand_device *nand, + loff_t offs, struct mtd_oob_ops *req, + struct nand_io_iter *iter) +{ + struct mtd_info *mtd = nanddev_to_mtd(nand); + + iter->req.dataoffs = nanddev_offs_to_pos(nand, offs, &iter->req.pos); + iter->req.ooboffs = req->ooboffs; + iter->oobbytes_per_page = mtd_oobavail(mtd, req); + iter->dataleft = req->len; + iter->oobleft = req->ooblen; + iter->req.databuf.in = req->datbuf; + iter->req.datalen = min_t(unsigned int, + nand->memorg.pagesize - iter->req.dataoffs, + iter->dataleft); + iter->req.oobbuf.in = req->oobbuf; + iter->req.ooblen = min_t(unsigned int, + iter->oobbytes_per_page - iter->req.ooboffs, + iter->oobleft); +} + +/** + * nand_io_iter_next_page - Move to the next page + * @nand: NAND device + * @iter: NAND I/O iterator + * + * Updates the @iter to point to the next page. + */ +static inline void nanddev_io_iter_next_page(struct nand_device *nand, + struct nand_io_iter *iter) +{ + nanddev_pos_next_page(nand, &iter->req.pos); + iter->dataleft -= iter->req.datalen; + iter->req.databuf.in += iter->req.datalen; + iter->oobleft -= iter->req.ooblen; + iter->req.oobbuf.in += iter->req.ooblen; + iter->req.dataoffs = 0; + iter->req.ooboffs = 0; + iter->req.datalen = min_t(unsigned int, nand->memorg.pagesize, + iter->dataleft); + iter->req.ooblen = min_t(unsigned int, iter->oobbytes_per_page, + iter->oobleft); +} + +/** + * nand_io_iter_end - Should end iteration or not + * @nand: NAND device + * @iter: NAND I/O iterator + * + * Check whether @iter has reached the end of the NAND portion it was asked to + * iterate on or not. + * + * Return: true if @iter has reached the end of the iteration request, false + * otherwise. + */ +static inline bool nanddev_io_iter_end(struct nand_device *nand, + const struct nand_io_iter *iter) +{ + if (iter->dataleft || iter->oobleft) + return false; + + return true; +} + +/** + * nand_io_for_each_page - Iterate over all NAND pages contained in an MTD I/O + * request + * @nand: NAND device + * @start: start address to read/write from + * @req: MTD I/O request + * @iter: NAND I/O iterator + * + * Should be used for iterate over pages that are contained in an MTD request. + */ +#define nanddev_io_for_each_page(nand, start, req, iter) \ + for (nanddev_io_iter_init(nand, start, req, iter); \ + !nanddev_io_iter_end(nand, iter); \ + nanddev_io_iter_next_page(nand, iter)) + +bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos); +bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos); +int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos); +int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos); + +/* BBT related functions */ +enum nand_bbt_block_status { + NAND_BBT_BLOCK_STATUS_UNKNOWN, + NAND_BBT_BLOCK_GOOD, + NAND_BBT_BLOCK_WORN, + NAND_BBT_BLOCK_RESERVED, + NAND_BBT_BLOCK_FACTORY_BAD, + NAND_BBT_BLOCK_NUM_STATUS, +}; + +int nanddev_bbt_init(struct nand_device *nand); +void nanddev_bbt_cleanup(struct nand_device *nand); +int nanddev_bbt_update(struct nand_device *nand); +int nanddev_bbt_get_block_status(const struct nand_device *nand, + unsigned int entry); +int nanddev_bbt_set_block_status(struct nand_device *nand, unsigned int entry, + enum nand_bbt_block_status status); +int nanddev_bbt_markbad(struct nand_device *nand, unsigned int block); + +/** + * nanddev_bbt_pos_to_entry() - Convert a NAND position into a BBT entry + * @nand: NAND device + * @pos: the NAND position we want to get BBT entry for + * + * Return the BBT entry used to store information about the eraseblock pointed + * by @pos. + * + * Return: the BBT entry storing information about eraseblock pointed by @pos. + */ +static inline unsigned int nanddev_bbt_pos_to_entry(struct nand_device *nand, + const struct nand_pos *pos) +{ + return pos->eraseblock + + ((pos->lun + (pos->target * nand->memorg.luns_per_target)) * + nand->memorg.eraseblocks_per_lun); +} + +/** + * nanddev_bbt_is_initialized() - Check if the BBT has been initialized + * @nand: NAND device + * + * Return: true if the BBT has been initialized, false otherwise. + */ +static inline bool nanddev_bbt_is_initialized(struct nand_device *nand) +{ + return !!nand->bbt.cache; +} + +/* MTD -> NAND helper functions. */ +int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo); + +#endif /* __LINUX_MTD_NAND_H */ -- cgit v1.2.3 From 6de0b13cc0b4ba10e98a9263d7a83b940720b77a Mon Sep 17 00:00:00 2001 From: Aaron Ma Date: Mon, 8 Jan 2018 10:41:41 +0800 Subject: HID: core: Fix size as type u32 When size is negative, calling memset will make segment fault. Declare the size as type u32 to keep memset safe. size in struct hid_report is unsigned, fix return type of hid_report_len to u32. Cc: stable@vger.kernel.org Signed-off-by: Aaron Ma Signed-off-by: Jiri Kosina --- drivers/hid/hid-core.c | 10 +++++----- include/linux/hid.h | 6 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index c2560aae5542..4fc08c38bc0e 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -1365,7 +1365,7 @@ u8 *hid_alloc_report_buf(struct hid_report *report, gfp_t flags) * of implement() working on 8 byte chunks */ - int len = hid_report_len(report) + 7; + u32 len = hid_report_len(report) + 7; return kmalloc(len, flags); } @@ -1430,7 +1430,7 @@ void __hid_request(struct hid_device *hid, struct hid_report *report, { char *buf; int ret; - int len; + u32 len; buf = hid_alloc_report_buf(report, GFP_KERNEL); if (!buf) @@ -1456,14 +1456,14 @@ out: } EXPORT_SYMBOL_GPL(__hid_request); -int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, int size, +int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, u32 size, int interrupt) { struct hid_report_enum *report_enum = hid->report_enum + type; struct hid_report *report; struct hid_driver *hdrv; unsigned int a; - int rsize, csize = size; + u32 rsize, csize = size; u8 *cdata = data; int ret = 0; @@ -1521,7 +1521,7 @@ EXPORT_SYMBOL_GPL(hid_report_raw_event); * * This is data entry for lower layers. */ -int hid_input_report(struct hid_device *hid, int type, u8 *data, int size, int interrupt) +int hid_input_report(struct hid_device *hid, int type, u8 *data, u32 size, int interrupt) { struct hid_report_enum *report_enum; struct hid_driver *hdrv; diff --git a/include/linux/hid.h b/include/linux/hid.h index 091a81cf330f..0efe80b59156 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -851,7 +851,7 @@ extern int hidinput_connect(struct hid_device *hid, unsigned int force); extern void hidinput_disconnect(struct hid_device *); int hid_set_field(struct hid_field *, unsigned, __s32); -int hid_input_report(struct hid_device *, int type, u8 *, int, int); +int hid_input_report(struct hid_device *, int type, u8 *, u32, int); int hidinput_find_field(struct hid_device *hid, unsigned int type, unsigned int code, struct hid_field **field); struct hid_field *hidinput_get_led_field(struct hid_device *hid); unsigned int hidinput_count_leds(struct hid_device *hid); @@ -1102,13 +1102,13 @@ static inline void hid_hw_wait(struct hid_device *hdev) * * @report: the report we want to know the length */ -static inline int hid_report_len(struct hid_report *report) +static inline u32 hid_report_len(struct hid_report *report) { /* equivalent to DIV_ROUND_UP(report->size, 8) + !!(report->id > 0) */ return ((report->size - 1) >> 3) + 1 + (report->id > 0); } -int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, int size, +int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, u32 size, int interrupt); /* HID quirks API */ -- cgit v1.2.3 From 0957a2c1d97586893d5ba7ce864b1d7e0b82b162 Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Tue, 13 Feb 2018 08:22:36 +1100 Subject: sched/wait: add wait_event_idle() functions. The new TASK_IDLE state (TASK_UNINTERRUPTIBLE | __TASK_NOLOAD) is not much used. One way to make it easier to use is to add wait_event*() family functions that make use of it. This patch adds: wait_event_idle() wait_event_idle_timeout() wait_event_idle_exclusive() wait_event_idle_exclusive_timeout() This set was chosen because lustre needs them before it can discard its own l_wait_event() macro. Acked-by: Peter Zijlstra (Intel) Reviewed-by: James Simmons Signed-off-by: NeilBrown Reviewed-by: Patrick Farrell Signed-off-by: Greg Kroah-Hartman --- include/linux/wait.h | 114 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) (limited to 'include/linux') diff --git a/include/linux/wait.h b/include/linux/wait.h index 55a611486bac..d9f131ecf708 100644 --- a/include/linux/wait.h +++ b/include/linux/wait.h @@ -599,6 +599,120 @@ do { \ __ret; \ }) +/** + * wait_event_idle - wait for a condition without contributing to system load + * @wq_head: the waitqueue to wait on + * @condition: a C expression for the event to wait for + * + * The process is put to sleep (TASK_IDLE) until the + * @condition evaluates to true. + * The @condition is checked each time the waitqueue @wq_head is woken up. + * + * wake_up() has to be called after changing any variable that could + * change the result of the wait condition. + * + */ +#define wait_event_idle(wq_head, condition) \ +do { \ + might_sleep(); \ + if (!(condition)) \ + ___wait_event(wq_head, condition, TASK_IDLE, 0, 0, schedule()); \ +} while (0) + +/** + * wait_event_idle_exclusive - wait for a condition with contributing to system load + * @wq_head: the waitqueue to wait on + * @condition: a C expression for the event to wait for + * + * The process is put to sleep (TASK_IDLE) until the + * @condition evaluates to true. + * The @condition is checked each time the waitqueue @wq_head is woken up. + * + * The process is put on the wait queue with an WQ_FLAG_EXCLUSIVE flag + * set thus if other processes wait on the same list, when this + * process is woken further processes are not considered. + * + * wake_up() has to be called after changing any variable that could + * change the result of the wait condition. + * + */ +#define wait_event_idle_exclusive(wq_head, condition) \ +do { \ + might_sleep(); \ + if (!(condition)) \ + ___wait_event(wq_head, condition, TASK_IDLE, 1, 0, schedule()); \ +} while (0) + +#define __wait_event_idle_timeout(wq_head, condition, timeout) \ + ___wait_event(wq_head, ___wait_cond_timeout(condition), \ + TASK_IDLE, 0, timeout, \ + __ret = schedule_timeout(__ret)) + +/** + * wait_event_idle_timeout - sleep without load until a condition becomes true or a timeout elapses + * @wq_head: the waitqueue to wait on + * @condition: a C expression for the event to wait for + * @timeout: timeout, in jiffies + * + * The process is put to sleep (TASK_IDLE) until the + * @condition evaluates to true. The @condition is checked each time + * the waitqueue @wq_head is woken up. + * + * wake_up() has to be called after changing any variable that could + * change the result of the wait condition. + * + * Returns: + * 0 if the @condition evaluated to %false after the @timeout elapsed, + * 1 if the @condition evaluated to %true after the @timeout elapsed, + * or the remaining jiffies (at least 1) if the @condition evaluated + * to %true before the @timeout elapsed. + */ +#define wait_event_idle_timeout(wq_head, condition, timeout) \ +({ \ + long __ret = timeout; \ + might_sleep(); \ + if (!___wait_cond_timeout(condition)) \ + __ret = __wait_event_idle_timeout(wq_head, condition, timeout); \ + __ret; \ +}) + +#define __wait_event_idle_exclusive_timeout(wq_head, condition, timeout) \ + ___wait_event(wq_head, ___wait_cond_timeout(condition), \ + TASK_IDLE, 1, timeout, \ + __ret = schedule_timeout(__ret)) + +/** + * wait_event_idle_exclusive_timeout - sleep without load until a condition becomes true or a timeout elapses + * @wq_head: the waitqueue to wait on + * @condition: a C expression for the event to wait for + * @timeout: timeout, in jiffies + * + * The process is put to sleep (TASK_IDLE) until the + * @condition evaluates to true. The @condition is checked each time + * the waitqueue @wq_head is woken up. + * + * The process is put on the wait queue with an WQ_FLAG_EXCLUSIVE flag + * set thus if other processes wait on the same list, when this + * process is woken further processes are not considered. + * + * wake_up() has to be called after changing any variable that could + * change the result of the wait condition. + * + * Returns: + * 0 if the @condition evaluated to %false after the @timeout elapsed, + * 1 if the @condition evaluated to %true after the @timeout elapsed, + * or the remaining jiffies (at least 1) if the @condition evaluated + * to %true before the @timeout elapsed. + */ +#define wait_event_idle_exclusive_timeout(wq_head, condition, timeout) \ +({ \ + long __ret = timeout; \ + might_sleep(); \ + if (!___wait_cond_timeout(condition)) \ + __ret = __wait_event_idle_exclusive_timeout(wq_head, condition, timeout);\ + __ret; \ +}) + extern int do_wait_intr(wait_queue_head_t *, wait_queue_entry_t *); extern int do_wait_intr_irq(wait_queue_head_t *, wait_queue_entry_t *); -- cgit v1.2.3 From 5cf0c37a71da0f3a4802806c597b21d99c33ca60 Mon Sep 17 00:00:00 2001 From: Sinan Kaya Date: Tue, 19 Dec 2017 00:38:02 -0500 Subject: PCI: Remove pci_get_bus_and_slot() function pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as where a PCI device is present. This restricts the device drivers to be reused for other domain numbers. Now that all users of pci_get_bus_and_slot() switched to pci_get_domain_bus_and_slot(), it is now safe to remove this function. Signed-off-by: Sinan Kaya Signed-off-by: Bjorn Helgaas --- include/linux/pci.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1beda008..25b7a3535d26 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -949,11 +949,6 @@ struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, unsigned int devfn); -static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, - unsigned int devfn) -{ - return pci_get_domain_bus_and_slot(0, bus, devfn); -} struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); int pci_dev_present(const struct pci_device_id *ids); @@ -1661,9 +1656,6 @@ static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn) { return NULL; } -static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, - unsigned int devfn) -{ return NULL; } static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, unsigned int devfn) { return NULL; } -- cgit v1.2.3 From e45e290a882e2c0dc8ebb7dd21c66a8209d8e3a5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 12 Feb 2018 14:16:57 +0100 Subject: regulator: core: Support passing an initialized GPIO enable descriptor We are currently passing a GPIO number from the global GPIO numberspace into the regulator core for handling enable GPIOs. This is not good since it ties into the global GPIO numberspace and uses gpio_to_desc() to overcome this. Start supporting passing an already initialized GPIO descriptor to the core instead: leaf drivers pick their descriptors, associated directly with the device node (or from ACPI or from a board descriptor table) and use that directly without any roundtrip over the global GPIO numberspace. This looks messy since it adds a bunch of extra code in the core, but at the end of the patch series we will delete the handling of the GPIO number and only deal with descriptors so things end up neat. Signed-off-by: Linus Walleij Signed-off-by: Mark Brown --- drivers/regulator/core.c | 25 ++++++++++++++++--------- include/linux/regulator/driver.h | 3 +++ 2 files changed, 19 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index dd4708c58480..4549b93b0ff9 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1937,7 +1937,10 @@ static int regulator_ena_gpio_request(struct regulator_dev *rdev, struct gpio_desc *gpiod; int ret; - gpiod = gpio_to_desc(config->ena_gpio); + if (config->ena_gpiod) + gpiod = config->ena_gpiod; + else + gpiod = gpio_to_desc(config->ena_gpio); list_for_each_entry(pin, ®ulator_ena_gpio_list, list) { if (pin->gpiod == gpiod) { @@ -1947,15 +1950,18 @@ static int regulator_ena_gpio_request(struct regulator_dev *rdev, } } - ret = gpio_request_one(config->ena_gpio, - GPIOF_DIR_OUT | config->ena_gpio_flags, - rdev_get_name(rdev)); - if (ret) - return ret; + if (!config->ena_gpiod) { + ret = gpio_request_one(config->ena_gpio, + GPIOF_DIR_OUT | config->ena_gpio_flags, + rdev_get_name(rdev)); + if (ret) + return ret; + } pin = kzalloc(sizeof(struct regulator_enable_gpio), GFP_KERNEL); if (pin == NULL) { - gpio_free(config->ena_gpio); + if (!config->ena_gpiod) + gpio_free(config->ena_gpio); return -ENOMEM; } @@ -4154,8 +4160,9 @@ regulator_register(const struct regulator_desc *regulator_desc, goto clean; } - if ((config->ena_gpio || config->ena_gpio_initialized) && - gpio_is_valid(config->ena_gpio)) { + if (config->ena_gpiod || + ((config->ena_gpio || config->ena_gpio_initialized) && + gpio_is_valid(config->ena_gpio))) { mutex_lock(®ulator_list_mutex); ret = regulator_ena_gpio_request(rdev, config); mutex_unlock(®ulator_list_mutex); diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index 4c00486b7a78..4fc96cb8e5d7 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -19,6 +19,7 @@ #include #include +struct gpio_desc; struct regmap; struct regulator_dev; struct regulator_config; @@ -387,6 +388,7 @@ struct regulator_desc { * initialized, meaning that >= 0 is a valid gpio * identifier and < 0 is a non existent gpio. * @ena_gpio: GPIO controlling regulator enable. + * @ena_gpiod: GPIO descriptor controlling regulator enable. * @ena_gpio_invert: Sense for GPIO enable control. * @ena_gpio_flags: Flags to use when calling gpio_request_one() */ @@ -399,6 +401,7 @@ struct regulator_config { bool ena_gpio_initialized; int ena_gpio; + struct gpio_desc *ena_gpiod; unsigned int ena_gpio_invert:1; unsigned int ena_gpio_flags; }; -- cgit v1.2.3 From 8d05560d1d011e5a842556efdbd70cc8a21499bb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 12 Feb 2018 14:17:00 +0100 Subject: regulator: da9055: Pass descriptor instead of GPIO number When setting up a fixed regulator on the DA9055, pass a descriptor instead of a global GPIO number. This facility is not used in the kernel so we can easily just say that this should be a descriptor if/when put to use. Signed-off-by: Linus Walleij Acked-by: Lee Jones Signed-off-by: Mark Brown --- drivers/regulator/da9055-regulator.c | 4 ++-- include/linux/mfd/da9055/pdata.h | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/drivers/regulator/da9055-regulator.c b/drivers/regulator/da9055-regulator.c index d029c941a1e1..f40c3b8644ae 100644 --- a/drivers/regulator/da9055-regulator.c +++ b/drivers/regulator/da9055-regulator.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -455,8 +456,7 @@ static int da9055_gpio_init(struct da9055_regulator *regulator, char name[18]; int gpio_mux = pdata->gpio_ren[id]; - config->ena_gpio = pdata->ena_gpio[id]; - config->ena_gpio_flags = GPIOF_OUT_INIT_HIGH; + config->ena_gpiod = pdata->ena_gpiods[id]; config->ena_gpio_invert = 1; /* diff --git a/include/linux/mfd/da9055/pdata.h b/include/linux/mfd/da9055/pdata.h index 04e092be4b07..1a94fa2ac309 100644 --- a/include/linux/mfd/da9055/pdata.h +++ b/include/linux/mfd/da9055/pdata.h @@ -12,6 +12,7 @@ #define DA9055_MAX_REGULATORS 8 struct da9055; +struct gpio_desc; enum gpio_select { NO_GPIO = 0, @@ -47,7 +48,7 @@ struct da9055_pdata { * controls the regulator set A/B, 0 if not available. */ enum gpio_select *reg_rsel; - /* GPIOs to enable regulator, 0 if not available */ - int *ena_gpio; + /* GPIO descriptors to enable regulator, NULL if not available */ + struct gpio_desc **ena_gpiods; }; #endif /* __DA9055_PDATA_H */ -- cgit v1.2.3 From 11da04af0d3b4c24ab057dd17f54dbc854d735de Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 12 Feb 2018 14:17:02 +0100 Subject: regulator: da9211: Pass descriptors instead of GPIO numbers This augments the DA9211 regulator driver to fetch its GPIO descriptors directly from the device tree using the newly exported devm_get_gpiod_from_child(). Signed-off-by: Linus Walleij Signed-off-by: Mark Brown --- drivers/regulator/da9211-regulator.c | 23 +++++++++++------------ include/linux/regulator/da9211.h | 4 +++- 2 files changed, 14 insertions(+), 13 deletions(-) (limited to 'include/linux') diff --git a/drivers/regulator/da9211-regulator.c b/drivers/regulator/da9211-regulator.c index 9b8f47617724..6c122b3df5d0 100644 --- a/drivers/regulator/da9211-regulator.c +++ b/drivers/regulator/da9211-regulator.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -25,7 +24,7 @@ #include #include #include -#include +#include #include #include #include "da9211-regulator.h" @@ -294,9 +293,12 @@ static struct da9211_pdata *da9211_parse_regulators_dt( pdata->init_data[n] = da9211_matches[i].init_data; pdata->reg_node[n] = da9211_matches[i].of_node; - pdata->gpio_ren[n] = - of_get_named_gpio(da9211_matches[i].of_node, - "enable-gpios", 0); + pdata->gpiod_ren[n] = devm_gpiod_get_from_of_node(dev, + da9211_matches[i].of_node, + "enable", + 0, + GPIOD_OUT_HIGH, + "da9211-enable"); n++; } @@ -382,13 +384,10 @@ static int da9211_regulator_init(struct da9211 *chip) config.regmap = chip->regmap; config.of_node = chip->pdata->reg_node[i]; - if (gpio_is_valid(chip->pdata->gpio_ren[i])) { - config.ena_gpio = chip->pdata->gpio_ren[i]; - config.ena_gpio_initialized = true; - } else { - config.ena_gpio = -EINVAL; - config.ena_gpio_initialized = false; - } + if (chip->pdata->gpiod_ren[i]) + config.ena_gpiod = chip->pdata->gpiod_ren[i]; + else + config.ena_gpiod = NULL; chip->rdev[i] = devm_regulator_register(chip->dev, &da9211_regulators[i], &config); diff --git a/include/linux/regulator/da9211.h b/include/linux/regulator/da9211.h index f2fd2d3bf58f..d1f2073e4d5f 100644 --- a/include/linux/regulator/da9211.h +++ b/include/linux/regulator/da9211.h @@ -21,6 +21,8 @@ #define DA9211_MAX_REGULATORS 2 +struct gpio_desc; + enum da9211_chip_id { DA9211, DA9212, @@ -39,7 +41,7 @@ struct da9211_pdata { * 2 : 2 phase 2 buck */ int num_buck; - int gpio_ren[DA9211_MAX_REGULATORS]; + struct gpio_desc *gpiod_ren[DA9211_MAX_REGULATORS]; struct device_node *reg_node[DA9211_MAX_REGULATORS]; struct regulator_init_data *init_data[DA9211_MAX_REGULATORS]; }; -- cgit v1.2.3 From 6f89dbce8e1134458de8a8e376acaaca4eee602e Mon Sep 17 00:00:00 2001 From: Sowmini Varadhan Date: Thu, 15 Feb 2018 10:49:32 -0800 Subject: skbuff: export mm_[un]account_pinned_pages for other modules RDS would like to use the helper functions for managing pinned pages added by Commit a91dbff551a6 ("sock: ulimit on MSG_ZEROCOPY pages") Signed-off-by: Sowmini Varadhan Acked-by: Willem de Bruijn Signed-off-by: David S. Miller --- include/linux/skbuff.h | 3 +++ net/core/skbuff.c | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 5ebc0f869720..b1cc38af53e1 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -466,6 +466,9 @@ struct ubuf_info { #define skb_uarg(SKB) ((struct ubuf_info *)(skb_shinfo(SKB)->destructor_arg)) +int mm_account_pinned_pages(struct mmpin *mmp, size_t size); +void mm_unaccount_pinned_pages(struct mmpin *mmp); + struct ubuf_info *sock_zerocopy_alloc(struct sock *sk, size_t size); struct ubuf_info *sock_zerocopy_realloc(struct sock *sk, size_t size, struct ubuf_info *uarg); diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 09bd89c90a71..1a7485a2cdfa 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -890,7 +890,7 @@ struct sk_buff *skb_morph(struct sk_buff *dst, struct sk_buff *src) } EXPORT_SYMBOL_GPL(skb_morph); -static int mm_account_pinned_pages(struct mmpin *mmp, size_t size) +int mm_account_pinned_pages(struct mmpin *mmp, size_t size) { unsigned long max_pg, num_pg, new_pg, old_pg; struct user_struct *user; @@ -919,14 +919,16 @@ static int mm_account_pinned_pages(struct mmpin *mmp, size_t size) return 0; } +EXPORT_SYMBOL_GPL(mm_account_pinned_pages); -static void mm_unaccount_pinned_pages(struct mmpin *mmp) +void mm_unaccount_pinned_pages(struct mmpin *mmp) { if (mmp->user) { atomic_long_sub(mmp->num_pg, &mmp->user->locked_vm); free_uid(mmp->user); } } +EXPORT_SYMBOL_GPL(mm_unaccount_pinned_pages); struct ubuf_info *sock_zerocopy_alloc(struct sock *sk, size_t size) { -- cgit v1.2.3 From bdec5a6b57896da81bc47262868468717a06bb69 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Sat, 17 Feb 2018 21:22:24 -0600 Subject: ARM: da8xx: use platform data for CFGCHIP syscon regmap This converts from using a platform device for the CFGCHIP syscon regmap to using platform data to pass the regmap to consumers. A lazy getter function is used so that the regmap will only be created if it is actually used. This function will also be used in the clock init when we convert to the common clock framework. The USB PHY driver is currently the only consumer. This driver is updated to use platform data to get the CFGCHIP regmap instead of syscon_regmap_lookup_by_pdevname(). Signed-off-by: David Lechner Acked-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-da830-evm.c | 4 --- arch/arm/mach-davinci/board-da850-evm.c | 4 --- arch/arm/mach-davinci/board-mityomapl138.c | 4 --- arch/arm/mach-davinci/board-omapl138-hawk.c | 4 --- arch/arm/mach-davinci/devices-da8xx.c | 45 +++++++++++++++-------------- arch/arm/mach-davinci/include/mach/da8xx.h | 3 +- arch/arm/mach-davinci/usb-da8xx.c | 6 ++++ drivers/phy/ti/phy-da8xx-usb.c | 8 +++-- include/linux/platform_data/phy-da8xx-usb.h | 21 ++++++++++++++ 9 files changed, 58 insertions(+), 41 deletions(-) create mode 100644 include/linux/platform_data/phy-da8xx-usb.h (limited to 'include/linux') diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index f673cd7a6766..f960cbef6538 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -551,10 +551,6 @@ static __init void da830_evm_init(void) struct davinci_soc_info *soc_info = &davinci_soc_info; int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - ret = da830_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index d898a94f6eae..26bdb10a8927 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1334,10 +1334,6 @@ static __init void da850_evm_init(void) { int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index b73ce7bae81f..9e7388ba413c 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -502,10 +502,6 @@ static void __init mityomapl138_init(void) { int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - /* for now, no special EDMA channels are reserved */ ret = da850_register_edma(NULL); if (ret) diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index a3e78074be70..baab7eb61632 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -281,10 +281,6 @@ static __init void omapl138_hawk_init(void) { int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index e1c40e73d30a..166bf29b1296 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -11,7 +11,6 @@ * (at your option) any later version. */ #include -#include #include #include #include @@ -1118,29 +1117,33 @@ int __init da850_register_sata(unsigned long refclkpn) } #endif -static struct syscon_platform_data da8xx_cfgchip_platform_data = { - .label = "cfgchip", -}; +static struct regmap *da8xx_cfgchip; -static struct resource da8xx_cfgchip_resources[] = { - { - .start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG, - .end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3, - .flags = IORESOURCE_MEM, - }, -}; +/* regmap doesn't make a copy of this, so we need to keep the pointer around */ +static const char da8xx_cfgchip_name[] = "cfgchip"; -static struct platform_device da8xx_cfgchip_device = { - .name = "syscon", - .id = -1, - .dev = { - .platform_data = &da8xx_cfgchip_platform_data, - }, - .num_resources = ARRAY_SIZE(da8xx_cfgchip_resources), - .resource = da8xx_cfgchip_resources, +static const struct regmap_config da8xx_cfgchip_config __initconst = { + .name = da8xx_cfgchip_name, + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, }; -int __init da8xx_register_cfgchip(void) +/** + * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap + * + * This is for use on non-DT boards only. For DT boards, use + * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") + * + * Returns: Pointer to the CFGCHIP regmap or negative error code. + */ +struct regmap * __init da8xx_get_cfgchip(void) { - return platform_device_register(&da8xx_cfgchip_device); + if (IS_ERR_OR_NULL(da8xx_cfgchip)) + da8xx_cfgchip = regmap_init_mmio(NULL, + DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), + &da8xx_cfgchip_config); + + return da8xx_cfgchip; } diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 93ff1569cee5..03f37ef4297f 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -123,7 +124,7 @@ void da8xx_rproc_reserve_cma(void); int da8xx_register_rproc(void); int da850_register_gpio(void); int da830_register_gpio(void); -int da8xx_register_cfgchip(void); +struct regmap *da8xx_get_cfgchip(void); extern struct platform_device da8xx_serial_device[]; extern struct emac_platform_data da8xx_emac_pdata; diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c index fb31f6eeba96..4d89d86ce7e5 100644 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,11 @@ static struct platform_device da8xx_usb_phy = { int __init da8xx_register_usb_phy(void) { + struct da8xx_usb_phy_platform_data pdata; + + pdata.cfgchip = da8xx_get_cfgchip(); + da8xx_usb_phy.dev.platform_data = &pdata; + return platform_device_register(&da8xx_usb_phy); } diff --git a/drivers/phy/ti/phy-da8xx-usb.c b/drivers/phy/ti/phy-da8xx-usb.c index 5bd33d06df95..befb886ff121 100644 --- a/drivers/phy/ti/phy-da8xx-usb.c +++ b/drivers/phy/ti/phy-da8xx-usb.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -145,6 +146,7 @@ static struct phy *da8xx_usb_phy_of_xlate(struct device *dev, static int da8xx_usb_phy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct da8xx_usb_phy_platform_data *pdata = dev->platform_data; struct device_node *node = dev->of_node; struct da8xx_usb_phy *d_phy; @@ -152,11 +154,11 @@ static int da8xx_usb_phy_probe(struct platform_device *pdev) if (!d_phy) return -ENOMEM; - if (node) + if (pdata) + d_phy->regmap = pdata->cfgchip; + else d_phy->regmap = syscon_regmap_lookup_by_compatible( "ti,da830-cfgchip"); - else - d_phy->regmap = syscon_regmap_lookup_by_pdevname("syscon"); if (IS_ERR(d_phy->regmap)) { dev_err(dev, "Failed to get syscon\n"); return PTR_ERR(d_phy->regmap); diff --git a/include/linux/platform_data/phy-da8xx-usb.h b/include/linux/platform_data/phy-da8xx-usb.h new file mode 100644 index 000000000000..85c2b99381b2 --- /dev/null +++ b/include/linux/platform_data/phy-da8xx-usb.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-da8xx-usb - TI DaVinci DA8xx USB PHY driver + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __LINUX_PLATFORM_DATA_PHY_DA8XX_USB_H__ +#define __LINUX_PLATFORM_DATA_PHY_DA8XX_USB_H__ + +#include + +/** + * da8xx_usb_phy_platform_data + * @cfgchip: CFGCHIP syscon regmap + */ +struct da8xx_usb_phy_platform_data { + struct regmap *cfgchip; +}; + +#endif /* __LINUX_PLATFORM_DATA_PHY_DA8XX_USB_H__ */ -- cgit v1.2.3 From 22e76844c566e474a9a3e0c2206e45766b5941b7 Mon Sep 17 00:00:00 2001 From: Srinivas Dasari Date: Tue, 6 Feb 2018 19:49:35 +0530 Subject: ieee80211: Increase PMK maximum length to 64 bytes Increase the PMK maximum length to 64 bytes to accommodate the key length used in DPP with the NIST P-521 and Brainpool 512 curves. Signed-off-by: Srinivas Dasari Signed-off-by: Johannes Berg --- include/linux/ieee80211.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index ee6657a0ed69..e4cba332b705 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h @@ -2111,7 +2111,7 @@ enum ieee80211_key_len { #define FILS_ERP_MAX_REALM_LEN 253 #define FILS_ERP_MAX_RRK_LEN 64 -#define PMK_MAX_LEN 48 +#define PMK_MAX_LEN 64 /* Public action codes (IEEE Std 802.11-2016, 9.6.8.1, Table 9-307) */ enum ieee80211_pub_actioncode { -- cgit v1.2.3 From e3f9f41757f5ce1e95ef3bc3bfb72bbcdb23ece2 Mon Sep 17 00:00:00 2001 From: Andrea Parri Date: Fri, 16 Feb 2018 12:06:13 +0100 Subject: ptr_ring: Remove now-redundant smp_read_barrier_depends() Because READ_ONCE() now implies smp_read_barrier_depends(), the smp_read_barrier_depends() in __ptr_ring_consume() is redundant; this commit removes it and updates the comments. Signed-off-by: Andrea Parri Cc: "David S. Miller" Cc: "Michael S. Tsirkin" Cc: Jason Wang Cc: John Fastabend Cc: Eric Dumazet Cc: Cc: Signed-off-by: David S. Miller --- include/linux/ptr_ring.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ptr_ring.h b/include/linux/ptr_ring.h index b884b7794187..ddfed1dce936 100644 --- a/include/linux/ptr_ring.h +++ b/include/linux/ptr_ring.h @@ -296,13 +296,14 @@ static inline void *__ptr_ring_consume(struct ptr_ring *r) { void *ptr; + /* The READ_ONCE in __ptr_ring_peek guarantees that anyone + * accessing data through the pointer is up to date. Pairs + * with smp_wmb in __ptr_ring_produce. + */ ptr = __ptr_ring_peek(r); if (ptr) __ptr_ring_discard_one(r); - /* Make sure anyone accessing data through the pointer is up to date. */ - /* Pairs with smp_wmb in __ptr_ring_produce. */ - smp_read_barrier_depends(); return ptr; } -- cgit v1.2.3 From 19efbd93e6fb05eab81856b4fc8d64211dd37088 Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Mon, 19 Feb 2018 12:58:38 +0300 Subject: net: Kill net_mutex We take net_mutex, when there are !async pernet_operations registered, and read locking of net_sem is not enough. But we may get rid of taking the mutex, and just change the logic to write lock net_sem in such cases. This obviously reduces the number of lock operations, we do. Signed-off-by: Kirill Tkhai Signed-off-by: David S. Miller --- include/linux/rtnetlink.h | 1 - include/net/net_namespace.h | 11 ++++++---- net/core/net_namespace.c | 53 +++++++++++++++++++++++++++------------------ 3 files changed, 39 insertions(+), 26 deletions(-) (limited to 'include/linux') diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index e9ee9ad0a681..3573b4bf2fdf 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -35,7 +35,6 @@ extern int rtnl_trylock(void); extern int rtnl_is_locked(void); extern wait_queue_head_t netdev_unregistering_wq; -extern struct mutex net_mutex; extern struct rw_semaphore net_sem; #ifdef CONFIG_PROVE_LOCKING diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h index 9158ec1ad06f..115b01b92f4d 100644 --- a/include/net/net_namespace.h +++ b/include/net/net_namespace.h @@ -60,8 +60,11 @@ struct net { struct list_head list; /* list of network namespaces */ struct list_head cleanup_list; /* namespaces on death row */ - struct list_head exit_list; /* Use only net_mutex */ - + struct list_head exit_list; /* To linked to call pernet exit + * methods on dead net (net_sem + * read locked), or to unregister + * pernet ops (net_sem wr locked). + */ struct user_namespace *user_ns; /* Owning user namespace */ struct ucounts *ucounts; spinlock_t nsid_lock; @@ -89,7 +92,7 @@ struct net { /* core fib_rules */ struct list_head rules_ops; - struct list_head fib_notifier_ops; /* protected by net_mutex */ + struct list_head fib_notifier_ops; /* protected by net_sem */ struct net_device *loopback_dev; /* The loopback */ struct netns_core core; @@ -316,7 +319,7 @@ struct pernet_operations { /* * Indicates above methods are allowed to be executed in parallel * with methods of any other pernet_operations, i.e. they are not - * need synchronization via net_mutex. + * need write locked net_sem. */ bool async; }; diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c index bcab9a938d6f..e89a516620dd 100644 --- a/net/core/net_namespace.c +++ b/net/core/net_namespace.c @@ -29,8 +29,6 @@ static LIST_HEAD(pernet_list); static struct list_head *first_device = &pernet_list; -/* Used only if there are !async pernet_operations registered */ -DEFINE_MUTEX(net_mutex); LIST_HEAD(net_namespace_list); EXPORT_SYMBOL_GPL(net_namespace_list); @@ -407,6 +405,7 @@ struct net *copy_net_ns(unsigned long flags, { struct ucounts *ucounts; struct net *net; + unsigned write; int rv; if (!(flags & CLONE_NEWNET)) @@ -424,20 +423,26 @@ struct net *copy_net_ns(unsigned long flags, refcount_set(&net->passive, 1); net->ucounts = ucounts; get_user_ns(user_ns); - - rv = down_read_killable(&net_sem); +again: + write = READ_ONCE(nr_sync_pernet_ops); + if (write) + rv = down_write_killable(&net_sem); + else + rv = down_read_killable(&net_sem); if (rv < 0) goto put_userns; - if (nr_sync_pernet_ops) { - rv = mutex_lock_killable(&net_mutex); - if (rv < 0) - goto up_read; + + if (!write && unlikely(READ_ONCE(nr_sync_pernet_ops))) { + up_read(&net_sem); + goto again; } rv = setup_net(net, user_ns); - if (nr_sync_pernet_ops) - mutex_unlock(&net_mutex); -up_read: - up_read(&net_sem); + + if (write) + up_write(&net_sem); + else + up_read(&net_sem); + if (rv < 0) { put_userns: put_user_ns(user_ns); @@ -485,15 +490,23 @@ static void cleanup_net(struct work_struct *work) struct net *net, *tmp, *last; struct list_head net_kill_list; LIST_HEAD(net_exit_list); + unsigned write; /* Atomically snapshot the list of namespaces to cleanup */ spin_lock_irq(&cleanup_list_lock); list_replace_init(&cleanup_list, &net_kill_list); spin_unlock_irq(&cleanup_list_lock); +again: + write = READ_ONCE(nr_sync_pernet_ops); + if (write) + down_write(&net_sem); + else + down_read(&net_sem); - down_read(&net_sem); - if (nr_sync_pernet_ops) - mutex_lock(&net_mutex); + if (!write && unlikely(READ_ONCE(nr_sync_pernet_ops))) { + up_read(&net_sem); + goto again; + } /* Don't let anyone else find us. */ rtnl_lock(); @@ -528,14 +541,14 @@ static void cleanup_net(struct work_struct *work) list_for_each_entry_reverse(ops, &pernet_list, list) ops_exit_list(ops, &net_exit_list); - if (nr_sync_pernet_ops) - mutex_unlock(&net_mutex); - /* Free the net generic variables */ list_for_each_entry_reverse(ops, &pernet_list, list) ops_free_list(ops, &net_exit_list); - up_read(&net_sem); + if (write) + up_write(&net_sem); + else + up_read(&net_sem); /* Ensure there are no outstanding rcu callbacks using this * network namespace. @@ -563,8 +576,6 @@ static void cleanup_net(struct work_struct *work) void net_ns_barrier(void) { down_write(&net_sem); - mutex_lock(&net_mutex); - mutex_unlock(&net_mutex); up_write(&net_sem); } EXPORT_SYMBOL(net_ns_barrier); -- cgit v1.2.3 From 30a050defbca46f60a04f22dc4306612eeaaf04b Mon Sep 17 00:00:00 2001 From: Lihao Liang Date: Thu, 21 Dec 2017 16:16:10 +0800 Subject: doc: Fix typo in rcu_head comments Signed-off-by: Lihao Liang Signed-off-by: Paul E. McKenney --- include/linux/types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/types.h b/include/linux/types.h index c94d59ef96cc..ec13d02b3481 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -217,7 +217,7 @@ struct ustat { * * This guarantee is important for few reasons: * - future call_rcu_lazy() will make use of lower bits in the pointer; - * - the structure shares storage spacer in struct page with @compound_head, + * - the structure shares storage space in struct page with @compound_head, * which encode PageTail() in bit 0. The guarantee is needed to avoid * false-positive PageTail(). */ -- cgit v1.2.3 From b5482a06593c851028b5dc061f9c8882bcc20008 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Tue, 23 Jan 2018 14:48:33 -0800 Subject: rcu: Fix init_rcu_head() comment. The current (and implicit) comment header for init_rcu_head() and destroy_rcu_head() incorrectly says that they are not needed for statically allocated rcu_head structures. This commit therefore fixes this comment. Reported-by: Bart Van Assche Signed-off-by: Paul E. McKenney Reviewed-by: Bart Van Assche Reviewed-by: Leon Romanovsky --- include/linux/rcupdate.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 043d04784675..36360d07f25b 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -214,10 +214,12 @@ do { \ #endif /* - * init_rcu_head_on_stack()/destroy_rcu_head_on_stack() are needed for dynamic - * initialization and destruction of rcu_head on the stack. rcu_head structures - * allocated dynamically in the heap or defined statically don't need any - * initialization. + * The init_rcu_head_on_stack() and destroy_rcu_head_on_stack() calls + * are needed for dynamic initialization and destruction of rcu_head + * on the stack, and init_rcu_head()/destroy_rcu_head() are needed for + * dynamic initialization and destruction of statically allocated rcu_head + * structures. However, rcu_head structures allocated dynamically in the + * heap don't need any initialization. */ #ifdef CONFIG_DEBUG_OBJECTS_RCU_HEAD void init_rcu_head(struct rcu_head *head); -- cgit v1.2.3 From a364298359e74a414857bbbf3b725564feb22d09 Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Wed, 21 Feb 2018 05:17:24 +0100 Subject: nohz: Convert tick_nohz_tick_stopped() to bool It makes this function more self-explanatory about what it does and how to use it. Reported-by: Thomas Gleixner Signed-off-by: Frederic Weisbecker Reviewed-by: Thomas Gleixner Acked-by: Peter Zijlstra Cc: Chris Metcalf Cc: Christoph Lameter Cc: Linus Torvalds Cc: Luiz Capitulino Cc: Mike Galbraith Cc: Paul E. McKenney Cc: Rik van Riel Cc: Wanpeng Li Link: http://lkml.kernel.org/r/1519186649-3242-3-git-send-email-frederic@kernel.org Signed-off-by: Ingo Molnar --- include/linux/tick.h | 2 +- kernel/time/tick-sched.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/tick.h b/include/linux/tick.h index 7cc35921218e..86576d9d2311 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -113,7 +113,7 @@ enum tick_dep_bits { #ifdef CONFIG_NO_HZ_COMMON extern bool tick_nohz_enabled; -extern int tick_nohz_tick_stopped(void); +extern bool tick_nohz_tick_stopped(void); extern void tick_nohz_idle_enter(void); extern void tick_nohz_idle_exit(void); extern void tick_nohz_irq_exit(void); diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index 29a5733eff83..0aba0412ede5 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -481,7 +481,7 @@ static int __init setup_tick_nohz(char *str) __setup("nohz=", setup_tick_nohz); -int tick_nohz_tick_stopped(void) +bool tick_nohz_tick_stopped(void) { return __this_cpu_read(tick_cpu_sched.tick_stopped); } -- cgit v1.2.3 From 22ab8bc02a5f6e8ffc418759894f7a6b0b632331 Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Wed, 21 Feb 2018 05:17:25 +0100 Subject: nohz: Allow to check if remote CPU tick is stopped This check is racy but provides a good heuristic to determine whether a CPU may need a remote tick or not. Signed-off-by: Frederic Weisbecker Reviewed-by: Thomas Gleixner Acked-by: Peter Zijlstra Cc: Chris Metcalf Cc: Christoph Lameter Cc: Linus Torvalds Cc: Luiz Capitulino Cc: Mike Galbraith Cc: Paul E. McKenney Cc: Rik van Riel Cc: Wanpeng Li Link: http://lkml.kernel.org/r/1519186649-3242-4-git-send-email-frederic@kernel.org Signed-off-by: Ingo Molnar --- include/linux/tick.h | 2 ++ kernel/time/tick-sched.c | 7 +++++++ 2 files changed, 9 insertions(+) (limited to 'include/linux') diff --git a/include/linux/tick.h b/include/linux/tick.h index 86576d9d2311..7f8c9a127f5a 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -114,6 +114,7 @@ enum tick_dep_bits { #ifdef CONFIG_NO_HZ_COMMON extern bool tick_nohz_enabled; extern bool tick_nohz_tick_stopped(void); +extern bool tick_nohz_tick_stopped_cpu(int cpu); extern void tick_nohz_idle_enter(void); extern void tick_nohz_idle_exit(void); extern void tick_nohz_irq_exit(void); @@ -125,6 +126,7 @@ extern u64 get_cpu_iowait_time_us(int cpu, u64 *last_update_time); #else /* !CONFIG_NO_HZ_COMMON */ #define tick_nohz_enabled (0) static inline int tick_nohz_tick_stopped(void) { return 0; } +static inline int tick_nohz_tick_stopped_cpu(int cpu) { return 0; } static inline void tick_nohz_idle_enter(void) { } static inline void tick_nohz_idle_exit(void) { } diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index 0aba0412ede5..d479b21a848b 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -486,6 +486,13 @@ bool tick_nohz_tick_stopped(void) return __this_cpu_read(tick_cpu_sched.tick_stopped); } +bool tick_nohz_tick_stopped_cpu(int cpu) +{ + struct tick_sched *ts = per_cpu_ptr(&tick_cpu_sched, cpu); + + return ts->tick_stopped; +} + /** * tick_nohz_update_jiffies - update jiffies when idle was interrupted * -- cgit v1.2.3 From 1bda3f8087fce9063da0b8aef87f17a3fe541aca Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Wed, 21 Feb 2018 05:17:26 +0100 Subject: sched/isolation: Isolate workqueues when "nohz_full=" is set As we prepare for offloading the residual 1hz scheduler ticks to workqueue, let's affine those to housekeepers so that they don't interrupt the CPUs that don't want to be disturbed. Signed-off-by: Frederic Weisbecker Reviewed-by: Thomas Gleixner Acked-by: Peter Zijlstra Cc: Chris Metcalf Cc: Christoph Lameter Cc: Linus Torvalds Cc: Luiz Capitulino Cc: Mike Galbraith Cc: Paul E. McKenney Cc: Rik van Riel Cc: Wanpeng Li Link: http://lkml.kernel.org/r/1519186649-3242-5-git-send-email-frederic@kernel.org Signed-off-by: Ingo Molnar --- include/linux/sched/isolation.h | 1 + kernel/sched/isolation.c | 3 ++- kernel/workqueue.c | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched/isolation.h b/include/linux/sched/isolation.h index d849431c8060..4a6582c27dea 100644 --- a/include/linux/sched/isolation.h +++ b/include/linux/sched/isolation.h @@ -12,6 +12,7 @@ enum hk_flags { HK_FLAG_SCHED = (1 << 3), HK_FLAG_TICK = (1 << 4), HK_FLAG_DOMAIN = (1 << 5), + HK_FLAG_WQ = (1 << 6), }; #ifdef CONFIG_CPU_ISOLATION diff --git a/kernel/sched/isolation.c b/kernel/sched/isolation.c index b71b436f59f2..a2500c459617 100644 --- a/kernel/sched/isolation.c +++ b/kernel/sched/isolation.c @@ -3,6 +3,7 @@ * any CPU: unbound workqueues, timers, kthreads and any offloadable work. * * Copyright (C) 2017 Red Hat, Inc., Frederic Weisbecker + * Copyright (C) 2017-2018 SUSE, Frederic Weisbecker * */ @@ -119,7 +120,7 @@ static int __init housekeeping_nohz_full_setup(char *str) { unsigned int flags; - flags = HK_FLAG_TICK | HK_FLAG_TIMER | HK_FLAG_RCU | HK_FLAG_MISC; + flags = HK_FLAG_TICK | HK_FLAG_WQ | HK_FLAG_TIMER | HK_FLAG_RCU | HK_FLAG_MISC; return housekeeping_setup(str, flags); } diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 017044c26233..593dbe749174 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -5565,12 +5565,13 @@ static void __init wq_numa_init(void) int __init workqueue_init_early(void) { int std_nice[NR_STD_WORKER_POOLS] = { 0, HIGHPRI_NICE_LEVEL }; + int hk_flags = HK_FLAG_DOMAIN | HK_FLAG_WQ; int i, cpu; WARN_ON(__alignof__(struct pool_workqueue) < __alignof__(long long)); BUG_ON(!alloc_cpumask_var(&wq_unbound_cpumask, GFP_KERNEL)); - cpumask_copy(wq_unbound_cpumask, housekeeping_cpumask(HK_FLAG_DOMAIN)); + cpumask_copy(wq_unbound_cpumask, housekeeping_cpumask(hk_flags)); pwq_cache = KMEM_CACHE(pool_workqueue, SLAB_PANIC); -- cgit v1.2.3 From dcdedb24159be3487e3dbbe1faa79ae7d00c92ac Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Wed, 21 Feb 2018 05:17:28 +0100 Subject: sched/nohz: Remove the 1 Hz tick code Now that the 1Hz tick is offloaded to workqueues, we can safely remove the residual code that used to handle it locally. Signed-off-by: Frederic Weisbecker Reviewed-by: Thomas Gleixner Acked-by: Peter Zijlstra Cc: Chris Metcalf Cc: Christoph Lameter Cc: Linus Torvalds Cc: Luiz Capitulino Cc: Mike Galbraith Cc: Paul E. McKenney Cc: Rik van Riel Cc: Wanpeng Li Link: http://lkml.kernel.org/r/1519186649-3242-7-git-send-email-frederic@kernel.org Signed-off-by: Ingo Molnar --- include/linux/sched/nohz.h | 4 ---- kernel/sched/core.c | 29 ----------------------------- kernel/sched/idle_task.c | 1 - kernel/sched/sched.h | 11 +---------- kernel/time/tick-sched.c | 6 ------ 5 files changed, 1 insertion(+), 50 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched/nohz.h b/include/linux/sched/nohz.h index 3d3a97d9399d..094217273ff9 100644 --- a/include/linux/sched/nohz.h +++ b/include/linux/sched/nohz.h @@ -37,8 +37,4 @@ extern void wake_up_nohz_cpu(int cpu); static inline void wake_up_nohz_cpu(int cpu) { } #endif -#ifdef CONFIG_NO_HZ_FULL -extern u64 scheduler_tick_max_deferment(void); -#endif - #endif /* _LINUX_SCHED_NOHZ_H */ diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 5dfef458ab52..8fff4f16c510 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -3096,35 +3096,9 @@ void scheduler_tick(void) rq->idle_balance = idle_cpu(cpu); trigger_load_balance(rq); #endif - rq_last_tick_reset(rq); } #ifdef CONFIG_NO_HZ_FULL -/** - * scheduler_tick_max_deferment - * - * Keep at least one tick per second when a single - * active task is running because the scheduler doesn't - * yet completely support full dynticks environment. - * - * This makes sure that uptime, CFS vruntime, load - * balancing, etc... continue to move forward, even - * with a very low granularity. - * - * Return: Maximum deferment in nanoseconds. - */ -u64 scheduler_tick_max_deferment(void) -{ - struct rq *rq = this_rq(); - unsigned long next, now = READ_ONCE(jiffies); - - next = rq->last_sched_tick + HZ; - - if (time_before_eq(next, now)) - return 0; - - return jiffies_to_nsecs(next - now); -} struct tick_work { int cpu; @@ -6116,9 +6090,6 @@ void __init sched_init(void) rq->last_load_update_tick = jiffies; rq->nohz_flags = 0; #endif -#ifdef CONFIG_NO_HZ_FULL - rq->last_sched_tick = 0; -#endif #endif /* CONFIG_SMP */ hrtick_rq_init(rq); atomic_set(&rq->nr_iowait, 0); diff --git a/kernel/sched/idle_task.c b/kernel/sched/idle_task.c index e1b46e08c8e1..48b8a83f5185 100644 --- a/kernel/sched/idle_task.c +++ b/kernel/sched/idle_task.c @@ -48,7 +48,6 @@ dequeue_task_idle(struct rq *rq, struct task_struct *p, int flags) static void put_prev_task_idle(struct rq *rq, struct task_struct *prev) { - rq_last_tick_reset(rq); } /* diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index c1c7c788da1c..dc6c8b5a24ad 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -727,9 +727,7 @@ struct rq { #endif /* CONFIG_SMP */ unsigned long nohz_flags; #endif /* CONFIG_NO_HZ_COMMON */ -#ifdef CONFIG_NO_HZ_FULL - unsigned long last_sched_tick; -#endif + /* capture load from *all* tasks on this cpu: */ struct load_weight load; unsigned long nr_load_updates; @@ -1626,13 +1624,6 @@ static inline void sub_nr_running(struct rq *rq, unsigned count) sched_update_tick_dependency(rq); } -static inline void rq_last_tick_reset(struct rq *rq) -{ -#ifdef CONFIG_NO_HZ_FULL - rq->last_sched_tick = jiffies; -#endif -} - extern void update_rq_clock(struct rq *rq); extern void activate_task(struct rq *rq, struct task_struct *p, int flags); diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index d479b21a848b..f2fa2e940fe5 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -748,12 +748,6 @@ static ktime_t tick_nohz_stop_sched_tick(struct tick_sched *ts, delta = KTIME_MAX; } -#ifdef CONFIG_NO_HZ_FULL - /* Limit the tick delta to the maximum scheduler deferment */ - if (!ts->inidle) - delta = min(delta, scheduler_tick_max_deferment()); -#endif - /* Calculate the next expiry time */ if (delta < (KTIME_MAX - basemono)) expires = basemono + delta; -- cgit v1.2.3 From 285995d15d3b1725d021a8a274e55f2ce30ccfa0 Mon Sep 17 00:00:00 2001 From: Ognjen Galic Date: Wed, 7 Feb 2018 15:58:27 +0100 Subject: power: add to_power_supply macro to the API This patch adds the to_power_supply macro to upcast a device to a power_supply struct. This is needed because the same piece of code using container_of is used in various other places, so we abstract away such low-level operations via a macro. Suggested-by: Andy Shevchenko Reviewed-by: Andy Shevchenko Signed-off-by: Ognjen Galic Reviewed-by: Sebastian Reichel Signed-off-by: Rafael J. Wysocki --- drivers/power/supply/ds2780_battery.c | 5 ----- drivers/power/supply/ds2781_battery.c | 5 ----- drivers/power/supply/power_supply_core.c | 2 +- include/linux/power_supply.h | 2 ++ 4 files changed, 3 insertions(+), 11 deletions(-) (limited to 'include/linux') diff --git a/drivers/power/supply/ds2780_battery.c b/drivers/power/supply/ds2780_battery.c index e5d81b493c45..370e9109342b 100644 --- a/drivers/power/supply/ds2780_battery.c +++ b/drivers/power/supply/ds2780_battery.c @@ -56,11 +56,6 @@ to_ds2780_device_info(struct power_supply *psy) return power_supply_get_drvdata(psy); } -static inline struct power_supply *to_power_supply(struct device *dev) -{ - return dev_get_drvdata(dev); -} - static inline int ds2780_battery_io(struct ds2780_device_info *dev_info, char *buf, int addr, size_t count, int io) { diff --git a/drivers/power/supply/ds2781_battery.c b/drivers/power/supply/ds2781_battery.c index efe83ef8670c..d1b5a19aae7c 100644 --- a/drivers/power/supply/ds2781_battery.c +++ b/drivers/power/supply/ds2781_battery.c @@ -54,11 +54,6 @@ to_ds2781_device_info(struct power_supply *psy) return power_supply_get_drvdata(psy); } -static inline struct power_supply *to_power_supply(struct device *dev) -{ - return dev_get_drvdata(dev); -} - static inline int ds2781_battery_io(struct ds2781_device_info *dev_info, char *buf, int addr, size_t count, int io) { diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c index 82f998ab5a52..feac7b066e6c 100644 --- a/drivers/power/supply/power_supply_core.c +++ b/drivers/power/supply/power_supply_core.c @@ -668,7 +668,7 @@ EXPORT_SYMBOL_GPL(power_supply_powers); static void power_supply_dev_release(struct device *dev) { - struct power_supply *psy = container_of(dev, struct power_supply, dev); + struct power_supply *psy = to_power_supply(dev); dev_dbg(dev, "%s\n", __func__); kfree(psy); } diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 79e90b3d3288..f0139b460a72 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -371,6 +371,8 @@ devm_power_supply_register_no_ws(struct device *parent, extern void power_supply_unregister(struct power_supply *psy); extern int power_supply_powers(struct power_supply *psy, struct device *dev); +#define to_power_supply(device) container_of(device, struct power_supply, dev) + extern void *power_supply_get_drvdata(struct power_supply *psy); /* For APM emulation, think legacy userspace. */ extern struct class *power_supply_class; -- cgit v1.2.3 From 6bd067c48efed50ac0200c4a83a415bd524254e0 Mon Sep 17 00:00:00 2001 From: Bogdan Purcareata Date: Mon, 5 Feb 2018 08:07:42 -0600 Subject: staging: fsl-mc: Move core bus out of staging Move the source files out of staging into their final locations: -mc.h include file in drivers/staging/fsl-mc/include go to include/linux/fsl -source files in drivers/staging/fsl-mc/bus go to drivers/bus/fsl-mc -overview.rst, providing an overview of DPAA2, goes to Documentation/networking/dpaa2/overview.rst Update or delete other remaining staging files -- Makefile, Kconfig, TODO. Update dpaa2_eth and dpio staging drivers. Add integration bits for the documentation build system. Signed-off-by: Stuart Yoder [rebased, add dpaa2_eth and dpio #include updates] Signed-off-by: Laurentiu Tudor [rebased, split irqchip to separate patch] Signed-off-by: Bogdan Purcareata Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Greg Kroah-Hartman --- Documentation/networking/dpaa2/index.rst | 8 + Documentation/networking/dpaa2/overview.rst | 404 +++++++++ Documentation/networking/index.rst | 1 + MAINTAINERS | 3 +- drivers/bus/Kconfig | 2 + drivers/bus/Makefile | 4 + drivers/bus/fsl-mc/Kconfig | 16 + drivers/bus/fsl-mc/Makefile | 16 + drivers/bus/fsl-mc/dpmcp.c | 99 +++ drivers/bus/fsl-mc/dprc-driver.c | 809 ++++++++++++++++++ drivers/bus/fsl-mc/dprc.c | 532 ++++++++++++ drivers/bus/fsl-mc/fsl-mc-allocator.c | 648 ++++++++++++++ drivers/bus/fsl-mc/fsl-mc-bus.c | 948 +++++++++++++++++++++ drivers/bus/fsl-mc/fsl-mc-msi.c | 285 +++++++ drivers/bus/fsl-mc/fsl-mc-private.h | 475 +++++++++++ drivers/bus/fsl-mc/mc-io.c | 268 ++++++ drivers/bus/fsl-mc/mc-sys.c | 296 +++++++ drivers/staging/fsl-dpaa2/ethernet/README | 2 +- drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 2 +- drivers/staging/fsl-dpaa2/ethernet/dpni.c | 2 +- drivers/staging/fsl-mc/TODO | 18 - drivers/staging/fsl-mc/bus/Kconfig | 10 - drivers/staging/fsl-mc/bus/Makefile | 16 +- drivers/staging/fsl-mc/bus/dpbp.c | 2 +- drivers/staging/fsl-mc/bus/dpcon.c | 2 +- drivers/staging/fsl-mc/bus/dpio/dpio-driver.c | 2 +- drivers/staging/fsl-mc/bus/dpio/dpio-service.c | 2 +- drivers/staging/fsl-mc/bus/dpio/dpio.c | 2 +- drivers/staging/fsl-mc/bus/dpmcp.c | 99 --- drivers/staging/fsl-mc/bus/dprc-driver.c | 809 ------------------ drivers/staging/fsl-mc/bus/dprc.c | 531 ------------ drivers/staging/fsl-mc/bus/fsl-mc-allocator.c | 648 -------------- drivers/staging/fsl-mc/bus/fsl-mc-bus.c | 948 --------------------- drivers/staging/fsl-mc/bus/fsl-mc-msi.c | 284 ------ drivers/staging/fsl-mc/bus/fsl-mc-private.h | 475 ----------- .../staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c | 2 +- drivers/staging/fsl-mc/bus/mc-io.c | 268 ------ drivers/staging/fsl-mc/bus/mc-sys.c | 296 ------- drivers/staging/fsl-mc/include/mc.h | 454 ---------- drivers/staging/fsl-mc/overview.rst | 404 --------- include/linux/fsl/mc.h | 454 ++++++++++ 41 files changed, 5279 insertions(+), 5267 deletions(-) create mode 100644 Documentation/networking/dpaa2/index.rst create mode 100644 Documentation/networking/dpaa2/overview.rst create mode 100644 drivers/bus/fsl-mc/Kconfig create mode 100644 drivers/bus/fsl-mc/Makefile create mode 100644 drivers/bus/fsl-mc/dpmcp.c create mode 100644 drivers/bus/fsl-mc/dprc-driver.c create mode 100644 drivers/bus/fsl-mc/dprc.c create mode 100644 drivers/bus/fsl-mc/fsl-mc-allocator.c create mode 100644 drivers/bus/fsl-mc/fsl-mc-bus.c create mode 100644 drivers/bus/fsl-mc/fsl-mc-msi.c create mode 100644 drivers/bus/fsl-mc/fsl-mc-private.h create mode 100644 drivers/bus/fsl-mc/mc-io.c create mode 100644 drivers/bus/fsl-mc/mc-sys.c delete mode 100644 drivers/staging/fsl-mc/TODO delete mode 100644 drivers/staging/fsl-mc/bus/dpmcp.c delete mode 100644 drivers/staging/fsl-mc/bus/dprc-driver.c delete mode 100644 drivers/staging/fsl-mc/bus/dprc.c delete mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-allocator.c delete mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-bus.c delete mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-msi.c delete mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-private.h delete mode 100644 drivers/staging/fsl-mc/bus/mc-io.c delete mode 100644 drivers/staging/fsl-mc/bus/mc-sys.c delete mode 100644 drivers/staging/fsl-mc/include/mc.h delete mode 100644 drivers/staging/fsl-mc/overview.rst create mode 100644 include/linux/fsl/mc.h (limited to 'include/linux') diff --git a/Documentation/networking/dpaa2/index.rst b/Documentation/networking/dpaa2/index.rst new file mode 100644 index 000000000000..4c6586c87969 --- /dev/null +++ b/Documentation/networking/dpaa2/index.rst @@ -0,0 +1,8 @@ +=================== +DPAA2 Documentation +=================== + +.. toctree:: + :maxdepth: 1 + + overview diff --git a/Documentation/networking/dpaa2/overview.rst b/Documentation/networking/dpaa2/overview.rst new file mode 100644 index 000000000000..79fede4447d6 --- /dev/null +++ b/Documentation/networking/dpaa2/overview.rst @@ -0,0 +1,404 @@ +.. include:: + +DPAA2 (Data Path Acceleration Architecture Gen2) Overview +========================================================= + +:Copyright: |copy| 2015 Freescale Semiconductor Inc. +:Copyright: |copy| 2018 NXP + +This document provides an overview of the Freescale DPAA2 architecture +and how it is integrated into the Linux kernel. + +Introduction +============ + +DPAA2 is a hardware architecture designed for high-speeed network +packet processing. DPAA2 consists of sophisticated mechanisms for +processing Ethernet packets, queue management, buffer management, +autonomous L2 switching, virtual Ethernet bridging, and accelerator +(e.g. crypto) sharing. + +A DPAA2 hardware component called the Management Complex (or MC) manages the +DPAA2 hardware resources. The MC provides an object-based abstraction for +software drivers to use the DPAA2 hardware. +The MC uses DPAA2 hardware resources such as queues, buffer pools, and +network ports to create functional objects/devices such as network +interfaces, an L2 switch, or accelerator instances. +The MC provides memory-mapped I/O command interfaces (MC portals) +which DPAA2 software drivers use to operate on DPAA2 objects. + +The diagram below shows an overview of the DPAA2 resource management +architecture:: + + +--------------------------------------+ + | OS | + | DPAA2 drivers | + | | | + +-----------------------------|--------+ + | + | (create,discover,connect + | config,use,destroy) + | + DPAA2 | + +------------------------| mc portal |-+ + | | | + | +- - - - - - - - - - - - -V- - -+ | + | | | | + | | Management Complex (MC) | | + | | | | + | +- - - - - - - - - - - - - - - -+ | + | | + | Hardware Hardware | + | Resources Objects | + | --------- ------- | + | -queues -DPRC | + | -buffer pools -DPMCP | + | -Eth MACs/ports -DPIO | + | -network interface -DPNI | + | profiles -DPMAC | + | -queue portals -DPBP | + | -MC portals ... | + | ... | + | | + +--------------------------------------+ + + +The MC mediates operations such as create, discover, +connect, configuration, and destroy. Fast-path operations +on data, such as packet transmit/receive, are not mediated by +the MC and are done directly using memory mapped regions in +DPIO objects. + +Overview of DPAA2 Objects +========================= + +The section provides a brief overview of some key DPAA2 objects. +A simple scenario is described illustrating the objects involved +in creating a network interfaces. + +DPRC (Datapath Resource Container) +---------------------------------- + +A DPRC is a container object that holds all the other +types of DPAA2 objects. In the example diagram below there +are 8 objects of 5 types (DPMCP, DPIO, DPBP, DPNI, and DPMAC) +in the container. + +:: + + +---------------------------------------------------------+ + | DPRC | + | | + | +-------+ +-------+ +-------+ +-------+ +-------+ | + | | DPMCP | | DPIO | | DPBP | | DPNI | | DPMAC | | + | +-------+ +-------+ +-------+ +---+---+ +---+---+ | + | | DPMCP | | DPIO | | + | +-------+ +-------+ | + | | DPMCP | | + | +-------+ | + | | + +---------------------------------------------------------+ + +From the point of view of an OS, a DPRC behaves similar to a plug and +play bus, like PCI. DPRC commands can be used to enumerate the contents +of the DPRC, discover the hardware objects present (including mappable +regions and interrupts). + +:: + + DPRC.1 (bus) + | + +--+--------+-------+-------+-------+ + | | | | | + DPMCP.1 DPIO.1 DPBP.1 DPNI.1 DPMAC.1 + DPMCP.2 DPIO.2 + DPMCP.3 + +Hardware objects can be created and destroyed dynamically, providing +the ability to hot plug/unplug objects in and out of the DPRC. + +A DPRC has a mappable MMIO region (an MC portal) that can be used +to send MC commands. It has an interrupt for status events (like +hotplug). +All objects in a container share the same hardware "isolation context". +This means that with respect to an IOMMU the isolation granularity +is at the DPRC (container) level, not at the individual object +level. + +DPRCs can be defined statically and populated with objects +via a config file passed to the MC when firmware starts it. + +DPAA2 Objects for an Ethernet Network Interface +----------------------------------------------- + +A typical Ethernet NIC is monolithic-- the NIC device contains TX/RX +queuing mechanisms, configuration mechanisms, buffer management, +physical ports, and interrupts. DPAA2 uses a more granular approach +utilizing multiple hardware objects. Each object provides specialized +functions. Groups of these objects are used by software to provide +Ethernet network interface functionality. This approach provides +efficient use of finite hardware resources, flexibility, and +performance advantages. + +The diagram below shows the objects needed for a simple +network interface configuration on a system with 2 CPUs. + +:: + + +---+---+ +---+---+ + CPU0 CPU1 + +---+---+ +---+---+ + | | + +---+---+ +---+---+ + DPIO DPIO + +---+---+ +---+---+ + \ / + \ / + \ / + +---+---+ + DPNI --- DPBP,DPMCP + +---+---+ + | + | + +---+---+ + DPMAC + +---+---+ + | + port/PHY + +Below the objects are described. For each object a brief description +is provided along with a summary of the kinds of operations the object +supports and a summary of key resources of the object (MMIO regions +and IRQs). + +DPMAC (Datapath Ethernet MAC) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Represents an Ethernet MAC, a hardware device that connects to an Ethernet +PHY and allows physical transmission and reception of Ethernet frames. + +- MMIO regions: none +- IRQs: DPNI link change +- commands: set link up/down, link config, get stats, + IRQ config, enable, reset + +DPNI (Datapath Network Interface) +Contains TX/RX queues, network interface configuration, and RX buffer pool +configuration mechanisms. The TX/RX queues are in memory and are identified +by queue number. + +- MMIO regions: none +- IRQs: link state +- commands: port config, offload config, queue config, + parse/classify config, IRQ config, enable, reset + +DPIO (Datapath I/O) +~~~~~~~~~~~~~~~~~~~ +Provides interfaces to enqueue and dequeue +packets and do hardware buffer pool management operations. The DPAA2 +architecture separates the mechanism to access queues (the DPIO object) +from the queues themselves. The DPIO provides an MMIO interface to +enqueue/dequeue packets. To enqueue something a descriptor is written +to the DPIO MMIO region, which includes the target queue number. +There will typically be one DPIO assigned to each CPU. This allows all +CPUs to simultaneously perform enqueue/dequeued operations. DPIOs are +expected to be shared by different DPAA2 drivers. + +- MMIO regions: queue operations, buffer management +- IRQs: data availability, congestion notification, buffer + pool depletion +- commands: IRQ config, enable, reset + +DPBP (Datapath Buffer Pool) +~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Represents a hardware buffer pool. + +- MMIO regions: none +- IRQs: none +- commands: enable, reset + +DPMCP (Datapath MC Portal) +~~~~~~~~~~~~~~~~~~~~~~~~~~ +Provides an MC command portal. +Used by drivers to send commands to the MC to manage +objects. + +- MMIO regions: MC command portal +- IRQs: command completion +- commands: IRQ config, enable, reset + +Object Connections +================== +Some objects have explicit relationships that must +be configured: + +- DPNI <--> DPMAC +- DPNI <--> DPNI +- DPNI <--> L2-switch-port + + A DPNI must be connected to something such as a DPMAC, + another DPNI, or L2 switch port. The DPNI connection + is made via a DPRC command. + +:: + + +-------+ +-------+ + | DPNI | | DPMAC | + +---+---+ +---+---+ + | | + +==========+ + +- DPNI <--> DPBP + + A network interface requires a 'buffer pool' (DPBP + object) which provides a list of pointers to memory + where received Ethernet data is to be copied. The + Ethernet driver configures the DPBPs associated with + the network interface. + +Interrupts +========== +All interrupts generated by DPAA2 objects are message +interrupts. At the hardware level message interrupts +generated by devices will normally have 3 components-- +1) a non-spoofable 'device-id' expressed on the hardware +bus, 2) an address, 3) a data value. + +In the case of DPAA2 devices/objects, all objects in the +same container/DPRC share the same 'device-id'. +For ARM-based SoC this is the same as the stream ID. + + +DPAA2 Linux Drivers Overview +============================ + +This section provides an overview of the Linux kernel drivers for +DPAA2-- 1) the bus driver and associated "DPAA2 infrastructure" +drivers and 2) functional object drivers (such as Ethernet). + +As described previously, a DPRC is a container that holds the other +types of DPAA2 objects. It is functionally similar to a plug-and-play +bus controller. +Each object in the DPRC is a Linux "device" and is bound to a driver. +The diagram below shows the Linux drivers involved in a networking +scenario and the objects bound to each driver. A brief description +of each driver follows. + +:: + + +------------+ + | OS Network | + | Stack | + +------------+ +------------+ + | Allocator |. . . . . . . | Ethernet | + |(DPMCP,DPBP)| | (DPNI) | + +-.----------+ +---+---+----+ + . . ^ | + . . | | dequeue> + +-------------+ . | | + | DPRC driver | . +---+---V----+ +---------+ + | (DPRC) | . . . . . .| DPIO driver| | MAC | + +----------+--+ | (DPIO) | | (DPMAC) | + | +------+-----+ +-----+---+ + | | | + | | | + +--------+----------+ | +--+---+ + | MC-bus driver | | | PHY | + | | | |driver| + | /bus/fsl-mc | | +--+---+ + +-------------------+ | | + | | + ========================= HARDWARE =========|=================|====== + DPIO | + | | + DPNI---DPBP | + | | + DPMAC | + | | + PHY ---------------+ + ============================================|======================== + +A brief description of each driver is provided below. + +MC-bus driver +------------- +The MC-bus driver is a platform driver and is probed from a +node in the device tree (compatible "fsl,qoriq-mc") passed in by boot +firmware. It is responsible for bootstrapping the DPAA2 kernel +infrastructure. +Key functions include: + +- registering a new bus type named "fsl-mc" with the kernel, + and implementing bus call-backs (e.g. match/uevent/dev_groups) +- implementing APIs for DPAA2 driver registration and for device + add/remove +- creates an MSI IRQ domain +- doing a 'device add' to expose the 'root' DPRC, in turn triggering + a bind of the root DPRC to the DPRC driver + +The binding for the MC-bus device-tree node can be consulted at +*Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt*. +The sysfs bind/unbind interfaces for the MC-bus can be consulted at +*Documentation/ABI/testing/sysfs-bus-fsl-mc*. + +DPRC driver +----------- +The DPRC driver is bound to DPRC objects and does runtime management +of a bus instance. It performs the initial bus scan of the DPRC +and handles interrupts for container events such as hot plug by +re-scanning the DPRC. + +Allocator +--------- +Certain objects such as DPMCP and DPBP are generic and fungible, +and are intended to be used by other drivers. For example, +the DPAA2 Ethernet driver needs: + +- DPMCPs to send MC commands, to configure network interfaces +- DPBPs for network buffer pools + +The allocator driver registers for these allocatable object types +and those objects are bound to the allocator when the bus is probed. +The allocator maintains a pool of objects that are available for +allocation by other DPAA2 drivers. + +DPIO driver +----------- +The DPIO driver is bound to DPIO objects and provides services that allow +other drivers such as the Ethernet driver to enqueue and dequeue data for +their respective objects. +Key services include: + +- data availability notifications +- hardware queuing operations (enqueue and dequeue of data) +- hardware buffer pool management + +To transmit a packet the Ethernet driver puts data on a queue and +invokes a DPIO API. For receive, the Ethernet driver registers +a data availability notification callback. To dequeue a packet +a DPIO API is used. +There is typically one DPIO object per physical CPU for optimum +performance, allowing different CPUs to simultaneously enqueue +and dequeue data. + +The DPIO driver operates on behalf of all DPAA2 drivers +active in the kernel-- Ethernet, crypto, compression, +etc. + +Ethernet driver +--------------- +The Ethernet driver is bound to a DPNI and implements the kernel +interfaces needed to connect the DPAA2 network interface to +the network stack. +Each DPNI corresponds to a Linux network interface. + +MAC driver +---------- +An Ethernet PHY is an off-chip, board specific component and is managed +by the appropriate PHY driver via an mdio bus. The MAC driver +plays a role of being a proxy between the PHY driver and the +MC. It does this proxy via the MC commands to a DPMAC object. +If the PHY driver signals a link change, the MAC driver notifies +the MC via a DPMAC command. If a network interface is brought +up or down, the MC notifies the DPMAC driver via an interrupt and +the driver can take appropriate action. diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst index 90966c2692d8..f204eaff657d 100644 --- a/Documentation/networking/index.rst +++ b/Documentation/networking/index.rst @@ -8,6 +8,7 @@ Contents: batman-adv can + dpaa2/index kapi z8530book msg_zerocopy diff --git a/MAINTAINERS b/MAINTAINERS index 0c34d96c54e7..885d20072d97 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11452,8 +11452,9 @@ M: Stuart Yoder M: Laurentiu Tudor L: linux-kernel@vger.kernel.org S: Maintained -F: drivers/staging/fsl-mc/ +F: drivers/bus/fsl-mc/ F: Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt +F: Documentation/networking/dpaa2/overview.rst QT1010 MEDIA DRIVER M: Antti Palosaari diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 57e011d36a79..769599bc1bab 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -199,4 +199,6 @@ config DA8XX_MSTPRI configuration. Allows to adjust the priorities of all master peripherals. +source "drivers/bus/fsl-mc/Kconfig" + endmenu diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 9bcd0bf3954b..b666c49f249e 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -8,6 +8,10 @@ obj-$(CONFIG_ARM_CCI) += arm-cci.o obj-$(CONFIG_ARM_CCN) += arm-ccn.o obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o + +# DPAA2 fsl-mc bus +obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/ + obj-$(CONFIG_IMX_WEIM) += imx-weim.o obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o diff --git a/drivers/bus/fsl-mc/Kconfig b/drivers/bus/fsl-mc/Kconfig new file mode 100644 index 000000000000..bcca64486fd3 --- /dev/null +++ b/drivers/bus/fsl-mc/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# DPAA2 fsl-mc bus +# +# Copyright (C) 2014-2016 Freescale Semiconductor, Inc. +# + +config FSL_MC_BUS + bool "QorIQ DPAA2 fsl-mc bus driver" + depends on OF && (ARCH_LAYERSCAPE || (COMPILE_TEST && (ARM || ARM64 || X86 || PPC))) + select GENERIC_MSI_IRQ_DOMAIN + help + Driver to enable the bus infrastructure for the QorIQ DPAA2 + architecture. The fsl-mc bus driver handles discovery of + DPAA2 objects (which are represented as Linux devices) and + binding objects to drivers. diff --git a/drivers/bus/fsl-mc/Makefile b/drivers/bus/fsl-mc/Makefile new file mode 100644 index 000000000000..6a97f2c3a065 --- /dev/null +++ b/drivers/bus/fsl-mc/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Freescale Management Complex (MC) bus drivers +# +# Copyright (C) 2014 Freescale Semiconductor, Inc. +# +obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o + +mc-bus-driver-objs := fsl-mc-bus.o \ + mc-sys.o \ + mc-io.o \ + dprc.o \ + dprc-driver.o \ + fsl-mc-allocator.o \ + fsl-mc-msi.o \ + dpmcp.o diff --git a/drivers/bus/fsl-mc/dpmcp.c b/drivers/bus/fsl-mc/dpmcp.c new file mode 100644 index 000000000000..8d997b0f6ba3 --- /dev/null +++ b/drivers/bus/fsl-mc/dpmcp.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2013-2016 Freescale Semiconductor Inc. + * + */ +#include +#include + +#include "fsl-mc-private.h" + +/** + * dpmcp_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpmcp_id: DPMCP unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpmcp_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmcp_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int dpmcp_id, + u16 *token) +{ + struct mc_command cmd = { 0 }; + struct dpmcp_cmd_open *cmd_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMCP_CMDID_OPEN, + cmd_flags, 0); + cmd_params = (struct dpmcp_cmd_open *)cmd.params; + cmd_params->dpmcp_id = cpu_to_le32(dpmcp_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return err; +} + +/** + * dpmcp_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMCP object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmcp_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CLOSE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpmcp_reset() - Reset the DPMCP, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMCP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmcp_reset(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMCP_CMDID_RESET, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c new file mode 100644 index 000000000000..52c7e15143d6 --- /dev/null +++ b/drivers/bus/fsl-mc/dprc-driver.c @@ -0,0 +1,809 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Freescale data path resource container (DPRC) driver + * + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Author: German Rivera + * + */ + +#include +#include +#include +#include +#include + +#include "fsl-mc-private.h" + +#define FSL_MC_DPRC_DRIVER_NAME "fsl_mc_dprc" + +struct fsl_mc_child_objs { + int child_count; + struct fsl_mc_obj_desc *child_array; +}; + +static bool fsl_mc_device_match(struct fsl_mc_device *mc_dev, + struct fsl_mc_obj_desc *obj_desc) +{ + return mc_dev->obj_desc.id == obj_desc->id && + strcmp(mc_dev->obj_desc.type, obj_desc->type) == 0; + +} + +static int __fsl_mc_device_remove_if_not_in_mc(struct device *dev, void *data) +{ + int i; + struct fsl_mc_child_objs *objs; + struct fsl_mc_device *mc_dev; + + mc_dev = to_fsl_mc_device(dev); + objs = data; + + for (i = 0; i < objs->child_count; i++) { + struct fsl_mc_obj_desc *obj_desc = &objs->child_array[i]; + + if (strlen(obj_desc->type) != 0 && + fsl_mc_device_match(mc_dev, obj_desc)) + break; + } + + if (i == objs->child_count) + fsl_mc_device_remove(mc_dev); + + return 0; +} + +static int __fsl_mc_device_remove(struct device *dev, void *data) +{ + fsl_mc_device_remove(to_fsl_mc_device(dev)); + return 0; +} + +/** + * dprc_remove_devices - Removes devices for objects removed from a DPRC + * + * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object + * @obj_desc_array: array of object descriptors for child objects currently + * present in the DPRC in the MC. + * @num_child_objects_in_mc: number of entries in obj_desc_array + * + * Synchronizes the state of the Linux bus driver with the actual state of + * the MC by removing devices that represent MC objects that have + * been dynamically removed in the physical DPRC. + */ +static void dprc_remove_devices(struct fsl_mc_device *mc_bus_dev, + struct fsl_mc_obj_desc *obj_desc_array, + int num_child_objects_in_mc) +{ + if (num_child_objects_in_mc != 0) { + /* + * Remove child objects that are in the DPRC in Linux, + * but not in the MC: + */ + struct fsl_mc_child_objs objs; + + objs.child_count = num_child_objects_in_mc; + objs.child_array = obj_desc_array; + device_for_each_child(&mc_bus_dev->dev, &objs, + __fsl_mc_device_remove_if_not_in_mc); + } else { + /* + * There are no child objects for this DPRC in the MC. + * So, remove all the child devices from Linux: + */ + device_for_each_child(&mc_bus_dev->dev, NULL, + __fsl_mc_device_remove); + } +} + +static int __fsl_mc_device_match(struct device *dev, void *data) +{ + struct fsl_mc_obj_desc *obj_desc = data; + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + + return fsl_mc_device_match(mc_dev, obj_desc); +} + +static struct fsl_mc_device *fsl_mc_device_lookup(struct fsl_mc_obj_desc + *obj_desc, + struct fsl_mc_device + *mc_bus_dev) +{ + struct device *dev; + + dev = device_find_child(&mc_bus_dev->dev, obj_desc, + __fsl_mc_device_match); + + return dev ? to_fsl_mc_device(dev) : NULL; +} + +/** + * check_plugged_state_change - Check change in an MC object's plugged state + * + * @mc_dev: pointer to the fsl-mc device for a given MC object + * @obj_desc: pointer to the MC object's descriptor in the MC + * + * If the plugged state has changed from unplugged to plugged, the fsl-mc + * device is bound to the corresponding device driver. + * If the plugged state has changed from plugged to unplugged, the fsl-mc + * device is unbound from the corresponding device driver. + */ +static void check_plugged_state_change(struct fsl_mc_device *mc_dev, + struct fsl_mc_obj_desc *obj_desc) +{ + int error; + u32 plugged_flag_at_mc = + obj_desc->state & FSL_MC_OBJ_STATE_PLUGGED; + + if (plugged_flag_at_mc != + (mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED)) { + if (plugged_flag_at_mc) { + mc_dev->obj_desc.state |= FSL_MC_OBJ_STATE_PLUGGED; + error = device_attach(&mc_dev->dev); + if (error < 0) { + dev_err(&mc_dev->dev, + "device_attach() failed: %d\n", + error); + } + } else { + mc_dev->obj_desc.state &= ~FSL_MC_OBJ_STATE_PLUGGED; + device_release_driver(&mc_dev->dev); + } + } +} + +/** + * dprc_add_new_devices - Adds devices to the logical bus for a DPRC + * + * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object + * @obj_desc_array: array of device descriptors for child devices currently + * present in the physical DPRC. + * @num_child_objects_in_mc: number of entries in obj_desc_array + * + * Synchronizes the state of the Linux bus driver with the actual + * state of the MC by adding objects that have been newly discovered + * in the physical DPRC. + */ +static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, + struct fsl_mc_obj_desc *obj_desc_array, + int num_child_objects_in_mc) +{ + int error; + int i; + + for (i = 0; i < num_child_objects_in_mc; i++) { + struct fsl_mc_device *child_dev; + struct fsl_mc_obj_desc *obj_desc = &obj_desc_array[i]; + + if (strlen(obj_desc->type) == 0) + continue; + + /* + * Check if device is already known to Linux: + */ + child_dev = fsl_mc_device_lookup(obj_desc, mc_bus_dev); + if (child_dev) { + check_plugged_state_change(child_dev, obj_desc); + put_device(&child_dev->dev); + continue; + } + + error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev, + &child_dev); + if (error < 0) + continue; + } +} + +/** + * dprc_scan_objects - Discover objects in a DPRC + * + * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object + * @total_irq_count: If argument is provided the function populates the + * total number of IRQs created by objects in the DPRC. + * + * Detects objects added and removed from a DPRC and synchronizes the + * state of the Linux bus driver, MC by adding and removing + * devices accordingly. + * Two types of devices can be found in a DPRC: allocatable objects (e.g., + * dpbp, dpmcp) and non-allocatable devices (e.g., dprc, dpni). + * All allocatable devices needed to be probed before all non-allocatable + * devices, to ensure that device drivers for non-allocatable + * devices can allocate any type of allocatable devices. + * That is, we need to ensure that the corresponding resource pools are + * populated before they can get allocation requests from probe callbacks + * of the device drivers for the non-allocatable devices. + */ +static int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, + unsigned int *total_irq_count) +{ + int num_child_objects; + int dprc_get_obj_failures; + int error; + unsigned int irq_count = mc_bus_dev->obj_desc.irq_count; + struct fsl_mc_obj_desc *child_obj_desc_array = NULL; + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); + + error = dprc_get_obj_count(mc_bus_dev->mc_io, + 0, + mc_bus_dev->mc_handle, + &num_child_objects); + if (error < 0) { + dev_err(&mc_bus_dev->dev, "dprc_get_obj_count() failed: %d\n", + error); + return error; + } + + if (num_child_objects != 0) { + int i; + + child_obj_desc_array = + devm_kmalloc_array(&mc_bus_dev->dev, num_child_objects, + sizeof(*child_obj_desc_array), + GFP_KERNEL); + if (!child_obj_desc_array) + return -ENOMEM; + + /* + * Discover objects currently present in the physical DPRC: + */ + dprc_get_obj_failures = 0; + for (i = 0; i < num_child_objects; i++) { + struct fsl_mc_obj_desc *obj_desc = + &child_obj_desc_array[i]; + + error = dprc_get_obj(mc_bus_dev->mc_io, + 0, + mc_bus_dev->mc_handle, + i, obj_desc); + if (error < 0) { + dev_err(&mc_bus_dev->dev, + "dprc_get_obj(i=%d) failed: %d\n", + i, error); + /* + * Mark the obj entry as "invalid", by using the + * empty string as obj type: + */ + obj_desc->type[0] = '\0'; + obj_desc->id = error; + dprc_get_obj_failures++; + continue; + } + + /* + * add a quirk for all versions of dpsec < 4.0...none + * are coherent regardless of what the MC reports. + */ + if ((strcmp(obj_desc->type, "dpseci") == 0) && + (obj_desc->ver_major < 4)) + obj_desc->flags |= + FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY; + + irq_count += obj_desc->irq_count; + dev_dbg(&mc_bus_dev->dev, + "Discovered object: type %s, id %d\n", + obj_desc->type, obj_desc->id); + } + + if (dprc_get_obj_failures != 0) { + dev_err(&mc_bus_dev->dev, + "%d out of %d devices could not be retrieved\n", + dprc_get_obj_failures, num_child_objects); + } + } + + /* + * Allocate IRQ's before binding the scanned devices with their + * respective drivers. + */ + if (dev_get_msi_domain(&mc_bus_dev->dev) && !mc_bus->irq_resources) { + if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { + dev_warn(&mc_bus_dev->dev, + "IRQs needed (%u) exceed IRQs preallocated (%u)\n", + irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); + } + + error = fsl_mc_populate_irq_pool(mc_bus, + FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); + if (error < 0) + return error; + } + + if (total_irq_count) + *total_irq_count = irq_count; + + dprc_remove_devices(mc_bus_dev, child_obj_desc_array, + num_child_objects); + + dprc_add_new_devices(mc_bus_dev, child_obj_desc_array, + num_child_objects); + + if (child_obj_desc_array) + devm_kfree(&mc_bus_dev->dev, child_obj_desc_array); + + return 0; +} + +/** + * dprc_scan_container - Scans a physical DPRC and synchronizes Linux bus state + * + * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object + * + * Scans the physical DPRC and synchronizes the state of the Linux + * bus driver with the actual state of the MC by adding and removing + * devices as appropriate. + */ +static int dprc_scan_container(struct fsl_mc_device *mc_bus_dev) +{ + int error; + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); + + fsl_mc_init_all_resource_pools(mc_bus_dev); + + /* + * Discover objects in the DPRC: + */ + mutex_lock(&mc_bus->scan_mutex); + error = dprc_scan_objects(mc_bus_dev, NULL); + mutex_unlock(&mc_bus->scan_mutex); + if (error < 0) { + fsl_mc_cleanup_all_resource_pools(mc_bus_dev); + return error; + } + + return 0; +} + +/** + * dprc_irq0_handler - Regular ISR for DPRC interrupt 0 + * + * @irq: IRQ number of the interrupt being handled + * @arg: Pointer to device structure + */ +static irqreturn_t dprc_irq0_handler(int irq_num, void *arg) +{ + return IRQ_WAKE_THREAD; +} + +/** + * dprc_irq0_handler_thread - Handler thread function for DPRC interrupt 0 + * + * @irq: IRQ number of the interrupt being handled + * @arg: Pointer to device structure + */ +static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg) +{ + int error; + u32 status; + struct device *dev = arg; + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); + struct fsl_mc_io *mc_io = mc_dev->mc_io; + struct msi_desc *msi_desc = mc_dev->irqs[0]->msi_desc; + + dev_dbg(dev, "DPRC IRQ %d triggered on CPU %u\n", + irq_num, smp_processor_id()); + + if (!(mc_dev->flags & FSL_MC_IS_DPRC)) + return IRQ_HANDLED; + + mutex_lock(&mc_bus->scan_mutex); + if (!msi_desc || msi_desc->irq != (u32)irq_num) + goto out; + + status = 0; + error = dprc_get_irq_status(mc_io, 0, mc_dev->mc_handle, 0, + &status); + if (error < 0) { + dev_err(dev, + "dprc_get_irq_status() failed: %d\n", error); + goto out; + } + + error = dprc_clear_irq_status(mc_io, 0, mc_dev->mc_handle, 0, + status); + if (error < 0) { + dev_err(dev, + "dprc_clear_irq_status() failed: %d\n", error); + goto out; + } + + if (status & (DPRC_IRQ_EVENT_OBJ_ADDED | + DPRC_IRQ_EVENT_OBJ_REMOVED | + DPRC_IRQ_EVENT_CONTAINER_DESTROYED | + DPRC_IRQ_EVENT_OBJ_DESTROYED | + DPRC_IRQ_EVENT_OBJ_CREATED)) { + unsigned int irq_count; + + error = dprc_scan_objects(mc_dev, &irq_count); + if (error < 0) { + /* + * If the error is -ENXIO, we ignore it, as it indicates + * that the object scan was aborted, as we detected that + * an object was removed from the DPRC in the MC, while + * we were scanning the DPRC. + */ + if (error != -ENXIO) { + dev_err(dev, "dprc_scan_objects() failed: %d\n", + error); + } + + goto out; + } + + if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { + dev_warn(dev, + "IRQs needed (%u) exceed IRQs preallocated (%u)\n", + irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); + } + } + +out: + mutex_unlock(&mc_bus->scan_mutex); + return IRQ_HANDLED; +} + +/* + * Disable and clear interrupt for a given DPRC object + */ +static int disable_dprc_irq(struct fsl_mc_device *mc_dev) +{ + int error; + struct fsl_mc_io *mc_io = mc_dev->mc_io; + + /* + * Disable generation of interrupt, while we configure it: + */ + error = dprc_set_irq_enable(mc_io, 0, mc_dev->mc_handle, 0, 0); + if (error < 0) { + dev_err(&mc_dev->dev, + "Disabling DPRC IRQ failed: dprc_set_irq_enable() failed: %d\n", + error); + return error; + } + + /* + * Disable all interrupt causes for the interrupt: + */ + error = dprc_set_irq_mask(mc_io, 0, mc_dev->mc_handle, 0, 0x0); + if (error < 0) { + dev_err(&mc_dev->dev, + "Disabling DPRC IRQ failed: dprc_set_irq_mask() failed: %d\n", + error); + return error; + } + + /* + * Clear any leftover interrupts: + */ + error = dprc_clear_irq_status(mc_io, 0, mc_dev->mc_handle, 0, ~0x0U); + if (error < 0) { + dev_err(&mc_dev->dev, + "Disabling DPRC IRQ failed: dprc_clear_irq_status() failed: %d\n", + error); + return error; + } + + return 0; +} + +static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev) +{ + int error; + struct fsl_mc_device_irq *irq = mc_dev->irqs[0]; + + /* + * NOTE: devm_request_threaded_irq() invokes the device-specific + * function that programs the MSI physically in the device + */ + error = devm_request_threaded_irq(&mc_dev->dev, + irq->msi_desc->irq, + dprc_irq0_handler, + dprc_irq0_handler_thread, + IRQF_NO_SUSPEND | IRQF_ONESHOT, + dev_name(&mc_dev->dev), + &mc_dev->dev); + if (error < 0) { + dev_err(&mc_dev->dev, + "devm_request_threaded_irq() failed: %d\n", + error); + return error; + } + + return 0; +} + +static int enable_dprc_irq(struct fsl_mc_device *mc_dev) +{ + int error; + + /* + * Enable all interrupt causes for the interrupt: + */ + error = dprc_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, 0, + ~0x0u); + if (error < 0) { + dev_err(&mc_dev->dev, + "Enabling DPRC IRQ failed: dprc_set_irq_mask() failed: %d\n", + error); + + return error; + } + + /* + * Enable generation of the interrupt: + */ + error = dprc_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, 0, 1); + if (error < 0) { + dev_err(&mc_dev->dev, + "Enabling DPRC IRQ failed: dprc_set_irq_enable() failed: %d\n", + error); + + return error; + } + + return 0; +} + +/* + * Setup interrupt for a given DPRC device + */ +static int dprc_setup_irq(struct fsl_mc_device *mc_dev) +{ + int error; + + error = fsl_mc_allocate_irqs(mc_dev); + if (error < 0) + return error; + + error = disable_dprc_irq(mc_dev); + if (error < 0) + goto error_free_irqs; + + error = register_dprc_irq_handler(mc_dev); + if (error < 0) + goto error_free_irqs; + + error = enable_dprc_irq(mc_dev); + if (error < 0) + goto error_free_irqs; + + return 0; + +error_free_irqs: + fsl_mc_free_irqs(mc_dev); + return error; +} + +/** + * dprc_probe - callback invoked when a DPRC is being bound to this driver + * + * @mc_dev: Pointer to fsl-mc device representing a DPRC + * + * It opens the physical DPRC in the MC. + * It scans the DPRC to discover the MC objects contained in it. + * It creates the interrupt pool for the MC bus associated with the DPRC. + * It configures the interrupts for the DPRC device itself. + */ +static int dprc_probe(struct fsl_mc_device *mc_dev) +{ + int error; + size_t region_size; + struct device *parent_dev = mc_dev->dev.parent; + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); + bool mc_io_created = false; + bool msi_domain_set = false; + u16 major_ver, minor_ver; + + if (!is_fsl_mc_bus_dprc(mc_dev)) + return -EINVAL; + + if (dev_get_msi_domain(&mc_dev->dev)) + return -EINVAL; + + if (!mc_dev->mc_io) { + /* + * This is a child DPRC: + */ + if (!dev_is_fsl_mc(parent_dev)) + return -EINVAL; + + if (mc_dev->obj_desc.region_count == 0) + return -EINVAL; + + region_size = resource_size(mc_dev->regions); + + error = fsl_create_mc_io(&mc_dev->dev, + mc_dev->regions[0].start, + region_size, + NULL, + FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, + &mc_dev->mc_io); + if (error < 0) + return error; + + mc_io_created = true; + + /* + * Inherit parent MSI domain: + */ + dev_set_msi_domain(&mc_dev->dev, + dev_get_msi_domain(parent_dev)); + msi_domain_set = true; + } else { + /* + * This is a root DPRC + */ + struct irq_domain *mc_msi_domain; + + if (dev_is_fsl_mc(parent_dev)) + return -EINVAL; + + error = fsl_mc_find_msi_domain(parent_dev, + &mc_msi_domain); + if (error < 0) { + dev_warn(&mc_dev->dev, + "WARNING: MC bus without interrupt support\n"); + } else { + dev_set_msi_domain(&mc_dev->dev, mc_msi_domain); + msi_domain_set = true; + } + } + + error = dprc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id, + &mc_dev->mc_handle); + if (error < 0) { + dev_err(&mc_dev->dev, "dprc_open() failed: %d\n", error); + goto error_cleanup_msi_domain; + } + + error = dprc_get_attributes(mc_dev->mc_io, 0, mc_dev->mc_handle, + &mc_bus->dprc_attr); + if (error < 0) { + dev_err(&mc_dev->dev, "dprc_get_attributes() failed: %d\n", + error); + goto error_cleanup_open; + } + + error = dprc_get_api_version(mc_dev->mc_io, 0, + &major_ver, + &minor_ver); + if (error < 0) { + dev_err(&mc_dev->dev, "dprc_get_api_version() failed: %d\n", + error); + goto error_cleanup_open; + } + + if (major_ver < DPRC_MIN_VER_MAJOR || + (major_ver == DPRC_MIN_VER_MAJOR && + minor_ver < DPRC_MIN_VER_MINOR)) { + dev_err(&mc_dev->dev, + "ERROR: DPRC version %d.%d not supported\n", + major_ver, minor_ver); + error = -ENOTSUPP; + goto error_cleanup_open; + } + + mutex_init(&mc_bus->scan_mutex); + + /* + * Discover MC objects in DPRC object: + */ + error = dprc_scan_container(mc_dev); + if (error < 0) + goto error_cleanup_open; + + /* + * Configure interrupt for the DPRC object associated with this MC bus: + */ + error = dprc_setup_irq(mc_dev); + if (error < 0) + goto error_cleanup_open; + + dev_info(&mc_dev->dev, "DPRC device bound to driver"); + return 0; + +error_cleanup_open: + (void)dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); + +error_cleanup_msi_domain: + if (msi_domain_set) + dev_set_msi_domain(&mc_dev->dev, NULL); + + if (mc_io_created) { + fsl_destroy_mc_io(mc_dev->mc_io); + mc_dev->mc_io = NULL; + } + + return error; +} + +/* + * Tear down interrupt for a given DPRC object + */ +static void dprc_teardown_irq(struct fsl_mc_device *mc_dev) +{ + struct fsl_mc_device_irq *irq = mc_dev->irqs[0]; + + (void)disable_dprc_irq(mc_dev); + + devm_free_irq(&mc_dev->dev, irq->msi_desc->irq, &mc_dev->dev); + + fsl_mc_free_irqs(mc_dev); +} + +/** + * dprc_remove - callback invoked when a DPRC is being unbound from this driver + * + * @mc_dev: Pointer to fsl-mc device representing the DPRC + * + * It removes the DPRC's child objects from Linux (not from the MC) and + * closes the DPRC device in the MC. + * It tears down the interrupts that were configured for the DPRC device. + * It destroys the interrupt pool associated with this MC bus. + */ +static int dprc_remove(struct fsl_mc_device *mc_dev) +{ + int error; + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); + + if (!is_fsl_mc_bus_dprc(mc_dev)) + return -EINVAL; + if (!mc_dev->mc_io) + return -EINVAL; + + if (!mc_bus->irq_resources) + return -EINVAL; + + if (dev_get_msi_domain(&mc_dev->dev)) + dprc_teardown_irq(mc_dev); + + device_for_each_child(&mc_dev->dev, NULL, __fsl_mc_device_remove); + + if (dev_get_msi_domain(&mc_dev->dev)) { + fsl_mc_cleanup_irq_pool(mc_bus); + dev_set_msi_domain(&mc_dev->dev, NULL); + } + + fsl_mc_cleanup_all_resource_pools(mc_dev); + + error = dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); + if (error < 0) + dev_err(&mc_dev->dev, "dprc_close() failed: %d\n", error); + + if (!fsl_mc_is_root_dprc(&mc_dev->dev)) { + fsl_destroy_mc_io(mc_dev->mc_io); + mc_dev->mc_io = NULL; + } + + dev_info(&mc_dev->dev, "DPRC device unbound from driver"); + return 0; +} + +static const struct fsl_mc_device_id match_id_table[] = { + { + .vendor = FSL_MC_VENDOR_FREESCALE, + .obj_type = "dprc"}, + {.vendor = 0x0}, +}; + +static struct fsl_mc_driver dprc_driver = { + .driver = { + .name = FSL_MC_DPRC_DRIVER_NAME, + .owner = THIS_MODULE, + .pm = NULL, + }, + .match_id_table = match_id_table, + .probe = dprc_probe, + .remove = dprc_remove, +}; + +int __init dprc_driver_init(void) +{ + return fsl_mc_driver_register(&dprc_driver); +} + +void dprc_driver_exit(void) +{ + fsl_mc_driver_unregister(&dprc_driver); +} diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c new file mode 100644 index 000000000000..5c23e8d4ddb3 --- /dev/null +++ b/drivers/bus/fsl-mc/dprc.c @@ -0,0 +1,532 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2013-2016 Freescale Semiconductor Inc. + * + */ +#include +#include + +#include "fsl-mc-private.h" + +/** + * dprc_open() - Open DPRC object for use + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Container ID to open + * @token: Returned token of DPRC object + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Required before any operation on the object. + */ +int dprc_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int container_id, + u16 *token) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_open *cmd_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags, + 0); + cmd_params = (struct dprc_cmd_open *)cmd.params; + cmd_params->container_id = cpu_to_le32(container_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return 0; +} +EXPORT_SYMBOL_GPL(dprc_open); + +/** + * dprc_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dprc_close); + +/** + * dprc_set_irq() - Set IRQ information for the DPRC to trigger an interrupt. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @irq_index: Identifies the interrupt index to configure + * @irq_cfg: IRQ configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_set_irq(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + struct dprc_irq_cfg *irq_cfg) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_set_irq *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ, + cmd_flags, + token); + cmd_params = (struct dprc_cmd_set_irq *)cmd.params; + cmd_params->irq_val = cpu_to_le32(irq_cfg->val); + cmd_params->irq_index = irq_index; + cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr); + cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dprc_set_irq_enable() - Set overall interrupt state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @irq_index: The interrupt index to configure + * @en: Interrupt state - enable = 1, disable = 0 + * + * Allows GPP software to control when interrupts are generated. + * Each interrupt can have up to 32 causes. The enable/disable control's the + * overall interrupt state. if the interrupt is disabled no causes will cause + * an interrupt. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_set_irq_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u8 en) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_set_irq_enable *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_ENABLE, + cmd_flags, token); + cmd_params = (struct dprc_cmd_set_irq_enable *)cmd.params; + cmd_params->enable = en & DPRC_ENABLE; + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dprc_set_irq_mask() - Set interrupt mask. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @irq_index: The interrupt index to configure + * @mask: event mask to trigger interrupt; + * each bit: + * 0 = ignore event + * 1 = consider event for asserting irq + * + * Every interrupt can have up to 32 causes and the interrupt model supports + * masking/unmasking each cause independently + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_set_irq_mask(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 mask) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_set_irq_mask *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_MASK, + cmd_flags, token); + cmd_params = (struct dprc_cmd_set_irq_mask *)cmd.params; + cmd_params->mask = cpu_to_le32(mask); + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dprc_get_irq_status() - Get the current status of any pending interrupts. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @irq_index: The interrupt index to configure + * @status: Returned interrupts status - one bit per cause: + * 0 = no interrupt pending + * 1 = interrupt pending + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 *status) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_get_irq_status *cmd_params; + struct dprc_rsp_get_irq_status *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_STATUS, + cmd_flags, token); + cmd_params = (struct dprc_cmd_get_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(*status); + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dprc_rsp_get_irq_status *)cmd.params; + *status = le32_to_cpu(rsp_params->status); + + return 0; +} + +/** + * dprc_clear_irq_status() - Clear a pending interrupt's status + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @irq_index: The interrupt index to configure + * @status: bits to clear (W1C) - one bit per cause: + * 0 = don't change + * 1 = clear status bit + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_clear_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 status) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_clear_irq_status *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLEAR_IRQ_STATUS, + cmd_flags, token); + cmd_params = (struct dprc_cmd_clear_irq_status *)cmd.params; + cmd_params->status = cpu_to_le32(status); + cmd_params->irq_index = irq_index; + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dprc_get_attributes() - Obtains container attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @attributes Returned container attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_attributes(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dprc_attributes *attr) +{ + struct mc_command cmd = { 0 }; + struct dprc_rsp_get_attributes *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dprc_rsp_get_attributes *)cmd.params; + attr->container_id = le32_to_cpu(rsp_params->container_id); + attr->icid = le16_to_cpu(rsp_params->icid); + attr->options = le32_to_cpu(rsp_params->options); + attr->portal_id = le32_to_cpu(rsp_params->portal_id); + + return 0; +} + +/** + * dprc_get_obj_count() - Obtains the number of objects in the DPRC + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @obj_count: Number of objects assigned to the DPRC + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj_count(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + int *obj_count) +{ + struct mc_command cmd = { 0 }; + struct dprc_rsp_get_obj_count *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT, + cmd_flags, token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dprc_rsp_get_obj_count *)cmd.params; + *obj_count = le32_to_cpu(rsp_params->obj_count); + + return 0; +} +EXPORT_SYMBOL_GPL(dprc_get_obj_count); + +/** + * dprc_get_obj() - Get general information on an object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @obj_index: Index of the object to be queried (< obj_count) + * @obj_desc: Returns the requested object descriptor + * + * The object descriptors are retrieved one by one by incrementing + * obj_index up to (not including) the value of obj_count returned + * from dprc_get_obj_count(). dprc_get_obj_count() must + * be called prior to dprc_get_obj(). + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + int obj_index, + struct fsl_mc_obj_desc *obj_desc) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_get_obj *cmd_params; + struct dprc_rsp_get_obj *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ, + cmd_flags, + token); + cmd_params = (struct dprc_cmd_get_obj *)cmd.params; + cmd_params->obj_index = cpu_to_le32(obj_index); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dprc_rsp_get_obj *)cmd.params; + obj_desc->id = le32_to_cpu(rsp_params->id); + obj_desc->vendor = le16_to_cpu(rsp_params->vendor); + obj_desc->irq_count = rsp_params->irq_count; + obj_desc->region_count = rsp_params->region_count; + obj_desc->state = le32_to_cpu(rsp_params->state); + obj_desc->ver_major = le16_to_cpu(rsp_params->version_major); + obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor); + obj_desc->flags = le16_to_cpu(rsp_params->flags); + strncpy(obj_desc->type, rsp_params->type, 16); + obj_desc->type[15] = '\0'; + strncpy(obj_desc->label, rsp_params->label, 16); + obj_desc->label[15] = '\0'; + return 0; +} +EXPORT_SYMBOL_GPL(dprc_get_obj); + +/** + * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @obj_type: Type of the object to set its IRQ + * @obj_id: ID of the object to set its IRQ + * @irq_index: The interrupt index to configure + * @irq_cfg: IRQ configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_set_obj_irq(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + char *obj_type, + int obj_id, + u8 irq_index, + struct dprc_irq_cfg *irq_cfg) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_set_obj_irq *cmd_params; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_IRQ, + cmd_flags, + token); + cmd_params = (struct dprc_cmd_set_obj_irq *)cmd.params; + cmd_params->irq_val = cpu_to_le32(irq_cfg->val); + cmd_params->irq_index = irq_index; + cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr); + cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num); + cmd_params->obj_id = cpu_to_le32(obj_id); + strncpy(cmd_params->obj_type, obj_type, 16); + cmd_params->obj_type[15] = '\0'; + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dprc_set_obj_irq); + +/** + * dprc_get_obj_region() - Get region information for a specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @obj_type; Object type as returned in dprc_get_obj() + * @obj_id: Unique object instance as returned in dprc_get_obj() + * @region_index: The specific region to query + * @region_desc: Returns the requested region descriptor + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj_region(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + char *obj_type, + int obj_id, + u8 region_index, + struct dprc_region_desc *region_desc) +{ + struct mc_command cmd = { 0 }; + struct dprc_cmd_get_obj_region *cmd_params; + struct dprc_rsp_get_obj_region *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG, + cmd_flags, token); + cmd_params = (struct dprc_cmd_get_obj_region *)cmd.params; + cmd_params->obj_id = cpu_to_le32(obj_id); + cmd_params->region_index = region_index; + strncpy(cmd_params->obj_type, obj_type, 16); + cmd_params->obj_type[15] = '\0'; + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params; + region_desc->base_offset = le64_to_cpu(rsp_params->base_addr); + region_desc->size = le32_to_cpu(rsp_params->size); + + return 0; +} +EXPORT_SYMBOL_GPL(dprc_get_obj_region); + +/** + * dprc_get_api_version - Get Data Path Resource Container API version + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of Data Path Resource Container API + * @minor_ver: Minor version of Data Path Resource Container API + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION, + cmd_flags, 0); + + /* send command to mc */ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + mc_cmd_read_api_version(&cmd, major_ver, minor_ver); + + return 0; +} + +/** + * dprc_get_container_id - Get container ID associated with a given portal. + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Requested container id + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_container_id(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int *container_id) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID, + cmd_flags, + 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *container_id = (int)mc_cmd_read_object_id(&cmd); + + return 0; +} diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c new file mode 100644 index 000000000000..452c5d7a12e9 --- /dev/null +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * fsl-mc object allocator driver + * + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * + */ + +#include +#include +#include + +#include "fsl-mc-private.h" + +static bool __must_check fsl_mc_is_allocatable(struct fsl_mc_device *mc_dev) +{ + return is_fsl_mc_bus_dpbp(mc_dev) || + is_fsl_mc_bus_dpmcp(mc_dev) || + is_fsl_mc_bus_dpcon(mc_dev); +} + +/** + * fsl_mc_resource_pool_add_device - add allocatable object to a resource + * pool of a given fsl-mc bus + * + * @mc_bus: pointer to the fsl-mc bus + * @pool_type: pool type + * @mc_dev: pointer to allocatable fsl-mc device + */ +static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus + *mc_bus, + enum fsl_mc_pool_type + pool_type, + struct fsl_mc_device + *mc_dev) +{ + struct fsl_mc_resource_pool *res_pool; + struct fsl_mc_resource *resource; + struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; + int error = -EINVAL; + + if (pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES) + goto out; + if (!fsl_mc_is_allocatable(mc_dev)) + goto out; + if (mc_dev->resource) + goto out; + + res_pool = &mc_bus->resource_pools[pool_type]; + if (res_pool->type != pool_type) + goto out; + if (res_pool->mc_bus != mc_bus) + goto out; + + mutex_lock(&res_pool->mutex); + + if (res_pool->max_count < 0) + goto out_unlock; + if (res_pool->free_count < 0 || + res_pool->free_count > res_pool->max_count) + goto out_unlock; + + resource = devm_kzalloc(&mc_bus_dev->dev, sizeof(*resource), + GFP_KERNEL); + if (!resource) { + error = -ENOMEM; + dev_err(&mc_bus_dev->dev, + "Failed to allocate memory for fsl_mc_resource\n"); + goto out_unlock; + } + + resource->type = pool_type; + resource->id = mc_dev->obj_desc.id; + resource->data = mc_dev; + resource->parent_pool = res_pool; + INIT_LIST_HEAD(&resource->node); + list_add_tail(&resource->node, &res_pool->free_list); + mc_dev->resource = resource; + res_pool->free_count++; + res_pool->max_count++; + error = 0; +out_unlock: + mutex_unlock(&res_pool->mutex); +out: + return error; +} + +/** + * fsl_mc_resource_pool_remove_device - remove an allocatable device from a + * resource pool + * + * @mc_dev: pointer to allocatable fsl-mc device + * + * It permanently removes an allocatable fsl-mc device from the resource + * pool. It's an error if the device is in use. + */ +static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device + *mc_dev) +{ + struct fsl_mc_device *mc_bus_dev; + struct fsl_mc_bus *mc_bus; + struct fsl_mc_resource_pool *res_pool; + struct fsl_mc_resource *resource; + int error = -EINVAL; + + if (!fsl_mc_is_allocatable(mc_dev)) + goto out; + + resource = mc_dev->resource; + if (!resource || resource->data != mc_dev) + goto out; + + mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); + mc_bus = to_fsl_mc_bus(mc_bus_dev); + res_pool = resource->parent_pool; + if (res_pool != &mc_bus->resource_pools[resource->type]) + goto out; + + mutex_lock(&res_pool->mutex); + + if (res_pool->max_count <= 0) + goto out_unlock; + if (res_pool->free_count <= 0 || + res_pool->free_count > res_pool->max_count) + goto out_unlock; + + /* + * If the device is currently allocated, its resource is not + * in the free list and thus, the device cannot be removed. + */ + if (list_empty(&resource->node)) { + error = -EBUSY; + dev_err(&mc_bus_dev->dev, + "Device %s cannot be removed from resource pool\n", + dev_name(&mc_dev->dev)); + goto out_unlock; + } + + list_del_init(&resource->node); + res_pool->free_count--; + res_pool->max_count--; + + devm_kfree(&mc_bus_dev->dev, resource); + mc_dev->resource = NULL; + error = 0; +out_unlock: + mutex_unlock(&res_pool->mutex); +out: + return error; +} + +static const char *const fsl_mc_pool_type_strings[] = { + [FSL_MC_POOL_DPMCP] = "dpmcp", + [FSL_MC_POOL_DPBP] = "dpbp", + [FSL_MC_POOL_DPCON] = "dpcon", + [FSL_MC_POOL_IRQ] = "irq", +}; + +static int __must_check object_type_to_pool_type(const char *object_type, + enum fsl_mc_pool_type + *pool_type) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(fsl_mc_pool_type_strings); i++) { + if (strcmp(object_type, fsl_mc_pool_type_strings[i]) == 0) { + *pool_type = i; + return 0; + } + } + + return -EINVAL; +} + +int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, + enum fsl_mc_pool_type pool_type, + struct fsl_mc_resource **new_resource) +{ + struct fsl_mc_resource_pool *res_pool; + struct fsl_mc_resource *resource; + struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; + int error = -EINVAL; + + BUILD_BUG_ON(ARRAY_SIZE(fsl_mc_pool_type_strings) != + FSL_MC_NUM_POOL_TYPES); + + *new_resource = NULL; + if (pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES) + goto out; + + res_pool = &mc_bus->resource_pools[pool_type]; + if (res_pool->mc_bus != mc_bus) + goto out; + + mutex_lock(&res_pool->mutex); + resource = list_first_entry_or_null(&res_pool->free_list, + struct fsl_mc_resource, node); + + if (!resource) { + error = -ENXIO; + dev_err(&mc_bus_dev->dev, + "No more resources of type %s left\n", + fsl_mc_pool_type_strings[pool_type]); + goto out_unlock; + } + + if (resource->type != pool_type) + goto out_unlock; + if (resource->parent_pool != res_pool) + goto out_unlock; + if (res_pool->free_count <= 0 || + res_pool->free_count > res_pool->max_count) + goto out_unlock; + + list_del_init(&resource->node); + + res_pool->free_count--; + error = 0; +out_unlock: + mutex_unlock(&res_pool->mutex); + *new_resource = resource; +out: + return error; +} +EXPORT_SYMBOL_GPL(fsl_mc_resource_allocate); + +void fsl_mc_resource_free(struct fsl_mc_resource *resource) +{ + struct fsl_mc_resource_pool *res_pool; + + res_pool = resource->parent_pool; + if (resource->type != res_pool->type) + return; + + mutex_lock(&res_pool->mutex); + if (res_pool->free_count < 0 || + res_pool->free_count >= res_pool->max_count) + goto out_unlock; + + if (!list_empty(&resource->node)) + goto out_unlock; + + list_add_tail(&resource->node, &res_pool->free_list); + res_pool->free_count++; +out_unlock: + mutex_unlock(&res_pool->mutex); +} +EXPORT_SYMBOL_GPL(fsl_mc_resource_free); + +/** + * fsl_mc_object_allocate - Allocates an fsl-mc object of the given + * pool type from a given fsl-mc bus instance + * + * @mc_dev: fsl-mc device which is used in conjunction with the + * allocated object + * @pool_type: pool type + * @new_mc_dev: pointer to area where the pointer to the allocated device + * is to be returned + * + * Allocatable objects are always used in conjunction with some functional + * device. This function allocates an object of the specified type from + * the DPRC containing the functional device. + * + * NOTE: pool_type must be different from FSL_MC_POOL_MCP, since MC + * portals are allocated using fsl_mc_portal_allocate(), instead of + * this function. + */ +int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev, + enum fsl_mc_pool_type pool_type, + struct fsl_mc_device **new_mc_adev) +{ + struct fsl_mc_device *mc_bus_dev; + struct fsl_mc_bus *mc_bus; + struct fsl_mc_device *mc_adev; + int error = -EINVAL; + struct fsl_mc_resource *resource = NULL; + + *new_mc_adev = NULL; + if (mc_dev->flags & FSL_MC_IS_DPRC) + goto error; + + if (!dev_is_fsl_mc(mc_dev->dev.parent)) + goto error; + + if (pool_type == FSL_MC_POOL_DPMCP) + goto error; + + mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); + mc_bus = to_fsl_mc_bus(mc_bus_dev); + error = fsl_mc_resource_allocate(mc_bus, pool_type, &resource); + if (error < 0) + goto error; + + mc_adev = resource->data; + if (!mc_adev) + goto error; + + *new_mc_adev = mc_adev; + return 0; +error: + if (resource) + fsl_mc_resource_free(resource); + + return error; +} +EXPORT_SYMBOL_GPL(fsl_mc_object_allocate); + +/** + * fsl_mc_object_free - Returns an fsl-mc object to the resource + * pool where it came from. + * @mc_adev: Pointer to the fsl-mc device + */ +void fsl_mc_object_free(struct fsl_mc_device *mc_adev) +{ + struct fsl_mc_resource *resource; + + resource = mc_adev->resource; + if (resource->type == FSL_MC_POOL_DPMCP) + return; + if (resource->data != mc_adev) + return; + + fsl_mc_resource_free(resource); +} +EXPORT_SYMBOL_GPL(fsl_mc_object_free); + +/* + * A DPRC and the devices in the DPRC all share the same GIC-ITS device + * ID. A block of IRQs is pre-allocated and maintained in a pool + * from which devices can allocate them when needed. + */ + +/* + * Initialize the interrupt pool associated with an fsl-mc bus. + * It allocates a block of IRQs from the GIC-ITS. + */ +int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, + unsigned int irq_count) +{ + unsigned int i; + struct msi_desc *msi_desc; + struct fsl_mc_device_irq *irq_resources; + struct fsl_mc_device_irq *mc_dev_irq; + int error; + struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; + struct fsl_mc_resource_pool *res_pool = + &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; + + if (irq_count == 0 || + irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) + return -EINVAL; + + error = fsl_mc_msi_domain_alloc_irqs(&mc_bus_dev->dev, irq_count); + if (error < 0) + return error; + + irq_resources = devm_kzalloc(&mc_bus_dev->dev, + sizeof(*irq_resources) * irq_count, + GFP_KERNEL); + if (!irq_resources) { + error = -ENOMEM; + goto cleanup_msi_irqs; + } + + for (i = 0; i < irq_count; i++) { + mc_dev_irq = &irq_resources[i]; + + /* + * NOTE: This mc_dev_irq's MSI addr/value pair will be set + * by the fsl_mc_msi_write_msg() callback + */ + mc_dev_irq->resource.type = res_pool->type; + mc_dev_irq->resource.data = mc_dev_irq; + mc_dev_irq->resource.parent_pool = res_pool; + INIT_LIST_HEAD(&mc_dev_irq->resource.node); + list_add_tail(&mc_dev_irq->resource.node, &res_pool->free_list); + } + + for_each_msi_entry(msi_desc, &mc_bus_dev->dev) { + mc_dev_irq = &irq_resources[msi_desc->fsl_mc.msi_index]; + mc_dev_irq->msi_desc = msi_desc; + mc_dev_irq->resource.id = msi_desc->irq; + } + + res_pool->max_count = irq_count; + res_pool->free_count = irq_count; + mc_bus->irq_resources = irq_resources; + return 0; + +cleanup_msi_irqs: + fsl_mc_msi_domain_free_irqs(&mc_bus_dev->dev); + return error; +} +EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool); + +/** + * Teardown the interrupt pool associated with an fsl-mc bus. + * It frees the IRQs that were allocated to the pool, back to the GIC-ITS. + */ +void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus) +{ + struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; + struct fsl_mc_resource_pool *res_pool = + &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; + + if (!mc_bus->irq_resources) + return; + + if (res_pool->max_count == 0) + return; + + if (res_pool->free_count != res_pool->max_count) + return; + + INIT_LIST_HEAD(&res_pool->free_list); + res_pool->max_count = 0; + res_pool->free_count = 0; + mc_bus->irq_resources = NULL; + fsl_mc_msi_domain_free_irqs(&mc_bus_dev->dev); +} +EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool); + +/** + * Allocate the IRQs required by a given fsl-mc device. + */ +int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev) +{ + int i; + int irq_count; + int res_allocated_count = 0; + int error = -EINVAL; + struct fsl_mc_device_irq **irqs = NULL; + struct fsl_mc_bus *mc_bus; + struct fsl_mc_resource_pool *res_pool; + + if (mc_dev->irqs) + return -EINVAL; + + irq_count = mc_dev->obj_desc.irq_count; + if (irq_count == 0) + return -EINVAL; + + if (is_fsl_mc_bus_dprc(mc_dev)) + mc_bus = to_fsl_mc_bus(mc_dev); + else + mc_bus = to_fsl_mc_bus(to_fsl_mc_device(mc_dev->dev.parent)); + + if (!mc_bus->irq_resources) + return -EINVAL; + + res_pool = &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; + if (res_pool->free_count < irq_count) { + dev_err(&mc_dev->dev, + "Not able to allocate %u irqs for device\n", irq_count); + return -ENOSPC; + } + + irqs = devm_kzalloc(&mc_dev->dev, irq_count * sizeof(irqs[0]), + GFP_KERNEL); + if (!irqs) + return -ENOMEM; + + for (i = 0; i < irq_count; i++) { + struct fsl_mc_resource *resource; + + error = fsl_mc_resource_allocate(mc_bus, FSL_MC_POOL_IRQ, + &resource); + if (error < 0) + goto error_resource_alloc; + + irqs[i] = to_fsl_mc_irq(resource); + res_allocated_count++; + + irqs[i]->mc_dev = mc_dev; + irqs[i]->dev_irq_index = i; + } + + mc_dev->irqs = irqs; + return 0; + +error_resource_alloc: + for (i = 0; i < res_allocated_count; i++) { + irqs[i]->mc_dev = NULL; + fsl_mc_resource_free(&irqs[i]->resource); + } + + return error; +} +EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs); + +/* + * Frees the IRQs that were allocated for an fsl-mc device. + */ +void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev) +{ + int i; + int irq_count; + struct fsl_mc_bus *mc_bus; + struct fsl_mc_device_irq **irqs = mc_dev->irqs; + + if (!irqs) + return; + + irq_count = mc_dev->obj_desc.irq_count; + + if (is_fsl_mc_bus_dprc(mc_dev)) + mc_bus = to_fsl_mc_bus(mc_dev); + else + mc_bus = to_fsl_mc_bus(to_fsl_mc_device(mc_dev->dev.parent)); + + if (!mc_bus->irq_resources) + return; + + for (i = 0; i < irq_count; i++) { + irqs[i]->mc_dev = NULL; + fsl_mc_resource_free(&irqs[i]->resource); + } + + mc_dev->irqs = NULL; +} +EXPORT_SYMBOL_GPL(fsl_mc_free_irqs); + +void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev) +{ + int pool_type; + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); + + for (pool_type = 0; pool_type < FSL_MC_NUM_POOL_TYPES; pool_type++) { + struct fsl_mc_resource_pool *res_pool = + &mc_bus->resource_pools[pool_type]; + + res_pool->type = pool_type; + res_pool->max_count = 0; + res_pool->free_count = 0; + res_pool->mc_bus = mc_bus; + INIT_LIST_HEAD(&res_pool->free_list); + mutex_init(&res_pool->mutex); + } +} + +static void fsl_mc_cleanup_resource_pool(struct fsl_mc_device *mc_bus_dev, + enum fsl_mc_pool_type pool_type) +{ + struct fsl_mc_resource *resource; + struct fsl_mc_resource *next; + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); + struct fsl_mc_resource_pool *res_pool = + &mc_bus->resource_pools[pool_type]; + int free_count = 0; + + list_for_each_entry_safe(resource, next, &res_pool->free_list, node) { + free_count++; + devm_kfree(&mc_bus_dev->dev, resource); + } +} + +void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) +{ + int pool_type; + + for (pool_type = 0; pool_type < FSL_MC_NUM_POOL_TYPES; pool_type++) + fsl_mc_cleanup_resource_pool(mc_bus_dev, pool_type); +} + +/** + * fsl_mc_allocator_probe - callback invoked when an allocatable device is + * being added to the system + */ +static int fsl_mc_allocator_probe(struct fsl_mc_device *mc_dev) +{ + enum fsl_mc_pool_type pool_type; + struct fsl_mc_device *mc_bus_dev; + struct fsl_mc_bus *mc_bus; + int error; + + if (!fsl_mc_is_allocatable(mc_dev)) + return -EINVAL; + + mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); + if (!dev_is_fsl_mc(&mc_bus_dev->dev)) + return -EINVAL; + + mc_bus = to_fsl_mc_bus(mc_bus_dev); + error = object_type_to_pool_type(mc_dev->obj_desc.type, &pool_type); + if (error < 0) + return error; + + error = fsl_mc_resource_pool_add_device(mc_bus, pool_type, mc_dev); + if (error < 0) + return error; + + dev_dbg(&mc_dev->dev, + "Allocatable fsl-mc device bound to fsl_mc_allocator driver"); + return 0; +} + +/** + * fsl_mc_allocator_remove - callback invoked when an allocatable device is + * being removed from the system + */ +static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) +{ + int error; + + if (!fsl_mc_is_allocatable(mc_dev)) + return -EINVAL; + + if (mc_dev->resource) { + error = fsl_mc_resource_pool_remove_device(mc_dev); + if (error < 0) + return error; + } + + dev_dbg(&mc_dev->dev, + "Allocatable fsl-mc device unbound from fsl_mc_allocator driver"); + return 0; +} + +static const struct fsl_mc_device_id match_id_table[] = { + { + .vendor = FSL_MC_VENDOR_FREESCALE, + .obj_type = "dpbp", + }, + { + .vendor = FSL_MC_VENDOR_FREESCALE, + .obj_type = "dpmcp", + }, + { + .vendor = FSL_MC_VENDOR_FREESCALE, + .obj_type = "dpcon", + }, + {.vendor = 0x0}, +}; + +static struct fsl_mc_driver fsl_mc_allocator_driver = { + .driver = { + .name = "fsl_mc_allocator", + .pm = NULL, + }, + .match_id_table = match_id_table, + .probe = fsl_mc_allocator_probe, + .remove = fsl_mc_allocator_remove, +}; + +int __init fsl_mc_allocator_driver_init(void) +{ + return fsl_mc_driver_register(&fsl_mc_allocator_driver); +} diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c new file mode 100644 index 000000000000..1b333c43aae9 --- /dev/null +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -0,0 +1,948 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Freescale Management Complex (MC) bus driver + * + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Author: German Rivera + * + */ + +#define pr_fmt(fmt) "fsl-mc: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fsl-mc-private.h" + +/** + * Default DMA mask for devices on a fsl-mc bus + */ +#define FSL_MC_DEFAULT_DMA_MASK (~0ULL) + +/** + * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device + * @root_mc_bus_dev: fsl-mc device representing the root DPRC + * @num_translation_ranges: number of entries in addr_translation_ranges + * @translation_ranges: array of bus to system address translation ranges + */ +struct fsl_mc { + struct fsl_mc_device *root_mc_bus_dev; + u8 num_translation_ranges; + struct fsl_mc_addr_translation_range *translation_ranges; +}; + +/** + * struct fsl_mc_addr_translation_range - bus to system address translation + * range + * @mc_region_type: Type of MC region for the range being translated + * @start_mc_offset: Start MC offset of the range being translated + * @end_mc_offset: MC offset of the first byte after the range (last MC + * offset of the range is end_mc_offset - 1) + * @start_phys_addr: system physical address corresponding to start_mc_addr + */ +struct fsl_mc_addr_translation_range { + enum dprc_region_type mc_region_type; + u64 start_mc_offset; + u64 end_mc_offset; + phys_addr_t start_phys_addr; +}; + +/** + * struct mc_version + * @major: Major version number: incremented on API compatibility changes + * @minor: Minor version number: incremented on API additions (that are + * backward compatible); reset when major version is incremented + * @revision: Internal revision number: incremented on implementation changes + * and/or bug fixes that have no impact on API + */ +struct mc_version { + u32 major; + u32 minor; + u32 revision; +}; + +/** + * fsl_mc_bus_match - device to driver matching callback + * @dev: the fsl-mc device to match against + * @drv: the device driver to search for matching fsl-mc object type + * structures + * + * Returns 1 on success, 0 otherwise. + */ +static int fsl_mc_bus_match(struct device *dev, struct device_driver *drv) +{ + const struct fsl_mc_device_id *id; + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv); + bool found = false; + + if (!mc_drv->match_id_table) + goto out; + + /* + * If the object is not 'plugged' don't match. + * Only exception is the root DPRC, which is a special case. + */ + if ((mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED) == 0 && + !fsl_mc_is_root_dprc(&mc_dev->dev)) + goto out; + + /* + * Traverse the match_id table of the given driver, trying to find + * a matching for the given device. + */ + for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) { + if (id->vendor == mc_dev->obj_desc.vendor && + strcmp(id->obj_type, mc_dev->obj_desc.type) == 0) { + found = true; + + break; + } + } + +out: + dev_dbg(dev, "%smatched\n", found ? "" : "not "); + return found; +} + +/** + * fsl_mc_bus_uevent - callback invoked when a device is added + */ +static int fsl_mc_bus_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + + if (add_uevent_var(env, "MODALIAS=fsl-mc:v%08Xd%s", + mc_dev->obj_desc.vendor, + mc_dev->obj_desc.type)) + return -ENOMEM; + + return 0; +} + +static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + + return sprintf(buf, "fsl-mc:v%08Xd%s\n", mc_dev->obj_desc.vendor, + mc_dev->obj_desc.type); +} +static DEVICE_ATTR_RO(modalias); + +static struct attribute *fsl_mc_dev_attrs[] = { + &dev_attr_modalias.attr, + NULL, +}; + +ATTRIBUTE_GROUPS(fsl_mc_dev); + +struct bus_type fsl_mc_bus_type = { + .name = "fsl-mc", + .match = fsl_mc_bus_match, + .uevent = fsl_mc_bus_uevent, + .dev_groups = fsl_mc_dev_groups, +}; +EXPORT_SYMBOL_GPL(fsl_mc_bus_type); + +struct device_type fsl_mc_bus_dprc_type = { + .name = "fsl_mc_bus_dprc" +}; + +struct device_type fsl_mc_bus_dpni_type = { + .name = "fsl_mc_bus_dpni" +}; + +struct device_type fsl_mc_bus_dpio_type = { + .name = "fsl_mc_bus_dpio" +}; + +struct device_type fsl_mc_bus_dpsw_type = { + .name = "fsl_mc_bus_dpsw" +}; + +struct device_type fsl_mc_bus_dpbp_type = { + .name = "fsl_mc_bus_dpbp" +}; + +struct device_type fsl_mc_bus_dpcon_type = { + .name = "fsl_mc_bus_dpcon" +}; + +struct device_type fsl_mc_bus_dpmcp_type = { + .name = "fsl_mc_bus_dpmcp" +}; + +struct device_type fsl_mc_bus_dpmac_type = { + .name = "fsl_mc_bus_dpmac" +}; + +struct device_type fsl_mc_bus_dprtc_type = { + .name = "fsl_mc_bus_dprtc" +}; + +static struct device_type *fsl_mc_get_device_type(const char *type) +{ + static const struct { + struct device_type *dev_type; + const char *type; + } dev_types[] = { + { &fsl_mc_bus_dprc_type, "dprc" }, + { &fsl_mc_bus_dpni_type, "dpni" }, + { &fsl_mc_bus_dpio_type, "dpio" }, + { &fsl_mc_bus_dpsw_type, "dpsw" }, + { &fsl_mc_bus_dpbp_type, "dpbp" }, + { &fsl_mc_bus_dpcon_type, "dpcon" }, + { &fsl_mc_bus_dpmcp_type, "dpmcp" }, + { &fsl_mc_bus_dpmac_type, "dpmac" }, + { &fsl_mc_bus_dprtc_type, "dprtc" }, + { NULL, NULL } + }; + int i; + + for (i = 0; dev_types[i].dev_type; i++) + if (!strcmp(dev_types[i].type, type)) + return dev_types[i].dev_type; + + return NULL; +} + +static int fsl_mc_driver_probe(struct device *dev) +{ + struct fsl_mc_driver *mc_drv; + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + int error; + + mc_drv = to_fsl_mc_driver(dev->driver); + + error = mc_drv->probe(mc_dev); + if (error < 0) { + if (error != -EPROBE_DEFER) + dev_err(dev, "%s failed: %d\n", __func__, error); + return error; + } + + return 0; +} + +static int fsl_mc_driver_remove(struct device *dev) +{ + struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver); + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + int error; + + error = mc_drv->remove(mc_dev); + if (error < 0) { + dev_err(dev, "%s failed: %d\n", __func__, error); + return error; + } + + return 0; +} + +static void fsl_mc_driver_shutdown(struct device *dev) +{ + struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver); + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + + mc_drv->shutdown(mc_dev); +} + +/** + * __fsl_mc_driver_register - registers a child device driver with the + * MC bus + * + * This function is implicitly invoked from the registration function of + * fsl_mc device drivers, which is generated by the + * module_fsl_mc_driver() macro. + */ +int __fsl_mc_driver_register(struct fsl_mc_driver *mc_driver, + struct module *owner) +{ + int error; + + mc_driver->driver.owner = owner; + mc_driver->driver.bus = &fsl_mc_bus_type; + + if (mc_driver->probe) + mc_driver->driver.probe = fsl_mc_driver_probe; + + if (mc_driver->remove) + mc_driver->driver.remove = fsl_mc_driver_remove; + + if (mc_driver->shutdown) + mc_driver->driver.shutdown = fsl_mc_driver_shutdown; + + error = driver_register(&mc_driver->driver); + if (error < 0) { + pr_err("driver_register() failed for %s: %d\n", + mc_driver->driver.name, error); + return error; + } + + return 0; +} +EXPORT_SYMBOL_GPL(__fsl_mc_driver_register); + +/** + * fsl_mc_driver_unregister - unregisters a device driver from the + * MC bus + */ +void fsl_mc_driver_unregister(struct fsl_mc_driver *mc_driver) +{ + driver_unregister(&mc_driver->driver); +} +EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister); + +/** + * mc_get_version() - Retrieves the Management Complex firmware + * version information + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @mc_ver_info: Returned version information structure + * + * Return: '0' on Success; Error code otherwise. + */ +static int mc_get_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + struct mc_version *mc_ver_info) +{ + struct mc_command cmd = { 0 }; + struct dpmng_rsp_get_version *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION, + cmd_flags, + 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpmng_rsp_get_version *)cmd.params; + mc_ver_info->revision = le32_to_cpu(rsp_params->revision); + mc_ver_info->major = le32_to_cpu(rsp_params->version_major); + mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor); + + return 0; +} + +/** + * fsl_mc_get_root_dprc - function to traverse to the root dprc + */ +static void fsl_mc_get_root_dprc(struct device *dev, + struct device **root_dprc_dev) +{ + if (!dev) { + *root_dprc_dev = NULL; + } else if (!dev_is_fsl_mc(dev)) { + *root_dprc_dev = NULL; + } else { + *root_dprc_dev = dev; + while (dev_is_fsl_mc((*root_dprc_dev)->parent)) + *root_dprc_dev = (*root_dprc_dev)->parent; + } +} + +static int get_dprc_attr(struct fsl_mc_io *mc_io, + int container_id, struct dprc_attributes *attr) +{ + u16 dprc_handle; + int error; + + error = dprc_open(mc_io, 0, container_id, &dprc_handle); + if (error < 0) { + dev_err(mc_io->dev, "dprc_open() failed: %d\n", error); + return error; + } + + memset(attr, 0, sizeof(struct dprc_attributes)); + error = dprc_get_attributes(mc_io, 0, dprc_handle, attr); + if (error < 0) { + dev_err(mc_io->dev, "dprc_get_attributes() failed: %d\n", + error); + goto common_cleanup; + } + + error = 0; + +common_cleanup: + (void)dprc_close(mc_io, 0, dprc_handle); + return error; +} + +static int get_dprc_icid(struct fsl_mc_io *mc_io, + int container_id, u16 *icid) +{ + struct dprc_attributes attr; + int error; + + error = get_dprc_attr(mc_io, container_id, &attr); + if (error == 0) + *icid = attr.icid; + + return error; +} + +static int translate_mc_addr(struct fsl_mc_device *mc_dev, + enum dprc_region_type mc_region_type, + u64 mc_offset, phys_addr_t *phys_addr) +{ + int i; + struct device *root_dprc_dev; + struct fsl_mc *mc; + + fsl_mc_get_root_dprc(&mc_dev->dev, &root_dprc_dev); + mc = dev_get_drvdata(root_dprc_dev->parent); + + if (mc->num_translation_ranges == 0) { + /* + * Do identity mapping: + */ + *phys_addr = mc_offset; + return 0; + } + + for (i = 0; i < mc->num_translation_ranges; i++) { + struct fsl_mc_addr_translation_range *range = + &mc->translation_ranges[i]; + + if (mc_region_type == range->mc_region_type && + mc_offset >= range->start_mc_offset && + mc_offset < range->end_mc_offset) { + *phys_addr = range->start_phys_addr + + (mc_offset - range->start_mc_offset); + return 0; + } + } + + return -EFAULT; +} + +static int fsl_mc_device_get_mmio_regions(struct fsl_mc_device *mc_dev, + struct fsl_mc_device *mc_bus_dev) +{ + int i; + int error; + struct resource *regions; + struct fsl_mc_obj_desc *obj_desc = &mc_dev->obj_desc; + struct device *parent_dev = mc_dev->dev.parent; + enum dprc_region_type mc_region_type; + + if (is_fsl_mc_bus_dprc(mc_dev) || + is_fsl_mc_bus_dpmcp(mc_dev)) { + mc_region_type = DPRC_REGION_TYPE_MC_PORTAL; + } else if (is_fsl_mc_bus_dpio(mc_dev)) { + mc_region_type = DPRC_REGION_TYPE_QBMAN_PORTAL; + } else { + /* + * This function should not have been called for this MC object + * type, as this object type is not supposed to have MMIO + * regions + */ + return -EINVAL; + } + + regions = kmalloc_array(obj_desc->region_count, + sizeof(regions[0]), GFP_KERNEL); + if (!regions) + return -ENOMEM; + + for (i = 0; i < obj_desc->region_count; i++) { + struct dprc_region_desc region_desc; + + error = dprc_get_obj_region(mc_bus_dev->mc_io, + 0, + mc_bus_dev->mc_handle, + obj_desc->type, + obj_desc->id, i, ®ion_desc); + if (error < 0) { + dev_err(parent_dev, + "dprc_get_obj_region() failed: %d\n", error); + goto error_cleanup_regions; + } + + error = translate_mc_addr(mc_dev, mc_region_type, + region_desc.base_offset, + ®ions[i].start); + if (error < 0) { + dev_err(parent_dev, + "Invalid MC offset: %#x (for %s.%d\'s region %d)\n", + region_desc.base_offset, + obj_desc->type, obj_desc->id, i); + goto error_cleanup_regions; + } + + regions[i].end = regions[i].start + region_desc.size - 1; + regions[i].name = "fsl-mc object MMIO region"; + regions[i].flags = IORESOURCE_IO; + if (region_desc.flags & DPRC_REGION_CACHEABLE) + regions[i].flags |= IORESOURCE_CACHEABLE; + } + + mc_dev->regions = regions; + return 0; + +error_cleanup_regions: + kfree(regions); + return error; +} + +/** + * fsl_mc_is_root_dprc - function to check if a given device is a root dprc + */ +bool fsl_mc_is_root_dprc(struct device *dev) +{ + struct device *root_dprc_dev; + + fsl_mc_get_root_dprc(dev, &root_dprc_dev); + if (!root_dprc_dev) + return false; + return dev == root_dprc_dev; +} + +static void fsl_mc_device_release(struct device *dev) +{ + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); + + kfree(mc_dev->regions); + + if (is_fsl_mc_bus_dprc(mc_dev)) + kfree(to_fsl_mc_bus(mc_dev)); + else + kfree(mc_dev); +} + +/** + * Add a newly discovered fsl-mc device to be visible in Linux + */ +int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, + struct fsl_mc_io *mc_io, + struct device *parent_dev, + struct fsl_mc_device **new_mc_dev) +{ + int error; + struct fsl_mc_device *mc_dev = NULL; + struct fsl_mc_bus *mc_bus = NULL; + struct fsl_mc_device *parent_mc_dev; + + if (dev_is_fsl_mc(parent_dev)) + parent_mc_dev = to_fsl_mc_device(parent_dev); + else + parent_mc_dev = NULL; + + if (strcmp(obj_desc->type, "dprc") == 0) { + /* + * Allocate an MC bus device object: + */ + mc_bus = kzalloc(sizeof(*mc_bus), GFP_KERNEL); + if (!mc_bus) + return -ENOMEM; + + mc_dev = &mc_bus->mc_dev; + } else { + /* + * Allocate a regular fsl_mc_device object: + */ + mc_dev = kzalloc(sizeof(*mc_dev), GFP_KERNEL); + if (!mc_dev) + return -ENOMEM; + } + + mc_dev->obj_desc = *obj_desc; + mc_dev->mc_io = mc_io; + device_initialize(&mc_dev->dev); + mc_dev->dev.parent = parent_dev; + mc_dev->dev.bus = &fsl_mc_bus_type; + mc_dev->dev.release = fsl_mc_device_release; + mc_dev->dev.type = fsl_mc_get_device_type(obj_desc->type); + if (!mc_dev->dev.type) { + error = -ENODEV; + dev_err(parent_dev, "unknown device type %s\n", obj_desc->type); + goto error_cleanup_dev; + } + dev_set_name(&mc_dev->dev, "%s.%d", obj_desc->type, obj_desc->id); + + if (strcmp(obj_desc->type, "dprc") == 0) { + struct fsl_mc_io *mc_io2; + + mc_dev->flags |= FSL_MC_IS_DPRC; + + /* + * To get the DPRC's ICID, we need to open the DPRC + * in get_dprc_icid(). For child DPRCs, we do so using the + * parent DPRC's MC portal instead of the child DPRC's MC + * portal, in case the child DPRC is already opened with + * its own portal (e.g., the DPRC used by AIOP). + * + * NOTE: There cannot be more than one active open for a + * given MC object, using the same MC portal. + */ + if (parent_mc_dev) { + /* + * device being added is a child DPRC device + */ + mc_io2 = parent_mc_dev->mc_io; + } else { + /* + * device being added is the root DPRC device + */ + if (!mc_io) { + error = -EINVAL; + goto error_cleanup_dev; + } + + mc_io2 = mc_io; + } + + error = get_dprc_icid(mc_io2, obj_desc->id, &mc_dev->icid); + if (error < 0) + goto error_cleanup_dev; + } else { + /* + * A non-DPRC object has to be a child of a DPRC, use the + * parent's ICID and interrupt domain. + */ + mc_dev->icid = parent_mc_dev->icid; + mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK; + mc_dev->dev.dma_mask = &mc_dev->dma_mask; + dev_set_msi_domain(&mc_dev->dev, + dev_get_msi_domain(&parent_mc_dev->dev)); + } + + /* + * Get MMIO regions for the device from the MC: + * + * NOTE: the root DPRC is a special case as its MMIO region is + * obtained from the device tree + */ + if (parent_mc_dev && obj_desc->region_count != 0) { + error = fsl_mc_device_get_mmio_regions(mc_dev, + parent_mc_dev); + if (error < 0) + goto error_cleanup_dev; + } + + /* Objects are coherent, unless 'no shareability' flag set. */ + if (!(obj_desc->flags & FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY)) + arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true); + + /* + * The device-specific probe callback will get invoked by device_add() + */ + error = device_add(&mc_dev->dev); + if (error < 0) { + dev_err(parent_dev, + "device_add() failed for device %s: %d\n", + dev_name(&mc_dev->dev), error); + goto error_cleanup_dev; + } + + dev_dbg(parent_dev, "added %s\n", dev_name(&mc_dev->dev)); + + *new_mc_dev = mc_dev; + return 0; + +error_cleanup_dev: + kfree(mc_dev->regions); + kfree(mc_bus); + kfree(mc_dev); + + return error; +} +EXPORT_SYMBOL_GPL(fsl_mc_device_add); + +/** + * fsl_mc_device_remove - Remove an fsl-mc device from being visible to + * Linux + * + * @mc_dev: Pointer to an fsl-mc device + */ +void fsl_mc_device_remove(struct fsl_mc_device *mc_dev) +{ + /* + * The device-specific remove callback will get invoked by device_del() + */ + device_del(&mc_dev->dev); + put_device(&mc_dev->dev); +} +EXPORT_SYMBOL_GPL(fsl_mc_device_remove); + +static int parse_mc_ranges(struct device *dev, + int *paddr_cells, + int *mc_addr_cells, + int *mc_size_cells, + const __be32 **ranges_start) +{ + const __be32 *prop; + int range_tuple_cell_count; + int ranges_len; + int tuple_len; + struct device_node *mc_node = dev->of_node; + + *ranges_start = of_get_property(mc_node, "ranges", &ranges_len); + if (!(*ranges_start) || !ranges_len) { + dev_warn(dev, + "missing or empty ranges property for device tree node '%s'\n", + mc_node->name); + return 0; + } + + *paddr_cells = of_n_addr_cells(mc_node); + + prop = of_get_property(mc_node, "#address-cells", NULL); + if (prop) + *mc_addr_cells = be32_to_cpup(prop); + else + *mc_addr_cells = *paddr_cells; + + prop = of_get_property(mc_node, "#size-cells", NULL); + if (prop) + *mc_size_cells = be32_to_cpup(prop); + else + *mc_size_cells = of_n_size_cells(mc_node); + + range_tuple_cell_count = *paddr_cells + *mc_addr_cells + + *mc_size_cells; + + tuple_len = range_tuple_cell_count * sizeof(__be32); + if (ranges_len % tuple_len != 0) { + dev_err(dev, "malformed ranges property '%s'\n", mc_node->name); + return -EINVAL; + } + + return ranges_len / tuple_len; +} + +static int get_mc_addr_translation_ranges(struct device *dev, + struct fsl_mc_addr_translation_range + **ranges, + u8 *num_ranges) +{ + int ret; + int paddr_cells; + int mc_addr_cells; + int mc_size_cells; + int i; + const __be32 *ranges_start; + const __be32 *cell; + + ret = parse_mc_ranges(dev, + &paddr_cells, + &mc_addr_cells, + &mc_size_cells, + &ranges_start); + if (ret < 0) + return ret; + + *num_ranges = ret; + if (!ret) { + /* + * Missing or empty ranges property ("ranges;") for the + * 'fsl,qoriq-mc' node. In this case, identity mapping + * will be used. + */ + *ranges = NULL; + return 0; + } + + *ranges = devm_kcalloc(dev, *num_ranges, + sizeof(struct fsl_mc_addr_translation_range), + GFP_KERNEL); + if (!(*ranges)) + return -ENOMEM; + + cell = ranges_start; + for (i = 0; i < *num_ranges; ++i) { + struct fsl_mc_addr_translation_range *range = &(*ranges)[i]; + + range->mc_region_type = of_read_number(cell, 1); + range->start_mc_offset = of_read_number(cell + 1, + mc_addr_cells - 1); + cell += mc_addr_cells; + range->start_phys_addr = of_read_number(cell, paddr_cells); + cell += paddr_cells; + range->end_mc_offset = range->start_mc_offset + + of_read_number(cell, mc_size_cells); + + cell += mc_size_cells; + } + + return 0; +} + +/** + * fsl_mc_bus_probe - callback invoked when the root MC bus is being + * added + */ +static int fsl_mc_bus_probe(struct platform_device *pdev) +{ + struct fsl_mc_obj_desc obj_desc; + int error; + struct fsl_mc *mc; + struct fsl_mc_device *mc_bus_dev = NULL; + struct fsl_mc_io *mc_io = NULL; + int container_id; + phys_addr_t mc_portal_phys_addr; + u32 mc_portal_size; + struct mc_version mc_version; + struct resource res; + + mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); + if (!mc) + return -ENOMEM; + + platform_set_drvdata(pdev, mc); + + /* + * Get physical address of MC portal for the root DPRC: + */ + error = of_address_to_resource(pdev->dev.of_node, 0, &res); + if (error < 0) { + dev_err(&pdev->dev, + "of_address_to_resource() failed for %pOF\n", + pdev->dev.of_node); + return error; + } + + mc_portal_phys_addr = res.start; + mc_portal_size = resource_size(&res); + error = fsl_create_mc_io(&pdev->dev, mc_portal_phys_addr, + mc_portal_size, NULL, + FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, &mc_io); + if (error < 0) + return error; + + error = mc_get_version(mc_io, 0, &mc_version); + if (error != 0) { + dev_err(&pdev->dev, + "mc_get_version() failed with error %d\n", error); + goto error_cleanup_mc_io; + } + + dev_info(&pdev->dev, "MC firmware version: %u.%u.%u\n", + mc_version.major, mc_version.minor, mc_version.revision); + + error = get_mc_addr_translation_ranges(&pdev->dev, + &mc->translation_ranges, + &mc->num_translation_ranges); + if (error < 0) + goto error_cleanup_mc_io; + + error = dprc_get_container_id(mc_io, 0, &container_id); + if (error < 0) { + dev_err(&pdev->dev, + "dprc_get_container_id() failed: %d\n", error); + goto error_cleanup_mc_io; + } + + memset(&obj_desc, 0, sizeof(struct fsl_mc_obj_desc)); + error = dprc_get_api_version(mc_io, 0, + &obj_desc.ver_major, + &obj_desc.ver_minor); + if (error < 0) + goto error_cleanup_mc_io; + + obj_desc.vendor = FSL_MC_VENDOR_FREESCALE; + strcpy(obj_desc.type, "dprc"); + obj_desc.id = container_id; + obj_desc.irq_count = 1; + obj_desc.region_count = 0; + + error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev); + if (error < 0) + goto error_cleanup_mc_io; + + mc->root_mc_bus_dev = mc_bus_dev; + return 0; + +error_cleanup_mc_io: + fsl_destroy_mc_io(mc_io); + return error; +} + +/** + * fsl_mc_bus_remove - callback invoked when the root MC bus is being + * removed + */ +static int fsl_mc_bus_remove(struct platform_device *pdev) +{ + struct fsl_mc *mc = platform_get_drvdata(pdev); + + if (!fsl_mc_is_root_dprc(&mc->root_mc_bus_dev->dev)) + return -EINVAL; + + fsl_mc_device_remove(mc->root_mc_bus_dev); + + fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io); + mc->root_mc_bus_dev->mc_io = NULL; + + return 0; +} + +static const struct of_device_id fsl_mc_bus_match_table[] = { + {.compatible = "fsl,qoriq-mc",}, + {}, +}; + +MODULE_DEVICE_TABLE(of, fsl_mc_bus_match_table); + +static struct platform_driver fsl_mc_bus_driver = { + .driver = { + .name = "fsl_mc_bus", + .pm = NULL, + .of_match_table = fsl_mc_bus_match_table, + }, + .probe = fsl_mc_bus_probe, + .remove = fsl_mc_bus_remove, +}; + +static int __init fsl_mc_bus_driver_init(void) +{ + int error; + + error = bus_register(&fsl_mc_bus_type); + if (error < 0) { + pr_err("bus type registration failed: %d\n", error); + goto error_cleanup_cache; + } + + error = platform_driver_register(&fsl_mc_bus_driver); + if (error < 0) { + pr_err("platform_driver_register() failed: %d\n", error); + goto error_cleanup_bus; + } + + error = dprc_driver_init(); + if (error < 0) + goto error_cleanup_driver; + + error = fsl_mc_allocator_driver_init(); + if (error < 0) + goto error_cleanup_dprc_driver; + + return 0; + +error_cleanup_dprc_driver: + dprc_driver_exit(); + +error_cleanup_driver: + platform_driver_unregister(&fsl_mc_bus_driver); + +error_cleanup_bus: + bus_unregister(&fsl_mc_bus_type); + +error_cleanup_cache: + return error; +} +postcore_initcall(fsl_mc_bus_driver_init); diff --git a/drivers/bus/fsl-mc/fsl-mc-msi.c b/drivers/bus/fsl-mc/fsl-mc-msi.c new file mode 100644 index 000000000000..ec35e255b496 --- /dev/null +++ b/drivers/bus/fsl-mc/fsl-mc-msi.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Freescale Management Complex (MC) bus driver MSI support + * + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Author: German Rivera + * + */ + +#include +#include +#include +#include +#include +#include + +#include "fsl-mc-private.h" + +#ifdef GENERIC_MSI_DOMAIN_OPS +/* + * Generate a unique ID identifying the interrupt (only used within the MSI + * irqdomain. Combine the icid with the interrupt index. + */ +static irq_hw_number_t fsl_mc_domain_calc_hwirq(struct fsl_mc_device *dev, + struct msi_desc *desc) +{ + /* + * Make the base hwirq value for ICID*10000 so it is readable + * as a decimal value in /proc/interrupts. + */ + return (irq_hw_number_t)(desc->fsl_mc.msi_index + (dev->icid * 10000)); +} + +static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg, + struct msi_desc *desc) +{ + arg->desc = desc; + arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), + desc); +} +#else +#define fsl_mc_msi_set_desc NULL +#endif + +static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info) +{ + struct msi_domain_ops *ops = info->ops; + + if (!ops) + return; + + /* + * set_desc should not be set by the caller + */ + if (!ops->set_desc) + ops->set_desc = fsl_mc_msi_set_desc; +} + +static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev, + struct fsl_mc_device_irq *mc_dev_irq) +{ + int error; + struct fsl_mc_device *owner_mc_dev = mc_dev_irq->mc_dev; + struct msi_desc *msi_desc = mc_dev_irq->msi_desc; + struct dprc_irq_cfg irq_cfg; + + /* + * msi_desc->msg.address is 0x0 when this function is invoked in + * the free_irq() code path. In this case, for the MC, we don't + * really need to "unprogram" the MSI, so we just return. + */ + if (msi_desc->msg.address_lo == 0x0 && msi_desc->msg.address_hi == 0x0) + return; + + if (!owner_mc_dev) + return; + + irq_cfg.paddr = ((u64)msi_desc->msg.address_hi << 32) | + msi_desc->msg.address_lo; + irq_cfg.val = msi_desc->msg.data; + irq_cfg.irq_num = msi_desc->irq; + + if (owner_mc_dev == mc_bus_dev) { + /* + * IRQ is for the mc_bus_dev's DPRC itself + */ + error = dprc_set_irq(mc_bus_dev->mc_io, + MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, + mc_bus_dev->mc_handle, + mc_dev_irq->dev_irq_index, + &irq_cfg); + if (error < 0) { + dev_err(&owner_mc_dev->dev, + "dprc_set_irq() failed: %d\n", error); + } + } else { + /* + * IRQ is for for a child device of mc_bus_dev + */ + error = dprc_set_obj_irq(mc_bus_dev->mc_io, + MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, + mc_bus_dev->mc_handle, + owner_mc_dev->obj_desc.type, + owner_mc_dev->obj_desc.id, + mc_dev_irq->dev_irq_index, + &irq_cfg); + if (error < 0) { + dev_err(&owner_mc_dev->dev, + "dprc_obj_set_irq() failed: %d\n", error); + } + } +} + +/* + * NOTE: This function is invoked with interrupts disabled + */ +static void fsl_mc_msi_write_msg(struct irq_data *irq_data, + struct msi_msg *msg) +{ + struct msi_desc *msi_desc = irq_data_get_msi_desc(irq_data); + struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev); + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); + struct fsl_mc_device_irq *mc_dev_irq = + &mc_bus->irq_resources[msi_desc->fsl_mc.msi_index]; + + msi_desc->msg = *msg; + + /* + * Program the MSI (paddr, value) pair in the device: + */ + __fsl_mc_msi_write_msg(mc_bus_dev, mc_dev_irq); +} + +static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info) +{ + struct irq_chip *chip = info->chip; + + if (!chip) + return; + + /* + * irq_write_msi_msg should not be set by the caller + */ + if (!chip->irq_write_msi_msg) + chip->irq_write_msi_msg = fsl_mc_msi_write_msg; +} + +/** + * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain + * @np: Optional device-tree node of the interrupt controller + * @info: MSI domain info + * @parent: Parent irq domain + * + * Updates the domain and chip ops and creates a fsl-mc MSI + * interrupt domain. + * + * Returns: + * A domain pointer or NULL in case of failure. + */ +struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, + struct msi_domain_info *info, + struct irq_domain *parent) +{ + struct irq_domain *domain; + + if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) + fsl_mc_msi_update_dom_ops(info); + if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) + fsl_mc_msi_update_chip_ops(info); + + domain = msi_create_irq_domain(fwnode, info, parent); + if (domain) + irq_domain_update_bus_token(domain, DOMAIN_BUS_FSL_MC_MSI); + + return domain; +} + +int fsl_mc_find_msi_domain(struct device *mc_platform_dev, + struct irq_domain **mc_msi_domain) +{ + struct irq_domain *msi_domain; + struct device_node *mc_of_node = mc_platform_dev->of_node; + + msi_domain = of_msi_get_domain(mc_platform_dev, mc_of_node, + DOMAIN_BUS_FSL_MC_MSI); + if (!msi_domain) { + pr_err("Unable to find fsl-mc MSI domain for %pOF\n", + mc_of_node); + + return -ENOENT; + } + + *mc_msi_domain = msi_domain; + return 0; +} + +static void fsl_mc_msi_free_descs(struct device *dev) +{ + struct msi_desc *desc, *tmp; + + list_for_each_entry_safe(desc, tmp, dev_to_msi_list(dev), list) { + list_del(&desc->list); + free_msi_entry(desc); + } +} + +static int fsl_mc_msi_alloc_descs(struct device *dev, unsigned int irq_count) + +{ + unsigned int i; + int error; + struct msi_desc *msi_desc; + + for (i = 0; i < irq_count; i++) { + msi_desc = alloc_msi_entry(dev, 1, NULL); + if (!msi_desc) { + dev_err(dev, "Failed to allocate msi entry\n"); + error = -ENOMEM; + goto cleanup_msi_descs; + } + + msi_desc->fsl_mc.msi_index = i; + INIT_LIST_HEAD(&msi_desc->list); + list_add_tail(&msi_desc->list, dev_to_msi_list(dev)); + } + + return 0; + +cleanup_msi_descs: + fsl_mc_msi_free_descs(dev); + return error; +} + +int fsl_mc_msi_domain_alloc_irqs(struct device *dev, + unsigned int irq_count) +{ + struct irq_domain *msi_domain; + int error; + + if (!list_empty(dev_to_msi_list(dev))) + return -EINVAL; + + error = fsl_mc_msi_alloc_descs(dev, irq_count); + if (error < 0) + return error; + + msi_domain = dev_get_msi_domain(dev); + if (!msi_domain) { + error = -EINVAL; + goto cleanup_msi_descs; + } + + /* + * NOTE: Calling this function will trigger the invocation of the + * its_fsl_mc_msi_prepare() callback + */ + error = msi_domain_alloc_irqs(msi_domain, dev, irq_count); + + if (error) { + dev_err(dev, "Failed to allocate IRQs\n"); + goto cleanup_msi_descs; + } + + return 0; + +cleanup_msi_descs: + fsl_mc_msi_free_descs(dev); + return error; +} + +void fsl_mc_msi_domain_free_irqs(struct device *dev) +{ + struct irq_domain *msi_domain; + + msi_domain = dev_get_msi_domain(dev); + if (!msi_domain) + return; + + msi_domain_free_irqs(msi_domain, dev); + + if (list_empty(dev_to_msi_list(dev))) + return; + + fsl_mc_msi_free_descs(dev); +} diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h new file mode 100644 index 000000000000..bed990c517f3 --- /dev/null +++ b/drivers/bus/fsl-mc/fsl-mc-private.h @@ -0,0 +1,475 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale Management Complex (MC) bus private declarations + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + */ +#ifndef _FSL_MC_PRIVATE_H_ +#define _FSL_MC_PRIVATE_H_ + +#include +#include + +/* + * Data Path Management Complex (DPMNG) General API + */ + +/* DPMNG command versioning */ +#define DPMNG_CMD_BASE_VERSION 1 +#define DPMNG_CMD_ID_OFFSET 4 + +#define DPMNG_CMD(id) (((id) << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION) + +/* DPMNG command IDs */ +#define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831) + +struct dpmng_rsp_get_version { + __le32 revision; + __le32 version_major; + __le32 version_minor; +}; + +/* + * Data Path Management Command Portal (DPMCP) API + */ + +/* Minimal supported DPMCP Version */ +#define DPMCP_MIN_VER_MAJOR 3 +#define DPMCP_MIN_VER_MINOR 0 + +/* DPMCP command versioning */ +#define DPMCP_CMD_BASE_VERSION 1 +#define DPMCP_CMD_ID_OFFSET 4 + +#define DPMCP_CMD(id) (((id) << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION) + +/* DPMCP command IDs */ +#define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800) +#define DPMCP_CMDID_OPEN DPMCP_CMD(0x80b) +#define DPMCP_CMDID_RESET DPMCP_CMD(0x005) + +struct dpmcp_cmd_open { + __le32 dpmcp_id; +}; + +/* + * Initialization and runtime control APIs for DPMCP + */ +int dpmcp_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int dpmcp_id, + u16 *token); + +int dpmcp_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +int dpmcp_reset(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +/* + * Data Path Resource Container (DPRC) API + */ + +/* Minimal supported DPRC Version */ +#define DPRC_MIN_VER_MAJOR 6 +#define DPRC_MIN_VER_MINOR 0 + +/* DPRC command versioning */ +#define DPRC_CMD_BASE_VERSION 1 +#define DPRC_CMD_ID_OFFSET 4 + +#define DPRC_CMD(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION) + +/* DPRC command IDs */ +#define DPRC_CMDID_CLOSE DPRC_CMD(0x800) +#define DPRC_CMDID_OPEN DPRC_CMD(0x805) +#define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05) + +#define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004) + +#define DPRC_CMDID_SET_IRQ DPRC_CMD(0x010) +#define DPRC_CMDID_SET_IRQ_ENABLE DPRC_CMD(0x012) +#define DPRC_CMDID_SET_IRQ_MASK DPRC_CMD(0x014) +#define DPRC_CMDID_GET_IRQ_STATUS DPRC_CMD(0x016) +#define DPRC_CMDID_CLEAR_IRQ_STATUS DPRC_CMD(0x017) + +#define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830) +#define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159) +#define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A) +#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E) +#define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F) + +struct dprc_cmd_open { + __le32 container_id; +}; + +struct dprc_cmd_set_irq { + /* cmd word 0 */ + __le32 irq_val; + u8 irq_index; + u8 pad[3]; + /* cmd word 1 */ + __le64 irq_addr; + /* cmd word 2 */ + __le32 irq_num; +}; + +#define DPRC_ENABLE 0x1 + +struct dprc_cmd_set_irq_enable { + u8 enable; + u8 pad[3]; + u8 irq_index; +}; + +struct dprc_cmd_set_irq_mask { + __le32 mask; + u8 irq_index; +}; + +struct dprc_cmd_get_irq_status { + __le32 status; + u8 irq_index; +}; + +struct dprc_rsp_get_irq_status { + __le32 status; +}; + +struct dprc_cmd_clear_irq_status { + __le32 status; + u8 irq_index; +}; + +struct dprc_rsp_get_attributes { + /* response word 0 */ + __le32 container_id; + __le16 icid; + __le16 pad; + /* response word 1 */ + __le32 options; + __le32 portal_id; +}; + +struct dprc_rsp_get_obj_count { + __le32 pad; + __le32 obj_count; +}; + +struct dprc_cmd_get_obj { + __le32 obj_index; +}; + +struct dprc_rsp_get_obj { + /* response word 0 */ + __le32 pad0; + __le32 id; + /* response word 1 */ + __le16 vendor; + u8 irq_count; + u8 region_count; + __le32 state; + /* response word 2 */ + __le16 version_major; + __le16 version_minor; + __le16 flags; + __le16 pad1; + /* response word 3-4 */ + u8 type[16]; + /* response word 5-6 */ + u8 label[16]; +}; + +struct dprc_cmd_get_obj_region { + /* cmd word 0 */ + __le32 obj_id; + __le16 pad0; + u8 region_index; + u8 pad1; + /* cmd word 1-2 */ + __le64 pad2[2]; + /* cmd word 3-4 */ + u8 obj_type[16]; +}; + +struct dprc_rsp_get_obj_region { + /* response word 0 */ + __le64 pad; + /* response word 1 */ + __le64 base_addr; + /* response word 2 */ + __le32 size; +}; + +struct dprc_cmd_set_obj_irq { + /* cmd word 0 */ + __le32 irq_val; + u8 irq_index; + u8 pad[3]; + /* cmd word 1 */ + __le64 irq_addr; + /* cmd word 2 */ + __le32 irq_num; + __le32 obj_id; + /* cmd word 3-4 */ + u8 obj_type[16]; +}; + +/* + * DPRC API for managing and querying DPAA resources + */ +int dprc_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int container_id, + u16 *token); + +int dprc_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +/* DPRC IRQ events */ + +/* IRQ event - Indicates that a new object added to the container */ +#define DPRC_IRQ_EVENT_OBJ_ADDED 0x00000001 +/* IRQ event - Indicates that an object was removed from the container */ +#define DPRC_IRQ_EVENT_OBJ_REMOVED 0x00000002 +/* + * IRQ event - Indicates that one of the descendant containers that opened by + * this container is destroyed + */ +#define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010 + +/* + * IRQ event - Indicates that on one of the container's opened object is + * destroyed + */ +#define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020 + +/* Irq event - Indicates that object is created at the container */ +#define DPRC_IRQ_EVENT_OBJ_CREATED 0x00000040 + +/** + * struct dprc_irq_cfg - IRQ configuration + * @paddr: Address that must be written to signal a message-based interrupt + * @val: Value to write into irq_addr address + * @irq_num: A user defined number associated with this IRQ + */ +struct dprc_irq_cfg { + phys_addr_t paddr; + u32 val; + int irq_num; +}; + +int dprc_set_irq(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + struct dprc_irq_cfg *irq_cfg); + +int dprc_set_irq_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u8 en); + +int dprc_set_irq_mask(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 mask); + +int dprc_get_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 *status); + +int dprc_clear_irq_status(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + u8 irq_index, + u32 status); + +/** + * struct dprc_attributes - Container attributes + * @container_id: Container's ID + * @icid: Container's ICID + * @portal_id: Container's portal ID + * @options: Container's options as set at container's creation + */ +struct dprc_attributes { + int container_id; + u16 icid; + int portal_id; + u64 options; +}; + +int dprc_get_attributes(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dprc_attributes *attributes); + +int dprc_get_obj_count(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + int *obj_count); + +int dprc_get_obj(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + int obj_index, + struct fsl_mc_obj_desc *obj_desc); + +int dprc_set_obj_irq(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + char *obj_type, + int obj_id, + u8 irq_index, + struct dprc_irq_cfg *irq_cfg); + +/* Region flags */ +/* Cacheable - Indicates that region should be mapped as cacheable */ +#define DPRC_REGION_CACHEABLE 0x00000001 + +/** + * enum dprc_region_type - Region type + * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region + * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region + */ +enum dprc_region_type { + DPRC_REGION_TYPE_MC_PORTAL, + DPRC_REGION_TYPE_QBMAN_PORTAL +}; + +/** + * struct dprc_region_desc - Mappable region descriptor + * @base_offset: Region offset from region's base address. + * For DPMCP and DPRC objects, region base is offset from SoC MC portals + * base address; For DPIO, region base is offset from SoC QMan portals + * base address + * @size: Region size (in bytes) + * @flags: Region attributes + * @type: Portal region type + */ +struct dprc_region_desc { + u32 base_offset; + u32 size; + u32 flags; + enum dprc_region_type type; +}; + +int dprc_get_obj_region(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + char *obj_type, + int obj_id, + u8 region_index, + struct dprc_region_desc *region_desc); + +int dprc_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + +int dprc_get_container_id(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int *container_id); + +/** + * Maximum number of total IRQs that can be pre-allocated for an MC bus' + * IRQ pool + */ +#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS 256 + +/** + * struct fsl_mc_resource_pool - Pool of MC resources of a given + * type + * @type: type of resources in the pool + * @max_count: maximum number of resources in the pool + * @free_count: number of free resources in the pool + * @mutex: mutex to serialize access to the pool's free list + * @free_list: anchor node of list of free resources in the pool + * @mc_bus: pointer to the MC bus that owns this resource pool + */ +struct fsl_mc_resource_pool { + enum fsl_mc_pool_type type; + int max_count; + int free_count; + struct mutex mutex; /* serializes access to free_list */ + struct list_head free_list; + struct fsl_mc_bus *mc_bus; +}; + +/** + * struct fsl_mc_bus - logical bus that corresponds to a physical DPRC + * @mc_dev: fsl-mc device for the bus device itself. + * @resource_pools: array of resource pools (one pool per resource type) + * for this MC bus. These resources represent allocatable entities + * from the physical DPRC. + * @irq_resources: Pointer to array of IRQ objects for the IRQ pool + * @scan_mutex: Serializes bus scanning + * @dprc_attr: DPRC attributes + */ +struct fsl_mc_bus { + struct fsl_mc_device mc_dev; + struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; + struct fsl_mc_device_irq *irq_resources; + struct mutex scan_mutex; /* serializes bus scanning */ + struct dprc_attributes dprc_attr; +}; + +#define to_fsl_mc_bus(_mc_dev) \ + container_of(_mc_dev, struct fsl_mc_bus, mc_dev) + +int __must_check fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, + struct fsl_mc_io *mc_io, + struct device *parent_dev, + struct fsl_mc_device **new_mc_dev); + +void fsl_mc_device_remove(struct fsl_mc_device *mc_dev); + +int __init dprc_driver_init(void); + +void dprc_driver_exit(void); + +int __init fsl_mc_allocator_driver_init(void); + +void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev); + +void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev); + +int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, + enum fsl_mc_pool_type pool_type, + struct fsl_mc_resource + **new_resource); + +void fsl_mc_resource_free(struct fsl_mc_resource *resource); + +int fsl_mc_msi_domain_alloc_irqs(struct device *dev, + unsigned int irq_count); + +void fsl_mc_msi_domain_free_irqs(struct device *dev); + +int fsl_mc_find_msi_domain(struct device *mc_platform_dev, + struct irq_domain **mc_msi_domain); + +int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, + unsigned int irq_count); + +void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus); + +int __must_check fsl_create_mc_io(struct device *dev, + phys_addr_t mc_portal_phys_addr, + u32 mc_portal_size, + struct fsl_mc_device *dpmcp_dev, + u32 flags, struct fsl_mc_io **new_mc_io); + +void fsl_destroy_mc_io(struct fsl_mc_io *mc_io); + +bool fsl_mc_is_root_dprc(struct device *dev); + +#endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/drivers/bus/fsl-mc/mc-io.c b/drivers/bus/fsl-mc/mc-io.c new file mode 100644 index 000000000000..7226cfc49b6f --- /dev/null +++ b/drivers/bus/fsl-mc/mc-io.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2013-2016 Freescale Semiconductor Inc. + * + */ + +#include +#include + +#include "fsl-mc-private.h" + +static int fsl_mc_io_set_dpmcp(struct fsl_mc_io *mc_io, + struct fsl_mc_device *dpmcp_dev) +{ + int error; + + if (mc_io->dpmcp_dev) + return -EINVAL; + + if (dpmcp_dev->mc_io) + return -EINVAL; + + error = dpmcp_open(mc_io, + 0, + dpmcp_dev->obj_desc.id, + &dpmcp_dev->mc_handle); + if (error < 0) + return error; + + mc_io->dpmcp_dev = dpmcp_dev; + dpmcp_dev->mc_io = mc_io; + return 0; +} + +static void fsl_mc_io_unset_dpmcp(struct fsl_mc_io *mc_io) +{ + int error; + struct fsl_mc_device *dpmcp_dev = mc_io->dpmcp_dev; + + error = dpmcp_close(mc_io, + 0, + dpmcp_dev->mc_handle); + if (error < 0) { + dev_err(&dpmcp_dev->dev, "dpmcp_close() failed: %d\n", + error); + } + + mc_io->dpmcp_dev = NULL; + dpmcp_dev->mc_io = NULL; +} + +/** + * Creates an MC I/O object + * + * @dev: device to be associated with the MC I/O object + * @mc_portal_phys_addr: physical address of the MC portal to use + * @mc_portal_size: size in bytes of the MC portal + * @dpmcp-dev: Pointer to the DPMCP object associated with this MC I/O + * object or NULL if none. + * @flags: flags for the new MC I/O object + * @new_mc_io: Area to return pointer to newly created MC I/O object + * + * Returns '0' on Success; Error code otherwise. + */ +int __must_check fsl_create_mc_io(struct device *dev, + phys_addr_t mc_portal_phys_addr, + u32 mc_portal_size, + struct fsl_mc_device *dpmcp_dev, + u32 flags, struct fsl_mc_io **new_mc_io) +{ + int error; + struct fsl_mc_io *mc_io; + void __iomem *mc_portal_virt_addr; + struct resource *res; + + mc_io = devm_kzalloc(dev, sizeof(*mc_io), GFP_KERNEL); + if (!mc_io) + return -ENOMEM; + + mc_io->dev = dev; + mc_io->flags = flags; + mc_io->portal_phys_addr = mc_portal_phys_addr; + mc_io->portal_size = mc_portal_size; + if (flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) + spin_lock_init(&mc_io->spinlock); + else + mutex_init(&mc_io->mutex); + + res = devm_request_mem_region(dev, + mc_portal_phys_addr, + mc_portal_size, + "mc_portal"); + if (!res) { + dev_err(dev, + "devm_request_mem_region failed for MC portal %pa\n", + &mc_portal_phys_addr); + return -EBUSY; + } + + mc_portal_virt_addr = devm_ioremap_nocache(dev, + mc_portal_phys_addr, + mc_portal_size); + if (!mc_portal_virt_addr) { + dev_err(dev, + "devm_ioremap_nocache failed for MC portal %pa\n", + &mc_portal_phys_addr); + return -ENXIO; + } + + mc_io->portal_virt_addr = mc_portal_virt_addr; + if (dpmcp_dev) { + error = fsl_mc_io_set_dpmcp(mc_io, dpmcp_dev); + if (error < 0) + goto error_destroy_mc_io; + } + + *new_mc_io = mc_io; + return 0; + +error_destroy_mc_io: + fsl_destroy_mc_io(mc_io); + return error; +} + +/** + * Destroys an MC I/O object + * + * @mc_io: MC I/O object to destroy + */ +void fsl_destroy_mc_io(struct fsl_mc_io *mc_io) +{ + struct fsl_mc_device *dpmcp_dev = mc_io->dpmcp_dev; + + if (dpmcp_dev) + fsl_mc_io_unset_dpmcp(mc_io); + + devm_iounmap(mc_io->dev, mc_io->portal_virt_addr); + devm_release_mem_region(mc_io->dev, + mc_io->portal_phys_addr, + mc_io->portal_size); + + mc_io->portal_virt_addr = NULL; + devm_kfree(mc_io->dev, mc_io); +} + +/** + * fsl_mc_portal_allocate - Allocates an MC portal + * + * @mc_dev: MC device for which the MC portal is to be allocated + * @mc_io_flags: Flags for the fsl_mc_io object that wraps the allocated + * MC portal. + * @new_mc_io: Pointer to area where the pointer to the fsl_mc_io object + * that wraps the allocated MC portal is to be returned + * + * This function allocates an MC portal from the device's parent DPRC, + * from the corresponding MC bus' pool of MC portals and wraps + * it in a new fsl_mc_io object. If 'mc_dev' is a DPRC itself, the + * portal is allocated from its own MC bus. + */ +int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev, + u16 mc_io_flags, + struct fsl_mc_io **new_mc_io) +{ + struct fsl_mc_device *mc_bus_dev; + struct fsl_mc_bus *mc_bus; + phys_addr_t mc_portal_phys_addr; + size_t mc_portal_size; + struct fsl_mc_device *dpmcp_dev; + int error = -EINVAL; + struct fsl_mc_resource *resource = NULL; + struct fsl_mc_io *mc_io = NULL; + + if (mc_dev->flags & FSL_MC_IS_DPRC) { + mc_bus_dev = mc_dev; + } else { + if (!dev_is_fsl_mc(mc_dev->dev.parent)) + return error; + + mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); + } + + mc_bus = to_fsl_mc_bus(mc_bus_dev); + *new_mc_io = NULL; + error = fsl_mc_resource_allocate(mc_bus, FSL_MC_POOL_DPMCP, &resource); + if (error < 0) + return error; + + error = -EINVAL; + dpmcp_dev = resource->data; + + if (dpmcp_dev->obj_desc.ver_major < DPMCP_MIN_VER_MAJOR || + (dpmcp_dev->obj_desc.ver_major == DPMCP_MIN_VER_MAJOR && + dpmcp_dev->obj_desc.ver_minor < DPMCP_MIN_VER_MINOR)) { + dev_err(&dpmcp_dev->dev, + "ERROR: Version %d.%d of DPMCP not supported.\n", + dpmcp_dev->obj_desc.ver_major, + dpmcp_dev->obj_desc.ver_minor); + error = -ENOTSUPP; + goto error_cleanup_resource; + } + + mc_portal_phys_addr = dpmcp_dev->regions[0].start; + mc_portal_size = resource_size(dpmcp_dev->regions); + + error = fsl_create_mc_io(&mc_bus_dev->dev, + mc_portal_phys_addr, + mc_portal_size, dpmcp_dev, + mc_io_flags, &mc_io); + if (error < 0) + goto error_cleanup_resource; + + *new_mc_io = mc_io; + return 0; + +error_cleanup_resource: + fsl_mc_resource_free(resource); + return error; +} +EXPORT_SYMBOL_GPL(fsl_mc_portal_allocate); + +/** + * fsl_mc_portal_free - Returns an MC portal to the pool of free MC portals + * of a given MC bus + * + * @mc_io: Pointer to the fsl_mc_io object that wraps the MC portal to free + */ +void fsl_mc_portal_free(struct fsl_mc_io *mc_io) +{ + struct fsl_mc_device *dpmcp_dev; + struct fsl_mc_resource *resource; + + /* + * Every mc_io obtained by calling fsl_mc_portal_allocate() is supposed + * to have a DPMCP object associated with. + */ + dpmcp_dev = mc_io->dpmcp_dev; + + resource = dpmcp_dev->resource; + if (!resource || resource->type != FSL_MC_POOL_DPMCP) + return; + + if (resource->data != dpmcp_dev) + return; + + fsl_destroy_mc_io(mc_io); + fsl_mc_resource_free(resource); +} +EXPORT_SYMBOL_GPL(fsl_mc_portal_free); + +/** + * fsl_mc_portal_reset - Resets the dpmcp object for a given fsl_mc_io object + * + * @mc_io: Pointer to the fsl_mc_io object that wraps the MC portal to free + */ +int fsl_mc_portal_reset(struct fsl_mc_io *mc_io) +{ + int error; + struct fsl_mc_device *dpmcp_dev = mc_io->dpmcp_dev; + + error = dpmcp_reset(mc_io, 0, dpmcp_dev->mc_handle); + if (error < 0) { + dev_err(&dpmcp_dev->dev, "dpmcp_reset() failed: %d\n", error); + return error; + } + + return 0; +} +EXPORT_SYMBOL_GPL(fsl_mc_portal_reset); diff --git a/drivers/bus/fsl-mc/mc-sys.c b/drivers/bus/fsl-mc/mc-sys.c new file mode 100644 index 000000000000..bd03f1524ecb --- /dev/null +++ b/drivers/bus/fsl-mc/mc-sys.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2013-2016 Freescale Semiconductor Inc. + * + * I/O services to send MC commands to the MC hardware + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "fsl-mc-private.h" + +/** + * Timeout in milliseconds to wait for the completion of an MC command + */ +#define MC_CMD_COMPLETION_TIMEOUT_MS 500 + +/* + * usleep_range() min and max values used to throttle down polling + * iterations while waiting for MC command completion + */ +#define MC_CMD_COMPLETION_POLLING_MIN_SLEEP_USECS 10 +#define MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS 500 + +static enum mc_cmd_status mc_cmd_hdr_read_status(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + + return (enum mc_cmd_status)hdr->status; +} + +static u16 mc_cmd_hdr_read_cmdid(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 cmd_id = le16_to_cpu(hdr->cmd_id); + + return cmd_id; +} + +static int mc_status_to_error(enum mc_cmd_status status) +{ + static const int mc_status_to_error_map[] = { + [MC_CMD_STATUS_OK] = 0, + [MC_CMD_STATUS_AUTH_ERR] = -EACCES, + [MC_CMD_STATUS_NO_PRIVILEGE] = -EPERM, + [MC_CMD_STATUS_DMA_ERR] = -EIO, + [MC_CMD_STATUS_CONFIG_ERR] = -ENXIO, + [MC_CMD_STATUS_TIMEOUT] = -ETIMEDOUT, + [MC_CMD_STATUS_NO_RESOURCE] = -ENAVAIL, + [MC_CMD_STATUS_NO_MEMORY] = -ENOMEM, + [MC_CMD_STATUS_BUSY] = -EBUSY, + [MC_CMD_STATUS_UNSUPPORTED_OP] = -ENOTSUPP, + [MC_CMD_STATUS_INVALID_STATE] = -ENODEV, + }; + + if ((u32)status >= ARRAY_SIZE(mc_status_to_error_map)) + return -EINVAL; + + return mc_status_to_error_map[status]; +} + +static const char *mc_status_to_string(enum mc_cmd_status status) +{ + static const char *const status_strings[] = { + [MC_CMD_STATUS_OK] = "Command completed successfully", + [MC_CMD_STATUS_READY] = "Command ready to be processed", + [MC_CMD_STATUS_AUTH_ERR] = "Authentication error", + [MC_CMD_STATUS_NO_PRIVILEGE] = "No privilege", + [MC_CMD_STATUS_DMA_ERR] = "DMA or I/O error", + [MC_CMD_STATUS_CONFIG_ERR] = "Configuration error", + [MC_CMD_STATUS_TIMEOUT] = "Operation timed out", + [MC_CMD_STATUS_NO_RESOURCE] = "No resources", + [MC_CMD_STATUS_NO_MEMORY] = "No memory available", + [MC_CMD_STATUS_BUSY] = "Device is busy", + [MC_CMD_STATUS_UNSUPPORTED_OP] = "Unsupported operation", + [MC_CMD_STATUS_INVALID_STATE] = "Invalid state" + }; + + if ((unsigned int)status >= ARRAY_SIZE(status_strings)) + return "Unknown MC error"; + + return status_strings[status]; +} + +/** + * mc_write_command - writes a command to a Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @cmd: pointer to a filled command + */ +static inline void mc_write_command(struct mc_command __iomem *portal, + struct mc_command *cmd) +{ + int i; + + /* copy command parameters into the portal */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + /* + * Data is already in the expected LE byte-order. Do an + * extra LE -> CPU conversion so that the CPU -> LE done in + * the device io write api puts it back in the right order. + */ + writeq_relaxed(le64_to_cpu(cmd->params[i]), &portal->params[i]); + + /* submit the command by writing the header */ + writeq(le64_to_cpu(cmd->header), &portal->header); +} + +/** + * mc_read_response - reads the response for the last MC command from a + * Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @resp: pointer to command response buffer + * + * Returns MC_CMD_STATUS_OK on Success; Error code otherwise. + */ +static inline enum mc_cmd_status mc_read_response(struct mc_command __iomem * + portal, + struct mc_command *resp) +{ + int i; + enum mc_cmd_status status; + + /* Copy command response header from MC portal: */ + resp->header = cpu_to_le64(readq_relaxed(&portal->header)); + status = mc_cmd_hdr_read_status(resp); + if (status != MC_CMD_STATUS_OK) + return status; + + /* Copy command response data from MC portal: */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + /* + * Data is expected to be in LE byte-order. Do an + * extra CPU -> LE to revert the LE -> CPU done in + * the device io read api. + */ + resp->params[i] = + cpu_to_le64(readq_relaxed(&portal->params[i])); + + return status; +} + +/** + * Waits for the completion of an MC command doing preemptible polling. + * uslepp_range() is called between polling iterations. + * + * @mc_io: MC I/O object to be used + * @cmd: command buffer to receive MC response + * @mc_status: MC command completion status + */ +static int mc_polling_wait_preemptible(struct fsl_mc_io *mc_io, + struct mc_command *cmd, + enum mc_cmd_status *mc_status) +{ + enum mc_cmd_status status; + unsigned long jiffies_until_timeout = + jiffies + msecs_to_jiffies(MC_CMD_COMPLETION_TIMEOUT_MS); + + /* + * Wait for response from the MC hardware: + */ + for (;;) { + status = mc_read_response(mc_io->portal_virt_addr, cmd); + if (status != MC_CMD_STATUS_READY) + break; + + /* + * TODO: When MC command completion interrupts are supported + * call wait function here instead of usleep_range() + */ + usleep_range(MC_CMD_COMPLETION_POLLING_MIN_SLEEP_USECS, + MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); + + if (time_after_eq(jiffies, jiffies_until_timeout)) { + dev_dbg(mc_io->dev, + "MC command timed out (portal: %pa, dprc handle: %#x, command: %#x)\n", + &mc_io->portal_phys_addr, + (unsigned int)mc_cmd_hdr_read_token(cmd), + (unsigned int)mc_cmd_hdr_read_cmdid(cmd)); + + return -ETIMEDOUT; + } + } + + *mc_status = status; + return 0; +} + +/** + * Waits for the completion of an MC command doing atomic polling. + * udelay() is called between polling iterations. + * + * @mc_io: MC I/O object to be used + * @cmd: command buffer to receive MC response + * @mc_status: MC command completion status + */ +static int mc_polling_wait_atomic(struct fsl_mc_io *mc_io, + struct mc_command *cmd, + enum mc_cmd_status *mc_status) +{ + enum mc_cmd_status status; + unsigned long timeout_usecs = MC_CMD_COMPLETION_TIMEOUT_MS * 1000; + + BUILD_BUG_ON((MC_CMD_COMPLETION_TIMEOUT_MS * 1000) % + MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS != 0); + + for (;;) { + status = mc_read_response(mc_io->portal_virt_addr, cmd); + if (status != MC_CMD_STATUS_READY) + break; + + udelay(MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); + timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS; + if (timeout_usecs == 0) { + dev_dbg(mc_io->dev, + "MC command timed out (portal: %pa, dprc handle: %#x, command: %#x)\n", + &mc_io->portal_phys_addr, + (unsigned int)mc_cmd_hdr_read_token(cmd), + (unsigned int)mc_cmd_hdr_read_cmdid(cmd)); + + return -ETIMEDOUT; + } + } + + *mc_status = status; + return 0; +} + +/** + * Sends a command to the MC device using the given MC I/O object + * + * @mc_io: MC I/O object to be used + * @cmd: command to be sent + * + * Returns '0' on Success; Error code otherwise. + */ +int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd) +{ + int error; + enum mc_cmd_status status; + unsigned long irq_flags = 0; + + if (in_irq() && !(mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL)) + return -EINVAL; + + if (mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) + spin_lock_irqsave(&mc_io->spinlock, irq_flags); + else + mutex_lock(&mc_io->mutex); + + /* + * Send command to the MC hardware: + */ + mc_write_command(mc_io->portal_virt_addr, cmd); + + /* + * Wait for response from the MC hardware: + */ + if (!(mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL)) + error = mc_polling_wait_preemptible(mc_io, cmd, &status); + else + error = mc_polling_wait_atomic(mc_io, cmd, &status); + + if (error < 0) + goto common_exit; + + if (status != MC_CMD_STATUS_OK) { + dev_dbg(mc_io->dev, + "MC command failed: portal: %pa, dprc handle: %#x, command: %#x, status: %s (%#x)\n", + &mc_io->portal_phys_addr, + (unsigned int)mc_cmd_hdr_read_token(cmd), + (unsigned int)mc_cmd_hdr_read_cmdid(cmd), + mc_status_to_string(status), + (unsigned int)status); + + error = mc_status_to_error(status); + goto common_exit; + } + + error = 0; +common_exit: + if (mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) + spin_unlock_irqrestore(&mc_io->spinlock, irq_flags); + else + mutex_unlock(&mc_io->mutex); + + return error; +} +EXPORT_SYMBOL_GPL(mc_send_command); diff --git a/drivers/staging/fsl-dpaa2/ethernet/README b/drivers/staging/fsl-dpaa2/ethernet/README index 410952ecf657..e3b5c90197e4 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/README +++ b/drivers/staging/fsl-dpaa2/ethernet/README @@ -36,7 +36,7 @@ are treated as internal resources of other objects. For a more detailed description of the DPAA2 architecture and its object abstractions see: - drivers/staging/fsl-mc/README.txt + Documentation/networking/dpaa2/overview.rst Each Linux net device is built on top of a Datapath Network Interface (DPNI) object and uses Buffer Pools (DPBPs), I/O Portals (DPIOs) and Concentrators diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c index 1ea5747b5f22..dc7be5388430 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c @@ -39,7 +39,7 @@ #include #include -#include "../../fsl-mc/include/mc.h" +#include #include "dpaa2-eth.h" /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpni.c b/drivers/staging/fsl-dpaa2/ethernet/dpni.c index e8be76181c36..b16ff5c2f8c1 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpni.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c @@ -32,7 +32,7 @@ */ #include #include -#include "../../fsl-mc/include/mc.h" +#include #include "dpni.h" #include "dpni-cmd.h" diff --git a/drivers/staging/fsl-mc/TODO b/drivers/staging/fsl-mc/TODO deleted file mode 100644 index 54a8bc69222e..000000000000 --- a/drivers/staging/fsl-mc/TODO +++ /dev/null @@ -1,18 +0,0 @@ -* Add at least one device driver for a DPAA2 object (child device of the - fsl-mc bus). Most likely candidate for this is adding DPAA2 Ethernet - driver support, which depends on drivers for several objects: DPNI, - DPIO, DPMAC. Other pre-requisites include: - - * MC firmware uprev. The MC firmware upon which the fsl-mc - bus driver and DPAA2 object drivers are based is continuing - to evolve, so minor updates are needed to keep in sync with binary - interface changes to the MC. - -* Cleanup - -Please send any patches to Greg Kroah-Hartman , -german.rivera@freescale.com, devel@driverdev.osuosl.org, -linux-kernel@vger.kernel.org - -[1] https://lkml.org/lkml/2015/7/9/93 -[2] https://lkml.org/lkml/2015/7/7/712 diff --git a/drivers/staging/fsl-mc/bus/Kconfig b/drivers/staging/fsl-mc/bus/Kconfig index 1f9100049176..5f4115d76c06 100644 --- a/drivers/staging/fsl-mc/bus/Kconfig +++ b/drivers/staging/fsl-mc/bus/Kconfig @@ -5,16 +5,6 @@ # Copyright (C) 2014-2016 Freescale Semiconductor, Inc. # -config FSL_MC_BUS - bool "QorIQ DPAA2 fsl-mc bus driver" - depends on OF && (ARCH_LAYERSCAPE || (COMPILE_TEST && (ARM || ARM64 || X86 || PPC))) - select GENERIC_MSI_IRQ_DOMAIN - help - Driver to enable the bus infrastructure for the QorIQ DPAA2 - architecture. The fsl-mc bus driver handles discovery of - DPAA2 objects (which are represented as Linux devices) and - binding objects to drivers. - config FSL_MC_DPIO tristate "QorIQ DPAA2 DPIO driver" depends on FSL_MC_BUS && ARCH_LAYERSCAPE diff --git a/drivers/staging/fsl-mc/bus/Makefile b/drivers/staging/fsl-mc/bus/Makefile index 29059db95ecc..18b1b5fdaf76 100644 --- a/drivers/staging/fsl-mc/bus/Makefile +++ b/drivers/staging/fsl-mc/bus/Makefile @@ -4,19 +4,9 @@ # # Copyright (C) 2014 Freescale Semiconductor, Inc. # -obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o - -mc-bus-driver-objs := fsl-mc-bus.o \ - mc-sys.o \ - mc-io.o \ - dprc.o \ - dprc-driver.o \ - fsl-mc-allocator.o \ - fsl-mc-msi.o \ - irq-gic-v3-its-fsl-mc-msi.o \ - dpmcp.o \ - dpbp.o \ - dpcon.o +obj-$(CONFIG_FSL_MC_BUS) += irq-gic-v3-its-fsl-mc-msi.o \ + dpbp.o \ + dpcon.o # MC DPIO driver obj-$(CONFIG_FSL_MC_DPIO) += dpio/ diff --git a/drivers/staging/fsl-mc/bus/dpbp.c b/drivers/staging/fsl-mc/bus/dpbp.c index a4df84668d5b..c0addaa37f61 100644 --- a/drivers/staging/fsl-mc/bus/dpbp.c +++ b/drivers/staging/fsl-mc/bus/dpbp.c @@ -4,7 +4,7 @@ * */ #include -#include "../include/mc.h" +#include #include "../include/dpbp.h" #include "dpbp-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/dpcon.c b/drivers/staging/fsl-mc/bus/dpcon.c index 8f84d7b5465c..021b4252eba0 100644 --- a/drivers/staging/fsl-mc/bus/dpcon.c +++ b/drivers/staging/fsl-mc/bus/dpcon.c @@ -4,7 +4,7 @@ * */ #include -#include "../include/mc.h" +#include #include "../include/dpcon.h" #include "dpcon-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c index b8479ef64c71..182b38412a82 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c @@ -14,7 +14,7 @@ #include #include -#include "../../include/mc.h" +#include #include "../../include/dpaa2-io.h" #include "qbman-portal.h" diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c index d3c8462d43e8..1acff7ee7bb9 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c @@ -5,7 +5,7 @@ * */ #include -#include "../../include/mc.h" +#include #include "../../include/dpaa2-io.h" #include #include diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio.c b/drivers/staging/fsl-mc/bus/dpio/dpio.c index 20cdeae54a74..3175057e0265 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio.c +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c @@ -5,7 +5,7 @@ * */ #include -#include "../../include/mc.h" +#include #include "dpio.h" #include "dpio-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/dpmcp.c b/drivers/staging/fsl-mc/bus/dpmcp.c deleted file mode 100644 index be07c77520af..000000000000 --- a/drivers/staging/fsl-mc/bus/dpmcp.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#include -#include "../include/mc.h" - -#include "fsl-mc-private.h" - -/** - * dpmcp_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpmcp_id: DPMCP unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpmcp_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmcp_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int dpmcp_id, - u16 *token) -{ - struct mc_command cmd = { 0 }; - struct dpmcp_cmd_open *cmd_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_OPEN, - cmd_flags, 0); - cmd_params = (struct dpmcp_cmd_open *)cmd.params; - cmd_params->dpmcp_id = cpu_to_le32(dpmcp_id); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - *token = mc_cmd_hdr_read_token(&cmd); - - return err; -} - -/** - * dpmcp_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMCP object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmcp_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CLOSE, - cmd_flags, token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -/** - * dpmcp_reset() - Reset the DPMCP, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMCP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmcp_reset(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_RESET, - cmd_flags, token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} diff --git a/drivers/staging/fsl-mc/bus/dprc-driver.c b/drivers/staging/fsl-mc/bus/dprc-driver.c deleted file mode 100644 index b09075731e62..000000000000 --- a/drivers/staging/fsl-mc/bus/dprc-driver.c +++ /dev/null @@ -1,809 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Freescale data path resource container (DPRC) driver - * - * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * Author: German Rivera - * - */ - -#include -#include -#include -#include -#include "../include/mc.h" - -#include "fsl-mc-private.h" - -#define FSL_MC_DPRC_DRIVER_NAME "fsl_mc_dprc" - -struct fsl_mc_child_objs { - int child_count; - struct fsl_mc_obj_desc *child_array; -}; - -static bool fsl_mc_device_match(struct fsl_mc_device *mc_dev, - struct fsl_mc_obj_desc *obj_desc) -{ - return mc_dev->obj_desc.id == obj_desc->id && - strcmp(mc_dev->obj_desc.type, obj_desc->type) == 0; - -} - -static int __fsl_mc_device_remove_if_not_in_mc(struct device *dev, void *data) -{ - int i; - struct fsl_mc_child_objs *objs; - struct fsl_mc_device *mc_dev; - - mc_dev = to_fsl_mc_device(dev); - objs = data; - - for (i = 0; i < objs->child_count; i++) { - struct fsl_mc_obj_desc *obj_desc = &objs->child_array[i]; - - if (strlen(obj_desc->type) != 0 && - fsl_mc_device_match(mc_dev, obj_desc)) - break; - } - - if (i == objs->child_count) - fsl_mc_device_remove(mc_dev); - - return 0; -} - -static int __fsl_mc_device_remove(struct device *dev, void *data) -{ - fsl_mc_device_remove(to_fsl_mc_device(dev)); - return 0; -} - -/** - * dprc_remove_devices - Removes devices for objects removed from a DPRC - * - * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object - * @obj_desc_array: array of object descriptors for child objects currently - * present in the DPRC in the MC. - * @num_child_objects_in_mc: number of entries in obj_desc_array - * - * Synchronizes the state of the Linux bus driver with the actual state of - * the MC by removing devices that represent MC objects that have - * been dynamically removed in the physical DPRC. - */ -static void dprc_remove_devices(struct fsl_mc_device *mc_bus_dev, - struct fsl_mc_obj_desc *obj_desc_array, - int num_child_objects_in_mc) -{ - if (num_child_objects_in_mc != 0) { - /* - * Remove child objects that are in the DPRC in Linux, - * but not in the MC: - */ - struct fsl_mc_child_objs objs; - - objs.child_count = num_child_objects_in_mc; - objs.child_array = obj_desc_array; - device_for_each_child(&mc_bus_dev->dev, &objs, - __fsl_mc_device_remove_if_not_in_mc); - } else { - /* - * There are no child objects for this DPRC in the MC. - * So, remove all the child devices from Linux: - */ - device_for_each_child(&mc_bus_dev->dev, NULL, - __fsl_mc_device_remove); - } -} - -static int __fsl_mc_device_match(struct device *dev, void *data) -{ - struct fsl_mc_obj_desc *obj_desc = data; - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - - return fsl_mc_device_match(mc_dev, obj_desc); -} - -static struct fsl_mc_device *fsl_mc_device_lookup(struct fsl_mc_obj_desc - *obj_desc, - struct fsl_mc_device - *mc_bus_dev) -{ - struct device *dev; - - dev = device_find_child(&mc_bus_dev->dev, obj_desc, - __fsl_mc_device_match); - - return dev ? to_fsl_mc_device(dev) : NULL; -} - -/** - * check_plugged_state_change - Check change in an MC object's plugged state - * - * @mc_dev: pointer to the fsl-mc device for a given MC object - * @obj_desc: pointer to the MC object's descriptor in the MC - * - * If the plugged state has changed from unplugged to plugged, the fsl-mc - * device is bound to the corresponding device driver. - * If the plugged state has changed from plugged to unplugged, the fsl-mc - * device is unbound from the corresponding device driver. - */ -static void check_plugged_state_change(struct fsl_mc_device *mc_dev, - struct fsl_mc_obj_desc *obj_desc) -{ - int error; - u32 plugged_flag_at_mc = - obj_desc->state & FSL_MC_OBJ_STATE_PLUGGED; - - if (plugged_flag_at_mc != - (mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED)) { - if (plugged_flag_at_mc) { - mc_dev->obj_desc.state |= FSL_MC_OBJ_STATE_PLUGGED; - error = device_attach(&mc_dev->dev); - if (error < 0) { - dev_err(&mc_dev->dev, - "device_attach() failed: %d\n", - error); - } - } else { - mc_dev->obj_desc.state &= ~FSL_MC_OBJ_STATE_PLUGGED; - device_release_driver(&mc_dev->dev); - } - } -} - -/** - * dprc_add_new_devices - Adds devices to the logical bus for a DPRC - * - * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object - * @obj_desc_array: array of device descriptors for child devices currently - * present in the physical DPRC. - * @num_child_objects_in_mc: number of entries in obj_desc_array - * - * Synchronizes the state of the Linux bus driver with the actual - * state of the MC by adding objects that have been newly discovered - * in the physical DPRC. - */ -static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, - struct fsl_mc_obj_desc *obj_desc_array, - int num_child_objects_in_mc) -{ - int error; - int i; - - for (i = 0; i < num_child_objects_in_mc; i++) { - struct fsl_mc_device *child_dev; - struct fsl_mc_obj_desc *obj_desc = &obj_desc_array[i]; - - if (strlen(obj_desc->type) == 0) - continue; - - /* - * Check if device is already known to Linux: - */ - child_dev = fsl_mc_device_lookup(obj_desc, mc_bus_dev); - if (child_dev) { - check_plugged_state_change(child_dev, obj_desc); - put_device(&child_dev->dev); - continue; - } - - error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev, - &child_dev); - if (error < 0) - continue; - } -} - -/** - * dprc_scan_objects - Discover objects in a DPRC - * - * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object - * @total_irq_count: If argument is provided the function populates the - * total number of IRQs created by objects in the DPRC. - * - * Detects objects added and removed from a DPRC and synchronizes the - * state of the Linux bus driver, MC by adding and removing - * devices accordingly. - * Two types of devices can be found in a DPRC: allocatable objects (e.g., - * dpbp, dpmcp) and non-allocatable devices (e.g., dprc, dpni). - * All allocatable devices needed to be probed before all non-allocatable - * devices, to ensure that device drivers for non-allocatable - * devices can allocate any type of allocatable devices. - * That is, we need to ensure that the corresponding resource pools are - * populated before they can get allocation requests from probe callbacks - * of the device drivers for the non-allocatable devices. - */ -static int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, - unsigned int *total_irq_count) -{ - int num_child_objects; - int dprc_get_obj_failures; - int error; - unsigned int irq_count = mc_bus_dev->obj_desc.irq_count; - struct fsl_mc_obj_desc *child_obj_desc_array = NULL; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - - error = dprc_get_obj_count(mc_bus_dev->mc_io, - 0, - mc_bus_dev->mc_handle, - &num_child_objects); - if (error < 0) { - dev_err(&mc_bus_dev->dev, "dprc_get_obj_count() failed: %d\n", - error); - return error; - } - - if (num_child_objects != 0) { - int i; - - child_obj_desc_array = - devm_kmalloc_array(&mc_bus_dev->dev, num_child_objects, - sizeof(*child_obj_desc_array), - GFP_KERNEL); - if (!child_obj_desc_array) - return -ENOMEM; - - /* - * Discover objects currently present in the physical DPRC: - */ - dprc_get_obj_failures = 0; - for (i = 0; i < num_child_objects; i++) { - struct fsl_mc_obj_desc *obj_desc = - &child_obj_desc_array[i]; - - error = dprc_get_obj(mc_bus_dev->mc_io, - 0, - mc_bus_dev->mc_handle, - i, obj_desc); - if (error < 0) { - dev_err(&mc_bus_dev->dev, - "dprc_get_obj(i=%d) failed: %d\n", - i, error); - /* - * Mark the obj entry as "invalid", by using the - * empty string as obj type: - */ - obj_desc->type[0] = '\0'; - obj_desc->id = error; - dprc_get_obj_failures++; - continue; - } - - /* - * add a quirk for all versions of dpsec < 4.0...none - * are coherent regardless of what the MC reports. - */ - if ((strcmp(obj_desc->type, "dpseci") == 0) && - (obj_desc->ver_major < 4)) - obj_desc->flags |= - FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY; - - irq_count += obj_desc->irq_count; - dev_dbg(&mc_bus_dev->dev, - "Discovered object: type %s, id %d\n", - obj_desc->type, obj_desc->id); - } - - if (dprc_get_obj_failures != 0) { - dev_err(&mc_bus_dev->dev, - "%d out of %d devices could not be retrieved\n", - dprc_get_obj_failures, num_child_objects); - } - } - - /* - * Allocate IRQ's before binding the scanned devices with their - * respective drivers. - */ - if (dev_get_msi_domain(&mc_bus_dev->dev) && !mc_bus->irq_resources) { - if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { - dev_warn(&mc_bus_dev->dev, - "IRQs needed (%u) exceed IRQs preallocated (%u)\n", - irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); - } - - error = fsl_mc_populate_irq_pool(mc_bus, - FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); - if (error < 0) - return error; - } - - if (total_irq_count) - *total_irq_count = irq_count; - - dprc_remove_devices(mc_bus_dev, child_obj_desc_array, - num_child_objects); - - dprc_add_new_devices(mc_bus_dev, child_obj_desc_array, - num_child_objects); - - if (child_obj_desc_array) - devm_kfree(&mc_bus_dev->dev, child_obj_desc_array); - - return 0; -} - -/** - * dprc_scan_container - Scans a physical DPRC and synchronizes Linux bus state - * - * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object - * - * Scans the physical DPRC and synchronizes the state of the Linux - * bus driver with the actual state of the MC by adding and removing - * devices as appropriate. - */ -static int dprc_scan_container(struct fsl_mc_device *mc_bus_dev) -{ - int error; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - - fsl_mc_init_all_resource_pools(mc_bus_dev); - - /* - * Discover objects in the DPRC: - */ - mutex_lock(&mc_bus->scan_mutex); - error = dprc_scan_objects(mc_bus_dev, NULL); - mutex_unlock(&mc_bus->scan_mutex); - if (error < 0) { - fsl_mc_cleanup_all_resource_pools(mc_bus_dev); - return error; - } - - return 0; -} - -/** - * dprc_irq0_handler - Regular ISR for DPRC interrupt 0 - * - * @irq: IRQ number of the interrupt being handled - * @arg: Pointer to device structure - */ -static irqreturn_t dprc_irq0_handler(int irq_num, void *arg) -{ - return IRQ_WAKE_THREAD; -} - -/** - * dprc_irq0_handler_thread - Handler thread function for DPRC interrupt 0 - * - * @irq: IRQ number of the interrupt being handled - * @arg: Pointer to device structure - */ -static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg) -{ - int error; - u32 status; - struct device *dev = arg; - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - struct fsl_mc_io *mc_io = mc_dev->mc_io; - struct msi_desc *msi_desc = mc_dev->irqs[0]->msi_desc; - - dev_dbg(dev, "DPRC IRQ %d triggered on CPU %u\n", - irq_num, smp_processor_id()); - - if (!(mc_dev->flags & FSL_MC_IS_DPRC)) - return IRQ_HANDLED; - - mutex_lock(&mc_bus->scan_mutex); - if (!msi_desc || msi_desc->irq != (u32)irq_num) - goto out; - - status = 0; - error = dprc_get_irq_status(mc_io, 0, mc_dev->mc_handle, 0, - &status); - if (error < 0) { - dev_err(dev, - "dprc_get_irq_status() failed: %d\n", error); - goto out; - } - - error = dprc_clear_irq_status(mc_io, 0, mc_dev->mc_handle, 0, - status); - if (error < 0) { - dev_err(dev, - "dprc_clear_irq_status() failed: %d\n", error); - goto out; - } - - if (status & (DPRC_IRQ_EVENT_OBJ_ADDED | - DPRC_IRQ_EVENT_OBJ_REMOVED | - DPRC_IRQ_EVENT_CONTAINER_DESTROYED | - DPRC_IRQ_EVENT_OBJ_DESTROYED | - DPRC_IRQ_EVENT_OBJ_CREATED)) { - unsigned int irq_count; - - error = dprc_scan_objects(mc_dev, &irq_count); - if (error < 0) { - /* - * If the error is -ENXIO, we ignore it, as it indicates - * that the object scan was aborted, as we detected that - * an object was removed from the DPRC in the MC, while - * we were scanning the DPRC. - */ - if (error != -ENXIO) { - dev_err(dev, "dprc_scan_objects() failed: %d\n", - error); - } - - goto out; - } - - if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { - dev_warn(dev, - "IRQs needed (%u) exceed IRQs preallocated (%u)\n", - irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); - } - } - -out: - mutex_unlock(&mc_bus->scan_mutex); - return IRQ_HANDLED; -} - -/* - * Disable and clear interrupt for a given DPRC object - */ -static int disable_dprc_irq(struct fsl_mc_device *mc_dev) -{ - int error; - struct fsl_mc_io *mc_io = mc_dev->mc_io; - - /* - * Disable generation of interrupt, while we configure it: - */ - error = dprc_set_irq_enable(mc_io, 0, mc_dev->mc_handle, 0, 0); - if (error < 0) { - dev_err(&mc_dev->dev, - "Disabling DPRC IRQ failed: dprc_set_irq_enable() failed: %d\n", - error); - return error; - } - - /* - * Disable all interrupt causes for the interrupt: - */ - error = dprc_set_irq_mask(mc_io, 0, mc_dev->mc_handle, 0, 0x0); - if (error < 0) { - dev_err(&mc_dev->dev, - "Disabling DPRC IRQ failed: dprc_set_irq_mask() failed: %d\n", - error); - return error; - } - - /* - * Clear any leftover interrupts: - */ - error = dprc_clear_irq_status(mc_io, 0, mc_dev->mc_handle, 0, ~0x0U); - if (error < 0) { - dev_err(&mc_dev->dev, - "Disabling DPRC IRQ failed: dprc_clear_irq_status() failed: %d\n", - error); - return error; - } - - return 0; -} - -static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev) -{ - int error; - struct fsl_mc_device_irq *irq = mc_dev->irqs[0]; - - /* - * NOTE: devm_request_threaded_irq() invokes the device-specific - * function that programs the MSI physically in the device - */ - error = devm_request_threaded_irq(&mc_dev->dev, - irq->msi_desc->irq, - dprc_irq0_handler, - dprc_irq0_handler_thread, - IRQF_NO_SUSPEND | IRQF_ONESHOT, - dev_name(&mc_dev->dev), - &mc_dev->dev); - if (error < 0) { - dev_err(&mc_dev->dev, - "devm_request_threaded_irq() failed: %d\n", - error); - return error; - } - - return 0; -} - -static int enable_dprc_irq(struct fsl_mc_device *mc_dev) -{ - int error; - - /* - * Enable all interrupt causes for the interrupt: - */ - error = dprc_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, 0, - ~0x0u); - if (error < 0) { - dev_err(&mc_dev->dev, - "Enabling DPRC IRQ failed: dprc_set_irq_mask() failed: %d\n", - error); - - return error; - } - - /* - * Enable generation of the interrupt: - */ - error = dprc_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, 0, 1); - if (error < 0) { - dev_err(&mc_dev->dev, - "Enabling DPRC IRQ failed: dprc_set_irq_enable() failed: %d\n", - error); - - return error; - } - - return 0; -} - -/* - * Setup interrupt for a given DPRC device - */ -static int dprc_setup_irq(struct fsl_mc_device *mc_dev) -{ - int error; - - error = fsl_mc_allocate_irqs(mc_dev); - if (error < 0) - return error; - - error = disable_dprc_irq(mc_dev); - if (error < 0) - goto error_free_irqs; - - error = register_dprc_irq_handler(mc_dev); - if (error < 0) - goto error_free_irqs; - - error = enable_dprc_irq(mc_dev); - if (error < 0) - goto error_free_irqs; - - return 0; - -error_free_irqs: - fsl_mc_free_irqs(mc_dev); - return error; -} - -/** - * dprc_probe - callback invoked when a DPRC is being bound to this driver - * - * @mc_dev: Pointer to fsl-mc device representing a DPRC - * - * It opens the physical DPRC in the MC. - * It scans the DPRC to discover the MC objects contained in it. - * It creates the interrupt pool for the MC bus associated with the DPRC. - * It configures the interrupts for the DPRC device itself. - */ -static int dprc_probe(struct fsl_mc_device *mc_dev) -{ - int error; - size_t region_size; - struct device *parent_dev = mc_dev->dev.parent; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - bool mc_io_created = false; - bool msi_domain_set = false; - u16 major_ver, minor_ver; - - if (!is_fsl_mc_bus_dprc(mc_dev)) - return -EINVAL; - - if (dev_get_msi_domain(&mc_dev->dev)) - return -EINVAL; - - if (!mc_dev->mc_io) { - /* - * This is a child DPRC: - */ - if (!dev_is_fsl_mc(parent_dev)) - return -EINVAL; - - if (mc_dev->obj_desc.region_count == 0) - return -EINVAL; - - region_size = resource_size(mc_dev->regions); - - error = fsl_create_mc_io(&mc_dev->dev, - mc_dev->regions[0].start, - region_size, - NULL, - FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, - &mc_dev->mc_io); - if (error < 0) - return error; - - mc_io_created = true; - - /* - * Inherit parent MSI domain: - */ - dev_set_msi_domain(&mc_dev->dev, - dev_get_msi_domain(parent_dev)); - msi_domain_set = true; - } else { - /* - * This is a root DPRC - */ - struct irq_domain *mc_msi_domain; - - if (dev_is_fsl_mc(parent_dev)) - return -EINVAL; - - error = fsl_mc_find_msi_domain(parent_dev, - &mc_msi_domain); - if (error < 0) { - dev_warn(&mc_dev->dev, - "WARNING: MC bus without interrupt support\n"); - } else { - dev_set_msi_domain(&mc_dev->dev, mc_msi_domain); - msi_domain_set = true; - } - } - - error = dprc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id, - &mc_dev->mc_handle); - if (error < 0) { - dev_err(&mc_dev->dev, "dprc_open() failed: %d\n", error); - goto error_cleanup_msi_domain; - } - - error = dprc_get_attributes(mc_dev->mc_io, 0, mc_dev->mc_handle, - &mc_bus->dprc_attr); - if (error < 0) { - dev_err(&mc_dev->dev, "dprc_get_attributes() failed: %d\n", - error); - goto error_cleanup_open; - } - - error = dprc_get_api_version(mc_dev->mc_io, 0, - &major_ver, - &minor_ver); - if (error < 0) { - dev_err(&mc_dev->dev, "dprc_get_api_version() failed: %d\n", - error); - goto error_cleanup_open; - } - - if (major_ver < DPRC_MIN_VER_MAJOR || - (major_ver == DPRC_MIN_VER_MAJOR && - minor_ver < DPRC_MIN_VER_MINOR)) { - dev_err(&mc_dev->dev, - "ERROR: DPRC version %d.%d not supported\n", - major_ver, minor_ver); - error = -ENOTSUPP; - goto error_cleanup_open; - } - - mutex_init(&mc_bus->scan_mutex); - - /* - * Discover MC objects in DPRC object: - */ - error = dprc_scan_container(mc_dev); - if (error < 0) - goto error_cleanup_open; - - /* - * Configure interrupt for the DPRC object associated with this MC bus: - */ - error = dprc_setup_irq(mc_dev); - if (error < 0) - goto error_cleanup_open; - - dev_info(&mc_dev->dev, "DPRC device bound to driver"); - return 0; - -error_cleanup_open: - (void)dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); - -error_cleanup_msi_domain: - if (msi_domain_set) - dev_set_msi_domain(&mc_dev->dev, NULL); - - if (mc_io_created) { - fsl_destroy_mc_io(mc_dev->mc_io); - mc_dev->mc_io = NULL; - } - - return error; -} - -/* - * Tear down interrupt for a given DPRC object - */ -static void dprc_teardown_irq(struct fsl_mc_device *mc_dev) -{ - struct fsl_mc_device_irq *irq = mc_dev->irqs[0]; - - (void)disable_dprc_irq(mc_dev); - - devm_free_irq(&mc_dev->dev, irq->msi_desc->irq, &mc_dev->dev); - - fsl_mc_free_irqs(mc_dev); -} - -/** - * dprc_remove - callback invoked when a DPRC is being unbound from this driver - * - * @mc_dev: Pointer to fsl-mc device representing the DPRC - * - * It removes the DPRC's child objects from Linux (not from the MC) and - * closes the DPRC device in the MC. - * It tears down the interrupts that were configured for the DPRC device. - * It destroys the interrupt pool associated with this MC bus. - */ -static int dprc_remove(struct fsl_mc_device *mc_dev) -{ - int error; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - - if (!is_fsl_mc_bus_dprc(mc_dev)) - return -EINVAL; - if (!mc_dev->mc_io) - return -EINVAL; - - if (!mc_bus->irq_resources) - return -EINVAL; - - if (dev_get_msi_domain(&mc_dev->dev)) - dprc_teardown_irq(mc_dev); - - device_for_each_child(&mc_dev->dev, NULL, __fsl_mc_device_remove); - - if (dev_get_msi_domain(&mc_dev->dev)) { - fsl_mc_cleanup_irq_pool(mc_bus); - dev_set_msi_domain(&mc_dev->dev, NULL); - } - - fsl_mc_cleanup_all_resource_pools(mc_dev); - - error = dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); - if (error < 0) - dev_err(&mc_dev->dev, "dprc_close() failed: %d\n", error); - - if (!fsl_mc_is_root_dprc(&mc_dev->dev)) { - fsl_destroy_mc_io(mc_dev->mc_io); - mc_dev->mc_io = NULL; - } - - dev_info(&mc_dev->dev, "DPRC device unbound from driver"); - return 0; -} - -static const struct fsl_mc_device_id match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dprc"}, - {.vendor = 0x0}, -}; - -static struct fsl_mc_driver dprc_driver = { - .driver = { - .name = FSL_MC_DPRC_DRIVER_NAME, - .owner = THIS_MODULE, - .pm = NULL, - }, - .match_id_table = match_id_table, - .probe = dprc_probe, - .remove = dprc_remove, -}; - -int __init dprc_driver_init(void) -{ - return fsl_mc_driver_register(&dprc_driver); -} - -void dprc_driver_exit(void) -{ - fsl_mc_driver_unregister(&dprc_driver); -} diff --git a/drivers/staging/fsl-mc/bus/dprc.c b/drivers/staging/fsl-mc/bus/dprc.c deleted file mode 100644 index 97f51726fa7e..000000000000 --- a/drivers/staging/fsl-mc/bus/dprc.c +++ /dev/null @@ -1,531 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#include -#include "../include/mc.h" -#include "fsl-mc-private.h" - -/** - * dprc_open() - Open DPRC object for use - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Container ID to open - * @token: Returned token of DPRC object - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Required before any operation on the object. - */ -int dprc_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int container_id, - u16 *token) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_open *cmd_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags, - 0); - cmd_params = (struct dprc_cmd_open *)cmd.params; - cmd_params->container_id = cpu_to_le32(container_id); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - *token = mc_cmd_hdr_read_token(&cmd); - - return 0; -} -EXPORT_SYMBOL_GPL(dprc_open); - -/** - * dprc_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dprc_close); - -/** - * dprc_set_irq() - Set IRQ information for the DPRC to trigger an interrupt. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @irq_index: Identifies the interrupt index to configure - * @irq_cfg: IRQ configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_set_irq(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - struct dprc_irq_cfg *irq_cfg) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_set_irq *cmd_params; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ, - cmd_flags, - token); - cmd_params = (struct dprc_cmd_set_irq *)cmd.params; - cmd_params->irq_val = cpu_to_le32(irq_cfg->val); - cmd_params->irq_index = irq_index; - cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr); - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -/** - * dprc_set_irq_enable() - Set overall interrupt state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @irq_index: The interrupt index to configure - * @en: Interrupt state - enable = 1, disable = 0 - * - * Allows GPP software to control when interrupts are generated. - * Each interrupt can have up to 32 causes. The enable/disable control's the - * overall interrupt state. if the interrupt is disabled no causes will cause - * an interrupt. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_set_irq_enable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u8 en) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_set_irq_enable *cmd_params; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_ENABLE, - cmd_flags, token); - cmd_params = (struct dprc_cmd_set_irq_enable *)cmd.params; - cmd_params->enable = en & DPRC_ENABLE; - cmd_params->irq_index = irq_index; - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -/** - * dprc_set_irq_mask() - Set interrupt mask. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @irq_index: The interrupt index to configure - * @mask: event mask to trigger interrupt; - * each bit: - * 0 = ignore event - * 1 = consider event for asserting irq - * - * Every interrupt can have up to 32 causes and the interrupt model supports - * masking/unmasking each cause independently - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_set_irq_mask(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 mask) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_set_irq_mask *cmd_params; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_MASK, - cmd_flags, token); - cmd_params = (struct dprc_cmd_set_irq_mask *)cmd.params; - cmd_params->mask = cpu_to_le32(mask); - cmd_params->irq_index = irq_index; - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -/** - * dprc_get_irq_status() - Get the current status of any pending interrupts. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @irq_index: The interrupt index to configure - * @status: Returned interrupts status - one bit per cause: - * 0 = no interrupt pending - * 1 = interrupt pending - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_irq_status(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 *status) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_get_irq_status *cmd_params; - struct dprc_rsp_get_irq_status *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_STATUS, - cmd_flags, token); - cmd_params = (struct dprc_cmd_get_irq_status *)cmd.params; - cmd_params->status = cpu_to_le32(*status); - cmd_params->irq_index = irq_index; - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dprc_rsp_get_irq_status *)cmd.params; - *status = le32_to_cpu(rsp_params->status); - - return 0; -} - -/** - * dprc_clear_irq_status() - Clear a pending interrupt's status - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @irq_index: The interrupt index to configure - * @status: bits to clear (W1C) - one bit per cause: - * 0 = don't change - * 1 = clear status bit - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_clear_irq_status(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 status) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_clear_irq_status *cmd_params; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLEAR_IRQ_STATUS, - cmd_flags, token); - cmd_params = (struct dprc_cmd_clear_irq_status *)cmd.params; - cmd_params->status = cpu_to_le32(status); - cmd_params->irq_index = irq_index; - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -/** - * dprc_get_attributes() - Obtains container attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @attributes Returned container attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_attributes(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dprc_attributes *attr) -{ - struct mc_command cmd = { 0 }; - struct dprc_rsp_get_attributes *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dprc_rsp_get_attributes *)cmd.params; - attr->container_id = le32_to_cpu(rsp_params->container_id); - attr->icid = le16_to_cpu(rsp_params->icid); - attr->options = le32_to_cpu(rsp_params->options); - attr->portal_id = le32_to_cpu(rsp_params->portal_id); - - return 0; -} - -/** - * dprc_get_obj_count() - Obtains the number of objects in the DPRC - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_count: Number of objects assigned to the DPRC - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - int *obj_count) -{ - struct mc_command cmd = { 0 }; - struct dprc_rsp_get_obj_count *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT, - cmd_flags, token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dprc_rsp_get_obj_count *)cmd.params; - *obj_count = le32_to_cpu(rsp_params->obj_count); - - return 0; -} -EXPORT_SYMBOL_GPL(dprc_get_obj_count); - -/** - * dprc_get_obj() - Get general information on an object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_index: Index of the object to be queried (< obj_count) - * @obj_desc: Returns the requested object descriptor - * - * The object descriptors are retrieved one by one by incrementing - * obj_index up to (not including) the value of obj_count returned - * from dprc_get_obj_count(). dprc_get_obj_count() must - * be called prior to dprc_get_obj(). - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - int obj_index, - struct fsl_mc_obj_desc *obj_desc) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_get_obj *cmd_params; - struct dprc_rsp_get_obj *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ, - cmd_flags, - token); - cmd_params = (struct dprc_cmd_get_obj *)cmd.params; - cmd_params->obj_index = cpu_to_le32(obj_index); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dprc_rsp_get_obj *)cmd.params; - obj_desc->id = le32_to_cpu(rsp_params->id); - obj_desc->vendor = le16_to_cpu(rsp_params->vendor); - obj_desc->irq_count = rsp_params->irq_count; - obj_desc->region_count = rsp_params->region_count; - obj_desc->state = le32_to_cpu(rsp_params->state); - obj_desc->ver_major = le16_to_cpu(rsp_params->version_major); - obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor); - obj_desc->flags = le16_to_cpu(rsp_params->flags); - strncpy(obj_desc->type, rsp_params->type, 16); - obj_desc->type[15] = '\0'; - strncpy(obj_desc->label, rsp_params->label, 16); - obj_desc->label[15] = '\0'; - return 0; -} -EXPORT_SYMBOL_GPL(dprc_get_obj); - -/** - * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_type: Type of the object to set its IRQ - * @obj_id: ID of the object to set its IRQ - * @irq_index: The interrupt index to configure - * @irq_cfg: IRQ configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_set_obj_irq(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - char *obj_type, - int obj_id, - u8 irq_index, - struct dprc_irq_cfg *irq_cfg) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_set_obj_irq *cmd_params; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_IRQ, - cmd_flags, - token); - cmd_params = (struct dprc_cmd_set_obj_irq *)cmd.params; - cmd_params->irq_val = cpu_to_le32(irq_cfg->val); - cmd_params->irq_index = irq_index; - cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr); - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num); - cmd_params->obj_id = cpu_to_le32(obj_id); - strncpy(cmd_params->obj_type, obj_type, 16); - cmd_params->obj_type[15] = '\0'; - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dprc_set_obj_irq); - -/** - * dprc_get_obj_region() - Get region information for a specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_type; Object type as returned in dprc_get_obj() - * @obj_id: Unique object instance as returned in dprc_get_obj() - * @region_index: The specific region to query - * @region_desc: Returns the requested region descriptor - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - char *obj_type, - int obj_id, - u8 region_index, - struct dprc_region_desc *region_desc) -{ - struct mc_command cmd = { 0 }; - struct dprc_cmd_get_obj_region *cmd_params; - struct dprc_rsp_get_obj_region *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG, - cmd_flags, token); - cmd_params = (struct dprc_cmd_get_obj_region *)cmd.params; - cmd_params->obj_id = cpu_to_le32(obj_id); - cmd_params->region_index = region_index; - strncpy(cmd_params->obj_type, obj_type, 16); - cmd_params->obj_type[15] = '\0'; - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params; - region_desc->base_offset = le64_to_cpu(rsp_params->base_addr); - region_desc->size = le32_to_cpu(rsp_params->size); - - return 0; -} -EXPORT_SYMBOL_GPL(dprc_get_obj_region); - -/** - * dprc_get_api_version - Get Data Path Resource Container API version - * @mc_io: Pointer to Mc portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: Major version of Data Path Resource Container API - * @minor_ver: Minor version of Data Path Resource Container API - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION, - cmd_flags, 0); - - /* send command to mc */ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - mc_cmd_read_api_version(&cmd, major_ver, minor_ver); - - return 0; -} - -/** - * dprc_get_container_id - Get container ID associated with a given portal. - * @mc_io: Pointer to Mc portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Requested container id - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_container_id(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int *container_id) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID, - cmd_flags, - 0); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - *container_id = (int)mc_cmd_read_object_id(&cmd); - - return 0; -} diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c deleted file mode 100644 index 8f313a41240b..000000000000 --- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c +++ /dev/null @@ -1,648 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * fsl-mc object allocator driver - * - * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. - * - */ - -#include -#include -#include "../include/mc.h" - -#include "fsl-mc-private.h" - -static bool __must_check fsl_mc_is_allocatable(struct fsl_mc_device *mc_dev) -{ - return is_fsl_mc_bus_dpbp(mc_dev) || - is_fsl_mc_bus_dpmcp(mc_dev) || - is_fsl_mc_bus_dpcon(mc_dev); -} - -/** - * fsl_mc_resource_pool_add_device - add allocatable object to a resource - * pool of a given fsl-mc bus - * - * @mc_bus: pointer to the fsl-mc bus - * @pool_type: pool type - * @mc_dev: pointer to allocatable fsl-mc device - */ -static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus - *mc_bus, - enum fsl_mc_pool_type - pool_type, - struct fsl_mc_device - *mc_dev) -{ - struct fsl_mc_resource_pool *res_pool; - struct fsl_mc_resource *resource; - struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; - int error = -EINVAL; - - if (pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES) - goto out; - if (!fsl_mc_is_allocatable(mc_dev)) - goto out; - if (mc_dev->resource) - goto out; - - res_pool = &mc_bus->resource_pools[pool_type]; - if (res_pool->type != pool_type) - goto out; - if (res_pool->mc_bus != mc_bus) - goto out; - - mutex_lock(&res_pool->mutex); - - if (res_pool->max_count < 0) - goto out_unlock; - if (res_pool->free_count < 0 || - res_pool->free_count > res_pool->max_count) - goto out_unlock; - - resource = devm_kzalloc(&mc_bus_dev->dev, sizeof(*resource), - GFP_KERNEL); - if (!resource) { - error = -ENOMEM; - dev_err(&mc_bus_dev->dev, - "Failed to allocate memory for fsl_mc_resource\n"); - goto out_unlock; - } - - resource->type = pool_type; - resource->id = mc_dev->obj_desc.id; - resource->data = mc_dev; - resource->parent_pool = res_pool; - INIT_LIST_HEAD(&resource->node); - list_add_tail(&resource->node, &res_pool->free_list); - mc_dev->resource = resource; - res_pool->free_count++; - res_pool->max_count++; - error = 0; -out_unlock: - mutex_unlock(&res_pool->mutex); -out: - return error; -} - -/** - * fsl_mc_resource_pool_remove_device - remove an allocatable device from a - * resource pool - * - * @mc_dev: pointer to allocatable fsl-mc device - * - * It permanently removes an allocatable fsl-mc device from the resource - * pool. It's an error if the device is in use. - */ -static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device - *mc_dev) -{ - struct fsl_mc_device *mc_bus_dev; - struct fsl_mc_bus *mc_bus; - struct fsl_mc_resource_pool *res_pool; - struct fsl_mc_resource *resource; - int error = -EINVAL; - - if (!fsl_mc_is_allocatable(mc_dev)) - goto out; - - resource = mc_dev->resource; - if (!resource || resource->data != mc_dev) - goto out; - - mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); - mc_bus = to_fsl_mc_bus(mc_bus_dev); - res_pool = resource->parent_pool; - if (res_pool != &mc_bus->resource_pools[resource->type]) - goto out; - - mutex_lock(&res_pool->mutex); - - if (res_pool->max_count <= 0) - goto out_unlock; - if (res_pool->free_count <= 0 || - res_pool->free_count > res_pool->max_count) - goto out_unlock; - - /* - * If the device is currently allocated, its resource is not - * in the free list and thus, the device cannot be removed. - */ - if (list_empty(&resource->node)) { - error = -EBUSY; - dev_err(&mc_bus_dev->dev, - "Device %s cannot be removed from resource pool\n", - dev_name(&mc_dev->dev)); - goto out_unlock; - } - - list_del_init(&resource->node); - res_pool->free_count--; - res_pool->max_count--; - - devm_kfree(&mc_bus_dev->dev, resource); - mc_dev->resource = NULL; - error = 0; -out_unlock: - mutex_unlock(&res_pool->mutex); -out: - return error; -} - -static const char *const fsl_mc_pool_type_strings[] = { - [FSL_MC_POOL_DPMCP] = "dpmcp", - [FSL_MC_POOL_DPBP] = "dpbp", - [FSL_MC_POOL_DPCON] = "dpcon", - [FSL_MC_POOL_IRQ] = "irq", -}; - -static int __must_check object_type_to_pool_type(const char *object_type, - enum fsl_mc_pool_type - *pool_type) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(fsl_mc_pool_type_strings); i++) { - if (strcmp(object_type, fsl_mc_pool_type_strings[i]) == 0) { - *pool_type = i; - return 0; - } - } - - return -EINVAL; -} - -int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, - enum fsl_mc_pool_type pool_type, - struct fsl_mc_resource **new_resource) -{ - struct fsl_mc_resource_pool *res_pool; - struct fsl_mc_resource *resource; - struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; - int error = -EINVAL; - - BUILD_BUG_ON(ARRAY_SIZE(fsl_mc_pool_type_strings) != - FSL_MC_NUM_POOL_TYPES); - - *new_resource = NULL; - if (pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES) - goto out; - - res_pool = &mc_bus->resource_pools[pool_type]; - if (res_pool->mc_bus != mc_bus) - goto out; - - mutex_lock(&res_pool->mutex); - resource = list_first_entry_or_null(&res_pool->free_list, - struct fsl_mc_resource, node); - - if (!resource) { - error = -ENXIO; - dev_err(&mc_bus_dev->dev, - "No more resources of type %s left\n", - fsl_mc_pool_type_strings[pool_type]); - goto out_unlock; - } - - if (resource->type != pool_type) - goto out_unlock; - if (resource->parent_pool != res_pool) - goto out_unlock; - if (res_pool->free_count <= 0 || - res_pool->free_count > res_pool->max_count) - goto out_unlock; - - list_del_init(&resource->node); - - res_pool->free_count--; - error = 0; -out_unlock: - mutex_unlock(&res_pool->mutex); - *new_resource = resource; -out: - return error; -} -EXPORT_SYMBOL_GPL(fsl_mc_resource_allocate); - -void fsl_mc_resource_free(struct fsl_mc_resource *resource) -{ - struct fsl_mc_resource_pool *res_pool; - - res_pool = resource->parent_pool; - if (resource->type != res_pool->type) - return; - - mutex_lock(&res_pool->mutex); - if (res_pool->free_count < 0 || - res_pool->free_count >= res_pool->max_count) - goto out_unlock; - - if (!list_empty(&resource->node)) - goto out_unlock; - - list_add_tail(&resource->node, &res_pool->free_list); - res_pool->free_count++; -out_unlock: - mutex_unlock(&res_pool->mutex); -} -EXPORT_SYMBOL_GPL(fsl_mc_resource_free); - -/** - * fsl_mc_object_allocate - Allocates an fsl-mc object of the given - * pool type from a given fsl-mc bus instance - * - * @mc_dev: fsl-mc device which is used in conjunction with the - * allocated object - * @pool_type: pool type - * @new_mc_dev: pointer to area where the pointer to the allocated device - * is to be returned - * - * Allocatable objects are always used in conjunction with some functional - * device. This function allocates an object of the specified type from - * the DPRC containing the functional device. - * - * NOTE: pool_type must be different from FSL_MC_POOL_MCP, since MC - * portals are allocated using fsl_mc_portal_allocate(), instead of - * this function. - */ -int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev, - enum fsl_mc_pool_type pool_type, - struct fsl_mc_device **new_mc_adev) -{ - struct fsl_mc_device *mc_bus_dev; - struct fsl_mc_bus *mc_bus; - struct fsl_mc_device *mc_adev; - int error = -EINVAL; - struct fsl_mc_resource *resource = NULL; - - *new_mc_adev = NULL; - if (mc_dev->flags & FSL_MC_IS_DPRC) - goto error; - - if (!dev_is_fsl_mc(mc_dev->dev.parent)) - goto error; - - if (pool_type == FSL_MC_POOL_DPMCP) - goto error; - - mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); - mc_bus = to_fsl_mc_bus(mc_bus_dev); - error = fsl_mc_resource_allocate(mc_bus, pool_type, &resource); - if (error < 0) - goto error; - - mc_adev = resource->data; - if (!mc_adev) - goto error; - - *new_mc_adev = mc_adev; - return 0; -error: - if (resource) - fsl_mc_resource_free(resource); - - return error; -} -EXPORT_SYMBOL_GPL(fsl_mc_object_allocate); - -/** - * fsl_mc_object_free - Returns an fsl-mc object to the resource - * pool where it came from. - * @mc_adev: Pointer to the fsl-mc device - */ -void fsl_mc_object_free(struct fsl_mc_device *mc_adev) -{ - struct fsl_mc_resource *resource; - - resource = mc_adev->resource; - if (resource->type == FSL_MC_POOL_DPMCP) - return; - if (resource->data != mc_adev) - return; - - fsl_mc_resource_free(resource); -} -EXPORT_SYMBOL_GPL(fsl_mc_object_free); - -/* - * A DPRC and the devices in the DPRC all share the same GIC-ITS device - * ID. A block of IRQs is pre-allocated and maintained in a pool - * from which devices can allocate them when needed. - */ - -/* - * Initialize the interrupt pool associated with an fsl-mc bus. - * It allocates a block of IRQs from the GIC-ITS. - */ -int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, - unsigned int irq_count) -{ - unsigned int i; - struct msi_desc *msi_desc; - struct fsl_mc_device_irq *irq_resources; - struct fsl_mc_device_irq *mc_dev_irq; - int error; - struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; - struct fsl_mc_resource_pool *res_pool = - &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; - - if (irq_count == 0 || - irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) - return -EINVAL; - - error = fsl_mc_msi_domain_alloc_irqs(&mc_bus_dev->dev, irq_count); - if (error < 0) - return error; - - irq_resources = devm_kzalloc(&mc_bus_dev->dev, - sizeof(*irq_resources) * irq_count, - GFP_KERNEL); - if (!irq_resources) { - error = -ENOMEM; - goto cleanup_msi_irqs; - } - - for (i = 0; i < irq_count; i++) { - mc_dev_irq = &irq_resources[i]; - - /* - * NOTE: This mc_dev_irq's MSI addr/value pair will be set - * by the fsl_mc_msi_write_msg() callback - */ - mc_dev_irq->resource.type = res_pool->type; - mc_dev_irq->resource.data = mc_dev_irq; - mc_dev_irq->resource.parent_pool = res_pool; - INIT_LIST_HEAD(&mc_dev_irq->resource.node); - list_add_tail(&mc_dev_irq->resource.node, &res_pool->free_list); - } - - for_each_msi_entry(msi_desc, &mc_bus_dev->dev) { - mc_dev_irq = &irq_resources[msi_desc->fsl_mc.msi_index]; - mc_dev_irq->msi_desc = msi_desc; - mc_dev_irq->resource.id = msi_desc->irq; - } - - res_pool->max_count = irq_count; - res_pool->free_count = irq_count; - mc_bus->irq_resources = irq_resources; - return 0; - -cleanup_msi_irqs: - fsl_mc_msi_domain_free_irqs(&mc_bus_dev->dev); - return error; -} -EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool); - -/** - * Teardown the interrupt pool associated with an fsl-mc bus. - * It frees the IRQs that were allocated to the pool, back to the GIC-ITS. - */ -void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus) -{ - struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; - struct fsl_mc_resource_pool *res_pool = - &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; - - if (!mc_bus->irq_resources) - return; - - if (res_pool->max_count == 0) - return; - - if (res_pool->free_count != res_pool->max_count) - return; - - INIT_LIST_HEAD(&res_pool->free_list); - res_pool->max_count = 0; - res_pool->free_count = 0; - mc_bus->irq_resources = NULL; - fsl_mc_msi_domain_free_irqs(&mc_bus_dev->dev); -} -EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool); - -/** - * Allocate the IRQs required by a given fsl-mc device. - */ -int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev) -{ - int i; - int irq_count; - int res_allocated_count = 0; - int error = -EINVAL; - struct fsl_mc_device_irq **irqs = NULL; - struct fsl_mc_bus *mc_bus; - struct fsl_mc_resource_pool *res_pool; - - if (mc_dev->irqs) - return -EINVAL; - - irq_count = mc_dev->obj_desc.irq_count; - if (irq_count == 0) - return -EINVAL; - - if (is_fsl_mc_bus_dprc(mc_dev)) - mc_bus = to_fsl_mc_bus(mc_dev); - else - mc_bus = to_fsl_mc_bus(to_fsl_mc_device(mc_dev->dev.parent)); - - if (!mc_bus->irq_resources) - return -EINVAL; - - res_pool = &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; - if (res_pool->free_count < irq_count) { - dev_err(&mc_dev->dev, - "Not able to allocate %u irqs for device\n", irq_count); - return -ENOSPC; - } - - irqs = devm_kzalloc(&mc_dev->dev, irq_count * sizeof(irqs[0]), - GFP_KERNEL); - if (!irqs) - return -ENOMEM; - - for (i = 0; i < irq_count; i++) { - struct fsl_mc_resource *resource; - - error = fsl_mc_resource_allocate(mc_bus, FSL_MC_POOL_IRQ, - &resource); - if (error < 0) - goto error_resource_alloc; - - irqs[i] = to_fsl_mc_irq(resource); - res_allocated_count++; - - irqs[i]->mc_dev = mc_dev; - irqs[i]->dev_irq_index = i; - } - - mc_dev->irqs = irqs; - return 0; - -error_resource_alloc: - for (i = 0; i < res_allocated_count; i++) { - irqs[i]->mc_dev = NULL; - fsl_mc_resource_free(&irqs[i]->resource); - } - - return error; -} -EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs); - -/* - * Frees the IRQs that were allocated for an fsl-mc device. - */ -void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev) -{ - int i; - int irq_count; - struct fsl_mc_bus *mc_bus; - struct fsl_mc_device_irq **irqs = mc_dev->irqs; - - if (!irqs) - return; - - irq_count = mc_dev->obj_desc.irq_count; - - if (is_fsl_mc_bus_dprc(mc_dev)) - mc_bus = to_fsl_mc_bus(mc_dev); - else - mc_bus = to_fsl_mc_bus(to_fsl_mc_device(mc_dev->dev.parent)); - - if (!mc_bus->irq_resources) - return; - - for (i = 0; i < irq_count; i++) { - irqs[i]->mc_dev = NULL; - fsl_mc_resource_free(&irqs[i]->resource); - } - - mc_dev->irqs = NULL; -} -EXPORT_SYMBOL_GPL(fsl_mc_free_irqs); - -void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev) -{ - int pool_type; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - - for (pool_type = 0; pool_type < FSL_MC_NUM_POOL_TYPES; pool_type++) { - struct fsl_mc_resource_pool *res_pool = - &mc_bus->resource_pools[pool_type]; - - res_pool->type = pool_type; - res_pool->max_count = 0; - res_pool->free_count = 0; - res_pool->mc_bus = mc_bus; - INIT_LIST_HEAD(&res_pool->free_list); - mutex_init(&res_pool->mutex); - } -} - -static void fsl_mc_cleanup_resource_pool(struct fsl_mc_device *mc_bus_dev, - enum fsl_mc_pool_type pool_type) -{ - struct fsl_mc_resource *resource; - struct fsl_mc_resource *next; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - struct fsl_mc_resource_pool *res_pool = - &mc_bus->resource_pools[pool_type]; - int free_count = 0; - - list_for_each_entry_safe(resource, next, &res_pool->free_list, node) { - free_count++; - devm_kfree(&mc_bus_dev->dev, resource); - } -} - -void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) -{ - int pool_type; - - for (pool_type = 0; pool_type < FSL_MC_NUM_POOL_TYPES; pool_type++) - fsl_mc_cleanup_resource_pool(mc_bus_dev, pool_type); -} - -/** - * fsl_mc_allocator_probe - callback invoked when an allocatable device is - * being added to the system - */ -static int fsl_mc_allocator_probe(struct fsl_mc_device *mc_dev) -{ - enum fsl_mc_pool_type pool_type; - struct fsl_mc_device *mc_bus_dev; - struct fsl_mc_bus *mc_bus; - int error; - - if (!fsl_mc_is_allocatable(mc_dev)) - return -EINVAL; - - mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); - if (!dev_is_fsl_mc(&mc_bus_dev->dev)) - return -EINVAL; - - mc_bus = to_fsl_mc_bus(mc_bus_dev); - error = object_type_to_pool_type(mc_dev->obj_desc.type, &pool_type); - if (error < 0) - return error; - - error = fsl_mc_resource_pool_add_device(mc_bus, pool_type, mc_dev); - if (error < 0) - return error; - - dev_dbg(&mc_dev->dev, - "Allocatable fsl-mc device bound to fsl_mc_allocator driver"); - return 0; -} - -/** - * fsl_mc_allocator_remove - callback invoked when an allocatable device is - * being removed from the system - */ -static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) -{ - int error; - - if (!fsl_mc_is_allocatable(mc_dev)) - return -EINVAL; - - if (mc_dev->resource) { - error = fsl_mc_resource_pool_remove_device(mc_dev); - if (error < 0) - return error; - } - - dev_dbg(&mc_dev->dev, - "Allocatable fsl-mc device unbound from fsl_mc_allocator driver"); - return 0; -} - -static const struct fsl_mc_device_id match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpbp", - }, - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpmcp", - }, - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpcon", - }, - {.vendor = 0x0}, -}; - -static struct fsl_mc_driver fsl_mc_allocator_driver = { - .driver = { - .name = "fsl_mc_allocator", - .pm = NULL, - }, - .match_id_table = match_id_table, - .probe = fsl_mc_allocator_probe, - .remove = fsl_mc_allocator_remove, -}; - -int __init fsl_mc_allocator_driver_init(void) -{ - return fsl_mc_driver_register(&fsl_mc_allocator_driver); -} diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c deleted file mode 100644 index 1b333c43aae9..000000000000 --- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c +++ /dev/null @@ -1,948 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Freescale Management Complex (MC) bus driver - * - * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * Author: German Rivera - * - */ - -#define pr_fmt(fmt) "fsl-mc: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "fsl-mc-private.h" - -/** - * Default DMA mask for devices on a fsl-mc bus - */ -#define FSL_MC_DEFAULT_DMA_MASK (~0ULL) - -/** - * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device - * @root_mc_bus_dev: fsl-mc device representing the root DPRC - * @num_translation_ranges: number of entries in addr_translation_ranges - * @translation_ranges: array of bus to system address translation ranges - */ -struct fsl_mc { - struct fsl_mc_device *root_mc_bus_dev; - u8 num_translation_ranges; - struct fsl_mc_addr_translation_range *translation_ranges; -}; - -/** - * struct fsl_mc_addr_translation_range - bus to system address translation - * range - * @mc_region_type: Type of MC region for the range being translated - * @start_mc_offset: Start MC offset of the range being translated - * @end_mc_offset: MC offset of the first byte after the range (last MC - * offset of the range is end_mc_offset - 1) - * @start_phys_addr: system physical address corresponding to start_mc_addr - */ -struct fsl_mc_addr_translation_range { - enum dprc_region_type mc_region_type; - u64 start_mc_offset; - u64 end_mc_offset; - phys_addr_t start_phys_addr; -}; - -/** - * struct mc_version - * @major: Major version number: incremented on API compatibility changes - * @minor: Minor version number: incremented on API additions (that are - * backward compatible); reset when major version is incremented - * @revision: Internal revision number: incremented on implementation changes - * and/or bug fixes that have no impact on API - */ -struct mc_version { - u32 major; - u32 minor; - u32 revision; -}; - -/** - * fsl_mc_bus_match - device to driver matching callback - * @dev: the fsl-mc device to match against - * @drv: the device driver to search for matching fsl-mc object type - * structures - * - * Returns 1 on success, 0 otherwise. - */ -static int fsl_mc_bus_match(struct device *dev, struct device_driver *drv) -{ - const struct fsl_mc_device_id *id; - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv); - bool found = false; - - if (!mc_drv->match_id_table) - goto out; - - /* - * If the object is not 'plugged' don't match. - * Only exception is the root DPRC, which is a special case. - */ - if ((mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED) == 0 && - !fsl_mc_is_root_dprc(&mc_dev->dev)) - goto out; - - /* - * Traverse the match_id table of the given driver, trying to find - * a matching for the given device. - */ - for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) { - if (id->vendor == mc_dev->obj_desc.vendor && - strcmp(id->obj_type, mc_dev->obj_desc.type) == 0) { - found = true; - - break; - } - } - -out: - dev_dbg(dev, "%smatched\n", found ? "" : "not "); - return found; -} - -/** - * fsl_mc_bus_uevent - callback invoked when a device is added - */ -static int fsl_mc_bus_uevent(struct device *dev, struct kobj_uevent_env *env) -{ - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - - if (add_uevent_var(env, "MODALIAS=fsl-mc:v%08Xd%s", - mc_dev->obj_desc.vendor, - mc_dev->obj_desc.type)) - return -ENOMEM; - - return 0; -} - -static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - - return sprintf(buf, "fsl-mc:v%08Xd%s\n", mc_dev->obj_desc.vendor, - mc_dev->obj_desc.type); -} -static DEVICE_ATTR_RO(modalias); - -static struct attribute *fsl_mc_dev_attrs[] = { - &dev_attr_modalias.attr, - NULL, -}; - -ATTRIBUTE_GROUPS(fsl_mc_dev); - -struct bus_type fsl_mc_bus_type = { - .name = "fsl-mc", - .match = fsl_mc_bus_match, - .uevent = fsl_mc_bus_uevent, - .dev_groups = fsl_mc_dev_groups, -}; -EXPORT_SYMBOL_GPL(fsl_mc_bus_type); - -struct device_type fsl_mc_bus_dprc_type = { - .name = "fsl_mc_bus_dprc" -}; - -struct device_type fsl_mc_bus_dpni_type = { - .name = "fsl_mc_bus_dpni" -}; - -struct device_type fsl_mc_bus_dpio_type = { - .name = "fsl_mc_bus_dpio" -}; - -struct device_type fsl_mc_bus_dpsw_type = { - .name = "fsl_mc_bus_dpsw" -}; - -struct device_type fsl_mc_bus_dpbp_type = { - .name = "fsl_mc_bus_dpbp" -}; - -struct device_type fsl_mc_bus_dpcon_type = { - .name = "fsl_mc_bus_dpcon" -}; - -struct device_type fsl_mc_bus_dpmcp_type = { - .name = "fsl_mc_bus_dpmcp" -}; - -struct device_type fsl_mc_bus_dpmac_type = { - .name = "fsl_mc_bus_dpmac" -}; - -struct device_type fsl_mc_bus_dprtc_type = { - .name = "fsl_mc_bus_dprtc" -}; - -static struct device_type *fsl_mc_get_device_type(const char *type) -{ - static const struct { - struct device_type *dev_type; - const char *type; - } dev_types[] = { - { &fsl_mc_bus_dprc_type, "dprc" }, - { &fsl_mc_bus_dpni_type, "dpni" }, - { &fsl_mc_bus_dpio_type, "dpio" }, - { &fsl_mc_bus_dpsw_type, "dpsw" }, - { &fsl_mc_bus_dpbp_type, "dpbp" }, - { &fsl_mc_bus_dpcon_type, "dpcon" }, - { &fsl_mc_bus_dpmcp_type, "dpmcp" }, - { &fsl_mc_bus_dpmac_type, "dpmac" }, - { &fsl_mc_bus_dprtc_type, "dprtc" }, - { NULL, NULL } - }; - int i; - - for (i = 0; dev_types[i].dev_type; i++) - if (!strcmp(dev_types[i].type, type)) - return dev_types[i].dev_type; - - return NULL; -} - -static int fsl_mc_driver_probe(struct device *dev) -{ - struct fsl_mc_driver *mc_drv; - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - int error; - - mc_drv = to_fsl_mc_driver(dev->driver); - - error = mc_drv->probe(mc_dev); - if (error < 0) { - if (error != -EPROBE_DEFER) - dev_err(dev, "%s failed: %d\n", __func__, error); - return error; - } - - return 0; -} - -static int fsl_mc_driver_remove(struct device *dev) -{ - struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver); - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - int error; - - error = mc_drv->remove(mc_dev); - if (error < 0) { - dev_err(dev, "%s failed: %d\n", __func__, error); - return error; - } - - return 0; -} - -static void fsl_mc_driver_shutdown(struct device *dev) -{ - struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver); - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - - mc_drv->shutdown(mc_dev); -} - -/** - * __fsl_mc_driver_register - registers a child device driver with the - * MC bus - * - * This function is implicitly invoked from the registration function of - * fsl_mc device drivers, which is generated by the - * module_fsl_mc_driver() macro. - */ -int __fsl_mc_driver_register(struct fsl_mc_driver *mc_driver, - struct module *owner) -{ - int error; - - mc_driver->driver.owner = owner; - mc_driver->driver.bus = &fsl_mc_bus_type; - - if (mc_driver->probe) - mc_driver->driver.probe = fsl_mc_driver_probe; - - if (mc_driver->remove) - mc_driver->driver.remove = fsl_mc_driver_remove; - - if (mc_driver->shutdown) - mc_driver->driver.shutdown = fsl_mc_driver_shutdown; - - error = driver_register(&mc_driver->driver); - if (error < 0) { - pr_err("driver_register() failed for %s: %d\n", - mc_driver->driver.name, error); - return error; - } - - return 0; -} -EXPORT_SYMBOL_GPL(__fsl_mc_driver_register); - -/** - * fsl_mc_driver_unregister - unregisters a device driver from the - * MC bus - */ -void fsl_mc_driver_unregister(struct fsl_mc_driver *mc_driver) -{ - driver_unregister(&mc_driver->driver); -} -EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister); - -/** - * mc_get_version() - Retrieves the Management Complex firmware - * version information - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @mc_ver_info: Returned version information structure - * - * Return: '0' on Success; Error code otherwise. - */ -static int mc_get_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - struct mc_version *mc_ver_info) -{ - struct mc_command cmd = { 0 }; - struct dpmng_rsp_get_version *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION, - cmd_flags, - 0); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dpmng_rsp_get_version *)cmd.params; - mc_ver_info->revision = le32_to_cpu(rsp_params->revision); - mc_ver_info->major = le32_to_cpu(rsp_params->version_major); - mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor); - - return 0; -} - -/** - * fsl_mc_get_root_dprc - function to traverse to the root dprc - */ -static void fsl_mc_get_root_dprc(struct device *dev, - struct device **root_dprc_dev) -{ - if (!dev) { - *root_dprc_dev = NULL; - } else if (!dev_is_fsl_mc(dev)) { - *root_dprc_dev = NULL; - } else { - *root_dprc_dev = dev; - while (dev_is_fsl_mc((*root_dprc_dev)->parent)) - *root_dprc_dev = (*root_dprc_dev)->parent; - } -} - -static int get_dprc_attr(struct fsl_mc_io *mc_io, - int container_id, struct dprc_attributes *attr) -{ - u16 dprc_handle; - int error; - - error = dprc_open(mc_io, 0, container_id, &dprc_handle); - if (error < 0) { - dev_err(mc_io->dev, "dprc_open() failed: %d\n", error); - return error; - } - - memset(attr, 0, sizeof(struct dprc_attributes)); - error = dprc_get_attributes(mc_io, 0, dprc_handle, attr); - if (error < 0) { - dev_err(mc_io->dev, "dprc_get_attributes() failed: %d\n", - error); - goto common_cleanup; - } - - error = 0; - -common_cleanup: - (void)dprc_close(mc_io, 0, dprc_handle); - return error; -} - -static int get_dprc_icid(struct fsl_mc_io *mc_io, - int container_id, u16 *icid) -{ - struct dprc_attributes attr; - int error; - - error = get_dprc_attr(mc_io, container_id, &attr); - if (error == 0) - *icid = attr.icid; - - return error; -} - -static int translate_mc_addr(struct fsl_mc_device *mc_dev, - enum dprc_region_type mc_region_type, - u64 mc_offset, phys_addr_t *phys_addr) -{ - int i; - struct device *root_dprc_dev; - struct fsl_mc *mc; - - fsl_mc_get_root_dprc(&mc_dev->dev, &root_dprc_dev); - mc = dev_get_drvdata(root_dprc_dev->parent); - - if (mc->num_translation_ranges == 0) { - /* - * Do identity mapping: - */ - *phys_addr = mc_offset; - return 0; - } - - for (i = 0; i < mc->num_translation_ranges; i++) { - struct fsl_mc_addr_translation_range *range = - &mc->translation_ranges[i]; - - if (mc_region_type == range->mc_region_type && - mc_offset >= range->start_mc_offset && - mc_offset < range->end_mc_offset) { - *phys_addr = range->start_phys_addr + - (mc_offset - range->start_mc_offset); - return 0; - } - } - - return -EFAULT; -} - -static int fsl_mc_device_get_mmio_regions(struct fsl_mc_device *mc_dev, - struct fsl_mc_device *mc_bus_dev) -{ - int i; - int error; - struct resource *regions; - struct fsl_mc_obj_desc *obj_desc = &mc_dev->obj_desc; - struct device *parent_dev = mc_dev->dev.parent; - enum dprc_region_type mc_region_type; - - if (is_fsl_mc_bus_dprc(mc_dev) || - is_fsl_mc_bus_dpmcp(mc_dev)) { - mc_region_type = DPRC_REGION_TYPE_MC_PORTAL; - } else if (is_fsl_mc_bus_dpio(mc_dev)) { - mc_region_type = DPRC_REGION_TYPE_QBMAN_PORTAL; - } else { - /* - * This function should not have been called for this MC object - * type, as this object type is not supposed to have MMIO - * regions - */ - return -EINVAL; - } - - regions = kmalloc_array(obj_desc->region_count, - sizeof(regions[0]), GFP_KERNEL); - if (!regions) - return -ENOMEM; - - for (i = 0; i < obj_desc->region_count; i++) { - struct dprc_region_desc region_desc; - - error = dprc_get_obj_region(mc_bus_dev->mc_io, - 0, - mc_bus_dev->mc_handle, - obj_desc->type, - obj_desc->id, i, ®ion_desc); - if (error < 0) { - dev_err(parent_dev, - "dprc_get_obj_region() failed: %d\n", error); - goto error_cleanup_regions; - } - - error = translate_mc_addr(mc_dev, mc_region_type, - region_desc.base_offset, - ®ions[i].start); - if (error < 0) { - dev_err(parent_dev, - "Invalid MC offset: %#x (for %s.%d\'s region %d)\n", - region_desc.base_offset, - obj_desc->type, obj_desc->id, i); - goto error_cleanup_regions; - } - - regions[i].end = regions[i].start + region_desc.size - 1; - regions[i].name = "fsl-mc object MMIO region"; - regions[i].flags = IORESOURCE_IO; - if (region_desc.flags & DPRC_REGION_CACHEABLE) - regions[i].flags |= IORESOURCE_CACHEABLE; - } - - mc_dev->regions = regions; - return 0; - -error_cleanup_regions: - kfree(regions); - return error; -} - -/** - * fsl_mc_is_root_dprc - function to check if a given device is a root dprc - */ -bool fsl_mc_is_root_dprc(struct device *dev) -{ - struct device *root_dprc_dev; - - fsl_mc_get_root_dprc(dev, &root_dprc_dev); - if (!root_dprc_dev) - return false; - return dev == root_dprc_dev; -} - -static void fsl_mc_device_release(struct device *dev) -{ - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - - kfree(mc_dev->regions); - - if (is_fsl_mc_bus_dprc(mc_dev)) - kfree(to_fsl_mc_bus(mc_dev)); - else - kfree(mc_dev); -} - -/** - * Add a newly discovered fsl-mc device to be visible in Linux - */ -int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, - struct fsl_mc_io *mc_io, - struct device *parent_dev, - struct fsl_mc_device **new_mc_dev) -{ - int error; - struct fsl_mc_device *mc_dev = NULL; - struct fsl_mc_bus *mc_bus = NULL; - struct fsl_mc_device *parent_mc_dev; - - if (dev_is_fsl_mc(parent_dev)) - parent_mc_dev = to_fsl_mc_device(parent_dev); - else - parent_mc_dev = NULL; - - if (strcmp(obj_desc->type, "dprc") == 0) { - /* - * Allocate an MC bus device object: - */ - mc_bus = kzalloc(sizeof(*mc_bus), GFP_KERNEL); - if (!mc_bus) - return -ENOMEM; - - mc_dev = &mc_bus->mc_dev; - } else { - /* - * Allocate a regular fsl_mc_device object: - */ - mc_dev = kzalloc(sizeof(*mc_dev), GFP_KERNEL); - if (!mc_dev) - return -ENOMEM; - } - - mc_dev->obj_desc = *obj_desc; - mc_dev->mc_io = mc_io; - device_initialize(&mc_dev->dev); - mc_dev->dev.parent = parent_dev; - mc_dev->dev.bus = &fsl_mc_bus_type; - mc_dev->dev.release = fsl_mc_device_release; - mc_dev->dev.type = fsl_mc_get_device_type(obj_desc->type); - if (!mc_dev->dev.type) { - error = -ENODEV; - dev_err(parent_dev, "unknown device type %s\n", obj_desc->type); - goto error_cleanup_dev; - } - dev_set_name(&mc_dev->dev, "%s.%d", obj_desc->type, obj_desc->id); - - if (strcmp(obj_desc->type, "dprc") == 0) { - struct fsl_mc_io *mc_io2; - - mc_dev->flags |= FSL_MC_IS_DPRC; - - /* - * To get the DPRC's ICID, we need to open the DPRC - * in get_dprc_icid(). For child DPRCs, we do so using the - * parent DPRC's MC portal instead of the child DPRC's MC - * portal, in case the child DPRC is already opened with - * its own portal (e.g., the DPRC used by AIOP). - * - * NOTE: There cannot be more than one active open for a - * given MC object, using the same MC portal. - */ - if (parent_mc_dev) { - /* - * device being added is a child DPRC device - */ - mc_io2 = parent_mc_dev->mc_io; - } else { - /* - * device being added is the root DPRC device - */ - if (!mc_io) { - error = -EINVAL; - goto error_cleanup_dev; - } - - mc_io2 = mc_io; - } - - error = get_dprc_icid(mc_io2, obj_desc->id, &mc_dev->icid); - if (error < 0) - goto error_cleanup_dev; - } else { - /* - * A non-DPRC object has to be a child of a DPRC, use the - * parent's ICID and interrupt domain. - */ - mc_dev->icid = parent_mc_dev->icid; - mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK; - mc_dev->dev.dma_mask = &mc_dev->dma_mask; - dev_set_msi_domain(&mc_dev->dev, - dev_get_msi_domain(&parent_mc_dev->dev)); - } - - /* - * Get MMIO regions for the device from the MC: - * - * NOTE: the root DPRC is a special case as its MMIO region is - * obtained from the device tree - */ - if (parent_mc_dev && obj_desc->region_count != 0) { - error = fsl_mc_device_get_mmio_regions(mc_dev, - parent_mc_dev); - if (error < 0) - goto error_cleanup_dev; - } - - /* Objects are coherent, unless 'no shareability' flag set. */ - if (!(obj_desc->flags & FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY)) - arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true); - - /* - * The device-specific probe callback will get invoked by device_add() - */ - error = device_add(&mc_dev->dev); - if (error < 0) { - dev_err(parent_dev, - "device_add() failed for device %s: %d\n", - dev_name(&mc_dev->dev), error); - goto error_cleanup_dev; - } - - dev_dbg(parent_dev, "added %s\n", dev_name(&mc_dev->dev)); - - *new_mc_dev = mc_dev; - return 0; - -error_cleanup_dev: - kfree(mc_dev->regions); - kfree(mc_bus); - kfree(mc_dev); - - return error; -} -EXPORT_SYMBOL_GPL(fsl_mc_device_add); - -/** - * fsl_mc_device_remove - Remove an fsl-mc device from being visible to - * Linux - * - * @mc_dev: Pointer to an fsl-mc device - */ -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev) -{ - /* - * The device-specific remove callback will get invoked by device_del() - */ - device_del(&mc_dev->dev); - put_device(&mc_dev->dev); -} -EXPORT_SYMBOL_GPL(fsl_mc_device_remove); - -static int parse_mc_ranges(struct device *dev, - int *paddr_cells, - int *mc_addr_cells, - int *mc_size_cells, - const __be32 **ranges_start) -{ - const __be32 *prop; - int range_tuple_cell_count; - int ranges_len; - int tuple_len; - struct device_node *mc_node = dev->of_node; - - *ranges_start = of_get_property(mc_node, "ranges", &ranges_len); - if (!(*ranges_start) || !ranges_len) { - dev_warn(dev, - "missing or empty ranges property for device tree node '%s'\n", - mc_node->name); - return 0; - } - - *paddr_cells = of_n_addr_cells(mc_node); - - prop = of_get_property(mc_node, "#address-cells", NULL); - if (prop) - *mc_addr_cells = be32_to_cpup(prop); - else - *mc_addr_cells = *paddr_cells; - - prop = of_get_property(mc_node, "#size-cells", NULL); - if (prop) - *mc_size_cells = be32_to_cpup(prop); - else - *mc_size_cells = of_n_size_cells(mc_node); - - range_tuple_cell_count = *paddr_cells + *mc_addr_cells + - *mc_size_cells; - - tuple_len = range_tuple_cell_count * sizeof(__be32); - if (ranges_len % tuple_len != 0) { - dev_err(dev, "malformed ranges property '%s'\n", mc_node->name); - return -EINVAL; - } - - return ranges_len / tuple_len; -} - -static int get_mc_addr_translation_ranges(struct device *dev, - struct fsl_mc_addr_translation_range - **ranges, - u8 *num_ranges) -{ - int ret; - int paddr_cells; - int mc_addr_cells; - int mc_size_cells; - int i; - const __be32 *ranges_start; - const __be32 *cell; - - ret = parse_mc_ranges(dev, - &paddr_cells, - &mc_addr_cells, - &mc_size_cells, - &ranges_start); - if (ret < 0) - return ret; - - *num_ranges = ret; - if (!ret) { - /* - * Missing or empty ranges property ("ranges;") for the - * 'fsl,qoriq-mc' node. In this case, identity mapping - * will be used. - */ - *ranges = NULL; - return 0; - } - - *ranges = devm_kcalloc(dev, *num_ranges, - sizeof(struct fsl_mc_addr_translation_range), - GFP_KERNEL); - if (!(*ranges)) - return -ENOMEM; - - cell = ranges_start; - for (i = 0; i < *num_ranges; ++i) { - struct fsl_mc_addr_translation_range *range = &(*ranges)[i]; - - range->mc_region_type = of_read_number(cell, 1); - range->start_mc_offset = of_read_number(cell + 1, - mc_addr_cells - 1); - cell += mc_addr_cells; - range->start_phys_addr = of_read_number(cell, paddr_cells); - cell += paddr_cells; - range->end_mc_offset = range->start_mc_offset + - of_read_number(cell, mc_size_cells); - - cell += mc_size_cells; - } - - return 0; -} - -/** - * fsl_mc_bus_probe - callback invoked when the root MC bus is being - * added - */ -static int fsl_mc_bus_probe(struct platform_device *pdev) -{ - struct fsl_mc_obj_desc obj_desc; - int error; - struct fsl_mc *mc; - struct fsl_mc_device *mc_bus_dev = NULL; - struct fsl_mc_io *mc_io = NULL; - int container_id; - phys_addr_t mc_portal_phys_addr; - u32 mc_portal_size; - struct mc_version mc_version; - struct resource res; - - mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); - if (!mc) - return -ENOMEM; - - platform_set_drvdata(pdev, mc); - - /* - * Get physical address of MC portal for the root DPRC: - */ - error = of_address_to_resource(pdev->dev.of_node, 0, &res); - if (error < 0) { - dev_err(&pdev->dev, - "of_address_to_resource() failed for %pOF\n", - pdev->dev.of_node); - return error; - } - - mc_portal_phys_addr = res.start; - mc_portal_size = resource_size(&res); - error = fsl_create_mc_io(&pdev->dev, mc_portal_phys_addr, - mc_portal_size, NULL, - FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, &mc_io); - if (error < 0) - return error; - - error = mc_get_version(mc_io, 0, &mc_version); - if (error != 0) { - dev_err(&pdev->dev, - "mc_get_version() failed with error %d\n", error); - goto error_cleanup_mc_io; - } - - dev_info(&pdev->dev, "MC firmware version: %u.%u.%u\n", - mc_version.major, mc_version.minor, mc_version.revision); - - error = get_mc_addr_translation_ranges(&pdev->dev, - &mc->translation_ranges, - &mc->num_translation_ranges); - if (error < 0) - goto error_cleanup_mc_io; - - error = dprc_get_container_id(mc_io, 0, &container_id); - if (error < 0) { - dev_err(&pdev->dev, - "dprc_get_container_id() failed: %d\n", error); - goto error_cleanup_mc_io; - } - - memset(&obj_desc, 0, sizeof(struct fsl_mc_obj_desc)); - error = dprc_get_api_version(mc_io, 0, - &obj_desc.ver_major, - &obj_desc.ver_minor); - if (error < 0) - goto error_cleanup_mc_io; - - obj_desc.vendor = FSL_MC_VENDOR_FREESCALE; - strcpy(obj_desc.type, "dprc"); - obj_desc.id = container_id; - obj_desc.irq_count = 1; - obj_desc.region_count = 0; - - error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev); - if (error < 0) - goto error_cleanup_mc_io; - - mc->root_mc_bus_dev = mc_bus_dev; - return 0; - -error_cleanup_mc_io: - fsl_destroy_mc_io(mc_io); - return error; -} - -/** - * fsl_mc_bus_remove - callback invoked when the root MC bus is being - * removed - */ -static int fsl_mc_bus_remove(struct platform_device *pdev) -{ - struct fsl_mc *mc = platform_get_drvdata(pdev); - - if (!fsl_mc_is_root_dprc(&mc->root_mc_bus_dev->dev)) - return -EINVAL; - - fsl_mc_device_remove(mc->root_mc_bus_dev); - - fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io); - mc->root_mc_bus_dev->mc_io = NULL; - - return 0; -} - -static const struct of_device_id fsl_mc_bus_match_table[] = { - {.compatible = "fsl,qoriq-mc",}, - {}, -}; - -MODULE_DEVICE_TABLE(of, fsl_mc_bus_match_table); - -static struct platform_driver fsl_mc_bus_driver = { - .driver = { - .name = "fsl_mc_bus", - .pm = NULL, - .of_match_table = fsl_mc_bus_match_table, - }, - .probe = fsl_mc_bus_probe, - .remove = fsl_mc_bus_remove, -}; - -static int __init fsl_mc_bus_driver_init(void) -{ - int error; - - error = bus_register(&fsl_mc_bus_type); - if (error < 0) { - pr_err("bus type registration failed: %d\n", error); - goto error_cleanup_cache; - } - - error = platform_driver_register(&fsl_mc_bus_driver); - if (error < 0) { - pr_err("platform_driver_register() failed: %d\n", error); - goto error_cleanup_bus; - } - - error = dprc_driver_init(); - if (error < 0) - goto error_cleanup_driver; - - error = fsl_mc_allocator_driver_init(); - if (error < 0) - goto error_cleanup_dprc_driver; - - return 0; - -error_cleanup_dprc_driver: - dprc_driver_exit(); - -error_cleanup_driver: - platform_driver_unregister(&fsl_mc_bus_driver); - -error_cleanup_bus: - bus_unregister(&fsl_mc_bus_type); - -error_cleanup_cache: - return error; -} -postcore_initcall(fsl_mc_bus_driver_init); diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c deleted file mode 100644 index 971ad87c584c..000000000000 --- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Freescale Management Complex (MC) bus driver MSI support - * - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. - * Author: German Rivera - * - */ - -#include -#include -#include -#include -#include -#include -#include "fsl-mc-private.h" - -#ifdef GENERIC_MSI_DOMAIN_OPS -/* - * Generate a unique ID identifying the interrupt (only used within the MSI - * irqdomain. Combine the icid with the interrupt index. - */ -static irq_hw_number_t fsl_mc_domain_calc_hwirq(struct fsl_mc_device *dev, - struct msi_desc *desc) -{ - /* - * Make the base hwirq value for ICID*10000 so it is readable - * as a decimal value in /proc/interrupts. - */ - return (irq_hw_number_t)(desc->fsl_mc.msi_index + (dev->icid * 10000)); -} - -static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg, - struct msi_desc *desc) -{ - arg->desc = desc; - arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), - desc); -} -#else -#define fsl_mc_msi_set_desc NULL -#endif - -static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info) -{ - struct msi_domain_ops *ops = info->ops; - - if (!ops) - return; - - /* - * set_desc should not be set by the caller - */ - if (!ops->set_desc) - ops->set_desc = fsl_mc_msi_set_desc; -} - -static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev, - struct fsl_mc_device_irq *mc_dev_irq) -{ - int error; - struct fsl_mc_device *owner_mc_dev = mc_dev_irq->mc_dev; - struct msi_desc *msi_desc = mc_dev_irq->msi_desc; - struct dprc_irq_cfg irq_cfg; - - /* - * msi_desc->msg.address is 0x0 when this function is invoked in - * the free_irq() code path. In this case, for the MC, we don't - * really need to "unprogram" the MSI, so we just return. - */ - if (msi_desc->msg.address_lo == 0x0 && msi_desc->msg.address_hi == 0x0) - return; - - if (!owner_mc_dev) - return; - - irq_cfg.paddr = ((u64)msi_desc->msg.address_hi << 32) | - msi_desc->msg.address_lo; - irq_cfg.val = msi_desc->msg.data; - irq_cfg.irq_num = msi_desc->irq; - - if (owner_mc_dev == mc_bus_dev) { - /* - * IRQ is for the mc_bus_dev's DPRC itself - */ - error = dprc_set_irq(mc_bus_dev->mc_io, - MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, - mc_bus_dev->mc_handle, - mc_dev_irq->dev_irq_index, - &irq_cfg); - if (error < 0) { - dev_err(&owner_mc_dev->dev, - "dprc_set_irq() failed: %d\n", error); - } - } else { - /* - * IRQ is for for a child device of mc_bus_dev - */ - error = dprc_set_obj_irq(mc_bus_dev->mc_io, - MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, - mc_bus_dev->mc_handle, - owner_mc_dev->obj_desc.type, - owner_mc_dev->obj_desc.id, - mc_dev_irq->dev_irq_index, - &irq_cfg); - if (error < 0) { - dev_err(&owner_mc_dev->dev, - "dprc_obj_set_irq() failed: %d\n", error); - } - } -} - -/* - * NOTE: This function is invoked with interrupts disabled - */ -static void fsl_mc_msi_write_msg(struct irq_data *irq_data, - struct msi_msg *msg) -{ - struct msi_desc *msi_desc = irq_data_get_msi_desc(irq_data); - struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev); - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - struct fsl_mc_device_irq *mc_dev_irq = - &mc_bus->irq_resources[msi_desc->fsl_mc.msi_index]; - - msi_desc->msg = *msg; - - /* - * Program the MSI (paddr, value) pair in the device: - */ - __fsl_mc_msi_write_msg(mc_bus_dev, mc_dev_irq); -} - -static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info) -{ - struct irq_chip *chip = info->chip; - - if (!chip) - return; - - /* - * irq_write_msi_msg should not be set by the caller - */ - if (!chip->irq_write_msi_msg) - chip->irq_write_msi_msg = fsl_mc_msi_write_msg; -} - -/** - * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain - * @np: Optional device-tree node of the interrupt controller - * @info: MSI domain info - * @parent: Parent irq domain - * - * Updates the domain and chip ops and creates a fsl-mc MSI - * interrupt domain. - * - * Returns: - * A domain pointer or NULL in case of failure. - */ -struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent) -{ - struct irq_domain *domain; - - if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) - fsl_mc_msi_update_dom_ops(info); - if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) - fsl_mc_msi_update_chip_ops(info); - - domain = msi_create_irq_domain(fwnode, info, parent); - if (domain) - irq_domain_update_bus_token(domain, DOMAIN_BUS_FSL_MC_MSI); - - return domain; -} - -int fsl_mc_find_msi_domain(struct device *mc_platform_dev, - struct irq_domain **mc_msi_domain) -{ - struct irq_domain *msi_domain; - struct device_node *mc_of_node = mc_platform_dev->of_node; - - msi_domain = of_msi_get_domain(mc_platform_dev, mc_of_node, - DOMAIN_BUS_FSL_MC_MSI); - if (!msi_domain) { - pr_err("Unable to find fsl-mc MSI domain for %pOF\n", - mc_of_node); - - return -ENOENT; - } - - *mc_msi_domain = msi_domain; - return 0; -} - -static void fsl_mc_msi_free_descs(struct device *dev) -{ - struct msi_desc *desc, *tmp; - - list_for_each_entry_safe(desc, tmp, dev_to_msi_list(dev), list) { - list_del(&desc->list); - free_msi_entry(desc); - } -} - -static int fsl_mc_msi_alloc_descs(struct device *dev, unsigned int irq_count) - -{ - unsigned int i; - int error; - struct msi_desc *msi_desc; - - for (i = 0; i < irq_count; i++) { - msi_desc = alloc_msi_entry(dev, 1, NULL); - if (!msi_desc) { - dev_err(dev, "Failed to allocate msi entry\n"); - error = -ENOMEM; - goto cleanup_msi_descs; - } - - msi_desc->fsl_mc.msi_index = i; - INIT_LIST_HEAD(&msi_desc->list); - list_add_tail(&msi_desc->list, dev_to_msi_list(dev)); - } - - return 0; - -cleanup_msi_descs: - fsl_mc_msi_free_descs(dev); - return error; -} - -int fsl_mc_msi_domain_alloc_irqs(struct device *dev, - unsigned int irq_count) -{ - struct irq_domain *msi_domain; - int error; - - if (!list_empty(dev_to_msi_list(dev))) - return -EINVAL; - - error = fsl_mc_msi_alloc_descs(dev, irq_count); - if (error < 0) - return error; - - msi_domain = dev_get_msi_domain(dev); - if (!msi_domain) { - error = -EINVAL; - goto cleanup_msi_descs; - } - - /* - * NOTE: Calling this function will trigger the invocation of the - * its_fsl_mc_msi_prepare() callback - */ - error = msi_domain_alloc_irqs(msi_domain, dev, irq_count); - - if (error) { - dev_err(dev, "Failed to allocate IRQs\n"); - goto cleanup_msi_descs; - } - - return 0; - -cleanup_msi_descs: - fsl_mc_msi_free_descs(dev); - return error; -} - -void fsl_mc_msi_domain_free_irqs(struct device *dev) -{ - struct irq_domain *msi_domain; - - msi_domain = dev_get_msi_domain(dev); - if (!msi_domain) - return; - - msi_domain_free_irqs(msi_domain, dev); - - if (list_empty(dev_to_msi_list(dev))) - return; - - fsl_mc_msi_free_descs(dev); -} diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-private.h b/drivers/staging/fsl-mc/bus/fsl-mc-private.h deleted file mode 100644 index 83b89d6241f2..000000000000 --- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h +++ /dev/null @@ -1,475 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Freescale Management Complex (MC) bus private declarations - * - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - */ -#ifndef _FSL_MC_PRIVATE_H_ -#define _FSL_MC_PRIVATE_H_ - -#include "../include/mc.h" -#include - -/* - * Data Path Management Complex (DPMNG) General API - */ - -/* DPMNG command versioning */ -#define DPMNG_CMD_BASE_VERSION 1 -#define DPMNG_CMD_ID_OFFSET 4 - -#define DPMNG_CMD(id) (((id) << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION) - -/* DPMNG command IDs */ -#define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831) - -struct dpmng_rsp_get_version { - __le32 revision; - __le32 version_major; - __le32 version_minor; -}; - -/* - * Data Path Management Command Portal (DPMCP) API - */ - -/* Minimal supported DPMCP Version */ -#define DPMCP_MIN_VER_MAJOR 3 -#define DPMCP_MIN_VER_MINOR 0 - -/* DPMCP command versioning */ -#define DPMCP_CMD_BASE_VERSION 1 -#define DPMCP_CMD_ID_OFFSET 4 - -#define DPMCP_CMD(id) (((id) << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION) - -/* DPMCP command IDs */ -#define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800) -#define DPMCP_CMDID_OPEN DPMCP_CMD(0x80b) -#define DPMCP_CMDID_RESET DPMCP_CMD(0x005) - -struct dpmcp_cmd_open { - __le32 dpmcp_id; -}; - -/* - * Initialization and runtime control APIs for DPMCP - */ -int dpmcp_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int dpmcp_id, - u16 *token); - -int dpmcp_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -int dpmcp_reset(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/* - * Data Path Resource Container (DPRC) API - */ - -/* Minimal supported DPRC Version */ -#define DPRC_MIN_VER_MAJOR 6 -#define DPRC_MIN_VER_MINOR 0 - -/* DPRC command versioning */ -#define DPRC_CMD_BASE_VERSION 1 -#define DPRC_CMD_ID_OFFSET 4 - -#define DPRC_CMD(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION) - -/* DPRC command IDs */ -#define DPRC_CMDID_CLOSE DPRC_CMD(0x800) -#define DPRC_CMDID_OPEN DPRC_CMD(0x805) -#define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05) - -#define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004) - -#define DPRC_CMDID_SET_IRQ DPRC_CMD(0x010) -#define DPRC_CMDID_SET_IRQ_ENABLE DPRC_CMD(0x012) -#define DPRC_CMDID_SET_IRQ_MASK DPRC_CMD(0x014) -#define DPRC_CMDID_GET_IRQ_STATUS DPRC_CMD(0x016) -#define DPRC_CMDID_CLEAR_IRQ_STATUS DPRC_CMD(0x017) - -#define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830) -#define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159) -#define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A) -#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E) -#define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F) - -struct dprc_cmd_open { - __le32 container_id; -}; - -struct dprc_cmd_set_irq { - /* cmd word 0 */ - __le32 irq_val; - u8 irq_index; - u8 pad[3]; - /* cmd word 1 */ - __le64 irq_addr; - /* cmd word 2 */ - __le32 irq_num; -}; - -#define DPRC_ENABLE 0x1 - -struct dprc_cmd_set_irq_enable { - u8 enable; - u8 pad[3]; - u8 irq_index; -}; - -struct dprc_cmd_set_irq_mask { - __le32 mask; - u8 irq_index; -}; - -struct dprc_cmd_get_irq_status { - __le32 status; - u8 irq_index; -}; - -struct dprc_rsp_get_irq_status { - __le32 status; -}; - -struct dprc_cmd_clear_irq_status { - __le32 status; - u8 irq_index; -}; - -struct dprc_rsp_get_attributes { - /* response word 0 */ - __le32 container_id; - __le16 icid; - __le16 pad; - /* response word 1 */ - __le32 options; - __le32 portal_id; -}; - -struct dprc_rsp_get_obj_count { - __le32 pad; - __le32 obj_count; -}; - -struct dprc_cmd_get_obj { - __le32 obj_index; -}; - -struct dprc_rsp_get_obj { - /* response word 0 */ - __le32 pad0; - __le32 id; - /* response word 1 */ - __le16 vendor; - u8 irq_count; - u8 region_count; - __le32 state; - /* response word 2 */ - __le16 version_major; - __le16 version_minor; - __le16 flags; - __le16 pad1; - /* response word 3-4 */ - u8 type[16]; - /* response word 5-6 */ - u8 label[16]; -}; - -struct dprc_cmd_get_obj_region { - /* cmd word 0 */ - __le32 obj_id; - __le16 pad0; - u8 region_index; - u8 pad1; - /* cmd word 1-2 */ - __le64 pad2[2]; - /* cmd word 3-4 */ - u8 obj_type[16]; -}; - -struct dprc_rsp_get_obj_region { - /* response word 0 */ - __le64 pad; - /* response word 1 */ - __le64 base_addr; - /* response word 2 */ - __le32 size; -}; - -struct dprc_cmd_set_obj_irq { - /* cmd word 0 */ - __le32 irq_val; - u8 irq_index; - u8 pad[3]; - /* cmd word 1 */ - __le64 irq_addr; - /* cmd word 2 */ - __le32 irq_num; - __le32 obj_id; - /* cmd word 3-4 */ - u8 obj_type[16]; -}; - -/* - * DPRC API for managing and querying DPAA resources - */ -int dprc_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int container_id, - u16 *token); - -int dprc_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/* DPRC IRQ events */ - -/* IRQ event - Indicates that a new object added to the container */ -#define DPRC_IRQ_EVENT_OBJ_ADDED 0x00000001 -/* IRQ event - Indicates that an object was removed from the container */ -#define DPRC_IRQ_EVENT_OBJ_REMOVED 0x00000002 -/* - * IRQ event - Indicates that one of the descendant containers that opened by - * this container is destroyed - */ -#define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010 - -/* - * IRQ event - Indicates that on one of the container's opened object is - * destroyed - */ -#define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020 - -/* Irq event - Indicates that object is created at the container */ -#define DPRC_IRQ_EVENT_OBJ_CREATED 0x00000040 - -/** - * struct dprc_irq_cfg - IRQ configuration - * @paddr: Address that must be written to signal a message-based interrupt - * @val: Value to write into irq_addr address - * @irq_num: A user defined number associated with this IRQ - */ -struct dprc_irq_cfg { - phys_addr_t paddr; - u32 val; - int irq_num; -}; - -int dprc_set_irq(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - struct dprc_irq_cfg *irq_cfg); - -int dprc_set_irq_enable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u8 en); - -int dprc_set_irq_mask(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 mask); - -int dprc_get_irq_status(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 *status); - -int dprc_clear_irq_status(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u8 irq_index, - u32 status); - -/** - * struct dprc_attributes - Container attributes - * @container_id: Container's ID - * @icid: Container's ICID - * @portal_id: Container's portal ID - * @options: Container's options as set at container's creation - */ -struct dprc_attributes { - int container_id; - u16 icid; - int portal_id; - u64 options; -}; - -int dprc_get_attributes(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dprc_attributes *attributes); - -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - int *obj_count); - -int dprc_get_obj(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - int obj_index, - struct fsl_mc_obj_desc *obj_desc); - -int dprc_set_obj_irq(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - char *obj_type, - int obj_id, - u8 irq_index, - struct dprc_irq_cfg *irq_cfg); - -/* Region flags */ -/* Cacheable - Indicates that region should be mapped as cacheable */ -#define DPRC_REGION_CACHEABLE 0x00000001 - -/** - * enum dprc_region_type - Region type - * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region - * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region - */ -enum dprc_region_type { - DPRC_REGION_TYPE_MC_PORTAL, - DPRC_REGION_TYPE_QBMAN_PORTAL -}; - -/** - * struct dprc_region_desc - Mappable region descriptor - * @base_offset: Region offset from region's base address. - * For DPMCP and DPRC objects, region base is offset from SoC MC portals - * base address; For DPIO, region base is offset from SoC QMan portals - * base address - * @size: Region size (in bytes) - * @flags: Region attributes - * @type: Portal region type - */ -struct dprc_region_desc { - u32 base_offset; - u32 size; - u32 flags; - enum dprc_region_type type; -}; - -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - char *obj_type, - int obj_id, - u8 region_index, - struct dprc_region_desc *region_desc); - -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); - -int dprc_get_container_id(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int *container_id); - -/** - * Maximum number of total IRQs that can be pre-allocated for an MC bus' - * IRQ pool - */ -#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS 256 - -/** - * struct fsl_mc_resource_pool - Pool of MC resources of a given - * type - * @type: type of resources in the pool - * @max_count: maximum number of resources in the pool - * @free_count: number of free resources in the pool - * @mutex: mutex to serialize access to the pool's free list - * @free_list: anchor node of list of free resources in the pool - * @mc_bus: pointer to the MC bus that owns this resource pool - */ -struct fsl_mc_resource_pool { - enum fsl_mc_pool_type type; - int max_count; - int free_count; - struct mutex mutex; /* serializes access to free_list */ - struct list_head free_list; - struct fsl_mc_bus *mc_bus; -}; - -/** - * struct fsl_mc_bus - logical bus that corresponds to a physical DPRC - * @mc_dev: fsl-mc device for the bus device itself. - * @resource_pools: array of resource pools (one pool per resource type) - * for this MC bus. These resources represent allocatable entities - * from the physical DPRC. - * @irq_resources: Pointer to array of IRQ objects for the IRQ pool - * @scan_mutex: Serializes bus scanning - * @dprc_attr: DPRC attributes - */ -struct fsl_mc_bus { - struct fsl_mc_device mc_dev; - struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; - struct fsl_mc_device_irq *irq_resources; - struct mutex scan_mutex; /* serializes bus scanning */ - struct dprc_attributes dprc_attr; -}; - -#define to_fsl_mc_bus(_mc_dev) \ - container_of(_mc_dev, struct fsl_mc_bus, mc_dev) - -int __must_check fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, - struct fsl_mc_io *mc_io, - struct device *parent_dev, - struct fsl_mc_device **new_mc_dev); - -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev); - -int __init dprc_driver_init(void); - -void dprc_driver_exit(void); - -int __init fsl_mc_allocator_driver_init(void); - -void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev); - -void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev); - -int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, - enum fsl_mc_pool_type pool_type, - struct fsl_mc_resource - **new_resource); - -void fsl_mc_resource_free(struct fsl_mc_resource *resource); - -int fsl_mc_msi_domain_alloc_irqs(struct device *dev, - unsigned int irq_count); - -void fsl_mc_msi_domain_free_irqs(struct device *dev); - -int fsl_mc_find_msi_domain(struct device *mc_platform_dev, - struct irq_domain **mc_msi_domain); - -int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, - unsigned int irq_count); - -void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus); - -int __must_check fsl_create_mc_io(struct device *dev, - phys_addr_t mc_portal_phys_addr, - u32 mc_portal_size, - struct fsl_mc_device *dpmcp_dev, - u32 flags, struct fsl_mc_io **new_mc_io); - -void fsl_destroy_mc_io(struct fsl_mc_io *mc_io); - -bool fsl_mc_is_root_dprc(struct device *dev); - -#endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c index 5064d5ddf581..b365fbb00fd3 100644 --- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c +++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c @@ -13,7 +13,7 @@ #include #include #include -#include "../include/mc.h" +#include static struct irq_chip its_msi_irq_chip = { .name = "ITS-fMSI", diff --git a/drivers/staging/fsl-mc/bus/mc-io.c b/drivers/staging/fsl-mc/bus/mc-io.c deleted file mode 100644 index 7e6fb360ef12..000000000000 --- a/drivers/staging/fsl-mc/bus/mc-io.c +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ - -#include -#include "../include/mc.h" - -#include "fsl-mc-private.h" - -static int fsl_mc_io_set_dpmcp(struct fsl_mc_io *mc_io, - struct fsl_mc_device *dpmcp_dev) -{ - int error; - - if (mc_io->dpmcp_dev) - return -EINVAL; - - if (dpmcp_dev->mc_io) - return -EINVAL; - - error = dpmcp_open(mc_io, - 0, - dpmcp_dev->obj_desc.id, - &dpmcp_dev->mc_handle); - if (error < 0) - return error; - - mc_io->dpmcp_dev = dpmcp_dev; - dpmcp_dev->mc_io = mc_io; - return 0; -} - -static void fsl_mc_io_unset_dpmcp(struct fsl_mc_io *mc_io) -{ - int error; - struct fsl_mc_device *dpmcp_dev = mc_io->dpmcp_dev; - - error = dpmcp_close(mc_io, - 0, - dpmcp_dev->mc_handle); - if (error < 0) { - dev_err(&dpmcp_dev->dev, "dpmcp_close() failed: %d\n", - error); - } - - mc_io->dpmcp_dev = NULL; - dpmcp_dev->mc_io = NULL; -} - -/** - * Creates an MC I/O object - * - * @dev: device to be associated with the MC I/O object - * @mc_portal_phys_addr: physical address of the MC portal to use - * @mc_portal_size: size in bytes of the MC portal - * @dpmcp-dev: Pointer to the DPMCP object associated with this MC I/O - * object or NULL if none. - * @flags: flags for the new MC I/O object - * @new_mc_io: Area to return pointer to newly created MC I/O object - * - * Returns '0' on Success; Error code otherwise. - */ -int __must_check fsl_create_mc_io(struct device *dev, - phys_addr_t mc_portal_phys_addr, - u32 mc_portal_size, - struct fsl_mc_device *dpmcp_dev, - u32 flags, struct fsl_mc_io **new_mc_io) -{ - int error; - struct fsl_mc_io *mc_io; - void __iomem *mc_portal_virt_addr; - struct resource *res; - - mc_io = devm_kzalloc(dev, sizeof(*mc_io), GFP_KERNEL); - if (!mc_io) - return -ENOMEM; - - mc_io->dev = dev; - mc_io->flags = flags; - mc_io->portal_phys_addr = mc_portal_phys_addr; - mc_io->portal_size = mc_portal_size; - if (flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) - spin_lock_init(&mc_io->spinlock); - else - mutex_init(&mc_io->mutex); - - res = devm_request_mem_region(dev, - mc_portal_phys_addr, - mc_portal_size, - "mc_portal"); - if (!res) { - dev_err(dev, - "devm_request_mem_region failed for MC portal %pa\n", - &mc_portal_phys_addr); - return -EBUSY; - } - - mc_portal_virt_addr = devm_ioremap_nocache(dev, - mc_portal_phys_addr, - mc_portal_size); - if (!mc_portal_virt_addr) { - dev_err(dev, - "devm_ioremap_nocache failed for MC portal %pa\n", - &mc_portal_phys_addr); - return -ENXIO; - } - - mc_io->portal_virt_addr = mc_portal_virt_addr; - if (dpmcp_dev) { - error = fsl_mc_io_set_dpmcp(mc_io, dpmcp_dev); - if (error < 0) - goto error_destroy_mc_io; - } - - *new_mc_io = mc_io; - return 0; - -error_destroy_mc_io: - fsl_destroy_mc_io(mc_io); - return error; -} - -/** - * Destroys an MC I/O object - * - * @mc_io: MC I/O object to destroy - */ -void fsl_destroy_mc_io(struct fsl_mc_io *mc_io) -{ - struct fsl_mc_device *dpmcp_dev = mc_io->dpmcp_dev; - - if (dpmcp_dev) - fsl_mc_io_unset_dpmcp(mc_io); - - devm_iounmap(mc_io->dev, mc_io->portal_virt_addr); - devm_release_mem_region(mc_io->dev, - mc_io->portal_phys_addr, - mc_io->portal_size); - - mc_io->portal_virt_addr = NULL; - devm_kfree(mc_io->dev, mc_io); -} - -/** - * fsl_mc_portal_allocate - Allocates an MC portal - * - * @mc_dev: MC device for which the MC portal is to be allocated - * @mc_io_flags: Flags for the fsl_mc_io object that wraps the allocated - * MC portal. - * @new_mc_io: Pointer to area where the pointer to the fsl_mc_io object - * that wraps the allocated MC portal is to be returned - * - * This function allocates an MC portal from the device's parent DPRC, - * from the corresponding MC bus' pool of MC portals and wraps - * it in a new fsl_mc_io object. If 'mc_dev' is a DPRC itself, the - * portal is allocated from its own MC bus. - */ -int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev, - u16 mc_io_flags, - struct fsl_mc_io **new_mc_io) -{ - struct fsl_mc_device *mc_bus_dev; - struct fsl_mc_bus *mc_bus; - phys_addr_t mc_portal_phys_addr; - size_t mc_portal_size; - struct fsl_mc_device *dpmcp_dev; - int error = -EINVAL; - struct fsl_mc_resource *resource = NULL; - struct fsl_mc_io *mc_io = NULL; - - if (mc_dev->flags & FSL_MC_IS_DPRC) { - mc_bus_dev = mc_dev; - } else { - if (!dev_is_fsl_mc(mc_dev->dev.parent)) - return error; - - mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); - } - - mc_bus = to_fsl_mc_bus(mc_bus_dev); - *new_mc_io = NULL; - error = fsl_mc_resource_allocate(mc_bus, FSL_MC_POOL_DPMCP, &resource); - if (error < 0) - return error; - - error = -EINVAL; - dpmcp_dev = resource->data; - - if (dpmcp_dev->obj_desc.ver_major < DPMCP_MIN_VER_MAJOR || - (dpmcp_dev->obj_desc.ver_major == DPMCP_MIN_VER_MAJOR && - dpmcp_dev->obj_desc.ver_minor < DPMCP_MIN_VER_MINOR)) { - dev_err(&dpmcp_dev->dev, - "ERROR: Version %d.%d of DPMCP not supported.\n", - dpmcp_dev->obj_desc.ver_major, - dpmcp_dev->obj_desc.ver_minor); - error = -ENOTSUPP; - goto error_cleanup_resource; - } - - mc_portal_phys_addr = dpmcp_dev->regions[0].start; - mc_portal_size = resource_size(dpmcp_dev->regions); - - error = fsl_create_mc_io(&mc_bus_dev->dev, - mc_portal_phys_addr, - mc_portal_size, dpmcp_dev, - mc_io_flags, &mc_io); - if (error < 0) - goto error_cleanup_resource; - - *new_mc_io = mc_io; - return 0; - -error_cleanup_resource: - fsl_mc_resource_free(resource); - return error; -} -EXPORT_SYMBOL_GPL(fsl_mc_portal_allocate); - -/** - * fsl_mc_portal_free - Returns an MC portal to the pool of free MC portals - * of a given MC bus - * - * @mc_io: Pointer to the fsl_mc_io object that wraps the MC portal to free - */ -void fsl_mc_portal_free(struct fsl_mc_io *mc_io) -{ - struct fsl_mc_device *dpmcp_dev; - struct fsl_mc_resource *resource; - - /* - * Every mc_io obtained by calling fsl_mc_portal_allocate() is supposed - * to have a DPMCP object associated with. - */ - dpmcp_dev = mc_io->dpmcp_dev; - - resource = dpmcp_dev->resource; - if (!resource || resource->type != FSL_MC_POOL_DPMCP) - return; - - if (resource->data != dpmcp_dev) - return; - - fsl_destroy_mc_io(mc_io); - fsl_mc_resource_free(resource); -} -EXPORT_SYMBOL_GPL(fsl_mc_portal_free); - -/** - * fsl_mc_portal_reset - Resets the dpmcp object for a given fsl_mc_io object - * - * @mc_io: Pointer to the fsl_mc_io object that wraps the MC portal to free - */ -int fsl_mc_portal_reset(struct fsl_mc_io *mc_io) -{ - int error; - struct fsl_mc_device *dpmcp_dev = mc_io->dpmcp_dev; - - error = dpmcp_reset(mc_io, 0, dpmcp_dev->mc_handle); - if (error < 0) { - dev_err(&dpmcp_dev->dev, "dpmcp_reset() failed: %d\n", error); - return error; - } - - return 0; -} -EXPORT_SYMBOL_GPL(fsl_mc_portal_reset); diff --git a/drivers/staging/fsl-mc/bus/mc-sys.c b/drivers/staging/fsl-mc/bus/mc-sys.c deleted file mode 100644 index f09d75d9a976..000000000000 --- a/drivers/staging/fsl-mc/bus/mc-sys.c +++ /dev/null @@ -1,296 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - * I/O services to send MC commands to the MC hardware - * - */ - -#include -#include -#include -#include -#include -#include -#include "../include/mc.h" - -#include "fsl-mc-private.h" - -/** - * Timeout in milliseconds to wait for the completion of an MC command - */ -#define MC_CMD_COMPLETION_TIMEOUT_MS 500 - -/* - * usleep_range() min and max values used to throttle down polling - * iterations while waiting for MC command completion - */ -#define MC_CMD_COMPLETION_POLLING_MIN_SLEEP_USECS 10 -#define MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS 500 - -static enum mc_cmd_status mc_cmd_hdr_read_status(struct mc_command *cmd) -{ - struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; - - return (enum mc_cmd_status)hdr->status; -} - -static u16 mc_cmd_hdr_read_cmdid(struct mc_command *cmd) -{ - struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; - u16 cmd_id = le16_to_cpu(hdr->cmd_id); - - return cmd_id; -} - -static int mc_status_to_error(enum mc_cmd_status status) -{ - static const int mc_status_to_error_map[] = { - [MC_CMD_STATUS_OK] = 0, - [MC_CMD_STATUS_AUTH_ERR] = -EACCES, - [MC_CMD_STATUS_NO_PRIVILEGE] = -EPERM, - [MC_CMD_STATUS_DMA_ERR] = -EIO, - [MC_CMD_STATUS_CONFIG_ERR] = -ENXIO, - [MC_CMD_STATUS_TIMEOUT] = -ETIMEDOUT, - [MC_CMD_STATUS_NO_RESOURCE] = -ENAVAIL, - [MC_CMD_STATUS_NO_MEMORY] = -ENOMEM, - [MC_CMD_STATUS_BUSY] = -EBUSY, - [MC_CMD_STATUS_UNSUPPORTED_OP] = -ENOTSUPP, - [MC_CMD_STATUS_INVALID_STATE] = -ENODEV, - }; - - if ((u32)status >= ARRAY_SIZE(mc_status_to_error_map)) - return -EINVAL; - - return mc_status_to_error_map[status]; -} - -static const char *mc_status_to_string(enum mc_cmd_status status) -{ - static const char *const status_strings[] = { - [MC_CMD_STATUS_OK] = "Command completed successfully", - [MC_CMD_STATUS_READY] = "Command ready to be processed", - [MC_CMD_STATUS_AUTH_ERR] = "Authentication error", - [MC_CMD_STATUS_NO_PRIVILEGE] = "No privilege", - [MC_CMD_STATUS_DMA_ERR] = "DMA or I/O error", - [MC_CMD_STATUS_CONFIG_ERR] = "Configuration error", - [MC_CMD_STATUS_TIMEOUT] = "Operation timed out", - [MC_CMD_STATUS_NO_RESOURCE] = "No resources", - [MC_CMD_STATUS_NO_MEMORY] = "No memory available", - [MC_CMD_STATUS_BUSY] = "Device is busy", - [MC_CMD_STATUS_UNSUPPORTED_OP] = "Unsupported operation", - [MC_CMD_STATUS_INVALID_STATE] = "Invalid state" - }; - - if ((unsigned int)status >= ARRAY_SIZE(status_strings)) - return "Unknown MC error"; - - return status_strings[status]; -} - -/** - * mc_write_command - writes a command to a Management Complex (MC) portal - * - * @portal: pointer to an MC portal - * @cmd: pointer to a filled command - */ -static inline void mc_write_command(struct mc_command __iomem *portal, - struct mc_command *cmd) -{ - int i; - - /* copy command parameters into the portal */ - for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) - /* - * Data is already in the expected LE byte-order. Do an - * extra LE -> CPU conversion so that the CPU -> LE done in - * the device io write api puts it back in the right order. - */ - writeq_relaxed(le64_to_cpu(cmd->params[i]), &portal->params[i]); - - /* submit the command by writing the header */ - writeq(le64_to_cpu(cmd->header), &portal->header); -} - -/** - * mc_read_response - reads the response for the last MC command from a - * Management Complex (MC) portal - * - * @portal: pointer to an MC portal - * @resp: pointer to command response buffer - * - * Returns MC_CMD_STATUS_OK on Success; Error code otherwise. - */ -static inline enum mc_cmd_status mc_read_response(struct mc_command __iomem * - portal, - struct mc_command *resp) -{ - int i; - enum mc_cmd_status status; - - /* Copy command response header from MC portal: */ - resp->header = cpu_to_le64(readq_relaxed(&portal->header)); - status = mc_cmd_hdr_read_status(resp); - if (status != MC_CMD_STATUS_OK) - return status; - - /* Copy command response data from MC portal: */ - for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) - /* - * Data is expected to be in LE byte-order. Do an - * extra CPU -> LE to revert the LE -> CPU done in - * the device io read api. - */ - resp->params[i] = - cpu_to_le64(readq_relaxed(&portal->params[i])); - - return status; -} - -/** - * Waits for the completion of an MC command doing preemptible polling. - * uslepp_range() is called between polling iterations. - * - * @mc_io: MC I/O object to be used - * @cmd: command buffer to receive MC response - * @mc_status: MC command completion status - */ -static int mc_polling_wait_preemptible(struct fsl_mc_io *mc_io, - struct mc_command *cmd, - enum mc_cmd_status *mc_status) -{ - enum mc_cmd_status status; - unsigned long jiffies_until_timeout = - jiffies + msecs_to_jiffies(MC_CMD_COMPLETION_TIMEOUT_MS); - - /* - * Wait for response from the MC hardware: - */ - for (;;) { - status = mc_read_response(mc_io->portal_virt_addr, cmd); - if (status != MC_CMD_STATUS_READY) - break; - - /* - * TODO: When MC command completion interrupts are supported - * call wait function here instead of usleep_range() - */ - usleep_range(MC_CMD_COMPLETION_POLLING_MIN_SLEEP_USECS, - MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - - if (time_after_eq(jiffies, jiffies_until_timeout)) { - dev_dbg(mc_io->dev, - "MC command timed out (portal: %pa, dprc handle: %#x, command: %#x)\n", - &mc_io->portal_phys_addr, - (unsigned int)mc_cmd_hdr_read_token(cmd), - (unsigned int)mc_cmd_hdr_read_cmdid(cmd)); - - return -ETIMEDOUT; - } - } - - *mc_status = status; - return 0; -} - -/** - * Waits for the completion of an MC command doing atomic polling. - * udelay() is called between polling iterations. - * - * @mc_io: MC I/O object to be used - * @cmd: command buffer to receive MC response - * @mc_status: MC command completion status - */ -static int mc_polling_wait_atomic(struct fsl_mc_io *mc_io, - struct mc_command *cmd, - enum mc_cmd_status *mc_status) -{ - enum mc_cmd_status status; - unsigned long timeout_usecs = MC_CMD_COMPLETION_TIMEOUT_MS * 1000; - - BUILD_BUG_ON((MC_CMD_COMPLETION_TIMEOUT_MS * 1000) % - MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS != 0); - - for (;;) { - status = mc_read_response(mc_io->portal_virt_addr, cmd); - if (status != MC_CMD_STATUS_READY) - break; - - udelay(MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS; - if (timeout_usecs == 0) { - dev_dbg(mc_io->dev, - "MC command timed out (portal: %pa, dprc handle: %#x, command: %#x)\n", - &mc_io->portal_phys_addr, - (unsigned int)mc_cmd_hdr_read_token(cmd), - (unsigned int)mc_cmd_hdr_read_cmdid(cmd)); - - return -ETIMEDOUT; - } - } - - *mc_status = status; - return 0; -} - -/** - * Sends a command to the MC device using the given MC I/O object - * - * @mc_io: MC I/O object to be used - * @cmd: command to be sent - * - * Returns '0' on Success; Error code otherwise. - */ -int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd) -{ - int error; - enum mc_cmd_status status; - unsigned long irq_flags = 0; - - if (in_irq() && !(mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL)) - return -EINVAL; - - if (mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) - spin_lock_irqsave(&mc_io->spinlock, irq_flags); - else - mutex_lock(&mc_io->mutex); - - /* - * Send command to the MC hardware: - */ - mc_write_command(mc_io->portal_virt_addr, cmd); - - /* - * Wait for response from the MC hardware: - */ - if (!(mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL)) - error = mc_polling_wait_preemptible(mc_io, cmd, &status); - else - error = mc_polling_wait_atomic(mc_io, cmd, &status); - - if (error < 0) - goto common_exit; - - if (status != MC_CMD_STATUS_OK) { - dev_dbg(mc_io->dev, - "MC command failed: portal: %pa, dprc handle: %#x, command: %#x, status: %s (%#x)\n", - &mc_io->portal_phys_addr, - (unsigned int)mc_cmd_hdr_read_token(cmd), - (unsigned int)mc_cmd_hdr_read_cmdid(cmd), - mc_status_to_string(status), - (unsigned int)status); - - error = mc_status_to_error(status); - goto common_exit; - } - - error = 0; -common_exit: - if (mc_io->flags & FSL_MC_IO_ATOMIC_CONTEXT_PORTAL) - spin_unlock_irqrestore(&mc_io->spinlock, irq_flags); - else - mutex_unlock(&mc_io->mutex); - - return error; -} -EXPORT_SYMBOL_GPL(mc_send_command); diff --git a/drivers/staging/fsl-mc/include/mc.h b/drivers/staging/fsl-mc/include/mc.h deleted file mode 100644 index 765ba41f5987..000000000000 --- a/drivers/staging/fsl-mc/include/mc.h +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Freescale Management Complex (MC) bus public interface - * - * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * Author: German Rivera - * - */ -#ifndef _FSL_MC_H_ -#define _FSL_MC_H_ - -#include -#include -#include - -#define FSL_MC_VENDOR_FREESCALE 0x1957 - -struct irq_domain; -struct msi_domain_info; - -struct fsl_mc_device; -struct fsl_mc_io; - -/** - * struct fsl_mc_driver - MC object device driver object - * @driver: Generic device driver - * @match_id_table: table of supported device matching Ids - * @probe: Function called when a device is added - * @remove: Function called when a device is removed - * @shutdown: Function called at shutdown time to quiesce the device - * @suspend: Function called when a device is stopped - * @resume: Function called when a device is resumed - * - * Generic DPAA device driver object for device drivers that are registered - * with a DPRC bus. This structure is to be embedded in each device-specific - * driver structure. - */ -struct fsl_mc_driver { - struct device_driver driver; - const struct fsl_mc_device_id *match_id_table; - int (*probe)(struct fsl_mc_device *dev); - int (*remove)(struct fsl_mc_device *dev); - void (*shutdown)(struct fsl_mc_device *dev); - int (*suspend)(struct fsl_mc_device *dev, pm_message_t state); - int (*resume)(struct fsl_mc_device *dev); -}; - -#define to_fsl_mc_driver(_drv) \ - container_of(_drv, struct fsl_mc_driver, driver) - -/** - * enum fsl_mc_pool_type - Types of allocatable MC bus resources - * - * Entries in these enum are used as indices in the array of resource - * pools of an fsl_mc_bus object. - */ -enum fsl_mc_pool_type { - FSL_MC_POOL_DPMCP = 0x0, /* corresponds to "dpmcp" in the MC */ - FSL_MC_POOL_DPBP, /* corresponds to "dpbp" in the MC */ - FSL_MC_POOL_DPCON, /* corresponds to "dpcon" in the MC */ - FSL_MC_POOL_IRQ, - - /* - * NOTE: New resource pool types must be added before this entry - */ - FSL_MC_NUM_POOL_TYPES -}; - -/** - * struct fsl_mc_resource - MC generic resource - * @type: type of resource - * @id: unique MC resource Id within the resources of the same type - * @data: pointer to resource-specific data if the resource is currently - * allocated, or NULL if the resource is not currently allocated. - * @parent_pool: pointer to the parent resource pool from which this - * resource is allocated from. - * @node: Node in the free list of the corresponding resource pool - * - * NOTE: This structure is to be embedded as a field of specific - * MC resource structures. - */ -struct fsl_mc_resource { - enum fsl_mc_pool_type type; - s32 id; - void *data; - struct fsl_mc_resource_pool *parent_pool; - struct list_head node; -}; - -/** - * struct fsl_mc_device_irq - MC object device message-based interrupt - * @msi_desc: pointer to MSI descriptor allocated by fsl_mc_msi_alloc_descs() - * @mc_dev: MC object device that owns this interrupt - * @dev_irq_index: device-relative IRQ index - * @resource: MC generic resource associated with the interrupt - */ -struct fsl_mc_device_irq { - struct msi_desc *msi_desc; - struct fsl_mc_device *mc_dev; - u8 dev_irq_index; - struct fsl_mc_resource resource; -}; - -#define to_fsl_mc_irq(_mc_resource) \ - container_of(_mc_resource, struct fsl_mc_device_irq, resource) - -/* Opened state - Indicates that an object is open by at least one owner */ -#define FSL_MC_OBJ_STATE_OPEN 0x00000001 -/* Plugged state - Indicates that the object is plugged */ -#define FSL_MC_OBJ_STATE_PLUGGED 0x00000002 - -/** - * Shareability flag - Object flag indicating no memory shareability. - * the object generates memory accesses that are non coherent with other - * masters; - * user is responsible for proper memory handling through IOMMU configuration. - */ -#define FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 - -/** - * struct fsl_mc_obj_desc - Object descriptor - * @type: Type of object: NULL terminated string - * @id: ID of logical object resource - * @vendor: Object vendor identifier - * @ver_major: Major version number - * @ver_minor: Minor version number - * @irq_count: Number of interrupts supported by the object - * @region_count: Number of mappable regions supported by the object - * @state: Object state: combination of FSL_MC_OBJ_STATE_ states - * @label: Object label: NULL terminated string - * @flags: Object's flags - */ -struct fsl_mc_obj_desc { - char type[16]; - int id; - u16 vendor; - u16 ver_major; - u16 ver_minor; - u8 irq_count; - u8 region_count; - u32 state; - char label[16]; - u16 flags; -}; - -/** - * Bit masks for a MC object device (struct fsl_mc_device) flags - */ -#define FSL_MC_IS_DPRC 0x0001 - -/** - * struct fsl_mc_device - MC object device object - * @dev: Linux driver model device object - * @dma_mask: Default DMA mask - * @flags: MC object device flags - * @icid: Isolation context ID for the device - * @mc_handle: MC handle for the corresponding MC object opened - * @mc_io: Pointer to MC IO object assigned to this device or - * NULL if none. - * @obj_desc: MC description of the DPAA device - * @regions: pointer to array of MMIO region entries - * @irqs: pointer to array of pointers to interrupts allocated to this device - * @resource: generic resource associated with this MC object device, if any. - * - * Generic device object for MC object devices that are "attached" to a - * MC bus. - * - * NOTES: - * - For a non-DPRC object its icid is the same as its parent DPRC's icid. - * - The SMMU notifier callback gets invoked after device_add() has been - * called for an MC object device, but before the device-specific probe - * callback gets called. - * - DP_OBJ_DPRC objects are the only MC objects that have built-in MC - * portals. For all other MC objects, their device drivers are responsible for - * allocating MC portals for them by calling fsl_mc_portal_allocate(). - * - Some types of MC objects (e.g., DP_OBJ_DPBP, DP_OBJ_DPCON) are - * treated as resources that can be allocated/deallocated from the - * corresponding resource pool in the object's parent DPRC, using the - * fsl_mc_object_allocate()/fsl_mc_object_free() functions. These MC objects - * are known as "allocatable" objects. For them, the corresponding - * fsl_mc_device's 'resource' points to the associated resource object. - * For MC objects that are not allocatable (e.g., DP_OBJ_DPRC, DP_OBJ_DPNI), - * 'resource' is NULL. - */ -struct fsl_mc_device { - struct device dev; - u64 dma_mask; - u16 flags; - u16 icid; - u16 mc_handle; - struct fsl_mc_io *mc_io; - struct fsl_mc_obj_desc obj_desc; - struct resource *regions; - struct fsl_mc_device_irq **irqs; - struct fsl_mc_resource *resource; -}; - -#define to_fsl_mc_device(_dev) \ - container_of(_dev, struct fsl_mc_device, dev) - -#define MC_CMD_NUM_OF_PARAMS 7 - -struct mc_cmd_header { - u8 src_id; - u8 flags_hw; - u8 status; - u8 flags_sw; - __le16 token; - __le16 cmd_id; -}; - -struct mc_command { - u64 header; - u64 params[MC_CMD_NUM_OF_PARAMS]; -}; - -enum mc_cmd_status { - MC_CMD_STATUS_OK = 0x0, /* Completed successfully */ - MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */ - MC_CMD_STATUS_AUTH_ERR = 0x3, /* Authentication error */ - MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /* No privilege */ - MC_CMD_STATUS_DMA_ERR = 0x5, /* DMA or I/O error */ - MC_CMD_STATUS_CONFIG_ERR = 0x6, /* Configuration error */ - MC_CMD_STATUS_TIMEOUT = 0x7, /* Operation timed out */ - MC_CMD_STATUS_NO_RESOURCE = 0x8, /* No resources */ - MC_CMD_STATUS_NO_MEMORY = 0x9, /* No memory available */ - MC_CMD_STATUS_BUSY = 0xA, /* Device is busy */ - MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /* Unsupported operation */ - MC_CMD_STATUS_INVALID_STATE = 0xC /* Invalid state */ -}; - -/* - * MC command flags - */ - -/* High priority flag */ -#define MC_CMD_FLAG_PRI 0x80 -/* Command completion flag */ -#define MC_CMD_FLAG_INTR_DIS 0x01 - -static inline u64 mc_encode_cmd_header(u16 cmd_id, - u32 cmd_flags, - u16 token) -{ - u64 header = 0; - struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header; - - hdr->cmd_id = cpu_to_le16(cmd_id); - hdr->token = cpu_to_le16(token); - hdr->status = MC_CMD_STATUS_READY; - if (cmd_flags & MC_CMD_FLAG_PRI) - hdr->flags_hw = MC_CMD_FLAG_PRI; - if (cmd_flags & MC_CMD_FLAG_INTR_DIS) - hdr->flags_sw = MC_CMD_FLAG_INTR_DIS; - - return header; -} - -static inline u16 mc_cmd_hdr_read_token(struct mc_command *cmd) -{ - struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; - u16 token = le16_to_cpu(hdr->token); - - return token; -} - -struct mc_rsp_create { - __le32 object_id; -}; - -struct mc_rsp_api_ver { - __le16 major_ver; - __le16 minor_ver; -}; - -static inline u32 mc_cmd_read_object_id(struct mc_command *cmd) -{ - struct mc_rsp_create *rsp_params; - - rsp_params = (struct mc_rsp_create *)cmd->params; - return le32_to_cpu(rsp_params->object_id); -} - -static inline void mc_cmd_read_api_version(struct mc_command *cmd, - u16 *major_ver, - u16 *minor_ver) -{ - struct mc_rsp_api_ver *rsp_params; - - rsp_params = (struct mc_rsp_api_ver *)cmd->params; - *major_ver = le16_to_cpu(rsp_params->major_ver); - *minor_ver = le16_to_cpu(rsp_params->minor_ver); -} - -/** - * Bit masks for a MC I/O object (struct fsl_mc_io) flags - */ -#define FSL_MC_IO_ATOMIC_CONTEXT_PORTAL 0x0001 - -/** - * struct fsl_mc_io - MC I/O object to be passed-in to mc_send_command() - * @dev: device associated with this Mc I/O object - * @flags: flags for mc_send_command() - * @portal_size: MC command portal size in bytes - * @portal_phys_addr: MC command portal physical address - * @portal_virt_addr: MC command portal virtual address - * @dpmcp_dev: pointer to the DPMCP device associated with the MC portal. - * - * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not - * set: - * @mutex: Mutex to serialize mc_send_command() calls that use the same MC - * portal, if the fsl_mc_io object was created with the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag off. mc_send_command() calls for this - * fsl_mc_io object must be made only from non-atomic context. - * - * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is - * set: - * @spinlock: Spinlock to serialize mc_send_command() calls that use the same MC - * portal, if the fsl_mc_io object was created with the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag on. mc_send_command() calls for this - * fsl_mc_io object can be made from atomic or non-atomic context. - */ -struct fsl_mc_io { - struct device *dev; - u16 flags; - u32 portal_size; - phys_addr_t portal_phys_addr; - void __iomem *portal_virt_addr; - struct fsl_mc_device *dpmcp_dev; - union { - /* - * This field is only meaningful if the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not set - */ - struct mutex mutex; /* serializes mc_send_command() */ - - /* - * This field is only meaningful if the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is set - */ - spinlock_t spinlock; /* serializes mc_send_command() */ - }; -}; - -int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); - -#ifdef CONFIG_FSL_MC_BUS -#define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type) -#else -/* If fsl-mc bus is not present device cannot belong to fsl-mc bus */ -#define dev_is_fsl_mc(_dev) (0) -#endif - -/* - * module_fsl_mc_driver() - Helper macro for drivers that don't do - * anything special in module init/exit. This eliminates a lot of - * boilerplate. Each module may only use this macro once, and - * calling it replaces module_init() and module_exit() - */ -#define module_fsl_mc_driver(__fsl_mc_driver) \ - module_driver(__fsl_mc_driver, fsl_mc_driver_register, \ - fsl_mc_driver_unregister) - -/* - * Macro to avoid include chaining to get THIS_MODULE - */ -#define fsl_mc_driver_register(drv) \ - __fsl_mc_driver_register(drv, THIS_MODULE) - -int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver, - struct module *owner); - -void fsl_mc_driver_unregister(struct fsl_mc_driver *driver); - -int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev, - u16 mc_io_flags, - struct fsl_mc_io **new_mc_io); - -void fsl_mc_portal_free(struct fsl_mc_io *mc_io); - -int fsl_mc_portal_reset(struct fsl_mc_io *mc_io); - -int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev, - enum fsl_mc_pool_type pool_type, - struct fsl_mc_device **new_mc_adev); - -void fsl_mc_object_free(struct fsl_mc_device *mc_adev); - -struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent); - -int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev); - -void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev); - -extern struct bus_type fsl_mc_bus_type; - -extern struct device_type fsl_mc_bus_dprc_type; -extern struct device_type fsl_mc_bus_dpni_type; -extern struct device_type fsl_mc_bus_dpio_type; -extern struct device_type fsl_mc_bus_dpsw_type; -extern struct device_type fsl_mc_bus_dpbp_type; -extern struct device_type fsl_mc_bus_dpcon_type; -extern struct device_type fsl_mc_bus_dpmcp_type; -extern struct device_type fsl_mc_bus_dpmac_type; -extern struct device_type fsl_mc_bus_dprtc_type; - -static inline bool is_fsl_mc_bus_dprc(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dprc_type; -} - -static inline bool is_fsl_mc_bus_dpni(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dpni_type; -} - -static inline bool is_fsl_mc_bus_dpio(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dpio_type; -} - -static inline bool is_fsl_mc_bus_dpsw(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dpsw_type; -} - -static inline bool is_fsl_mc_bus_dpbp(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dpbp_type; -} - -static inline bool is_fsl_mc_bus_dpcon(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dpcon_type; -} - -static inline bool is_fsl_mc_bus_dpmcp(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dpmcp_type; -} - -static inline bool is_fsl_mc_bus_dpmac(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dpmac_type; -} - -static inline bool is_fsl_mc_bus_dprtc(const struct fsl_mc_device *mc_dev) -{ - return mc_dev->dev.type == &fsl_mc_bus_dprtc_type; -} - -#endif /* _FSL_MC_H_ */ diff --git a/drivers/staging/fsl-mc/overview.rst b/drivers/staging/fsl-mc/overview.rst deleted file mode 100644 index 79fede4447d6..000000000000 --- a/drivers/staging/fsl-mc/overview.rst +++ /dev/null @@ -1,404 +0,0 @@ -.. include:: - -DPAA2 (Data Path Acceleration Architecture Gen2) Overview -========================================================= - -:Copyright: |copy| 2015 Freescale Semiconductor Inc. -:Copyright: |copy| 2018 NXP - -This document provides an overview of the Freescale DPAA2 architecture -and how it is integrated into the Linux kernel. - -Introduction -============ - -DPAA2 is a hardware architecture designed for high-speeed network -packet processing. DPAA2 consists of sophisticated mechanisms for -processing Ethernet packets, queue management, buffer management, -autonomous L2 switching, virtual Ethernet bridging, and accelerator -(e.g. crypto) sharing. - -A DPAA2 hardware component called the Management Complex (or MC) manages the -DPAA2 hardware resources. The MC provides an object-based abstraction for -software drivers to use the DPAA2 hardware. -The MC uses DPAA2 hardware resources such as queues, buffer pools, and -network ports to create functional objects/devices such as network -interfaces, an L2 switch, or accelerator instances. -The MC provides memory-mapped I/O command interfaces (MC portals) -which DPAA2 software drivers use to operate on DPAA2 objects. - -The diagram below shows an overview of the DPAA2 resource management -architecture:: - - +--------------------------------------+ - | OS | - | DPAA2 drivers | - | | | - +-----------------------------|--------+ - | - | (create,discover,connect - | config,use,destroy) - | - DPAA2 | - +------------------------| mc portal |-+ - | | | - | +- - - - - - - - - - - - -V- - -+ | - | | | | - | | Management Complex (MC) | | - | | | | - | +- - - - - - - - - - - - - - - -+ | - | | - | Hardware Hardware | - | Resources Objects | - | --------- ------- | - | -queues -DPRC | - | -buffer pools -DPMCP | - | -Eth MACs/ports -DPIO | - | -network interface -DPNI | - | profiles -DPMAC | - | -queue portals -DPBP | - | -MC portals ... | - | ... | - | | - +--------------------------------------+ - - -The MC mediates operations such as create, discover, -connect, configuration, and destroy. Fast-path operations -on data, such as packet transmit/receive, are not mediated by -the MC and are done directly using memory mapped regions in -DPIO objects. - -Overview of DPAA2 Objects -========================= - -The section provides a brief overview of some key DPAA2 objects. -A simple scenario is described illustrating the objects involved -in creating a network interfaces. - -DPRC (Datapath Resource Container) ----------------------------------- - -A DPRC is a container object that holds all the other -types of DPAA2 objects. In the example diagram below there -are 8 objects of 5 types (DPMCP, DPIO, DPBP, DPNI, and DPMAC) -in the container. - -:: - - +---------------------------------------------------------+ - | DPRC | - | | - | +-------+ +-------+ +-------+ +-------+ +-------+ | - | | DPMCP | | DPIO | | DPBP | | DPNI | | DPMAC | | - | +-------+ +-------+ +-------+ +---+---+ +---+---+ | - | | DPMCP | | DPIO | | - | +-------+ +-------+ | - | | DPMCP | | - | +-------+ | - | | - +---------------------------------------------------------+ - -From the point of view of an OS, a DPRC behaves similar to a plug and -play bus, like PCI. DPRC commands can be used to enumerate the contents -of the DPRC, discover the hardware objects present (including mappable -regions and interrupts). - -:: - - DPRC.1 (bus) - | - +--+--------+-------+-------+-------+ - | | | | | - DPMCP.1 DPIO.1 DPBP.1 DPNI.1 DPMAC.1 - DPMCP.2 DPIO.2 - DPMCP.3 - -Hardware objects can be created and destroyed dynamically, providing -the ability to hot plug/unplug objects in and out of the DPRC. - -A DPRC has a mappable MMIO region (an MC portal) that can be used -to send MC commands. It has an interrupt for status events (like -hotplug). -All objects in a container share the same hardware "isolation context". -This means that with respect to an IOMMU the isolation granularity -is at the DPRC (container) level, not at the individual object -level. - -DPRCs can be defined statically and populated with objects -via a config file passed to the MC when firmware starts it. - -DPAA2 Objects for an Ethernet Network Interface ------------------------------------------------ - -A typical Ethernet NIC is monolithic-- the NIC device contains TX/RX -queuing mechanisms, configuration mechanisms, buffer management, -physical ports, and interrupts. DPAA2 uses a more granular approach -utilizing multiple hardware objects. Each object provides specialized -functions. Groups of these objects are used by software to provide -Ethernet network interface functionality. This approach provides -efficient use of finite hardware resources, flexibility, and -performance advantages. - -The diagram below shows the objects needed for a simple -network interface configuration on a system with 2 CPUs. - -:: - - +---+---+ +---+---+ - CPU0 CPU1 - +---+---+ +---+---+ - | | - +---+---+ +---+---+ - DPIO DPIO - +---+---+ +---+---+ - \ / - \ / - \ / - +---+---+ - DPNI --- DPBP,DPMCP - +---+---+ - | - | - +---+---+ - DPMAC - +---+---+ - | - port/PHY - -Below the objects are described. For each object a brief description -is provided along with a summary of the kinds of operations the object -supports and a summary of key resources of the object (MMIO regions -and IRQs). - -DPMAC (Datapath Ethernet MAC) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Represents an Ethernet MAC, a hardware device that connects to an Ethernet -PHY and allows physical transmission and reception of Ethernet frames. - -- MMIO regions: none -- IRQs: DPNI link change -- commands: set link up/down, link config, get stats, - IRQ config, enable, reset - -DPNI (Datapath Network Interface) -Contains TX/RX queues, network interface configuration, and RX buffer pool -configuration mechanisms. The TX/RX queues are in memory and are identified -by queue number. - -- MMIO regions: none -- IRQs: link state -- commands: port config, offload config, queue config, - parse/classify config, IRQ config, enable, reset - -DPIO (Datapath I/O) -~~~~~~~~~~~~~~~~~~~ -Provides interfaces to enqueue and dequeue -packets and do hardware buffer pool management operations. The DPAA2 -architecture separates the mechanism to access queues (the DPIO object) -from the queues themselves. The DPIO provides an MMIO interface to -enqueue/dequeue packets. To enqueue something a descriptor is written -to the DPIO MMIO region, which includes the target queue number. -There will typically be one DPIO assigned to each CPU. This allows all -CPUs to simultaneously perform enqueue/dequeued operations. DPIOs are -expected to be shared by different DPAA2 drivers. - -- MMIO regions: queue operations, buffer management -- IRQs: data availability, congestion notification, buffer - pool depletion -- commands: IRQ config, enable, reset - -DPBP (Datapath Buffer Pool) -~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Represents a hardware buffer pool. - -- MMIO regions: none -- IRQs: none -- commands: enable, reset - -DPMCP (Datapath MC Portal) -~~~~~~~~~~~~~~~~~~~~~~~~~~ -Provides an MC command portal. -Used by drivers to send commands to the MC to manage -objects. - -- MMIO regions: MC command portal -- IRQs: command completion -- commands: IRQ config, enable, reset - -Object Connections -================== -Some objects have explicit relationships that must -be configured: - -- DPNI <--> DPMAC -- DPNI <--> DPNI -- DPNI <--> L2-switch-port - - A DPNI must be connected to something such as a DPMAC, - another DPNI, or L2 switch port. The DPNI connection - is made via a DPRC command. - -:: - - +-------+ +-------+ - | DPNI | | DPMAC | - +---+---+ +---+---+ - | | - +==========+ - -- DPNI <--> DPBP - - A network interface requires a 'buffer pool' (DPBP - object) which provides a list of pointers to memory - where received Ethernet data is to be copied. The - Ethernet driver configures the DPBPs associated with - the network interface. - -Interrupts -========== -All interrupts generated by DPAA2 objects are message -interrupts. At the hardware level message interrupts -generated by devices will normally have 3 components-- -1) a non-spoofable 'device-id' expressed on the hardware -bus, 2) an address, 3) a data value. - -In the case of DPAA2 devices/objects, all objects in the -same container/DPRC share the same 'device-id'. -For ARM-based SoC this is the same as the stream ID. - - -DPAA2 Linux Drivers Overview -============================ - -This section provides an overview of the Linux kernel drivers for -DPAA2-- 1) the bus driver and associated "DPAA2 infrastructure" -drivers and 2) functional object drivers (such as Ethernet). - -As described previously, a DPRC is a container that holds the other -types of DPAA2 objects. It is functionally similar to a plug-and-play -bus controller. -Each object in the DPRC is a Linux "device" and is bound to a driver. -The diagram below shows the Linux drivers involved in a networking -scenario and the objects bound to each driver. A brief description -of each driver follows. - -:: - - +------------+ - | OS Network | - | Stack | - +------------+ +------------+ - | Allocator |. . . . . . . | Ethernet | - |(DPMCP,DPBP)| | (DPNI) | - +-.----------+ +---+---+----+ - . . ^ | - . . | | dequeue> - +-------------+ . | | - | DPRC driver | . +---+---V----+ +---------+ - | (DPRC) | . . . . . .| DPIO driver| | MAC | - +----------+--+ | (DPIO) | | (DPMAC) | - | +------+-----+ +-----+---+ - | | | - | | | - +--------+----------+ | +--+---+ - | MC-bus driver | | | PHY | - | | | |driver| - | /bus/fsl-mc | | +--+---+ - +-------------------+ | | - | | - ========================= HARDWARE =========|=================|====== - DPIO | - | | - DPNI---DPBP | - | | - DPMAC | - | | - PHY ---------------+ - ============================================|======================== - -A brief description of each driver is provided below. - -MC-bus driver -------------- -The MC-bus driver is a platform driver and is probed from a -node in the device tree (compatible "fsl,qoriq-mc") passed in by boot -firmware. It is responsible for bootstrapping the DPAA2 kernel -infrastructure. -Key functions include: - -- registering a new bus type named "fsl-mc" with the kernel, - and implementing bus call-backs (e.g. match/uevent/dev_groups) -- implementing APIs for DPAA2 driver registration and for device - add/remove -- creates an MSI IRQ domain -- doing a 'device add' to expose the 'root' DPRC, in turn triggering - a bind of the root DPRC to the DPRC driver - -The binding for the MC-bus device-tree node can be consulted at -*Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt*. -The sysfs bind/unbind interfaces for the MC-bus can be consulted at -*Documentation/ABI/testing/sysfs-bus-fsl-mc*. - -DPRC driver ------------ -The DPRC driver is bound to DPRC objects and does runtime management -of a bus instance. It performs the initial bus scan of the DPRC -and handles interrupts for container events such as hot plug by -re-scanning the DPRC. - -Allocator ---------- -Certain objects such as DPMCP and DPBP are generic and fungible, -and are intended to be used by other drivers. For example, -the DPAA2 Ethernet driver needs: - -- DPMCPs to send MC commands, to configure network interfaces -- DPBPs for network buffer pools - -The allocator driver registers for these allocatable object types -and those objects are bound to the allocator when the bus is probed. -The allocator maintains a pool of objects that are available for -allocation by other DPAA2 drivers. - -DPIO driver ------------ -The DPIO driver is bound to DPIO objects and provides services that allow -other drivers such as the Ethernet driver to enqueue and dequeue data for -their respective objects. -Key services include: - -- data availability notifications -- hardware queuing operations (enqueue and dequeue of data) -- hardware buffer pool management - -To transmit a packet the Ethernet driver puts data on a queue and -invokes a DPIO API. For receive, the Ethernet driver registers -a data availability notification callback. To dequeue a packet -a DPIO API is used. -There is typically one DPIO object per physical CPU for optimum -performance, allowing different CPUs to simultaneously enqueue -and dequeue data. - -The DPIO driver operates on behalf of all DPAA2 drivers -active in the kernel-- Ethernet, crypto, compression, -etc. - -Ethernet driver ---------------- -The Ethernet driver is bound to a DPNI and implements the kernel -interfaces needed to connect the DPAA2 network interface to -the network stack. -Each DPNI corresponds to a Linux network interface. - -MAC driver ----------- -An Ethernet PHY is an off-chip, board specific component and is managed -by the appropriate PHY driver via an mdio bus. The MAC driver -plays a role of being a proxy between the PHY driver and the -MC. It does this proxy via the MC commands to a DPMAC object. -If the PHY driver signals a link change, the MAC driver notifies -the MC via a DPMAC command. If a network interface is brought -up or down, the MC notifies the DPMAC driver via an interrupt and -the driver can take appropriate action. diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h new file mode 100644 index 000000000000..765ba41f5987 --- /dev/null +++ b/include/linux/fsl/mc.h @@ -0,0 +1,454 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Freescale Management Complex (MC) bus public interface + * + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Author: German Rivera + * + */ +#ifndef _FSL_MC_H_ +#define _FSL_MC_H_ + +#include +#include +#include + +#define FSL_MC_VENDOR_FREESCALE 0x1957 + +struct irq_domain; +struct msi_domain_info; + +struct fsl_mc_device; +struct fsl_mc_io; + +/** + * struct fsl_mc_driver - MC object device driver object + * @driver: Generic device driver + * @match_id_table: table of supported device matching Ids + * @probe: Function called when a device is added + * @remove: Function called when a device is removed + * @shutdown: Function called at shutdown time to quiesce the device + * @suspend: Function called when a device is stopped + * @resume: Function called when a device is resumed + * + * Generic DPAA device driver object for device drivers that are registered + * with a DPRC bus. This structure is to be embedded in each device-specific + * driver structure. + */ +struct fsl_mc_driver { + struct device_driver driver; + const struct fsl_mc_device_id *match_id_table; + int (*probe)(struct fsl_mc_device *dev); + int (*remove)(struct fsl_mc_device *dev); + void (*shutdown)(struct fsl_mc_device *dev); + int (*suspend)(struct fsl_mc_device *dev, pm_message_t state); + int (*resume)(struct fsl_mc_device *dev); +}; + +#define to_fsl_mc_driver(_drv) \ + container_of(_drv, struct fsl_mc_driver, driver) + +/** + * enum fsl_mc_pool_type - Types of allocatable MC bus resources + * + * Entries in these enum are used as indices in the array of resource + * pools of an fsl_mc_bus object. + */ +enum fsl_mc_pool_type { + FSL_MC_POOL_DPMCP = 0x0, /* corresponds to "dpmcp" in the MC */ + FSL_MC_POOL_DPBP, /* corresponds to "dpbp" in the MC */ + FSL_MC_POOL_DPCON, /* corresponds to "dpcon" in the MC */ + FSL_MC_POOL_IRQ, + + /* + * NOTE: New resource pool types must be added before this entry + */ + FSL_MC_NUM_POOL_TYPES +}; + +/** + * struct fsl_mc_resource - MC generic resource + * @type: type of resource + * @id: unique MC resource Id within the resources of the same type + * @data: pointer to resource-specific data if the resource is currently + * allocated, or NULL if the resource is not currently allocated. + * @parent_pool: pointer to the parent resource pool from which this + * resource is allocated from. + * @node: Node in the free list of the corresponding resource pool + * + * NOTE: This structure is to be embedded as a field of specific + * MC resource structures. + */ +struct fsl_mc_resource { + enum fsl_mc_pool_type type; + s32 id; + void *data; + struct fsl_mc_resource_pool *parent_pool; + struct list_head node; +}; + +/** + * struct fsl_mc_device_irq - MC object device message-based interrupt + * @msi_desc: pointer to MSI descriptor allocated by fsl_mc_msi_alloc_descs() + * @mc_dev: MC object device that owns this interrupt + * @dev_irq_index: device-relative IRQ index + * @resource: MC generic resource associated with the interrupt + */ +struct fsl_mc_device_irq { + struct msi_desc *msi_desc; + struct fsl_mc_device *mc_dev; + u8 dev_irq_index; + struct fsl_mc_resource resource; +}; + +#define to_fsl_mc_irq(_mc_resource) \ + container_of(_mc_resource, struct fsl_mc_device_irq, resource) + +/* Opened state - Indicates that an object is open by at least one owner */ +#define FSL_MC_OBJ_STATE_OPEN 0x00000001 +/* Plugged state - Indicates that the object is plugged */ +#define FSL_MC_OBJ_STATE_PLUGGED 0x00000002 + +/** + * Shareability flag - Object flag indicating no memory shareability. + * the object generates memory accesses that are non coherent with other + * masters; + * user is responsible for proper memory handling through IOMMU configuration. + */ +#define FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 + +/** + * struct fsl_mc_obj_desc - Object descriptor + * @type: Type of object: NULL terminated string + * @id: ID of logical object resource + * @vendor: Object vendor identifier + * @ver_major: Major version number + * @ver_minor: Minor version number + * @irq_count: Number of interrupts supported by the object + * @region_count: Number of mappable regions supported by the object + * @state: Object state: combination of FSL_MC_OBJ_STATE_ states + * @label: Object label: NULL terminated string + * @flags: Object's flags + */ +struct fsl_mc_obj_desc { + char type[16]; + int id; + u16 vendor; + u16 ver_major; + u16 ver_minor; + u8 irq_count; + u8 region_count; + u32 state; + char label[16]; + u16 flags; +}; + +/** + * Bit masks for a MC object device (struct fsl_mc_device) flags + */ +#define FSL_MC_IS_DPRC 0x0001 + +/** + * struct fsl_mc_device - MC object device object + * @dev: Linux driver model device object + * @dma_mask: Default DMA mask + * @flags: MC object device flags + * @icid: Isolation context ID for the device + * @mc_handle: MC handle for the corresponding MC object opened + * @mc_io: Pointer to MC IO object assigned to this device or + * NULL if none. + * @obj_desc: MC description of the DPAA device + * @regions: pointer to array of MMIO region entries + * @irqs: pointer to array of pointers to interrupts allocated to this device + * @resource: generic resource associated with this MC object device, if any. + * + * Generic device object for MC object devices that are "attached" to a + * MC bus. + * + * NOTES: + * - For a non-DPRC object its icid is the same as its parent DPRC's icid. + * - The SMMU notifier callback gets invoked after device_add() has been + * called for an MC object device, but before the device-specific probe + * callback gets called. + * - DP_OBJ_DPRC objects are the only MC objects that have built-in MC + * portals. For all other MC objects, their device drivers are responsible for + * allocating MC portals for them by calling fsl_mc_portal_allocate(). + * - Some types of MC objects (e.g., DP_OBJ_DPBP, DP_OBJ_DPCON) are + * treated as resources that can be allocated/deallocated from the + * corresponding resource pool in the object's parent DPRC, using the + * fsl_mc_object_allocate()/fsl_mc_object_free() functions. These MC objects + * are known as "allocatable" objects. For them, the corresponding + * fsl_mc_device's 'resource' points to the associated resource object. + * For MC objects that are not allocatable (e.g., DP_OBJ_DPRC, DP_OBJ_DPNI), + * 'resource' is NULL. + */ +struct fsl_mc_device { + struct device dev; + u64 dma_mask; + u16 flags; + u16 icid; + u16 mc_handle; + struct fsl_mc_io *mc_io; + struct fsl_mc_obj_desc obj_desc; + struct resource *regions; + struct fsl_mc_device_irq **irqs; + struct fsl_mc_resource *resource; +}; + +#define to_fsl_mc_device(_dev) \ + container_of(_dev, struct fsl_mc_device, dev) + +#define MC_CMD_NUM_OF_PARAMS 7 + +struct mc_cmd_header { + u8 src_id; + u8 flags_hw; + u8 status; + u8 flags_sw; + __le16 token; + __le16 cmd_id; +}; + +struct mc_command { + u64 header; + u64 params[MC_CMD_NUM_OF_PARAMS]; +}; + +enum mc_cmd_status { + MC_CMD_STATUS_OK = 0x0, /* Completed successfully */ + MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */ + MC_CMD_STATUS_AUTH_ERR = 0x3, /* Authentication error */ + MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /* No privilege */ + MC_CMD_STATUS_DMA_ERR = 0x5, /* DMA or I/O error */ + MC_CMD_STATUS_CONFIG_ERR = 0x6, /* Configuration error */ + MC_CMD_STATUS_TIMEOUT = 0x7, /* Operation timed out */ + MC_CMD_STATUS_NO_RESOURCE = 0x8, /* No resources */ + MC_CMD_STATUS_NO_MEMORY = 0x9, /* No memory available */ + MC_CMD_STATUS_BUSY = 0xA, /* Device is busy */ + MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /* Unsupported operation */ + MC_CMD_STATUS_INVALID_STATE = 0xC /* Invalid state */ +}; + +/* + * MC command flags + */ + +/* High priority flag */ +#define MC_CMD_FLAG_PRI 0x80 +/* Command completion flag */ +#define MC_CMD_FLAG_INTR_DIS 0x01 + +static inline u64 mc_encode_cmd_header(u16 cmd_id, + u32 cmd_flags, + u16 token) +{ + u64 header = 0; + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header; + + hdr->cmd_id = cpu_to_le16(cmd_id); + hdr->token = cpu_to_le16(token); + hdr->status = MC_CMD_STATUS_READY; + if (cmd_flags & MC_CMD_FLAG_PRI) + hdr->flags_hw = MC_CMD_FLAG_PRI; + if (cmd_flags & MC_CMD_FLAG_INTR_DIS) + hdr->flags_sw = MC_CMD_FLAG_INTR_DIS; + + return header; +} + +static inline u16 mc_cmd_hdr_read_token(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 token = le16_to_cpu(hdr->token); + + return token; +} + +struct mc_rsp_create { + __le32 object_id; +}; + +struct mc_rsp_api_ver { + __le16 major_ver; + __le16 minor_ver; +}; + +static inline u32 mc_cmd_read_object_id(struct mc_command *cmd) +{ + struct mc_rsp_create *rsp_params; + + rsp_params = (struct mc_rsp_create *)cmd->params; + return le32_to_cpu(rsp_params->object_id); +} + +static inline void mc_cmd_read_api_version(struct mc_command *cmd, + u16 *major_ver, + u16 *minor_ver) +{ + struct mc_rsp_api_ver *rsp_params; + + rsp_params = (struct mc_rsp_api_ver *)cmd->params; + *major_ver = le16_to_cpu(rsp_params->major_ver); + *minor_ver = le16_to_cpu(rsp_params->minor_ver); +} + +/** + * Bit masks for a MC I/O object (struct fsl_mc_io) flags + */ +#define FSL_MC_IO_ATOMIC_CONTEXT_PORTAL 0x0001 + +/** + * struct fsl_mc_io - MC I/O object to be passed-in to mc_send_command() + * @dev: device associated with this Mc I/O object + * @flags: flags for mc_send_command() + * @portal_size: MC command portal size in bytes + * @portal_phys_addr: MC command portal physical address + * @portal_virt_addr: MC command portal virtual address + * @dpmcp_dev: pointer to the DPMCP device associated with the MC portal. + * + * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not + * set: + * @mutex: Mutex to serialize mc_send_command() calls that use the same MC + * portal, if the fsl_mc_io object was created with the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag off. mc_send_command() calls for this + * fsl_mc_io object must be made only from non-atomic context. + * + * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is + * set: + * @spinlock: Spinlock to serialize mc_send_command() calls that use the same MC + * portal, if the fsl_mc_io object was created with the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag on. mc_send_command() calls for this + * fsl_mc_io object can be made from atomic or non-atomic context. + */ +struct fsl_mc_io { + struct device *dev; + u16 flags; + u32 portal_size; + phys_addr_t portal_phys_addr; + void __iomem *portal_virt_addr; + struct fsl_mc_device *dpmcp_dev; + union { + /* + * This field is only meaningful if the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not set + */ + struct mutex mutex; /* serializes mc_send_command() */ + + /* + * This field is only meaningful if the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is set + */ + spinlock_t spinlock; /* serializes mc_send_command() */ + }; +}; + +int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); + +#ifdef CONFIG_FSL_MC_BUS +#define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type) +#else +/* If fsl-mc bus is not present device cannot belong to fsl-mc bus */ +#define dev_is_fsl_mc(_dev) (0) +#endif + +/* + * module_fsl_mc_driver() - Helper macro for drivers that don't do + * anything special in module init/exit. This eliminates a lot of + * boilerplate. Each module may only use this macro once, and + * calling it replaces module_init() and module_exit() + */ +#define module_fsl_mc_driver(__fsl_mc_driver) \ + module_driver(__fsl_mc_driver, fsl_mc_driver_register, \ + fsl_mc_driver_unregister) + +/* + * Macro to avoid include chaining to get THIS_MODULE + */ +#define fsl_mc_driver_register(drv) \ + __fsl_mc_driver_register(drv, THIS_MODULE) + +int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver, + struct module *owner); + +void fsl_mc_driver_unregister(struct fsl_mc_driver *driver); + +int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev, + u16 mc_io_flags, + struct fsl_mc_io **new_mc_io); + +void fsl_mc_portal_free(struct fsl_mc_io *mc_io); + +int fsl_mc_portal_reset(struct fsl_mc_io *mc_io); + +int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev, + enum fsl_mc_pool_type pool_type, + struct fsl_mc_device **new_mc_adev); + +void fsl_mc_object_free(struct fsl_mc_device *mc_adev); + +struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, + struct msi_domain_info *info, + struct irq_domain *parent); + +int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev); + +void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev); + +extern struct bus_type fsl_mc_bus_type; + +extern struct device_type fsl_mc_bus_dprc_type; +extern struct device_type fsl_mc_bus_dpni_type; +extern struct device_type fsl_mc_bus_dpio_type; +extern struct device_type fsl_mc_bus_dpsw_type; +extern struct device_type fsl_mc_bus_dpbp_type; +extern struct device_type fsl_mc_bus_dpcon_type; +extern struct device_type fsl_mc_bus_dpmcp_type; +extern struct device_type fsl_mc_bus_dpmac_type; +extern struct device_type fsl_mc_bus_dprtc_type; + +static inline bool is_fsl_mc_bus_dprc(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dprc_type; +} + +static inline bool is_fsl_mc_bus_dpni(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dpni_type; +} + +static inline bool is_fsl_mc_bus_dpio(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dpio_type; +} + +static inline bool is_fsl_mc_bus_dpsw(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dpsw_type; +} + +static inline bool is_fsl_mc_bus_dpbp(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dpbp_type; +} + +static inline bool is_fsl_mc_bus_dpcon(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dpcon_type; +} + +static inline bool is_fsl_mc_bus_dpmcp(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dpmcp_type; +} + +static inline bool is_fsl_mc_bus_dpmac(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dpmac_type; +} + +static inline bool is_fsl_mc_bus_dprtc(const struct fsl_mc_device *mc_dev) +{ + return mc_dev->dev.type == &fsl_mc_bus_dprtc_type; +} + +#endif /* _FSL_MC_H_ */ -- cgit v1.2.3 From a7f249e33a44432de30d50f3c57868bc00a8f362 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Thu, 15 Feb 2018 11:31:47 +0530 Subject: clocksource: timer-ti-dm: Add timer ops to the platform data structure Add timer ops to the platform data structure Signed-off-by: Keerthy Reviewed-by: Sebastian Reichel Tested-by: Ladislav Michl Signed-off-by: Tony Lindgren --- include/linux/platform_data/dmtimer-omap.h | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'include/linux') diff --git a/include/linux/platform_data/dmtimer-omap.h b/include/linux/platform_data/dmtimer-omap.h index a19b78d826e9..757a0f9e26f9 100644 --- a/include/linux/platform_data/dmtimer-omap.h +++ b/include/linux/platform_data/dmtimer-omap.h @@ -20,12 +20,50 @@ #ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__ #define __PLATFORM_DATA_DMTIMER_OMAP_H__ +struct omap_dm_timer_ops { + struct omap_dm_timer *(*request_by_node)(struct device_node *np); + struct omap_dm_timer *(*request_specific)(int timer_id); + struct omap_dm_timer *(*request)(void); + + int (*free)(struct omap_dm_timer *timer); + + void (*enable)(struct omap_dm_timer *timer); + void (*disable)(struct omap_dm_timer *timer); + + int (*get_irq)(struct omap_dm_timer *timer); + int (*set_int_enable)(struct omap_dm_timer *timer, + unsigned int value); + int (*set_int_disable)(struct omap_dm_timer *timer, u32 mask); + + struct clk *(*get_fclk)(struct omap_dm_timer *timer); + + int (*start)(struct omap_dm_timer *timer); + int (*stop)(struct omap_dm_timer *timer); + int (*set_source)(struct omap_dm_timer *timer, int source); + + int (*set_load)(struct omap_dm_timer *timer, int autoreload, + unsigned int value); + int (*set_match)(struct omap_dm_timer *timer, int enable, + unsigned int match); + int (*set_pwm)(struct omap_dm_timer *timer, int def_on, + int toggle, int trigger); + int (*set_prescaler)(struct omap_dm_timer *timer, int prescaler); + + unsigned int (*read_counter)(struct omap_dm_timer *timer); + int (*write_counter)(struct omap_dm_timer *timer, + unsigned int value); + unsigned int (*read_status)(struct omap_dm_timer *timer); + int (*write_status)(struct omap_dm_timer *timer, + unsigned int value); +}; + struct dmtimer_platform_data { /* set_timer_src - Only used for OMAP1 devices */ int (*set_timer_src)(struct platform_device *pdev, int source); u32 timer_capability; u32 timer_errata; int (*get_context_loss_count)(struct device *); + const struct omap_dm_timer_ops *timer_ops; }; #endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */ -- cgit v1.2.3 From 72e89f50084c6dbc58a00aeedf92c450dc1a8b1c Mon Sep 17 00:00:00 2001 From: Richard Haines Date: Tue, 13 Feb 2018 20:53:21 +0000 Subject: security: Add support for SCTP security hooks The SCTP security hooks are explained in: Documentation/security/LSM-sctp.rst Signed-off-by: Richard Haines Signed-off-by: Paul Moore --- Documentation/security/LSM-sctp.rst | 175 ++++++++++++++++++++++++++++++++++++ include/linux/lsm_hooks.h | 36 ++++++++ include/linux/security.h | 25 ++++++ security/security.c | 22 +++++ 4 files changed, 258 insertions(+) create mode 100644 Documentation/security/LSM-sctp.rst (limited to 'include/linux') diff --git a/Documentation/security/LSM-sctp.rst b/Documentation/security/LSM-sctp.rst new file mode 100644 index 000000000000..6e5a3925a860 --- /dev/null +++ b/Documentation/security/LSM-sctp.rst @@ -0,0 +1,175 @@ +SCTP LSM Support +================ + +For security module support, three SCTP specific hooks have been implemented:: + + security_sctp_assoc_request() + security_sctp_bind_connect() + security_sctp_sk_clone() + +Also the following security hook has been utilised:: + + security_inet_conn_established() + +The usage of these hooks are described below with the SELinux implementation +described in ``Documentation/security/SELinux-sctp.rst`` + + +security_sctp_assoc_request() +----------------------------- +Passes the ``@ep`` and ``@chunk->skb`` of the association INIT packet to the +security module. Returns 0 on success, error on failure. +:: + + @ep - pointer to sctp endpoint structure. + @skb - pointer to skbuff of association packet. + + +security_sctp_bind_connect() +----------------------------- +Passes one or more ipv4/ipv6 addresses to the security module for validation +based on the ``@optname`` that will result in either a bind or connect +service as shown in the permission check tables below. +Returns 0 on success, error on failure. +:: + + @sk - Pointer to sock structure. + @optname - Name of the option to validate. + @address - One or more ipv4 / ipv6 addresses. + @addrlen - The total length of address(s). This is calculated on each + ipv4 or ipv6 address using sizeof(struct sockaddr_in) or + sizeof(struct sockaddr_in6). + + ------------------------------------------------------------------ + | BIND Type Checks | + | @optname | @address contains | + |----------------------------|-----------------------------------| + | SCTP_SOCKOPT_BINDX_ADD | One or more ipv4 / ipv6 addresses | + | SCTP_PRIMARY_ADDR | Single ipv4 or ipv6 address | + | SCTP_SET_PEER_PRIMARY_ADDR | Single ipv4 or ipv6 address | + ------------------------------------------------------------------ + + ------------------------------------------------------------------ + | CONNECT Type Checks | + | @optname | @address contains | + |----------------------------|-----------------------------------| + | SCTP_SOCKOPT_CONNECTX | One or more ipv4 / ipv6 addresses | + | SCTP_PARAM_ADD_IP | One or more ipv4 / ipv6 addresses | + | SCTP_SENDMSG_CONNECT | Single ipv4 or ipv6 address | + | SCTP_PARAM_SET_PRIMARY | Single ipv4 or ipv6 address | + ------------------------------------------------------------------ + +A summary of the ``@optname`` entries is as follows:: + + SCTP_SOCKOPT_BINDX_ADD - Allows additional bind addresses to be + associated after (optionally) calling + bind(3). + sctp_bindx(3) adds a set of bind + addresses on a socket. + + SCTP_SOCKOPT_CONNECTX - Allows the allocation of multiple + addresses for reaching a peer + (multi-homed). + sctp_connectx(3) initiates a connection + on an SCTP socket using multiple + destination addresses. + + SCTP_SENDMSG_CONNECT - Initiate a connection that is generated by a + sendmsg(2) or sctp_sendmsg(3) on a new asociation. + + SCTP_PRIMARY_ADDR - Set local primary address. + + SCTP_SET_PEER_PRIMARY_ADDR - Request peer sets address as + association primary. + + SCTP_PARAM_ADD_IP - These are used when Dynamic Address + SCTP_PARAM_SET_PRIMARY - Reconfiguration is enabled as explained below. + + +To support Dynamic Address Reconfiguration the following parameters must be +enabled on both endpoints (or use the appropriate **setsockopt**\(2)):: + + /proc/sys/net/sctp/addip_enable + /proc/sys/net/sctp/addip_noauth_enable + +then the following *_PARAM_*'s are sent to the peer in an +ASCONF chunk when the corresponding ``@optname``'s are present:: + + @optname ASCONF Parameter + ---------- ------------------ + SCTP_SOCKOPT_BINDX_ADD -> SCTP_PARAM_ADD_IP + SCTP_SET_PEER_PRIMARY_ADDR -> SCTP_PARAM_SET_PRIMARY + + +security_sctp_sk_clone() +------------------------- +Called whenever a new socket is created by **accept**\(2) +(i.e. a TCP style socket) or when a socket is 'peeled off' e.g userspace +calls **sctp_peeloff**\(3). +:: + + @ep - pointer to current sctp endpoint structure. + @sk - pointer to current sock structure. + @sk - pointer to new sock structure. + + +security_inet_conn_established() +--------------------------------- +Called when a COOKIE ACK is received:: + + @sk - pointer to sock structure. + @skb - pointer to skbuff of the COOKIE ACK packet. + + +Security Hooks used for Association Establishment +================================================= +The following diagram shows the use of ``security_sctp_bind_connect()``, +``security_sctp_assoc_request()``, ``security_inet_conn_established()`` when +establishing an association. +:: + + SCTP endpoint "A" SCTP endpoint "Z" + ================= ================= + sctp_sf_do_prm_asoc() + Association setup can be initiated + by a connect(2), sctp_connectx(3), + sendmsg(2) or sctp_sendmsg(3). + These will result in a call to + security_sctp_bind_connect() to + initiate an association to + SCTP peer endpoint "Z". + INIT ---------------------------------------------> + sctp_sf_do_5_1B_init() + Respond to an INIT chunk. + SCTP peer endpoint "A" is + asking for an association. Call + security_sctp_assoc_request() + to set the peer label if first + association. + If not first association, check + whether allowed, IF so send: + <----------------------------------------------- INIT ACK + | ELSE audit event and silently + | discard the packet. + | + COOKIE ECHO ------------------------------------------> + | + | + | + <------------------------------------------- COOKIE ACK + | | + sctp_sf_do_5_1E_ca | + Call security_inet_conn_established() | + to set the peer label. | + | | + | If SCTP_SOCKET_TCP or peeled off + | socket security_sctp_sk_clone() is + | called to clone the new socket. + | | + ESTABLISHED ESTABLISHED + | | + ------------------------------------------------------------------ + | Association Established | + ------------------------------------------------------------------ + + diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index 7161d8e7ee79..84c0b927ea85 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -906,6 +906,33 @@ * associated with the TUN device's security structure. * @security pointer to the TUN devices's security structure. * + * Security hooks for SCTP + * + * @sctp_assoc_request: + * Passes the @ep and @chunk->skb of the association INIT packet to + * the security module. + * @ep pointer to sctp endpoint structure. + * @skb pointer to skbuff of association packet. + * Return 0 on success, error on failure. + * @sctp_bind_connect: + * Validiate permissions required for each address associated with sock + * @sk. Depending on @optname, the addresses will be treated as either + * for a connect or bind service. The @addrlen is calculated on each + * ipv4 and ipv6 address using sizeof(struct sockaddr_in) or + * sizeof(struct sockaddr_in6). + * @sk pointer to sock structure. + * @optname name of the option to validate. + * @address list containing one or more ipv4/ipv6 addresses. + * @addrlen total length of address(s). + * Return 0 on success, error on failure. + * @sctp_sk_clone: + * Called whenever a new socket is created by accept(2) (i.e. a TCP + * style socket) or when a socket is 'peeled off' e.g userspace + * calls sctp_peeloff(3). + * @ep pointer to current sctp endpoint structure. + * @sk pointer to current sock structure. + * @sk pointer to new sock structure. + * * Security hooks for Infiniband * * @ib_pkey_access: @@ -1665,6 +1692,12 @@ union security_list_options { int (*tun_dev_attach_queue)(void *security); int (*tun_dev_attach)(struct sock *sk, void *security); int (*tun_dev_open)(void *security); + int (*sctp_assoc_request)(struct sctp_endpoint *ep, + struct sk_buff *skb); + int (*sctp_bind_connect)(struct sock *sk, int optname, + struct sockaddr *address, int addrlen); + void (*sctp_sk_clone)(struct sctp_endpoint *ep, struct sock *sk, + struct sock *newsk); #endif /* CONFIG_SECURITY_NETWORK */ #ifdef CONFIG_SECURITY_INFINIBAND @@ -1914,6 +1947,9 @@ struct security_hook_heads { struct list_head tun_dev_attach_queue; struct list_head tun_dev_attach; struct list_head tun_dev_open; + struct list_head sctp_assoc_request; + struct list_head sctp_bind_connect; + struct list_head sctp_sk_clone; #endif /* CONFIG_SECURITY_NETWORK */ #ifdef CONFIG_SECURITY_INFINIBAND struct list_head ib_pkey_access; diff --git a/include/linux/security.h b/include/linux/security.h index 73f1ef625d40..2ff5f5777a53 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -115,6 +115,7 @@ struct xfrm_policy; struct xfrm_state; struct xfrm_user_sec_ctx; struct seq_file; +struct sctp_endpoint; #ifdef CONFIG_MMU extern unsigned long mmap_min_addr; @@ -1229,6 +1230,11 @@ int security_tun_dev_create(void); int security_tun_dev_attach_queue(void *security); int security_tun_dev_attach(struct sock *sk, void *security); int security_tun_dev_open(void *security); +int security_sctp_assoc_request(struct sctp_endpoint *ep, struct sk_buff *skb); +int security_sctp_bind_connect(struct sock *sk, int optname, + struct sockaddr *address, int addrlen); +void security_sctp_sk_clone(struct sctp_endpoint *ep, struct sock *sk, + struct sock *newsk); #else /* CONFIG_SECURITY_NETWORK */ static inline int security_unix_stream_connect(struct sock *sock, @@ -1421,6 +1427,25 @@ static inline int security_tun_dev_open(void *security) { return 0; } + +static inline int security_sctp_assoc_request(struct sctp_endpoint *ep, + struct sk_buff *skb) +{ + return 0; +} + +static inline int security_sctp_bind_connect(struct sock *sk, int optname, + struct sockaddr *address, + int addrlen) +{ + return 0; +} + +static inline void security_sctp_sk_clone(struct sctp_endpoint *ep, + struct sock *sk, + struct sock *newsk) +{ +} #endif /* CONFIG_SECURITY_NETWORK */ #ifdef CONFIG_SECURITY_INFINIBAND diff --git a/security/security.c b/security/security.c index 1cd8526cb0b7..133bc9915f18 100644 --- a/security/security.c +++ b/security/security.c @@ -1473,6 +1473,7 @@ void security_inet_conn_established(struct sock *sk, { call_void_hook(inet_conn_established, sk, skb); } +EXPORT_SYMBOL(security_inet_conn_established); int security_secmark_relabel_packet(u32 secid) { @@ -1528,6 +1529,27 @@ int security_tun_dev_open(void *security) } EXPORT_SYMBOL(security_tun_dev_open); +int security_sctp_assoc_request(struct sctp_endpoint *ep, struct sk_buff *skb) +{ + return call_int_hook(sctp_assoc_request, 0, ep, skb); +} +EXPORT_SYMBOL(security_sctp_assoc_request); + +int security_sctp_bind_connect(struct sock *sk, int optname, + struct sockaddr *address, int addrlen) +{ + return call_int_hook(sctp_bind_connect, 0, sk, optname, + address, addrlen); +} +EXPORT_SYMBOL(security_sctp_bind_connect); + +void security_sctp_sk_clone(struct sctp_endpoint *ep, struct sock *sk, + struct sock *newsk) +{ + call_void_hook(sctp_sk_clone, ep, sk, newsk); +} +EXPORT_SYMBOL(security_sctp_sk_clone); + #endif /* CONFIG_SECURITY_NETWORK */ #ifdef CONFIG_SECURITY_INFINIBAND -- cgit v1.2.3 From a1f2ba04cc92414b6b933289365eab878b0b2bf4 Mon Sep 17 00:00:00 2001 From: Sara Sharon Date: Mon, 19 Feb 2018 14:48:40 +0200 Subject: mac80211: add get TID helper Extracting the TID from the QOS header is common enough to justify helper. Signed-off-by: Sara Sharon Signed-off-by: Luca Coelho Signed-off-by: Johannes Berg --- include/linux/ieee80211.h | 12 ++++++++++++ net/mac80211/iface.c | 3 +-- net/mac80211/michael.c | 2 +- net/mac80211/mlme.c | 2 +- net/mac80211/rc80211_minstrel_ht.c | 2 +- net/mac80211/rx.c | 6 ++---- net/mac80211/tx.c | 9 ++------- net/mac80211/wpa.c | 8 +++----- 8 files changed, 23 insertions(+), 21 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index e4cba332b705..8fe7e4306816 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h @@ -8,6 +8,7 @@ * Copyright (c) 2006, Michael Wu * Copyright (c) 2013 - 2014 Intel Mobile Communications GmbH * Copyright (c) 2016 - 2017 Intel Deutschland GmbH + * Copyright (c) 2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -2501,6 +2502,17 @@ static inline u8 *ieee80211_get_qos_ctl(struct ieee80211_hdr *hdr) return (u8 *)hdr + 24; } +/** + * ieee80211_get_tid - get qos TID + * @hdr: the frame + */ +static inline u8 ieee80211_get_tid(struct ieee80211_hdr *hdr) +{ + u8 *qc = ieee80211_get_qos_ctl(hdr); + + return qc[0] & IEEE80211_QOS_CTL_TID_MASK; +} + /** * ieee80211_get_SA - get pointer to SA * @hdr: the frame diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c index 5fe01f82df12..d13ba064951f 100644 --- a/net/mac80211/iface.c +++ b/net/mac80211/iface.c @@ -1324,8 +1324,7 @@ static void ieee80211_iface_work(struct work_struct *work) mutex_lock(&local->sta_mtx); sta = sta_info_get_bss(sdata, mgmt->sa); if (sta) { - u16 tid = *ieee80211_get_qos_ctl(hdr) & - IEEE80211_QOS_CTL_TID_MASK; + u16 tid = ieee80211_get_tid(hdr); __ieee80211_stop_rx_ba_session( sta, tid, WLAN_BACK_RECIPIENT, diff --git a/net/mac80211/michael.c b/net/mac80211/michael.c index 408649bd4702..37e172701a63 100644 --- a/net/mac80211/michael.c +++ b/net/mac80211/michael.c @@ -35,7 +35,7 @@ static void michael_mic_hdr(struct michael_mic_ctx *mctx, const u8 *key, da = ieee80211_get_DA(hdr); sa = ieee80211_get_SA(hdr); if (ieee80211_is_data_qos(hdr->frame_control)) - tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; + tid = ieee80211_get_tid(hdr); else tid = 0; diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 39b660b9a908..010b127a3937 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -2151,7 +2151,7 @@ static void ieee80211_sta_tx_wmm_ac_notify(struct ieee80211_sub_if_data *sdata, u16 tx_time) { struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - u16 tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; + u16 tid = ieee80211_get_tid(hdr); int ac = ieee80211_ac_from_tid(tid); struct ieee80211_sta_tx_tspec *tx_tspec = &ifmgd->tx_tspec[ac]; unsigned long now = jiffies; diff --git a/net/mac80211/rc80211_minstrel_ht.c b/net/mac80211/rc80211_minstrel_ht.c index 4a5bdad9f303..fb586b6e5d49 100644 --- a/net/mac80211/rc80211_minstrel_ht.c +++ b/net/mac80211/rc80211_minstrel_ht.c @@ -669,7 +669,7 @@ minstrel_aggr_check(struct ieee80211_sta *pubsta, struct sk_buff *skb) if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) return; - tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; + tid = ieee80211_get_tid(hdr); if (likely(sta->ampdu_mlme.tid_tx[tid])) return; diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c index 478a9c735edb..3dc162ddc3a6 100644 --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c @@ -1189,7 +1189,7 @@ static void ieee80211_rx_reorder_ampdu(struct ieee80211_rx_data *rx, ack_policy = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_ACK_POLICY_MASK; - tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; + tid = ieee80211_get_tid(hdr); tid_agg_rx = rcu_dereference(sta->ampdu_mlme.tid_rx[tid]); if (!tid_agg_rx) { @@ -1528,9 +1528,7 @@ ieee80211_rx_h_uapsd_and_pspoll(struct ieee80211_rx_data *rx) ieee80211_has_pm(hdr->frame_control) && (ieee80211_is_data_qos(hdr->frame_control) || ieee80211_is_qos_nullfunc(hdr->frame_control))) { - u8 tid; - - tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; + u8 tid = ieee80211_get_tid(hdr); ieee80211_sta_uapsd_trigger(&rx->sta->sta, tid); } diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index 5decd0fb247c..7643178ef132 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c @@ -797,7 +797,6 @@ ieee80211_tx_h_sequence(struct ieee80211_tx_data *tx) { struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb); struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data; - u8 *qc; int tid; /* @@ -844,9 +843,7 @@ ieee80211_tx_h_sequence(struct ieee80211_tx_data *tx) return TX_CONTINUE; /* include per-STA, per-TID sequence counter */ - - qc = ieee80211_get_qos_ctl(hdr); - tid = *qc & IEEE80211_QOS_CTL_TID_MASK; + tid = ieee80211_get_tid(hdr); tx->sta->tx_stats.msdu[tid]++; hdr->seq_ctrl = ieee80211_tx_next_seq(tx->sta, tid); @@ -1158,7 +1155,6 @@ ieee80211_tx_prepare(struct ieee80211_sub_if_data *sdata, struct ieee80211_hdr *hdr; struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); int tid; - u8 *qc; memset(tx, 0, sizeof(*tx)); tx->skb = skb; @@ -1198,8 +1194,7 @@ ieee80211_tx_prepare(struct ieee80211_sub_if_data *sdata, !ieee80211_hw_check(&local->hw, TX_AMPDU_SETUP_IN_HW)) { struct tid_ampdu_tx *tid_tx; - qc = ieee80211_get_qos_ctl(hdr); - tid = *qc & IEEE80211_QOS_CTL_TID_MASK; + tid = ieee80211_get_tid(hdr); tid_tx = rcu_dereference(tx->sta->ampdu_mlme.tid_tx[tid]); if (tid_tx) { diff --git a/net/mac80211/wpa.c b/net/mac80211/wpa.c index 785056cb76f6..58d0b258b684 100644 --- a/net/mac80211/wpa.c +++ b/net/mac80211/wpa.c @@ -340,7 +340,7 @@ static void ccmp_special_blocks(struct sk_buff *skb, u8 *pn, u8 *b_0, u8 *aad) a4_included = ieee80211_has_a4(hdr->frame_control); if (ieee80211_is_data_qos(hdr->frame_control)) - qos_tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; + qos_tid = ieee80211_get_tid(hdr); else qos_tid = 0; @@ -601,8 +601,7 @@ static void gcmp_special_blocks(struct sk_buff *skb, u8 *pn, u8 *j_0, u8 *aad) aad[23] = 0; if (ieee80211_is_data_qos(hdr->frame_control)) - qos_tid = *ieee80211_get_qos_ctl(hdr) & - IEEE80211_QOS_CTL_TID_MASK; + qos_tid = ieee80211_get_tid(hdr); else qos_tid = 0; @@ -867,8 +866,7 @@ ieee80211_crypto_cs_decrypt(struct ieee80211_rx_data *rx) return RX_DROP_UNUSABLE; if (ieee80211_is_data_qos(hdr->frame_control)) - qos_tid = *ieee80211_get_qos_ctl(hdr) & - IEEE80211_QOS_CTL_TID_MASK; + qos_tid = ieee80211_get_tid(hdr); else qos_tid = 0; -- cgit v1.2.3 From d060b40523dcd91428c7fb2aaa307de37887484a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 22 Feb 2018 13:57:30 -0800 Subject: ARM: OMAP2+: Prepare to pass auxdata for smartreflex We are still initializing smartreflex with platform data using omap_device_build(). We can instead pass the platform data in with auxdata in pdata-quirks.c and make the driver use that in later patches. Note that we cannot enable the auxdata use yet, this is done in the last patch of the series. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 13 +++++++++++++ arch/arm/mach-omap2/sr_device.c | 2 ++ include/linux/power/smartreflex.h | 10 +++++++++- 3 files changed, 24 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6b433fce65a5..1cca66ad68b5 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -542,6 +543,8 @@ static struct pdata_init auxdata_quirks[] __initdata = { { /* sentinel */ }, }; +struct omap_sr_data __maybe_unused omap_sr_pdata[OMAP_SR_NR]; + static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { #ifdef CONFIG_MACH_NOKIA_N8X0 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), @@ -551,6 +554,10 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { #ifdef CONFIG_ARCH_OMAP3 OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu", &omap3_iommu_pdata), + OF_DEV_AUXDATA("ti,omap3-smartreflex-core", 0x480cb000, + "480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]), + OF_DEV_AUXDATA("ti,omap3-smartreflex-mpu-iva", 0x480c9000, + "480c9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]), OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x4809c000, "4809c000.mmc", &mmc_pdata[0]), OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]), OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_ir_data), @@ -580,6 +587,12 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu", &omap4_iommu_pdata), + OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000, + "4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]), + OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000, + "4a0dd000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]), + OF_DEV_AUXDATA("ti,omap4-smartreflex-mpu", 0x4a0d9000, + "4a0d9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]), #endif #ifdef CONFIG_SOC_DRA7XX OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc", diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index eef6935e0403..906b03b29c49 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -89,6 +89,8 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, sr_data->nvalue_count = j; } +extern struct omap_sr_data omap_sr_pdata[]; + static int __init sr_dev_init(struct omap_hwmod *oh, void *user) { struct omap_sr_data *sr_data; diff --git a/include/linux/power/smartreflex.h b/include/linux/power/smartreflex.h index d8b187c3925d..7b81dad712de 100644 --- a/include/linux/power/smartreflex.h +++ b/include/linux/power/smartreflex.h @@ -143,6 +143,13 @@ #define OMAP3430_SR_ERRWEIGHT 0x04 #define OMAP3430_SR_ERRMAXLIMIT 0x02 +enum sr_instance { + OMAP_SR_MPU, /* shared with iva on omap3 */ + OMAP_SR_CORE, + OMAP_SR_IVA, + OMAP_SR_NR, +}; + struct omap_sr { char *name; struct list_head node; @@ -207,7 +214,6 @@ struct omap_smartreflex_dev_attr { const char *sensor_voltdm_name; }; -#ifdef CONFIG_POWER_AVS_OMAP /* * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR. * The smartreflex class driver should pass the class type. @@ -290,6 +296,8 @@ struct omap_sr_data { struct voltagedomain *voltdm; }; +#ifdef CONFIG_POWER_AVS_OMAP + /* Smartreflex module enable/disable interface */ void omap_sr_enable(struct voltagedomain *voltdm); void omap_sr_disable(struct voltagedomain *voltdm); -- cgit v1.2.3 From 3ecac020d6dd09259414f423b577347ebee9f533 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 8 Feb 2018 23:20:35 +1100 Subject: PCI/AER: Move pci_uevent_ers() out of pci.h There's no reason pci_uevent_ers() needs to be inline in pci.h, so move it out to a C file. Given it's used by AER the obvious location would be somewhere in drivers/pci/pcie/aer, but because it's also used by powerpc EEH code unfortunately that doesn't work in the case where EEH is enabled but PCIEPORTBUS is not. So for now put it in pci-driver.c, next to pci_uevent(), with an appropriate #ifdef so it's not built if AER and EEH are both disabled. While we're moving it also fix up the kernel doc comment for @pdev to be accurate. Reported-by: Linus Torvalds Signed-off-by: Michael Ellerman Signed-off-by: Bjorn Helgaas Reviewed-by: Bryant G. Ly --- drivers/pci/pci-driver.c | 36 ++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 38 +++----------------------------------- 2 files changed, 39 insertions(+), 35 deletions(-) (limited to 'include/linux') diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 3bed6beda051..8876b98546ce 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -1517,6 +1517,42 @@ static int pci_uevent(struct device *dev, struct kobj_uevent_env *env) return 0; } +#if defined(CONFIG_PCIEAER) || defined(CONFIG_EEH) +/** + * pci_uevent_ers - emit a uevent during recovery path of PCI device + * @pdev: PCI device undergoing error recovery + * @err_type: type of error event + */ +void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type) +{ + int idx = 0; + char *envp[3]; + + switch (err_type) { + case PCI_ERS_RESULT_NONE: + case PCI_ERS_RESULT_CAN_RECOVER: + envp[idx++] = "ERROR_EVENT=BEGIN_RECOVERY"; + envp[idx++] = "DEVICE_ONLINE=0"; + break; + case PCI_ERS_RESULT_RECOVERED: + envp[idx++] = "ERROR_EVENT=SUCCESSFUL_RECOVERY"; + envp[idx++] = "DEVICE_ONLINE=1"; + break; + case PCI_ERS_RESULT_DISCONNECT: + envp[idx++] = "ERROR_EVENT=FAILED_RECOVERY"; + envp[idx++] = "DEVICE_ONLINE=0"; + break; + default: + break; + } + + if (idx > 0) { + envp[idx++] = NULL; + kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, envp); + } +} +#endif + static int pci_bus_num_vf(struct device *dev) { return pci_num_vf(to_pci_dev(dev)); diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1beda008..19c1dbcff0c6 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2280,41 +2280,9 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) return false; } -/** - * pci_uevent_ers - emit a uevent during recovery path of pci device - * @pdev: pci device to check - * @err_type: type of error event - * - */ -static inline void pci_uevent_ers(struct pci_dev *pdev, - enum pci_ers_result err_type) -{ - int idx = 0; - char *envp[3]; - - switch (err_type) { - case PCI_ERS_RESULT_NONE: - case PCI_ERS_RESULT_CAN_RECOVER: - envp[idx++] = "ERROR_EVENT=BEGIN_RECOVERY"; - envp[idx++] = "DEVICE_ONLINE=0"; - break; - case PCI_ERS_RESULT_RECOVERED: - envp[idx++] = "ERROR_EVENT=SUCCESSFUL_RECOVERY"; - envp[idx++] = "DEVICE_ONLINE=1"; - break; - case PCI_ERS_RESULT_DISCONNECT: - envp[idx++] = "ERROR_EVENT=FAILED_RECOVERY"; - envp[idx++] = "DEVICE_ONLINE=0"; - break; - default: - break; - } - - if (idx > 0) { - envp[idx++] = NULL; - kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, envp); - } -} +#if defined(CONFIG_PCIEAER) || defined(CONFIG_EEH) +void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); +#endif /* Provide the legacy pci_dma_* API */ #include -- cgit v1.2.3 From c37e627f9565368ed7bd1f3cf59a2d223ddba85a Mon Sep 17 00:00:00 2001 From: Frederick Lawler Date: Tue, 13 Feb 2018 21:52:18 -0600 Subject: PCI/portdrv: Move pcieport_if.h to drivers/pci/pcie/ Move pcieport_if.h from include/linux to drivers/pci/pcie/pcieport_if.h because the interfaces there are only used by the PCI core. Replace all uses of #include with relative paths to the new file location, e.g., #include "../pcieport_if.h" Signed-off-by: Frederick Lawler Signed-off-by: Bjorn Helgaas --- drivers/pci/hotplug/pciehp.h | 3 +- drivers/pci/pcie/aer/aerdrv.c | 1 - drivers/pci/pcie/aer/aerdrv.h | 3 +- drivers/pci/pcie/pcie-dpc.c | 3 +- drivers/pci/pcie/pcieport_if.h | 71 +++++++++++++++++++++++++++++++++++++++++ drivers/pci/pcie/pme.c | 2 +- drivers/pci/pcie/portdrv_acpi.c | 2 +- drivers/pci/pcie/portdrv_bus.c | 2 +- drivers/pci/pcie/portdrv_core.c | 2 +- drivers/pci/pcie/portdrv_pci.c | 2 +- include/linux/pcieport_if.h | 71 ----------------------------------------- 11 files changed, 82 insertions(+), 80 deletions(-) create mode 100644 drivers/pci/pcie/pcieport_if.h delete mode 100644 include/linux/pcieport_if.h (limited to 'include/linux') diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 636ed8f4b869..08072bcaa381 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -20,10 +20,11 @@ #include #include #include /* signal_pending() */ -#include #include #include +#include "../pcie/pcieport_if.h" + #define MY_NAME "pciehp" extern bool pciehp_poll_mode; diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index da8331f5684d..28329e16ad8f 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "aerdrv.h" diff --git a/drivers/pci/pcie/aer/aerdrv.h b/drivers/pci/pcie/aer/aerdrv.h index 5449e5ce139d..568326f385b7 100644 --- a/drivers/pci/pcie/aer/aerdrv.h +++ b/drivers/pci/pcie/aer/aerdrv.h @@ -10,10 +10,11 @@ #define _AERDRV_H_ #include -#include #include #include +#include "../pcieport_if.h" + #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \ PCI_EXP_RTCTL_SENFEE| \ PCI_EXP_RTCTL_SEFEE) diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c index 38e40c6c576f..bac895de4c72 100644 --- a/drivers/pci/pcie/pcie-dpc.c +++ b/drivers/pci/pcie/pcie-dpc.c @@ -10,7 +10,8 @@ #include #include #include -#include + +#include "pcieport_if.h" #include "../pci.h" #include "aer/aerdrv.h" diff --git a/drivers/pci/pcie/pcieport_if.h b/drivers/pci/pcie/pcieport_if.h new file mode 100644 index 000000000000..b69769dbf659 --- /dev/null +++ b/drivers/pci/pcie/pcieport_if.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * File: pcieport_if.h + * Purpose: PCI Express Port Bus Driver's IF Data Structure + * + * Copyright (C) 2004 Intel + * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) + */ + +#ifndef _PCIEPORT_IF_H_ +#define _PCIEPORT_IF_H_ + +/* Port Type */ +#define PCIE_ANY_PORT (~0) + +/* Service Type */ +#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */ +#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT) +#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */ +#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT) +#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */ +#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT) +#define PCIE_PORT_SERVICE_VC_SHIFT 3 /* Virtual Channel */ +#define PCIE_PORT_SERVICE_VC (1 << PCIE_PORT_SERVICE_VC_SHIFT) +#define PCIE_PORT_SERVICE_DPC_SHIFT 4 /* Downstream Port Containment */ +#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT) + +struct pcie_device { + int irq; /* Service IRQ/MSI/MSI-X Vector */ + struct pci_dev *port; /* Root/Upstream/Downstream Port */ + u32 service; /* Port service this device represents */ + void *priv_data; /* Service Private Data */ + struct device device; /* Generic Device Interface */ +}; +#define to_pcie_device(d) container_of(d, struct pcie_device, device) + +static inline void set_service_data(struct pcie_device *dev, void *data) +{ + dev->priv_data = data; +} + +static inline void *get_service_data(struct pcie_device *dev) +{ + return dev->priv_data; +} + +struct pcie_port_service_driver { + const char *name; + int (*probe) (struct pcie_device *dev); + void (*remove) (struct pcie_device *dev); + int (*suspend) (struct pcie_device *dev); + int (*resume) (struct pcie_device *dev); + + /* Device driver may resume normal operations */ + void (*error_resume)(struct pci_dev *dev); + + /* Link Reset Capability - AER service driver specific */ + pci_ers_result_t (*reset_link) (struct pci_dev *dev); + + int port_type; /* Type of the port this driver can handle */ + u32 service; /* Port service this device represents */ + + struct device_driver driver; +}; +#define to_service_driver(d) \ + container_of(d, struct pcie_port_service_driver, driver) + +int pcie_port_service_register(struct pcie_port_service_driver *new); +void pcie_port_service_unregister(struct pcie_port_service_driver *new); + +#endif /* _PCIEPORT_IF_H_ */ diff --git a/drivers/pci/pcie/pme.c b/drivers/pci/pcie/pme.c index 5480f54f7612..d29678958d92 100644 --- a/drivers/pci/pcie/pme.c +++ b/drivers/pci/pcie/pme.c @@ -14,9 +14,9 @@ #include #include #include -#include #include +#include "pcieport_if.h" #include "../pci.h" #include "portdrv.h" diff --git a/drivers/pci/pcie/portdrv_acpi.c b/drivers/pci/pcie/portdrv_acpi.c index 319c94976873..c7d8debb4a5c 100644 --- a/drivers/pci/pcie/portdrv_acpi.c +++ b/drivers/pci/pcie/portdrv_acpi.c @@ -10,8 +10,8 @@ #include #include #include -#include +#include "pcieport_if.h" #include "aer/aerdrv.h" #include "../pci.h" #include "portdrv.h" diff --git a/drivers/pci/pcie/portdrv_bus.c b/drivers/pci/pcie/portdrv_bus.c index f0fba552a0e2..b5c5697cfb30 100644 --- a/drivers/pci/pcie/portdrv_bus.c +++ b/drivers/pci/pcie/portdrv_bus.c @@ -13,7 +13,7 @@ #include #include -#include +#include "pcieport_if.h" #include "portdrv.h" static int pcie_port_bus_match(struct device *dev, struct device_driver *drv); diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index ef3bad4ad010..bab9cb71130f 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -15,9 +15,9 @@ #include #include #include -#include #include +#include "pcieport_if.h" #include "../pci.h" #include "portdrv.h" diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c index fb1c1bb87316..13dbe846a1d1 100644 --- a/drivers/pci/pcie/portdrv_pci.c +++ b/drivers/pci/pcie/portdrv_pci.c @@ -15,11 +15,11 @@ #include #include #include -#include #include #include #include +#include "pcieport_if.h" #include "../pci.h" #include "portdrv.h" diff --git a/include/linux/pcieport_if.h b/include/linux/pcieport_if.h deleted file mode 100644 index b69769dbf659..000000000000 --- a/include/linux/pcieport_if.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * File: pcieport_if.h - * Purpose: PCI Express Port Bus Driver's IF Data Structure - * - * Copyright (C) 2004 Intel - * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) - */ - -#ifndef _PCIEPORT_IF_H_ -#define _PCIEPORT_IF_H_ - -/* Port Type */ -#define PCIE_ANY_PORT (~0) - -/* Service Type */ -#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */ -#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT) -#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */ -#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT) -#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */ -#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT) -#define PCIE_PORT_SERVICE_VC_SHIFT 3 /* Virtual Channel */ -#define PCIE_PORT_SERVICE_VC (1 << PCIE_PORT_SERVICE_VC_SHIFT) -#define PCIE_PORT_SERVICE_DPC_SHIFT 4 /* Downstream Port Containment */ -#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT) - -struct pcie_device { - int irq; /* Service IRQ/MSI/MSI-X Vector */ - struct pci_dev *port; /* Root/Upstream/Downstream Port */ - u32 service; /* Port service this device represents */ - void *priv_data; /* Service Private Data */ - struct device device; /* Generic Device Interface */ -}; -#define to_pcie_device(d) container_of(d, struct pcie_device, device) - -static inline void set_service_data(struct pcie_device *dev, void *data) -{ - dev->priv_data = data; -} - -static inline void *get_service_data(struct pcie_device *dev) -{ - return dev->priv_data; -} - -struct pcie_port_service_driver { - const char *name; - int (*probe) (struct pcie_device *dev); - void (*remove) (struct pcie_device *dev); - int (*suspend) (struct pcie_device *dev); - int (*resume) (struct pcie_device *dev); - - /* Device driver may resume normal operations */ - void (*error_resume)(struct pci_dev *dev); - - /* Link Reset Capability - AER service driver specific */ - pci_ers_result_t (*reset_link) (struct pci_dev *dev); - - int port_type; /* Type of the port this driver can handle */ - u32 service; /* Port service this device represents */ - - struct device_driver driver; -}; -#define to_service_driver(d) \ - container_of(d, struct pcie_port_service_driver, driver) - -int pcie_port_service_register(struct pcie_port_service_driver *new); -void pcie_port_service_unregister(struct pcie_port_service_driver *new); - -#endif /* _PCIEPORT_IF_H_ */ -- cgit v1.2.3 From 4ef76ad0462cf25ce948541c8724eaa8a8365e1d Mon Sep 17 00:00:00 2001 From: Feng Kan Date: Tue, 20 Feb 2018 19:19:27 -0800 Subject: PCI: Add ACS quirk for Ampere root ports The Ampere Computing PCIe root port does not support ACS at this point. However, the hardware provides isolation and source validation through the SMMU. The stream ID generated by the PCIe ports contain both the bus/device/function number as well as the port ID in its 3 most significant bits. Turn on ACS but disable all the peer-to-peer features. APM is being rebranded to Ampere. The Vendor and Device IDs change, but the functionality stays the same. Signed-off-by: Feng Kan Signed-off-by: Bjorn Helgaas --- drivers/pci/quirks.c | 9 +++++++++ include/linux/pci_ids.h | 1 + 2 files changed, 10 insertions(+) (limited to 'include/linux') diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index fc734014206f..57748a3b83f0 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4514,6 +4514,15 @@ static const struct pci_dev_acs_enabled { { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, /* APM X-Gene */ { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, + /* Ampere Computing */ + { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, { 0 } }; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a6b30667a331..c875d4223f44 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -1333,6 +1333,7 @@ #define PCI_DEVICE_ID_IMS_TT3D 0x9135 #define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_VENDOR_ID_AMPERE 0x1def #define PCI_VENDOR_ID_INTERG 0x10ea #define PCI_DEVICE_ID_INTERG_1682 0x1682 -- cgit v1.2.3 From 492a1abd61e4b4f78c1c5804840a304a9e32da04 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 22 Feb 2018 14:59:20 +0200 Subject: dmi: Introduce the dmi_get_bios_year() helper function The pattern to only extract the year portion of date is used in several places and more users may come. By using this helper they may create slightly cleaner code. Signed-off-by: Andy Shevchenko [ Minor stylistic cleanup. ] Cc: Bjorn Helgaas Cc: Jean Delvare Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Thomas Gleixner Cc: linux-acpi@vger.kernel.org Cc: linux-pci@vger.kernel.org Link: http://lkml.kernel.org/r/20180222125923.57385-1-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar --- include/linux/dmi.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/linux') diff --git a/include/linux/dmi.h b/include/linux/dmi.h index 46e151172d95..0bade156e908 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -147,4 +147,13 @@ static inline const struct dmi_system_id * #endif +static inline int dmi_get_bios_year(void) +{ + int year; + + dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL); + + return year; +} + #endif /* __DMI_H__ */ -- cgit v1.2.3 From 5f171577b4f35b44795a73bde8cf2c49b4073925 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 24 Oct 2017 16:52:32 +0100 Subject: Drop a bunch of metag references Now that arch/metag/ has been removed, drop a bunch of metag references in various codes across the whole tree: - VM_GROWSUP and __VM_ARCH_SPECIFIC_1. - MT_METAG_* ELF note types. - METAG Kconfig dependencies (FRAME_POINTER) and ranges (MAX_STACK_SIZE_MB). - metag cases in tools (checkstack.pl, recordmcount.c, perf). Signed-off-by: James Hogan Acked-by: Steven Rostedt (VMware) Acked-by: Peter Zijlstra (Intel) Reviewed-by: Guenter Roeck Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: linux-mm@kvack.org Cc: linux-metag@vger.kernel.org --- include/linux/cpuhotplug.h | 1 - include/linux/mm.h | 2 -- include/trace/events/mmflags.h | 2 +- include/uapi/linux/elf.h | 3 --- lib/Kconfig.debug | 2 +- mm/Kconfig | 7 +++---- scripts/checkstack.pl | 4 ---- scripts/recordmcount.c | 20 -------------------- tools/perf/perf-sys.h | 4 ---- 9 files changed, 5 insertions(+), 40 deletions(-) (limited to 'include/linux') diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 5172ad0daa7c..c7a950681f3a 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -108,7 +108,6 @@ enum cpuhp_state { CPUHP_AP_PERF_X86_CQM_STARTING, CPUHP_AP_PERF_X86_CSTATE_STARTING, CPUHP_AP_PERF_XTENSA_STARTING, - CPUHP_AP_PERF_METAG_STARTING, CPUHP_AP_MIPS_OP_LOONGSON3_STARTING, CPUHP_AP_ARM_SDEI_STARTING, CPUHP_AP_ARM_VFP_STARTING, diff --git a/include/linux/mm.h b/include/linux/mm.h index ad06d42adb1a..ccac10682ce5 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -241,8 +241,6 @@ extern unsigned int kobjsize(const void *objp); # define VM_SAO VM_ARCH_1 /* Strong Access Ordering (powerpc) */ #elif defined(CONFIG_PARISC) # define VM_GROWSUP VM_ARCH_1 -#elif defined(CONFIG_METAG) -# define VM_GROWSUP VM_ARCH_1 #elif defined(CONFIG_IA64) # define VM_GROWSUP VM_ARCH_1 #elif !defined(CONFIG_MMU) diff --git a/include/trace/events/mmflags.h b/include/trace/events/mmflags.h index dbe1bb058c09..a81cffb76d89 100644 --- a/include/trace/events/mmflags.h +++ b/include/trace/events/mmflags.h @@ -115,7 +115,7 @@ IF_HAVE_PG_IDLE(PG_idle, "idle" ) #define __VM_ARCH_SPECIFIC_1 {VM_PAT, "pat" } #elif defined(CONFIG_PPC) #define __VM_ARCH_SPECIFIC_1 {VM_SAO, "sao" } -#elif defined(CONFIG_PARISC) || defined(CONFIG_METAG) || defined(CONFIG_IA64) +#elif defined(CONFIG_PARISC) || defined(CONFIG_IA64) #define __VM_ARCH_SPECIFIC_1 {VM_GROWSUP, "growsup" } #elif !defined(CONFIG_MMU) #define __VM_ARCH_SPECIFIC_1 {VM_MAPPED_COPY,"mappedcopy" } diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 3bf73fb58045..e2535d6dcec7 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -420,9 +420,6 @@ typedef struct elf64_shdr { #define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */ #define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */ #define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension registers */ -#define NT_METAG_CBUF 0x500 /* Metag catch buffer registers */ -#define NT_METAG_RPIPE 0x501 /* Metag read pipeline state */ -#define NT_METAG_TLS 0x502 /* Metag TLS pointer */ #define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */ /* Note header in a PT_NOTE section */ diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 6088408ef26c..d1c523e408e9 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -356,7 +356,7 @@ config FRAME_POINTER bool "Compile the kernel with frame pointers" depends on DEBUG_KERNEL && \ (CRIS || M68K || FRV || UML || \ - SUPERH || BLACKFIN || MN10300 || METAG) || \ + SUPERH || BLACKFIN || MN10300) || \ ARCH_WANT_FRAME_POINTERS default y if (DEBUG_INFO && UML) || ARCH_WANT_FRAME_POINTERS help diff --git a/mm/Kconfig b/mm/Kconfig index c782e8fb7235..abefa573bcd8 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -627,15 +627,14 @@ config GENERIC_EARLY_IOREMAP config MAX_STACK_SIZE_MB int "Maximum user stack size for 32-bit processes (MB)" default 80 - range 8 256 if METAG range 8 2048 depends on STACK_GROWSUP && (!64BIT || COMPAT) help This is the maximum stack size in Megabytes in the VM layout of 32-bit user processes when the stack grows upwards (currently only on parisc - and metag arch). The stack will be located at the highest memory - address minus the given value, unless the RLIMIT_STACK hard limit is - changed to a smaller value in which case that is used. + arch). The stack will be located at the highest memory address minus + the given value, unless the RLIMIT_STACK hard limit is changed to a + smaller value in which case that is used. A sane initial value is 80 MB. diff --git a/scripts/checkstack.pl b/scripts/checkstack.pl index cb993801e4b2..eeb9ac8dbcfb 100755 --- a/scripts/checkstack.pl +++ b/scripts/checkstack.pl @@ -64,10 +64,6 @@ my (@stack, $re, $dre, $x, $xs, $funcre); # 2b6c: 4e56 fb70 linkw %fp,#-1168 # 1df770: defc ffe4 addaw #-28,%sp $re = qr/.*(?:linkw %fp,|addaw )#-([0-9]{1,4})(?:,%sp)?$/o; - } elsif ($arch eq 'metag') { - #400026fc: 40 00 00 82 ADD A0StP,A0StP,#0x8 - $re = qr/.*ADD.*A0StP,A0StP,\#(0x$x{1,8})/o; - $funcre = qr/^$x* <[^\$](.*)>:$/; } elsif ($arch eq 'mips64') { #8800402c: 67bdfff0 daddiu sp,sp,-16 $re = qr/.*daddiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o; diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c index 16e086dcc567..8c9691c3329e 100644 --- a/scripts/recordmcount.c +++ b/scripts/recordmcount.c @@ -33,20 +33,6 @@ #include #include -/* - * glibc synced up and added the metag number but didn't add the relocations. - * Work around this in a crude manner for now. - */ -#ifndef EM_METAG -#define EM_METAG 174 -#endif -#ifndef R_METAG_ADDR32 -#define R_METAG_ADDR32 2 -#endif -#ifndef R_METAG_NONE -#define R_METAG_NONE 3 -#endif - #ifndef EM_AARCH64 #define EM_AARCH64 183 #define R_AARCH64_NONE 0 @@ -538,12 +524,6 @@ do_file(char const *const fname) gpfx = '_'; break; case EM_IA_64: reltype = R_IA64_IMM64; gpfx = '_'; break; - case EM_METAG: reltype = R_METAG_ADDR32; - altmcount = "_mcount_wrapper"; - rel_type_nop = R_METAG_NONE; - /* We happen to have the same requirement as MIPS */ - is_fake_mcount32 = MIPS32_is_fake_mcount; - break; case EM_MIPS: /* reltype: e_class */ gpfx = '_'; break; case EM_PPC: reltype = R_PPC_ADDR32; gpfx = '_'; break; case EM_PPC64: reltype = R_PPC64_ADDR64; gpfx = '_'; break; diff --git a/tools/perf/perf-sys.h b/tools/perf/perf-sys.h index 36673f98d66b..3eb7a39169f6 100644 --- a/tools/perf/perf-sys.h +++ b/tools/perf/perf-sys.h @@ -46,10 +46,6 @@ #define CPUINFO_PROC {"Processor"} #endif -#ifdef __metag__ -#define CPUINFO_PROC {"CPU"} -#endif - #ifdef __xtensa__ #define CPUINFO_PROC {"core ID"} #endif -- cgit v1.2.3 From df46bb1909d92eedccd4216c88e43f75cb0b2901 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 21 Feb 2018 15:31:32 +0000 Subject: irqchip: Remove metag irqchip drivers Now that arch/metag/ has been removed, remove the two metag irqchip drivers. They are of no value without the architecture code. - irq-metag: Meta internal (HWSTATMETA) interrupt code. - irq-metag-ext: Meta External interrupt code. Signed-off-by: James Hogan Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: linux-metag@vger.kernel.org --- drivers/irqchip/Makefile | 2 - drivers/irqchip/irq-metag-ext.c | 871 -------------------------------------- drivers/irqchip/irq-metag.c | 343 --------------- include/linux/irqchip/metag-ext.h | 34 -- include/linux/irqchip/metag.h | 25 -- 5 files changed, 1275 deletions(-) delete mode 100644 drivers/irqchip/irq-metag-ext.c delete mode 100644 drivers/irqchip/irq-metag.c delete mode 100644 include/linux/irqchip/metag-ext.h delete mode 100644 include/linux/irqchip/metag.h (limited to 'include/linux') diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index d27e3e3619e0..b5b1f4c93413 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -15,8 +15,6 @@ obj-$(CONFIG_IRQ_MXS) += irq-mxs.o obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o -obj-$(CONFIG_METAG) += irq-metag-ext.o -obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o obj-$(CONFIG_OMPIC) += irq-ompic.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o diff --git a/drivers/irqchip/irq-metag-ext.c b/drivers/irqchip/irq-metag-ext.c deleted file mode 100644 index e67483161f0f..000000000000 --- a/drivers/irqchip/irq-metag-ext.c +++ /dev/null @@ -1,871 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Meta External interrupt code. - * - * Copyright (C) 2005-2012 Imagination Technologies Ltd. - * - * External interrupts on Meta are configured at two-levels, in the CPU core and - * in the external trigger block. Interrupts from SoC peripherals are - * multiplexed onto a single Meta CPU "trigger" - traditionally it has always - * been trigger 2 (TR2). For info on how de-multiplexing happens check out - * meta_intc_irq_demux(). - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define HWSTAT_STRIDE 8 -#define HWVEC_BLK_STRIDE 0x1000 - -/** - * struct meta_intc_priv - private meta external interrupt data - * @nr_banks: Number of interrupt banks - * @domain: IRQ domain for all banks of external IRQs - * @unmasked: Record of unmasked IRQs - * @levels_altered: Record of altered level bits - */ -struct meta_intc_priv { - unsigned int nr_banks; - struct irq_domain *domain; - - unsigned long unmasked[4]; - -#ifdef CONFIG_METAG_SUSPEND_MEM - unsigned long levels_altered[4]; -#endif -}; - -/* Private data for the one and only external interrupt controller */ -static struct meta_intc_priv meta_intc_priv; - -/** - * meta_intc_offset() - Get the offset into the bank of a hardware IRQ number - * @hw: Hardware IRQ number (within external trigger block) - * - * Returns: Bit offset into the IRQ's bank registers - */ -static unsigned int meta_intc_offset(irq_hw_number_t hw) -{ - return hw & 0x1f; -} - -/** - * meta_intc_bank() - Get the bank number of a hardware IRQ number - * @hw: Hardware IRQ number (within external trigger block) - * - * Returns: Bank number indicating which register the IRQ's bits are - */ -static unsigned int meta_intc_bank(irq_hw_number_t hw) -{ - return hw >> 5; -} - -/** - * meta_intc_stat_addr() - Get the address of a HWSTATEXT register - * @hw: Hardware IRQ number (within external trigger block) - * - * Returns: Address of a HWSTATEXT register containing the status bit for - * the specified hardware IRQ number - */ -static void __iomem *meta_intc_stat_addr(irq_hw_number_t hw) -{ - return (void __iomem *)(HWSTATEXT + - HWSTAT_STRIDE * meta_intc_bank(hw)); -} - -/** - * meta_intc_level_addr() - Get the address of a HWLEVELEXT register - * @hw: Hardware IRQ number (within external trigger block) - * - * Returns: Address of a HWLEVELEXT register containing the sense bit for - * the specified hardware IRQ number - */ -static void __iomem *meta_intc_level_addr(irq_hw_number_t hw) -{ - return (void __iomem *)(HWLEVELEXT + - HWSTAT_STRIDE * meta_intc_bank(hw)); -} - -/** - * meta_intc_mask_addr() - Get the address of a HWMASKEXT register - * @hw: Hardware IRQ number (within external trigger block) - * - * Returns: Address of a HWMASKEXT register containing the mask bit for the - * specified hardware IRQ number - */ -static void __iomem *meta_intc_mask_addr(irq_hw_number_t hw) -{ - return (void __iomem *)(HWMASKEXT + - HWSTAT_STRIDE * meta_intc_bank(hw)); -} - -/** - * meta_intc_vec_addr() - Get the vector address of a hardware interrupt - * @hw: Hardware IRQ number (within external trigger block) - * - * Returns: Address of a HWVECEXT register controlling the core trigger to - * vector the IRQ onto - */ -static inline void __iomem *meta_intc_vec_addr(irq_hw_number_t hw) -{ - return (void __iomem *)(HWVEC0EXT + - HWVEC_BLK_STRIDE * meta_intc_bank(hw) + - HWVECnEXT_STRIDE * meta_intc_offset(hw)); -} - -/** - * meta_intc_startup_irq() - set up an external irq - * @data: data for the external irq to start up - * - * Multiplex interrupts for irq onto TR2. Clear any pending interrupts and - * unmask irq, both using the appropriate callbacks. - */ -static unsigned int meta_intc_startup_irq(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - void __iomem *vec_addr = meta_intc_vec_addr(hw); - int thread = hard_processor_id(); - - /* Perform any necessary acking. */ - if (data->chip->irq_ack) - data->chip->irq_ack(data); - - /* Wire up this interrupt to the core with HWVECxEXT. */ - metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr); - - /* Perform any necessary unmasking. */ - data->chip->irq_unmask(data); - - return 0; -} - -/** - * meta_intc_shutdown_irq() - turn off an external irq - * @data: data for the external irq to turn off - * - * Mask irq using the appropriate callback and stop muxing it onto TR2. - */ -static void meta_intc_shutdown_irq(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - void __iomem *vec_addr = meta_intc_vec_addr(hw); - - /* Mask the IRQ */ - data->chip->irq_mask(data); - - /* - * Disable the IRQ at the core by removing the interrupt from - * the HW vector mapping. - */ - metag_out32(0, vec_addr); -} - -/** - * meta_intc_ack_irq() - acknowledge an external irq - * @data: data for the external irq to ack - * - * Clear down an edge interrupt in the status register. - */ -static void meta_intc_ack_irq(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << meta_intc_offset(hw); - void __iomem *stat_addr = meta_intc_stat_addr(hw); - - /* Ack the int, if it is still 'on'. - * NOTE - this only works for edge triggered interrupts. - */ - if (metag_in32(stat_addr) & bit) - metag_out32(bit, stat_addr); -} - -/** - * record_irq_is_masked() - record the IRQ masked so it doesn't get handled - * @data: data for the external irq to record - * - * This should get called whenever an external IRQ is masked (by whichever - * callback is used). It records the IRQ masked so that it doesn't get handled - * if it still shows up in the status register. - */ -static void record_irq_is_masked(struct irq_data *data) -{ - struct meta_intc_priv *priv = &meta_intc_priv; - irq_hw_number_t hw = data->hwirq; - - clear_bit(meta_intc_offset(hw), &priv->unmasked[meta_intc_bank(hw)]); -} - -/** - * record_irq_is_unmasked() - record the IRQ unmasked so it can be handled - * @data: data for the external irq to record - * - * This should get called whenever an external IRQ is unmasked (by whichever - * callback is used). It records the IRQ unmasked so that it gets handled if it - * shows up in the status register. - */ -static void record_irq_is_unmasked(struct irq_data *data) -{ - struct meta_intc_priv *priv = &meta_intc_priv; - irq_hw_number_t hw = data->hwirq; - - set_bit(meta_intc_offset(hw), &priv->unmasked[meta_intc_bank(hw)]); -} - -/* - * For use by wrapper IRQ drivers - */ - -/** - * meta_intc_mask_irq_simple() - minimal mask used by wrapper IRQ drivers - * @data: data for the external irq being masked - * - * This should be called by any wrapper IRQ driver mask functions. it doesn't do - * any masking but records the IRQ as masked so that the core code knows the - * mask has taken place. It is the callers responsibility to ensure that the IRQ - * won't trigger an interrupt to the core. - */ -void meta_intc_mask_irq_simple(struct irq_data *data) -{ - record_irq_is_masked(data); -} - -/** - * meta_intc_unmask_irq_simple() - minimal unmask used by wrapper IRQ drivers - * @data: data for the external irq being unmasked - * - * This should be called by any wrapper IRQ driver unmask functions. it doesn't - * do any unmasking but records the IRQ as unmasked so that the core code knows - * the unmask has taken place. It is the callers responsibility to ensure that - * the IRQ can now trigger an interrupt to the core. - */ -void meta_intc_unmask_irq_simple(struct irq_data *data) -{ - record_irq_is_unmasked(data); -} - - -/** - * meta_intc_mask_irq() - mask an external irq using HWMASKEXT - * @data: data for the external irq to mask - * - * This is a default implementation of a mask function which makes use of the - * HWMASKEXT registers available in newer versions. - * - * Earlier versions without these registers should use SoC level IRQ masking - * which call the meta_intc_*_simple() functions above, or if that isn't - * available should use the fallback meta_intc_*_nomask() functions below. - */ -static void meta_intc_mask_irq(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << meta_intc_offset(hw); - void __iomem *mask_addr = meta_intc_mask_addr(hw); - unsigned long flags; - - record_irq_is_masked(data); - - /* update the interrupt mask */ - __global_lock2(flags); - metag_out32(metag_in32(mask_addr) & ~bit, mask_addr); - __global_unlock2(flags); -} - -/** - * meta_intc_unmask_irq() - unmask an external irq using HWMASKEXT - * @data: data for the external irq to unmask - * - * This is a default implementation of an unmask function which makes use of the - * HWMASKEXT registers available on new versions. It should be paired with - * meta_intc_mask_irq() above. - */ -static void meta_intc_unmask_irq(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << meta_intc_offset(hw); - void __iomem *mask_addr = meta_intc_mask_addr(hw); - unsigned long flags; - - record_irq_is_unmasked(data); - - /* update the interrupt mask */ - __global_lock2(flags); - metag_out32(metag_in32(mask_addr) | bit, mask_addr); - __global_unlock2(flags); -} - -/** - * meta_intc_mask_irq_nomask() - mask an external irq by unvectoring - * @data: data for the external irq to mask - * - * This is the version of the mask function for older versions which don't have - * HWMASKEXT registers, or a SoC level means of masking IRQs. Instead the IRQ is - * unvectored from the core and retriggered if necessary later. - */ -static void meta_intc_mask_irq_nomask(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - void __iomem *vec_addr = meta_intc_vec_addr(hw); - - record_irq_is_masked(data); - - /* there is no interrupt mask, so unvector the interrupt */ - metag_out32(0, vec_addr); -} - -/** - * meta_intc_unmask_edge_irq_nomask() - unmask an edge irq by revectoring - * @data: data for the external irq to unmask - * - * This is the version of the unmask function for older versions which don't - * have HWMASKEXT registers, or a SoC level means of masking IRQs. Instead the - * IRQ is revectored back to the core and retriggered if necessary. - * - * The retriggering done by this function is specific to edge interrupts. - */ -static void meta_intc_unmask_edge_irq_nomask(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << meta_intc_offset(hw); - void __iomem *stat_addr = meta_intc_stat_addr(hw); - void __iomem *vec_addr = meta_intc_vec_addr(hw); - unsigned int thread = hard_processor_id(); - - record_irq_is_unmasked(data); - - /* there is no interrupt mask, so revector the interrupt */ - metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr); - - /* - * Re-trigger interrupt - * - * Writing a 1 toggles, and a 0->1 transition triggers. We only - * retrigger if the status bit is already set, which means we - * need to clear it first. Retriggering is fundamentally racy - * because if the interrupt fires again after we clear it we - * could end up clearing it again and the interrupt handler - * thinking it hasn't fired. Therefore we need to keep trying to - * retrigger until the bit is set. - */ - if (metag_in32(stat_addr) & bit) { - metag_out32(bit, stat_addr); - while (!(metag_in32(stat_addr) & bit)) - metag_out32(bit, stat_addr); - } -} - -/** - * meta_intc_unmask_level_irq_nomask() - unmask a level irq by revectoring - * @data: data for the external irq to unmask - * - * This is the version of the unmask function for older versions which don't - * have HWMASKEXT registers, or a SoC level means of masking IRQs. Instead the - * IRQ is revectored back to the core and retriggered if necessary. - * - * The retriggering done by this function is specific to level interrupts. - */ -static void meta_intc_unmask_level_irq_nomask(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << meta_intc_offset(hw); - void __iomem *stat_addr = meta_intc_stat_addr(hw); - void __iomem *vec_addr = meta_intc_vec_addr(hw); - unsigned int thread = hard_processor_id(); - - record_irq_is_unmasked(data); - - /* there is no interrupt mask, so revector the interrupt */ - metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr); - - /* Re-trigger interrupt */ - /* Writing a 1 triggers interrupt */ - if (metag_in32(stat_addr) & bit) - metag_out32(bit, stat_addr); -} - -/** - * meta_intc_irq_set_type() - set the type of an external irq - * @data: data for the external irq to set the type of - * @flow_type: new irq flow type - * - * Set the flow type of an external interrupt. This updates the irq chip and irq - * handler depending on whether the irq is edge or level sensitive (the polarity - * is ignored), and also sets up the bit in HWLEVELEXT so the hardware knows - * when to trigger. - */ -static int meta_intc_irq_set_type(struct irq_data *data, unsigned int flow_type) -{ -#ifdef CONFIG_METAG_SUSPEND_MEM - struct meta_intc_priv *priv = &meta_intc_priv; -#endif - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << meta_intc_offset(hw); - void __iomem *level_addr = meta_intc_level_addr(hw); - unsigned long flags; - unsigned int level; - - /* update the chip/handler */ - if (flow_type & IRQ_TYPE_LEVEL_MASK) - irq_set_chip_handler_name_locked(data, &meta_intc_level_chip, - handle_level_irq, NULL); - else - irq_set_chip_handler_name_locked(data, &meta_intc_edge_chip, - handle_edge_irq, NULL); - - /* and clear/set the bit in HWLEVELEXT */ - __global_lock2(flags); - level = metag_in32(level_addr); - if (flow_type & IRQ_TYPE_LEVEL_MASK) - level |= bit; - else - level &= ~bit; - metag_out32(level, level_addr); -#ifdef CONFIG_METAG_SUSPEND_MEM - priv->levels_altered[meta_intc_bank(hw)] |= bit; -#endif - __global_unlock2(flags); - - return 0; -} - -/** - * meta_intc_irq_demux() - external irq de-multiplexer - * @desc: the interrupt description structure for this irq - * - * The cpu receives an interrupt on TR2 when a SoC interrupt has occurred. It is - * this function's job to demux this irq and figure out exactly which external - * irq needs servicing. - * - * Whilst using TR2 to detect external interrupts is a software convention it is - * (hopefully) unlikely to change. - */ -static void meta_intc_irq_demux(struct irq_desc *desc) -{ - struct meta_intc_priv *priv = &meta_intc_priv; - irq_hw_number_t hw; - unsigned int bank, irq_no, status; - void __iomem *stat_addr = meta_intc_stat_addr(0); - - /* - * Locate which interrupt has caused our handler to run. - */ - for (bank = 0; bank < priv->nr_banks; ++bank) { - /* Which interrupts are currently pending in this bank? */ -recalculate: - status = metag_in32(stat_addr) & priv->unmasked[bank]; - - for (hw = bank*32; status; status >>= 1, ++hw) { - if (status & 0x1) { - /* - * Map the hardware IRQ number to a virtual - * Linux IRQ number. - */ - irq_no = irq_linear_revmap(priv->domain, hw); - - /* - * Only fire off external interrupts that are - * registered to be handled by the kernel. - * Other external interrupts are probably being - * handled by other Meta hardware threads. - */ - generic_handle_irq(irq_no); - - /* - * The handler may have re-enabled interrupts - * which could have caused a nested invocation - * of this code and make the copy of the - * status register we are using invalid. - */ - goto recalculate; - } - } - stat_addr += HWSTAT_STRIDE; - } -} - -#ifdef CONFIG_SMP -/** - * meta_intc_set_affinity() - set the affinity for an interrupt - * @data: data for the external irq to set the affinity of - * @cpumask: cpu mask representing cpus which can handle the interrupt - * @force: whether to force (ignored) - * - * Revector the specified external irq onto a specific cpu's TR2 trigger, so - * that that cpu tends to be the one who handles it. - */ -static int meta_intc_set_affinity(struct irq_data *data, - const struct cpumask *cpumask, bool force) -{ - irq_hw_number_t hw = data->hwirq; - void __iomem *vec_addr = meta_intc_vec_addr(hw); - unsigned int cpu, thread; - - /* - * Wire up this interrupt from HWVECxEXT to the Meta core. - * - * Note that we can't wire up HWVECxEXT to interrupt more than - * one cpu (the interrupt code doesn't support it), so we just - * pick the first cpu we find in 'cpumask'. - */ - cpu = cpumask_any_and(cpumask, cpu_online_mask); - thread = cpu_2_hwthread_id[cpu]; - - metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr); - - irq_data_update_effective_affinity(data, cpumask_of(cpu)); - - return 0; -} -#else -#define meta_intc_set_affinity NULL -#endif - -#ifdef CONFIG_PM_SLEEP -#define META_INTC_CHIP_FLAGS (IRQCHIP_MASK_ON_SUSPEND \ - | IRQCHIP_SKIP_SET_WAKE) -#else -#define META_INTC_CHIP_FLAGS 0 -#endif - -/* public edge/level irq chips which SoCs can override */ - -struct irq_chip meta_intc_edge_chip = { - .irq_startup = meta_intc_startup_irq, - .irq_shutdown = meta_intc_shutdown_irq, - .irq_ack = meta_intc_ack_irq, - .irq_mask = meta_intc_mask_irq, - .irq_unmask = meta_intc_unmask_irq, - .irq_set_type = meta_intc_irq_set_type, - .irq_set_affinity = meta_intc_set_affinity, - .flags = META_INTC_CHIP_FLAGS, -}; - -struct irq_chip meta_intc_level_chip = { - .irq_startup = meta_intc_startup_irq, - .irq_shutdown = meta_intc_shutdown_irq, - .irq_set_type = meta_intc_irq_set_type, - .irq_mask = meta_intc_mask_irq, - .irq_unmask = meta_intc_unmask_irq, - .irq_set_affinity = meta_intc_set_affinity, - .flags = META_INTC_CHIP_FLAGS, -}; - -/** - * meta_intc_map() - map an external irq - * @d: irq domain of external trigger block - * @irq: virtual irq number - * @hw: hardware irq number within external trigger block - * - * This sets up a virtual irq for a specified hardware interrupt. The irq chip - * and handler is configured, using the HWLEVELEXT registers to determine - * edge/level flow type. These registers will have been set when the irq type is - * set (or set to a default at init time). - */ -static int meta_intc_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) -{ - unsigned int bit = 1 << meta_intc_offset(hw); - void __iomem *level_addr = meta_intc_level_addr(hw); - - /* Go by the current sense in the HWLEVELEXT register */ - if (metag_in32(level_addr) & bit) - irq_set_chip_and_handler(irq, &meta_intc_level_chip, - handle_level_irq); - else - irq_set_chip_and_handler(irq, &meta_intc_edge_chip, - handle_edge_irq); - - irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); - return 0; -} - -static const struct irq_domain_ops meta_intc_domain_ops = { - .map = meta_intc_map, - .xlate = irq_domain_xlate_twocell, -}; - -#ifdef CONFIG_METAG_SUSPEND_MEM - -/** - * struct meta_intc_context - suspend context - * @levels: State of HWLEVELEXT registers - * @masks: State of HWMASKEXT registers - * @vectors: State of HWVECEXT registers - * @txvecint: State of TxVECINT registers - * - * This structure stores the IRQ state across suspend. - */ -struct meta_intc_context { - u32 levels[4]; - u32 masks[4]; - u8 vectors[4*32]; - - u8 txvecint[4][4]; -}; - -/* suspend context */ -static struct meta_intc_context *meta_intc_context; - -/** - * meta_intc_suspend() - store irq state - * - * To avoid interfering with other threads we only save the IRQ state of IRQs in - * use by Linux. - */ -static int meta_intc_suspend(void) -{ - struct meta_intc_priv *priv = &meta_intc_priv; - int i, j; - irq_hw_number_t hw; - unsigned int bank; - unsigned long flags; - struct meta_intc_context *context; - void __iomem *level_addr, *mask_addr, *vec_addr; - u32 mask, bit; - - context = kzalloc(sizeof(*context), GFP_ATOMIC); - if (!context) - return -ENOMEM; - - hw = 0; - level_addr = meta_intc_level_addr(0); - mask_addr = meta_intc_mask_addr(0); - for (bank = 0; bank < priv->nr_banks; ++bank) { - vec_addr = meta_intc_vec_addr(hw); - - /* create mask of interrupts in use */ - mask = 0; - for (bit = 1; bit; bit <<= 1) { - i = irq_linear_revmap(priv->domain, hw); - /* save mapped irqs which are enabled or have actions */ - if (i && (!irqd_irq_disabled(irq_get_irq_data(i)) || - irq_has_action(i))) { - mask |= bit; - - /* save trigger vector */ - context->vectors[hw] = metag_in32(vec_addr); - } - - ++hw; - vec_addr += HWVECnEXT_STRIDE; - } - - /* save level state if any IRQ levels altered */ - if (priv->levels_altered[bank]) - context->levels[bank] = metag_in32(level_addr); - /* save mask state if any IRQs in use */ - if (mask) - context->masks[bank] = metag_in32(mask_addr); - - level_addr += HWSTAT_STRIDE; - mask_addr += HWSTAT_STRIDE; - } - - /* save trigger matrixing */ - __global_lock2(flags); - for (i = 0; i < 4; ++i) - for (j = 0; j < 4; ++j) - context->txvecint[i][j] = metag_in32(T0VECINT_BHALT + - TnVECINT_STRIDE*i + - 8*j); - __global_unlock2(flags); - - meta_intc_context = context; - return 0; -} - -/** - * meta_intc_resume() - restore saved irq state - * - * Restore the saved IRQ state and drop it. - */ -static void meta_intc_resume(void) -{ - struct meta_intc_priv *priv = &meta_intc_priv; - int i, j; - irq_hw_number_t hw; - unsigned int bank; - unsigned long flags; - struct meta_intc_context *context = meta_intc_context; - void __iomem *level_addr, *mask_addr, *vec_addr; - u32 mask, bit, tmp; - - meta_intc_context = NULL; - - hw = 0; - level_addr = meta_intc_level_addr(0); - mask_addr = meta_intc_mask_addr(0); - for (bank = 0; bank < priv->nr_banks; ++bank) { - vec_addr = meta_intc_vec_addr(hw); - - /* create mask of interrupts in use */ - mask = 0; - for (bit = 1; bit; bit <<= 1) { - i = irq_linear_revmap(priv->domain, hw); - /* restore mapped irqs, enabled or with actions */ - if (i && (!irqd_irq_disabled(irq_get_irq_data(i)) || - irq_has_action(i))) { - mask |= bit; - - /* restore trigger vector */ - metag_out32(context->vectors[hw], vec_addr); - } - - ++hw; - vec_addr += HWVECnEXT_STRIDE; - } - - if (mask) { - /* restore mask state */ - __global_lock2(flags); - tmp = metag_in32(mask_addr); - tmp = (tmp & ~mask) | (context->masks[bank] & mask); - metag_out32(tmp, mask_addr); - __global_unlock2(flags); - } - - mask = priv->levels_altered[bank]; - if (mask) { - /* restore level state */ - __global_lock2(flags); - tmp = metag_in32(level_addr); - tmp = (tmp & ~mask) | (context->levels[bank] & mask); - metag_out32(tmp, level_addr); - __global_unlock2(flags); - } - - level_addr += HWSTAT_STRIDE; - mask_addr += HWSTAT_STRIDE; - } - - /* restore trigger matrixing */ - __global_lock2(flags); - for (i = 0; i < 4; ++i) { - for (j = 0; j < 4; ++j) { - metag_out32(context->txvecint[i][j], - T0VECINT_BHALT + - TnVECINT_STRIDE*i + - 8*j); - } - } - __global_unlock2(flags); - - kfree(context); -} - -static struct syscore_ops meta_intc_syscore_ops = { - .suspend = meta_intc_suspend, - .resume = meta_intc_resume, -}; - -static void __init meta_intc_init_syscore_ops(struct meta_intc_priv *priv) -{ - register_syscore_ops(&meta_intc_syscore_ops); -} -#else -#define meta_intc_init_syscore_ops(priv) do {} while (0) -#endif - -/** - * meta_intc_init_cpu() - register with a Meta cpu - * @priv: private interrupt controller data - * @cpu: the CPU to register on - * - * Configure @cpu's TR2 irq so that we can demux external irqs. - */ -static void __init meta_intc_init_cpu(struct meta_intc_priv *priv, int cpu) -{ - unsigned int thread = cpu_2_hwthread_id[cpu]; - unsigned int signum = TBID_SIGNUM_TR2(thread); - int irq = tbisig_map(signum); - - /* Register the multiplexed IRQ handler */ - irq_set_chained_handler(irq, meta_intc_irq_demux); - irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); -} - -/** - * meta_intc_no_mask() - indicate lack of HWMASKEXT registers - * - * Called from SoC code (or init code below) to dynamically indicate the lack of - * HWMASKEXT registers (for example depending on some SoC revision register). - * This alters the irq mask and unmask callbacks to use the fallback - * unvectoring/retriggering technique instead of using HWMASKEXT registers. - */ -void __init meta_intc_no_mask(void) -{ - meta_intc_edge_chip.irq_mask = meta_intc_mask_irq_nomask; - meta_intc_edge_chip.irq_unmask = meta_intc_unmask_edge_irq_nomask; - meta_intc_level_chip.irq_mask = meta_intc_mask_irq_nomask; - meta_intc_level_chip.irq_unmask = meta_intc_unmask_level_irq_nomask; -} - -/** - * init_external_IRQ() - initialise the external irq controller - * - * Set up the external irq controller using device tree properties. This is - * called from init_IRQ(). - */ -int __init init_external_IRQ(void) -{ - struct meta_intc_priv *priv = &meta_intc_priv; - struct device_node *node; - int ret, cpu; - u32 val; - bool no_masks = false; - - node = of_find_compatible_node(NULL, NULL, "img,meta-intc"); - if (!node) - return -ENOENT; - - /* Get number of banks */ - ret = of_property_read_u32(node, "num-banks", &val); - if (ret) { - pr_err("meta-intc: No num-banks property found\n"); - return ret; - } - if (val < 1 || val > 4) { - pr_err("meta-intc: num-banks (%u) out of range\n", val); - return -EINVAL; - } - priv->nr_banks = val; - - /* Are any mask registers present? */ - if (of_get_property(node, "no-mask", NULL)) - no_masks = true; - - /* No HWMASKEXT registers present? */ - if (no_masks) - meta_intc_no_mask(); - - /* Set up an IRQ domain */ - /* - * This is a legacy IRQ domain for now until all the platform setup code - * has been converted to devicetree. - */ - priv->domain = irq_domain_add_linear(node, priv->nr_banks*32, - &meta_intc_domain_ops, priv); - if (unlikely(!priv->domain)) { - pr_err("meta-intc: cannot add IRQ domain\n"); - return -ENOMEM; - } - - /* Setup TR2 for all cpus. */ - for_each_possible_cpu(cpu) - meta_intc_init_cpu(priv, cpu); - - /* Set up system suspend/resume callbacks */ - meta_intc_init_syscore_ops(priv); - - pr_info("meta-intc: External IRQ controller initialised (%u IRQs)\n", - priv->nr_banks*32); - - return 0; -} diff --git a/drivers/irqchip/irq-metag.c b/drivers/irqchip/irq-metag.c deleted file mode 100644 index 857b946747eb..000000000000 --- a/drivers/irqchip/irq-metag.c +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Meta internal (HWSTATMETA) interrupt code. - * - * Copyright (C) 2011-2012 Imagination Technologies Ltd. - * - * This code is based on the code in SoC/common/irq.c and SoC/comet/irq.c - * The code base could be generalised/merged as a lot of the functionality is - * similar. Until this is done, we try to keep the code simple here. - */ - -#include -#include -#include - -#include -#include - -#define PERF0VECINT 0x04820580 -#define PERF1VECINT 0x04820588 -#define PERF0TRIG_OFFSET 16 -#define PERF1TRIG_OFFSET 17 - -/** - * struct metag_internal_irq_priv - private meta internal interrupt data - * @domain: IRQ domain for all internal Meta IRQs (HWSTATMETA) - * @unmasked: Record of unmasked IRQs - */ -struct metag_internal_irq_priv { - struct irq_domain *domain; - - unsigned long unmasked; -}; - -/* Private data for the one and only internal interrupt controller */ -static struct metag_internal_irq_priv metag_internal_irq_priv; - -static unsigned int metag_internal_irq_startup(struct irq_data *data); -static void metag_internal_irq_shutdown(struct irq_data *data); -static void metag_internal_irq_ack(struct irq_data *data); -static void metag_internal_irq_mask(struct irq_data *data); -static void metag_internal_irq_unmask(struct irq_data *data); -#ifdef CONFIG_SMP -static int metag_internal_irq_set_affinity(struct irq_data *data, - const struct cpumask *cpumask, bool force); -#endif - -static struct irq_chip internal_irq_edge_chip = { - .name = "HWSTATMETA-IRQ", - .irq_startup = metag_internal_irq_startup, - .irq_shutdown = metag_internal_irq_shutdown, - .irq_ack = metag_internal_irq_ack, - .irq_mask = metag_internal_irq_mask, - .irq_unmask = metag_internal_irq_unmask, -#ifdef CONFIG_SMP - .irq_set_affinity = metag_internal_irq_set_affinity, -#endif -}; - -/* - * metag_hwvec_addr - get the address of *VECINT regs of irq - * - * This function is a table of supported triggers on HWSTATMETA - * Could do with a structure, but better keep it simple. Changes - * in this code should be rare. - */ -static inline void __iomem *metag_hwvec_addr(irq_hw_number_t hw) -{ - void __iomem *addr; - - switch (hw) { - case PERF0TRIG_OFFSET: - addr = (void __iomem *)PERF0VECINT; - break; - case PERF1TRIG_OFFSET: - addr = (void __iomem *)PERF1VECINT; - break; - default: - addr = NULL; - break; - } - return addr; -} - -/* - * metag_internal_startup - setup an internal irq - * @irq: the irq to startup - * - * Multiplex interrupts for @irq onto TR1. Clear any pending - * interrupts. - */ -static unsigned int metag_internal_irq_startup(struct irq_data *data) -{ - /* Clear (toggle) the bit in HWSTATMETA for our interrupt. */ - metag_internal_irq_ack(data); - - /* Enable the interrupt by unmasking it */ - metag_internal_irq_unmask(data); - - return 0; -} - -/* - * metag_internal_irq_shutdown - turn off the irq - * @irq: the irq number to turn off - * - * Mask @irq and clear any pending interrupts. - * Stop muxing @irq onto TR1. - */ -static void metag_internal_irq_shutdown(struct irq_data *data) -{ - /* Disable the IRQ at the core by masking it. */ - metag_internal_irq_mask(data); - - /* Clear (toggle) the bit in HWSTATMETA for our interrupt. */ - metag_internal_irq_ack(data); -} - -/* - * metag_internal_irq_ack - acknowledge irq - * @irq: the irq to ack - */ -static void metag_internal_irq_ack(struct irq_data *data) -{ - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << hw; - - if (metag_in32(HWSTATMETA) & bit) - metag_out32(bit, HWSTATMETA); -} - -/** - * metag_internal_irq_mask() - mask an internal irq by unvectoring - * @data: data for the internal irq to mask - * - * HWSTATMETA has no mask register. Instead the IRQ is unvectored from the core - * and retriggered if necessary later. - */ -static void metag_internal_irq_mask(struct irq_data *data) -{ - struct metag_internal_irq_priv *priv = &metag_internal_irq_priv; - irq_hw_number_t hw = data->hwirq; - void __iomem *vec_addr = metag_hwvec_addr(hw); - - clear_bit(hw, &priv->unmasked); - - /* there is no interrupt mask, so unvector the interrupt */ - metag_out32(0, vec_addr); -} - -/** - * meta_intc_unmask_edge_irq_nomask() - unmask an edge irq by revectoring - * @data: data for the internal irq to unmask - * - * HWSTATMETA has no mask register. Instead the IRQ is revectored back to the - * core and retriggered if necessary. - */ -static void metag_internal_irq_unmask(struct irq_data *data) -{ - struct metag_internal_irq_priv *priv = &metag_internal_irq_priv; - irq_hw_number_t hw = data->hwirq; - unsigned int bit = 1 << hw; - void __iomem *vec_addr = metag_hwvec_addr(hw); - unsigned int thread = hard_processor_id(); - - set_bit(hw, &priv->unmasked); - - /* there is no interrupt mask, so revector the interrupt */ - metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR1(thread)), vec_addr); - - /* - * Re-trigger interrupt - * - * Writing a 1 toggles, and a 0->1 transition triggers. We only - * retrigger if the status bit is already set, which means we - * need to clear it first. Retriggering is fundamentally racy - * because if the interrupt fires again after we clear it we - * could end up clearing it again and the interrupt handler - * thinking it hasn't fired. Therefore we need to keep trying to - * retrigger until the bit is set. - */ - if (metag_in32(HWSTATMETA) & bit) { - metag_out32(bit, HWSTATMETA); - while (!(metag_in32(HWSTATMETA) & bit)) - metag_out32(bit, HWSTATMETA); - } -} - -#ifdef CONFIG_SMP -/* - * metag_internal_irq_set_affinity - set the affinity for an interrupt - */ -static int metag_internal_irq_set_affinity(struct irq_data *data, - const struct cpumask *cpumask, bool force) -{ - unsigned int cpu, thread; - irq_hw_number_t hw = data->hwirq; - /* - * Wire up this interrupt from *VECINT to the Meta core. - * - * Note that we can't wire up *VECINT to interrupt more than - * one cpu (the interrupt code doesn't support it), so we just - * pick the first cpu we find in 'cpumask'. - */ - cpu = cpumask_any_and(cpumask, cpu_online_mask); - thread = cpu_2_hwthread_id[cpu]; - - metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR1(thread)), - metag_hwvec_addr(hw)); - - return 0; -} -#endif - -/* - * metag_internal_irq_demux - irq de-multiplexer - * @irq: the interrupt number - * @desc: the interrupt description structure for this irq - * - * The cpu receives an interrupt on TR1 when an interrupt has - * occurred. It is this function's job to demux this irq and - * figure out exactly which trigger needs servicing. - */ -static void metag_internal_irq_demux(struct irq_desc *desc) -{ - struct metag_internal_irq_priv *priv = irq_desc_get_handler_data(desc); - irq_hw_number_t hw; - unsigned int irq_no; - u32 status; - -recalculate: - status = metag_in32(HWSTATMETA) & priv->unmasked; - - for (hw = 0; status != 0; status >>= 1, ++hw) { - if (status & 0x1) { - /* - * Map the hardware IRQ number to a virtual Linux IRQ - * number. - */ - irq_no = irq_linear_revmap(priv->domain, hw); - - /* - * Only fire off interrupts that are - * registered to be handled by the kernel. - * Other interrupts are probably being - * handled by other Meta hardware threads. - */ - generic_handle_irq(irq_no); - - /* - * The handler may have re-enabled interrupts - * which could have caused a nested invocation - * of this code and make the copy of the - * status register we are using invalid. - */ - goto recalculate; - } - } -} - -/** - * internal_irq_map() - Map an internal meta IRQ to a virtual IRQ number. - * @hw: Number of the internal IRQ. Must be in range. - * - * Returns: The virtual IRQ number of the Meta internal IRQ specified by - * @hw. - */ -int internal_irq_map(unsigned int hw) -{ - struct metag_internal_irq_priv *priv = &metag_internal_irq_priv; - if (!priv->domain) - return -ENODEV; - return irq_create_mapping(priv->domain, hw); -} - -/** - * metag_internal_irq_init_cpu - regsister with the Meta cpu - * @cpu: the CPU to register on - * - * Configure @cpu's TR1 irq so that we can demux irqs. - */ -static void metag_internal_irq_init_cpu(struct metag_internal_irq_priv *priv, - int cpu) -{ - unsigned int thread = cpu_2_hwthread_id[cpu]; - unsigned int signum = TBID_SIGNUM_TR1(thread); - int irq = tbisig_map(signum); - - /* Register the multiplexed IRQ handler */ - irq_set_chained_handler_and_data(irq, metag_internal_irq_demux, priv); - irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); -} - -/** - * metag_internal_intc_map() - map an internal irq - * @d: irq domain of internal trigger block - * @irq: virtual irq number - * @hw: hardware irq number within internal trigger block - * - * This sets up a virtual irq for a specified hardware interrupt. The irq chip - * and handler is configured. - */ -static int metag_internal_intc_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) -{ - /* only register interrupt if it is mapped */ - if (!metag_hwvec_addr(hw)) - return -EINVAL; - - irq_set_chip_and_handler(irq, &internal_irq_edge_chip, - handle_edge_irq); - return 0; -} - -static const struct irq_domain_ops metag_internal_intc_domain_ops = { - .map = metag_internal_intc_map, -}; - -/** - * metag_internal_irq_register - register internal IRQs - * - * Register the irq chip and handler function for all internal IRQs - */ -int __init init_internal_IRQ(void) -{ - struct metag_internal_irq_priv *priv = &metag_internal_irq_priv; - unsigned int cpu; - - /* Set up an IRQ domain */ - priv->domain = irq_domain_add_linear(NULL, 32, - &metag_internal_intc_domain_ops, - priv); - if (unlikely(!priv->domain)) { - pr_err("meta-internal-intc: cannot add IRQ domain\n"); - return -ENOMEM; - } - - /* Setup TR1 for all cpus. */ - for_each_possible_cpu(cpu) - metag_internal_irq_init_cpu(priv, cpu); - - return 0; -}; diff --git a/include/linux/irqchip/metag-ext.h b/include/linux/irqchip/metag-ext.h deleted file mode 100644 index d120496370b9..000000000000 --- a/include/linux/irqchip/metag-ext.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2012 Imagination Technologies - */ - -#ifndef _LINUX_IRQCHIP_METAG_EXT_H_ -#define _LINUX_IRQCHIP_METAG_EXT_H_ - -struct irq_data; -struct platform_device; - -/* called from core irq code at init */ -int init_external_IRQ(void); - -/* - * called from SoC init_irq() callback to dynamically indicate the lack of - * HWMASKEXT registers. - */ -void meta_intc_no_mask(void); - -/* - * These allow SoCs to specialise the interrupt controller from their init_irq - * callbacks. - */ - -extern struct irq_chip meta_intc_edge_chip; -extern struct irq_chip meta_intc_level_chip; - -/* this should be called in the mask callback */ -void meta_intc_mask_irq_simple(struct irq_data *data); -/* this should be called in the unmask callback */ -void meta_intc_unmask_irq_simple(struct irq_data *data); - -#endif /* _LINUX_IRQCHIP_METAG_EXT_H_ */ diff --git a/include/linux/irqchip/metag.h b/include/linux/irqchip/metag.h deleted file mode 100644 index 0adcf449e4e4..000000000000 --- a/include/linux/irqchip/metag.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2011 Imagination Technologies - */ - -#ifndef _LINUX_IRQCHIP_METAG_H_ -#define _LINUX_IRQCHIP_METAG_H_ - -#include - -#ifdef CONFIG_METAG_PERFCOUNTER_IRQS -extern int init_internal_IRQ(void); -extern int internal_irq_map(unsigned int hw); -#else -static inline int init_internal_IRQ(void) -{ - return 0; -} -static inline int internal_irq_map(unsigned int hw) -{ - return -EINVAL; -} -#endif - -#endif /* _LINUX_IRQCHIP_METAG_H_ */ -- cgit v1.2.3 From b79a732504ad2d6552458eaf72b4ed807da88340 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 21 Feb 2018 15:42:32 +0000 Subject: clocksource: Remove metag generic timer driver Now that arch/metag/ has been removed, remove the metag generic per-thread timer driver. It is of no value without the architecture code. Signed-off-by: James Hogan Acked-by: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-metag@vger.kernel.org --- drivers/clocksource/Kconfig | 5 -- drivers/clocksource/Makefile | 1 - drivers/clocksource/metag_generic.c | 161 ------------------------------------ include/clocksource/metag_generic.h | 21 ----- include/linux/cpuhotplug.h | 1 - 5 files changed, 189 deletions(-) delete mode 100644 drivers/clocksource/metag_generic.c delete mode 100644 include/clocksource/metag_generic.h (limited to 'include/linux') diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index b3b4ed9b6874..f99dbc2f7ee4 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -391,11 +391,6 @@ config ATMEL_ST help Support for the Atmel ST timer. -config CLKSRC_METAG_GENERIC - def_bool y if METAG - help - This option enables support for the Meta per-thread timers. - config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index d6dec4489d66..a2d47e9ecf91 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -61,7 +61,6 @@ obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o -obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o diff --git a/drivers/clocksource/metag_generic.c b/drivers/clocksource/metag_generic.c deleted file mode 100644 index 3e5fa2f62d5f..000000000000 --- a/drivers/clocksource/metag_generic.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (C) 2005-2013 Imagination Technologies Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * - * Support for Meta per-thread timers. - * - * Meta hardware threads have 2 timers. The background timer (TXTIMER) is used - * as a free-running time base (hz clocksource), and the interrupt timer - * (TXTIMERI) is used for the timer interrupt (clock event). Both counters - * traditionally count at approximately 1MHz. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define HARDWARE_FREQ 1000000 /* 1MHz */ -#define HARDWARE_DIV 1 /* divide by 1 = 1MHz clock */ -#define HARDWARE_TO_NS_SHIFT 10 /* convert ticks to ns */ - -static unsigned int hwtimer_freq = HARDWARE_FREQ; -static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); -static DEFINE_PER_CPU(char [11], local_clockevent_name); - -static int metag_timer_set_next_event(unsigned long delta, - struct clock_event_device *dev) -{ - __core_reg_set(TXTIMERI, -delta); - return 0; -} - -static u64 metag_clocksource_read(struct clocksource *cs) -{ - return __core_reg_get(TXTIMER); -} - -static struct clocksource clocksource_metag = { - .name = "META", - .rating = 200, - .mask = CLOCKSOURCE_MASK(32), - .read = metag_clocksource_read, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static irqreturn_t metag_timer_interrupt(int irq, void *dummy) -{ - struct clock_event_device *evt = this_cpu_ptr(&local_clockevent); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction metag_timer_irq = { - .name = "META core timer", - .handler = metag_timer_interrupt, - .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU, -}; - -unsigned long long sched_clock(void) -{ - unsigned long long ticks = __core_reg_get(TXTIMER); - return ticks << HARDWARE_TO_NS_SHIFT; -} - -static int arch_timer_starting_cpu(unsigned int cpu) -{ - unsigned int txdivtime; - struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); - char *name = per_cpu(local_clockevent_name, cpu); - - txdivtime = __core_reg_get(TXDIVTIME); - - txdivtime &= ~TXDIVTIME_DIV_BITS; - txdivtime |= (HARDWARE_DIV & TXDIVTIME_DIV_BITS); - - __core_reg_set(TXDIVTIME, txdivtime); - - sprintf(name, "META %d", cpu); - clk->name = name; - clk->features = CLOCK_EVT_FEAT_ONESHOT, - - clk->rating = 200, - clk->shift = 12, - clk->irq = tbisig_map(TBID_SIGNUM_TRT), - clk->set_next_event = metag_timer_set_next_event, - - clk->mult = div_sc(hwtimer_freq, NSEC_PER_SEC, clk->shift); - clk->max_delta_ns = clockevent_delta2ns(0x7fffffff, clk); - clk->max_delta_ticks = 0x7fffffff; - clk->min_delta_ns = clockevent_delta2ns(0xf, clk); - clk->min_delta_ticks = 0xf; - clk->cpumask = cpumask_of(cpu); - - clockevents_register_device(clk); - - /* - * For all non-boot CPUs we need to synchronize our free - * running clock (TXTIMER) with the boot CPU's clock. - * - * While this won't be accurate, it should be close enough. - */ - if (cpu) { - unsigned int thread0 = cpu_2_hwthread_id[0]; - unsigned long val; - - val = core_reg_read(TXUCT_ID, TXTIMER_REGNUM, thread0); - __core_reg_set(TXTIMER, val); - } - return 0; -} - -int __init metag_generic_timer_init(void) -{ - /* - * On Meta 2 SoCs, the actual frequency of the timer is based on the - * Meta core clock speed divided by an integer, so it is only - * approximately 1MHz. Calculating the real frequency here drastically - * reduces clock skew on these SoCs. - */ -#ifdef CONFIG_METAG_META21 - hwtimer_freq = get_coreclock() / (metag_in32(EXPAND_TIMER_DIV) + 1); -#endif - pr_info("Timer frequency: %u Hz\n", hwtimer_freq); - - clocksource_register_hz(&clocksource_metag, hwtimer_freq); - - setup_irq(tbisig_map(TBID_SIGNUM_TRT), &metag_timer_irq); - - /* Hook cpu boot to configure the CPU's timers */ - return cpuhp_setup_state(CPUHP_AP_METAG_TIMER_STARTING, - "clockevents/metag:starting", - arch_timer_starting_cpu, NULL); -} diff --git a/include/clocksource/metag_generic.h b/include/clocksource/metag_generic.h deleted file mode 100644 index ac17e7d06cfb..000000000000 --- a/include/clocksource/metag_generic.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2013 Imaginaton Technologies Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef __CLKSOURCE_METAG_GENERIC_H -#define __CLKSOURCE_METAG_GENERIC_H - -extern int metag_generic_timer_init(void); - -#endif /* __CLKSOURCE_METAG_GENERIC_H */ diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index c7a950681f3a..5b211fe295f0 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -121,7 +121,6 @@ enum cpuhp_state { CPUHP_AP_JCORE_TIMER_STARTING, CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, - CPUHP_AP_METAG_TIMER_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MARCO_TIMER_STARTING, -- cgit v1.2.3 From ee07862f7b4594d390b978f6636a6a6191632ab3 Mon Sep 17 00:00:00 2001 From: Yafang Shao Date: Fri, 23 Feb 2018 14:58:41 +0800 Subject: bpf: NULL pointer check is not needed in BPF_CGROUP_RUN_PROG_INET_SOCK sk is already allocated in inet_create/inet6_create, hence when BPF_CGROUP_RUN_PROG_INET_SOCK is executed sk will never be NULL. The logic is as bellow, sk = sk_alloc(); if (!sk) goto out; BPF_CGROUP_RUN_PROG_INET_SOCK(sk); Signed-off-by: Yafang Shao Signed-off-by: Daniel Borkmann --- include/linux/bpf-cgroup.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/bpf-cgroup.h b/include/linux/bpf-cgroup.h index a7f16e0f8d68..8a4566691c8f 100644 --- a/include/linux/bpf-cgroup.h +++ b/include/linux/bpf-cgroup.h @@ -96,7 +96,7 @@ int __cgroup_bpf_check_dev_permission(short dev_type, u32 major, u32 minor, #define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) \ ({ \ int __ret = 0; \ - if (cgroup_bpf_enabled && sk) { \ + if (cgroup_bpf_enabled) { \ __ret = __cgroup_bpf_run_filter_sk(sk, \ BPF_CGROUP_INET_SOCK_CREATE); \ } \ -- cgit v1.2.3 From 57cbd893c4c575a24594fa6c0835247506ce26e2 Mon Sep 17 00:00:00 2001 From: Mark Bloch Date: Tue, 16 Jan 2018 14:04:14 +0000 Subject: net/mlx5: E-Switch, Move representors definition to a global scope In preparation for IB representors, move representors structs to a global scope, also expose functions needed for registration, unregistration, eswitch mode and creating a flow rule to direct traffic from SQs to the right VF. Signed-off-by: Mark Bloch Reviewed-by: Or Gerlitz Signed-off-by: Leon Romanovsky Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/eswitch.c | 6 +++ drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 44 +---------------- .../ethernet/mellanox/mlx5/core/eswitch_offloads.c | 12 +++++ .../net/ethernet/mellanox/mlx5/core/mlx5_core.h | 6 --- include/linux/mlx5/driver.h | 6 +++ include/linux/mlx5/eswitch.h | 57 ++++++++++++++++++++++ 6 files changed, 82 insertions(+), 49 deletions(-) create mode 100644 include/linux/mlx5/eswitch.h (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c index 5ecf2cddc16d..aec4653d88bc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2175,3 +2175,9 @@ free_out: kvfree(out); return err; } + +u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw) +{ + return esw->mode; +} +EXPORT_SYMBOL_GPL(mlx5_eswitch_mode); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 4dfb1da435a4..9c1e1a2d02ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -37,19 +37,9 @@ #include #include #include +#include #include "lib/mpfs.h" -enum { - SRIOV_NONE, - SRIOV_LEGACY, - SRIOV_OFFLOADS -}; - -enum { - REP_ETH, - NUM_REP_TYPES, -}; - #ifdef CONFIG_MLX5_ESWITCH #define MLX5_MAX_UC_PER_VPORT(dev) \ @@ -145,24 +135,6 @@ struct mlx5_eswitch_fdb { }; }; -struct mlx5_eswitch_rep; -struct mlx5_eswitch_rep_if { - int (*load)(struct mlx5_core_dev *dev, - struct mlx5_eswitch_rep *rep); - void (*unload)(struct mlx5_eswitch_rep *rep); - void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep); - void *priv; - bool valid; -}; - -struct mlx5_eswitch_rep { - struct mlx5_eswitch_rep_if rep_if[NUM_REP_TYPES]; - u16 vport; - u8 hw_id[ETH_ALEN]; - u16 vlan; - u32 vlan_refcount; -}; - struct mlx5_esw_offload { struct mlx5_flow_table *ft_offloads; struct mlx5_flow_group *vport_rx_group; @@ -232,9 +204,6 @@ int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, int vport, struct ifla_vf_stats *vf_stats); -struct mlx5_flow_handle * -mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport, - u32 sqn); void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); struct mlx5_flow_spec; @@ -279,18 +248,7 @@ int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode); int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap); int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap); -void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw, - int vport_index, - struct mlx5_eswitch_rep_if *rep_if, - u8 rep_type); -void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw, - int vport_index, - u8 rep_type); void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); -void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, - int vport, - u8 rep_type); -void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type); int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *attr); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 06623c8e92a2..92fdb10dd29f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -338,6 +338,7 @@ out: kvfree(spec); return flow_rule; } +EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule); void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule) { @@ -1165,6 +1166,7 @@ void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw, rep_if->valid = true; } +EXPORT_SYMBOL(mlx5_eswitch_register_vport_rep); void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw, int vport_index, u8 rep_type) @@ -1179,6 +1181,7 @@ void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw, rep->rep_if[rep_type].valid = false; } +EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_rep); void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type) { @@ -1207,8 +1210,17 @@ void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, return rep->rep_if[rep_type].get_proto_dev(rep); return NULL; } +EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev); void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type) { return mlx5_eswitch_get_proto_dev(esw, UPLINK_REP_INDEX, rep_type); } +EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev); + +struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw, + int vport) +{ + return &esw->offloads.vport_reps[vport]; +} +EXPORT_SYMBOL(mlx5_eswitch_vport_rep); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index 23e17ac0cba5..ee1a42a078ee 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -43,12 +43,6 @@ #define DRIVER_NAME "mlx5_core" #define DRIVER_VERSION "5.0-0" -#define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs(mdev->pdev)) -#define MLX5_VPORT_MANAGER(mdev) \ - (MLX5_CAP_GEN(mdev, vport_group_manager) && \ - (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ - mlx5_core_is_pf(mdev)) - extern uint mlx5_core_debug_mask; #define mlx5_core_dbg(__dev, format, ...) \ diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index bfea26af6de5..4814cad7456e 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1224,6 +1224,12 @@ static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); } +#define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) +#define MLX5_VPORT_MANAGER(mdev) \ + (MLX5_CAP_GEN(mdev, vport_group_manager) && \ + (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ + mlx5_core_is_pf(mdev)) + static inline int mlx5_get_gid_table_len(u16 param) { if (param > 4) { diff --git a/include/linux/mlx5/eswitch.h b/include/linux/mlx5/eswitch.h new file mode 100644 index 000000000000..f62bf486c18c --- /dev/null +++ b/include/linux/mlx5/eswitch.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2018 Mellanox Technologies. All rights reserved. + */ + +#ifndef _MLX5_ESWITCH_ +#define _MLX5_ESWITCH_ + +#include + +enum { + SRIOV_NONE, + SRIOV_LEGACY, + SRIOV_OFFLOADS +}; + +enum { + REP_ETH, + NUM_REP_TYPES, +}; + +struct mlx5_eswitch_rep; +struct mlx5_eswitch_rep_if { + int (*load)(struct mlx5_core_dev *dev, + struct mlx5_eswitch_rep *rep); + void (*unload)(struct mlx5_eswitch_rep *rep); + void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep); + void *priv; + bool valid; +}; + +struct mlx5_eswitch_rep { + struct mlx5_eswitch_rep_if rep_if[NUM_REP_TYPES]; + u16 vport; + u8 hw_id[ETH_ALEN]; + u16 vlan; + u32 vlan_refcount; +}; + +void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw, + int vport_index, + struct mlx5_eswitch_rep_if *rep_if, + u8 rep_type); +void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw, + int vport_index, + u8 rep_type); +void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, + int vport, + u8 rep_type); +struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw, + int vport); +void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type); +u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw); +struct mlx5_flow_handle * +mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, + int vport, u32 sqn); +#endif -- cgit v1.2.3 From 5e65b02c00900155833008b7992bbbbc7f0df2ac Mon Sep 17 00:00:00 2001 From: Mark Bloch Date: Tue, 16 Jan 2018 14:13:46 +0000 Subject: net/mlx5: E-Switch, Add definition of IB representor Create a new representor type: REP_IB. which will be initialized by an IB device that is used as a logical representor of a eswitch vport (VF or uplink) just like we have a net device today in switchdev mode. Signed-off-by: Mark Bloch Reviewed-by: Or Gerlitz Signed-off-by: Leon Romanovsky Signed-off-by: Saeed Mahameed --- include/linux/mlx5/eswitch.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/mlx5/eswitch.h b/include/linux/mlx5/eswitch.h index f62bf486c18c..d3c9db492b30 100644 --- a/include/linux/mlx5/eswitch.h +++ b/include/linux/mlx5/eswitch.h @@ -16,6 +16,7 @@ enum { enum { REP_ETH, + REP_IB, NUM_REP_TYPES, }; -- cgit v1.2.3 From e69c61dd050e410d78363e5fe6e56a9f719abdf5 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 24 Feb 2018 21:22:18 -0800 Subject: genirq: Drop 5 #included header files from irq.h does not use nor need several of its #included files, so drop those header files from irq.h. is currently #included in around 1135 C source files (oops, I didn't count other header files that #include it), making it the 29th most-used header file. Build tested on i386 and x86_64 * (allnoconfig, tiny.config, defconfig, allyesconfig, and allmodconfig) and x64_64 allmodconfig + SMP=disabled. Signed-off-by: Randy Dunlap Signed-off-by: Thomas Gleixner Link: https://lkml.kernel.org/r/02745e91-c117-74b5-d043-dceb3d4bb4e0@infradead.org --- include/linux/irq.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/irq.h b/include/linux/irq.h index a0231e96a578..979eed1b2654 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -10,18 +10,13 @@ * Thanks. --rmk */ -#include -#include #include #include #include -#include #include #include #include -#include #include -#include #include #include -- cgit v1.2.3 From 6ce5ae7977c89f2a09092954396a66c90e8213f2 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 24 Feb 2018 21:22:12 -0800 Subject: mutex: Drop linkage.h from mutex.h does not use nor need , so drop that one header file from mutex.h. is currently #included in around 1250 C source files (oops, I didn't count other header files that #include it), making it the 27th most-used header file. Build tested on i386 and x86_64 * (allnoconfig, tiny.config, defconfig, allyesconfig, and allmodconfig) and x64_64 allmodconfig + SMP=disabled. Signed-off-by: Randy Dunlap Signed-off-by: Thomas Gleixner Link: https://lkml.kernel.org/r/582b3892-4e4c-06b2-a368-5c2d439de7fc@infradead.org --- include/linux/mutex.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/mutex.h b/include/linux/mutex.h index f25c13423bd4..9b7fe56692bd 100644 --- a/include/linux/mutex.h +++ b/include/linux/mutex.h @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.3 From dfc9327ab7c99bc13e12106448615efba833886b Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Mon, 19 Feb 2018 11:09:04 +0100 Subject: acpi: Introduce acpi_arch_get_root_pointer() for getting rsdp address Add an architecture specific function to get the address of the RSDP table. Per default it will just return 0 indicating falling back to the current mechanism. Signed-off-by: Juergen Gross Reviewed-by: Andy Shevchenko Acked-by: Thomas Gleixner Acked-by: Rafael J. Wysocki Cc: Borislav Petkov Cc: Eric Biederman Cc: H. Peter Anvin Cc: Kees Cook Cc: Kirill A. Shutemov Cc: Linus Torvalds Cc: Peter Zijlstra Cc: boris.ostrovsky@oracle.com Cc: lenb@kernel.org Cc: linux-acpi@vger.kernel.org Cc: xen-devel@lists.xenproject.org Link: http://lkml.kernel.org/r/20180219100906.14265-2-jgross@suse.com Signed-off-by: Ingo Molnar --- drivers/acpi/osl.c | 5 ++++- include/linux/acpi.h | 7 +++++++ 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 3bb46cb24a99..7ca41bf023c9 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -189,12 +189,15 @@ early_param("acpi_rsdp", setup_acpi_rsdp); acpi_physical_address __init acpi_os_get_root_pointer(void) { - acpi_physical_address pa = 0; + acpi_physical_address pa; #ifdef CONFIG_KEXEC if (acpi_rsdp) return acpi_rsdp; #endif + pa = acpi_arch_get_root_pointer(); + if (pa) + return pa; if (efi_enabled(EFI_CONFIG_TABLES)) { if (efi.acpi20 != EFI_INVALID_TABLE_ADDR) diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 968173ec2726..15bfb15c2fa5 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -623,6 +623,13 @@ bool acpi_gtdt_c3stop(int type); int acpi_arch_timer_mem_init(struct arch_timer_mem *timer_mem, int *timer_count); #endif +#ifndef ACPI_HAVE_ARCH_GET_ROOT_POINTER +static inline u64 acpi_arch_get_root_pointer(void) +{ + return 0; +} +#endif + #else /* !CONFIG_ACPI */ #define acpi_disabled 1 -- cgit v1.2.3 From 31895662f9ba81e8ea9ef05abf8edcb29d4b9c18 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Feb 2018 10:20:25 +0100 Subject: regmap: mmio: Add function to attach a clock regmap_init_mmio_clk allows to specify a clock that needs to be enabled while accessing the registers. However, that clock is retrieved through its clock ID, which means it will lookup that clock based on the current device that registers the regmap, and, in the DT case, will only look in that device OF node. This might be problematic if the clock to enable is stored in another node. Let's add a function that allows to attach a clock that has already been retrieved to a regmap in order to fix this. Signed-off-by: Maxime Ripard Signed-off-by: Mark Brown --- drivers/base/regmap/regmap-mmio.c | 24 ++++++++++++++++++++++++ include/linux/regmap.h | 3 +++ 2 files changed, 27 insertions(+) (limited to 'include/linux') diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c index 5189fd6182f6..5cadfd3394d8 100644 --- a/drivers/base/regmap/regmap-mmio.c +++ b/drivers/base/regmap/regmap-mmio.c @@ -28,6 +28,8 @@ struct regmap_mmio_context { void __iomem *regs; unsigned val_bytes; + + bool attached_clk; struct clk *clk; void (*reg_write)(struct regmap_mmio_context *ctx, @@ -363,4 +365,26 @@ struct regmap *__devm_regmap_init_mmio_clk(struct device *dev, } EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk); +int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk) +{ + struct regmap_mmio_context *ctx = map->bus_context; + + ctx->clk = clk; + ctx->attached_clk = true; + + return clk_prepare(ctx->clk); +} +EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk); + +void regmap_mmio_detach_clk(struct regmap *map) +{ + struct regmap_mmio_context *ctx = map->bus_context; + + clk_unprepare(ctx->clk); + + ctx->attached_clk = false; + ctx->clk = NULL; +} +EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk); + MODULE_LICENSE("GPL v2"); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 6a3aeba40e9e..5f7ad0552c03 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -21,6 +21,7 @@ #include struct module; +struct clk; struct device; struct i2c_client; struct irq_domain; @@ -905,6 +906,8 @@ bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg); __regmap_lockdep_wrapper(__devm_regmap_init_sdw, #config, \ sdw, config) +int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk); +void regmap_mmio_detach_clk(struct regmap *map); void regmap_exit(struct regmap *map); int regmap_reinit_cache(struct regmap *map, const struct regmap_config *config); -- cgit v1.2.3 From ef70b0bdeaf893dd6d9c3a8d05d9b65d395506c0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 22 Feb 2018 14:00:25 -0800 Subject: bus: ti-sysc: Add support for platform data callbacks We want to pass the device tree configuration for interconnect target modules from ti-sysc driver to the existing platform hwmod code. This allows us to first validate the dts data against the existing platform data before we start dropping the platform data in favor of device tree data. To do this, let's add platform data callbacks for PM runtime functions to call for the interconnect target modules if platform data is available. Note that as ti-sysc driver can rebind, omap_auxdata_lookup and related functions can no longer be __init. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 4 +- arch/arm/mach-omap2/pdata-quirks.c | 40 ++++++++++++++- drivers/bus/ti-sysc.c | 96 ++++++++++++++++++++++++++++++----- include/linux/platform_data/ti-sysc.h | 49 ++++++++++++++++++ 4 files changed, 172 insertions(+), 17 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 20f25539d572..75bc18646df6 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -566,11 +566,11 @@ static int n8x0_menelaus_late_init(struct device *dev) } #endif -struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { +struct menelaus_platform_data n8x0_menelaus_platform_data = { .late_init = n8x0_menelaus_late_init, }; -struct aic3x_pdata n810_aic33_data __initdata = { +struct aic3x_pdata n810_aic33_data = { .gpio_reset = 118, }; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 1cca66ad68b5..eea82c31ee77 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -455,6 +456,42 @@ static void __init dra7x_evm_mmc_quirk(void) } #endif +static int ti_sysc_enable_module(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (!cookie->data) + return -EINVAL; + + return omap_hwmod_enable(cookie->data); +} + +static int ti_sysc_idle_module(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (!cookie->data) + return -EINVAL; + + return omap_hwmod_idle(cookie->data); +} + +static int ti_sysc_shutdown_module(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (!cookie->data) + return -EINVAL; + + return omap_hwmod_shutdown(cookie->data); +} + +static struct of_dev_auxdata omap_auxdata_lookup[]; + +static struct ti_sysc_platform_data ti_sysc_pdata = { + .auxdata = omap_auxdata_lookup, + .enable_module = ti_sysc_enable_module, + .idle_module = ti_sysc_idle_module, + .shutdown_module = ti_sysc_shutdown_module, +}; + static struct pcs_pdata pcs_pdata; void omap_pcs_legacy_init(int irq, void (*rearm)(void)) @@ -545,7 +582,7 @@ static struct pdata_init auxdata_quirks[] __initdata = { struct omap_sr_data __maybe_unused omap_sr_pdata[OMAP_SR_NR]; -static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { +static struct of_dev_auxdata omap_auxdata_lookup[] = { #ifdef CONFIG_MACH_NOKIA_N8X0 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data), @@ -603,6 +640,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &dra7_hsmmc_data_mmc3), #endif /* Common auxdata */ + OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), { /* sentinel */ }, }; diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index fc9aac3d4d02..50fcb04e8179 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -25,13 +25,6 @@ #include -enum sysc_registers { - SYSC_REVISION, - SYSC_SYSCONFIG, - SYSC_SYSSTATUS, - SYSC_MAX_REGS, -}; - static const char * const reg_names[] = { "rev", "sysc", "syss", }; enum sysc_clocks { @@ -70,6 +63,7 @@ struct sysc { const char *legacy_mode; const struct sysc_capabilities *cap; struct sysc_config cfg; + struct ti_sysc_cookie cookie; const char *name; u32 revision; bool enabled; @@ -494,6 +488,7 @@ static void sysc_show_registers(struct sysc *ddata) bufp += sysc_show_reg(ddata, bufp, i); bufp += sysc_show_rev(bufp, ddata); + bufp += sysc_show_rev(bufp, ddata); dev_dbg(ddata->dev, "%llx:%x%s\n", ddata->module_pa, ddata->module_size, @@ -502,33 +497,70 @@ static void sysc_show_registers(struct sysc *ddata) static int __maybe_unused sysc_runtime_suspend(struct device *dev) { + struct ti_sysc_platform_data *pdata; struct sysc *ddata; - int i; + int error = 0, i; ddata = dev_get_drvdata(dev); - if (ddata->legacy_mode) + if (!ddata->enabled) return 0; + if (ddata->legacy_mode) { + pdata = dev_get_platdata(ddata->dev); + if (!pdata) + return 0; + + if (!pdata->idle_module) + return -ENODEV; + + error = pdata->idle_module(dev, &ddata->cookie); + if (error) + dev_err(dev, "%s: could not idle: %i\n", + __func__, error); + + goto idled; + } + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { if (IS_ERR_OR_NULL(ddata->clocks[i])) continue; clk_disable(ddata->clocks[i]); } - return 0; +idled: + ddata->enabled = false; + + return error; } static int __maybe_unused sysc_runtime_resume(struct device *dev) { + struct ti_sysc_platform_data *pdata; struct sysc *ddata; - int i, error; + int error = 0, i; ddata = dev_get_drvdata(dev); - if (ddata->legacy_mode) + if (ddata->enabled) return 0; + if (ddata->legacy_mode) { + pdata = dev_get_platdata(ddata->dev); + if (!pdata) + return 0; + + if (!pdata->enable_module) + return -ENODEV; + + error = pdata->enable_module(dev, &ddata->cookie); + if (error) + dev_err(dev, "%s: could not enable: %i\n", + __func__, error); + + goto awake; + } + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { if (IS_ERR_OR_NULL(ddata->clocks[i])) continue; @@ -537,7 +569,10 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev) return error; } - return 0; +awake: + ddata->enabled = true; + + return error; } #ifdef CONFIG_PM_SLEEP @@ -1007,6 +1042,33 @@ static const struct sysc_capabilities sysc_omap4_usb_host_fs = { .regbits = &sysc_regbits_omap4_usb_host_fs, }; +static int sysc_init_pdata(struct sysc *ddata) +{ + struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); + struct ti_sysc_module_data mdata; + int error = 0; + + if (!pdata || !ddata->legacy_mode) + return 0; + + mdata.name = ddata->legacy_mode; + mdata.module_pa = ddata->module_pa; + mdata.module_size = ddata->module_size; + mdata.offsets = ddata->offsets; + mdata.nr_offsets = SYSC_MAX_REGS; + mdata.cap = ddata->cap; + mdata.cfg = &ddata->cfg; + + if (!pdata->init_module) + return -ENODEV; + + error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie); + if (error == -EEXIST) + error = 0; + + return error; +} + static int sysc_init_match(struct sysc *ddata) { const struct sysc_capabilities *cap; @@ -1034,6 +1096,7 @@ static void ti_sysc_idle(struct work_struct *work) static int sysc_probe(struct platform_device *pdev) { + struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); struct sysc *ddata; int error; @@ -1072,6 +1135,10 @@ static int sysc_probe(struct platform_device *pdev) if (error) goto unprepare; + error = sysc_init_pdata(ddata); + if (error) + goto unprepare; + pm_runtime_enable(ddata->dev); error = sysc_init_module(ddata); @@ -1089,7 +1156,8 @@ static int sysc_probe(struct platform_device *pdev) ddata->dev->type = &sysc_device_type; error = of_platform_populate(ddata->dev->of_node, - NULL, NULL, ddata->dev); + NULL, pdata ? pdata->auxdata : NULL, + ddata->dev); if (error) goto err; diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 1be356330b96..4176cb90e195 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -16,6 +16,10 @@ enum ti_sysc_module_type { TI_SYSC_OMAP4_USB_HOST_FS, }; +struct ti_sysc_cookie { + void *data; +}; + /** * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets * @midle_shift: Offset of the midle bit @@ -83,4 +87,49 @@ struct sysc_config { u32 quirks; }; +enum sysc_registers { + SYSC_REVISION, + SYSC_SYSCONFIG, + SYSC_SYSSTATUS, + SYSC_MAX_REGS, +}; + +/** + * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module + * @name: legacy "ti,hwmods" module name + * @module_pa: physical address of the interconnect target module + * @module_size: size of the interconnect target module + * @offsets: array of register offsets as listed in enum sysc_registers + * @nr_offsets: number of registers + * @cap: interconnect target module capabilities + * @cfg: interconnect target module configuration + * + * This data is enough to allocate a new struct omap_hwmod_class_sysconfig + * based on device tree data parsed by ti-sysc driver. + */ +struct ti_sysc_module_data { + const char *name; + u64 module_pa; + u32 module_size; + int *offsets; + int nr_offsets; + const struct sysc_capabilities *cap; + struct sysc_config *cfg; +}; + +struct device; + +struct ti_sysc_platform_data { + struct of_dev_auxdata *auxdata; + int (*init_module)(struct device *dev, + const struct ti_sysc_module_data *data, + struct ti_sysc_cookie *cookie); + int (*enable_module)(struct device *dev, + const struct ti_sysc_cookie *cookie); + int (*idle_module)(struct device *dev, + const struct ti_sysc_cookie *cookie); + int (*shutdown_module)(struct device *dev, + const struct ti_sysc_cookie *cookie); +}; + #endif /* __TI_SYSC_DATA_H__ */ -- cgit v1.2.3 From a885f0fe209f262efa2c1cac9278a5774e5f7a80 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 22 Feb 2018 14:03:48 -0800 Subject: bus: ti-sysc: Handle some devices in omap_device compatible way Now that ti-sysc can manage child devices, we must also be backwards compatible with the current omap_device code. With omap_device, we assume that the child device manages the interconnect target module directly. The drivers needing special handling are the ones that still set pm_runtime_irq_safe(). In the long run we want to update those drivers as otherwise they will cause problems with genpd as a permanent PM runtime usage count is set on the parent device. We can handle omap_device these devices by improving the ti-sysc quirk handling to detect the devices needing special handling based on register map and revision register if usable. We also need to implement dev_pm_domain for these child devices just like omap_device does. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 226 +++++++++++++++++++++++++++++++++- include/linux/platform_data/ti-sysc.h | 1 + 2 files changed, 224 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 50fcb04e8179..5aeab4533b5f 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -68,6 +70,7 @@ struct sysc { u32 revision; bool enabled; bool needs_resume; + bool child_needs_resume; struct delayed_work idle_work; }; @@ -474,6 +477,14 @@ static int sysc_show_reg(struct sysc *ddata, return sprintf(bufp, ":%x", ddata->offsets[reg]); } +static int sysc_show_name(char *bufp, struct sysc *ddata) +{ + if (!ddata->name) + return 0; + + return sprintf(bufp, ":%s", ddata->name); +} + /** * sysc_show_registers - show information about interconnect target module * @ddata: device driver data @@ -488,7 +499,7 @@ static void sysc_show_registers(struct sysc *ddata) bufp += sysc_show_reg(ddata, bufp, i); bufp += sysc_show_rev(bufp, ddata); - bufp += sysc_show_rev(bufp, ddata); + bufp += sysc_show_name(bufp, ddata); dev_dbg(ddata->dev, "%llx:%x%s\n", ddata->module_pa, ddata->module_size, @@ -612,11 +623,93 @@ static const struct dev_pm_ops sysc_pm_ops = { NULL) }; +/* Module revision register based quirks */ +struct sysc_revision_quirk { + const char *name; + u32 base; + int rev_offset; + int sysc_offset; + int syss_offset; + u32 revision; + u32 revision_mask; + u32 quirks; +}; + +#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ + optrev_val, optrevmask, optquirkmask) \ + { \ + .name = (optname), \ + .base = (optbase), \ + .rev_offset = (optrev), \ + .sysc_offset = (optsysc), \ + .syss_offset = (optsyss), \ + .revision = (optrev_val), \ + .revision_mask = (optrevmask), \ + .quirks = (optquirkmask), \ + } + +static const struct sysc_revision_quirk sysc_revision_quirks[] = { + /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ + SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), +}; + +static void sysc_init_revision_quirks(struct sysc *ddata) +{ + const struct sysc_revision_quirk *q; + int i; + + for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { + q = &sysc_revision_quirks[i]; + + if (q->base && q->base != ddata->module_pa) + continue; + + if (q->rev_offset >= 0 && + q->rev_offset != ddata->offsets[SYSC_REVISION]) + continue; + + if (q->sysc_offset >= 0 && + q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) + continue; + + if (q->syss_offset >= 0 && + q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) + continue; + + if (q->revision == ddata->revision || + (q->revision & q->revision_mask) == + (ddata->revision & q->revision_mask)) { + ddata->name = q->name; + ddata->cfg.quirks |= q->quirks; + } + } +} + /* At this point the module is configured enough to read the revision */ static int sysc_init_module(struct sysc *ddata) { int error; + if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) { + ddata->revision = sysc_read_revision(ddata); + goto rev_quirks; + } + error = pm_runtime_get_sync(ddata->dev); if (error < 0) { pm_runtime_put_noidle(ddata->dev); @@ -626,6 +719,9 @@ static int sysc_init_module(struct sysc *ddata) ddata->revision = sysc_read_revision(ddata); pm_runtime_put_sync(ddata->dev); +rev_quirks: + sysc_init_revision_quirks(ddata); + return 0; } @@ -753,6 +849,127 @@ static struct sysc *sysc_child_to_parent(struct device *dev) return dev_get_drvdata(parent); } +static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + error = pm_generic_runtime_suspend(dev); + if (error) + return error; + + if (!ddata->enabled) + return 0; + + return sysc_runtime_suspend(ddata->dev); +} + +static int __maybe_unused sysc_child_runtime_resume(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + if (!ddata->enabled) { + error = sysc_runtime_resume(ddata->dev); + if (error < 0) + dev_err(ddata->dev, + "%s error: %i\n", __func__, error); + } + + return pm_generic_runtime_resume(dev); +} + +#ifdef CONFIG_PM_SLEEP +static int sysc_child_suspend_noirq(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + error = pm_generic_suspend_noirq(dev); + if (error) + return error; + + if (!pm_runtime_status_suspended(dev)) { + error = pm_generic_runtime_suspend(dev); + if (error) + return error; + + error = sysc_runtime_suspend(ddata->dev); + if (error) + return error; + + ddata->child_needs_resume = true; + } + + return 0; +} + +static int sysc_child_resume_noirq(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + if (ddata->child_needs_resume) { + ddata->child_needs_resume = false; + + error = sysc_runtime_resume(ddata->dev); + if (error) + dev_err(ddata->dev, + "%s runtime resume error: %i\n", + __func__, error); + + error = pm_generic_runtime_resume(dev); + if (error) + dev_err(ddata->dev, + "%s generic runtime resume: %i\n", + __func__, error); + } + + return pm_generic_resume_noirq(dev); +} +#endif + +struct dev_pm_domain sysc_child_pm_domain = { + .ops = { + SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, + sysc_child_runtime_resume, + NULL) + USE_PLATFORM_PM_SLEEP_OPS + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, + sysc_child_resume_noirq) + } +}; + +/** + * sysc_legacy_idle_quirk - handle children in omap_device compatible way + * @ddata: device driver data + * @child: child device driver + * + * Allow idle for child devices as done with _od_runtime_suspend(). + * Otherwise many child devices will not idle because of the permanent + * parent usecount set in pm_runtime_irq_safe(). + * + * Note that the long term solution is to just modify the child device + * drivers to not set pm_runtime_irq_safe() and then this can be just + * dropped. + */ +static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) +{ + if (!ddata->legacy_mode) + return; + + if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) + dev_pm_domain_set(child, &sysc_child_pm_domain); +} + static int sysc_notifier_call(struct notifier_block *nb, unsigned long event, void *device) { @@ -770,6 +987,7 @@ static int sysc_notifier_call(struct notifier_block *nb, if (error && error != -EEXIST) dev_warn(ddata->dev, "could not add %s fck: %i\n", dev_name(dev), error); + sysc_legacy_idle_quirk(ddata, dev); break; default: break; @@ -974,7 +1192,8 @@ static const struct sysc_capabilities sysc_34xx_sr = { .type = TI_SYSC_OMAP34XX_SR, .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, .regbits = &sysc_regbits_omap34xx_sr, - .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED, + .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | + SYSC_QUIRK_LEGACY_IDLE, }; /* @@ -995,12 +1214,13 @@ static const struct sysc_capabilities sysc_36xx_sr = { .type = TI_SYSC_OMAP36XX_SR, .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, .regbits = &sysc_regbits_omap36xx_sr, - .mod_quirks = SYSC_QUIRK_UNCACHED, + .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, }; static const struct sysc_capabilities sysc_omap4_sr = { .type = TI_SYSC_OMAP4_SR, .regbits = &sysc_regbits_omap36xx_sr, + .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, }; /* diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 4176cb90e195..80ce28d40832 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -45,6 +45,7 @@ struct sysc_regbits { s8 emufree_shift; }; +#define SYSC_QUIRK_LEGACY_IDLE BIT(8) #define SYSC_QUIRK_RESET_STATUS BIT(7) #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) -- cgit v1.2.3 From 209f668cd29d2b6b9f39a0b9f179ee40f47c2014 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Mon, 26 Feb 2018 16:04:19 -0800 Subject: console: Fill in struct consw argument names Reading the function declarations for the console callbacks lacks any hints as to what the arguments are. Instead of going and digging around in various implementations that may each only have a subset of the callbacks, name all the arguments in the declaration. This has no functional change. Signed-off-by: Kees Cook Signed-off-by: Greg Kroah-Hartman --- include/linux/console.h | 58 +++++++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 26 deletions(-) (limited to 'include/linux') diff --git a/include/linux/console.h b/include/linux/console.h index b8920a031a3e..dfd6b0e97855 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -46,46 +46,52 @@ enum con_scroll { struct consw { struct module *owner; const char *(*con_startup)(void); - void (*con_init)(struct vc_data *, int); - void (*con_deinit)(struct vc_data *); - void (*con_clear)(struct vc_data *, int, int, int, int); - void (*con_putc)(struct vc_data *, int, int, int); - void (*con_putcs)(struct vc_data *, const unsigned short *, int, int, int); - void (*con_cursor)(struct vc_data *, int); - bool (*con_scroll)(struct vc_data *, unsigned int top, + void (*con_init)(struct vc_data *vc, int init); + void (*con_deinit)(struct vc_data *vc); + void (*con_clear)(struct vc_data *vc, int sy, int sx, int height, + int width); + void (*con_putc)(struct vc_data *vc, int c, int ypos, int xpos); + void (*con_putcs)(struct vc_data *vc, const unsigned short *s, + int count, int ypos, int xpos); + void (*con_cursor)(struct vc_data *vc, int mode); + bool (*con_scroll)(struct vc_data *vc, unsigned int top, unsigned int bottom, enum con_scroll dir, unsigned int lines); - int (*con_switch)(struct vc_data *); - int (*con_blank)(struct vc_data *, int, int); - int (*con_font_set)(struct vc_data *, struct console_font *, unsigned); - int (*con_font_get)(struct vc_data *, struct console_font *); - int (*con_font_default)(struct vc_data *, struct console_font *, char *); - int (*con_font_copy)(struct vc_data *, int); - int (*con_resize)(struct vc_data *, unsigned int, unsigned int, - unsigned int); - void (*con_set_palette)(struct vc_data *, + int (*con_switch)(struct vc_data *vc); + int (*con_blank)(struct vc_data *vc, int blank, int mode_switch); + int (*con_font_set)(struct vc_data *vc, struct console_font *font, + unsigned int flags); + int (*con_font_get)(struct vc_data *vc, struct console_font *font); + int (*con_font_default)(struct vc_data *vc, + struct console_font *font, char *name); + int (*con_font_copy)(struct vc_data *vc, int con); + int (*con_resize)(struct vc_data *vc, unsigned int width, + unsigned int height, unsigned int user); + void (*con_set_palette)(struct vc_data *vc, const unsigned char *table); - void (*con_scrolldelta)(struct vc_data *, int lines); - int (*con_set_origin)(struct vc_data *); - void (*con_save_screen)(struct vc_data *); - u8 (*con_build_attr)(struct vc_data *, u8, u8, u8, u8, u8, u8); - void (*con_invert_region)(struct vc_data *, u16 *, int); - u16 *(*con_screen_pos)(struct vc_data *, int); - unsigned long (*con_getxy)(struct vc_data *, unsigned long, int *, int *); + void (*con_scrolldelta)(struct vc_data *vc, int lines); + int (*con_set_origin)(struct vc_data *vc); + void (*con_save_screen)(struct vc_data *vc); + u8 (*con_build_attr)(struct vc_data *vc, u8 color, u8 intensity, + u8 blink, u8 underline, u8 reverse, u8 italic); + void (*con_invert_region)(struct vc_data *vc, u16 *p, int count); + u16 *(*con_screen_pos)(struct vc_data *vc, int offset); + unsigned long (*con_getxy)(struct vc_data *vc, unsigned long position, + int *px, int *py); /* * Flush the video console driver's scrollback buffer */ - void (*con_flush_scrollback)(struct vc_data *); + void (*con_flush_scrollback)(struct vc_data *vc); /* * Prepare the console for the debugger. This includes, but is not * limited to, unblanking the console, loading an appropriate * palette, and allowing debugger generated output. */ - int (*con_debug_enter)(struct vc_data *); + int (*con_debug_enter)(struct vc_data *vc); /* * Restore the console to its pre-debug state as closely as possible. */ - int (*con_debug_leave)(struct vc_data *); + int (*con_debug_leave)(struct vc_data *vc); }; extern const struct consw *conswitchp; -- cgit v1.2.3 From 7b1f641776e0c8b824fb10135168e4b683a9e2ba Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Wed, 21 Feb 2018 15:07:52 +0100 Subject: fsnotify: Let userspace know about lost events due to ENOMEM Currently if notification event is lost due to event allocation failing we ENOMEM, we just silently continue (except for fanotify permission events where we deny the access). This is undesirable as userspace has no way of knowing whether the notifications it got are complete or not. Treat lost events due to ENOMEM the same way as lost events due to queue overflow so that userspace knows something bad happened and it likely needs to rescan the filesystem. Reviewed-by: Amir Goldstein Signed-off-by: Jan Kara --- fs/notify/fanotify/fanotify.c | 9 ++++++++- fs/notify/inotify/inotify_fsnotify.c | 8 +++++++- fs/notify/notification.c | 3 ++- include/linux/fsnotify_backend.h | 6 ++++++ 4 files changed, 23 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/fs/notify/fanotify/fanotify.c b/fs/notify/fanotify/fanotify.c index 928f2a5eedb7..d51e1bb781cf 100644 --- a/fs/notify/fanotify/fanotify.c +++ b/fs/notify/fanotify/fanotify.c @@ -221,8 +221,15 @@ static int fanotify_handle_event(struct fsnotify_group *group, event = fanotify_alloc_event(group, inode, mask, data); ret = -ENOMEM; - if (unlikely(!event)) + if (unlikely(!event)) { + /* + * We don't queue overflow events for permission events as + * there the access is denied and so no event is in fact lost. + */ + if (!fanotify_is_perm_event(mask)) + fsnotify_queue_overflow(group); goto finish; + } fsn_event = &event->fse; ret = fsnotify_add_event(group, fsn_event, fanotify_merge); diff --git a/fs/notify/inotify/inotify_fsnotify.c b/fs/notify/inotify/inotify_fsnotify.c index 8b73332735ba..40dedb37a1f3 100644 --- a/fs/notify/inotify/inotify_fsnotify.c +++ b/fs/notify/inotify/inotify_fsnotify.c @@ -99,8 +99,14 @@ int inotify_handle_event(struct fsnotify_group *group, fsn_mark); event = kmalloc(alloc_len, GFP_KERNEL); - if (unlikely(!event)) + if (unlikely(!event)) { + /* + * Treat lost event due to ENOMEM the same way as queue + * overflow to let userspace know event was lost. + */ + fsnotify_queue_overflow(group); return -ENOMEM; + } fsn_event = &event->fse; fsnotify_init_event(fsn_event, inode, mask); diff --git a/fs/notify/notification.c b/fs/notify/notification.c index 66f85c651c52..3c3e36745f59 100644 --- a/fs/notify/notification.c +++ b/fs/notify/notification.c @@ -111,7 +111,8 @@ int fsnotify_add_event(struct fsnotify_group *group, return 2; } - if (group->q_len >= group->max_events) { + if (event == group->overflow_event || + group->q_len >= group->max_events) { ret = 2; /* Queue overflow event only if it isn't already queued */ if (!list_empty(&group->overflow_event->list)) { diff --git a/include/linux/fsnotify_backend.h b/include/linux/fsnotify_backend.h index 067d52e95f02..9f1edb92c97e 100644 --- a/include/linux/fsnotify_backend.h +++ b/include/linux/fsnotify_backend.h @@ -331,6 +331,12 @@ extern int fsnotify_add_event(struct fsnotify_group *group, struct fsnotify_event *event, int (*merge)(struct list_head *, struct fsnotify_event *)); +/* Queue overflow event to a notification group */ +static inline void fsnotify_queue_overflow(struct fsnotify_group *group) +{ + fsnotify_add_event(group, group->overflow_event, NULL); +} + /* true if the group notification queue is empty */ extern bool fsnotify_notify_queue_is_empty(struct fsnotify_group *group); /* return, but do not dequeue the first event on the notification queue */ -- cgit v1.2.3 From 243ac21035176ac9692c1308a9f3b8f6a4e5d733 Mon Sep 17 00:00:00 2001 From: Corey Minyard Date: Tue, 20 Feb 2018 07:30:22 -0600 Subject: ipmi: Add or fix SPDX-License-Identifier in all files And get rid of the license text that is no longer necessary. Signed-off-by: Corey Minyard Cc: Kees Cook Cc: Alistair Popple Cc: Jeremy Kerr Cc: Joel Stanley Cc: Rocky Craig --- drivers/char/ipmi/bt-bmc.c | 6 +----- drivers/char/ipmi/ipmi_bt_sm.c | 22 ++-------------------- drivers/char/ipmi/ipmi_devintf.c | 22 +--------------------- drivers/char/ipmi/ipmi_dmi.c | 2 +- drivers/char/ipmi/ipmi_dmi.h | 2 +- drivers/char/ipmi/ipmi_kcs_sm.c | 22 +--------------------- drivers/char/ipmi/ipmi_msghandler.c | 22 +--------------------- drivers/char/ipmi/ipmi_powernv.c | 6 +----- drivers/char/ipmi/ipmi_poweroff.c | 22 +--------------------- drivers/char/ipmi/ipmi_si.h | 1 + drivers/char/ipmi/ipmi_si_hardcode.c | 1 + drivers/char/ipmi/ipmi_si_hotmod.c | 1 + drivers/char/ipmi/ipmi_si_intf.c | 22 +--------------------- drivers/char/ipmi/ipmi_si_mem_io.c | 1 + drivers/char/ipmi/ipmi_si_parisc.c | 1 + drivers/char/ipmi/ipmi_si_pci.c | 1 + drivers/char/ipmi/ipmi_si_platform.c | 1 + drivers/char/ipmi/ipmi_si_port_io.c | 1 + drivers/char/ipmi/ipmi_si_sm.h | 22 +--------------------- drivers/char/ipmi/ipmi_smic_sm.c | 24 ++---------------------- drivers/char/ipmi/ipmi_ssif.c | 6 +----- drivers/char/ipmi/ipmi_watchdog.c | 22 +--------------------- include/linux/ipmi-fru.h | 3 +-- include/linux/ipmi.h | 21 +-------------------- include/linux/ipmi_smi.h | 21 +-------------------- include/uapi/linux/ipmi.h | 20 -------------------- include/uapi/linux/ipmi_msgdefs.h | 20 -------------------- 27 files changed, 27 insertions(+), 288 deletions(-) (limited to 'include/linux') diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c index c95b93b7598b..40b9927c072c 100644 --- a/drivers/char/ipmi/bt-bmc.c +++ b/drivers/char/ipmi/bt-bmc.c @@ -1,10 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2015-2016, IBM Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. */ #include diff --git a/drivers/char/ipmi/ipmi_bt_sm.c b/drivers/char/ipmi/ipmi_bt_sm.c index feafdab734ae..fd4ea8d87d4b 100644 --- a/drivers/char/ipmi/ipmi_bt_sm.c +++ b/drivers/char/ipmi/ipmi_bt_sm.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_bt_sm.c * @@ -5,26 +6,7 @@ * of the driver architecture at http://sourceforge.net/projects/openipmi * * Author: Rocky Craig - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ + */ #include /* For printk. */ #include diff --git a/drivers/char/ipmi/ipmi_devintf.c b/drivers/char/ipmi/ipmi_devintf.c index 5f1bc9174735..8ecfd47806fa 100644 --- a/drivers/char/ipmi/ipmi_devintf.c +++ b/drivers/char/ipmi/ipmi_devintf.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_devintf.c * @@ -8,27 +9,6 @@ * source@mvista.com * * Copyright 2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include diff --git a/drivers/char/ipmi/ipmi_dmi.c b/drivers/char/ipmi/ipmi_dmi.c index f1df63bc859a..e2c143861b1e 100644 --- a/drivers/char/ipmi/ipmi_dmi.c +++ b/drivers/char/ipmi/ipmi_dmi.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /* * A hack to create a platform device from a DMI entry. This will * allow autoloading of the IPMI drive based on SMBIOS entries. diff --git a/drivers/char/ipmi/ipmi_dmi.h b/drivers/char/ipmi/ipmi_dmi.h index 6c21018e3668..8d2b094db8e6 100644 --- a/drivers/char/ipmi/ipmi_dmi.h +++ b/drivers/char/ipmi/ipmi_dmi.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * DMI defines for use by IPMI */ diff --git a/drivers/char/ipmi/ipmi_kcs_sm.c b/drivers/char/ipmi/ipmi_kcs_sm.c index 1da61af7f576..f4ea9f47230a 100644 --- a/drivers/char/ipmi/ipmi_kcs_sm.c +++ b/drivers/char/ipmi/ipmi_kcs_sm.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_kcs_sm.c * @@ -8,27 +9,6 @@ * source@mvista.com * * Copyright 2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ /* diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c index e0b0d7e2d976..361148938801 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_msghandler.c * @@ -8,27 +9,6 @@ * source@mvista.com * * Copyright 2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include diff --git a/drivers/char/ipmi/ipmi_powernv.c b/drivers/char/ipmi/ipmi_powernv.c index bcf493d8e238..e96500372ce2 100644 --- a/drivers/char/ipmi/ipmi_powernv.c +++ b/drivers/char/ipmi/ipmi_powernv.c @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * PowerNV OPAL IPMI driver * * Copyright 2014 IBM Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. */ #define pr_fmt(fmt) "ipmi-powernv: " fmt diff --git a/drivers/char/ipmi/ipmi_poweroff.c b/drivers/char/ipmi/ipmi_poweroff.c index 38e6af1c8e38..07fa366bc8f0 100644 --- a/drivers/char/ipmi/ipmi_poweroff.c +++ b/drivers/char/ipmi/ipmi_poweroff.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_poweroff.c * @@ -9,27 +10,6 @@ * source@mvista.com * * Copyright 2002,2004 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include diff --git a/drivers/char/ipmi/ipmi_si.h b/drivers/char/ipmi/ipmi_si.h index 17ce5f7b89ab..52f6152d1fcb 100644 --- a/drivers/char/ipmi/ipmi_si.h +++ b/drivers/char/ipmi/ipmi_si.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * ipmi_si.h * diff --git a/drivers/char/ipmi/ipmi_si_hardcode.c b/drivers/char/ipmi/ipmi_si_hardcode.c index fa9a4780de36..10219f24546b 100644 --- a/drivers/char/ipmi/ipmi_si_hardcode.c +++ b/drivers/char/ipmi/ipmi_si_hardcode.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ #include #include "ipmi_si.h" diff --git a/drivers/char/ipmi/ipmi_si_hotmod.c b/drivers/char/ipmi/ipmi_si_hotmod.c index fc03b9be2f3d..a98ca42a50b1 100644 --- a/drivers/char/ipmi/ipmi_si_hotmod.c +++ b/drivers/char/ipmi/ipmi_si_hotmod.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_si_hotmod.c * diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index 6768cb2dd740..5141ccf0b958 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_si.c * @@ -10,27 +11,6 @@ * * Copyright 2002 MontaVista Software Inc. * Copyright 2006 IBM Corp., Christian Krafft - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ /* diff --git a/drivers/char/ipmi/ipmi_si_mem_io.c b/drivers/char/ipmi/ipmi_si_mem_io.c index 8796396ecd0f..1b869d530884 100644 --- a/drivers/char/ipmi/ipmi_si_mem_io.c +++ b/drivers/char/ipmi/ipmi_si_mem_io.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ #include #include "ipmi_si.h" diff --git a/drivers/char/ipmi/ipmi_si_parisc.c b/drivers/char/ipmi/ipmi_si_parisc.c index 6b10f0e18a95..f3c99820f564 100644 --- a/drivers/char/ipmi/ipmi_si_parisc.c +++ b/drivers/char/ipmi/ipmi_si_parisc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ #include #include /* for register_parisc_driver() stuff */ diff --git a/drivers/char/ipmi/ipmi_si_pci.c b/drivers/char/ipmi/ipmi_si_pci.c index ad4e20b94c08..b1c055540b26 100644 --- a/drivers/char/ipmi/ipmi_si_pci.c +++ b/drivers/char/ipmi/ipmi_si_pci.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_si_pci.c * diff --git a/drivers/char/ipmi/ipmi_si_platform.c b/drivers/char/ipmi/ipmi_si_platform.c index f4214870d726..3d45bf1ee5bc 100644 --- a/drivers/char/ipmi/ipmi_si_platform.c +++ b/drivers/char/ipmi/ipmi_si_platform.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_si_platform.c * diff --git a/drivers/char/ipmi/ipmi_si_port_io.c b/drivers/char/ipmi/ipmi_si_port_io.c index e5ce174fbeeb..ef6dffcea9fa 100644 --- a/drivers/char/ipmi/ipmi_si_port_io.c +++ b/drivers/char/ipmi/ipmi_si_port_io.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ #include #include "ipmi_si.h" diff --git a/drivers/char/ipmi/ipmi_si_sm.h b/drivers/char/ipmi/ipmi_si_sm.h index aa8d88ab4433..aaddf047d923 100644 --- a/drivers/char/ipmi/ipmi_si_sm.h +++ b/drivers/char/ipmi/ipmi_si_sm.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * ipmi_si_sm.h * @@ -11,27 +12,6 @@ * source@mvista.com * * Copyright 2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include diff --git a/drivers/char/ipmi/ipmi_smic_sm.c b/drivers/char/ipmi/ipmi_smic_sm.c index 8f7c73ff58f2..466a5aac5298 100644 --- a/drivers/char/ipmi/ipmi_smic_sm.c +++ b/drivers/char/ipmi/ipmi_smic_sm.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_smic_sm.c * @@ -18,28 +19,7 @@ * copyright notice: * (c) Copyright 2001 Grant Grundler (c) Copyright * 2001 Hewlett-Packard Company - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ + */ #include /* For printk. */ #include diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index f929e72bdac8..9d3b0fa27560 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_ssif.c * @@ -13,11 +14,6 @@ * * Copyright 2003 Intel Corporation * Copyright 2005 MontaVista Software - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. */ /* diff --git a/drivers/char/ipmi/ipmi_watchdog.c b/drivers/char/ipmi/ipmi_watchdog.c index a58acdcf7414..22bc287eac2d 100644 --- a/drivers/char/ipmi/ipmi_watchdog.c +++ b/drivers/char/ipmi/ipmi_watchdog.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * ipmi_watchdog.c * @@ -8,27 +9,6 @@ * source@mvista.com * * Copyright 2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include diff --git a/include/linux/ipmi-fru.h b/include/linux/ipmi-fru.h index 4d3a76380e32..05c9422624c6 100644 --- a/include/linux/ipmi-fru.h +++ b/include/linux/ipmi-fru.h @@ -1,9 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2012 CERN (www.cern.ch) * Author: Alessandro Rubini * - * Released according to the GNU GPL, version 2 or any later version. - * * This work is part of the White Rabbit project, a research effort led * by CERN, the European Institute for Nuclear Research. */ diff --git a/include/linux/ipmi.h b/include/linux/ipmi.h index f4ffacf4fe9d..8b0626cec980 100644 --- a/include/linux/ipmi.h +++ b/include/linux/ipmi.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * ipmi.h * @@ -9,26 +10,6 @@ * * Copyright 2002 MontaVista Software Inc. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __LINUX_IPMI_H #define __LINUX_IPMI_H diff --git a/include/linux/ipmi_smi.h b/include/linux/ipmi_smi.h index 5be51281e14d..af457b5a689e 100644 --- a/include/linux/ipmi_smi.h +++ b/include/linux/ipmi_smi.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * ipmi_smi.h * @@ -9,26 +10,6 @@ * * Copyright 2002 MontaVista Software Inc. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __LINUX_IPMI_SMI_H diff --git a/include/uapi/linux/ipmi.h b/include/uapi/linux/ipmi.h index b076f7a47407..32d148309b16 100644 --- a/include/uapi/linux/ipmi.h +++ b/include/uapi/linux/ipmi.h @@ -10,26 +10,6 @@ * * Copyright 2002 MontaVista Software Inc. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef _UAPI__LINUX_IPMI_H diff --git a/include/uapi/linux/ipmi_msgdefs.h b/include/uapi/linux/ipmi_msgdefs.h index 17f349459587..c2b23a9fdf3d 100644 --- a/include/uapi/linux/ipmi_msgdefs.h +++ b/include/uapi/linux/ipmi_msgdefs.h @@ -10,26 +10,6 @@ * * Copyright 2002 MontaVista Software Inc. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __LINUX_IPMI_MSGDEFS_H -- cgit v1.2.3 From 41d9d44d725808f27b53f266733e6d17d83020ba Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 23 Feb 2018 09:43:56 -0600 Subject: ARM: OMAP2+: pm33xx-core: Add platform code needed for PM Most of the PM code needed for am335x and am437x can be moved into a module under drivers but some core code must remain in mach-omap2 at the moment. This includes some internal clockdomain APIs and low-level ARM APIs which are also not exported for use by modules. Implement a few functions that handle these low-level platform operations can be passed to the pm33xx module through the use of platform data. In addition to this, to be able to share data structures between C and the sleep33xx and sleep43xx assembly code, we can automatically generate all of the C struct member offsets and sizes as macros by processing pm-asm-offsets.c into assembly code and then extracting the relevant data as is done for the generated platform asm-offsets.h files. Finally, add amx3_common_pm_init to create a dummy platform_device for pm33xx so that our soon to be introduced pm33xx module can probe on am335x and am437x platforms to enable basic suspend to mem and standby support. Signed-off-by: Dave Gerlach Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/Makefile | 16 +++ arch/arm/mach-omap2/common.h | 7 ++ arch/arm/mach-omap2/io.c | 2 + arch/arm/mach-omap2/pm-asm-offsets.c | 31 ++++++ arch/arm/mach-omap2/pm.h | 3 + arch/arm/mach-omap2/pm33xx-core.c | 189 +++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/sleep33xx.S | 2 + arch/arm/mach-omap2/sleep43xx.S | 2 + include/linux/platform_data/pm33xx.h | 42 ++++++++ 10 files changed, 295 insertions(+) create mode 100644 arch/arm/mach-omap2/pm-asm-offsets.c create mode 100644 arch/arm/mach-omap2/pm33xx-core.c create mode 100644 include/linux/platform_data/pm33xx.h (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 00b1f17f8d44..9f27b486a536 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -72,6 +72,7 @@ config SOC_AM43XX select ARM_ERRATA_754322 select ARM_ERRATA_775420 select OMAP_INTERCONNECT + select ARM_CPU_SUSPEND if PM config SOC_DRA7XX bool "TI DRA7XX" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index c15bbcad5f67..4603c30fef73 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -88,6 +88,8 @@ omap-4-5-pm-common += pm44xx.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common) obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common) +obj-$(CONFIG_SOC_AM33XX) += pm33xx-core.o sleep33xx.o +obj-$(CONFIG_SOC_AM43XX) += pm33xx-core.o sleep43xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o @@ -95,6 +97,8 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec) endif @@ -232,3 +236,15 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) obj-y += omap_phy_internal.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o + +arch/arm/mach-omap2/pm-asm-offsets.s: arch/arm/mach-omap2/pm-asm-offsets.c + $(call if_changed_dep,cc_s_c) + +include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORCE + $(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__) + +# For rule to generate ti-emif-asm-offsets.h dependency +include drivers/memory/Makefile.asm-offsets + +arch/arm/mach-omap2/sleep33xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h +arch/arm/mach-omap2/sleep43xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index bc202835371b..fbe0b78bf489 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -77,6 +77,13 @@ static inline int omap4_pm_init_early(void) } #endif +#if defined(CONFIG_PM) && (defined(CONFIG_SOC_AM33XX) || \ + defined(CONFIG_SOC_AM43XX)) +void amx3_common_pm_init(void); +#else +static inline void amx3_common_pm_init(void) { } +#endif + extern void omap2_init_common_infrastructure(void); extern void omap_init_time(void); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cb5d7314cf99..cf546dfe3b32 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -622,6 +622,7 @@ void __init am33xx_init_early(void) void __init am33xx_init_late(void) { omap_common_late_init(); + amx3_common_pm_init(); } #endif @@ -646,6 +647,7 @@ void __init am43xx_init_late(void) { omap_common_late_init(); omap2_clk_enable_autoidle_all(); + amx3_common_pm_init(); } #endif diff --git a/arch/arm/mach-omap2/pm-asm-offsets.c b/arch/arm/mach-omap2/pm-asm-offsets.c new file mode 100644 index 000000000000..6d4392da7c11 --- /dev/null +++ b/arch/arm/mach-omap2/pm-asm-offsets.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI AM33XX and AM43XX PM Assembly Offsets + * + * Copyright (C) 2017-2018 Texas Instruments Inc. + */ + +#include +#include + +int main(void) +{ + DEFINE(AMX3_PM_WFI_FLAGS_OFFSET, + offsetof(struct am33xx_pm_sram_data, wfi_flags)); + DEFINE(AMX3_PM_L2_AUX_CTRL_VAL_OFFSET, + offsetof(struct am33xx_pm_sram_data, l2_aux_ctrl_val)); + DEFINE(AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET, + offsetof(struct am33xx_pm_sram_data, l2_prefetch_ctrl_val)); + DEFINE(AMX3_PM_SRAM_DATA_SIZE, sizeof(struct am33xx_pm_sram_data)); + + BLANK(); + + DEFINE(AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET, + offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_virt)); + DEFINE(AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET, + offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_phys)); + DEFINE(AMX3_PM_RO_SRAM_DATA_SIZE, + sizeof(struct am33xx_pm_ro_sram_data)); + + return 0; +} diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 8e30772cfe32..c73776b82348 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -81,6 +81,9 @@ extern unsigned int omap3_do_wfi_sz; /* ... and its pointer from SRAM after copy */ extern void (*omap3_do_wfi_sram)(void); +extern struct am33xx_pm_sram_addr am33xx_pm_sram; +extern struct am33xx_pm_sram_addr am43xx_pm_sram; + extern void omap3_save_scratchpad_contents(void); #define PM_RTA_ERRATUM_i608 (1 << 0) diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c new file mode 100644 index 000000000000..93c0b5ba9f09 --- /dev/null +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM33XX Arch Power Management Routines + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Dave Gerlach + */ + +#include +#include +#include +#include + +#include "cm33xx.h" +#include "common.h" +#include "control.h" +#include "clockdomain.h" +#include "iomap.h" +#include "omap_hwmod.h" +#include "pm.h" +#include "powerdomain.h" +#include "prm33xx.h" +#include "soc.h" +#include "sram.h" + +static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; +static struct clockdomain *gfx_l4ls_clkdm; +static void __iomem *scu_base; + +static int __init am43xx_map_scu(void) +{ + scu_base = ioremap(scu_a9_get_base(), SZ_256); + + if (!scu_base) + return -ENOMEM; + + return 0; +} + +static int amx3_common_init(void) +{ + gfx_pwrdm = pwrdm_lookup("gfx_pwrdm"); + per_pwrdm = pwrdm_lookup("per_pwrdm"); + mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); + + if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm)) + return -ENODEV; + + (void)clkdm_for_each(omap_pm_clkdms_setup, NULL); + + /* CEFUSE domain can be turned off post bootup */ + cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm"); + if (cefuse_pwrdm) + omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF); + else + pr_err("PM: Failed to get cefuse_pwrdm\n"); + + return 0; +} + +static int am33xx_suspend_init(void) +{ + int ret; + + gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm"); + + if (!gfx_l4ls_clkdm) { + pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n"); + return -ENODEV; + } + + ret = amx3_common_init(); + + return ret; +} + +static int am43xx_suspend_init(void) +{ + int ret = 0; + + ret = am43xx_map_scu(); + if (ret) { + pr_err("PM: Could not ioremap SCU\n"); + return ret; + } + + ret = amx3_common_init(); + + return ret; +} + +static void amx3_pre_suspend_common(void) +{ + omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF); +} + +static void amx3_post_suspend_common(void) +{ + int status; + /* + * Because gfx_pwrdm is the only one under MPU control, + * comment on transition status + */ + status = pwrdm_read_pwrst(gfx_pwrdm); + if (status != PWRDM_POWER_OFF) + pr_err("PM: GFX domain did not transition: %x\n", status); +} + +static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long)) +{ + int ret = 0; + + amx3_pre_suspend_common(); + ret = cpu_suspend(0, fn); + amx3_post_suspend_common(); + + /* + * BUG: GFX_L4LS clock domain needs to be woken up to + * ensure thet L4LS clock domain does not get stuck in + * transition. If that happens L3 module does not get + * disabled, thereby leading to PER power domain + * transition failing + */ + + clkdm_wakeup(gfx_l4ls_clkdm); + clkdm_sleep(gfx_l4ls_clkdm); + + return ret; +} + +static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long)) +{ + int ret = 0; + + amx3_pre_suspend_common(); + scu_power_mode(scu_base, SCU_PM_POWEROFF); + ret = cpu_suspend(0, fn); + scu_power_mode(scu_base, SCU_PM_NORMAL); + amx3_post_suspend_common(); + + return ret; +} + +static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void) +{ + if (soc_is_am33xx()) + return &am33xx_pm_sram; + else if (soc_is_am437x()) + return &am43xx_pm_sram; + else + return NULL; +} + +static struct am33xx_pm_platform_data am33xx_ops = { + .init = am33xx_suspend_init, + .soc_suspend = am33xx_suspend, + .get_sram_addrs = amx3_get_sram_addrs, +}; + +static struct am33xx_pm_platform_data am43xx_ops = { + .init = am43xx_suspend_init, + .soc_suspend = am43xx_suspend, + .get_sram_addrs = amx3_get_sram_addrs, +}; + +static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) +{ + if (soc_is_am33xx()) + return &am33xx_ops; + else if (soc_is_am437x()) + return &am43xx_ops; + else + return NULL; +} + +void __init amx3_common_pm_init(void) +{ + struct am33xx_pm_platform_data *pdata; + struct platform_device_info devinfo; + + pdata = am33xx_pm_get_pdata(); + + memset(&devinfo, 0, sizeof(devinfo)); + devinfo.name = "pm33xx"; + devinfo.data = pdata; + devinfo.size_data = sizeof(*pdata); + devinfo.id = -1; + platform_device_register_full(&devinfo); +} diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S index 04015f98b6e3..218d79930b04 100644 --- a/arch/arm/mach-omap2/sleep33xx.S +++ b/arch/arm/mach-omap2/sleep33xx.S @@ -6,6 +6,8 @@ * Dave Gerlach, Vaibhav Bedia */ +#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S index 0defc735e319..59770a69396b 100644 --- a/arch/arm/mach-omap2/sleep43xx.S +++ b/arch/arm/mach-omap2/sleep43xx.S @@ -6,6 +6,8 @@ * Dave Gerlach, Vaibhav Bedia */ +#include +#include #include #include diff --git a/include/linux/platform_data/pm33xx.h b/include/linux/platform_data/pm33xx.h new file mode 100644 index 000000000000..f9bed2a0af9d --- /dev/null +++ b/include/linux/platform_data/pm33xx.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TI pm33xx platform data + * + * Copyright (C) 2016-2018 Texas Instruments, Inc. + * Dave Gerlach + */ + +#ifndef _LINUX_PLATFORM_DATA_PM33XX_H +#define _LINUX_PLATFORM_DATA_PM33XX_H + +#include +#include + +#ifndef __ASSEMBLER__ +struct am33xx_pm_sram_addr { + void (*do_wfi)(void); + unsigned long *do_wfi_sz; + unsigned long *resume_offset; + unsigned long *emif_sram_table; + unsigned long *ro_sram_data; +}; + +struct am33xx_pm_platform_data { + int (*init)(void); + int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long)); + struct am33xx_pm_sram_addr *(*get_sram_addrs)(void); +}; + +struct am33xx_pm_sram_data { + u32 wfi_flags; + u32 l2_aux_ctrl_val; + u32 l2_prefetch_ctrl_val; +} __packed __aligned(8); + +struct am33xx_pm_ro_sram_data { + u32 amx3_pm_sram_data_virt; + u32 amx3_pm_sram_data_phys; +} __packed __aligned(8); + +#endif /* __ASSEMBLER__ */ +#endif /* _LINUX_PLATFORM_DATA_PM33XX_H */ -- cgit v1.2.3 From ead18c23c263374ed098a7d955b29b4a466d4573 Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Sat, 10 Feb 2018 19:27:12 +0100 Subject: driver core: Introduce device links reference counting If device_link_add() is invoked multiple times with the same supplier and consumer combo, it will create the link on first addition and return a pointer to the already existing link on all subsequent additions. The semantics for device_link_del() are quite different, it deletes the link unconditionally, so multiple invocations are not allowed. In other words, this snippet ... struct device *dev1, *dev2; struct device_link *link1, *link2; link1 = device_link_add(dev1, dev2, 0); link2 = device_link_add(dev1, dev2, 0); device_link_del(link1); device_link_del(link2); ... causes the following crash: WARNING: CPU: 4 PID: 2686 at drivers/base/power/runtime.c:1611 pm_runtime_drop_link+0x40/0x50 [...] list_del corruption, 0000000039b800a4->prev is LIST_POISON2 (00000000ecf79852) kernel BUG at lib/list_debug.c:50! The issue isn't as arbitrary as it may seem: Imagine a device link which is added in both the supplier's and the consumer's ->probe hook. The two drivers can't just call device_link_del() in their ->remove hook without coordination. Fix by counting multiple additions and dropping the device link only when the last addition is unwound. Signed-off-by: Lukas Wunner [ rjw: Subject ] Signed-off-by: Rafael J. Wysocki --- drivers/base/core.c | 25 +++++++++++++++++-------- include/linux/device.h | 2 ++ 2 files changed, 19 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/base/core.c b/drivers/base/core.c index 5847364f25d9..b610816eb887 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -196,8 +196,10 @@ struct device_link *device_link_add(struct device *consumer, } list_for_each_entry(link, &supplier->links.consumers, s_node) - if (link->consumer == consumer) + if (link->consumer == consumer) { + kref_get(&link->kref); goto out; + } link = kzalloc(sizeof(*link), GFP_KERNEL); if (!link) @@ -222,6 +224,7 @@ struct device_link *device_link_add(struct device *consumer, link->consumer = consumer; INIT_LIST_HEAD(&link->c_node); link->flags = flags; + kref_init(&link->kref); /* Determine the initial link state. */ if (flags & DL_FLAG_STATELESS) { @@ -292,8 +295,10 @@ static void __device_link_free_srcu(struct rcu_head *rhead) device_link_free(container_of(rhead, struct device_link, rcu_head)); } -static void __device_link_del(struct device_link *link) +static void __device_link_del(struct kref *kref) { + struct device_link *link = container_of(kref, struct device_link, kref); + dev_info(link->consumer, "Dropping the link to %s\n", dev_name(link->supplier)); @@ -305,8 +310,10 @@ static void __device_link_del(struct device_link *link) call_srcu(&device_links_srcu, &link->rcu_head, __device_link_free_srcu); } #else /* !CONFIG_SRCU */ -static void __device_link_del(struct device_link *link) +static void __device_link_del(struct kref *kref) { + struct device_link *link = container_of(kref, struct device_link, kref); + dev_info(link->consumer, "Dropping the link to %s\n", dev_name(link->supplier)); @@ -324,13 +331,15 @@ static void __device_link_del(struct device_link *link) * @link: Device link to delete. * * The caller must ensure proper synchronization of this function with runtime - * PM. + * PM. If the link was added multiple times, it needs to be deleted as often. + * Care is required for hotplugged devices: Their links are purged on removal + * and calling device_link_del() is then no longer allowed. */ void device_link_del(struct device_link *link) { device_links_write_lock(); device_pm_lock(); - __device_link_del(link); + kref_put(&link->kref, __device_link_del); device_pm_unlock(); device_links_write_unlock(); } @@ -444,7 +453,7 @@ static void __device_links_no_driver(struct device *dev) continue; if (link->flags & DL_FLAG_AUTOREMOVE) - __device_link_del(link); + kref_put(&link->kref, __device_link_del); else if (link->status != DL_STATE_SUPPLIER_UNBIND) WRITE_ONCE(link->status, DL_STATE_AVAILABLE); } @@ -597,13 +606,13 @@ static void device_links_purge(struct device *dev) list_for_each_entry_safe_reverse(link, ln, &dev->links.suppliers, c_node) { WARN_ON(link->status == DL_STATE_ACTIVE); - __device_link_del(link); + __device_link_del(&link->kref); } list_for_each_entry_safe_reverse(link, ln, &dev->links.consumers, s_node) { WARN_ON(link->status != DL_STATE_DORMANT && link->status != DL_STATE_NONE); - __device_link_del(link); + __device_link_del(&link->kref); } device_links_write_unlock(); diff --git a/include/linux/device.h b/include/linux/device.h index b093405ed525..abf952c82c6d 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -769,6 +769,7 @@ enum device_link_state { * @status: The state of the link (with respect to the presence of drivers). * @flags: Link flags. * @rpm_active: Whether or not the consumer device is runtime-PM-active. + * @kref: Count repeated addition of the same link. * @rcu_head: An RCU head to use for deferred execution of SRCU callbacks. */ struct device_link { @@ -779,6 +780,7 @@ struct device_link { enum device_link_state status; u32 flags; bool rpm_active; + struct kref kref; #ifdef CONFIG_SRCU struct rcu_head rcu_head; #endif -- cgit v1.2.3 From d417e0691ac00d35c4e6b90fc3fc85631a7865ad Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 22 Feb 2018 11:29:44 +0530 Subject: cpufreq: Validate frequency table in the core By design, cpufreq drivers are responsible for calling cpufreq_frequency_table_cpuinfo() from their ->init() callbacks to validate the frequency table. However, if a cpufreq driver is buggy and fails to do so properly, it lead to unexpected behavior of the driver or the cpufreq core at a later point in time. It would be better if the core could validate the frequency table during driver initialization. To that end, introduce cpufreq_table_validate_and_sort() and make the cpufreq core call it right after invoking the ->init() callback of the driver and destroy the cpufreq policy if the table is invalid. For the time being the validation of the table happens twice, once from the driver and then from the core. The individual drivers will be updated separately to drop table validation if they don't need it for other reasons. The frequency table is marked "sorted" or "unsorted" by the new helper now instead of in cpufreq_table_validate_and_show(), as it should only be done after validating the table (which the drivers won't do going forward). Signed-off-by: Viresh Kumar [ rjw: Subject/changelog ] Signed-off-by: Rafael J. Wysocki --- drivers/cpufreq/cpufreq.c | 13 +++++++++---- drivers/cpufreq/freq_table.c | 16 +++++++++++++++- include/linux/cpufreq.h | 1 + 3 files changed, 25 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 8814c572e263..239063fb6afc 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -1219,6 +1219,10 @@ static int cpufreq_online(unsigned int cpu) goto out_free_policy; } + ret = cpufreq_table_validate_and_sort(policy); + if (ret) + goto out_exit_policy; + down_write(&policy->rwsem); if (new_policy) { @@ -1249,7 +1253,7 @@ static int cpufreq_online(unsigned int cpu) policy->cur = cpufreq_driver->get(policy->cpu); if (!policy->cur) { pr_err("%s: ->get() failed\n", __func__); - goto out_exit_policy; + goto out_destroy_policy; } } @@ -1296,7 +1300,7 @@ static int cpufreq_online(unsigned int cpu) if (new_policy) { ret = cpufreq_add_dev_interface(policy); if (ret) - goto out_exit_policy; + goto out_destroy_policy; cpufreq_stats_create_table(policy); @@ -1311,7 +1315,7 @@ static int cpufreq_online(unsigned int cpu) __func__, cpu, ret); /* cpufreq_policy_free() will notify based on this */ new_policy = false; - goto out_exit_policy; + goto out_destroy_policy; } up_write(&policy->rwsem); @@ -1326,12 +1330,13 @@ static int cpufreq_online(unsigned int cpu) return 0; -out_exit_policy: +out_destroy_policy: for_each_cpu(j, policy->real_cpus) remove_cpu_dev_symlink(policy, get_cpu_device(j)); up_write(&policy->rwsem); +out_exit_policy: if (cpufreq_driver->exit) cpufreq_driver->exit(policy); diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c index 6d007f824ca7..10e119ae66dd 100644 --- a/drivers/cpufreq/freq_table.c +++ b/drivers/cpufreq/freq_table.c @@ -362,10 +362,24 @@ int cpufreq_table_validate_and_show(struct cpufreq_policy *policy, return ret; policy->freq_table = table; - return set_freq_table_sorted(policy); + return 0; } EXPORT_SYMBOL_GPL(cpufreq_table_validate_and_show); +int cpufreq_table_validate_and_sort(struct cpufreq_policy *policy) +{ + int ret; + + if (!policy->freq_table) + return 0; + + ret = cpufreq_frequency_table_cpuinfo(policy, policy->freq_table); + if (ret) + return ret; + + return set_freq_table_sorted(policy); +} + MODULE_AUTHOR("Dominik Brodowski "); MODULE_DESCRIPTION("CPUfreq frequency table helpers"); MODULE_LICENSE("GPL"); diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 21e8d248d956..1fe49724da9e 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -962,6 +962,7 @@ extern struct freq_attr cpufreq_freq_attr_scaling_boost_freqs; extern struct freq_attr *cpufreq_generic_attr[]; int cpufreq_table_validate_and_show(struct cpufreq_policy *policy, struct cpufreq_frequency_table *table); +int cpufreq_table_validate_and_sort(struct cpufreq_policy *policy); unsigned int cpufreq_generic_get(unsigned int cpu); int cpufreq_generic_init(struct cpufreq_policy *policy, -- cgit v1.2.3 From 9c2c2e62df3fa30fb13fbeb7512a4eede729383b Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 27 Feb 2018 01:56:06 +0100 Subject: net: phy: Restore phy_resume() locking assumption commit f5e64032a799 ("net: phy: fix resume handling") changes the locking semantics for phy_resume() such that the caller now needs to hold the phy mutex. Not all call sites were adopted to this new semantic, resulting in warnings from the added WARN_ON(!mutex_is_locked(&phydev->lock)). Rather than change the semantics, add a __phy_resume() and restore the old behavior of phy_resume(). Reported-by: Heiner Kallweit Fixes: f5e64032a799 ("net: phy: fix resume handling") Signed-off-by: Andrew Lunn Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/phy/phy.c | 2 +- drivers/net/phy/phy_device.c | 18 +++++++++++++----- include/linux/phy.h | 1 + 3 files changed, 15 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index e3e29c2b028b..a6f924fee584 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -819,7 +819,7 @@ void phy_start(struct phy_device *phydev) break; case PHY_HALTED: /* if phy was suspended, bring the physical link up again */ - phy_resume(phydev); + __phy_resume(phydev); /* make sure interrupts are re-enabled for the PHY */ if (phy_interrupt_is_valid(phydev)) { diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index d39ae77707ef..478405e544cc 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -135,9 +135,7 @@ static int mdio_bus_phy_resume(struct device *dev) if (!mdio_bus_phy_may_suspend(phydev)) goto no_resume; - mutex_lock(&phydev->lock); ret = phy_resume(phydev); - mutex_unlock(&phydev->lock); if (ret < 0) return ret; @@ -1041,9 +1039,7 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, if (err) goto error; - mutex_lock(&phydev->lock); phy_resume(phydev); - mutex_unlock(&phydev->lock); phy_led_triggers_register(phydev); return err; @@ -1172,7 +1168,7 @@ int phy_suspend(struct phy_device *phydev) } EXPORT_SYMBOL(phy_suspend); -int phy_resume(struct phy_device *phydev) +int __phy_resume(struct phy_device *phydev) { struct phy_driver *phydrv = to_phy_driver(phydev->mdio.dev.driver); int ret = 0; @@ -1189,6 +1185,18 @@ int phy_resume(struct phy_device *phydev) return ret; } +EXPORT_SYMBOL(__phy_resume); + +int phy_resume(struct phy_device *phydev) +{ + int ret; + + mutex_lock(&phydev->lock); + ret = __phy_resume(phydev); + mutex_unlock(&phydev->lock); + + return ret; +} EXPORT_SYMBOL(phy_resume); int phy_loopback(struct phy_device *phydev, bool enable) diff --git a/include/linux/phy.h b/include/linux/phy.h index 5a0c3e53e7c2..d7069539f351 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -924,6 +924,7 @@ void phy_device_remove(struct phy_device *phydev); int phy_init_hw(struct phy_device *phydev); int phy_suspend(struct phy_device *phydev); int phy_resume(struct phy_device *phydev); +int __phy_resume(struct phy_device *phydev); int phy_loopback(struct phy_device *phydev, bool enable); struct phy_device *phy_attach(struct net_device *dev, const char *bus_id, phy_interface_t interface); -- cgit v1.2.3 From 91295d79d65892eabd02a2a75fd4ac88197d17a1 Mon Sep 17 00:00:00 2001 From: Sinan Kaya Date: Tue, 27 Feb 2018 14:14:08 -0600 Subject: PCI: Handle FLR failure and allow other reset types pci_flr_wait() and pci_af_flr() functions assume graceful return even though the device is inaccessible under error conditions. Return -ENOTTY in error cases so that __pci_reset_function_locked() can try other reset types if AF_FLR/FLR reset fails. Signed-off-by: Sinan Kaya Signed-off-by: Bjorn Helgaas Reviewed-by: Christoph Hellwig --- drivers/pci/pci.c | 18 ++++++++++-------- include/linux/pci.h | 2 +- 2 files changed, 11 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 660c848aa14a..7aa11b1fbee3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4017,7 +4017,7 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) } EXPORT_SYMBOL(pci_wait_for_pending_transaction); -static void pci_flr_wait(struct pci_dev *dev) +static int pci_flr_wait(struct pci_dev *dev) { int delay = 1, timeout = 60000; u32 id; @@ -4046,7 +4046,7 @@ static void pci_flr_wait(struct pci_dev *dev) if (delay > timeout) { pci_warn(dev, "not ready %dms after FLR; giving up\n", 100 + delay - 1); - return; + return -ENOTTY; } if (delay > 1000) @@ -4060,6 +4060,8 @@ static void pci_flr_wait(struct pci_dev *dev) if (delay > 1000) pci_info(dev, "ready %dms after FLR\n", 100 + delay - 1); + + return 0; } /** @@ -4088,13 +4090,13 @@ static bool pcie_has_flr(struct pci_dev *dev) * device supports FLR before calling this function, e.g. by using the * pcie_has_flr() helper. */ -void pcie_flr(struct pci_dev *dev) +int pcie_flr(struct pci_dev *dev) { if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); - pci_flr_wait(dev); + return pci_flr_wait(dev); } EXPORT_SYMBOL_GPL(pcie_flr); @@ -4127,8 +4129,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); - pci_flr_wait(dev); - return 0; + return pci_flr_wait(dev); } /** @@ -4379,8 +4380,9 @@ int __pci_reset_function_locked(struct pci_dev *dev) if (rc != -ENOTTY) return rc; if (pcie_has_flr(dev)) { - pcie_flr(dev); - return 0; + rc = pcie_flr(dev); + if (rc != -ENOTTY) + return rc; } rc = pci_af_flr(dev, 0); if (rc != -ENOTTY) diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1beda008..af75d9d76189 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1082,7 +1082,7 @@ int pcie_get_mps(struct pci_dev *dev); int pcie_set_mps(struct pci_dev *dev, int mps); int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width); -void pcie_flr(struct pci_dev *dev); +int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); int pci_reset_function_locked(struct pci_dev *dev); -- cgit v1.2.3 From 28b0f8a6962a24ed21737578f3b1b07424635c9e Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Tue, 13 Feb 2018 07:38:08 -0800 Subject: tty: make n_tty_read() always abort if hangup is in progress A tty is hung up by __tty_hangup() setting file->f_op to hung_up_tty_fops, which is skipped on ttys whose write operation isn't tty_write(). This means that, for example, /dev/console whose write op is redirected_tty_write() is never actually marked hung up. Because n_tty_read() uses the hung up status to decide whether to abort the waiting readers, the lack of hung-up marking can lead to the following scenario. 1. A session contains two processes. The leader and its child. The child ignores SIGHUP. 2. The leader exits and starts disassociating from the controlling terminal (/dev/console). 3. __tty_hangup() skips setting f_op to hung_up_tty_fops. 4. SIGHUP is delivered and ignored. 5. tty_ldisc_hangup() is invoked. It wakes up the waits which should clear the read lockers of tty->ldisc_sem. 6. The reader wakes up but because tty_hung_up_p() is false, it doesn't abort and goes back to sleep while read-holding tty->ldisc_sem. 7. The leader progresses to tty_ldisc_lock() in tty_ldisc_hangup() and is now stuck in D sleep indefinitely waiting for tty->ldisc_sem. The following is Alan's explanation on why some ttys aren't hung up. http://lkml.kernel.org/r/20171101170908.6ad08580@alans-desktop 1. It broke the serial consoles because they would hang up and close down the hardware. With tty_port that *should* be fixable properly for any cases remaining. 2. The console layer was (and still is) completely broken and doens't refcount properly. So if you turn on console hangups it breaks (as indeed does freeing consoles and half a dozen other things). As neither can be fixed quickly, this patch works around the problem by introducing a new flag, TTY_HUPPING, which is used solely to tell n_tty_read() that hang-up is in progress for the console and the readers should be aborted regardless of the hung-up status of the device. The following is a sample hung task warning caused by this issue. INFO: task agetty:2662 blocked for more than 120 seconds. Not tainted 4.11.3-dbg-tty-lockup-02478-gfd6c7ee-dirty #28 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. 0 2662 1 0x00000086 Call Trace: __schedule+0x267/0x890 schedule+0x36/0x80 schedule_timeout+0x23c/0x2e0 ldsem_down_write+0xce/0x1f6 tty_ldisc_lock+0x16/0x30 tty_ldisc_hangup+0xb3/0x1b0 __tty_hangup+0x300/0x410 disassociate_ctty+0x6c/0x290 do_exit+0x7ef/0xb00 do_group_exit+0x3f/0xa0 get_signal+0x1b3/0x5d0 do_signal+0x28/0x660 exit_to_usermode_loop+0x46/0x86 do_syscall_64+0x9c/0xb0 entry_SYSCALL64_slow_path+0x25/0x25 The following is the repro. Run "$PROG /dev/console". The parent process hangs in D state. #include #include #include #include #include #include #include #include #include #include #include #include int main(int argc, char **argv) { struct sigaction sact = { .sa_handler = SIG_IGN }; struct timespec ts1s = { .tv_sec = 1 }; pid_t pid; int fd; if (argc < 2) { fprintf(stderr, "test-hung-tty /dev/$TTY\n"); return 1; } /* fork a child to ensure that it isn't already the session leader */ pid = fork(); if (pid < 0) { perror("fork"); return 1; } if (pid > 0) { /* top parent, wait for everyone */ while (waitpid(-1, NULL, 0) >= 0) ; if (errno != ECHILD) perror("waitpid"); return 0; } /* new session, start a new session and set the controlling tty */ if (setsid() < 0) { perror("setsid"); return 1; } fd = open(argv[1], O_RDWR); if (fd < 0) { perror("open"); return 1; } if (ioctl(fd, TIOCSCTTY, 1) < 0) { perror("ioctl"); return 1; } /* fork a child, sleep a bit and exit */ pid = fork(); if (pid < 0) { perror("fork"); return 1; } if (pid > 0) { nanosleep(&ts1s, NULL); printf("Session leader exiting\n"); exit(0); } /* * The child ignores SIGHUP and keeps reading from the controlling * tty. Because SIGHUP is ignored, the child doesn't get killed on * parent exit and the bug in n_tty makes the read(2) block the * parent's control terminal hangup attempt. The parent ends up in * D sleep until the child is explicitly killed. */ sigaction(SIGHUP, &sact, NULL); printf("Child reading tty\n"); while (1) { char buf[1024]; if (read(fd, buf, sizeof(buf)) < 0) { perror("read"); return 1; } } return 0; } Signed-off-by: Tejun Heo Cc: Alan Cox Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/tty/n_tty.c | 6 ++++++ drivers/tty/tty_io.c | 9 +++++++++ include/linux/tty.h | 1 + 3 files changed, 16 insertions(+) (limited to 'include/linux') diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c index 5c0e59e8fe46..cbe98bc2b998 100644 --- a/drivers/tty/n_tty.c +++ b/drivers/tty/n_tty.c @@ -2180,6 +2180,12 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file, } if (tty_hung_up_p(file)) break; + /* + * Abort readers for ttys which never actually + * get hung up. See __tty_hangup(). + */ + if (test_bit(TTY_HUPPING, &tty->flags)) + break; if (!timeout) break; if (file->f_flags & O_NONBLOCK) { diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index eb9133b472f4..63114ea35ec1 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c @@ -586,6 +586,14 @@ static void __tty_hangup(struct tty_struct *tty, int exit_session) return; } + /* + * Some console devices aren't actually hung up for technical and + * historical reasons, which can lead to indefinite interruptible + * sleep in n_tty_read(). The following explicitly tells + * n_tty_read() to abort readers. + */ + set_bit(TTY_HUPPING, &tty->flags); + /* inuse_filps is protected by the single tty lock, this really needs to change if we want to flush the workqueue with the lock held */ @@ -640,6 +648,7 @@ static void __tty_hangup(struct tty_struct *tty, int exit_session) * from the ldisc side, which is now guaranteed. */ set_bit(TTY_HUPPED, &tty->flags); + clear_bit(TTY_HUPPING, &tty->flags); tty_unlock(tty); if (f) diff --git a/include/linux/tty.h b/include/linux/tty.h index 0a6c71e0ad01..47f8af22f216 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -364,6 +364,7 @@ struct tty_file_private { #define TTY_PTY_LOCK 16 /* pty private */ #define TTY_NO_WRITE_SPLIT 17 /* Preserve write boundaries to driver */ #define TTY_HUPPED 18 /* Post driver->hangup() */ +#define TTY_HUPPING 19 /* Hangup in progress */ #define TTY_LDISC_HALTED 22 /* Line discipline is halted */ /* Values for tty->flow_change */ -- cgit v1.2.3 From aad76f2c48b70d993706580c254a89326ad4d7de Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 2 Feb 2018 18:46:36 +0200 Subject: serial, pci_ids: Move duplicate IDs to PCI IDs database PCI ID database is for IDs used across several drivers. Here is the case for SUNIX combo cards. No functional change intended. Signed-off-by: Andy Shevchenko Signed-off-by: Greg Kroah-Hartman --- drivers/parport/parport_serial.c | 3 --- drivers/tty/serial/8250/8250_pci.c | 3 --- include/linux/pci_ids.h | 3 +++ 3 files changed, 3 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/drivers/parport/parport_serial.c b/drivers/parport/parport_serial.c index e15b4845f7c6..087e847b1da2 100644 --- a/drivers/parport/parport_serial.c +++ b/drivers/parport/parport_serial.c @@ -156,9 +156,6 @@ static struct parport_pc_pci cards[] = { /* sunix_2s1p */ { 1, { { 3, -1 }, } }, }; -#define PCI_VENDOR_ID_SUNIX 0x1fd4 -#define PCI_DEVICE_ID_SUNIX_1999 0x1999 - static struct pci_device_id parport_serial_pci_tbl[] = { /* PCI cards */ { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L, diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 54adf8d56350..881730cd48c1 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -1685,9 +1685,6 @@ pci_wch_ch38x_setup(struct serial_private *priv, #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e -#define PCI_VENDOR_ID_SUNIX 0x1fd4 -#define PCI_DEVICE_ID_SUNIX_1999 0x1999 - #define PCIE_VENDOR_ID_WCH 0x1c00 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a6b30667a331..e4b0387956cf 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2556,6 +2556,9 @@ #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 #define PCI_DEVICE_ID_TEHUTI_3014 0x3014 +#define PCI_VENDOR_ID_SUNIX 0x1fd4 +#define PCI_DEVICE_ID_SUNIX_1999 0x1999 + #define PCI_VENDOR_ID_HINT 0x3388 #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 -- cgit v1.2.3 From a9c79364df324a69ba1b71accd5b8a3155e570ac Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 27 Feb 2018 15:53:02 +0000 Subject: phylink,sfp: negotiate interface format with MAC Negotiate the interface format with the MAC rather than requiring it to be a fixed type specified solely by the SFP module. This allows modules that can work with several different interface signalling formats to select a format compatible with the MAC - for example, a Fiber module supporing Gigabit ethernet and faster connected to a Gigabit only MAC needs to select the 1000BASE-X mode. Signed-off-by: Russell King Signed-off-by: David S. Miller --- drivers/net/phy/phylink.c | 33 ++++++++------- drivers/net/phy/sfp-bus.c | 101 ++++++++++++++++++---------------------------- include/linux/sfp.h | 18 +++++---- 3 files changed, 68 insertions(+), 84 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 6ac8b29b2dc3..27327c917a59 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1584,25 +1584,14 @@ static int phylink_sfp_module_insert(void *upstream, bool changed; u8 port; - sfp_parse_support(pl->sfp_bus, id, support); - port = sfp_parse_port(pl->sfp_bus, id, support); - iface = sfp_parse_interface(pl->sfp_bus, id); - ASSERT_RTNL(); - switch (iface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_1000BASEX: - case PHY_INTERFACE_MODE_2500BASEX: - case PHY_INTERFACE_MODE_10GKR: - break; - default: - return -EINVAL; - } + sfp_parse_support(pl->sfp_bus, id, support); + port = sfp_parse_port(pl->sfp_bus, id, support); memset(&config, 0, sizeof(config)); linkmode_copy(config.advertising, support); - config.interface = iface; + config.interface = PHY_INTERFACE_MODE_NA; config.speed = SPEED_UNKNOWN; config.duplex = DUPLEX_UNKNOWN; config.pause = MLO_PAUSE_AN; @@ -1610,6 +1599,22 @@ static int phylink_sfp_module_insert(void *upstream, /* Ignore errors if we're expecting a PHY to attach later */ ret = phylink_validate(pl, support, &config); + if (ret) { + netdev_err(pl->netdev, "validation with support %*pb failed: %d\n", + __ETHTOOL_LINK_MODE_MASK_NBITS, support, ret); + return ret; + } + + iface = sfp_select_interface(pl->sfp_bus, id, config.advertising); + if (iface == PHY_INTERFACE_MODE_NA) { + netdev_err(pl->netdev, + "selection of interface failed, advertisment %*pb\n", + __ETHTOOL_LINK_MODE_MASK_NBITS, config.advertising); + return -EINVAL; + } + + config.interface = iface; + ret = phylink_validate(pl, support, &config); if (ret) { netdev_err(pl->netdev, "validation of %s/%s with support %*pb failed: %d\n", phylink_an_mode_str(MLO_AN_INBAND), diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c index 15749428679e..3d4ff5d0d2a6 100644 --- a/drivers/net/phy/sfp-bus.c +++ b/drivers/net/phy/sfp-bus.c @@ -105,68 +105,6 @@ int sfp_parse_port(struct sfp_bus *bus, const struct sfp_eeprom_id *id, } EXPORT_SYMBOL_GPL(sfp_parse_port); -/** - * sfp_parse_interface() - Parse the phy_interface_t - * @bus: a pointer to the &struct sfp_bus structure for the sfp module - * @id: a pointer to the module's &struct sfp_eeprom_id - * - * Derive the phy_interface_t mode for the information found in the - * module's identifying EEPROM. There is no standard or defined way - * to derive this information, so we use some heuristics. - * - * If the encoding is 64b66b, then the module must be >= 10G, so - * return %PHY_INTERFACE_MODE_10GKR. - * - * If it's 8b10b, then it's 1G or slower. If it's definitely a fibre - * module, return %PHY_INTERFACE_MODE_1000BASEX mode, otherwise return - * %PHY_INTERFACE_MODE_SGMII mode. - * - * If the encoding is not known, return %PHY_INTERFACE_MODE_NA. - */ -phy_interface_t sfp_parse_interface(struct sfp_bus *bus, - const struct sfp_eeprom_id *id) -{ - phy_interface_t iface; - - /* Setting the serdes link mode is guesswork: there's no field in - * the EEPROM which indicates what mode should be used. - * - * If the module wants 64b66b, then it must be >= 10G. - * - * If it's a gigabit-only fiber module, it probably does not have - * a PHY, so switch to 802.3z negotiation mode. Otherwise, switch - * to SGMII mode (which is required to support non-gigabit speeds). - */ - switch (id->base.encoding) { - case SFP_ENCODING_8472_64B66B: - iface = PHY_INTERFACE_MODE_10GKR; - break; - - case SFP_ENCODING_8B10B: - if (!id->base.e1000_base_t && - !id->base.e100_base_lx && - !id->base.e100_base_fx) - iface = PHY_INTERFACE_MODE_1000BASEX; - else - iface = PHY_INTERFACE_MODE_SGMII; - break; - - default: - if (id->base.e1000_base_cx) { - iface = PHY_INTERFACE_MODE_1000BASEX; - break; - } - - iface = PHY_INTERFACE_MODE_NA; - dev_err(bus->sfp_dev, - "SFP module encoding does not support 8b10b nor 64b66b\n"); - break; - } - - return iface; -} -EXPORT_SYMBOL_GPL(sfp_parse_interface); - /** * sfp_parse_support() - Parse the eeprom id for supported link modes * @bus: a pointer to the &struct sfp_bus structure for the sfp module @@ -296,6 +234,45 @@ void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id, } EXPORT_SYMBOL_GPL(sfp_parse_support); +/** + * sfp_select_interface() - Select appropriate phy_interface_t mode + * @bus: a pointer to the &struct sfp_bus structure for the sfp module + * @id: a pointer to the module's &struct sfp_eeprom_id + * @link_modes: ethtool link modes mask + * + * Derive the phy_interface_t mode for the information found in the + * module's identifying EEPROM and the link modes mask. There is no + * standard or defined way to derive this information, so we decide + * based upon the link mode mask. + */ +phy_interface_t sfp_select_interface(struct sfp_bus *bus, + const struct sfp_eeprom_id *id, + unsigned long *link_modes) +{ + if (phylink_test(link_modes, 10000baseCR_Full) || + phylink_test(link_modes, 10000baseSR_Full) || + phylink_test(link_modes, 10000baseLR_Full) || + phylink_test(link_modes, 10000baseLRM_Full) || + phylink_test(link_modes, 10000baseER_Full)) + return PHY_INTERFACE_MODE_10GKR; + + if (phylink_test(link_modes, 2500baseX_Full)) + return PHY_INTERFACE_MODE_2500BASEX; + + if (id->base.e1000_base_t || + id->base.e100_base_lx || + id->base.e100_base_fx) + return PHY_INTERFACE_MODE_SGMII; + + if (phylink_test(link_modes, 1000baseX_Full)) + return PHY_INTERFACE_MODE_1000BASEX; + + dev_warn(bus->sfp_dev, "Unable to ascertain link mode\n"); + + return PHY_INTERFACE_MODE_NA; +} +EXPORT_SYMBOL_GPL(sfp_select_interface); + static LIST_HEAD(sfp_buses); static DEFINE_MUTEX(sfp_mutex); diff --git a/include/linux/sfp.h b/include/linux/sfp.h index e724d5a3dd80..ebce9e24906a 100644 --- a/include/linux/sfp.h +++ b/include/linux/sfp.h @@ -422,10 +422,11 @@ struct sfp_upstream_ops { #if IS_ENABLED(CONFIG_SFP) int sfp_parse_port(struct sfp_bus *bus, const struct sfp_eeprom_id *id, unsigned long *support); -phy_interface_t sfp_parse_interface(struct sfp_bus *bus, - const struct sfp_eeprom_id *id); void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id, unsigned long *support); +phy_interface_t sfp_select_interface(struct sfp_bus *bus, + const struct sfp_eeprom_id *id, + unsigned long *link_modes); int sfp_get_module_info(struct sfp_bus *bus, struct ethtool_modinfo *modinfo); int sfp_get_module_eeprom(struct sfp_bus *bus, struct ethtool_eeprom *ee, @@ -444,18 +445,19 @@ static inline int sfp_parse_port(struct sfp_bus *bus, return PORT_OTHER; } -static inline phy_interface_t sfp_parse_interface(struct sfp_bus *bus, - const struct sfp_eeprom_id *id) -{ - return PHY_INTERFACE_MODE_NA; -} - static inline void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id, unsigned long *support) { } +static inline phy_interface_t sfp_select_interface(struct sfp_bus *bus, + const struct sfp_eeprom_id *id, + unsigned long *link_modes) +{ + return PHY_INTERFACE_MODE_NA; +} + static inline int sfp_get_module_info(struct sfp_bus *bus, struct ethtool_modinfo *modinfo) { -- cgit v1.2.3 From aa4f886f3893f88146e8e02fd1e9c5c9e43cbcc1 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 28 Mar 2017 11:36:07 +0100 Subject: firmware: arm_scmi: add basic driver infrastructure for SCMI The SCMI is intended to allow OSPM to manage various functions that are provided by the hardware platform it is running on, including power and performance functions. SCMI provides two levels of abstraction, protocols and transports. Protocols define individual groups of system control and management messages. A protocol specification describes the messages that it supports. Transports describe the method by which protocol messages are communicated between agents and the platform. This patch adds basic infrastructure to manage the message allocation, initialisation, packing/unpacking and shared memory management. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- MAINTAINERS | 3 +- drivers/firmware/Kconfig | 21 ++ drivers/firmware/Makefile | 1 + drivers/firmware/arm_scmi/Makefile | 2 + drivers/firmware/arm_scmi/common.h | 66 ++++ drivers/firmware/arm_scmi/driver.c | 678 +++++++++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 16 + 7 files changed, 786 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/Makefile create mode 100644 drivers/firmware/arm_scmi/common.h create mode 100644 drivers/firmware/arm_scmi/driver.c create mode 100644 include/linux/scmi_protocol.h (limited to 'include/linux') diff --git a/MAINTAINERS b/MAINTAINERS index 5c8c55ba22a3..7cede6e7dfed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13387,7 +13387,8 @@ F: Documentation/devicetree/bindings/arm/arm,sc[mp]i.txt F: drivers/clk/clk-scpi.c F: drivers/cpufreq/scpi-cpufreq.c F: drivers/firmware/arm_scpi.c -F: include/linux/scpi_protocol.h +F: drivers/firmware/arm_scmi/ +F: include/linux/sc[mp]i_protocol.h SYSTEM RESET/SHUTDOWN DRIVERS M: Sebastian Reichel diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index b7c748248e53..704961e0473a 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -19,6 +19,27 @@ config ARM_PSCI_CHECKER on and off through hotplug, so for now torture tests and PSCI checker are mutually exclusive. +config ARM_SCMI_PROTOCOL + bool "ARM System Control and Management Interface (SCMI) Message Protocol" + depends on ARM || ARM64 || COMPILE_TEST + depends on MAILBOX + help + ARM System Control and Management Interface (SCMI) protocol is a + set of operating system-independent software interfaces that are + used in system management. SCMI is extensible and currently provides + interfaces for: Discovery and self-description of the interfaces + it supports, Power domain management which is the ability to place + a given device or domain into the various power-saving states that + it supports, Performance management which is the ability to control + the performance of a domain that is composed of compute engines + such as application processors and other accelerators, Clock + management which is the ability to set and inquire rates on platform + managed clocks and Sensor management which is the ability to read + sensor data, and be notified of sensor value. + + This protocol library provides interface for all the client drivers + making use of the features offered by the SCMI. + config ARM_SCPI_PROTOCOL tristate "ARM System Control and Power Interface (SCPI) Message Protocol" depends on ARM || ARM64 || COMPILE_TEST diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index b248238ddc6a..e18a041cfc53 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o +obj-$(CONFIG_ARM_SCMI_PROTOCOL) += arm_scmi/ obj-y += broadcom/ obj-y += meson/ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile new file mode 100644 index 000000000000..b2a24ba2b636 --- /dev/null +++ b/drivers/firmware/arm_scmi/Makefile @@ -0,0 +1,2 @@ +obj-y = scmi-driver.o +scmi-driver-y = driver.o diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h new file mode 100644 index 000000000000..d57eb1862f68 --- /dev/null +++ b/drivers/firmware/arm_scmi/common.h @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Message Protocol + * driver common header file containing some definitions, structures + * and function prototypes used in all the different SCMI protocols. + * + * Copyright (C) 2018 ARM Ltd. + */ + +#include +#include +#include + +/** + * struct scmi_msg_hdr - Message(Tx/Rx) header + * + * @id: The identifier of the command being sent + * @protocol_id: The identifier of the protocol used to send @id command + * @seq: The token to identify the message. when a message/command returns, + * the platform returns the whole message header unmodified including + * the token. + */ +struct scmi_msg_hdr { + u8 id; + u8 protocol_id; + u16 seq; + u32 status; + bool poll_completion; +}; + +/** + * struct scmi_msg - Message(Tx/Rx) structure + * + * @buf: Buffer pointer + * @len: Length of data in the Buffer + */ +struct scmi_msg { + void *buf; + size_t len; +}; + +/** + * struct scmi_xfer - Structure representing a message flow + * + * @hdr: Transmit message header + * @tx: Transmit message + * @rx: Receive message, the buffer should be pre-allocated to store + * message. If request-ACK protocol is used, we can reuse the same + * buffer for the rx path as we use for the tx path. + * @done: completion event + */ + +struct scmi_xfer { + void *con_priv; + struct scmi_msg_hdr hdr; + struct scmi_msg tx; + struct scmi_msg rx; + struct completion done; +}; + +void scmi_one_xfer_put(const struct scmi_handle *h, struct scmi_xfer *xfer); +int scmi_do_xfer(const struct scmi_handle *h, struct scmi_xfer *xfer); +int scmi_one_xfer_init(const struct scmi_handle *h, u8 msg_id, u8 prot_id, + size_t tx_size, size_t rx_size, struct scmi_xfer **p); +int scmi_handle_put(const struct scmi_handle *handle); +struct scmi_handle *scmi_handle_get(struct device *dev); diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c new file mode 100644 index 000000000000..7824cce54373 --- /dev/null +++ b/drivers/firmware/arm_scmi/driver.c @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Message Protocol driver + * + * SCMI Message Protocol is used between the System Control Processor(SCP) + * and the Application Processors(AP). The Message Handling Unit(MHU) + * provides a mechanism for inter-processor communication between SCP's + * Cortex M3 and AP. + * + * SCP offers control and management of the core/cluster power states, + * various power domain DVFS including the core/cluster, certain system + * clocks configuration, thermal sensors and many others. + * + * Copyright (C) 2018 ARM Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" + +#define MSG_ID_SHIFT 0 +#define MSG_ID_MASK 0xff +#define MSG_TYPE_SHIFT 8 +#define MSG_TYPE_MASK 0x3 +#define MSG_PROTOCOL_ID_SHIFT 10 +#define MSG_PROTOCOL_ID_MASK 0xff +#define MSG_TOKEN_ID_SHIFT 18 +#define MSG_TOKEN_ID_MASK 0x3ff +#define MSG_XTRACT_TOKEN(header) \ + (((header) >> MSG_TOKEN_ID_SHIFT) & MSG_TOKEN_ID_MASK) + +enum scmi_error_codes { + SCMI_SUCCESS = 0, /* Success */ + SCMI_ERR_SUPPORT = -1, /* Not supported */ + SCMI_ERR_PARAMS = -2, /* Invalid Parameters */ + SCMI_ERR_ACCESS = -3, /* Invalid access/permission denied */ + SCMI_ERR_ENTRY = -4, /* Not found */ + SCMI_ERR_RANGE = -5, /* Value out of range */ + SCMI_ERR_BUSY = -6, /* Device busy */ + SCMI_ERR_COMMS = -7, /* Communication Error */ + SCMI_ERR_GENERIC = -8, /* Generic Error */ + SCMI_ERR_HARDWARE = -9, /* Hardware Error */ + SCMI_ERR_PROTOCOL = -10,/* Protocol Error */ + SCMI_ERR_MAX +}; + +/* List of all SCMI devices active in system */ +static LIST_HEAD(scmi_list); +/* Protection for the entire list */ +static DEFINE_MUTEX(scmi_list_mutex); + +/** + * struct scmi_xfers_info - Structure to manage transfer information + * + * @xfer_block: Preallocated Message array + * @xfer_alloc_table: Bitmap table for allocated messages. + * Index of this bitmap table is also used for message + * sequence identifier. + * @xfer_lock: Protection for message allocation + */ +struct scmi_xfers_info { + struct scmi_xfer *xfer_block; + unsigned long *xfer_alloc_table; + /* protect transfer allocation */ + spinlock_t xfer_lock; +}; + +/** + * struct scmi_desc - Description of SoC integration + * + * @max_rx_timeout_ms: Timeout for communication with SoC (in Milliseconds) + * @max_msg: Maximum number of messages that can be pending + * simultaneously in the system + * @max_msg_size: Maximum size of data per message that can be handled. + */ +struct scmi_desc { + int max_rx_timeout_ms; + int max_msg; + int max_msg_size; +}; + +/** + * struct scmi_info - Structure representing a SCMI instance + * + * @dev: Device pointer + * @desc: SoC description for this instance + * @handle: Instance of SCMI handle to send to clients + * @cl: Mailbox Client + * @tx_chan: Transmit mailbox channel + * @tx_payload: Transmit mailbox channel payload area + * @minfo: Message info + * @node: list head + * @users: Number of users of this instance + */ +struct scmi_info { + struct device *dev; + const struct scmi_desc *desc; + struct scmi_handle handle; + struct mbox_client cl; + struct mbox_chan *tx_chan; + void __iomem *tx_payload; + struct scmi_xfers_info minfo; + struct list_head node; + int users; +}; + +#define client_to_scmi_info(c) container_of(c, struct scmi_info, cl) +#define handle_to_scmi_info(h) container_of(h, struct scmi_info, handle) + +/* + * SCMI specification requires all parameters, message headers, return + * arguments or any protocol data to be expressed in little endian + * format only. + */ +struct scmi_shared_mem { + __le32 reserved; + __le32 channel_status; +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR BIT(1) +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE BIT(0) + __le32 reserved1[2]; + __le32 flags; +#define SCMI_SHMEM_FLAG_INTR_ENABLED BIT(0) + __le32 length; + __le32 msg_header; + u8 msg_payload[0]; +}; + +static const int scmi_linux_errmap[] = { + /* better than switch case as long as return value is continuous */ + 0, /* SCMI_SUCCESS */ + -EOPNOTSUPP, /* SCMI_ERR_SUPPORT */ + -EINVAL, /* SCMI_ERR_PARAM */ + -EACCES, /* SCMI_ERR_ACCESS */ + -ENOENT, /* SCMI_ERR_ENTRY */ + -ERANGE, /* SCMI_ERR_RANGE */ + -EBUSY, /* SCMI_ERR_BUSY */ + -ECOMM, /* SCMI_ERR_COMMS */ + -EIO, /* SCMI_ERR_GENERIC */ + -EREMOTEIO, /* SCMI_ERR_HARDWARE */ + -EPROTO, /* SCMI_ERR_PROTOCOL */ +}; + +static inline int scmi_to_linux_errno(int errno) +{ + if (errno < SCMI_SUCCESS && errno > SCMI_ERR_MAX) + return scmi_linux_errmap[-errno]; + return -EIO; +} + +/** + * scmi_dump_header_dbg() - Helper to dump a message header. + * + * @dev: Device pointer corresponding to the SCMI entity + * @hdr: pointer to header. + */ +static inline void scmi_dump_header_dbg(struct device *dev, + struct scmi_msg_hdr *hdr) +{ + dev_dbg(dev, "Command ID: %x Sequence ID: %x Protocol: %x\n", + hdr->id, hdr->seq, hdr->protocol_id); +} + +static void scmi_fetch_response(struct scmi_xfer *xfer, + struct scmi_shared_mem __iomem *mem) +{ + xfer->hdr.status = ioread32(mem->msg_payload); + /* Skip the length of header and statues in payload area i.e 8 bytes*/ + xfer->rx.len = min_t(size_t, xfer->rx.len, ioread32(&mem->length) - 8); + + /* Take a copy to the rx buffer.. */ + memcpy_fromio(xfer->rx.buf, mem->msg_payload + 4, xfer->rx.len); +} + +/** + * scmi_rx_callback() - mailbox client callback for receive messages + * + * @cl: client pointer + * @m: mailbox message + * + * Processes one received message to appropriate transfer information and + * signals completion of the transfer. + * + * NOTE: This function will be invoked in IRQ context, hence should be + * as optimal as possible. + */ +static void scmi_rx_callback(struct mbox_client *cl, void *m) +{ + u16 xfer_id; + struct scmi_xfer *xfer; + struct scmi_info *info = client_to_scmi_info(cl); + struct scmi_xfers_info *minfo = &info->minfo; + struct device *dev = info->dev; + struct scmi_shared_mem __iomem *mem = info->tx_payload; + + xfer_id = MSG_XTRACT_TOKEN(ioread32(&mem->msg_header)); + + /* + * Are we even expecting this? + */ + if (!test_bit(xfer_id, minfo->xfer_alloc_table)) { + dev_err(dev, "message for %d is not expected!\n", xfer_id); + return; + } + + xfer = &minfo->xfer_block[xfer_id]; + + scmi_dump_header_dbg(dev, &xfer->hdr); + /* Is the message of valid length? */ + if (xfer->rx.len > info->desc->max_msg_size) { + dev_err(dev, "unable to handle %zu xfer(max %d)\n", + xfer->rx.len, info->desc->max_msg_size); + return; + } + + scmi_fetch_response(xfer, mem); + complete(&xfer->done); +} + +/** + * pack_scmi_header() - packs and returns 32-bit header + * + * @hdr: pointer to header containing all the information on message id, + * protocol id and sequence id. + */ +static inline u32 pack_scmi_header(struct scmi_msg_hdr *hdr) +{ + return ((hdr->id & MSG_ID_MASK) << MSG_ID_SHIFT) | + ((hdr->seq & MSG_TOKEN_ID_MASK) << MSG_TOKEN_ID_SHIFT) | + ((hdr->protocol_id & MSG_PROTOCOL_ID_MASK) << MSG_PROTOCOL_ID_SHIFT); +} + +/** + * scmi_tx_prepare() - mailbox client callback to prepare for the transfer + * + * @cl: client pointer + * @m: mailbox message + * + * This function prepares the shared memory which contains the header and the + * payload. + */ +static void scmi_tx_prepare(struct mbox_client *cl, void *m) +{ + struct scmi_xfer *t = m; + struct scmi_info *info = client_to_scmi_info(cl); + struct scmi_shared_mem __iomem *mem = info->tx_payload; + + /* Mark channel busy + clear error */ + iowrite32(0x0, &mem->channel_status); + iowrite32(t->hdr.poll_completion ? 0 : SCMI_SHMEM_FLAG_INTR_ENABLED, + &mem->flags); + iowrite32(sizeof(mem->msg_header) + t->tx.len, &mem->length); + iowrite32(pack_scmi_header(&t->hdr), &mem->msg_header); + if (t->tx.buf) + memcpy_toio(mem->msg_payload, t->tx.buf, t->tx.len); +} + +/** + * scmi_one_xfer_get() - Allocate one message + * + * @handle: SCMI entity handle + * + * Helper function which is used by various command functions that are + * exposed to clients of this driver for allocating a message traffic event. + * + * This function can sleep depending on pending requests already in the system + * for the SCMI entity. Further, this also holds a spinlock to maintain + * integrity of internal data structures. + * + * Return: 0 if all went fine, else corresponding error. + */ +static struct scmi_xfer *scmi_one_xfer_get(const struct scmi_handle *handle) +{ + u16 xfer_id; + struct scmi_xfer *xfer; + unsigned long flags, bit_pos; + struct scmi_info *info = handle_to_scmi_info(handle); + struct scmi_xfers_info *minfo = &info->minfo; + + /* Keep the locked section as small as possible */ + spin_lock_irqsave(&minfo->xfer_lock, flags); + bit_pos = find_first_zero_bit(minfo->xfer_alloc_table, + info->desc->max_msg); + if (bit_pos == info->desc->max_msg) { + spin_unlock_irqrestore(&minfo->xfer_lock, flags); + return ERR_PTR(-ENOMEM); + } + set_bit(bit_pos, minfo->xfer_alloc_table); + spin_unlock_irqrestore(&minfo->xfer_lock, flags); + + xfer_id = bit_pos; + + xfer = &minfo->xfer_block[xfer_id]; + xfer->hdr.seq = xfer_id; + reinit_completion(&xfer->done); + + return xfer; +} + +/** + * scmi_one_xfer_put() - Release a message + * + * @minfo: transfer info pointer + * @xfer: message that was reserved by scmi_one_xfer_get + * + * This holds a spinlock to maintain integrity of internal data structures. + */ +void scmi_one_xfer_put(const struct scmi_handle *handle, struct scmi_xfer *xfer) +{ + unsigned long flags; + struct scmi_info *info = handle_to_scmi_info(handle); + struct scmi_xfers_info *minfo = &info->minfo; + + /* + * Keep the locked section as small as possible + * NOTE: we might escape with smp_mb and no lock here.. + * but just be conservative and symmetric. + */ + spin_lock_irqsave(&minfo->xfer_lock, flags); + clear_bit(xfer->hdr.seq, minfo->xfer_alloc_table); + spin_unlock_irqrestore(&minfo->xfer_lock, flags); +} + +/** + * scmi_do_xfer() - Do one transfer + * + * @info: Pointer to SCMI entity information + * @xfer: Transfer to initiate and wait for response + * + * Return: -ETIMEDOUT in case of no response, if transmit error, + * return corresponding error, else if all goes well, + * return 0. + */ +int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer) +{ + int ret; + int timeout; + struct scmi_info *info = handle_to_scmi_info(handle); + struct device *dev = info->dev; + + ret = mbox_send_message(info->tx_chan, xfer); + if (ret < 0) { + dev_dbg(dev, "mbox send fail %d\n", ret); + return ret; + } + + /* mbox_send_message returns non-negative value on success, so reset */ + ret = 0; + + /* And we wait for the response. */ + timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms); + if (!wait_for_completion_timeout(&xfer->done, timeout)) { + dev_err(dev, "mbox timed out in resp(caller: %pS)\n", + (void *)_RET_IP_); + ret = -ETIMEDOUT; + } else if (xfer->hdr.status) { + ret = scmi_to_linux_errno(xfer->hdr.status); + } + /* + * NOTE: we might prefer not to need the mailbox ticker to manage the + * transfer queueing since the protocol layer queues things by itself. + * Unfortunately, we have to kick the mailbox framework after we have + * received our message. + */ + mbox_client_txdone(info->tx_chan, ret); + + return ret; +} + +/** + * scmi_one_xfer_init() - Allocate and initialise one message + * + * @handle: SCMI entity handle + * @msg_id: Message identifier + * @msg_prot_id: Protocol identifier for the message + * @tx_size: transmit message size + * @rx_size: receive message size + * @p: pointer to the allocated and initialised message + * + * This function allocates the message using @scmi_one_xfer_get and + * initialise the header. + * + * Return: 0 if all went fine with @p pointing to message, else + * corresponding error. + */ +int scmi_one_xfer_init(const struct scmi_handle *handle, u8 msg_id, u8 prot_id, + size_t tx_size, size_t rx_size, struct scmi_xfer **p) +{ + int ret; + struct scmi_xfer *xfer; + struct scmi_info *info = handle_to_scmi_info(handle); + struct device *dev = info->dev; + + /* Ensure we have sane transfer sizes */ + if (rx_size > info->desc->max_msg_size || + tx_size > info->desc->max_msg_size) + return -ERANGE; + + xfer = scmi_one_xfer_get(handle); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "failed to get free message slot(%d)\n", ret); + return ret; + } + + xfer->tx.len = tx_size; + xfer->rx.len = rx_size ? : info->desc->max_msg_size; + xfer->hdr.id = msg_id; + xfer->hdr.protocol_id = prot_id; + xfer->hdr.poll_completion = false; + + *p = xfer; + return 0; +} + +/** + * scmi_handle_get() - Get the SCMI handle for a device + * + * @dev: pointer to device for which we want SCMI handle + * + * NOTE: The function does not track individual clients of the framework + * and is expected to be maintained by caller of SCMI protocol library. + * scmi_handle_put must be balanced with successful scmi_handle_get + * + * Return: pointer to handle if successful, NULL on error + */ +struct scmi_handle *scmi_handle_get(struct device *dev) +{ + struct list_head *p; + struct scmi_info *info; + struct scmi_handle *handle = NULL; + + mutex_lock(&scmi_list_mutex); + list_for_each(p, &scmi_list) { + info = list_entry(p, struct scmi_info, node); + if (dev->parent == info->dev) { + handle = &info->handle; + info->users++; + break; + } + } + mutex_unlock(&scmi_list_mutex); + + return handle; +} + +/** + * scmi_handle_put() - Release the handle acquired by scmi_handle_get + * + * @handle: handle acquired by scmi_handle_get + * + * NOTE: The function does not track individual clients of the framework + * and is expected to be maintained by caller of SCMI protocol library. + * scmi_handle_put must be balanced with successful scmi_handle_get + * + * Return: 0 is successfully released + * if null was passed, it returns -EINVAL; + */ +int scmi_handle_put(const struct scmi_handle *handle) +{ + struct scmi_info *info; + + if (!handle) + return -EINVAL; + + info = handle_to_scmi_info(handle); + mutex_lock(&scmi_list_mutex); + if (!WARN_ON(!info->users)) + info->users--; + mutex_unlock(&scmi_list_mutex); + + return 0; +} + +static const struct scmi_desc scmi_generic_desc = { + .max_rx_timeout_ms = 30, /* we may increase this if required */ + .max_msg = 20, /* Limited by MBOX_TX_QUEUE_LEN */ + .max_msg_size = 128, +}; + +/* Each compatible listed below must have descriptor associated with it */ +static const struct of_device_id scmi_of_match[] = { + { .compatible = "arm,scmi", .data = &scmi_generic_desc }, + { /* Sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, scmi_of_match); + +static int scmi_xfer_info_init(struct scmi_info *sinfo) +{ + int i; + struct scmi_xfer *xfer; + struct device *dev = sinfo->dev; + const struct scmi_desc *desc = sinfo->desc; + struct scmi_xfers_info *info = &sinfo->minfo; + + /* Pre-allocated messages, no more than what hdr.seq can support */ + if (WARN_ON(desc->max_msg >= (MSG_TOKEN_ID_MASK + 1))) { + dev_err(dev, "Maximum message of %d exceeds supported %d\n", + desc->max_msg, MSG_TOKEN_ID_MASK + 1); + return -EINVAL; + } + + info->xfer_block = devm_kcalloc(dev, desc->max_msg, + sizeof(*info->xfer_block), GFP_KERNEL); + if (!info->xfer_block) + return -ENOMEM; + + info->xfer_alloc_table = devm_kcalloc(dev, BITS_TO_LONGS(desc->max_msg), + sizeof(long), GFP_KERNEL); + if (!info->xfer_alloc_table) + return -ENOMEM; + + bitmap_zero(info->xfer_alloc_table, desc->max_msg); + + /* Pre-initialize the buffer pointer to pre-allocated buffers */ + for (i = 0, xfer = info->xfer_block; i < desc->max_msg; i++, xfer++) { + xfer->rx.buf = devm_kcalloc(dev, sizeof(u8), desc->max_msg_size, + GFP_KERNEL); + if (!xfer->rx.buf) + return -ENOMEM; + + xfer->tx.buf = xfer->rx.buf; + init_completion(&xfer->done); + } + + spin_lock_init(&info->xfer_lock); + + return 0; +} + +static int scmi_mailbox_check(struct device_node *np) +{ + struct of_phandle_args arg; + + return of_parse_phandle_with_args(np, "mboxes", "#mbox-cells", 0, &arg); +} + +static int scmi_mbox_free_channel(struct scmi_info *info) +{ + if (!IS_ERR_OR_NULL(info->tx_chan)) { + mbox_free_channel(info->tx_chan); + info->tx_chan = NULL; + } + + return 0; +} + +static int scmi_remove(struct platform_device *pdev) +{ + int ret = 0; + struct scmi_info *info = platform_get_drvdata(pdev); + + mutex_lock(&scmi_list_mutex); + if (info->users) + ret = -EBUSY; + else + list_del(&info->node); + mutex_unlock(&scmi_list_mutex); + + if (!ret) + /* Safe to free channels since no more users */ + return scmi_mbox_free_channel(info); + + return ret; +} + +static inline int scmi_mbox_chan_setup(struct scmi_info *info) +{ + int ret; + struct resource res; + resource_size_t size; + struct device *dev = info->dev; + struct device_node *shmem, *np = dev->of_node; + struct mbox_client *cl; + + cl = &info->cl; + cl->dev = dev; + cl->rx_callback = scmi_rx_callback; + cl->tx_prepare = scmi_tx_prepare; + cl->tx_block = false; + cl->knows_txdone = true; + + shmem = of_parse_phandle(np, "shmem", 0); + ret = of_address_to_resource(shmem, 0, &res); + of_node_put(shmem); + if (ret) { + dev_err(dev, "failed to get SCMI Tx payload mem resource\n"); + return ret; + } + + size = resource_size(&res); + info->tx_payload = devm_ioremap(dev, res.start, size); + if (!info->tx_payload) { + dev_err(dev, "failed to ioremap SCMI Tx payload\n"); + return -EADDRNOTAVAIL; + } + + /* Transmit channel is first entry i.e. index 0 */ + info->tx_chan = mbox_request_channel(cl, 0); + if (IS_ERR(info->tx_chan)) { + ret = PTR_ERR(info->tx_chan); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to request SCMI Tx mailbox\n"); + return ret; + } + + return 0; +} + +static int scmi_probe(struct platform_device *pdev) +{ + int ret; + struct scmi_handle *handle; + const struct scmi_desc *desc; + struct scmi_info *info; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + + /* Only mailbox method supported, check for the presence of one */ + if (scmi_mailbox_check(np)) { + dev_err(dev, "no mailbox found in %pOF\n", np); + return -EINVAL; + } + + desc = of_match_device(scmi_of_match, dev)->data; + + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = dev; + info->desc = desc; + INIT_LIST_HEAD(&info->node); + + ret = scmi_xfer_info_init(info); + if (ret) + return ret; + + platform_set_drvdata(pdev, info); + + handle = &info->handle; + handle->dev = info->dev; + + ret = scmi_mbox_chan_setup(info); + if (ret) + return ret; + + mutex_lock(&scmi_list_mutex); + list_add_tail(&info->node, &scmi_list); + mutex_unlock(&scmi_list_mutex); + + return 0; +} + +static struct platform_driver scmi_driver = { + .driver = { + .name = "arm-scmi", + .of_match_table = scmi_of_match, + }, + .probe = scmi_probe, + .remove = scmi_remove, +}; + +module_platform_driver(scmi_driver); + +MODULE_ALIAS("platform: arm-scmi"); +MODULE_AUTHOR("Sudeep Holla "); +MODULE_DESCRIPTION("ARM SCMI protocol driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h new file mode 100644 index 000000000000..1f0e89b270c6 --- /dev/null +++ b/include/linux/scmi_protocol.h @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SCMI Message Protocol driver header + * + * Copyright (C) 2018 ARM Ltd. + */ +#include + +/** + * struct scmi_handle - Handle returned to ARM SCMI clients for usage. + * + * @dev: pointer to the SCMI device + */ +struct scmi_handle { + struct device *dev; +}; -- cgit v1.2.3 From b6f20ff8bd94ad34032804a60bab5ee56752007e Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 6 Jun 2017 11:16:15 +0100 Subject: firmware: arm_scmi: add common infrastructure and support for base protocol The base protocol describes the properties of the implementation and provide generic error management. The base protocol provides commands to describe protocol version, discover implementation specific attributes and vendor/sub-vendor identification, list of protocols implemented and the various agents are in the system including OSPM and the platform. It also supports registering for notifications of platform errors. This protocol is mandatory. This patch adds support for the same along with some basic infrastructure to add support for other protocols. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/Makefile | 3 +- drivers/firmware/arm_scmi/base.c | 253 +++++++++++++++++++++++++++++++++++++ drivers/firmware/arm_scmi/common.h | 37 ++++++ drivers/firmware/arm_scmi/driver.c | 53 ++++++++ include/linux/scmi_protocol.h | 37 ++++++ 5 files changed, 382 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/base.c (limited to 'include/linux') diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index b2a24ba2b636..5d9c7ef35f0f 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -1,2 +1,3 @@ -obj-y = scmi-driver.o +obj-y = scmi-driver.o scmi-protocols.o scmi-driver-y = driver.o +scmi-protocols-y = base.o diff --git a/drivers/firmware/arm_scmi/base.c b/drivers/firmware/arm_scmi/base.c new file mode 100644 index 000000000000..0d3806c0d432 --- /dev/null +++ b/drivers/firmware/arm_scmi/base.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Base Protocol + * + * Copyright (C) 2018 ARM Ltd. + */ + +#include "common.h" + +enum scmi_base_protocol_cmd { + BASE_DISCOVER_VENDOR = 0x3, + BASE_DISCOVER_SUB_VENDOR = 0x4, + BASE_DISCOVER_IMPLEMENT_VERSION = 0x5, + BASE_DISCOVER_LIST_PROTOCOLS = 0x6, + BASE_DISCOVER_AGENT = 0x7, + BASE_NOTIFY_ERRORS = 0x8, +}; + +struct scmi_msg_resp_base_attributes { + u8 num_protocols; + u8 num_agents; + __le16 reserved; +}; + +/** + * scmi_base_attributes_get() - gets the implementation details + * that are associated with the base protocol. + * + * @handle - SCMI entity handle + * + * Return: 0 on success, else appropriate SCMI error. + */ +static int scmi_base_attributes_get(const struct scmi_handle *handle) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_base_attributes *attr_info; + struct scmi_revision_info *rev = handle->version; + + ret = scmi_one_xfer_init(handle, PROTOCOL_ATTRIBUTES, + SCMI_PROTOCOL_BASE, 0, sizeof(*attr_info), &t); + if (ret) + return ret; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + attr_info = t->rx.buf; + rev->num_protocols = attr_info->num_protocols; + rev->num_agents = attr_info->num_agents; + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +/** + * scmi_base_vendor_id_get() - gets vendor/subvendor identifier ASCII string. + * + * @handle - SCMI entity handle + * @sub_vendor - specify true if sub-vendor ID is needed + * + * Return: 0 on success, else appropriate SCMI error. + */ +static int +scmi_base_vendor_id_get(const struct scmi_handle *handle, bool sub_vendor) +{ + u8 cmd; + int ret, size; + char *vendor_id; + struct scmi_xfer *t; + struct scmi_revision_info *rev = handle->version; + + if (sub_vendor) { + cmd = BASE_DISCOVER_SUB_VENDOR; + vendor_id = rev->sub_vendor_id; + size = ARRAY_SIZE(rev->sub_vendor_id); + } else { + cmd = BASE_DISCOVER_VENDOR; + vendor_id = rev->vendor_id; + size = ARRAY_SIZE(rev->vendor_id); + } + + ret = scmi_one_xfer_init(handle, cmd, SCMI_PROTOCOL_BASE, 0, size, &t); + if (ret) + return ret; + + ret = scmi_do_xfer(handle, t); + if (!ret) + memcpy(vendor_id, t->rx.buf, size); + + scmi_one_xfer_put(handle, t); + return ret; +} + +/** + * scmi_base_implementation_version_get() - gets a vendor-specific + * implementation 32-bit version. The format of the version number is + * vendor-specific + * + * @handle - SCMI entity handle + * + * Return: 0 on success, else appropriate SCMI error. + */ +static int +scmi_base_implementation_version_get(const struct scmi_handle *handle) +{ + int ret; + __le32 *impl_ver; + struct scmi_xfer *t; + struct scmi_revision_info *rev = handle->version; + + ret = scmi_one_xfer_init(handle, BASE_DISCOVER_IMPLEMENT_VERSION, + SCMI_PROTOCOL_BASE, 0, sizeof(*impl_ver), &t); + if (ret) + return ret; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + impl_ver = t->rx.buf; + rev->impl_ver = le32_to_cpu(*impl_ver); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +/** + * scmi_base_implementation_list_get() - gets the list of protocols it is + * OSPM is allowed to access + * + * @handle - SCMI entity handle + * @protocols_imp - pointer to hold the list of protocol identifiers + * + * Return: 0 on success, else appropriate SCMI error. + */ +static int scmi_base_implementation_list_get(const struct scmi_handle *handle, + u8 *protocols_imp) +{ + u8 *list; + int ret, loop; + struct scmi_xfer *t; + __le32 *num_skip, *num_ret; + u32 tot_num_ret = 0, loop_num_ret; + struct device *dev = handle->dev; + + ret = scmi_one_xfer_init(handle, BASE_DISCOVER_LIST_PROTOCOLS, + SCMI_PROTOCOL_BASE, sizeof(*num_skip), 0, &t); + if (ret) + return ret; + + num_skip = t->tx.buf; + num_ret = t->rx.buf; + list = t->rx.buf + sizeof(*num_ret); + + do { + /* Set the number of protocols to be skipped/already read */ + *num_skip = cpu_to_le32(tot_num_ret); + + ret = scmi_do_xfer(handle, t); + if (ret) + break; + + loop_num_ret = le32_to_cpu(*num_ret); + if (tot_num_ret + loop_num_ret > MAX_PROTOCOLS_IMP) { + dev_err(dev, "No. of Protocol > MAX_PROTOCOLS_IMP"); + break; + } + + for (loop = 0; loop < loop_num_ret; loop++) + protocols_imp[tot_num_ret + loop] = *(list + loop); + + tot_num_ret += loop_num_ret; + } while (loop_num_ret); + + scmi_one_xfer_put(handle, t); + return ret; +} + +/** + * scmi_base_discover_agent_get() - discover the name of an agent + * + * @handle - SCMI entity handle + * @id - Agent identifier + * @name - Agent identifier ASCII string + * + * An agent id of 0 is reserved to identify the platform itself. + * Generally operating system is represented as "OSPM" + * + * Return: 0 on success, else appropriate SCMI error. + */ +static int scmi_base_discover_agent_get(const struct scmi_handle *handle, + int id, char *name) +{ + int ret; + struct scmi_xfer *t; + + ret = scmi_one_xfer_init(handle, BASE_DISCOVER_AGENT, + SCMI_PROTOCOL_BASE, sizeof(__le32), + SCMI_MAX_STR_SIZE, &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(id); + + ret = scmi_do_xfer(handle, t); + if (!ret) + memcpy(name, t->rx.buf, SCMI_MAX_STR_SIZE); + + scmi_one_xfer_put(handle, t); + return ret; +} + +int scmi_base_protocol_init(struct scmi_handle *h) +{ + int id, ret; + u8 *prot_imp; + u32 version; + char name[SCMI_MAX_STR_SIZE]; + const struct scmi_handle *handle = h; + struct device *dev = handle->dev; + struct scmi_revision_info *rev = handle->version; + + ret = scmi_version_get(handle, SCMI_PROTOCOL_BASE, &version); + if (ret) + return ret; + + prot_imp = devm_kcalloc(dev, MAX_PROTOCOLS_IMP, sizeof(u8), GFP_KERNEL); + if (!prot_imp) + return -ENOMEM; + + rev->major_ver = PROTOCOL_REV_MAJOR(version), + rev->minor_ver = PROTOCOL_REV_MINOR(version); + + scmi_base_attributes_get(handle); + scmi_base_vendor_id_get(handle, false); + scmi_base_vendor_id_get(handle, true); + scmi_base_implementation_version_get(handle); + scmi_base_implementation_list_get(handle, prot_imp); + scmi_setup_protocol_implemented(handle, prot_imp); + + dev_info(dev, "SCMI Protocol v%d.%d '%s:%s' Firmware version 0x%x\n", + rev->major_ver, rev->minor_ver, rev->vendor_id, + rev->sub_vendor_id, rev->impl_ver); + dev_dbg(dev, "Found %d protocol(s) %d agent(s)\n", rev->num_protocols, + rev->num_agents); + + for (id = 0; id < rev->num_agents; id++) { + scmi_base_discover_agent_get(handle, id, name); + dev_dbg(dev, "Agent %d: %s\n", id, name); + } + + return 0; +} diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index d57eb1862f68..0fc9f5ae8684 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -8,9 +8,41 @@ */ #include +#include +#include +#include #include #include +#define PROTOCOL_REV_MINOR_BITS 16 +#define PROTOCOL_REV_MINOR_MASK ((1U << PROTOCOL_REV_MINOR_BITS) - 1) +#define PROTOCOL_REV_MAJOR(x) ((x) >> PROTOCOL_REV_MINOR_BITS) +#define PROTOCOL_REV_MINOR(x) ((x) & PROTOCOL_REV_MINOR_MASK) +#define MAX_PROTOCOLS_IMP 16 + +enum scmi_common_cmd { + PROTOCOL_VERSION = 0x0, + PROTOCOL_ATTRIBUTES = 0x1, + PROTOCOL_MESSAGE_ATTRIBUTES = 0x2, +}; + +/** + * struct scmi_msg_resp_prot_version - Response for a message + * + * @major_version: Major version of the ABI that firmware supports + * @minor_version: Minor version of the ABI that firmware supports + * + * In general, ABI version changes follow the rule that minor version increments + * are backward compatible. Major revision changes in ABI may not be + * backward compatible. + * + * Response to a generic message with message type SCMI_MSG_VERSION + */ +struct scmi_msg_resp_prot_version { + __le16 minor_version; + __le16 major_version; +}; + /** * struct scmi_msg_hdr - Message(Tx/Rx) header * @@ -64,3 +96,8 @@ int scmi_one_xfer_init(const struct scmi_handle *h, u8 msg_id, u8 prot_id, size_t tx_size, size_t rx_size, struct scmi_xfer **p); int scmi_handle_put(const struct scmi_handle *handle); struct scmi_handle *scmi_handle_get(struct device *dev); +int scmi_version_get(const struct scmi_handle *h, u8 protocol, u32 *version); +void scmi_setup_protocol_implemented(const struct scmi_handle *handle, + u8 *prot_imp); + +int scmi_base_protocol_init(struct scmi_handle *h); diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 7824cce54373..49875cd68365 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -94,21 +94,27 @@ struct scmi_desc { * @dev: Device pointer * @desc: SoC description for this instance * @handle: Instance of SCMI handle to send to clients + * @version: SCMI revision information containing protocol version, + * implementation version and (sub-)vendor identification. * @cl: Mailbox Client * @tx_chan: Transmit mailbox channel * @tx_payload: Transmit mailbox channel payload area * @minfo: Message info + * @protocols_imp: list of protocols implemented, currently maximum of + * MAX_PROTOCOLS_IMP elements allocated by the base protocol * @node: list head * @users: Number of users of this instance */ struct scmi_info { struct device *dev; const struct scmi_desc *desc; + struct scmi_revision_info version; struct scmi_handle handle; struct mbox_client cl; struct mbox_chan *tx_chan; void __iomem *tx_payload; struct scmi_xfers_info minfo; + u8 *protocols_imp; struct list_head node; int users; }; @@ -421,6 +427,45 @@ int scmi_one_xfer_init(const struct scmi_handle *handle, u8 msg_id, u8 prot_id, return 0; } +/** + * scmi_version_get() - command to get the revision of the SCMI entity + * + * @handle: Handle to SCMI entity information + * + * Updates the SCMI information in the internal data structure. + * + * Return: 0 if all went fine, else return appropriate error. + */ +int scmi_version_get(const struct scmi_handle *handle, u8 protocol, + u32 *version) +{ + int ret; + __le32 *rev_info; + struct scmi_xfer *t; + + ret = scmi_one_xfer_init(handle, PROTOCOL_VERSION, protocol, 0, + sizeof(*version), &t); + if (ret) + return ret; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + rev_info = t->rx.buf; + *version = le32_to_cpu(*rev_info); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +void scmi_setup_protocol_implemented(const struct scmi_handle *handle, + u8 *prot_imp) +{ + struct scmi_info *info = handle_to_scmi_info(handle); + + info->protocols_imp = prot_imp; +} + /** * scmi_handle_get() - Get the SCMI handle for a device * @@ -649,11 +694,19 @@ static int scmi_probe(struct platform_device *pdev) handle = &info->handle; handle->dev = info->dev; + handle->version = &info->version; ret = scmi_mbox_chan_setup(info); if (ret) return ret; + ret = scmi_base_protocol_init(handle); + if (ret) { + dev_err(dev, "unable to communicate with SCMI(%d)\n", ret); + scmi_mbox_free_channel(info); + return ret; + } + mutex_lock(&scmi_list_mutex); list_add_tail(&info->node, &scmi_list); mutex_unlock(&scmi_list_mutex); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 1f0e89b270c6..08fcc1dd0276 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -6,11 +6,48 @@ */ #include +#define SCMI_MAX_STR_SIZE 16 + +/** + * struct scmi_revision_info - version information structure + * + * @major_ver: Major ABI version. Change here implies risk of backward + * compatibility break. + * @minor_ver: Minor ABI version. Change here implies new feature addition, + * or compatible change in ABI. + * @num_protocols: Number of protocols that are implemented, excluding the + * base protocol. + * @num_agents: Number of agents in the system. + * @impl_ver: A vendor-specific implementation version. + * @vendor_id: A vendor identifier(Null terminated ASCII string) + * @sub_vendor_id: A sub-vendor identifier(Null terminated ASCII string) + */ +struct scmi_revision_info { + u16 major_ver; + u16 minor_ver; + u8 num_protocols; + u8 num_agents; + u32 impl_ver; + char vendor_id[SCMI_MAX_STR_SIZE]; + char sub_vendor_id[SCMI_MAX_STR_SIZE]; +}; + /** * struct scmi_handle - Handle returned to ARM SCMI clients for usage. * * @dev: pointer to the SCMI device + * @version: pointer to the structure containing SCMI version information */ struct scmi_handle { struct device *dev; + struct scmi_revision_info *version; +}; + +enum scmi_std_protocol { + SCMI_PROTOCOL_BASE = 0x10, + SCMI_PROTOCOL_POWER = 0x11, + SCMI_PROTOCOL_SYSTEM = 0x12, + SCMI_PROTOCOL_PERF = 0x13, + SCMI_PROTOCOL_CLOCK = 0x14, + SCMI_PROTOCOL_SENSOR = 0x15, }; -- cgit v1.2.3 From 933c504424a2bc784fdb4cd5c318049d55da20e0 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Mon, 30 Oct 2017 18:33:30 +0000 Subject: firmware: arm_scmi: add scmi protocol bus to enumerate protocol devices The SCMI specification encompasses various protocols. However, not every protocol has to be present on a given platform/implementation as not every protocol is relevant for it. Furthermore, the platform chooses which protocols it exposes to a given agent. The only protocol that must be implemented is the base protocol. The base protocol is used by an agent to discover which protocols are available to it. In order to enumerate the discovered implemented protocols, this patch adds support for a separate scmi protocol bus. It also adds mechanism to register support for different protocols. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/Makefile | 3 +- drivers/firmware/arm_scmi/bus.c | 221 +++++++++++++++++++++++++++++++++++++ drivers/firmware/arm_scmi/common.h | 1 + include/linux/scmi_protocol.h | 64 +++++++++++ 4 files changed, 288 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/bus.c (limited to 'include/linux') diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index 5d9c7ef35f0f..5f4ec2613db6 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -1,3 +1,4 @@ -obj-y = scmi-driver.o scmi-protocols.o +obj-y = scmi-bus.o scmi-driver.o scmi-protocols.o +scmi-bus-y = bus.o scmi-driver-y = driver.o scmi-protocols-y = base.o diff --git a/drivers/firmware/arm_scmi/bus.c b/drivers/firmware/arm_scmi/bus.c new file mode 100644 index 000000000000..f2760a596c28 --- /dev/null +++ b/drivers/firmware/arm_scmi/bus.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Message Protocol bus layer + * + * Copyright (C) 2018 ARM Ltd. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include + +#include "common.h" + +static DEFINE_IDA(scmi_bus_id); +static DEFINE_IDR(scmi_protocols); +static DEFINE_SPINLOCK(protocol_lock); + +static const struct scmi_device_id * +scmi_dev_match_id(struct scmi_device *scmi_dev, struct scmi_driver *scmi_drv) +{ + const struct scmi_device_id *id = scmi_drv->id_table; + + if (!id) + return NULL; + + for (; id->protocol_id; id++) + if (id->protocol_id == scmi_dev->protocol_id) + return id; + + return NULL; +} + +static int scmi_dev_match(struct device *dev, struct device_driver *drv) +{ + struct scmi_driver *scmi_drv = to_scmi_driver(drv); + struct scmi_device *scmi_dev = to_scmi_dev(dev); + const struct scmi_device_id *id; + + id = scmi_dev_match_id(scmi_dev, scmi_drv); + if (id) + return 1; + + return 0; +} + +static int scmi_protocol_init(int protocol_id, struct scmi_handle *handle) +{ + scmi_prot_init_fn_t fn = idr_find(&scmi_protocols, protocol_id); + + if (unlikely(!fn)) + return -EINVAL; + return fn(handle); +} + +static int scmi_dev_probe(struct device *dev) +{ + struct scmi_driver *scmi_drv = to_scmi_driver(dev->driver); + struct scmi_device *scmi_dev = to_scmi_dev(dev); + const struct scmi_device_id *id; + int ret; + + id = scmi_dev_match_id(scmi_dev, scmi_drv); + if (!id) + return -ENODEV; + + if (!scmi_dev->handle) + return -EPROBE_DEFER; + + ret = scmi_protocol_init(scmi_dev->protocol_id, scmi_dev->handle); + if (ret) + return ret; + + return scmi_drv->probe(scmi_dev); +} + +static int scmi_dev_remove(struct device *dev) +{ + struct scmi_driver *scmi_drv = to_scmi_driver(dev->driver); + struct scmi_device *scmi_dev = to_scmi_dev(dev); + + if (scmi_drv->remove) + scmi_drv->remove(scmi_dev); + + return 0; +} + +static struct bus_type scmi_bus_type = { + .name = "scmi_protocol", + .match = scmi_dev_match, + .probe = scmi_dev_probe, + .remove = scmi_dev_remove, +}; + +int scmi_driver_register(struct scmi_driver *driver, struct module *owner, + const char *mod_name) +{ + int retval; + + driver->driver.bus = &scmi_bus_type; + driver->driver.name = driver->name; + driver->driver.owner = owner; + driver->driver.mod_name = mod_name; + + retval = driver_register(&driver->driver); + if (!retval) + pr_debug("registered new scmi driver %s\n", driver->name); + + return retval; +} +EXPORT_SYMBOL_GPL(scmi_driver_register); + +void scmi_driver_unregister(struct scmi_driver *driver) +{ + driver_unregister(&driver->driver); +} +EXPORT_SYMBOL_GPL(scmi_driver_unregister); + +struct scmi_device * +scmi_device_create(struct device_node *np, struct device *parent, int protocol) +{ + int id, retval; + struct scmi_device *scmi_dev; + + id = ida_simple_get(&scmi_bus_id, 1, 0, GFP_KERNEL); + if (id < 0) + return NULL; + + scmi_dev = kzalloc(sizeof(*scmi_dev), GFP_KERNEL); + if (!scmi_dev) + goto no_mem; + + scmi_dev->id = id; + scmi_dev->protocol_id = protocol; + scmi_dev->dev.parent = parent; + scmi_dev->dev.of_node = np; + scmi_dev->dev.bus = &scmi_bus_type; + dev_set_name(&scmi_dev->dev, "scmi_dev.%d", id); + + retval = device_register(&scmi_dev->dev); + if (!retval) + return scmi_dev; + + put_device(&scmi_dev->dev); + kfree(scmi_dev); +no_mem: + ida_simple_remove(&scmi_bus_id, id); + return NULL; +} + +void scmi_device_destroy(struct scmi_device *scmi_dev) +{ + scmi_handle_put(scmi_dev->handle); + device_unregister(&scmi_dev->dev); + ida_simple_remove(&scmi_bus_id, scmi_dev->id); + kfree(scmi_dev); +} + +void scmi_set_handle(struct scmi_device *scmi_dev) +{ + scmi_dev->handle = scmi_handle_get(&scmi_dev->dev); +} + +int scmi_protocol_register(int protocol_id, scmi_prot_init_fn_t fn) +{ + int ret; + + spin_lock(&protocol_lock); + ret = idr_alloc(&scmi_protocols, fn, protocol_id, protocol_id + 1, + GFP_ATOMIC); + if (ret != protocol_id) + pr_err("unable to allocate SCMI idr slot, err %d\n", ret); + spin_unlock(&protocol_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(scmi_protocol_register); + +void scmi_protocol_unregister(int protocol_id) +{ + spin_lock(&protocol_lock); + idr_remove(&scmi_protocols, protocol_id); + spin_unlock(&protocol_lock); +} +EXPORT_SYMBOL_GPL(scmi_protocol_unregister); + +static int __scmi_devices_unregister(struct device *dev, void *data) +{ + struct scmi_device *scmi_dev = to_scmi_dev(dev); + + scmi_device_destroy(scmi_dev); + return 0; +} + +static void scmi_devices_unregister(void) +{ + bus_for_each_dev(&scmi_bus_type, NULL, NULL, __scmi_devices_unregister); +} + +static int __init scmi_bus_init(void) +{ + int retval; + + retval = bus_register(&scmi_bus_type); + if (retval) + pr_err("scmi protocol bus register failed (%d)\n", retval); + + return retval; +} +subsys_initcall(scmi_bus_init); + +static void __exit scmi_bus_exit(void) +{ + scmi_devices_unregister(); + bus_unregister(&scmi_bus_type); + ida_destroy(&scmi_bus_id); +} +module_exit(scmi_bus_exit); diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index 0fc9f5ae8684..95053ed5ccb9 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -96,6 +96,7 @@ int scmi_one_xfer_init(const struct scmi_handle *h, u8 msg_id, u8 prot_id, size_t tx_size, size_t rx_size, struct scmi_xfer **p); int scmi_handle_put(const struct scmi_handle *handle); struct scmi_handle *scmi_handle_get(struct device *dev); +void scmi_set_handle(struct scmi_device *scmi_dev); int scmi_version_get(const struct scmi_handle *h, u8 protocol, u32 *version); void scmi_setup_protocol_implemented(const struct scmi_handle *handle, u8 *prot_imp); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 08fcc1dd0276..464086b9d8c5 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -4,6 +4,7 @@ * * Copyright (C) 2018 ARM Ltd. */ +#include #include #define SCMI_MAX_STR_SIZE 16 @@ -51,3 +52,66 @@ enum scmi_std_protocol { SCMI_PROTOCOL_CLOCK = 0x14, SCMI_PROTOCOL_SENSOR = 0x15, }; + +struct scmi_device { + u32 id; + u8 protocol_id; + struct device dev; + struct scmi_handle *handle; +}; + +#define to_scmi_dev(d) container_of(d, struct scmi_device, dev) + +struct scmi_device * +scmi_device_create(struct device_node *np, struct device *parent, int protocol); +void scmi_device_destroy(struct scmi_device *scmi_dev); + +struct scmi_device_id { + u8 protocol_id; +}; + +struct scmi_driver { + const char *name; + int (*probe)(struct scmi_device *sdev); + void (*remove)(struct scmi_device *sdev); + const struct scmi_device_id *id_table; + + struct device_driver driver; +}; + +#define to_scmi_driver(d) container_of(d, struct scmi_driver, driver) + +#ifdef CONFIG_ARM_SCMI_PROTOCOL +int scmi_driver_register(struct scmi_driver *driver, + struct module *owner, const char *mod_name); +void scmi_driver_unregister(struct scmi_driver *driver); +#else +static inline int +scmi_driver_register(struct scmi_driver *driver, struct module *owner, + const char *mod_name) +{ + return -EINVAL; +} + +static inline void scmi_driver_unregister(struct scmi_driver *driver) {} +#endif /* CONFIG_ARM_SCMI_PROTOCOL */ + +#define scmi_register(driver) \ + scmi_driver_register(driver, THIS_MODULE, KBUILD_MODNAME) +#define scmi_unregister(driver) \ + scmi_driver_unregister(driver) + +/** + * module_scmi_driver() - Helper macro for registering a scmi driver + * @__scmi_driver: scmi_driver structure + * + * Helper macro for scmi drivers to set up proper module init / exit + * functions. Replaces module_init() and module_exit() and keeps people from + * printing pointless things to the kernel log when their driver is loaded. + */ +#define module_scmi_driver(__scmi_driver) \ + module_driver(__scmi_driver, scmi_register, scmi_unregister) + +typedef int (*scmi_prot_init_fn_t)(struct scmi_handle *); +int scmi_protocol_register(int protocol_id, scmi_prot_init_fn_t fn); +void scmi_protocol_unregister(int protocol_id); -- cgit v1.2.3 From a9e3fbfaa0ff885aacafe6f33e72448a2993d072 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 6 Jun 2017 11:22:51 +0100 Subject: firmware: arm_scmi: add initial support for performance protocol The performance protocol is intended for the performance management of group(s) of device(s) that run in the same performance domain. It includes even the CPUs. A performance domain is defined by a set of devices that always have to run at the same performance level. For example, a set of CPUs that share a voltage domain, and have a common frequency control, is said to be in the same performance domain. The commands in this protocol provide functionality to describe the protocol version, describe various attribute flags, set and get the performance level of a domain. It also supports discovery of the list of performance levels supported by a performance domain, and the properties of each performance level. This patch adds basic support for the performance protocol. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/Makefile | 2 +- drivers/firmware/arm_scmi/common.h | 1 + drivers/firmware/arm_scmi/perf.c | 478 +++++++++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 42 ++++ 4 files changed, 522 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/perf.c (limited to 'include/linux') diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index 5f4ec2613db6..687cbbfb3af6 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -1,4 +1,4 @@ obj-y = scmi-bus.o scmi-driver.o scmi-protocols.o scmi-bus-y = bus.o scmi-driver-y = driver.o -scmi-protocols-y = base.o +scmi-protocols-y = base.o perf.o diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index 95053ed5ccb9..0c30234f9098 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -19,6 +19,7 @@ #define PROTOCOL_REV_MAJOR(x) ((x) >> PROTOCOL_REV_MINOR_BITS) #define PROTOCOL_REV_MINOR(x) ((x) & PROTOCOL_REV_MINOR_MASK) #define MAX_PROTOCOLS_IMP 16 +#define MAX_OPPS 16 enum scmi_common_cmd { PROTOCOL_VERSION = 0x0, diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c new file mode 100644 index 000000000000..9c56ea503890 --- /dev/null +++ b/drivers/firmware/arm_scmi/perf.c @@ -0,0 +1,478 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Performance Protocol + * + * Copyright (C) 2018 ARM Ltd. + */ + +#include +#include +#include +#include + +#include "common.h" + +enum scmi_performance_protocol_cmd { + PERF_DOMAIN_ATTRIBUTES = 0x3, + PERF_DESCRIBE_LEVELS = 0x4, + PERF_LIMITS_SET = 0x5, + PERF_LIMITS_GET = 0x6, + PERF_LEVEL_SET = 0x7, + PERF_LEVEL_GET = 0x8, + PERF_NOTIFY_LIMITS = 0x9, + PERF_NOTIFY_LEVEL = 0xa, +}; + +struct scmi_opp { + u32 perf; + u32 power; + u32 trans_latency_us; +}; + +struct scmi_msg_resp_perf_attributes { + __le16 num_domains; + __le16 flags; +#define POWER_SCALE_IN_MILLIWATT(x) ((x) & BIT(0)) + __le32 stats_addr_low; + __le32 stats_addr_high; + __le32 stats_size; +}; + +struct scmi_msg_resp_perf_domain_attributes { + __le32 flags; +#define SUPPORTS_SET_LIMITS(x) ((x) & BIT(31)) +#define SUPPORTS_SET_PERF_LVL(x) ((x) & BIT(30)) +#define SUPPORTS_PERF_LIMIT_NOTIFY(x) ((x) & BIT(29)) +#define SUPPORTS_PERF_LEVEL_NOTIFY(x) ((x) & BIT(28)) + __le32 rate_limit_us; + __le32 sustained_freq_khz; + __le32 sustained_perf_level; + u8 name[SCMI_MAX_STR_SIZE]; +}; + +struct scmi_msg_perf_describe_levels { + __le32 domain; + __le32 level_index; +}; + +struct scmi_perf_set_limits { + __le32 domain; + __le32 max_level; + __le32 min_level; +}; + +struct scmi_perf_get_limits { + __le32 max_level; + __le32 min_level; +}; + +struct scmi_perf_set_level { + __le32 domain; + __le32 level; +}; + +struct scmi_perf_notify_level_or_limits { + __le32 domain; + __le32 notify_enable; +}; + +struct scmi_msg_resp_perf_describe_levels { + __le16 num_returned; + __le16 num_remaining; + struct { + __le32 perf_val; + __le32 power; + __le16 transition_latency_us; + __le16 reserved; + } opp[0]; +}; + +struct perf_dom_info { + bool set_limits; + bool set_perf; + bool perf_limit_notify; + bool perf_level_notify; + u32 opp_count; + u32 sustained_freq_khz; + u32 sustained_perf_level; + u32 mult_factor; + char name[SCMI_MAX_STR_SIZE]; + struct scmi_opp opp[MAX_OPPS]; +}; + +struct scmi_perf_info { + int num_domains; + bool power_scale_mw; + u64 stats_addr; + u32 stats_size; + struct perf_dom_info *dom_info; +}; + +static int scmi_perf_attributes_get(const struct scmi_handle *handle, + struct scmi_perf_info *pi) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_perf_attributes *attr; + + ret = scmi_one_xfer_init(handle, PROTOCOL_ATTRIBUTES, + SCMI_PROTOCOL_PERF, 0, sizeof(*attr), &t); + if (ret) + return ret; + + attr = t->rx.buf; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + u16 flags = le16_to_cpu(attr->flags); + + pi->num_domains = le16_to_cpu(attr->num_domains); + pi->power_scale_mw = POWER_SCALE_IN_MILLIWATT(flags); + pi->stats_addr = le32_to_cpu(attr->stats_addr_low) | + (u64)le32_to_cpu(attr->stats_addr_high) << 32; + pi->stats_size = le32_to_cpu(attr->stats_size); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_perf_domain_attributes_get(const struct scmi_handle *handle, u32 domain, + struct perf_dom_info *dom_info) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_perf_domain_attributes *attr; + + ret = scmi_one_xfer_init(handle, PERF_DOMAIN_ATTRIBUTES, + SCMI_PROTOCOL_PERF, sizeof(domain), + sizeof(*attr), &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(domain); + attr = t->rx.buf; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + u32 flags = le32_to_cpu(attr->flags); + + dom_info->set_limits = SUPPORTS_SET_LIMITS(flags); + dom_info->set_perf = SUPPORTS_SET_PERF_LVL(flags); + dom_info->perf_limit_notify = SUPPORTS_PERF_LIMIT_NOTIFY(flags); + dom_info->perf_level_notify = SUPPORTS_PERF_LEVEL_NOTIFY(flags); + dom_info->sustained_freq_khz = + le32_to_cpu(attr->sustained_freq_khz); + dom_info->sustained_perf_level = + le32_to_cpu(attr->sustained_perf_level); + dom_info->mult_factor = (dom_info->sustained_freq_khz * 1000) / + dom_info->sustained_perf_level; + memcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int opp_cmp_func(const void *opp1, const void *opp2) +{ + const struct scmi_opp *t1 = opp1, *t2 = opp2; + + return t1->perf - t2->perf; +} + +static int +scmi_perf_describe_levels_get(const struct scmi_handle *handle, u32 domain, + struct perf_dom_info *perf_dom) +{ + int ret, cnt; + u32 tot_opp_cnt = 0; + u16 num_returned, num_remaining; + struct scmi_xfer *t; + struct scmi_opp *opp; + struct scmi_msg_perf_describe_levels *dom_info; + struct scmi_msg_resp_perf_describe_levels *level_info; + + ret = scmi_one_xfer_init(handle, PERF_DESCRIBE_LEVELS, + SCMI_PROTOCOL_PERF, sizeof(*dom_info), 0, &t); + if (ret) + return ret; + + dom_info = t->tx.buf; + level_info = t->rx.buf; + + do { + dom_info->domain = cpu_to_le32(domain); + /* Set the number of OPPs to be skipped/already read */ + dom_info->level_index = cpu_to_le32(tot_opp_cnt); + + ret = scmi_do_xfer(handle, t); + if (ret) + break; + + num_returned = le16_to_cpu(level_info->num_returned); + num_remaining = le16_to_cpu(level_info->num_remaining); + if (tot_opp_cnt + num_returned > MAX_OPPS) { + dev_err(handle->dev, "No. of OPPs exceeded MAX_OPPS"); + break; + } + + opp = &perf_dom->opp[tot_opp_cnt]; + for (cnt = 0; cnt < num_returned; cnt++, opp++) { + opp->perf = le32_to_cpu(level_info->opp[cnt].perf_val); + opp->power = le32_to_cpu(level_info->opp[cnt].power); + opp->trans_latency_us = le16_to_cpu + (level_info->opp[cnt].transition_latency_us); + + dev_dbg(handle->dev, "Level %d Power %d Latency %dus\n", + opp->perf, opp->power, opp->trans_latency_us); + } + + tot_opp_cnt += num_returned; + /* + * check for both returned and remaining to avoid infinite + * loop due to buggy firmware + */ + } while (num_returned && num_remaining); + + perf_dom->opp_count = tot_opp_cnt; + scmi_one_xfer_put(handle, t); + + sort(perf_dom->opp, tot_opp_cnt, sizeof(*opp), opp_cmp_func, NULL); + return ret; +} + +static int scmi_perf_limits_set(const struct scmi_handle *handle, u32 domain, + u32 max_perf, u32 min_perf) +{ + int ret; + struct scmi_xfer *t; + struct scmi_perf_set_limits *limits; + + ret = scmi_one_xfer_init(handle, PERF_LIMITS_SET, SCMI_PROTOCOL_PERF, + sizeof(*limits), 0, &t); + if (ret) + return ret; + + limits = t->tx.buf; + limits->domain = cpu_to_le32(domain); + limits->max_level = cpu_to_le32(max_perf); + limits->min_level = cpu_to_le32(min_perf); + + ret = scmi_do_xfer(handle, t); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_perf_limits_get(const struct scmi_handle *handle, u32 domain, + u32 *max_perf, u32 *min_perf) +{ + int ret; + struct scmi_xfer *t; + struct scmi_perf_get_limits *limits; + + ret = scmi_one_xfer_init(handle, PERF_LIMITS_GET, SCMI_PROTOCOL_PERF, + sizeof(__le32), 0, &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(domain); + + ret = scmi_do_xfer(handle, t); + if (!ret) { + limits = t->rx.buf; + + *max_perf = le32_to_cpu(limits->max_level); + *min_perf = le32_to_cpu(limits->min_level); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_perf_level_set(const struct scmi_handle *handle, u32 domain, u32 level) +{ + int ret; + struct scmi_xfer *t; + struct scmi_perf_set_level *lvl; + + ret = scmi_one_xfer_init(handle, PERF_LEVEL_SET, SCMI_PROTOCOL_PERF, + sizeof(*lvl), 0, &t); + if (ret) + return ret; + + lvl = t->tx.buf; + lvl->domain = cpu_to_le32(domain); + lvl->level = cpu_to_le32(level); + + ret = scmi_do_xfer(handle, t); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_perf_level_get(const struct scmi_handle *handle, u32 domain, u32 *level) +{ + int ret; + struct scmi_xfer *t; + + ret = scmi_one_xfer_init(handle, PERF_LEVEL_GET, SCMI_PROTOCOL_PERF, + sizeof(u32), sizeof(u32), &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(domain); + + ret = scmi_do_xfer(handle, t); + if (!ret) + *level = le32_to_cpu(*(__le32 *)t->rx.buf); + + scmi_one_xfer_put(handle, t); + return ret; +} + +/* Device specific ops */ +static int scmi_dev_domain_id(struct device *dev) +{ + struct of_phandle_args clkspec; + + if (of_parse_phandle_with_args(dev->of_node, "clocks", "#clock-cells", + 0, &clkspec)) + return -EINVAL; + + return clkspec.args[0]; +} + +static int scmi_dvfs_add_opps_to_device(const struct scmi_handle *handle, + struct device *dev) +{ + int idx, ret, domain; + unsigned long freq; + struct scmi_opp *opp; + struct perf_dom_info *dom; + struct scmi_perf_info *pi = handle->perf_priv; + + domain = scmi_dev_domain_id(dev); + if (domain < 0) + return domain; + + dom = pi->dom_info + domain; + if (!dom) + return -EIO; + + for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { + freq = opp->perf * dom->mult_factor; + + ret = dev_pm_opp_add(dev, freq, 0); + if (ret) { + dev_warn(dev, "failed to add opp %luHz\n", freq); + + while (idx-- > 0) { + freq = (--opp)->perf * dom->mult_factor; + dev_pm_opp_remove(dev, freq); + } + return ret; + } + } + return 0; +} + +static int scmi_dvfs_get_transition_latency(const struct scmi_handle *handle, + struct device *dev) +{ + struct perf_dom_info *dom; + struct scmi_perf_info *pi = handle->perf_priv; + int domain = scmi_dev_domain_id(dev); + + if (domain < 0) + return domain; + + dom = pi->dom_info + domain; + if (!dom) + return -EIO; + + /* uS to nS */ + return dom->opp[dom->opp_count - 1].trans_latency_us * 1000; +} + +static int scmi_dvfs_freq_set(const struct scmi_handle *handle, u32 domain, + unsigned long freq) +{ + struct scmi_perf_info *pi = handle->perf_priv; + struct perf_dom_info *dom = pi->dom_info + domain; + + return scmi_perf_level_set(handle, domain, freq / dom->mult_factor); +} + +static int scmi_dvfs_freq_get(const struct scmi_handle *handle, u32 domain, + unsigned long *freq) +{ + int ret; + u32 level; + struct scmi_perf_info *pi = handle->perf_priv; + struct perf_dom_info *dom = pi->dom_info + domain; + + ret = scmi_perf_level_get(handle, domain, &level); + if (!ret) + *freq = level * dom->mult_factor; + + return ret; +} + +static struct scmi_perf_ops perf_ops = { + .limits_set = scmi_perf_limits_set, + .limits_get = scmi_perf_limits_get, + .level_set = scmi_perf_level_set, + .level_get = scmi_perf_level_get, + .device_domain_id = scmi_dev_domain_id, + .get_transition_latency = scmi_dvfs_get_transition_latency, + .add_opps_to_device = scmi_dvfs_add_opps_to_device, + .freq_set = scmi_dvfs_freq_set, + .freq_get = scmi_dvfs_freq_get, +}; + +static int scmi_perf_protocol_init(struct scmi_handle *handle) +{ + int domain; + u32 version; + struct scmi_perf_info *pinfo; + + scmi_version_get(handle, SCMI_PROTOCOL_PERF, &version); + + dev_dbg(handle->dev, "Performance Version %d.%d\n", + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); + + pinfo = devm_kzalloc(handle->dev, sizeof(*pinfo), GFP_KERNEL); + if (!pinfo) + return -ENOMEM; + + scmi_perf_attributes_get(handle, pinfo); + + pinfo->dom_info = devm_kcalloc(handle->dev, pinfo->num_domains, + sizeof(*pinfo->dom_info), GFP_KERNEL); + if (!pinfo->dom_info) + return -ENOMEM; + + for (domain = 0; domain < pinfo->num_domains; domain++) { + struct perf_dom_info *dom = pinfo->dom_info + domain; + + scmi_perf_domain_attributes_get(handle, domain, dom); + scmi_perf_describe_levels_get(handle, domain, dom); + } + + handle->perf_ops = &perf_ops; + handle->perf_priv = pinfo; + + return 0; +} + +static int __init scmi_perf_init(void) +{ + return scmi_protocol_register(SCMI_PROTOCOL_PERF, + &scmi_perf_protocol_init); +} +subsys_initcall(scmi_perf_init); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 464086b9d8c5..57d4b1c099e5 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -33,15 +33,57 @@ struct scmi_revision_info { char sub_vendor_id[SCMI_MAX_STR_SIZE]; }; +struct scmi_handle; + +/** + * struct scmi_perf_ops - represents the various operations provided + * by SCMI Performance Protocol + * + * @limits_set: sets limits on the performance level of a domain + * @limits_get: gets limits on the performance level of a domain + * @level_set: sets the performance level of a domain + * @level_get: gets the performance level of a domain + * @device_domain_id: gets the scmi domain id for a given device + * @get_transition_latency: gets the DVFS transition latency for a given device + * @add_opps_to_device: adds all the OPPs for a given device + * @freq_set: sets the frequency for a given device using sustained frequency + * to sustained performance level mapping + * @freq_get: gets the frequency for a given device using sustained frequency + * to sustained performance level mapping + */ +struct scmi_perf_ops { + int (*limits_set)(const struct scmi_handle *handle, u32 domain, + u32 max_perf, u32 min_perf); + int (*limits_get)(const struct scmi_handle *handle, u32 domain, + u32 *max_perf, u32 *min_perf); + int (*level_set)(const struct scmi_handle *handle, u32 domain, + u32 level); + int (*level_get)(const struct scmi_handle *handle, u32 domain, + u32 *level); + int (*device_domain_id)(struct device *dev); + int (*get_transition_latency)(const struct scmi_handle *handle, + struct device *dev); + int (*add_opps_to_device)(const struct scmi_handle *handle, + struct device *dev); + int (*freq_set)(const struct scmi_handle *handle, u32 domain, + unsigned long rate); + int (*freq_get)(const struct scmi_handle *handle, u32 domain, + unsigned long *rate); +}; + /** * struct scmi_handle - Handle returned to ARM SCMI clients for usage. * * @dev: pointer to the SCMI device * @version: pointer to the structure containing SCMI version information + * @perf_ops: pointer to set of performance protocol operations */ struct scmi_handle { struct device *dev; struct scmi_revision_info *version; + struct scmi_perf_ops *perf_ops; + /* for protocol internal use */ + void *perf_priv; }; enum scmi_std_protocol { -- cgit v1.2.3 From 5f6c6430e904d21bfe5d0076b1ff3e8b9ed94ba0 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 6 Jun 2017 11:27:57 +0100 Subject: firmware: arm_scmi: add initial support for clock protocol The clock protocol is intended for management of clocks. It is used to enable or disable clocks, and to set and get the clock rates. This protocol provides commands to describe the protocol version, discover various implementation specific attributes, describe a clock, enable and disable a clock and get/set the rate of the clock synchronously or asynchronously. This patch adds initial support for the clock protocol. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/Makefile | 2 +- drivers/firmware/arm_scmi/clock.c | 342 +++++++++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 44 +++++ 3 files changed, 387 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/clock.c (limited to 'include/linux') diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index 687cbbfb3af6..2130ee9ac825 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -1,4 +1,4 @@ obj-y = scmi-bus.o scmi-driver.o scmi-protocols.o scmi-bus-y = bus.o scmi-driver-y = driver.o -scmi-protocols-y = base.o perf.o +scmi-protocols-y = base.o clock.o perf.o diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c new file mode 100644 index 000000000000..e8ffad33a0ff --- /dev/null +++ b/drivers/firmware/arm_scmi/clock.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Clock Protocol + * + * Copyright (C) 2018 ARM Ltd. + */ + +#include "common.h" + +enum scmi_clock_protocol_cmd { + CLOCK_ATTRIBUTES = 0x3, + CLOCK_DESCRIBE_RATES = 0x4, + CLOCK_RATE_SET = 0x5, + CLOCK_RATE_GET = 0x6, + CLOCK_CONFIG_SET = 0x7, +}; + +struct scmi_msg_resp_clock_protocol_attributes { + __le16 num_clocks; + u8 max_async_req; + u8 reserved; +}; + +struct scmi_msg_resp_clock_attributes { + __le32 attributes; +#define CLOCK_ENABLE BIT(0) + u8 name[SCMI_MAX_STR_SIZE]; +}; + +struct scmi_clock_set_config { + __le32 id; + __le32 attributes; +}; + +struct scmi_msg_clock_describe_rates { + __le32 id; + __le32 rate_index; +}; + +struct scmi_msg_resp_clock_describe_rates { + __le32 num_rates_flags; +#define NUM_RETURNED(x) ((x) & 0xfff) +#define RATE_DISCRETE(x) !((x) & BIT(12)) +#define NUM_REMAINING(x) ((x) >> 16) + struct { + __le32 value_low; + __le32 value_high; + } rate[0]; +#define RATE_TO_U64(X) \ +({ \ + typeof(X) x = (X); \ + le32_to_cpu((x).value_low) | (u64)le32_to_cpu((x).value_high) << 32; \ +}) +}; + +struct scmi_clock_set_rate { + __le32 flags; +#define CLOCK_SET_ASYNC BIT(0) +#define CLOCK_SET_DELAYED BIT(1) +#define CLOCK_SET_ROUND_UP BIT(2) +#define CLOCK_SET_ROUND_AUTO BIT(3) + __le32 id; + __le32 value_low; + __le32 value_high; +}; + +struct clock_info { + int num_clocks; + int max_async_req; + struct scmi_clock_info *clk; +}; + +static int scmi_clock_protocol_attributes_get(const struct scmi_handle *handle, + struct clock_info *ci) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_clock_protocol_attributes *attr; + + ret = scmi_one_xfer_init(handle, PROTOCOL_ATTRIBUTES, + SCMI_PROTOCOL_CLOCK, 0, sizeof(*attr), &t); + if (ret) + return ret; + + attr = t->rx.buf; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + ci->num_clocks = le16_to_cpu(attr->num_clocks); + ci->max_async_req = attr->max_async_req; + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_clock_attributes_get(const struct scmi_handle *handle, + u32 clk_id, struct scmi_clock_info *clk) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_clock_attributes *attr; + + ret = scmi_one_xfer_init(handle, CLOCK_ATTRIBUTES, SCMI_PROTOCOL_CLOCK, + sizeof(clk_id), sizeof(*attr), &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(clk_id); + attr = t->rx.buf; + + ret = scmi_do_xfer(handle, t); + if (!ret) + memcpy(clk->name, attr->name, SCMI_MAX_STR_SIZE); + else + clk->name[0] = '\0'; + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_clock_describe_rates_get(const struct scmi_handle *handle, u32 clk_id, + struct scmi_clock_info *clk) +{ + u64 *rate; + int ret, cnt; + bool rate_discrete; + u32 tot_rate_cnt = 0, rates_flag; + u16 num_returned, num_remaining; + struct scmi_xfer *t; + struct scmi_msg_clock_describe_rates *clk_desc; + struct scmi_msg_resp_clock_describe_rates *rlist; + + ret = scmi_one_xfer_init(handle, CLOCK_DESCRIBE_RATES, + SCMI_PROTOCOL_CLOCK, sizeof(*clk_desc), 0, &t); + if (ret) + return ret; + + clk_desc = t->tx.buf; + rlist = t->rx.buf; + + do { + clk_desc->id = cpu_to_le32(clk_id); + /* Set the number of rates to be skipped/already read */ + clk_desc->rate_index = cpu_to_le32(tot_rate_cnt); + + ret = scmi_do_xfer(handle, t); + if (ret) + break; + + rates_flag = le32_to_cpu(rlist->num_rates_flags); + num_remaining = NUM_REMAINING(rates_flag); + rate_discrete = RATE_DISCRETE(rates_flag); + num_returned = NUM_RETURNED(rates_flag); + + if (tot_rate_cnt + num_returned > SCMI_MAX_NUM_RATES) { + dev_err(handle->dev, "No. of rates > MAX_NUM_RATES"); + break; + } + + if (!rate_discrete) { + clk->range.min_rate = RATE_TO_U64(rlist->rate[0]); + clk->range.max_rate = RATE_TO_U64(rlist->rate[1]); + clk->range.step_size = RATE_TO_U64(rlist->rate[2]); + dev_dbg(handle->dev, "Min %llu Max %llu Step %llu Hz\n", + clk->range.min_rate, clk->range.max_rate, + clk->range.step_size); + break; + } + + rate = &clk->list.rates[tot_rate_cnt]; + for (cnt = 0; cnt < num_returned; cnt++, rate++) { + *rate = RATE_TO_U64(rlist->rate[cnt]); + dev_dbg(handle->dev, "Rate %llu Hz\n", *rate); + } + + tot_rate_cnt += num_returned; + /* + * check for both returned and remaining to avoid infinite + * loop due to buggy firmware + */ + } while (num_returned && num_remaining); + + if (rate_discrete) + clk->list.num_rates = tot_rate_cnt; + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_clock_rate_get(const struct scmi_handle *handle, u32 clk_id, u64 *value) +{ + int ret; + struct scmi_xfer *t; + + ret = scmi_one_xfer_init(handle, CLOCK_RATE_GET, SCMI_PROTOCOL_CLOCK, + sizeof(__le32), sizeof(u64), &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(clk_id); + + ret = scmi_do_xfer(handle, t); + if (!ret) { + __le32 *pval = t->rx.buf; + + *value = le32_to_cpu(*pval); + *value |= (u64)le32_to_cpu(*(pval + 1)) << 32; + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_clock_rate_set(const struct scmi_handle *handle, u32 clk_id, + u32 config, u64 rate) +{ + int ret; + struct scmi_xfer *t; + struct scmi_clock_set_rate *cfg; + + ret = scmi_one_xfer_init(handle, CLOCK_RATE_SET, SCMI_PROTOCOL_CLOCK, + sizeof(*cfg), 0, &t); + if (ret) + return ret; + + cfg = t->tx.buf; + cfg->flags = cpu_to_le32(config); + cfg->id = cpu_to_le32(clk_id); + cfg->value_low = cpu_to_le32(rate & 0xffffffff); + cfg->value_high = cpu_to_le32(rate >> 32); + + ret = scmi_do_xfer(handle, t); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_clock_config_set(const struct scmi_handle *handle, u32 clk_id, u32 config) +{ + int ret; + struct scmi_xfer *t; + struct scmi_clock_set_config *cfg; + + ret = scmi_one_xfer_init(handle, CLOCK_CONFIG_SET, SCMI_PROTOCOL_CLOCK, + sizeof(*cfg), 0, &t); + if (ret) + return ret; + + cfg = t->tx.buf; + cfg->id = cpu_to_le32(clk_id); + cfg->attributes = cpu_to_le32(config); + + ret = scmi_do_xfer(handle, t); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_clock_enable(const struct scmi_handle *handle, u32 clk_id) +{ + return scmi_clock_config_set(handle, clk_id, CLOCK_ENABLE); +} + +static int scmi_clock_disable(const struct scmi_handle *handle, u32 clk_id) +{ + return scmi_clock_config_set(handle, clk_id, 0); +} + +static int scmi_clock_count_get(const struct scmi_handle *handle) +{ + struct clock_info *ci = handle->clk_priv; + + return ci->num_clocks; +} + +static const struct scmi_clock_info * +scmi_clock_info_get(const struct scmi_handle *handle, u32 clk_id) +{ + struct clock_info *ci = handle->clk_priv; + struct scmi_clock_info *clk = ci->clk + clk_id; + + if (!clk->name || !clk->name[0]) + return NULL; + + return clk; +} + +static struct scmi_clk_ops clk_ops = { + .count_get = scmi_clock_count_get, + .info_get = scmi_clock_info_get, + .rate_get = scmi_clock_rate_get, + .rate_set = scmi_clock_rate_set, + .enable = scmi_clock_enable, + .disable = scmi_clock_disable, +}; + +static int scmi_clock_protocol_init(struct scmi_handle *handle) +{ + u32 version; + int clkid, ret; + struct clock_info *cinfo; + + scmi_version_get(handle, SCMI_PROTOCOL_CLOCK, &version); + + dev_dbg(handle->dev, "Clock Version %d.%d\n", + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); + + cinfo = devm_kzalloc(handle->dev, sizeof(*cinfo), GFP_KERNEL); + if (!cinfo) + return -ENOMEM; + + scmi_clock_protocol_attributes_get(handle, cinfo); + + cinfo->clk = devm_kcalloc(handle->dev, cinfo->num_clocks, + sizeof(*cinfo->clk), GFP_KERNEL); + if (!cinfo->clk) + return -ENOMEM; + + for (clkid = 0; clkid < cinfo->num_clocks; clkid++) { + struct scmi_clock_info *clk = cinfo->clk + clkid; + + ret = scmi_clock_attributes_get(handle, clkid, clk); + if (!ret) + scmi_clock_describe_rates_get(handle, clkid, clk); + } + + handle->clk_ops = &clk_ops; + handle->clk_priv = cinfo; + + return 0; +} + +static int __init scmi_clock_init(void) +{ + return scmi_protocol_register(SCMI_PROTOCOL_CLOCK, + &scmi_clock_protocol_init); +} +subsys_initcall(scmi_clock_init); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 57d4b1c099e5..5a3092f05011 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -8,6 +8,7 @@ #include #define SCMI_MAX_STR_SIZE 16 +#define SCMI_MAX_NUM_RATES 16 /** * struct scmi_revision_info - version information structure @@ -33,8 +34,48 @@ struct scmi_revision_info { char sub_vendor_id[SCMI_MAX_STR_SIZE]; }; +struct scmi_clock_info { + char name[SCMI_MAX_STR_SIZE]; + bool rate_discrete; + union { + struct { + int num_rates; + u64 rates[SCMI_MAX_NUM_RATES]; + } list; + struct { + u64 min_rate; + u64 max_rate; + u64 step_size; + } range; + }; +}; + struct scmi_handle; +/** + * struct scmi_clk_ops - represents the various operations provided + * by SCMI Clock Protocol + * + * @count_get: get the count of clocks provided by SCMI + * @info_get: get the information of the specified clock + * @rate_get: request the current clock rate of a clock + * @rate_set: set the clock rate of a clock + * @enable: enables the specified clock + * @disable: disables the specified clock + */ +struct scmi_clk_ops { + int (*count_get)(const struct scmi_handle *handle); + + const struct scmi_clock_info *(*info_get) + (const struct scmi_handle *handle, u32 clk_id); + int (*rate_get)(const struct scmi_handle *handle, u32 clk_id, + u64 *rate); + int (*rate_set)(const struct scmi_handle *handle, u32 clk_id, + u32 config, u64 rate); + int (*enable)(const struct scmi_handle *handle, u32 clk_id); + int (*disable)(const struct scmi_handle *handle, u32 clk_id); +}; + /** * struct scmi_perf_ops - represents the various operations provided * by SCMI Performance Protocol @@ -77,13 +118,16 @@ struct scmi_perf_ops { * @dev: pointer to the SCMI device * @version: pointer to the structure containing SCMI version information * @perf_ops: pointer to set of performance protocol operations + * @clk_ops: pointer to set of clock protocol operations */ struct scmi_handle { struct device *dev; struct scmi_revision_info *version; struct scmi_perf_ops *perf_ops; + struct scmi_clk_ops *clk_ops; /* for protocol internal use */ void *perf_priv; + void *clk_priv; }; enum scmi_std_protocol { -- cgit v1.2.3 From 76a6550990e296a7acbb4d33201c9740be912a8c Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 6 Jun 2017 11:32:24 +0100 Subject: firmware: arm_scmi: add initial support for power protocol The power protocol is intended for management of power states of various power domains. The power domain management protocol provides commands to describe the protocol version, discover the implementation specific attributes, set and get the power state of a domain. This patch adds support for the above mention features of the protocol. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla -- drivers/firmware/arm_scmi/Makefile | 2 +- drivers/firmware/arm_scmi/power.c | 242 +++++++++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 28 +++++ 3 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/power.c --- drivers/firmware/arm_scmi/Makefile | 2 +- drivers/firmware/arm_scmi/power.c | 221 +++++++++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 28 +++++ 3 files changed, 250 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/power.c (limited to 'include/linux') diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index 2130ee9ac825..420c761ced94 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -1,4 +1,4 @@ obj-y = scmi-bus.o scmi-driver.o scmi-protocols.o scmi-bus-y = bus.o scmi-driver-y = driver.o -scmi-protocols-y = base.o clock.o perf.o +scmi-protocols-y = base.o clock.o perf.o power.o diff --git a/drivers/firmware/arm_scmi/power.c b/drivers/firmware/arm_scmi/power.c new file mode 100644 index 000000000000..087c2876cdf2 --- /dev/null +++ b/drivers/firmware/arm_scmi/power.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Power Protocol + * + * Copyright (C) 2018 ARM Ltd. + */ + +#include "common.h" + +enum scmi_power_protocol_cmd { + POWER_DOMAIN_ATTRIBUTES = 0x3, + POWER_STATE_SET = 0x4, + POWER_STATE_GET = 0x5, + POWER_STATE_NOTIFY = 0x6, +}; + +struct scmi_msg_resp_power_attributes { + __le16 num_domains; + __le16 reserved; + __le32 stats_addr_low; + __le32 stats_addr_high; + __le32 stats_size; +}; + +struct scmi_msg_resp_power_domain_attributes { + __le32 flags; +#define SUPPORTS_STATE_SET_NOTIFY(x) ((x) & BIT(31)) +#define SUPPORTS_STATE_SET_ASYNC(x) ((x) & BIT(30)) +#define SUPPORTS_STATE_SET_SYNC(x) ((x) & BIT(29)) + u8 name[SCMI_MAX_STR_SIZE]; +}; + +struct scmi_power_set_state { + __le32 flags; +#define STATE_SET_ASYNC BIT(0) + __le32 domain; + __le32 state; +}; + +struct scmi_power_state_notify { + __le32 domain; + __le32 notify_enable; +}; + +struct power_dom_info { + bool state_set_sync; + bool state_set_async; + bool state_set_notify; + char name[SCMI_MAX_STR_SIZE]; +}; + +struct scmi_power_info { + int num_domains; + u64 stats_addr; + u32 stats_size; + struct power_dom_info *dom_info; +}; + +static int scmi_power_attributes_get(const struct scmi_handle *handle, + struct scmi_power_info *pi) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_power_attributes *attr; + + ret = scmi_one_xfer_init(handle, PROTOCOL_ATTRIBUTES, + SCMI_PROTOCOL_POWER, 0, sizeof(*attr), &t); + if (ret) + return ret; + + attr = t->rx.buf; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + pi->num_domains = le16_to_cpu(attr->num_domains); + pi->stats_addr = le32_to_cpu(attr->stats_addr_low) | + (u64)le32_to_cpu(attr->stats_addr_high) << 32; + pi->stats_size = le32_to_cpu(attr->stats_size); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_power_domain_attributes_get(const struct scmi_handle *handle, u32 domain, + struct power_dom_info *dom_info) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_power_domain_attributes *attr; + + ret = scmi_one_xfer_init(handle, POWER_DOMAIN_ATTRIBUTES, + SCMI_PROTOCOL_POWER, sizeof(domain), + sizeof(*attr), &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(domain); + attr = t->rx.buf; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + u32 flags = le32_to_cpu(attr->flags); + + dom_info->state_set_notify = SUPPORTS_STATE_SET_NOTIFY(flags); + dom_info->state_set_async = SUPPORTS_STATE_SET_ASYNC(flags); + dom_info->state_set_sync = SUPPORTS_STATE_SET_SYNC(flags); + memcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_power_state_set(const struct scmi_handle *handle, u32 domain, u32 state) +{ + int ret; + struct scmi_xfer *t; + struct scmi_power_set_state *st; + + ret = scmi_one_xfer_init(handle, POWER_STATE_SET, SCMI_PROTOCOL_POWER, + sizeof(*st), 0, &t); + if (ret) + return ret; + + st = t->tx.buf; + st->flags = cpu_to_le32(0); + st->domain = cpu_to_le32(domain); + st->state = cpu_to_le32(state); + + ret = scmi_do_xfer(handle, t); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_power_state_get(const struct scmi_handle *handle, u32 domain, u32 *state) +{ + int ret; + struct scmi_xfer *t; + + ret = scmi_one_xfer_init(handle, POWER_STATE_GET, SCMI_PROTOCOL_POWER, + sizeof(u32), sizeof(u32), &t); + if (ret) + return ret; + + *(__le32 *)t->tx.buf = cpu_to_le32(domain); + + ret = scmi_do_xfer(handle, t); + if (!ret) + *state = le32_to_cpu(*(__le32 *)t->rx.buf); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_power_num_domains_get(const struct scmi_handle *handle) +{ + struct scmi_power_info *pi = handle->power_priv; + + return pi->num_domains; +} + +static char *scmi_power_name_get(const struct scmi_handle *handle, u32 domain) +{ + struct scmi_power_info *pi = handle->power_priv; + struct power_dom_info *dom = pi->dom_info + domain; + + return dom->name; +} + +static struct scmi_power_ops power_ops = { + .num_domains_get = scmi_power_num_domains_get, + .name_get = scmi_power_name_get, + .state_set = scmi_power_state_set, + .state_get = scmi_power_state_get, +}; + +static int scmi_power_protocol_init(struct scmi_handle *handle) +{ + int domain; + u32 version; + struct scmi_power_info *pinfo; + + scmi_version_get(handle, SCMI_PROTOCOL_POWER, &version); + + dev_dbg(handle->dev, "Power Version %d.%d\n", + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); + + pinfo = devm_kzalloc(handle->dev, sizeof(*pinfo), GFP_KERNEL); + if (!pinfo) + return -ENOMEM; + + scmi_power_attributes_get(handle, pinfo); + + pinfo->dom_info = devm_kcalloc(handle->dev, pinfo->num_domains, + sizeof(*pinfo->dom_info), GFP_KERNEL); + if (!pinfo->dom_info) + return -ENOMEM; + + for (domain = 0; domain < pinfo->num_domains; domain++) { + struct power_dom_info *dom = pinfo->dom_info + domain; + + scmi_power_domain_attributes_get(handle, domain, dom); + } + + handle->power_ops = &power_ops; + handle->power_priv = pinfo; + + return 0; +} + +static int __init scmi_power_init(void) +{ + return scmi_protocol_register(SCMI_PROTOCOL_POWER, + &scmi_power_protocol_init); +} +subsys_initcall(scmi_power_init); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 5a3092f05011..8cd0348787bc 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -112,11 +112,37 @@ struct scmi_perf_ops { unsigned long *rate); }; +/** + * struct scmi_power_ops - represents the various operations provided + * by SCMI Power Protocol + * + * @num_domains_get: get the count of power domains provided by SCMI + * @name_get: gets the name of a power domain + * @state_set: sets the power state of a power domain + * @state_get: gets the power state of a power domain + */ +struct scmi_power_ops { + int (*num_domains_get)(const struct scmi_handle *handle); + char *(*name_get)(const struct scmi_handle *handle, u32 domain); +#define SCMI_POWER_STATE_TYPE_SHIFT 30 +#define SCMI_POWER_STATE_ID_MASK (BIT(28) - 1) +#define SCMI_POWER_STATE_PARAM(type, id) \ + ((((type) & BIT(0)) << SCMI_POWER_STATE_TYPE_SHIFT) | \ + ((id) & SCMI_POWER_STATE_ID_MASK)) +#define SCMI_POWER_STATE_GENERIC_ON SCMI_POWER_STATE_PARAM(0, 0) +#define SCMI_POWER_STATE_GENERIC_OFF SCMI_POWER_STATE_PARAM(1, 0) + int (*state_set)(const struct scmi_handle *handle, u32 domain, + u32 state); + int (*state_get)(const struct scmi_handle *handle, u32 domain, + u32 *state); +}; + /** * struct scmi_handle - Handle returned to ARM SCMI clients for usage. * * @dev: pointer to the SCMI device * @version: pointer to the structure containing SCMI version information + * @power_ops: pointer to set of power protocol operations * @perf_ops: pointer to set of performance protocol operations * @clk_ops: pointer to set of clock protocol operations */ @@ -125,9 +151,11 @@ struct scmi_handle { struct scmi_revision_info *version; struct scmi_perf_ops *perf_ops; struct scmi_clk_ops *clk_ops; + struct scmi_power_ops *power_ops; /* for protocol internal use */ void *perf_priv; void *clk_priv; + void *power_priv; }; enum scmi_std_protocol { -- cgit v1.2.3 From 5179c523c1eae4b80fbafe9656bc24a375217cac Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 6 Jun 2017 11:38:10 +0100 Subject: firmware: arm_scmi: add initial support for sensor protocol The sensor protocol provides functions to manage platform sensors, and provides the commands to describe the protocol version and the various attribute flags. It also provides commands to discover various sensors implemented and managed by the platform, read any sensor synchronously or asynchronously as allowed by the platform, program sensor attributes and/or configurations, if applicable. This patch adds support for most of the above features. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/Makefile | 2 +- drivers/firmware/arm_scmi/sensors.c | 291 ++++++++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 46 ++++++ 3 files changed, 338 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/sensors.c (limited to 'include/linux') diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index 420c761ced94..3236890905b9 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -1,4 +1,4 @@ obj-y = scmi-bus.o scmi-driver.o scmi-protocols.o scmi-bus-y = bus.o scmi-driver-y = driver.o -scmi-protocols-y = base.o clock.o perf.o power.o +scmi-protocols-y = base.o clock.o perf.o power.o sensors.o diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c new file mode 100644 index 000000000000..bbb469fea0ed --- /dev/null +++ b/drivers/firmware/arm_scmi/sensors.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Sensor Protocol + * + * Copyright (C) 2018 ARM Ltd. + */ + +#include "common.h" + +enum scmi_sensor_protocol_cmd { + SENSOR_DESCRIPTION_GET = 0x3, + SENSOR_CONFIG_SET = 0x4, + SENSOR_TRIP_POINT_SET = 0x5, + SENSOR_READING_GET = 0x6, +}; + +struct scmi_msg_resp_sensor_attributes { + __le16 num_sensors; + u8 max_requests; + u8 reserved; + __le32 reg_addr_low; + __le32 reg_addr_high; + __le32 reg_size; +}; + +struct scmi_msg_resp_sensor_description { + __le16 num_returned; + __le16 num_remaining; + struct { + __le32 id; + __le32 attributes_low; +#define SUPPORTS_ASYNC_READ(x) ((x) & BIT(31)) +#define NUM_TRIP_POINTS(x) (((x) >> 4) & 0xff) + __le32 attributes_high; +#define SENSOR_TYPE(x) ((x) & 0xff) +#define SENSOR_SCALE(x) (((x) >> 11) & 0x3f) +#define SENSOR_UPDATE_SCALE(x) (((x) >> 22) & 0x1f) +#define SENSOR_UPDATE_BASE(x) (((x) >> 27) & 0x1f) + u8 name[SCMI_MAX_STR_SIZE]; + } desc[0]; +}; + +struct scmi_msg_set_sensor_config { + __le32 id; + __le32 event_control; +}; + +struct scmi_msg_set_sensor_trip_point { + __le32 id; + __le32 event_control; +#define SENSOR_TP_EVENT_MASK (0x3) +#define SENSOR_TP_DISABLED 0x0 +#define SENSOR_TP_POSITIVE 0x1 +#define SENSOR_TP_NEGATIVE 0x2 +#define SENSOR_TP_BOTH 0x3 +#define SENSOR_TP_ID(x) (((x) & 0xff) << 4) + __le32 value_low; + __le32 value_high; +}; + +struct scmi_msg_sensor_reading_get { + __le32 id; + __le32 flags; +#define SENSOR_READ_ASYNC BIT(0) +}; + +struct sensors_info { + int num_sensors; + int max_requests; + u64 reg_addr; + u32 reg_size; + struct scmi_sensor_info *sensors; +}; + +static int scmi_sensor_attributes_get(const struct scmi_handle *handle, + struct sensors_info *si) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_resp_sensor_attributes *attr; + + ret = scmi_one_xfer_init(handle, PROTOCOL_ATTRIBUTES, + SCMI_PROTOCOL_SENSOR, 0, sizeof(*attr), &t); + if (ret) + return ret; + + attr = t->rx.buf; + + ret = scmi_do_xfer(handle, t); + if (!ret) { + si->num_sensors = le16_to_cpu(attr->num_sensors); + si->max_requests = attr->max_requests; + si->reg_addr = le32_to_cpu(attr->reg_addr_low) | + (u64)le32_to_cpu(attr->reg_addr_high) << 32; + si->reg_size = le32_to_cpu(attr->reg_size); + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_sensor_description_get(const struct scmi_handle *handle, + struct sensors_info *si) +{ + int ret, cnt; + u32 desc_index = 0; + u16 num_returned, num_remaining; + struct scmi_xfer *t; + struct scmi_msg_resp_sensor_description *buf; + + ret = scmi_one_xfer_init(handle, SENSOR_DESCRIPTION_GET, + SCMI_PROTOCOL_SENSOR, sizeof(__le32), 0, &t); + if (ret) + return ret; + + buf = t->rx.buf; + + do { + /* Set the number of sensors to be skipped/already read */ + *(__le32 *)t->tx.buf = cpu_to_le32(desc_index); + + ret = scmi_do_xfer(handle, t); + if (ret) + break; + + num_returned = le16_to_cpu(buf->num_returned); + num_remaining = le16_to_cpu(buf->num_remaining); + + if (desc_index + num_returned > si->num_sensors) { + dev_err(handle->dev, "No. of sensors can't exceed %d", + si->num_sensors); + break; + } + + for (cnt = 0; cnt < num_returned; cnt++) { + u32 attrh; + struct scmi_sensor_info *s; + + attrh = le32_to_cpu(buf->desc[cnt].attributes_high); + s = &si->sensors[desc_index + cnt]; + s->id = le32_to_cpu(buf->desc[cnt].id); + s->type = SENSOR_TYPE(attrh); + memcpy(s->name, buf->desc[cnt].name, SCMI_MAX_STR_SIZE); + } + + desc_index += num_returned; + /* + * check for both returned and remaining to avoid infinite + * loop due to buggy firmware + */ + } while (num_returned && num_remaining); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int +scmi_sensor_configuration_set(const struct scmi_handle *handle, u32 sensor_id) +{ + int ret; + u32 evt_cntl = BIT(0); + struct scmi_xfer *t; + struct scmi_msg_set_sensor_config *cfg; + + ret = scmi_one_xfer_init(handle, SENSOR_CONFIG_SET, + SCMI_PROTOCOL_SENSOR, sizeof(*cfg), 0, &t); + if (ret) + return ret; + + cfg = t->tx.buf; + cfg->id = cpu_to_le32(sensor_id); + cfg->event_control = cpu_to_le32(evt_cntl); + + ret = scmi_do_xfer(handle, t); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_sensor_trip_point_set(const struct scmi_handle *handle, + u32 sensor_id, u8 trip_id, u64 trip_value) +{ + int ret; + u32 evt_cntl = SENSOR_TP_BOTH; + struct scmi_xfer *t; + struct scmi_msg_set_sensor_trip_point *trip; + + ret = scmi_one_xfer_init(handle, SENSOR_TRIP_POINT_SET, + SCMI_PROTOCOL_SENSOR, sizeof(*trip), 0, &t); + if (ret) + return ret; + + trip = t->tx.buf; + trip->id = cpu_to_le32(sensor_id); + trip->event_control = cpu_to_le32(evt_cntl | SENSOR_TP_ID(trip_id)); + trip->value_low = cpu_to_le32(trip_value & 0xffffffff); + trip->value_high = cpu_to_le32(trip_value >> 32); + + ret = scmi_do_xfer(handle, t); + + scmi_one_xfer_put(handle, t); + return ret; +} + +static int scmi_sensor_reading_get(const struct scmi_handle *handle, + u32 sensor_id, bool async, u64 *value) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_sensor_reading_get *sensor; + + ret = scmi_one_xfer_init(handle, SENSOR_READING_GET, + SCMI_PROTOCOL_SENSOR, sizeof(*sensor), + sizeof(u64), &t); + if (ret) + return ret; + + sensor = t->tx.buf; + sensor->id = cpu_to_le32(sensor_id); + sensor->flags = cpu_to_le32(async ? SENSOR_READ_ASYNC : 0); + + ret = scmi_do_xfer(handle, t); + if (!ret) { + __le32 *pval = t->rx.buf; + + *value = le32_to_cpu(*pval); + *value |= (u64)le32_to_cpu(*(pval + 1)) << 32; + } + + scmi_one_xfer_put(handle, t); + return ret; +} + +static const struct scmi_sensor_info * +scmi_sensor_info_get(const struct scmi_handle *handle, u32 sensor_id) +{ + struct sensors_info *si = handle->sensor_priv; + + return si->sensors + sensor_id; +} + +static int scmi_sensor_count_get(const struct scmi_handle *handle) +{ + struct sensors_info *si = handle->sensor_priv; + + return si->num_sensors; +} + +static struct scmi_sensor_ops sensor_ops = { + .count_get = scmi_sensor_count_get, + .info_get = scmi_sensor_info_get, + .configuration_set = scmi_sensor_configuration_set, + .trip_point_set = scmi_sensor_trip_point_set, + .reading_get = scmi_sensor_reading_get, +}; + +static int scmi_sensors_protocol_init(struct scmi_handle *handle) +{ + u32 version; + struct sensors_info *sinfo; + + scmi_version_get(handle, SCMI_PROTOCOL_SENSOR, &version); + + dev_dbg(handle->dev, "Sensor Version %d.%d\n", + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); + + sinfo = devm_kzalloc(handle->dev, sizeof(*sinfo), GFP_KERNEL); + if (!sinfo) + return -ENOMEM; + + scmi_sensor_attributes_get(handle, sinfo); + + sinfo->sensors = devm_kcalloc(handle->dev, sinfo->num_sensors, + sizeof(*sinfo->sensors), GFP_KERNEL); + if (!sinfo->sensors) + return -ENOMEM; + + scmi_sensor_description_get(handle, sinfo); + + handle->sensor_ops = &sensor_ops; + handle->sensor_priv = sinfo; + + return 0; +} + +static int __init scmi_sensors_init(void) +{ + return scmi_protocol_register(SCMI_PROTOCOL_SENSOR, + &scmi_sensors_protocol_init); +} +subsys_initcall(scmi_sensors_init); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 8cd0348787bc..5d63da9435ba 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -137,6 +137,49 @@ struct scmi_power_ops { u32 *state); }; +struct scmi_sensor_info { + u32 id; + u8 type; + char name[SCMI_MAX_STR_SIZE]; +}; + +/* + * Partial list from Distributed Management Task Force (DMTF) specification: + * DSP0249 (Platform Level Data Model specification) + */ +enum scmi_sensor_class { + NONE = 0x0, + TEMPERATURE_C = 0x2, + VOLTAGE = 0x5, + CURRENT = 0x6, + POWER = 0x7, + ENERGY = 0x8, +}; + +/** + * struct scmi_sensor_ops - represents the various operations provided + * by SCMI Sensor Protocol + * + * @count_get: get the count of sensors provided by SCMI + * @info_get: get the information of the specified sensor + * @configuration_set: control notifications on cross-over events for + * the trip-points + * @trip_point_set: selects and configures a trip-point of interest + * @reading_get: gets the current value of the sensor + */ +struct scmi_sensor_ops { + int (*count_get)(const struct scmi_handle *handle); + + const struct scmi_sensor_info *(*info_get) + (const struct scmi_handle *handle, u32 sensor_id); + int (*configuration_set)(const struct scmi_handle *handle, + u32 sensor_id); + int (*trip_point_set)(const struct scmi_handle *handle, u32 sensor_id, + u8 trip_id, u64 trip_value); + int (*reading_get)(const struct scmi_handle *handle, u32 sensor_id, + bool async, u64 *value); +}; + /** * struct scmi_handle - Handle returned to ARM SCMI clients for usage. * @@ -145,6 +188,7 @@ struct scmi_power_ops { * @power_ops: pointer to set of power protocol operations * @perf_ops: pointer to set of performance protocol operations * @clk_ops: pointer to set of clock protocol operations + * @sensor_ops: pointer to set of sensor protocol operations */ struct scmi_handle { struct device *dev; @@ -152,10 +196,12 @@ struct scmi_handle { struct scmi_perf_ops *perf_ops; struct scmi_clk_ops *clk_ops; struct scmi_power_ops *power_ops; + struct scmi_sensor_ops *sensor_ops; /* for protocol internal use */ void *perf_priv; void *clk_priv; void *power_priv; + void *sensor_priv; }; enum scmi_std_protocol { -- cgit v1.2.3 From 5c4ba3cc85296398855d621bf90b78866ea80444 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Jul 2017 11:42:24 +0100 Subject: firmware: arm_scmi: add option for polling based performance domain operations In order to implement fast CPU DVFS switching, we need to perform all DVFS operations atomically. Since SCMI transfer already provide option to choose between pooling vs interrupt driven(default), we can opt for polling based transfers for set,get performance domain operations. This patch adds option to choose between polling vs interrupt driven SCMI transfers for set,get performance level operations. Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/perf.c | 19 +++++++++++-------- include/linux/scmi_protocol.h | 8 ++++---- 2 files changed, 15 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c index 9c56ea503890..987c64d19801 100644 --- a/drivers/firmware/arm_scmi/perf.c +++ b/drivers/firmware/arm_scmi/perf.c @@ -292,8 +292,8 @@ static int scmi_perf_limits_get(const struct scmi_handle *handle, u32 domain, return ret; } -static int -scmi_perf_level_set(const struct scmi_handle *handle, u32 domain, u32 level) +static int scmi_perf_level_set(const struct scmi_handle *handle, u32 domain, + u32 level, bool poll) { int ret; struct scmi_xfer *t; @@ -304,6 +304,7 @@ scmi_perf_level_set(const struct scmi_handle *handle, u32 domain, u32 level) if (ret) return ret; + t->hdr.poll_completion = poll; lvl = t->tx.buf; lvl->domain = cpu_to_le32(domain); lvl->level = cpu_to_le32(level); @@ -314,8 +315,8 @@ scmi_perf_level_set(const struct scmi_handle *handle, u32 domain, u32 level) return ret; } -static int -scmi_perf_level_get(const struct scmi_handle *handle, u32 domain, u32 *level) +static int scmi_perf_level_get(const struct scmi_handle *handle, u32 domain, + u32 *level, bool poll) { int ret; struct scmi_xfer *t; @@ -325,6 +326,7 @@ scmi_perf_level_get(const struct scmi_handle *handle, u32 domain, u32 *level) if (ret) return ret; + t->hdr.poll_completion = poll; *(__le32 *)t->tx.buf = cpu_to_le32(domain); ret = scmi_do_xfer(handle, t); @@ -400,23 +402,24 @@ static int scmi_dvfs_get_transition_latency(const struct scmi_handle *handle, } static int scmi_dvfs_freq_set(const struct scmi_handle *handle, u32 domain, - unsigned long freq) + unsigned long freq, bool poll) { struct scmi_perf_info *pi = handle->perf_priv; struct perf_dom_info *dom = pi->dom_info + domain; - return scmi_perf_level_set(handle, domain, freq / dom->mult_factor); + return scmi_perf_level_set(handle, domain, freq / dom->mult_factor, + poll); } static int scmi_dvfs_freq_get(const struct scmi_handle *handle, u32 domain, - unsigned long *freq) + unsigned long *freq, bool poll) { int ret; u32 level; struct scmi_perf_info *pi = handle->perf_priv; struct perf_dom_info *dom = pi->dom_info + domain; - ret = scmi_perf_level_get(handle, domain, &level); + ret = scmi_perf_level_get(handle, domain, &level, poll); if (!ret) *freq = level * dom->mult_factor; diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 5d63da9435ba..b458c87b866c 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -98,18 +98,18 @@ struct scmi_perf_ops { int (*limits_get)(const struct scmi_handle *handle, u32 domain, u32 *max_perf, u32 *min_perf); int (*level_set)(const struct scmi_handle *handle, u32 domain, - u32 level); + u32 level, bool poll); int (*level_get)(const struct scmi_handle *handle, u32 domain, - u32 *level); + u32 *level, bool poll); int (*device_domain_id)(struct device *dev); int (*get_transition_latency)(const struct scmi_handle *handle, struct device *dev); int (*add_opps_to_device)(const struct scmi_handle *handle, struct device *dev); int (*freq_set)(const struct scmi_handle *handle, u32 domain, - unsigned long rate); + unsigned long rate, bool poll); int (*freq_get)(const struct scmi_handle *handle, u32 domain, - unsigned long *rate); + unsigned long *rate, bool poll); }; /** -- cgit v1.2.3 From d57538004b2e57be6a5d8583b65d1b049245abf7 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 27 Sep 2017 16:20:50 +0100 Subject: hwmon: (core) Add hwmon_max to hwmon_sensor_types enumeration It's useful to know the maximum types of sensor supported by hwmon framework. It can be used to allocate some data structures when sorting the monitors based on their type. This will be used by scmi hwmon support. Cc: linux-hwmon@vger.kernel.org Acked-by: Guenter Roeck Signed-off-by: Sudeep Holla --- include/linux/hwmon.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/hwmon.h b/include/linux/hwmon.h index ceb751987c40..e5fd2707b6df 100644 --- a/include/linux/hwmon.h +++ b/include/linux/hwmon.h @@ -29,6 +29,7 @@ enum hwmon_sensor_types { hwmon_humidity, hwmon_fan, hwmon_pwm, + hwmon_max, }; enum hwmon_chip_attributes { -- cgit v1.2.3 From 723fbf563a6a9cefbd3c58e95694583ad1cb8704 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Thu, 15 Feb 2018 09:03:56 +0530 Subject: lib/scatterlist: Add SG_CHAIN and SG_END macros for LSB encodings This replaces scatterlist->page_link LSB encodings with SG_CHAIN and SG_END definitions without any functional change. Signed-off-by: Anshuman Khandual Signed-off-by: Jens Axboe --- include/linux/scatterlist.h | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h index 22b2131bcdcd..b6fe1815f5c4 100644 --- a/include/linux/scatterlist.h +++ b/include/linux/scatterlist.h @@ -65,16 +65,18 @@ struct sg_table { */ #define SG_MAGIC 0x87654321 +#define SG_CHAIN 0x01UL +#define SG_END 0x02UL /* * We overload the LSB of the page pointer to indicate whether it's * a valid sg entry, or whether it points to the start of a new scatterlist. * Those low bits are there for everyone! (thanks mason :-) */ -#define sg_is_chain(sg) ((sg)->page_link & 0x01) -#define sg_is_last(sg) ((sg)->page_link & 0x02) +#define sg_is_chain(sg) ((sg)->page_link & SG_CHAIN) +#define sg_is_last(sg) ((sg)->page_link & SG_END) #define sg_chain_ptr(sg) \ - ((struct scatterlist *) ((sg)->page_link & ~0x03)) + ((struct scatterlist *) ((sg)->page_link & ~(SG_CHAIN | SG_END))) /** * sg_assign_page - Assign a given page to an SG entry @@ -88,13 +90,13 @@ struct sg_table { **/ static inline void sg_assign_page(struct scatterlist *sg, struct page *page) { - unsigned long page_link = sg->page_link & 0x3; + unsigned long page_link = sg->page_link & (SG_CHAIN | SG_END); /* * In order for the low bit stealing approach to work, pages * must be aligned at a 32-bit boundary as a minimum. */ - BUG_ON((unsigned long) page & 0x03); + BUG_ON((unsigned long) page & (SG_CHAIN | SG_END)); #ifdef CONFIG_DEBUG_SG BUG_ON(sg->sg_magic != SG_MAGIC); BUG_ON(sg_is_chain(sg)); @@ -130,7 +132,7 @@ static inline struct page *sg_page(struct scatterlist *sg) BUG_ON(sg->sg_magic != SG_MAGIC); BUG_ON(sg_is_chain(sg)); #endif - return (struct page *)((sg)->page_link & ~0x3); + return (struct page *)((sg)->page_link & ~(SG_CHAIN | SG_END)); } /** @@ -178,7 +180,8 @@ static inline void sg_chain(struct scatterlist *prv, unsigned int prv_nents, * Set lowest bit to indicate a link pointer, and make sure to clear * the termination bit if it happens to be set. */ - prv[prv_nents - 1].page_link = ((unsigned long) sgl | 0x01) & ~0x02; + prv[prv_nents - 1].page_link = ((unsigned long) sgl | SG_CHAIN) + & ~SG_END; } /** @@ -198,8 +201,8 @@ static inline void sg_mark_end(struct scatterlist *sg) /* * Set termination bit, clear potential chain bit */ - sg->page_link |= 0x02; - sg->page_link &= ~0x01; + sg->page_link |= SG_END; + sg->page_link &= ~SG_CHAIN; } /** @@ -215,7 +218,7 @@ static inline void sg_unmark_end(struct scatterlist *sg) #ifdef CONFIG_DEBUG_SG BUG_ON(sg->sg_magic != SG_MAGIC); #endif - sg->page_link &= ~0x02; + sg->page_link &= ~SG_END; } /** -- cgit v1.2.3 From 4ace53f1ed40a5cfee4bdd7614c8a8b2798227ad Mon Sep 17 00:00:00 2001 From: Omar Sandoval Date: Tue, 27 Feb 2018 16:56:43 -0800 Subject: sbitmap: use test_and_set_bit_lock()/clear_bit_unlock() sbitmap_queue_get()/sbitmap_queue_clear() are used for allocating/freeing a resource, so they should provide acquire/release barrier semantics, respectively. sbitmap_get() currently contains a full barrier, which is unnecessary, so use test_and_set_bit_lock() instead of test_and_set_bit() (these are equivalent on x86_64). sbitmap_clear_bit() does not imply any barriers, which is incorrect, as accesses of the resource (e.g., request) could potentially get reordered to after the clear_bit(). Introduce sbitmap_clear_bit_unlock() and use it for sbitmap_queue_clear() (this only adds a compiler barrier on x86_64). The other existing user of sbitmap_clear_bit() (the blk-mq software queue pending map) is serialized through a spinlock and does not need this. Reported-by: Tejun Heo Acked-by: Tejun Heo Signed-off-by: Omar Sandoval Signed-off-by: Jens Axboe --- include/linux/sbitmap.h | 8 ++++++++ lib/sbitmap.c | 10 +++++----- 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sbitmap.h b/include/linux/sbitmap.h index 0dcc60e820de..841585f6e5f2 100644 --- a/include/linux/sbitmap.h +++ b/include/linux/sbitmap.h @@ -171,6 +171,8 @@ void sbitmap_resize(struct sbitmap *sb, unsigned int depth); * starting from the last allocated bit. This is less efficient * than the default behavior (false). * + * This operation provides acquire barrier semantics if it succeeds. + * * Return: Non-negative allocated bit number if successful, -1 otherwise. */ int sbitmap_get(struct sbitmap *sb, unsigned int alloc_hint, bool round_robin); @@ -300,6 +302,12 @@ static inline void sbitmap_clear_bit(struct sbitmap *sb, unsigned int bitnr) clear_bit(SB_NR_TO_BIT(sb, bitnr), __sbitmap_word(sb, bitnr)); } +static inline void sbitmap_clear_bit_unlock(struct sbitmap *sb, + unsigned int bitnr) +{ + clear_bit_unlock(SB_NR_TO_BIT(sb, bitnr), __sbitmap_word(sb, bitnr)); +} + static inline int sbitmap_test_bit(struct sbitmap *sb, unsigned int bitnr) { return test_bit(SB_NR_TO_BIT(sb, bitnr), __sbitmap_word(sb, bitnr)); diff --git a/lib/sbitmap.c b/lib/sbitmap.c index 42b5ca0acf93..e6a9c06ec70c 100644 --- a/lib/sbitmap.c +++ b/lib/sbitmap.c @@ -100,7 +100,7 @@ static int __sbitmap_get_word(unsigned long *word, unsigned long depth, return -1; } - if (!test_and_set_bit(nr, word)) + if (!test_and_set_bit_lock(nr, word)) break; hint = nr + 1; @@ -434,9 +434,9 @@ static void sbq_wake_up(struct sbitmap_queue *sbq) /* * Pairs with the memory barrier in set_current_state() to ensure the * proper ordering of clear_bit()/waitqueue_active() in the waker and - * test_and_set_bit()/prepare_to_wait()/finish_wait() in the waiter. See - * the comment on waitqueue_active(). This is __after_atomic because we - * just did clear_bit() in the caller. + * test_and_set_bit_lock()/prepare_to_wait()/finish_wait() in the + * waiter. See the comment on waitqueue_active(). This is __after_atomic + * because we just did clear_bit_unlock() in the caller. */ smp_mb__after_atomic(); @@ -469,7 +469,7 @@ static void sbq_wake_up(struct sbitmap_queue *sbq) void sbitmap_queue_clear(struct sbitmap_queue *sbq, unsigned int nr, unsigned int cpu) { - sbitmap_clear_bit(&sbq->sb, nr); + sbitmap_clear_bit_unlock(&sbq->sb, nr); sbq_wake_up(sbq); if (likely(!sbq->round_robin && nr < sbq->sb.depth)) *per_cpu_ptr(sbq->alloc_hint, cpu) = nr; -- cgit v1.2.3 From 5ee0524ba137fe928a88b440d014e3c8451fb32c Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Wed, 28 Feb 2018 10:15:31 -0800 Subject: block: Add 'lock' as third argument to blk_alloc_queue_node() This patch does not change any functionality. Signed-off-by: Bart Van Assche Reviewed-by: Joseph Qi Cc: Christoph Hellwig Cc: Philipp Reisner Cc: Ulf Hansson Cc: Kees Cook Signed-off-by: Jens Axboe --- block/blk-core.c | 7 ++++--- block/blk-mq.c | 2 +- drivers/block/null_blk.c | 3 ++- drivers/ide/ide-probe.c | 2 +- drivers/lightnvm/core.c | 2 +- drivers/md/dm.c | 2 +- drivers/nvdimm/pmem.c | 2 +- drivers/nvme/host/multipath.c | 2 +- drivers/scsi/scsi_lib.c | 2 +- include/linux/blkdev.h | 3 ++- 10 files changed, 15 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/block/blk-core.c b/block/blk-core.c index 2d1a7bbe0634..e873a24bf82d 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -810,7 +810,7 @@ void blk_exit_rl(struct request_queue *q, struct request_list *rl) struct request_queue *blk_alloc_queue(gfp_t gfp_mask) { - return blk_alloc_queue_node(gfp_mask, NUMA_NO_NODE); + return blk_alloc_queue_node(gfp_mask, NUMA_NO_NODE, NULL); } EXPORT_SYMBOL(blk_alloc_queue); @@ -888,7 +888,8 @@ static void blk_rq_timed_out_timer(struct timer_list *t) kblockd_schedule_work(&q->timeout_work); } -struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) +struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id, + spinlock_t *lock) { struct request_queue *q; @@ -1030,7 +1031,7 @@ blk_init_queue_node(request_fn_proc *rfn, spinlock_t *lock, int node_id) { struct request_queue *q; - q = blk_alloc_queue_node(GFP_KERNEL, node_id); + q = blk_alloc_queue_node(GFP_KERNEL, node_id, NULL); if (!q) return NULL; diff --git a/block/blk-mq.c b/block/blk-mq.c index 9594a0e9f65b..75336848f7a7 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -2556,7 +2556,7 @@ struct request_queue *blk_mq_init_queue(struct blk_mq_tag_set *set) { struct request_queue *uninit_q, *q; - uninit_q = blk_alloc_queue_node(GFP_KERNEL, set->numa_node); + uninit_q = blk_alloc_queue_node(GFP_KERNEL, set->numa_node, NULL); if (!uninit_q) return ERR_PTR(-ENOMEM); diff --git a/drivers/block/null_blk.c b/drivers/block/null_blk.c index d12d7a8325ad..6dc7e7cfca4a 100644 --- a/drivers/block/null_blk.c +++ b/drivers/block/null_blk.c @@ -1760,7 +1760,8 @@ static int null_add_dev(struct nullb_device *dev) } null_init_queues(nullb); } else if (dev->queue_mode == NULL_Q_BIO) { - nullb->q = blk_alloc_queue_node(GFP_KERNEL, dev->home_node); + nullb->q = blk_alloc_queue_node(GFP_KERNEL, dev->home_node, + NULL); if (!nullb->q) { rv = -ENOMEM; goto out_cleanup_queues; diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c index caa20eb5f26b..d6b8c7e1545d 100644 --- a/drivers/ide/ide-probe.c +++ b/drivers/ide/ide-probe.c @@ -766,7 +766,7 @@ static int ide_init_queue(ide_drive_t *drive) * limits and LBA48 we could raise it but as yet * do not. */ - q = blk_alloc_queue_node(GFP_KERNEL, hwif_to_node(hwif)); + q = blk_alloc_queue_node(GFP_KERNEL, hwif_to_node(hwif), NULL); if (!q) return 1; diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index dcc9e621e651..5f1988df1593 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -384,7 +384,7 @@ static int nvm_create_tgt(struct nvm_dev *dev, struct nvm_ioctl_create *create) goto err_dev; } - tqueue = blk_alloc_queue_node(GFP_KERNEL, dev->q->node); + tqueue = blk_alloc_queue_node(GFP_KERNEL, dev->q->node, NULL); if (!tqueue) { ret = -ENOMEM; goto err_disk; diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 68136806d365..7586d249266c 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -1841,7 +1841,7 @@ static struct mapped_device *alloc_dev(int minor) INIT_LIST_HEAD(&md->table_devices); spin_lock_init(&md->uevent_lock); - md->queue = blk_alloc_queue_node(GFP_KERNEL, numa_node_id); + md->queue = blk_alloc_queue_node(GFP_KERNEL, numa_node_id, NULL); if (!md->queue) goto bad; md->queue->queuedata = md; diff --git a/drivers/nvdimm/pmem.c b/drivers/nvdimm/pmem.c index 10041ac4032c..cfb15ac50925 100644 --- a/drivers/nvdimm/pmem.c +++ b/drivers/nvdimm/pmem.c @@ -344,7 +344,7 @@ static int pmem_attach_disk(struct device *dev, return -EBUSY; } - q = blk_alloc_queue_node(GFP_KERNEL, dev_to_node(dev)); + q = blk_alloc_queue_node(GFP_KERNEL, dev_to_node(dev), NULL); if (!q) return -ENOMEM; diff --git a/drivers/nvme/host/multipath.c b/drivers/nvme/host/multipath.c index b7e5c6db4d92..88440562a197 100644 --- a/drivers/nvme/host/multipath.c +++ b/drivers/nvme/host/multipath.c @@ -162,7 +162,7 @@ int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, struct nvme_ns_head *head) if (!(ctrl->subsys->cmic & (1 << 1)) || !multipath) return 0; - q = blk_alloc_queue_node(GFP_KERNEL, NUMA_NO_NODE); + q = blk_alloc_queue_node(GFP_KERNEL, NUMA_NO_NODE, NULL); if (!q) goto out; q->queuedata = head; diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index a86df9ca7d1c..71d1135f94d0 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -2223,7 +2223,7 @@ struct request_queue *scsi_old_alloc_queue(struct scsi_device *sdev) struct Scsi_Host *shost = sdev->host; struct request_queue *q; - q = blk_alloc_queue_node(GFP_KERNEL, NUMA_NO_NODE); + q = blk_alloc_queue_node(GFP_KERNEL, NUMA_NO_NODE, NULL); if (!q) return NULL; q->cmd_size = sizeof(struct scsi_cmnd) + shost->hostt->cmd_size; diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index ed63f3b69c12..667a9b0053d9 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -1321,7 +1321,8 @@ extern long nr_blockdev_pages(void); bool __must_check blk_get_queue(struct request_queue *); struct request_queue *blk_alloc_queue(gfp_t); -struct request_queue *blk_alloc_queue_node(gfp_t, int); +struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id, + spinlock_t *lock); extern void blk_put_queue(struct request_queue *); extern void blk_set_queue_dying(struct request_queue *); -- cgit v1.2.3 From 25e3fca492035a2e1d4ac6e3b1edd9c1acd48897 Mon Sep 17 00:00:00 2001 From: "Jason A. Donenfeld" Date: Sun, 4 Feb 2018 23:07:46 +0100 Subject: random: always fill buffer in get_random_bytes_wait In the unfortunate event that a developer fails to check the return value of get_random_bytes_wait, or simply wants to make a "best effort" attempt, for whatever that's worth, it's much better to still fill the buffer with _something_ rather than catastrophically failing in the case of an interruption. This is both a defense in depth measure against inevitable programming bugs, as well as a means of making the API a bit more useful. Signed-off-by: Jason A. Donenfeld Signed-off-by: Theodore Ts'o --- include/linux/random.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/random.h b/include/linux/random.h index 4024f7d9c77d..2ddf13b4281e 100644 --- a/include/linux/random.h +++ b/include/linux/random.h @@ -85,10 +85,8 @@ static inline unsigned long get_random_canary(void) static inline int get_random_bytes_wait(void *buf, int nbytes) { int ret = wait_for_random_bytes(); - if (unlikely(ret)) - return ret; get_random_bytes(buf, nbytes); - return 0; + return ret; } #define declare_get_random_var_wait(var) \ -- cgit v1.2.3 From fd5cd21d995e67f87b3eb4adf938be85fe83ef4b Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 12 Feb 2018 23:47:19 +0100 Subject: rtc: export rtc_nvmem_register() to drivers Export rtc_nvmem_register() so it can be called from drivers instead of only the core. Signed-off-by: Alexandre Belloni --- drivers/rtc/nvmem.c | 3 +-- drivers/rtc/rtc-core.h | 13 ------------- include/linux/rtc.h | 13 +++++++++++++ 3 files changed, 14 insertions(+), 15 deletions(-) (limited to 'include/linux') diff --git a/drivers/rtc/nvmem.c b/drivers/rtc/nvmem.c index eb8c622cfcf4..17ec4c8d0fad 100644 --- a/drivers/rtc/nvmem.c +++ b/drivers/rtc/nvmem.c @@ -14,8 +14,6 @@ #include #include -#include "rtc-core.h" - /* * Deprecated ABI compatibility, this should be removed at some point */ @@ -105,6 +103,7 @@ int rtc_nvmem_register(struct rtc_device *rtc, return 0; } +EXPORT_SYMBOL_GPL(rtc_nvmem_register); void rtc_nvmem_unregister(struct rtc_device *rtc) { diff --git a/drivers/rtc/rtc-core.h b/drivers/rtc/rtc-core.h index 05a67837fd76..0abf98983e13 100644 --- a/drivers/rtc/rtc-core.h +++ b/drivers/rtc/rtc-core.h @@ -46,16 +46,3 @@ static inline const struct attribute_group **rtc_get_dev_attribute_groups(void) return NULL; } #endif - -#ifdef CONFIG_RTC_NVMEM -int rtc_nvmem_register(struct rtc_device *rtc, - struct nvmem_config *nvmem_config); -void rtc_nvmem_unregister(struct rtc_device *rtc); -#else -static inline int rtc_nvmem_register(struct rtc_device *rtc, - struct nvmem_config *nvmem_config) -{ - return -ENODEV; -} -static inline void rtc_nvmem_unregister(struct rtc_device *rtc) {} -#endif diff --git a/include/linux/rtc.h b/include/linux/rtc.h index fc6c90b57be0..fbc92fff7c2e 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -271,4 +271,17 @@ extern int rtc_hctosys_ret; #define rtc_hctosys_ret -ENODEV #endif +#ifdef CONFIG_RTC_NVMEM +int rtc_nvmem_register(struct rtc_device *rtc, + struct nvmem_config *nvmem_config); +void rtc_nvmem_unregister(struct rtc_device *rtc); +#else +static inline int rtc_nvmem_register(struct rtc_device *rtc, + struct nvmem_config *nvmem_config) +{ + return -ENODEV; +} +static inline void rtc_nvmem_unregister(struct rtc_device *rtc) {} +#endif + #endif /* _LINUX_RTC_H_ */ -- cgit v1.2.3 From 0391df74a608e4e65c29ddf80e704edfa8f8ef25 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 12 Feb 2018 23:47:34 +0100 Subject: rtc: remove nvmem_config Because nvmem_config is only used and copied at nvmem registration, remove it from struct rtc_device. All the rtc drivers using nvmem are now calling rtc_nvmem_register directly. Signed-off-by: Alexandre Belloni --- drivers/rtc/class.c | 2 -- include/linux/rtc.h | 1 - 2 files changed, 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c index 0cab397f6e37..5a5ab4fa14f9 100644 --- a/drivers/rtc/class.c +++ b/drivers/rtc/class.c @@ -454,8 +454,6 @@ int __rtc_register_device(struct module *owner, struct rtc_device *rtc) rtc_proc_add_device(rtc); - rtc_nvmem_register(rtc, rtc->nvmem_config); - rtc->registered = true; dev_info(rtc->dev.parent, "registered as %s\n", dev_name(&rtc->dev)); diff --git a/include/linux/rtc.h b/include/linux/rtc.h index fbc92fff7c2e..37b041f72f8d 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -145,7 +145,6 @@ struct rtc_device { bool registered; - struct nvmem_config *nvmem_config; struct nvmem_device *nvmem; /* Old ABI support */ bool nvram_old_abi; -- cgit v1.2.3 From 9e7002a70e4294a093b3cacf2346af33aeefd265 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 6 Feb 2018 23:12:26 +0100 Subject: char: rtc: remove unused rtc_control() API Since commit 34ce71a96dcb ("ALSA: timer: remove legacy rtctimer"), the rtc_register/rtc_control/rtc_unregister API is unused. As it is highly unlikely to be needed again, remove it. Acked-by: Greg Kroah-Hartman Acked-by: Arnd Bergmann Signed-off-by: Alexandre Belloni --- drivers/char/rtc.c | 83 ----------------------------------------------------- include/linux/rtc.h | 4 --- 2 files changed, 87 deletions(-) (limited to 'include/linux') diff --git a/drivers/char/rtc.c b/drivers/char/rtc.c index 0c858d027bf3..57dc546628b5 100644 --- a/drivers/char/rtc.c +++ b/drivers/char/rtc.c @@ -809,89 +809,6 @@ static __poll_t rtc_poll(struct file *file, poll_table *wait) } #endif -int rtc_register(rtc_task_t *task) -{ -#ifndef RTC_IRQ - return -EIO; -#else - if (task == NULL || task->func == NULL) - return -EINVAL; - spin_lock_irq(&rtc_lock); - if (rtc_status & RTC_IS_OPEN) { - spin_unlock_irq(&rtc_lock); - return -EBUSY; - } - spin_lock(&rtc_task_lock); - if (rtc_callback) { - spin_unlock(&rtc_task_lock); - spin_unlock_irq(&rtc_lock); - return -EBUSY; - } - rtc_status |= RTC_IS_OPEN; - rtc_callback = task; - spin_unlock(&rtc_task_lock); - spin_unlock_irq(&rtc_lock); - return 0; -#endif -} -EXPORT_SYMBOL(rtc_register); - -int rtc_unregister(rtc_task_t *task) -{ -#ifndef RTC_IRQ - return -EIO; -#else - unsigned char tmp; - - spin_lock_irq(&rtc_lock); - spin_lock(&rtc_task_lock); - if (rtc_callback != task) { - spin_unlock(&rtc_task_lock); - spin_unlock_irq(&rtc_lock); - return -ENXIO; - } - rtc_callback = NULL; - - /* disable controls */ - if (!hpet_mask_rtc_irq_bit(RTC_PIE | RTC_AIE | RTC_UIE)) { - tmp = CMOS_READ(RTC_CONTROL); - tmp &= ~RTC_PIE; - tmp &= ~RTC_AIE; - tmp &= ~RTC_UIE; - CMOS_WRITE(tmp, RTC_CONTROL); - CMOS_READ(RTC_INTR_FLAGS); - } - if (rtc_status & RTC_TIMER_ON) { - rtc_status &= ~RTC_TIMER_ON; - del_timer(&rtc_irq_timer); - } - rtc_status &= ~RTC_IS_OPEN; - spin_unlock(&rtc_task_lock); - spin_unlock_irq(&rtc_lock); - return 0; -#endif -} -EXPORT_SYMBOL(rtc_unregister); - -int rtc_control(rtc_task_t *task, unsigned int cmd, unsigned long arg) -{ -#ifndef RTC_IRQ - return -EIO; -#else - unsigned long flags; - if (cmd != RTC_PIE_ON && cmd != RTC_PIE_OFF && cmd != RTC_IRQP_SET) - return -EINVAL; - spin_lock_irqsave(&rtc_task_lock, flags); - if (rtc_callback != task) { - spin_unlock_irqrestore(&rtc_task_lock, flags); - return -ENXIO; - } - spin_unlock_irqrestore(&rtc_task_lock, flags); - return rtc_do_ioctl(cmd, arg, 1); -#endif -} -EXPORT_SYMBOL(rtc_control); - /* * The various file operations we support. */ diff --git a/include/linux/rtc.h b/include/linux/rtc.h index 37b041f72f8d..3b65b201169c 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -211,10 +211,6 @@ void rtc_aie_update_irq(void *private); void rtc_uie_update_irq(void *private); enum hrtimer_restart rtc_pie_update_irq(struct hrtimer *timer); -int rtc_register(rtc_task_t *task); -int rtc_unregister(rtc_task_t *task); -int rtc_control(rtc_task_t *t, unsigned int cmd, unsigned long arg); - void rtc_timer_init(struct rtc_timer *timer, void (*f)(void *p), void *data); int rtc_timer_start(struct rtc_device *rtc, struct rtc_timer *timer, ktime_t expires, ktime_t period); -- cgit v1.2.3 From f16ee7c7ec0fa5f0322bd64d5ee183a28ed1ec08 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 1 Mar 2018 11:31:28 +0100 Subject: misc: rtsx: rename SG_END macro A change to the generic scatterlist code caused a conflict with the rtsx card reader driver: In file included from drivers/misc/cardreader/rtsx_pcr.c:32: include/linux/rtsx_pci.h:40: error: "SG_END" redefined [-Werror] This changes one instance of the driver to prefix SG_END and related constants. Fixes: 723fbf563a6a ("lib/scatterlist: Add SG_CHAIN and SG_END macros for LSB encodings") Cc: Anshuman Khandual Signed-off-by: Arnd Bergmann Signed-off-by: Jens Axboe --- drivers/misc/cardreader/rtsx_pcr.c | 4 ++-- include/linux/rtsx_pci.h | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c index fd09b0960097..e8f1d4bb806a 100644 --- a/drivers/misc/cardreader/rtsx_pcr.c +++ b/drivers/misc/cardreader/rtsx_pcr.c @@ -444,12 +444,12 @@ static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, { u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; u64 val; - u8 option = SG_VALID | SG_TRANS_DATA; + u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA; pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); if (end) - option |= SG_END; + option |= RTSX_SG_END; val = ((u64)addr << 32) | ((u64)len << 12) | option; put_unaligned_le64(val, ptr); diff --git a/include/linux/rtsx_pci.h b/include/linux/rtsx_pci.h index 478acf6efac6..e964bbd03fc2 100644 --- a/include/linux/rtsx_pci.h +++ b/include/linux/rtsx_pci.h @@ -36,12 +36,12 @@ #define CHECK_REG_CMD 2 #define RTSX_HDBAR 0x08 -#define SG_INT 0x04 -#define SG_END 0x02 -#define SG_VALID 0x01 -#define SG_NO_OP 0x00 -#define SG_TRANS_DATA (0x02 << 4) -#define SG_LINK_DESC (0x03 << 4) +#define RTSX_SG_INT 0x04 +#define RTSX_SG_END 0x02 +#define RTSX_SG_VALID 0x01 +#define RTSX_SG_NO_OP 0x00 +#define RTSX_SG_TRANS_DATA (0x02 << 4) +#define RTSX_SG_LINK_DESC (0x03 << 4) #define RTSX_HDBCTLR 0x0C #define SDMA_MODE 0x00 #define ADMA_MODE (0x02 << 26) -- cgit v1.2.3 From 6853f21f764b04e58df5e44629fec1fb8f3cbf2e Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:29 +0200 Subject: ipmr,ipmr6: Define a uniform vif_device The two implementations have almost identical structures - vif_device and mif_device. As a step toward uniforming the mr_tables, eliminate the mif_device and relocate the vif_device definition into a new common header file. Also, introduce a common initializing function for setting most of the vif_device fields in a new common source file. This requires modifying the ipv{4,6] Kconfig and ipv4 makefile as we're introducing a new common config option - CONFIG_IP_MROUTE_COMMON. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute.h | 13 +----------- include/linux/mroute6.h | 11 +--------- include/linux/mroute_base.h | 52 +++++++++++++++++++++++++++++++++++++++++++++ net/ipv4/Kconfig | 5 +++++ net/ipv4/Makefile | 1 + net/ipv4/ipmr.c | 32 +++++++++++++--------------- net/ipv4/ipmr_base.c | 28 ++++++++++++++++++++++++ net/ipv6/Kconfig | 1 + net/ipv6/ip6mr.c | 37 ++++++++++++-------------------- 9 files changed, 117 insertions(+), 63 deletions(-) create mode 100644 include/linux/mroute_base.h create mode 100644 net/ipv4/ipmr_base.c (limited to 'include/linux') diff --git a/include/linux/mroute.h b/include/linux/mroute.h index 5396521a776a..b8aadffe6237 100644 --- a/include/linux/mroute.h +++ b/include/linux/mroute.h @@ -9,6 +9,7 @@ #include #include #include +#include #ifdef CONFIG_IP_MROUTE static inline int ip_mroute_opt(int opt) @@ -56,18 +57,6 @@ static inline bool ipmr_rule_default(const struct fib_rule *rule) } #endif -struct vif_device { - struct net_device *dev; /* Device we are using */ - struct netdev_phys_item_id dev_parent_id; /* Device parent ID */ - unsigned long bytes_in,bytes_out; - unsigned long pkt_in,pkt_out; /* Statistics */ - unsigned long rate_limit; /* Traffic shaping (NI) */ - unsigned char threshold; /* TTL threshold */ - unsigned short flags; /* Control flags */ - __be32 local,remote; /* Addresses(remote for tunnels)*/ - int link; /* Physical interface index */ -}; - struct vif_entry_notifier_info { struct fib_notifier_info info; struct net_device *dev; diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h index 3014c52bfd86..e5e5b8282551 100644 --- a/include/linux/mroute6.h +++ b/include/linux/mroute6.h @@ -7,6 +7,7 @@ #include /* for struct sk_buff_head */ #include #include +#include #ifdef CONFIG_IPV6_MROUTE static inline int ip6_mroute_opt(int opt) @@ -62,16 +63,6 @@ static inline void ip6_mr_cleanup(void) } #endif -struct mif_device { - struct net_device *dev; /* Device we are using */ - unsigned long bytes_in,bytes_out; - unsigned long pkt_in,pkt_out; /* Statistics */ - unsigned long rate_limit; /* Traffic shaping (NI) */ - unsigned char threshold; /* TTL threshold */ - unsigned short flags; /* Control flags */ - int link; /* Physical interface index */ -}; - #define VIFF_STATIC 0x8000 struct mfc6_cache { diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h new file mode 100644 index 000000000000..0de651e15f27 --- /dev/null +++ b/include/linux/mroute_base.h @@ -0,0 +1,52 @@ +#ifndef __LINUX_MROUTE_BASE_H +#define __LINUX_MROUTE_BASE_H + +#include + +/** + * struct vif_device - interface representor for multicast routing + * @dev: network device being used + * @bytes_in: statistic; bytes ingressing + * @bytes_out: statistic; bytes egresing + * @pkt_in: statistic; packets ingressing + * @pkt_out: statistic; packets egressing + * @rate_limit: Traffic shaping (NI) + * @threshold: TTL threshold + * @flags: Control flags + * @link: Physical interface index + * @dev_parent_id: device parent id + * @local: Local address + * @remote: Remote address for tunnels + */ +struct vif_device { + struct net_device *dev; + unsigned long bytes_in, bytes_out; + unsigned long pkt_in, pkt_out; + unsigned long rate_limit; + unsigned char threshold; + unsigned short flags; + int link; + + /* Currently only used by ipmr */ + struct netdev_phys_item_id dev_parent_id; + __be32 local, remote; +}; + +#ifdef CONFIG_IP_MROUTE_COMMON +void vif_device_init(struct vif_device *v, + struct net_device *dev, + unsigned long rate_limit, + unsigned char threshold, + unsigned short flags, + unsigned short get_iflink_mask); +#else +static inline void vif_device_init(struct vif_device *v, + struct net_device *dev, + unsigned long rate_limit, + unsigned char threshold, + unsigned short flags, + unsigned short get_iflink_mask) +{ +} +#endif +#endif diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig index f48fe6fc7e8c..80dad301361d 100644 --- a/net/ipv4/Kconfig +++ b/net/ipv4/Kconfig @@ -212,9 +212,14 @@ config NET_IPGRE_BROADCAST Network), but can be distributed all over the Internet. If you want to do that, say Y here and to "IP multicast routing" below. +config IP_MROUTE_COMMON + bool + depends on IP_MROUTE || IPV6_MROUTE + config IP_MROUTE bool "IP: multicast routing" depends on IP_MULTICAST + select IP_MROUTE_COMMON help This is used if you want your machine to act as a router for IP packets that have several destination addresses. It is needed on the diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile index 47a0a6649a9d..a07b7dd06def 100644 --- a/net/ipv4/Makefile +++ b/net/ipv4/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o obj-$(CONFIG_IP_MROUTE) += ipmr.o +obj-$(CONFIG_IP_MROUTE_COMMON) += ipmr_base.o obj-$(CONFIG_NET_IPIP) += ipip.o gre-y := gre_demux.o obj-$(CONFIG_NET_FOU) += fou.o diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 591d1fc80a1f..1370edad64bf 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -945,6 +945,10 @@ static int vif_add(struct net *net, struct mr_table *mrt, ip_rt_multicast_event(in_dev); /* Fill in the VIF structures */ + vif_device_init(v, dev, vifc->vifc_rate_limit, + vifc->vifc_threshold, + vifc->vifc_flags | (!mrtsock ? VIFF_STATIC : 0), + (VIFF_TUNNEL | VIFF_REGISTER)); attr.orig_dev = dev; if (!switchdev_port_attr_get(dev, &attr)) { @@ -953,20 +957,9 @@ static int vif_add(struct net *net, struct mr_table *mrt, } else { v->dev_parent_id.id_len = 0; } - v->rate_limit = vifc->vifc_rate_limit; + v->local = vifc->vifc_lcl_addr.s_addr; v->remote = vifc->vifc_rmt_addr.s_addr; - v->flags = vifc->vifc_flags; - if (!mrtsock) - v->flags |= VIFF_STATIC; - v->threshold = vifc->vifc_threshold; - v->bytes_in = 0; - v->bytes_out = 0; - v->pkt_in = 0; - v->pkt_out = 0; - v->link = dev->ifindex; - if (v->flags & (VIFF_TUNNEL | VIFF_REGISTER)) - v->link = dev_get_iflink(dev); /* And finish update writing critical data */ write_lock_bh(&mrt_lock); @@ -2316,7 +2309,8 @@ static int __ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, } if (VIF_EXISTS(mrt, c->mfc_parent) && - nla_put_u32(skb, RTA_IIF, mrt->vif_table[c->mfc_parent].dev->ifindex) < 0) + nla_put_u32(skb, RTA_IIF, + mrt->vif_table[c->mfc_parent].dev->ifindex) < 0) return -EMSGSIZE; if (c->mfc_flags & MFC_OFFLOAD) @@ -2327,6 +2321,8 @@ static int __ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, for (ct = c->mfc_un.res.minvif; ct < c->mfc_un.res.maxvif; ct++) { if (VIF_EXISTS(mrt, ct) && c->mfc_un.res.ttls[ct] < 255) { + struct vif_device *vif; + if (!(nhp = nla_reserve_nohdr(skb, sizeof(*nhp)))) { nla_nest_cancel(skb, mp_attr); return -EMSGSIZE; @@ -2334,7 +2330,8 @@ static int __ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, nhp->rtnh_flags = 0; nhp->rtnh_hops = c->mfc_un.res.ttls[ct]; - nhp->rtnh_ifindex = mrt->vif_table[ct].dev->ifindex; + vif = &mrt->vif_table[ct]; + nhp->rtnh_ifindex = vif->dev->ifindex; nhp->rtnh_len = sizeof(*nhp); } } @@ -2954,8 +2951,8 @@ struct ipmr_vif_iter { }; static struct vif_device *ipmr_vif_seq_idx(struct net *net, - struct ipmr_vif_iter *iter, - loff_t pos) + struct ipmr_vif_iter *iter, + loff_t pos) { struct mr_table *mrt = iter->mrt; @@ -3020,7 +3017,8 @@ static int ipmr_vif_seq_show(struct seq_file *seq, void *v) "Interface BytesIn PktsIn BytesOut PktsOut Flags Local Remote\n"); } else { const struct vif_device *vif = v; - const char *name = vif->dev ? vif->dev->name : "none"; + const char *name = vif->dev ? + vif->dev->name : "none"; seq_printf(seq, "%2td %-10s %8ld %7ld %8ld %7ld %05X %08X %08X\n", diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c new file mode 100644 index 000000000000..22758f848344 --- /dev/null +++ b/net/ipv4/ipmr_base.c @@ -0,0 +1,28 @@ +/* Linux multicast routing support + * Common logic shared by IPv4 [ipmr] and IPv6 [ip6mr] implementation + */ + +#include + +/* Sets everything common except 'dev', since that is done under locking */ +void vif_device_init(struct vif_device *v, + struct net_device *dev, + unsigned long rate_limit, + unsigned char threshold, + unsigned short flags, + unsigned short get_iflink_mask) +{ + v->dev = NULL; + v->bytes_in = 0; + v->bytes_out = 0; + v->pkt_in = 0; + v->pkt_out = 0; + v->rate_limit = rate_limit; + v->flags = flags; + v->threshold = threshold; + if (v->flags & get_iflink_mask) + v->link = dev_get_iflink(dev); + else + v->link = dev->ifindex; +} +EXPORT_SYMBOL(vif_device_init); diff --git a/net/ipv6/Kconfig b/net/ipv6/Kconfig index ea71e4b0ab7a..6794ddf0547c 100644 --- a/net/ipv6/Kconfig +++ b/net/ipv6/Kconfig @@ -278,6 +278,7 @@ config IPV6_SUBTREES config IPV6_MROUTE bool "IPv6: multicast routing" depends on IPV6 + select IP_MROUTE_COMMON ---help--- Experimental support for IPv6 multicast forwarding. If unsure, say N. diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index 295eb5ecaee5..e397990f6eb8 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -62,7 +62,7 @@ struct mr6_table { struct timer_list ipmr_expire_timer; struct list_head mfc6_unres_queue; struct list_head mfc6_cache_array[MFC6_LINES]; - struct mif_device vif6_table[MAXMIFS]; + struct vif_device vif6_table[MAXMIFS]; int maxvif; atomic_t cache_resolve_queue_len; bool mroute_do_assert; @@ -384,7 +384,7 @@ struct ipmr_vif_iter { int ct; }; -static struct mif_device *ip6mr_vif_seq_idx(struct net *net, +static struct vif_device *ip6mr_vif_seq_idx(struct net *net, struct ipmr_vif_iter *iter, loff_t pos) { @@ -450,7 +450,7 @@ static int ip6mr_vif_seq_show(struct seq_file *seq, void *v) seq_puts(seq, "Interface BytesIn PktsIn BytesOut PktsOut Flags\n"); } else { - const struct mif_device *vif = v; + const struct vif_device *vif = v; const char *name = vif->dev ? vif->dev->name : "none"; seq_printf(seq, @@ -776,7 +776,7 @@ failure: static int mif6_delete(struct mr6_table *mrt, int vifi, int notify, struct list_head *head) { - struct mif_device *v; + struct vif_device *v; struct net_device *dev; struct inet6_dev *in6_dev; @@ -929,7 +929,7 @@ static int mif6_add(struct net *net, struct mr6_table *mrt, struct mif6ctl *vifc, int mrtsock) { int vifi = vifc->mif6c_mifi; - struct mif_device *v = &mrt->vif6_table[vifi]; + struct vif_device *v = &mrt->vif6_table[vifi]; struct net_device *dev; struct inet6_dev *in6_dev; int err; @@ -980,21 +980,10 @@ static int mif6_add(struct net *net, struct mr6_table *mrt, dev->ifindex, &in6_dev->cnf); } - /* - * Fill in the VIF structures - */ - v->rate_limit = vifc->vifc_rate_limit; - v->flags = vifc->mif6c_flags; - if (!mrtsock) - v->flags |= VIFF_STATIC; - v->threshold = vifc->vifc_threshold; - v->bytes_in = 0; - v->bytes_out = 0; - v->pkt_in = 0; - v->pkt_out = 0; - v->link = dev->ifindex; - if (v->flags & MIFF_REGISTER) - v->link = dev_get_iflink(dev); + /* Fill in the VIF structures */ + vif_device_init(v, dev, vifc->vifc_rate_limit, vifc->vifc_threshold, + vifc->mif6c_flags | (!mrtsock ? VIFF_STATIC : 0), + MIFF_REGISTER); /* And finish update writing critical data */ write_lock_bh(&mrt_lock); @@ -1332,7 +1321,7 @@ static int ip6mr_device_event(struct notifier_block *this, struct net_device *dev = netdev_notifier_info_to_dev(ptr); struct net *net = dev_net(dev); struct mr6_table *mrt; - struct mif_device *v; + struct vif_device *v; int ct; if (event != NETDEV_UNREGISTER) @@ -1873,7 +1862,7 @@ int ip6mr_ioctl(struct sock *sk, int cmd, void __user *arg) { struct sioc_sg_req6 sr; struct sioc_mif_req6 vr; - struct mif_device *vif; + struct vif_device *vif; struct mfc6_cache *c; struct net *net = sock_net(sk); struct mr6_table *mrt; @@ -1947,7 +1936,7 @@ int ip6mr_compat_ioctl(struct sock *sk, unsigned int cmd, void __user *arg) { struct compat_sioc_sg_req6 sr; struct compat_sioc_mif_req6 vr; - struct mif_device *vif; + struct vif_device *vif; struct mfc6_cache *c; struct net *net = sock_net(sk); struct mr6_table *mrt; @@ -2018,7 +2007,7 @@ static int ip6mr_forward2(struct net *net, struct mr6_table *mrt, struct sk_buff *skb, struct mfc6_cache *c, int vifi) { struct ipv6hdr *ipv6h; - struct mif_device *vif = &mrt->vif6_table[vifi]; + struct vif_device *vif = &mrt->vif6_table[vifi]; struct net_device *dev; struct dst_entry *dst; struct flowi6 fl6; -- cgit v1.2.3 From 8571ab479a6e1ef46ead5ebee567e128a422767c Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:30 +0200 Subject: ip6mr: Make mroute_sk rcu-based In ipmr the mr_table socket is handled under RCU. Introduce the same for ip6mr. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute6.h | 6 +++--- net/ipv6/ip6_output.c | 2 +- net/ipv6/ip6mr.c | 45 +++++++++++++++++++++++++++------------------ 3 files changed, 31 insertions(+), 22 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h index e5e5b8282551..e1b9fb06e1ea 100644 --- a/include/linux/mroute6.h +++ b/include/linux/mroute6.h @@ -111,12 +111,12 @@ extern int ip6mr_get_route(struct net *net, struct sk_buff *skb, struct rtmsg *rtm, u32 portid); #ifdef CONFIG_IPV6_MROUTE -extern struct sock *mroute6_socket(struct net *net, struct sk_buff *skb); +bool mroute6_is_socket(struct net *net, struct sk_buff *skb); extern int ip6mr_sk_done(struct sock *sk); #else -static inline struct sock *mroute6_socket(struct net *net, struct sk_buff *skb) +static inline bool mroute6_is_socket(struct net *net, struct sk_buff *skb) { - return NULL; + return false; } static inline int ip6mr_sk_done(struct sock *sk) { diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index 997c7f19ad62..a6eb0e699b15 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -71,7 +71,7 @@ static int ip6_finish_output2(struct net *net, struct sock *sk, struct sk_buff * struct inet6_dev *idev = ip6_dst_idev(skb_dst(skb)); if (!(dev->flags & IFF_LOOPBACK) && sk_mc_loop(sk) && - ((mroute6_socket(net, skb) && + ((mroute6_is_socket(net, skb) && !(IP6CB(skb)->flags & IP6SKB_FORWARDED)) || ipv6_chk_mcast_addr(dev, &ipv6_hdr(skb)->daddr, &ipv6_hdr(skb)->saddr))) { diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index e397990f6eb8..a0e297ddca6e 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -58,7 +58,7 @@ struct mr6_table { struct list_head list; possible_net_t net; u32 id; - struct sock *mroute6_sk; + struct sock __rcu *mroute6_sk; struct timer_list ipmr_expire_timer; struct list_head mfc6_unres_queue; struct list_head mfc6_cache_array[MFC6_LINES]; @@ -1121,6 +1121,7 @@ static void ip6mr_cache_resolve(struct net *net, struct mr6_table *mrt, static int ip6mr_cache_report(struct mr6_table *mrt, struct sk_buff *pkt, mifi_t mifi, int assert) { + struct sock *mroute6_sk; struct sk_buff *skb; struct mrt6msg *msg; int ret; @@ -1190,17 +1191,19 @@ static int ip6mr_cache_report(struct mr6_table *mrt, struct sk_buff *pkt, skb->ip_summed = CHECKSUM_UNNECESSARY; } - if (!mrt->mroute6_sk) { + rcu_read_lock(); + mroute6_sk = rcu_dereference(mrt->mroute6_sk); + if (!mroute6_sk) { + rcu_read_unlock(); kfree_skb(skb); return -EINVAL; } mrt6msg_netlink_event(mrt, skb); - /* - * Deliver to user space multicast routing algorithms - */ - ret = sock_queue_rcv_skb(mrt->mroute6_sk, skb); + /* Deliver to user space multicast routing algorithms */ + ret = sock_queue_rcv_skb(mroute6_sk, skb); + rcu_read_unlock(); if (ret < 0) { net_warn_ratelimited("mroute6: pending queue full, dropping entries\n"); kfree_skb(skb); @@ -1584,11 +1587,11 @@ static int ip6mr_sk_init(struct mr6_table *mrt, struct sock *sk) rtnl_lock(); write_lock_bh(&mrt_lock); - if (likely(mrt->mroute6_sk == NULL)) { - mrt->mroute6_sk = sk; - net->ipv6.devconf_all->mc_forwarding++; - } else { + if (rtnl_dereference(mrt->mroute6_sk)) { err = -EADDRINUSE; + } else { + rcu_assign_pointer(mrt->mroute6_sk, sk); + net->ipv6.devconf_all->mc_forwarding++; } write_unlock_bh(&mrt_lock); @@ -1614,9 +1617,9 @@ int ip6mr_sk_done(struct sock *sk) rtnl_lock(); ip6mr_for_each_table(mrt, net) { - if (sk == mrt->mroute6_sk) { + if (sk == rtnl_dereference(mrt->mroute6_sk)) { write_lock_bh(&mrt_lock); - mrt->mroute6_sk = NULL; + RCU_INIT_POINTER(mrt->mroute6_sk, NULL); net->ipv6.devconf_all->mc_forwarding--; write_unlock_bh(&mrt_lock); inet6_netconf_notify_devconf(net, RTM_NEWNETCONF, @@ -1630,11 +1633,12 @@ int ip6mr_sk_done(struct sock *sk) } } rtnl_unlock(); + synchronize_rcu(); return err; } -struct sock *mroute6_socket(struct net *net, struct sk_buff *skb) +bool mroute6_is_socket(struct net *net, struct sk_buff *skb) { struct mr6_table *mrt; struct flowi6 fl6 = { @@ -1646,8 +1650,9 @@ struct sock *mroute6_socket(struct net *net, struct sk_buff *skb) if (ip6mr_fib_lookup(net, &fl6, &mrt) < 0) return NULL; - return mrt->mroute6_sk; + return rcu_access_pointer(mrt->mroute6_sk); } +EXPORT_SYMBOL(mroute6_is_socket); /* * Socket options and virtual interface manipulation. The whole @@ -1674,7 +1679,8 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns return -ENOENT; if (optname != MRT6_INIT) { - if (sk != mrt->mroute6_sk && !ns_capable(net->user_ns, CAP_NET_ADMIN)) + if (sk != rcu_access_pointer(mrt->mroute6_sk) && + !ns_capable(net->user_ns, CAP_NET_ADMIN)) return -EACCES; } @@ -1696,7 +1702,8 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns if (vif.mif6c_mifi >= MAXMIFS) return -ENFILE; rtnl_lock(); - ret = mif6_add(net, mrt, &vif, sk == mrt->mroute6_sk); + ret = mif6_add(net, mrt, &vif, + sk == rtnl_dereference(mrt->mroute6_sk)); rtnl_unlock(); return ret; @@ -1731,7 +1738,9 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns ret = ip6mr_mfc_delete(mrt, &mfc, parent); else ret = ip6mr_mfc_add(net, mrt, &mfc, - sk == mrt->mroute6_sk, parent); + sk == + rtnl_dereference(mrt->mroute6_sk), + parent); rtnl_unlock(); return ret; @@ -1783,7 +1792,7 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns /* "pim6reg%u" should not exceed 16 bytes (IFNAMSIZ) */ if (v != RT_TABLE_DEFAULT && v >= 100000000) return -EINVAL; - if (sk == mrt->mroute6_sk) + if (sk == rcu_access_pointer(mrt->mroute6_sk)) return -EBUSY; rtnl_lock(); -- cgit v1.2.3 From 87c418bf1323d57140f4b448715f64de3fbb7e91 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:31 +0200 Subject: ip6mr: Align hash implementation to ipmr Since commit 8fb472c09b9d ("ipmr: improve hash scalability") ipmr has been using rhashtable as a basis for its mfc routes, but ip6mr is currently still using the old private MFC hash implementation. Align ip6mr to the current ipmr implementation. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute6.h | 30 ++--- net/ipv6/ip6mr.c | 313 ++++++++++++++++++++++++++---------------------- 2 files changed, 184 insertions(+), 159 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h index e1b9fb06e1ea..e2dac199861e 100644 --- a/include/linux/mroute6.h +++ b/include/linux/mroute6.h @@ -8,6 +8,7 @@ #include #include #include +#include #ifdef CONFIG_IPV6_MROUTE static inline int ip6_mroute_opt(int opt) @@ -65,10 +66,20 @@ static inline void ip6_mr_cleanup(void) #define VIFF_STATIC 0x8000 +struct mfc6_cache_cmp_arg { + struct in6_addr mf6c_mcastgrp; + struct in6_addr mf6c_origin; +}; + struct mfc6_cache { - struct list_head list; - struct in6_addr mf6c_mcastgrp; /* Group the entry belongs to */ - struct in6_addr mf6c_origin; /* Source of packet */ + struct rhlist_head mnode; + union { + struct { + struct in6_addr mf6c_mcastgrp; + struct in6_addr mf6c_origin; + }; + struct mfc6_cache_cmp_arg cmparg; + }; mifi_t mf6c_parent; /* Source interface */ int mfc_flags; /* Flags on line */ @@ -88,22 +99,13 @@ struct mfc6_cache { unsigned char ttls[MAXMIFS]; /* TTL thresholds */ } res; } mfc_un; + struct list_head list; + struct rcu_head rcu; }; #define MFC_STATIC 1 #define MFC_NOTIFY 2 -#define MFC6_LINES 64 - -#define MFC6_HASH(a, g) (((__force u32)(a)->s6_addr32[0] ^ \ - (__force u32)(a)->s6_addr32[1] ^ \ - (__force u32)(a)->s6_addr32[2] ^ \ - (__force u32)(a)->s6_addr32[3] ^ \ - (__force u32)(g)->s6_addr32[0] ^ \ - (__force u32)(g)->s6_addr32[1] ^ \ - (__force u32)(g)->s6_addr32[2] ^ \ - (__force u32)(g)->s6_addr32[3]) % MFC6_LINES) - #define MFC_ASSERT_THRESH (3*HZ) /* Maximal freq. of asserts */ struct rtmsg; diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index a0e297ddca6e..6f0b7f4894b2 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -61,8 +61,9 @@ struct mr6_table { struct sock __rcu *mroute6_sk; struct timer_list ipmr_expire_timer; struct list_head mfc6_unres_queue; - struct list_head mfc6_cache_array[MFC6_LINES]; struct vif_device vif6_table[MAXMIFS]; + struct rhltable mfc6_hash; + struct list_head mfc6_cache_list; int maxvif; atomic_t cache_resolve_queue_len; bool mroute_do_assert; @@ -299,10 +300,29 @@ static void __net_exit ip6mr_rules_exit(struct net *net) } #endif +static int ip6mr_hash_cmp(struct rhashtable_compare_arg *arg, + const void *ptr) +{ + const struct mfc6_cache_cmp_arg *cmparg = arg->key; + struct mfc6_cache *c = (struct mfc6_cache *)ptr; + + return !ipv6_addr_equal(&c->mf6c_mcastgrp, &cmparg->mf6c_mcastgrp) || + !ipv6_addr_equal(&c->mf6c_origin, &cmparg->mf6c_origin); +} + +static const struct rhashtable_params ip6mr_rht_params = { + .head_offset = offsetof(struct mfc6_cache, mnode), + .key_offset = offsetof(struct mfc6_cache, cmparg), + .key_len = sizeof(struct mfc6_cache_cmp_arg), + .nelem_hint = 3, + .locks_mul = 1, + .obj_cmpfn = ip6mr_hash_cmp, + .automatic_shrinking = true, +}; + static struct mr6_table *ip6mr_new_table(struct net *net, u32 id) { struct mr6_table *mrt; - unsigned int i; mrt = ip6mr_get_table(net, id); if (mrt) @@ -314,10 +334,8 @@ static struct mr6_table *ip6mr_new_table(struct net *net, u32 id) mrt->id = id; write_pnet(&mrt->net, net); - /* Forwarding cache */ - for (i = 0; i < MFC6_LINES; i++) - INIT_LIST_HEAD(&mrt->mfc6_cache_array[i]); - + rhltable_init(&mrt->mfc6_hash, &ip6mr_rht_params); + INIT_LIST_HEAD(&mrt->mfc6_cache_list); INIT_LIST_HEAD(&mrt->mfc6_unres_queue); timer_setup(&mrt->ipmr_expire_timer, ipmr_expire_process, 0); @@ -335,6 +353,7 @@ static void ip6mr_free_table(struct mr6_table *mrt) { del_timer_sync(&mrt->ipmr_expire_timer); mroute_clean_tables(mrt, true); + rhltable_destroy(&mrt->mfc6_hash); kfree(mrt); } @@ -344,7 +363,6 @@ struct ipmr_mfc_iter { struct seq_net_private p; struct mr6_table *mrt; struct list_head *cache; - int ct; }; @@ -354,14 +372,12 @@ static struct mfc6_cache *ipmr_mfc_seq_idx(struct net *net, struct mr6_table *mrt = it->mrt; struct mfc6_cache *mfc; - read_lock(&mrt_lock); - for (it->ct = 0; it->ct < MFC6_LINES; it->ct++) { - it->cache = &mrt->mfc6_cache_array[it->ct]; - list_for_each_entry(mfc, it->cache, list) - if (pos-- == 0) - return mfc; - } - read_unlock(&mrt_lock); + rcu_read_lock(); + it->cache = &mrt->mfc6_cache_list; + list_for_each_entry_rcu(mfc, &mrt->mfc6_cache_list, list) + if (pos-- == 0) + return mfc; + rcu_read_unlock(); spin_lock_bh(&mfc_unres_lock); it->cache = &mrt->mfc6_unres_queue; @@ -517,19 +533,9 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) if (it->cache == &mrt->mfc6_unres_queue) goto end_of_list; - BUG_ON(it->cache != &mrt->mfc6_cache_array[it->ct]); - - while (++it->ct < MFC6_LINES) { - it->cache = &mrt->mfc6_cache_array[it->ct]; - if (list_empty(it->cache)) - continue; - return list_first_entry(it->cache, struct mfc6_cache, list); - } - /* exhausted cache_array, show unresolved */ - read_unlock(&mrt_lock); + rcu_read_unlock(); it->cache = &mrt->mfc6_unres_queue; - it->ct = 0; spin_lock_bh(&mfc_unres_lock); if (!list_empty(it->cache)) @@ -549,8 +555,8 @@ static void ipmr_mfc_seq_stop(struct seq_file *seq, void *v) if (it->cache == &mrt->mfc6_unres_queue) spin_unlock_bh(&mfc_unres_lock); - else if (it->cache == &mrt->mfc6_cache_array[it->ct]) - read_unlock(&mrt_lock); + else if (it->cache == &mrt->mfc6_cache_list) + rcu_read_unlock(); } static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) @@ -827,11 +833,18 @@ static int mif6_delete(struct mr6_table *mrt, int vifi, int notify, return 0; } -static inline void ip6mr_cache_free(struct mfc6_cache *c) +static inline void ip6mr_cache_free_rcu(struct rcu_head *head) { + struct mfc6_cache *c = container_of(head, struct mfc6_cache, rcu); + kmem_cache_free(mrt_cachep, c); } +static inline void ip6mr_cache_free(struct mfc6_cache *c) +{ + call_rcu(&c->rcu, ip6mr_cache_free_rcu); +} + /* Destroy an unresolved cache entry, killing queued skbs and reporting error to netlink readers. */ @@ -1002,14 +1015,17 @@ static struct mfc6_cache *ip6mr_cache_find(struct mr6_table *mrt, const struct in6_addr *origin, const struct in6_addr *mcastgrp) { - int line = MFC6_HASH(mcastgrp, origin); + struct mfc6_cache_cmp_arg arg = { + .mf6c_origin = *origin, + .mf6c_mcastgrp = *mcastgrp, + }; + struct rhlist_head *tmp, *list; struct mfc6_cache *c; - list_for_each_entry(c, &mrt->mfc6_cache_array[line], list) { - if (ipv6_addr_equal(&c->mf6c_origin, origin) && - ipv6_addr_equal(&c->mf6c_mcastgrp, mcastgrp)) - return c; - } + list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + rhl_for_each_entry_rcu(c, tmp, list, mnode) + return c; + return NULL; } @@ -1017,13 +1033,16 @@ static struct mfc6_cache *ip6mr_cache_find(struct mr6_table *mrt, static struct mfc6_cache *ip6mr_cache_find_any_parent(struct mr6_table *mrt, mifi_t mifi) { - int line = MFC6_HASH(&in6addr_any, &in6addr_any); + struct mfc6_cache_cmp_arg arg = { + .mf6c_origin = in6addr_any, + .mf6c_mcastgrp = in6addr_any, + }; + struct rhlist_head *tmp, *list; struct mfc6_cache *c; - list_for_each_entry(c, &mrt->mfc6_cache_array[line], list) - if (ipv6_addr_any(&c->mf6c_origin) && - ipv6_addr_any(&c->mf6c_mcastgrp) && - (c->mfc_un.res.ttls[mifi] < 255)) + list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + rhl_for_each_entry_rcu(c, tmp, list, mnode) + if (c->mfc_un.res.ttls[mifi] < 255) return c; return NULL; @@ -1034,29 +1053,53 @@ static struct mfc6_cache *ip6mr_cache_find_any(struct mr6_table *mrt, struct in6_addr *mcastgrp, mifi_t mifi) { - int line = MFC6_HASH(mcastgrp, &in6addr_any); + struct mfc6_cache_cmp_arg arg = { + .mf6c_origin = in6addr_any, + .mf6c_mcastgrp = *mcastgrp, + }; + struct rhlist_head *tmp, *list; struct mfc6_cache *c, *proxy; if (ipv6_addr_any(mcastgrp)) goto skip; - list_for_each_entry(c, &mrt->mfc6_cache_array[line], list) - if (ipv6_addr_any(&c->mf6c_origin) && - ipv6_addr_equal(&c->mf6c_mcastgrp, mcastgrp)) { - if (c->mfc_un.res.ttls[mifi] < 255) - return c; - - /* It's ok if the mifi is part of the static tree */ - proxy = ip6mr_cache_find_any_parent(mrt, - c->mf6c_parent); - if (proxy && proxy->mfc_un.res.ttls[mifi] < 255) - return c; - } + list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + rhl_for_each_entry_rcu(c, tmp, list, mnode) { + if (c->mfc_un.res.ttls[mifi] < 255) + return c; + + /* It's ok if the mifi is part of the static tree */ + proxy = ip6mr_cache_find_any_parent(mrt, c->mf6c_parent); + if (proxy && proxy->mfc_un.res.ttls[mifi] < 255) + return c; + } skip: return ip6mr_cache_find_any_parent(mrt, mifi); } +/* Look for a (S,G,iif) entry if parent != -1 */ +static struct mfc6_cache * +ip6mr_cache_find_parent(struct mr6_table *mrt, + const struct in6_addr *origin, + const struct in6_addr *mcastgrp, + int parent) +{ + struct mfc6_cache_cmp_arg arg = { + .mf6c_origin = *origin, + .mf6c_mcastgrp = *mcastgrp, + }; + struct rhlist_head *tmp, *list; + struct mfc6_cache *c; + + list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + rhl_for_each_entry_rcu(c, tmp, list, mnode) + if (parent == -1 || parent == c->mf6c_parent) + return c; + + return NULL; +} + /* * Allocate a multicast cache entry */ @@ -1296,26 +1339,21 @@ ip6mr_cache_unresolved(struct mr6_table *mrt, mifi_t mifi, struct sk_buff *skb) static int ip6mr_mfc_delete(struct mr6_table *mrt, struct mf6cctl *mfc, int parent) { - int line; - struct mfc6_cache *c, *next; - - line = MFC6_HASH(&mfc->mf6cc_mcastgrp.sin6_addr, &mfc->mf6cc_origin.sin6_addr); + struct mfc6_cache *c; - list_for_each_entry_safe(c, next, &mrt->mfc6_cache_array[line], list) { - if (ipv6_addr_equal(&c->mf6c_origin, &mfc->mf6cc_origin.sin6_addr) && - ipv6_addr_equal(&c->mf6c_mcastgrp, - &mfc->mf6cc_mcastgrp.sin6_addr) && - (parent == -1 || parent == c->mf6c_parent)) { - write_lock_bh(&mrt_lock); - list_del(&c->list); - write_unlock_bh(&mrt_lock); + /* The entries are added/deleted only under RTNL */ + rcu_read_lock(); + c = ip6mr_cache_find_parent(mrt, &mfc->mf6cc_origin.sin6_addr, + &mfc->mf6cc_mcastgrp.sin6_addr, parent); + rcu_read_unlock(); + if (!c) + return -ENOENT; + rhltable_remove(&mrt->mfc6_hash, &c->mnode, ip6mr_rht_params); + list_del_rcu(&c->list); - mr6_netlink_event(mrt, c, RTM_DELROUTE); - ip6mr_cache_free(c); - return 0; - } - } - return -ENOENT; + mr6_netlink_event(mrt, c, RTM_DELROUTE); + ip6mr_cache_free(c); + return 0; } static int ip6mr_device_event(struct notifier_block *this, @@ -1448,11 +1486,10 @@ void ip6_mr_cleanup(void) static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, struct mf6cctl *mfc, int mrtsock, int parent) { - bool found = false; - int line; - struct mfc6_cache *uc, *c; unsigned char ttls[MAXMIFS]; - int i; + struct mfc6_cache *uc, *c; + bool found; + int i, err; if (mfc->mf6cc_parent >= MAXMIFS) return -ENFILE; @@ -1461,22 +1498,14 @@ static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, for (i = 0; i < MAXMIFS; i++) { if (IF_ISSET(i, &mfc->mf6cc_ifset)) ttls[i] = 1; - - } - - line = MFC6_HASH(&mfc->mf6cc_mcastgrp.sin6_addr, &mfc->mf6cc_origin.sin6_addr); - - list_for_each_entry(c, &mrt->mfc6_cache_array[line], list) { - if (ipv6_addr_equal(&c->mf6c_origin, &mfc->mf6cc_origin.sin6_addr) && - ipv6_addr_equal(&c->mf6c_mcastgrp, - &mfc->mf6cc_mcastgrp.sin6_addr) && - (parent == -1 || parent == mfc->mf6cc_parent)) { - found = true; - break; - } } - if (found) { + /* The entries are added/deleted only under RTNL */ + rcu_read_lock(); + c = ip6mr_cache_find_parent(mrt, &mfc->mf6cc_origin.sin6_addr, + &mfc->mf6cc_mcastgrp.sin6_addr, parent); + rcu_read_unlock(); + if (c) { write_lock_bh(&mrt_lock); c->mf6c_parent = mfc->mf6cc_parent; ip6mr_update_thresholds(mrt, c, ttls); @@ -1502,13 +1531,17 @@ static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, if (!mrtsock) c->mfc_flags |= MFC_STATIC; - write_lock_bh(&mrt_lock); - list_add(&c->list, &mrt->mfc6_cache_array[line]); - write_unlock_bh(&mrt_lock); + err = rhltable_insert_key(&mrt->mfc6_hash, &c->cmparg, &c->mnode, + ip6mr_rht_params); + if (err) { + pr_err("ip6mr: rhtable insert error %d\n", err); + ip6mr_cache_free(c); + return err; + } + list_add_tail_rcu(&c->list, &mrt->mfc6_cache_list); - /* - * Check to see if we resolved a queued list. If so we - * need to send on the frames and tidy up. + /* Check to see if we resolved a queued list. If so we + * need to send on the frames and tidy up. */ found = false; spin_lock_bh(&mfc_unres_lock); @@ -1539,13 +1572,11 @@ static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, static void mroute_clean_tables(struct mr6_table *mrt, bool all) { - int i; + struct mfc6_cache *c, *tmp; LIST_HEAD(list); - struct mfc6_cache *c, *next; + int i; - /* - * Shut down all active vif entries - */ + /* Shut down all active vif entries */ for (i = 0; i < mrt->maxvif; i++) { if (!all && (mrt->vif6_table[i].flags & VIFF_STATIC)) continue; @@ -1553,25 +1584,19 @@ static void mroute_clean_tables(struct mr6_table *mrt, bool all) } unregister_netdevice_many(&list); - /* - * Wipe the cache - */ - for (i = 0; i < MFC6_LINES; i++) { - list_for_each_entry_safe(c, next, &mrt->mfc6_cache_array[i], list) { - if (!all && (c->mfc_flags & MFC_STATIC)) - continue; - write_lock_bh(&mrt_lock); - list_del(&c->list); - write_unlock_bh(&mrt_lock); - - mr6_netlink_event(mrt, c, RTM_DELROUTE); - ip6mr_cache_free(c); - } + /* Wipe the cache */ + list_for_each_entry_safe(c, tmp, &mrt->mfc6_cache_list, list) { + if (!all && (c->mfc_flags & MFC_STATIC)) + continue; + rhltable_remove(&mrt->mfc6_hash, &c->mnode, ip6mr_rht_params); + list_del_rcu(&c->list); + mr6_netlink_event(mrt, c, RTM_DELROUTE); + ip6mr_cache_free(c); } if (atomic_read(&mrt->cache_resolve_queue_len) != 0) { spin_lock_bh(&mfc_unres_lock); - list_for_each_entry_safe(c, next, &mrt->mfc6_unres_queue, list) { + list_for_each_entry_safe(c, tmp, &mrt->mfc6_unres_queue, list) { list_del(&c->list); mr6_netlink_event(mrt, c, RTM_DELROUTE); ip6mr_destroy_unres(mrt, c); @@ -1905,19 +1930,19 @@ int ip6mr_ioctl(struct sock *sk, int cmd, void __user *arg) if (copy_from_user(&sr, arg, sizeof(sr))) return -EFAULT; - read_lock(&mrt_lock); + rcu_read_lock(); c = ip6mr_cache_find(mrt, &sr.src.sin6_addr, &sr.grp.sin6_addr); if (c) { sr.pktcnt = c->mfc_un.res.pkt; sr.bytecnt = c->mfc_un.res.bytes; sr.wrong_if = c->mfc_un.res.wrong_if; - read_unlock(&mrt_lock); + rcu_read_unlock(); if (copy_to_user(arg, &sr, sizeof(sr))) return -EFAULT; return 0; } - read_unlock(&mrt_lock); + rcu_read_unlock(); return -EADDRNOTAVAIL; default: return -ENOIOCTLCMD; @@ -1979,19 +2004,19 @@ int ip6mr_compat_ioctl(struct sock *sk, unsigned int cmd, void __user *arg) if (copy_from_user(&sr, arg, sizeof(sr))) return -EFAULT; - read_lock(&mrt_lock); + rcu_read_lock(); c = ip6mr_cache_find(mrt, &sr.src.sin6_addr, &sr.grp.sin6_addr); if (c) { sr.pktcnt = c->mfc_un.res.pkt; sr.bytecnt = c->mfc_un.res.bytes; sr.wrong_if = c->mfc_un.res.wrong_if; - read_unlock(&mrt_lock); + rcu_read_unlock(); if (copy_to_user(arg, &sr, sizeof(sr))) return -EFAULT; return 0; } - read_unlock(&mrt_lock); + rcu_read_unlock(); return -EADDRNOTAVAIL; default: return -ENOIOCTLCMD; @@ -2115,10 +2140,14 @@ static void ip6_mr_forward(struct net *net, struct mr6_table *mrt, /* For an (*,G) entry, we only check that the incoming * interface is part of the static tree. */ + rcu_read_lock(); cache_proxy = ip6mr_cache_find_any_parent(mrt, vif); if (cache_proxy && - cache_proxy->mfc_un.res.ttls[true_vifi] < 255) + cache_proxy->mfc_un.res.ttls[true_vifi] < 255) { + rcu_read_unlock(); goto forward; + } + rcu_read_unlock(); } /* @@ -2535,34 +2564,30 @@ static int ip6mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) struct mr6_table *mrt; struct mfc6_cache *mfc; unsigned int t = 0, s_t; - unsigned int h = 0, s_h; unsigned int e = 0, s_e; s_t = cb->args[0]; - s_h = cb->args[1]; - s_e = cb->args[2]; + s_e = cb->args[1]; - read_lock(&mrt_lock); + rcu_read_lock(); ip6mr_for_each_table(mrt, net) { if (t < s_t) goto next_table; - if (t > s_t) - s_h = 0; - for (h = s_h; h < MFC6_LINES; h++) { - list_for_each_entry(mfc, &mrt->mfc6_cache_array[h], list) { - if (e < s_e) - goto next_entry; - if (ip6mr_fill_mroute(mrt, skb, - NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, - mfc, RTM_NEWROUTE, - NLM_F_MULTI) < 0) - goto done; + list_for_each_entry_rcu(mfc, &mrt->mfc6_cache_list, list) { + if (e < s_e) + goto next_entry; + if (ip6mr_fill_mroute(mrt, skb, + NETLINK_CB(cb->skb).portid, + cb->nlh->nlmsg_seq, + mfc, RTM_NEWROUTE, + NLM_F_MULTI) < 0) + goto done; next_entry: - e++; - } - e = s_e = 0; + e++; } + e = 0; + s_e = 0; + spin_lock_bh(&mfc_unres_lock); list_for_each_entry(mfc, &mrt->mfc6_unres_queue, list) { if (e < s_e) @@ -2580,15 +2605,13 @@ next_entry2: } spin_unlock_bh(&mfc_unres_lock); e = s_e = 0; - s_h = 0; next_table: t++; } done: - read_unlock(&mrt_lock); + rcu_read_unlock(); - cb->args[2] = e; - cb->args[1] = h; + cb->args[1] = e; cb->args[0] = t; return skb->len; -- cgit v1.2.3 From b70432f7319eb75b24ca57dde8146c5e27244780 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:32 +0200 Subject: mroute*: Make mr_table a common struct Following previous changes to ip6mr, mr_table and mr6_table are basically the same [up to mr6_table having additional '6' suffixes to its variable names]. Move the common structure definition into a common header; This requires renaming all references in ip6mr to variables that had the distinct suffix. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute.h | 21 ---- include/linux/mroute6.h | 1 - include/linux/mroute_base.h | 46 +++++++ include/net/netns/ipv6.h | 2 +- net/ipv4/ipmr.c | 2 - net/ipv6/ip6mr.c | 301 ++++++++++++++++++++------------------------ 6 files changed, 186 insertions(+), 187 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute.h b/include/linux/mroute.h index b8aadffe6237..8688c5d03a24 100644 --- a/include/linux/mroute.h +++ b/include/linux/mroute.h @@ -4,8 +4,6 @@ #include #include -#include -#include #include #include #include @@ -67,25 +65,6 @@ struct vif_entry_notifier_info { #define VIFF_STATIC 0x8000 -#define VIF_EXISTS(_mrt, _idx) ((_mrt)->vif_table[_idx].dev != NULL) - -struct mr_table { - struct list_head list; - possible_net_t net; - u32 id; - struct sock __rcu *mroute_sk; - struct timer_list ipmr_expire_timer; - struct list_head mfc_unres_queue; - struct vif_device vif_table[MAXVIFS]; - struct rhltable mfc_hash; - struct list_head mfc_cache_list; - int maxvif; - atomic_t cache_resolve_queue_len; - bool mroute_do_assert; - bool mroute_do_pim; - int mroute_reg_vif_num; -}; - /* mfc_flags: * MFC_STATIC - the entry was added statically (not by a routing daemon) * MFC_OFFLOAD - the entry was offloaded to the hardware diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h index e2dac199861e..d5c8dc155a42 100644 --- a/include/linux/mroute6.h +++ b/include/linux/mroute6.h @@ -8,7 +8,6 @@ #include #include #include -#include #ifdef CONFIG_IPV6_MROUTE static inline int ip6_mroute_opt(int opt) diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 0de651e15f27..1cc944a14df5 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -2,6 +2,9 @@ #define __LINUX_MROUTE_BASE_H #include +#include +#include +#include /** * struct vif_device - interface representor for multicast routing @@ -32,6 +35,49 @@ struct vif_device { __be32 local, remote; }; +#ifndef MAXVIFS +/* This one is nasty; value is defined in uapi using different symbols for + * mroute and morute6 but both map into same 32. + */ +#define MAXVIFS 32 +#endif + +#define VIF_EXISTS(_mrt, _idx) (!!((_mrt)->vif_table[_idx].dev)) + +/** + * struct mr_table - a multicast routing table + * @list: entry within a list of multicast routing tables + * @net: net where this table belongs + * @id: identifier of the table + * @mroute_sk: socket associated with the table + * @ipmr_expire_timer: timer for handling unresolved routes + * @mfc_unres_queue: list of unresolved MFC entries + * @vif_table: array containing all possible vifs + * @mfc_hash: Hash table of all resolved routes for easy lookup + * @mfc_cache_list: list of resovled routes for possible traversal + * @maxvif: Identifier of highest value vif currently in use + * @cache_resolve_queue_len: current size of unresolved queue + * @mroute_do_assert: Whether to inform userspace on wrong ingress + * @mroute_do_pim: Whether to receive IGMP PIMv1 + * @mroute_reg_vif_num: PIM-device vif index + */ +struct mr_table { + struct list_head list; + possible_net_t net; + u32 id; + struct sock __rcu *mroute_sk; + struct timer_list ipmr_expire_timer; + struct list_head mfc_unres_queue; + struct vif_device vif_table[MAXVIFS]; + struct rhltable mfc_hash; + struct list_head mfc_cache_list; + int maxvif; + atomic_t cache_resolve_queue_len; + bool mroute_do_assert; + bool mroute_do_pim; + int mroute_reg_vif_num; +}; + #ifdef CONFIG_IP_MROUTE_COMMON void vif_device_init(struct vif_device *v, struct net_device *dev, diff --git a/include/net/netns/ipv6.h b/include/net/netns/ipv6.h index 2b9194229a56..e286fda09fcf 100644 --- a/include/net/netns/ipv6.h +++ b/include/net/netns/ipv6.h @@ -85,7 +85,7 @@ struct netns_ipv6 { struct sock *mc_autojoin_sk; #ifdef CONFIG_IPV6_MROUTE #ifndef CONFIG_IPV6_MROUTE_MULTIPLE_TABLES - struct mr6_table *mrt6; + struct mr_table *mrt6; #else struct list_head mr6_tables; struct fib_rules_ops *mr6_rules_ops; diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 1370edad64bf..a1bf0020cad1 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -53,7 +52,6 @@ #include #include #include -#include #include #include #include diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index 6f0b7f4894b2..adbb826ca8fd 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -36,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -54,31 +52,12 @@ #include #include -struct mr6_table { - struct list_head list; - possible_net_t net; - u32 id; - struct sock __rcu *mroute6_sk; - struct timer_list ipmr_expire_timer; - struct list_head mfc6_unres_queue; - struct vif_device vif6_table[MAXMIFS]; - struct rhltable mfc6_hash; - struct list_head mfc6_cache_list; - int maxvif; - atomic_t cache_resolve_queue_len; - bool mroute_do_assert; - bool mroute_do_pim; -#ifdef CONFIG_IPV6_PIMSM_V2 - int mroute_reg_vif_num; -#endif -}; - struct ip6mr_rule { struct fib_rule common; }; struct ip6mr_result { - struct mr6_table *mrt; + struct mr_table *mrt; }; /* Big lock, protecting vif table, mrt cache and mroute socket state. @@ -87,11 +66,7 @@ struct ip6mr_result { static DEFINE_RWLOCK(mrt_lock); -/* - * Multicast router control variables - */ - -#define MIF_EXISTS(_mrt, _idx) ((_mrt)->vif6_table[_idx].dev != NULL) +/* Multicast router control variables */ /* Special spinlock for queue of unresolved entries */ static DEFINE_SPINLOCK(mfc_unres_lock); @@ -106,30 +81,30 @@ static DEFINE_SPINLOCK(mfc_unres_lock); static struct kmem_cache *mrt_cachep __read_mostly; -static struct mr6_table *ip6mr_new_table(struct net *net, u32 id); -static void ip6mr_free_table(struct mr6_table *mrt); +static struct mr_table *ip6mr_new_table(struct net *net, u32 id); +static void ip6mr_free_table(struct mr_table *mrt); -static void ip6_mr_forward(struct net *net, struct mr6_table *mrt, +static void ip6_mr_forward(struct net *net, struct mr_table *mrt, struct sk_buff *skb, struct mfc6_cache *cache); -static int ip6mr_cache_report(struct mr6_table *mrt, struct sk_buff *pkt, +static int ip6mr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, mifi_t mifi, int assert); -static int __ip6mr_fill_mroute(struct mr6_table *mrt, struct sk_buff *skb, +static int __ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, struct mfc6_cache *c, struct rtmsg *rtm); -static void mr6_netlink_event(struct mr6_table *mrt, struct mfc6_cache *mfc, +static void mr6_netlink_event(struct mr_table *mrt, struct mfc6_cache *mfc, int cmd); -static void mrt6msg_netlink_event(struct mr6_table *mrt, struct sk_buff *pkt); +static void mrt6msg_netlink_event(struct mr_table *mrt, struct sk_buff *pkt); static int ip6mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb); -static void mroute_clean_tables(struct mr6_table *mrt, bool all); +static void mroute_clean_tables(struct mr_table *mrt, bool all); static void ipmr_expire_process(struct timer_list *t); #ifdef CONFIG_IPV6_MROUTE_MULTIPLE_TABLES #define ip6mr_for_each_table(mrt, net) \ list_for_each_entry_rcu(mrt, &net->ipv6.mr6_tables, list) -static struct mr6_table *ip6mr_get_table(struct net *net, u32 id) +static struct mr_table *ip6mr_get_table(struct net *net, u32 id) { - struct mr6_table *mrt; + struct mr_table *mrt; ip6mr_for_each_table(mrt, net) { if (mrt->id == id) @@ -139,7 +114,7 @@ static struct mr6_table *ip6mr_get_table(struct net *net, u32 id) } static int ip6mr_fib_lookup(struct net *net, struct flowi6 *flp6, - struct mr6_table **mrt) + struct mr_table **mrt) { int err; struct ip6mr_result res; @@ -160,7 +135,7 @@ static int ip6mr_rule_action(struct fib_rule *rule, struct flowi *flp, int flags, struct fib_lookup_arg *arg) { struct ip6mr_result *res = arg->result; - struct mr6_table *mrt; + struct mr_table *mrt; switch (rule->action) { case FR_ACT_TO_TBL: @@ -228,7 +203,7 @@ static const struct fib_rules_ops __net_initconst ip6mr_rules_ops_template = { static int __net_init ip6mr_rules_init(struct net *net) { struct fib_rules_ops *ops; - struct mr6_table *mrt; + struct mr_table *mrt; int err; ops = fib_rules_register(&ip6mr_rules_ops_template, net); @@ -259,7 +234,7 @@ err1: static void __net_exit ip6mr_rules_exit(struct net *net) { - struct mr6_table *mrt, *next; + struct mr_table *mrt, *next; rtnl_lock(); list_for_each_entry_safe(mrt, next, &net->ipv6.mr6_tables, list) { @@ -273,13 +248,13 @@ static void __net_exit ip6mr_rules_exit(struct net *net) #define ip6mr_for_each_table(mrt, net) \ for (mrt = net->ipv6.mrt6; mrt; mrt = NULL) -static struct mr6_table *ip6mr_get_table(struct net *net, u32 id) +static struct mr_table *ip6mr_get_table(struct net *net, u32 id) { return net->ipv6.mrt6; } static int ip6mr_fib_lookup(struct net *net, struct flowi6 *flp6, - struct mr6_table **mrt) + struct mr_table **mrt) { *mrt = net->ipv6.mrt6; return 0; @@ -320,9 +295,9 @@ static const struct rhashtable_params ip6mr_rht_params = { .automatic_shrinking = true, }; -static struct mr6_table *ip6mr_new_table(struct net *net, u32 id) +static struct mr_table *ip6mr_new_table(struct net *net, u32 id) { - struct mr6_table *mrt; + struct mr_table *mrt; mrt = ip6mr_get_table(net, id); if (mrt) @@ -334,9 +309,9 @@ static struct mr6_table *ip6mr_new_table(struct net *net, u32 id) mrt->id = id; write_pnet(&mrt->net, net); - rhltable_init(&mrt->mfc6_hash, &ip6mr_rht_params); - INIT_LIST_HEAD(&mrt->mfc6_cache_list); - INIT_LIST_HEAD(&mrt->mfc6_unres_queue); + rhltable_init(&mrt->mfc_hash, &ip6mr_rht_params); + INIT_LIST_HEAD(&mrt->mfc_cache_list); + INIT_LIST_HEAD(&mrt->mfc_unres_queue); timer_setup(&mrt->ipmr_expire_timer, ipmr_expire_process, 0); @@ -349,11 +324,11 @@ static struct mr6_table *ip6mr_new_table(struct net *net, u32 id) return mrt; } -static void ip6mr_free_table(struct mr6_table *mrt) +static void ip6mr_free_table(struct mr_table *mrt) { del_timer_sync(&mrt->ipmr_expire_timer); mroute_clean_tables(mrt, true); - rhltable_destroy(&mrt->mfc6_hash); + rhltable_destroy(&mrt->mfc_hash); kfree(mrt); } @@ -361,7 +336,7 @@ static void ip6mr_free_table(struct mr6_table *mrt) struct ipmr_mfc_iter { struct seq_net_private p; - struct mr6_table *mrt; + struct mr_table *mrt; struct list_head *cache; }; @@ -369,18 +344,18 @@ struct ipmr_mfc_iter { static struct mfc6_cache *ipmr_mfc_seq_idx(struct net *net, struct ipmr_mfc_iter *it, loff_t pos) { - struct mr6_table *mrt = it->mrt; + struct mr_table *mrt = it->mrt; struct mfc6_cache *mfc; rcu_read_lock(); - it->cache = &mrt->mfc6_cache_list; - list_for_each_entry_rcu(mfc, &mrt->mfc6_cache_list, list) + it->cache = &mrt->mfc_cache_list; + list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) if (pos-- == 0) return mfc; rcu_read_unlock(); spin_lock_bh(&mfc_unres_lock); - it->cache = &mrt->mfc6_unres_queue; + it->cache = &mrt->mfc_unres_queue; list_for_each_entry(mfc, it->cache, list) if (pos-- == 0) return mfc; @@ -396,7 +371,7 @@ static struct mfc6_cache *ipmr_mfc_seq_idx(struct net *net, struct ipmr_vif_iter { struct seq_net_private p; - struct mr6_table *mrt; + struct mr_table *mrt; int ct; }; @@ -404,13 +379,13 @@ static struct vif_device *ip6mr_vif_seq_idx(struct net *net, struct ipmr_vif_iter *iter, loff_t pos) { - struct mr6_table *mrt = iter->mrt; + struct mr_table *mrt = iter->mrt; for (iter->ct = 0; iter->ct < mrt->maxvif; ++iter->ct) { - if (!MIF_EXISTS(mrt, iter->ct)) + if (!VIF_EXISTS(mrt, iter->ct)) continue; if (pos-- == 0) - return &mrt->vif6_table[iter->ct]; + return &mrt->vif_table[iter->ct]; } return NULL; } @@ -420,7 +395,7 @@ static void *ip6mr_vif_seq_start(struct seq_file *seq, loff_t *pos) { struct ipmr_vif_iter *iter = seq->private; struct net *net = seq_file_net(seq); - struct mr6_table *mrt; + struct mr_table *mrt; mrt = ip6mr_get_table(net, RT6_TABLE_DFLT); if (!mrt) @@ -437,16 +412,16 @@ static void *ip6mr_vif_seq_next(struct seq_file *seq, void *v, loff_t *pos) { struct ipmr_vif_iter *iter = seq->private; struct net *net = seq_file_net(seq); - struct mr6_table *mrt = iter->mrt; + struct mr_table *mrt = iter->mrt; ++*pos; if (v == SEQ_START_TOKEN) return ip6mr_vif_seq_idx(net, iter, 0); while (++iter->ct < mrt->maxvif) { - if (!MIF_EXISTS(mrt, iter->ct)) + if (!VIF_EXISTS(mrt, iter->ct)) continue; - return &mrt->vif6_table[iter->ct]; + return &mrt->vif_table[iter->ct]; } return NULL; } @@ -460,7 +435,7 @@ static void ip6mr_vif_seq_stop(struct seq_file *seq, void *v) static int ip6mr_vif_seq_show(struct seq_file *seq, void *v) { struct ipmr_vif_iter *iter = seq->private; - struct mr6_table *mrt = iter->mrt; + struct mr_table *mrt = iter->mrt; if (v == SEQ_START_TOKEN) { seq_puts(seq, @@ -471,7 +446,7 @@ static int ip6mr_vif_seq_show(struct seq_file *seq, void *v) seq_printf(seq, "%2td %-10s %8ld %7ld %8ld %7ld %05X\n", - vif - mrt->vif6_table, + vif - mrt->vif_table, name, vif->bytes_in, vif->pkt_in, vif->bytes_out, vif->pkt_out, vif->flags); @@ -503,7 +478,7 @@ static void *ipmr_mfc_seq_start(struct seq_file *seq, loff_t *pos) { struct ipmr_mfc_iter *it = seq->private; struct net *net = seq_file_net(seq); - struct mr6_table *mrt; + struct mr_table *mrt; mrt = ip6mr_get_table(net, RT6_TABLE_DFLT); if (!mrt) @@ -520,7 +495,7 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) struct mfc6_cache *mfc = v; struct ipmr_mfc_iter *it = seq->private; struct net *net = seq_file_net(seq); - struct mr6_table *mrt = it->mrt; + struct mr_table *mrt = it->mrt; ++*pos; @@ -530,12 +505,12 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) if (mfc->list.next != it->cache) return list_entry(mfc->list.next, struct mfc6_cache, list); - if (it->cache == &mrt->mfc6_unres_queue) + if (it->cache == &mrt->mfc_unres_queue) goto end_of_list; /* exhausted cache_array, show unresolved */ rcu_read_unlock(); - it->cache = &mrt->mfc6_unres_queue; + it->cache = &mrt->mfc_unres_queue; spin_lock_bh(&mfc_unres_lock); if (!list_empty(it->cache)) @@ -551,11 +526,11 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) static void ipmr_mfc_seq_stop(struct seq_file *seq, void *v) { struct ipmr_mfc_iter *it = seq->private; - struct mr6_table *mrt = it->mrt; + struct mr_table *mrt = it->mrt; - if (it->cache == &mrt->mfc6_unres_queue) + if (it->cache == &mrt->mfc_unres_queue) spin_unlock_bh(&mfc_unres_lock); - else if (it->cache == &mrt->mfc6_cache_list) + else if (it->cache == &mrt->mfc_cache_list) rcu_read_unlock(); } @@ -571,20 +546,20 @@ static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) } else { const struct mfc6_cache *mfc = v; const struct ipmr_mfc_iter *it = seq->private; - struct mr6_table *mrt = it->mrt; + struct mr_table *mrt = it->mrt; seq_printf(seq, "%pI6 %pI6 %-3hd", &mfc->mf6c_mcastgrp, &mfc->mf6c_origin, mfc->mf6c_parent); - if (it->cache != &mrt->mfc6_unres_queue) { + if (it->cache != &mrt->mfc_unres_queue) { seq_printf(seq, " %8lu %8lu %8lu", mfc->mfc_un.res.pkt, mfc->mfc_un.res.bytes, mfc->mfc_un.res.wrong_if); for (n = mfc->mfc_un.res.minvif; n < mfc->mfc_un.res.maxvif; n++) { - if (MIF_EXISTS(mrt, n) && + if (VIF_EXISTS(mrt, n) && mfc->mfc_un.res.ttls[n] < 255) seq_printf(seq, " %2d:%-3d", @@ -630,7 +605,7 @@ static int pim6_rcv(struct sk_buff *skb) struct ipv6hdr *encap; struct net_device *reg_dev = NULL; struct net *net = dev_net(skb->dev); - struct mr6_table *mrt; + struct mr_table *mrt; struct flowi6 fl6 = { .flowi6_iif = skb->dev->ifindex, .flowi6_mark = skb->mark, @@ -664,7 +639,7 @@ static int pim6_rcv(struct sk_buff *skb) read_lock(&mrt_lock); if (reg_vif_num >= 0) - reg_dev = mrt->vif6_table[reg_vif_num].dev; + reg_dev = mrt->vif_table[reg_vif_num].dev; if (reg_dev) dev_hold(reg_dev); read_unlock(&mrt_lock); @@ -699,7 +674,7 @@ static netdev_tx_t reg_vif_xmit(struct sk_buff *skb, struct net_device *dev) { struct net *net = dev_net(dev); - struct mr6_table *mrt; + struct mr_table *mrt; struct flowi6 fl6 = { .flowi6_oif = dev->ifindex, .flowi6_iif = skb->skb_iif ? : LOOPBACK_IFINDEX, @@ -742,7 +717,7 @@ static void reg_vif_setup(struct net_device *dev) dev->features |= NETIF_F_NETNS_LOCAL; } -static struct net_device *ip6mr_reg_vif(struct net *net, struct mr6_table *mrt) +static struct net_device *ip6mr_reg_vif(struct net *net, struct mr_table *mrt) { struct net_device *dev; char name[IFNAMSIZ]; @@ -779,7 +754,7 @@ failure: * Delete a VIF entry */ -static int mif6_delete(struct mr6_table *mrt, int vifi, int notify, +static int mif6_delete(struct mr_table *mrt, int vifi, int notify, struct list_head *head) { struct vif_device *v; @@ -789,7 +764,7 @@ static int mif6_delete(struct mr6_table *mrt, int vifi, int notify, if (vifi < 0 || vifi >= mrt->maxvif) return -EADDRNOTAVAIL; - v = &mrt->vif6_table[vifi]; + v = &mrt->vif_table[vifi]; write_lock_bh(&mrt_lock); dev = v->dev; @@ -808,7 +783,7 @@ static int mif6_delete(struct mr6_table *mrt, int vifi, int notify, if (vifi + 1 == mrt->maxvif) { int tmp; for (tmp = vifi - 1; tmp >= 0; tmp--) { - if (MIF_EXISTS(mrt, tmp)) + if (VIF_EXISTS(mrt, tmp)) break; } mrt->maxvif = tmp + 1; @@ -849,7 +824,7 @@ static inline void ip6mr_cache_free(struct mfc6_cache *c) and reporting error to netlink readers. */ -static void ip6mr_destroy_unres(struct mr6_table *mrt, struct mfc6_cache *c) +static void ip6mr_destroy_unres(struct mr_table *mrt, struct mfc6_cache *c) { struct net *net = read_pnet(&mrt->net); struct sk_buff *skb; @@ -875,13 +850,13 @@ static void ip6mr_destroy_unres(struct mr6_table *mrt, struct mfc6_cache *c) /* Timer process for all the unresolved queue. */ -static void ipmr_do_expire_process(struct mr6_table *mrt) +static void ipmr_do_expire_process(struct mr_table *mrt) { unsigned long now = jiffies; unsigned long expires = 10 * HZ; struct mfc6_cache *c, *next; - list_for_each_entry_safe(c, next, &mrt->mfc6_unres_queue, list) { + list_for_each_entry_safe(c, next, &mrt->mfc_unres_queue, list) { if (time_after(c->mfc_un.unres.expires, now)) { /* not yet... */ unsigned long interval = c->mfc_un.unres.expires - now; @@ -895,20 +870,20 @@ static void ipmr_do_expire_process(struct mr6_table *mrt) ip6mr_destroy_unres(mrt, c); } - if (!list_empty(&mrt->mfc6_unres_queue)) + if (!list_empty(&mrt->mfc_unres_queue)) mod_timer(&mrt->ipmr_expire_timer, jiffies + expires); } static void ipmr_expire_process(struct timer_list *t) { - struct mr6_table *mrt = from_timer(mrt, t, ipmr_expire_timer); + struct mr_table *mrt = from_timer(mrt, t, ipmr_expire_timer); if (!spin_trylock(&mfc_unres_lock)) { mod_timer(&mrt->ipmr_expire_timer, jiffies + 1); return; } - if (!list_empty(&mrt->mfc6_unres_queue)) + if (!list_empty(&mrt->mfc_unres_queue)) ipmr_do_expire_process(mrt); spin_unlock(&mfc_unres_lock); @@ -916,7 +891,8 @@ static void ipmr_expire_process(struct timer_list *t) /* Fill oifs list. It is called under write locked mrt_lock. */ -static void ip6mr_update_thresholds(struct mr6_table *mrt, struct mfc6_cache *cache, +static void ip6mr_update_thresholds(struct mr_table *mrt, + struct mfc6_cache *cache, unsigned char *ttls) { int vifi; @@ -926,7 +902,7 @@ static void ip6mr_update_thresholds(struct mr6_table *mrt, struct mfc6_cache *ca memset(cache->mfc_un.res.ttls, 255, MAXMIFS); for (vifi = 0; vifi < mrt->maxvif; vifi++) { - if (MIF_EXISTS(mrt, vifi) && + if (VIF_EXISTS(mrt, vifi) && ttls[vifi] && ttls[vifi] < 255) { cache->mfc_un.res.ttls[vifi] = ttls[vifi]; if (cache->mfc_un.res.minvif > vifi) @@ -938,17 +914,17 @@ static void ip6mr_update_thresholds(struct mr6_table *mrt, struct mfc6_cache *ca cache->mfc_un.res.lastuse = jiffies; } -static int mif6_add(struct net *net, struct mr6_table *mrt, +static int mif6_add(struct net *net, struct mr_table *mrt, struct mif6ctl *vifc, int mrtsock) { int vifi = vifc->mif6c_mifi; - struct vif_device *v = &mrt->vif6_table[vifi]; + struct vif_device *v = &mrt->vif_table[vifi]; struct net_device *dev; struct inet6_dev *in6_dev; int err; /* Is vif busy ? */ - if (MIF_EXISTS(mrt, vifi)) + if (VIF_EXISTS(mrt, vifi)) return -EADDRINUSE; switch (vifc->mif6c_flags) { @@ -1011,7 +987,7 @@ static int mif6_add(struct net *net, struct mr6_table *mrt, return 0; } -static struct mfc6_cache *ip6mr_cache_find(struct mr6_table *mrt, +static struct mfc6_cache *ip6mr_cache_find(struct mr_table *mrt, const struct in6_addr *origin, const struct in6_addr *mcastgrp) { @@ -1022,7 +998,7 @@ static struct mfc6_cache *ip6mr_cache_find(struct mr6_table *mrt, struct rhlist_head *tmp, *list; struct mfc6_cache *c; - list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) return c; @@ -1030,7 +1006,7 @@ static struct mfc6_cache *ip6mr_cache_find(struct mr6_table *mrt, } /* Look for a (*,*,oif) entry */ -static struct mfc6_cache *ip6mr_cache_find_any_parent(struct mr6_table *mrt, +static struct mfc6_cache *ip6mr_cache_find_any_parent(struct mr_table *mrt, mifi_t mifi) { struct mfc6_cache_cmp_arg arg = { @@ -1040,7 +1016,7 @@ static struct mfc6_cache *ip6mr_cache_find_any_parent(struct mr6_table *mrt, struct rhlist_head *tmp, *list; struct mfc6_cache *c; - list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) if (c->mfc_un.res.ttls[mifi] < 255) return c; @@ -1049,7 +1025,7 @@ static struct mfc6_cache *ip6mr_cache_find_any_parent(struct mr6_table *mrt, } /* Look for a (*,G) entry */ -static struct mfc6_cache *ip6mr_cache_find_any(struct mr6_table *mrt, +static struct mfc6_cache *ip6mr_cache_find_any(struct mr_table *mrt, struct in6_addr *mcastgrp, mifi_t mifi) { @@ -1063,7 +1039,7 @@ static struct mfc6_cache *ip6mr_cache_find_any(struct mr6_table *mrt, if (ipv6_addr_any(mcastgrp)) goto skip; - list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) { if (c->mfc_un.res.ttls[mifi] < 255) return c; @@ -1080,7 +1056,7 @@ skip: /* Look for a (S,G,iif) entry if parent != -1 */ static struct mfc6_cache * -ip6mr_cache_find_parent(struct mr6_table *mrt, +ip6mr_cache_find_parent(struct mr_table *mrt, const struct in6_addr *origin, const struct in6_addr *mcastgrp, int parent) @@ -1092,7 +1068,7 @@ ip6mr_cache_find_parent(struct mr6_table *mrt, struct rhlist_head *tmp, *list; struct mfc6_cache *c; - list = rhltable_lookup(&mrt->mfc6_hash, &arg, ip6mr_rht_params); + list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) if (parent == -1 || parent == c->mf6c_parent) return c; @@ -1127,7 +1103,7 @@ static struct mfc6_cache *ip6mr_cache_alloc_unres(void) * A cache entry has gone into a resolved state from queued */ -static void ip6mr_cache_resolve(struct net *net, struct mr6_table *mrt, +static void ip6mr_cache_resolve(struct net *net, struct mr_table *mrt, struct mfc6_cache *uc, struct mfc6_cache *c) { struct sk_buff *skb; @@ -1161,7 +1137,7 @@ static void ip6mr_cache_resolve(struct net *net, struct mr6_table *mrt, * Called under mrt_lock. */ -static int ip6mr_cache_report(struct mr6_table *mrt, struct sk_buff *pkt, +static int ip6mr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, mifi_t mifi, int assert) { struct sock *mroute6_sk; @@ -1235,7 +1211,7 @@ static int ip6mr_cache_report(struct mr6_table *mrt, struct sk_buff *pkt, } rcu_read_lock(); - mroute6_sk = rcu_dereference(mrt->mroute6_sk); + mroute6_sk = rcu_dereference(mrt->mroute_sk); if (!mroute6_sk) { rcu_read_unlock(); kfree_skb(skb); @@ -1260,14 +1236,14 @@ static int ip6mr_cache_report(struct mr6_table *mrt, struct sk_buff *pkt, */ static int -ip6mr_cache_unresolved(struct mr6_table *mrt, mifi_t mifi, struct sk_buff *skb) +ip6mr_cache_unresolved(struct mr_table *mrt, mifi_t mifi, struct sk_buff *skb) { bool found = false; int err; struct mfc6_cache *c; spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(c, &mrt->mfc6_unres_queue, list) { + list_for_each_entry(c, &mrt->mfc_unres_queue, list) { if (ipv6_addr_equal(&c->mf6c_mcastgrp, &ipv6_hdr(skb)->daddr) && ipv6_addr_equal(&c->mf6c_origin, &ipv6_hdr(skb)->saddr)) { found = true; @@ -1311,7 +1287,7 @@ ip6mr_cache_unresolved(struct mr6_table *mrt, mifi_t mifi, struct sk_buff *skb) } atomic_inc(&mrt->cache_resolve_queue_len); - list_add(&c->list, &mrt->mfc6_unres_queue); + list_add(&c->list, &mrt->mfc_unres_queue); mr6_netlink_event(mrt, c, RTM_NEWROUTE); ipmr_do_expire_process(mrt); @@ -1336,7 +1312,7 @@ ip6mr_cache_unresolved(struct mr6_table *mrt, mifi_t mifi, struct sk_buff *skb) * MFC6 cache manipulation by user space */ -static int ip6mr_mfc_delete(struct mr6_table *mrt, struct mf6cctl *mfc, +static int ip6mr_mfc_delete(struct mr_table *mrt, struct mf6cctl *mfc, int parent) { struct mfc6_cache *c; @@ -1348,7 +1324,7 @@ static int ip6mr_mfc_delete(struct mr6_table *mrt, struct mf6cctl *mfc, rcu_read_unlock(); if (!c) return -ENOENT; - rhltable_remove(&mrt->mfc6_hash, &c->mnode, ip6mr_rht_params); + rhltable_remove(&mrt->mfc_hash, &c->mnode, ip6mr_rht_params); list_del_rcu(&c->list); mr6_netlink_event(mrt, c, RTM_DELROUTE); @@ -1361,7 +1337,7 @@ static int ip6mr_device_event(struct notifier_block *this, { struct net_device *dev = netdev_notifier_info_to_dev(ptr); struct net *net = dev_net(dev); - struct mr6_table *mrt; + struct mr_table *mrt; struct vif_device *v; int ct; @@ -1369,7 +1345,7 @@ static int ip6mr_device_event(struct notifier_block *this, return NOTIFY_DONE; ip6mr_for_each_table(mrt, net) { - v = &mrt->vif6_table[0]; + v = &mrt->vif_table[0]; for (ct = 0; ct < mrt->maxvif; ct++, v++) { if (v->dev == dev) mif6_delete(mrt, ct, 1, NULL); @@ -1483,7 +1459,7 @@ void ip6_mr_cleanup(void) kmem_cache_destroy(mrt_cachep); } -static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, +static int ip6mr_mfc_add(struct net *net, struct mr_table *mrt, struct mf6cctl *mfc, int mrtsock, int parent) { unsigned char ttls[MAXMIFS]; @@ -1531,21 +1507,21 @@ static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, if (!mrtsock) c->mfc_flags |= MFC_STATIC; - err = rhltable_insert_key(&mrt->mfc6_hash, &c->cmparg, &c->mnode, + err = rhltable_insert_key(&mrt->mfc_hash, &c->cmparg, &c->mnode, ip6mr_rht_params); if (err) { pr_err("ip6mr: rhtable insert error %d\n", err); ip6mr_cache_free(c); return err; } - list_add_tail_rcu(&c->list, &mrt->mfc6_cache_list); + list_add_tail_rcu(&c->list, &mrt->mfc_cache_list); /* Check to see if we resolved a queued list. If so we * need to send on the frames and tidy up. */ found = false; spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(uc, &mrt->mfc6_unres_queue, list) { + list_for_each_entry(uc, &mrt->mfc_unres_queue, list) { if (ipv6_addr_equal(&uc->mf6c_origin, &c->mf6c_origin) && ipv6_addr_equal(&uc->mf6c_mcastgrp, &c->mf6c_mcastgrp)) { list_del(&uc->list); @@ -1554,7 +1530,7 @@ static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, break; } } - if (list_empty(&mrt->mfc6_unres_queue)) + if (list_empty(&mrt->mfc_unres_queue)) del_timer(&mrt->ipmr_expire_timer); spin_unlock_bh(&mfc_unres_lock); @@ -1570,7 +1546,7 @@ static int ip6mr_mfc_add(struct net *net, struct mr6_table *mrt, * Close the multicast socket, and clear the vif tables etc */ -static void mroute_clean_tables(struct mr6_table *mrt, bool all) +static void mroute_clean_tables(struct mr_table *mrt, bool all) { struct mfc6_cache *c, *tmp; LIST_HEAD(list); @@ -1578,17 +1554,17 @@ static void mroute_clean_tables(struct mr6_table *mrt, bool all) /* Shut down all active vif entries */ for (i = 0; i < mrt->maxvif; i++) { - if (!all && (mrt->vif6_table[i].flags & VIFF_STATIC)) + if (!all && (mrt->vif_table[i].flags & VIFF_STATIC)) continue; mif6_delete(mrt, i, 0, &list); } unregister_netdevice_many(&list); /* Wipe the cache */ - list_for_each_entry_safe(c, tmp, &mrt->mfc6_cache_list, list) { + list_for_each_entry_safe(c, tmp, &mrt->mfc_cache_list, list) { if (!all && (c->mfc_flags & MFC_STATIC)) continue; - rhltable_remove(&mrt->mfc6_hash, &c->mnode, ip6mr_rht_params); + rhltable_remove(&mrt->mfc_hash, &c->mnode, ip6mr_rht_params); list_del_rcu(&c->list); mr6_netlink_event(mrt, c, RTM_DELROUTE); ip6mr_cache_free(c); @@ -1596,7 +1572,7 @@ static void mroute_clean_tables(struct mr6_table *mrt, bool all) if (atomic_read(&mrt->cache_resolve_queue_len) != 0) { spin_lock_bh(&mfc_unres_lock); - list_for_each_entry_safe(c, tmp, &mrt->mfc6_unres_queue, list) { + list_for_each_entry_safe(c, tmp, &mrt->mfc_unres_queue, list) { list_del(&c->list); mr6_netlink_event(mrt, c, RTM_DELROUTE); ip6mr_destroy_unres(mrt, c); @@ -1605,17 +1581,17 @@ static void mroute_clean_tables(struct mr6_table *mrt, bool all) } } -static int ip6mr_sk_init(struct mr6_table *mrt, struct sock *sk) +static int ip6mr_sk_init(struct mr_table *mrt, struct sock *sk) { int err = 0; struct net *net = sock_net(sk); rtnl_lock(); write_lock_bh(&mrt_lock); - if (rtnl_dereference(mrt->mroute6_sk)) { + if (rtnl_dereference(mrt->mroute_sk)) { err = -EADDRINUSE; } else { - rcu_assign_pointer(mrt->mroute6_sk, sk); + rcu_assign_pointer(mrt->mroute_sk, sk); net->ipv6.devconf_all->mc_forwarding++; } write_unlock_bh(&mrt_lock); @@ -1634,7 +1610,7 @@ int ip6mr_sk_done(struct sock *sk) { int err = -EACCES; struct net *net = sock_net(sk); - struct mr6_table *mrt; + struct mr_table *mrt; if (sk->sk_type != SOCK_RAW || inet_sk(sk)->inet_num != IPPROTO_ICMPV6) @@ -1642,9 +1618,9 @@ int ip6mr_sk_done(struct sock *sk) rtnl_lock(); ip6mr_for_each_table(mrt, net) { - if (sk == rtnl_dereference(mrt->mroute6_sk)) { + if (sk == rtnl_dereference(mrt->mroute_sk)) { write_lock_bh(&mrt_lock); - RCU_INIT_POINTER(mrt->mroute6_sk, NULL); + RCU_INIT_POINTER(mrt->mroute_sk, NULL); net->ipv6.devconf_all->mc_forwarding--; write_unlock_bh(&mrt_lock); inet6_netconf_notify_devconf(net, RTM_NEWNETCONF, @@ -1665,7 +1641,7 @@ int ip6mr_sk_done(struct sock *sk) bool mroute6_is_socket(struct net *net, struct sk_buff *skb) { - struct mr6_table *mrt; + struct mr_table *mrt; struct flowi6 fl6 = { .flowi6_iif = skb->skb_iif ? : LOOPBACK_IFINDEX, .flowi6_oif = skb->dev->ifindex, @@ -1675,7 +1651,7 @@ bool mroute6_is_socket(struct net *net, struct sk_buff *skb) if (ip6mr_fib_lookup(net, &fl6, &mrt) < 0) return NULL; - return rcu_access_pointer(mrt->mroute6_sk); + return rcu_access_pointer(mrt->mroute_sk); } EXPORT_SYMBOL(mroute6_is_socket); @@ -1693,7 +1669,7 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns struct mf6cctl mfc; mifi_t mifi; struct net *net = sock_net(sk); - struct mr6_table *mrt; + struct mr_table *mrt; if (sk->sk_type != SOCK_RAW || inet_sk(sk)->inet_num != IPPROTO_ICMPV6) @@ -1704,7 +1680,7 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns return -ENOENT; if (optname != MRT6_INIT) { - if (sk != rcu_access_pointer(mrt->mroute6_sk) && + if (sk != rcu_access_pointer(mrt->mroute_sk) && !ns_capable(net->user_ns, CAP_NET_ADMIN)) return -EACCES; } @@ -1728,7 +1704,7 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns return -ENFILE; rtnl_lock(); ret = mif6_add(net, mrt, &vif, - sk == rtnl_dereference(mrt->mroute6_sk)); + sk == rtnl_dereference(mrt->mroute_sk)); rtnl_unlock(); return ret; @@ -1764,7 +1740,7 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns else ret = ip6mr_mfc_add(net, mrt, &mfc, sk == - rtnl_dereference(mrt->mroute6_sk), + rtnl_dereference(mrt->mroute_sk), parent); rtnl_unlock(); return ret; @@ -1817,7 +1793,7 @@ int ip6_mroute_setsockopt(struct sock *sk, int optname, char __user *optval, uns /* "pim6reg%u" should not exceed 16 bytes (IFNAMSIZ) */ if (v != RT_TABLE_DEFAULT && v >= 100000000) return -EINVAL; - if (sk == rcu_access_pointer(mrt->mroute6_sk)) + if (sk == rcu_access_pointer(mrt->mroute_sk)) return -EBUSY; rtnl_lock(); @@ -1848,7 +1824,7 @@ int ip6_mroute_getsockopt(struct sock *sk, int optname, char __user *optval, int olr; int val; struct net *net = sock_net(sk); - struct mr6_table *mrt; + struct mr_table *mrt; if (sk->sk_type != SOCK_RAW || inet_sk(sk)->inet_num != IPPROTO_ICMPV6) @@ -1899,7 +1875,7 @@ int ip6mr_ioctl(struct sock *sk, int cmd, void __user *arg) struct vif_device *vif; struct mfc6_cache *c; struct net *net = sock_net(sk); - struct mr6_table *mrt; + struct mr_table *mrt; mrt = ip6mr_get_table(net, raw6_sk(sk)->ip6mr_table ? : RT6_TABLE_DFLT); if (!mrt) @@ -1912,8 +1888,8 @@ int ip6mr_ioctl(struct sock *sk, int cmd, void __user *arg) if (vr.mifi >= mrt->maxvif) return -EINVAL; read_lock(&mrt_lock); - vif = &mrt->vif6_table[vr.mifi]; - if (MIF_EXISTS(mrt, vr.mifi)) { + vif = &mrt->vif_table[vr.mifi]; + if (VIF_EXISTS(mrt, vr.mifi)) { vr.icount = vif->pkt_in; vr.ocount = vif->pkt_out; vr.ibytes = vif->bytes_in; @@ -1973,7 +1949,7 @@ int ip6mr_compat_ioctl(struct sock *sk, unsigned int cmd, void __user *arg) struct vif_device *vif; struct mfc6_cache *c; struct net *net = sock_net(sk); - struct mr6_table *mrt; + struct mr_table *mrt; mrt = ip6mr_get_table(net, raw6_sk(sk)->ip6mr_table ? : RT6_TABLE_DFLT); if (!mrt) @@ -1986,8 +1962,8 @@ int ip6mr_compat_ioctl(struct sock *sk, unsigned int cmd, void __user *arg) if (vr.mifi >= mrt->maxvif) return -EINVAL; read_lock(&mrt_lock); - vif = &mrt->vif6_table[vr.mifi]; - if (MIF_EXISTS(mrt, vr.mifi)) { + vif = &mrt->vif_table[vr.mifi]; + if (VIF_EXISTS(mrt, vr.mifi)) { vr.icount = vif->pkt_in; vr.ocount = vif->pkt_out; vr.ibytes = vif->bytes_in; @@ -2037,11 +2013,11 @@ static inline int ip6mr_forward2_finish(struct net *net, struct sock *sk, struct * Processing handlers for ip6mr_forward */ -static int ip6mr_forward2(struct net *net, struct mr6_table *mrt, +static int ip6mr_forward2(struct net *net, struct mr_table *mrt, struct sk_buff *skb, struct mfc6_cache *c, int vifi) { struct ipv6hdr *ipv6h; - struct vif_device *vif = &mrt->vif6_table[vifi]; + struct vif_device *vif = &mrt->vif_table[vifi]; struct net_device *dev; struct dst_entry *dst; struct flowi6 fl6; @@ -2111,18 +2087,18 @@ out_free: return 0; } -static int ip6mr_find_vif(struct mr6_table *mrt, struct net_device *dev) +static int ip6mr_find_vif(struct mr_table *mrt, struct net_device *dev) { int ct; for (ct = mrt->maxvif - 1; ct >= 0; ct--) { - if (mrt->vif6_table[ct].dev == dev) + if (mrt->vif_table[ct].dev == dev) break; } return ct; } -static void ip6_mr_forward(struct net *net, struct mr6_table *mrt, +static void ip6_mr_forward(struct net *net, struct mr_table *mrt, struct sk_buff *skb, struct mfc6_cache *cache) { int psend = -1; @@ -2153,7 +2129,7 @@ static void ip6_mr_forward(struct net *net, struct mr6_table *mrt, /* * Wrong interface: drop packet and (maybe) send PIM assert. */ - if (mrt->vif6_table[vif].dev != skb->dev) { + if (mrt->vif_table[vif].dev != skb->dev) { cache->mfc_un.res.wrong_if++; if (true_vifi >= 0 && mrt->mroute_do_assert && @@ -2173,8 +2149,8 @@ static void ip6_mr_forward(struct net *net, struct mr6_table *mrt, } forward: - mrt->vif6_table[vif].pkt_in++; - mrt->vif6_table[vif].bytes_in += skb->len; + mrt->vif_table[vif].pkt_in++; + mrt->vif_table[vif].bytes_in += skb->len; /* * Forward the frame @@ -2225,7 +2201,7 @@ int ip6_mr_input(struct sk_buff *skb) { struct mfc6_cache *cache; struct net *net = dev_net(skb->dev); - struct mr6_table *mrt; + struct mr_table *mrt; struct flowi6 fl6 = { .flowi6_iif = skb->dev->ifindex, .flowi6_mark = skb->mark, @@ -2276,7 +2252,7 @@ int ip6_mr_input(struct sk_buff *skb) } -static int __ip6mr_fill_mroute(struct mr6_table *mrt, struct sk_buff *skb, +static int __ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, struct mfc6_cache *c, struct rtmsg *rtm) { struct rta_mfc_stats mfcs; @@ -2291,15 +2267,16 @@ static int __ip6mr_fill_mroute(struct mr6_table *mrt, struct sk_buff *skb, return -ENOENT; } - if (MIF_EXISTS(mrt, c->mf6c_parent) && - nla_put_u32(skb, RTA_IIF, mrt->vif6_table[c->mf6c_parent].dev->ifindex) < 0) + if (VIF_EXISTS(mrt, c->mf6c_parent) && + nla_put_u32(skb, RTA_IIF, + mrt->vif_table[c->mf6c_parent].dev->ifindex) < 0) return -EMSGSIZE; mp_attr = nla_nest_start(skb, RTA_MULTIPATH); if (!mp_attr) return -EMSGSIZE; for (ct = c->mfc_un.res.minvif; ct < c->mfc_un.res.maxvif; ct++) { - if (MIF_EXISTS(mrt, ct) && c->mfc_un.res.ttls[ct] < 255) { + if (VIF_EXISTS(mrt, ct) && c->mfc_un.res.ttls[ct] < 255) { nhp = nla_reserve_nohdr(skb, sizeof(*nhp)); if (!nhp) { nla_nest_cancel(skb, mp_attr); @@ -2308,7 +2285,7 @@ static int __ip6mr_fill_mroute(struct mr6_table *mrt, struct sk_buff *skb, nhp->rtnh_flags = 0; nhp->rtnh_hops = c->mfc_un.res.ttls[ct]; - nhp->rtnh_ifindex = mrt->vif6_table[ct].dev->ifindex; + nhp->rtnh_ifindex = mrt->vif_table[ct].dev->ifindex; nhp->rtnh_len = sizeof(*nhp); } } @@ -2334,7 +2311,7 @@ int ip6mr_get_route(struct net *net, struct sk_buff *skb, struct rtmsg *rtm, u32 portid) { int err; - struct mr6_table *mrt; + struct mr_table *mrt; struct mfc6_cache *cache; struct rt6_info *rt = (struct rt6_info *)skb_dst(skb); @@ -2403,7 +2380,7 @@ int ip6mr_get_route(struct net *net, struct sk_buff *skb, struct rtmsg *rtm, return err; } -static int ip6mr_fill_mroute(struct mr6_table *mrt, struct sk_buff *skb, +static int ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, u32 portid, u32 seq, struct mfc6_cache *c, int cmd, int flags) { @@ -2468,7 +2445,7 @@ static int mr6_msgsize(bool unresolved, int maxvif) return len; } -static void mr6_netlink_event(struct mr6_table *mrt, struct mfc6_cache *mfc, +static void mr6_netlink_event(struct mr_table *mrt, struct mfc6_cache *mfc, int cmd) { struct net *net = read_pnet(&mrt->net); @@ -2510,7 +2487,7 @@ static size_t mrt6msg_netlink_msgsize(size_t payloadlen) return len; } -static void mrt6msg_netlink_event(struct mr6_table *mrt, struct sk_buff *pkt) +static void mrt6msg_netlink_event(struct mr_table *mrt, struct sk_buff *pkt) { struct net *net = read_pnet(&mrt->net); struct nlmsghdr *nlh; @@ -2561,7 +2538,7 @@ errout: static int ip6mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) { struct net *net = sock_net(skb->sk); - struct mr6_table *mrt; + struct mr_table *mrt; struct mfc6_cache *mfc; unsigned int t = 0, s_t; unsigned int e = 0, s_e; @@ -2573,7 +2550,7 @@ static int ip6mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) ip6mr_for_each_table(mrt, net) { if (t < s_t) goto next_table; - list_for_each_entry_rcu(mfc, &mrt->mfc6_cache_list, list) { + list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) { if (e < s_e) goto next_entry; if (ip6mr_fill_mroute(mrt, skb, @@ -2589,7 +2566,7 @@ next_entry: s_e = 0; spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(mfc, &mrt->mfc6_unres_queue, list) { + list_for_each_entry(mfc, &mrt->mfc_unres_queue, list) { if (e < s_e) goto next_entry2; if (ip6mr_fill_mroute(mrt, skb, -- cgit v1.2.3 From 0bbbf0e7d0e7ea8267836986346a9b3a35b74e4e Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:33 +0200 Subject: ipmr, ip6mr: Unite creation of new mr_table Now that both ipmr and ip6mr are using the same mr_table structure, we can have a common function to allocate & initialize a new instance. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute_base.h | 17 +++++++++++++++++ net/ipv4/ipmr.c | 27 ++++++++++----------------- net/ipv4/ipmr_base.c | 27 +++++++++++++++++++++++++++ net/ipv6/ip6mr.c | 30 ++++++++++-------------------- 4 files changed, 64 insertions(+), 37 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 1cc944a14df5..805305722803 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -85,6 +85,13 @@ void vif_device_init(struct vif_device *v, unsigned char threshold, unsigned short flags, unsigned short get_iflink_mask); + +struct mr_table * +mr_table_alloc(struct net *net, u32 id, + const struct rhashtable_params *rht_params, + void (*expire_func)(struct timer_list *t), + void (*table_set)(struct mr_table *mrt, + struct net *net)); #else static inline void vif_device_init(struct vif_device *v, struct net_device *dev, @@ -94,5 +101,15 @@ static inline void vif_device_init(struct vif_device *v, unsigned short get_iflink_mask) { } + +static inline struct mr_table * +mr_table_alloc(struct net *net, u32 id, + const struct rhashtable_params *rht_params, + void (*expire_func)(struct timer_list *t), + void (*table_set)(struct mr_table *mrt, + struct net *net)) +{ + return NULL; +} #endif #endif diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index a1bf0020cad1..f213933db177 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -352,6 +352,14 @@ static const struct rhashtable_params ipmr_rht_params = { .automatic_shrinking = true, }; +static void ipmr_new_table_set(struct mr_table *mrt, + struct net *net) +{ +#ifdef CONFIG_IP_MROUTE_MULTIPLE_TABLES + list_add_tail_rcu(&mrt->list, &net->ipv4.mr_tables); +#endif +} + static struct mr_table *ipmr_new_table(struct net *net, u32 id) { struct mr_table *mrt; @@ -364,23 +372,8 @@ static struct mr_table *ipmr_new_table(struct net *net, u32 id) if (mrt) return mrt; - mrt = kzalloc(sizeof(*mrt), GFP_KERNEL); - if (!mrt) - return ERR_PTR(-ENOMEM); - write_pnet(&mrt->net, net); - mrt->id = id; - - rhltable_init(&mrt->mfc_hash, &ipmr_rht_params); - INIT_LIST_HEAD(&mrt->mfc_cache_list); - INIT_LIST_HEAD(&mrt->mfc_unres_queue); - - timer_setup(&mrt->ipmr_expire_timer, ipmr_expire_process, 0); - - mrt->mroute_reg_vif_num = -1; -#ifdef CONFIG_IP_MROUTE_MULTIPLE_TABLES - list_add_tail_rcu(&mrt->list, &net->ipv4.mr_tables); -#endif - return mrt; + return mr_table_alloc(net, id, &ipmr_rht_params, + ipmr_expire_process, ipmr_new_table_set); } static void ipmr_free_table(struct mr_table *mrt) diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c index 22758f848344..3e21a5806d0e 100644 --- a/net/ipv4/ipmr_base.c +++ b/net/ipv4/ipmr_base.c @@ -26,3 +26,30 @@ void vif_device_init(struct vif_device *v, v->link = dev->ifindex; } EXPORT_SYMBOL(vif_device_init); + +struct mr_table * +mr_table_alloc(struct net *net, u32 id, + const struct rhashtable_params *rht_params, + void (*expire_func)(struct timer_list *t), + void (*table_set)(struct mr_table *mrt, + struct net *net)) +{ + struct mr_table *mrt; + + mrt = kzalloc(sizeof(*mrt), GFP_KERNEL); + if (!mrt) + return NULL; + mrt->id = id; + write_pnet(&mrt->net, net); + + rhltable_init(&mrt->mfc_hash, rht_params); + INIT_LIST_HEAD(&mrt->mfc_cache_list); + INIT_LIST_HEAD(&mrt->mfc_unres_queue); + + timer_setup(&mrt->ipmr_expire_timer, expire_func, 0); + + mrt->mroute_reg_vif_num = -1; + table_set(mrt, net); + return mrt; +} +EXPORT_SYMBOL(mr_table_alloc); diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index adbb826ca8fd..d50852882966 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -295,6 +294,14 @@ static const struct rhashtable_params ip6mr_rht_params = { .automatic_shrinking = true, }; +static void ip6mr_new_table_set(struct mr_table *mrt, + struct net *net) +{ +#ifdef CONFIG_IPV6_MROUTE_MULTIPLE_TABLES + list_add_tail_rcu(&mrt->list, &net->ipv6.mr6_tables); +#endif +} + static struct mr_table *ip6mr_new_table(struct net *net, u32 id) { struct mr_table *mrt; @@ -303,25 +310,8 @@ static struct mr_table *ip6mr_new_table(struct net *net, u32 id) if (mrt) return mrt; - mrt = kzalloc(sizeof(*mrt), GFP_KERNEL); - if (!mrt) - return NULL; - mrt->id = id; - write_pnet(&mrt->net, net); - - rhltable_init(&mrt->mfc_hash, &ip6mr_rht_params); - INIT_LIST_HEAD(&mrt->mfc_cache_list); - INIT_LIST_HEAD(&mrt->mfc_unres_queue); - - timer_setup(&mrt->ipmr_expire_timer, ipmr_expire_process, 0); - -#ifdef CONFIG_IPV6_PIMSM_V2 - mrt->mroute_reg_vif_num = -1; -#endif -#ifdef CONFIG_IPV6_MROUTE_MULTIPLE_TABLES - list_add_tail_rcu(&mrt->list, &net->ipv6.mr6_tables); -#endif - return mrt; + return mr_table_alloc(net, id, &ip6mr_rht_params, + ipmr_expire_process, ip6mr_new_table_set); } static void ip6mr_free_table(struct mr_table *mrt) -- cgit v1.2.3 From 494fff56379c4ad5b8fe36a5b7ffede4044ca7bb Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:34 +0200 Subject: ipmr, ip6mr: Make mfc_cache a common structure mfc_cache and mfc6_cache are almost identical - the main difference is in the origin/group addresses and comparison-key. Make a common structure encapsulating most of the multicast routing logic - mr_mfc and convert both ipmr and ip6mr into using it. For easy conversion [casting, in this case] mr_mfc has to be the first field inside every multicast routing abstraction utilizing it. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c | 21 +- include/linux/mroute.h | 45 +--- include/linux/mroute6.h | 23 +- include/linux/mroute_base.h | 45 ++++ net/ipv4/ipmr.c | 233 ++++++++++---------- net/ipv6/ip6mr.c | 248 +++++++++++----------- 6 files changed, 312 insertions(+), 303 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c index d20b143de3b4..978a3c70653a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c @@ -126,8 +126,8 @@ mlxsw_sp_mr_route_ivif_in_evifs(const struct mlxsw_sp_mr_route *mr_route) switch (mr_route->mr_table->proto) { case MLXSW_SP_L3_PROTO_IPV4: - ivif = mr_route->mfc4->mfc_parent; - return mr_route->mfc4->mfc_un.res.ttls[ivif] != 255; + ivif = mr_route->mfc4->_c.mfc_parent; + return mr_route->mfc4->_c.mfc_un.res.ttls[ivif] != 255; case MLXSW_SP_L3_PROTO_IPV6: /* fall through */ default: @@ -364,7 +364,7 @@ mlxsw_sp_mr_route4_create(struct mlxsw_sp_mr_table *mr_table, mr_route->mfc4 = mfc; mr_route->mr_table = mr_table; for (i = 0; i < MAXVIFS; i++) { - if (mfc->mfc_un.res.ttls[i] != 255) { + if (mfc->_c.mfc_un.res.ttls[i] != 255) { err = mlxsw_sp_mr_route_evif_link(mr_route, &mr_table->vifs[i]); if (err) @@ -374,7 +374,8 @@ mlxsw_sp_mr_route4_create(struct mlxsw_sp_mr_table *mr_table, mr_route->min_mtu = mr_table->vifs[i].dev->mtu; } } - mlxsw_sp_mr_route_ivif_link(mr_route, &mr_table->vifs[mfc->mfc_parent]); + mlxsw_sp_mr_route_ivif_link(mr_route, + &mr_table->vifs[mfc->_c.mfc_parent]); mr_route->route_action = mlxsw_sp_mr_route_action(mr_route); return mr_route; @@ -418,9 +419,9 @@ static void mlxsw_sp_mr_mfc_offload_set(struct mlxsw_sp_mr_route *mr_route, switch (mr_route->mr_table->proto) { case MLXSW_SP_L3_PROTO_IPV4: if (offload) - mr_route->mfc4->mfc_flags |= MFC_OFFLOAD; + mr_route->mfc4->_c.mfc_flags |= MFC_OFFLOAD; else - mr_route->mfc4->mfc_flags &= ~MFC_OFFLOAD; + mr_route->mfc4->_c.mfc_flags &= ~MFC_OFFLOAD; break; case MLXSW_SP_L3_PROTO_IPV6: /* fall through */ @@ -943,10 +944,10 @@ static void mlxsw_sp_mr_route_stats_update(struct mlxsw_sp *mlxsw_sp, switch (mr_route->mr_table->proto) { case MLXSW_SP_L3_PROTO_IPV4: - if (mr_route->mfc4->mfc_un.res.pkt != packets) - mr_route->mfc4->mfc_un.res.lastuse = jiffies; - mr_route->mfc4->mfc_un.res.pkt = packets; - mr_route->mfc4->mfc_un.res.bytes = bytes; + if (mr_route->mfc4->_c.mfc_un.res.pkt != packets) + mr_route->mfc4->_c.mfc_un.res.lastuse = jiffies; + mr_route->mfc4->_c.mfc_un.res.pkt = packets; + mr_route->mfc4->_c.mfc_un.res.bytes = bytes; break; case MLXSW_SP_L3_PROTO_IPV6: /* fall through */ diff --git a/include/linux/mroute.h b/include/linux/mroute.h index 8688c5d03a24..63b36e6c72a0 100644 --- a/include/linux/mroute.h +++ b/include/linux/mroute.h @@ -81,28 +81,13 @@ struct mfc_cache_cmp_arg { /** * struct mfc_cache - multicast routing entries - * @mnode: rhashtable list + * @_c: Common multicast routing information; has to be first [for casting] * @mfc_mcastgrp: destination multicast group address * @mfc_origin: source address * @cmparg: used for rhashtable comparisons - * @mfc_parent: source interface (iif) - * @mfc_flags: entry flags - * @expires: unresolved entry expire time - * @unresolved: unresolved cached skbs - * @last_assert: time of last assert - * @minvif: minimum VIF id - * @maxvif: maximum VIF id - * @bytes: bytes that have passed for this entry - * @pkt: packets that have passed for this entry - * @wrong_if: number of wrong source interface hits - * @lastuse: time of last use of the group (traffic or update) - * @ttls: OIF TTL threshold array - * @refcount: reference count for this entry - * @list: global entry list - * @rcu: used for entry destruction */ struct mfc_cache { - struct rhlist_head mnode; + struct mr_mfc _c; union { struct { __be32 mfc_mcastgrp; @@ -110,28 +95,6 @@ struct mfc_cache { }; struct mfc_cache_cmp_arg cmparg; }; - vifi_t mfc_parent; - int mfc_flags; - - union { - struct { - unsigned long expires; - struct sk_buff_head unresolved; - } unres; - struct { - unsigned long last_assert; - int minvif; - int maxvif; - unsigned long bytes; - unsigned long pkt; - unsigned long wrong_if; - unsigned long lastuse; - unsigned char ttls[MAXVIFS]; - refcount_t refcount; - } res; - } mfc_un; - struct list_head list; - struct rcu_head rcu; }; struct mfc_entry_notifier_info { @@ -155,12 +118,12 @@ static inline void ipmr_cache_free(struct mfc_cache *mfc_cache) static inline void ipmr_cache_put(struct mfc_cache *c) { - if (refcount_dec_and_test(&c->mfc_un.res.refcount)) + if (refcount_dec_and_test(&c->_c.mfc_un.res.refcount)) ipmr_cache_free(c); } static inline void ipmr_cache_hold(struct mfc_cache *c) { - refcount_inc(&c->mfc_un.res.refcount); + refcount_inc(&c->_c.mfc_un.res.refcount); } #endif diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h index d5c8dc155a42..6acf576fc135 100644 --- a/include/linux/mroute6.h +++ b/include/linux/mroute6.h @@ -71,7 +71,7 @@ struct mfc6_cache_cmp_arg { }; struct mfc6_cache { - struct rhlist_head mnode; + struct mr_mfc _c; union { struct { struct in6_addr mf6c_mcastgrp; @@ -79,27 +79,6 @@ struct mfc6_cache { }; struct mfc6_cache_cmp_arg cmparg; }; - mifi_t mf6c_parent; /* Source interface */ - int mfc_flags; /* Flags on line */ - - union { - struct { - unsigned long expires; - struct sk_buff_head unresolved; /* Unresolved buffers */ - } unres; - struct { - unsigned long last_assert; - int minvif; - int maxvif; - unsigned long bytes; - unsigned long pkt; - unsigned long wrong_if; - unsigned long lastuse; - unsigned char ttls[MAXMIFS]; /* TTL thresholds */ - } res; - } mfc_un; - struct list_head list; - struct rcu_head rcu; }; #define MFC_STATIC 1 diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 805305722803..2769e2f98b32 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -44,6 +44,51 @@ struct vif_device { #define VIF_EXISTS(_mrt, _idx) (!!((_mrt)->vif_table[_idx].dev)) +/** + * struct mr_mfc - common multicast routing entries + * @mnode: rhashtable list + * @mfc_parent: source interface (iif) + * @mfc_flags: entry flags + * @expires: unresolved entry expire time + * @unresolved: unresolved cached skbs + * @last_assert: time of last assert + * @minvif: minimum VIF id + * @maxvif: maximum VIF id + * @bytes: bytes that have passed for this entry + * @pkt: packets that have passed for this entry + * @wrong_if: number of wrong source interface hits + * @lastuse: time of last use of the group (traffic or update) + * @ttls: OIF TTL threshold array + * @refcount: reference count for this entry + * @list: global entry list + * @rcu: used for entry destruction + */ +struct mr_mfc { + struct rhlist_head mnode; + unsigned short mfc_parent; + int mfc_flags; + + union { + struct { + unsigned long expires; + struct sk_buff_head unresolved; + } unres; + struct { + unsigned long last_assert; + int minvif; + int maxvif; + unsigned long bytes; + unsigned long pkt; + unsigned long wrong_if; + unsigned long lastuse; + unsigned char ttls[MAXVIFS]; + refcount_t refcount; + } res; + } mfc_un; + struct list_head list; + struct rcu_head rcu; +}; + /** * struct mr_table - a multicast routing table * @list: entry within a list of multicast routing tables diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index f213933db177..3f7515086e85 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -106,7 +106,7 @@ static void ip_mr_forward(struct net *net, struct mr_table *mrt, static int ipmr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, vifi_t vifi, int assert); static int __ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, - struct mfc_cache *c, struct rtmsg *rtm); + struct mr_mfc *c, struct rtmsg *rtm); static void mroute_netlink_event(struct mr_table *mrt, struct mfc_cache *mfc, int cmd); static void igmpmsg_netlink_event(struct mr_table *mrt, struct sk_buff *pkt); @@ -343,7 +343,7 @@ static inline int ipmr_hash_cmp(struct rhashtable_compare_arg *arg, } static const struct rhashtable_params ipmr_rht_params = { - .head_offset = offsetof(struct mfc_cache, mnode), + .head_offset = offsetof(struct mr_mfc, mnode), .key_offset = offsetof(struct mfc_cache, cmparg), .key_len = sizeof(struct mfc_cache_cmp_arg), .nelem_hint = 3, @@ -752,14 +752,14 @@ static int vif_delete(struct mr_table *mrt, int vifi, int notify, static void ipmr_cache_free_rcu(struct rcu_head *head) { - struct mfc_cache *c = container_of(head, struct mfc_cache, rcu); + struct mr_mfc *c = container_of(head, struct mr_mfc, rcu); - kmem_cache_free(mrt_cachep, c); + kmem_cache_free(mrt_cachep, (struct mfc_cache *)c); } void ipmr_cache_free(struct mfc_cache *c) { - call_rcu(&c->rcu, ipmr_cache_free_rcu); + call_rcu(&c->_c.rcu, ipmr_cache_free_rcu); } EXPORT_SYMBOL(ipmr_cache_free); @@ -774,7 +774,7 @@ static void ipmr_destroy_unres(struct mr_table *mrt, struct mfc_cache *c) atomic_dec(&mrt->cache_resolve_queue_len); - while ((skb = skb_dequeue(&c->mfc_un.unres.unresolved))) { + while ((skb = skb_dequeue(&c->_c.mfc_un.unres.unresolved))) { if (ip_hdr(skb)->version == 0) { struct nlmsghdr *nlh = skb_pull(skb, sizeof(struct iphdr)); @@ -798,9 +798,9 @@ static void ipmr_destroy_unres(struct mr_table *mrt, struct mfc_cache *c) static void ipmr_expire_process(struct timer_list *t) { struct mr_table *mrt = from_timer(mrt, t, ipmr_expire_timer); - unsigned long now; + struct mr_mfc *c, *next; unsigned long expires; - struct mfc_cache *c, *next; + unsigned long now; if (!spin_trylock(&mfc_unres_lock)) { mod_timer(&mrt->ipmr_expire_timer, jiffies+HZ/10); @@ -822,8 +822,8 @@ static void ipmr_expire_process(struct timer_list *t) } list_del(&c->list); - mroute_netlink_event(mrt, c, RTM_DELROUTE); - ipmr_destroy_unres(mrt, c); + mroute_netlink_event(mrt, (struct mfc_cache *)c, RTM_DELROUTE); + ipmr_destroy_unres(mrt, (struct mfc_cache *)c); } if (!list_empty(&mrt->mfc_unres_queue)) @@ -834,7 +834,7 @@ out: } /* Fill oifs list. It is called under write locked mrt_lock. */ -static void ipmr_update_thresholds(struct mr_table *mrt, struct mfc_cache *cache, +static void ipmr_update_thresholds(struct mr_table *mrt, struct mr_mfc *cache, unsigned char *ttls) { int vifi; @@ -974,11 +974,11 @@ static struct mfc_cache *ipmr_cache_find(struct mr_table *mrt, .mfc_origin = origin }; struct rhlist_head *tmp, *list; - struct mfc_cache *c; + struct mr_mfc *c; list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) - return c; + return (struct mfc_cache *)c; return NULL; } @@ -992,12 +992,12 @@ static struct mfc_cache *ipmr_cache_find_any_parent(struct mr_table *mrt, .mfc_origin = htonl(INADDR_ANY) }; struct rhlist_head *tmp, *list; - struct mfc_cache *c; + struct mr_mfc *c; list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) if (c->mfc_un.res.ttls[vifi] < 255) - return c; + return (struct mfc_cache *)c; return NULL; } @@ -1011,20 +1011,22 @@ static struct mfc_cache *ipmr_cache_find_any(struct mr_table *mrt, .mfc_origin = htonl(INADDR_ANY) }; struct rhlist_head *tmp, *list; - struct mfc_cache *c, *proxy; + struct mr_mfc *c; if (mcastgrp == htonl(INADDR_ANY)) goto skip; list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) { + struct mfc_cache *proxy; + if (c->mfc_un.res.ttls[vifi] < 255) - return c; + return (struct mfc_cache *)c; /* It's ok if the vifi is part of the static tree */ proxy = ipmr_cache_find_any_parent(mrt, c->mfc_parent); - if (proxy && proxy->mfc_un.res.ttls[vifi] < 255) - return c; + if (proxy && proxy->_c.mfc_un.res.ttls[vifi] < 255) + return (struct mfc_cache *)c; } skip: @@ -1041,12 +1043,12 @@ static struct mfc_cache *ipmr_cache_find_parent(struct mr_table *mrt, .mfc_origin = origin, }; struct rhlist_head *tmp, *list; - struct mfc_cache *c; + struct mr_mfc *c; list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) if (parent == -1 || parent == c->mfc_parent) - return c; + return (struct mfc_cache *)c; return NULL; } @@ -1057,9 +1059,9 @@ static struct mfc_cache *ipmr_cache_alloc(void) struct mfc_cache *c = kmem_cache_zalloc(mrt_cachep, GFP_KERNEL); if (c) { - c->mfc_un.res.last_assert = jiffies - MFC_ASSERT_THRESH - 1; - c->mfc_un.res.minvif = MAXVIFS; - refcount_set(&c->mfc_un.res.refcount, 1); + c->_c.mfc_un.res.last_assert = jiffies - MFC_ASSERT_THRESH - 1; + c->_c.mfc_un.res.minvif = MAXVIFS; + refcount_set(&c->_c.mfc_un.res.refcount, 1); } return c; } @@ -1069,8 +1071,8 @@ static struct mfc_cache *ipmr_cache_alloc_unres(void) struct mfc_cache *c = kmem_cache_zalloc(mrt_cachep, GFP_ATOMIC); if (c) { - skb_queue_head_init(&c->mfc_un.unres.unresolved); - c->mfc_un.unres.expires = jiffies + 10*HZ; + skb_queue_head_init(&c->_c.mfc_un.unres.unresolved); + c->_c.mfc_un.unres.expires = jiffies + 10 * HZ; } return c; } @@ -1083,12 +1085,13 @@ static void ipmr_cache_resolve(struct net *net, struct mr_table *mrt, struct nlmsgerr *e; /* Play the pending entries through our router */ - while ((skb = __skb_dequeue(&uc->mfc_un.unres.unresolved))) { + while ((skb = __skb_dequeue(&uc->_c.mfc_un.unres.unresolved))) { if (ip_hdr(skb)->version == 0) { struct nlmsghdr *nlh = skb_pull(skb, sizeof(struct iphdr)); - if (__ipmr_fill_mroute(mrt, skb, c, nlmsg_data(nlh)) > 0) { + if (__ipmr_fill_mroute(mrt, skb, &c->_c, + nlmsg_data(nlh)) > 0) { nlh->nlmsg_len = skb_tail_pointer(skb) - (u8 *)nlh; } else { @@ -1196,7 +1199,7 @@ static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, int err; spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(c, &mrt->mfc_unres_queue, list) { + list_for_each_entry(c, &mrt->mfc_unres_queue, _c.list) { if (c->mfc_mcastgrp == iph->daddr && c->mfc_origin == iph->saddr) { found = true; @@ -1215,12 +1218,13 @@ static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, } /* Fill in the new cache entry */ - c->mfc_parent = -1; + c->_c.mfc_parent = -1; c->mfc_origin = iph->saddr; c->mfc_mcastgrp = iph->daddr; /* Reflect first query at mrouted. */ err = ipmr_cache_report(mrt, skb, vifi, IGMPMSG_NOCACHE); + if (err < 0) { /* If the report failed throw the cache entry out - Brad Parker @@ -1233,15 +1237,16 @@ static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, } atomic_inc(&mrt->cache_resolve_queue_len); - list_add(&c->list, &mrt->mfc_unres_queue); + list_add(&c->_c.list, &mrt->mfc_unres_queue); mroute_netlink_event(mrt, c, RTM_NEWROUTE); if (atomic_read(&mrt->cache_resolve_queue_len) == 1) - mod_timer(&mrt->ipmr_expire_timer, c->mfc_un.unres.expires); + mod_timer(&mrt->ipmr_expire_timer, + c->_c.mfc_un.unres.expires); } /* See if we can append the packet */ - if (c->mfc_un.unres.unresolved.qlen > 3) { + if (c->_c.mfc_un.unres.unresolved.qlen > 3) { kfree_skb(skb); err = -ENOBUFS; } else { @@ -1249,7 +1254,7 @@ static int ipmr_cache_unresolved(struct mr_table *mrt, vifi_t vifi, skb->dev = dev; skb->skb_iif = dev->ifindex; } - skb_queue_tail(&c->mfc_un.unres.unresolved, skb); + skb_queue_tail(&c->_c.mfc_un.unres.unresolved, skb); err = 0; } @@ -1271,8 +1276,8 @@ static int ipmr_mfc_delete(struct mr_table *mrt, struct mfcctl *mfc, int parent) rcu_read_unlock(); if (!c) return -ENOENT; - rhltable_remove(&mrt->mfc_hash, &c->mnode, ipmr_rht_params); - list_del_rcu(&c->list); + rhltable_remove(&mrt->mfc_hash, &c->_c.mnode, ipmr_rht_params); + list_del_rcu(&c->_c.list); call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_DEL, c, mrt->id); mroute_netlink_event(mrt, c, RTM_DELROUTE); ipmr_cache_put(c); @@ -1284,6 +1289,7 @@ static int ipmr_mfc_add(struct net *net, struct mr_table *mrt, struct mfcctl *mfc, int mrtsock, int parent) { struct mfc_cache *uc, *c; + struct mr_mfc *_uc; bool found; int ret; @@ -1297,10 +1303,10 @@ static int ipmr_mfc_add(struct net *net, struct mr_table *mrt, rcu_read_unlock(); if (c) { write_lock_bh(&mrt_lock); - c->mfc_parent = mfc->mfcc_parent; - ipmr_update_thresholds(mrt, c, mfc->mfcc_ttls); + c->_c.mfc_parent = mfc->mfcc_parent; + ipmr_update_thresholds(mrt, &c->_c, mfc->mfcc_ttls); if (!mrtsock) - c->mfc_flags |= MFC_STATIC; + c->_c.mfc_flags |= MFC_STATIC; write_unlock_bh(&mrt_lock); call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_REPLACE, c, mrt->id); @@ -1318,28 +1324,29 @@ static int ipmr_mfc_add(struct net *net, struct mr_table *mrt, c->mfc_origin = mfc->mfcc_origin.s_addr; c->mfc_mcastgrp = mfc->mfcc_mcastgrp.s_addr; - c->mfc_parent = mfc->mfcc_parent; - ipmr_update_thresholds(mrt, c, mfc->mfcc_ttls); + c->_c.mfc_parent = mfc->mfcc_parent; + ipmr_update_thresholds(mrt, &c->_c, mfc->mfcc_ttls); if (!mrtsock) - c->mfc_flags |= MFC_STATIC; + c->_c.mfc_flags |= MFC_STATIC; - ret = rhltable_insert_key(&mrt->mfc_hash, &c->cmparg, &c->mnode, + ret = rhltable_insert_key(&mrt->mfc_hash, &c->cmparg, &c->_c.mnode, ipmr_rht_params); if (ret) { pr_err("ipmr: rhtable insert error %d\n", ret); ipmr_cache_free(c); return ret; } - list_add_tail_rcu(&c->list, &mrt->mfc_cache_list); + list_add_tail_rcu(&c->_c.list, &mrt->mfc_cache_list); /* Check to see if we resolved a queued list. If so we * need to send on the frames and tidy up. */ found = false; spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(uc, &mrt->mfc_unres_queue, list) { + list_for_each_entry(_uc, &mrt->mfc_unres_queue, list) { + uc = (struct mfc_cache *)_uc; if (uc->mfc_origin == c->mfc_origin && uc->mfc_mcastgrp == c->mfc_mcastgrp) { - list_del(&uc->list); + list_del(&_uc->list); atomic_dec(&mrt->cache_resolve_queue_len); found = true; break; @@ -1362,7 +1369,8 @@ static int ipmr_mfc_add(struct net *net, struct mr_table *mrt, static void mroute_clean_tables(struct mr_table *mrt, bool all) { struct net *net = read_pnet(&mrt->net); - struct mfc_cache *c, *tmp; + struct mr_mfc *c, *tmp; + struct mfc_cache *cache; LIST_HEAD(list); int i; @@ -1380,18 +1388,20 @@ static void mroute_clean_tables(struct mr_table *mrt, bool all) continue; rhltable_remove(&mrt->mfc_hash, &c->mnode, ipmr_rht_params); list_del_rcu(&c->list); - call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_DEL, c, + cache = (struct mfc_cache *)c; + call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_DEL, cache, mrt->id); - mroute_netlink_event(mrt, c, RTM_DELROUTE); - ipmr_cache_put(c); + mroute_netlink_event(mrt, cache, RTM_DELROUTE); + ipmr_cache_put(cache); } if (atomic_read(&mrt->cache_resolve_queue_len) != 0) { spin_lock_bh(&mfc_unres_lock); list_for_each_entry_safe(c, tmp, &mrt->mfc_unres_queue, list) { list_del(&c->list); - mroute_netlink_event(mrt, c, RTM_DELROUTE); - ipmr_destroy_unres(mrt, c); + cache = (struct mfc_cache *)c; + mroute_netlink_event(mrt, cache, RTM_DELROUTE); + ipmr_destroy_unres(mrt, cache); } spin_unlock_bh(&mfc_unres_lock); } @@ -1683,9 +1693,9 @@ int ipmr_ioctl(struct sock *sk, int cmd, void __user *arg) rcu_read_lock(); c = ipmr_cache_find(mrt, sr.src.s_addr, sr.grp.s_addr); if (c) { - sr.pktcnt = c->mfc_un.res.pkt; - sr.bytecnt = c->mfc_un.res.bytes; - sr.wrong_if = c->mfc_un.res.wrong_if; + sr.pktcnt = c->_c.mfc_un.res.pkt; + sr.bytecnt = c->_c.mfc_un.res.bytes; + sr.wrong_if = c->_c.mfc_un.res.wrong_if; rcu_read_unlock(); if (copy_to_user(arg, &sr, sizeof(sr))) @@ -1757,9 +1767,9 @@ int ipmr_compat_ioctl(struct sock *sk, unsigned int cmd, void __user *arg) rcu_read_lock(); c = ipmr_cache_find(mrt, sr.src.s_addr, sr.grp.s_addr); if (c) { - sr.pktcnt = c->mfc_un.res.pkt; - sr.bytecnt = c->mfc_un.res.bytes; - sr.wrong_if = c->mfc_un.res.wrong_if; + sr.pktcnt = c->_c.mfc_un.res.pkt; + sr.bytecnt = c->_c.mfc_un.res.bytes; + sr.wrong_if = c->_c.mfc_un.res.wrong_if; rcu_read_unlock(); if (copy_to_user(arg, &sr, sizeof(sr))) @@ -1983,18 +1993,18 @@ static int ipmr_find_vif(struct mr_table *mrt, struct net_device *dev) /* "local" means that we should preserve one skb (for local delivery) */ static void ip_mr_forward(struct net *net, struct mr_table *mrt, struct net_device *dev, struct sk_buff *skb, - struct mfc_cache *cache, int local) + struct mfc_cache *c, int local) { int true_vifi = ipmr_find_vif(mrt, dev); int psend = -1; int vif, ct; - vif = cache->mfc_parent; - cache->mfc_un.res.pkt++; - cache->mfc_un.res.bytes += skb->len; - cache->mfc_un.res.lastuse = jiffies; + vif = c->_c.mfc_parent; + c->_c.mfc_un.res.pkt++; + c->_c.mfc_un.res.bytes += skb->len; + c->_c.mfc_un.res.lastuse = jiffies; - if (cache->mfc_origin == htonl(INADDR_ANY) && true_vifi >= 0) { + if (c->mfc_origin == htonl(INADDR_ANY) && true_vifi >= 0) { struct mfc_cache *cache_proxy; /* For an (*,G) entry, we only check that the incomming @@ -2002,7 +2012,7 @@ static void ip_mr_forward(struct net *net, struct mr_table *mrt, */ cache_proxy = ipmr_cache_find_any_parent(mrt, vif); if (cache_proxy && - cache_proxy->mfc_un.res.ttls[true_vifi] < 255) + cache_proxy->_c.mfc_un.res.ttls[true_vifi] < 255) goto forward; } @@ -2023,7 +2033,7 @@ static void ip_mr_forward(struct net *net, struct mr_table *mrt, goto dont_forward; } - cache->mfc_un.res.wrong_if++; + c->_c.mfc_un.res.wrong_if++; if (true_vifi >= 0 && mrt->mroute_do_assert && /* pimsm uses asserts, when switching from RPT to SPT, @@ -2032,10 +2042,11 @@ static void ip_mr_forward(struct net *net, struct mr_table *mrt, * large chunk of pimd to kernel. Ough... --ANK */ (mrt->mroute_do_pim || - cache->mfc_un.res.ttls[true_vifi] < 255) && + c->_c.mfc_un.res.ttls[true_vifi] < 255) && time_after(jiffies, - cache->mfc_un.res.last_assert + MFC_ASSERT_THRESH)) { - cache->mfc_un.res.last_assert = jiffies; + c->_c.mfc_un.res.last_assert + + MFC_ASSERT_THRESH)) { + c->_c.mfc_un.res.last_assert = jiffies; ipmr_cache_report(mrt, skb, true_vifi, IGMPMSG_WRONGVIF); } goto dont_forward; @@ -2046,33 +2057,33 @@ forward: mrt->vif_table[vif].bytes_in += skb->len; /* Forward the frame */ - if (cache->mfc_origin == htonl(INADDR_ANY) && - cache->mfc_mcastgrp == htonl(INADDR_ANY)) { + if (c->mfc_origin == htonl(INADDR_ANY) && + c->mfc_mcastgrp == htonl(INADDR_ANY)) { if (true_vifi >= 0 && - true_vifi != cache->mfc_parent && + true_vifi != c->_c.mfc_parent && ip_hdr(skb)->ttl > - cache->mfc_un.res.ttls[cache->mfc_parent]) { + c->_c.mfc_un.res.ttls[c->_c.mfc_parent]) { /* It's an (*,*) entry and the packet is not coming from * the upstream: forward the packet to the upstream * only. */ - psend = cache->mfc_parent; + psend = c->_c.mfc_parent; goto last_forward; } goto dont_forward; } - for (ct = cache->mfc_un.res.maxvif - 1; - ct >= cache->mfc_un.res.minvif; ct--) { + for (ct = c->_c.mfc_un.res.maxvif - 1; + ct >= c->_c.mfc_un.res.minvif; ct--) { /* For (*,G) entry, don't forward to the incoming interface */ - if ((cache->mfc_origin != htonl(INADDR_ANY) || + if ((c->mfc_origin != htonl(INADDR_ANY) || ct != true_vifi) && - ip_hdr(skb)->ttl > cache->mfc_un.res.ttls[ct]) { + ip_hdr(skb)->ttl > c->_c.mfc_un.res.ttls[ct]) { if (psend != -1) { struct sk_buff *skb2 = skb_clone(skb, GFP_ATOMIC); if (skb2) ipmr_queue_xmit(net, mrt, true_vifi, - skb2, cache, psend); + skb2, c, psend); } psend = ct; } @@ -2084,9 +2095,9 @@ last_forward: if (skb2) ipmr_queue_xmit(net, mrt, true_vifi, skb2, - cache, psend); + c, psend); } else { - ipmr_queue_xmit(net, mrt, true_vifi, skb, cache, psend); + ipmr_queue_xmit(net, mrt, true_vifi, skb, c, psend); return; } } @@ -2285,7 +2296,7 @@ drop: #endif static int __ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, - struct mfc_cache *c, struct rtmsg *rtm) + struct mr_mfc *c, struct rtmsg *rtm) { struct rta_mfc_stats mfcs; struct nlattr *mp_attr; @@ -2401,7 +2412,7 @@ int ipmr_get_route(struct net *net, struct sk_buff *skb, } read_lock(&mrt_lock); - err = __ipmr_fill_mroute(mrt, skb, cache, rtm); + err = __ipmr_fill_mroute(mrt, skb, &cache->_c, rtm); read_unlock(&mrt_lock); rcu_read_unlock(); return err; @@ -2429,7 +2440,7 @@ static int ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, goto nla_put_failure; rtm->rtm_type = RTN_MULTICAST; rtm->rtm_scope = RT_SCOPE_UNIVERSE; - if (c->mfc_flags & MFC_STATIC) + if (c->_c.mfc_flags & MFC_STATIC) rtm->rtm_protocol = RTPROT_STATIC; else rtm->rtm_protocol = RTPROT_MROUTED; @@ -2438,7 +2449,7 @@ static int ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, if (nla_put_in_addr(skb, RTA_SRC, c->mfc_origin) || nla_put_in_addr(skb, RTA_DST, c->mfc_mcastgrp)) goto nla_put_failure; - err = __ipmr_fill_mroute(mrt, skb, c, rtm); + err = __ipmr_fill_mroute(mrt, skb, &c->_c, rtm); /* do not break the dump if cache is unresolved */ if (err < 0 && err != -ENOENT) goto nla_put_failure; @@ -2479,7 +2490,8 @@ static void mroute_netlink_event(struct mr_table *mrt, struct mfc_cache *mfc, struct sk_buff *skb; int err = -ENOBUFS; - skb = nlmsg_new(mroute_msgsize(mfc->mfc_parent >= MAXVIFS, mrt->maxvif), + skb = nlmsg_new(mroute_msgsize(mfc->_c.mfc_parent >= MAXVIFS, + mrt->maxvif), GFP_ATOMIC); if (!skb) goto errout; @@ -2624,10 +2636,10 @@ errout_free: static int ipmr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) { struct net *net = sock_net(skb->sk); - struct mr_table *mrt; - struct mfc_cache *mfc; unsigned int t = 0, s_t; unsigned int e = 0, s_e; + struct mr_table *mrt; + struct mr_mfc *mfc; s_t = cb->args[0]; s_e = cb->args[1]; @@ -2642,8 +2654,8 @@ static int ipmr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) if (ipmr_fill_mroute(mrt, skb, NETLINK_CB(cb->skb).portid, cb->nlh->nlmsg_seq, - mfc, RTM_NEWROUTE, - NLM_F_MULTI) < 0) + (struct mfc_cache *)mfc, + RTM_NEWROUTE, NLM_F_MULTI) < 0) goto done; next_entry: e++; @@ -2658,8 +2670,8 @@ next_entry: if (ipmr_fill_mroute(mrt, skb, NETLINK_CB(cb->skb).portid, cb->nlh->nlmsg_seq, - mfc, RTM_NEWROUTE, - NLM_F_MULTI) < 0) { + (struct mfc_cache *)mfc, + RTM_NEWROUTE, NLM_F_MULTI) < 0) { spin_unlock_bh(&mfc_unres_lock); goto done; } @@ -3051,20 +3063,21 @@ static struct mfc_cache *ipmr_mfc_seq_idx(struct net *net, struct ipmr_mfc_iter *it, loff_t pos) { struct mr_table *mrt = it->mrt; - struct mfc_cache *mfc; + struct mr_mfc *mfc; rcu_read_lock(); it->cache = &mrt->mfc_cache_list; list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) if (pos-- == 0) - return mfc; + return (struct mfc_cache *)mfc; rcu_read_unlock(); spin_lock_bh(&mfc_unres_lock); it->cache = &mrt->mfc_unres_queue; list_for_each_entry(mfc, it->cache, list) if (pos-- == 0) - return mfc; + return (struct mfc_cache *)mfc; + spin_unlock_bh(&mfc_unres_lock); it->cache = NULL; @@ -3100,8 +3113,9 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) if (v == SEQ_START_TOKEN) return ipmr_mfc_seq_idx(net, seq->private, 0); - if (mfc->list.next != it->cache) - return list_entry(mfc->list.next, struct mfc_cache, list); + if (mfc->_c.list.next != it->cache) + return (struct mfc_cache *)(list_entry(mfc->_c.list.next, + struct mr_mfc, list)); if (it->cache == &mrt->mfc_unres_queue) goto end_of_list; @@ -3112,7 +3126,9 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) spin_lock_bh(&mfc_unres_lock); if (!list_empty(it->cache)) - return list_first_entry(it->cache, struct mfc_cache, list); + return (struct mfc_cache *)(list_first_entry(it->cache, + struct mr_mfc, + list)); end_of_list: spin_unlock_bh(&mfc_unres_lock); @@ -3147,20 +3163,20 @@ static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) seq_printf(seq, "%08X %08X %-3hd", (__force u32) mfc->mfc_mcastgrp, (__force u32) mfc->mfc_origin, - mfc->mfc_parent); + mfc->_c.mfc_parent); if (it->cache != &mrt->mfc_unres_queue) { seq_printf(seq, " %8lu %8lu %8lu", - mfc->mfc_un.res.pkt, - mfc->mfc_un.res.bytes, - mfc->mfc_un.res.wrong_if); - for (n = mfc->mfc_un.res.minvif; - n < mfc->mfc_un.res.maxvif; n++) { + mfc->_c.mfc_un.res.pkt, + mfc->_c.mfc_un.res.bytes, + mfc->_c.mfc_un.res.wrong_if); + for (n = mfc->_c.mfc_un.res.minvif; + n < mfc->_c.mfc_un.res.maxvif; n++) { if (VIF_EXISTS(mrt, n) && - mfc->mfc_un.res.ttls[n] < 255) + mfc->_c.mfc_un.res.ttls[n] < 255) seq_printf(seq, " %2d:%-3d", - n, mfc->mfc_un.res.ttls[n]); + n, mfc->_c.mfc_un.res.ttls[n]); } } else { /* unresolved mfc_caches don't contain @@ -3219,7 +3235,7 @@ static int ipmr_dump(struct net *net, struct notifier_block *nb) ipmr_for_each_table(mrt, net) { struct vif_device *v = &mrt->vif_table[0]; - struct mfc_cache *mfc; + struct mr_mfc *mfc; int vifi; /* Notifiy on table VIF entries */ @@ -3236,7 +3252,8 @@ static int ipmr_dump(struct net *net, struct notifier_block *nb) /* Notify on table MFC entries */ list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) call_ipmr_mfc_entry_notifier(nb, net, - FIB_EVENT_ENTRY_ADD, mfc, + FIB_EVENT_ENTRY_ADD, + (struct mfc_cache *)mfc, mrt->id); } diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index d50852882966..3fe254f9f9b7 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -285,7 +285,7 @@ static int ip6mr_hash_cmp(struct rhashtable_compare_arg *arg, } static const struct rhashtable_params ip6mr_rht_params = { - .head_offset = offsetof(struct mfc6_cache, mnode), + .head_offset = offsetof(struct mr_mfc, mnode), .key_offset = offsetof(struct mfc6_cache, cmparg), .key_len = sizeof(struct mfc6_cache_cmp_arg), .nelem_hint = 3, @@ -335,20 +335,20 @@ static struct mfc6_cache *ipmr_mfc_seq_idx(struct net *net, struct ipmr_mfc_iter *it, loff_t pos) { struct mr_table *mrt = it->mrt; - struct mfc6_cache *mfc; + struct mr_mfc *mfc; rcu_read_lock(); it->cache = &mrt->mfc_cache_list; list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) if (pos-- == 0) - return mfc; + return (struct mfc6_cache *)mfc; rcu_read_unlock(); spin_lock_bh(&mfc_unres_lock); it->cache = &mrt->mfc_unres_queue; list_for_each_entry(mfc, it->cache, list) if (pos-- == 0) - return mfc; + return (struct mfc6_cache *)mfc; spin_unlock_bh(&mfc_unres_lock); it->cache = NULL; @@ -492,8 +492,9 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) if (v == SEQ_START_TOKEN) return ipmr_mfc_seq_idx(net, seq->private, 0); - if (mfc->list.next != it->cache) - return list_entry(mfc->list.next, struct mfc6_cache, list); + if (mfc->_c.list.next != it->cache) + return (struct mfc6_cache *)(list_entry(mfc->_c.list.next, + struct mr_mfc, list)); if (it->cache == &mrt->mfc_unres_queue) goto end_of_list; @@ -504,7 +505,9 @@ static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) spin_lock_bh(&mfc_unres_lock); if (!list_empty(it->cache)) - return list_first_entry(it->cache, struct mfc6_cache, list); + return (struct mfc6_cache *)(list_first_entry(it->cache, + struct mr_mfc, + list)); end_of_list: spin_unlock_bh(&mfc_unres_lock); @@ -540,20 +543,20 @@ static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) seq_printf(seq, "%pI6 %pI6 %-3hd", &mfc->mf6c_mcastgrp, &mfc->mf6c_origin, - mfc->mf6c_parent); + mfc->_c.mfc_parent); if (it->cache != &mrt->mfc_unres_queue) { seq_printf(seq, " %8lu %8lu %8lu", - mfc->mfc_un.res.pkt, - mfc->mfc_un.res.bytes, - mfc->mfc_un.res.wrong_if); - for (n = mfc->mfc_un.res.minvif; - n < mfc->mfc_un.res.maxvif; n++) { + mfc->_c.mfc_un.res.pkt, + mfc->_c.mfc_un.res.bytes, + mfc->_c.mfc_un.res.wrong_if); + for (n = mfc->_c.mfc_un.res.minvif; + n < mfc->_c.mfc_un.res.maxvif; n++) { if (VIF_EXISTS(mrt, n) && - mfc->mfc_un.res.ttls[n] < 255) + mfc->_c.mfc_un.res.ttls[n] < 255) seq_printf(seq, - " %2d:%-3d", - n, mfc->mfc_un.res.ttls[n]); + " %2d:%-3d", n, + mfc->_c.mfc_un.res.ttls[n]); } } else { /* unresolved mfc_caches don't contain @@ -800,14 +803,14 @@ static int mif6_delete(struct mr_table *mrt, int vifi, int notify, static inline void ip6mr_cache_free_rcu(struct rcu_head *head) { - struct mfc6_cache *c = container_of(head, struct mfc6_cache, rcu); + struct mr_mfc *c = container_of(head, struct mr_mfc, rcu); - kmem_cache_free(mrt_cachep, c); + kmem_cache_free(mrt_cachep, (struct mfc6_cache *)c); } static inline void ip6mr_cache_free(struct mfc6_cache *c) { - call_rcu(&c->rcu, ip6mr_cache_free_rcu); + call_rcu(&c->_c.rcu, ip6mr_cache_free_rcu); } /* Destroy an unresolved cache entry, killing queued skbs @@ -821,7 +824,7 @@ static void ip6mr_destroy_unres(struct mr_table *mrt, struct mfc6_cache *c) atomic_dec(&mrt->cache_resolve_queue_len); - while ((skb = skb_dequeue(&c->mfc_un.unres.unresolved)) != NULL) { + while ((skb = skb_dequeue(&c->_c.mfc_un.unres.unresolved)) != NULL) { if (ipv6_hdr(skb)->version == 0) { struct nlmsghdr *nlh = skb_pull(skb, sizeof(struct ipv6hdr)); @@ -844,7 +847,7 @@ static void ipmr_do_expire_process(struct mr_table *mrt) { unsigned long now = jiffies; unsigned long expires = 10 * HZ; - struct mfc6_cache *c, *next; + struct mr_mfc *c, *next; list_for_each_entry_safe(c, next, &mrt->mfc_unres_queue, list) { if (time_after(c->mfc_un.unres.expires, now)) { @@ -856,8 +859,8 @@ static void ipmr_do_expire_process(struct mr_table *mrt) } list_del(&c->list); - mr6_netlink_event(mrt, c, RTM_DELROUTE); - ip6mr_destroy_unres(mrt, c); + mr6_netlink_event(mrt, (struct mfc6_cache *)c, RTM_DELROUTE); + ip6mr_destroy_unres(mrt, (struct mfc6_cache *)c); } if (!list_empty(&mrt->mfc_unres_queue)) @@ -882,7 +885,7 @@ static void ipmr_expire_process(struct timer_list *t) /* Fill oifs list. It is called under write locked mrt_lock. */ static void ip6mr_update_thresholds(struct mr_table *mrt, - struct mfc6_cache *cache, + struct mr_mfc *cache, unsigned char *ttls) { int vifi; @@ -986,11 +989,11 @@ static struct mfc6_cache *ip6mr_cache_find(struct mr_table *mrt, .mf6c_mcastgrp = *mcastgrp, }; struct rhlist_head *tmp, *list; - struct mfc6_cache *c; + struct mr_mfc *c; list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) - return c; + return (struct mfc6_cache *)c; return NULL; } @@ -1004,12 +1007,12 @@ static struct mfc6_cache *ip6mr_cache_find_any_parent(struct mr_table *mrt, .mf6c_mcastgrp = in6addr_any, }; struct rhlist_head *tmp, *list; - struct mfc6_cache *c; + struct mr_mfc *c; list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) if (c->mfc_un.res.ttls[mifi] < 255) - return c; + return (struct mfc6_cache *)c; return NULL; } @@ -1024,7 +1027,8 @@ static struct mfc6_cache *ip6mr_cache_find_any(struct mr_table *mrt, .mf6c_mcastgrp = *mcastgrp, }; struct rhlist_head *tmp, *list; - struct mfc6_cache *c, *proxy; + struct mr_mfc *c; + struct mfc6_cache *proxy; if (ipv6_addr_any(mcastgrp)) goto skip; @@ -1032,12 +1036,12 @@ static struct mfc6_cache *ip6mr_cache_find_any(struct mr_table *mrt, list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) { if (c->mfc_un.res.ttls[mifi] < 255) - return c; + return (struct mfc6_cache *)c; /* It's ok if the mifi is part of the static tree */ - proxy = ip6mr_cache_find_any_parent(mrt, c->mf6c_parent); - if (proxy && proxy->mfc_un.res.ttls[mifi] < 255) - return c; + proxy = ip6mr_cache_find_any_parent(mrt, c->mfc_parent); + if (proxy && proxy->_c.mfc_un.res.ttls[mifi] < 255) + return (struct mfc6_cache *)c; } skip: @@ -1056,12 +1060,12 @@ ip6mr_cache_find_parent(struct mr_table *mrt, .mf6c_mcastgrp = *mcastgrp, }; struct rhlist_head *tmp, *list; - struct mfc6_cache *c; + struct mr_mfc *c; list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); rhl_for_each_entry_rcu(c, tmp, list, mnode) - if (parent == -1 || parent == c->mf6c_parent) - return c; + if (parent == -1 || parent == c->mfc_parent) + return (struct mfc6_cache *)c; return NULL; } @@ -1074,8 +1078,8 @@ static struct mfc6_cache *ip6mr_cache_alloc(void) struct mfc6_cache *c = kmem_cache_zalloc(mrt_cachep, GFP_KERNEL); if (!c) return NULL; - c->mfc_un.res.last_assert = jiffies - MFC_ASSERT_THRESH - 1; - c->mfc_un.res.minvif = MAXMIFS; + c->_c.mfc_un.res.last_assert = jiffies - MFC_ASSERT_THRESH - 1; + c->_c.mfc_un.res.minvif = MAXMIFS; return c; } @@ -1084,8 +1088,8 @@ static struct mfc6_cache *ip6mr_cache_alloc_unres(void) struct mfc6_cache *c = kmem_cache_zalloc(mrt_cachep, GFP_ATOMIC); if (!c) return NULL; - skb_queue_head_init(&c->mfc_un.unres.unresolved); - c->mfc_un.unres.expires = jiffies + 10 * HZ; + skb_queue_head_init(&c->_c.mfc_un.unres.unresolved); + c->_c.mfc_un.unres.expires = jiffies + 10 * HZ; return c; } @@ -1102,7 +1106,7 @@ static void ip6mr_cache_resolve(struct net *net, struct mr_table *mrt, * Play the pending entries through our router */ - while ((skb = __skb_dequeue(&uc->mfc_un.unres.unresolved))) { + while ((skb = __skb_dequeue(&uc->_c.mfc_un.unres.unresolved))) { if (ipv6_hdr(skb)->version == 0) { struct nlmsghdr *nlh = skb_pull(skb, sizeof(struct ipv6hdr)); @@ -1221,19 +1225,16 @@ static int ip6mr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, return ret; } -/* - * Queue a packet for resolution. It gets locked cache entry! - */ - -static int -ip6mr_cache_unresolved(struct mr_table *mrt, mifi_t mifi, struct sk_buff *skb) +/* Queue a packet for resolution. It gets locked cache entry! */ +static int ip6mr_cache_unresolved(struct mr_table *mrt, mifi_t mifi, + struct sk_buff *skb) { + struct mfc6_cache *c; bool found = false; int err; - struct mfc6_cache *c; spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(c, &mrt->mfc_unres_queue, list) { + list_for_each_entry(c, &mrt->mfc_unres_queue, _c.list) { if (ipv6_addr_equal(&c->mf6c_mcastgrp, &ipv6_hdr(skb)->daddr) && ipv6_addr_equal(&c->mf6c_origin, &ipv6_hdr(skb)->saddr)) { found = true; @@ -1254,10 +1255,8 @@ ip6mr_cache_unresolved(struct mr_table *mrt, mifi_t mifi, struct sk_buff *skb) return -ENOBUFS; } - /* - * Fill in the new cache entry - */ - c->mf6c_parent = -1; + /* Fill in the new cache entry */ + c->_c.mfc_parent = -1; c->mf6c_origin = ipv6_hdr(skb)->saddr; c->mf6c_mcastgrp = ipv6_hdr(skb)->daddr; @@ -1277,20 +1276,18 @@ ip6mr_cache_unresolved(struct mr_table *mrt, mifi_t mifi, struct sk_buff *skb) } atomic_inc(&mrt->cache_resolve_queue_len); - list_add(&c->list, &mrt->mfc_unres_queue); + list_add(&c->_c.list, &mrt->mfc_unres_queue); mr6_netlink_event(mrt, c, RTM_NEWROUTE); ipmr_do_expire_process(mrt); } - /* - * See if we can append the packet - */ - if (c->mfc_un.unres.unresolved.qlen > 3) { + /* See if we can append the packet */ + if (c->_c.mfc_un.unres.unresolved.qlen > 3) { kfree_skb(skb); err = -ENOBUFS; } else { - skb_queue_tail(&c->mfc_un.unres.unresolved, skb); + skb_queue_tail(&c->_c.mfc_un.unres.unresolved, skb); err = 0; } @@ -1314,8 +1311,8 @@ static int ip6mr_mfc_delete(struct mr_table *mrt, struct mf6cctl *mfc, rcu_read_unlock(); if (!c) return -ENOENT; - rhltable_remove(&mrt->mfc_hash, &c->mnode, ip6mr_rht_params); - list_del_rcu(&c->list); + rhltable_remove(&mrt->mfc_hash, &c->_c.mnode, ip6mr_rht_params); + list_del_rcu(&c->_c.list); mr6_netlink_event(mrt, c, RTM_DELROUTE); ip6mr_cache_free(c); @@ -1454,6 +1451,7 @@ static int ip6mr_mfc_add(struct net *net, struct mr_table *mrt, { unsigned char ttls[MAXMIFS]; struct mfc6_cache *uc, *c; + struct mr_mfc *_uc; bool found; int i, err; @@ -1473,10 +1471,10 @@ static int ip6mr_mfc_add(struct net *net, struct mr_table *mrt, rcu_read_unlock(); if (c) { write_lock_bh(&mrt_lock); - c->mf6c_parent = mfc->mf6cc_parent; - ip6mr_update_thresholds(mrt, c, ttls); + c->_c.mfc_parent = mfc->mf6cc_parent; + ip6mr_update_thresholds(mrt, &c->_c, ttls); if (!mrtsock) - c->mfc_flags |= MFC_STATIC; + c->_c.mfc_flags |= MFC_STATIC; write_unlock_bh(&mrt_lock); mr6_netlink_event(mrt, c, RTM_NEWROUTE); return 0; @@ -1492,29 +1490,30 @@ static int ip6mr_mfc_add(struct net *net, struct mr_table *mrt, c->mf6c_origin = mfc->mf6cc_origin.sin6_addr; c->mf6c_mcastgrp = mfc->mf6cc_mcastgrp.sin6_addr; - c->mf6c_parent = mfc->mf6cc_parent; - ip6mr_update_thresholds(mrt, c, ttls); + c->_c.mfc_parent = mfc->mf6cc_parent; + ip6mr_update_thresholds(mrt, &c->_c, ttls); if (!mrtsock) - c->mfc_flags |= MFC_STATIC; + c->_c.mfc_flags |= MFC_STATIC; - err = rhltable_insert_key(&mrt->mfc_hash, &c->cmparg, &c->mnode, + err = rhltable_insert_key(&mrt->mfc_hash, &c->cmparg, &c->_c.mnode, ip6mr_rht_params); if (err) { pr_err("ip6mr: rhtable insert error %d\n", err); ip6mr_cache_free(c); return err; } - list_add_tail_rcu(&c->list, &mrt->mfc_cache_list); + list_add_tail_rcu(&c->_c.list, &mrt->mfc_cache_list); /* Check to see if we resolved a queued list. If so we * need to send on the frames and tidy up. */ found = false; spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(uc, &mrt->mfc_unres_queue, list) { + list_for_each_entry(_uc, &mrt->mfc_unres_queue, list) { + uc = (struct mfc6_cache *)_uc; if (ipv6_addr_equal(&uc->mf6c_origin, &c->mf6c_origin) && ipv6_addr_equal(&uc->mf6c_mcastgrp, &c->mf6c_mcastgrp)) { - list_del(&uc->list); + list_del(&_uc->list); atomic_dec(&mrt->cache_resolve_queue_len); found = true; break; @@ -1538,7 +1537,7 @@ static int ip6mr_mfc_add(struct net *net, struct mr_table *mrt, static void mroute_clean_tables(struct mr_table *mrt, bool all) { - struct mfc6_cache *c, *tmp; + struct mr_mfc *c, *tmp; LIST_HEAD(list); int i; @@ -1556,16 +1555,17 @@ static void mroute_clean_tables(struct mr_table *mrt, bool all) continue; rhltable_remove(&mrt->mfc_hash, &c->mnode, ip6mr_rht_params); list_del_rcu(&c->list); - mr6_netlink_event(mrt, c, RTM_DELROUTE); - ip6mr_cache_free(c); + mr6_netlink_event(mrt, (struct mfc6_cache *)c, RTM_DELROUTE); + ip6mr_cache_free((struct mfc6_cache *)c); } if (atomic_read(&mrt->cache_resolve_queue_len) != 0) { spin_lock_bh(&mfc_unres_lock); list_for_each_entry_safe(c, tmp, &mrt->mfc_unres_queue, list) { list_del(&c->list); - mr6_netlink_event(mrt, c, RTM_DELROUTE); - ip6mr_destroy_unres(mrt, c); + mr6_netlink_event(mrt, (struct mfc6_cache *)c, + RTM_DELROUTE); + ip6mr_destroy_unres(mrt, (struct mfc6_cache *)c); } spin_unlock_bh(&mfc_unres_lock); } @@ -1899,9 +1899,9 @@ int ip6mr_ioctl(struct sock *sk, int cmd, void __user *arg) rcu_read_lock(); c = ip6mr_cache_find(mrt, &sr.src.sin6_addr, &sr.grp.sin6_addr); if (c) { - sr.pktcnt = c->mfc_un.res.pkt; - sr.bytecnt = c->mfc_un.res.bytes; - sr.wrong_if = c->mfc_un.res.wrong_if; + sr.pktcnt = c->_c.mfc_un.res.pkt; + sr.bytecnt = c->_c.mfc_un.res.bytes; + sr.wrong_if = c->_c.mfc_un.res.wrong_if; rcu_read_unlock(); if (copy_to_user(arg, &sr, sizeof(sr))) @@ -1973,9 +1973,9 @@ int ip6mr_compat_ioctl(struct sock *sk, unsigned int cmd, void __user *arg) rcu_read_lock(); c = ip6mr_cache_find(mrt, &sr.src.sin6_addr, &sr.grp.sin6_addr); if (c) { - sr.pktcnt = c->mfc_un.res.pkt; - sr.bytecnt = c->mfc_un.res.bytes; - sr.wrong_if = c->mfc_un.res.wrong_if; + sr.pktcnt = c->_c.mfc_un.res.pkt; + sr.bytecnt = c->_c.mfc_un.res.bytes; + sr.wrong_if = c->_c.mfc_un.res.wrong_if; rcu_read_unlock(); if (copy_to_user(arg, &sr, sizeof(sr))) @@ -2089,18 +2089,18 @@ static int ip6mr_find_vif(struct mr_table *mrt, struct net_device *dev) } static void ip6_mr_forward(struct net *net, struct mr_table *mrt, - struct sk_buff *skb, struct mfc6_cache *cache) + struct sk_buff *skb, struct mfc6_cache *c) { int psend = -1; int vif, ct; int true_vifi = ip6mr_find_vif(mrt, skb->dev); - vif = cache->mf6c_parent; - cache->mfc_un.res.pkt++; - cache->mfc_un.res.bytes += skb->len; - cache->mfc_un.res.lastuse = jiffies; + vif = c->_c.mfc_parent; + c->_c.mfc_un.res.pkt++; + c->_c.mfc_un.res.bytes += skb->len; + c->_c.mfc_un.res.lastuse = jiffies; - if (ipv6_addr_any(&cache->mf6c_origin) && true_vifi >= 0) { + if (ipv6_addr_any(&c->mf6c_origin) && true_vifi >= 0) { struct mfc6_cache *cache_proxy; /* For an (*,G) entry, we only check that the incoming @@ -2109,7 +2109,7 @@ static void ip6_mr_forward(struct net *net, struct mr_table *mrt, rcu_read_lock(); cache_proxy = ip6mr_cache_find_any_parent(mrt, vif); if (cache_proxy && - cache_proxy->mfc_un.res.ttls[true_vifi] < 255) { + cache_proxy->_c.mfc_un.res.ttls[true_vifi] < 255) { rcu_read_unlock(); goto forward; } @@ -2120,7 +2120,7 @@ static void ip6_mr_forward(struct net *net, struct mr_table *mrt, * Wrong interface: drop packet and (maybe) send PIM assert. */ if (mrt->vif_table[vif].dev != skb->dev) { - cache->mfc_un.res.wrong_if++; + c->_c.mfc_un.res.wrong_if++; if (true_vifi >= 0 && mrt->mroute_do_assert && /* pimsm uses asserts, when switching from RPT to SPT, @@ -2129,10 +2129,11 @@ static void ip6_mr_forward(struct net *net, struct mr_table *mrt, large chunk of pimd to kernel. Ough... --ANK */ (mrt->mroute_do_pim || - cache->mfc_un.res.ttls[true_vifi] < 255) && + c->_c.mfc_un.res.ttls[true_vifi] < 255) && time_after(jiffies, - cache->mfc_un.res.last_assert + MFC_ASSERT_THRESH)) { - cache->mfc_un.res.last_assert = jiffies; + c->_c.mfc_un.res.last_assert + + MFC_ASSERT_THRESH)) { + c->_c.mfc_un.res.last_assert = jiffies; ip6mr_cache_report(mrt, skb, true_vifi, MRT6MSG_WRONGMIF); } goto dont_forward; @@ -2145,36 +2146,38 @@ forward: /* * Forward the frame */ - if (ipv6_addr_any(&cache->mf6c_origin) && - ipv6_addr_any(&cache->mf6c_mcastgrp)) { + if (ipv6_addr_any(&c->mf6c_origin) && + ipv6_addr_any(&c->mf6c_mcastgrp)) { if (true_vifi >= 0 && - true_vifi != cache->mf6c_parent && + true_vifi != c->_c.mfc_parent && ipv6_hdr(skb)->hop_limit > - cache->mfc_un.res.ttls[cache->mf6c_parent]) { + c->_c.mfc_un.res.ttls[c->_c.mfc_parent]) { /* It's an (*,*) entry and the packet is not coming from * the upstream: forward the packet to the upstream * only. */ - psend = cache->mf6c_parent; + psend = c->_c.mfc_parent; goto last_forward; } goto dont_forward; } - for (ct = cache->mfc_un.res.maxvif - 1; ct >= cache->mfc_un.res.minvif; ct--) { + for (ct = c->_c.mfc_un.res.maxvif - 1; + ct >= c->_c.mfc_un.res.minvif; ct--) { /* For (*,G) entry, don't forward to the incoming interface */ - if ((!ipv6_addr_any(&cache->mf6c_origin) || ct != true_vifi) && - ipv6_hdr(skb)->hop_limit > cache->mfc_un.res.ttls[ct]) { + if ((!ipv6_addr_any(&c->mf6c_origin) || ct != true_vifi) && + ipv6_hdr(skb)->hop_limit > c->_c.mfc_un.res.ttls[ct]) { if (psend != -1) { struct sk_buff *skb2 = skb_clone(skb, GFP_ATOMIC); if (skb2) - ip6mr_forward2(net, mrt, skb2, cache, psend); + ip6mr_forward2(net, mrt, skb2, + c, psend); } psend = ct; } } last_forward: if (psend != -1) { - ip6mr_forward2(net, mrt, skb, cache, psend); + ip6mr_forward2(net, mrt, skb, c, psend); return; } @@ -2252,21 +2255,22 @@ static int __ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, int ct; /* If cache is unresolved, don't try to parse IIF and OIF */ - if (c->mf6c_parent >= MAXMIFS) { + if (c->_c.mfc_parent >= MAXMIFS) { rtm->rtm_flags |= RTNH_F_UNRESOLVED; return -ENOENT; } - if (VIF_EXISTS(mrt, c->mf6c_parent) && + if (VIF_EXISTS(mrt, c->_c.mfc_parent) && nla_put_u32(skb, RTA_IIF, - mrt->vif_table[c->mf6c_parent].dev->ifindex) < 0) + mrt->vif_table[c->_c.mfc_parent].dev->ifindex) < 0) return -EMSGSIZE; mp_attr = nla_nest_start(skb, RTA_MULTIPATH); if (!mp_attr) return -EMSGSIZE; - for (ct = c->mfc_un.res.minvif; ct < c->mfc_un.res.maxvif; ct++) { - if (VIF_EXISTS(mrt, ct) && c->mfc_un.res.ttls[ct] < 255) { + for (ct = c->_c.mfc_un.res.minvif; + ct < c->_c.mfc_un.res.maxvif; ct++) { + if (VIF_EXISTS(mrt, ct) && c->_c.mfc_un.res.ttls[ct] < 255) { nhp = nla_reserve_nohdr(skb, sizeof(*nhp)); if (!nhp) { nla_nest_cancel(skb, mp_attr); @@ -2274,7 +2278,7 @@ static int __ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, } nhp->rtnh_flags = 0; - nhp->rtnh_hops = c->mfc_un.res.ttls[ct]; + nhp->rtnh_hops = c->_c.mfc_un.res.ttls[ct]; nhp->rtnh_ifindex = mrt->vif_table[ct].dev->ifindex; nhp->rtnh_len = sizeof(*nhp); } @@ -2282,12 +2286,12 @@ static int __ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, nla_nest_end(skb, mp_attr); - lastuse = READ_ONCE(c->mfc_un.res.lastuse); + lastuse = READ_ONCE(c->_c.mfc_un.res.lastuse); lastuse = time_after_eq(jiffies, lastuse) ? jiffies - lastuse : 0; - mfcs.mfcs_packets = c->mfc_un.res.pkt; - mfcs.mfcs_bytes = c->mfc_un.res.bytes; - mfcs.mfcs_wrong_if = c->mfc_un.res.wrong_if; + mfcs.mfcs_packets = c->_c.mfc_un.res.pkt; + mfcs.mfcs_bytes = c->_c.mfc_un.res.bytes; + mfcs.mfcs_wrong_if = c->_c.mfc_un.res.wrong_if; if (nla_put_64bit(skb, RTA_MFC_STATS, sizeof(mfcs), &mfcs, RTA_PAD) || nla_put_u64_64bit(skb, RTA_EXPIRES, jiffies_to_clock_t(lastuse), RTA_PAD)) @@ -2363,7 +2367,7 @@ int ip6mr_get_route(struct net *net, struct sk_buff *skb, struct rtmsg *rtm, } if (rtm->rtm_flags & RTM_F_NOTIFY) - cache->mfc_flags |= MFC_NOTIFY; + cache->_c.mfc_flags |= MFC_NOTIFY; err = __ip6mr_fill_mroute(mrt, skb, cache, rtm); read_unlock(&mrt_lock); @@ -2392,7 +2396,7 @@ static int ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, goto nla_put_failure; rtm->rtm_type = RTN_MULTICAST; rtm->rtm_scope = RT_SCOPE_UNIVERSE; - if (c->mfc_flags & MFC_STATIC) + if (c->_c.mfc_flags & MFC_STATIC) rtm->rtm_protocol = RTPROT_STATIC; else rtm->rtm_protocol = RTPROT_MROUTED; @@ -2442,7 +2446,7 @@ static void mr6_netlink_event(struct mr_table *mrt, struct mfc6_cache *mfc, struct sk_buff *skb; int err = -ENOBUFS; - skb = nlmsg_new(mr6_msgsize(mfc->mf6c_parent >= MAXMIFS, mrt->maxvif), + skb = nlmsg_new(mr6_msgsize(mfc->_c.mfc_parent >= MAXMIFS, mrt->maxvif), GFP_ATOMIC); if (!skb) goto errout; @@ -2528,10 +2532,10 @@ errout: static int ip6mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) { struct net *net = sock_net(skb->sk); - struct mr_table *mrt; - struct mfc6_cache *mfc; unsigned int t = 0, s_t; unsigned int e = 0, s_e; + struct mr_table *mrt; + struct mr_mfc *mfc; s_t = cb->args[0]; s_e = cb->args[1]; @@ -2546,8 +2550,8 @@ static int ip6mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) if (ip6mr_fill_mroute(mrt, skb, NETLINK_CB(cb->skb).portid, cb->nlh->nlmsg_seq, - mfc, RTM_NEWROUTE, - NLM_F_MULTI) < 0) + (struct mfc6_cache *)mfc, + RTM_NEWROUTE, NLM_F_MULTI) < 0) goto done; next_entry: e++; @@ -2562,8 +2566,8 @@ next_entry: if (ip6mr_fill_mroute(mrt, skb, NETLINK_CB(cb->skb).portid, cb->nlh->nlmsg_seq, - mfc, RTM_NEWROUTE, - NLM_F_MULTI) < 0) { + (struct mfc6_cache *)mfc, + RTM_NEWROUTE, NLM_F_MULTI) < 0) { spin_unlock_bh(&mfc_unres_lock); goto done; } -- cgit v1.2.3 From 845c9a7ae7f5342ba42280c3a2f2aa92bce641d7 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:35 +0200 Subject: ipmr, ip6mr: Unite logic for searching in MFC cache ipmr and ip6mr utilize the exact same methods for searching the hashed resolved connections, difference being only in the construction of the hash comparison key. In order to unite the flow, introduce an mr_table operation set that would contain the protocol specific information required for common flows, in this case - the hash parameters and a comparison key representing a (*,*) route. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute_base.h | 52 +++++++++++++++++++++++++++++-- net/ipv4/ipmr.c | 71 ++++++++++--------------------------------- net/ipv4/ipmr_base.c | 54 +++++++++++++++++++++++++++++++-- net/ipv6/ip6mr.c | 74 +++++++++++---------------------------------- 4 files changed, 134 insertions(+), 117 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 2769e2f98b32..46a082e25dab 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -89,10 +89,23 @@ struct mr_mfc { struct rcu_head rcu; }; +struct mr_table; + +/** + * struct mr_table_ops - callbacks and info for protocol-specific ops + * @rht_params: parameters for accessing the MFC hash + * @cmparg_any: a hash key to be used for matching on (*,*) routes + */ +struct mr_table_ops { + const struct rhashtable_params *rht_params; + void *cmparg_any; +}; + /** * struct mr_table - a multicast routing table * @list: entry within a list of multicast routing tables * @net: net where this table belongs + * @ops: protocol specific operations * @id: identifier of the table * @mroute_sk: socket associated with the table * @ipmr_expire_timer: timer for handling unresolved routes @@ -109,6 +122,7 @@ struct mr_mfc { struct mr_table { struct list_head list; possible_net_t net; + struct mr_table_ops ops; u32 id; struct sock __rcu *mroute_sk; struct timer_list ipmr_expire_timer; @@ -133,10 +147,19 @@ void vif_device_init(struct vif_device *v, struct mr_table * mr_table_alloc(struct net *net, u32 id, - const struct rhashtable_params *rht_params, + struct mr_table_ops *ops, void (*expire_func)(struct timer_list *t), void (*table_set)(struct mr_table *mrt, struct net *net)); + +/* These actually return 'struct mr_mfc *', but to avoid need for explicit + * castings they simply return void. + */ +void *mr_mfc_find_parent(struct mr_table *mrt, + void *hasharg, int parent); +void *mr_mfc_find_any_parent(struct mr_table *mrt, int vifi); +void *mr_mfc_find_any(struct mr_table *mrt, int vifi, void *hasharg); + #else static inline void vif_device_init(struct vif_device *v, struct net_device *dev, @@ -147,14 +170,37 @@ static inline void vif_device_init(struct vif_device *v, { } -static inline struct mr_table * +static inline void * mr_table_alloc(struct net *net, u32 id, - const struct rhashtable_params *rht_params, + struct mr_table_ops *ops, void (*expire_func)(struct timer_list *t), void (*table_set)(struct mr_table *mrt, struct net *net)) { return NULL; } + +static inline void *mr_mfc_find_parent(struct mr_table *mrt, + void *hasharg, int parent) +{ + return NULL; +} + +static inline void *mr_mfc_find_any_parent(struct mr_table *mrt, + int vifi) +{ + return NULL; +} + +static inline struct mr_mfc *mr_mfc_find_any(struct mr_table *mrt, + int vifi, void *hasharg) +{ + return NULL; +} #endif + +static inline void *mr_mfc_find(struct mr_table *mrt, void *hasharg) +{ + return mr_mfc_find_parent(mrt, hasharg, -1); +} #endif diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 3f7515086e85..00898c319cc5 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -360,6 +360,16 @@ static void ipmr_new_table_set(struct mr_table *mrt, #endif } +static struct mfc_cache_cmp_arg ipmr_mr_table_ops_cmparg_any = { + .mfc_mcastgrp = htonl(INADDR_ANY), + .mfc_origin = htonl(INADDR_ANY), +}; + +static struct mr_table_ops ipmr_mr_table_ops = { + .rht_params = &ipmr_rht_params, + .cmparg_any = &ipmr_mr_table_ops_cmparg_any, +}; + static struct mr_table *ipmr_new_table(struct net *net, u32 id) { struct mr_table *mrt; @@ -372,7 +382,7 @@ static struct mr_table *ipmr_new_table(struct net *net, u32 id) if (mrt) return mrt; - return mr_table_alloc(net, id, &ipmr_rht_params, + return mr_table_alloc(net, id, &ipmr_mr_table_ops, ipmr_expire_process, ipmr_new_table_set); } @@ -973,33 +983,8 @@ static struct mfc_cache *ipmr_cache_find(struct mr_table *mrt, .mfc_mcastgrp = mcastgrp, .mfc_origin = origin }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; - - list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) - return (struct mfc_cache *)c; - - return NULL; -} - -/* Look for a (*,*,oif) entry */ -static struct mfc_cache *ipmr_cache_find_any_parent(struct mr_table *mrt, - int vifi) -{ - struct mfc_cache_cmp_arg arg = { - .mfc_mcastgrp = htonl(INADDR_ANY), - .mfc_origin = htonl(INADDR_ANY) - }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; - - list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) - if (c->mfc_un.res.ttls[vifi] < 255) - return (struct mfc_cache *)c; - return NULL; + return mr_mfc_find(mrt, &arg); } /* Look for a (*,G) entry */ @@ -1010,27 +995,10 @@ static struct mfc_cache *ipmr_cache_find_any(struct mr_table *mrt, .mfc_mcastgrp = mcastgrp, .mfc_origin = htonl(INADDR_ANY) }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; if (mcastgrp == htonl(INADDR_ANY)) - goto skip; - - list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) { - struct mfc_cache *proxy; - - if (c->mfc_un.res.ttls[vifi] < 255) - return (struct mfc_cache *)c; - - /* It's ok if the vifi is part of the static tree */ - proxy = ipmr_cache_find_any_parent(mrt, c->mfc_parent); - if (proxy && proxy->_c.mfc_un.res.ttls[vifi] < 255) - return (struct mfc_cache *)c; - } - -skip: - return ipmr_cache_find_any_parent(mrt, vifi); + return mr_mfc_find_any_parent(mrt, vifi); + return mr_mfc_find_any(mrt, vifi, &arg); } /* Look for a (S,G,iif) entry if parent != -1 */ @@ -1042,15 +1010,8 @@ static struct mfc_cache *ipmr_cache_find_parent(struct mr_table *mrt, .mfc_mcastgrp = mcastgrp, .mfc_origin = origin, }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; - list = rhltable_lookup(&mrt->mfc_hash, &arg, ipmr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) - if (parent == -1 || parent == c->mfc_parent) - return (struct mfc_cache *)c; - - return NULL; + return mr_mfc_find_parent(mrt, &arg, parent); } /* Allocate a multicast cache entry */ @@ -2010,7 +1971,7 @@ static void ip_mr_forward(struct net *net, struct mr_table *mrt, /* For an (*,G) entry, we only check that the incomming * interface is part of the static tree. */ - cache_proxy = ipmr_cache_find_any_parent(mrt, vif); + cache_proxy = mr_mfc_find_any_parent(mrt, vif); if (cache_proxy && cache_proxy->_c.mfc_un.res.ttls[true_vifi] < 255) goto forward; diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c index 3e21a5806d0e..172f92acffef 100644 --- a/net/ipv4/ipmr_base.c +++ b/net/ipv4/ipmr_base.c @@ -29,7 +29,7 @@ EXPORT_SYMBOL(vif_device_init); struct mr_table * mr_table_alloc(struct net *net, u32 id, - const struct rhashtable_params *rht_params, + struct mr_table_ops *ops, void (*expire_func)(struct timer_list *t), void (*table_set)(struct mr_table *mrt, struct net *net)) @@ -42,7 +42,8 @@ mr_table_alloc(struct net *net, u32 id, mrt->id = id; write_pnet(&mrt->net, net); - rhltable_init(&mrt->mfc_hash, rht_params); + mrt->ops = *ops; + rhltable_init(&mrt->mfc_hash, mrt->ops.rht_params); INIT_LIST_HEAD(&mrt->mfc_cache_list); INIT_LIST_HEAD(&mrt->mfc_unres_queue); @@ -53,3 +54,52 @@ mr_table_alloc(struct net *net, u32 id, return mrt; } EXPORT_SYMBOL(mr_table_alloc); + +void *mr_mfc_find_parent(struct mr_table *mrt, void *hasharg, int parent) +{ + struct rhlist_head *tmp, *list; + struct mr_mfc *c; + + list = rhltable_lookup(&mrt->mfc_hash, hasharg, *mrt->ops.rht_params); + rhl_for_each_entry_rcu(c, tmp, list, mnode) + if (parent == -1 || parent == c->mfc_parent) + return c; + + return NULL; +} +EXPORT_SYMBOL(mr_mfc_find_parent); + +void *mr_mfc_find_any_parent(struct mr_table *mrt, int vifi) +{ + struct rhlist_head *tmp, *list; + struct mr_mfc *c; + + list = rhltable_lookup(&mrt->mfc_hash, mrt->ops.cmparg_any, + *mrt->ops.rht_params); + rhl_for_each_entry_rcu(c, tmp, list, mnode) + if (c->mfc_un.res.ttls[vifi] < 255) + return c; + + return NULL; +} +EXPORT_SYMBOL(mr_mfc_find_any_parent); + +void *mr_mfc_find_any(struct mr_table *mrt, int vifi, void *hasharg) +{ + struct rhlist_head *tmp, *list; + struct mr_mfc *c, *proxy; + + list = rhltable_lookup(&mrt->mfc_hash, hasharg, *mrt->ops.rht_params); + rhl_for_each_entry_rcu(c, tmp, list, mnode) { + if (c->mfc_un.res.ttls[vifi] < 255) + return c; + + /* It's ok if the vifi is part of the static tree */ + proxy = mr_mfc_find_any_parent(mrt, c->mfc_parent); + if (proxy && proxy->mfc_un.res.ttls[vifi] < 255) + return c; + } + + return mr_mfc_find_any_parent(mrt, vifi); +} +EXPORT_SYMBOL(mr_mfc_find_any); diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index 3fe254f9f9b7..ea902a952fb6 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -302,6 +302,16 @@ static void ip6mr_new_table_set(struct mr_table *mrt, #endif } +static struct mfc6_cache_cmp_arg ip6mr_mr_table_ops_cmparg_any = { + .mf6c_origin = IN6ADDR_ANY_INIT, + .mf6c_mcastgrp = IN6ADDR_ANY_INIT, +}; + +static struct mr_table_ops ip6mr_mr_table_ops = { + .rht_params = &ip6mr_rht_params, + .cmparg_any = &ip6mr_mr_table_ops_cmparg_any, +}; + static struct mr_table *ip6mr_new_table(struct net *net, u32 id) { struct mr_table *mrt; @@ -310,7 +320,7 @@ static struct mr_table *ip6mr_new_table(struct net *net, u32 id) if (mrt) return mrt; - return mr_table_alloc(net, id, &ip6mr_rht_params, + return mr_table_alloc(net, id, &ip6mr_mr_table_ops, ipmr_expire_process, ip6mr_new_table_set); } @@ -988,33 +998,8 @@ static struct mfc6_cache *ip6mr_cache_find(struct mr_table *mrt, .mf6c_origin = *origin, .mf6c_mcastgrp = *mcastgrp, }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; - - list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) - return (struct mfc6_cache *)c; - return NULL; -} - -/* Look for a (*,*,oif) entry */ -static struct mfc6_cache *ip6mr_cache_find_any_parent(struct mr_table *mrt, - mifi_t mifi) -{ - struct mfc6_cache_cmp_arg arg = { - .mf6c_origin = in6addr_any, - .mf6c_mcastgrp = in6addr_any, - }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; - - list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) - if (c->mfc_un.res.ttls[mifi] < 255) - return (struct mfc6_cache *)c; - - return NULL; + return mr_mfc_find(mrt, &arg); } /* Look for a (*,G) entry */ @@ -1026,26 +1011,10 @@ static struct mfc6_cache *ip6mr_cache_find_any(struct mr_table *mrt, .mf6c_origin = in6addr_any, .mf6c_mcastgrp = *mcastgrp, }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; - struct mfc6_cache *proxy; if (ipv6_addr_any(mcastgrp)) - goto skip; - - list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) { - if (c->mfc_un.res.ttls[mifi] < 255) - return (struct mfc6_cache *)c; - - /* It's ok if the mifi is part of the static tree */ - proxy = ip6mr_cache_find_any_parent(mrt, c->mfc_parent); - if (proxy && proxy->_c.mfc_un.res.ttls[mifi] < 255) - return (struct mfc6_cache *)c; - } - -skip: - return ip6mr_cache_find_any_parent(mrt, mifi); + return mr_mfc_find_any_parent(mrt, mifi); + return mr_mfc_find_any(mrt, mifi, &arg); } /* Look for a (S,G,iif) entry if parent != -1 */ @@ -1059,20 +1028,11 @@ ip6mr_cache_find_parent(struct mr_table *mrt, .mf6c_origin = *origin, .mf6c_mcastgrp = *mcastgrp, }; - struct rhlist_head *tmp, *list; - struct mr_mfc *c; - - list = rhltable_lookup(&mrt->mfc_hash, &arg, ip6mr_rht_params); - rhl_for_each_entry_rcu(c, tmp, list, mnode) - if (parent == -1 || parent == c->mfc_parent) - return (struct mfc6_cache *)c; - return NULL; + return mr_mfc_find_parent(mrt, &arg, parent); } -/* - * Allocate a multicast cache entry - */ +/* Allocate a multicast cache entry */ static struct mfc6_cache *ip6mr_cache_alloc(void) { struct mfc6_cache *c = kmem_cache_zalloc(mrt_cachep, GFP_KERNEL); @@ -2107,7 +2067,7 @@ static void ip6_mr_forward(struct net *net, struct mr_table *mrt, * interface is part of the static tree. */ rcu_read_lock(); - cache_proxy = ip6mr_cache_find_any_parent(mrt, vif); + cache_proxy = mr_mfc_find_any_parent(mrt, vif); if (cache_proxy && cache_proxy->_c.mfc_un.res.ttls[true_vifi] < 255) { rcu_read_unlock(); -- cgit v1.2.3 From c8d6196803265484f7e1cdd1b00a188dc59a5988 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:36 +0200 Subject: ipmr, ip6mr: Unite mfc seq logic With the exception of the final dump, ipmr and ip6mr have the exact same seq logic for traversing a given mr_table. Refactor that code and make it common. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute_base.h | 69 ++++++++++++++++++++++++++++++++ net/ipv4/ipmr.c | 93 +++---------------------------------------- net/ipv4/ipmr_base.c | 62 +++++++++++++++++++++++++++++ net/ipv6/ip6mr.c | 97 ++++----------------------------------------- 4 files changed, 143 insertions(+), 178 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 46a082e25dab..a007c5ad0fde 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -3,6 +3,7 @@ #include #include +#include #include #include @@ -203,4 +204,72 @@ static inline void *mr_mfc_find(struct mr_table *mrt, void *hasharg) { return mr_mfc_find_parent(mrt, hasharg, -1); } + +#ifdef CONFIG_PROC_FS +struct mr_mfc_iter { + struct seq_net_private p; + struct mr_table *mrt; + struct list_head *cache; + + /* Lock protecting the mr_table's unresolved queue */ + spinlock_t *lock; +}; + +#ifdef CONFIG_IP_MROUTE_COMMON +/* These actually return 'struct mr_mfc *', but to avoid need for explicit + * castings they simply return void. + */ +void *mr_mfc_seq_idx(struct net *net, + struct mr_mfc_iter *it, loff_t pos); +void *mr_mfc_seq_next(struct seq_file *seq, void *v, + loff_t *pos); + +static inline void *mr_mfc_seq_start(struct seq_file *seq, loff_t *pos, + struct mr_table *mrt, spinlock_t *lock) +{ + struct mr_mfc_iter *it = seq->private; + + it->mrt = mrt; + it->cache = NULL; + it->lock = lock; + + return *pos ? mr_mfc_seq_idx(seq_file_net(seq), + seq->private, *pos - 1) + : SEQ_START_TOKEN; +} + +static inline void mr_mfc_seq_stop(struct seq_file *seq, void *v) +{ + struct mr_mfc_iter *it = seq->private; + struct mr_table *mrt = it->mrt; + + if (it->cache == &mrt->mfc_unres_queue) + spin_unlock_bh(it->lock); + else if (it->cache == &mrt->mfc_cache_list) + rcu_read_unlock(); +} +#else +static inline void *mr_mfc_seq_idx(struct net *net, + struct mr_mfc_iter *it, loff_t pos) +{ + return NULL; +} + +static inline void *mr_mfc_seq_next(struct seq_file *seq, void *v, + loff_t *pos) +{ + return NULL; +} + +static inline void *mr_mfc_seq_start(struct seq_file *seq, loff_t *pos, + struct mr_table *mrt, spinlock_t *lock) +{ + return NULL; +} + +static inline void mr_mfc_seq_stop(struct seq_file *seq, void *v) +{ +} +#endif +#endif #endif diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 00898c319cc5..1eb19d9b1be0 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -3014,41 +3014,8 @@ static const struct file_operations ipmr_vif_fops = { .release = seq_release_net, }; -struct ipmr_mfc_iter { - struct seq_net_private p; - struct mr_table *mrt; - struct list_head *cache; -}; - -static struct mfc_cache *ipmr_mfc_seq_idx(struct net *net, - struct ipmr_mfc_iter *it, loff_t pos) -{ - struct mr_table *mrt = it->mrt; - struct mr_mfc *mfc; - - rcu_read_lock(); - it->cache = &mrt->mfc_cache_list; - list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) - if (pos-- == 0) - return (struct mfc_cache *)mfc; - rcu_read_unlock(); - - spin_lock_bh(&mfc_unres_lock); - it->cache = &mrt->mfc_unres_queue; - list_for_each_entry(mfc, it->cache, list) - if (pos-- == 0) - return (struct mfc_cache *)mfc; - - spin_unlock_bh(&mfc_unres_lock); - - it->cache = NULL; - return NULL; -} - - static void *ipmr_mfc_seq_start(struct seq_file *seq, loff_t *pos) { - struct ipmr_mfc_iter *it = seq->private; struct net *net = seq_file_net(seq); struct mr_table *mrt; @@ -3056,57 +3023,7 @@ static void *ipmr_mfc_seq_start(struct seq_file *seq, loff_t *pos) if (!mrt) return ERR_PTR(-ENOENT); - it->mrt = mrt; - it->cache = NULL; - return *pos ? ipmr_mfc_seq_idx(net, seq->private, *pos - 1) - : SEQ_START_TOKEN; -} - -static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct ipmr_mfc_iter *it = seq->private; - struct net *net = seq_file_net(seq); - struct mr_table *mrt = it->mrt; - struct mfc_cache *mfc = v; - - ++*pos; - - if (v == SEQ_START_TOKEN) - return ipmr_mfc_seq_idx(net, seq->private, 0); - - if (mfc->_c.list.next != it->cache) - return (struct mfc_cache *)(list_entry(mfc->_c.list.next, - struct mr_mfc, list)); - - if (it->cache == &mrt->mfc_unres_queue) - goto end_of_list; - - /* exhausted cache_array, show unresolved */ - rcu_read_unlock(); - it->cache = &mrt->mfc_unres_queue; - - spin_lock_bh(&mfc_unres_lock); - if (!list_empty(it->cache)) - return (struct mfc_cache *)(list_first_entry(it->cache, - struct mr_mfc, - list)); - -end_of_list: - spin_unlock_bh(&mfc_unres_lock); - it->cache = NULL; - - return NULL; -} - -static void ipmr_mfc_seq_stop(struct seq_file *seq, void *v) -{ - struct ipmr_mfc_iter *it = seq->private; - struct mr_table *mrt = it->mrt; - - if (it->cache == &mrt->mfc_unres_queue) - spin_unlock_bh(&mfc_unres_lock); - else if (it->cache == &mrt->mfc_cache_list) - rcu_read_unlock(); + return mr_mfc_seq_start(seq, pos, mrt, &mfc_unres_lock); } static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) @@ -3118,7 +3035,7 @@ static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) "Group Origin Iif Pkts Bytes Wrong Oifs\n"); } else { const struct mfc_cache *mfc = v; - const struct ipmr_mfc_iter *it = seq->private; + const struct mr_mfc_iter *it = seq->private; const struct mr_table *mrt = it->mrt; seq_printf(seq, "%08X %08X %-3hd", @@ -3152,15 +3069,15 @@ static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) static const struct seq_operations ipmr_mfc_seq_ops = { .start = ipmr_mfc_seq_start, - .next = ipmr_mfc_seq_next, - .stop = ipmr_mfc_seq_stop, + .next = mr_mfc_seq_next, + .stop = mr_mfc_seq_stop, .show = ipmr_mfc_seq_show, }; static int ipmr_mfc_open(struct inode *inode, struct file *file) { return seq_open_net(inode, file, &ipmr_mfc_seq_ops, - sizeof(struct ipmr_mfc_iter)); + sizeof(struct mr_mfc_iter)); } static const struct file_operations ipmr_mfc_fops = { diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c index 172f92acffef..37ad0a793035 100644 --- a/net/ipv4/ipmr_base.c +++ b/net/ipv4/ipmr_base.c @@ -103,3 +103,65 @@ void *mr_mfc_find_any(struct mr_table *mrt, int vifi, void *hasharg) return mr_mfc_find_any_parent(mrt, vifi); } EXPORT_SYMBOL(mr_mfc_find_any); + +#ifdef CONFIG_PROC_FS +void *mr_mfc_seq_idx(struct net *net, + struct mr_mfc_iter *it, loff_t pos) +{ + struct mr_table *mrt = it->mrt; + struct mr_mfc *mfc; + + rcu_read_lock(); + it->cache = &mrt->mfc_cache_list; + list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) + if (pos-- == 0) + return mfc; + rcu_read_unlock(); + + spin_lock_bh(it->lock); + it->cache = &mrt->mfc_unres_queue; + list_for_each_entry(mfc, it->cache, list) + if (pos-- == 0) + return mfc; + spin_unlock_bh(it->lock); + + it->cache = NULL; + return NULL; +} +EXPORT_SYMBOL(mr_mfc_seq_idx); + +void *mr_mfc_seq_next(struct seq_file *seq, void *v, + loff_t *pos) +{ + struct mr_mfc_iter *it = seq->private; + struct net *net = seq_file_net(seq); + struct mr_table *mrt = it->mrt; + struct mr_mfc *c = v; + + ++*pos; + + if (v == SEQ_START_TOKEN) + return mr_mfc_seq_idx(net, seq->private, 0); + + if (c->list.next != it->cache) + return list_entry(c->list.next, struct mr_mfc, list); + + if (it->cache == &mrt->mfc_unres_queue) + goto end_of_list; + + /* exhausted cache_array, show unresolved */ + rcu_read_unlock(); + it->cache = &mrt->mfc_unres_queue; + + spin_lock_bh(it->lock); + if (!list_empty(it->cache)) + return list_first_entry(it->cache, struct mr_mfc, list); + +end_of_list: + spin_unlock_bh(it->lock); + it->cache = NULL; + + return NULL; +} +EXPORT_SYMBOL(mr_mfc_seq_next); +#endif diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index ea902a952fb6..26315065e7df 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -333,40 +333,8 @@ static void ip6mr_free_table(struct mr_table *mrt) } #ifdef CONFIG_PROC_FS - -struct ipmr_mfc_iter { - struct seq_net_private p; - struct mr_table *mrt; - struct list_head *cache; -}; - - -static struct mfc6_cache *ipmr_mfc_seq_idx(struct net *net, - struct ipmr_mfc_iter *it, loff_t pos) -{ - struct mr_table *mrt = it->mrt; - struct mr_mfc *mfc; - - rcu_read_lock(); - it->cache = &mrt->mfc_cache_list; - list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) - if (pos-- == 0) - return (struct mfc6_cache *)mfc; - rcu_read_unlock(); - - spin_lock_bh(&mfc_unres_lock); - it->cache = &mrt->mfc_unres_queue; - list_for_each_entry(mfc, it->cache, list) - if (pos-- == 0) - return (struct mfc6_cache *)mfc; - spin_unlock_bh(&mfc_unres_lock); - - it->cache = NULL; - return NULL; -} - -/* - * The /proc interfaces to multicast routing /proc/ip6_mr_cache /proc/ip6_mr_vif +/* The /proc interfaces to multicast routing + * /proc/ip6_mr_cache /proc/ip6_mr_vif */ struct ipmr_vif_iter { @@ -476,7 +444,6 @@ static const struct file_operations ip6mr_vif_fops = { static void *ipmr_mfc_seq_start(struct seq_file *seq, loff_t *pos) { - struct ipmr_mfc_iter *it = seq->private; struct net *net = seq_file_net(seq); struct mr_table *mrt; @@ -484,57 +451,7 @@ static void *ipmr_mfc_seq_start(struct seq_file *seq, loff_t *pos) if (!mrt) return ERR_PTR(-ENOENT); - it->mrt = mrt; - it->cache = NULL; - return *pos ? ipmr_mfc_seq_idx(net, seq->private, *pos - 1) - : SEQ_START_TOKEN; -} - -static void *ipmr_mfc_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct mfc6_cache *mfc = v; - struct ipmr_mfc_iter *it = seq->private; - struct net *net = seq_file_net(seq); - struct mr_table *mrt = it->mrt; - - ++*pos; - - if (v == SEQ_START_TOKEN) - return ipmr_mfc_seq_idx(net, seq->private, 0); - - if (mfc->_c.list.next != it->cache) - return (struct mfc6_cache *)(list_entry(mfc->_c.list.next, - struct mr_mfc, list)); - - if (it->cache == &mrt->mfc_unres_queue) - goto end_of_list; - - /* exhausted cache_array, show unresolved */ - rcu_read_unlock(); - it->cache = &mrt->mfc_unres_queue; - - spin_lock_bh(&mfc_unres_lock); - if (!list_empty(it->cache)) - return (struct mfc6_cache *)(list_first_entry(it->cache, - struct mr_mfc, - list)); - - end_of_list: - spin_unlock_bh(&mfc_unres_lock); - it->cache = NULL; - - return NULL; -} - -static void ipmr_mfc_seq_stop(struct seq_file *seq, void *v) -{ - struct ipmr_mfc_iter *it = seq->private; - struct mr_table *mrt = it->mrt; - - if (it->cache == &mrt->mfc_unres_queue) - spin_unlock_bh(&mfc_unres_lock); - else if (it->cache == &mrt->mfc_cache_list) - rcu_read_unlock(); + return mr_mfc_seq_start(seq, pos, mrt, &mfc_unres_lock); } static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) @@ -548,7 +465,7 @@ static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) "Iif Pkts Bytes Wrong Oifs\n"); } else { const struct mfc6_cache *mfc = v; - const struct ipmr_mfc_iter *it = seq->private; + const struct mr_mfc_iter *it = seq->private; struct mr_table *mrt = it->mrt; seq_printf(seq, "%pI6 %pI6 %-3hd", @@ -581,15 +498,15 @@ static int ipmr_mfc_seq_show(struct seq_file *seq, void *v) static const struct seq_operations ipmr_mfc_seq_ops = { .start = ipmr_mfc_seq_start, - .next = ipmr_mfc_seq_next, - .stop = ipmr_mfc_seq_stop, + .next = mr_mfc_seq_next, + .stop = mr_mfc_seq_stop, .show = ipmr_mfc_seq_show, }; static int ipmr_mfc_open(struct inode *inode, struct file *file) { return seq_open_net(inode, file, &ipmr_mfc_seq_ops, - sizeof(struct ipmr_mfc_iter)); + sizeof(struct mr_mfc_iter)); } static const struct file_operations ip6mr_mfc_fops = { -- cgit v1.2.3 From 3feda6b46f734704840685a62b645cbe4efb810c Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:37 +0200 Subject: ipmr, ip6mr: Unite vif seq functions Same as previously done with the mfc seq, the logic for the vif seq is refactored to be shared between ipmr and ip6mr. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute_base.h | 33 ++++++++++++++++++++++++++++++ net/ipv4/ipmr.c | 49 +++++--------------------------------------- net/ipv4/ipmr_base.c | 33 ++++++++++++++++++++++++++++++ net/ipv6/ip6mr.c | 50 +++++---------------------------------------- 4 files changed, 76 insertions(+), 89 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index a007c5ad0fde..cfaec9bd2d3c 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -206,6 +206,12 @@ static inline void *mr_mfc_find(struct mr_table *mrt, void *hasharg) } #ifdef CONFIG_PROC_FS +struct mr_vif_iter { + struct seq_net_private p; + struct mr_table *mrt; + int ct; +}; + struct mr_mfc_iter { struct seq_net_private p; struct mr_table *mrt; @@ -216,6 +222,16 @@ struct mr_mfc_iter { }; #ifdef CONFIG_IP_MROUTE_COMMON +void *mr_vif_seq_idx(struct net *net, struct mr_vif_iter *iter, loff_t pos); +void *mr_vif_seq_next(struct seq_file *seq, void *v, loff_t *pos); + +static inline void *mr_vif_seq_start(struct seq_file *seq, loff_t *pos) +{ + return *pos ? mr_vif_seq_idx(seq_file_net(seq), + seq->private, *pos - 1) + : SEQ_START_TOKEN; +} + /* These actually return 'struct mr_mfc *', but to avoid need for explicit * castings they simply return void. */ @@ -249,6 +265,23 @@ static inline void mr_mfc_seq_stop(struct seq_file *seq, void *v) rcu_read_unlock(); } #else +static inline void *mr_vif_seq_idx(struct net *net, struct mr_vif_iter *iter, + loff_t pos) +{ + return NULL; +} + +static inline void *mr_vif_seq_next(struct seq_file *seq, + void *v, loff_t *pos) +{ + return NULL; +} + +static inline void *mr_vif_seq_start(struct seq_file *seq, loff_t *pos) +{ + return NULL; +} + static inline void *mr_mfc_seq_idx(struct net *net, struct mr_mfc_iter *it, loff_t pos) { diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 1eb19d9b1be0..f5ff54297824 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -2908,31 +2908,11 @@ out: /* The /proc interfaces to multicast routing : * /proc/net/ip_mr_cache & /proc/net/ip_mr_vif */ -struct ipmr_vif_iter { - struct seq_net_private p; - struct mr_table *mrt; - int ct; -}; - -static struct vif_device *ipmr_vif_seq_idx(struct net *net, - struct ipmr_vif_iter *iter, - loff_t pos) -{ - struct mr_table *mrt = iter->mrt; - - for (iter->ct = 0; iter->ct < mrt->maxvif; ++iter->ct) { - if (!VIF_EXISTS(mrt, iter->ct)) - continue; - if (pos-- == 0) - return &mrt->vif_table[iter->ct]; - } - return NULL; -} static void *ipmr_vif_seq_start(struct seq_file *seq, loff_t *pos) __acquires(mrt_lock) { - struct ipmr_vif_iter *iter = seq->private; + struct mr_vif_iter *iter = seq->private; struct net *net = seq_file_net(seq); struct mr_table *mrt; @@ -2943,26 +2923,7 @@ static void *ipmr_vif_seq_start(struct seq_file *seq, loff_t *pos) iter->mrt = mrt; read_lock(&mrt_lock); - return *pos ? ipmr_vif_seq_idx(net, seq->private, *pos - 1) - : SEQ_START_TOKEN; -} - -static void *ipmr_vif_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct ipmr_vif_iter *iter = seq->private; - struct net *net = seq_file_net(seq); - struct mr_table *mrt = iter->mrt; - - ++*pos; - if (v == SEQ_START_TOKEN) - return ipmr_vif_seq_idx(net, iter, 0); - - while (++iter->ct < mrt->maxvif) { - if (!VIF_EXISTS(mrt, iter->ct)) - continue; - return &mrt->vif_table[iter->ct]; - } - return NULL; + return mr_vif_seq_start(seq, pos); } static void ipmr_vif_seq_stop(struct seq_file *seq, void *v) @@ -2973,7 +2934,7 @@ static void ipmr_vif_seq_stop(struct seq_file *seq, void *v) static int ipmr_vif_seq_show(struct seq_file *seq, void *v) { - struct ipmr_vif_iter *iter = seq->private; + struct mr_vif_iter *iter = seq->private; struct mr_table *mrt = iter->mrt; if (v == SEQ_START_TOKEN) { @@ -2996,7 +2957,7 @@ static int ipmr_vif_seq_show(struct seq_file *seq, void *v) static const struct seq_operations ipmr_vif_seq_ops = { .start = ipmr_vif_seq_start, - .next = ipmr_vif_seq_next, + .next = mr_vif_seq_next, .stop = ipmr_vif_seq_stop, .show = ipmr_vif_seq_show, }; @@ -3004,7 +2965,7 @@ static const struct seq_operations ipmr_vif_seq_ops = { static int ipmr_vif_open(struct inode *inode, struct file *file) { return seq_open_net(inode, file, &ipmr_vif_seq_ops, - sizeof(struct ipmr_vif_iter)); + sizeof(struct mr_vif_iter)); } static const struct file_operations ipmr_vif_fops = { diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c index 37ad0a793035..e1b7b639e9b1 100644 --- a/net/ipv4/ipmr_base.c +++ b/net/ipv4/ipmr_base.c @@ -105,6 +105,39 @@ void *mr_mfc_find_any(struct mr_table *mrt, int vifi, void *hasharg) EXPORT_SYMBOL(mr_mfc_find_any); #ifdef CONFIG_PROC_FS +void *mr_vif_seq_idx(struct net *net, struct mr_vif_iter *iter, loff_t pos) +{ + struct mr_table *mrt = iter->mrt; + + for (iter->ct = 0; iter->ct < mrt->maxvif; ++iter->ct) { + if (!VIF_EXISTS(mrt, iter->ct)) + continue; + if (pos-- == 0) + return &mrt->vif_table[iter->ct]; + } + return NULL; +} +EXPORT_SYMBOL(mr_vif_seq_idx); + +void *mr_vif_seq_next(struct seq_file *seq, void *v, loff_t *pos) +{ + struct mr_vif_iter *iter = seq->private; + struct net *net = seq_file_net(seq); + struct mr_table *mrt = iter->mrt; + + ++*pos; + if (v == SEQ_START_TOKEN) + return mr_vif_seq_idx(net, iter, 0); + + while (++iter->ct < mrt->maxvif) { + if (!VIF_EXISTS(mrt, iter->ct)) + continue; + return &mrt->vif_table[iter->ct]; + } + return NULL; +} +EXPORT_SYMBOL(mr_vif_seq_next); + void *mr_mfc_seq_idx(struct net *net, struct mr_mfc_iter *it, loff_t pos) { diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index 26315065e7df..ddd9e6bba499 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -337,31 +337,10 @@ static void ip6mr_free_table(struct mr_table *mrt) * /proc/ip6_mr_cache /proc/ip6_mr_vif */ -struct ipmr_vif_iter { - struct seq_net_private p; - struct mr_table *mrt; - int ct; -}; - -static struct vif_device *ip6mr_vif_seq_idx(struct net *net, - struct ipmr_vif_iter *iter, - loff_t pos) -{ - struct mr_table *mrt = iter->mrt; - - for (iter->ct = 0; iter->ct < mrt->maxvif; ++iter->ct) { - if (!VIF_EXISTS(mrt, iter->ct)) - continue; - if (pos-- == 0) - return &mrt->vif_table[iter->ct]; - } - return NULL; -} - static void *ip6mr_vif_seq_start(struct seq_file *seq, loff_t *pos) __acquires(mrt_lock) { - struct ipmr_vif_iter *iter = seq->private; + struct mr_vif_iter *iter = seq->private; struct net *net = seq_file_net(seq); struct mr_table *mrt; @@ -372,26 +351,7 @@ static void *ip6mr_vif_seq_start(struct seq_file *seq, loff_t *pos) iter->mrt = mrt; read_lock(&mrt_lock); - return *pos ? ip6mr_vif_seq_idx(net, seq->private, *pos - 1) - : SEQ_START_TOKEN; -} - -static void *ip6mr_vif_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct ipmr_vif_iter *iter = seq->private; - struct net *net = seq_file_net(seq); - struct mr_table *mrt = iter->mrt; - - ++*pos; - if (v == SEQ_START_TOKEN) - return ip6mr_vif_seq_idx(net, iter, 0); - - while (++iter->ct < mrt->maxvif) { - if (!VIF_EXISTS(mrt, iter->ct)) - continue; - return &mrt->vif_table[iter->ct]; - } - return NULL; + return mr_vif_seq_start(seq, pos); } static void ip6mr_vif_seq_stop(struct seq_file *seq, void *v) @@ -402,7 +362,7 @@ static void ip6mr_vif_seq_stop(struct seq_file *seq, void *v) static int ip6mr_vif_seq_show(struct seq_file *seq, void *v) { - struct ipmr_vif_iter *iter = seq->private; + struct mr_vif_iter *iter = seq->private; struct mr_table *mrt = iter->mrt; if (v == SEQ_START_TOKEN) { @@ -424,7 +384,7 @@ static int ip6mr_vif_seq_show(struct seq_file *seq, void *v) static const struct seq_operations ip6mr_vif_seq_ops = { .start = ip6mr_vif_seq_start, - .next = ip6mr_vif_seq_next, + .next = mr_vif_seq_next, .stop = ip6mr_vif_seq_stop, .show = ip6mr_vif_seq_show, }; @@ -432,7 +392,7 @@ static const struct seq_operations ip6mr_vif_seq_ops = { static int ip6mr_vif_open(struct inode *inode, struct file *file) { return seq_open_net(inode, file, &ip6mr_vif_seq_ops, - sizeof(struct ipmr_vif_iter)); + sizeof(struct mr_vif_iter)); } static const struct file_operations ip6mr_vif_fops = { -- cgit v1.2.3 From 889cd83cbe411dda854429f3223ab2d31a860a4a Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:38 +0200 Subject: ip6mr: Remove MFC_NOTIFY and refactor flags MFC_NOTIFY exists in ip6mr, probably as some legacy code [was already removed for ipmr in commit 06bd6c0370bb ("net: ipmr: remove unused MFC_NOTIFY flag and make the flags enum"). Remove it from ip6mr as well, and move the enum into a common file; Notice MFC_OFFLOAD is currently only used by ipmr. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute.h | 9 --------- include/linux/mroute6.h | 3 --- include/linux/mroute_base.h | 9 +++++++++ net/ipv6/ip6mr.c | 3 --- 4 files changed, 9 insertions(+), 15 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute.h b/include/linux/mroute.h index 63b36e6c72a0..7ed82e4f11b3 100644 --- a/include/linux/mroute.h +++ b/include/linux/mroute.h @@ -65,15 +65,6 @@ struct vif_entry_notifier_info { #define VIFF_STATIC 0x8000 -/* mfc_flags: - * MFC_STATIC - the entry was added statically (not by a routing daemon) - * MFC_OFFLOAD - the entry was offloaded to the hardware - */ -enum { - MFC_STATIC = BIT(0), - MFC_OFFLOAD = BIT(1), -}; - struct mfc_cache_cmp_arg { __be32 mfc_mcastgrp; __be32 mfc_origin; diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h index 6acf576fc135..1ac38e6819f5 100644 --- a/include/linux/mroute6.h +++ b/include/linux/mroute6.h @@ -81,9 +81,6 @@ struct mfc6_cache { }; }; -#define MFC_STATIC 1 -#define MFC_NOTIFY 2 - #define MFC_ASSERT_THRESH (3*HZ) /* Maximal freq. of asserts */ struct rtmsg; diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index cfaec9bd2d3c..f40202b16dae 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -45,6 +45,15 @@ struct vif_device { #define VIF_EXISTS(_mrt, _idx) (!!((_mrt)->vif_table[_idx].dev)) +/* mfc_flags: + * MFC_STATIC - the entry was added statically (not by a routing daemon) + * MFC_OFFLOAD - the entry was offloaded to the hardware + */ +enum { + MFC_STATIC = BIT(0), + MFC_OFFLOAD = BIT(1), +}; + /** * struct mr_mfc - common multicast routing entries * @mnode: rhashtable list diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index ddd9e6bba499..c3b3f1c381e1 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -2203,9 +2203,6 @@ int ip6mr_get_route(struct net *net, struct sk_buff *skb, struct rtmsg *rtm, return err; } - if (rtm->rtm_flags & RTM_F_NOTIFY) - cache->_c.mfc_flags |= MFC_NOTIFY; - err = __ip6mr_fill_mroute(mrt, skb, cache, rtm); read_unlock(&mrt_lock); return err; -- cgit v1.2.3 From 7b0db85737db3f4d76b2a412e4f19eae59b8b494 Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Wed, 28 Feb 2018 23:29:39 +0200 Subject: ipmr, ip6mr: Unite dumproute flows The various MFC entries are being held in the same kind of mr_tables for both ipmr and ip6mr, and their traversal logic is identical. Also, with the exception of the addresses [and other small tidbits] the major bulk of the nla setting is identical. Unite as much of the dumping as possible between the two. Notice this requires creating an mr_table iterator for each, as the for-each preprocessor macro can't be used by the common logic. Signed-off-by: Yuval Mintz Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller --- include/linux/mroute_base.h | 29 ++++++++ net/ipv4/ipmr.c | 161 +++++++++++--------------------------------- net/ipv4/ipmr_base.c | 123 +++++++++++++++++++++++++++++++++ net/ipv6/ip6mr.c | 156 +++++++++++------------------------------- 4 files changed, 230 insertions(+), 239 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index f40202b16dae..c2560cb50f1d 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -170,6 +170,16 @@ void *mr_mfc_find_parent(struct mr_table *mrt, void *mr_mfc_find_any_parent(struct mr_table *mrt, int vifi); void *mr_mfc_find_any(struct mr_table *mrt, int vifi, void *hasharg); +int mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, + struct mr_mfc *c, struct rtmsg *rtm); +int mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb, + struct mr_table *(*iter)(struct net *net, + struct mr_table *mrt), + int (*fill)(struct mr_table *mrt, + struct sk_buff *skb, + u32 portid, u32 seq, struct mr_mfc *c, + int cmd, int flags), + spinlock_t *lock); #else static inline void vif_device_init(struct vif_device *v, struct net_device *dev, @@ -207,6 +217,25 @@ static inline struct mr_mfc *mr_mfc_find_any(struct mr_table *mrt, { return NULL; } + +static inline int mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, + struct mr_mfc *c, struct rtmsg *rtm) +{ + return -EINVAL; +} + +static inline int +mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb, + struct mr_table *(*iter)(struct net *net, + struct mr_table *mrt), + int (*fill)(struct mr_table *mrt, + struct sk_buff *skb, + u32 portid, u32 seq, struct mr_mfc *c, + int cmd, int flags), + spinlock_t *lock) +{ + return -EINVAL; +} #endif static inline void *mr_mfc_find(struct mr_table *mrt, void *hasharg) diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index f5ff54297824..d752a70855d8 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -105,8 +105,6 @@ static void ip_mr_forward(struct net *net, struct mr_table *mrt, struct mfc_cache *cache, int local); static int ipmr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, vifi_t vifi, int assert); -static int __ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, - struct mr_mfc *c, struct rtmsg *rtm); static void mroute_netlink_event(struct mr_table *mrt, struct mfc_cache *mfc, int cmd); static void igmpmsg_netlink_event(struct mr_table *mrt, struct sk_buff *pkt); @@ -117,6 +115,23 @@ static void ipmr_expire_process(struct timer_list *t); #define ipmr_for_each_table(mrt, net) \ list_for_each_entry_rcu(mrt, &net->ipv4.mr_tables, list) +static struct mr_table *ipmr_mr_table_iter(struct net *net, + struct mr_table *mrt) +{ + struct mr_table *ret; + + if (!mrt) + ret = list_entry_rcu(net->ipv4.mr_tables.next, + struct mr_table, list); + else + ret = list_entry_rcu(mrt->list.next, + struct mr_table, list); + + if (&ret->list == &net->ipv4.mr_tables) + return NULL; + return ret; +} + static struct mr_table *ipmr_get_table(struct net *net, u32 id) { struct mr_table *mrt; @@ -284,6 +299,14 @@ EXPORT_SYMBOL(ipmr_rule_default); #define ipmr_for_each_table(mrt, net) \ for (mrt = net->ipv4.mrt; mrt; mrt = NULL) +static struct mr_table *ipmr_mr_table_iter(struct net *net, + struct mr_table *mrt) +{ + if (!mrt) + return net->ipv4.mrt; + return NULL; +} + static struct mr_table *ipmr_get_table(struct net *net, u32 id) { return net->ipv4.mrt; @@ -1051,8 +1074,8 @@ static void ipmr_cache_resolve(struct net *net, struct mr_table *mrt, struct nlmsghdr *nlh = skb_pull(skb, sizeof(struct iphdr)); - if (__ipmr_fill_mroute(mrt, skb, &c->_c, - nlmsg_data(nlh)) > 0) { + if (mr_fill_mroute(mrt, skb, &c->_c, + nlmsg_data(nlh)) > 0) { nlh->nlmsg_len = skb_tail_pointer(skb) - (u8 *)nlh; } else { @@ -2256,66 +2279,6 @@ drop: } #endif -static int __ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, - struct mr_mfc *c, struct rtmsg *rtm) -{ - struct rta_mfc_stats mfcs; - struct nlattr *mp_attr; - struct rtnexthop *nhp; - unsigned long lastuse; - int ct; - - /* If cache is unresolved, don't try to parse IIF and OIF */ - if (c->mfc_parent >= MAXVIFS) { - rtm->rtm_flags |= RTNH_F_UNRESOLVED; - return -ENOENT; - } - - if (VIF_EXISTS(mrt, c->mfc_parent) && - nla_put_u32(skb, RTA_IIF, - mrt->vif_table[c->mfc_parent].dev->ifindex) < 0) - return -EMSGSIZE; - - if (c->mfc_flags & MFC_OFFLOAD) - rtm->rtm_flags |= RTNH_F_OFFLOAD; - - if (!(mp_attr = nla_nest_start(skb, RTA_MULTIPATH))) - return -EMSGSIZE; - - for (ct = c->mfc_un.res.minvif; ct < c->mfc_un.res.maxvif; ct++) { - if (VIF_EXISTS(mrt, ct) && c->mfc_un.res.ttls[ct] < 255) { - struct vif_device *vif; - - if (!(nhp = nla_reserve_nohdr(skb, sizeof(*nhp)))) { - nla_nest_cancel(skb, mp_attr); - return -EMSGSIZE; - } - - nhp->rtnh_flags = 0; - nhp->rtnh_hops = c->mfc_un.res.ttls[ct]; - vif = &mrt->vif_table[ct]; - nhp->rtnh_ifindex = vif->dev->ifindex; - nhp->rtnh_len = sizeof(*nhp); - } - } - - nla_nest_end(skb, mp_attr); - - lastuse = READ_ONCE(c->mfc_un.res.lastuse); - lastuse = time_after_eq(jiffies, lastuse) ? jiffies - lastuse : 0; - - mfcs.mfcs_packets = c->mfc_un.res.pkt; - mfcs.mfcs_bytes = c->mfc_un.res.bytes; - mfcs.mfcs_wrong_if = c->mfc_un.res.wrong_if; - if (nla_put_64bit(skb, RTA_MFC_STATS, sizeof(mfcs), &mfcs, RTA_PAD) || - nla_put_u64_64bit(skb, RTA_EXPIRES, jiffies_to_clock_t(lastuse), - RTA_PAD)) - return -EMSGSIZE; - - rtm->rtm_type = RTN_MULTICAST; - return 1; -} - int ipmr_get_route(struct net *net, struct sk_buff *skb, __be32 saddr, __be32 daddr, struct rtmsg *rtm, u32 portid) @@ -2373,7 +2336,7 @@ int ipmr_get_route(struct net *net, struct sk_buff *skb, } read_lock(&mrt_lock); - err = __ipmr_fill_mroute(mrt, skb, &cache->_c, rtm); + err = mr_fill_mroute(mrt, skb, &cache->_c, rtm); read_unlock(&mrt_lock); rcu_read_unlock(); return err; @@ -2410,7 +2373,7 @@ static int ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, if (nla_put_in_addr(skb, RTA_SRC, c->mfc_origin) || nla_put_in_addr(skb, RTA_DST, c->mfc_mcastgrp)) goto nla_put_failure; - err = __ipmr_fill_mroute(mrt, skb, &c->_c, rtm); + err = mr_fill_mroute(mrt, skb, &c->_c, rtm); /* do not break the dump if cache is unresolved */ if (err < 0 && err != -ENOENT) goto nla_put_failure; @@ -2423,6 +2386,14 @@ nla_put_failure: return -EMSGSIZE; } +static int _ipmr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, + u32 portid, u32 seq, struct mr_mfc *c, int cmd, + int flags) +{ + return ipmr_fill_mroute(mrt, skb, portid, seq, (struct mfc_cache *)c, + cmd, flags); +} + static size_t mroute_msgsize(bool unresolved, int maxvif) { size_t len = @@ -2596,62 +2567,8 @@ errout_free: static int ipmr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) { - struct net *net = sock_net(skb->sk); - unsigned int t = 0, s_t; - unsigned int e = 0, s_e; - struct mr_table *mrt; - struct mr_mfc *mfc; - - s_t = cb->args[0]; - s_e = cb->args[1]; - - rcu_read_lock(); - ipmr_for_each_table(mrt, net) { - if (t < s_t) - goto next_table; - list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) { - if (e < s_e) - goto next_entry; - if (ipmr_fill_mroute(mrt, skb, - NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, - (struct mfc_cache *)mfc, - RTM_NEWROUTE, NLM_F_MULTI) < 0) - goto done; -next_entry: - e++; - } - e = 0; - s_e = 0; - - spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(mfc, &mrt->mfc_unres_queue, list) { - if (e < s_e) - goto next_entry2; - if (ipmr_fill_mroute(mrt, skb, - NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, - (struct mfc_cache *)mfc, - RTM_NEWROUTE, NLM_F_MULTI) < 0) { - spin_unlock_bh(&mfc_unres_lock); - goto done; - } -next_entry2: - e++; - } - spin_unlock_bh(&mfc_unres_lock); - e = 0; - s_e = 0; -next_table: - t++; - } -done: - rcu_read_unlock(); - - cb->args[1] = e; - cb->args[0] = t; - - return skb->len; + return mr_rtm_dumproute(skb, cb, ipmr_mr_table_iter, + _ipmr_fill_mroute, &mfc_unres_lock); } static const struct nla_policy rtm_ipmr_policy[RTA_MAX + 1] = { diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c index e1b7b639e9b1..8ba55bfda817 100644 --- a/net/ipv4/ipmr_base.c +++ b/net/ipv4/ipmr_base.c @@ -198,3 +198,126 @@ end_of_list: } EXPORT_SYMBOL(mr_mfc_seq_next); #endif + +int mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, + struct mr_mfc *c, struct rtmsg *rtm) +{ + struct rta_mfc_stats mfcs; + struct nlattr *mp_attr; + struct rtnexthop *nhp; + unsigned long lastuse; + int ct; + + /* If cache is unresolved, don't try to parse IIF and OIF */ + if (c->mfc_parent >= MAXVIFS) { + rtm->rtm_flags |= RTNH_F_UNRESOLVED; + return -ENOENT; + } + + if (VIF_EXISTS(mrt, c->mfc_parent) && + nla_put_u32(skb, RTA_IIF, + mrt->vif_table[c->mfc_parent].dev->ifindex) < 0) + return -EMSGSIZE; + + if (c->mfc_flags & MFC_OFFLOAD) + rtm->rtm_flags |= RTNH_F_OFFLOAD; + + mp_attr = nla_nest_start(skb, RTA_MULTIPATH); + if (!mp_attr) + return -EMSGSIZE; + + for (ct = c->mfc_un.res.minvif; ct < c->mfc_un.res.maxvif; ct++) { + if (VIF_EXISTS(mrt, ct) && c->mfc_un.res.ttls[ct] < 255) { + struct vif_device *vif; + + nhp = nla_reserve_nohdr(skb, sizeof(*nhp)); + if (!nhp) { + nla_nest_cancel(skb, mp_attr); + return -EMSGSIZE; + } + + nhp->rtnh_flags = 0; + nhp->rtnh_hops = c->mfc_un.res.ttls[ct]; + vif = &mrt->vif_table[ct]; + nhp->rtnh_ifindex = vif->dev->ifindex; + nhp->rtnh_len = sizeof(*nhp); + } + } + + nla_nest_end(skb, mp_attr); + + lastuse = READ_ONCE(c->mfc_un.res.lastuse); + lastuse = time_after_eq(jiffies, lastuse) ? jiffies - lastuse : 0; + + mfcs.mfcs_packets = c->mfc_un.res.pkt; + mfcs.mfcs_bytes = c->mfc_un.res.bytes; + mfcs.mfcs_wrong_if = c->mfc_un.res.wrong_if; + if (nla_put_64bit(skb, RTA_MFC_STATS, sizeof(mfcs), &mfcs, RTA_PAD) || + nla_put_u64_64bit(skb, RTA_EXPIRES, jiffies_to_clock_t(lastuse), + RTA_PAD)) + return -EMSGSIZE; + + rtm->rtm_type = RTN_MULTICAST; + return 1; +} +EXPORT_SYMBOL(mr_fill_mroute); + +int mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb, + struct mr_table *(*iter)(struct net *net, + struct mr_table *mrt), + int (*fill)(struct mr_table *mrt, + struct sk_buff *skb, + u32 portid, u32 seq, struct mr_mfc *c, + int cmd, int flags), + spinlock_t *lock) +{ + unsigned int t = 0, e = 0, s_t = cb->args[0], s_e = cb->args[1]; + struct net *net = sock_net(skb->sk); + struct mr_table *mrt; + struct mr_mfc *mfc; + + rcu_read_lock(); + for (mrt = iter(net, NULL); mrt; mrt = iter(net, mrt)) { + if (t < s_t) + goto next_table; + list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) { + if (e < s_e) + goto next_entry; + if (fill(mrt, skb, NETLINK_CB(cb->skb).portid, + cb->nlh->nlmsg_seq, mfc, + RTM_NEWROUTE, NLM_F_MULTI) < 0) + goto done; +next_entry: + e++; + } + e = 0; + s_e = 0; + + spin_lock_bh(lock); + list_for_each_entry(mfc, &mrt->mfc_unres_queue, list) { + if (e < s_e) + goto next_entry2; + if (fill(mrt, skb, NETLINK_CB(cb->skb).portid, + cb->nlh->nlmsg_seq, mfc, + RTM_NEWROUTE, NLM_F_MULTI) < 0) { + spin_unlock_bh(lock); + goto done; + } +next_entry2: + e++; + } + spin_unlock_bh(lock); + e = 0; + s_e = 0; +next_table: + t++; + } +done: + rcu_read_unlock(); + + cb->args[1] = e; + cb->args[0] = t; + + return skb->len; +} +EXPORT_SYMBOL(mr_rtm_dumproute); diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index c3b3f1c381e1..2a38f9de45d3 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -87,8 +87,6 @@ static void ip6_mr_forward(struct net *net, struct mr_table *mrt, struct sk_buff *skb, struct mfc6_cache *cache); static int ip6mr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, mifi_t mifi, int assert); -static int __ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, - struct mfc6_cache *c, struct rtmsg *rtm); static void mr6_netlink_event(struct mr_table *mrt, struct mfc6_cache *mfc, int cmd); static void mrt6msg_netlink_event(struct mr_table *mrt, struct sk_buff *pkt); @@ -101,6 +99,23 @@ static void ipmr_expire_process(struct timer_list *t); #define ip6mr_for_each_table(mrt, net) \ list_for_each_entry_rcu(mrt, &net->ipv6.mr6_tables, list) +static struct mr_table *ip6mr_mr_table_iter(struct net *net, + struct mr_table *mrt) +{ + struct mr_table *ret; + + if (!mrt) + ret = list_entry_rcu(net->ipv6.mr6_tables.next, + struct mr_table, list); + else + ret = list_entry_rcu(mrt->list.next, + struct mr_table, list); + + if (&ret->list == &net->ipv6.mr6_tables) + return NULL; + return ret; +} + static struct mr_table *ip6mr_get_table(struct net *net, u32 id) { struct mr_table *mrt; @@ -247,6 +262,14 @@ static void __net_exit ip6mr_rules_exit(struct net *net) #define ip6mr_for_each_table(mrt, net) \ for (mrt = net->ipv6.mrt6; mrt; mrt = NULL) +static struct mr_table *ip6mr_mr_table_iter(struct net *net, + struct mr_table *mrt) +{ + if (!mrt) + return net->ipv6.mrt6; + return NULL; +} + static struct mr_table *ip6mr_get_table(struct net *net, u32 id) { return net->ipv6.mrt6; @@ -948,7 +971,8 @@ static void ip6mr_cache_resolve(struct net *net, struct mr_table *mrt, struct nlmsghdr *nlh = skb_pull(skb, sizeof(struct ipv6hdr)); - if (__ip6mr_fill_mroute(mrt, skb, c, nlmsg_data(nlh)) > 0) { + if (mr_fill_mroute(mrt, skb, &c->_c, + nlmsg_data(nlh)) > 0) { nlh->nlmsg_len = skb_tail_pointer(skb) - (u8 *)nlh; } else { nlh->nlmsg_type = NLMSG_ERROR; @@ -2081,63 +2105,6 @@ int ip6_mr_input(struct sk_buff *skb) return 0; } - -static int __ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, - struct mfc6_cache *c, struct rtmsg *rtm) -{ - struct rta_mfc_stats mfcs; - struct nlattr *mp_attr; - struct rtnexthop *nhp; - unsigned long lastuse; - int ct; - - /* If cache is unresolved, don't try to parse IIF and OIF */ - if (c->_c.mfc_parent >= MAXMIFS) { - rtm->rtm_flags |= RTNH_F_UNRESOLVED; - return -ENOENT; - } - - if (VIF_EXISTS(mrt, c->_c.mfc_parent) && - nla_put_u32(skb, RTA_IIF, - mrt->vif_table[c->_c.mfc_parent].dev->ifindex) < 0) - return -EMSGSIZE; - mp_attr = nla_nest_start(skb, RTA_MULTIPATH); - if (!mp_attr) - return -EMSGSIZE; - - for (ct = c->_c.mfc_un.res.minvif; - ct < c->_c.mfc_un.res.maxvif; ct++) { - if (VIF_EXISTS(mrt, ct) && c->_c.mfc_un.res.ttls[ct] < 255) { - nhp = nla_reserve_nohdr(skb, sizeof(*nhp)); - if (!nhp) { - nla_nest_cancel(skb, mp_attr); - return -EMSGSIZE; - } - - nhp->rtnh_flags = 0; - nhp->rtnh_hops = c->_c.mfc_un.res.ttls[ct]; - nhp->rtnh_ifindex = mrt->vif_table[ct].dev->ifindex; - nhp->rtnh_len = sizeof(*nhp); - } - } - - nla_nest_end(skb, mp_attr); - - lastuse = READ_ONCE(c->_c.mfc_un.res.lastuse); - lastuse = time_after_eq(jiffies, lastuse) ? jiffies - lastuse : 0; - - mfcs.mfcs_packets = c->_c.mfc_un.res.pkt; - mfcs.mfcs_bytes = c->_c.mfc_un.res.bytes; - mfcs.mfcs_wrong_if = c->_c.mfc_un.res.wrong_if; - if (nla_put_64bit(skb, RTA_MFC_STATS, sizeof(mfcs), &mfcs, RTA_PAD) || - nla_put_u64_64bit(skb, RTA_EXPIRES, jiffies_to_clock_t(lastuse), - RTA_PAD)) - return -EMSGSIZE; - - rtm->rtm_type = RTN_MULTICAST; - return 1; -} - int ip6mr_get_route(struct net *net, struct sk_buff *skb, struct rtmsg *rtm, u32 portid) { @@ -2203,7 +2170,7 @@ int ip6mr_get_route(struct net *net, struct sk_buff *skb, struct rtmsg *rtm, return err; } - err = __ip6mr_fill_mroute(mrt, skb, cache, rtm); + err = mr_fill_mroute(mrt, skb, &cache->_c, rtm); read_unlock(&mrt_lock); return err; } @@ -2239,7 +2206,7 @@ static int ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, if (nla_put_in6_addr(skb, RTA_SRC, &c->mf6c_origin) || nla_put_in6_addr(skb, RTA_DST, &c->mf6c_mcastgrp)) goto nla_put_failure; - err = __ip6mr_fill_mroute(mrt, skb, c, rtm); + err = mr_fill_mroute(mrt, skb, &c->_c, rtm); /* do not break the dump if cache is unresolved */ if (err < 0 && err != -ENOENT) goto nla_put_failure; @@ -2252,6 +2219,14 @@ nla_put_failure: return -EMSGSIZE; } +static int _ip6mr_fill_mroute(struct mr_table *mrt, struct sk_buff *skb, + u32 portid, u32 seq, struct mr_mfc *c, + int cmd, int flags) +{ + return ip6mr_fill_mroute(mrt, skb, portid, seq, (struct mfc6_cache *)c, + cmd, flags); +} + static int mr6_msgsize(bool unresolved, int maxvif) { size_t len = @@ -2365,59 +2340,6 @@ errout: static int ip6mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb) { - struct net *net = sock_net(skb->sk); - unsigned int t = 0, s_t; - unsigned int e = 0, s_e; - struct mr_table *mrt; - struct mr_mfc *mfc; - - s_t = cb->args[0]; - s_e = cb->args[1]; - - rcu_read_lock(); - ip6mr_for_each_table(mrt, net) { - if (t < s_t) - goto next_table; - list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) { - if (e < s_e) - goto next_entry; - if (ip6mr_fill_mroute(mrt, skb, - NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, - (struct mfc6_cache *)mfc, - RTM_NEWROUTE, NLM_F_MULTI) < 0) - goto done; -next_entry: - e++; - } - e = 0; - s_e = 0; - - spin_lock_bh(&mfc_unres_lock); - list_for_each_entry(mfc, &mrt->mfc_unres_queue, list) { - if (e < s_e) - goto next_entry2; - if (ip6mr_fill_mroute(mrt, skb, - NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, - (struct mfc6_cache *)mfc, - RTM_NEWROUTE, NLM_F_MULTI) < 0) { - spin_unlock_bh(&mfc_unres_lock); - goto done; - } -next_entry2: - e++; - } - spin_unlock_bh(&mfc_unres_lock); - e = s_e = 0; -next_table: - t++; - } -done: - rcu_read_unlock(); - - cb->args[1] = e; - cb->args[0] = t; - - return skb->len; + return mr_rtm_dumproute(skb, cb, ip6mr_mr_table_iter, + _ip6mr_fill_mroute, &mfc_unres_lock); } -- cgit v1.2.3 From e8a714e086e42972fd0e2d59e90c28eb2d839429 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 1 Mar 2018 16:08:56 -0800 Subject: net: phy: Export gen10g_* functions In order to remove a fair amount of duplication in the different 10G PHY drivers, export all gen10g_* functions to be able to make use of those. While we are at it, rename gen10g_soft_reset() to gen10g_no_soft_reset() to illustrate what it does. Signed-off-by: Florian Fainelli --- drivers/net/phy/phy-c45.c | 20 +++++++++++++------- include/linux/phy.h | 8 ++++++++ 2 files changed, 21 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c index a4576859afae..0017eddc24db 100644 --- a/drivers/net/phy/phy-c45.c +++ b/drivers/net/phy/phy-c45.c @@ -268,12 +268,13 @@ EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); /* The gen10g_* functions are the old Clause 45 stub */ -static int gen10g_config_aneg(struct phy_device *phydev) +int gen10g_config_aneg(struct phy_device *phydev) { return 0; } +EXPORT_SYMBOL_GPL(gen10g_config_aneg); -static int gen10g_read_status(struct phy_device *phydev) +int gen10g_read_status(struct phy_device *phydev) { u32 mmd_mask = phydev->c45_ids.devices_in_package; int ret; @@ -291,14 +292,16 @@ static int gen10g_read_status(struct phy_device *phydev) return 0; } +EXPORT_SYMBOL_GPL(gen10g_read_status); -static int gen10g_soft_reset(struct phy_device *phydev) +int gen10g_no_soft_reset(struct phy_device *phydev) { /* Do nothing for now */ return 0; } +EXPORT_SYMBOL_GPL(gen10g_no_soft_reset); -static int gen10g_config_init(struct phy_device *phydev) +int gen10g_config_init(struct phy_device *phydev) { /* Temporarily just say we support everything */ phydev->supported = SUPPORTED_10000baseT_Full; @@ -306,22 +309,25 @@ static int gen10g_config_init(struct phy_device *phydev) return 0; } +EXPORT_SYMBOL_GPL(gen10g_config_init); -static int gen10g_suspend(struct phy_device *phydev) +int gen10g_suspend(struct phy_device *phydev) { return 0; } +EXPORT_SYMBOL_GPL(gen10g_suspend); -static int gen10g_resume(struct phy_device *phydev) +int gen10g_resume(struct phy_device *phydev) { return 0; } +EXPORT_SYMBOL_GPL(gen10g_resume); struct phy_driver genphy_10g_driver = { .phy_id = 0xffffffff, .phy_id_mask = 0xffffffff, .name = "Generic 10G PHY", - .soft_reset = gen10g_soft_reset, + .soft_reset = gen10g_no_soft_reset, .config_init = gen10g_config_init, .features = 0, .config_aneg = gen10g_config_aneg, diff --git a/include/linux/phy.h b/include/linux/phy.h index 5a0c3e53e7c2..6e38c699b753 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -994,6 +994,14 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev); int genphy_c45_an_disable_aneg(struct phy_device *phydev); int genphy_c45_read_mdix(struct phy_device *phydev); +/* The gen10g_* functions are the old Clause 45 stub */ +int gen10g_config_aneg(struct phy_device *phydev); +int gen10g_read_status(struct phy_device *phydev); +int gen10g_no_soft_reset(struct phy_device *phydev); +int gen10g_config_init(struct phy_device *phydev); +int gen10g_suspend(struct phy_device *phydev); +int gen10g_resume(struct phy_device *phydev); + static inline int phy_read_status(struct phy_device *phydev) { if (!phydev->drv) -- cgit v1.2.3 From 7576594c8e69f5a9e08c5b952d5139bb43574bbc Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Feb 2018 23:35:54 +0100 Subject: mtd: nand: remove useless fields from pxa3xx NAND platform data The "enable arbiter" bit is available only for pxa3xx based platforms but it was experimentally shown that even if this bit is reserved, some Marvell platforms (64-bit) actually need it to be set. The driver always set this bit regardless of this property, which is harmless. Then this property is not needed. The "num_cs" field is always 1 and for a good reason, the old driver (pxa3xx_nand.c) could only handle one. The new driver that replaces it (marvell_nand.c) can handle more, but better use device tree for such description. As there is only one available chip select, there is no need for an array of partitions neither an array of partition numbers. Signed-off-by: Miquel Raynal Acked-by: Robert Jarzmik Signed-off-by: Boris Brezillon --- arch/arm/mach-mmp/aspenite.c | 6 ++-- arch/arm/mach-mmp/ttc_dkb.c | 5 +--- arch/arm/mach-pxa/cm-x300.c | 6 ++-- arch/arm/mach-pxa/colibri-pxa3xx.c | 6 ++-- arch/arm/mach-pxa/littleton.c | 6 ++-- arch/arm/mach-pxa/mxm8x10.c | 6 ++-- arch/arm/mach-pxa/raumfeld.c | 6 ++-- arch/arm/mach-pxa/zylonite.c | 6 ++-- drivers/mtd/nand/marvell_nand.c | 3 +- include/linux/platform_data/mtd-nand-pxa3xx.h | 43 ++++++++------------------- 10 files changed, 28 insertions(+), 65 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index d2283009a5ff..6c2ebf01893a 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -172,10 +172,8 @@ static struct mtd_partition aspenite_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data aspenite_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, - .parts[0] = aspenite_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(aspenite_nand_partitions), + .parts = aspenite_nand_partitions, + .nr_parts = ARRAY_SIZE(aspenite_nand_partitions), }; static struct i2c_board_info aspenite_i2c_info[] __initdata = { diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index e0b6073c61a7..c7897fb2b6da 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -179,10 +179,7 @@ static struct mv_usb_platform_data ttc_usb_pdata = { #endif #if IS_ENABLED(CONFIG_MTD_NAND_MARVELL) -static struct pxa3xx_nand_platform_data dkb_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, -}; +static struct pxa3xx_nand_platform_data dkb_nand_info = {}; #endif #if IS_ENABLED(CONFIG_MMP_DISP) diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index de1f8c995076..0e71799cab25 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -429,11 +429,9 @@ static struct mtd_partition cm_x300_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data cm_x300_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = cm_x300_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(cm_x300_nand_partitions), + .parts = cm_x300_nand_partitions, + .nr_parts = ARRAY_SIZE(cm_x300_nand_partitions), }; static void __init cm_x300_init_nand(void) diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 3018eafd723e..e31a591e949f 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -138,11 +138,9 @@ static struct mtd_partition colibri_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data colibri_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = colibri_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(colibri_nand_partitions), + .parts = colibri_nand_partitions, + .nr_parts = ARRAY_SIZE(colibri_nand_partitions), }; void __init colibri_pxa3xx_init_nand(void) diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 193dccca1086..9e132b3e48c6 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -329,10 +329,8 @@ static struct mtd_partition littleton_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data littleton_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, - .parts[0] = littleton_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(littleton_nand_partitions), + .parts = littleton_nand_partitions, + .nr_parts = ARRAY_SIZE(littleton_nand_partitions), }; static void __init littleton_init_nand(void) diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c index 5cc379c0626c..616b22397d73 100644 --- a/arch/arm/mach-pxa/mxm8x10.c +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -389,11 +389,9 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = mxm_8x10_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(mxm_8x10_nand_partitions) + .parts = mxm_8x10_nand_partitions, + .nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions) }; static void __init mxm_8x10_nand_init(void) diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 4d5d05cf87d6..8c95ae58312a 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -346,11 +346,9 @@ static struct mtd_partition raumfeld_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data raumfeld_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = raumfeld_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(raumfeld_nand_partitions), + .parts = raumfeld_nand_partitions, + .nr_parts = ARRAY_SIZE(raumfeld_nand_partitions), }; /** diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 3a99fc054e96..d69de312d8d9 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -376,10 +376,8 @@ static struct mtd_partition zylonite_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data zylonite_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, - .parts[0] = zylonite_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(zylonite_nand_partitions), + .parts = zylonite_nand_partitions, + .nr_parts = ARRAY_SIZE(zylonite_nand_partitions), }; static void __init zylonite_init_nand(void) diff --git a/drivers/mtd/nand/marvell_nand.c b/drivers/mtd/nand/marvell_nand.c index 2196f2a233d6..03805f9669da 100644 --- a/drivers/mtd/nand/marvell_nand.c +++ b/drivers/mtd/nand/marvell_nand.c @@ -2520,8 +2520,7 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc, if (pdata) /* Legacy bindings support only one chip */ - ret = mtd_device_register(mtd, pdata->parts[0], - pdata->nr_parts[0]); + ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); else ret = mtd_device_register(mtd, NULL, 0); if (ret) { diff --git a/include/linux/platform_data/mtd-nand-pxa3xx.h b/include/linux/platform_data/mtd-nand-pxa3xx.h index b42ad83cbc20..4fd0f592a2d2 100644 --- a/include/linux/platform_data/mtd-nand-pxa3xx.h +++ b/include/linux/platform_data/mtd-nand-pxa3xx.h @@ -6,41 +6,22 @@ #include /* - * Current pxa3xx_nand controller has two chip select which - * both be workable. - * - * Notice should be taken that: - * When you want to use this feature, you should not enable the - * keep configuration feature, for two chip select could be - * attached with different nand chip. The different page size - * and timing requirement make the keep configuration impossible. + * Current pxa3xx_nand controller has two chip select which both be workable but + * historically all platforms remaining on platform data used only one. Switch + * to device tree if you need more. */ - -/* The max num of chip select current support */ -#define NUM_CHIP_SELECT (2) struct pxa3xx_nand_platform_data { - - /* the data flash bus is shared between the Static Memory - * Controller and the Data Flash Controller, the arbiter - * controls the ownership of the bus - */ - int enable_arbiter; - - /* allow platform code to keep OBM/bootloader defined NFC config */ - int keep_config; - - /* indicate how many chip selects will be used */ - int num_cs; - - /* use an flash-based bad block table */ - bool flash_bbt; - - /* requested ECC strength and ECC step size */ + /* Keep OBM/bootloader NFC timing configuration */ + bool keep_config; + /* Use a flash-based bad block table */ + bool flash_bbt; + /* Requested ECC strength and ECC step size */ int ecc_strength, ecc_step_size; - - const struct mtd_partition *parts[NUM_CHIP_SELECT]; - unsigned int nr_parts[NUM_CHIP_SELECT]; + /* Partitions */ + const struct mtd_partition *parts; + unsigned int nr_parts; }; extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); + #endif /* __ASM_ARCH_PXA3XX_NAND_H */ -- cgit v1.2.3 From fde9fc766e96c494b82931b1d270a9a751be07c0 Mon Sep 17 00:00:00 2001 From: Matt Redfearn Date: Mon, 19 Feb 2018 16:55:06 +0000 Subject: signals: Move put_compat_sigset to compat.h to silence hardened usercopy Since commit afcc90f8621e ("usercopy: WARN() on slab cache usercopy region violations"), MIPS systems booting with a compat root filesystem emit a warning when copying compat siginfo to userspace: WARNING: CPU: 0 PID: 953 at mm/usercopy.c:81 usercopy_warn+0x98/0xe8 Bad or missing usercopy whitelist? Kernel memory exposure attempt detected from SLAB object 'task_struct' (offset 1432, size 16)! Modules linked in: CPU: 0 PID: 953 Comm: S01logging Not tainted 4.16.0-rc2 #10 Stack : ffffffff808c0000 0000000000000000 0000000000000001 65ac85163f3bdc4a 65ac85163f3bdc4a 0000000000000000 90000000ff667ab8 ffffffff808c0000 00000000000003f8 ffffffff808d0000 00000000000000d1 0000000000000000 000000000000003c 0000000000000000 ffffffff808c8ca8 ffffffff808d0000 ffffffff808d0000 ffffffff80810000 fffffc0000000000 ffffffff80785c30 0000000000000009 0000000000000051 90000000ff667eb0 90000000ff667db0 000000007fe0d938 0000000000000018 ffffffff80449958 0000000020052798 ffffffff808c0000 90000000ff664000 90000000ff667ab0 00000000100c0000 ffffffff80698810 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ffffffff8010d02c 65ac85163f3bdc4a ... Call Trace: [] show_stack+0x9c/0x130 [] dump_stack+0x90/0xd0 [] __warn+0x100/0x118 [] warn_slowpath_fmt+0x4c/0x70 [] usercopy_warn+0x98/0xe8 [] __check_object_size+0xfc/0x250 [] put_compat_sigset+0x30/0x88 [] setup_rt_frame_n32+0xc4/0x160 [] do_signal+0x19c/0x230 [] do_notify_resume+0x60/0x78 [] work_notifysig+0x10/0x18 ---[ end trace 88fffbf69147f48a ]--- Commit 5905429ad856 ("fork: Provide usercopy whitelisting for task_struct") noted that: "While the blocked and saved_sigmask fields of task_struct are copied to userspace (via sigmask_to_save() and setup_rt_frame()), it is always copied with a static length (i.e. sizeof(sigset_t))." However, this is not true in the case of compat signals, whose sigset is copied by put_compat_sigset and receives size as an argument. At most call sites, put_compat_sigset is copying a sigset from the current task_struct. This triggers a warning when CONFIG_HARDENED_USERCOPY is active. However, by marking this function as static inline, the warning can be avoided because in all of these cases the size is constant at compile time, which is allowed. The only site where this is not the case is handling the rt_sigpending syscall, but there the copy is being made from a stack local variable so does not trigger the warning. Move put_compat_sigset to compat.h, and mark it static inline. This fixes the WARN on MIPS. Fixes: afcc90f8621e ("usercopy: WARN() on slab cache usercopy region violations") Signed-off-by: Matt Redfearn Acked-by: Kees Cook Cc: "Dmitry V . Levin" Cc: Al Viro Cc: kernel-hardening@lists.openwall.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18639/ Signed-off-by: James Hogan --- include/linux/compat.h | 26 ++++++++++++++++++++++++-- kernel/compat.c | 19 ------------------- 2 files changed, 24 insertions(+), 21 deletions(-) (limited to 'include/linux') diff --git a/include/linux/compat.h b/include/linux/compat.h index 8a9643857c4a..c4139c7a0de0 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -17,6 +17,7 @@ #include #include #include /* for aio_context_t */ +#include #include #include @@ -550,8 +551,29 @@ asmlinkage long compat_sys_settimeofday(struct compat_timeval __user *tv, asmlinkage long compat_sys_adjtimex(struct compat_timex __user *utp); extern int get_compat_sigset(sigset_t *set, const compat_sigset_t __user *compat); -extern int put_compat_sigset(compat_sigset_t __user *compat, - const sigset_t *set, unsigned int size); + +/* + * Defined inline such that size can be compile time constant, which avoids + * CONFIG_HARDENED_USERCOPY complaining about copies from task_struct + */ +static inline int +put_compat_sigset(compat_sigset_t __user *compat, const sigset_t *set, + unsigned int size) +{ + /* size <= sizeof(compat_sigset_t) <= sizeof(sigset_t) */ +#ifdef __BIG_ENDIAN + compat_sigset_t v; + switch (_NSIG_WORDS) { + case 4: v.sig[7] = (set->sig[3] >> 32); v.sig[6] = set->sig[3]; + case 3: v.sig[5] = (set->sig[2] >> 32); v.sig[4] = set->sig[2]; + case 2: v.sig[3] = (set->sig[1] >> 32); v.sig[2] = set->sig[1]; + case 1: v.sig[1] = (set->sig[0] >> 32); v.sig[0] = set->sig[0]; + } + return copy_to_user(compat, &v, size) ? -EFAULT : 0; +#else + return copy_to_user(compat, set, size) ? -EFAULT : 0; +#endif +} asmlinkage long compat_sys_migrate_pages(compat_pid_t pid, compat_ulong_t maxnode, const compat_ulong_t __user *old_nodes, diff --git a/kernel/compat.c b/kernel/compat.c index 3247fe761f60..3f5fa8902e7d 100644 --- a/kernel/compat.c +++ b/kernel/compat.c @@ -488,25 +488,6 @@ get_compat_sigset(sigset_t *set, const compat_sigset_t __user *compat) } EXPORT_SYMBOL_GPL(get_compat_sigset); -int -put_compat_sigset(compat_sigset_t __user *compat, const sigset_t *set, - unsigned int size) -{ - /* size <= sizeof(compat_sigset_t) <= sizeof(sigset_t) */ -#ifdef __BIG_ENDIAN - compat_sigset_t v; - switch (_NSIG_WORDS) { - case 4: v.sig[7] = (set->sig[3] >> 32); v.sig[6] = set->sig[3]; - case 3: v.sig[5] = (set->sig[2] >> 32); v.sig[4] = set->sig[2]; - case 2: v.sig[3] = (set->sig[1] >> 32); v.sig[2] = set->sig[1]; - case 1: v.sig[1] = (set->sig[0] >> 32); v.sig[0] = set->sig[0]; - } - return copy_to_user(compat, &v, size) ? -EFAULT : 0; -#else - return copy_to_user(compat, set, size) ? -EFAULT : 0; -#endif -} - #ifdef CONFIG_NUMA COMPAT_SYSCALL_DEFINE6(move_pages, pid_t, pid, compat_ulong_t, nr_pages, compat_uptr_t __user *, pages32, -- cgit v1.2.3 From d02f51cbcf12b09ab945873e35046045875eed9a Mon Sep 17 00:00:00 2001 From: Daniel Axtens Date: Sat, 3 Mar 2018 03:03:46 +0100 Subject: bpf: fix bpf_skb_adjust_net/bpf_skb_proto_xlat to deal with gso sctp skbs SCTP GSO skbs have a gso_size of GSO_BY_FRAGS, so any sort of unconditionally mangling of that will result in nonsense value and would corrupt the skb later on. Therefore, i) add two helpers skb_increase_gso_size() and skb_decrease_gso_size() that would throw a one time warning and bail out for such skbs and ii) refuse and return early with an error in those BPF helpers that are affected. We do need to bail out as early as possible from there before any changes on the skb have been performed. Fixes: 6578171a7ff0 ("bpf: add bpf_skb_change_proto helper") Co-authored-by: Daniel Borkmann Signed-off-by: Daniel Axtens Cc: Marcelo Ricardo Leitner Acked-by: Alexei Starovoitov Signed-off-by: Alexei Starovoitov --- Documentation/networking/segmentation-offloads.txt | 11 +++- include/linux/skbuff.h | 22 ++++++++ net/core/filter.c | 60 +++++++++++++++------- 3 files changed, 73 insertions(+), 20 deletions(-) (limited to 'include/linux') diff --git a/Documentation/networking/segmentation-offloads.txt b/Documentation/networking/segmentation-offloads.txt index d47480b61ac6..23a8dd91a9ec 100644 --- a/Documentation/networking/segmentation-offloads.txt +++ b/Documentation/networking/segmentation-offloads.txt @@ -153,8 +153,15 @@ To signal this, gso_size is set to the special value GSO_BY_FRAGS. Therefore, any code in the core networking stack must be aware of the possibility that gso_size will be GSO_BY_FRAGS and handle that case -appropriately. (For size checks, the skb_gso_validate_*_len family of -helpers do this automatically.) +appropriately. + +There are a couple of helpers to make this easier: + + - For size checks, the skb_gso_validate_*_len family of helpers correctly + considers GSO_BY_FRAGS. + + - For manipulating packets, skb_increase_gso_size and skb_decrease_gso_size + will check for GSO_BY_FRAGS and WARN if asked to manipulate these skbs. This also affects drivers with the NETIF_F_FRAGLIST & NETIF_F_GSO_SCTP bits set. Note also that NETIF_F_GSO_SCTP is included in NETIF_F_GSO_SOFTWARE. diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index c1e66bdcf583..8c67c33f40c9 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -4038,6 +4038,12 @@ static inline bool skb_is_gso_v6(const struct sk_buff *skb) return skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6; } +/* Note: Should be called only if skb_is_gso(skb) is true */ +static inline bool skb_is_gso_sctp(const struct sk_buff *skb) +{ + return skb_shinfo(skb)->gso_type & SKB_GSO_SCTP; +} + static inline void skb_gso_reset(struct sk_buff *skb) { skb_shinfo(skb)->gso_size = 0; @@ -4045,6 +4051,22 @@ static inline void skb_gso_reset(struct sk_buff *skb) skb_shinfo(skb)->gso_type = 0; } +static inline void skb_increase_gso_size(struct skb_shared_info *shinfo, + u16 increment) +{ + if (WARN_ON_ONCE(shinfo->gso_size == GSO_BY_FRAGS)) + return; + shinfo->gso_size += increment; +} + +static inline void skb_decrease_gso_size(struct skb_shared_info *shinfo, + u16 decrement) +{ + if (WARN_ON_ONCE(shinfo->gso_size == GSO_BY_FRAGS)) + return; + shinfo->gso_size -= decrement; +} + void __skb_warn_lro_forwarding(const struct sk_buff *skb); static inline bool skb_warn_if_lro(const struct sk_buff *skb) diff --git a/net/core/filter.c b/net/core/filter.c index 0c121adbdbaa..48aa7c7320db 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -2087,6 +2087,10 @@ static int bpf_skb_proto_4_to_6(struct sk_buff *skb) u32 off = skb_mac_header_len(skb); int ret; + /* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */ + if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb))) + return -ENOTSUPP; + ret = skb_cow(skb, len_diff); if (unlikely(ret < 0)) return ret; @@ -2096,19 +2100,21 @@ static int bpf_skb_proto_4_to_6(struct sk_buff *skb) return ret; if (skb_is_gso(skb)) { + struct skb_shared_info *shinfo = skb_shinfo(skb); + /* SKB_GSO_TCPV4 needs to be changed into * SKB_GSO_TCPV6. */ - if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { - skb_shinfo(skb)->gso_type &= ~SKB_GSO_TCPV4; - skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6; + if (shinfo->gso_type & SKB_GSO_TCPV4) { + shinfo->gso_type &= ~SKB_GSO_TCPV4; + shinfo->gso_type |= SKB_GSO_TCPV6; } /* Due to IPv6 header, MSS needs to be downgraded. */ - skb_shinfo(skb)->gso_size -= len_diff; + skb_decrease_gso_size(shinfo, len_diff); /* Header must be checked, and gso_segs recomputed. */ - skb_shinfo(skb)->gso_type |= SKB_GSO_DODGY; - skb_shinfo(skb)->gso_segs = 0; + shinfo->gso_type |= SKB_GSO_DODGY; + shinfo->gso_segs = 0; } skb->protocol = htons(ETH_P_IPV6); @@ -2123,6 +2129,10 @@ static int bpf_skb_proto_6_to_4(struct sk_buff *skb) u32 off = skb_mac_header_len(skb); int ret; + /* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */ + if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb))) + return -ENOTSUPP; + ret = skb_unclone(skb, GFP_ATOMIC); if (unlikely(ret < 0)) return ret; @@ -2132,19 +2142,21 @@ static int bpf_skb_proto_6_to_4(struct sk_buff *skb) return ret; if (skb_is_gso(skb)) { + struct skb_shared_info *shinfo = skb_shinfo(skb); + /* SKB_GSO_TCPV6 needs to be changed into * SKB_GSO_TCPV4. */ - if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { - skb_shinfo(skb)->gso_type &= ~SKB_GSO_TCPV6; - skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4; + if (shinfo->gso_type & SKB_GSO_TCPV6) { + shinfo->gso_type &= ~SKB_GSO_TCPV6; + shinfo->gso_type |= SKB_GSO_TCPV4; } /* Due to IPv4 header, MSS can be upgraded. */ - skb_shinfo(skb)->gso_size += len_diff; + skb_increase_gso_size(shinfo, len_diff); /* Header must be checked, and gso_segs recomputed. */ - skb_shinfo(skb)->gso_type |= SKB_GSO_DODGY; - skb_shinfo(skb)->gso_segs = 0; + shinfo->gso_type |= SKB_GSO_DODGY; + shinfo->gso_segs = 0; } skb->protocol = htons(ETH_P_IP); @@ -2243,6 +2255,10 @@ static int bpf_skb_net_grow(struct sk_buff *skb, u32 len_diff) u32 off = skb_mac_header_len(skb) + bpf_skb_net_base_len(skb); int ret; + /* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */ + if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb))) + return -ENOTSUPP; + ret = skb_cow(skb, len_diff); if (unlikely(ret < 0)) return ret; @@ -2252,11 +2268,13 @@ static int bpf_skb_net_grow(struct sk_buff *skb, u32 len_diff) return ret; if (skb_is_gso(skb)) { + struct skb_shared_info *shinfo = skb_shinfo(skb); + /* Due to header grow, MSS needs to be downgraded. */ - skb_shinfo(skb)->gso_size -= len_diff; + skb_decrease_gso_size(shinfo, len_diff); /* Header must be checked, and gso_segs recomputed. */ - skb_shinfo(skb)->gso_type |= SKB_GSO_DODGY; - skb_shinfo(skb)->gso_segs = 0; + shinfo->gso_type |= SKB_GSO_DODGY; + shinfo->gso_segs = 0; } return 0; @@ -2267,6 +2285,10 @@ static int bpf_skb_net_shrink(struct sk_buff *skb, u32 len_diff) u32 off = skb_mac_header_len(skb) + bpf_skb_net_base_len(skb); int ret; + /* SCTP uses GSO_BY_FRAGS, thus cannot adjust it. */ + if (skb_is_gso(skb) && unlikely(skb_is_gso_sctp(skb))) + return -ENOTSUPP; + ret = skb_unclone(skb, GFP_ATOMIC); if (unlikely(ret < 0)) return ret; @@ -2276,11 +2298,13 @@ static int bpf_skb_net_shrink(struct sk_buff *skb, u32 len_diff) return ret; if (skb_is_gso(skb)) { + struct skb_shared_info *shinfo = skb_shinfo(skb); + /* Due to header shrink, MSS can be upgraded. */ - skb_shinfo(skb)->gso_size += len_diff; + skb_increase_gso_size(shinfo, len_diff); /* Header must be checked, and gso_segs recomputed. */ - skb_shinfo(skb)->gso_type |= SKB_GSO_DODGY; - skb_shinfo(skb)->gso_segs = 0; + shinfo->gso_type |= SKB_GSO_DODGY; + shinfo->gso_segs = 0; } return 0; -- cgit v1.2.3 From 39a751a4cb7e4798f0ce1169ec92de4a1aae39e3 Mon Sep 17 00:00:00 2001 From: Frank Rowand Date: Mon, 12 Feb 2018 00:19:42 -0800 Subject: of: change overlay apply input data from unflattened to FDT Move duplicating and unflattening of an overlay flattened devicetree (FDT) into the overlay application code. To accomplish this, of_overlay_apply() is replaced by of_overlay_fdt_apply(). The copy of the FDT (aka "duplicate FDT") now belongs to devicetree code, which is thus responsible for freeing the duplicate FDT. The caller of of_overlay_fdt_apply() remains responsible for freeing the original FDT. The unflattened devicetree now belongs to devicetree code, which is thus responsible for freeing the unflattened devicetree. These ownership changes prevent early freeing of the duplicated FDT or the unflattened devicetree, which could result in use after free errors. of_overlay_fdt_apply() is a private function for the anticipated overlay loader. Update unittest.c to use of_overlay_fdt_apply() instead of of_overlay_apply(). Move overlay fragments from artificial locations in drivers/of/unittest-data/tests-overlay.dtsi into one devicetree source file per overlay. This led to changes in drivers/of/unitest-data/Makefile and drivers/of/unitest.c. - Add overlay directives to the overlay devicetree source files so that dtc will compile them as true overlays into one FDT data chunk per overlay. - Set CFLAGS for drivers/of/unittest-data/testcases.dts so that symbols will be generated for overlay resolution of overlays that are no longer artificially contained in testcases.dts - Unflatten and apply each unittest overlay FDT using of_overlay_fdt_apply(). - Enable the of_resolve_phandles() check for whether the unflattened overlay is detached. This check was previously disabled because the overlays from tests-overlay.dtsi were not unflattened into detached trees. - Other changes to unittest.c infrastructure to manage multiple test FDTs built into the kernel image (access by name instead of arbitrary number). - of_unittest_overlay_high_level(): previously unused code to add properties from the overlay_base devicetree to the live tree was triggered by the restructuring of tests-overlay.dtsi and thus testcases.dts. This exposed two bugs: (1) the need to dup a property before adding it, and (2) property 'name' is auto-generated in the unflatten code and thus will be a duplicate in the __symbols__ node - do not treat this duplicate as an error. Signed-off-by: Frank Rowand --- drivers/of/Kconfig | 1 + drivers/of/overlay.c | 112 ++++++++++- drivers/of/resolver.c | 6 - drivers/of/unittest-data/Makefile | 28 ++- drivers/of/unittest-data/overlay_0.dts | 14 ++ drivers/of/unittest-data/overlay_1.dts | 14 ++ drivers/of/unittest-data/overlay_10.dts | 34 ++++ drivers/of/unittest-data/overlay_11.dts | 34 ++++ drivers/of/unittest-data/overlay_12.dts | 14 ++ drivers/of/unittest-data/overlay_13.dts | 14 ++ drivers/of/unittest-data/overlay_15.dts | 35 ++++ drivers/of/unittest-data/overlay_2.dts | 14 ++ drivers/of/unittest-data/overlay_3.dts | 14 ++ drivers/of/unittest-data/overlay_4.dts | 23 +++ drivers/of/unittest-data/overlay_5.dts | 14 ++ drivers/of/unittest-data/overlay_6.dts | 15 ++ drivers/of/unittest-data/overlay_7.dts | 15 ++ drivers/of/unittest-data/overlay_8.dts | 15 ++ drivers/of/unittest-data/overlay_9.dts | 15 ++ drivers/of/unittest-data/tests-overlay.dtsi | 213 -------------------- drivers/of/unittest.c | 300 ++++++++++++++-------------- include/linux/of.h | 6 +- 22 files changed, 562 insertions(+), 388 deletions(-) create mode 100644 drivers/of/unittest-data/overlay_0.dts create mode 100644 drivers/of/unittest-data/overlay_1.dts create mode 100644 drivers/of/unittest-data/overlay_10.dts create mode 100644 drivers/of/unittest-data/overlay_11.dts create mode 100644 drivers/of/unittest-data/overlay_12.dts create mode 100644 drivers/of/unittest-data/overlay_13.dts create mode 100644 drivers/of/unittest-data/overlay_15.dts create mode 100644 drivers/of/unittest-data/overlay_2.dts create mode 100644 drivers/of/unittest-data/overlay_3.dts create mode 100644 drivers/of/unittest-data/overlay_4.dts create mode 100644 drivers/of/unittest-data/overlay_5.dts create mode 100644 drivers/of/unittest-data/overlay_6.dts create mode 100644 drivers/of/unittest-data/overlay_7.dts create mode 100644 drivers/of/unittest-data/overlay_8.dts create mode 100644 drivers/of/unittest-data/overlay_9.dts (limited to 'include/linux') diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index 783e0870bd22..ad3fcad4d75b 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -92,6 +92,7 @@ config OF_RESOLVE config OF_OVERLAY bool "Device Tree overlays" select OF_DYNAMIC + select OF_FLATTREE select OF_RESOLVE help Overlays are a method to dynamically modify part of the kernel's diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index 3397d7642958..e3d7f69a8333 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -12,10 +12,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -33,7 +35,9 @@ struct fragment { /** * struct overlay_changeset + * @id: changeset identifier * @ovcs_list: list on which we are located + * @fdt: FDT that was unflattened to create @overlay_tree * @overlay_tree: expanded device tree that contains the fragment nodes * @count: count of fragment structures * @fragments: fragment nodes in the overlay expanded device tree @@ -43,6 +47,7 @@ struct fragment { struct overlay_changeset { int id; struct list_head ovcs_list; + const void *fdt; struct device_node *overlay_tree; int count; struct fragment *fragments; @@ -503,7 +508,8 @@ static struct device_node *find_target_node(struct device_node *info_node) /** * init_overlay_changeset() - initialize overlay changeset from overlay tree - * @ovcs Overlay changeset to build + * @ovcs: Overlay changeset to build + * @fdt: the FDT that was unflattened to create @tree * @tree: Contains all the overlay fragments and overlay fixup nodes * * Initialize @ovcs. Populate @ovcs->fragments with node information from @@ -514,7 +520,7 @@ static struct device_node *find_target_node(struct device_node *info_node) * detected in @tree, or -ENOSPC if idr_alloc() error. */ static int init_overlay_changeset(struct overlay_changeset *ovcs, - struct device_node *tree) + const void *fdt, struct device_node *tree) { struct device_node *node, *overlay_node; struct fragment *fragment; @@ -535,6 +541,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, pr_debug("%s() tree is not root\n", __func__); ovcs->overlay_tree = tree; + ovcs->fdt = fdt; INIT_LIST_HEAD(&ovcs->ovcs_list); @@ -606,6 +613,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs, } if (!cnt) { + pr_err("no fragments or symbols in overlay\n"); ret = -EINVAL; goto err_free_fragments; } @@ -642,11 +650,24 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs) } kfree(ovcs->fragments); + /* + * TODO + * + * would like to: kfree(ovcs->overlay_tree); + * but can not since drivers may have pointers into this data + * + * would like to: kfree(ovcs->fdt); + * but can not since drivers may have pointers into this data + */ + kfree(ovcs); } -/** +/* + * internal documentation + * * of_overlay_apply() - Create and apply an overlay changeset + * @fdt: the FDT that was unflattened to create @tree * @tree: Expanded overlay device tree * @ovcs_id: Pointer to overlay changeset id * @@ -685,21 +706,29 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs) * id is returned to *ovcs_id. */ -int of_overlay_apply(struct device_node *tree, int *ovcs_id) +static int of_overlay_apply(const void *fdt, struct device_node *tree, + int *ovcs_id) { struct overlay_changeset *ovcs; int ret = 0, ret_revert, ret_tmp; - *ovcs_id = 0; + /* + * As of this point, fdt and tree belong to the overlay changeset. + * overlay changeset code is responsible for freeing them. + */ if (devicetree_corrupt()) { pr_err("devicetree state suspect, refuse to apply overlay\n"); + kfree(fdt); + kfree(tree); ret = -EBUSY; goto out; } ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL); if (!ovcs) { + kfree(fdt); + kfree(tree); ret = -ENOMEM; goto out; } @@ -709,12 +738,17 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id) ret = of_resolve_phandles(tree); if (ret) - goto err_free_overlay_changeset; + goto err_free_tree; - ret = init_overlay_changeset(ovcs, tree); + ret = init_overlay_changeset(ovcs, fdt, tree); if (ret) - goto err_free_overlay_changeset; + goto err_free_tree; + /* + * after overlay_notify(), ovcs->overlay_tree related pointers may have + * leaked to drivers, so can not kfree() tree, aka ovcs->overlay_tree; + * and can not free fdt, aka ovcs->fdt + */ ret = overlay_notify(ovcs, OF_OVERLAY_PRE_APPLY); if (ret) { pr_err("overlay changeset pre-apply notify error %d\n", ret); @@ -754,6 +788,10 @@ int of_overlay_apply(struct device_node *tree, int *ovcs_id) goto out_unlock; +err_free_tree: + kfree(fdt); + kfree(tree); + err_free_overlay_changeset: free_overlay_changeset(ovcs); @@ -766,7 +804,63 @@ out: return ret; } -EXPORT_SYMBOL_GPL(of_overlay_apply); + +int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size, + int *ovcs_id) +{ + const void *new_fdt; + int ret; + u32 size; + struct device_node *overlay_root; + + *ovcs_id = 0; + ret = 0; + + if (overlay_fdt_size < sizeof(struct fdt_header) || + fdt_check_header(overlay_fdt)) { + pr_err("Invalid overlay_fdt header\n"); + return -EINVAL; + } + + size = fdt_totalsize(overlay_fdt); + if (overlay_fdt_size < size) + return -EINVAL; + + /* + * Must create permanent copy of FDT because of_fdt_unflatten_tree() + * will create pointers to the passed in FDT in the unflattened tree. + */ + new_fdt = kmemdup(overlay_fdt, size, GFP_KERNEL); + if (!new_fdt) + return -ENOMEM; + + of_fdt_unflatten_tree(new_fdt, NULL, &overlay_root); + if (!overlay_root) { + pr_err("unable to unflatten overlay_fdt\n"); + ret = -EINVAL; + goto out_free_new_fdt; + } + + ret = of_overlay_apply(new_fdt, overlay_root, ovcs_id); + if (ret < 0) { + /* + * new_fdt and overlay_root now belong to the overlay + * changeset. + * overlay changeset code is responsible for freeing them. + */ + goto out; + } + + return 0; + + +out_free_new_fdt: + kfree(new_fdt); + +out: + return ret; +} +EXPORT_SYMBOL_GPL(of_overlay_fdt_apply); /* * Find @np in @tree. diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c index 740d19bde601..b2f645187213 100644 --- a/drivers/of/resolver.c +++ b/drivers/of/resolver.c @@ -269,17 +269,11 @@ int of_resolve_phandles(struct device_node *overlay) goto out; } -#if 0 - Temporarily disable check so that old style overlay unittests - do not fail when of_resolve_phandles() is moved into - of_overlay_apply(). - if (!of_node_check_flag(overlay, OF_DETACHED)) { pr_err("overlay not detached\n"); err = -EINVAL; goto out; } -#endif phandle_delta = live_tree_max_phandle() + 1; adjust_overlay_phandles(overlay, phandle_delta); diff --git a/drivers/of/unittest-data/Makefile b/drivers/of/unittest-data/Makefile index df697976740a..8fd0ea4b92b0 100644 --- a/drivers/of/unittest-data/Makefile +++ b/drivers/of/unittest-data/Makefile @@ -1,8 +1,22 @@ # SPDX-License-Identifier: GPL-2.0 -DTC_FLAGS_testcases := -Wno-interrupts_property obj-y += testcases.dtb.o obj-$(CONFIG_OF_OVERLAY) += overlay.dtb.o \ + overlay_0.dtb.o \ + overlay_1.dtb.o \ + overlay_2.dtb.o \ + overlay_3.dtb.o \ + overlay_4.dtb.o \ + overlay_5.dtb.o \ + overlay_6.dtb.o \ + overlay_7.dtb.o \ + overlay_8.dtb.o \ + overlay_9.dtb.o \ + overlay_10.dtb.o \ + overlay_11.dtb.o \ + overlay_12.dtb.o \ + overlay_13.dtb.o \ + overlay_15.dtb.o \ overlay_bad_phandle.dtb.o \ overlay_bad_symbol.dtb.o \ overlay_base.dtb.o @@ -10,10 +24,14 @@ obj-$(CONFIG_OF_OVERLAY) += overlay.dtb.o \ targets += $(foreach suffix, dtb dtb.S, $(patsubst %.dtb.o,%.$(suffix),$(obj-y))) # enable creation of __symbols__ node -DTC_FLAGS_overlay := -@ -DTC_FLAGS_overlay_bad_phandle := -@ -DTC_FLAGS_overlay_bad_symbol := -@ -DTC_FLAGS_overlay_base := -@ +DTC_FLAGS_overlay += -@ +DTC_FLAGS_overlay_bad_phandle += -@ +DTC_FLAGS_overlay_bad_symbol += -@ +DTC_FLAGS_overlay_base += -@ +DTC_FLAGS_testcases += -@ + +# suppress warnings about intentional errors +DTC_FLAGS_testcases += -Wno-interrupts_property .PRECIOUS: \ $(obj)/%.dtb.S \ diff --git a/drivers/of/unittest-data/overlay_0.dts b/drivers/of/unittest-data/overlay_0.dts new file mode 100644 index 000000000000..ac0f9e0fe65f --- /dev/null +++ b/drivers/of/unittest-data/overlay_0.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_0 - enable using absolute target path */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/test-unittest0"; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_1.dts b/drivers/of/unittest-data/overlay_1.dts new file mode 100644 index 000000000000..e92a626e2948 --- /dev/null +++ b/drivers/of/unittest-data/overlay_1.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_1 - disable using absolute target path */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/test-unittest1"; + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_10.dts b/drivers/of/unittest-data/overlay_10.dts new file mode 100644 index 000000000000..445925a10cd3 --- /dev/null +++ b/drivers/of/unittest-data/overlay_10.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_10 */ + /* overlays 8, 9, 10, 11 application and removal in bad sequence */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus"; + __overlay__ { + + /* suppress DTC warning */ + #address-cells = <1>; + #size-cells = <0>; + + test-unittest10 { + compatible = "unittest"; + status = "okay"; + reg = <10>; + + #address-cells = <1>; + #size-cells = <0>; + + test-unittest101 { + compatible = "unittest"; + status = "okay"; + reg = <1>; + }; + + }; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_11.dts b/drivers/of/unittest-data/overlay_11.dts new file mode 100644 index 000000000000..c1d14f34359e --- /dev/null +++ b/drivers/of/unittest-data/overlay_11.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_11 */ + /* overlays 8, 9, 10, 11 application and removal in bad sequence */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus"; + __overlay__ { + + /* suppress DTC warning */ + #address-cells = <1>; + #size-cells = <0>; + + test-unittest11 { + compatible = "unittest"; + status = "okay"; + reg = <11>; + + #address-cells = <1>; + #size-cells = <0>; + + test-unittest111 { + compatible = "unittest"; + status = "okay"; + reg = <1>; + }; + + }; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_12.dts b/drivers/of/unittest-data/overlay_12.dts new file mode 100644 index 000000000000..ca3441e2cbec --- /dev/null +++ b/drivers/of/unittest-data/overlay_12.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_12 - enable using absolute target path (i2c) */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12"; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_13.dts b/drivers/of/unittest-data/overlay_13.dts new file mode 100644 index 000000000000..3c30dec63894 --- /dev/null +++ b/drivers/of/unittest-data/overlay_13.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_13 - disable using absolute target path (i2c) */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13"; + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_15.dts b/drivers/of/unittest-data/overlay_15.dts new file mode 100644 index 000000000000..44e44c62b739 --- /dev/null +++ b/drivers/of/unittest-data/overlay_15.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_15 - mux overlay */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + test-unittest15 { + reg = <11>; + compatible = "unittest-i2c-mux"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + test-mux-dev { + reg = <32>; + compatible = "unittest-i2c-dev"; + status = "okay"; + }; + }; + }; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_2.dts b/drivers/of/unittest-data/overlay_2.dts new file mode 100644 index 000000000000..cf1e4245b7ce --- /dev/null +++ b/drivers/of/unittest-data/overlay_2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_2 - enable using label */ + + fragment@0 { + target = <&unittest2>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_3.dts b/drivers/of/unittest-data/overlay_3.dts new file mode 100644 index 000000000000..158dc44fc20a --- /dev/null +++ b/drivers/of/unittest-data/overlay_3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_3 - disable using label */ + + fragment@0 { + target = <&unittest3>; + __overlay__ { + status = "disabled"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_4.dts b/drivers/of/unittest-data/overlay_4.dts new file mode 100644 index 000000000000..b4a2e6c6b016 --- /dev/null +++ b/drivers/of/unittest-data/overlay_4.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_4 - test insertion of a full node */ + + fragment@0 { + target = <&unittestbus>; + __overlay__ { + + /* suppress DTC warning */ + #address-cells = <1>; + #size-cells = <0>; + + test-unittest4 { + compatible = "unittest"; + status = "okay"; + reg = <4>; + }; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_5.dts b/drivers/of/unittest-data/overlay_5.dts new file mode 100644 index 000000000000..02ad25c1f19c --- /dev/null +++ b/drivers/of/unittest-data/overlay_5.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_5 - test overlay apply revert */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/test-unittest5"; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_6.dts b/drivers/of/unittest-data/overlay_6.dts new file mode 100644 index 000000000000..a14e965f5497 --- /dev/null +++ b/drivers/of/unittest-data/overlay_6.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_6 */ + /* overlays 6, 7 application and removal in sequence */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/test-unittest6"; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_7.dts b/drivers/of/unittest-data/overlay_7.dts new file mode 100644 index 000000000000..4bd7e423209c --- /dev/null +++ b/drivers/of/unittest-data/overlay_7.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_7 */ + /* overlays 6, 7 application and removal in sequence */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/test-unittest7"; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_8.dts b/drivers/of/unittest-data/overlay_8.dts new file mode 100644 index 000000000000..5b21c53945a9 --- /dev/null +++ b/drivers/of/unittest-data/overlay_8.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_8 */ + /* overlays 8, 9, 10, 11 application and removal in bad sequence */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/test-unittest8"; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_9.dts b/drivers/of/unittest-data/overlay_9.dts new file mode 100644 index 000000000000..20ff055a5349 --- /dev/null +++ b/drivers/of/unittest-data/overlay_9.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +/ { + /* overlay_9 */ + /* overlays 8, 9, 10, 11 application and removal in bad sequence */ + + fragment@0 { + target-path = "/testcase-data/overlay-node/test-bus/test-unittest8"; + __overlay__ { + property-foo = "bar"; + }; + }; +}; diff --git a/drivers/of/unittest-data/tests-overlay.dtsi b/drivers/of/unittest-data/tests-overlay.dtsi index 7b8001ab9f3a..fa2fb43bccac 100644 --- a/drivers/of/unittest-data/tests-overlay.dtsi +++ b/drivers/of/unittest-data/tests-overlay.dtsi @@ -113,218 +113,5 @@ }; }; }; - - /* test enable using absolute target path */ - overlay0 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/test-unittest0"; - __overlay__ { - status = "okay"; - }; - }; - }; - - /* test disable using absolute target path */ - overlay1 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/test-unittest1"; - __overlay__ { - status = "disabled"; - }; - }; - }; - - /* test enable using label */ - overlay2 { - fragment@0 { - target = <&unittest2>; - __overlay__ { - status = "okay"; - }; - }; - }; - - /* test disable using label */ - overlay3 { - fragment@0 { - target = <&unittest3>; - __overlay__ { - status = "disabled"; - }; - }; - }; - - /* test insertion of a full node */ - overlay4 { - fragment@0 { - target = <&unittestbus>; - __overlay__ { - - /* suppress DTC warning */ - #address-cells = <1>; - #size-cells = <0>; - - test-unittest4 { - compatible = "unittest"; - status = "okay"; - reg = <4>; - }; - }; - }; - }; - - /* test overlay apply revert */ - overlay5 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/test-unittest5"; - __overlay__ { - status = "okay"; - }; - }; - }; - - /* test overlays application and removal in sequence */ - overlay6 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/test-unittest6"; - __overlay__ { - status = "okay"; - }; - }; - }; - overlay7 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/test-unittest7"; - __overlay__ { - status = "okay"; - }; - }; - }; - - /* test overlays application and removal in bad sequence */ - overlay8 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/test-unittest8"; - __overlay__ { - status = "okay"; - }; - }; - }; - overlay9 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/test-unittest8"; - __overlay__ { - property-foo = "bar"; - }; - }; - }; - - overlay10 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus"; - __overlay__ { - - /* suppress DTC warning */ - #address-cells = <1>; - #size-cells = <0>; - - test-unittest10 { - compatible = "unittest"; - status = "okay"; - reg = <10>; - - #address-cells = <1>; - #size-cells = <0>; - - test-unittest101 { - compatible = "unittest"; - status = "okay"; - reg = <1>; - }; - - }; - }; - }; - }; - - overlay11 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus"; - __overlay__ { - - /* suppress DTC warning */ - #address-cells = <1>; - #size-cells = <0>; - - test-unittest11 { - compatible = "unittest"; - status = "okay"; - reg = <11>; - - #address-cells = <1>; - #size-cells = <0>; - - test-unittest111 { - compatible = "unittest"; - status = "okay"; - reg = <1>; - }; - - }; - }; - }; - }; - - /* test enable using absolute target path (i2c) */ - overlay12 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12"; - __overlay__ { - status = "okay"; - }; - }; - }; - - /* test disable using absolute target path (i2c) */ - overlay13 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13"; - __overlay__ { - status = "disabled"; - }; - }; - }; - - /* test mux overlay */ - overlay15 { - fragment@0 { - target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus"; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - test-unittest15 { - reg = <11>; - compatible = "unittest-i2c-mux"; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - test-mux-dev { - reg = <32>; - compatible = "unittest-i2c-dev"; - status = "okay"; - }; - }; - }; - }; - }; - }; - }; }; diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 7a9abaae874d..a23b54780c7d 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -45,6 +45,8 @@ static struct unittest_results { failed; \ }) +static int __init overlay_data_apply(const char *overlay_name, int *overlay_id); + static void __init of_unittest_find_node_by_name(void) { struct device_node *np; @@ -997,8 +999,7 @@ static int __init unittest_data_add(void) } /* - * This lock normally encloses of_overlay_apply() as well as - * of_resolve_phandles(). + * This lock normally encloses of_resolve_phandles() */ of_overlay_mutex_lock(); @@ -1191,12 +1192,12 @@ static int of_unittest_device_exists(int unittest_nr, enum overlay_type ovtype) return 0; } -static const char *overlay_path(int nr) +static const char *overlay_name_from_nr(int nr) { static char buf[256]; snprintf(buf, sizeof(buf) - 1, - "/testcase-data/overlay%d", nr); + "overlay_%d", nr); buf[sizeof(buf) - 1] = '\0'; return buf; @@ -1263,25 +1264,19 @@ static void of_unittest_destroy_tracked_overlays(void) } while (defers > 0); } -static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr, +static int __init of_unittest_apply_overlay(int overlay_nr, int unittest_nr, int *overlay_id) { struct device_node *np = NULL; + const char *overlay_name; int ret; - np = of_find_node_by_path(overlay_path(overlay_nr)); - if (np == NULL) { - unittest(0, "could not find overlay node @\"%s\"\n", - overlay_path(overlay_nr)); - ret = -EINVAL; - goto out; - } + overlay_name = overlay_name_from_nr(overlay_nr); - *overlay_id = 0; - ret = of_overlay_apply(np, overlay_id); - if (ret < 0) { - unittest(0, "could not create overlay from \"%s\"\n", - overlay_path(overlay_nr)); + ret = overlay_data_apply(overlay_name, overlay_id); + if (!ret) { + unittest(0, "could not apply overlay \"%s\"\n", + overlay_name); goto out; } of_unittest_track_overlay(*overlay_id); @@ -1295,15 +1290,16 @@ out: } /* apply an overlay while checking before and after states */ -static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr, - int before, int after, enum overlay_type ovtype) +static int __init of_unittest_apply_overlay_check(int overlay_nr, + int unittest_nr, int before, int after, + enum overlay_type ovtype) { int ret, ovcs_id; /* unittest device must not be in before state */ if (of_unittest_device_exists(unittest_nr, ovtype) != before) { - unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n", - overlay_path(overlay_nr), + unittest(0, "%s with device @\"%s\" %s\n", + overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype), !before ? "enabled" : "disabled"); return -EINVAL; @@ -1318,8 +1314,8 @@ static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr, /* unittest device must be to set to after state */ if (of_unittest_device_exists(unittest_nr, ovtype) != after) { - unittest(0, "overlay @\"%s\" failed to create @\"%s\" %s\n", - overlay_path(overlay_nr), + unittest(0, "%s failed to create @\"%s\" %s\n", + overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype), !after ? "enabled" : "disabled"); return -EINVAL; @@ -1329,7 +1325,7 @@ static int of_unittest_apply_overlay_check(int overlay_nr, int unittest_nr, } /* apply an overlay and then revert it while checking before, after states */ -static int of_unittest_apply_revert_overlay_check(int overlay_nr, +static int __init of_unittest_apply_revert_overlay_check(int overlay_nr, int unittest_nr, int before, int after, enum overlay_type ovtype) { @@ -1337,8 +1333,8 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr, /* unittest device must be in before state */ if (of_unittest_device_exists(unittest_nr, ovtype) != before) { - unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n", - overlay_path(overlay_nr), + unittest(0, "%s with device @\"%s\" %s\n", + overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype), !before ? "enabled" : "disabled"); return -EINVAL; @@ -1354,8 +1350,8 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr, /* unittest device must be in after state */ if (of_unittest_device_exists(unittest_nr, ovtype) != after) { - unittest(0, "overlay @\"%s\" failed to create @\"%s\" %s\n", - overlay_path(overlay_nr), + unittest(0, "%s failed to create @\"%s\" %s\n", + overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype), !after ? "enabled" : "disabled"); return -EINVAL; @@ -1363,16 +1359,16 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr, ret = of_overlay_remove(&ovcs_id); if (ret != 0) { - unittest(0, "overlay @\"%s\" failed to be destroyed @\"%s\"\n", - overlay_path(overlay_nr), + unittest(0, "%s failed to be destroyed @\"%s\"\n", + overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype)); return ret; } /* unittest device must be again in before state */ if (of_unittest_device_exists(unittest_nr, PDEV_OVERLAY) != before) { - unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n", - overlay_path(overlay_nr), + unittest(0, "%s with device @\"%s\" %s\n", + overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype), !before ? "enabled" : "disabled"); return -EINVAL; @@ -1382,7 +1378,7 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr, } /* test activation of device */ -static void of_unittest_overlay_0(void) +static void __init of_unittest_overlay_0(void) { int ret; @@ -1395,7 +1391,7 @@ static void of_unittest_overlay_0(void) } /* test deactivation of device */ -static void of_unittest_overlay_1(void) +static void __init of_unittest_overlay_1(void) { int ret; @@ -1408,7 +1404,7 @@ static void of_unittest_overlay_1(void) } /* test activation of device */ -static void of_unittest_overlay_2(void) +static void __init of_unittest_overlay_2(void) { int ret; @@ -1421,7 +1417,7 @@ static void of_unittest_overlay_2(void) } /* test deactivation of device */ -static void of_unittest_overlay_3(void) +static void __init of_unittest_overlay_3(void) { int ret; @@ -1434,7 +1430,7 @@ static void of_unittest_overlay_3(void) } /* test activation of a full device node */ -static void of_unittest_overlay_4(void) +static void __init of_unittest_overlay_4(void) { int ret; @@ -1447,7 +1443,7 @@ static void of_unittest_overlay_4(void) } /* test overlay apply/revert sequence */ -static void of_unittest_overlay_5(void) +static void __init of_unittest_overlay_5(void) { int ret; @@ -1460,19 +1456,19 @@ static void of_unittest_overlay_5(void) } /* test overlay application in sequence */ -static void of_unittest_overlay_6(void) +static void __init of_unittest_overlay_6(void) { - struct device_node *np; int ret, i, ov_id[2], ovcs_id; int overlay_nr = 6, unittest_nr = 6; int before = 0, after = 1; + const char *overlay_name; /* unittest device must be in before state */ for (i = 0; i < 2; i++) { if (of_unittest_device_exists(unittest_nr + i, PDEV_OVERLAY) != before) { - unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n", - overlay_path(overlay_nr + i), + unittest(0, "%s with device @\"%s\" %s\n", + overlay_name_from_nr(overlay_nr + i), unittest_path(unittest_nr + i, PDEV_OVERLAY), !before ? "enabled" : "disabled"); @@ -1483,18 +1479,12 @@ static void of_unittest_overlay_6(void) /* apply the overlays */ for (i = 0; i < 2; i++) { - np = of_find_node_by_path(overlay_path(overlay_nr + i)); - if (np == NULL) { - unittest(0, "could not find overlay node @\"%s\"\n", - overlay_path(overlay_nr + i)); - return; - } + overlay_name = overlay_name_from_nr(overlay_nr + i); - ovcs_id = 0; - ret = of_overlay_apply(np, &ovcs_id); - if (ret < 0) { - unittest(0, "could not create overlay from \"%s\"\n", - overlay_path(overlay_nr + i)); + ret = overlay_data_apply(overlay_name, &ovcs_id); + if (!ret) { + unittest(0, "could not apply overlay \"%s\"\n", + overlay_name); return; } ov_id[i] = ovcs_id; @@ -1506,7 +1496,7 @@ static void of_unittest_overlay_6(void) if (of_unittest_device_exists(unittest_nr + i, PDEV_OVERLAY) != after) { unittest(0, "overlay @\"%s\" failed @\"%s\" %s\n", - overlay_path(overlay_nr + i), + overlay_name_from_nr(overlay_nr + i), unittest_path(unittest_nr + i, PDEV_OVERLAY), !after ? "enabled" : "disabled"); @@ -1518,8 +1508,8 @@ static void of_unittest_overlay_6(void) ovcs_id = ov_id[i]; ret = of_overlay_remove(&ovcs_id); if (ret != 0) { - unittest(0, "overlay @\"%s\" failed destroy @\"%s\"\n", - overlay_path(overlay_nr + i), + unittest(0, "%s failed destroy @\"%s\"\n", + overlay_name_from_nr(overlay_nr + i), unittest_path(unittest_nr + i, PDEV_OVERLAY)); return; @@ -1531,8 +1521,8 @@ static void of_unittest_overlay_6(void) /* unittest device must be again in before state */ if (of_unittest_device_exists(unittest_nr + i, PDEV_OVERLAY) != before) { - unittest(0, "overlay @\"%s\" with device @\"%s\" %s\n", - overlay_path(overlay_nr + i), + unittest(0, "%s with device @\"%s\" %s\n", + overlay_name_from_nr(overlay_nr + i), unittest_path(unittest_nr + i, PDEV_OVERLAY), !before ? "enabled" : "disabled"); @@ -1544,29 +1534,23 @@ static void of_unittest_overlay_6(void) } /* test overlay application in sequence */ -static void of_unittest_overlay_8(void) +static void __init of_unittest_overlay_8(void) { - struct device_node *np; int ret, i, ov_id[2], ovcs_id; int overlay_nr = 8, unittest_nr = 8; + const char *overlay_name; /* we don't care about device state in this test */ /* apply the overlays */ for (i = 0; i < 2; i++) { - np = of_find_node_by_path(overlay_path(overlay_nr + i)); - if (np == NULL) { - unittest(0, "could not find overlay node @\"%s\"\n", - overlay_path(overlay_nr + i)); - return; - } + overlay_name = overlay_name_from_nr(overlay_nr + i); - ovcs_id = 0; - ret = of_overlay_apply(np, &ovcs_id); + ret = overlay_data_apply(overlay_name, &ovcs_id); if (ret < 0) { - unittest(0, "could not create overlay from \"%s\"\n", - overlay_path(overlay_nr + i)); + unittest(0, "could not apply overlay \"%s\"\n", + overlay_name); return; } ov_id[i] = ovcs_id; @@ -1577,8 +1561,8 @@ static void of_unittest_overlay_8(void) ovcs_id = ov_id[0]; ret = of_overlay_remove(&ovcs_id); if (ret == 0) { - unittest(0, "overlay @\"%s\" was destroyed @\"%s\"\n", - overlay_path(overlay_nr + 0), + unittest(0, "%s was destroyed @\"%s\"\n", + overlay_name_from_nr(overlay_nr + 0), unittest_path(unittest_nr, PDEV_OVERLAY)); return; @@ -1589,8 +1573,8 @@ static void of_unittest_overlay_8(void) ovcs_id = ov_id[i]; ret = of_overlay_remove(&ovcs_id); if (ret != 0) { - unittest(0, "overlay @\"%s\" not destroyed @\"%s\"\n", - overlay_path(overlay_nr + i), + unittest(0, "%s not destroyed @\"%s\"\n", + overlay_name_from_nr(overlay_nr + i), unittest_path(unittest_nr, PDEV_OVERLAY)); return; @@ -1602,7 +1586,7 @@ static void of_unittest_overlay_8(void) } /* test insertion of a bus with parent devices */ -static void of_unittest_overlay_10(void) +static void __init of_unittest_overlay_10(void) { int ret; char *child_path; @@ -1625,7 +1609,7 @@ static void of_unittest_overlay_10(void) } /* test insertion of a bus with parent devices (and revert) */ -static void of_unittest_overlay_11(void) +static void __init of_unittest_overlay_11(void) { int ret; @@ -1891,7 +1875,7 @@ static void of_unittest_overlay_i2c_cleanup(void) i2c_del_driver(&unittest_i2c_dev_driver); } -static void of_unittest_overlay_i2c_12(void) +static void __init of_unittest_overlay_i2c_12(void) { int ret; @@ -1904,7 +1888,7 @@ static void of_unittest_overlay_i2c_12(void) } /* test deactivation of device */ -static void of_unittest_overlay_i2c_13(void) +static void __init of_unittest_overlay_i2c_13(void) { int ret; @@ -1921,7 +1905,7 @@ static void of_unittest_overlay_i2c_14(void) { } -static void of_unittest_overlay_i2c_15(void) +static void __init of_unittest_overlay_i2c_15(void) { int ret; @@ -2023,23 +2007,38 @@ static inline void __init of_unittest_overlay(void) { } extern uint8_t __dtb_##name##_begin[]; \ extern uint8_t __dtb_##name##_end[] -#define OVERLAY_INFO(name, expected) \ -{ .dtb_begin = __dtb_##name##_begin, \ - .dtb_end = __dtb_##name##_end, \ - .expected_result = expected, \ +#define OVERLAY_INFO(overlay_name, expected) \ +{ .dtb_begin = __dtb_##overlay_name##_begin, \ + .dtb_end = __dtb_##overlay_name##_end, \ + .expected_result = expected, \ + .name = #overlay_name, \ } struct overlay_info { - uint8_t *dtb_begin; - uint8_t *dtb_end; - void *data; - struct device_node *np_overlay; - int expected_result; - int overlay_id; + uint8_t *dtb_begin; + uint8_t *dtb_end; + int expected_result; + int overlay_id; + char *name; }; OVERLAY_INFO_EXTERN(overlay_base); OVERLAY_INFO_EXTERN(overlay); +OVERLAY_INFO_EXTERN(overlay_0); +OVERLAY_INFO_EXTERN(overlay_1); +OVERLAY_INFO_EXTERN(overlay_2); +OVERLAY_INFO_EXTERN(overlay_3); +OVERLAY_INFO_EXTERN(overlay_4); +OVERLAY_INFO_EXTERN(overlay_5); +OVERLAY_INFO_EXTERN(overlay_6); +OVERLAY_INFO_EXTERN(overlay_7); +OVERLAY_INFO_EXTERN(overlay_8); +OVERLAY_INFO_EXTERN(overlay_9); +OVERLAY_INFO_EXTERN(overlay_10); +OVERLAY_INFO_EXTERN(overlay_11); +OVERLAY_INFO_EXTERN(overlay_12); +OVERLAY_INFO_EXTERN(overlay_13); +OVERLAY_INFO_EXTERN(overlay_15); OVERLAY_INFO_EXTERN(overlay_bad_phandle); OVERLAY_INFO_EXTERN(overlay_bad_symbol); @@ -2047,6 +2046,21 @@ OVERLAY_INFO_EXTERN(overlay_bad_symbol); static struct overlay_info overlays[] = { OVERLAY_INFO(overlay_base, -9999), OVERLAY_INFO(overlay, 0), + OVERLAY_INFO(overlay_0, 0), + OVERLAY_INFO(overlay_1, 0), + OVERLAY_INFO(overlay_2, 0), + OVERLAY_INFO(overlay_3, 0), + OVERLAY_INFO(overlay_4, 0), + OVERLAY_INFO(overlay_5, 0), + OVERLAY_INFO(overlay_6, 0), + OVERLAY_INFO(overlay_7, 0), + OVERLAY_INFO(overlay_8, 0), + OVERLAY_INFO(overlay_9, 0), + OVERLAY_INFO(overlay_10, 0), + OVERLAY_INFO(overlay_11, 0), + OVERLAY_INFO(overlay_12, 0), + OVERLAY_INFO(overlay_13, 0), + OVERLAY_INFO(overlay_15, 0), OVERLAY_INFO(overlay_bad_phandle, -EINVAL), OVERLAY_INFO(overlay_bad_symbol, -EINVAL), {} @@ -2077,6 +2091,7 @@ void __init unittest_unflatten_overlay_base(void) { struct overlay_info *info; u32 data_size; + void *new_fdt; u32 size; info = &overlays[0]; @@ -2098,17 +2113,16 @@ void __init unittest_unflatten_overlay_base(void) return; } - info->data = dt_alloc_memory(size, roundup_pow_of_two(FDT_V17_SIZE)); - if (!info->data) { + new_fdt = dt_alloc_memory(size, roundup_pow_of_two(FDT_V17_SIZE)); + if (!new_fdt) { pr_err("alloc for dtb 'overlay_base' failed"); return; } - memcpy(info->data, info->dtb_begin, size); + memcpy(new_fdt, info->dtb_begin, size); - __unflatten_device_tree(info->data, NULL, &info->np_overlay, + __unflatten_device_tree(new_fdt, NULL, &overlay_base_root, dt_alloc_memory, true); - overlay_base_root = info->np_overlay; } /* @@ -2122,73 +2136,44 @@ void __init unittest_unflatten_overlay_base(void) * * Return 0 on unexpected error. */ -static int __init overlay_data_add(int onum) +static int __init overlay_data_apply(const char *overlay_name, int *overlay_id) { struct overlay_info *info; + int found = 0; int k; int ret; u32 size; - u32 size_from_header; - for (k = 0, info = overlays; info; info++, k++) { - if (k == onum) + for (k = 0, info = overlays; info && info->name; info++, k++) { + if (!strcmp(overlay_name, info->name)) { + found = 1; break; + } } - if (onum > k) + if (!found) { + pr_err("no overlay data for %s\n", overlay_name); return 0; + } size = info->dtb_end - info->dtb_begin; if (!size) { - pr_err("no overlay to attach, %d\n", onum); + pr_err("no overlay data for %s\n", overlay_name); ret = 0; } - size_from_header = fdt_totalsize(info->dtb_begin); - if (size_from_header != size) { - pr_err("overlay header totalsize != actual size, %d", onum); - return 0; - } - - /* - * Must create permanent copy of FDT because of_fdt_unflatten_tree() - * will create pointers to the passed in FDT in the EDT. - */ - info->data = kmemdup(info->dtb_begin, size, GFP_KERNEL); - if (!info->data) { - pr_err("unable to allocate memory for data, %d\n", onum); - return 0; - } - - of_fdt_unflatten_tree(info->data, NULL, &info->np_overlay); - if (!info->np_overlay) { - pr_err("unable to unflatten overlay, %d\n", onum); - ret = 0; - goto out_free_data; - } - - info->overlay_id = 0; - ret = of_overlay_apply(info->np_overlay, &info->overlay_id); - if (ret < 0) { - pr_err("of_overlay_apply() (ret=%d), %d\n", ret, onum); - goto out_free_np_overlay; - } - - pr_debug("__dtb_overlay_begin applied, overlay id %d\n", ret); - - goto out; - -out_free_np_overlay: - /* - * info->np_overlay is the unflattened device tree - * It has not been spliced into the live tree. - */ - - /* todo: function to free unflattened device tree */ + ret = of_overlay_fdt_apply(info->dtb_begin, size, &info->overlay_id); + if (overlay_id) + *overlay_id = info->overlay_id; + if (ret < 0) + goto out; -out_free_data: - kfree(info->data); + pr_debug("%s applied\n", overlay_name); out: + if (ret != info->expected_result) + pr_err("of_overlay_fdt_apply() expected %d, ret=%d, %s\n", + info->expected_result, ret, overlay_name); + return (ret == info->expected_result); } @@ -2290,18 +2275,29 @@ static __init void of_unittest_overlay_high_level(void) __of_attach_node_sysfs(np); if (of_symbols) { + struct property *new_prop; for_each_property_of_node(overlay_base_symbols, prop) { - ret = __of_add_property(of_symbols, prop); + + new_prop = __of_prop_dup(prop, GFP_KERNEL); + if (!new_prop) { + unittest(0, "__of_prop_dup() of '%s' from overlay_base node __symbols__", + prop->name); + goto err_unlock; + } + ret = __of_add_property(of_symbols, new_prop); if (ret) { - unittest(0, - "duplicate property '%s' in overlay_base node __symbols__", + if (!strcmp(new_prop->name, "name")) { + /* auto-generated by unflatten */ + ret = 0; + continue; + } + unittest(0, "duplicate property '%s' in overlay_base node __symbols__", prop->name); goto err_unlock; } - ret = __of_add_property_sysfs(of_symbols, prop); + ret = __of_add_property_sysfs(of_symbols, new_prop); if (ret) { - unittest(0, - "unable to add property '%s' in overlay_base node __symbols__ to sysfs", + unittest(0, "unable to add property '%s' in overlay_base node __symbols__ to sysfs", prop->name); goto err_unlock; } @@ -2313,13 +2309,13 @@ static __init void of_unittest_overlay_high_level(void) /* now do the normal overlay usage test */ - unittest(overlay_data_add(1), + unittest(overlay_data_apply("overlay", NULL), "Adding overlay 'overlay' failed\n"); - unittest(overlay_data_add(2), + unittest(overlay_data_apply("overlay_bad_phandle", NULL), "Adding overlay 'overlay_bad_phandle' failed\n"); - unittest(overlay_data_add(3), + unittest(overlay_data_apply("overlay_bad_symbol", NULL), "Adding overlay 'overlay_bad_symbol' failed\n"); return; diff --git a/include/linux/of.h b/include/linux/of.h index da1ee95241c1..ebf22dd0860c 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -1359,8 +1359,8 @@ struct of_overlay_notify_data { #ifdef CONFIG_OF_OVERLAY -/* ID based overlays; the API for external users */ -int of_overlay_apply(struct device_node *tree, int *ovcs_id); +int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size, + int *ovcs_id); int of_overlay_remove(int *ovcs_id); int of_overlay_remove_all(void); @@ -1369,7 +1369,7 @@ int of_overlay_notifier_unregister(struct notifier_block *nb); #else -static inline int of_overlay_apply(struct device_node *tree, int *ovcs_id) +static inline int of_overlay_fdt_apply(void *overlay_fdt, int *ovcs_id) { return -ENOTSUPP; } -- cgit v1.2.3 From 325ea10c0809406ce23f038602abbc454f3f761d Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Sat, 3 Mar 2018 12:20:47 +0100 Subject: sched/headers: Simplify and clean up header usage in the scheduler Do the following cleanups and simplifications: - sched/sched.h already includes , so no need to include it in sched/core.c again. - order the headers alphabetically - add all headers to kernel/sched/sched.h - remove all unnecessary includes from the .c files that are already included in kernel/sched/sched.h. Finally, make all scheduler .c files use a single common header: #include "sched.h" ... which now contains a union of the relied upon headers. This makes the various .c files easier to read and easier to handle. Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/sched/deadline.h | 6 --- kernel/sched/autogroup.c | 9 ++--- kernel/sched/autogroup.h | 4 -- kernel/sched/clock.c | 14 +------ kernel/sched/completion.c | 5 +-- kernel/sched/core.c | 40 +++++++------------- kernel/sched/cpuacct.c | 13 +------ kernel/sched/cpudeadline.c | 5 +-- kernel/sched/cpudeadline.h | 2 - kernel/sched/cpufreq.c | 1 - kernel/sched/cpufreq_schedutil.c | 8 +--- kernel/sched/cpupri.c | 6 +-- kernel/sched/cpupri.h | 1 - kernel/sched/cputime.c | 10 ++--- kernel/sched/deadline.c | 3 -- kernel/sched/debug.c | 11 +----- kernel/sched/fair.c | 16 +------- kernel/sched/idle.c | 15 +------- kernel/sched/idle_task.c | 5 +-- kernel/sched/isolation.c | 7 ---- kernel/sched/loadavg.c | 4 -- kernel/sched/membarrier.c | 9 +---- kernel/sched/rt.c | 4 -- kernel/sched/sched.h | 81 ++++++++++++++++++++++++++-------------- kernel/sched/stats.c | 13 +++---- kernel/sched/swait.c | 3 +- kernel/sched/topology.c | 4 -- kernel/sched/wait.c | 9 +---- kernel/sched/wait_bit.c | 5 +-- 29 files changed, 94 insertions(+), 219 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched/deadline.h b/include/linux/sched/deadline.h index a5bc8728ead7..0cb034331cbb 100644 --- a/include/linux/sched/deadline.h +++ b/include/linux/sched/deadline.h @@ -1,8 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _LINUX_SCHED_DEADLINE_H -#define _LINUX_SCHED_DEADLINE_H - -#include /* * SCHED_DEADLINE tasks has negative priorities, reflecting @@ -28,5 +24,3 @@ static inline bool dl_time_before(u64 a, u64 b) { return (s64)(a - b) < 0; } - -#endif /* _LINUX_SCHED_DEADLINE_H */ diff --git a/kernel/sched/autogroup.c b/kernel/sched/autogroup.c index ff1b7b647b86..6be6c575b6cd 100644 --- a/kernel/sched/autogroup.c +++ b/kernel/sched/autogroup.c @@ -1,10 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include - +/* + * Auto-group scheduling implementation: + */ #include "sched.h" unsigned int __read_mostly sysctl_sched_autogroup_enabled = 1; diff --git a/kernel/sched/autogroup.h b/kernel/sched/autogroup.h index 49e6ec9559cf..b96419974a1f 100644 --- a/kernel/sched/autogroup.h +++ b/kernel/sched/autogroup.h @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifdef CONFIG_SCHED_AUTOGROUP -#include -#include -#include - struct autogroup { /* * Reference doesn't mean how many threads attach to this diff --git a/kernel/sched/clock.c b/kernel/sched/clock.c index 7da6bec8a2ff..10c83e73837a 100644 --- a/kernel/sched/clock.c +++ b/kernel/sched/clock.c @@ -52,19 +52,7 @@ * that is otherwise invisible (TSC gets stopped). * */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "sched.h" /* * Scheduler clock - returns current time in nanosec units. diff --git a/kernel/sched/completion.c b/kernel/sched/completion.c index 0926aef10dad..5d2d56b0817a 100644 --- a/kernel/sched/completion.c +++ b/kernel/sched/completion.c @@ -11,10 +11,7 @@ * typically be used for exclusion which gives rise to priority inversion. * Waiting for completion is a typically sync point, but not an exclusion point. */ - -#include -#include -#include +#include "sched.h" /** * complete: - signals a single thread waiting on this completion diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 9427b59551c1..e1e334ba8ff9 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5,37 +5,11 @@ * * Copyright (C) 1991-2002 Linus Torvalds */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "sched.h" #include #include -#ifdef CONFIG_PARAVIRT -#include -#endif -#include "sched.h" #include "../workqueue_internal.h" #include "../smpboot.h" @@ -2629,6 +2603,18 @@ static inline void finish_lock_switch(struct rq *rq) raw_spin_unlock_irq(&rq->lock); } +/* + * NOP if the arch has not defined these: + */ + +#ifndef prepare_arch_switch +# define prepare_arch_switch(next) do { } while (0) +#endif + +#ifndef finish_arch_post_lock_switch +# define finish_arch_post_lock_switch() do { } while (0) +#endif + /** * prepare_task_switch - prepare to switch tasks * @rq: the runqueue preparing to switch diff --git a/kernel/sched/cpuacct.c b/kernel/sched/cpuacct.c index 1abd325e733a..9fbb10383434 100644 --- a/kernel/sched/cpuacct.c +++ b/kernel/sched/cpuacct.c @@ -1,22 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "sched.h" - /* * CPU accounting code for task groups. * * Based on the work by Paul Menage (menage@google.com) and Balbir Singh * (balbir@in.ibm.com). */ +#include "sched.h" /* Time spent by the tasks of the CPU accounting group executing in ... */ enum cpuacct_stat_index { diff --git a/kernel/sched/cpudeadline.c b/kernel/sched/cpudeadline.c index cb172b61d191..50316455ea66 100644 --- a/kernel/sched/cpudeadline.c +++ b/kernel/sched/cpudeadline.c @@ -10,10 +10,7 @@ * as published by the Free Software Foundation; version 2 * of the License. */ -#include -#include -#include -#include "cpudeadline.h" +#include "sched.h" static inline int parent(int i) { diff --git a/kernel/sched/cpudeadline.h b/kernel/sched/cpudeadline.h index c26e7a0e5a66..0adeda93b5fb 100644 --- a/kernel/sched/cpudeadline.h +++ b/kernel/sched/cpudeadline.h @@ -1,6 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#include -#include #define IDX_INVALID -1 diff --git a/kernel/sched/cpufreq.c b/kernel/sched/cpufreq.c index dbc51442ecbc..5e54cbcae673 100644 --- a/kernel/sched/cpufreq.c +++ b/kernel/sched/cpufreq.c @@ -8,7 +8,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - #include "sched.h" DEFINE_PER_CPU(struct update_util_data *, cpufreq_update_util_data); diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c index 0dad8160e00f..feb5f89020f2 100644 --- a/kernel/sched/cpufreq_schedutil.c +++ b/kernel/sched/cpufreq_schedutil.c @@ -11,14 +11,10 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#include -#include -#include -#include -#include - #include "sched.h" +#include + struct sugov_tunables { struct gov_attr_set attr_set; unsigned int rate_limit_us; diff --git a/kernel/sched/cpupri.c b/kernel/sched/cpupri.c index f43e14ccb67d..daaadf939ccb 100644 --- a/kernel/sched/cpupri.c +++ b/kernel/sched/cpupri.c @@ -26,11 +26,7 @@ * as published by the Free Software Foundation; version 2 * of the License. */ -#include -#include -#include -#include -#include "cpupri.h" +#include "sched.h" /* Convert between a 140 based task->prio, and our 102 based cpupri */ static int convert_prio(int prio) diff --git a/kernel/sched/cpupri.h b/kernel/sched/cpupri.h index 141a06c914c6..7dc20a3232e7 100644 --- a/kernel/sched/cpupri.h +++ b/kernel/sched/cpupri.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#include #define CPUPRI_NR_PRIORITIES (MAX_RT_PRIO + 2) diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c index d3b450b57ade..0796f938c4f0 100644 --- a/kernel/sched/cputime.c +++ b/kernel/sched/cputime.c @@ -1,10 +1,6 @@ -#include -#include -#include -#include -#include -#include -#include +/* + * Simple CPU accounting cgroup controller + */ #include "sched.h" #ifdef CONFIG_IRQ_TIME_ACCOUNTING diff --git a/kernel/sched/deadline.c b/kernel/sched/deadline.c index 58f8b7b37983..af491f537636 100644 --- a/kernel/sched/deadline.c +++ b/kernel/sched/deadline.c @@ -17,9 +17,6 @@ */ #include "sched.h" -#include -#include - struct dl_bandwidth def_dl_bandwidth; static inline struct task_struct *dl_task_of(struct sched_dl_entity *dl_se) diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c index 7c82a9b88510..644d9a464380 100644 --- a/kernel/sched/debug.c +++ b/kernel/sched/debug.c @@ -1,7 +1,7 @@ /* * kernel/sched/debug.c * - * Print the CFS rbtree + * Print the CFS rbtree and other debugging details * * Copyright(C) 2007, Red Hat, Inc., Ingo Molnar * @@ -9,15 +9,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include -#include -#include -#include -#include -#include -#include -#include - #include "sched.h" static DEFINE_SPINLOCK(sched_debug_lock); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 1f877de96c9b..f5591071ae98 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -20,24 +20,10 @@ * Adaptive scheduling granularity, math enhancements by Peter Zijlstra * Copyright (C) 2007 Red Hat, Inc., Peter Zijlstra */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "sched.h" #include -#include "sched.h" - /* * Targeted preemption latency for CPU-bound tasks: * diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c index 343d25f85477..2760e0357271 100644 --- a/kernel/sched/idle.c +++ b/kernel/sched/idle.c @@ -1,23 +1,10 @@ /* * Generic entry points for the idle threads */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include +#include "sched.h" #include -#include "sched.h" - /* Linker adds these: start and end of __cpuidle functions */ extern char __cpuidle_text_start[], __cpuidle_text_end[]; diff --git a/kernel/sched/idle_task.c b/kernel/sched/idle_task.c index ec73680922f8..488222ac4651 100644 --- a/kernel/sched/idle_task.c +++ b/kernel/sched/idle_task.c @@ -1,12 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 -#include "sched.h" - /* * idle-task scheduling class. * - * (NOTE: these are not related to SCHED_IDLE tasks which are + * (NOTE: these are not related to SCHED_IDLE batch scheduling tasks which are * handled in sched/fair.c) */ +#include "sched.h" #ifdef CONFIG_SMP static int diff --git a/kernel/sched/isolation.c b/kernel/sched/isolation.c index aad5f48a07c6..e6802181900f 100644 --- a/kernel/sched/isolation.c +++ b/kernel/sched/isolation.c @@ -6,13 +6,6 @@ * Copyright (C) 2017-2018 SUSE, Frederic Weisbecker * */ -#include -#include -#include -#include -#include -#include - #include "sched.h" DEFINE_STATIC_KEY_FALSE(housekeeping_overriden); diff --git a/kernel/sched/loadavg.c b/kernel/sched/loadavg.c index a398e7e28a8a..a171c1258109 100644 --- a/kernel/sched/loadavg.c +++ b/kernel/sched/loadavg.c @@ -6,10 +6,6 @@ * figure. Its a silly number but people think its important. We go through * great pains to make it work on big machines and tickless kernels. */ - -#include -#include - #include "sched.h" /* diff --git a/kernel/sched/membarrier.c b/kernel/sched/membarrier.c index 2c6ae2413fa2..76e0eaf4654e 100644 --- a/kernel/sched/membarrier.c +++ b/kernel/sched/membarrier.c @@ -13,14 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include -#include -#include -#include -#include - -#include "sched.h" /* for cpu_rq(). */ +#include "sched.h" /* * Bitmask made from a "or" of all commands within enum membarrier_cmd, diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c index e40498872111..a3d438fec46c 100644 --- a/kernel/sched/rt.c +++ b/kernel/sched/rt.c @@ -3,12 +3,8 @@ * Real-Time Scheduling Class (mapped to the SCHED_FIFO and SCHED_RR * policies) */ - #include "sched.h" -#include -#include - int sched_rr_timeslice = RR_TIMESLICE; int sysctl_sched_rr_timeslice = (MSEC_PER_SEC / HZ) * RR_TIMESLICE; diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index bd1461ae06e4..23ba4dd76ac4 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -3,39 +3,71 @@ * Scheduler internal types and methods: */ #include + #include -#include -#include -#include -#include #include -#include -#include -#include -#include +#include #include -#include -#include +#include +#include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include #include -#include -#include +#include +#include +#include +#include + +#include -#include -#include #include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include -#include -#include -#include -#include +#include +#include +#include +#include +#include + +#include #ifdef CONFIG_PARAVIRT -#include +# include #endif #include "cpupri.h" @@ -1357,13 +1389,6 @@ static inline int task_on_rq_migrating(struct task_struct *p) return p->on_rq == TASK_ON_RQ_MIGRATING; } -#ifndef prepare_arch_switch -# define prepare_arch_switch(next) do { } while (0) -#endif -#ifndef finish_arch_post_lock_switch -# define finish_arch_post_lock_switch() do { } while (0) -#endif - /* * wake flags */ diff --git a/kernel/sched/stats.c b/kernel/sched/stats.c index 968c1fe3099a..ab112cbfd7c8 100644 --- a/kernel/sched/stats.c +++ b/kernel/sched/stats.c @@ -1,14 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include -#include - +/* + * /proc/schedstat implementation + */ #include "sched.h" /* - * bump this up when changing the output format or the meaning of an existing + * Current schedstat API version. + * + * Bump this up when changing the output format or the meaning of an existing * format, so that tools can adapt (or abort) */ #define SCHEDSTAT_VERSION 15 diff --git a/kernel/sched/swait.c b/kernel/sched/swait.c index b88ab4e0207f..b6fb2c3b3ff7 100644 --- a/kernel/sched/swait.c +++ b/kernel/sched/swait.c @@ -2,8 +2,7 @@ /* * (simple wait queues ) implementation: */ -#include -#include +#include "sched.h" void __init_swait_queue_head(struct swait_queue_head *q, const char *name, struct lock_class_key *key) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 219eee70e457..64cc564f5255 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -2,10 +2,6 @@ /* * Scheduler topology setup/handling methods */ -#include -#include -#include - #include "sched.h" DEFINE_MUTEX(sched_domains_mutex); diff --git a/kernel/sched/wait.c b/kernel/sched/wait.c index 7b2a142ae629..928be527477e 100644 --- a/kernel/sched/wait.c +++ b/kernel/sched/wait.c @@ -3,14 +3,7 @@ * * (C) 2004 Nadia Yvette Chambers, Oracle */ -#include -#include -#include -#include -#include -#include -#include -#include +#include "sched.h" void __init_waitqueue_head(struct wait_queue_head *wq_head, const char *name, struct lock_class_key *key) { diff --git a/kernel/sched/wait_bit.c b/kernel/sched/wait_bit.c index 5293c59163a6..4239c78f5cd3 100644 --- a/kernel/sched/wait_bit.c +++ b/kernel/sched/wait_bit.c @@ -1,10 +1,7 @@ /* * The implementation of the wait_bit*() and related waiting APIs: */ -#include -#include -#include -#include +#include "sched.h" #define WAIT_TABLE_BITS 8 #define WAIT_TABLE_SIZE (1 << WAIT_TABLE_BITS) -- cgit v1.2.3 From 779b7931b27bfa80bac46d0115d229259aef580b Mon Sep 17 00:00:00 2001 From: Daniel Axtens Date: Thu, 1 Mar 2018 17:13:37 +1100 Subject: net: rename skb_gso_validate_mtu -> skb_gso_validate_network_len If you take a GSO skb, and split it into packets, will the network length (L3 headers + L4 headers + payload) of those packets be small enough to fit within a given MTU? skb_gso_validate_mtu gives you the answer to that question. However, we recently added to add a way to validate the MAC length of a split GSO skb (L2+L3+L4+payload), and the names get confusing, so rename skb_gso_validate_mtu to skb_gso_validate_network_len Signed-off-by: Daniel Axtens Reviewed-by: Marcelo Ricardo Leitner Signed-off-by: David S. Miller --- include/linux/skbuff.h | 2 +- net/core/skbuff.c | 11 ++++++----- net/ipv4/ip_forward.c | 2 +- net/ipv4/ip_output.c | 2 +- net/ipv4/netfilter/nf_flow_table_ipv4.c | 2 +- net/ipv6/ip6_output.c | 2 +- net/ipv6/netfilter/nf_flow_table_ipv6.c | 2 +- net/mpls/af_mpls.c | 2 +- net/xfrm/xfrm_device.c | 2 +- 9 files changed, 14 insertions(+), 13 deletions(-) (limited to 'include/linux') diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index c1e66bdcf583..a057dd1a75c7 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -3286,7 +3286,7 @@ void skb_split(struct sk_buff *skb, struct sk_buff *skb1, const u32 len); int skb_shift(struct sk_buff *tgt, struct sk_buff *skb, int shiftlen); void skb_scrub_packet(struct sk_buff *skb, bool xnet); unsigned int skb_gso_transport_seglen(const struct sk_buff *skb); -bool skb_gso_validate_mtu(const struct sk_buff *skb, unsigned int mtu); +bool skb_gso_validate_network_len(const struct sk_buff *skb, unsigned int mtu); bool skb_gso_validate_mac_len(const struct sk_buff *skb, unsigned int len); struct sk_buff *skb_segment(struct sk_buff *skb, netdev_features_t features); struct sk_buff *skb_vlan_untag(struct sk_buff *skb); diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 09bd89c90a71..b63767008824 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -4955,19 +4955,20 @@ static inline bool skb_gso_size_check(const struct sk_buff *skb, } /** - * skb_gso_validate_mtu - Return in case such skb fits a given MTU + * skb_gso_validate_network_len - Will a split GSO skb fit into a given MTU? * * @skb: GSO skb * @mtu: MTU to validate against * - * skb_gso_validate_mtu validates if a given skb will fit a wanted MTU - * once split. + * skb_gso_validate_network_len validates if a given skb will fit a + * wanted MTU once split. It considers L3 headers, L4 headers, and the + * payload. */ -bool skb_gso_validate_mtu(const struct sk_buff *skb, unsigned int mtu) +bool skb_gso_validate_network_len(const struct sk_buff *skb, unsigned int mtu) { return skb_gso_size_check(skb, skb_gso_network_seglen(skb), mtu); } -EXPORT_SYMBOL_GPL(skb_gso_validate_mtu); +EXPORT_SYMBOL_GPL(skb_gso_validate_network_len); /** * skb_gso_validate_mac_len - Will a split GSO skb fit in a given length? diff --git a/net/ipv4/ip_forward.c b/net/ipv4/ip_forward.c index 2dd21c3281a1..b54b948b0596 100644 --- a/net/ipv4/ip_forward.c +++ b/net/ipv4/ip_forward.c @@ -55,7 +55,7 @@ static bool ip_exceeds_mtu(const struct sk_buff *skb, unsigned int mtu) if (skb->ignore_df) return false; - if (skb_is_gso(skb) && skb_gso_validate_mtu(skb, mtu)) + if (skb_is_gso(skb) && skb_gso_validate_network_len(skb, mtu)) return false; return true; diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c index e8e675be60ec..66340ab750e6 100644 --- a/net/ipv4/ip_output.c +++ b/net/ipv4/ip_output.c @@ -248,7 +248,7 @@ static int ip_finish_output_gso(struct net *net, struct sock *sk, /* common case: seglen is <= mtu */ - if (skb_gso_validate_mtu(skb, mtu)) + if (skb_gso_validate_network_len(skb, mtu)) return ip_finish_output2(net, sk, skb); /* Slowpath - GSO segment length exceeds the egress MTU. diff --git a/net/ipv4/netfilter/nf_flow_table_ipv4.c b/net/ipv4/netfilter/nf_flow_table_ipv4.c index 282b9cc4fe82..0cd46bffa469 100644 --- a/net/ipv4/netfilter/nf_flow_table_ipv4.c +++ b/net/ipv4/netfilter/nf_flow_table_ipv4.c @@ -186,7 +186,7 @@ static bool __nf_flow_exceeds_mtu(const struct sk_buff *skb, unsigned int mtu) if ((ip_hdr(skb)->frag_off & htons(IP_DF)) == 0) return false; - if (skb_is_gso(skb) && skb_gso_validate_mtu(skb, mtu)) + if (skb_is_gso(skb) && skb_gso_validate_network_len(skb, mtu)) return false; return true; diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index 997c7f19ad62..a8a919520090 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -412,7 +412,7 @@ static bool ip6_pkt_too_big(const struct sk_buff *skb, unsigned int mtu) if (skb->ignore_df) return false; - if (skb_is_gso(skb) && skb_gso_validate_mtu(skb, mtu)) + if (skb_is_gso(skb) && skb_gso_validate_network_len(skb, mtu)) return false; return true; diff --git a/net/ipv6/netfilter/nf_flow_table_ipv6.c b/net/ipv6/netfilter/nf_flow_table_ipv6.c index d346705d6ee6..207cb35569b1 100644 --- a/net/ipv6/netfilter/nf_flow_table_ipv6.c +++ b/net/ipv6/netfilter/nf_flow_table_ipv6.c @@ -178,7 +178,7 @@ static bool __nf_flow_exceeds_mtu(const struct sk_buff *skb, unsigned int mtu) if (skb->len <= mtu) return false; - if (skb_is_gso(skb) && skb_gso_validate_mtu(skb, mtu)) + if (skb_is_gso(skb) && skb_gso_validate_network_len(skb, mtu)) return false; return true; diff --git a/net/mpls/af_mpls.c b/net/mpls/af_mpls.c index e545a3c9365f..7a4de6d618b1 100644 --- a/net/mpls/af_mpls.c +++ b/net/mpls/af_mpls.c @@ -122,7 +122,7 @@ bool mpls_pkt_too_big(const struct sk_buff *skb, unsigned int mtu) if (skb->len <= mtu) return false; - if (skb_is_gso(skb) && skb_gso_validate_mtu(skb, mtu)) + if (skb_is_gso(skb) && skb_gso_validate_network_len(skb, mtu)) return false; return true; diff --git a/net/xfrm/xfrm_device.c b/net/xfrm/xfrm_device.c index 8e70291e586a..e87d6c4dd5b6 100644 --- a/net/xfrm/xfrm_device.c +++ b/net/xfrm/xfrm_device.c @@ -217,7 +217,7 @@ bool xfrm_dev_offload_ok(struct sk_buff *skb, struct xfrm_state *x) if (skb->len <= mtu) goto ok; - if (skb_is_gso(skb) && skb_gso_validate_mtu(skb, mtu)) + if (skb_is_gso(skb) && skb_gso_validate_network_len(skb, mtu)) goto ok; } -- cgit v1.2.3 From a4a77718ee4053a44aa40fe67247c1afb5ce2f1e Mon Sep 17 00:00:00 2001 From: Daniel Axtens Date: Thu, 1 Mar 2018 17:13:40 +1100 Subject: net: make skb_gso_*_seglen functions private They're very hard to use properly as they do not consider the GSO_BY_FRAGS case. Code should use skb_gso_validate_network_len and skb_gso_validate_mac_len as they do consider this case. Make the seglen functions static, which stops people using them outside of skbuff.c Signed-off-by: Daniel Axtens Reviewed-by: Marcelo Ricardo Leitner Signed-off-by: David S. Miller --- include/linux/skbuff.h | 33 --------------------------------- net/core/skbuff.c | 37 +++++++++++++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 35 deletions(-) (limited to 'include/linux') diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index a057dd1a75c7..ddf77cf4ff2d 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -3285,7 +3285,6 @@ int skb_zerocopy(struct sk_buff *to, struct sk_buff *from, void skb_split(struct sk_buff *skb, struct sk_buff *skb1, const u32 len); int skb_shift(struct sk_buff *tgt, struct sk_buff *skb, int shiftlen); void skb_scrub_packet(struct sk_buff *skb, bool xnet); -unsigned int skb_gso_transport_seglen(const struct sk_buff *skb); bool skb_gso_validate_network_len(const struct sk_buff *skb, unsigned int mtu); bool skb_gso_validate_mac_len(const struct sk_buff *skb, unsigned int len); struct sk_buff *skb_segment(struct sk_buff *skb, netdev_features_t features); @@ -4104,38 +4103,6 @@ static inline bool skb_head_is_locked(const struct sk_buff *skb) return !skb->head_frag || skb_cloned(skb); } -/** - * skb_gso_network_seglen - Return length of individual segments of a gso packet - * - * @skb: GSO skb - * - * skb_gso_network_seglen is used to determine the real size of the - * individual segments, including Layer3 (IP, IPv6) and L4 headers (TCP/UDP). - * - * The MAC/L2 header is not accounted for. - */ -static inline unsigned int skb_gso_network_seglen(const struct sk_buff *skb) -{ - unsigned int hdr_len = skb_transport_header(skb) - - skb_network_header(skb); - return hdr_len + skb_gso_transport_seglen(skb); -} - -/** - * skb_gso_mac_seglen - Return length of individual segments of a gso packet - * - * @skb: GSO skb - * - * skb_gso_mac_seglen is used to determine the real size of the - * individual segments, including MAC/L2, Layer3 (IP, IPv6) and L4 - * headers (TCP/UDP). - */ -static inline unsigned int skb_gso_mac_seglen(const struct sk_buff *skb) -{ - unsigned int hdr_len = skb_transport_header(skb) - skb_mac_header(skb); - return hdr_len + skb_gso_transport_seglen(skb); -} - /* Local Checksum Offload. * Compute outer checksum based on the assumption that the * inner checksum will be offloaded later. diff --git a/net/core/skbuff.c b/net/core/skbuff.c index b63767008824..0bb0d8877954 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -4891,7 +4891,7 @@ EXPORT_SYMBOL_GPL(skb_scrub_packet); * * The MAC/L2 or network (IP, IPv6) headers are not accounted for. */ -unsigned int skb_gso_transport_seglen(const struct sk_buff *skb) +static unsigned int skb_gso_transport_seglen(const struct sk_buff *skb) { const struct skb_shared_info *shinfo = skb_shinfo(skb); unsigned int thlen = 0; @@ -4913,7 +4913,40 @@ unsigned int skb_gso_transport_seglen(const struct sk_buff *skb) */ return thlen + shinfo->gso_size; } -EXPORT_SYMBOL_GPL(skb_gso_transport_seglen); + +/** + * skb_gso_network_seglen - Return length of individual segments of a gso packet + * + * @skb: GSO skb + * + * skb_gso_network_seglen is used to determine the real size of the + * individual segments, including Layer3 (IP, IPv6) and L4 headers (TCP/UDP). + * + * The MAC/L2 header is not accounted for. + */ +static unsigned int skb_gso_network_seglen(const struct sk_buff *skb) +{ + unsigned int hdr_len = skb_transport_header(skb) - + skb_network_header(skb); + + return hdr_len + skb_gso_transport_seglen(skb); +} + +/** + * skb_gso_mac_seglen - Return length of individual segments of a gso packet + * + * @skb: GSO skb + * + * skb_gso_mac_seglen is used to determine the real size of the + * individual segments, including MAC/L2, Layer3 (IP, IPv6) and L4 + * headers (TCP/UDP). + */ +static unsigned int skb_gso_mac_seglen(const struct sk_buff *skb) +{ + unsigned int hdr_len = skb_transport_header(skb) - skb_mac_header(skb); + + return hdr_len + skb_gso_transport_seglen(skb); +} /** * skb_gso_size_check - check the skb size, considering GSO_BY_FRAGS -- cgit v1.2.3 From 218f6024abec04ec78e56b6761f70d404bab8637 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 18 Jan 2018 01:28:10 +0900 Subject: mmc: tmio: remove TMIO_MMC_WRPROTECT_DISABLE The use of this flag has been replaced with MMC_CAP2_NO_WRITE_PROTECT. No platform defines this flag any more. Remove. Signed-off-by: Masahiro Yamada Acked-by: Lee Jones Reviewed-by: Wolfram Sang Signed-off-by: Ulf Hansson Tested-by: Wolfram Sang --- drivers/mmc/host/tmio_mmc_core.c | 5 ++--- include/linux/mfd/tmio.h | 1 - 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index 1497da07e33c..fb5a29c93ec5 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -1061,10 +1061,9 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) static int tmio_mmc_get_ro(struct mmc_host *mmc) { struct tmio_mmc_host *host = mmc_priv(mmc); - struct tmio_mmc_data *pdata = host->pdata; - return !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) || - (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)); + return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & + TMIO_STAT_WRPROTECT); } static int tmio_multi_io_quirk(struct mmc_card *card, diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 396a103c8bc6..91f92215ca74 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -36,7 +36,6 @@ } while (0) /* tmio MMC platform flags */ -#define TMIO_MMC_WRPROTECT_DISABLE BIT(0) /* * Some controllers can support a 2-byte block size when the bus width * is configured in 4-bit mode. -- cgit v1.2.3 From 36f1d7e817a5540f6624ce1007339688bd443308 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 27 Feb 2018 14:51:25 +0200 Subject: mmc: slot-gpio: Add a function to enable/disable card detect IRQ wakeup Commit 03dbaa04a2e5 ("mmc: slot-gpio: Add support to enable irq wake on cd_irq") enabled wakeup at initialization. However drivers may wish to enable and disable based on different criteria. Add a helper function mmc_gpio_set_cd_wake() to make it easy for drivers to do that. Signed-off-by: Adrian Hunter Signed-off-by: Ulf Hansson --- drivers/mmc/core/core.c | 3 +-- drivers/mmc/core/slot-gpio.c | 21 +++++++++++++++++++++ include/linux/mmc/slot-gpio.h | 1 + 3 files changed, 23 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index e01910dd964b..121ce50b6d5e 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -2655,8 +2655,7 @@ void mmc_start_host(struct mmc_host *host) void mmc_stop_host(struct mmc_host *host) { if (host->slot.cd_irq >= 0) { - if (host->slot.cd_wake_enabled) - disable_irq_wake(host->slot.cd_irq); + mmc_gpio_set_cd_wake(host, false); disable_irq(host->slot.cd_irq); } diff --git a/drivers/mmc/core/slot-gpio.c b/drivers/mmc/core/slot-gpio.c index 3698b0576009..dccbc52af5c4 100644 --- a/drivers/mmc/core/slot-gpio.c +++ b/drivers/mmc/core/slot-gpio.c @@ -154,6 +154,27 @@ void mmc_gpiod_request_cd_irq(struct mmc_host *host) } EXPORT_SYMBOL(mmc_gpiod_request_cd_irq); +int mmc_gpio_set_cd_wake(struct mmc_host *host, bool on) +{ + int ret = 0; + + if (!(host->caps & MMC_CAP_CD_WAKE) || + host->slot.cd_irq < 0 || + on == host->slot.cd_wake_enabled) + return 0; + + if (on) { + ret = enable_irq_wake(host->slot.cd_irq); + host->slot.cd_wake_enabled = !ret; + } else { + disable_irq_wake(host->slot.cd_irq); + host->slot.cd_wake_enabled = false; + } + + return ret; +} +EXPORT_SYMBOL(mmc_gpio_set_cd_wake); + /* Register an alternate interrupt service routine for * the card-detect GPIO. */ diff --git a/include/linux/mmc/slot-gpio.h b/include/linux/mmc/slot-gpio.h index 91f1ba0663c8..06607c59c4d0 100644 --- a/include/linux/mmc/slot-gpio.h +++ b/include/linux/mmc/slot-gpio.h @@ -31,6 +31,7 @@ int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id, unsigned int debounce, bool *gpio_invert); void mmc_gpio_set_cd_isr(struct mmc_host *host, irqreturn_t (*isr)(int irq, void *dev_id)); +int mmc_gpio_set_cd_wake(struct mmc_host *host, bool on); void mmc_gpiod_request_cd_irq(struct mmc_host *host); bool mmc_can_gpio_cd(struct mmc_host *host); bool mmc_can_gpio_ro(struct mmc_host *host); -- cgit v1.2.3 From 01fd61c0b9bd85ab41fb60fbd781d44882ee6887 Mon Sep 17 00:00:00 2001 From: Sinan Kaya Date: Tue, 27 Feb 2018 14:14:11 -0600 Subject: PCI: Add a return type for pci_reset_bridge_secondary_bus() Add a return value to pci_reset_bridge_secondary_bus() so we can return an error if the device doesn't become ready after the reset. Signed-off-by: Sinan Kaya Signed-off-by: Bjorn Helgaas Reviewed-by: Christoph Hellwig --- drivers/pci/pci.c | 4 +++- include/linux/pci.h | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index a3042e475901..dde40506ffe5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4229,9 +4229,11 @@ void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) * Use the bridge control register to assert reset on the secondary bus. * Devices on the secondary bus are left in power-on state. */ -void pci_reset_bridge_secondary_bus(struct pci_dev *dev) +int pci_reset_bridge_secondary_bus(struct pci_dev *dev) { pcibios_reset_secondary_bus(dev); + + return 0; } EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); diff --git a/include/linux/pci.h b/include/linux/pci.h index af75d9d76189..562875d34b98 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1095,7 +1095,7 @@ int pci_reset_bus(struct pci_bus *bus); int pci_try_reset_bus(struct pci_bus *bus); void pci_reset_secondary_bus(struct pci_dev *dev); void pcibios_reset_secondary_bus(struct pci_dev *dev); -void pci_reset_bridge_secondary_bus(struct pci_dev *dev); +int pci_reset_bridge_secondary_bus(struct pci_dev *dev); void pci_update_resource(struct pci_dev *dev, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); -- cgit v1.2.3 From cceae76ef3a1181242e4f7b559a7bfc904a9855c Mon Sep 17 00:00:00 2001 From: Taehee Yoo Date: Sun, 11 Feb 2018 19:17:20 +0900 Subject: netfilter: nfnetlink_acct: remove useless parameter parameter skb in nfnl_acct_overquota is not used anywhere. Signed-off-by: Taehee Yoo Signed-off-by: Pablo Neira Ayuso --- include/linux/netfilter/nfnetlink_acct.h | 3 +-- net/netfilter/nfnetlink_acct.c | 3 +-- net/netfilter/xt_nfacct.c | 2 +- 3 files changed, 3 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/netfilter/nfnetlink_acct.h b/include/linux/netfilter/nfnetlink_acct.h index b4d741195c28..beee8bffe49e 100644 --- a/include/linux/netfilter/nfnetlink_acct.h +++ b/include/linux/netfilter/nfnetlink_acct.h @@ -16,6 +16,5 @@ struct nf_acct; struct nf_acct *nfnl_acct_find_get(struct net *net, const char *filter_name); void nfnl_acct_put(struct nf_acct *acct); void nfnl_acct_update(const struct sk_buff *skb, struct nf_acct *nfacct); -int nfnl_acct_overquota(struct net *net, const struct sk_buff *skb, - struct nf_acct *nfacct); +int nfnl_acct_overquota(struct net *net, struct nf_acct *nfacct); #endif /* _NFNL_ACCT_H */ diff --git a/net/netfilter/nfnetlink_acct.c b/net/netfilter/nfnetlink_acct.c index 88d427f9f9e6..b9505bcd3827 100644 --- a/net/netfilter/nfnetlink_acct.c +++ b/net/netfilter/nfnetlink_acct.c @@ -467,8 +467,7 @@ static void nfnl_overquota_report(struct net *net, struct nf_acct *nfacct) GFP_ATOMIC); } -int nfnl_acct_overquota(struct net *net, const struct sk_buff *skb, - struct nf_acct *nfacct) +int nfnl_acct_overquota(struct net *net, struct nf_acct *nfacct) { u64 now; u64 *quota; diff --git a/net/netfilter/xt_nfacct.c b/net/netfilter/xt_nfacct.c index c8674deed4eb..6b56f4170860 100644 --- a/net/netfilter/xt_nfacct.c +++ b/net/netfilter/xt_nfacct.c @@ -28,7 +28,7 @@ static bool nfacct_mt(const struct sk_buff *skb, struct xt_action_param *par) nfnl_acct_update(skb, info->nfacct); - overquota = nfnl_acct_overquota(xt_net(par), skb, info->nfacct); + overquota = nfnl_acct_overquota(xt_net(par), info->nfacct); return overquota == NFACCT_UNDERQUOTA ? false : true; } -- cgit v1.2.3 From 1b293e30f759b03f246baae862bdf35e57b2c39e Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 27 Feb 2018 19:42:29 +0100 Subject: netfilter: x_tables: move hook entry checks into core Allow followup patch to change on location instead of three. Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- include/linux/netfilter/x_tables.h | 2 ++ net/ipv4/netfilter/arp_tables.c | 13 +++---------- net/ipv4/netfilter/ip_tables.c | 13 +++---------- net/ipv6/netfilter/ip6_tables.c | 13 +++---------- net/netfilter/x_tables.c | 29 +++++++++++++++++++++++++++++ 5 files changed, 40 insertions(+), 30 deletions(-) (limited to 'include/linux') diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h index 1313b35c3ab7..fa0c19c328f1 100644 --- a/include/linux/netfilter/x_tables.h +++ b/include/linux/netfilter/x_tables.h @@ -281,6 +281,8 @@ int xt_check_entry_offsets(const void *base, const char *elems, unsigned int target_offset, unsigned int next_offset); +int xt_check_table_hooks(const struct xt_table_info *info, unsigned int valid_hooks); + unsigned int *xt_alloc_entry_offsets(unsigned int size); bool xt_find_jump_offset(const unsigned int *offsets, unsigned int target, unsigned int size); diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index c9ffa884a4ee..be5821215ea0 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -555,16 +555,9 @@ static int translate_table(struct xt_table_info *newinfo, void *entry0, if (i != repl->num_entries) goto out_free; - /* Check hooks all assigned */ - for (i = 0; i < NF_ARP_NUMHOOKS; i++) { - /* Only hooks which are valid */ - if (!(repl->valid_hooks & (1 << i))) - continue; - if (newinfo->hook_entry[i] == 0xFFFFFFFF) - goto out_free; - if (newinfo->underflow[i] == 0xFFFFFFFF) - goto out_free; - } + ret = xt_check_table_hooks(newinfo, repl->valid_hooks); + if (ret) + goto out_free; if (!mark_source_chains(newinfo, repl->valid_hooks, entry0, offsets)) { ret = -ELOOP; diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c index c9b57a6bf96a..29bda9484a33 100644 --- a/net/ipv4/netfilter/ip_tables.c +++ b/net/ipv4/netfilter/ip_tables.c @@ -702,16 +702,9 @@ translate_table(struct net *net, struct xt_table_info *newinfo, void *entry0, if (i != repl->num_entries) goto out_free; - /* Check hooks all assigned */ - for (i = 0; i < NF_INET_NUMHOOKS; i++) { - /* Only hooks which are valid */ - if (!(repl->valid_hooks & (1 << i))) - continue; - if (newinfo->hook_entry[i] == 0xFFFFFFFF) - goto out_free; - if (newinfo->underflow[i] == 0xFFFFFFFF) - goto out_free; - } + ret = xt_check_table_hooks(newinfo, repl->valid_hooks); + if (ret) + goto out_free; if (!mark_source_chains(newinfo, repl->valid_hooks, entry0, offsets)) { ret = -ELOOP; diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c index f46954221933..ba3776a4d305 100644 --- a/net/ipv6/netfilter/ip6_tables.c +++ b/net/ipv6/netfilter/ip6_tables.c @@ -720,16 +720,9 @@ translate_table(struct net *net, struct xt_table_info *newinfo, void *entry0, if (i != repl->num_entries) goto out_free; - /* Check hooks all assigned */ - for (i = 0; i < NF_INET_NUMHOOKS; i++) { - /* Only hooks which are valid */ - if (!(repl->valid_hooks & (1 << i))) - continue; - if (newinfo->hook_entry[i] == 0xFFFFFFFF) - goto out_free; - if (newinfo->underflow[i] == 0xFFFFFFFF) - goto out_free; - } + ret = xt_check_table_hooks(newinfo, repl->valid_hooks); + if (ret) + goto out_free; if (!mark_source_chains(newinfo, repl->valid_hooks, entry0, offsets)) { ret = -ELOOP; diff --git a/net/netfilter/x_tables.c b/net/netfilter/x_tables.c index f045bb4f7063..5d8ba89a8da8 100644 --- a/net/netfilter/x_tables.c +++ b/net/netfilter/x_tables.c @@ -518,6 +518,35 @@ static int xt_check_entry_match(const char *match, const char *target, return 0; } +/** xt_check_table_hooks - check hook entry points are sane + * + * @info xt_table_info to check + * @valid_hooks - hook entry points that we can enter from + * + * Validates that the hook entry and underflows points are set up. + * + * Return: 0 on success, negative errno on failure. + */ +int xt_check_table_hooks(const struct xt_table_info *info, unsigned int valid_hooks) +{ + unsigned int i; + + BUILD_BUG_ON(ARRAY_SIZE(info->hook_entry) != ARRAY_SIZE(info->underflow)); + + for (i = 0; i < ARRAY_SIZE(info->hook_entry); i++) { + if (!(valid_hooks & (1 << i))) + continue; + + if (info->hook_entry[i] == 0xFFFFFFFF) + return -EINVAL; + if (info->underflow[i] == 0xFFFFFFFF) + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(xt_check_table_hooks); + #ifdef CONFIG_COMPAT int xt_compat_add_offset(u_int8_t af, unsigned int offset, int delta) { -- cgit v1.2.3 From c84ca954ac9fa67a6ce27f91f01e4451c74fd8f6 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 27 Feb 2018 19:42:33 +0100 Subject: netfilter: x_tables: add counters allocation wrapper allows to have size checks in a single spot. This is supposed to reduce oom situations when fuzz-testing xtables. Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- include/linux/netfilter/x_tables.h | 1 + net/ipv4/netfilter/arp_tables.c | 2 +- net/ipv4/netfilter/ip_tables.c | 2 +- net/ipv6/netfilter/ip6_tables.c | 2 +- net/netfilter/x_tables.c | 15 +++++++++++++++ 5 files changed, 19 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h index fa0c19c328f1..0bd93c589a8c 100644 --- a/include/linux/netfilter/x_tables.h +++ b/include/linux/netfilter/x_tables.h @@ -301,6 +301,7 @@ int xt_data_to_user(void __user *dst, const void *src, void *xt_copy_counters_from_user(const void __user *user, unsigned int len, struct xt_counters_info *info, bool compat); +struct xt_counters *xt_counters_alloc(unsigned int counters); struct xt_table *xt_register_table(struct net *net, const struct xt_table *table, diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index be5821215ea0..82ba09b50fdb 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -883,7 +883,7 @@ static int __do_replace(struct net *net, const char *name, struct arpt_entry *iter; ret = 0; - counters = vzalloc(num_counters * sizeof(struct xt_counters)); + counters = xt_counters_alloc(num_counters); if (!counters) { ret = -ENOMEM; goto out; diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c index 29bda9484a33..4901ca6c3e09 100644 --- a/net/ipv4/netfilter/ip_tables.c +++ b/net/ipv4/netfilter/ip_tables.c @@ -1045,7 +1045,7 @@ __do_replace(struct net *net, const char *name, unsigned int valid_hooks, struct ipt_entry *iter; ret = 0; - counters = vzalloc(num_counters * sizeof(struct xt_counters)); + counters = xt_counters_alloc(num_counters); if (!counters) { ret = -ENOMEM; goto out; diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c index ba3776a4d305..e84cec49b60f 100644 --- a/net/ipv6/netfilter/ip6_tables.c +++ b/net/ipv6/netfilter/ip6_tables.c @@ -1063,7 +1063,7 @@ __do_replace(struct net *net, const char *name, unsigned int valid_hooks, struct ip6t_entry *iter; ret = 0; - counters = vzalloc(num_counters * sizeof(struct xt_counters)); + counters = xt_counters_alloc(num_counters); if (!counters) { ret = -ENOMEM; goto out; diff --git a/net/netfilter/x_tables.c b/net/netfilter/x_tables.c index 01f8e122e74e..82b1f8f52ac6 100644 --- a/net/netfilter/x_tables.c +++ b/net/netfilter/x_tables.c @@ -1290,6 +1290,21 @@ static int xt_jumpstack_alloc(struct xt_table_info *i) return 0; } +struct xt_counters *xt_counters_alloc(unsigned int counters) +{ + struct xt_counters *mem; + + if (counters == 0 || counters > INT_MAX / sizeof(*mem)) + return NULL; + + counters *= sizeof(*mem); + if (counters > XT_MAX_TABLE_SIZE) + return NULL; + + return vzalloc(counters); +} +EXPORT_SYMBOL(xt_counters_alloc); + struct xt_table_info * xt_replace_table(struct xt_table *table, unsigned int num_counters, -- cgit v1.2.3 From 9782a11efc072faaf91d4aa60e9d23553f918029 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 27 Feb 2018 19:42:34 +0100 Subject: netfilter: compat: prepare xt_compat_init_offsets to return errors should have no impact, function still always returns 0. This patch is only to ease review. Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- include/linux/netfilter/x_tables.h | 2 +- net/bridge/netfilter/ebtables.c | 10 ++++++++-- net/ipv4/netfilter/arp_tables.c | 10 +++++++--- net/ipv4/netfilter/ip_tables.c | 8 ++++++-- net/ipv6/netfilter/ip6_tables.c | 10 +++++++--- net/netfilter/x_tables.c | 4 +++- 6 files changed, 32 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h index 0bd93c589a8c..7bd896dc78df 100644 --- a/include/linux/netfilter/x_tables.h +++ b/include/linux/netfilter/x_tables.h @@ -510,7 +510,7 @@ void xt_compat_unlock(u_int8_t af); int xt_compat_add_offset(u_int8_t af, unsigned int offset, int delta); void xt_compat_flush_offsets(u_int8_t af); -void xt_compat_init_offsets(u_int8_t af, unsigned int number); +int xt_compat_init_offsets(u8 af, unsigned int number); int xt_compat_calc_jump(u_int8_t af, unsigned int offset); int xt_compat_match_offset(const struct xt_match *match); diff --git a/net/bridge/netfilter/ebtables.c b/net/bridge/netfilter/ebtables.c index 02c4b409d317..217aa79f7b2a 100644 --- a/net/bridge/netfilter/ebtables.c +++ b/net/bridge/netfilter/ebtables.c @@ -1819,10 +1819,14 @@ static int compat_table_info(const struct ebt_table_info *info, { unsigned int size = info->entries_size; const void *entries = info->entries; + int ret; newinfo->entries_size = size; - xt_compat_init_offsets(NFPROTO_BRIDGE, info->nentries); + ret = xt_compat_init_offsets(NFPROTO_BRIDGE, info->nentries); + if (ret) + return ret; + return EBT_ENTRY_ITERATE(entries, size, compat_calc_entry, info, entries, newinfo); } @@ -2245,7 +2249,9 @@ static int compat_do_replace(struct net *net, void __user *user, xt_compat_lock(NFPROTO_BRIDGE); - xt_compat_init_offsets(NFPROTO_BRIDGE, tmp.nentries); + ret = xt_compat_init_offsets(NFPROTO_BRIDGE, tmp.nentries); + if (ret < 0) + goto out_unlock; ret = compat_copy_entries(entries_tmp, tmp.entries_size, &state); if (ret < 0) goto out_unlock; diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index 82ba09b50fdb..aaafdbd15ad3 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -769,7 +769,9 @@ static int compat_table_info(const struct xt_table_info *info, memcpy(newinfo, info, offsetof(struct xt_table_info, entries)); newinfo->initial_entries = 0; loc_cpu_entry = info->entries; - xt_compat_init_offsets(NFPROTO_ARP, info->number); + ret = xt_compat_init_offsets(NFPROTO_ARP, info->number); + if (ret) + return ret; xt_entry_foreach(iter, loc_cpu_entry, info->size) { ret = compat_calc_entry(iter, info, loc_cpu_entry, newinfo); if (ret != 0) @@ -1156,7 +1158,7 @@ static int translate_compat_table(struct xt_table_info **pinfo, struct compat_arpt_entry *iter0; struct arpt_replace repl; unsigned int size; - int ret = 0; + int ret; info = *pinfo; entry0 = *pentry0; @@ -1165,7 +1167,9 @@ static int translate_compat_table(struct xt_table_info **pinfo, j = 0; xt_compat_lock(NFPROTO_ARP); - xt_compat_init_offsets(NFPROTO_ARP, compatr->num_entries); + ret = xt_compat_init_offsets(NFPROTO_ARP, compatr->num_entries); + if (ret) + goto out_unlock; /* Walk through entries, checking offsets. */ xt_entry_foreach(iter0, entry0, compatr->size) { ret = check_compat_entry_size_and_hooks(iter0, info, &size, diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c index 4901ca6c3e09..f9063513f9d1 100644 --- a/net/ipv4/netfilter/ip_tables.c +++ b/net/ipv4/netfilter/ip_tables.c @@ -933,7 +933,9 @@ static int compat_table_info(const struct xt_table_info *info, memcpy(newinfo, info, offsetof(struct xt_table_info, entries)); newinfo->initial_entries = 0; loc_cpu_entry = info->entries; - xt_compat_init_offsets(AF_INET, info->number); + ret = xt_compat_init_offsets(AF_INET, info->number); + if (ret) + return ret; xt_entry_foreach(iter, loc_cpu_entry, info->size) { ret = compat_calc_entry(iter, info, loc_cpu_entry, newinfo); if (ret != 0) @@ -1407,7 +1409,9 @@ translate_compat_table(struct net *net, j = 0; xt_compat_lock(AF_INET); - xt_compat_init_offsets(AF_INET, compatr->num_entries); + ret = xt_compat_init_offsets(AF_INET, compatr->num_entries); + if (ret) + goto out_unlock; /* Walk through entries, checking offsets. */ xt_entry_foreach(iter0, entry0, compatr->size) { ret = check_compat_entry_size_and_hooks(iter0, info, &size, diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c index e84cec49b60f..3c36a4c77f29 100644 --- a/net/ipv6/netfilter/ip6_tables.c +++ b/net/ipv6/netfilter/ip6_tables.c @@ -950,7 +950,9 @@ static int compat_table_info(const struct xt_table_info *info, memcpy(newinfo, info, offsetof(struct xt_table_info, entries)); newinfo->initial_entries = 0; loc_cpu_entry = info->entries; - xt_compat_init_offsets(AF_INET6, info->number); + ret = xt_compat_init_offsets(AF_INET6, info->number); + if (ret) + return ret; xt_entry_foreach(iter, loc_cpu_entry, info->size) { ret = compat_calc_entry(iter, info, loc_cpu_entry, newinfo); if (ret != 0) @@ -1414,7 +1416,7 @@ translate_compat_table(struct net *net, struct compat_ip6t_entry *iter0; struct ip6t_replace repl; unsigned int size; - int ret = 0; + int ret; info = *pinfo; entry0 = *pentry0; @@ -1423,7 +1425,9 @@ translate_compat_table(struct net *net, j = 0; xt_compat_lock(AF_INET6); - xt_compat_init_offsets(AF_INET6, compatr->num_entries); + ret = xt_compat_init_offsets(AF_INET6, compatr->num_entries); + if (ret) + goto out_unlock; /* Walk through entries, checking offsets. */ xt_entry_foreach(iter0, entry0, compatr->size) { ret = check_compat_entry_size_and_hooks(iter0, info, &size, diff --git a/net/netfilter/x_tables.c b/net/netfilter/x_tables.c index 82b1f8f52ac6..e878c85a9268 100644 --- a/net/netfilter/x_tables.c +++ b/net/netfilter/x_tables.c @@ -632,10 +632,12 @@ int xt_compat_calc_jump(u_int8_t af, unsigned int offset) } EXPORT_SYMBOL_GPL(xt_compat_calc_jump); -void xt_compat_init_offsets(u_int8_t af, unsigned int number) +int xt_compat_init_offsets(u8 af, unsigned int number) { xt[af].number = number; xt[af].cur = 0; + + return 0; } EXPORT_SYMBOL(xt_compat_init_offsets); -- cgit v1.2.3 From a6f1086e29e93621a6394b94b8c0e4a4e490f38b Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Mon, 5 Mar 2018 15:22:30 -0800 Subject: PCI: Move of_irq_parse_and_map_pci() declaration under OF_IRQ Since commit 4670d610d592 ("PCI: Move OF-related PCI functions into PCI core"), sparc:allmodconfig fails to build with the following error. pcie-cadence-host.c:(.text+0x4c4): undefined reference to `of_irq_parse_and_map_pci' pcie-cadence-host.c:(.text+0x4c8): undefined reference to `of_irq_parse_and_map_pci' of_irq_parse_and_map_pci() is now only available if OF_IRQ is enabled. Make its declaration and its dummy function dependent on OF_IRQ to solve the problem. Fixes: 4670d610d592 ("PCI: Move OF-related PCI functions into PCI core") Signed-off-by: Guenter Roeck Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring --- include/linux/of_pci.h | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index 88865e0ebf4d..091033a6b836 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -13,7 +13,6 @@ struct device_node; struct device_node *of_pci_find_child_device(struct device_node *parent, unsigned int devfn); int of_pci_get_devfn(struct device_node *np); -int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin); int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); int of_pci_get_max_link_speed(struct device_node *node); @@ -33,12 +32,6 @@ static inline int of_pci_get_devfn(struct device_node *np) return -EINVAL; } -static inline int -of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return 0; -} - static inline int of_pci_parse_bus_range(struct device_node *node, struct resource *res) { @@ -67,6 +60,16 @@ of_pci_get_max_link_speed(struct device_node *node) static inline void of_pci_check_probe_only(void) { } #endif +#if IS_ENABLED(CONFIG_OF_IRQ) +int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin); +#else +static inline int +of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return 0; +} +#endif + #if defined(CONFIG_OF_ADDRESS) int of_pci_get_host_bridge_resources(struct device_node *dev, unsigned char busno, unsigned char bus_max, -- cgit v1.2.3 From 9130ba884640328bb78aaa4840e5ddf06ccafb1c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 27 Feb 2018 17:40:38 -0600 Subject: scripts/dtc: Update to upstream version v1.4.6-9-gaadd0b65c987 This adds the following commits from upstream: aadd0b65c987 checks: centralize printing of property names in failure messages 88960e398907 checks: centralize printing of node path in check_msg f1879e1a50eb Add limited read-only support for older (V2 and V3) device tree to libfdt. 37dea76e9700 srcpos: drop special handling of tab 65893da4aee0 libfdt: overlay: Add missing license 962a45ca034d Avoid installing pylibfdt when dependencies are missing cd6ea1b2bea6 Makefile: Split INSTALL out into INSTALL_{PROGRAM,LIB,DATA,SCRIPT} 51b3a16338df Makefile.tests: Add LIBDL make(1) variable for portability sake 333d533a8f4d Attempt to auto-detect stat(1) being used if not given proper invocation e54388015af1 dtc: Bump version to v1.4.6 a1fe86f380cb fdtoverlay: Switch from using alloca to malloc c8d5472de3ff tests: Improve compatibility with other platforms c81d389a10cc checks: add chosen node checks e671852042a7 checks: add aliases node checks d0c44ebe3f42 checks: check for #{size,address}-cells without child nodes 18a3d84bb802 checks: add string list check for *-names properties 8fe94fd6f19f checks: add string list check 6c5730819604 checks: add a string check for 'label' property a384191eba09 checks: fix sound-dai phandle with arg property check b260c4f610c0 Fix ambiguous grammar for devicetree rule fe667e382bac tests: Add some basic tests for the pci_bridge checks 7975f6422260 Fix widespread incorrect use of strneq(), replace with new strprefixeq() fca296445eab Add strstarts() helper function cc392f089007 tests: Check non-matching cases for fdt_node_check_compatible() bba26a5291c8 livetree: avoid assertion of orphan phandles with overlays c8f8194d76cc implement strnlen for systems that need it c8b38f65fdec libfdt: Remove leading underscores from identifiers 3b62fdaebfe5 Remove leading underscores from identifiers 2d45d1c5c65e Replace FDT_VERSION() with stringify() 2e6fe5a107b5 Fix some errors in comments b0ae9e4b0ceb tests: Correct warning in sw_tree1.c Commit c8b38f65fdec upstream ("libfdt: Remove leading underscores from identifiers") changed the multiple inclusion define protection, so the kernel's libfdt_env.h needs the corresponding update. Signed-off-by: Rob Herring --- include/linux/libfdt_env.h | 6 +- scripts/dtc/checks.c | 439 +++++++++++++++++++++++------------ scripts/dtc/dtc-parser.y | 17 +- scripts/dtc/dtc.c | 7 +- scripts/dtc/dtc.h | 11 +- scripts/dtc/flattree.c | 2 +- scripts/dtc/libfdt/fdt.c | 13 +- scripts/dtc/libfdt/fdt.h | 6 +- scripts/dtc/libfdt/fdt_overlay.c | 51 ++++ scripts/dtc/libfdt/fdt_ro.c | 132 ++++++++--- scripts/dtc/libfdt/fdt_rw.c | 90 +++---- scripts/dtc/libfdt/fdt_sw.c | 24 +- scripts/dtc/libfdt/fdt_wip.c | 10 +- scripts/dtc/libfdt/libfdt.h | 37 +-- scripts/dtc/libfdt/libfdt_env.h | 33 ++- scripts/dtc/libfdt/libfdt_internal.h | 32 +-- scripts/dtc/livetree.c | 10 +- scripts/dtc/srcpos.c | 5 - scripts/dtc/srcpos.h | 6 +- scripts/dtc/util.h | 9 +- scripts/dtc/version_gen.h | 2 +- 21 files changed, 622 insertions(+), 320 deletions(-) (limited to 'include/linux') diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h index 14997285e53d..c6ac1fe7ec68 100644 --- a/include/linux/libfdt_env.h +++ b/include/linux/libfdt_env.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _LIBFDT_ENV_H -#define _LIBFDT_ENV_H +#ifndef LIBFDT_ENV_H +#define LIBFDT_ENV_H #include @@ -15,4 +15,4 @@ typedef __be64 fdt64_t; #define fdt64_to_cpu(x) be64_to_cpu(x) #define cpu_to_fdt64(x) cpu_to_be64(x) -#endif /* _LIBFDT_ENV_H */ +#endif /* LIBFDT_ENV_H */ diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c index e66138449886..c07ba4da9e36 100644 --- a/scripts/dtc/checks.c +++ b/scripts/dtc/checks.c @@ -53,26 +53,28 @@ struct check { struct check **prereq; }; -#define CHECK_ENTRY(_nm, _fn, _d, _w, _e, ...) \ - static struct check *_nm##_prereqs[] = { __VA_ARGS__ }; \ - static struct check _nm = { \ - .name = #_nm, \ - .fn = (_fn), \ - .data = (_d), \ - .warn = (_w), \ - .error = (_e), \ +#define CHECK_ENTRY(nm_, fn_, d_, w_, e_, ...) \ + static struct check *nm_##_prereqs[] = { __VA_ARGS__ }; \ + static struct check nm_ = { \ + .name = #nm_, \ + .fn = (fn_), \ + .data = (d_), \ + .warn = (w_), \ + .error = (e_), \ .status = UNCHECKED, \ - .num_prereqs = ARRAY_SIZE(_nm##_prereqs), \ - .prereq = _nm##_prereqs, \ + .num_prereqs = ARRAY_SIZE(nm_##_prereqs), \ + .prereq = nm_##_prereqs, \ }; -#define WARNING(_nm, _fn, _d, ...) \ - CHECK_ENTRY(_nm, _fn, _d, true, false, __VA_ARGS__) -#define ERROR(_nm, _fn, _d, ...) \ - CHECK_ENTRY(_nm, _fn, _d, false, true, __VA_ARGS__) -#define CHECK(_nm, _fn, _d, ...) \ - CHECK_ENTRY(_nm, _fn, _d, false, false, __VA_ARGS__) - -static inline void PRINTF(3, 4) check_msg(struct check *c, struct dt_info *dti, +#define WARNING(nm_, fn_, d_, ...) \ + CHECK_ENTRY(nm_, fn_, d_, true, false, __VA_ARGS__) +#define ERROR(nm_, fn_, d_, ...) \ + CHECK_ENTRY(nm_, fn_, d_, false, true, __VA_ARGS__) +#define CHECK(nm_, fn_, d_, ...) \ + CHECK_ENTRY(nm_, fn_, d_, false, false, __VA_ARGS__) + +static inline void PRINTF(5, 6) check_msg(struct check *c, struct dt_info *dti, + struct node *node, + struct property *prop, const char *fmt, ...) { va_list ap; @@ -83,19 +85,33 @@ static inline void PRINTF(3, 4) check_msg(struct check *c, struct dt_info *dti, fprintf(stderr, "%s: %s (%s): ", strcmp(dti->outname, "-") ? dti->outname : "", (c->error) ? "ERROR" : "Warning", c->name); + if (node) { + fprintf(stderr, "%s", node->fullpath); + if (prop) + fprintf(stderr, ":%s", prop->name); + fputs(": ", stderr); + } vfprintf(stderr, fmt, ap); fprintf(stderr, "\n"); } va_end(ap); } -#define FAIL(c, dti, ...) \ +#define FAIL(c, dti, node, ...) \ + do { \ + TRACE((c), "\t\tFAILED at %s:%d", __FILE__, __LINE__); \ + (c)->status = FAILED; \ + check_msg((c), dti, node, NULL, __VA_ARGS__); \ + } while (0) + +#define FAIL_PROP(c, dti, node, prop, ...) \ do { \ TRACE((c), "\t\tFAILED at %s:%d", __FILE__, __LINE__); \ (c)->status = FAILED; \ - check_msg((c), dti, __VA_ARGS__); \ + check_msg((c), dti, node, prop, __VA_ARGS__); \ } while (0) + static void check_nodes_props(struct check *c, struct dt_info *dti, struct node *node) { struct node *child; @@ -126,7 +142,7 @@ static bool run_check(struct check *c, struct dt_info *dti) error = error || run_check(prq, dti); if (prq->status != PASSED) { c->status = PREREQ; - check_msg(c, dti, "Failed prerequisite '%s'", + check_msg(c, dti, NULL, NULL, "Failed prerequisite '%s'", c->prereq[i]->name); } } @@ -156,7 +172,7 @@ out: static inline void check_always_fail(struct check *c, struct dt_info *dti, struct node *node) { - FAIL(c, dti, "always_fail check"); + FAIL(c, dti, node, "always_fail check"); } CHECK(always_fail, check_always_fail, NULL); @@ -171,14 +187,42 @@ static void check_is_string(struct check *c, struct dt_info *dti, return; /* Not present, assumed ok */ if (!data_is_one_string(prop->val)) - FAIL(c, dti, "\"%s\" property in %s is not a string", - propname, node->fullpath); + FAIL_PROP(c, dti, node, prop, "property is not a string"); } #define WARNING_IF_NOT_STRING(nm, propname) \ WARNING(nm, check_is_string, (propname)) #define ERROR_IF_NOT_STRING(nm, propname) \ ERROR(nm, check_is_string, (propname)) +static void check_is_string_list(struct check *c, struct dt_info *dti, + struct node *node) +{ + int rem, l; + struct property *prop; + char *propname = c->data; + char *str; + + prop = get_property(node, propname); + if (!prop) + return; /* Not present, assumed ok */ + + str = prop->val.val; + rem = prop->val.len; + while (rem > 0) { + l = strnlen(str, rem); + if (l == rem) { + FAIL_PROP(c, dti, node, prop, "property is not a string list"); + break; + } + rem -= l + 1; + str += l + 1; + } +} +#define WARNING_IF_NOT_STRING_LIST(nm, propname) \ + WARNING(nm, check_is_string_list, (propname)) +#define ERROR_IF_NOT_STRING_LIST(nm, propname) \ + ERROR(nm, check_is_string_list, (propname)) + static void check_is_cell(struct check *c, struct dt_info *dti, struct node *node) { @@ -190,8 +234,7 @@ static void check_is_cell(struct check *c, struct dt_info *dti, return; /* Not present, assumed ok */ if (prop->val.len != sizeof(cell_t)) - FAIL(c, dti, "\"%s\" property in %s is not a single cell", - propname, node->fullpath); + FAIL_PROP(c, dti, node, prop, "property is not a single cell"); } #define WARNING_IF_NOT_CELL(nm, propname) \ WARNING(nm, check_is_cell, (propname)) @@ -212,8 +255,7 @@ static void check_duplicate_node_names(struct check *c, struct dt_info *dti, child2; child2 = child2->next_sibling) if (streq(child->name, child2->name)) - FAIL(c, dti, "Duplicate node name %s", - child->fullpath); + FAIL(c, dti, node, "Duplicate node name"); } ERROR(duplicate_node_names, check_duplicate_node_names, NULL); @@ -227,8 +269,7 @@ static void check_duplicate_property_names(struct check *c, struct dt_info *dti, if (prop2->deleted) continue; if (streq(prop->name, prop2->name)) - FAIL(c, dti, "Duplicate property name %s in %s", - prop->name, node->fullpath); + FAIL_PROP(c, dti, node, prop, "Duplicate property name"); } } } @@ -246,8 +287,8 @@ static void check_node_name_chars(struct check *c, struct dt_info *dti, int n = strspn(node->name, c->data); if (n < strlen(node->name)) - FAIL(c, dti, "Bad character '%c' in node %s", - node->name[n], node->fullpath); + FAIL(c, dti, node, "Bad character '%c' in node name", + node->name[n]); } ERROR(node_name_chars, check_node_name_chars, PROPNODECHARS "@"); @@ -257,8 +298,8 @@ static void check_node_name_chars_strict(struct check *c, struct dt_info *dti, int n = strspn(node->name, c->data); if (n < node->basenamelen) - FAIL(c, dti, "Character '%c' not recommended in node %s", - node->name[n], node->fullpath); + FAIL(c, dti, node, "Character '%c' not recommended in node name", + node->name[n]); } CHECK(node_name_chars_strict, check_node_name_chars_strict, PROPNODECHARSSTRICT); @@ -266,8 +307,7 @@ static void check_node_name_format(struct check *c, struct dt_info *dti, struct node *node) { if (strchr(get_unitname(node), '@')) - FAIL(c, dti, "Node %s has multiple '@' characters in name", - node->fullpath); + FAIL(c, dti, node, "multiple '@' characters in node name"); } ERROR(node_name_format, check_node_name_format, NULL, &node_name_chars); @@ -285,12 +325,10 @@ static void check_unit_address_vs_reg(struct check *c, struct dt_info *dti, if (prop) { if (!unitname[0]) - FAIL(c, dti, "Node %s has a reg or ranges property, but no unit name", - node->fullpath); + FAIL(c, dti, node, "node has a reg or ranges property, but no unit name"); } else { if (unitname[0]) - FAIL(c, dti, "Node %s has a unit name, but no reg property", - node->fullpath); + FAIL(c, dti, node, "node has a unit name, but no reg property"); } } WARNING(unit_address_vs_reg, check_unit_address_vs_reg, NULL); @@ -304,8 +342,8 @@ static void check_property_name_chars(struct check *c, struct dt_info *dti, int n = strspn(prop->name, c->data); if (n < strlen(prop->name)) - FAIL(c, dti, "Bad character '%c' in property name \"%s\", node %s", - prop->name[n], prop->name, node->fullpath); + FAIL_PROP(c, dti, node, prop, "Bad character '%c' in property name", + prop->name[n]); } } ERROR(property_name_chars, check_property_name_chars, PROPNODECHARS); @@ -336,8 +374,8 @@ static void check_property_name_chars_strict(struct check *c, n = strspn(name, c->data); } if (n < strlen(name)) - FAIL(c, dti, "Character '%c' not recommended in property name \"%s\", node %s", - name[n], prop->name, node->fullpath); + FAIL_PROP(c, dti, node, prop, "Character '%c' not recommended in property name", + name[n]); } } CHECK(property_name_chars_strict, check_property_name_chars_strict, PROPNODECHARSSTRICT); @@ -370,7 +408,7 @@ static void check_duplicate_label(struct check *c, struct dt_info *dti, return; if ((othernode != node) || (otherprop != prop) || (othermark != mark)) - FAIL(c, dti, "Duplicate label '%s' on " DESCLABEL_FMT + FAIL(c, dti, node, "Duplicate label '%s' on " DESCLABEL_FMT " and " DESCLABEL_FMT, label, DESCLABEL_ARGS(node, prop, mark), DESCLABEL_ARGS(othernode, otherprop, othermark)); @@ -410,8 +448,8 @@ static cell_t check_phandle_prop(struct check *c, struct dt_info *dti, return 0; if (prop->val.len != sizeof(cell_t)) { - FAIL(c, dti, "%s has bad length (%d) %s property", - node->fullpath, prop->val.len, prop->name); + FAIL_PROP(c, dti, node, prop, "bad length (%d) %s property", + prop->val.len, prop->name); return 0; } @@ -422,8 +460,8 @@ static cell_t check_phandle_prop(struct check *c, struct dt_info *dti, /* "Set this node's phandle equal to some * other node's phandle". That's nonsensical * by construction. */ { - FAIL(c, dti, "%s in %s is a reference to another node", - prop->name, node->fullpath); + FAIL(c, dti, node, "%s is a reference to another node", + prop->name); } /* But setting this node's phandle equal to its own * phandle is allowed - that means allocate a unique @@ -436,8 +474,8 @@ static cell_t check_phandle_prop(struct check *c, struct dt_info *dti, phandle = propval_cell(prop); if ((phandle == 0) || (phandle == -1)) { - FAIL(c, dti, "%s has bad value (0x%x) in %s property", - node->fullpath, phandle, prop->name); + FAIL_PROP(c, dti, node, prop, "bad value (0x%x) in %s property", + phandle, prop->name); return 0; } @@ -463,16 +501,16 @@ static void check_explicit_phandles(struct check *c, struct dt_info *dti, return; if (linux_phandle && phandle && (phandle != linux_phandle)) - FAIL(c, dti, "%s has mismatching 'phandle' and 'linux,phandle'" - " properties", node->fullpath); + FAIL(c, dti, node, "mismatching 'phandle' and 'linux,phandle'" + " properties"); if (linux_phandle && !phandle) phandle = linux_phandle; other = get_node_by_phandle(root, phandle); if (other && (other != node)) { - FAIL(c, dti, "%s has duplicated phandle 0x%x (seen before at %s)", - node->fullpath, phandle, other->fullpath); + FAIL(c, dti, node, "duplicated phandle 0x%x (seen before at %s)", + phandle, other->fullpath); return; } @@ -496,8 +534,8 @@ static void check_name_properties(struct check *c, struct dt_info *dti, if ((prop->val.len != node->basenamelen+1) || (memcmp(prop->val.val, node->name, node->basenamelen) != 0)) { - FAIL(c, dti, "\"name\" property in %s is incorrect (\"%s\" instead" - " of base node name)", node->fullpath, prop->val.val); + FAIL(c, dti, node, "\"name\" property is incorrect (\"%s\" instead" + " of base node name)", prop->val.val); } else { /* The name property is correct, and therefore redundant. * Delete it */ @@ -531,7 +569,7 @@ static void fixup_phandle_references(struct check *c, struct dt_info *dti, refnode = get_node_by_ref(dt, m->ref); if (! refnode) { if (!(dti->dtsflags & DTSF_PLUGIN)) - FAIL(c, dti, "Reference to non-existent node or " + FAIL(c, dti, node, "Reference to non-existent node or " "label \"%s\"\n", m->ref); else /* mark the entry as unresolved */ *((fdt32_t *)(prop->val.val + m->offset)) = @@ -563,7 +601,7 @@ static void fixup_path_references(struct check *c, struct dt_info *dti, refnode = get_node_by_ref(dt, m->ref); if (!refnode) { - FAIL(c, dti, "Reference to non-existent node or label \"%s\"\n", + FAIL(c, dti, node, "Reference to non-existent node or label \"%s\"\n", m->ref); continue; } @@ -586,6 +624,45 @@ WARNING_IF_NOT_CELL(interrupt_cells_is_cell, "#interrupt-cells"); WARNING_IF_NOT_STRING(device_type_is_string, "device_type"); WARNING_IF_NOT_STRING(model_is_string, "model"); WARNING_IF_NOT_STRING(status_is_string, "status"); +WARNING_IF_NOT_STRING(label_is_string, "label"); + +WARNING_IF_NOT_STRING_LIST(compatible_is_string_list, "compatible"); + +static void check_names_is_string_list(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + for_each_property(node, prop) { + const char *s = strrchr(prop->name, '-'); + if (!s || !streq(s, "-names")) + continue; + + c->data = prop->name; + check_is_string_list(c, dti, node); + } +} +WARNING(names_is_string_list, check_names_is_string_list, NULL); + +static void check_alias_paths(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + if (!streq(node->name, "aliases")) + return; + + for_each_property(node, prop) { + if (!prop->val.val || !get_node_by_path(dti->dt, prop->val.val)) { + FAIL_PROP(c, dti, node, prop, "aliases property is not a valid node (%s)", + prop->val.val); + continue; + } + if (strspn(prop->name, LOWERCASE DIGITS "-") != strlen(prop->name)) + FAIL(c, dti, node, "aliases property name must include only lowercase and '-'"); + } +} +WARNING(alias_paths, check_alias_paths, NULL); static void fixup_addr_size_cells(struct check *c, struct dt_info *dti, struct node *node) @@ -622,21 +699,21 @@ static void check_reg_format(struct check *c, struct dt_info *dti, return; /* No "reg", that's fine */ if (!node->parent) { - FAIL(c, dti, "Root node has a \"reg\" property"); + FAIL(c, dti, node, "Root node has a \"reg\" property"); return; } if (prop->val.len == 0) - FAIL(c, dti, "\"reg\" property in %s is empty", node->fullpath); + FAIL_PROP(c, dti, node, prop, "property is empty"); addr_cells = node_addr_cells(node->parent); size_cells = node_size_cells(node->parent); entrylen = (addr_cells + size_cells) * sizeof(cell_t); if (!entrylen || (prop->val.len % entrylen) != 0) - FAIL(c, dti, "\"reg\" property in %s has invalid length (%d bytes) " - "(#address-cells == %d, #size-cells == %d)", - node->fullpath, prop->val.len, addr_cells, size_cells); + FAIL_PROP(c, dti, node, prop, "property has invalid length (%d bytes) " + "(#address-cells == %d, #size-cells == %d)", + prop->val.len, addr_cells, size_cells); } WARNING(reg_format, check_reg_format, NULL, &addr_size_cells); @@ -651,7 +728,7 @@ static void check_ranges_format(struct check *c, struct dt_info *dti, return; if (!node->parent) { - FAIL(c, dti, "Root node has a \"ranges\" property"); + FAIL_PROP(c, dti, node, prop, "Root node has a \"ranges\" property"); return; } @@ -663,20 +740,20 @@ static void check_ranges_format(struct check *c, struct dt_info *dti, if (prop->val.len == 0) { if (p_addr_cells != c_addr_cells) - FAIL(c, dti, "%s has empty \"ranges\" property but its " - "#address-cells (%d) differs from %s (%d)", - node->fullpath, c_addr_cells, node->parent->fullpath, - p_addr_cells); + FAIL_PROP(c, dti, node, prop, "empty \"ranges\" property but its " + "#address-cells (%d) differs from %s (%d)", + c_addr_cells, node->parent->fullpath, + p_addr_cells); if (p_size_cells != c_size_cells) - FAIL(c, dti, "%s has empty \"ranges\" property but its " - "#size-cells (%d) differs from %s (%d)", - node->fullpath, c_size_cells, node->parent->fullpath, - p_size_cells); + FAIL_PROP(c, dti, node, prop, "empty \"ranges\" property but its " + "#size-cells (%d) differs from %s (%d)", + c_size_cells, node->parent->fullpath, + p_size_cells); } else if ((prop->val.len % entrylen) != 0) { - FAIL(c, dti, "\"ranges\" property in %s has invalid length (%d bytes) " - "(parent #address-cells == %d, child #address-cells == %d, " - "#size-cells == %d)", node->fullpath, prop->val.len, - p_addr_cells, c_addr_cells, c_size_cells); + FAIL_PROP(c, dti, node, prop, "\"ranges\" property has invalid length (%d bytes) " + "(parent #address-cells == %d, child #address-cells == %d, " + "#size-cells == %d)", prop->val.len, + p_addr_cells, c_addr_cells, c_size_cells); } } WARNING(ranges_format, check_ranges_format, NULL, &addr_size_cells); @@ -696,41 +773,33 @@ static void check_pci_bridge(struct check *c, struct dt_info *dti, struct node * node->bus = &pci_bus; - if (!strneq(node->name, "pci", node->basenamelen) && - !strneq(node->name, "pcie", node->basenamelen)) - FAIL(c, dti, "Node %s node name is not \"pci\" or \"pcie\"", - node->fullpath); + if (!strprefixeq(node->name, node->basenamelen, "pci") && + !strprefixeq(node->name, node->basenamelen, "pcie")) + FAIL(c, dti, node, "node name is not \"pci\" or \"pcie\""); prop = get_property(node, "ranges"); if (!prop) - FAIL(c, dti, "Node %s missing ranges for PCI bridge (or not a bridge)", - node->fullpath); + FAIL(c, dti, node, "missing ranges for PCI bridge (or not a bridge)"); if (node_addr_cells(node) != 3) - FAIL(c, dti, "Node %s incorrect #address-cells for PCI bridge", - node->fullpath); + FAIL(c, dti, node, "incorrect #address-cells for PCI bridge"); if (node_size_cells(node) != 2) - FAIL(c, dti, "Node %s incorrect #size-cells for PCI bridge", - node->fullpath); + FAIL(c, dti, node, "incorrect #size-cells for PCI bridge"); prop = get_property(node, "bus-range"); if (!prop) { - FAIL(c, dti, "Node %s missing bus-range for PCI bridge", - node->fullpath); + FAIL(c, dti, node, "missing bus-range for PCI bridge"); return; } if (prop->val.len != (sizeof(cell_t) * 2)) { - FAIL(c, dti, "Node %s bus-range must be 2 cells", - node->fullpath); + FAIL_PROP(c, dti, node, prop, "value must be 2 cells"); return; } cells = (cell_t *)prop->val.val; if (fdt32_to_cpu(cells[0]) > fdt32_to_cpu(cells[1])) - FAIL(c, dti, "Node %s bus-range 1st cell must be less than or equal to 2nd cell", - node->fullpath); + FAIL_PROP(c, dti, node, prop, "1st cell must be less than or equal to 2nd cell"); if (fdt32_to_cpu(cells[1]) > 0xff) - FAIL(c, dti, "Node %s bus-range maximum bus number must be less than 256", - node->fullpath); + FAIL_PROP(c, dti, node, prop, "maximum bus number must be less than 256"); } WARNING(pci_bridge, check_pci_bridge, NULL, &device_type_is_string, &addr_size_cells); @@ -760,8 +829,8 @@ static void check_pci_device_bus_num(struct check *c, struct dt_info *dti, struc max_bus = fdt32_to_cpu(cells[0]); } if ((bus_num < min_bus) || (bus_num > max_bus)) - FAIL(c, dti, "Node %s PCI bus number %d out of range, expected (%d - %d)", - node->fullpath, bus_num, min_bus, max_bus); + FAIL_PROP(c, dti, node, prop, "PCI bus number %d out of range, expected (%d - %d)", + bus_num, min_bus, max_bus); } WARNING(pci_device_bus_num, check_pci_device_bus_num, NULL, ®_format, &pci_bridge); @@ -778,25 +847,22 @@ static void check_pci_device_reg(struct check *c, struct dt_info *dti, struct no prop = get_property(node, "reg"); if (!prop) { - FAIL(c, dti, "Node %s missing PCI reg property", node->fullpath); + FAIL(c, dti, node, "missing PCI reg property"); return; } cells = (cell_t *)prop->val.val; if (cells[1] || cells[2]) - FAIL(c, dti, "Node %s PCI reg config space address cells 2 and 3 must be 0", - node->fullpath); + FAIL_PROP(c, dti, node, prop, "PCI reg config space address cells 2 and 3 must be 0"); reg = fdt32_to_cpu(cells[0]); dev = (reg & 0xf800) >> 11; func = (reg & 0x700) >> 8; if (reg & 0xff000000) - FAIL(c, dti, "Node %s PCI reg address is not configuration space", - node->fullpath); + FAIL_PROP(c, dti, node, prop, "PCI reg address is not configuration space"); if (reg & 0x000000ff) - FAIL(c, dti, "Node %s PCI reg config space address register number must be 0", - node->fullpath); + FAIL_PROP(c, dti, node, prop, "PCI reg config space address register number must be 0"); if (func == 0) { snprintf(unit_addr, sizeof(unit_addr), "%x", dev); @@ -808,8 +874,8 @@ static void check_pci_device_reg(struct check *c, struct dt_info *dti, struct no if (streq(unitname, unit_addr)) return; - FAIL(c, dti, "Node %s PCI unit address format error, expected \"%s\"", - node->fullpath, unit_addr); + FAIL(c, dti, node, "PCI unit address format error, expected \"%s\"", + unit_addr); } WARNING(pci_device_reg, check_pci_device_reg, NULL, ®_format, &pci_bridge); @@ -828,7 +894,7 @@ static bool node_is_compatible(struct node *node, const char *compat) for (str = prop->val.val, end = str + prop->val.len; str < end; str += strnlen(str, end - str) + 1) { - if (strneq(str, compat, end - str)) + if (strprefixeq(str, end - str, compat)) return true; } return false; @@ -865,7 +931,7 @@ static void check_simple_bus_reg(struct check *c, struct dt_info *dti, struct no if (!cells) { if (node->parent->parent && !(node->bus == &simple_bus)) - FAIL(c, dti, "Node %s missing or empty reg/ranges property", node->fullpath); + FAIL(c, dti, node, "missing or empty reg/ranges property"); return; } @@ -875,8 +941,8 @@ static void check_simple_bus_reg(struct check *c, struct dt_info *dti, struct no snprintf(unit_addr, sizeof(unit_addr), "%"PRIx64, reg); if (!streq(unitname, unit_addr)) - FAIL(c, dti, "Node %s simple-bus unit address format error, expected \"%s\"", - node->fullpath, unit_addr); + FAIL(c, dti, node, "simple-bus unit address format error, expected \"%s\"", + unit_addr); } WARNING(simple_bus_reg, check_simple_bus_reg, NULL, ®_format, &simple_bus_bridge); @@ -892,14 +958,12 @@ static void check_unit_address_format(struct check *c, struct dt_info *dti, return; if (!strncmp(unitname, "0x", 2)) { - FAIL(c, dti, "Node %s unit name should not have leading \"0x\"", - node->fullpath); + FAIL(c, dti, node, "unit name should not have leading \"0x\""); /* skip over 0x for next test */ unitname += 2; } if (unitname[0] == '0' && isxdigit(unitname[1])) - FAIL(c, dti, "Node %s unit name should not have leading 0s", - node->fullpath); + FAIL(c, dti, node, "unit name should not have leading 0s"); } WARNING(unit_address_format, check_unit_address_format, NULL, &node_name_format, &pci_bridge, &simple_bus_bridge); @@ -922,16 +986,38 @@ static void check_avoid_default_addr_size(struct check *c, struct dt_info *dti, return; if (node->parent->addr_cells == -1) - FAIL(c, dti, "Relying on default #address-cells value for %s", - node->fullpath); + FAIL(c, dti, node, "Relying on default #address-cells value"); if (node->parent->size_cells == -1) - FAIL(c, dti, "Relying on default #size-cells value for %s", - node->fullpath); + FAIL(c, dti, node, "Relying on default #size-cells value"); } WARNING(avoid_default_addr_size, check_avoid_default_addr_size, NULL, &addr_size_cells); +static void check_avoid_unnecessary_addr_size(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + struct node *child; + bool has_reg = false; + + if (!node->parent || node->addr_cells < 0 || node->size_cells < 0) + return; + + if (get_property(node, "ranges") || !node->children) + return; + + for_each_child(node, child) { + prop = get_property(child, "reg"); + if (prop) + has_reg = true; + } + + if (!has_reg) + FAIL(c, dti, node, "unnecessary #address-cells/#size-cells without \"ranges\" or child \"reg\" property"); +} +WARNING(avoid_unnecessary_addr_size, check_avoid_unnecessary_addr_size, NULL, &avoid_default_addr_size); + static void check_obsolete_chosen_interrupt_controller(struct check *c, struct dt_info *dti, struct node *node) @@ -950,12 +1036,61 @@ static void check_obsolete_chosen_interrupt_controller(struct check *c, prop = get_property(chosen, "interrupt-controller"); if (prop) - FAIL(c, dti, "/chosen has obsolete \"interrupt-controller\" " - "property"); + FAIL_PROP(c, dti, node, prop, + "/chosen has obsolete \"interrupt-controller\" property"); } WARNING(obsolete_chosen_interrupt_controller, check_obsolete_chosen_interrupt_controller, NULL); +static void check_chosen_node_is_root(struct check *c, struct dt_info *dti, + struct node *node) +{ + if (!streq(node->name, "chosen")) + return; + + if (node->parent != dti->dt) + FAIL(c, dti, node, "chosen node must be at root node"); +} +WARNING(chosen_node_is_root, check_chosen_node_is_root, NULL); + +static void check_chosen_node_bootargs(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + if (!streq(node->name, "chosen")) + return; + + prop = get_property(node, "bootargs"); + if (!prop) + return; + + c->data = prop->name; + check_is_string(c, dti, node); +} +WARNING(chosen_node_bootargs, check_chosen_node_bootargs, NULL); + +static void check_chosen_node_stdout_path(struct check *c, struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + if (!streq(node->name, "chosen")) + return; + + prop = get_property(node, "stdout-path"); + if (!prop) { + prop = get_property(node, "linux,stdout-path"); + if (!prop) + return; + FAIL_PROP(c, dti, node, prop, "Use 'stdout-path' instead"); + } + + c->data = prop->name; + check_is_string(c, dti, node); +} +WARNING(chosen_node_stdout_path, check_chosen_node_stdout_path, NULL); + struct provider { const char *prop_name; const char *cell_name; @@ -972,8 +1107,9 @@ static void check_property_phandle_args(struct check *c, int cell, cellsize = 0; if (prop->val.len % sizeof(cell_t)) { - FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %zu in node %s", - prop->name, prop->val.len, sizeof(cell_t), node->fullpath); + FAIL_PROP(c, dti, node, prop, + "property size (%d) is invalid, expected multiple of %zu", + prop->val.len, sizeof(cell_t)); return; } @@ -1004,14 +1140,16 @@ static void check_property_phandle_args(struct check *c, break; } if (!m) - FAIL(c, dti, "Property '%s', cell %d is not a phandle reference in %s", - prop->name, cell, node->fullpath); + FAIL_PROP(c, dti, node, prop, + "cell %d is not a phandle reference", + cell); } provider_node = get_node_by_phandle(root, phandle); if (!provider_node) { - FAIL(c, dti, "Could not get phandle node for %s:%s(cell %d)", - node->fullpath, prop->name, cell); + FAIL_PROP(c, dti, node, prop, + "Could not get phandle node for (cell %d)", + cell); break; } @@ -1021,16 +1159,17 @@ static void check_property_phandle_args(struct check *c, } else if (provider->optional) { cellsize = 0; } else { - FAIL(c, dti, "Missing property '%s' in node %s or bad phandle (referred from %s:%s[%d])", + FAIL(c, dti, node, "Missing property '%s' in node %s or bad phandle (referred from %s[%d])", provider->cell_name, provider_node->fullpath, - node->fullpath, prop->name, cell); + prop->name, cell); break; } if (prop->val.len < ((cell + cellsize + 1) * sizeof(cell_t))) { - FAIL(c, dti, "%s property size (%d) too small for cell size %d in %s", - prop->name, prop->val.len, cellsize, node->fullpath); + FAIL_PROP(c, dti, node, prop, + "property size (%d) too small for cell size %d", + prop->val.len, cellsize); } } } @@ -1066,7 +1205,7 @@ WARNING_PROPERTY_PHANDLE_CELLS(phys, "phys", "#phy-cells"); WARNING_PROPERTY_PHANDLE_CELLS(power_domains, "power-domains", "#power-domain-cells"); WARNING_PROPERTY_PHANDLE_CELLS(pwms, "pwms", "#pwm-cells"); WARNING_PROPERTY_PHANDLE_CELLS(resets, "resets", "#reset-cells"); -WARNING_PROPERTY_PHANDLE_CELLS(sound_dais, "sound-dais", "#sound-dai-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(sound_dai, "sound-dai", "#sound-dai-cells"); WARNING_PROPERTY_PHANDLE_CELLS(thermal_sensors, "thermal-sensors", "#thermal-sensor-cells"); static bool prop_is_gpio(struct property *prop) @@ -1132,8 +1271,8 @@ static void check_deprecated_gpio_property(struct check *c, if (!streq(str, "gpio")) continue; - FAIL(c, dti, "'[*-]gpio' is deprecated, use '[*-]gpios' instead for %s:%s", - node->fullpath, prop->name); + FAIL_PROP(c, dti, node, prop, + "'[*-]gpio' is deprecated, use '[*-]gpios' instead"); } } @@ -1167,9 +1306,8 @@ static void check_interrupts_property(struct check *c, return; if (irq_prop->val.len % sizeof(cell_t)) - FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %zu in node %s", - irq_prop->name, irq_prop->val.len, sizeof(cell_t), - node->fullpath); + FAIL_PROP(c, dti, node, irq_prop, "size (%d) is invalid, expected multiple of %zu", + irq_prop->val.len, sizeof(cell_t)); while (parent && !prop) { if (parent != node && node_is_interrupt_provider(parent)) { @@ -1187,14 +1325,12 @@ static void check_interrupts_property(struct check *c, irq_node = get_node_by_phandle(root, phandle); if (!irq_node) { - FAIL(c, dti, "Bad interrupt-parent phandle for %s", - node->fullpath); + FAIL_PROP(c, dti, parent, prop, "Bad phandle"); return; } if (!node_is_interrupt_provider(irq_node)) - FAIL(c, dti, - "Missing interrupt-controller or interrupt-map property in %s", - irq_node->fullpath); + FAIL(c, dti, irq_node, + "Missing interrupt-controller or interrupt-map property"); break; } @@ -1203,23 +1339,21 @@ static void check_interrupts_property(struct check *c, } if (!irq_node) { - FAIL(c, dti, "Missing interrupt-parent for %s", node->fullpath); + FAIL(c, dti, node, "Missing interrupt-parent"); return; } prop = get_property(irq_node, "#interrupt-cells"); if (!prop) { - FAIL(c, dti, "Missing #interrupt-cells in interrupt-parent %s", - irq_node->fullpath); + FAIL(c, dti, irq_node, "Missing #interrupt-cells in interrupt-parent"); return; } irq_cells = propval_cell(prop); if (irq_prop->val.len % (irq_cells * sizeof(cell_t))) { - FAIL(c, dti, - "interrupts size is (%d), expected multiple of %d in %s", - irq_prop->val.len, (int)(irq_cells * sizeof(cell_t)), - node->fullpath); + FAIL_PROP(c, dti, node, prop, + "size is (%d), expected multiple of %d", + irq_prop->val.len, (int)(irq_cells * sizeof(cell_t))); } } WARNING(interrupts_property, check_interrupts_property, &phandle_references); @@ -1236,6 +1370,9 @@ static struct check *check_table[] = { &address_cells_is_cell, &size_cells_is_cell, &interrupt_cells_is_cell, &device_type_is_string, &model_is_string, &status_is_string, + &label_is_string, + + &compatible_is_string_list, &names_is_string_list, &property_name_chars_strict, &node_name_chars_strict, @@ -1253,7 +1390,9 @@ static struct check *check_table[] = { &simple_bus_reg, &avoid_default_addr_size, + &avoid_unnecessary_addr_size, &obsolete_chosen_interrupt_controller, + &chosen_node_is_root, &chosen_node_bootargs, &chosen_node_stdout_path, &clocks_property, &cooling_device_property, @@ -1269,13 +1408,15 @@ static struct check *check_table[] = { &power_domains_property, &pwms_property, &resets_property, - &sound_dais_property, + &sound_dai_property, &thermal_sensors_property, &deprecated_gpio_property, &gpios_property, &interrupts_property, + &alias_paths, + &always_fail, }; diff --git a/scripts/dtc/dtc-parser.y b/scripts/dtc/dtc-parser.y index affc81a8f9ab..44af170abfea 100644 --- a/scripts/dtc/dtc-parser.y +++ b/scripts/dtc/dtc-parser.y @@ -166,7 +166,17 @@ devicetree: { $$ = merge_nodes($1, $3); } - + | DT_REF nodedef + { + /* + * We rely on the rule being always: + * versioninfo plugindecl memreserves devicetree + * so $-1 is what we want (plugindecl) + */ + if (!($-1 & DTSF_PLUGIN)) + ERROR(&@2, "Label or path %s not found", $1); + $$ = add_orphan_node(name_node(build_node(NULL, NULL), ""), $2, $1); + } | devicetree DT_LABEL DT_REF nodedef { struct node *target = get_node_by_ref($1, $3); @@ -209,11 +219,6 @@ devicetree: $$ = $1; } - | /* empty */ - { - /* build empty node */ - $$ = name_node(build_node(NULL, NULL), ""); - } ; nodedef: diff --git a/scripts/dtc/dtc.c b/scripts/dtc/dtc.c index 5ed873c72ad1..c36994e6eac5 100644 --- a/scripts/dtc/dtc.c +++ b/scripts/dtc/dtc.c @@ -59,8 +59,6 @@ static void fill_fullpaths(struct node *tree, const char *prefix) } /* Usage related data. */ -#define FDT_VERSION(version) _FDT_VERSION(version) -#define _FDT_VERSION(version) #version static const char usage_synopsis[] = "dtc [options] "; static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:a:fb:i:H:sW:E:@Ahv"; static struct option const usage_long_opts[] = { @@ -98,7 +96,7 @@ static const char * const usage_opts_help[] = { "\t\tdts - device tree source text\n" "\t\tdtb - device tree blob\n" "\t\tasm - assembler source", - "\n\tBlob version to produce, defaults to "FDT_VERSION(DEFAULT_FDT_VERSION)" (for dtb and asm output)", + "\n\tBlob version to produce, defaults to "stringify(DEFAULT_FDT_VERSION)" (for dtb and asm output)", "\n\tOutput dependency file", "\n\tMake space for reserve map entries (for dtb and asm output)", "\n\tMake the blob at least long (extra space)", @@ -319,13 +317,14 @@ int main(int argc, char *argv[]) dti->boot_cpuid_phys = cmdline_boot_cpuid; fill_fullpaths(dti->dt, ""); - process_checks(force, dti); /* on a plugin, generate by default */ if (dti->dtsflags & DTSF_PLUGIN) { generate_fixups = 1; } + process_checks(force, dti); + if (auto_label_aliases) generate_label_tree(dti, "aliases", false); diff --git a/scripts/dtc/dtc.h b/scripts/dtc/dtc.h index 35cf926cc14a..3b18a42b866e 100644 --- a/scripts/dtc/dtc.h +++ b/scripts/dtc/dtc.h @@ -1,5 +1,5 @@ -#ifndef _DTC_H -#define _DTC_H +#ifndef DTC_H +#define DTC_H /* * (C) Copyright David Gibson , IBM Corporation. 2005. @@ -67,7 +67,8 @@ typedef uint32_t cell_t; #define streq(a, b) (strcmp((a), (b)) == 0) -#define strneq(a, b, n) (strncmp((a), (b), (n)) == 0) +#define strstarts(s, prefix) (strncmp((s), (prefix), strlen(prefix)) == 0) +#define strprefixeq(a, n, b) (strlen(b) == (n) && (memcmp(a, b, n) == 0)) #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) @@ -203,7 +204,7 @@ struct node *build_node_delete(void); struct node *name_node(struct node *node, char *name); struct node *chain_node(struct node *first, struct node *list); struct node *merge_nodes(struct node *old_node, struct node *new_node); -void add_orphan_node(struct node *old_node, struct node *new_node, char *ref); +struct node *add_orphan_node(struct node *old_node, struct node *new_node, char *ref); void add_property(struct node *node, struct property *prop); void delete_property_by_name(struct node *node, char *name); @@ -289,4 +290,4 @@ struct dt_info *dt_from_source(const char *f); struct dt_info *dt_from_fs(const char *dirname); -#endif /* _DTC_H */ +#endif /* DTC_H */ diff --git a/scripts/dtc/flattree.c b/scripts/dtc/flattree.c index fcf71541d8a7..8d268fb785db 100644 --- a/scripts/dtc/flattree.c +++ b/scripts/dtc/flattree.c @@ -731,7 +731,7 @@ static char *nodename_from_path(const char *ppath, const char *cpath) plen = strlen(ppath); - if (!strneq(ppath, cpath, plen)) + if (!strstarts(cpath, ppath)) die("Path \"%s\" is not valid as a child of \"%s\"\n", cpath, ppath); diff --git a/scripts/dtc/libfdt/fdt.c b/scripts/dtc/libfdt/fdt.c index 22286a1aaeaf..7855a1787763 100644 --- a/scripts/dtc/libfdt/fdt.c +++ b/scripts/dtc/libfdt/fdt.c @@ -88,7 +88,7 @@ const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len) || ((offset + len) > fdt_size_dt_struct(fdt))) return NULL; - return _fdt_offset_ptr(fdt, offset); + return fdt_offset_ptr_(fdt, offset); } uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset) @@ -123,6 +123,9 @@ uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset) /* skip-name offset, length and value */ offset += sizeof(struct fdt_property) - FDT_TAGSIZE + fdt32_to_cpu(*lenp); + if (fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 && + ((offset - fdt32_to_cpu(*lenp)) % 8) != 0) + offset += 4; break; case FDT_END: @@ -141,7 +144,7 @@ uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset) return tag; } -int _fdt_check_node_offset(const void *fdt, int offset) +int fdt_check_node_offset_(const void *fdt, int offset) { if ((offset < 0) || (offset % FDT_TAGSIZE) || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE)) @@ -150,7 +153,7 @@ int _fdt_check_node_offset(const void *fdt, int offset) return offset; } -int _fdt_check_prop_offset(const void *fdt, int offset) +int fdt_check_prop_offset_(const void *fdt, int offset) { if ((offset < 0) || (offset % FDT_TAGSIZE) || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP)) @@ -165,7 +168,7 @@ int fdt_next_node(const void *fdt, int offset, int *depth) uint32_t tag; if (offset >= 0) - if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0) + if ((nextoffset = fdt_check_node_offset_(fdt, offset)) < 0) return nextoffset; do { @@ -227,7 +230,7 @@ int fdt_next_subnode(const void *fdt, int offset) return offset; } -const char *_fdt_find_string(const char *strtab, int tabsize, const char *s) +const char *fdt_find_string_(const char *strtab, int tabsize, const char *s) { int len = strlen(s) + 1; const char *last = strtab + tabsize - len; diff --git a/scripts/dtc/libfdt/fdt.h b/scripts/dtc/libfdt/fdt.h index 526aedb51556..74961f9026d1 100644 --- a/scripts/dtc/libfdt/fdt.h +++ b/scripts/dtc/libfdt/fdt.h @@ -1,5 +1,5 @@ -#ifndef _FDT_H -#define _FDT_H +#ifndef FDT_H +#define FDT_H /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. @@ -108,4 +108,4 @@ struct fdt_property { #define FDT_V16_SIZE FDT_V3_SIZE #define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) -#endif /* _FDT_H */ +#endif /* FDT_H */ diff --git a/scripts/dtc/libfdt/fdt_overlay.c b/scripts/dtc/libfdt/fdt_overlay.c index bd81241e6658..bf75388ec9a2 100644 --- a/scripts/dtc/libfdt/fdt_overlay.c +++ b/scripts/dtc/libfdt/fdt_overlay.c @@ -1,3 +1,54 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2016 Free Electrons + * Copyright (C) 2016 NextThing Co. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include "libfdt_env.h" #include diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c index 08de2cce674d..dfb3236da388 100644 --- a/scripts/dtc/libfdt/fdt_ro.c +++ b/scripts/dtc/libfdt/fdt_ro.c @@ -55,12 +55,13 @@ #include "libfdt_internal.h" -static int _fdt_nodename_eq(const void *fdt, int offset, +static int fdt_nodename_eq_(const void *fdt, int offset, const char *s, int len) { - const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1); + int olen; + const char *p = fdt_get_name(fdt, offset, &olen); - if (!p) + if (!p || olen < len) /* short match */ return 0; @@ -80,7 +81,7 @@ const char *fdt_string(const void *fdt, int stroffset) return (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset; } -static int _fdt_string_eq(const void *fdt, int stroffset, +static int fdt_string_eq_(const void *fdt, int stroffset, const char *s, int len) { const char *p = fdt_string(fdt, stroffset); @@ -117,8 +118,8 @@ uint32_t fdt_get_max_phandle(const void *fdt) int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) { FDT_CHECK_HEADER(fdt); - *address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address); - *size = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->size); + *address = fdt64_to_cpu(fdt_mem_rsv_(fdt, n)->address); + *size = fdt64_to_cpu(fdt_mem_rsv_(fdt, n)->size); return 0; } @@ -126,12 +127,12 @@ int fdt_num_mem_rsv(const void *fdt) { int i = 0; - while (fdt64_to_cpu(_fdt_mem_rsv(fdt, i)->size) != 0) + while (fdt64_to_cpu(fdt_mem_rsv_(fdt, i)->size) != 0) i++; return i; } -static int _nextprop(const void *fdt, int offset) +static int nextprop_(const void *fdt, int offset) { uint32_t tag; int nextoffset; @@ -166,7 +167,7 @@ int fdt_subnode_offset_namelen(const void *fdt, int offset, (offset >= 0) && (depth >= 0); offset = fdt_next_node(fdt, offset, &depth)) if ((depth == 1) - && _fdt_nodename_eq(fdt, offset, name, namelen)) + && fdt_nodename_eq_(fdt, offset, name, namelen)) return offset; if (depth < 0) @@ -232,17 +233,35 @@ int fdt_path_offset(const void *fdt, const char *path) const char *fdt_get_name(const void *fdt, int nodeoffset, int *len) { - const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset); + const struct fdt_node_header *nh = fdt_offset_ptr_(fdt, nodeoffset); + const char *nameptr; int err; if (((err = fdt_check_header(fdt)) != 0) - || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0)) + || ((err = fdt_check_node_offset_(fdt, nodeoffset)) < 0)) goto fail; + nameptr = nh->name; + + if (fdt_version(fdt) < 0x10) { + /* + * For old FDT versions, match the naming conventions of V16: + * give only the leaf name (after all /). The actual tree + * contents are loosely checked. + */ + const char *leaf; + leaf = strrchr(nameptr, '/'); + if (leaf == NULL) { + err = -FDT_ERR_BADSTRUCTURE; + goto fail; + } + nameptr = leaf+1; + } + if (len) - *len = strlen(nh->name); + *len = strlen(nameptr); - return nh->name; + return nameptr; fail: if (len) @@ -254,34 +273,34 @@ int fdt_first_property_offset(const void *fdt, int nodeoffset) { int offset; - if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0) + if ((offset = fdt_check_node_offset_(fdt, nodeoffset)) < 0) return offset; - return _nextprop(fdt, offset); + return nextprop_(fdt, offset); } int fdt_next_property_offset(const void *fdt, int offset) { - if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0) + if ((offset = fdt_check_prop_offset_(fdt, offset)) < 0) return offset; - return _nextprop(fdt, offset); + return nextprop_(fdt, offset); } -const struct fdt_property *fdt_get_property_by_offset(const void *fdt, - int offset, - int *lenp) +static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt, + int offset, + int *lenp) { int err; const struct fdt_property *prop; - if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) { + if ((err = fdt_check_prop_offset_(fdt, offset)) < 0) { if (lenp) *lenp = err; return NULL; } - prop = _fdt_offset_ptr(fdt, offset); + prop = fdt_offset_ptr_(fdt, offset); if (lenp) *lenp = fdt32_to_cpu(prop->len); @@ -289,23 +308,44 @@ const struct fdt_property *fdt_get_property_by_offset(const void *fdt, return prop; } -const struct fdt_property *fdt_get_property_namelen(const void *fdt, - int offset, - const char *name, - int namelen, int *lenp) +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp) +{ + /* Prior to version 16, properties may need realignment + * and this API does not work. fdt_getprop_*() will, however. */ + + if (fdt_version(fdt) < 0x10) { + if (lenp) + *lenp = -FDT_ERR_BADVERSION; + return NULL; + } + + return fdt_get_property_by_offset_(fdt, offset, lenp); +} + +static const struct fdt_property *fdt_get_property_namelen_(const void *fdt, + int offset, + const char *name, + int namelen, + int *lenp, + int *poffset) { for (offset = fdt_first_property_offset(fdt, offset); (offset >= 0); (offset = fdt_next_property_offset(fdt, offset))) { const struct fdt_property *prop; - if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) { + if (!(prop = fdt_get_property_by_offset_(fdt, offset, lenp))) { offset = -FDT_ERR_INTERNAL; break; } - if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff), - name, namelen)) + if (fdt_string_eq_(fdt, fdt32_to_cpu(prop->nameoff), + name, namelen)) { + if (poffset) + *poffset = offset; return prop; + } } if (lenp) @@ -313,6 +353,25 @@ const struct fdt_property *fdt_get_property_namelen(const void *fdt, return NULL; } + +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int offset, + const char *name, + int namelen, int *lenp) +{ + /* Prior to version 16, properties may need realignment + * and this API does not work. fdt_getprop_*() will, however. */ + if (fdt_version(fdt) < 0x10) { + if (lenp) + *lenp = -FDT_ERR_BADVERSION; + return NULL; + } + + return fdt_get_property_namelen_(fdt, offset, name, namelen, lenp, + NULL); +} + + const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, const char *name, int *lenp) @@ -324,12 +383,18 @@ const struct fdt_property *fdt_get_property(const void *fdt, const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, const char *name, int namelen, int *lenp) { + int poffset; const struct fdt_property *prop; - prop = fdt_get_property_namelen(fdt, nodeoffset, name, namelen, lenp); + prop = fdt_get_property_namelen_(fdt, nodeoffset, name, namelen, lenp, + &poffset); if (!prop) return NULL; + /* Handle realignment */ + if (fdt_version(fdt) < 0x10 && (poffset + sizeof(*prop)) % 8 && + fdt32_to_cpu(prop->len) >= 8) + return prop->data + 4; return prop->data; } @@ -338,11 +403,16 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, { const struct fdt_property *prop; - prop = fdt_get_property_by_offset(fdt, offset, lenp); + prop = fdt_get_property_by_offset_(fdt, offset, lenp); if (!prop) return NULL; if (namep) *namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); + + /* Handle realignment */ + if (fdt_version(fdt) < 0x10 && (offset + sizeof(*prop)) % 8 && + fdt32_to_cpu(prop->len) >= 8) + return prop->data + 4; return prop->data; } diff --git a/scripts/dtc/libfdt/fdt_rw.c b/scripts/dtc/libfdt/fdt_rw.c index 5c3a2bb0bc6b..9b829051e444 100644 --- a/scripts/dtc/libfdt/fdt_rw.c +++ b/scripts/dtc/libfdt/fdt_rw.c @@ -55,8 +55,8 @@ #include "libfdt_internal.h" -static int _fdt_blocks_misordered(const void *fdt, - int mem_rsv_size, int struct_size) +static int fdt_blocks_misordered_(const void *fdt, + int mem_rsv_size, int struct_size) { return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8)) || (fdt_off_dt_struct(fdt) < @@ -67,13 +67,13 @@ static int _fdt_blocks_misordered(const void *fdt, (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt))); } -static int _fdt_rw_check_header(void *fdt) +static int fdt_rw_check_header_(void *fdt) { FDT_CHECK_HEADER(fdt); if (fdt_version(fdt) < 17) return -FDT_ERR_BADVERSION; - if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry), + if (fdt_blocks_misordered_(fdt, sizeof(struct fdt_reserve_entry), fdt_size_dt_struct(fdt))) return -FDT_ERR_BADLAYOUT; if (fdt_version(fdt) > 17) @@ -84,20 +84,20 @@ static int _fdt_rw_check_header(void *fdt) #define FDT_RW_CHECK_HEADER(fdt) \ { \ - int __err; \ - if ((__err = _fdt_rw_check_header(fdt)) != 0) \ - return __err; \ + int err_; \ + if ((err_ = fdt_rw_check_header_(fdt)) != 0) \ + return err_; \ } -static inline int _fdt_data_size(void *fdt) +static inline int fdt_data_size_(void *fdt) { return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); } -static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen) +static int fdt_splice_(void *fdt, void *splicepoint, int oldlen, int newlen) { char *p = splicepoint; - char *end = (char *)fdt + _fdt_data_size(fdt); + char *end = (char *)fdt + fdt_data_size_(fdt); if (((p + oldlen) < p) || ((p + oldlen) > end)) return -FDT_ERR_BADOFFSET; @@ -109,12 +109,12 @@ static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen) return 0; } -static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p, +static int fdt_splice_mem_rsv_(void *fdt, struct fdt_reserve_entry *p, int oldn, int newn) { int delta = (newn - oldn) * sizeof(*p); int err; - err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p)); + err = fdt_splice_(fdt, p, oldn * sizeof(*p), newn * sizeof(*p)); if (err) return err; fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta); @@ -122,13 +122,13 @@ static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p, return 0; } -static int _fdt_splice_struct(void *fdt, void *p, +static int fdt_splice_struct_(void *fdt, void *p, int oldlen, int newlen) { int delta = newlen - oldlen; int err; - if ((err = _fdt_splice(fdt, p, oldlen, newlen))) + if ((err = fdt_splice_(fdt, p, oldlen, newlen))) return err; fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta); @@ -136,20 +136,20 @@ static int _fdt_splice_struct(void *fdt, void *p, return 0; } -static int _fdt_splice_string(void *fdt, int newlen) +static int fdt_splice_string_(void *fdt, int newlen) { void *p = (char *)fdt + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); int err; - if ((err = _fdt_splice(fdt, p, 0, newlen))) + if ((err = fdt_splice_(fdt, p, 0, newlen))) return err; fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen); return 0; } -static int _fdt_find_add_string(void *fdt, const char *s) +static int fdt_find_add_string_(void *fdt, const char *s) { char *strtab = (char *)fdt + fdt_off_dt_strings(fdt); const char *p; @@ -157,13 +157,13 @@ static int _fdt_find_add_string(void *fdt, const char *s) int len = strlen(s) + 1; int err; - p = _fdt_find_string(strtab, fdt_size_dt_strings(fdt), s); + p = fdt_find_string_(strtab, fdt_size_dt_strings(fdt), s); if (p) /* found it */ return (p - strtab); new = strtab + fdt_size_dt_strings(fdt); - err = _fdt_splice_string(fdt, len); + err = fdt_splice_string_(fdt, len); if (err) return err; @@ -178,8 +178,8 @@ int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size) FDT_RW_CHECK_HEADER(fdt); - re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt)); - err = _fdt_splice_mem_rsv(fdt, re, 0, 1); + re = fdt_mem_rsv_w_(fdt, fdt_num_mem_rsv(fdt)); + err = fdt_splice_mem_rsv_(fdt, re, 0, 1); if (err) return err; @@ -190,17 +190,17 @@ int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size) int fdt_del_mem_rsv(void *fdt, int n) { - struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n); + struct fdt_reserve_entry *re = fdt_mem_rsv_w_(fdt, n); FDT_RW_CHECK_HEADER(fdt); if (n >= fdt_num_mem_rsv(fdt)) return -FDT_ERR_NOTFOUND; - return _fdt_splice_mem_rsv(fdt, re, 1, 0); + return fdt_splice_mem_rsv_(fdt, re, 1, 0); } -static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name, +static int fdt_resize_property_(void *fdt, int nodeoffset, const char *name, int len, struct fdt_property **prop) { int oldlen; @@ -210,7 +210,7 @@ static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name, if (!*prop) return oldlen; - if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen), + if ((err = fdt_splice_struct_(fdt, (*prop)->data, FDT_TAGALIGN(oldlen), FDT_TAGALIGN(len)))) return err; @@ -218,7 +218,7 @@ static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name, return 0; } -static int _fdt_add_property(void *fdt, int nodeoffset, const char *name, +static int fdt_add_property_(void *fdt, int nodeoffset, const char *name, int len, struct fdt_property **prop) { int proplen; @@ -226,17 +226,17 @@ static int _fdt_add_property(void *fdt, int nodeoffset, const char *name, int namestroff; int err; - if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0) + if ((nextoffset = fdt_check_node_offset_(fdt, nodeoffset)) < 0) return nextoffset; - namestroff = _fdt_find_add_string(fdt, name); + namestroff = fdt_find_add_string_(fdt, name); if (namestroff < 0) return namestroff; - *prop = _fdt_offset_ptr_w(fdt, nextoffset); + *prop = fdt_offset_ptr_w_(fdt, nextoffset); proplen = sizeof(**prop) + FDT_TAGALIGN(len); - err = _fdt_splice_struct(fdt, *prop, 0, proplen); + err = fdt_splice_struct_(fdt, *prop, 0, proplen); if (err) return err; @@ -260,7 +260,7 @@ int fdt_set_name(void *fdt, int nodeoffset, const char *name) newlen = strlen(name); - err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1), + err = fdt_splice_struct_(fdt, namep, FDT_TAGALIGN(oldlen+1), FDT_TAGALIGN(newlen+1)); if (err) return err; @@ -277,9 +277,9 @@ int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, FDT_RW_CHECK_HEADER(fdt); - err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop); + err = fdt_resize_property_(fdt, nodeoffset, name, len, &prop); if (err == -FDT_ERR_NOTFOUND) - err = _fdt_add_property(fdt, nodeoffset, name, len, &prop); + err = fdt_add_property_(fdt, nodeoffset, name, len, &prop); if (err) return err; @@ -313,7 +313,7 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name, prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); if (prop) { newlen = len + oldlen; - err = _fdt_splice_struct(fdt, prop->data, + err = fdt_splice_struct_(fdt, prop->data, FDT_TAGALIGN(oldlen), FDT_TAGALIGN(newlen)); if (err) @@ -321,7 +321,7 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name, prop->len = cpu_to_fdt32(newlen); memcpy(prop->data + oldlen, val, len); } else { - err = _fdt_add_property(fdt, nodeoffset, name, len, &prop); + err = fdt_add_property_(fdt, nodeoffset, name, len, &prop); if (err) return err; memcpy(prop->data, val, len); @@ -341,7 +341,7 @@ int fdt_delprop(void *fdt, int nodeoffset, const char *name) return len; proplen = sizeof(*prop) + FDT_TAGALIGN(len); - return _fdt_splice_struct(fdt, prop, proplen, 0); + return fdt_splice_struct_(fdt, prop, proplen, 0); } int fdt_add_subnode_namelen(void *fdt, int parentoffset, @@ -369,10 +369,10 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, tag = fdt_next_tag(fdt, offset, &nextoffset); } while ((tag == FDT_PROP) || (tag == FDT_NOP)); - nh = _fdt_offset_ptr_w(fdt, offset); + nh = fdt_offset_ptr_w_(fdt, offset); nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE; - err = _fdt_splice_struct(fdt, nh, 0, nodelen); + err = fdt_splice_struct_(fdt, nh, 0, nodelen); if (err) return err; @@ -396,15 +396,15 @@ int fdt_del_node(void *fdt, int nodeoffset) FDT_RW_CHECK_HEADER(fdt); - endoffset = _fdt_node_end_offset(fdt, nodeoffset); + endoffset = fdt_node_end_offset_(fdt, nodeoffset); if (endoffset < 0) return endoffset; - return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset), + return fdt_splice_struct_(fdt, fdt_offset_ptr_w_(fdt, nodeoffset), endoffset - nodeoffset, 0); } -static void _fdt_packblocks(const char *old, char *new, +static void fdt_packblocks_(const char *old, char *new, int mem_rsv_size, int struct_size) { int mem_rsv_off, struct_off, strings_off; @@ -450,7 +450,7 @@ int fdt_open_into(const void *fdt, void *buf, int bufsize) return struct_size; } - if (!_fdt_blocks_misordered(fdt, mem_rsv_size, struct_size)) { + if (!fdt_blocks_misordered_(fdt, mem_rsv_size, struct_size)) { /* no further work necessary */ err = fdt_move(fdt, buf, bufsize); if (err) @@ -478,7 +478,7 @@ int fdt_open_into(const void *fdt, void *buf, int bufsize) return -FDT_ERR_NOSPACE; } - _fdt_packblocks(fdt, tmp, mem_rsv_size, struct_size); + fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size); memmove(buf, tmp, newsize); fdt_set_magic(buf, FDT_MAGIC); @@ -498,8 +498,8 @@ int fdt_pack(void *fdt) mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) * sizeof(struct fdt_reserve_entry); - _fdt_packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); - fdt_set_totalsize(fdt, _fdt_data_size(fdt)); + fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); + fdt_set_totalsize(fdt, fdt_data_size_(fdt)); return 0; } diff --git a/scripts/dtc/libfdt/fdt_sw.c b/scripts/dtc/libfdt/fdt_sw.c index 2bd15e7aef87..6d33cc29d022 100644 --- a/scripts/dtc/libfdt/fdt_sw.c +++ b/scripts/dtc/libfdt/fdt_sw.c @@ -55,7 +55,7 @@ #include "libfdt_internal.h" -static int _fdt_sw_check_header(void *fdt) +static int fdt_sw_check_header_(void *fdt) { if (fdt_magic(fdt) != FDT_SW_MAGIC) return -FDT_ERR_BADMAGIC; @@ -66,11 +66,11 @@ static int _fdt_sw_check_header(void *fdt) #define FDT_SW_CHECK_HEADER(fdt) \ { \ int err; \ - if ((err = _fdt_sw_check_header(fdt)) != 0) \ + if ((err = fdt_sw_check_header_(fdt)) != 0) \ return err; \ } -static void *_fdt_grab_space(void *fdt, size_t len) +static void *fdt_grab_space_(void *fdt, size_t len) { int offset = fdt_size_dt_struct(fdt); int spaceleft; @@ -82,7 +82,7 @@ static void *_fdt_grab_space(void *fdt, size_t len) return NULL; fdt_set_size_dt_struct(fdt, offset + len); - return _fdt_offset_ptr_w(fdt, offset); + return fdt_offset_ptr_w_(fdt, offset); } int fdt_create(void *buf, int bufsize) @@ -174,7 +174,7 @@ int fdt_begin_node(void *fdt, const char *name) FDT_SW_CHECK_HEADER(fdt); - nh = _fdt_grab_space(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen)); + nh = fdt_grab_space_(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen)); if (! nh) return -FDT_ERR_NOSPACE; @@ -189,7 +189,7 @@ int fdt_end_node(void *fdt) FDT_SW_CHECK_HEADER(fdt); - en = _fdt_grab_space(fdt, FDT_TAGSIZE); + en = fdt_grab_space_(fdt, FDT_TAGSIZE); if (! en) return -FDT_ERR_NOSPACE; @@ -197,7 +197,7 @@ int fdt_end_node(void *fdt) return 0; } -static int _fdt_find_add_string(void *fdt, const char *s) +static int fdt_find_add_string_(void *fdt, const char *s) { char *strtab = (char *)fdt + fdt_totalsize(fdt); const char *p; @@ -205,7 +205,7 @@ static int _fdt_find_add_string(void *fdt, const char *s) int len = strlen(s) + 1; int struct_top, offset; - p = _fdt_find_string(strtab - strtabsize, strtabsize, s); + p = fdt_find_string_(strtab - strtabsize, strtabsize, s); if (p) return p - strtab; @@ -227,11 +227,11 @@ int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp) FDT_SW_CHECK_HEADER(fdt); - nameoff = _fdt_find_add_string(fdt, name); + nameoff = fdt_find_add_string_(fdt, name); if (nameoff == 0) return -FDT_ERR_NOSPACE; - prop = _fdt_grab_space(fdt, sizeof(*prop) + FDT_TAGALIGN(len)); + prop = fdt_grab_space_(fdt, sizeof(*prop) + FDT_TAGALIGN(len)); if (! prop) return -FDT_ERR_NOSPACE; @@ -265,7 +265,7 @@ int fdt_finish(void *fdt) FDT_SW_CHECK_HEADER(fdt); /* Add terminator */ - end = _fdt_grab_space(fdt, sizeof(*end)); + end = fdt_grab_space_(fdt, sizeof(*end)); if (! end) return -FDT_ERR_NOSPACE; *end = cpu_to_fdt32(FDT_END); @@ -281,7 +281,7 @@ int fdt_finish(void *fdt) while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) { if (tag == FDT_PROP) { struct fdt_property *prop = - _fdt_offset_ptr_w(fdt, offset); + fdt_offset_ptr_w_(fdt, offset); int nameoff; nameoff = fdt32_to_cpu(prop->nameoff); diff --git a/scripts/dtc/libfdt/fdt_wip.c b/scripts/dtc/libfdt/fdt_wip.c index 5e859198622b..534c1cbbb2f3 100644 --- a/scripts/dtc/libfdt/fdt_wip.c +++ b/scripts/dtc/libfdt/fdt_wip.c @@ -93,7 +93,7 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, val, len); } -static void _fdt_nop_region(void *start, int len) +static void fdt_nop_region_(void *start, int len) { fdt32_t *p; @@ -110,12 +110,12 @@ int fdt_nop_property(void *fdt, int nodeoffset, const char *name) if (!prop) return len; - _fdt_nop_region(prop, len + sizeof(*prop)); + fdt_nop_region_(prop, len + sizeof(*prop)); return 0; } -int _fdt_node_end_offset(void *fdt, int offset) +int fdt_node_end_offset_(void *fdt, int offset) { int depth = 0; @@ -129,11 +129,11 @@ int fdt_nop_node(void *fdt, int nodeoffset) { int endoffset; - endoffset = _fdt_node_end_offset(fdt, nodeoffset); + endoffset = fdt_node_end_offset_(fdt, nodeoffset); if (endoffset < 0) return endoffset; - _fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0), + fdt_nop_region_(fdt_offset_ptr_w(fdt, nodeoffset, 0), endoffset - nodeoffset); return 0; } diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h index 7f83023ee109..1e27780e1185 100644 --- a/scripts/dtc/libfdt/libfdt.h +++ b/scripts/dtc/libfdt/libfdt.h @@ -1,5 +1,5 @@ -#ifndef _LIBFDT_H -#define _LIBFDT_H +#ifndef LIBFDT_H +#define LIBFDT_H /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. @@ -54,7 +54,7 @@ #include "libfdt_env.h" #include "fdt.h" -#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_FIRST_SUPPORTED_VERSION 0x02 #define FDT_LAST_SUPPORTED_VERSION 0x11 /* Error codes: informative error codes */ @@ -225,23 +225,23 @@ int fdt_next_subnode(const void *fdt, int offset); #define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) #define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) -#define __fdt_set_hdr(name) \ +#define fdt_set_hdr_(name) \ static inline void fdt_set_##name(void *fdt, uint32_t val) \ { \ struct fdt_header *fdth = (struct fdt_header *)fdt; \ fdth->name = cpu_to_fdt32(val); \ } -__fdt_set_hdr(magic); -__fdt_set_hdr(totalsize); -__fdt_set_hdr(off_dt_struct); -__fdt_set_hdr(off_dt_strings); -__fdt_set_hdr(off_mem_rsvmap); -__fdt_set_hdr(version); -__fdt_set_hdr(last_comp_version); -__fdt_set_hdr(boot_cpuid_phys); -__fdt_set_hdr(size_dt_strings); -__fdt_set_hdr(size_dt_struct); -#undef __fdt_set_hdr +fdt_set_hdr_(magic); +fdt_set_hdr_(totalsize); +fdt_set_hdr_(off_dt_struct); +fdt_set_hdr_(off_dt_strings); +fdt_set_hdr_(off_mem_rsvmap); +fdt_set_hdr_(version); +fdt_set_hdr_(last_comp_version); +fdt_set_hdr_(boot_cpuid_phys); +fdt_set_hdr_(size_dt_strings); +fdt_set_hdr_(size_dt_struct); +#undef fdt_set_hdr_ /** * fdt_check_header - sanity check a device tree or possible device tree @@ -527,6 +527,9 @@ int fdt_next_property_offset(const void *fdt, int offset); * offset. If lenp is non-NULL, the length of the property value is * also returned, in the integer pointed to by lenp. * + * Note that this code only works on device tree versions >= 16. fdt_getprop() + * works on all versions. + * * returns: * pointer to the structure representing the property * if lenp is non-NULL, *lenp contains the length of the property @@ -1449,7 +1452,7 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); /** - * fdt_setprop _placeholder - allocate space for a property + * fdt_setprop_placeholder - allocate space for a property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change * @name: name of the property to change @@ -1896,4 +1899,4 @@ int fdt_overlay_apply(void *fdt, void *fdto); const char *fdt_strerror(int errval); -#endif /* _LIBFDT_H */ +#endif /* LIBFDT_H */ diff --git a/scripts/dtc/libfdt/libfdt_env.h b/scripts/dtc/libfdt/libfdt_env.h index 952056cddf09..bd2474628775 100644 --- a/scripts/dtc/libfdt/libfdt_env.h +++ b/scripts/dtc/libfdt/libfdt_env.h @@ -1,5 +1,5 @@ -#ifndef _LIBFDT_ENV_H -#define _LIBFDT_ENV_H +#ifndef LIBFDT_ENV_H +#define LIBFDT_ENV_H /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. @@ -109,4 +109,31 @@ static inline fdt64_t cpu_to_fdt64(uint64_t x) #undef CPU_TO_FDT16 #undef EXTRACT_BYTE -#endif /* _LIBFDT_ENV_H */ +#ifdef __APPLE__ +#include + +/* strnlen() is not available on Mac OS < 10.7 */ +# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \ + MAC_OS_X_VERSION_10_7) + +#define strnlen fdt_strnlen + +/* + * fdt_strnlen: returns the length of a string or max_count - which ever is + * smallest. + * Input 1 string: the string whose size is to be determined + * Input 2 max_count: the maximum value returned by this function + * Output: length of the string or max_count (the smallest of the two) + */ +static inline size_t fdt_strnlen(const char *string, size_t max_count) +{ + const char *p = memchr(string, 0, max_count); + return p ? p - string : max_count; +} + +#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < + MAC_OS_X_VERSION_10_7) */ + +#endif /* __APPLE__ */ + +#endif /* LIBFDT_ENV_H */ diff --git a/scripts/dtc/libfdt/libfdt_internal.h b/scripts/dtc/libfdt/libfdt_internal.h index 02cfa6fb612d..7681e192295b 100644 --- a/scripts/dtc/libfdt/libfdt_internal.h +++ b/scripts/dtc/libfdt/libfdt_internal.h @@ -1,5 +1,5 @@ -#ifndef _LIBFDT_INTERNAL_H -#define _LIBFDT_INTERNAL_H +#ifndef LIBFDT_INTERNAL_H +#define LIBFDT_INTERNAL_H /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. @@ -57,27 +57,27 @@ #define FDT_CHECK_HEADER(fdt) \ { \ - int __err; \ - if ((__err = fdt_check_header(fdt)) != 0) \ - return __err; \ + int err_; \ + if ((err_ = fdt_check_header(fdt)) != 0) \ + return err_; \ } -int _fdt_check_node_offset(const void *fdt, int offset); -int _fdt_check_prop_offset(const void *fdt, int offset); -const char *_fdt_find_string(const char *strtab, int tabsize, const char *s); -int _fdt_node_end_offset(void *fdt, int nodeoffset); +int fdt_check_node_offset_(const void *fdt, int offset); +int fdt_check_prop_offset_(const void *fdt, int offset); +const char *fdt_find_string_(const char *strtab, int tabsize, const char *s); +int fdt_node_end_offset_(void *fdt, int nodeoffset); -static inline const void *_fdt_offset_ptr(const void *fdt, int offset) +static inline const void *fdt_offset_ptr_(const void *fdt, int offset) { return (const char *)fdt + fdt_off_dt_struct(fdt) + offset; } -static inline void *_fdt_offset_ptr_w(void *fdt, int offset) +static inline void *fdt_offset_ptr_w_(void *fdt, int offset) { - return (void *)(uintptr_t)_fdt_offset_ptr(fdt, offset); + return (void *)(uintptr_t)fdt_offset_ptr_(fdt, offset); } -static inline const struct fdt_reserve_entry *_fdt_mem_rsv(const void *fdt, int n) +static inline const struct fdt_reserve_entry *fdt_mem_rsv_(const void *fdt, int n) { const struct fdt_reserve_entry *rsv_table = (const struct fdt_reserve_entry *) @@ -85,11 +85,11 @@ static inline const struct fdt_reserve_entry *_fdt_mem_rsv(const void *fdt, int return rsv_table + n; } -static inline struct fdt_reserve_entry *_fdt_mem_rsv_w(void *fdt, int n) +static inline struct fdt_reserve_entry *fdt_mem_rsv_w_(void *fdt, int n) { - return (void *)(uintptr_t)_fdt_mem_rsv(fdt, n); + return (void *)(uintptr_t)fdt_mem_rsv_(fdt, n); } #define FDT_SW_MAGIC (~FDT_MAGIC) -#endif /* _LIBFDT_INTERNAL_H */ +#endif /* LIBFDT_INTERNAL_H */ diff --git a/scripts/dtc/livetree.c b/scripts/dtc/livetree.c index 6846ad2fd6d2..57b7db2ed153 100644 --- a/scripts/dtc/livetree.c +++ b/scripts/dtc/livetree.c @@ -216,7 +216,7 @@ struct node *merge_nodes(struct node *old_node, struct node *new_node) return old_node; } -void add_orphan_node(struct node *dt, struct node *new_node, char *ref) +struct node * add_orphan_node(struct node *dt, struct node *new_node, char *ref) { static unsigned int next_orphan_fragment = 0; struct node *node; @@ -236,6 +236,7 @@ void add_orphan_node(struct node *dt, struct node *new_node, char *ref) name_node(node, name); add_child(dt, node); + return dt; } struct node *chain_node(struct node *first, struct node *list) @@ -507,7 +508,7 @@ struct node *get_node_by_path(struct node *tree, const char *path) for_each_child(tree, child) { if (p && (strlen(child->name) == p-path) && - strneq(path, child->name, p-path)) + strprefixeq(path, p - path, child->name)) return get_node_by_path(child, p+1); else if (!p && streq(path, child->name)) return child; @@ -540,7 +541,10 @@ struct node *get_node_by_phandle(struct node *tree, cell_t phandle) { struct node *child, *node; - assert((phandle != 0) && (phandle != -1)); + if ((phandle == 0) || (phandle == -1)) { + assert(generate_fixups); + return NULL; + } if (tree->phandle == phandle) { if (tree->deleted) diff --git a/scripts/dtc/srcpos.c b/scripts/dtc/srcpos.c index 9d38459902f3..cb6ed0e3e5e4 100644 --- a/scripts/dtc/srcpos.c +++ b/scripts/dtc/srcpos.c @@ -209,8 +209,6 @@ struct srcpos srcpos_empty = { .file = NULL, }; -#define TAB_SIZE 8 - void srcpos_update(struct srcpos *pos, const char *text, int len) { int i; @@ -224,9 +222,6 @@ void srcpos_update(struct srcpos *pos, const char *text, int len) if (text[i] == '\n') { current_srcfile->lineno++; current_srcfile->colno = 1; - } else if (text[i] == '\t') { - current_srcfile->colno = - ALIGN(current_srcfile->colno, TAB_SIZE); } else { current_srcfile->colno++; } diff --git a/scripts/dtc/srcpos.h b/scripts/dtc/srcpos.h index 7caca8257c6d..9ded12a3830a 100644 --- a/scripts/dtc/srcpos.h +++ b/scripts/dtc/srcpos.h @@ -17,8 +17,8 @@ * USA */ -#ifndef _SRCPOS_H_ -#define _SRCPOS_H_ +#ifndef SRCPOS_H +#define SRCPOS_H #include #include @@ -114,4 +114,4 @@ extern void PRINTF(3, 4) srcpos_error(struct srcpos *pos, const char *prefix, extern void srcpos_set_line(char *f, int l); -#endif /* _SRCPOS_H_ */ +#endif /* SRCPOS_H */ diff --git a/scripts/dtc/util.h b/scripts/dtc/util.h index ad5f41199edb..66fba8ea709b 100644 --- a/scripts/dtc/util.h +++ b/scripts/dtc/util.h @@ -1,5 +1,5 @@ -#ifndef _UTIL_H -#define _UTIL_H +#ifndef UTIL_H +#define UTIL_H #include #include @@ -35,6 +35,9 @@ #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define stringify(s) stringify_(s) +#define stringify_(s) #s + static inline void NORETURN PRINTF(1, 2) die(const char *str, ...) { va_list ap; @@ -260,4 +263,4 @@ void NORETURN util_usage(const char *errmsg, const char *synopsis, case 'V': util_version(); \ case '?': usage("unknown option"); -#endif /* _UTIL_H */ +#endif /* UTIL_H */ diff --git a/scripts/dtc/version_gen.h b/scripts/dtc/version_gen.h index 6a4e84798966..ad87849e333b 100644 --- a/scripts/dtc/version_gen.h +++ b/scripts/dtc/version_gen.h @@ -1 +1 @@ -#define DTC_VERSION "DTC 1.4.5-gc1e55a55" +#define DTC_VERSION "DTC 1.4.6-gaadd0b65" -- cgit v1.2.3 From 859d880cf544dbe095ce97534ef04cd88ba2f2b4 Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Tue, 6 Mar 2018 00:20:25 -0600 Subject: signal: Correct the offset of si_pkey in struct siginfo The change moving addr_lsb into the _sigfault union failed to take into account that _sigfault._addr_bnd._lower being a pointer forced the entire union to have pointer alignment. In practice this only mattered for the offset of si_pkey which is why this has taken so long to discover. To correct this change _dummy_pkey and _dummy_bnd to have pointer type. Reported-by: kernel test robot Fixes: b68a68d3dcc1 ("signal: Move addr_lsb into the _sigfault union for clarity") Signed-off-by: "Eric W. Biederman" --- include/linux/compat.h | 4 ++-- include/uapi/asm-generic/siginfo.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/compat.h b/include/linux/compat.h index 8a9643857c4a..e16d07eb08cf 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -229,13 +229,13 @@ typedef struct compat_siginfo { short int _addr_lsb; /* Valid LSB of the reported address. */ /* used when si_code=SEGV_BNDERR */ struct { - short _dummy_bnd; + compat_uptr_t _dummy_bnd; compat_uptr_t _lower; compat_uptr_t _upper; } _addr_bnd; /* used when si_code=SEGV_PKUERR */ struct { - short _dummy_pkey; + compat_uptr_t _dummy_pkey; u32 _pkey; } _addr_pkey; }; diff --git a/include/uapi/asm-generic/siginfo.h b/include/uapi/asm-generic/siginfo.h index 85dc965afd89..99c902e460c2 100644 --- a/include/uapi/asm-generic/siginfo.h +++ b/include/uapi/asm-generic/siginfo.h @@ -102,13 +102,13 @@ typedef struct siginfo { short _addr_lsb; /* LSB of the reported address */ /* used when si_code=SEGV_BNDERR */ struct { - short _dummy_bnd; + void *_dummy_bnd; void __user *_lower; void __user *_upper; } _addr_bnd; /* used when si_code=SEGV_PKUERR */ struct { - short _dummy_pkey; + void *_dummy_pkey; __u32 _pkey; } _addr_pkey; }; -- cgit v1.2.3 From dde67eb1beebcd8493e7b30e74a80f0865ab7e36 Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Mon, 22 Jan 2018 08:32:01 +0100 Subject: i2c: add i2c_get_device_id() to get the standard i2c device id Can be used during probe to double check that the probed device is what is expected. Loosely based on code from Adrian Fiergolski . Tested-by: Adrian Fiergolski Reviewed-by: Wolfram Sang Signed-off-by: Peter Rosin --- drivers/i2c/i2c-core-base.c | 33 +++++++++++++++++++++++++++++++++ include/linux/i2c.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) (limited to 'include/linux') diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index 5a00bf443d06..aa03eeb43814 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -58,6 +58,8 @@ #define I2C_ADDR_7BITS_MAX 0x77 #define I2C_ADDR_7BITS_COUNT (I2C_ADDR_7BITS_MAX + 1) +#define I2C_ADDR_DEVICE_ID 0x7c + /* * core_lock protects i2c_adapter_idr, and guarantees that device detection, * deletion of detected devices, and attach_adapter calls are serialized @@ -1968,6 +1970,37 @@ int i2c_transfer_buffer_flags(const struct i2c_client *client, char *buf, } EXPORT_SYMBOL(i2c_transfer_buffer_flags); +/** + * i2c_get_device_id - get manufacturer, part id and die revision of a device + * @client: The device to query + * @id: The queried information + * + * Returns negative errno on error, zero on success. + */ +int i2c_get_device_id(const struct i2c_client *client, + struct i2c_device_identity *id) +{ + struct i2c_adapter *adap = client->adapter; + union i2c_smbus_data raw_id; + int ret; + + if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_READ_I2C_BLOCK)) + return -EOPNOTSUPP; + + raw_id.block[0] = 3; + ret = i2c_smbus_xfer(adap, I2C_ADDR_DEVICE_ID, 0, + I2C_SMBUS_READ, client->addr << 1, + I2C_SMBUS_I2C_BLOCK_DATA, &raw_id); + if (ret) + return ret; + + id->manufacturer_id = (raw_id.block[1] << 4) | (raw_id.block[2] >> 4); + id->part_id = ((raw_id.block[2] & 0xf) << 5) | (raw_id.block[3] >> 3); + id->die_revision = raw_id.block[3] & 0x7; + return 0; +} +EXPORT_SYMBOL_GPL(i2c_get_device_id); + /* ---------------------------------------------------- * the i2c address scanning function * Will not work for 10-bit addresses! diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 419a38e7c315..44ad14e016b5 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -47,6 +47,7 @@ struct i2c_algorithm; struct i2c_adapter; struct i2c_client; struct i2c_driver; +struct i2c_device_identity; union i2c_smbus_data; struct i2c_board_info; enum i2c_slave_event; @@ -186,8 +187,37 @@ extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client, extern s32 i2c_smbus_read_i2c_block_data_or_emulated(const struct i2c_client *client, u8 command, u8 length, u8 *values); +int i2c_get_device_id(const struct i2c_client *client, + struct i2c_device_identity *id); #endif /* I2C */ +/** + * struct i2c_device_identity - i2c client device identification + * @manufacturer_id: 0 - 4095, database maintained by NXP + * @part_id: 0 - 511, according to manufacturer + * @die_revision: 0 - 7, according to manufacturer + */ +struct i2c_device_identity { + u16 manufacturer_id; +#define I2C_DEVICE_ID_NXP_SEMICONDUCTORS 0 +#define I2C_DEVICE_ID_NXP_SEMICONDUCTORS_1 1 +#define I2C_DEVICE_ID_NXP_SEMICONDUCTORS_2 2 +#define I2C_DEVICE_ID_NXP_SEMICONDUCTORS_3 3 +#define I2C_DEVICE_ID_RAMTRON_INTERNATIONAL 4 +#define I2C_DEVICE_ID_ANALOG_DEVICES 5 +#define I2C_DEVICE_ID_STMICROELECTRONICS 6 +#define I2C_DEVICE_ID_ON_SEMICONDUCTOR 7 +#define I2C_DEVICE_ID_SPRINTEK_CORPORATION 8 +#define I2C_DEVICE_ID_ESPROS_PHOTONICS_AG 9 +#define I2C_DEVICE_ID_FUJITSU_SEMICONDUCTOR 10 +#define I2C_DEVICE_ID_FLIR 11 +#define I2C_DEVICE_ID_O2MICRO 12 +#define I2C_DEVICE_ID_ATMEL 13 +#define I2C_DEVICE_ID_NONE 0xffff + u16 part_id; + u8 die_revision; +}; + enum i2c_alert_protocol { I2C_PROTOCOL_SMBUS_ALERT, I2C_PROTOCOL_SMBUS_HOST_NOTIFY, -- cgit v1.2.3 From c17a7476e4c41884d82e3675c25ceae982c07a63 Mon Sep 17 00:00:00 2001 From: Benjamin Tissoires Date: Fri, 8 Dec 2017 15:29:44 +0100 Subject: HID: core: rewrite the hid-generic automatic unbind We actually can have the unbind/rebind logic in hid-core.c, leaving only the match function in hid-generic. This makes hid-generic simpler and the whole logic simpler too. Signed-off-by: Benjamin Tissoires Signed-off-by: Jiri Kosina --- drivers/hid/hid-core.c | 35 ++++++++++++++++++++++++----------- drivers/hid/hid-generic.c | 33 --------------------------------- include/linux/hid.h | 4 ---- 3 files changed, 24 insertions(+), 48 deletions(-) (limited to 'include/linux') diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index c2560aae5542..c058bb911ca1 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -2197,31 +2197,40 @@ void hid_destroy_device(struct hid_device *hdev) EXPORT_SYMBOL_GPL(hid_destroy_device); -static int __bus_add_driver(struct device_driver *drv, void *data) +static int __hid_bus_reprobe_drivers(struct device *dev, void *data) { - struct hid_driver *added_hdrv = data; - struct hid_driver *hdrv = to_hid_driver(drv); + struct hid_driver *hdrv = data; + struct hid_device *hdev = to_hid_device(dev); - if (hdrv->bus_add_driver) - hdrv->bus_add_driver(added_hdrv); + if (hdev->driver == hdrv && + !hdrv->match(hdev, hid_ignore_special_drivers)) + return device_reprobe(dev); return 0; } -static int __bus_removed_driver(struct device_driver *drv, void *data) +static int __hid_bus_driver_added(struct device_driver *drv, void *data) { - struct hid_driver *removed_hdrv = data; struct hid_driver *hdrv = to_hid_driver(drv); - if (hdrv->bus_removed_driver) - hdrv->bus_removed_driver(removed_hdrv); + if (hdrv->match) { + bus_for_each_dev(&hid_bus_type, NULL, hdrv, + __hid_bus_reprobe_drivers); + } return 0; } +static int __bus_removed_driver(struct device_driver *drv, void *data) +{ + return bus_rescan_devices(&hid_bus_type); +} + int __hid_register_driver(struct hid_driver *hdrv, struct module *owner, const char *mod_name) { + int ret; + hdrv->driver.name = hdrv->name; hdrv->driver.bus = &hid_bus_type; hdrv->driver.owner = owner; @@ -2230,9 +2239,13 @@ int __hid_register_driver(struct hid_driver *hdrv, struct module *owner, INIT_LIST_HEAD(&hdrv->dyn_list); spin_lock_init(&hdrv->dyn_lock); - bus_for_each_drv(&hid_bus_type, NULL, hdrv, __bus_add_driver); + ret = driver_register(&hdrv->driver); + + if (ret == 0) + bus_for_each_drv(&hid_bus_type, NULL, NULL, + __hid_bus_driver_added); - return driver_register(&hdrv->driver); + return ret; } EXPORT_SYMBOL_GPL(__hid_register_driver); diff --git a/drivers/hid/hid-generic.c b/drivers/hid/hid-generic.c index 3c0a1bf433d7..c25b4718de44 100644 --- a/drivers/hid/hid-generic.c +++ b/drivers/hid/hid-generic.c @@ -26,37 +26,6 @@ static struct hid_driver hid_generic; -static int __unmap_hid_generic(struct device *dev, void *data) -{ - struct hid_driver *hdrv = data; - struct hid_device *hdev = to_hid_device(dev); - - /* only unbind matching devices already bound to hid-generic */ - if (hdev->driver != &hid_generic || - hid_match_device(hdev, hdrv) == NULL) - return 0; - - if (dev->parent) /* Needed for USB */ - device_lock(dev->parent); - device_release_driver(dev); - if (dev->parent) - device_unlock(dev->parent); - - return 0; -} - -static void hid_generic_add_driver(struct hid_driver *hdrv) -{ - bus_for_each_dev(&hid_bus_type, NULL, hdrv, __unmap_hid_generic); -} - -static void hid_generic_removed_driver(struct hid_driver *hdrv) -{ - int ret; - - ret = driver_attach(&hid_generic.driver); -} - static int __check_hid_generic(struct device_driver *drv, void *data) { struct hid_driver *hdrv = to_hid_driver(drv); @@ -97,8 +66,6 @@ static struct hid_driver hid_generic = { .name = "hid-generic", .id_table = hid_table, .match = hid_generic_match, - .bus_add_driver = hid_generic_add_driver, - .bus_removed_driver = hid_generic_removed_driver, }; module_hid_driver(hid_generic); diff --git a/include/linux/hid.h b/include/linux/hid.h index 091a81cf330f..a62ee4a609ac 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -686,8 +686,6 @@ struct hid_usage_id { * @input_mapped: invoked on input registering after mapping an usage * @input_configured: invoked just before the device is registered * @feature_mapping: invoked on feature registering - * @bus_add_driver: invoked when a HID driver is about to be added - * @bus_removed_driver: invoked when a HID driver has been removed * @suspend: invoked on suspend (NULL means nop) * @resume: invoked on resume if device was not reset (NULL means nop) * @reset_resume: invoked on resume if device was reset (NULL means nop) @@ -742,8 +740,6 @@ struct hid_driver { void (*feature_mapping)(struct hid_device *hdev, struct hid_field *field, struct hid_usage *usage); - void (*bus_add_driver)(struct hid_driver *driver); - void (*bus_removed_driver)(struct hid_driver *driver); #ifdef CONFIG_PM int (*suspend)(struct hid_device *hdev, pm_message_t message); int (*resume)(struct hid_device *hdev); -- cgit v1.2.3 From cb88a0588717ba6c756cb5972d75766b273a6817 Mon Sep 17 00:00:00 2001 From: Danilo Krummrich Date: Tue, 6 Mar 2018 09:38:49 +0100 Subject: usb: quirks: add control message delay for 1b1c:1b20 Corsair Strafe RGB keyboard does not respond to usb control messages sometimes and hence generates timeouts. Commit de3af5bf259d ("usb: quirks: add delay init quirk for Corsair Strafe RGB keyboard") tried to fix those timeouts by adding USB_QUIRK_DELAY_INIT. Unfortunately, even with this quirk timeouts of usb_control_msg() can still be seen, but with a lower frequency (approx. 1 out of 15): [ 29.103520] usb 1-8: string descriptor 0 read error: -110 [ 34.363097] usb 1-8: can't set config #1, error -110 Adding further delays to different locations where usb control messages are issued just moves the timeouts to other locations, e.g.: [ 35.400533] usbhid 1-8:1.0: can't add hid device: -110 [ 35.401014] usbhid: probe of 1-8:1.0 failed with error -110 The only way to reliably avoid those issues is having a pause after each usb control message. In approx. 200 boot cycles no more timeouts were seen. Addionaly, keep USB_QUIRK_DELAY_INIT as it turned out to be necessary to have the delay in hub_port_connect() after hub_port_init(). The overall boot time seems not to be influenced by these additional delays, even on fast machines and lightweight distributions. Fixes: de3af5bf259d ("usb: quirks: add delay init quirk for Corsair Strafe RGB keyboard") Cc: stable@vger.kernel.org Signed-off-by: Danilo Krummrich Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/message.c | 4 ++++ drivers/usb/core/quirks.c | 3 ++- include/linux/usb/quirks.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c index c64cf6c4a83d..0c11d40a12bc 100644 --- a/drivers/usb/core/message.c +++ b/drivers/usb/core/message.c @@ -151,6 +151,10 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, __u8 request, ret = usb_internal_control_msg(dev, pipe, dr, data, size, timeout); + /* Linger a bit, prior to the next control message. */ + if (dev->quirks & USB_QUIRK_DELAY_CTRL_MSG) + msleep(200); + kfree(dr); return ret; diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index f4a548471f0f..54b019e267c5 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -230,7 +230,8 @@ static const struct usb_device_id usb_quirk_list[] = { { USB_DEVICE(0x1b1c, 0x1b13), .driver_info = USB_QUIRK_DELAY_INIT }, /* Corsair Strafe RGB */ - { USB_DEVICE(0x1b1c, 0x1b20), .driver_info = USB_QUIRK_DELAY_INIT }, + { USB_DEVICE(0x1b1c, 0x1b20), .driver_info = USB_QUIRK_DELAY_INIT | + USB_QUIRK_DELAY_CTRL_MSG }, /* Corsair K70 LUX */ { USB_DEVICE(0x1b1c, 0x1b36), .driver_info = USB_QUIRK_DELAY_INIT }, diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h index f1fcec2fd5f8..b7a99ce56bc9 100644 --- a/include/linux/usb/quirks.h +++ b/include/linux/usb/quirks.h @@ -63,4 +63,7 @@ */ #define USB_QUIRK_DISCONNECT_SUSPEND BIT(12) +/* Device needs a pause after every control message. */ +#define USB_QUIRK_DELAY_CTRL_MSG BIT(13) + #endif /* __LINUX_USB_QUIRKS_H */ -- cgit v1.2.3 From a4429e53c9b3082b05e51224c3d58dbdd39306c5 Mon Sep 17 00:00:00 2001 From: Wanpeng Li Date: Tue, 13 Feb 2018 09:05:40 +0800 Subject: KVM: Introduce paravirtualization hints and KVM_HINTS_DEDICATED MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces kvm_para_has_hint() to query for hints about the configuration of the guests. The first hint KVM_HINTS_DEDICATED, is set if the guest has dedicated physical CPUs for each vCPU (i.e. pinning and no over-commitment). This allows optimizing spinlocks and tells the guest to avoid PV TLB flush. Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Eduardo Habkost Signed-off-by: Wanpeng Li Signed-off-by: Paolo Bonzini Signed-off-by: Radim Krčmář --- Documentation/virtual/kvm/cpuid.txt | 15 +++++++++++++-- arch/mips/include/asm/kvm_para.h | 5 +++++ arch/powerpc/include/asm/kvm_para.h | 5 +++++ arch/s390/include/asm/kvm_para.h | 5 +++++ arch/x86/include/asm/kvm_para.h | 6 ++++++ arch/x86/include/uapi/asm/kvm_para.h | 8 ++++++-- arch/x86/kernel/kvm.c | 5 +++++ include/asm-generic/kvm_para.h | 5 +++++ include/linux/kvm_para.h | 5 +++++ 9 files changed, 55 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/Documentation/virtual/kvm/cpuid.txt b/Documentation/virtual/kvm/cpuid.txt index 87a7506f31c2..d4f33eb805dd 100644 --- a/Documentation/virtual/kvm/cpuid.txt +++ b/Documentation/virtual/kvm/cpuid.txt @@ -23,8 +23,8 @@ This function queries the presence of KVM cpuid leafs. function: define KVM_CPUID_FEATURES (0x40000001) -returns : ebx, ecx, edx = 0 - eax = and OR'ed group of (1 << flag), where each flags is: +returns : ebx, ecx + eax = an OR'ed group of (1 << flag), where each flags is: flag || value || meaning @@ -66,3 +66,14 @@ KVM_FEATURE_CLOCKSOURCE_STABLE_BIT || 24 || host will warn if no guest-side || || per-cpu warps are expected in || || kvmclock. ------------------------------------------------------------------------------ + + edx = an OR'ed group of (1 << flag), where each flags is: + + +flag || value || meaning +================================================================================== +KVM_HINTS_DEDICATED || 0 || guest checks this feature bit to + || || determine if there is vCPU pinning + || || and there is no vCPU over-commitment, + || || allowing optimizations +---------------------------------------------------------------------------------- diff --git a/arch/mips/include/asm/kvm_para.h b/arch/mips/include/asm/kvm_para.h index 60b1aa0b7014..b57e978b0946 100644 --- a/arch/mips/include/asm/kvm_para.h +++ b/arch/mips/include/asm/kvm_para.h @@ -94,6 +94,11 @@ static inline unsigned int kvm_arch_para_features(void) return 0; } +static inline unsigned int kvm_arch_para_hints(void) +{ + return 0; +} + #ifdef CONFIG_MIPS_PARAVIRT static inline bool kvm_para_available(void) { diff --git a/arch/powerpc/include/asm/kvm_para.h b/arch/powerpc/include/asm/kvm_para.h index 336a91acb8b1..5ceb4efca65f 100644 --- a/arch/powerpc/include/asm/kvm_para.h +++ b/arch/powerpc/include/asm/kvm_para.h @@ -61,6 +61,11 @@ static inline unsigned int kvm_arch_para_features(void) return r; } +static inline unsigned int kvm_arch_para_hints(void) +{ + return 0; +} + static inline bool kvm_check_and_clear_guest_paused(void) { return false; diff --git a/arch/s390/include/asm/kvm_para.h b/arch/s390/include/asm/kvm_para.h index 74eeec9c0a80..cbc7c3a68e4d 100644 --- a/arch/s390/include/asm/kvm_para.h +++ b/arch/s390/include/asm/kvm_para.h @@ -193,6 +193,11 @@ static inline unsigned int kvm_arch_para_features(void) return 0; } +static inline unsigned int kvm_arch_para_hints(void) +{ + return 0; +} + static inline bool kvm_check_and_clear_guest_paused(void) { return false; diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h index 7b407dda2bd7..3aea2658323a 100644 --- a/arch/x86/include/asm/kvm_para.h +++ b/arch/x86/include/asm/kvm_para.h @@ -88,6 +88,7 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1, #ifdef CONFIG_KVM_GUEST bool kvm_para_available(void); unsigned int kvm_arch_para_features(void); +unsigned int kvm_arch_para_hints(void); void kvm_async_pf_task_wait(u32 token, int interrupt_kernel); void kvm_async_pf_task_wake(u32 token); u32 kvm_read_and_reset_pf_reason(void); @@ -115,6 +116,11 @@ static inline unsigned int kvm_arch_para_features(void) return 0; } +static inline unsigned int kvm_arch_para_hints(void) +{ + return 0; +} + static inline u32 kvm_read_and_reset_pf_reason(void) { return 0; diff --git a/arch/x86/include/uapi/asm/kvm_para.h b/arch/x86/include/uapi/asm/kvm_para.h index 6cfa9c8cb7d6..68a41b6ba3da 100644 --- a/arch/x86/include/uapi/asm/kvm_para.h +++ b/arch/x86/include/uapi/asm/kvm_para.h @@ -10,8 +10,10 @@ */ #define KVM_CPUID_SIGNATURE 0x40000000 -/* This CPUID returns a feature bitmap in eax. Before enabling a particular - * paravirtualization, the appropriate feature bit should be checked. +/* This CPUID returns two feature bitmaps in eax, edx. Before enabling + * a particular paravirtualization, the appropriate feature bit should + * be checked in eax. The performance hint feature bit should be checked + * in edx. */ #define KVM_CPUID_FEATURES 0x40000001 #define KVM_FEATURE_CLOCKSOURCE 0 @@ -28,6 +30,8 @@ #define KVM_FEATURE_PV_TLB_FLUSH 9 #define KVM_FEATURE_ASYNC_PF_VMEXIT 10 +#define KVM_HINTS_DEDICATED 0 + /* The last 8 bits are used to indicate how to interpret the flags field * in pvclock structure. If no bits are set, all flags are ignored. */ diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index bc1a27280c4b..8c9d98c46f84 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -605,6 +605,11 @@ unsigned int kvm_arch_para_features(void) return cpuid_eax(kvm_cpuid_base() | KVM_CPUID_FEATURES); } +unsigned int kvm_arch_para_hints(void) +{ + return cpuid_edx(kvm_cpuid_base() | KVM_CPUID_FEATURES); +} + static uint32_t __init kvm_detect(void) { return kvm_cpuid_base(); diff --git a/include/asm-generic/kvm_para.h b/include/asm-generic/kvm_para.h index 18c6abe81fbd..728e5c5706c4 100644 --- a/include/asm-generic/kvm_para.h +++ b/include/asm-generic/kvm_para.h @@ -19,6 +19,11 @@ static inline unsigned int kvm_arch_para_features(void) return 0; } +static inline unsigned int kvm_arch_para_hints(void) +{ + return 0; +} + static inline bool kvm_para_available(void) { return false; diff --git a/include/linux/kvm_para.h b/include/linux/kvm_para.h index 51f6ef2c2ff4..f23b90b02898 100644 --- a/include/linux/kvm_para.h +++ b/include/linux/kvm_para.h @@ -9,4 +9,9 @@ static inline bool kvm_para_has_feature(unsigned int feature) { return !!(kvm_arch_para_features() & (1UL << feature)); } + +static inline bool kvm_para_has_hint(unsigned int feature) +{ + return !!(kvm_arch_para_hints() & (1UL << feature)); +} #endif /* __LINUX_KVM_PARA_H */ -- cgit v1.2.3 From ce767047b1b731a1899a528338644f2bfdab8b36 Mon Sep 17 00:00:00 2001 From: Haiyang Zhang Date: Sun, 4 Mar 2018 22:17:17 -0700 Subject: hv_vmbus: Correct the stale comments regarding cpu affinity The comments doesn't match what the current code does, also have a typo. This patch corrects them. Signed-off-by: Haiyang Zhang Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- drivers/hv/channel_mgmt.c | 6 ++---- include/linux/hyperv.h | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c index c21020b69114..c6d9d19bc04e 100644 --- a/drivers/hv/channel_mgmt.c +++ b/drivers/hv/channel_mgmt.c @@ -596,10 +596,8 @@ static int next_numa_node_id; /* * Starting with Win8, we can statically distribute the incoming * channel interrupt load by binding a channel to VCPU. - * We do this in a hierarchical fashion: - * First distribute the primary channels across available NUMA nodes - * and then distribute the subchannels amongst the CPUs in the NUMA - * node assigned to the primary channel. + * We distribute the interrupt loads to one or more NUMA nodes based on + * the channel's affinity_policy. * * For pre-win8 hosts or non-performance critical channels we assign the * first CPU in the first NUMA node. diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 93bd6fcd6e62..2048f3c3b68a 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -844,7 +844,7 @@ struct vmbus_channel { /* * NUMA distribution policy: - * We support teo policies: + * We support two policies: * 1) Balanced: Here all performance critical channels are * distributed evenly amongst all the NUMA nodes. * This policy will be the default policy. -- cgit v1.2.3 From 6b4f3d01052a479c7ebbe99d52a663558dc1be2a Mon Sep 17 00:00:00 2001 From: Stephen Smalley Date: Fri, 8 Sep 2017 12:40:01 -0400 Subject: usb, signal, security: only pass the cred, not the secid, to kill_pid_info_as_cred and security_task_kill commit d178bc3a708f39cbfefc3fab37032d3f2511b4ec ("user namespace: usb: make usb urbs user namespace aware (v2)") changed kill_pid_info_as_uid to kill_pid_info_as_cred, saving and passing a cred structure instead of uids. Since the secid can be obtained from the cred, drop the secid fields from the usb_dev_state and async structures, and drop the secid argument to kill_pid_info_as_cred. Replace the secid argument to security_task_kill with the cred. Update SELinux, Smack, and AppArmor to use the cred, which avoids the need for Smack and AppArmor to use a secid at all in this hook. Further changes to Smack might still be required to take full advantage of this change, since it should now be possible to perform capability checking based on the supplied cred. The changes to Smack and AppArmor have only been compile-tested. Signed-off-by: Stephen Smalley Acked-by: Paul Moore Acked-by: Casey Schaufler Acked-by: Greg Kroah-Hartman Acked-by: John Johansen Signed-off-by: James Morris --- drivers/usb/core/devio.c | 10 ++-------- include/linux/lsm_hooks.h | 5 +++-- include/linux/sched/signal.h | 2 +- include/linux/security.h | 4 ++-- kernel/signal.c | 6 +++--- security/apparmor/lsm.c | 17 ++++++++++++----- security/security.c | 4 ++-- security/selinux/hooks.c | 7 +++++-- security/smack/smack_lsm.c | 12 +++++------- 9 files changed, 35 insertions(+), 32 deletions(-) (limited to 'include/linux') diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c index d526595bc959..76e16c5251b9 100644 --- a/drivers/usb/core/devio.c +++ b/drivers/usb/core/devio.c @@ -65,7 +65,6 @@ struct usb_dev_state { const struct cred *cred; void __user *disccontext; unsigned long ifclaimed; - u32 secid; u32 disabled_bulk_eps; bool privileges_dropped; unsigned long interface_allowed_mask; @@ -95,7 +94,6 @@ struct async { struct usb_memory *usbm; unsigned int mem_usage; int status; - u32 secid; u8 bulk_addr; u8 bulk_status; }; @@ -586,7 +584,6 @@ static void async_completed(struct urb *urb) struct usb_dev_state *ps = as->ps; struct siginfo sinfo; struct pid *pid = NULL; - u32 secid = 0; const struct cred *cred = NULL; int signr; @@ -602,7 +599,6 @@ static void async_completed(struct urb *urb) sinfo.si_addr = as->userurb; pid = get_pid(as->pid); cred = get_cred(as->cred); - secid = as->secid; } snoop(&urb->dev->dev, "urb complete\n"); snoop_urb(urb->dev, as->userurb, urb->pipe, urb->actual_length, @@ -618,7 +614,7 @@ static void async_completed(struct urb *urb) spin_unlock(&ps->lock); if (signr) { - kill_pid_info_as_cred(sinfo.si_signo, &sinfo, pid, cred, secid); + kill_pid_info_as_cred(sinfo.si_signo, &sinfo, pid, cred); put_pid(pid); put_cred(cred); } @@ -1013,7 +1009,6 @@ static int usbdev_open(struct inode *inode, struct file *file) init_waitqueue_head(&ps->wait); ps->disc_pid = get_pid(task_pid(current)); ps->cred = get_current_cred(); - security_task_getsecid(current, &ps->secid); smp_wmb(); list_add_tail(&ps->list, &dev->filelist); file->private_data = ps; @@ -1727,7 +1722,6 @@ static int proc_do_submiturb(struct usb_dev_state *ps, struct usbdevfs_urb *uurb as->ifnum = ifnum; as->pid = get_pid(task_pid(current)); as->cred = get_current_cred(); - security_task_getsecid(current, &as->secid); snoop_urb(ps->dev, as->userurb, as->urb->pipe, as->urb->transfer_buffer_length, 0, SUBMIT, NULL, 0); @@ -2617,7 +2611,7 @@ static void usbdev_remove(struct usb_device *udev) sinfo.si_code = SI_ASYNCIO; sinfo.si_addr = ps->disccontext; kill_pid_info_as_cred(ps->discsignr, &sinfo, - ps->disc_pid, ps->cred, ps->secid); + ps->disc_pid, ps->cred); } } } diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index 7161d8e7ee79..e0ac011d07a5 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -672,7 +672,8 @@ * @p contains the task_struct for process. * @info contains the signal information. * @sig contains the signal value. - * @secid contains the sid of the process where the signal originated + * @cred contains the cred of the process where the signal originated, or + * NULL if the current task is the originator. * Return 0 if permission is granted. * @task_prctl: * Check permission before performing a process control operation on the @@ -1564,7 +1565,7 @@ union security_list_options { int (*task_getscheduler)(struct task_struct *p); int (*task_movememory)(struct task_struct *p); int (*task_kill)(struct task_struct *p, struct siginfo *info, - int sig, u32 secid); + int sig, const struct cred *cred); int (*task_prctl)(int option, unsigned long arg2, unsigned long arg3, unsigned long arg4, unsigned long arg5); void (*task_to_inode)(struct task_struct *p, struct inode *inode); diff --git a/include/linux/sched/signal.h b/include/linux/sched/signal.h index 23b4f9cb82db..a7ce74c74e49 100644 --- a/include/linux/sched/signal.h +++ b/include/linux/sched/signal.h @@ -319,7 +319,7 @@ extern int force_sig_info(int, struct siginfo *, struct task_struct *); extern int __kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp); extern int kill_pid_info(int sig, struct siginfo *info, struct pid *pid); extern int kill_pid_info_as_cred(int, struct siginfo *, struct pid *, - const struct cred *, u32); + const struct cred *); extern int kill_pgrp(struct pid *pid, int sig, int priv); extern int kill_pid(struct pid *pid, int sig, int priv); extern __must_check bool do_notify_parent(struct task_struct *, int); diff --git a/include/linux/security.h b/include/linux/security.h index 73f1ef625d40..3f5fd988ee87 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -347,7 +347,7 @@ int security_task_setscheduler(struct task_struct *p); int security_task_getscheduler(struct task_struct *p); int security_task_movememory(struct task_struct *p); int security_task_kill(struct task_struct *p, struct siginfo *info, - int sig, u32 secid); + int sig, const struct cred *cred); int security_task_prctl(int option, unsigned long arg2, unsigned long arg3, unsigned long arg4, unsigned long arg5); void security_task_to_inode(struct task_struct *p, struct inode *inode); @@ -1010,7 +1010,7 @@ static inline int security_task_movememory(struct task_struct *p) static inline int security_task_kill(struct task_struct *p, struct siginfo *info, int sig, - u32 secid) + const struct cred *cred) { return 0; } diff --git a/kernel/signal.c b/kernel/signal.c index c6e4c83dc090..b033292f4beb 100644 --- a/kernel/signal.c +++ b/kernel/signal.c @@ -770,7 +770,7 @@ static int check_kill_permission(int sig, struct siginfo *info, } } - return security_task_kill(t, info, sig, 0); + return security_task_kill(t, info, sig, NULL); } /** @@ -1361,7 +1361,7 @@ static int kill_as_cred_perm(const struct cred *cred, /* like kill_pid_info(), but doesn't use uid/euid of "current" */ int kill_pid_info_as_cred(int sig, struct siginfo *info, struct pid *pid, - const struct cred *cred, u32 secid) + const struct cred *cred) { int ret = -EINVAL; struct task_struct *p; @@ -1380,7 +1380,7 @@ int kill_pid_info_as_cred(int sig, struct siginfo *info, struct pid *pid, ret = -EPERM; goto out_unlock; } - ret = security_task_kill(p, info, sig, secid); + ret = security_task_kill(p, info, sig, cred); if (ret) goto out_unlock; diff --git a/security/apparmor/lsm.c b/security/apparmor/lsm.c index 9a65eeaf7dfa..77bdfa7f8428 100644 --- a/security/apparmor/lsm.c +++ b/security/apparmor/lsm.c @@ -717,16 +717,23 @@ static int apparmor_task_setrlimit(struct task_struct *task, } static int apparmor_task_kill(struct task_struct *target, struct siginfo *info, - int sig, u32 secid) + int sig, const struct cred *cred) { struct aa_label *cl, *tl; int error; - if (secid) - /* TODO: after secid to label mapping is done. - * Dealing with USB IO specific behavior + if (cred) { + /* + * Dealing with USB IO specific behavior */ - return 0; + cl = aa_get_newest_cred_label(cred); + tl = aa_get_task_label(target); + error = aa_may_signal(cl, tl, sig); + aa_put_label(cl); + aa_put_label(tl); + return error; + } + cl = __begin_current_label_crit_section(); tl = aa_get_task_label(target); error = aa_may_signal(cl, tl, sig); diff --git a/security/security.c b/security/security.c index 1cd8526cb0b7..14c291910d25 100644 --- a/security/security.c +++ b/security/security.c @@ -1114,9 +1114,9 @@ int security_task_movememory(struct task_struct *p) } int security_task_kill(struct task_struct *p, struct siginfo *info, - int sig, u32 secid) + int sig, const struct cred *cred) { - return call_int_hook(task_kill, 0, p, info, sig, secid); + return call_int_hook(task_kill, 0, p, info, sig, cred); } int security_task_prctl(int option, unsigned long arg2, unsigned long arg3, diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 8644d864e3c1..8abd542c6b7c 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -4036,16 +4036,19 @@ static int selinux_task_movememory(struct task_struct *p) } static int selinux_task_kill(struct task_struct *p, struct siginfo *info, - int sig, u32 secid) + int sig, const struct cred *cred) { + u32 secid; u32 perm; if (!sig) perm = PROCESS__SIGNULL; /* null signal; existence test */ else perm = signal_to_av(sig); - if (!secid) + if (!cred) secid = current_sid(); + else + secid = cred_sid(cred); return avc_has_perm(secid, task_sid(p), SECCLASS_PROCESS, perm, NULL); } diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index 03fdecba93bb..feada2665322 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -2228,15 +2228,13 @@ static int smack_task_movememory(struct task_struct *p) * @p: the task object * @info: unused * @sig: unused - * @secid: identifies the smack to use in lieu of current's + * @cred: identifies the cred to use in lieu of current's * * Return 0 if write access is permitted * - * The secid behavior is an artifact of an SELinux hack - * in the USB code. Someday it may go away. */ static int smack_task_kill(struct task_struct *p, struct siginfo *info, - int sig, u32 secid) + int sig, const struct cred *cred) { struct smk_audit_info ad; struct smack_known *skp; @@ -2252,17 +2250,17 @@ static int smack_task_kill(struct task_struct *p, struct siginfo *info, * Sending a signal requires that the sender * can write the receiver. */ - if (secid == 0) { + if (cred == NULL) { rc = smk_curacc(tkp, MAY_DELIVER, &ad); rc = smk_bu_task(p, MAY_DELIVER, rc); return rc; } /* - * If the secid isn't 0 we're dealing with some USB IO + * If the cred isn't NULL we're dealing with some USB IO * specific behavior. This is not clean. For one thing * we can't take privilege into account. */ - skp = smack_from_secid(secid); + skp = smk_of_task(cred->security); rc = smk_access(skp, tkp, MAY_DELIVER, &ad); rc = smk_bu_note("USB signal", skp, tkp, MAY_DELIVER, rc); return rc; -- cgit v1.2.3 From a9db0ecf1578894ea3405f3eb5a441508840d479 Mon Sep 17 00:00:00 2001 From: Matan Barak Date: Wed, 16 Aug 2017 09:43:48 +0300 Subject: {net,IB}/mlx5: Add has_tag to mlx5_flow_act The has_tag member will indicate whether a tag action was specified in flow specification. A flow tag 0 = MLX5_FS_DEFAULT_FLOW_TAG is assumed a valid flow tag that is currently used by mlx5 RDMA driver, whereas in HW flow_tag = 0 means that the user doesn't care about flow_tag. HW always provide a flow_tag = 0 if all flow tags requested on a specific flow are 0. So we need a way (in the driver) to differentiate between a user really requesting flow_tag = 0 and a user who does not care, in order to be able to report conflicting flow tags on a specific flow. Signed-off-by: Matan Barak Reviewed-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- drivers/infiniband/hw/mlx5/main.c | 3 ++- drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 1 + drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 2 +- include/linux/mlx5/fs.h | 1 + 4 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index 1b305367a817..d50ace805995 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -2535,6 +2535,7 @@ static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, return -EINVAL; action->flow_tag = ib_spec->flow_tag.tag_id; + action->has_flow_tag = true; break; case IB_FLOW_SPEC_ACTION_DROP: if (FIELDS_NOT_SUPPORTED(ib_spec->drop, @@ -2847,7 +2848,7 @@ static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; } - if (flow_act.flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && + if (flow_act.has_flow_tag && (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c index fd98b0dc610f..eeff1fac77ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -675,6 +675,7 @@ mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv, struct mlx5_flow_destination dest[2] = {}; struct mlx5_flow_act flow_act = { .action = attr->action, + .has_flow_tag = true, .flow_tag = attr->flow_tag, .encap_id = 0, }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index c025c98700e4..d81da6920be8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -1443,7 +1443,7 @@ static int check_conflicting_ftes(struct fs_fte *fte, const struct mlx5_flow_act return -EEXIST; } - if (fte->flow_tag != flow_act->flow_tag) { + if (flow_act->has_flow_tag && fte->flow_tag != flow_act->flow_tag) { mlx5_core_warn(get_dev(&fte->node), "FTE flow tag %u already exists with different flow tag %u\n", fte->flow_tag, diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h index a0b48afcb422..f580bc4c2443 100644 --- a/include/linux/mlx5/fs.h +++ b/include/linux/mlx5/fs.h @@ -141,6 +141,7 @@ void mlx5_destroy_flow_group(struct mlx5_flow_group *fg); struct mlx5_flow_act { u32 action; + bool has_flow_tag; u32 flow_tag; u32 encap_id; u32 modify_id; -- cgit v1.2.3 From 5f4183781a303da5ab6731b8c19328c5b9df89fa Mon Sep 17 00:00:00 2001 From: Aviad Yehezkel Date: Sun, 18 Feb 2018 13:17:17 +0200 Subject: net/mlx5: Add empty egress namespace to flow steering core Currently, we don't support egress flow steering namespace in mlx5 flow steering core implementation. However, when we want to encrypt a packet, we model it as a flow steering rule in the egress path. To overcome this, we add an empty egress namespace to flow steering. This namespace is initialized only when ipsec support exists. In the future, this will grow to a full blown full steering implementation, resembling the ingress path. Signed-off-by: Matan Barak Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- .../mellanox/mlx5/core/diag/fs_tracepoint.c | 3 +++ drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c | 1 + drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 28 ++++++++++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/fs_core.h | 2 ++ include/linux/mlx5/fs.h | 1 + include/linux/mlx5/mlx5_ifc.h | 1 + 6 files changed, 36 insertions(+) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c index 0be4575b58a2..3816b4506561 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c @@ -246,6 +246,9 @@ const char *parse_fs_dst(struct trace_seq *p, case MLX5_FLOW_DESTINATION_TYPE_COUNTER: trace_seq_printf(p, "counter_id=%u\n", counter_id); break; + case MLX5_FLOW_DESTINATION_TYPE_PORT: + trace_seq_printf(p, "port\n"); + break; } trace_seq_putc(p, 0); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c index c3eaddb43e57..ed3ea80a24be 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -731,6 +731,7 @@ const struct mlx5_flow_cmds *mlx5_fs_cmd_get_default(enum fs_flow_table_type typ case FS_FT_SNIFFER_RX: case FS_FT_SNIFFER_TX: return mlx5_fs_cmd_get_fw_cmds(); + case FS_FT_NIC_TX: default: return mlx5_fs_cmd_get_stub_cmds(); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index f3a654b96b98..5c111186d103 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -37,6 +37,7 @@ #include "fs_core.h" #include "fs_cmd.h" #include "diag/fs_tracepoint.h" +#include "accel/ipsec.h" #define INIT_TREE_NODE_ARRAY_SIZE(...) (sizeof((struct init_tree_node[]){__VA_ARGS__}) /\ sizeof(struct init_tree_node)) @@ -2049,6 +2050,11 @@ struct mlx5_flow_namespace *mlx5_get_flow_namespace(struct mlx5_core_dev *dev, return &steering->sniffer_tx_root_ns->ns; else return NULL; + case MLX5_FLOW_NAMESPACE_EGRESS: + if (steering->egress_root_ns) + return &steering->egress_root_ns->ns; + else + return NULL; default: return NULL; } @@ -2413,6 +2419,7 @@ void mlx5_cleanup_fs(struct mlx5_core_dev *dev) cleanup_root_ns(steering->fdb_root_ns); cleanup_root_ns(steering->sniffer_rx_root_ns); cleanup_root_ns(steering->sniffer_tx_root_ns); + cleanup_root_ns(steering->egress_root_ns); mlx5_cleanup_fc_stats(dev); kmem_cache_destroy(steering->ftes_cache); kmem_cache_destroy(steering->fgs_cache); @@ -2558,6 +2565,20 @@ cleanup_root_ns: return err; } +static int init_egress_root_ns(struct mlx5_flow_steering *steering) +{ + struct fs_prio *prio; + + steering->egress_root_ns = create_root_ns(steering, + FS_FT_NIC_TX); + if (!steering->egress_root_ns) + return -ENOMEM; + + /* create 1 prio*/ + prio = fs_create_prio(&steering->egress_root_ns->ns, 0, 1); + return PTR_ERR_OR_ZERO(prio); +} + int mlx5_init_fs(struct mlx5_core_dev *dev) { struct mlx5_flow_steering *steering; @@ -2623,6 +2644,13 @@ int mlx5_init_fs(struct mlx5_core_dev *dev) goto err; } + if (mlx5_accel_ipsec_device_caps(steering->dev) & + MLX5_ACCEL_IPSEC_DEVICE) { + err = init_egress_root_ns(steering); + if (err) + goto err; + } + return 0; err: mlx5_cleanup_fs(dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h index 45791c792296..8586af9ce514 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -48,6 +48,7 @@ enum fs_node_type { enum fs_flow_table_type { FS_FT_NIC_RX = 0x0, + FS_FT_NIC_TX = 0x1, FS_FT_ESW_EGRESS_ACL = 0x2, FS_FT_ESW_INGRESS_ACL = 0x3, FS_FT_FDB = 0X4, @@ -75,6 +76,7 @@ struct mlx5_flow_steering { struct mlx5_flow_root_namespace **esw_ingress_root_ns; struct mlx5_flow_root_namespace *sniffer_tx_root_ns; struct mlx5_flow_root_namespace *sniffer_rx_root_ns; + struct mlx5_flow_root_namespace *egress_root_ns; }; struct fs_node { diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h index f580bc4c2443..744ea228acea 100644 --- a/include/linux/mlx5/fs.h +++ b/include/linux/mlx5/fs.h @@ -69,6 +69,7 @@ enum mlx5_flow_namespace_type { MLX5_FLOW_NAMESPACE_ESW_INGRESS, MLX5_FLOW_NAMESPACE_SNIFFER_RX, MLX5_FLOW_NAMESPACE_SNIFFER_TX, + MLX5_FLOW_NAMESPACE_EGRESS, }; struct mlx5_flow_table; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index f4e417686f62..9bc4ea0cf5a9 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1091,6 +1091,7 @@ enum mlx5_flow_destination_type { MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, + MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, }; -- cgit v1.2.3 From 3346c4873733a109bea29467308a754038b886a9 Mon Sep 17 00:00:00 2001 From: Boris Pismenny Date: Sun, 20 Aug 2017 15:13:08 +0300 Subject: {net,IB}/mlx5: Add flow steering helpers Add helper functions that check if a protocol is part of a flow steering match criteria. Signed-off-by: Boris Pismenny Signed-off-by: Matan Barak Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- drivers/infiniband/hw/mlx5/main.c | 7 +- include/linux/mlx5/fs_helpers.h | 134 ++++++++++++++++++++++++++++++++++++++ include/linux/mlx5/mlx5_ifc.h | 8 ++- 3 files changed, 143 insertions(+), 6 deletions(-) create mode 100644 include/linux/mlx5/fs_helpers.h (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index d50ace805995..d9474b95d8e5 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -59,6 +59,7 @@ #include "mlx5_ib.h" #include "ib_rep.h" #include "cmd.h" +#include #define DRIVER_NAME "mlx5_ib" #define DRIVER_VERSION "5.0-0" @@ -2312,8 +2313,6 @@ static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) offsetof(typeof(filter), field) -\ sizeof(filter.field)) -#define IPV4_VERSION 4 -#define IPV6_VERSION 6 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, u32 *match_v, const union ib_flow_spec *ib_spec, struct mlx5_flow_act *action) @@ -2399,7 +2398,7 @@ static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_version, 0xf); MLX5_SET(fte_match_set_lyr_2_4, headers_v, - ip_version, IPV4_VERSION); + ip_version, MLX5_FS_IPV4_VERSION); } else { MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype, 0xffff); @@ -2438,7 +2437,7 @@ static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_version, 0xf); MLX5_SET(fte_match_set_lyr_2_4, headers_v, - ip_version, IPV6_VERSION); + ip_version, MLX5_FS_IPV6_VERSION); } else { MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype, 0xffff); diff --git a/include/linux/mlx5/fs_helpers.h b/include/linux/mlx5/fs_helpers.h new file mode 100644 index 000000000000..7b476bbae731 --- /dev/null +++ b/include/linux/mlx5/fs_helpers.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2018, Mellanox Technologies. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _MLX5_FS_HELPERS_ +#define _MLX5_FS_HELPERS_ + +#include + +#define MLX5_FS_IPV4_VERSION 4 +#define MLX5_FS_IPV6_VERSION 6 + +static inline bool _mlx5_fs_is_outer_ipproto_flow(const u32 *match_c, + const u32 *match_v, u8 match) +{ + const void *headers_c = MLX5_ADDR_OF(fte_match_param, match_c, + outer_headers); + const void *headers_v = MLX5_ADDR_OF(fte_match_param, match_v, + outer_headers); + + return MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_protocol) == 0xff && + MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol) == match; +} + +static inline bool mlx5_fs_is_outer_tcp_flow(const u32 *match_c, + const u32 *match_v) +{ + return _mlx5_fs_is_outer_ipproto_flow(match_c, match_v, IPPROTO_TCP); +} + +static inline bool mlx5_fs_is_outer_udp_flow(const u32 *match_c, + const u32 *match_v) +{ + return _mlx5_fs_is_outer_ipproto_flow(match_c, match_v, IPPROTO_UDP); +} + +static inline bool mlx5_fs_is_vxlan_flow(const u32 *match_c) +{ + void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, + misc_parameters); + + return MLX5_GET(fte_match_set_misc, misc_params_c, vxlan_vni); +} + +static inline bool _mlx5_fs_is_outer_ipv_flow(struct mlx5_core_dev *mdev, + const u32 *match_c, + const u32 *match_v, int version) +{ + int match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, + ft_field_support.outer_ip_version); + const void *headers_c = MLX5_ADDR_OF(fte_match_param, match_c, + outer_headers); + const void *headers_v = MLX5_ADDR_OF(fte_match_param, match_v, + outer_headers); + + if (!match_ipv) { + u16 ethertype; + + switch (version) { + case MLX5_FS_IPV4_VERSION: + ethertype = ETH_P_IP; + break; + case MLX5_FS_IPV6_VERSION: + ethertype = ETH_P_IPV6; + break; + default: + return false; + } + + return MLX5_GET(fte_match_set_lyr_2_4, headers_c, + ethertype) == 0xffff && + MLX5_GET(fte_match_set_lyr_2_4, headers_v, + ethertype) == ethertype; + } + + return MLX5_GET(fte_match_set_lyr_2_4, headers_c, + ip_version) == 0xf && + MLX5_GET(fte_match_set_lyr_2_4, headers_v, + ip_version) == version; +} + +static inline bool +mlx5_fs_is_outer_ipv4_flow(struct mlx5_core_dev *mdev, const u32 *match_c, + const u32 *match_v) +{ + return _mlx5_fs_is_outer_ipv_flow(mdev, match_c, match_v, + MLX5_FS_IPV4_VERSION); +} + +static inline bool +mlx5_fs_is_outer_ipv6_flow(struct mlx5_core_dev *mdev, const u32 *match_c, + const u32 *match_v) +{ + return _mlx5_fs_is_outer_ipv_flow(mdev, match_c, match_v, + MLX5_FS_IPV6_VERSION); +} + +static inline bool mlx5_fs_is_outer_ipsec_flow(const u32 *match_c) +{ + void *misc_params_c = + MLX5_ADDR_OF(fte_match_param, match_c, misc_parameters); + + return MLX5_GET(fte_match_set_misc, misc_params_c, outer_esp_spi); +} + +#endif diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 9bc4ea0cf5a9..14ad84afe8ba 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -295,7 +295,9 @@ struct mlx5_ifc_flow_table_fields_supported_bits { u8 inner_tcp_dport[0x1]; u8 inner_tcp_flags[0x1]; u8 reserved_at_37[0x9]; - u8 reserved_at_40[0x1a]; + u8 reserved_at_40[0x17]; + u8 outer_esp_spi[0x1]; + u8 reserved_at_58[0x2]; u8 bth_dst_qp[0x1]; u8 reserved_at_5b[0x25]; @@ -437,7 +439,9 @@ struct mlx5_ifc_fte_match_set_misc_bits { u8 reserved_at_120[0x28]; u8 bth_dst_qp[0x18]; - u8 reserved_at_160[0xa0]; + u8 reserved_at_160[0x20]; + u8 outer_esp_spi[0x20]; + u8 reserved_at_1a0[0x60]; }; struct mlx5_ifc_cmd_pas_bits { -- cgit v1.2.3 From d3dcf8eb615537526bd42ff27a081d46d337816e Mon Sep 17 00:00:00 2001 From: Paul Blakey Date: Sun, 4 Mar 2018 17:29:48 +0200 Subject: rhashtable: Fix rhlist duplicates insertion When inserting duplicate objects (those with the same key), current rhlist implementation messes up the chain pointers by updating the bucket pointer instead of prev next pointer to the newly inserted node. This causes missing elements on removal and travesal. Fix that by properly updating pprev pointer to point to the correct rhash_head next pointer. Issue: 1241076 Change-Id: I86b2c140bcb4aeb10b70a72a267ff590bb2b17e7 Fixes: ca26893f05e8 ('rhashtable: Add rhlist interface') Signed-off-by: Paul Blakey Acked-by: Herbert Xu Signed-off-by: David S. Miller --- include/linux/rhashtable.h | 4 +++- lib/rhashtable.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/rhashtable.h b/include/linux/rhashtable.h index c9df2527e0cd..668a21f04b09 100644 --- a/include/linux/rhashtable.h +++ b/include/linux/rhashtable.h @@ -766,8 +766,10 @@ slow_path: if (!key || (params.obj_cmpfn ? params.obj_cmpfn(&arg, rht_obj(ht, head)) : - rhashtable_compare(&arg, rht_obj(ht, head)))) + rhashtable_compare(&arg, rht_obj(ht, head)))) { + pprev = &head->next; continue; + } data = rht_obj(ht, head); diff --git a/lib/rhashtable.c b/lib/rhashtable.c index 3825c30aaa36..47de025b6245 100644 --- a/lib/rhashtable.c +++ b/lib/rhashtable.c @@ -506,8 +506,10 @@ static void *rhashtable_lookup_one(struct rhashtable *ht, if (!key || (ht->p.obj_cmpfn ? ht->p.obj_cmpfn(&arg, rht_obj(ht, head)) : - rhashtable_compare(&arg, rht_obj(ht, head)))) + rhashtable_compare(&arg, rht_obj(ht, head)))) { + pprev = &head->next; continue; + } if (!ht->rhlist) return rht_obj(ht, head); -- cgit v1.2.3 From 2695578b896aea472b2c0dcbe9d92daa71738484 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 5 Mar 2018 11:41:13 -0800 Subject: net: usbnet: fix potential deadlock on 32bit hosts Marek reported a LOCKDEP issue occurring on 32bit host, that we tracked down to the fact that usbnet could either run from soft or hard irqs. This patch adds u64_stats_update_begin_irqsave() and u64_stats_update_end_irqrestore() helpers to solve this case. [ 17.768040] ================================ [ 17.772239] WARNING: inconsistent lock state [ 17.776511] 4.16.0-rc3-next-20180227-00007-g876c53a7493c #453 Not tainted [ 17.783329] -------------------------------- [ 17.787580] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. [ 17.793607] swapper/0/0 [HC0[0]:SC1[1]:HE1:SE0] takes: [ 17.798751] (&syncp->seq#5){?.-.}, at: [<9b22e5f0>] asix_rx_fixup_internal+0x188/0x288 [ 17.806790] {IN-HARDIRQ-W} state was registered at: [ 17.811677] tx_complete+0x100/0x208 [ 17.815319] __usb_hcd_giveback_urb+0x60/0xf0 [ 17.819770] xhci_giveback_urb_in_irq+0xa8/0x240 [ 17.824469] xhci_td_cleanup+0xf4/0x16c [ 17.828367] xhci_irq+0xe74/0x2240 [ 17.831827] usb_hcd_irq+0x24/0x38 [ 17.835343] __handle_irq_event_percpu+0x98/0x510 [ 17.840111] handle_irq_event_percpu+0x1c/0x58 [ 17.844623] handle_irq_event+0x38/0x5c [ 17.848519] handle_fasteoi_irq+0xa4/0x138 [ 17.852681] generic_handle_irq+0x18/0x28 [ 17.856760] __handle_domain_irq+0x6c/0xe4 [ 17.860941] gic_handle_irq+0x54/0xa0 [ 17.864666] __irq_svc+0x70/0xb0 [ 17.867964] arch_cpu_idle+0x20/0x3c [ 17.871578] arch_cpu_idle+0x20/0x3c [ 17.875190] do_idle+0x144/0x218 [ 17.878468] cpu_startup_entry+0x18/0x1c [ 17.882454] start_kernel+0x394/0x400 [ 17.886177] irq event stamp: 161912 [ 17.889616] hardirqs last enabled at (161912): [<7bedfacf>] __netdev_alloc_skb+0xcc/0x140 [ 17.897893] hardirqs last disabled at (161911): [] __netdev_alloc_skb+0x94/0x140 [ 17.904903] exynos5-hsi2c 12ca0000.i2c: tx timeout [ 17.906116] softirqs last enabled at (161904): [<387102ff>] irq_enter+0x78/0x80 [ 17.906123] softirqs last disabled at (161905): [] irq_exit+0x134/0x158 [ 17.925722]. [ 17.925722] other info that might help us debug this: [ 17.933435] Possible unsafe locking scenario: [ 17.933435]. [ 17.940331] CPU0 [ 17.942488] ---- [ 17.944894] lock(&syncp->seq#5); [ 17.948274] [ 17.950847] lock(&syncp->seq#5); [ 17.954386]. [ 17.954386] *** DEADLOCK *** [ 17.954386]. [ 17.962422] no locks held by swapper/0/0. Fixes: c8b5d129ee29 ("net: usbnet: support 64bit stats") Signed-off-by: Eric Dumazet Reported-by: Marek Szyprowski Cc: Greg Ungerer Signed-off-by: David S. Miller --- drivers/net/usb/usbnet.c | 10 ++++++---- include/linux/u64_stats_sync.h | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c index 8a22ff67b026..d9eea8cfe6cb 100644 --- a/drivers/net/usb/usbnet.c +++ b/drivers/net/usb/usbnet.c @@ -315,6 +315,7 @@ static void __usbnet_status_stop_force(struct usbnet *dev) void usbnet_skb_return (struct usbnet *dev, struct sk_buff *skb) { struct pcpu_sw_netstats *stats64 = this_cpu_ptr(dev->stats64); + unsigned long flags; int status; if (test_bit(EVENT_RX_PAUSED, &dev->flags)) { @@ -326,10 +327,10 @@ void usbnet_skb_return (struct usbnet *dev, struct sk_buff *skb) if (skb->protocol == 0) skb->protocol = eth_type_trans (skb, dev->net); - u64_stats_update_begin(&stats64->syncp); + flags = u64_stats_update_begin_irqsave(&stats64->syncp); stats64->rx_packets++; stats64->rx_bytes += skb->len; - u64_stats_update_end(&stats64->syncp); + u64_stats_update_end_irqrestore(&stats64->syncp, flags); netif_dbg(dev, rx_status, dev->net, "< rx, len %zu, type 0x%x\n", skb->len + sizeof (struct ethhdr), skb->protocol); @@ -1248,11 +1249,12 @@ static void tx_complete (struct urb *urb) if (urb->status == 0) { struct pcpu_sw_netstats *stats64 = this_cpu_ptr(dev->stats64); + unsigned long flags; - u64_stats_update_begin(&stats64->syncp); + flags = u64_stats_update_begin_irqsave(&stats64->syncp); stats64->tx_packets += entry->packets; stats64->tx_bytes += entry->length; - u64_stats_update_end(&stats64->syncp); + u64_stats_update_end_irqrestore(&stats64->syncp, flags); } else { dev->net->stats.tx_errors++; diff --git a/include/linux/u64_stats_sync.h b/include/linux/u64_stats_sync.h index 5bdbd9f49395..07ee0f84a46c 100644 --- a/include/linux/u64_stats_sync.h +++ b/include/linux/u64_stats_sync.h @@ -90,6 +90,28 @@ static inline void u64_stats_update_end(struct u64_stats_sync *syncp) #endif } +static inline unsigned long +u64_stats_update_begin_irqsave(struct u64_stats_sync *syncp) +{ + unsigned long flags = 0; + +#if BITS_PER_LONG==32 && defined(CONFIG_SMP) + local_irq_save(flags); + write_seqcount_begin(&syncp->seq); +#endif + return flags; +} + +static inline void +u64_stats_update_end_irqrestore(struct u64_stats_sync *syncp, + unsigned long flags) +{ +#if BITS_PER_LONG==32 && defined(CONFIG_SMP) + write_seqcount_end(&syncp->seq); + local_irq_restore(flags); +#endif +} + static inline void u64_stats_update_begin_raw(struct u64_stats_sync *syncp) { #if BITS_PER_LONG==32 && defined(CONFIG_SMP) -- cgit v1.2.3 From 1ec54cb44e6731c3cb251bcf9251d65a4b4f6306 Mon Sep 17 00:00:00 2001 From: Paolo Abeni Date: Tue, 6 Mar 2018 10:56:31 +0100 Subject: net: unpollute priv_flags space the ipvlan device driver defines and uses 2 bits inside the priv_flags net_device field. Such bits and the related helper are used only inside the ipvlan device driver, and the core networking does not need to be aware of them. This change moves netif_is_ipvlan* helper in the ipvlan driver and re-implement them looking for ipvlan specific symbols instead of using priv_flags. Overall this frees two bits inside priv_flags - and move the following ones to avoid gaps - without any intended functional change. Signed-off-by: Paolo Abeni Signed-off-by: David S. Miller --- drivers/net/ipvlan/ipvlan.h | 6 ++++++ drivers/net/ipvlan/ipvlan_main.c | 10 ++++++---- include/linux/netdevice.h | 32 ++++++++------------------------ 3 files changed, 20 insertions(+), 28 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ipvlan/ipvlan.h b/drivers/net/ipvlan/ipvlan.h index a115f12bf130..c818b9bdab6e 100644 --- a/drivers/net/ipvlan/ipvlan.h +++ b/drivers/net/ipvlan/ipvlan.h @@ -177,4 +177,10 @@ int ipvlan_link_new(struct net *src_net, struct net_device *dev, void ipvlan_link_delete(struct net_device *dev, struct list_head *head); void ipvlan_link_setup(struct net_device *dev); int ipvlan_link_register(struct rtnl_link_ops *ops); + +static inline bool netif_is_ipvlan_port(const struct net_device *dev) +{ + return dev->rx_handler == ipvlan_handle_frame; +} + #endif /* __IPVLAN_H */ diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c index 4cbe9e27287d..23fd5ab180e8 100644 --- a/drivers/net/ipvlan/ipvlan_main.c +++ b/drivers/net/ipvlan/ipvlan_main.c @@ -129,7 +129,6 @@ static int ipvlan_port_create(struct net_device *dev) if (err) goto err; - dev->priv_flags |= IFF_IPVLAN_MASTER; return 0; err: @@ -142,7 +141,6 @@ static void ipvlan_port_destroy(struct net_device *dev) struct ipvl_port *port = ipvlan_port_get_rtnl(dev); struct sk_buff *skb; - dev->priv_flags &= ~IFF_IPVLAN_MASTER; if (port->mode == IPVLAN_MODE_L3S) { dev->priv_flags &= ~IFF_L3MDEV_MASTER; ipvlan_unregister_nf_hook(dev_net(dev)); @@ -423,6 +421,12 @@ static const struct header_ops ipvlan_header_ops = { .cache_update = eth_header_cache_update, }; +static bool netif_is_ipvlan(const struct net_device *dev) +{ + /* both ipvlan and ipvtap devices use the same netdev_ops */ + return dev->netdev_ops == &ipvlan_netdev_ops; +} + static int ipvlan_ethtool_get_link_ksettings(struct net_device *dev, struct ethtool_link_ksettings *cmd) { @@ -600,8 +604,6 @@ int ipvlan_link_new(struct net *src_net, struct net_device *dev, */ memcpy(dev->dev_addr, phy_dev->dev_addr, ETH_ALEN); - dev->priv_flags |= IFF_IPVLAN_SLAVE; - err = register_netdevice(dev); if (err < 0) return err; diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index dbe6344b727a..95a613a7cc1c 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1381,8 +1381,6 @@ struct net_device_ops { * @IFF_MACVLAN: Macvlan device * @IFF_XMIT_DST_RELEASE_PERM: IFF_XMIT_DST_RELEASE not taking into account * underlying stacked devices - * @IFF_IPVLAN_MASTER: IPvlan master device - * @IFF_IPVLAN_SLAVE: IPvlan slave device * @IFF_L3MDEV_MASTER: device is an L3 master device * @IFF_NO_QUEUE: device can run without qdisc attached * @IFF_OPENVSWITCH: device is a Open vSwitch master @@ -1412,16 +1410,14 @@ enum netdev_priv_flags { IFF_LIVE_ADDR_CHANGE = 1<<15, IFF_MACVLAN = 1<<16, IFF_XMIT_DST_RELEASE_PERM = 1<<17, - IFF_IPVLAN_MASTER = 1<<18, - IFF_IPVLAN_SLAVE = 1<<19, - IFF_L3MDEV_MASTER = 1<<20, - IFF_NO_QUEUE = 1<<21, - IFF_OPENVSWITCH = 1<<22, - IFF_L3MDEV_SLAVE = 1<<23, - IFF_TEAM = 1<<24, - IFF_RXFH_CONFIGURED = 1<<25, - IFF_PHONY_HEADROOM = 1<<26, - IFF_MACSEC = 1<<27, + IFF_L3MDEV_MASTER = 1<<18, + IFF_NO_QUEUE = 1<<19, + IFF_OPENVSWITCH = 1<<20, + IFF_L3MDEV_SLAVE = 1<<21, + IFF_TEAM = 1<<22, + IFF_RXFH_CONFIGURED = 1<<23, + IFF_PHONY_HEADROOM = 1<<24, + IFF_MACSEC = 1<<25, }; #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN @@ -1442,8 +1438,6 @@ enum netdev_priv_flags { #define IFF_LIVE_ADDR_CHANGE IFF_LIVE_ADDR_CHANGE #define IFF_MACVLAN IFF_MACVLAN #define IFF_XMIT_DST_RELEASE_PERM IFF_XMIT_DST_RELEASE_PERM -#define IFF_IPVLAN_MASTER IFF_IPVLAN_MASTER -#define IFF_IPVLAN_SLAVE IFF_IPVLAN_SLAVE #define IFF_L3MDEV_MASTER IFF_L3MDEV_MASTER #define IFF_NO_QUEUE IFF_NO_QUEUE #define IFF_OPENVSWITCH IFF_OPENVSWITCH @@ -4223,16 +4217,6 @@ static inline bool netif_is_macvlan_port(const struct net_device *dev) return dev->priv_flags & IFF_MACVLAN_PORT; } -static inline bool netif_is_ipvlan(const struct net_device *dev) -{ - return dev->priv_flags & IFF_IPVLAN_SLAVE; -} - -static inline bool netif_is_ipvlan_port(const struct net_device *dev) -{ - return dev->priv_flags & IFF_IPVLAN_MASTER; -} - static inline bool netif_is_bond_master(const struct net_device *dev) { return dev->flags & IFF_MASTER && dev->priv_flags & IFF_BONDING; -- cgit v1.2.3 From f2531f1976d98a7a4328da7f3cbf31b7c1927738 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 7 Mar 2018 12:18:33 -0800 Subject: pstore/ram: Do not use stack VLA for parity workspace Instead of using a stack VLA for the parity workspace, preallocate a memory region. The preallocation is done to keep from needing to perform allocations during crash dump writing, etc. This also fixes a missed release of librs on free. Signed-off-by: Kees Cook --- fs/pstore/ram_core.c | 29 ++++++++++++++++++++++------- include/linux/pstore_ram.h | 1 + 2 files changed, 23 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/fs/pstore/ram_core.c b/fs/pstore/ram_core.c index e11672aa4575..951a14edcf51 100644 --- a/fs/pstore/ram_core.c +++ b/fs/pstore/ram_core.c @@ -98,24 +98,23 @@ static void notrace persistent_ram_encode_rs8(struct persistent_ram_zone *prz, uint8_t *data, size_t len, uint8_t *ecc) { int i; - uint16_t par[prz->ecc_info.ecc_size]; /* Initialize the parity buffer */ - memset(par, 0, sizeof(par)); - encode_rs8(prz->rs_decoder, data, len, par, 0); + memset(prz->ecc_info.par, 0, + prz->ecc_info.ecc_size * sizeof(prz->ecc_info.par[0])); + encode_rs8(prz->rs_decoder, data, len, prz->ecc_info.par, 0); for (i = 0; i < prz->ecc_info.ecc_size; i++) - ecc[i] = par[i]; + ecc[i] = prz->ecc_info.par[i]; } static int persistent_ram_decode_rs8(struct persistent_ram_zone *prz, void *data, size_t len, uint8_t *ecc) { int i; - uint16_t par[prz->ecc_info.ecc_size]; for (i = 0; i < prz->ecc_info.ecc_size; i++) - par[i] = ecc[i]; - return decode_rs8(prz->rs_decoder, data, par, len, + prz->ecc_info.par[i] = ecc[i]; + return decode_rs8(prz->rs_decoder, data, prz->ecc_info.par, len, NULL, 0, NULL, 0, NULL); } @@ -228,6 +227,15 @@ static int persistent_ram_init_ecc(struct persistent_ram_zone *prz, return -EINVAL; } + /* allocate workspace instead of using stack VLA */ + prz->ecc_info.par = kmalloc_array(prz->ecc_info.ecc_size, + sizeof(*prz->ecc_info.par), + GFP_KERNEL); + if (!prz->ecc_info.par) { + pr_err("cannot allocate ECC parity workspace\n"); + return -ENOMEM; + } + prz->corrected_bytes = 0; prz->bad_blocks = 0; @@ -514,6 +522,13 @@ void persistent_ram_free(struct persistent_ram_zone *prz) } prz->vaddr = NULL; } + if (prz->rs_decoder) { + free_rs(prz->rs_decoder); + prz->rs_decoder = NULL; + } + kfree(prz->ecc_info.par); + prz->ecc_info.par = NULL; + persistent_ram_free_old(prz); kfree(prz); } diff --git a/include/linux/pstore_ram.h b/include/linux/pstore_ram.h index 9395f06e8372..e6d226464838 100644 --- a/include/linux/pstore_ram.h +++ b/include/linux/pstore_ram.h @@ -39,6 +39,7 @@ struct persistent_ram_ecc_info { int ecc_size; int symsize; int poly; + uint16_t *par; }; struct persistent_ram_zone { -- cgit v1.2.3 From 581fdddee420cebe2cb781cb3c84c82676a86949 Mon Sep 17 00:00:00 2001 From: Yossi Kuperman Date: Sun, 22 Oct 2017 19:43:58 +0300 Subject: net/mlx5: IPSec, Generalize sandbox QP commands The current code assume only SA QP commands. Refactor in order to pave the way for new QP commands: 1. Generic cmd response format. 2. SA cmd checks are in dedicated functions. 3. Aligned debug prints. Signed-off-by: Yossi Kuperman Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 116 ++++++++++++--------- include/linux/mlx5/mlx5_ifc_fpga.h | 16 +++ 2 files changed, 81 insertions(+), 51 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index 95f9c5a8619b..e0f32b025e06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -41,35 +41,23 @@ #define SBU_QP_QUEUE_SIZE 8 #define MLX5_FPGA_IPSEC_CMD_TIMEOUT_MSEC (60 * 1000) -enum mlx5_ipsec_response_syndrome { - MLX5_IPSEC_RESPONSE_SUCCESS = 0, - MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1, - MLX5_IPSEC_RESPONSE_SADB_ISSUE = 2, - MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3, -}; - -enum mlx5_fpga_ipsec_sacmd_status { - MLX5_FPGA_IPSEC_SACMD_PENDING, - MLX5_FPGA_IPSEC_SACMD_SEND_FAIL, - MLX5_FPGA_IPSEC_SACMD_COMPLETE, +enum mlx5_fpga_ipsec_cmd_status { + MLX5_FPGA_IPSEC_CMD_PENDING, + MLX5_FPGA_IPSEC_CMD_SEND_FAIL, + MLX5_FPGA_IPSEC_CMD_COMPLETE, }; struct mlx5_ipsec_command_context { struct mlx5_fpga_dma_buf buf; - struct mlx5_accel_ipsec_sa sa; - enum mlx5_fpga_ipsec_sacmd_status status; + enum mlx5_fpga_ipsec_cmd_status status; + struct mlx5_ifc_fpga_ipsec_cmd_resp resp; int status_code; struct completion complete; struct mlx5_fpga_device *dev; struct list_head list; /* Item in pending_cmds */ + u8 command[0]; }; -struct mlx5_ipsec_sadb_resp { - __be32 syndrome; - __be32 sw_sa_handle; - u8 reserved[24]; -} __packed; - struct mlx5_fpga_ipsec { struct list_head pending_cmds; spinlock_t pending_cmds_lock; /* Protects pending_cmds */ @@ -105,21 +93,22 @@ static void mlx5_fpga_ipsec_send_complete(struct mlx5_fpga_conn *conn, buf); mlx5_fpga_warn(fdev, "IPSec command send failed with status %u\n", status); - context->status = MLX5_FPGA_IPSEC_SACMD_SEND_FAIL; + context->status = MLX5_FPGA_IPSEC_CMD_SEND_FAIL; complete(&context->complete); } } -static inline int syndrome_to_errno(enum mlx5_ipsec_response_syndrome syndrome) +static inline +int syndrome_to_errno(enum mlx5_ifc_fpga_ipsec_response_syndrome syndrome) { switch (syndrome) { - case MLX5_IPSEC_RESPONSE_SUCCESS: + case MLX5_FPGA_IPSEC_RESPONSE_SUCCESS: return 0; - case MLX5_IPSEC_RESPONSE_SADB_ISSUE: + case MLX5_FPGA_IPSEC_RESPONSE_SADB_ISSUE: return -EEXIST; - case MLX5_IPSEC_RESPONSE_ILLEGAL_REQUEST: + case MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST: return -EINVAL; - case MLX5_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE: + case MLX5_FPGA_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE: return -EIO; } return -EIO; @@ -127,9 +116,9 @@ static inline int syndrome_to_errno(enum mlx5_ipsec_response_syndrome syndrome) static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf) { - struct mlx5_ipsec_sadb_resp *resp = buf->sg[0].data; + struct mlx5_ifc_fpga_ipsec_cmd_resp *resp = buf->sg[0].data; struct mlx5_ipsec_command_context *context; - enum mlx5_ipsec_response_syndrome syndrome; + enum mlx5_ifc_fpga_ipsec_response_syndrome syndrome; struct mlx5_fpga_device *fdev = cb_arg; unsigned long flags; @@ -139,8 +128,8 @@ static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf) return; } - mlx5_fpga_dbg(fdev, "mlx5_ipsec recv_cb syndrome %08x sa_id %x\n", - ntohl(resp->syndrome), ntohl(resp->sw_sa_handle)); + mlx5_fpga_dbg(fdev, "mlx5_ipsec recv_cb syndrome %08x\n", + ntohl(resp->syndrome)); spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags); context = list_first_entry_or_null(&fdev->ipsec->pending_cmds, @@ -156,51 +145,48 @@ static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf) } mlx5_fpga_dbg(fdev, "Handling response for %p\n", context); - if (context->sa.sw_sa_handle != resp->sw_sa_handle) { - mlx5_fpga_err(fdev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n", - ntohl(context->sa.sw_sa_handle), - ntohl(resp->sw_sa_handle)); - return; - } - syndrome = ntohl(resp->syndrome); context->status_code = syndrome_to_errno(syndrome); - context->status = MLX5_FPGA_IPSEC_SACMD_COMPLETE; + context->status = MLX5_FPGA_IPSEC_CMD_COMPLETE; + memcpy(&context->resp, resp, sizeof(*resp)); if (context->status_code) - mlx5_fpga_warn(fdev, "IPSec SADB command failed with syndrome %08x\n", + mlx5_fpga_warn(fdev, "IPSec command failed with syndrome %08x\n", syndrome); + complete(&context->complete); } -void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd) +static void *mlx5_fpga_ipsec_cmd_exec(struct mlx5_core_dev *mdev, + const void *cmd, int cmd_size) { struct mlx5_ipsec_command_context *context; struct mlx5_fpga_device *fdev = mdev->fpga; unsigned long flags; - int res = 0; + int res; - BUILD_BUG_ON((sizeof(struct mlx5_accel_ipsec_sa) & 3) != 0); if (!fdev || !fdev->ipsec) return ERR_PTR(-EOPNOTSUPP); - context = kzalloc(sizeof(*context), GFP_ATOMIC); + if (cmd_size & 3) + return ERR_PTR(-EINVAL); + + context = kzalloc(sizeof(*context) + cmd_size, GFP_ATOMIC); if (!context) return ERR_PTR(-ENOMEM); - memcpy(&context->sa, cmd, sizeof(*cmd)); + context->status = MLX5_FPGA_IPSEC_CMD_PENDING; + context->dev = fdev; context->buf.complete = mlx5_fpga_ipsec_send_complete; - context->buf.sg[0].size = sizeof(context->sa); - context->buf.sg[0].data = &context->sa; init_completion(&context->complete); - context->dev = fdev; + memcpy(&context->command, cmd, cmd_size); + context->buf.sg[0].size = cmd_size; + context->buf.sg[0].data = &context->command; + spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags); list_add_tail(&context->list, &fdev->ipsec->pending_cmds); spin_unlock_irqrestore(&fdev->ipsec->pending_cmds_lock, flags); - context->status = MLX5_FPGA_IPSEC_SACMD_PENDING; - res = mlx5_fpga_sbu_conn_sendmsg(fdev->ipsec->conn, &context->buf); if (res) { mlx5_fpga_warn(fdev, "Failure sending IPSec command: %d\n", @@ -215,7 +201,7 @@ void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, return context; } -int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx) +static int mlx5_fpga_ipsec_cmd_wait(void *ctx) { struct mlx5_ipsec_command_context *context = ctx; unsigned long timeout = @@ -228,11 +214,39 @@ int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx) return -ETIMEDOUT; } - if (context->status == MLX5_FPGA_IPSEC_SACMD_COMPLETE) + if (context->status == MLX5_FPGA_IPSEC_CMD_COMPLETE) res = context->status_code; else res = -EIO; + return res; +} + +void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, + struct mlx5_accel_ipsec_sa *cmd) +{ + return mlx5_fpga_ipsec_cmd_exec(mdev, cmd, sizeof(*cmd)); +} + +int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx) +{ + struct mlx5_ipsec_command_context *context = ctx; + struct mlx5_accel_ipsec_sa *sa; + int res; + + res = mlx5_fpga_ipsec_cmd_wait(ctx); + if (res) + goto out; + + sa = (struct mlx5_accel_ipsec_sa *)&context->command; + if (sa->sw_sa_handle != context->resp.sw_sa_handle) { + mlx5_fpga_err(context->dev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n", + ntohl(sa->sw_sa_handle), + ntohl(context->resp.sw_sa_handle)); + res = -EIO; + } + +out: kfree(context); return res; } diff --git a/include/linux/mlx5/mlx5_ifc_fpga.h b/include/linux/mlx5/mlx5_ifc_fpga.h index 255a88d08078..7283fe780f93 100644 --- a/include/linux/mlx5/mlx5_ifc_fpga.h +++ b/include/linux/mlx5/mlx5_ifc_fpga.h @@ -429,4 +429,20 @@ struct mlx5_ifc_ipsec_counters_bits { u8 dropped_cmd[0x40]; }; +enum mlx5_ifc_fpga_ipsec_response_syndrome { + MLX5_FPGA_IPSEC_RESPONSE_SUCCESS = 0, + MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1, + MLX5_FPGA_IPSEC_RESPONSE_SADB_ISSUE = 2, + MLX5_FPGA_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3, +}; + +struct mlx5_ifc_fpga_ipsec_cmd_resp { + __be32 syndrome; + union { + __be32 sw_sa_handle; + __be32 flags; + }; + u8 reserved[24]; +} __packed; + #endif /* MLX5_IFC_FPGA_H */ -- cgit v1.2.3 From 788a8210764ce2977095010931959c87b60c2f51 Mon Sep 17 00:00:00 2001 From: Yossi Kuperman Date: Sun, 22 Oct 2017 19:45:45 +0300 Subject: net/mlx5e: IPSec, Add support for ESP trailer removal by hardware Current hardware decrypts and authenticates incoming ESP packets. Subsequently, the software extracts the nexthdr field, truncates the trailer and adjusts csum accordingly. With this patch and a capable device, the trailer is being removed by the hardware and the nexthdr field is conveyed via PET. This way we avoid both the need to access the trailer (cache miss) and to compute its relative checksum, which significantly improve the performance. Experiment shows that trailer removal improves the performance by 2Gbps, (netperf). Both forwarding and host-to-host configurations. Signed-off-by: Yossi Kuperman Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.h | 2 + .../ethernet/mellanox/mlx5/core/en_accel/ipsec.c | 2 + .../ethernet/mellanox/mlx5/core/en_accel/ipsec.h | 1 + .../mellanox/mlx5/core/en_accel/ipsec_rxtx.c | 10 +++- .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 54 ++++++++++++++++++++++ include/linux/mlx5/mlx5_ifc_fpga.h | 13 +++++- 6 files changed, 80 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h index 67cda8871f5a..4da9611a753d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h @@ -43,6 +43,7 @@ enum { MLX5_ACCEL_IPSEC_IPV6 = BIT(2), MLX5_ACCEL_IPSEC_ESP = BIT(3), MLX5_ACCEL_IPSEC_LSO = BIT(4), + MLX5_ACCEL_IPSEC_NO_TRAILER = BIT(5), }; #define MLX5_IPSEC_SADB_IP_AH BIT(7) @@ -55,6 +56,7 @@ enum { enum { MLX5_IPSEC_CMD_ADD_SA = 0, MLX5_IPSEC_CMD_DEL_SA = 1, + MLX5_IPSEC_CMD_SET_CAP = 5, }; enum mlx5_accel_ipsec_enc_mode { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 1b49afca65c0..460a613059fe 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -378,6 +378,8 @@ int mlx5e_ipsec_init(struct mlx5e_priv *priv) ida_init(&ipsec->halloc); ipsec->en_priv = priv; ipsec->en_priv->ipsec = ipsec; + ipsec->no_trailer = !!(mlx5_accel_ipsec_device_caps(priv->mdev) & + MLX5_ACCEL_IPSEC_NO_TRAILER); netdev_dbg(priv->netdev, "IPSec attached to netdevice\n"); return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index 56e00baf16cc..bffc3ed0574a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -77,6 +77,7 @@ struct mlx5e_ipsec_stats { struct mlx5e_ipsec { struct mlx5e_priv *en_priv; DECLARE_HASHTABLE(sadb_rx, MLX5E_IPSEC_SADB_RX_BITS); + bool no_trailer; spinlock_t sadb_rx_lock; /* Protects sadb_rx and halloc */ struct ida halloc; struct mlx5e_ipsec_sw_stats sw_stats; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c index 6a7c8b04447e..64c549a06678 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c @@ -42,10 +42,11 @@ enum { MLX5E_IPSEC_RX_SYNDROME_DECRYPTED = 0x11, MLX5E_IPSEC_RX_SYNDROME_AUTH_FAILED = 0x12, + MLX5E_IPSEC_RX_SYNDROME_BAD_PROTO = 0x17, }; struct mlx5e_ipsec_rx_metadata { - unsigned char reserved; + unsigned char nexthdr; __be32 sa_handle; } __packed; @@ -301,10 +302,17 @@ mlx5e_ipsec_build_sp(struct net_device *netdev, struct sk_buff *skb, switch (mdata->syndrome) { case MLX5E_IPSEC_RX_SYNDROME_DECRYPTED: xo->status = CRYPTO_SUCCESS; + if (likely(priv->ipsec->no_trailer)) { + xo->flags |= XFRM_ESP_NO_TRAILER; + xo->proto = mdata->content.rx.nexthdr; + } break; case MLX5E_IPSEC_RX_SYNDROME_AUTH_FAILED: xo->status = CRYPTO_TUNNEL_ESP_AUTH_FAILED; break; + case MLX5E_IPSEC_RX_SYNDROME_BAD_PROTO: + xo->status = CRYPTO_INVALID_PROTOCOL; + break; default: atomic64_inc(&priv->ipsec->sw_stats.ipsec_rx_drop_syndrome); return NULL; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index e0f32b025e06..3b10d46dc821 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -273,6 +273,9 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, lso)) ret |= MLX5_ACCEL_IPSEC_LSO; + if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, rx_no_trailer)) + ret |= MLX5_ACCEL_IPSEC_NO_TRAILER; + return ret; } @@ -335,6 +338,46 @@ out: return ret; } +static int mlx5_fpga_ipsec_set_caps(struct mlx5_core_dev *mdev, u32 flags) +{ + struct mlx5_ipsec_command_context *context; + struct mlx5_ifc_fpga_ipsec_cmd_cap cmd = {0}; + int err; + + cmd.cmd = htonl(MLX5_IPSEC_CMD_SET_CAP); + cmd.flags = htonl(flags); + context = mlx5_fpga_ipsec_cmd_exec(mdev, &cmd, sizeof(cmd)); + if (IS_ERR(context)) { + err = PTR_ERR(context); + goto out; + } + + err = mlx5_fpga_ipsec_cmd_wait(context); + if (err) + goto out; + + if ((context->resp.flags & cmd.flags) != cmd.flags) { + mlx5_fpga_err(context->dev, "Failed to set capabilities. cmd 0x%08x vs resp 0x%08x\n", + cmd.flags, + context->resp.flags); + err = -EIO; + } + +out: + return err; +} + +static int mlx5_fpga_ipsec_enable_supported_caps(struct mlx5_core_dev *mdev) +{ + u32 dev_caps = mlx5_fpga_ipsec_device_caps(mdev); + u32 flags = 0; + + if (dev_caps & MLX5_ACCEL_IPSEC_NO_TRAILER) + flags |= MLX5_FPGA_IPSEC_CAP_NO_TRAILER; + + return mlx5_fpga_ipsec_set_caps(mdev, flags); +} + int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) { struct mlx5_fpga_conn_attr init_attr = {0}; @@ -372,8 +415,19 @@ int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) goto error; } fdev->ipsec->conn = conn; + + err = mlx5_fpga_ipsec_enable_supported_caps(mdev); + if (err) { + mlx5_fpga_err(fdev, "Failed to enable IPSec extended capabilities: %d\n", + err); + goto err_destroy_conn; + } + return 0; +err_destroy_conn: + mlx5_fpga_sbu_conn_destroy(conn); + error: kfree(fdev->ipsec); fdev->ipsec = NULL; diff --git a/include/linux/mlx5/mlx5_ifc_fpga.h b/include/linux/mlx5/mlx5_ifc_fpga.h index 7283fe780f93..643544db180b 100644 --- a/include/linux/mlx5/mlx5_ifc_fpga.h +++ b/include/linux/mlx5/mlx5_ifc_fpga.h @@ -373,7 +373,8 @@ struct mlx5_ifc_fpga_destroy_qp_out_bits { struct mlx5_ifc_ipsec_extended_cap_bits { u8 encapsulation[0x20]; - u8 reserved_0[0x15]; + u8 reserved_0[0x14]; + u8 rx_no_trailer[0x1]; u8 ipv4_fragment[0x1]; u8 ipv6[0x1]; u8 esn[0x1]; @@ -445,4 +446,14 @@ struct mlx5_ifc_fpga_ipsec_cmd_resp { u8 reserved[24]; } __packed; +enum mlx5_ifc_fpga_ipsec_cap { + MLX5_FPGA_IPSEC_CAP_NO_TRAILER = BIT(0), +}; + +struct mlx5_ifc_fpga_ipsec_cmd_cap { + __be32 cmd; + __be32 flags; + u8 reserved[24]; +} __packed; + #endif /* MLX5_IFC_FPGA_H */ -- cgit v1.2.3 From 65802f480008066636a43173b12388bb3fb7bd3a Mon Sep 17 00:00:00 2001 From: Aviad Yehezkel Date: Tue, 16 Jan 2018 16:12:22 +0200 Subject: net/mlx5: IPSec, Add command V2 support This patch adds V2 command support. New fpga devices support extended features (udp encap, esn etc...), this features require new hardware sadb format therefore we have a new version of commands to manipulate it. Signed-off-by: Yossef Efraim Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.c | 9 +++- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.h | 21 ++++++-- .../ethernet/mellanox/mlx5/core/en_accel/ipsec.c | 60 ++++++++++------------ .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 11 ++-- .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.h | 5 +- include/linux/mlx5/mlx5_ifc_fpga.h | 4 +- 6 files changed, 66 insertions(+), 44 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c index 53e69edaedde..b88ae12d9066 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c @@ -40,10 +40,17 @@ void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, struct mlx5_accel_ipsec_sa *cmd) { + int cmd_size; + if (!MLX5_IPSEC_DEV(mdev)) return ERR_PTR(-EOPNOTSUPP); - return mlx5_fpga_ipsec_sa_cmd_exec(mdev, cmd); + if (mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_V2_CMD) + cmd_size = sizeof(*cmd); + else + cmd_size = sizeof(cmd->ipsec_sa_v1); + + return mlx5_fpga_ipsec_sa_cmd_exec(mdev, cmd, cmd_size); } int mlx5_accel_ipsec_sa_cmd_wait(void *ctx) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h index 4da9611a753d..14a2e95e82c3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h @@ -44,6 +44,7 @@ enum { MLX5_ACCEL_IPSEC_ESP = BIT(3), MLX5_ACCEL_IPSEC_LSO = BIT(4), MLX5_ACCEL_IPSEC_NO_TRAILER = BIT(5), + MLX5_ACCEL_IPSEC_V2_CMD = BIT(7), }; #define MLX5_IPSEC_SADB_IP_AH BIT(7) @@ -56,6 +57,9 @@ enum { enum { MLX5_IPSEC_CMD_ADD_SA = 0, MLX5_IPSEC_CMD_DEL_SA = 1, + MLX5_IPSEC_CMD_ADD_SA_V2 = 2, + MLX5_IPSEC_CMD_DEL_SA_V2 = 3, + MLX5_IPSEC_CMD_MOD_SA_V2 = 4, MLX5_IPSEC_CMD_SET_CAP = 5, }; @@ -68,7 +72,7 @@ enum mlx5_accel_ipsec_enc_mode { #define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \ MLX5_ACCEL_IPSEC_DEVICE) -struct mlx5_accel_ipsec_sa { +struct mlx5_accel_ipsec_sa_v1 { __be32 cmd; u8 key_enc[32]; u8 key_auth[32]; @@ -88,10 +92,19 @@ struct mlx5_accel_ipsec_sa { __be32 sw_sa_handle; __be16 tfclen; u8 enc_mode; - u8 sip_masklen; - u8 dip_masklen; + u8 reserved1[2]; u8 flags; - u8 reserved[2]; + u8 reserved2[2]; +}; + +struct mlx5_accel_ipsec_sa { + struct mlx5_accel_ipsec_sa_v1 ipsec_sa_v1; + __be16 udp_sp; + __be16 udp_dp; + u8 reserved1[4]; + __be32 esn; + __be16 vid; /* only 12 bits, rest is reserved */ + __be16 reserved2; } __packed; /** diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 460a613059fe..a8c3fe7cff0f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -133,50 +133,46 @@ static void mlx5e_ipsec_build_hw_sa(u32 op, struct mlx5e_ipsec_sa_entry *sa_entr memset(hw_sa, 0, sizeof(*hw_sa)); - if (op == MLX5_IPSEC_CMD_ADD_SA) { - crypto_data_len = (x->aead->alg_key_len + 7) / 8; - key_len = crypto_data_len - 4; /* 4 bytes salt at end */ - aead = x->data; - geniv_ctx = crypto_aead_ctx(aead); - ivsize = crypto_aead_ivsize(aead); - - memcpy(&hw_sa->key_enc, x->aead->alg_key, key_len); - /* Duplicate 128 bit key twice according to HW layout */ - if (key_len == 16) - memcpy(&hw_sa->key_enc[16], x->aead->alg_key, key_len); - memcpy(&hw_sa->gcm.salt_iv, geniv_ctx->salt, ivsize); - hw_sa->gcm.salt = *((__be32 *)(x->aead->alg_key + key_len)); - } - - hw_sa->cmd = htonl(op); - hw_sa->flags |= MLX5_IPSEC_SADB_SA_VALID | MLX5_IPSEC_SADB_SPI_EN; + crypto_data_len = (x->aead->alg_key_len + 7) / 8; + key_len = crypto_data_len - 4; /* 4 bytes salt at end */ + aead = x->data; + geniv_ctx = crypto_aead_ctx(aead); + ivsize = crypto_aead_ivsize(aead); + + memcpy(&hw_sa->ipsec_sa_v1.key_enc, x->aead->alg_key, key_len); + /* Duplicate 128 bit key twice according to HW layout */ + if (key_len == 16) + memcpy(&hw_sa->ipsec_sa_v1.key_enc[16], x->aead->alg_key, key_len); + memcpy(&hw_sa->ipsec_sa_v1.gcm.salt_iv, geniv_ctx->salt, ivsize); + hw_sa->ipsec_sa_v1.gcm.salt = *((__be32 *)(x->aead->alg_key + key_len)); + + hw_sa->ipsec_sa_v1.cmd = htonl(op); + hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_SA_VALID | MLX5_IPSEC_SADB_SPI_EN; if (x->props.family == AF_INET) { - hw_sa->sip[3] = x->props.saddr.a4; - hw_sa->dip[3] = x->id.daddr.a4; - hw_sa->sip_masklen = 32; - hw_sa->dip_masklen = 32; + hw_sa->ipsec_sa_v1.sip[3] = x->props.saddr.a4; + hw_sa->ipsec_sa_v1.dip[3] = x->id.daddr.a4; } else { - memcpy(hw_sa->sip, x->props.saddr.a6, sizeof(hw_sa->sip)); - memcpy(hw_sa->dip, x->id.daddr.a6, sizeof(hw_sa->dip)); - hw_sa->sip_masklen = 128; - hw_sa->dip_masklen = 128; - hw_sa->flags |= MLX5_IPSEC_SADB_IPV6; + memcpy(hw_sa->ipsec_sa_v1.sip, x->props.saddr.a6, + sizeof(hw_sa->ipsec_sa_v1.sip)); + memcpy(hw_sa->ipsec_sa_v1.dip, x->id.daddr.a6, + sizeof(hw_sa->ipsec_sa_v1.dip)); + hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_IPV6; } - hw_sa->spi = x->id.spi; - hw_sa->sw_sa_handle = htonl(sa_entry->handle); + hw_sa->ipsec_sa_v1.spi = x->id.spi; + hw_sa->ipsec_sa_v1.sw_sa_handle = htonl(sa_entry->handle); switch (x->id.proto) { case IPPROTO_ESP: - hw_sa->flags |= MLX5_IPSEC_SADB_IP_ESP; + hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_IP_ESP; break; case IPPROTO_AH: - hw_sa->flags |= MLX5_IPSEC_SADB_IP_AH; + hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_IP_AH; break; default: break; } - hw_sa->enc_mode = mlx5e_ipsec_enc_mode(x); + hw_sa->ipsec_sa_v1.enc_mode = mlx5e_ipsec_enc_mode(x); if (!(x->xso.flags & XFRM_OFFLOAD_INBOUND)) - hw_sa->flags |= MLX5_IPSEC_SADB_DIR_SX; + hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_DIR_SX; } static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index 3b10d46dc821..fa5b5a0888ec 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -223,9 +223,9 @@ static int mlx5_fpga_ipsec_cmd_wait(void *ctx) } void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd) + struct mlx5_accel_ipsec_sa *cmd, int cmd_size) { - return mlx5_fpga_ipsec_cmd_exec(mdev, cmd, sizeof(*cmd)); + return mlx5_fpga_ipsec_cmd_exec(mdev, cmd, cmd_size); } int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx) @@ -239,9 +239,9 @@ int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx) goto out; sa = (struct mlx5_accel_ipsec_sa *)&context->command; - if (sa->sw_sa_handle != context->resp.sw_sa_handle) { + if (sa->ipsec_sa_v1.sw_sa_handle != context->resp.sw_sa_handle) { mlx5_fpga_err(context->dev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n", - ntohl(sa->sw_sa_handle), + ntohl(sa->ipsec_sa_v1.sw_sa_handle), ntohl(context->resp.sw_sa_handle)); res = -EIO; } @@ -276,6 +276,9 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, rx_no_trailer)) ret |= MLX5_ACCEL_IPSEC_NO_TRAILER; + if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, v2_command)) + ret |= MLX5_ACCEL_IPSEC_V2_CMD; + return ret; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h index 26a3e4b56972..e5ec29f56532 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h @@ -39,7 +39,7 @@ #ifdef CONFIG_MLX5_FPGA void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd); + struct mlx5_accel_ipsec_sa *cmd, int cmd_size); int mlx5_fpga_ipsec_sa_cmd_wait(void *context); u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev); @@ -53,7 +53,8 @@ void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev); #else static inline void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd) + struct mlx5_accel_ipsec_sa *cmd, + int cmd_size) { return ERR_PTR(-EOPNOTSUPP); } diff --git a/include/linux/mlx5/mlx5_ifc_fpga.h b/include/linux/mlx5/mlx5_ifc_fpga.h index 643544db180b..dd7e4538159c 100644 --- a/include/linux/mlx5/mlx5_ifc_fpga.h +++ b/include/linux/mlx5/mlx5_ifc_fpga.h @@ -373,7 +373,9 @@ struct mlx5_ifc_fpga_destroy_qp_out_bits { struct mlx5_ifc_ipsec_extended_cap_bits { u8 encapsulation[0x20]; - u8 reserved_0[0x14]; + u8 reserved_0[0x12]; + u8 v2_command[0x1]; + u8 udp_encap[0x1]; u8 rx_no_trailer[0x1]; u8 ipv4_fragment[0x1]; u8 ipv6[0x1]; -- cgit v1.2.3 From 1d2005e2040b95af4c861e40cf806ff44cd7c883 Mon Sep 17 00:00:00 2001 From: Aviad Yehezkel Date: Mon, 29 Jan 2018 15:05:50 +0200 Subject: net/mlx5: Export ipsec capabilities We will need that for ipsec verbs. Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.c | 3 +- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.h | 14 +----- .../ethernet/mellanox/mlx5/core/en_accel/ipsec.c | 9 ++-- .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 14 +++--- include/linux/mlx5/accel.h | 57 ++++++++++++++++++++++ 5 files changed, 73 insertions(+), 24 deletions(-) create mode 100644 include/linux/mlx5/accel.h (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c index b88ae12d9066..375ba438e7cf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c @@ -45,7 +45,7 @@ void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, if (!MLX5_IPSEC_DEV(mdev)) return ERR_PTR(-EOPNOTSUPP); - if (mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_V2_CMD) + if (mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_V2_CMD) cmd_size = sizeof(*cmd); else cmd_size = sizeof(cmd->ipsec_sa_v1); @@ -62,6 +62,7 @@ u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return mlx5_fpga_ipsec_device_caps(mdev); } +EXPORT_SYMBOL_GPL(mlx5_accel_ipsec_device_caps); unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h index 14a2e95e82c3..421ed71a029b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h @@ -35,18 +35,10 @@ #define __MLX5_ACCEL_IPSEC_H__ #include +#include #ifdef CONFIG_MLX5_ACCEL -enum { - MLX5_ACCEL_IPSEC_DEVICE = BIT(1), - MLX5_ACCEL_IPSEC_IPV6 = BIT(2), - MLX5_ACCEL_IPSEC_ESP = BIT(3), - MLX5_ACCEL_IPSEC_LSO = BIT(4), - MLX5_ACCEL_IPSEC_NO_TRAILER = BIT(5), - MLX5_ACCEL_IPSEC_V2_CMD = BIT(7), -}; - #define MLX5_IPSEC_SADB_IP_AH BIT(7) #define MLX5_IPSEC_SADB_IP_ESP BIT(6) #define MLX5_IPSEC_SADB_SA_VALID BIT(5) @@ -70,7 +62,7 @@ enum mlx5_accel_ipsec_enc_mode { }; #define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \ - MLX5_ACCEL_IPSEC_DEVICE) + MLX5_ACCEL_IPSEC_CAP_DEVICE) struct mlx5_accel_ipsec_sa_v1 { __be32 cmd; @@ -126,8 +118,6 @@ void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, */ int mlx5_accel_ipsec_sa_cmd_wait(void *context); -u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev); - unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev); int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters, unsigned int count); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index a8c3fe7cff0f..6f4a01620cc3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -242,7 +242,8 @@ static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x) return -EINVAL; } if (x->props.family == AF_INET6 && - !(mlx5_accel_ipsec_device_caps(priv->mdev) & MLX5_ACCEL_IPSEC_IPV6)) { + !(mlx5_accel_ipsec_device_caps(priv->mdev) & + MLX5_ACCEL_IPSEC_CAP_IPV6)) { netdev_info(netdev, "IPv6 xfrm state offload is not supported by this device\n"); return -EINVAL; } @@ -375,7 +376,7 @@ int mlx5e_ipsec_init(struct mlx5e_priv *priv) ipsec->en_priv = priv; ipsec->en_priv->ipsec = ipsec; ipsec->no_trailer = !!(mlx5_accel_ipsec_device_caps(priv->mdev) & - MLX5_ACCEL_IPSEC_NO_TRAILER); + MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER); netdev_dbg(priv->netdev, "IPSec attached to netdevice\n"); return 0; } @@ -422,7 +423,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv) if (!priv->ipsec) return; - if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_ESP) || + if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_ESP) || !MLX5_CAP_ETH(mdev, swp)) { mlx5_core_dbg(mdev, "mlx5e: ESP and SWP offload not supported\n"); return; @@ -441,7 +442,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv) netdev->features |= NETIF_F_HW_ESP_TX_CSUM; netdev->hw_enc_features |= NETIF_F_HW_ESP_TX_CSUM; - if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_LSO) || + if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_LSO) || !MLX5_CAP_ETH(mdev, swp_lso)) { mlx5_core_dbg(mdev, "mlx5e: ESP LSO not supported\n"); return; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index fa5b5a0888ec..e7e28277733d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -257,7 +257,7 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) u32 ret = 0; if (mlx5_fpga_is_ipsec_device(mdev)) - ret |= MLX5_ACCEL_IPSEC_DEVICE; + ret |= MLX5_ACCEL_IPSEC_CAP_DEVICE; else return ret; @@ -265,19 +265,19 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) return ret; if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esp)) - ret |= MLX5_ACCEL_IPSEC_ESP; + ret |= MLX5_ACCEL_IPSEC_CAP_ESP; if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, ipv6)) - ret |= MLX5_ACCEL_IPSEC_IPV6; + ret |= MLX5_ACCEL_IPSEC_CAP_IPV6; if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, lso)) - ret |= MLX5_ACCEL_IPSEC_LSO; + ret |= MLX5_ACCEL_IPSEC_CAP_LSO; if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, rx_no_trailer)) - ret |= MLX5_ACCEL_IPSEC_NO_TRAILER; + ret |= MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER; if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, v2_command)) - ret |= MLX5_ACCEL_IPSEC_V2_CMD; + ret |= MLX5_ACCEL_IPSEC_CAP_V2_CMD; return ret; } @@ -375,7 +375,7 @@ static int mlx5_fpga_ipsec_enable_supported_caps(struct mlx5_core_dev *mdev) u32 dev_caps = mlx5_fpga_ipsec_device_caps(mdev); u32 flags = 0; - if (dev_caps & MLX5_ACCEL_IPSEC_NO_TRAILER) + if (dev_caps & MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER) flags |= MLX5_FPGA_IPSEC_CAP_NO_TRAILER; return mlx5_fpga_ipsec_set_caps(mdev, flags); diff --git a/include/linux/mlx5/accel.h b/include/linux/mlx5/accel.h new file mode 100644 index 000000000000..601280c782d3 --- /dev/null +++ b/include/linux/mlx5/accel.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2018 Mellanox Technologies. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifndef __MLX5_ACCEL_H__ +#define __MLX5_ACCEL_H__ + +#include + +enum mlx5_accel_ipsec_caps { + MLX5_ACCEL_IPSEC_CAP_DEVICE = 1 << 0, + MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 2, + MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 3, + MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 4, + MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER = 1 << 5, + MLX5_ACCEL_IPSEC_CAP_V2_CMD = 1 << 6, +}; + +#ifdef CONFIG_MLX5_ACCEL + +u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev); + +#else + +static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; } + +#endif +#endif -- cgit v1.2.3 From af9fe19d660e333ca9b0a6e1506e684a1126b9e7 Mon Sep 17 00:00:00 2001 From: Aviad Yehezkel Date: Wed, 17 Jan 2018 11:20:33 +0200 Subject: net/mlx5: Added required metadata capability for ipsec Currently our device requires additional metadata in packet to perform ipsec crypto offload. Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 6 ++++-- include/linux/mlx5/accel.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index e7e28277733d..8de992ba7230 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -256,10 +256,12 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) struct mlx5_fpga_device *fdev = mdev->fpga; u32 ret = 0; - if (mlx5_fpga_is_ipsec_device(mdev)) + if (mlx5_fpga_is_ipsec_device(mdev)) { ret |= MLX5_ACCEL_IPSEC_CAP_DEVICE; - else + ret |= MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA; + } else { return ret; + } if (!fdev->ipsec) return ret; diff --git a/include/linux/mlx5/accel.h b/include/linux/mlx5/accel.h index 601280c782d3..b674af63689b 100644 --- a/include/linux/mlx5/accel.h +++ b/include/linux/mlx5/accel.h @@ -38,6 +38,7 @@ enum mlx5_accel_ipsec_caps { MLX5_ACCEL_IPSEC_CAP_DEVICE = 1 << 0, + MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA = 1 << 1, MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 2, MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 3, MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 4, -- cgit v1.2.3 From d6c4f0298cec8c4c88d33aca17c066995e92fe91 Mon Sep 17 00:00:00 2001 From: Aviad Yehezkel Date: Thu, 18 Jan 2018 13:05:48 +0200 Subject: net/mlx5: Refactor accel IPSec code The current code has one layer that executed FPGA commands and the Ethernet part directly used this code. Since downstream patches introduces support for IPSec in mlx5_ib, we need to provide some abstractions. This patch refactors the accel code into one layer that creates a software IPSec transformation and another one which creates the actual hardware context. The internal command implementation is now hidden in the FPGA core layer. The code also adds the ability to share FPGA hardware contexts. If two contexts are the same, only a reference count is taken. Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.c | 58 +-- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.h | 97 ++--- .../ethernet/mellanox/mlx5/core/en_accel/ipsec.c | 150 ++++---- .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 391 +++++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.h | 55 ++- include/linux/mlx5/accel.h | 83 ++++- include/linux/mlx5/mlx5_ifc_fpga.h | 59 ++++ 7 files changed, 668 insertions(+), 225 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c index 375ba438e7cf..ab5bc82855fd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c @@ -37,27 +37,6 @@ #include "mlx5_core.h" #include "fpga/ipsec.h" -void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd) -{ - int cmd_size; - - if (!MLX5_IPSEC_DEV(mdev)) - return ERR_PTR(-EOPNOTSUPP); - - if (mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_V2_CMD) - cmd_size = sizeof(*cmd); - else - cmd_size = sizeof(cmd->ipsec_sa_v1); - - return mlx5_fpga_ipsec_sa_cmd_exec(mdev, cmd, cmd_size); -} - -int mlx5_accel_ipsec_sa_cmd_wait(void *ctx) -{ - return mlx5_fpga_ipsec_sa_cmd_wait(ctx); -} - u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return mlx5_fpga_ipsec_device_caps(mdev); @@ -75,6 +54,21 @@ int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters, return mlx5_fpga_ipsec_counters_read(mdev, counters, count); } +void *mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev, + struct mlx5_accel_esp_xfrm *xfrm, + const __be32 saddr[4], + const __be32 daddr[4], + const __be32 spi, bool is_ipv6) +{ + return mlx5_fpga_ipsec_create_sa_ctx(mdev, xfrm, saddr, daddr, + spi, is_ipv6); +} + +void mlx5_accel_esp_free_hw_context(void *context) +{ + mlx5_fpga_ipsec_delete_sa_ctx(context); +} + int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev) { return mlx5_fpga_ipsec_init(mdev); @@ -84,3 +78,25 @@ void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev) { mlx5_fpga_ipsec_cleanup(mdev); } + +struct mlx5_accel_esp_xfrm * +mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *attrs, + u32 flags) +{ + struct mlx5_accel_esp_xfrm *xfrm; + + xfrm = mlx5_fpga_esp_create_xfrm(mdev, attrs, flags); + if (IS_ERR(xfrm)) + return xfrm; + + xfrm->mdev = mdev; + return xfrm; +} +EXPORT_SYMBOL_GPL(mlx5_accel_esp_create_xfrm); + +void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) +{ + mlx5_fpga_esp_destroy_xfrm(xfrm); +} +EXPORT_SYMBOL_GPL(mlx5_accel_esp_destroy_xfrm); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h index 421ed71a029b..024dbd22a89b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h @@ -39,89 +39,20 @@ #ifdef CONFIG_MLX5_ACCEL -#define MLX5_IPSEC_SADB_IP_AH BIT(7) -#define MLX5_IPSEC_SADB_IP_ESP BIT(6) -#define MLX5_IPSEC_SADB_SA_VALID BIT(5) -#define MLX5_IPSEC_SADB_SPI_EN BIT(4) -#define MLX5_IPSEC_SADB_DIR_SX BIT(3) -#define MLX5_IPSEC_SADB_IPV6 BIT(2) - -enum { - MLX5_IPSEC_CMD_ADD_SA = 0, - MLX5_IPSEC_CMD_DEL_SA = 1, - MLX5_IPSEC_CMD_ADD_SA_V2 = 2, - MLX5_IPSEC_CMD_DEL_SA_V2 = 3, - MLX5_IPSEC_CMD_MOD_SA_V2 = 4, - MLX5_IPSEC_CMD_SET_CAP = 5, -}; - -enum mlx5_accel_ipsec_enc_mode { - MLX5_IPSEC_SADB_MODE_NONE = 0, - MLX5_IPSEC_SADB_MODE_AES_GCM_128_AUTH_128 = 1, - MLX5_IPSEC_SADB_MODE_AES_GCM_256_AUTH_128 = 3, -}; - #define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \ MLX5_ACCEL_IPSEC_CAP_DEVICE) -struct mlx5_accel_ipsec_sa_v1 { - __be32 cmd; - u8 key_enc[32]; - u8 key_auth[32]; - __be32 sip[4]; - __be32 dip[4]; - union { - struct { - __be32 reserved; - u8 salt_iv[8]; - __be32 salt; - } __packed gcm; - struct { - u8 salt[16]; - } __packed cbc; - }; - __be32 spi; - __be32 sw_sa_handle; - __be16 tfclen; - u8 enc_mode; - u8 reserved1[2]; - u8 flags; - u8 reserved2[2]; -}; - -struct mlx5_accel_ipsec_sa { - struct mlx5_accel_ipsec_sa_v1 ipsec_sa_v1; - __be16 udp_sp; - __be16 udp_dp; - u8 reserved1[4]; - __be32 esn; - __be16 vid; /* only 12 bits, rest is reserved */ - __be16 reserved2; -} __packed; - -/** - * mlx5_accel_ipsec_sa_cmd_exec - Execute an IPSec SADB command - * @mdev: mlx5 device - * @cmd: command to execute - * May be called from atomic context. Returns context pointer, or error - * Caller must eventually call mlx5_accel_ipsec_sa_cmd_wait from non-atomic - * context, to cleanup the context pointer - */ -void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd); - -/** - * mlx5_accel_ipsec_sa_cmd_wait - Wait for command execution completion - * @context: Context pointer returned from call to mlx5_accel_ipsec_sa_cmd_exec - * Sleeps (killable) until command execution is complete. - * Returns the command result, or -EINTR if killed - */ -int mlx5_accel_ipsec_sa_cmd_wait(void *context); - unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev); int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters, unsigned int count); +void *mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev, + struct mlx5_accel_esp_xfrm *xfrm, + const __be32 saddr[4], + const __be32 daddr[4], + const __be32 spi, bool is_ipv6); +void mlx5_accel_esp_free_hw_context(void *context); + int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev); void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev); @@ -129,6 +60,20 @@ void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev); #define MLX5_IPSEC_DEV(mdev) false +static inline void * +mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev, + struct mlx5_accel_esp_xfrm *xfrm, + const __be32 saddr[4], + const __be32 daddr[4], + const __be32 spi, bool is_ipv6) +{ + return NULL; +} + +static inline void mlx5_accel_esp_free_hw_context(void *context) +{ +} + static inline int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev) { return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 6f4a01620cc3..59df3dbd2e65 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -47,7 +47,8 @@ struct mlx5e_ipsec_sa_entry { unsigned int handle; /* Handle in SADB_RX */ struct xfrm_state *x; struct mlx5e_ipsec *ipsec; - void *context; + struct mlx5_accel_esp_xfrm *xfrm; + void *hw_context; }; struct xfrm_state *mlx5e_ipsec_sadb_rx_lookup(struct mlx5e_ipsec *ipsec, @@ -105,74 +106,51 @@ static void mlx5e_ipsec_sadb_rx_free(struct mlx5e_ipsec_sa_entry *sa_entry) ida_simple_remove(&ipsec->halloc, sa_entry->handle); } -static enum mlx5_accel_ipsec_enc_mode mlx5e_ipsec_enc_mode(struct xfrm_state *x) -{ - unsigned int key_len = (x->aead->alg_key_len + 7) / 8 - 4; - - switch (key_len) { - case 16: - return MLX5_IPSEC_SADB_MODE_AES_GCM_128_AUTH_128; - case 32: - return MLX5_IPSEC_SADB_MODE_AES_GCM_256_AUTH_128; - default: - netdev_warn(x->xso.dev, "Bad key len: %d for alg %s\n", - key_len, x->aead->alg_name); - return -1; - } -} - -static void mlx5e_ipsec_build_hw_sa(u32 op, struct mlx5e_ipsec_sa_entry *sa_entry, - struct mlx5_accel_ipsec_sa *hw_sa) +static void +mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry, + struct mlx5_accel_esp_xfrm_attrs *attrs) { struct xfrm_state *x = sa_entry->x; + struct aes_gcm_keymat *aes_gcm = &attrs->keymat.aes_gcm; struct aead_geniv_ctx *geniv_ctx; - unsigned int crypto_data_len; struct crypto_aead *aead; - unsigned int key_len; + unsigned int crypto_data_len, key_len; int ivsize; - memset(hw_sa, 0, sizeof(*hw_sa)); + memset(attrs, 0, sizeof(*attrs)); + /* key */ crypto_data_len = (x->aead->alg_key_len + 7) / 8; key_len = crypto_data_len - 4; /* 4 bytes salt at end */ + + memcpy(aes_gcm->aes_key, x->aead->alg_key, key_len); + aes_gcm->key_len = key_len * 8; + + /* salt and seq_iv */ aead = x->data; geniv_ctx = crypto_aead_ctx(aead); ivsize = crypto_aead_ivsize(aead); - - memcpy(&hw_sa->ipsec_sa_v1.key_enc, x->aead->alg_key, key_len); - /* Duplicate 128 bit key twice according to HW layout */ - if (key_len == 16) - memcpy(&hw_sa->ipsec_sa_v1.key_enc[16], x->aead->alg_key, key_len); - memcpy(&hw_sa->ipsec_sa_v1.gcm.salt_iv, geniv_ctx->salt, ivsize); - hw_sa->ipsec_sa_v1.gcm.salt = *((__be32 *)(x->aead->alg_key + key_len)); - - hw_sa->ipsec_sa_v1.cmd = htonl(op); - hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_SA_VALID | MLX5_IPSEC_SADB_SPI_EN; - if (x->props.family == AF_INET) { - hw_sa->ipsec_sa_v1.sip[3] = x->props.saddr.a4; - hw_sa->ipsec_sa_v1.dip[3] = x->id.daddr.a4; - } else { - memcpy(hw_sa->ipsec_sa_v1.sip, x->props.saddr.a6, - sizeof(hw_sa->ipsec_sa_v1.sip)); - memcpy(hw_sa->ipsec_sa_v1.dip, x->id.daddr.a6, - sizeof(hw_sa->ipsec_sa_v1.dip)); - hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_IPV6; - } - hw_sa->ipsec_sa_v1.spi = x->id.spi; - hw_sa->ipsec_sa_v1.sw_sa_handle = htonl(sa_entry->handle); - switch (x->id.proto) { - case IPPROTO_ESP: - hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_IP_ESP; - break; - case IPPROTO_AH: - hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_IP_AH; - break; - default: - break; - } - hw_sa->ipsec_sa_v1.enc_mode = mlx5e_ipsec_enc_mode(x); - if (!(x->xso.flags & XFRM_OFFLOAD_INBOUND)) - hw_sa->ipsec_sa_v1.flags |= MLX5_IPSEC_SADB_DIR_SX; + memcpy(&aes_gcm->seq_iv, &geniv_ctx->salt, ivsize); + memcpy(&aes_gcm->salt, x->aead->alg_key + key_len, + sizeof(aes_gcm->salt)); + + /* iv len */ + aes_gcm->icv_len = x->aead->alg_icv_len; + + /* rx handle */ + attrs->sa_handle = sa_entry->handle; + + /* algo type */ + attrs->keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; + + /* action */ + attrs->action = (!(x->xso.flags & XFRM_OFFLOAD_INBOUND)) ? + MLX5_ACCEL_ESP_ACTION_ENCRYPT : + MLX5_ACCEL_ESP_ACTION_DECRYPT; + /* flags */ + attrs->flags |= (x->props.mode == XFRM_MODE_TRANSPORT) ? + MLX5_ACCEL_ESP_FLAGS_TRANSPORT : + MLX5_ACCEL_ESP_FLAGS_TUNNEL; } static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x) @@ -254,9 +232,10 @@ static int mlx5e_xfrm_add_state(struct xfrm_state *x) { struct mlx5e_ipsec_sa_entry *sa_entry = NULL; struct net_device *netdev = x->xso.dev; - struct mlx5_accel_ipsec_sa hw_sa; + struct mlx5_accel_esp_xfrm_attrs attrs; struct mlx5e_priv *priv; - void *context; + __be32 saddr[4] = {0}, daddr[4] = {0}, spi; + bool is_ipv6 = false; int err; priv = netdev_priv(netdev); @@ -285,20 +264,41 @@ static int mlx5e_xfrm_add_state(struct xfrm_state *x) } } - mlx5e_ipsec_build_hw_sa(MLX5_IPSEC_CMD_ADD_SA, sa_entry, &hw_sa); - context = mlx5_accel_ipsec_sa_cmd_exec(sa_entry->ipsec->en_priv->mdev, &hw_sa); - if (IS_ERR(context)) { - err = PTR_ERR(context); + /* create xfrm */ + mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, &attrs); + sa_entry->xfrm = + mlx5_accel_esp_create_xfrm(priv->mdev, &attrs, + MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA); + if (IS_ERR(sa_entry->xfrm)) { + err = PTR_ERR(sa_entry->xfrm); goto err_sadb_rx; } - err = mlx5_accel_ipsec_sa_cmd_wait(context); - if (err) - goto err_sadb_rx; + /* create hw context */ + if (x->props.family == AF_INET) { + saddr[3] = x->props.saddr.a4; + daddr[3] = x->id.daddr.a4; + } else { + memcpy(saddr, x->props.saddr.a6, sizeof(saddr)); + memcpy(daddr, x->id.daddr.a6, sizeof(daddr)); + is_ipv6 = true; + } + spi = x->id.spi; + sa_entry->hw_context = + mlx5_accel_esp_create_hw_context(priv->mdev, + sa_entry->xfrm, + saddr, daddr, spi, + is_ipv6); + if (IS_ERR(sa_entry->hw_context)) { + err = PTR_ERR(sa_entry->hw_context); + goto err_xfrm; + } x->xso.offload_handle = (unsigned long)sa_entry; goto out; +err_xfrm: + mlx5_accel_esp_destroy_xfrm(sa_entry->xfrm); err_sadb_rx: if (x->xso.flags & XFRM_OFFLOAD_INBOUND) { mlx5e_ipsec_sadb_rx_del(sa_entry); @@ -313,8 +313,6 @@ out: static void mlx5e_xfrm_del_state(struct xfrm_state *x) { struct mlx5e_ipsec_sa_entry *sa_entry; - struct mlx5_accel_ipsec_sa hw_sa; - void *context; if (!x->xso.offload_handle) return; @@ -324,19 +322,11 @@ static void mlx5e_xfrm_del_state(struct xfrm_state *x) if (x->xso.flags & XFRM_OFFLOAD_INBOUND) mlx5e_ipsec_sadb_rx_del(sa_entry); - - mlx5e_ipsec_build_hw_sa(MLX5_IPSEC_CMD_DEL_SA, sa_entry, &hw_sa); - context = mlx5_accel_ipsec_sa_cmd_exec(sa_entry->ipsec->en_priv->mdev, &hw_sa); - if (IS_ERR(context)) - return; - - sa_entry->context = context; } static void mlx5e_xfrm_free_state(struct xfrm_state *x) { struct mlx5e_ipsec_sa_entry *sa_entry; - int res; if (!x->xso.offload_handle) return; @@ -344,11 +334,9 @@ static void mlx5e_xfrm_free_state(struct xfrm_state *x) sa_entry = (struct mlx5e_ipsec_sa_entry *)x->xso.offload_handle; WARN_ON(sa_entry->x != x); - res = mlx5_accel_ipsec_sa_cmd_wait(sa_entry->context); - sa_entry->context = NULL; - if (res) { - /* Leftover object will leak */ - return; + if (sa_entry->hw_context) { + mlx5_accel_esp_free_hw_context(sa_entry->hw_context); + mlx5_accel_esp_destroy_xfrm(sa_entry->xfrm); } if (x->xso.flags & XFRM_OFFLOAD_INBOUND) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index 8de992ba7230..daae44c937f0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -31,6 +31,7 @@ * */ +#include #include #include "mlx5_core.h" @@ -47,7 +48,7 @@ enum mlx5_fpga_ipsec_cmd_status { MLX5_FPGA_IPSEC_CMD_COMPLETE, }; -struct mlx5_ipsec_command_context { +struct mlx5_fpga_ipsec_cmd_context { struct mlx5_fpga_dma_buf buf; enum mlx5_fpga_ipsec_cmd_status status; struct mlx5_ifc_fpga_ipsec_cmd_resp resp; @@ -58,11 +59,43 @@ struct mlx5_ipsec_command_context { u8 command[0]; }; +struct mlx5_fpga_esp_xfrm; + +struct mlx5_fpga_ipsec_sa_ctx { + struct rhash_head hash; + struct mlx5_ifc_fpga_ipsec_sa hw_sa; + struct mlx5_core_dev *dev; + struct mlx5_fpga_esp_xfrm *fpga_xfrm; +}; + +struct mlx5_fpga_esp_xfrm { + unsigned int num_rules; + struct mlx5_fpga_ipsec_sa_ctx *sa_ctx; + struct mutex lock; /* xfrm lock */ + struct mlx5_accel_esp_xfrm accel_xfrm; +}; + +static const struct rhashtable_params rhash_sa = { + .key_len = FIELD_SIZEOF(struct mlx5_fpga_ipsec_sa_ctx, hw_sa), + .key_offset = offsetof(struct mlx5_fpga_ipsec_sa_ctx, hw_sa), + .head_offset = offsetof(struct mlx5_fpga_ipsec_sa_ctx, hash), + .automatic_shrinking = true, + .min_size = 1, +}; + struct mlx5_fpga_ipsec { struct list_head pending_cmds; spinlock_t pending_cmds_lock; /* Protects pending_cmds */ u32 caps[MLX5_ST_SZ_DW(ipsec_extended_cap)]; struct mlx5_fpga_conn *conn; + + /* Map hardware SA --> SA context + * (mlx5_fpga_ipsec_sa) (mlx5_fpga_ipsec_sa_ctx) + * We will use this hash to avoid SAs duplication in fpga which + * aren't allowed + */ + struct rhashtable sa_hash; /* hw_sa -> mlx5_fpga_ipsec_sa_ctx */ + struct mutex sa_hash_lock; }; static bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev) @@ -86,10 +119,10 @@ static void mlx5_fpga_ipsec_send_complete(struct mlx5_fpga_conn *conn, struct mlx5_fpga_dma_buf *buf, u8 status) { - struct mlx5_ipsec_command_context *context; + struct mlx5_fpga_ipsec_cmd_context *context; if (status) { - context = container_of(buf, struct mlx5_ipsec_command_context, + context = container_of(buf, struct mlx5_fpga_ipsec_cmd_context, buf); mlx5_fpga_warn(fdev, "IPSec command send failed with status %u\n", status); @@ -117,7 +150,7 @@ int syndrome_to_errno(enum mlx5_ifc_fpga_ipsec_response_syndrome syndrome) static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf) { struct mlx5_ifc_fpga_ipsec_cmd_resp *resp = buf->sg[0].data; - struct mlx5_ipsec_command_context *context; + struct mlx5_fpga_ipsec_cmd_context *context; enum mlx5_ifc_fpga_ipsec_response_syndrome syndrome; struct mlx5_fpga_device *fdev = cb_arg; unsigned long flags; @@ -133,7 +166,7 @@ static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf) spin_lock_irqsave(&fdev->ipsec->pending_cmds_lock, flags); context = list_first_entry_or_null(&fdev->ipsec->pending_cmds, - struct mlx5_ipsec_command_context, + struct mlx5_fpga_ipsec_cmd_context, list); if (context) list_del(&context->list); @@ -160,7 +193,7 @@ static void mlx5_fpga_ipsec_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf) static void *mlx5_fpga_ipsec_cmd_exec(struct mlx5_core_dev *mdev, const void *cmd, int cmd_size) { - struct mlx5_ipsec_command_context *context; + struct mlx5_fpga_ipsec_cmd_context *context; struct mlx5_fpga_device *fdev = mdev->fpga; unsigned long flags; int res; @@ -203,7 +236,7 @@ static void *mlx5_fpga_ipsec_cmd_exec(struct mlx5_core_dev *mdev, static int mlx5_fpga_ipsec_cmd_wait(void *ctx) { - struct mlx5_ipsec_command_context *context = ctx; + struct mlx5_fpga_ipsec_cmd_context *context = ctx; unsigned long timeout = msecs_to_jiffies(MLX5_FPGA_IPSEC_CMD_TIMEOUT_MSEC); int res; @@ -222,33 +255,49 @@ static int mlx5_fpga_ipsec_cmd_wait(void *ctx) return res; } -void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd, int cmd_size) +static inline bool is_v2_sadb_supported(struct mlx5_fpga_ipsec *fipsec) { - return mlx5_fpga_ipsec_cmd_exec(mdev, cmd, cmd_size); + if (MLX5_GET(ipsec_extended_cap, fipsec->caps, v2_command)) + return true; + return false; } -int mlx5_fpga_ipsec_sa_cmd_wait(void *ctx) +static int mlx5_fpga_ipsec_update_hw_sa(struct mlx5_fpga_device *fdev, + struct mlx5_ifc_fpga_ipsec_sa *hw_sa, + int opcode) { - struct mlx5_ipsec_command_context *context = ctx; - struct mlx5_accel_ipsec_sa *sa; - int res; + struct mlx5_core_dev *dev = fdev->mdev; + struct mlx5_ifc_fpga_ipsec_sa *sa; + struct mlx5_fpga_ipsec_cmd_context *cmd_context; + size_t sa_cmd_size; + int err; - res = mlx5_fpga_ipsec_cmd_wait(ctx); - if (res) + hw_sa->ipsec_sa_v1.cmd = htonl(opcode); + if (is_v2_sadb_supported(fdev->ipsec)) + sa_cmd_size = sizeof(*hw_sa); + else + sa_cmd_size = sizeof(hw_sa->ipsec_sa_v1); + + cmd_context = (struct mlx5_fpga_ipsec_cmd_context *) + mlx5_fpga_ipsec_cmd_exec(dev, hw_sa, sa_cmd_size); + if (IS_ERR(cmd_context)) + return PTR_ERR(cmd_context); + + err = mlx5_fpga_ipsec_cmd_wait(cmd_context); + if (err) goto out; - sa = (struct mlx5_accel_ipsec_sa *)&context->command; - if (sa->ipsec_sa_v1.sw_sa_handle != context->resp.sw_sa_handle) { - mlx5_fpga_err(context->dev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n", + sa = (struct mlx5_ifc_fpga_ipsec_sa *)&cmd_context->command; + if (sa->ipsec_sa_v1.sw_sa_handle != cmd_context->resp.sw_sa_handle) { + mlx5_fpga_err(fdev, "mismatch SA handle. cmd 0x%08x vs resp 0x%08x\n", ntohl(sa->ipsec_sa_v1.sw_sa_handle), - ntohl(context->resp.sw_sa_handle)); - res = -EIO; + ntohl(cmd_context->resp.sw_sa_handle)); + err = -EIO; } out: - kfree(context); - return res; + kfree(cmd_context); + return err; } u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) @@ -278,9 +327,6 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, rx_no_trailer)) ret |= MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER; - if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, v2_command)) - ret |= MLX5_ACCEL_IPSEC_CAP_V2_CMD; - return ret; } @@ -345,11 +391,11 @@ out: static int mlx5_fpga_ipsec_set_caps(struct mlx5_core_dev *mdev, u32 flags) { - struct mlx5_ipsec_command_context *context; + struct mlx5_fpga_ipsec_cmd_context *context; struct mlx5_ifc_fpga_ipsec_cmd_cap cmd = {0}; int err; - cmd.cmd = htonl(MLX5_IPSEC_CMD_SET_CAP); + cmd.cmd = htonl(MLX5_FPGA_IPSEC_CMD_OP_SET_CAP); cmd.flags = htonl(flags); context = mlx5_fpga_ipsec_cmd_exec(mdev, &cmd, sizeof(cmd)); if (IS_ERR(context)) { @@ -383,6 +429,200 @@ static int mlx5_fpga_ipsec_enable_supported_caps(struct mlx5_core_dev *mdev) return mlx5_fpga_ipsec_set_caps(mdev, flags); } +static void +mlx5_fpga_ipsec_build_hw_xfrm(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *xfrm_attrs, + struct mlx5_ifc_fpga_ipsec_sa *hw_sa) +{ + const struct aes_gcm_keymat *aes_gcm = &xfrm_attrs->keymat.aes_gcm; + + /* key */ + memcpy(&hw_sa->ipsec_sa_v1.key_enc, aes_gcm->aes_key, + aes_gcm->key_len / 8); + /* Duplicate 128 bit key twice according to HW layout */ + if (aes_gcm->key_len == 128) + memcpy(&hw_sa->ipsec_sa_v1.key_enc[16], + aes_gcm->aes_key, aes_gcm->key_len / 8); + + /* salt and seq_iv */ + memcpy(&hw_sa->ipsec_sa_v1.gcm.salt_iv, &aes_gcm->seq_iv, + sizeof(aes_gcm->seq_iv)); + memcpy(&hw_sa->ipsec_sa_v1.gcm.salt, &aes_gcm->salt, + sizeof(aes_gcm->salt)); + + /* rx handle */ + hw_sa->ipsec_sa_v1.sw_sa_handle = htonl(xfrm_attrs->sa_handle); + + /* enc mode */ + switch (aes_gcm->key_len) { + case 128: + hw_sa->ipsec_sa_v1.enc_mode = + MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128; + break; + case 256: + hw_sa->ipsec_sa_v1.enc_mode = + MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128; + break; + } + + /* flags */ + hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_SA_VALID | + MLX5_FPGA_IPSEC_SA_SPI_EN | + MLX5_FPGA_IPSEC_SA_IP_ESP; + + if (xfrm_attrs->action & MLX5_ACCEL_ESP_ACTION_ENCRYPT) + hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_DIR_SX; + else + hw_sa->ipsec_sa_v1.flags &= ~MLX5_FPGA_IPSEC_SA_DIR_SX; +} + +static void +mlx5_fpga_ipsec_build_hw_sa(struct mlx5_core_dev *mdev, + struct mlx5_accel_esp_xfrm_attrs *xfrm_attrs, + const __be32 saddr[4], + const __be32 daddr[4], + const __be32 spi, bool is_ipv6, + struct mlx5_ifc_fpga_ipsec_sa *hw_sa) +{ + mlx5_fpga_ipsec_build_hw_xfrm(mdev, xfrm_attrs, hw_sa); + + /* IPs */ + memcpy(hw_sa->ipsec_sa_v1.sip, saddr, sizeof(hw_sa->ipsec_sa_v1.sip)); + memcpy(hw_sa->ipsec_sa_v1.dip, daddr, sizeof(hw_sa->ipsec_sa_v1.dip)); + + /* SPI */ + hw_sa->ipsec_sa_v1.spi = spi; + + /* flags */ + if (is_ipv6) + hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_IPV6; +} + +void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev, + struct mlx5_accel_esp_xfrm *accel_xfrm, + const __be32 saddr[4], + const __be32 daddr[4], + const __be32 spi, bool is_ipv6) +{ + struct mlx5_fpga_ipsec_sa_ctx *sa_ctx; + struct mlx5_fpga_esp_xfrm *fpga_xfrm = + container_of(accel_xfrm, typeof(*fpga_xfrm), + accel_xfrm); + struct mlx5_fpga_device *fdev = mdev->fpga; + struct mlx5_fpga_ipsec *fipsec = fdev->ipsec; + int opcode, err; + void *context; + + /* alloc SA */ + sa_ctx = kzalloc(sizeof(*sa_ctx), GFP_KERNEL); + if (!sa_ctx) + return ERR_PTR(-ENOMEM); + + sa_ctx->dev = mdev; + + /* build candidate SA */ + mlx5_fpga_ipsec_build_hw_sa(mdev, &accel_xfrm->attrs, + saddr, daddr, spi, is_ipv6, + &sa_ctx->hw_sa); + + mutex_lock(&fpga_xfrm->lock); + + if (fpga_xfrm->sa_ctx) { /* multiple rules for same accel_xfrm */ + /* all rules must be with same IPs and SPI */ + if (memcmp(&sa_ctx->hw_sa, &fpga_xfrm->sa_ctx->hw_sa, + sizeof(sa_ctx->hw_sa))) { + context = ERR_PTR(-EINVAL); + goto exists; + } + + ++fpga_xfrm->num_rules; + context = fpga_xfrm->sa_ctx; + goto exists; + } + + /* This is unbounded fpga_xfrm, try to add to hash */ + mutex_lock(&fipsec->sa_hash_lock); + + err = rhashtable_lookup_insert_fast(&fipsec->sa_hash, &sa_ctx->hash, + rhash_sa); + if (err) { + /* Can't bound different accel_xfrm to already existing sa_ctx. + * This is because we can't support multiple ketmats for + * same IPs and SPI + */ + context = ERR_PTR(-EEXIST); + goto unlock_hash; + } + + /* Bound accel_xfrm to sa_ctx */ + opcode = is_v2_sadb_supported(fdev->ipsec) ? + MLX5_FPGA_IPSEC_CMD_OP_ADD_SA_V2 : + MLX5_FPGA_IPSEC_CMD_OP_ADD_SA; + err = mlx5_fpga_ipsec_update_hw_sa(fdev, &sa_ctx->hw_sa, opcode); + sa_ctx->hw_sa.ipsec_sa_v1.cmd = 0; + if (err) { + context = ERR_PTR(err); + goto delete_hash; + } + + mutex_unlock(&fipsec->sa_hash_lock); + + ++fpga_xfrm->num_rules; + fpga_xfrm->sa_ctx = sa_ctx; + sa_ctx->fpga_xfrm = fpga_xfrm; + + mutex_unlock(&fpga_xfrm->lock); + + return sa_ctx; + +delete_hash: + WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash, &sa_ctx->hash, + rhash_sa)); +unlock_hash: + mutex_unlock(&fipsec->sa_hash_lock); + +exists: + mutex_unlock(&fpga_xfrm->lock); + kfree(sa_ctx); + return context; +} + +static void +mlx5_fpga_ipsec_release_sa_ctx(struct mlx5_fpga_ipsec_sa_ctx *sa_ctx) +{ + struct mlx5_fpga_device *fdev = sa_ctx->dev->fpga; + struct mlx5_fpga_ipsec *fipsec = fdev->ipsec; + int opcode = is_v2_sadb_supported(fdev->ipsec) ? + MLX5_FPGA_IPSEC_CMD_OP_DEL_SA_V2 : + MLX5_FPGA_IPSEC_CMD_OP_DEL_SA; + int err; + + err = mlx5_fpga_ipsec_update_hw_sa(fdev, &sa_ctx->hw_sa, opcode); + sa_ctx->hw_sa.ipsec_sa_v1.cmd = 0; + if (err) { + WARN_ON(err); + return; + } + + mutex_lock(&fipsec->sa_hash_lock); + WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash, &sa_ctx->hash, + rhash_sa)); + mutex_unlock(&fipsec->sa_hash_lock); +} + +void mlx5_fpga_ipsec_delete_sa_ctx(void *context) +{ + struct mlx5_fpga_esp_xfrm *fpga_xfrm = + ((struct mlx5_fpga_ipsec_sa_ctx *)context)->fpga_xfrm; + + mutex_lock(&fpga_xfrm->lock); + if (!--fpga_xfrm->num_rules) { + mlx5_fpga_ipsec_release_sa_ctx(fpga_xfrm->sa_ctx); + fpga_xfrm->sa_ctx = NULL; + } + mutex_unlock(&fpga_xfrm->lock); +} + int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) { struct mlx5_fpga_conn_attr init_attr = {0}; @@ -421,15 +661,23 @@ int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) } fdev->ipsec->conn = conn; + err = rhashtable_init(&fdev->ipsec->sa_hash, &rhash_sa); + if (err) + goto err_destroy_conn; + mutex_init(&fdev->ipsec->sa_hash_lock); + err = mlx5_fpga_ipsec_enable_supported_caps(mdev); if (err) { mlx5_fpga_err(fdev, "Failed to enable IPSec extended capabilities: %d\n", err); - goto err_destroy_conn; + goto err_destroy_hash; } return 0; +err_destroy_hash: + rhashtable_destroy(&fdev->ipsec->sa_hash); + err_destroy_conn: mlx5_fpga_sbu_conn_destroy(conn); @@ -446,7 +694,92 @@ void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev) if (!mlx5_fpga_is_ipsec_device(mdev)) return; + rhashtable_destroy(&fdev->ipsec->sa_hash); + mlx5_fpga_sbu_conn_destroy(fdev->ipsec->conn); kfree(fdev->ipsec); fdev->ipsec = NULL; } + +static int +mlx5_fpga_esp_validate_xfrm_attrs(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *attrs) +{ + if (attrs->tfc_pad) { + mlx5_core_err(mdev, "Cannot offload xfrm states with tfc padding\n"); + return -EOPNOTSUPP; + } + + if (attrs->replay_type != MLX5_ACCEL_ESP_REPLAY_NONE) { + mlx5_core_err(mdev, "Cannot offload xfrm states with anti replay\n"); + return -EOPNOTSUPP; + } + + if (attrs->keymat_type != MLX5_ACCEL_ESP_KEYMAT_AES_GCM) { + mlx5_core_err(mdev, "Only aes gcm keymat is supported\n"); + return -EOPNOTSUPP; + } + + if (attrs->keymat.aes_gcm.iv_algo != + MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ) { + mlx5_core_err(mdev, "Only iv sequence algo is supported\n"); + return -EOPNOTSUPP; + } + + if (attrs->keymat.aes_gcm.icv_len != 128) { + mlx5_core_err(mdev, "Cannot offload xfrm states with AEAD ICV length other than 128bit\n"); + return -EOPNOTSUPP; + } + + if (attrs->keymat.aes_gcm.key_len != 128 && + attrs->keymat.aes_gcm.key_len != 256) { + mlx5_core_err(mdev, "Cannot offload xfrm states with AEAD key length other than 128/256 bit\n"); + return -EOPNOTSUPP; + } + + if ((attrs->flags & MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED) && + (!MLX5_GET(ipsec_extended_cap, mdev->fpga->ipsec->caps, + v2_command))) { + mlx5_core_err(mdev, "Cannot offload xfrm states with AEAD key length other than 128/256 bit\n"); + return -EOPNOTSUPP; + } + + return 0; +} + +struct mlx5_accel_esp_xfrm * +mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *attrs, + u32 flags) +{ + struct mlx5_fpga_esp_xfrm *fpga_xfrm; + + if (!(flags & MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA)) { + mlx5_core_warn(mdev, "Tried to create an esp action without metadata\n"); + return ERR_PTR(-EINVAL); + } + + if (mlx5_fpga_esp_validate_xfrm_attrs(mdev, attrs)) { + mlx5_core_warn(mdev, "Tried to create an esp with unsupported attrs\n"); + return ERR_PTR(-EOPNOTSUPP); + } + + fpga_xfrm = kzalloc(sizeof(*fpga_xfrm), GFP_KERNEL); + if (!fpga_xfrm) + return ERR_PTR(-ENOMEM); + + mutex_init(&fpga_xfrm->lock); + memcpy(&fpga_xfrm->accel_xfrm.attrs, attrs, + sizeof(fpga_xfrm->accel_xfrm.attrs)); + + return &fpga_xfrm->accel_xfrm; +} + +void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) +{ + struct mlx5_fpga_esp_xfrm *fpga_xfrm = + container_of(xfrm, struct mlx5_fpga_esp_xfrm, + accel_xfrm); + /* assuming no sa_ctx are connected to this xfrm_ctx */ + kfree(fpga_xfrm); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h index e5ec29f56532..7ad1e2cd3fb0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h @@ -38,31 +38,28 @@ #ifdef CONFIG_MLX5_FPGA -void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd, int cmd_size); -int mlx5_fpga_ipsec_sa_cmd_wait(void *context); - u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev); unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev); int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters, unsigned int counters_count); +void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev, + struct mlx5_accel_esp_xfrm *accel_xfrm, + const __be32 saddr[4], + const __be32 daddr[4], + const __be32 spi, bool is_ipv6); +void mlx5_fpga_ipsec_delete_sa_ctx(void *context); + int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev); void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev); -#else - -static inline void *mlx5_fpga_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev, - struct mlx5_accel_ipsec_sa *cmd, - int cmd_size) -{ - return ERR_PTR(-EOPNOTSUPP); -} +struct mlx5_accel_esp_xfrm * +mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *attrs, + u32 flags); +void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm); -static inline int mlx5_fpga_ipsec_sa_cmd_wait(void *context) -{ - return -EOPNOTSUPP; -} +#else static inline u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) { @@ -81,6 +78,20 @@ static inline int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, return 0; } +static inline void * +mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev, + struct mlx5_accel_esp_xfrm *accel_xfrm, + const __be32 saddr[4], + const __be32 daddr[4], + const __be32 spi, bool is_ipv6) +{ + return NULL; +} + +static inline void mlx5_fpga_ipsec_delete_sa_ctx(void *context) +{ +} + static inline int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) { return 0; @@ -90,6 +101,18 @@ static inline void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev) { } +static inline struct mlx5_accel_esp_xfrm * +mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *attrs, + u32 flags) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) +{ +} + #endif /* CONFIG_MLX5_FPGA */ #endif /* __MLX5_FPGA_SADB_H__ */ diff --git a/include/linux/mlx5/accel.h b/include/linux/mlx5/accel.h index b674af63689b..da6de465ea6d 100644 --- a/include/linux/mlx5/accel.h +++ b/include/linux/mlx5/accel.h @@ -36,23 +36,102 @@ #include -enum mlx5_accel_ipsec_caps { +enum mlx5_accel_esp_aes_gcm_keymat_iv_algo { + MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ, +}; + +enum mlx5_accel_esp_flags { + MLX5_ACCEL_ESP_FLAGS_TUNNEL = 0, /* Default */ + MLX5_ACCEL_ESP_FLAGS_TRANSPORT = 1UL << 0, + MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED = 1UL << 1, + MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP = 1UL << 2, +}; + +enum mlx5_accel_esp_action { + MLX5_ACCEL_ESP_ACTION_DECRYPT, + MLX5_ACCEL_ESP_ACTION_ENCRYPT, +}; + +enum mlx5_accel_esp_keymats { + MLX5_ACCEL_ESP_KEYMAT_AES_NONE, + MLX5_ACCEL_ESP_KEYMAT_AES_GCM, +}; + +enum mlx5_accel_esp_replay { + MLX5_ACCEL_ESP_REPLAY_NONE, + MLX5_ACCEL_ESP_REPLAY_BMP, +}; + +struct aes_gcm_keymat { + u64 seq_iv; + enum mlx5_accel_esp_aes_gcm_keymat_iv_algo iv_algo; + + u32 salt; + u32 icv_len; + + u32 key_len; + u32 aes_key[256 / 32]; +}; + +struct mlx5_accel_esp_xfrm_attrs { + enum mlx5_accel_esp_action action; + u32 esn; + u32 spi; + u32 seq; + u32 tfc_pad; + u32 flags; + u32 sa_handle; + enum mlx5_accel_esp_replay replay_type; + union { + struct { + u32 size; + + } bmp; + } replay; + enum mlx5_accel_esp_keymats keymat_type; + union { + struct aes_gcm_keymat aes_gcm; + } keymat; +}; + +struct mlx5_accel_esp_xfrm { + struct mlx5_core_dev *mdev; + struct mlx5_accel_esp_xfrm_attrs attrs; +}; + +enum { + MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA = 1UL << 0, +}; + +enum mlx5_accel_ipsec_cap { MLX5_ACCEL_IPSEC_CAP_DEVICE = 1 << 0, MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA = 1 << 1, MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 2, MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 3, MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 4, MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER = 1 << 5, - MLX5_ACCEL_IPSEC_CAP_V2_CMD = 1 << 6, }; #ifdef CONFIG_MLX5_ACCEL u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev); +struct mlx5_accel_esp_xfrm * +mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *attrs, + u32 flags); +void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm); + #else static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; } +static inline struct mlx5_accel_esp_xfrm * +mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev, + const struct mlx5_accel_esp_xfrm_attrs *attrs, + u32 flags) { return ERR_PTR(-EOPNOTSUPP); } +static inline void +mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) {} + #endif #endif diff --git a/include/linux/mlx5/mlx5_ifc_fpga.h b/include/linux/mlx5/mlx5_ifc_fpga.h index dd7e4538159c..debcc57de43a 100644 --- a/include/linux/mlx5/mlx5_ifc_fpga.h +++ b/include/linux/mlx5/mlx5_ifc_fpga.h @@ -448,6 +448,15 @@ struct mlx5_ifc_fpga_ipsec_cmd_resp { u8 reserved[24]; } __packed; +enum mlx5_ifc_fpga_ipsec_cmd_opcode { + MLX5_FPGA_IPSEC_CMD_OP_ADD_SA = 0, + MLX5_FPGA_IPSEC_CMD_OP_DEL_SA = 1, + MLX5_FPGA_IPSEC_CMD_OP_ADD_SA_V2 = 2, + MLX5_FPGA_IPSEC_CMD_OP_DEL_SA_V2 = 3, + MLX5_FPGA_IPSEC_CMD_OP_MOD_SA_V2 = 4, + MLX5_FPGA_IPSEC_CMD_OP_SET_CAP = 5, +}; + enum mlx5_ifc_fpga_ipsec_cap { MLX5_FPGA_IPSEC_CAP_NO_TRAILER = BIT(0), }; @@ -458,4 +467,54 @@ struct mlx5_ifc_fpga_ipsec_cmd_cap { u8 reserved[24]; } __packed; +enum mlx5_ifc_fpga_ipsec_sa_flags { + MLX5_FPGA_IPSEC_SA_IPV6 = BIT(2), + MLX5_FPGA_IPSEC_SA_DIR_SX = BIT(3), + MLX5_FPGA_IPSEC_SA_SPI_EN = BIT(4), + MLX5_FPGA_IPSEC_SA_SA_VALID = BIT(5), + MLX5_FPGA_IPSEC_SA_IP_ESP = BIT(6), + MLX5_FPGA_IPSEC_SA_IP_AH = BIT(7), +}; + +enum mlx5_ifc_fpga_ipsec_sa_enc_mode { + MLX5_FPGA_IPSEC_SA_ENC_MODE_NONE = 0, + MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128 = 1, + MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128 = 3, +}; + +struct mlx5_ifc_fpga_ipsec_sa_v1 { + __be32 cmd; + u8 key_enc[32]; + u8 key_auth[32]; + __be32 sip[4]; + __be32 dip[4]; + union { + struct { + __be32 reserved; + u8 salt_iv[8]; + __be32 salt; + } __packed gcm; + struct { + u8 salt[16]; + } __packed cbc; + }; + __be32 spi; + __be32 sw_sa_handle; + __be16 tfclen; + u8 enc_mode; + u8 reserved1[2]; + u8 flags; + u8 reserved2[2]; +}; + +struct mlx5_ifc_fpga_ipsec_sa { + struct mlx5_ifc_fpga_ipsec_sa_v1 ipsec_sa_v1; + __be16 udp_sp; + __be16 udp_dp; + u8 reserved1[4]; + __be32 esn; + __be16 vid; /* only 12 bits, rest is reserved */ + __be16 reserved2; +} __packed; + #endif /* MLX5_IFC_FPGA_H */ -- cgit v1.2.3 From 05564d0ae075b7a73339eaa05296c3034e439c32 Mon Sep 17 00:00:00 2001 From: Aviad Yehezkel Date: Sun, 18 Feb 2018 15:07:20 +0200 Subject: net/mlx5: Add flow-steering commands for FPGA IPSec implementation In order to add a context to the FPGA, we need to get both the software transform context (which includes the keys, etc) and the source/destination IPs (which are included in the steering rule). Therefore, we register new set of firmware like commands for the FPGA. Each time a rule is added, the steering core infrastructure calls the FPGA command layer. If the rule is intended for the FPGA, it combines the IPs information with the software transformation context and creates the respective hardware transform. Afterwards, it calls the standard steering command layer. Signed-off-by: Aviad Yehezkel Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/accel/ipsec.c | 7 + .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 724 +++++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.h | 24 + drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 5 + drivers/net/ethernet/mellanox/mlx5/core/main.c | 2 + include/linux/mlx5/accel.h | 5 + include/linux/mlx5/fs.h | 3 + 7 files changed, 770 insertions(+) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c index ab5bc82855fd..9f1b1939716a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c @@ -100,3 +100,10 @@ void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) mlx5_fpga_esp_destroy_xfrm(xfrm); } EXPORT_SYMBOL_GPL(mlx5_accel_esp_destroy_xfrm); + +int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm, + const struct mlx5_accel_esp_xfrm_attrs *attrs) +{ + return mlx5_fpga_esp_modify_xfrm(xfrm, attrs); +} +EXPORT_SYMBOL_GPL(mlx5_accel_esp_modify_xfrm); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index daae44c937f0..7b43fa269117 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -33,8 +33,12 @@ #include #include +#include +#include +#include #include "mlx5_core.h" +#include "fs_cmd.h" #include "fpga/ipsec.h" #include "fpga/sdk.h" #include "fpga/core.h" @@ -75,6 +79,12 @@ struct mlx5_fpga_esp_xfrm { struct mlx5_accel_esp_xfrm accel_xfrm; }; +struct mlx5_fpga_ipsec_rule { + struct rb_node node; + struct fs_fte *fte; + struct mlx5_fpga_ipsec_sa_ctx *ctx; +}; + static const struct rhashtable_params rhash_sa = { .key_len = FIELD_SIZEOF(struct mlx5_fpga_ipsec_sa_ctx, hw_sa), .key_offset = offsetof(struct mlx5_fpga_ipsec_sa_ctx, hw_sa), @@ -84,11 +94,15 @@ static const struct rhashtable_params rhash_sa = { }; struct mlx5_fpga_ipsec { + struct mlx5_fpga_device *fdev; struct list_head pending_cmds; spinlock_t pending_cmds_lock; /* Protects pending_cmds */ u32 caps[MLX5_ST_SZ_DW(ipsec_extended_cap)]; struct mlx5_fpga_conn *conn; + struct notifier_block fs_notifier_ingress_bypass; + struct notifier_block fs_notifier_egress; + /* Map hardware SA --> SA context * (mlx5_fpga_ipsec_sa) (mlx5_fpga_ipsec_sa_ctx) * We will use this hash to avoid SAs duplication in fpga which @@ -96,6 +110,12 @@ struct mlx5_fpga_ipsec { */ struct rhashtable sa_hash; /* hw_sa -> mlx5_fpga_ipsec_sa_ctx */ struct mutex sa_hash_lock; + + /* Tree holding all rules for this fpga device + * Key for searching a rule (mlx5_fpga_ipsec_rule) is (ft, id) + */ + struct rb_root rules_rb; + struct mutex rules_rb_lock; /* rules lock */ }; static bool mlx5_fpga_is_ipsec_device(struct mlx5_core_dev *mdev) @@ -498,6 +518,127 @@ mlx5_fpga_ipsec_build_hw_sa(struct mlx5_core_dev *mdev, hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_IPV6; } +static bool is_full_mask(const void *p, size_t len) +{ + WARN_ON(len % 4); + + return !memchr_inv(p, 0xff, len); +} + +static bool validate_fpga_full_mask(struct mlx5_core_dev *dev, + const u32 *match_c, + const u32 *match_v) +{ + const void *misc_params_c = MLX5_ADDR_OF(fte_match_param, + match_c, + misc_parameters); + const void *headers_c = MLX5_ADDR_OF(fte_match_param, + match_c, + outer_headers); + const void *headers_v = MLX5_ADDR_OF(fte_match_param, + match_v, + outer_headers); + + if (mlx5_fs_is_outer_ipv4_flow(dev, headers_c, headers_v)) { + const void *s_ipv4_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4, + headers_c, + src_ipv4_src_ipv6.ipv4_layout.ipv4); + const void *d_ipv4_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4, + headers_c, + dst_ipv4_dst_ipv6.ipv4_layout.ipv4); + + if (!is_full_mask(s_ipv4_c, MLX5_FLD_SZ_BYTES(ipv4_layout, + ipv4)) || + !is_full_mask(d_ipv4_c, MLX5_FLD_SZ_BYTES(ipv4_layout, + ipv4))) + return false; + } else { + const void *s_ipv6_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4, + headers_c, + src_ipv4_src_ipv6.ipv6_layout.ipv6); + const void *d_ipv6_c = MLX5_ADDR_OF(fte_match_set_lyr_2_4, + headers_c, + dst_ipv4_dst_ipv6.ipv6_layout.ipv6); + + if (!is_full_mask(s_ipv6_c, MLX5_FLD_SZ_BYTES(ipv6_layout, + ipv6)) || + !is_full_mask(d_ipv6_c, MLX5_FLD_SZ_BYTES(ipv6_layout, + ipv6))) + return false; + } + + if (!is_full_mask(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, + outer_esp_spi), + MLX5_FLD_SZ_BYTES(fte_match_set_misc, outer_esp_spi))) + return false; + + return true; +} + +static bool mlx5_is_fpga_ipsec_rule(struct mlx5_core_dev *dev, + u8 match_criteria_enable, + const u32 *match_c, + const u32 *match_v) +{ + u32 ipsec_dev_caps = mlx5_accel_ipsec_device_caps(dev); + bool ipv6_flow; + + ipv6_flow = mlx5_fs_is_outer_ipv6_flow(dev, match_c, match_v); + + if (!(match_criteria_enable & MLX5_MATCH_OUTER_HEADERS) || + mlx5_fs_is_outer_udp_flow(match_c, match_v) || + mlx5_fs_is_outer_tcp_flow(match_c, match_v) || + mlx5_fs_is_vxlan_flow(match_c) || + !(mlx5_fs_is_outer_ipv4_flow(dev, match_c, match_v) || + ipv6_flow)) + return false; + + if (!(ipsec_dev_caps & MLX5_ACCEL_IPSEC_CAP_DEVICE)) + return false; + + if (!(ipsec_dev_caps & MLX5_ACCEL_IPSEC_CAP_ESP) && + mlx5_fs_is_outer_ipsec_flow(match_c)) + return false; + + if (!(ipsec_dev_caps & MLX5_ACCEL_IPSEC_CAP_IPV6) && + ipv6_flow) + return false; + + if (!validate_fpga_full_mask(dev, match_c, match_v)) + return false; + + return true; +} + +static bool mlx5_is_fpga_egress_ipsec_rule(struct mlx5_core_dev *dev, + u8 match_criteria_enable, + const u32 *match_c, + const u32 *match_v, + struct mlx5_flow_act *flow_act) +{ + const void *outer_c = MLX5_ADDR_OF(fte_match_param, match_c, + outer_headers); + bool is_dmac = MLX5_GET(fte_match_set_lyr_2_4, outer_c, dmac_47_16) || + MLX5_GET(fte_match_set_lyr_2_4, outer_c, dmac_15_0); + bool is_smac = MLX5_GET(fte_match_set_lyr_2_4, outer_c, smac_47_16) || + MLX5_GET(fte_match_set_lyr_2_4, outer_c, smac_15_0); + int ret; + + ret = mlx5_is_fpga_ipsec_rule(dev, match_criteria_enable, match_c, + match_v); + if (!ret) + return ret; + + if (is_dmac || is_smac || + (match_criteria_enable & + ~(MLX5_MATCH_OUTER_HEADERS | MLX5_MATCH_MISC_PARAMETERS)) || + (flow_act->action & ~(MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | MLX5_FLOW_CONTEXT_ACTION_ALLOW)) || + flow_act->has_flow_tag) + return false; + + return true; +} + void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev, struct mlx5_accel_esp_xfrm *accel_xfrm, const __be32 saddr[4], @@ -587,6 +728,73 @@ exists: return context; } +static void * +mlx5_fpga_ipsec_fs_create_sa_ctx(struct mlx5_core_dev *mdev, + struct fs_fte *fte, + bool is_egress) +{ + struct mlx5_accel_esp_xfrm *accel_xfrm; + __be32 saddr[4], daddr[4], spi; + struct mlx5_flow_group *fg; + bool is_ipv6 = false; + + fs_get_obj(fg, fte->node.parent); + /* validate */ + if (is_egress && + !mlx5_is_fpga_egress_ipsec_rule(mdev, + fg->mask.match_criteria_enable, + fg->mask.match_criteria, + fte->val, + &fte->action)) + return ERR_PTR(-EINVAL); + else if (!mlx5_is_fpga_ipsec_rule(mdev, + fg->mask.match_criteria_enable, + fg->mask.match_criteria, + fte->val)) + return ERR_PTR(-EINVAL); + + /* get xfrm context */ + accel_xfrm = + (struct mlx5_accel_esp_xfrm *)fte->action.esp_id; + + /* IPs */ + if (mlx5_fs_is_outer_ipv4_flow(mdev, fg->mask.match_criteria, + fte->val)) { + memcpy(&saddr[3], + MLX5_ADDR_OF(fte_match_set_lyr_2_4, + fte->val, + src_ipv4_src_ipv6.ipv4_layout.ipv4), + sizeof(saddr[3])); + memcpy(&daddr[3], + MLX5_ADDR_OF(fte_match_set_lyr_2_4, + fte->val, + dst_ipv4_dst_ipv6.ipv4_layout.ipv4), + sizeof(daddr[3])); + } else { + memcpy(saddr, + MLX5_ADDR_OF(fte_match_param, + fte->val, + outer_headers.src_ipv4_src_ipv6.ipv6_layout.ipv6), + sizeof(saddr)); + memcpy(daddr, + MLX5_ADDR_OF(fte_match_param, + fte->val, + outer_headers.dst_ipv4_dst_ipv6.ipv6_layout.ipv6), + sizeof(daddr)); + is_ipv6 = true; + } + + /* SPI */ + spi = MLX5_GET_BE(typeof(spi), + fte_match_param, fte->val, + misc_parameters.outer_esp_spi); + + /* create */ + return mlx5_fpga_ipsec_create_sa_ctx(mdev, accel_xfrm, + saddr, daddr, + spi, is_ipv6); +} + static void mlx5_fpga_ipsec_release_sa_ctx(struct mlx5_fpga_ipsec_sa_ctx *sa_ctx) { @@ -623,6 +831,389 @@ void mlx5_fpga_ipsec_delete_sa_ctx(void *context) mutex_unlock(&fpga_xfrm->lock); } +static inline struct mlx5_fpga_ipsec_rule * +_rule_search(struct rb_root *root, struct fs_fte *fte) +{ + struct rb_node *node = root->rb_node; + + while (node) { + struct mlx5_fpga_ipsec_rule *rule = + container_of(node, struct mlx5_fpga_ipsec_rule, + node); + + if (rule->fte < fte) + node = node->rb_left; + else if (rule->fte > fte) + node = node->rb_right; + else + return rule; + } + return NULL; +} + +static struct mlx5_fpga_ipsec_rule * +rule_search(struct mlx5_fpga_ipsec *ipsec_dev, struct fs_fte *fte) +{ + struct mlx5_fpga_ipsec_rule *rule; + + mutex_lock(&ipsec_dev->rules_rb_lock); + rule = _rule_search(&ipsec_dev->rules_rb, fte); + mutex_unlock(&ipsec_dev->rules_rb_lock); + + return rule; +} + +static inline int _rule_insert(struct rb_root *root, + struct mlx5_fpga_ipsec_rule *rule) +{ + struct rb_node **new = &root->rb_node, *parent = NULL; + + /* Figure out where to put new node */ + while (*new) { + struct mlx5_fpga_ipsec_rule *this = + container_of(*new, struct mlx5_fpga_ipsec_rule, + node); + + parent = *new; + if (rule->fte < this->fte) + new = &((*new)->rb_left); + else if (rule->fte > this->fte) + new = &((*new)->rb_right); + else + return -EEXIST; + } + + /* Add new node and rebalance tree. */ + rb_link_node(&rule->node, parent, new); + rb_insert_color(&rule->node, root); + + return 0; +} + +static int rule_insert(struct mlx5_fpga_ipsec *ipsec_dev, + struct mlx5_fpga_ipsec_rule *rule) +{ + int ret; + + mutex_lock(&ipsec_dev->rules_rb_lock); + ret = _rule_insert(&ipsec_dev->rules_rb, rule); + mutex_unlock(&ipsec_dev->rules_rb_lock); + + return ret; +} + +static inline void _rule_delete(struct mlx5_fpga_ipsec *ipsec_dev, + struct mlx5_fpga_ipsec_rule *rule) +{ + struct rb_root *root = &ipsec_dev->rules_rb; + + mutex_lock(&ipsec_dev->rules_rb_lock); + rb_erase(&rule->node, root); + mutex_unlock(&ipsec_dev->rules_rb_lock); +} + +static void rule_delete(struct mlx5_fpga_ipsec *ipsec_dev, + struct mlx5_fpga_ipsec_rule *rule) +{ + _rule_delete(ipsec_dev, rule); + kfree(rule); +} + +struct mailbox_mod { + uintptr_t saved_esp_id; + u32 saved_action; + u32 saved_outer_esp_spi_value; +}; + +static void restore_spec_mailbox(struct fs_fte *fte, + struct mailbox_mod *mbox_mod) +{ + char *misc_params_v = MLX5_ADDR_OF(fte_match_param, + fte->val, + misc_parameters); + + MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, + mbox_mod->saved_outer_esp_spi_value); + fte->action.action |= mbox_mod->saved_action; + fte->action.esp_id = (uintptr_t)mbox_mod->saved_esp_id; +} + +static void modify_spec_mailbox(struct mlx5_core_dev *mdev, + struct fs_fte *fte, + struct mailbox_mod *mbox_mod) +{ + char *misc_params_v = MLX5_ADDR_OF(fte_match_param, + fte->val, + misc_parameters); + + mbox_mod->saved_esp_id = fte->action.esp_id; + mbox_mod->saved_action = fte->action.action & + (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | + MLX5_FLOW_CONTEXT_ACTION_DECRYPT); + mbox_mod->saved_outer_esp_spi_value = + MLX5_GET(fte_match_set_misc, misc_params_v, + outer_esp_spi); + + fte->action.esp_id = 0; + fte->action.action &= ~(MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | + MLX5_FLOW_CONTEXT_ACTION_DECRYPT); + if (!MLX5_CAP_FLOWTABLE(mdev, + flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) + MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 0); +} + +static enum fs_flow_table_type egress_to_fs_ft(bool egress) +{ + return egress ? FS_FT_NIC_TX : FS_FT_NIC_RX; +} + +static int fpga_ipsec_fs_create_flow_group(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + u32 *in, + unsigned int *group_id, + bool is_egress) +{ + int (*create_flow_group)(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, u32 *in, + unsigned int *group_id) = + mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->create_flow_group; + char *misc_params_c = MLX5_ADDR_OF(create_flow_group_in, in, + match_criteria.misc_parameters); + u32 saved_outer_esp_spi_mask; + u8 match_criteria_enable; + int ret; + + if (MLX5_CAP_FLOWTABLE(dev, + flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) + return create_flow_group(dev, ft, in, group_id); + + match_criteria_enable = + MLX5_GET(create_flow_group_in, in, match_criteria_enable); + saved_outer_esp_spi_mask = + MLX5_GET(fte_match_set_misc, misc_params_c, outer_esp_spi); + if (!match_criteria_enable || !saved_outer_esp_spi_mask) + return create_flow_group(dev, ft, in, group_id); + + MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 0); + + if (!(*misc_params_c) && + !memcmp(misc_params_c, misc_params_c + 1, MLX5_ST_SZ_BYTES(fte_match_set_misc) - 1)) + MLX5_SET(create_flow_group_in, in, match_criteria_enable, + match_criteria_enable & ~MLX5_MATCH_MISC_PARAMETERS); + + ret = create_flow_group(dev, ft, in, group_id); + + MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, saved_outer_esp_spi_mask); + MLX5_SET(create_flow_group_in, in, match_criteria_enable, match_criteria_enable); + + return ret; +} + +static int fpga_ipsec_fs_create_fte(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct mlx5_flow_group *fg, + struct fs_fte *fte, + bool is_egress) +{ + int (*create_fte)(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct mlx5_flow_group *fg, + struct fs_fte *fte) = + mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->create_fte; + struct mlx5_fpga_device *fdev = dev->fpga; + struct mlx5_fpga_ipsec *fipsec = fdev->ipsec; + struct mlx5_fpga_ipsec_rule *rule; + bool is_esp = fte->action.esp_id; + struct mailbox_mod mbox_mod; + int ret; + + if (!is_esp || + !(fte->action.action & + (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | + MLX5_FLOW_CONTEXT_ACTION_DECRYPT))) + return create_fte(dev, ft, fg, fte); + + rule = kzalloc(sizeof(*rule), GFP_KERNEL); + if (!rule) + return -ENOMEM; + + rule->ctx = mlx5_fpga_ipsec_fs_create_sa_ctx(dev, fte, is_egress); + if (IS_ERR(rule->ctx)) { + kfree(rule); + return PTR_ERR(rule->ctx); + } + + rule->fte = fte; + WARN_ON(rule_insert(fipsec, rule)); + + modify_spec_mailbox(dev, fte, &mbox_mod); + ret = create_fte(dev, ft, fg, fte); + restore_spec_mailbox(fte, &mbox_mod); + if (ret) { + _rule_delete(fipsec, rule); + mlx5_fpga_ipsec_delete_sa_ctx(rule->ctx); + kfree(rule); + } + + return ret; +} + +static int fpga_ipsec_fs_update_fte(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + unsigned int group_id, + int modify_mask, + struct fs_fte *fte, + bool is_egress) +{ + int (*update_fte)(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + unsigned int group_id, + int modify_mask, + struct fs_fte *fte) = + mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->update_fte; + bool is_esp = fte->action.esp_id; + struct mailbox_mod mbox_mod; + int ret; + + if (!is_esp || + !(fte->action.action & + (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | + MLX5_FLOW_CONTEXT_ACTION_DECRYPT))) + return update_fte(dev, ft, group_id, modify_mask, fte); + + modify_spec_mailbox(dev, fte, &mbox_mod); + ret = update_fte(dev, ft, group_id, modify_mask, fte); + restore_spec_mailbox(fte, &mbox_mod); + + return ret; +} + +static int fpga_ipsec_fs_delete_fte(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct fs_fte *fte, + bool is_egress) +{ + int (*delete_fte)(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct fs_fte *fte) = + mlx5_fs_cmd_get_default(egress_to_fs_ft(is_egress))->delete_fte; + struct mlx5_fpga_device *fdev = dev->fpga; + struct mlx5_fpga_ipsec *fipsec = fdev->ipsec; + struct mlx5_fpga_ipsec_rule *rule; + bool is_esp = fte->action.esp_id; + struct mailbox_mod mbox_mod; + int ret; + + if (!is_esp || + !(fte->action.action & + (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | + MLX5_FLOW_CONTEXT_ACTION_DECRYPT))) + return delete_fte(dev, ft, fte); + + rule = rule_search(fipsec, fte); + if (!rule) + return -ENOENT; + + mlx5_fpga_ipsec_delete_sa_ctx(rule->ctx); + rule_delete(fipsec, rule); + + modify_spec_mailbox(dev, fte, &mbox_mod); + ret = delete_fte(dev, ft, fte); + restore_spec_mailbox(fte, &mbox_mod); + + return ret; +} + +static int +mlx5_fpga_ipsec_fs_create_flow_group_egress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + u32 *in, + unsigned int *group_id) +{ + return fpga_ipsec_fs_create_flow_group(dev, ft, in, group_id, true); +} + +static int +mlx5_fpga_ipsec_fs_create_fte_egress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct mlx5_flow_group *fg, + struct fs_fte *fte) +{ + return fpga_ipsec_fs_create_fte(dev, ft, fg, fte, true); +} + +static int +mlx5_fpga_ipsec_fs_update_fte_egress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + unsigned int group_id, + int modify_mask, + struct fs_fte *fte) +{ + return fpga_ipsec_fs_update_fte(dev, ft, group_id, modify_mask, fte, + true); +} + +static int +mlx5_fpga_ipsec_fs_delete_fte_egress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct fs_fte *fte) +{ + return fpga_ipsec_fs_delete_fte(dev, ft, fte, true); +} + +static int +mlx5_fpga_ipsec_fs_create_flow_group_ingress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + u32 *in, + unsigned int *group_id) +{ + return fpga_ipsec_fs_create_flow_group(dev, ft, in, group_id, false); +} + +static int +mlx5_fpga_ipsec_fs_create_fte_ingress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct mlx5_flow_group *fg, + struct fs_fte *fte) +{ + return fpga_ipsec_fs_create_fte(dev, ft, fg, fte, false); +} + +static int +mlx5_fpga_ipsec_fs_update_fte_ingress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + unsigned int group_id, + int modify_mask, + struct fs_fte *fte) +{ + return fpga_ipsec_fs_update_fte(dev, ft, group_id, modify_mask, fte, + false); +} + +static int +mlx5_fpga_ipsec_fs_delete_fte_ingress(struct mlx5_core_dev *dev, + struct mlx5_flow_table *ft, + struct fs_fte *fte) +{ + return fpga_ipsec_fs_delete_fte(dev, ft, fte, false); +} + +static struct mlx5_flow_cmds fpga_ipsec_ingress; +static struct mlx5_flow_cmds fpga_ipsec_egress; + +const struct mlx5_flow_cmds *mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type) +{ + switch (type) { + case FS_FT_NIC_RX: + return &fpga_ipsec_ingress; + case FS_FT_NIC_TX: + return &fpga_ipsec_egress; + default: + WARN_ON(true); + return NULL; + } +} + int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) { struct mlx5_fpga_conn_attr init_attr = {0}; @@ -637,6 +1228,8 @@ int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) if (!fdev->ipsec) return -ENOMEM; + fdev->ipsec->fdev = fdev; + err = mlx5_fpga_get_sbu_caps(fdev, sizeof(fdev->ipsec->caps), fdev->ipsec->caps); if (err) { @@ -666,6 +1259,9 @@ int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev) goto err_destroy_conn; mutex_init(&fdev->ipsec->sa_hash_lock); + fdev->ipsec->rules_rb = RB_ROOT; + mutex_init(&fdev->ipsec->rules_rb_lock); + err = mlx5_fpga_ipsec_enable_supported_caps(mdev); if (err) { mlx5_fpga_err(fdev, "Failed to enable IPSec extended capabilities: %d\n", @@ -687,6 +1283,17 @@ error: return err; } +static void destroy_rules_rb(struct rb_root *root) +{ + struct mlx5_fpga_ipsec_rule *r, *tmp; + + rbtree_postorder_for_each_entry_safe(r, tmp, root, node) { + rb_erase(&r->node, root); + mlx5_fpga_ipsec_delete_sa_ctx(r->ctx); + kfree(r); + } +} + void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev) { struct mlx5_fpga_device *fdev = mdev->fpga; @@ -694,6 +1301,7 @@ void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev) if (!mlx5_fpga_is_ipsec_device(mdev)) return; + destroy_rules_rb(&fdev->ipsec->rules_rb); rhashtable_destroy(&fdev->ipsec->sa_hash); mlx5_fpga_sbu_conn_destroy(fdev->ipsec->conn); @@ -701,6 +1309,49 @@ void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev) fdev->ipsec = NULL; } +void mlx5_fpga_ipsec_build_fs_cmds(void) +{ + /* ingress */ + fpga_ipsec_ingress.create_flow_table = + mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->create_flow_table; + fpga_ipsec_ingress.destroy_flow_table = + mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->destroy_flow_table; + fpga_ipsec_ingress.modify_flow_table = + mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->modify_flow_table; + fpga_ipsec_ingress.create_flow_group = + mlx5_fpga_ipsec_fs_create_flow_group_ingress; + fpga_ipsec_ingress.destroy_flow_group = + mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->destroy_flow_group; + fpga_ipsec_ingress.create_fte = + mlx5_fpga_ipsec_fs_create_fte_ingress; + fpga_ipsec_ingress.update_fte = + mlx5_fpga_ipsec_fs_update_fte_ingress; + fpga_ipsec_ingress.delete_fte = + mlx5_fpga_ipsec_fs_delete_fte_ingress; + fpga_ipsec_ingress.update_root_ft = + mlx5_fs_cmd_get_default(egress_to_fs_ft(false))->update_root_ft; + + /* egress */ + fpga_ipsec_egress.create_flow_table = + mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->create_flow_table; + fpga_ipsec_egress.destroy_flow_table = + mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->destroy_flow_table; + fpga_ipsec_egress.modify_flow_table = + mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->modify_flow_table; + fpga_ipsec_egress.create_flow_group = + mlx5_fpga_ipsec_fs_create_flow_group_egress; + fpga_ipsec_egress.destroy_flow_group = + mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->destroy_flow_group; + fpga_ipsec_egress.create_fte = + mlx5_fpga_ipsec_fs_create_fte_egress; + fpga_ipsec_egress.update_fte = + mlx5_fpga_ipsec_fs_update_fte_egress; + fpga_ipsec_egress.delete_fte = + mlx5_fpga_ipsec_fs_delete_fte_egress; + fpga_ipsec_egress.update_root_ft = + mlx5_fs_cmd_get_default(egress_to_fs_ft(true))->update_root_ft; +} + static int mlx5_fpga_esp_validate_xfrm_attrs(struct mlx5_core_dev *mdev, const struct mlx5_accel_esp_xfrm_attrs *attrs) @@ -783,3 +1434,76 @@ void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) /* assuming no sa_ctx are connected to this xfrm_ctx */ kfree(fpga_xfrm); } + +int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm, + const struct mlx5_accel_esp_xfrm_attrs *attrs) +{ + struct mlx5_core_dev *mdev = xfrm->mdev; + struct mlx5_fpga_device *fdev = mdev->fpga; + struct mlx5_fpga_ipsec *fipsec = fdev->ipsec; + struct mlx5_fpga_esp_xfrm *fpga_xfrm; + struct mlx5_ifc_fpga_ipsec_sa org_hw_sa; + + int err = 0; + + if (!memcmp(&xfrm->attrs, attrs, sizeof(xfrm->attrs))) + return 0; + + if (!mlx5_fpga_esp_validate_xfrm_attrs(mdev, attrs)) { + mlx5_core_warn(mdev, "Tried to create an esp with unsupported attrs\n"); + return -EOPNOTSUPP; + } + + if (is_v2_sadb_supported(fipsec)) { + mlx5_core_warn(mdev, "Modify esp is not supported\n"); + return -EOPNOTSUPP; + } + + fpga_xfrm = container_of(xfrm, struct mlx5_fpga_esp_xfrm, accel_xfrm); + + mutex_lock(&fpga_xfrm->lock); + + if (!fpga_xfrm->sa_ctx) + /* Unbounded xfrm, chane only sw attrs */ + goto change_sw_xfrm_attrs; + + /* copy original hw sa */ + memcpy(&org_hw_sa, &fpga_xfrm->sa_ctx->hw_sa, sizeof(org_hw_sa)); + mutex_lock(&fipsec->sa_hash_lock); + /* remove original hw sa from hash */ + WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash, + &fpga_xfrm->sa_ctx->hash, rhash_sa)); + /* update hw_sa with new xfrm attrs*/ + mlx5_fpga_ipsec_build_hw_xfrm(xfrm->mdev, attrs, + &fpga_xfrm->sa_ctx->hw_sa); + /* try to insert new hw_sa to hash */ + err = rhashtable_insert_fast(&fipsec->sa_hash, + &fpga_xfrm->sa_ctx->hash, rhash_sa); + if (err) + goto rollback_sa; + + /* modify device with new hw_sa */ + err = mlx5_fpga_ipsec_update_hw_sa(fdev, &fpga_xfrm->sa_ctx->hw_sa, + MLX5_FPGA_IPSEC_CMD_OP_MOD_SA_V2); + fpga_xfrm->sa_ctx->hw_sa.ipsec_sa_v1.cmd = 0; + if (err) + WARN_ON(rhashtable_remove_fast(&fipsec->sa_hash, + &fpga_xfrm->sa_ctx->hash, + rhash_sa)); +rollback_sa: + if (err) { + /* return original hw_sa to hash */ + memcpy(&fpga_xfrm->sa_ctx->hw_sa, &org_hw_sa, + sizeof(org_hw_sa)); + WARN_ON(rhashtable_insert_fast(&fipsec->sa_hash, + &fpga_xfrm->sa_ctx->hash, + rhash_sa)); + } + mutex_unlock(&fipsec->sa_hash_lock); + +change_sw_xfrm_attrs: + if (!err) + memcpy(&xfrm->attrs, attrs, sizeof(xfrm->attrs)); + mutex_unlock(&fpga_xfrm->lock); + return err; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h index 7ad1e2cd3fb0..2b5e63b0d4d6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h @@ -35,6 +35,7 @@ #define __MLX5_FPGA_IPSEC_H__ #include "accel/ipsec.h" +#include "fs_cmd.h" #ifdef CONFIG_MLX5_FPGA @@ -52,12 +53,18 @@ void mlx5_fpga_ipsec_delete_sa_ctx(void *context); int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev); void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev); +void mlx5_fpga_ipsec_build_fs_cmds(void); struct mlx5_accel_esp_xfrm * mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev, const struct mlx5_accel_esp_xfrm_attrs *attrs, u32 flags); void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm); +int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm, + const struct mlx5_accel_esp_xfrm_attrs *attrs); + +const struct mlx5_flow_cmds * +mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type); #else @@ -101,6 +108,10 @@ static inline void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev) { } +static inline void mlx5_fpga_ipsec_build_fs_cmds(void) +{ +} + static inline struct mlx5_accel_esp_xfrm * mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev, const struct mlx5_accel_esp_xfrm_attrs *attrs, @@ -113,6 +124,19 @@ static inline void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) { } +static inline int +mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm, + const struct mlx5_accel_esp_xfrm_attrs *attrs) +{ + return -EOPNOTSUPP; +} + +static inline const struct mlx5_flow_cmds * +mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type) +{ + return mlx5_fs_cmd_get_default(type); +} + #endif /* CONFIG_MLX5_FPGA */ #endif /* __MLX5_FPGA_SADB_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index f836e6b76f65..09aad58c8e06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -38,6 +38,7 @@ #include "fs_cmd.h" #include "diag/fs_tracepoint.h" #include "accel/ipsec.h" +#include "fpga/ipsec.h" #define INIT_TREE_NODE_ARRAY_SIZE(...) (sizeof((struct init_tree_node[]){__VA_ARGS__}) /\ sizeof(struct init_tree_node)) @@ -2251,6 +2252,10 @@ static struct mlx5_flow_root_namespace struct mlx5_flow_root_namespace *root_ns; struct mlx5_flow_namespace *ns; + if (mlx5_accel_ipsec_device_caps(steering->dev) & MLX5_ACCEL_IPSEC_CAP_DEVICE && + (table_type == FS_FT_NIC_RX || table_type == FS_FT_NIC_TX)) + cmds = mlx5_fs_cmd_get_default_ipsec_fpga_cmds(table_type); + /* Create the root namespace */ root_ns = kvzalloc(sizeof(*root_ns), GFP_KERNEL); if (!root_ns) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 03972eed02cd..08c33657677c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -58,6 +58,7 @@ #include "eswitch.h" #include "lib/mlx5.h" #include "fpga/core.h" +#include "fpga/ipsec.h" #include "accel/ipsec.h" #include "lib/clock.h" @@ -1658,6 +1659,7 @@ static int __init init(void) get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); mlx5_core_verify_params(); + mlx5_fpga_ipsec_build_fs_cmds(); mlx5_register_debugfs(); err = pci_register_driver(&mlx5_core_driver); diff --git a/include/linux/mlx5/accel.h b/include/linux/mlx5/accel.h index da6de465ea6d..6c694709b0a2 100644 --- a/include/linux/mlx5/accel.h +++ b/include/linux/mlx5/accel.h @@ -121,6 +121,8 @@ mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev, const struct mlx5_accel_esp_xfrm_attrs *attrs, u32 flags); void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm); +int mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm, + const struct mlx5_accel_esp_xfrm_attrs *attrs); #else @@ -132,6 +134,9 @@ mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev, u32 flags) { return ERR_PTR(-EOPNOTSUPP); } static inline void mlx5_accel_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm) {} +static inline int +mlx5_accel_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm, + const struct mlx5_accel_esp_xfrm_attrs *attrs) { return -EOPNOTSUPP; } #endif #endif diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h index 744ea228acea..b957e52434f8 100644 --- a/include/linux/mlx5/fs.h +++ b/include/linux/mlx5/fs.h @@ -40,6 +40,8 @@ enum { MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO = 1 << 16, + MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 17, + MLX5_FLOW_CONTEXT_ACTION_DECRYPT = 1 << 18, }; enum { @@ -146,6 +148,7 @@ struct mlx5_flow_act { u32 flow_tag; u32 encap_id; u32 modify_id; + uintptr_t esp_id; }; #define MLX5_DECLARE_FLOW_ACT(name) \ -- cgit v1.2.3 From cb01008390bb0645d4728c7f8825e32d4b540a30 Mon Sep 17 00:00:00 2001 From: Aviad Yehezkel Date: Thu, 18 Jan 2018 16:02:17 +0200 Subject: net/mlx5: IPSec, Add support for ESN Currently ESN is not supported with IPSec device offload. This patch adds ESN support to IPsec device offload. Implementing new xfrm device operation to synchronize offloading device ESN with xfrm received SN. New QP command to update SA state at the following: ESN 1 ESN 2 ESN 3 |-----------*-----------|-----------*-----------|-----------* ^ ^ ^ ^ ^ ^ ^ - marks where QP command invoked to update the SA ESN state machine. | - marks the start of the ESN scope (0-2^32-1). At this point move SA ESN overlap bit to zero and increment ESN. * - marks the middle of the ESN scope (2^31). At this point move SA ESN overlap bit to one. Signed-off-by: Aviad Yehezkel Signed-off-by: Yossef Efraim Signed-off-by: Saeed Mahameed --- .../ethernet/mellanox/mlx5/core/en_accel/ipsec.c | 118 +++++++++++++++++++-- .../ethernet/mellanox/mlx5/core/en_accel/ipsec.h | 23 ++++ .../mellanox/mlx5/core/en_accel/ipsec_rxtx.c | 29 ++++- .../mellanox/mlx5/core/en_accel/ipsec_rxtx.h | 5 + .../net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 22 ++++ include/linux/mlx5/accel.h | 2 + include/linux/mlx5/mlx5_ifc_fpga.h | 2 + 7 files changed, 189 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index f5b1d60f96f5..cf58c9637904 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -38,18 +38,9 @@ #include #include "en.h" -#include "accel/ipsec.h" #include "en_accel/ipsec.h" #include "en_accel/ipsec_rxtx.h" -struct mlx5e_ipsec_sa_entry { - struct hlist_node hlist; /* Item in SADB_RX hashtable */ - unsigned int handle; /* Handle in SADB_RX */ - struct xfrm_state *x; - struct mlx5e_ipsec *ipsec; - struct mlx5_accel_esp_xfrm *xfrm; - void *hw_context; -}; static struct mlx5e_ipsec_sa_entry *to_ipsec_sa_entry(struct xfrm_state *x) { @@ -121,6 +112,40 @@ static void mlx5e_ipsec_sadb_rx_free(struct mlx5e_ipsec_sa_entry *sa_entry) ida_simple_remove(&ipsec->halloc, sa_entry->handle); } +static bool mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_entry) +{ + struct xfrm_replay_state_esn *replay_esn; + u32 seq_bottom; + u8 overlap; + u32 *esn; + + if (!(sa_entry->x->props.flags & XFRM_STATE_ESN)) { + sa_entry->esn_state.trigger = 0; + return false; + } + + replay_esn = sa_entry->x->replay_esn; + seq_bottom = replay_esn->seq - replay_esn->replay_window + 1; + overlap = sa_entry->esn_state.overlap; + + sa_entry->esn_state.esn = xfrm_replay_seqhi(sa_entry->x, + htonl(seq_bottom)); + esn = &sa_entry->esn_state.esn; + + sa_entry->esn_state.trigger = 1; + if (unlikely(overlap && seq_bottom < MLX5E_IPSEC_ESN_SCOPE_MID)) { + ++(*esn); + sa_entry->esn_state.overlap = 0; + return true; + } else if (unlikely(!overlap && + (seq_bottom >= MLX5E_IPSEC_ESN_SCOPE_MID))) { + sa_entry->esn_state.overlap = 1; + return true; + } + + return false; +} + static void mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry, struct mlx5_accel_esp_xfrm_attrs *attrs) @@ -152,6 +177,14 @@ mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry, /* iv len */ aes_gcm->icv_len = x->aead->alg_icv_len; + /* esn */ + if (sa_entry->esn_state.trigger) { + attrs->flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; + attrs->esn = sa_entry->esn_state.esn; + if (sa_entry->esn_state.overlap) + attrs->flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; + } + /* rx handle */ attrs->sa_handle = sa_entry->handle; @@ -187,7 +220,9 @@ static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x) netdev_info(netdev, "Cannot offload compressed xfrm states\n"); return -EINVAL; } - if (x->props.flags & XFRM_STATE_ESN) { + if (x->props.flags & XFRM_STATE_ESN && + !(mlx5_accel_ipsec_device_caps(priv->mdev) & + MLX5_ACCEL_IPSEC_CAP_ESN)) { netdev_info(netdev, "Cannot offload ESN xfrm states\n"); return -EINVAL; } @@ -277,8 +312,14 @@ static int mlx5e_xfrm_add_state(struct xfrm_state *x) netdev_info(netdev, "Failed adding to SADB_RX: %d\n", err); goto err_entry; } + } else { + sa_entry->set_iv_op = (x->props.flags & XFRM_STATE_ESN) ? + mlx5e_ipsec_set_iv_esn : mlx5e_ipsec_set_iv; } + /* check esn */ + mlx5e_ipsec_update_esn_state(sa_entry); + /* create xfrm */ mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, &attrs); sa_entry->xfrm = @@ -344,6 +385,7 @@ static void mlx5e_xfrm_free_state(struct xfrm_state *x) return; if (sa_entry->hw_context) { + flush_workqueue(sa_entry->ipsec->wq); mlx5_accel_esp_free_hw_context(sa_entry->hw_context); mlx5_accel_esp_destroy_xfrm(sa_entry->xfrm); } @@ -374,6 +416,12 @@ int mlx5e_ipsec_init(struct mlx5e_priv *priv) ipsec->en_priv->ipsec = ipsec; ipsec->no_trailer = !!(mlx5_accel_ipsec_device_caps(priv->mdev) & MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER); + ipsec->wq = alloc_ordered_workqueue("mlx5e_ipsec: %s", 0, + priv->netdev->name); + if (!ipsec->wq) { + kfree(ipsec); + return -ENOMEM; + } netdev_dbg(priv->netdev, "IPSec attached to netdevice\n"); return 0; } @@ -385,6 +433,9 @@ void mlx5e_ipsec_cleanup(struct mlx5e_priv *priv) if (!ipsec) return; + drain_workqueue(ipsec->wq); + destroy_workqueue(ipsec->wq); + ida_destroy(&ipsec->halloc); kfree(ipsec); priv->ipsec = NULL; @@ -405,11 +456,58 @@ static bool mlx5e_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *x) return true; } +struct mlx5e_ipsec_modify_state_work { + struct work_struct work; + struct mlx5_accel_esp_xfrm_attrs attrs; + struct mlx5e_ipsec_sa_entry *sa_entry; +}; + +static void _update_xfrm_state(struct work_struct *work) +{ + int ret; + struct mlx5e_ipsec_modify_state_work *modify_work = + container_of(work, struct mlx5e_ipsec_modify_state_work, work); + struct mlx5e_ipsec_sa_entry *sa_entry = modify_work->sa_entry; + + ret = mlx5_accel_esp_modify_xfrm(sa_entry->xfrm, + &modify_work->attrs); + if (ret) + netdev_warn(sa_entry->ipsec->en_priv->netdev, + "Not an IPSec offload device\n"); + + kfree(modify_work); +} + +static void mlx5e_xfrm_advance_esn_state(struct xfrm_state *x) +{ + struct mlx5e_ipsec_sa_entry *sa_entry = to_ipsec_sa_entry(x); + struct mlx5e_ipsec_modify_state_work *modify_work; + bool need_update; + + if (!sa_entry) + return; + + need_update = mlx5e_ipsec_update_esn_state(sa_entry); + if (!need_update) + return; + + modify_work = kzalloc(sizeof(*modify_work), GFP_ATOMIC); + if (!modify_work) + return; + + mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, &modify_work->attrs); + modify_work->sa_entry = sa_entry; + + INIT_WORK(&modify_work->work, _update_xfrm_state); + WARN_ON(!queue_work(sa_entry->ipsec->wq, &modify_work->work)); +} + static const struct xfrmdev_ops mlx5e_ipsec_xfrmdev_ops = { .xdo_dev_state_add = mlx5e_xfrm_add_state, .xdo_dev_state_delete = mlx5e_xfrm_del_state, .xdo_dev_state_free = mlx5e_xfrm_free_state, .xdo_dev_offload_ok = mlx5e_ipsec_offload_ok, + .xdo_dev_state_advance_esn = mlx5e_xfrm_advance_esn_state, }; void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index bffc3ed0574a..1198fc1eba4c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -40,7 +40,11 @@ #include #include +#include "accel/ipsec.h" + #define MLX5E_IPSEC_SADB_RX_BITS 10 +#define MLX5E_IPSEC_ESN_SCOPE_MID 0x80000000L + #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) #define MLX5E_METADATA_ETHER_LEN 8 @@ -82,6 +86,25 @@ struct mlx5e_ipsec { struct ida halloc; struct mlx5e_ipsec_sw_stats sw_stats; struct mlx5e_ipsec_stats stats; + struct workqueue_struct *wq; +}; + +struct mlx5e_ipsec_esn_state { + u32 esn; + u8 trigger: 1; + u8 overlap: 1; +}; + +struct mlx5e_ipsec_sa_entry { + struct hlist_node hlist; /* Item in SADB_RX hashtable */ + struct mlx5e_ipsec_esn_state esn_state; + unsigned int handle; /* Handle in SADB_RX */ + struct xfrm_state *x; + struct mlx5e_ipsec *ipsec; + struct mlx5_accel_esp_xfrm *xfrm; + void *hw_context; + void (*set_iv_op)(struct sk_buff *skb, struct xfrm_state *x, + struct xfrm_offload *xo); }; void mlx5e_ipsec_build_inverse_table(void); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c index 64c549a06678..c245d8e78509 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c @@ -176,7 +176,30 @@ static void mlx5e_ipsec_set_swp(struct sk_buff *skb, } } -static void mlx5e_ipsec_set_iv(struct sk_buff *skb, struct xfrm_offload *xo) +void mlx5e_ipsec_set_iv_esn(struct sk_buff *skb, struct xfrm_state *x, + struct xfrm_offload *xo) +{ + struct xfrm_replay_state_esn *replay_esn = x->replay_esn; + __u32 oseq = replay_esn->oseq; + int iv_offset; + __be64 seqno; + u32 seq_hi; + + if (unlikely(skb_is_gso(skb) && oseq < MLX5E_IPSEC_ESN_SCOPE_MID && + MLX5E_IPSEC_ESN_SCOPE_MID < (oseq - skb_shinfo(skb)->gso_segs))) { + seq_hi = xo->seq.hi - 1; + } else { + seq_hi = xo->seq.hi; + } + + /* Place the SN in the IV field */ + seqno = cpu_to_be64(xo->seq.low + ((u64)seq_hi << 32)); + iv_offset = skb_transport_offset(skb) + sizeof(struct ip_esp_hdr); + skb_store_bits(skb, iv_offset, &seqno, 8); +} + +void mlx5e_ipsec_set_iv(struct sk_buff *skb, struct xfrm_state *x, + struct xfrm_offload *xo) { int iv_offset; __be64 seqno; @@ -228,6 +251,7 @@ struct sk_buff *mlx5e_ipsec_handle_tx_skb(struct net_device *netdev, struct mlx5e_priv *priv = netdev_priv(netdev); struct xfrm_offload *xo = xfrm_offload(skb); struct mlx5e_ipsec_metadata *mdata; + struct mlx5e_ipsec_sa_entry *sa_entry; struct xfrm_state *x; if (!xo) @@ -262,7 +286,8 @@ struct sk_buff *mlx5e_ipsec_handle_tx_skb(struct net_device *netdev, goto drop; } mlx5e_ipsec_set_swp(skb, &wqe->eth, x->props.mode, xo); - mlx5e_ipsec_set_iv(skb, xo); + sa_entry = (struct mlx5e_ipsec_sa_entry *)x->xso.offload_handle; + sa_entry->set_iv_op(skb, x, xo); mlx5e_ipsec_set_metadata(skb, mdata, xo); return skb; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h index e37ae2598dbb..2bfbbef1b054 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h @@ -37,6 +37,7 @@ #ifdef CONFIG_MLX5_EN_IPSEC #include +#include #include "en.h" struct sk_buff *mlx5e_ipsec_handle_rx_skb(struct net_device *netdev, @@ -46,6 +47,10 @@ void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); void mlx5e_ipsec_inverse_table_init(void); bool mlx5e_ipsec_feature_check(struct sk_buff *skb, struct net_device *netdev, netdev_features_t features); +void mlx5e_ipsec_set_iv_esn(struct sk_buff *skb, struct xfrm_state *x, + struct xfrm_offload *xo); +void mlx5e_ipsec_set_iv(struct sk_buff *skb, struct xfrm_state *x, + struct xfrm_offload *xo); struct sk_buff *mlx5e_ipsec_handle_tx_skb(struct net_device *netdev, struct mlx5e_tx_wqe *wqe, struct sk_buff *skb); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c index 7b43fa269117..4f1568528738 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c @@ -347,6 +347,11 @@ u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev) if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, rx_no_trailer)) ret |= MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER; + if (MLX5_GET(ipsec_extended_cap, fdev->ipsec->caps, esn)) { + ret |= MLX5_ACCEL_IPSEC_CAP_ESN; + ret |= MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN; + } + return ret; } @@ -470,6 +475,23 @@ mlx5_fpga_ipsec_build_hw_xfrm(struct mlx5_core_dev *mdev, memcpy(&hw_sa->ipsec_sa_v1.gcm.salt, &aes_gcm->salt, sizeof(aes_gcm->salt)); + /* esn */ + if (xfrm_attrs->flags & MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED) { + hw_sa->ipsec_sa_v1.flags |= MLX5_FPGA_IPSEC_SA_ESN_EN; + hw_sa->ipsec_sa_v1.flags |= + (xfrm_attrs->flags & + MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP) ? + MLX5_FPGA_IPSEC_SA_ESN_OVERLAP : 0; + hw_sa->esn = htonl(xfrm_attrs->esn); + } else { + hw_sa->ipsec_sa_v1.flags &= ~MLX5_FPGA_IPSEC_SA_ESN_EN; + hw_sa->ipsec_sa_v1.flags &= + ~(xfrm_attrs->flags & + MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP) ? + MLX5_FPGA_IPSEC_SA_ESN_OVERLAP : 0; + hw_sa->esn = 0; + } + /* rx handle */ hw_sa->ipsec_sa_v1.sw_sa_handle = htonl(xfrm_attrs->sa_handle); diff --git a/include/linux/mlx5/accel.h b/include/linux/mlx5/accel.h index 6c694709b0a2..70e7e5673ce9 100644 --- a/include/linux/mlx5/accel.h +++ b/include/linux/mlx5/accel.h @@ -110,6 +110,8 @@ enum mlx5_accel_ipsec_cap { MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 3, MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 4, MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER = 1 << 5, + MLX5_ACCEL_IPSEC_CAP_ESN = 1 << 6, + MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN = 1 << 7, }; #ifdef CONFIG_MLX5_ACCEL diff --git a/include/linux/mlx5/mlx5_ifc_fpga.h b/include/linux/mlx5/mlx5_ifc_fpga.h index debcc57de43a..ec052491ba3d 100644 --- a/include/linux/mlx5/mlx5_ifc_fpga.h +++ b/include/linux/mlx5/mlx5_ifc_fpga.h @@ -468,6 +468,8 @@ struct mlx5_ifc_fpga_ipsec_cmd_cap { } __packed; enum mlx5_ifc_fpga_ipsec_sa_flags { + MLX5_FPGA_IPSEC_SA_ESN_EN = BIT(0), + MLX5_FPGA_IPSEC_SA_ESN_OVERLAP = BIT(1), MLX5_FPGA_IPSEC_SA_IPV6 = BIT(2), MLX5_FPGA_IPSEC_SA_DIR_SX = BIT(3), MLX5_FPGA_IPSEC_SA_SPI_EN = BIT(4), -- cgit v1.2.3 From 370ed7a9b9176d68c7b13e6cef32efa6ac5b2d97 Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Tue, 27 Feb 2018 13:22:07 +0100 Subject: extcon: add possibility to get extcon device by OF node Since extcon property is not allowed in DT, extcon subsystem requires another way to get extcon device. Lets try the simplest approach - get edev by of_node. Signed-off-by: Andrzej Hajda Acked-by: Chanwoo Choi Signed-off-by: Chanwoo Choi --- drivers/extcon/extcon.c | 44 ++++++++++++++++++++++++++++++++++---------- include/linux/extcon.h | 6 ++++++ 2 files changed, 40 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index cb38c2747684..8bff5fd18185 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -1336,6 +1336,28 @@ void extcon_dev_unregister(struct extcon_dev *edev) EXPORT_SYMBOL_GPL(extcon_dev_unregister); #ifdef CONFIG_OF + +/* + * extcon_find_edev_by_node - Find the extcon device from devicetree. + * @node : OF node identifying edev + * + * Return the pointer of extcon device if success or ERR_PTR(err) if fail. + */ +struct extcon_dev *extcon_find_edev_by_node(struct device_node *node) +{ + struct extcon_dev *edev; + + mutex_lock(&extcon_dev_list_lock); + list_for_each_entry(edev, &extcon_dev_list, entry) + if (edev->dev.parent && edev->dev.parent->of_node == node) + goto out; + edev = ERR_PTR(-EPROBE_DEFER); +out: + mutex_unlock(&extcon_dev_list_lock); + + return edev; +} + /* * extcon_get_edev_by_phandle - Get the extcon device from devicetree. * @dev : the instance to the given device @@ -1363,25 +1385,27 @@ struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, int index) return ERR_PTR(-ENODEV); } - mutex_lock(&extcon_dev_list_lock); - list_for_each_entry(edev, &extcon_dev_list, entry) { - if (edev->dev.parent && edev->dev.parent->of_node == node) { - mutex_unlock(&extcon_dev_list_lock); - of_node_put(node); - return edev; - } - } - mutex_unlock(&extcon_dev_list_lock); + edev = extcon_find_edev_by_node(node); of_node_put(node); - return ERR_PTR(-EPROBE_DEFER); + return edev; } + #else + +struct extcon_dev *extcon_find_edev_by_node(struct device_node *node) +{ + return ERR_PTR(-ENOSYS); +} + struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, int index) { return ERR_PTR(-ENOSYS); } + #endif /* CONFIG_OF */ + +EXPORT_SYMBOL_GPL(extcon_find_edev_by_node); EXPORT_SYMBOL_GPL(extcon_get_edev_by_phandle); /** diff --git a/include/linux/extcon.h b/include/linux/extcon.h index 6d94e82c8ad9..7f033b1ea568 100644 --- a/include/linux/extcon.h +++ b/include/linux/extcon.h @@ -230,6 +230,7 @@ extern void devm_extcon_unregister_notifier_all(struct device *dev, * Following APIs get the extcon_dev from devicetree or by through extcon name. */ extern struct extcon_dev *extcon_get_extcon_dev(const char *extcon_name); +extern struct extcon_dev *extcon_find_edev_by_node(struct device_node *node); extern struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, int index); @@ -283,6 +284,11 @@ static inline struct extcon_dev *extcon_get_extcon_dev(const char *extcon_name) return ERR_PTR(-ENODEV); } +static inline struct extcon_dev *extcon_find_edev_by_node(struct device_node *node) +{ + return ERR_PTR(-ENODEV); +} + static inline struct extcon_dev *extcon_get_edev_by_phandle(struct device *dev, int index) { -- cgit v1.2.3 From 3b3cd24ae61b3bbe9d3cecaff33e7cb3250ce47a Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Tue, 16 Jan 2018 16:27:09 +0530 Subject: phy: Add USB speed related PHY modes Add following USB speed related PHY modes: LS (Low Speed), FS (Full Speed), HS (High Speed), SS (Super Speed) Speed related information is required by some QCOM PHY drivers to program PHY monitor resume/remote-wakeup events in suspended state. Speed is needed in order to set correct polarity of wakeup events for detection. E.g. QUSB2 PHY monitors DP/DM line state depending on whether speed is LS or FS/HS to detect resume. Similarly QMP USB3 PHY in SS mode should monitor RX terminations attach/detach and LFPS events depending on SSPHY is active or not. Signed-off-by: Manu Gautam Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-core.c | 2 ++ include/linux/phy/phy.h | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'include/linux') diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 8f6e8e28996d..09ac8afb97ac 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -351,6 +351,8 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode) mutex_lock(&phy->mutex); ret = phy->ops->set_mode(phy, mode); + if (!ret) + phy->attrs.mode = mode; mutex_unlock(&phy->mutex); return ret; diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 4f8423a948d5..485469e6fa7f 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -25,7 +25,15 @@ struct phy; enum phy_mode { PHY_MODE_INVALID, PHY_MODE_USB_HOST, + PHY_MODE_USB_HOST_LS, + PHY_MODE_USB_HOST_FS, + PHY_MODE_USB_HOST_HS, + PHY_MODE_USB_HOST_SS, PHY_MODE_USB_DEVICE, + PHY_MODE_USB_DEVICE_LS, + PHY_MODE_USB_DEVICE_FS, + PHY_MODE_USB_DEVICE_HS, + PHY_MODE_USB_DEVICE_SS, PHY_MODE_USB_OTG, PHY_MODE_SGMII, PHY_MODE_10GKR, @@ -61,6 +69,7 @@ struct phy_ops { */ struct phy_attrs { u32 bus_width; + enum phy_mode mode; }; /** @@ -144,6 +153,10 @@ int phy_exit(struct phy *phy); int phy_power_on(struct phy *phy); int phy_power_off(struct phy *phy); int phy_set_mode(struct phy *phy, enum phy_mode mode); +static inline enum phy_mode phy_get_mode(struct phy *phy) +{ + return phy->attrs.mode; +} int phy_reset(struct phy *phy); int phy_calibrate(struct phy *phy); static inline int phy_get_bus_width(struct phy *phy) @@ -260,6 +273,11 @@ static inline int phy_set_mode(struct phy *phy, enum phy_mode mode) return -ENOSYS; } +static inline enum phy_mode phy_get_mode(struct phy *phy) +{ + return PHY_MODE_INVALID; +} + static inline int phy_reset(struct phy *phy) { if (!phy) -- cgit v1.2.3 From becaf17a58473e358e056ada2642e895aae93b0e Mon Sep 17 00:00:00 2001 From: Dov Levenglick Date: Fri, 2 Feb 2018 18:34:50 +0200 Subject: phy: fix structure documentation Add missing documentation of structure members and modify the order of documentation to match that of the structure declaration. Signed-off-by: Dov Levenglick Signed-off-by: Kishon Vijay Abraham I --- include/linux/phy/phy.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 485469e6fa7f..c9d14eeee7f5 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -81,7 +81,8 @@ struct phy_attrs { * @mutex: mutex to protect phy_ops * @init_count: used to protect when the PHY is used by multiple consumers * @power_count: used to protect when the PHY is used by multiple consumers - * @phy_attrs: used to specify PHY specific attributes + * @attrs: used to specify PHY specific attributes + * @pwr: power regulator associated with the phy */ struct phy { struct device dev; @@ -97,9 +98,10 @@ struct phy { /** * struct phy_provider - represents the phy provider * @dev: phy provider device + * @children: can be used to override the default (dev->of_node) child node * @owner: the module owner having of_xlate - * @of_xlate: function pointer to obtain phy instance from phy pointer * @list: to maintain a linked list of PHY providers + * @of_xlate: function pointer to obtain phy instance from phy pointer */ struct phy_provider { struct device *dev; @@ -110,6 +112,13 @@ struct phy_provider { struct of_phandle_args *args); }; +/** + * struct phy_lookup - PHY association in list of phys managed by the phy driver + * @node: list node + * @dev_id: the device of the association + * @con_id: connection ID string on device + * @phy: the phy of the association + */ struct phy_lookup { struct list_head node; const char *dev_id; -- cgit v1.2.3 From 4902c2025b8ade9c230d4bca25ec5f691e91cb1f Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 26 Jul 2017 16:47:27 +0300 Subject: clk: ti: add support for register read-modify-write low-level operation Useful for changing few bits on a register, this makes sure for example that the operation is done atomically in case of syscon. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk.c | 24 ++++++++++++++++++++++++ include/linux/clk/ti.h | 2 ++ 2 files changed, 26 insertions(+) (limited to 'include/linux') diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index f4d6802a8544..4efa2c9ea908 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -55,6 +55,29 @@ static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg) writel_relaxed(val, io->mem + reg->offset); } +static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr) +{ + u32 v; + + v = readl_relaxed(ptr); + v &= ~mask; + v |= val; + writel_relaxed(v, ptr); +} + +static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg) +{ + struct clk_iomap *io = clk_memmaps[reg->index]; + + if (reg->ptr) { + _clk_rmw(val, mask, reg->ptr); + } else if (io->regmap) { + regmap_update_bits(io->regmap, reg->offset, mask, val); + } else { + _clk_rmw(val, mask, io->mem + reg->offset); + } +} + static u32 clk_memmap_readl(const struct clk_omap_reg *reg) { u32 val; @@ -89,6 +112,7 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) ti_clk_ll_ops = ops; ops->clk_readl = clk_memmap_readl; ops->clk_writel = clk_memmap_writel; + ops->clk_rmw = clk_memmap_rmw; return 0; } diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index d18da839b810..9e8611470187 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -211,6 +211,7 @@ enum { * struct ti_clk_ll_ops - low-level ops for clocks * @clk_readl: pointer to register read function * @clk_writel: pointer to register write function + * @clk_rmw: pointer to register read-modify-write function * @clkdm_clk_enable: pointer to clockdomain enable function * @clkdm_clk_disable: pointer to clockdomain disable function * @clkdm_lookup: pointer to clockdomain lookup function @@ -226,6 +227,7 @@ enum { struct ti_clk_ll_ops { u32 (*clk_readl)(const struct clk_omap_reg *reg); void (*clk_writel)(u32 val, const struct clk_omap_reg *reg); + void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg); int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk); int (*clkdm_clk_disable)(struct clockdomain *clkdm, struct clk *clk); -- cgit v1.2.3 From 63338a38db955cb4e0352c11b78732157c78d30b Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Wed, 7 Mar 2018 08:39:12 +0100 Subject: jailhouse: Provide detection for non-x86 systems Implement jailhouse_paravirt() via device tree probing on architectures != x86. Will be used by the PCI core. Signed-off-by: Jan Kiszka Signed-off-by: Thomas Gleixner Reviewed-by: Juergen Gross Cc: jailhouse-dev@googlegroups.com Cc: Mark Rutland Cc: linux-pci@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: Andy Shevchenko Cc: Rob Herring Cc: Bjorn Helgaas Link: https://lkml.kernel.org/r/dae9fe0c6e63141c28ca90492fa5712b4c33ffb5.1520408357.git.jan.kiszka@siemens.com --- Documentation/devicetree/bindings/jailhouse.txt | 8 ++++++++ arch/x86/include/asm/jailhouse_para.h | 2 +- include/linux/hypervisor.h | 17 +++++++++++++++-- 3 files changed, 24 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/jailhouse.txt (limited to 'include/linux') diff --git a/Documentation/devicetree/bindings/jailhouse.txt b/Documentation/devicetree/bindings/jailhouse.txt new file mode 100644 index 000000000000..2901c25ff340 --- /dev/null +++ b/Documentation/devicetree/bindings/jailhouse.txt @@ -0,0 +1,8 @@ +Jailhouse non-root cell device tree bindings +-------------------------------------------- + +When running in a non-root Jailhouse cell (partition), the device tree of this +platform shall have a top-level "hypervisor" node with the following +properties: + +- compatible = "jailhouse,cell" diff --git a/arch/x86/include/asm/jailhouse_para.h b/arch/x86/include/asm/jailhouse_para.h index 875b54376689..b885a961a150 100644 --- a/arch/x86/include/asm/jailhouse_para.h +++ b/arch/x86/include/asm/jailhouse_para.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL2.0 */ /* - * Jailhouse paravirt_ops implementation + * Jailhouse paravirt detection * * Copyright (c) Siemens AG, 2015-2017 * diff --git a/include/linux/hypervisor.h b/include/linux/hypervisor.h index b19563f9a8eb..fc08b433c856 100644 --- a/include/linux/hypervisor.h +++ b/include/linux/hypervisor.h @@ -8,15 +8,28 @@ */ #ifdef CONFIG_X86 + +#include #include + static inline void hypervisor_pin_vcpu(int cpu) { x86_platform.hyper.pin_vcpu(cpu); } -#else + +#else /* !CONFIG_X86 */ + +#include + static inline void hypervisor_pin_vcpu(int cpu) { } -#endif + +static inline bool jailhouse_paravirt(void) +{ + return of_find_compatible_node(NULL, NULL, "jailhouse,cell"); +} + +#endif /* !CONFIG_X86 */ #endif /* __LINUX_HYPEVISOR_H */ -- cgit v1.2.3 From 5d6ae4f0da8a64a185074dabb1b2f8c148efa741 Mon Sep 17 00:00:00 2001 From: Chris Dickens Date: Sun, 31 Dec 2017 18:59:42 -0800 Subject: usb: gadget: composite: fix incorrect handling of OS desc requests When handling an OS descriptor request, one of the first operations is to zero out the request buffer using the wLength from the setup packet. There is no bounds checking, so a wLength > 4096 would clobber memory adjacent to the request buffer. Fix this by taking the min of wLength and the request buffer length prior to the memset. While at it, define the buffer length in a header file so that magic numbers don't appear throughout the code. When returning data to the host, the data length should be the min of the wLength and the valid data we have to return. Currently we are returning wLength, thus requests for a wLength greater than the amount of data in the OS descriptor buffer would return invalid (albeit zero'd) data following the valid descriptor data. Fix this by counting the number of bytes when constructing the data and using this when determining the length of the request. Signed-off-by: Chris Dickens Signed-off-by: Felipe Balbi --- drivers/usb/gadget/composite.c | 40 +++++++++++++++++++--------------------- include/linux/usb/composite.h | 3 +++ 2 files changed, 22 insertions(+), 21 deletions(-) (limited to 'include/linux') diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 77c7ecca816a..b8b629c615d3 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -1422,7 +1422,7 @@ static int count_ext_compat(struct usb_configuration *c) return res; } -static void fill_ext_compat(struct usb_configuration *c, u8 *buf) +static int fill_ext_compat(struct usb_configuration *c, u8 *buf) { int i, count; @@ -1449,10 +1449,12 @@ static void fill_ext_compat(struct usb_configuration *c, u8 *buf) buf += 23; } count += 24; - if (count >= 4096) - return; + if (count + 24 >= USB_COMP_EP0_OS_DESC_BUFSIZ) + return count; } } + + return count; } static int count_ext_prop(struct usb_configuration *c, int interface) @@ -1497,25 +1499,20 @@ static int fill_ext_prop(struct usb_configuration *c, int interface, u8 *buf) struct usb_os_desc *d; struct usb_os_desc_ext_prop *ext_prop; int j, count, n, ret; - u8 *start = buf; f = c->interface[interface]; + count = 10; /* header length */ for (j = 0; j < f->os_desc_n; ++j) { if (interface != f->os_desc_table[j].if_id) continue; d = f->os_desc_table[j].os_desc; if (d) list_for_each_entry(ext_prop, &d->ext_prop, entry) { - /* 4kB minus header length */ - n = buf - start; - if (n >= 4086) - return 0; - - count = ext_prop->data_len + + n = ext_prop->data_len + ext_prop->name_len + 14; - if (count > 4086 - n) - return -EINVAL; - usb_ext_prop_put_size(buf, count); + if (count + n >= USB_COMP_EP0_OS_DESC_BUFSIZ) + return count; + usb_ext_prop_put_size(buf, n); usb_ext_prop_put_type(buf, ext_prop->type); ret = usb_ext_prop_put_name(buf, ext_prop->name, ext_prop->name_len); @@ -1541,11 +1538,12 @@ static int fill_ext_prop(struct usb_configuration *c, int interface, u8 *buf) default: return -EINVAL; } - buf += count; + buf += n; + count += n; } } - return 0; + return count; } /* @@ -1827,6 +1825,7 @@ unknown: req->complete = composite_setup_complete; buf = req->buf; os_desc_cfg = cdev->os_desc_config; + w_length = min_t(u16, w_length, USB_COMP_EP0_OS_DESC_BUFSIZ); memset(buf, 0, w_length); buf[5] = 0x01; switch (ctrl->bRequestType & USB_RECIP_MASK) { @@ -1850,8 +1849,8 @@ unknown: count += 16; /* header */ put_unaligned_le32(count, buf); buf += 16; - fill_ext_compat(os_desc_cfg, buf); - value = w_length; + value = fill_ext_compat(os_desc_cfg, buf); + value = min_t(u16, w_length, value); } break; case USB_RECIP_INTERFACE: @@ -1880,8 +1879,7 @@ unknown: interface, buf); if (value < 0) return value; - - value = w_length; + value = min_t(u16, w_length, value); } break; } @@ -2156,8 +2154,8 @@ int composite_os_desc_req_prepare(struct usb_composite_dev *cdev, goto end; } - /* OS feature descriptor length <= 4kB */ - cdev->os_desc_req->buf = kmalloc(4096, GFP_KERNEL); + cdev->os_desc_req->buf = kmalloc(USB_COMP_EP0_OS_DESC_BUFSIZ, + GFP_KERNEL); if (!cdev->os_desc_req->buf) { ret = -ENOMEM; usb_ep_free_request(ep0, cdev->os_desc_req); diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h index cef0e44601f8..4b6b9283fa7b 100644 --- a/include/linux/usb/composite.h +++ b/include/linux/usb/composite.h @@ -54,6 +54,9 @@ /* big enough to hold our biggest descriptor */ #define USB_COMP_EP0_BUFSIZ 1024 +/* OS feature descriptor length <= 4kB */ +#define USB_COMP_EP0_OS_DESC_BUFSIZ 4096 + #define USB_MS_TO_HS_INTERVAL(x) (ilog2((x * 1000 / 125)) + 1) struct usb_configuration; -- cgit v1.2.3 From f2b9ba871beb92fd6884b957acb14621b15fbe2b Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 6 Mar 2018 17:15:32 +0000 Subject: arm64/kernel: kaslr: reduce module randomization range to 4 GB We currently have to rely on the GCC large code model for KASLR for two distinct but related reasons: - if we enable full randomization, modules will be loaded very far away from the core kernel, where they are out of range for ADRP instructions, - even without full randomization, the fact that the 128 MB module region is now no longer fully reserved for kernel modules means that there is a very low likelihood that the normal bottom-up allocation of other vmalloc regions may collide, and use up the range for other things. Large model code is suboptimal, given that each symbol reference involves a literal load that goes through the D-cache, reducing cache utilization. But more importantly, literals are not instructions but part of .text nonetheless, and hence mapped with executable permissions. So let's get rid of our dependency on the large model for KASLR, by: - reducing the full randomization range to 4 GB, thereby ensuring that ADRP references between modules and the kernel are always in range, - reduce the spillover range to 4 GB as well, so that we fallback to a region that is still guaranteed to be in range - move the randomization window of the core kernel to the middle of the VMALLOC space Note that KASAN always uses the module region outside of the vmalloc space, so keep the kernel close to that if KASAN is enabled. Signed-off-by: Ard Biesheuvel Signed-off-by: Will Deacon --- arch/arm64/Kconfig | 7 +++---- arch/arm64/kernel/kaslr.c | 20 ++++++++++++-------- arch/arm64/kernel/module.c | 7 ++++--- include/linux/sizes.h | 4 ++++ 4 files changed, 23 insertions(+), 15 deletions(-) (limited to 'include/linux') diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 655c0e99d9fa..b4234ddf6570 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1110,7 +1110,6 @@ config ARM64_MODULE_CMODEL_LARGE config ARM64_MODULE_PLTS bool - select ARM64_MODULE_CMODEL_LARGE select HAVE_MOD_ARCH_SPECIFIC config RELOCATABLE @@ -1144,12 +1143,12 @@ config RANDOMIZE_BASE If unsure, say N. config RANDOMIZE_MODULE_REGION_FULL - bool "Randomize the module region independently from the core kernel" + bool "Randomize the module region over a 4 GB range" depends on RANDOMIZE_BASE default y help - Randomizes the location of the module region without considering the - location of the core kernel. This way, it is impossible for modules + Randomizes the location of the module region inside a 4 GB window + covering the core kernel. This way, it is less likely for modules to leak information about the location of core kernel data structures but it does imply that function calls between modules and the core kernel will need to be resolved via veneers in the module PLT. diff --git a/arch/arm64/kernel/kaslr.c b/arch/arm64/kernel/kaslr.c index e3d5cbe2167b..f0e6ab8abe9c 100644 --- a/arch/arm64/kernel/kaslr.c +++ b/arch/arm64/kernel/kaslr.c @@ -117,13 +117,15 @@ u64 __init kaslr_early_init(u64 dt_phys) /* * OK, so we are proceeding with KASLR enabled. Calculate a suitable * kernel image offset from the seed. Let's place the kernel in the - * lower half of the VMALLOC area (VA_BITS - 2). + * middle half of the VMALLOC area (VA_BITS - 2), and stay clear of + * the lower and upper quarters to avoid colliding with other + * allocations. * Even if we could randomize at page granularity for 16k and 64k pages, * let's always round to 2 MB so we don't interfere with the ability to * map using contiguous PTEs */ mask = ((1UL << (VA_BITS - 2)) - 1) & ~(SZ_2M - 1); - offset = seed & mask; + offset = BIT(VA_BITS - 3) + (seed & mask); /* use the top 16 bits to randomize the linear region */ memstart_offset_seed = seed >> 48; @@ -134,21 +136,23 @@ u64 __init kaslr_early_init(u64 dt_phys) * vmalloc region, since shadow memory is allocated for each * module at load time, whereas the vmalloc region is shadowed * by KASAN zero pages. So keep modules out of the vmalloc - * region if KASAN is enabled. + * region if KASAN is enabled, and put the kernel well within + * 4 GB of the module region. */ - return offset; + return offset % SZ_2G; if (IS_ENABLED(CONFIG_RANDOMIZE_MODULE_REGION_FULL)) { /* - * Randomize the module region independently from the core - * kernel. This prevents modules from leaking any information + * Randomize the module region over a 4 GB window covering the + * kernel. This reduces the risk of modules leaking information * about the address of the kernel itself, but results in * branches between modules and the core kernel that are * resolved via PLTs. (Branches between modules will be * resolved normally.) */ - module_range = VMALLOC_END - VMALLOC_START - MODULES_VSIZE; - module_alloc_base = VMALLOC_START; + module_range = SZ_4G - (u64)(_end - _stext); + module_alloc_base = max((u64)_end + offset - SZ_4G, + (u64)MODULES_VADDR); } else { /* * Randomize the module region by setting module_alloc_base to diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index c8c6c2828b79..70c3e5518e95 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -55,9 +55,10 @@ void *module_alloc(unsigned long size) * less likely that the module region gets exhausted, so we * can simply omit this fallback in that case. */ - p = __vmalloc_node_range(size, MODULE_ALIGN, VMALLOC_START, - VMALLOC_END, GFP_KERNEL, PAGE_KERNEL_EXEC, 0, - NUMA_NO_NODE, __builtin_return_address(0)); + p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, + module_alloc_base + SZ_4G, GFP_KERNEL, + PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, + __builtin_return_address(0)); if (p && (kasan_module_alloc(p, size) < 0)) { vfree(p); diff --git a/include/linux/sizes.h b/include/linux/sizes.h index ce3e8150c174..fbde0bc7e882 100644 --- a/include/linux/sizes.h +++ b/include/linux/sizes.h @@ -8,6 +8,8 @@ #ifndef __LINUX_SIZES_H__ #define __LINUX_SIZES_H__ +#include + #define SZ_1 0x00000001 #define SZ_2 0x00000002 #define SZ_4 0x00000004 @@ -44,4 +46,6 @@ #define SZ_1G 0x40000000 #define SZ_2G 0x80000000 +#define SZ_4G _AC(0x100000000, ULL) + #endif /* __LINUX_SIZES_H__ */ -- cgit v1.2.3 From e403d00573431e1e3de1710a91c6090c60ec16af Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Thu, 25 Jan 2018 16:00:12 +0200 Subject: clk: tegra: MBIST work around for Tegra210 Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a domain. The reason is that the logic responsible for resetting the memory built-in self test mode can come up in an undefined state because its clock is gated by a second level clock gate (SLCG). Work around this by making sure the logic will get some clock edges by ensuring the relevant clock is enabled and temporarily override the relevant SLCGs. Unfortunately for some IP blocks, the control bits for overriding the SLCGs are not in CAR, but in the IP block itself. This means we need to map a few extra register banks in the clock code. Signed-off-by: Peter De Schrijver Reviewed-by: Jon Hunter Tested-by: Jon Hunter Tested-by: Hector Martin Tested-by: Andre Heider Tested-by: Mikko Perttunen Signed-off-by: Thierry Reding fixup mbist --- drivers/clk/tegra/clk-tegra210.c | 344 ++++++++++++++++++++++++++++++++++++++- include/linux/clk/tegra.h | 1 + 2 files changed, 343 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index f790c2dc5b5d..946d708add1e 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -22,10 +22,12 @@ #include #include #include +#include #include #include #include #include +#include #include "clk.h" #include "clk-id.h" @@ -232,6 +234,30 @@ #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac +#define LVL2_CLK_GATE_OVRA 0xf8 +#define LVL2_CLK_GATE_OVRC 0x3a0 +#define LVL2_CLK_GATE_OVRD 0x3a4 +#define LVL2_CLK_GATE_OVRE 0x554 + +/* I2S registers to handle during APE MBIST WAR */ +#define TEGRA210_I2S_BASE 0x1000 +#define TEGRA210_I2S_SIZE 0x100 +#define TEGRA210_I2S_CTRLS 5 +#define TEGRA210_I2S_CG 0x88 +#define TEGRA210_I2S_CTRL 0xa0 + +/* DISPA registers to handle during MBIST WAR */ +#define DC_CMD_DISPLAY_COMMAND 0xc8 +#define DC_COM_DSC_TOP_CTL 0xcf8 + +/* VIC register to handle during MBIST WAR */ +#define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c + +/* APE, DISPA and VIC base addesses needed for MBIST WAR */ +#define TEGRA210_AHUB_BASE 0x702d0000 +#define TEGRA210_DISPA_BASE 0x54200000 +#define TEGRA210_VIC_BASE 0x54340000 + /* * SDM fractional divisor is 16-bit 2's complement signed number within * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned @@ -256,8 +282,22 @@ static struct cpu_clk_suspend_context { } tegra210_cpu_clk_sctx; #endif +struct tegra210_domain_mbist_war { + void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist); + const u32 lvl2_offset; + const u32 lvl2_mask; + const unsigned int num_clks; + const unsigned int *clk_init_data; + struct clk_bulk_data *clks; +}; + +static struct clk **clks; + static void __iomem *clk_base; static void __iomem *pmc_base; +static void __iomem *ahub_base; +static void __iomem *dispa_base; +static void __iomem *vic_base; static unsigned long osc_freq; static unsigned long pll_ref_freq; @@ -268,6 +308,7 @@ static DEFINE_SPINLOCK(pll_re_lock); static DEFINE_SPINLOCK(pll_u_lock); static DEFINE_SPINLOCK(sor1_lock); static DEFINE_SPINLOCK(emc_lock); +static DEFINE_MUTEX(lvl2_ovr_lock); /* possible OSC frequencies in Hz */ static unsigned long tegra210_input_freq[] = { @@ -311,6 +352,8 @@ static const char *mux_pllmcp_clkm[] = { #define PLLA_MISC2_WRITE_MASK 0x06ffffff /* PLLD */ +#define PLLD_BASE_CSI_CLKSOURCE (1 << 23) + #define PLLD_MISC0_EN_SDM (1 << 16) #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17) #define PLLD_MISC0_LOCK_ENABLE (1 << 18) @@ -514,6 +557,115 @@ void tegra210_set_sata_pll_seq_sw(bool state) } EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); +static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist) +{ + u32 val; + + val = readl_relaxed(clk_base + mbist->lvl2_offset); + writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); + fence_udelay(1, clk_base); + writel_relaxed(val, clk_base + mbist->lvl2_offset); + fence_udelay(1, clk_base); +} + +static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist) +{ + u32 csi_src, ovra, ovre; + unsigned long flags = 0; + + spin_lock_irqsave(&pll_d_lock, flags); + + csi_src = readl_relaxed(clk_base + PLLD_BASE); + writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); + fence_udelay(1, clk_base); + + ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); + writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); + ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); + writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); + fence_udelay(1, clk_base); + + writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); + writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); + writel_relaxed(csi_src, clk_base + PLLD_BASE); + fence_udelay(1, clk_base); + + spin_unlock_irqrestore(&pll_d_lock, flags); +} + +static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist) +{ + u32 ovra, dsc_top_ctrl; + + ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); + writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA); + fence_udelay(1, clk_base); + + dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL); + writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL); + readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND); + writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL); + readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND); + + writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); + fence_udelay(1, clk_base); +} + +static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist) +{ + u32 ovre, val; + + ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); + writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); + fence_udelay(1, clk_base); + + val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); + writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24), + vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); + fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); + + writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); + readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); + + writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); + fence_udelay(1, clk_base); +} + +static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist) +{ + void __iomem *i2s_base; + unsigned int i; + u32 ovrc, ovre; + + ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC); + ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); + writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC); + writel_relaxed(ovre | BIT(10) | BIT(11), + clk_base + LVL2_CLK_GATE_OVRE); + fence_udelay(1, clk_base); + + i2s_base = ahub_base + TEGRA210_I2S_BASE; + + for (i = 0; i < TEGRA210_I2S_CTRLS; i++) { + u32 i2s_ctrl; + + i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL); + writel_relaxed(i2s_ctrl | BIT(10), + i2s_base + TEGRA210_I2S_CTRL); + writel_relaxed(0, i2s_base + TEGRA210_I2S_CG); + readl(i2s_base + TEGRA210_I2S_CG); + writel_relaxed(1, i2s_base + TEGRA210_I2S_CG); + writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL); + readl(i2s_base + TEGRA210_I2S_CTRL); + + i2s_base += TEGRA210_I2S_SIZE; + } + + writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC); + writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); + fence_udelay(1, clk_base); +} + static inline void _pll_misc_chk_default(void __iomem *base, struct tegra_clk_pll_params *params, u8 misc_num, u32 default_val, u32 mask) @@ -2412,13 +2564,150 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = { { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" }, }; -static struct clk **clks; - static const char * const aclk_parents[] = { "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", "clk_m" }; +static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC }; +static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG }; +static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X, + TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 }; +static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA, + TEGRA210_CLK_HOST1X}; +static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST, + TEGRA210_CLK_XUSB_DEV }; +static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST, + TEGRA210_CLK_XUSB_SS }; +static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV, + TEGRA210_CLK_XUSB_SS }; +static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X, + TEGRA210_CLK_PLL_D }; +static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK, + TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2, + TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT, + TEGRA210_CLK_D_AUDIO }; +static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X }; + +static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = { + [TEGRA_POWERGATE_VENC] = { + .handle_lvl2_ovr = tegra210_venc_mbist_war, + .num_clks = ARRAY_SIZE(venc_slcg_clkids), + .clk_init_data = venc_slcg_clkids, + }, + [TEGRA_POWERGATE_SATA] = { + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRC, + .lvl2_mask = BIT(0) | BIT(17) | BIT(19), + }, + [TEGRA_POWERGATE_MPE] = { + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRE, + .lvl2_mask = BIT(2), + }, + [TEGRA_POWERGATE_SOR] = { + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .num_clks = ARRAY_SIZE(sor_slcg_clkids), + .clk_init_data = sor_slcg_clkids, + .lvl2_offset = LVL2_CLK_GATE_OVRA, + .lvl2_mask = BIT(1) | BIT(2), + }, + [TEGRA_POWERGATE_DIS] = { + .handle_lvl2_ovr = tegra210_disp_mbist_war, + .num_clks = ARRAY_SIZE(disp_slcg_clkids), + .clk_init_data = disp_slcg_clkids, + }, + [TEGRA_POWERGATE_DISB] = { + .num_clks = ARRAY_SIZE(disp_slcg_clkids), + .clk_init_data = disp_slcg_clkids, + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRA, + .lvl2_mask = BIT(2), + }, + [TEGRA_POWERGATE_XUSBA] = { + .num_clks = ARRAY_SIZE(xusba_slcg_clkids), + .clk_init_data = xusba_slcg_clkids, + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRC, + .lvl2_mask = BIT(30) | BIT(31), + }, + [TEGRA_POWERGATE_XUSBB] = { + .num_clks = ARRAY_SIZE(xusbb_slcg_clkids), + .clk_init_data = xusbb_slcg_clkids, + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRC, + .lvl2_mask = BIT(30) | BIT(31), + }, + [TEGRA_POWERGATE_XUSBC] = { + .num_clks = ARRAY_SIZE(xusbc_slcg_clkids), + .clk_init_data = xusbc_slcg_clkids, + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRC, + .lvl2_mask = BIT(30) | BIT(31), + }, + [TEGRA_POWERGATE_VIC] = { + .num_clks = ARRAY_SIZE(vic_slcg_clkids), + .clk_init_data = vic_slcg_clkids, + .handle_lvl2_ovr = tegra210_vic_mbist_war, + }, + [TEGRA_POWERGATE_NVDEC] = { + .num_clks = ARRAY_SIZE(nvdec_slcg_clkids), + .clk_init_data = nvdec_slcg_clkids, + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRC, + .lvl2_mask = BIT(9) | BIT(31), + }, + [TEGRA_POWERGATE_NVJPG] = { + .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids), + .clk_init_data = nvjpg_slcg_clkids, + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRC, + .lvl2_mask = BIT(9) | BIT(31), + }, + [TEGRA_POWERGATE_AUD] = { + .num_clks = ARRAY_SIZE(ape_slcg_clkids), + .clk_init_data = ape_slcg_clkids, + .handle_lvl2_ovr = tegra210_ape_mbist_war, + }, + [TEGRA_POWERGATE_VE2] = { + .handle_lvl2_ovr = tegra210_generic_mbist_war, + .lvl2_offset = LVL2_CLK_GATE_OVRD, + .lvl2_mask = BIT(22), + }, +}; + +int tegra210_clk_handle_mbist_war(unsigned int id) +{ + int err; + struct tegra210_domain_mbist_war *mbist_war; + + if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) { + WARN(1, "unknown domain id in MBIST WAR handler\n"); + return -EINVAL; + } + + mbist_war = &tegra210_pg_mbist_war[id]; + if (!mbist_war->handle_lvl2_ovr) + return 0; + + if (mbist_war->num_clks && !mbist_war->clks) + return -ENODEV; + + err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks); + if (err < 0) + return err; + + mutex_lock(&lvl2_ovr_lock); + + mbist_war->handle_lvl2_ovr(mbist_war); + + mutex_unlock(&lvl2_ovr_lock); + + clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks); + + return 0; +} + void tegra210_put_utmipll_in_iddq(void) { u32 reg; @@ -3163,6 +3452,37 @@ static int tegra210_reset_deassert(unsigned long id) return 0; } +static void tegra210_mbist_clk_init(void) +{ + unsigned int i, j; + + for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) { + unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks; + struct clk_bulk_data *clk_data; + + if (!num_clks) + continue; + + clk_data = kmalloc_array(num_clks, sizeof(*clk_data), + GFP_KERNEL); + if (WARN_ON(!clk_data)) + return; + + tegra210_pg_mbist_war[i].clks = clk_data; + for (j = 0; j < num_clks; j++) { + int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j]; + struct clk *clk = clks[clk_id]; + + if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) { + kfree(clk_data); + tegra210_pg_mbist_war[i].clks = NULL; + break; + } + clk_data[j].clk = clk; + } + } +} + /** * tegra210_clock_init - Tegra210-specific clock initialization * @np: struct device_node * of the DT node for the SoC CAR IP block @@ -3197,6 +3517,24 @@ static void __init tegra210_clock_init(struct device_node *np) return; } + ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K); + if (!ahub_base) { + pr_err("ioremap tegra210 APE failed\n"); + return; + } + + dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K); + if (!dispa_base) { + pr_err("ioremap tegra210 DISPA failed\n"); + return; + } + + vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K); + if (!vic_base) { + pr_err("ioremap tegra210 VIC failed\n"); + return; + } + clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, TEGRA210_CAR_BANK_COUNT); if (!clks) @@ -3233,6 +3571,8 @@ static void __init tegra210_clock_init(struct device_node *np) tegra_add_of_provider(np); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); + tegra210_mbist_clk_init(); + tegra_cpu_car_ops = &tegra210_cpu_car_ops; } CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index d23c9cf26993..afb9edfa5d58 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -128,5 +128,6 @@ extern void tegra210_sata_pll_hw_sequence_start(void); extern void tegra210_set_sata_pll_seq_sw(bool state); extern void tegra210_put_utmipll_in_iddq(void); extern void tegra210_put_utmipll_out_iddq(void); +extern int tegra210_clk_handle_mbist_war(unsigned int id); #endif /* __LINUX_CLK_TEGRA_H_ */ -- cgit v1.2.3 From 66f91322f39cd18a01524264464c2ff4c98c936e Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Wed, 7 Mar 2018 17:10:02 -0800 Subject: block: Reorder the queue flag manipulation function definitions Move the definition of queue_flag_clear_unlocked() up and move the definition of queue_in_flight() down such that all queue flag manipulation function definitions become contiguous. This patch does not change any functionality. Cc: Christoph Hellwig Cc: Hannes Reinecke Cc: Ming Lei Reviewed-by: Johannes Thumshirn Reviewed-by: Martin K. Petersen Signed-off-by: Bart Van Assche Signed-off-by: Jens Axboe --- include/linux/blkdev.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'include/linux') diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 667a9b0053d9..c351aaec3ca7 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -726,6 +726,12 @@ static inline void queue_flag_set_unlocked(unsigned int flag, __set_bit(flag, &q->queue_flags); } +static inline void queue_flag_clear_unlocked(unsigned int flag, + struct request_queue *q) +{ + __clear_bit(flag, &q->queue_flags); +} + static inline int queue_flag_test_and_clear(unsigned int flag, struct request_queue *q) { @@ -758,17 +764,6 @@ static inline void queue_flag_set(unsigned int flag, struct request_queue *q) __set_bit(flag, &q->queue_flags); } -static inline void queue_flag_clear_unlocked(unsigned int flag, - struct request_queue *q) -{ - __clear_bit(flag, &q->queue_flags); -} - -static inline int queue_in_flight(struct request_queue *q) -{ - return q->in_flight[0] + q->in_flight[1]; -} - static inline void queue_flag_clear(unsigned int flag, struct request_queue *q) { queue_lockdep_assert_held(q); @@ -804,6 +799,11 @@ static inline void queue_flag_clear(unsigned int flag, struct request_queue *q) extern int blk_set_preempt_only(struct request_queue *q); extern void blk_clear_preempt_only(struct request_queue *q); +static inline int queue_in_flight(struct request_queue *q) +{ + return q->in_flight[0] + q->in_flight[1]; +} + static inline bool blk_account_rq(struct request *rq) { return (rq->rq_flags & RQF_STARTED) && !blk_rq_is_passthrough(rq); -- cgit v1.2.3 From 8814ce8a0f680599a837af18aefdec774e5c7b97 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Wed, 7 Mar 2018 17:10:04 -0800 Subject: block: Introduce blk_queue_flag_{set,clear,test_and_{set,clear}}() Introduce functions that modify the queue flags and that protect these modifications with the request queue lock. Except for moving one wake_up_all() call from inside to outside a critical section, this patch does not change any functionality. Cc: Christoph Hellwig Cc: Hannes Reinecke Cc: Ming Lei Reviewed-by: Johannes Thumshirn Reviewed-by: Martin K. Petersen Signed-off-by: Bart Van Assche Signed-off-by: Jens Axboe --- block/blk-core.c | 91 +++++++++++++++++++++++++++++++++++++++++--------- block/blk-mq.c | 12 ++----- block/blk-settings.c | 6 ++-- block/blk-sysfs.c | 22 ++++-------- block/blk-timeout.c | 6 ++-- include/linux/blkdev.h | 5 +++ 6 files changed, 93 insertions(+), 49 deletions(-) (limited to 'include/linux') diff --git a/block/blk-core.c b/block/blk-core.c index 241b73088617..74c6283f4509 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -71,6 +71,78 @@ struct kmem_cache *blk_requestq_cachep; */ static struct workqueue_struct *kblockd_workqueue; +/** + * blk_queue_flag_set - atomically set a queue flag + * @flag: flag to be set + * @q: request queue + */ +void blk_queue_flag_set(unsigned int flag, struct request_queue *q) +{ + unsigned long flags; + + spin_lock_irqsave(q->queue_lock, flags); + queue_flag_set(flag, q); + spin_unlock_irqrestore(q->queue_lock, flags); +} +EXPORT_SYMBOL(blk_queue_flag_set); + +/** + * blk_queue_flag_clear - atomically clear a queue flag + * @flag: flag to be cleared + * @q: request queue + */ +void blk_queue_flag_clear(unsigned int flag, struct request_queue *q) +{ + unsigned long flags; + + spin_lock_irqsave(q->queue_lock, flags); + queue_flag_clear(flag, q); + spin_unlock_irqrestore(q->queue_lock, flags); +} +EXPORT_SYMBOL(blk_queue_flag_clear); + +/** + * blk_queue_flag_test_and_set - atomically test and set a queue flag + * @flag: flag to be set + * @q: request queue + * + * Returns the previous value of @flag - 0 if the flag was not set and 1 if + * the flag was already set. + */ +bool blk_queue_flag_test_and_set(unsigned int flag, struct request_queue *q) +{ + unsigned long flags; + bool res; + + spin_lock_irqsave(q->queue_lock, flags); + res = queue_flag_test_and_set(flag, q); + spin_unlock_irqrestore(q->queue_lock, flags); + + return res; +} +EXPORT_SYMBOL_GPL(blk_queue_flag_test_and_set); + +/** + * blk_queue_flag_test_and_clear - atomically test and clear a queue flag + * @flag: flag to be cleared + * @q: request queue + * + * Returns the previous value of @flag - 0 if the flag was not set and 1 if + * the flag was set. + */ +bool blk_queue_flag_test_and_clear(unsigned int flag, struct request_queue *q) +{ + unsigned long flags; + bool res; + + spin_lock_irqsave(q->queue_lock, flags); + res = queue_flag_test_and_clear(flag, q); + spin_unlock_irqrestore(q->queue_lock, flags); + + return res; +} +EXPORT_SYMBOL_GPL(blk_queue_flag_test_and_clear); + static void blk_clear_congested(struct request_list *rl, int sync) { #ifdef CONFIG_CGROUP_WRITEBACK @@ -361,25 +433,14 @@ EXPORT_SYMBOL(blk_sync_queue); */ int blk_set_preempt_only(struct request_queue *q) { - unsigned long flags; - int res; - - spin_lock_irqsave(q->queue_lock, flags); - res = queue_flag_test_and_set(QUEUE_FLAG_PREEMPT_ONLY, q); - spin_unlock_irqrestore(q->queue_lock, flags); - - return res; + return blk_queue_flag_test_and_set(QUEUE_FLAG_PREEMPT_ONLY, q); } EXPORT_SYMBOL_GPL(blk_set_preempt_only); void blk_clear_preempt_only(struct request_queue *q) { - unsigned long flags; - - spin_lock_irqsave(q->queue_lock, flags); - queue_flag_clear(QUEUE_FLAG_PREEMPT_ONLY, q); + blk_queue_flag_clear(QUEUE_FLAG_PREEMPT_ONLY, q); wake_up_all(&q->mq_freeze_wq); - spin_unlock_irqrestore(q->queue_lock, flags); } EXPORT_SYMBOL_GPL(blk_clear_preempt_only); @@ -629,9 +690,7 @@ EXPORT_SYMBOL_GPL(blk_queue_bypass_end); void blk_set_queue_dying(struct request_queue *q) { - spin_lock_irq(q->queue_lock); - queue_flag_set(QUEUE_FLAG_DYING, q); - spin_unlock_irq(q->queue_lock); + blk_queue_flag_set(QUEUE_FLAG_DYING, q); /* * When queue DYING flag is set, we need to block new req diff --git a/block/blk-mq.c b/block/blk-mq.c index e70cc7d48f58..a86899022683 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -194,11 +194,7 @@ EXPORT_SYMBOL_GPL(blk_mq_unfreeze_queue); */ void blk_mq_quiesce_queue_nowait(struct request_queue *q) { - unsigned long flags; - - spin_lock_irqsave(q->queue_lock, flags); - queue_flag_set(QUEUE_FLAG_QUIESCED, q); - spin_unlock_irqrestore(q->queue_lock, flags); + blk_queue_flag_set(QUEUE_FLAG_QUIESCED, q); } EXPORT_SYMBOL_GPL(blk_mq_quiesce_queue_nowait); @@ -239,11 +235,7 @@ EXPORT_SYMBOL_GPL(blk_mq_quiesce_queue); */ void blk_mq_unquiesce_queue(struct request_queue *q) { - unsigned long flags; - - spin_lock_irqsave(q->queue_lock, flags); - queue_flag_clear(QUEUE_FLAG_QUIESCED, q); - spin_unlock_irqrestore(q->queue_lock, flags); + blk_queue_flag_clear(QUEUE_FLAG_QUIESCED, q); /* dispatch requests which are inserted during quiescing */ blk_mq_run_hw_queues(q, true); diff --git a/block/blk-settings.c b/block/blk-settings.c index 7f719da0eadd..d1de71124656 100644 --- a/block/blk-settings.c +++ b/block/blk-settings.c @@ -859,12 +859,10 @@ EXPORT_SYMBOL(blk_queue_update_dma_alignment); void blk_queue_flush_queueable(struct request_queue *q, bool queueable) { - spin_lock_irq(q->queue_lock); if (queueable) - queue_flag_clear(QUEUE_FLAG_FLUSH_NQ, q); + blk_queue_flag_clear(QUEUE_FLAG_FLUSH_NQ, q); else - queue_flag_set(QUEUE_FLAG_FLUSH_NQ, q); - spin_unlock_irq(q->queue_lock); + blk_queue_flag_set(QUEUE_FLAG_FLUSH_NQ, q); } EXPORT_SYMBOL_GPL(blk_queue_flush_queueable); diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c index fd71a00c9462..d00d1b0ec109 100644 --- a/block/blk-sysfs.c +++ b/block/blk-sysfs.c @@ -276,12 +276,10 @@ queue_store_##name(struct request_queue *q, const char *page, size_t count) \ if (neg) \ val = !val; \ \ - spin_lock_irq(q->queue_lock); \ if (val) \ - queue_flag_set(QUEUE_FLAG_##flag, q); \ + blk_queue_flag_set(QUEUE_FLAG_##flag, q); \ else \ - queue_flag_clear(QUEUE_FLAG_##flag, q); \ - spin_unlock_irq(q->queue_lock); \ + blk_queue_flag_clear(QUEUE_FLAG_##flag, q); \ return ret; \ } @@ -414,12 +412,10 @@ static ssize_t queue_poll_store(struct request_queue *q, const char *page, if (ret < 0) return ret; - spin_lock_irq(q->queue_lock); if (poll_on) - queue_flag_set(QUEUE_FLAG_POLL, q); + blk_queue_flag_set(QUEUE_FLAG_POLL, q); else - queue_flag_clear(QUEUE_FLAG_POLL, q); - spin_unlock_irq(q->queue_lock); + blk_queue_flag_clear(QUEUE_FLAG_POLL, q); return ret; } @@ -487,12 +483,10 @@ static ssize_t queue_wc_store(struct request_queue *q, const char *page, if (set == -1) return -EINVAL; - spin_lock_irq(q->queue_lock); if (set) - queue_flag_set(QUEUE_FLAG_WC, q); + blk_queue_flag_set(QUEUE_FLAG_WC, q); else - queue_flag_clear(QUEUE_FLAG_WC, q); - spin_unlock_irq(q->queue_lock); + blk_queue_flag_clear(QUEUE_FLAG_WC, q); return count; } @@ -946,9 +940,7 @@ void blk_unregister_queue(struct gendisk *disk) */ mutex_lock(&q->sysfs_lock); - spin_lock_irq(q->queue_lock); - queue_flag_clear(QUEUE_FLAG_REGISTERED, q); - spin_unlock_irq(q->queue_lock); + blk_queue_flag_clear(QUEUE_FLAG_REGISTERED, q); /* * Remove the sysfs attributes before unregistering the queue data diff --git a/block/blk-timeout.c b/block/blk-timeout.c index a05e3676d24a..34a55250f08a 100644 --- a/block/blk-timeout.c +++ b/block/blk-timeout.c @@ -57,12 +57,10 @@ ssize_t part_timeout_store(struct device *dev, struct device_attribute *attr, char *p = (char *) buf; val = simple_strtoul(p, &p, 10); - spin_lock_irq(q->queue_lock); if (val) - queue_flag_set(QUEUE_FLAG_FAIL_IO, q); + blk_queue_flag_set(QUEUE_FLAG_FAIL_IO, q); else - queue_flag_clear(QUEUE_FLAG_FAIL_IO, q); - spin_unlock_irq(q->queue_lock); + blk_queue_flag_clear(QUEUE_FLAG_FAIL_IO, q); } return count; diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index c351aaec3ca7..f84b3c7887b1 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -707,6 +707,11 @@ struct request_queue { (1 << QUEUE_FLAG_SAME_COMP) | \ (1 << QUEUE_FLAG_POLL)) +void blk_queue_flag_set(unsigned int flag, struct request_queue *q); +void blk_queue_flag_clear(unsigned int flag, struct request_queue *q); +bool blk_queue_flag_test_and_set(unsigned int flag, struct request_queue *q); +bool blk_queue_flag_test_and_clear(unsigned int flag, struct request_queue *q); + /* * @q->queue_lock is set while a queue is being initialized. Since we know * that no other threads access the queue object before @q->queue_lock has -- cgit v1.2.3 From 1db2008b79a32db2ad41338c6c74c4735cf74f6d Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Wed, 7 Mar 2018 17:10:11 -0800 Subject: block: Complain if queue_flag_(set|clear)_unlocked() is abused Since it is not safe to use queue_flag_(set|clear)_unlocked() without holding the queue lock after the sysfs entries for a queue have been created, complain if this happens. Cc: Mike Snitzer Cc: Christoph Hellwig Cc: Hannes Reinecke Cc: Ming Lei Reviewed-by: Johannes Thumshirn Reviewed-by: Martin K. Petersen Signed-off-by: Bart Van Assche Signed-off-by: Jens Axboe --- include/linux/blkdev.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux') diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index f84b3c7887b1..888c9b25cb8f 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -728,12 +728,18 @@ static inline void queue_lockdep_assert_held(struct request_queue *q) static inline void queue_flag_set_unlocked(unsigned int flag, struct request_queue *q) { + if (test_bit(QUEUE_FLAG_INIT_DONE, &q->queue_flags) && + kref_read(&q->kobj.kref)) + lockdep_assert_held(q->queue_lock); __set_bit(flag, &q->queue_flags); } static inline void queue_flag_clear_unlocked(unsigned int flag, struct request_queue *q) { + if (test_bit(QUEUE_FLAG_INIT_DONE, &q->queue_flags) && + kref_read(&q->kobj.kref)) + lockdep_assert_held(q->queue_lock); __clear_bit(flag, &q->queue_flags); } -- cgit v1.2.3 From 8a0ac14b8da9b86cfbe7aace40c8d485ed5c5b97 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Wed, 7 Mar 2018 17:10:12 -0800 Subject: block: Move the queue_flag_*() functions from a public into a private header file This patch helps to avoid that new code gets introduced in block drivers that manipulates queue flags without holding the queue lock when that lock should be held. Cc: Christoph Hellwig Cc: Hannes Reinecke Cc: Ming Lei Reviewed-by: Johannes Thumshirn Reviewed-by: Martin K. Petersen Signed-off-by: Bart Van Assche Signed-off-by: Jens Axboe --- block/blk.h | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/blkdev.h | 69 -------------------------------------------------- 2 files changed, 69 insertions(+), 69 deletions(-) (limited to 'include/linux') diff --git a/block/blk.h b/block/blk.h index 46db5dc83dcb..b034fd2460c4 100644 --- a/block/blk.h +++ b/block/blk.h @@ -41,6 +41,75 @@ extern struct kmem_cache *request_cachep; extern struct kobj_type blk_queue_ktype; extern struct ida blk_queue_ida; +/* + * @q->queue_lock is set while a queue is being initialized. Since we know + * that no other threads access the queue object before @q->queue_lock has + * been set, it is safe to manipulate queue flags without holding the + * queue_lock if @q->queue_lock == NULL. See also blk_alloc_queue_node() and + * blk_init_allocated_queue(). + */ +static inline void queue_lockdep_assert_held(struct request_queue *q) +{ + if (q->queue_lock) + lockdep_assert_held(q->queue_lock); +} + +static inline void queue_flag_set_unlocked(unsigned int flag, + struct request_queue *q) +{ + if (test_bit(QUEUE_FLAG_INIT_DONE, &q->queue_flags) && + kref_read(&q->kobj.kref)) + lockdep_assert_held(q->queue_lock); + __set_bit(flag, &q->queue_flags); +} + +static inline void queue_flag_clear_unlocked(unsigned int flag, + struct request_queue *q) +{ + if (test_bit(QUEUE_FLAG_INIT_DONE, &q->queue_flags) && + kref_read(&q->kobj.kref)) + lockdep_assert_held(q->queue_lock); + __clear_bit(flag, &q->queue_flags); +} + +static inline int queue_flag_test_and_clear(unsigned int flag, + struct request_queue *q) +{ + queue_lockdep_assert_held(q); + + if (test_bit(flag, &q->queue_flags)) { + __clear_bit(flag, &q->queue_flags); + return 1; + } + + return 0; +} + +static inline int queue_flag_test_and_set(unsigned int flag, + struct request_queue *q) +{ + queue_lockdep_assert_held(q); + + if (!test_bit(flag, &q->queue_flags)) { + __set_bit(flag, &q->queue_flags); + return 0; + } + + return 1; +} + +static inline void queue_flag_set(unsigned int flag, struct request_queue *q) +{ + queue_lockdep_assert_held(q); + __set_bit(flag, &q->queue_flags); +} + +static inline void queue_flag_clear(unsigned int flag, struct request_queue *q) +{ + queue_lockdep_assert_held(q); + __clear_bit(flag, &q->queue_flags); +} + static inline struct blk_flush_queue *blk_get_flush_queue( struct request_queue *q, struct blk_mq_ctx *ctx) { diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 888c9b25cb8f..19eaf8d89368 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -712,75 +712,6 @@ void blk_queue_flag_clear(unsigned int flag, struct request_queue *q); bool blk_queue_flag_test_and_set(unsigned int flag, struct request_queue *q); bool blk_queue_flag_test_and_clear(unsigned int flag, struct request_queue *q); -/* - * @q->queue_lock is set while a queue is being initialized. Since we know - * that no other threads access the queue object before @q->queue_lock has - * been set, it is safe to manipulate queue flags without holding the - * queue_lock if @q->queue_lock == NULL. See also blk_alloc_queue_node() and - * blk_init_allocated_queue(). - */ -static inline void queue_lockdep_assert_held(struct request_queue *q) -{ - if (q->queue_lock) - lockdep_assert_held(q->queue_lock); -} - -static inline void queue_flag_set_unlocked(unsigned int flag, - struct request_queue *q) -{ - if (test_bit(QUEUE_FLAG_INIT_DONE, &q->queue_flags) && - kref_read(&q->kobj.kref)) - lockdep_assert_held(q->queue_lock); - __set_bit(flag, &q->queue_flags); -} - -static inline void queue_flag_clear_unlocked(unsigned int flag, - struct request_queue *q) -{ - if (test_bit(QUEUE_FLAG_INIT_DONE, &q->queue_flags) && - kref_read(&q->kobj.kref)) - lockdep_assert_held(q->queue_lock); - __clear_bit(flag, &q->queue_flags); -} - -static inline int queue_flag_test_and_clear(unsigned int flag, - struct request_queue *q) -{ - queue_lockdep_assert_held(q); - - if (test_bit(flag, &q->queue_flags)) { - __clear_bit(flag, &q->queue_flags); - return 1; - } - - return 0; -} - -static inline int queue_flag_test_and_set(unsigned int flag, - struct request_queue *q) -{ - queue_lockdep_assert_held(q); - - if (!test_bit(flag, &q->queue_flags)) { - __set_bit(flag, &q->queue_flags); - return 0; - } - - return 1; -} - -static inline void queue_flag_set(unsigned int flag, struct request_queue *q) -{ - queue_lockdep_assert_held(q); - __set_bit(flag, &q->queue_flags); -} - -static inline void queue_flag_clear(unsigned int flag, struct request_queue *q) -{ - queue_lockdep_assert_held(q); - __clear_bit(flag, &q->queue_flags); -} - #define blk_queue_tagged(q) test_bit(QUEUE_FLAG_QUEUED, &(q)->queue_flags) #define blk_queue_stopped(q) test_bit(QUEUE_FLAG_STOPPED, &(q)->queue_flags) #define blk_queue_dying(q) test_bit(QUEUE_FLAG_DYING, &(q)->queue_flags) -- cgit v1.2.3 From 84a1d9c4820080bebcbd413a845076dcb62f45fa Mon Sep 17 00:00:00 2001 From: Edward Cree Date: Thu, 8 Mar 2018 15:45:03 +0000 Subject: net: ethtool: extend RXNFC API to support RSS spreading of filter matches We use a two-step process to configure a filter with RSS spreading. First, the RSS context is allocated and configured using ETHTOOL_SRSSH; this returns an identifier (rss_context) which can then be passed to subsequent invocations of ETHTOOL_SRXCLSRLINS to specify that the offset from the RSS indirection table lookup should be added to the queue number (ring_cookie) when delivering the packet. Drivers for devices which can only use the indirection table entry directly (not add it to a base queue number) should reject rule insertions combining RSS with a nonzero ring_cookie. Signed-off-by: Edward Cree Signed-off-by: David S. Miller --- include/linux/ethtool.h | 5 ++++ include/uapi/linux/ethtool.h | 32 +++++++++++++++++----- net/core/ethtool.c | 64 +++++++++++++++++++++++++++++++++----------- 3 files changed, 80 insertions(+), 21 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index 2ec41a7eb54f..ebe41811ed34 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -371,6 +371,11 @@ struct ethtool_ops { u8 *hfunc); int (*set_rxfh)(struct net_device *, const u32 *indir, const u8 *key, const u8 hfunc); + int (*get_rxfh_context)(struct net_device *, u32 *indir, u8 *key, + u8 *hfunc, u32 rss_context); + int (*set_rxfh_context)(struct net_device *, const u32 *indir, + const u8 *key, const u8 hfunc, + u32 *rss_context, bool delete); void (*get_channels)(struct net_device *, struct ethtool_channels *); int (*set_channels)(struct net_device *, struct ethtool_channels *); int (*get_dump_flag)(struct net_device *, struct ethtool_dump *); diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h index 44a0b675a6bc..20da156aaf64 100644 --- a/include/uapi/linux/ethtool.h +++ b/include/uapi/linux/ethtool.h @@ -914,12 +914,15 @@ static inline __u64 ethtool_get_flow_spec_ring_vf(__u64 ring_cookie) * @flow_type: Type of flow to be affected, e.g. %TCP_V4_FLOW * @data: Command-dependent value * @fs: Flow classification rule + * @rss_context: RSS context to be affected * @rule_cnt: Number of rules to be affected * @rule_locs: Array of used rule locations * * For %ETHTOOL_GRXFH and %ETHTOOL_SRXFH, @data is a bitmask indicating * the fields included in the flow hash, e.g. %RXH_IP_SRC. The following - * structure fields must not be used. + * structure fields must not be used, except that if @flow_type includes + * the %FLOW_RSS flag, then @rss_context determines which RSS context to + * act on. * * For %ETHTOOL_GRXRINGS, @data is set to the number of RX rings/queues * on return. @@ -931,7 +934,9 @@ static inline __u64 ethtool_get_flow_spec_ring_vf(__u64 ring_cookie) * set in @data then special location values should not be used. * * For %ETHTOOL_GRXCLSRULE, @fs.@location specifies the location of an - * existing rule on entry and @fs contains the rule on return. + * existing rule on entry and @fs contains the rule on return; if + * @fs.@flow_type includes the %FLOW_RSS flag, then @rss_context is + * filled with the RSS context ID associated with the rule. * * For %ETHTOOL_GRXCLSRLALL, @rule_cnt specifies the array size of the * user buffer for @rule_locs on entry. On return, @data is the size @@ -942,7 +947,11 @@ static inline __u64 ethtool_get_flow_spec_ring_vf(__u64 ring_cookie) * For %ETHTOOL_SRXCLSRLINS, @fs specifies the rule to add or update. * @fs.@location either specifies the location to use or is a special * location value with %RX_CLS_LOC_SPECIAL flag set. On return, - * @fs.@location is the actual rule location. + * @fs.@location is the actual rule location. If @fs.@flow_type + * includes the %FLOW_RSS flag, @rss_context is the RSS context ID to + * use for flow spreading traffic which matches this rule. The value + * from the rxfh indirection table will be added to @fs.@ring_cookie + * to choose which ring to deliver to. * * For %ETHTOOL_SRXCLSRLDEL, @fs.@location specifies the location of an * existing rule on entry. @@ -963,7 +972,10 @@ struct ethtool_rxnfc { __u32 flow_type; __u64 data; struct ethtool_rx_flow_spec fs; - __u32 rule_cnt; + union { + __u32 rule_cnt; + __u32 rss_context; + }; __u32 rule_locs[0]; }; @@ -990,7 +1002,11 @@ struct ethtool_rxfh_indir { /** * struct ethtool_rxfh - command to get/set RX flow hash indir or/and hash key. * @cmd: Specific command number - %ETHTOOL_GRSSH or %ETHTOOL_SRSSH - * @rss_context: RSS context identifier. + * @rss_context: RSS context identifier. Context 0 is the default for normal + * traffic; other contexts can be referenced as the destination for RX flow + * classification rules. %ETH_RXFH_CONTEXT_ALLOC is used with command + * %ETHTOOL_SRSSH to allocate a new RSS context; on return this field will + * contain the ID of the newly allocated context. * @indir_size: On entry, the array size of the user buffer for the * indirection table, which may be zero, or (for %ETHTOOL_SRSSH), * %ETH_RXFH_INDIR_NO_CHANGE. On return from %ETHTOOL_GRSSH, @@ -1009,7 +1025,8 @@ struct ethtool_rxfh_indir { * size should be returned. For %ETHTOOL_SRSSH, an @indir_size of * %ETH_RXFH_INDIR_NO_CHANGE means that indir table setting is not requested * and a @indir_size of zero means the indir table should be reset to default - * values. An hfunc of zero means that hash function setting is not requested. + * values (if @rss_context == 0) or that the RSS context should be deleted. + * An hfunc of zero means that hash function setting is not requested. */ struct ethtool_rxfh { __u32 cmd; @@ -1021,6 +1038,7 @@ struct ethtool_rxfh { __u32 rsvd32; __u32 rss_config[0]; }; +#define ETH_RXFH_CONTEXT_ALLOC 0xffffffff #define ETH_RXFH_INDIR_NO_CHANGE 0xffffffff /** @@ -1635,6 +1653,8 @@ static inline int ethtool_validate_duplex(__u8 duplex) /* Flag to enable additional fields in struct ethtool_rx_flow_spec */ #define FLOW_EXT 0x80000000 #define FLOW_MAC_EXT 0x40000000 +/* Flag to enable RSS spreading of traffic matching rule (nfc only) */ +#define FLOW_RSS 0x20000000 /* L3-L4 network traffic flow hash options */ #define RXH_L2DA (1 << 1) diff --git a/net/core/ethtool.c b/net/core/ethtool.c index 3f89c76d5c24..157cd9efa4be 100644 --- a/net/core/ethtool.c +++ b/net/core/ethtool.c @@ -1022,6 +1022,15 @@ static noinline_for_stack int ethtool_get_rxnfc(struct net_device *dev, if (copy_from_user(&info, useraddr, info_size)) return -EFAULT; + /* If FLOW_RSS was requested then user-space must be using the + * new definition, as FLOW_RSS is newer. + */ + if (cmd == ETHTOOL_GRXFH && info.flow_type & FLOW_RSS) { + info_size = sizeof(info); + if (copy_from_user(&info, useraddr, info_size)) + return -EFAULT; + } + if (info.cmd == ETHTOOL_GRXCLSRLALL) { if (info.rule_cnt > 0) { if (info.rule_cnt <= KMALLOC_MAX_SIZE / sizeof(u32)) @@ -1251,9 +1260,11 @@ static noinline_for_stack int ethtool_get_rxfh(struct net_device *dev, user_key_size = rxfh.key_size; /* Check that reserved fields are 0 for now */ - if (rxfh.rss_context || rxfh.rsvd8[0] || rxfh.rsvd8[1] || - rxfh.rsvd8[2] || rxfh.rsvd32) + if (rxfh.rsvd8[0] || rxfh.rsvd8[1] || rxfh.rsvd8[2] || rxfh.rsvd32) return -EINVAL; + /* Most drivers don't handle rss_context, check it's 0 as well */ + if (rxfh.rss_context && !ops->get_rxfh_context) + return -EOPNOTSUPP; rxfh.indir_size = dev_indir_size; rxfh.key_size = dev_key_size; @@ -1276,7 +1287,12 @@ static noinline_for_stack int ethtool_get_rxfh(struct net_device *dev, if (user_key_size) hkey = rss_config + indir_bytes; - ret = dev->ethtool_ops->get_rxfh(dev, indir, hkey, &dev_hfunc); + if (rxfh.rss_context) + ret = dev->ethtool_ops->get_rxfh_context(dev, indir, hkey, + &dev_hfunc, + rxfh.rss_context); + else + ret = dev->ethtool_ops->get_rxfh(dev, indir, hkey, &dev_hfunc); if (ret) goto out; @@ -1306,6 +1322,7 @@ static noinline_for_stack int ethtool_set_rxfh(struct net_device *dev, u8 *hkey = NULL; u8 *rss_config; u32 rss_cfg_offset = offsetof(struct ethtool_rxfh, rss_config[0]); + bool delete = false; if (!ops->get_rxnfc || !ops->set_rxfh) return -EOPNOTSUPP; @@ -1319,9 +1336,11 @@ static noinline_for_stack int ethtool_set_rxfh(struct net_device *dev, return -EFAULT; /* Check that reserved fields are 0 for now */ - if (rxfh.rss_context || rxfh.rsvd8[0] || rxfh.rsvd8[1] || - rxfh.rsvd8[2] || rxfh.rsvd32) + if (rxfh.rsvd8[0] || rxfh.rsvd8[1] || rxfh.rsvd8[2] || rxfh.rsvd32) return -EINVAL; + /* Most drivers don't handle rss_context, check it's 0 as well */ + if (rxfh.rss_context && !ops->set_rxfh_context) + return -EOPNOTSUPP; /* If either indir, hash key or function is valid, proceed further. * Must request at least one change: indir size, hash key or function. @@ -1346,7 +1365,8 @@ static noinline_for_stack int ethtool_set_rxfh(struct net_device *dev, if (ret) goto out; - /* rxfh.indir_size == 0 means reset the indir table to default. + /* rxfh.indir_size == 0 means reset the indir table to default (master + * context) or delete the context (other RSS contexts). * rxfh.indir_size == ETH_RXFH_INDIR_NO_CHANGE means leave it unchanged. */ if (rxfh.indir_size && @@ -1359,9 +1379,13 @@ static noinline_for_stack int ethtool_set_rxfh(struct net_device *dev, if (ret) goto out; } else if (rxfh.indir_size == 0) { - indir = (u32 *)rss_config; - for (i = 0; i < dev_indir_size; i++) - indir[i] = ethtool_rxfh_indir_default(i, rx_rings.data); + if (rxfh.rss_context == 0) { + indir = (u32 *)rss_config; + for (i = 0; i < dev_indir_size; i++) + indir[i] = ethtool_rxfh_indir_default(i, rx_rings.data); + } else { + delete = true; + } } if (rxfh.key_size) { @@ -1374,15 +1398,25 @@ static noinline_for_stack int ethtool_set_rxfh(struct net_device *dev, } } - ret = ops->set_rxfh(dev, indir, hkey, rxfh.hfunc); + if (rxfh.rss_context) + ret = ops->set_rxfh_context(dev, indir, hkey, rxfh.hfunc, + &rxfh.rss_context, delete); + else + ret = ops->set_rxfh(dev, indir, hkey, rxfh.hfunc); if (ret) goto out; - /* indicate whether rxfh was set to default */ - if (rxfh.indir_size == 0) - dev->priv_flags &= ~IFF_RXFH_CONFIGURED; - else if (rxfh.indir_size != ETH_RXFH_INDIR_NO_CHANGE) - dev->priv_flags |= IFF_RXFH_CONFIGURED; + if (copy_to_user(useraddr + offsetof(struct ethtool_rxfh, rss_context), + &rxfh.rss_context, sizeof(rxfh.rss_context))) + ret = -EFAULT; + + if (!rxfh.rss_context) { + /* indicate whether rxfh was set to default */ + if (rxfh.indir_size == 0) + dev->priv_flags &= ~IFF_RXFH_CONFIGURED; + else if (rxfh.indir_size != ETH_RXFH_INDIR_NO_CHANGE) + dev->priv_flags |= IFF_RXFH_CONFIGURED; + } out: kfree(rss_config); -- cgit v1.2.3 From 4042d003a0792a3b05c7c424219e4c6cf1abfe76 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 20 Dec 2017 15:37:26 +0100 Subject: cpufreq/schedutil: Remove unused CPUFREQ_DL Bitrot... Signed-off-by: Peter Zijlstra (Intel) Cc: Juri Lelli Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Thomas Gleixner Cc: Viresh Kumar Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/sched/cpufreq.h | 3 +-- kernel/sched/deadline.c | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched/cpufreq.h b/include/linux/sched/cpufreq.h index 0b55834efd46..d963cfd3a0c2 100644 --- a/include/linux/sched/cpufreq.h +++ b/include/linux/sched/cpufreq.h @@ -9,8 +9,7 @@ */ #define SCHED_CPUFREQ_RT (1U << 0) -#define SCHED_CPUFREQ_DL (1U << 1) -#define SCHED_CPUFREQ_IOWAIT (1U << 2) +#define SCHED_CPUFREQ_IOWAIT (1U << 1) #ifdef CONFIG_CPU_FREQ struct update_util_data { diff --git a/kernel/sched/deadline.c b/kernel/sched/deadline.c index 8b7c2b35bec9..d1c7bf7c7e5b 100644 --- a/kernel/sched/deadline.c +++ b/kernel/sched/deadline.c @@ -84,7 +84,7 @@ void __add_running_bw(u64 dl_bw, struct dl_rq *dl_rq) SCHED_WARN_ON(dl_rq->running_bw < old); /* overflow */ SCHED_WARN_ON(dl_rq->running_bw > dl_rq->this_bw); /* kick cpufreq (see the comment in kernel/sched/sched.h). */ - cpufreq_update_util(rq_of_dl_rq(dl_rq), SCHED_CPUFREQ_DL); + cpufreq_update_util(rq_of_dl_rq(dl_rq), 0); } static inline @@ -98,7 +98,7 @@ void __sub_running_bw(u64 dl_bw, struct dl_rq *dl_rq) if (dl_rq->running_bw > old) dl_rq->running_bw = 0; /* kick cpufreq (see the comment in kernel/sched/sched.h). */ - cpufreq_update_util(rq_of_dl_rq(dl_rq), SCHED_CPUFREQ_DL); + cpufreq_update_util(rq_of_dl_rq(dl_rq), 0); } static inline -- cgit v1.2.3 From 8f111bc357aa811e0bb5fdfe34c4c9efdafc15b9 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 20 Dec 2017 16:26:12 +0100 Subject: cpufreq/schedutil: Rewrite CPUFREQ_RT support Instead of trying to duplicate scheduler state to track if an RT task is running, directly use the scheduler runqueue state for it. This vastly simplifies things and fixes a number of bugs related to sugov and the scheduler getting out of sync wrt this state. As a consequence we not also update the remove cfs/dl state when iterating the shared mask. Signed-off-by: Peter Zijlstra (Intel) Cc: Juri Lelli Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Thomas Gleixner Cc: Viresh Kumar Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/sched/cpufreq.h | 3 +- kernel/sched/cpufreq_schedutil.c | 74 ++++++++++++++++++---------------------- kernel/sched/rt.c | 9 +++-- 3 files changed, 41 insertions(+), 45 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched/cpufreq.h b/include/linux/sched/cpufreq.h index d963cfd3a0c2..b48f2fb3b316 100644 --- a/include/linux/sched/cpufreq.h +++ b/include/linux/sched/cpufreq.h @@ -8,8 +8,7 @@ * Interface between cpufreq drivers and the scheduler: */ -#define SCHED_CPUFREQ_RT (1U << 0) -#define SCHED_CPUFREQ_IOWAIT (1U << 1) +#define SCHED_CPUFREQ_IOWAIT (1U << 0) #ifdef CONFIG_CPU_FREQ struct update_util_data { diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c index feb5f89020f2..89fe78ecb88c 100644 --- a/kernel/sched/cpufreq_schedutil.c +++ b/kernel/sched/cpufreq_schedutil.c @@ -57,7 +57,6 @@ struct sugov_cpu { unsigned long util_cfs; unsigned long util_dl; unsigned long max; - unsigned int flags; /* The field below is for single-CPU policies only: */ #ifdef CONFIG_NO_HZ_COMMON @@ -183,17 +182,28 @@ static void sugov_get_util(struct sugov_cpu *sg_cpu) static unsigned long sugov_aggregate_util(struct sugov_cpu *sg_cpu) { + struct rq *rq = cpu_rq(sg_cpu->cpu); + unsigned long util; + + if (rq->rt.rt_nr_running) { + util = sg_cpu->max; + } else { + util = sg_cpu->util_dl; + if (rq->cfs.h_nr_running) + util += sg_cpu->util_cfs; + } + /* * Ideally we would like to set util_dl as min/guaranteed freq and * util_cfs + util_dl as requested freq. However, cpufreq is not yet * ready for such an interface. So, we only do the latter for now. */ - return min(sg_cpu->util_cfs + sg_cpu->util_dl, sg_cpu->max); + return min(util, sg_cpu->max); } -static void sugov_set_iowait_boost(struct sugov_cpu *sg_cpu, u64 time) +static void sugov_set_iowait_boost(struct sugov_cpu *sg_cpu, u64 time, unsigned int flags) { - if (sg_cpu->flags & SCHED_CPUFREQ_IOWAIT) { + if (flags & SCHED_CPUFREQ_IOWAIT) { if (sg_cpu->iowait_boost_pending) return; @@ -262,12 +272,11 @@ static void sugov_update_single(struct update_util_data *hook, u64 time, { struct sugov_cpu *sg_cpu = container_of(hook, struct sugov_cpu, update_util); struct sugov_policy *sg_policy = sg_cpu->sg_policy; - struct cpufreq_policy *policy = sg_policy->policy; unsigned long util, max; unsigned int next_f; bool busy; - sugov_set_iowait_boost(sg_cpu, time); + sugov_set_iowait_boost(sg_cpu, time, flags); sg_cpu->last_update = time; if (!sugov_should_update_freq(sg_policy, time)) @@ -275,25 +284,22 @@ static void sugov_update_single(struct update_util_data *hook, u64 time, busy = sugov_cpu_is_busy(sg_cpu); - if (flags & SCHED_CPUFREQ_RT) { - next_f = policy->cpuinfo.max_freq; - } else { - sugov_get_util(sg_cpu); - max = sg_cpu->max; - util = sugov_aggregate_util(sg_cpu); - sugov_iowait_boost(sg_cpu, &util, &max); - next_f = get_next_freq(sg_policy, util, max); - /* - * Do not reduce the frequency if the CPU has not been idle - * recently, as the reduction is likely to be premature then. - */ - if (busy && next_f < sg_policy->next_freq) { - next_f = sg_policy->next_freq; + sugov_get_util(sg_cpu); + max = sg_cpu->max; + util = sugov_aggregate_util(sg_cpu); + sugov_iowait_boost(sg_cpu, &util, &max); + next_f = get_next_freq(sg_policy, util, max); + /* + * Do not reduce the frequency if the CPU has not been idle + * recently, as the reduction is likely to be premature then. + */ + if (busy && next_f < sg_policy->next_freq) { + next_f = sg_policy->next_freq; - /* Reset cached freq as next_freq has changed */ - sg_policy->cached_raw_freq = 0; - } + /* Reset cached freq as next_freq has changed */ + sg_policy->cached_raw_freq = 0; } + sugov_update_commit(sg_policy, time, next_f); } @@ -309,6 +315,8 @@ static unsigned int sugov_next_freq_shared(struct sugov_cpu *sg_cpu, u64 time) unsigned long j_util, j_max; s64 delta_ns; + sugov_get_util(j_sg_cpu); + /* * If the CFS CPU utilization was last updated before the * previous frequency update and the time elapsed between the @@ -322,21 +330,15 @@ static unsigned int sugov_next_freq_shared(struct sugov_cpu *sg_cpu, u64 time) if (delta_ns > TICK_NSEC) { j_sg_cpu->iowait_boost = 0; j_sg_cpu->iowait_boost_pending = false; - j_sg_cpu->util_cfs = 0; - if (j_sg_cpu->util_dl == 0) - continue; } - if (j_sg_cpu->flags & SCHED_CPUFREQ_RT) - return policy->cpuinfo.max_freq; j_max = j_sg_cpu->max; j_util = sugov_aggregate_util(j_sg_cpu); + sugov_iowait_boost(j_sg_cpu, &j_util, &j_max); if (j_util * max > j_max * util) { util = j_util; max = j_max; } - - sugov_iowait_boost(j_sg_cpu, &util, &max); } return get_next_freq(sg_policy, util, max); @@ -351,18 +353,11 @@ sugov_update_shared(struct update_util_data *hook, u64 time, unsigned int flags) raw_spin_lock(&sg_policy->update_lock); - sugov_get_util(sg_cpu); - sg_cpu->flags = flags; - - sugov_set_iowait_boost(sg_cpu, time); + sugov_set_iowait_boost(sg_cpu, time, flags); sg_cpu->last_update = time; if (sugov_should_update_freq(sg_policy, time)) { - if (flags & SCHED_CPUFREQ_RT) - next_f = sg_policy->policy->cpuinfo.max_freq; - else - next_f = sugov_next_freq_shared(sg_cpu, time); - + next_f = sugov_next_freq_shared(sg_cpu, time); sugov_update_commit(sg_policy, time, next_f); } @@ -673,7 +668,6 @@ static int sugov_start(struct cpufreq_policy *policy) memset(sg_cpu, 0, sizeof(*sg_cpu)); sg_cpu->cpu = cpu; sg_cpu->sg_policy = sg_policy; - sg_cpu->flags = 0; sg_cpu->iowait_boost_max = policy->cpuinfo.max_freq; } diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c index 4f4fd3b157f1..86b77987435e 100644 --- a/kernel/sched/rt.c +++ b/kernel/sched/rt.c @@ -957,9 +957,6 @@ static void update_curr_rt(struct rq *rq) if (unlikely((s64)delta_exec <= 0)) return; - /* Kick cpufreq (see the comment in kernel/sched/sched.h). */ - cpufreq_update_util(rq, SCHED_CPUFREQ_RT); - schedstat_set(curr->se.statistics.exec_max, max(curr->se.statistics.exec_max, delta_exec)); @@ -1001,6 +998,9 @@ dequeue_top_rt_rq(struct rt_rq *rt_rq) sub_nr_running(rq, rt_rq->rt_nr_running); rt_rq->rt_queued = 0; + + /* Kick cpufreq (see the comment in kernel/sched/sched.h). */ + cpufreq_update_util(rq, 0); } static void @@ -1017,6 +1017,9 @@ enqueue_top_rt_rq(struct rt_rq *rt_rq) add_nr_running(rq, rt_rq->rt_nr_running); rt_rq->rt_queued = 1; + + /* Kick cpufreq (see the comment in kernel/sched/sched.h). */ + cpufreq_update_util(rq, 0); } #if defined CONFIG_SMP -- cgit v1.2.3 From 00357f5ec5d67a52a175da6f29f85c2c19d59bc8 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 21 Dec 2017 15:06:50 +0100 Subject: sched/nohz: Clean up nohz enter/exit The primary observation is that nohz enter/exit is always from the current CPU, therefore NOHZ_TICK_STOPPED does not in fact need to be an atomic. Secondary is that we appear to have 2 nearly identical hooks in the nohz enter code, set_cpu_sd_state_idle() and nohz_balance_enter_idle(). Fold the whole set_cpu_sd_state thing into nohz_balance_{enter,exit}_idle. Removes an atomic op from both enter and exit paths. Signed-off-by: Peter Zijlstra (Intel) Cc: Frederic Weisbecker Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/sched/nohz.h | 2 -- kernel/sched/core.c | 2 +- kernel/sched/fair.c | 73 +++++++++++++++++++++++----------------------- kernel/sched/sched.h | 11 ++++--- kernel/time/tick-sched.c | 7 ----- 5 files changed, 43 insertions(+), 52 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched/nohz.h b/include/linux/sched/nohz.h index 094217273ff9..b36f4cf38111 100644 --- a/include/linux/sched/nohz.h +++ b/include/linux/sched/nohz.h @@ -16,11 +16,9 @@ static inline void cpu_load_update_nohz_stop(void) { } #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ_COMMON) extern void nohz_balance_enter_idle(int cpu); -extern void set_cpu_sd_state_idle(void); extern int get_nohz_timer_target(void); #else static inline void nohz_balance_enter_idle(int cpu) { } -static inline void set_cpu_sd_state_idle(void) { } #endif #ifdef CONFIG_NO_HZ_COMMON diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 8a10a2ce30a4..c7faeb7bd03a 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5861,7 +5861,7 @@ int sched_cpu_dying(unsigned int cpu) calc_load_migrate(rq); update_max_interval(); - nohz_balance_exit_idle(cpu); + nohz_balance_exit_idle(rq); hrtick_clear(rq); return 0; } diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 85232dad89c9..494d5db9a6cd 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -9103,23 +9103,6 @@ static inline int find_new_ilb(void) return nr_cpu_ids; } -static inline void set_cpu_sd_state_busy(void) -{ - struct sched_domain *sd; - int cpu = smp_processor_id(); - - rcu_read_lock(); - sd = rcu_dereference(per_cpu(sd_llc, cpu)); - - if (!sd || !sd->nohz_idle) - goto unlock; - sd->nohz_idle = 0; - - atomic_inc(&sd->shared->nr_busy_cpus); -unlock: - rcu_read_unlock(); -} - /* * Kick a CPU to do the nohz balancing, if it is time for it. We pick the * nohz_load_balancer CPU (if there is one) otherwise fallback to any idle @@ -9175,8 +9158,7 @@ static void nohz_balancer_kick(struct rq *rq) * We may be recently in ticked or tickless idle mode. At the first * busy tick after returning from idle, we will update the busy stats. */ - set_cpu_sd_state_busy(); - nohz_balance_exit_idle(cpu); + nohz_balance_exit_idle(rq); /* * None are in tickless mode and hence no need for NOHZ idle load @@ -9240,27 +9222,39 @@ out: kick_ilb(flags); } -void nohz_balance_exit_idle(unsigned int cpu) +static void set_cpu_sd_state_busy(int cpu) { - unsigned int flags = atomic_read(nohz_flags(cpu)); + struct sched_domain *sd; - if (unlikely(flags & NOHZ_TICK_STOPPED)) { - /* - * Completely isolated CPUs don't ever set, so we must test. - */ - if (likely(cpumask_test_cpu(cpu, nohz.idle_cpus_mask))) { - cpumask_clear_cpu(cpu, nohz.idle_cpus_mask); - atomic_dec(&nohz.nr_cpus); - } + rcu_read_lock(); + sd = rcu_dereference(per_cpu(sd_llc, cpu)); - atomic_andnot(NOHZ_TICK_STOPPED, nohz_flags(cpu)); - } + if (!sd || !sd->nohz_idle) + goto unlock; + sd->nohz_idle = 0; + + atomic_inc(&sd->shared->nr_busy_cpus); +unlock: + rcu_read_unlock(); } -void set_cpu_sd_state_idle(void) +void nohz_balance_exit_idle(struct rq *rq) +{ + SCHED_WARN_ON(rq != this_rq()); + + if (likely(!rq->nohz_tick_stopped)) + return; + + rq->nohz_tick_stopped = 0; + cpumask_clear_cpu(rq->cpu, nohz.idle_cpus_mask); + atomic_dec(&nohz.nr_cpus); + + set_cpu_sd_state_busy(rq->cpu); +} + +static void set_cpu_sd_state_idle(int cpu) { struct sched_domain *sd; - int cpu = smp_processor_id(); rcu_read_lock(); sd = rcu_dereference(per_cpu(sd_llc, cpu)); @@ -9280,6 +9274,10 @@ unlock: */ void nohz_balance_enter_idle(int cpu) { + struct rq *rq = cpu_rq(cpu); + + SCHED_WARN_ON(cpu != smp_processor_id()); + /* If this CPU is going down, then nothing needs to be done: */ if (!cpu_active(cpu)) return; @@ -9288,16 +9286,19 @@ void nohz_balance_enter_idle(int cpu) if (!housekeeping_cpu(cpu, HK_FLAG_SCHED)) return; - if (atomic_read(nohz_flags(cpu)) & NOHZ_TICK_STOPPED) + if (rq->nohz_tick_stopped) return; /* If we're a completely isolated CPU, we don't play: */ - if (on_null_domain(cpu_rq(cpu))) + if (on_null_domain(rq)) return; + rq->nohz_tick_stopped = 1; + cpumask_set_cpu(cpu, nohz.idle_cpus_mask); atomic_inc(&nohz.nr_cpus); - atomic_or(NOHZ_TICK_STOPPED, nohz_flags(cpu)); + + set_cpu_sd_state_idle(cpu); } #else static inline void nohz_balancer_kick(struct rq *rq) { } diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 21381d276709..818f22dbc7ea 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -764,6 +764,7 @@ struct rq { unsigned long last_load_update_tick; unsigned long last_blocked_load_update_tick; #endif /* CONFIG_SMP */ + unsigned int nohz_tick_stopped; atomic_t nohz_flags; #endif /* CONFIG_NO_HZ_COMMON */ @@ -2035,11 +2036,9 @@ extern void cfs_bandwidth_usage_inc(void); extern void cfs_bandwidth_usage_dec(void); #ifdef CONFIG_NO_HZ_COMMON -#define NOHZ_TICK_STOPPED_BIT 0 -#define NOHZ_BALANCE_KICK_BIT 1 -#define NOHZ_STATS_KICK_BIT 2 +#define NOHZ_BALANCE_KICK_BIT 0 +#define NOHZ_STATS_KICK_BIT 1 -#define NOHZ_TICK_STOPPED BIT(NOHZ_TICK_STOPPED_BIT) #define NOHZ_BALANCE_KICK BIT(NOHZ_BALANCE_KICK_BIT) #define NOHZ_STATS_KICK BIT(NOHZ_STATS_KICK_BIT) @@ -2047,9 +2046,9 @@ extern void cfs_bandwidth_usage_dec(void); #define nohz_flags(cpu) (&cpu_rq(cpu)->nohz_flags) -extern void nohz_balance_exit_idle(unsigned int cpu); +extern void nohz_balance_exit_idle(struct rq *rq); #else -static inline void nohz_balance_exit_idle(unsigned int cpu) { } +static inline void nohz_balance_exit_idle(struct rq *rq) { } #endif diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index f2fa2e940fe5..ab92aa4442df 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -954,13 +954,6 @@ void tick_nohz_idle_enter(void) struct tick_sched *ts; lockdep_assert_irqs_enabled(); - /* - * Update the idle state in the scheduler domain hierarchy - * when tick_nohz_stop_sched_tick() is called from the idle loop. - * State will be updated to busy during the first busy tick after - * exiting idle. - */ - set_cpu_sd_state_idle(); local_irq_disable(); -- cgit v1.2.3 From ea14b57e8a181ac0561eba7a787e088f8c89f822 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 2 Feb 2018 10:27:00 +0100 Subject: sched/cpufreq: Provide migration hint It was suggested that a migration hint might be usefull for the CPU-freq governors. Signed-off-by: Peter Zijlstra (Intel) Cc: Juri Lelli Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Thomas Gleixner Cc: Viresh Kumar Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/sched/cpufreq.h | 1 + kernel/sched/fair.c | 31 +++++++++++++++++++------------ 2 files changed, 20 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched/cpufreq.h b/include/linux/sched/cpufreq.h index b48f2fb3b316..59667444669f 100644 --- a/include/linux/sched/cpufreq.h +++ b/include/linux/sched/cpufreq.h @@ -9,6 +9,7 @@ */ #define SCHED_CPUFREQ_IOWAIT (1U << 0) +#define SCHED_CPUFREQ_MIGRATION (1U << 1) #ifdef CONFIG_CPU_FREQ struct update_util_data { diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 494d5db9a6cd..e8f5efe2936c 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -772,7 +772,7 @@ void post_init_entity_util_avg(struct sched_entity *se) * For !fair tasks do: * update_cfs_rq_load_avg(now, cfs_rq); - attach_entity_load_avg(cfs_rq, se); + attach_entity_load_avg(cfs_rq, se, 0); switched_from_fair(rq, p); * * such that the next switched_to_fair() has the @@ -3009,11 +3009,11 @@ static inline void update_cfs_group(struct sched_entity *se) } #endif /* CONFIG_FAIR_GROUP_SCHED */ -static inline void cfs_rq_util_change(struct cfs_rq *cfs_rq) +static inline void cfs_rq_util_change(struct cfs_rq *cfs_rq, int flags) { struct rq *rq = rq_of(cfs_rq); - if (&rq->cfs == cfs_rq) { + if (&rq->cfs == cfs_rq || (flags & SCHED_CPUFREQ_MIGRATION)) { /* * There are a few boundary cases this might miss but it should * get called often enough that that should (hopefully) not be @@ -3028,7 +3028,7 @@ static inline void cfs_rq_util_change(struct cfs_rq *cfs_rq) * * See cpu_util(). */ - cpufreq_update_util(rq, 0); + cpufreq_update_util(rq, flags); } } @@ -3686,7 +3686,7 @@ update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq) #endif if (decayed) - cfs_rq_util_change(cfs_rq); + cfs_rq_util_change(cfs_rq, 0); return decayed; } @@ -3699,7 +3699,7 @@ update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq) * Must call update_cfs_rq_load_avg() before this, since we rely on * cfs_rq->avg.last_update_time being current. */ -static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) +static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) { u32 divider = LOAD_AVG_MAX - 1024 + cfs_rq->avg.period_contrib; @@ -3735,7 +3735,7 @@ static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *s add_tg_cfs_propagate(cfs_rq, se->avg.load_sum); - cfs_rq_util_change(cfs_rq); + cfs_rq_util_change(cfs_rq, flags); } /** @@ -3754,7 +3754,7 @@ static void detach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *s add_tg_cfs_propagate(cfs_rq, -se->avg.load_sum); - cfs_rq_util_change(cfs_rq); + cfs_rq_util_change(cfs_rq, 0); } /* @@ -3784,7 +3784,14 @@ static inline void update_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *s if (!se->avg.last_update_time && (flags & DO_ATTACH)) { - attach_entity_load_avg(cfs_rq, se); + /* + * DO_ATTACH means we're here from enqueue_entity(). + * !last_update_time means we've passed through + * migrate_task_rq_fair() indicating we migrated. + * + * IOW we're enqueueing a task on a new CPU. + */ + attach_entity_load_avg(cfs_rq, se, SCHED_CPUFREQ_MIGRATION); update_tg_load_avg(cfs_rq, 0); } else if (decayed && (flags & UPDATE_TG)) @@ -3880,13 +3887,13 @@ update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq) static inline void update_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se, int not_used1) { - cfs_rq_util_change(cfs_rq); + cfs_rq_util_change(cfs_rq, 0); } static inline void remove_entity_load_avg(struct sched_entity *se) {} static inline void -attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) {} +attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) {} static inline void detach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) {} @@ -9726,7 +9733,7 @@ static void attach_entity_cfs_rq(struct sched_entity *se) /* Synchronize entity with its cfs_rq */ update_load_avg(cfs_rq, se, sched_feat(ATTACH_AGE_LOAD) ? 0 : SKIP_AGE_LOAD); - attach_entity_load_avg(cfs_rq, se); + attach_entity_load_avg(cfs_rq, se, 0); update_tg_load_avg(cfs_rq, false); propagate_entity_cfs_rq(se); } -- cgit v1.2.3 From 484cb153fe5ffcd0b7cf423cf29aaeadd0e862b1 Mon Sep 17 00:00:00 2001 From: Radion Mirchevsky Date: Wed, 4 Oct 2017 14:53:54 +0300 Subject: thunderbolt: Add tb_xdomain_find_by_route() This is needed by the new ICM interface to find xdomains by route string instead of link and depth. While there update existing tb_xdomain_find_* functions to use tb_xdomain_get() instead of open-coding the same. Signed-off-by: Radion Mirchevsky Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko --- drivers/thunderbolt/xdomain.c | 47 ++++++++++++++++++++++++++++++++----------- include/linux/thunderbolt.h | 13 ++++++++++++ 2 files changed, 48 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/drivers/thunderbolt/xdomain.c b/drivers/thunderbolt/xdomain.c index f25d88d4552b..8abb4e843085 100644 --- a/drivers/thunderbolt/xdomain.c +++ b/drivers/thunderbolt/xdomain.c @@ -1255,6 +1255,7 @@ struct tb_xdomain_lookup { const uuid_t *uuid; u8 link; u8 depth; + u64 route; }; static struct tb_xdomain *switch_find_xdomain(struct tb_switch *sw, @@ -1275,9 +1276,13 @@ static struct tb_xdomain *switch_find_xdomain(struct tb_switch *sw, if (lookup->uuid) { if (uuid_equal(xd->remote_uuid, lookup->uuid)) return xd; - } else if (lookup->link == xd->link && + } else if (lookup->link && + lookup->link == xd->link && lookup->depth == xd->depth) { return xd; + } else if (lookup->route && + lookup->route == xd->route) { + return xd; } } else if (port->remote) { xd = switch_find_xdomain(port->remote->sw, lookup); @@ -1313,12 +1318,7 @@ struct tb_xdomain *tb_xdomain_find_by_uuid(struct tb *tb, const uuid_t *uuid) lookup.uuid = uuid; xd = switch_find_xdomain(tb->root_switch, &lookup); - if (xd) { - get_device(&xd->dev); - return xd; - } - - return NULL; + return tb_xdomain_get(xd); } EXPORT_SYMBOL_GPL(tb_xdomain_find_by_uuid); @@ -1349,13 +1349,36 @@ struct tb_xdomain *tb_xdomain_find_by_link_depth(struct tb *tb, u8 link, lookup.depth = depth; xd = switch_find_xdomain(tb->root_switch, &lookup); - if (xd) { - get_device(&xd->dev); - return xd; - } + return tb_xdomain_get(xd); +} - return NULL; +/** + * tb_xdomain_find_by_route() - Find an XDomain by route string + * @tb: Domain where the XDomain belongs to + * @route: XDomain route string + * + * Finds XDomain by walking through the Thunderbolt topology below @tb. + * The returned XDomain will have its reference count increased so the + * caller needs to call tb_xdomain_put() when it is done with the + * object. + * + * This will find all XDomains including the ones that are not yet added + * to the bus (handshake is still in progress). + * + * The caller needs to hold @tb->lock. + */ +struct tb_xdomain *tb_xdomain_find_by_route(struct tb *tb, u64 route) +{ + struct tb_xdomain_lookup lookup; + struct tb_xdomain *xd; + + memset(&lookup, 0, sizeof(lookup)); + lookup.route = route; + + xd = switch_find_xdomain(tb->root_switch, &lookup); + return tb_xdomain_get(xd); } +EXPORT_SYMBOL_GPL(tb_xdomain_find_by_route); bool tb_xdomain_handle_request(struct tb *tb, enum tb_cfg_pkg_type type, const void *buf, size_t size) diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index 7b69853188b1..27b9be34d4b9 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -237,6 +237,7 @@ int tb_xdomain_enable_paths(struct tb_xdomain *xd, u16 transmit_path, u16 receive_ring); int tb_xdomain_disable_paths(struct tb_xdomain *xd); struct tb_xdomain *tb_xdomain_find_by_uuid(struct tb *tb, const uuid_t *uuid); +struct tb_xdomain *tb_xdomain_find_by_route(struct tb *tb, u64 route); static inline struct tb_xdomain * tb_xdomain_find_by_uuid_locked(struct tb *tb, const uuid_t *uuid) @@ -250,6 +251,18 @@ tb_xdomain_find_by_uuid_locked(struct tb *tb, const uuid_t *uuid) return xd; } +static inline struct tb_xdomain * +tb_xdomain_find_by_route_locked(struct tb *tb, u64 route) +{ + struct tb_xdomain *xd; + + mutex_lock(&tb->lock); + xd = tb_xdomain_find_by_route(tb, route); + mutex_unlock(&tb->lock); + + return xd; +} + static inline struct tb_xdomain *tb_xdomain_get(struct tb_xdomain *xd) { if (xd) -- cgit v1.2.3 From 9aaa3b8b4c56d24210acef37b7c800ca218c3d40 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Sun, 21 Jan 2018 12:08:04 +0200 Subject: thunderbolt: Add support for preboot ACL Preboot ACL is a mechanism that allows connecting Thunderbolt devices boot time in more secure way than the legacy Thunderbolt boot support. As with the legacy boot option, this also needs to be enabled from the BIOS before booting is allowed. Difference to the legacy mode is that the userspace software explicitly adds device UUIDs by sending a special message to the ICM firmware. Only the devices listed in the boot ACL are connected automatically during the boot. This works in both "user" and "secure" security levels. We implement this in Linux by exposing a new sysfs attribute (boot_acl) below each Thunderbolt domain. The userspace software can then update the full list as needed. Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko --- Documentation/ABI/testing/sysfs-bus-thunderbolt | 23 ++++ drivers/thunderbolt/domain.c | 123 ++++++++++++++++++ drivers/thunderbolt/icm.c | 158 ++++++++++++++++++++++-- drivers/thunderbolt/tb.h | 4 + drivers/thunderbolt/tb_msgs.h | 35 +++++- include/linux/thunderbolt.h | 2 + 6 files changed, 335 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt b/Documentation/ABI/testing/sysfs-bus-thunderbolt index 1f145b727d76..4ed229789852 100644 --- a/Documentation/ABI/testing/sysfs-bus-thunderbolt +++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt @@ -1,3 +1,26 @@ +What: /sys/bus/thunderbolt/devices/.../domainX/boot_acl +Date: Jun 2018 +KernelVersion: 4.17 +Contact: thunderbolt-software@lists.01.org +Description: Holds a comma separated list of device unique_ids that + are allowed to be connected automatically during system + startup (e.g boot devices). The list always contains + maximum supported number of unique_ids where unused + entries are empty. This allows the userspace software + to determine how many entries the controller supports. + If there are multiple controllers, each controller has + its own ACL list and size may be different between the + controllers. + + System BIOS may have an option "Preboot ACL" or similar + that needs to be selected before this list is taken into + consideration. + + Software always updates a full list in each write. + + If a device is authorized automatically during boot its + boot attribute is set to 1. + What: /sys/bus/thunderbolt/devices/.../domainX/security Date: Sep 2017 KernelVersion: 4.13 diff --git a/drivers/thunderbolt/domain.c b/drivers/thunderbolt/domain.c index 9b90115319ce..ab4b304306f7 100644 --- a/drivers/thunderbolt/domain.c +++ b/drivers/thunderbolt/domain.c @@ -119,6 +119,110 @@ static const char * const tb_security_names[] = { [TB_SECURITY_DPONLY] = "dponly", }; +static ssize_t boot_acl_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct tb *tb = container_of(dev, struct tb, dev); + uuid_t *uuids; + ssize_t ret; + int i; + + uuids = kcalloc(tb->nboot_acl, sizeof(uuid_t), GFP_KERNEL); + if (!uuids) + return -ENOMEM; + + if (mutex_lock_interruptible(&tb->lock)) { + ret = -ERESTARTSYS; + goto out; + } + ret = tb->cm_ops->get_boot_acl(tb, uuids, tb->nboot_acl); + if (ret) { + mutex_unlock(&tb->lock); + goto out; + } + mutex_unlock(&tb->lock); + + for (ret = 0, i = 0; i < tb->nboot_acl; i++) { + if (!uuid_is_null(&uuids[i])) + ret += snprintf(buf + ret, PAGE_SIZE - ret, "%pUb", + &uuids[i]); + + ret += snprintf(buf + ret, PAGE_SIZE - ret, "%s", + i < tb->nboot_acl - 1 ? "," : "\n"); + } + +out: + kfree(uuids); + return ret; +} + +static ssize_t boot_acl_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct tb *tb = container_of(dev, struct tb, dev); + char *str, *s, *uuid_str; + ssize_t ret = 0; + uuid_t *acl; + int i = 0; + + /* + * Make sure the value is not bigger than tb->nboot_acl * UUID + * length + commas and optional "\n". Also the smallest allowable + * string is tb->nboot_acl * ",". + */ + if (count > (UUID_STRING_LEN + 1) * tb->nboot_acl + 1) + return -EINVAL; + if (count < tb->nboot_acl - 1) + return -EINVAL; + + str = kstrdup(buf, GFP_KERNEL); + if (!str) + return -ENOMEM; + + acl = kcalloc(tb->nboot_acl, sizeof(uuid_t), GFP_KERNEL); + if (!acl) { + ret = -ENOMEM; + goto err_free_str; + } + + uuid_str = strim(str); + while ((s = strsep(&uuid_str, ",")) != NULL && i < tb->nboot_acl) { + size_t len = strlen(s); + + if (len) { + if (len != UUID_STRING_LEN) { + ret = -EINVAL; + goto err_free_acl; + } + ret = uuid_parse(s, &acl[i]); + if (ret) + goto err_free_acl; + } + + i++; + } + + if (s || i < tb->nboot_acl) { + ret = -EINVAL; + goto err_free_acl; + } + + if (mutex_lock_interruptible(&tb->lock)) { + ret = -ERESTARTSYS; + goto err_free_acl; + } + ret = tb->cm_ops->set_boot_acl(tb, acl, tb->nboot_acl); + mutex_unlock(&tb->lock); + +err_free_acl: + kfree(acl); +err_free_str: + kfree(str); + + return ret ?: count; +} +static DEVICE_ATTR_RW(boot_acl); + static ssize_t security_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -129,11 +233,30 @@ static ssize_t security_show(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR_RO(security); static struct attribute *domain_attrs[] = { + &dev_attr_boot_acl.attr, &dev_attr_security.attr, NULL, }; +static umode_t domain_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tb *tb = container_of(dev, struct tb, dev); + + if (attr == &dev_attr_boot_acl.attr) { + if (tb->nboot_acl && + tb->cm_ops->get_boot_acl && + tb->cm_ops->set_boot_acl) + return attr->mode; + return 0; + } + + return attr->mode; +} + static struct attribute_group domain_attr_group = { + .is_visible = domain_attr_is_visible, .attrs = domain_attrs, }; diff --git a/drivers/thunderbolt/icm.c b/drivers/thunderbolt/icm.c index bece5540b06b..93a198a17f42 100644 --- a/drivers/thunderbolt/icm.c +++ b/drivers/thunderbolt/icm.c @@ -56,6 +56,7 @@ * @vnd_cap: Vendor defined capability where PCIe2CIO mailbox resides * (only set when @upstream_port is not %NULL) * @safe_mode: ICM is in safe mode + * @max_boot_acl: Maximum number of preboot ACL entries (%0 if not supported) * @is_supported: Checks if we can support ICM on this controller * @get_mode: Read and return the ICM firmware mode (optional) * @get_route: Find a route string for given switch @@ -69,13 +70,15 @@ struct icm { struct mutex request_lock; struct delayed_work rescan_work; struct pci_dev *upstream_port; + size_t max_boot_acl; int vnd_cap; bool safe_mode; bool (*is_supported)(struct tb *tb); int (*get_mode)(struct tb *tb); int (*get_route)(struct tb *tb, u8 link, u8 depth, u64 *route); int (*driver_ready)(struct tb *tb, - enum tb_security_level *security_level); + enum tb_security_level *security_level, + size_t *nboot_acl); void (*device_connected)(struct tb *tb, const struct icm_pkg_header *hdr); void (*device_disconnected)(struct tb *tb, @@ -250,7 +253,8 @@ err_free: } static int -icm_fr_driver_ready(struct tb *tb, enum tb_security_level *security_level) +icm_fr_driver_ready(struct tb *tb, enum tb_security_level *security_level, + size_t *nboot_acl) { struct icm_fr_pkg_driver_ready_response reply; struct icm_pkg_driver_ready request = { @@ -827,6 +831,30 @@ static int icm_ar_get_mode(struct tb *tb) return nhi_mailbox_mode(nhi); } +static int +icm_ar_driver_ready(struct tb *tb, enum tb_security_level *security_level, + size_t *nboot_acl) +{ + struct icm_ar_pkg_driver_ready_response reply; + struct icm_pkg_driver_ready request = { + .hdr.code = ICM_DRIVER_READY, + }; + int ret; + + memset(&reply, 0, sizeof(reply)); + ret = icm_request(tb, &request, sizeof(request), &reply, sizeof(reply), + 1, ICM_TIMEOUT); + if (ret) + return ret; + + if (security_level) + *security_level = reply.info & ICM_AR_INFO_SLEVEL_MASK; + if (nboot_acl && (reply.info & ICM_AR_INFO_BOOT_ACL_SUPPORTED)) + *nboot_acl = (reply.info & ICM_AR_INFO_BOOT_ACL_MASK) >> + ICM_AR_INFO_BOOT_ACL_SHIFT; + return 0; +} + static int icm_ar_get_route(struct tb *tb, u8 link, u8 depth, u64 *route) { struct icm_ar_pkg_get_route_response reply; @@ -849,6 +877,87 @@ static int icm_ar_get_route(struct tb *tb, u8 link, u8 depth, u64 *route) return 0; } +static int icm_ar_get_boot_acl(struct tb *tb, uuid_t *uuids, size_t nuuids) +{ + struct icm_ar_pkg_preboot_acl_response reply; + struct icm_ar_pkg_preboot_acl request = { + .hdr = { .code = ICM_PREBOOT_ACL }, + }; + int ret, i; + + memset(&reply, 0, sizeof(reply)); + ret = icm_request(tb, &request, sizeof(request), &reply, sizeof(reply), + 1, ICM_TIMEOUT); + if (ret) + return ret; + + if (reply.hdr.flags & ICM_FLAGS_ERROR) + return -EIO; + + for (i = 0; i < nuuids; i++) { + u32 *uuid = (u32 *)&uuids[i]; + + uuid[0] = reply.acl[i].uuid_lo; + uuid[1] = reply.acl[i].uuid_hi; + + if (uuid[0] == 0xffffffff && uuid[1] == 0xffffffff) { + /* Map empty entries to null UUID */ + uuid[0] = 0; + uuid[1] = 0; + } else { + /* Upper two DWs are always one's */ + uuid[2] = 0xffffffff; + uuid[3] = 0xffffffff; + } + } + + return ret; +} + +static int icm_ar_set_boot_acl(struct tb *tb, const uuid_t *uuids, + size_t nuuids) +{ + struct icm_ar_pkg_preboot_acl_response reply; + struct icm_ar_pkg_preboot_acl request = { + .hdr = { + .code = ICM_PREBOOT_ACL, + .flags = ICM_FLAGS_WRITE, + }, + }; + int ret, i; + + for (i = 0; i < nuuids; i++) { + const u32 *uuid = (const u32 *)&uuids[i]; + + if (uuid_is_null(&uuids[i])) { + /* + * Map null UUID to the empty (all one) entries + * for ICM. + */ + request.acl[i].uuid_lo = 0xffffffff; + request.acl[i].uuid_hi = 0xffffffff; + } else { + /* Two high DWs need to be set to all one */ + if (uuid[2] != 0xffffffff || uuid[3] != 0xffffffff) + return -EINVAL; + + request.acl[i].uuid_lo = uuid[0]; + request.acl[i].uuid_hi = uuid[1]; + } + } + + memset(&reply, 0, sizeof(reply)); + ret = icm_request(tb, &request, sizeof(request), &reply, sizeof(reply), + 1, ICM_TIMEOUT); + if (ret) + return ret; + + if (reply.hdr.flags & ICM_FLAGS_ERROR) + return -EIO; + + return 0; +} + static void icm_handle_notification(struct work_struct *work) { struct icm_notification *n = container_of(work, typeof(*n), work); @@ -895,13 +1004,14 @@ static void icm_handle_event(struct tb *tb, enum tb_cfg_pkg_type type, } static int -__icm_driver_ready(struct tb *tb, enum tb_security_level *security_level) +__icm_driver_ready(struct tb *tb, enum tb_security_level *security_level, + size_t *nboot_acl) { struct icm *icm = tb_priv(tb); unsigned int retries = 50; int ret; - ret = icm->driver_ready(tb, security_level); + ret = icm->driver_ready(tb, security_level, nboot_acl); if (ret) { tb_err(tb, "failed to send driver ready to ICM\n"); return ret; @@ -1168,7 +1278,18 @@ static int icm_driver_ready(struct tb *tb) return 0; } - return __icm_driver_ready(tb, &tb->security_level); + ret = __icm_driver_ready(tb, &tb->security_level, &tb->nboot_acl); + if (ret) + return ret; + + /* + * Make sure the number of supported preboot ACL matches what we + * expect or disable the whole feature. + */ + if (tb->nboot_acl > icm->max_boot_acl) + tb->nboot_acl = 0; + + return 0; } static int icm_suspend(struct tb *tb) @@ -1264,7 +1385,7 @@ static void icm_complete(struct tb *tb) * Now all existing children should be resumed, start events * from ICM to get updated status. */ - __icm_driver_ready(tb, NULL); + __icm_driver_ready(tb, NULL, NULL); /* * We do not get notifications of devices that have been @@ -1317,7 +1438,7 @@ static int icm_disconnect_pcie_paths(struct tb *tb) return nhi_mailbox_cmd(tb->nhi, NHI_MAILBOX_DISCONNECT_PCIE_PATHS, 0); } -/* Falcon Ridge and Alpine Ridge */ +/* Falcon Ridge */ static const struct tb_cm_ops icm_fr_ops = { .driver_ready = icm_driver_ready, .start = icm_start, @@ -1333,6 +1454,24 @@ static const struct tb_cm_ops icm_fr_ops = { .disconnect_xdomain_paths = icm_fr_disconnect_xdomain_paths, }; +/* Alpine Ridge */ +static const struct tb_cm_ops icm_ar_ops = { + .driver_ready = icm_driver_ready, + .start = icm_start, + .stop = icm_stop, + .suspend = icm_suspend, + .complete = icm_complete, + .handle_event = icm_handle_event, + .get_boot_acl = icm_ar_get_boot_acl, + .set_boot_acl = icm_ar_set_boot_acl, + .approve_switch = icm_fr_approve_switch, + .add_switch_key = icm_fr_add_switch_key, + .challenge_switch_key = icm_fr_challenge_switch_key, + .disconnect_pcie_paths = icm_disconnect_pcie_paths, + .approve_xdomain_paths = icm_fr_approve_xdomain_paths, + .disconnect_xdomain_paths = icm_fr_disconnect_xdomain_paths, +}; + struct tb *icm_probe(struct tb_nhi *nhi) { struct icm *icm; @@ -1364,15 +1503,16 @@ struct tb *icm_probe(struct tb_nhi *nhi) case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI: + icm->max_boot_acl = ICM_AR_PREBOOT_ACL_ENTRIES; icm->is_supported = icm_ar_is_supported; icm->get_mode = icm_ar_get_mode; icm->get_route = icm_ar_get_route; - icm->driver_ready = icm_fr_driver_ready; + icm->driver_ready = icm_ar_driver_ready; icm->device_connected = icm_fr_device_connected; icm->device_disconnected = icm_fr_device_disconnected; icm->xdomain_connected = icm_fr_xdomain_connected; icm->xdomain_disconnected = icm_fr_xdomain_disconnected; - tb->cm_ops = &icm_fr_ops; + tb->cm_ops = &icm_ar_ops; break; } diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h index 9c9cef875ca8..9d9f0ca16bfb 100644 --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h @@ -200,6 +200,8 @@ struct tb_path { * @suspend: Connection manager specific suspend * @complete: Connection manager specific complete * @handle_event: Handle thunderbolt event + * @get_boot_acl: Get boot ACL list + * @set_boot_acl: Set boot ACL list * @approve_switch: Approve switch * @add_switch_key: Add key to switch * @challenge_switch_key: Challenge switch using key @@ -217,6 +219,8 @@ struct tb_cm_ops { void (*complete)(struct tb *tb); void (*handle_event)(struct tb *tb, enum tb_cfg_pkg_type, const void *buf, size_t size); + int (*get_boot_acl)(struct tb *tb, uuid_t *uuids, size_t nuuids); + int (*set_boot_acl)(struct tb *tb, const uuid_t *uuids, size_t nuuids); int (*approve_switch)(struct tb *tb, struct tb_switch *sw); int (*add_switch_key)(struct tb *tb, struct tb_switch *sw); int (*challenge_switch_key)(struct tb *tb, struct tb_switch *sw, diff --git a/drivers/thunderbolt/tb_msgs.h b/drivers/thunderbolt/tb_msgs.h index 9f52f842257a..496b91f3b579 100644 --- a/drivers/thunderbolt/tb_msgs.h +++ b/drivers/thunderbolt/tb_msgs.h @@ -102,6 +102,7 @@ enum icm_pkg_code { ICM_ADD_DEVICE_KEY = 0x6, ICM_GET_ROUTE = 0xa, ICM_APPROVE_XDOMAIN = 0x10, + ICM_PREBOOT_ACL = 0x18, }; enum icm_event_code { @@ -122,12 +123,13 @@ struct icm_pkg_header { #define ICM_FLAGS_NO_KEY BIT(1) #define ICM_FLAGS_SLEVEL_SHIFT 3 #define ICM_FLAGS_SLEVEL_MASK GENMASK(4, 3) +#define ICM_FLAGS_WRITE BIT(7) struct icm_pkg_driver_ready { struct icm_pkg_header hdr; }; -/* Falcon Ridge & Alpine Ridge common messages */ +/* Falcon Ridge only messages */ struct icm_fr_pkg_driver_ready_response { struct icm_pkg_header hdr; @@ -138,6 +140,8 @@ struct icm_fr_pkg_driver_ready_response { #define ICM_FR_SLEVEL_MASK 0xf +/* Falcon Ridge & Alpine Ridge common messages */ + struct icm_fr_pkg_get_topology { struct icm_pkg_header hdr; }; @@ -274,6 +278,18 @@ struct icm_fr_pkg_approve_xdomain_response { /* Alpine Ridge only messages */ +struct icm_ar_pkg_driver_ready_response { + struct icm_pkg_header hdr; + u8 romver; + u8 ramver; + u16 info; +}; + +#define ICM_AR_INFO_SLEVEL_MASK GENMASK(3, 0) +#define ICM_AR_INFO_BOOT_ACL_SHIFT 7 +#define ICM_AR_INFO_BOOT_ACL_MASK GENMASK(11, 7) +#define ICM_AR_INFO_BOOT_ACL_SUPPORTED BIT(13) + struct icm_ar_pkg_get_route { struct icm_pkg_header hdr; u16 reserved; @@ -288,6 +304,23 @@ struct icm_ar_pkg_get_route_response { u32 route_lo; }; +struct icm_ar_boot_acl_entry { + u32 uuid_lo; + u32 uuid_hi; +}; + +#define ICM_AR_PREBOOT_ACL_ENTRIES 16 + +struct icm_ar_pkg_preboot_acl { + struct icm_pkg_header hdr; + struct icm_ar_boot_acl_entry acl[ICM_AR_PREBOOT_ACL_ENTRIES]; +}; + +struct icm_ar_pkg_preboot_acl_response { + struct icm_pkg_header hdr; + struct icm_ar_boot_acl_entry acl[ICM_AR_PREBOOT_ACL_ENTRIES]; +}; + /* XDomain messages */ struct tb_xdomain_header { diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index 27b9be34d4b9..47251844d064 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -65,6 +65,7 @@ enum tb_security_level { * @cm_ops: Connection manager specific operations vector * @index: Linux assigned domain number * @security_level: Current security level + * @nboot_acl: Number of boot ACLs the domain supports * @privdata: Private connection manager specific data */ struct tb { @@ -77,6 +78,7 @@ struct tb { const struct tb_cm_ops *cm_ops; int index; enum tb_security_level security_level; + size_t nboot_acl; unsigned long privdata[0]; }; -- cgit v1.2.3 From 6fc14e1a44e53c472865252b47398346a27d600e Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Fri, 8 Dec 2017 14:11:39 +0300 Subject: thunderbolt: Introduce USB only (SL4) security level This new security level works so that it creates one PCIe tunnel to the connected Thunderbolt dock, removing PCIe links downstream of the dock. This leaves only the internal USB controller visible. Display Port tunnels are created normally. While there make sure security sysfs attribute returns "unknown" for any future security level. Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko --- Documentation/ABI/testing/sysfs-bus-thunderbolt | 3 +++ Documentation/admin-guide/thunderbolt.rst | 15 ++++++++++----- drivers/thunderbolt/domain.c | 7 ++++++- include/linux/thunderbolt.h | 4 ++++ 4 files changed, 23 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/Documentation/ABI/testing/sysfs-bus-thunderbolt b/Documentation/ABI/testing/sysfs-bus-thunderbolt index 4ed229789852..151584a1f950 100644 --- a/Documentation/ABI/testing/sysfs-bus-thunderbolt +++ b/Documentation/ABI/testing/sysfs-bus-thunderbolt @@ -35,6 +35,9 @@ Description: This attribute holds current Thunderbolt security level minimum. User needs to authorize each device. dponly: Automatically tunnel Display port (and USB). No PCIe tunnels are created. + usbonly: Automatically tunnel USB controller of the + connected Thunderbolt dock (and Display Port). All + PCIe links downstream of the dock are removed. What: /sys/bus/thunderbolt/devices/.../authorized Date: Sep 2017 diff --git a/Documentation/admin-guide/thunderbolt.rst b/Documentation/admin-guide/thunderbolt.rst index 9948ec36a204..35fccba6a9a6 100644 --- a/Documentation/admin-guide/thunderbolt.rst +++ b/Documentation/admin-guide/thunderbolt.rst @@ -21,11 +21,11 @@ vulnerable to DMA attacks. Security levels and how to use them ----------------------------------- Starting with Intel Falcon Ridge Thunderbolt controller there are 4 -security levels available. The reason for these is the fact that the -connected devices can be DMA masters and thus read contents of the host -memory without CPU and OS knowing about it. There are ways to prevent -this by setting up an IOMMU but it is not always available for various -reasons. +security levels available. Intel Titan Ridge added one more security level +(usbonly). The reason for these is the fact that the connected devices can +be DMA masters and thus read contents of the host memory without CPU and OS +knowing about it. There are ways to prevent this by setting up an IOMMU but +it is not always available for various reasons. The security levels are as follows: @@ -52,6 +52,11 @@ The security levels are as follows: USB. No PCIe tunneling is done. In BIOS settings this is typically called *Display Port Only*. + usbonly + The firmware automatically creates tunnels for the USB controller and + Display Port in a dock. All PCIe links downstream of the dock are + removed. + The current security level can be read from ``/sys/bus/thunderbolt/devices/domainX/security`` where ``domainX`` is the Thunderbolt domain the host controller manages. There is typically diff --git a/drivers/thunderbolt/domain.c b/drivers/thunderbolt/domain.c index ab4b304306f7..6281266b8ec0 100644 --- a/drivers/thunderbolt/domain.c +++ b/drivers/thunderbolt/domain.c @@ -117,6 +117,7 @@ static const char * const tb_security_names[] = { [TB_SECURITY_USER] = "user", [TB_SECURITY_SECURE] = "secure", [TB_SECURITY_DPONLY] = "dponly", + [TB_SECURITY_USBONLY] = "usbonly", }; static ssize_t boot_acl_show(struct device *dev, struct device_attribute *attr, @@ -227,8 +228,12 @@ static ssize_t security_show(struct device *dev, struct device_attribute *attr, char *buf) { struct tb *tb = container_of(dev, struct tb, dev); + const char *name = "unknown"; - return sprintf(buf, "%s\n", tb_security_names[tb->security_level]); + if (tb->security_level < ARRAY_SIZE(tb_security_names)) + name = tb_security_names[tb->security_level]; + + return sprintf(buf, "%s\n", name); } static DEVICE_ATTR_RO(security); diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index 47251844d064..a3ed26082bc1 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -45,12 +45,16 @@ enum tb_cfg_pkg_type { * @TB_SECURITY_USER: User approval required at minimum * @TB_SECURITY_SECURE: One time saved key required at minimum * @TB_SECURITY_DPONLY: Only tunnel Display port (and USB) + * @TB_SECURITY_USBONLY: Only tunnel USB controller of the connected + * Thunderbolt dock (and Display Port). All PCIe + * links downstream of the dock are removed. */ enum tb_security_level { TB_SECURITY_NONE, TB_SECURITY_USER, TB_SECURITY_SECURE, TB_SECURITY_DPONLY, + TB_SECURITY_USBONLY, }; /** -- cgit v1.2.3 From 79134e6ce2c9d1a00eab4d98cb48f975dd2474cb Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 8 Mar 2018 12:51:41 -0800 Subject: net: do not create fallback tunnels for non-default namespaces fallback tunnels (like tunl0, gre0, gretap0, erspan0, sit0, ip6tnl0, ip6gre0) are automatically created when the corresponding module is loaded. These tunnels are also automatically created when a new network namespace is created, at a great cost. In many cases, netns are used for isolation purposes, and these extra network devices are a waste of resources. We are using thousands of netns per host, and hit the netns creation/delete bottleneck a lot. (Many thanks to Kirill for recent work on this) Add a new sysctl so that we can opt-out from this automatic creation. Note that these tunnels are still created for the initial namespace, to be the least intrusive for typical setups. Tested: lpk43:~# cat add_del_unshare.sh for i in `seq 1 40` do (for j in `seq 1 100` ; do unshare -n /bin/true >/dev/null ; done) & done wait lpk43:~# echo 0 >/proc/sys/net/core/fb_tunnels_only_for_init_net lpk43:~# time ./add_del_unshare.sh real 0m37.521s user 0m0.886s sys 7m7.084s lpk43:~# echo 1 >/proc/sys/net/core/fb_tunnels_only_for_init_net lpk43:~# time ./add_del_unshare.sh real 0m4.761s user 0m0.851s sys 1m8.343s lpk43:~# Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller --- Documentation/sysctl/net.txt | 12 ++++++++++++ include/linux/netdevice.h | 7 +++++++ include/net/ip_tunnels.h | 2 ++ net/core/sysctl_net_core.c | 12 ++++++++++++ net/ipv4/ip_tunnel.c | 20 ++++++++++++-------- net/ipv6/ip6_gre.c | 4 +++- net/ipv6/ip6_tunnel.c | 2 ++ net/ipv6/sit.c | 5 ++++- 8 files changed, 54 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/Documentation/sysctl/net.txt b/Documentation/sysctl/net.txt index 35c62f522754..5992602469d8 100644 --- a/Documentation/sysctl/net.txt +++ b/Documentation/sysctl/net.txt @@ -270,6 +270,18 @@ optmem_max Maximum ancillary buffer size allowed per socket. Ancillary data is a sequence of struct cmsghdr structures with appended data. +fb_tunnels_only_for_init_net +---------------------------- + +Controls if fallback tunnels (like tunl0, gre0, gretap0, erspan0, +sit0, ip6tnl0, ip6gre0) are automatically created when a new +network namespace is created, if corresponding tunnel is present +in initial network namespace. +If set to 1, these devices are not automatically created, and +user space is responsible for creating them if needed. + +Default : 0 (for compatibility reasons) + 2. /proc/sys/net/unix - Parameters for Unix domain sockets ------------------------------------------------------- diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 95a613a7cc1c..9711108c3916 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -585,6 +585,13 @@ struct netdev_queue { #endif } ____cacheline_aligned_in_smp; +extern int sysctl_fb_tunnels_only_for_init_net; + +static inline bool net_has_fallback_tunnels(const struct net *net) +{ + return net == &init_net || !sysctl_fb_tunnels_only_for_init_net; +} + static inline int netdev_queue_numa_node_read(const struct netdev_queue *q) { #if defined(CONFIG_XPS) && defined(CONFIG_NUMA) diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h index cbe5addb9293..540a4b4417bf 100644 --- a/include/net/ip_tunnels.h +++ b/include/net/ip_tunnels.h @@ -180,8 +180,10 @@ struct tnl_ptk_info { struct ip_tunnel_net { struct net_device *fb_tunnel_dev; + struct rtnl_link_ops *rtnl_link_ops; struct hlist_head tunnels[IP_TNL_HASH_SIZE]; struct ip_tunnel __rcu *collect_md_tun; + int type; }; static inline void ip_tunnel_key_init(struct ip_tunnel_key *key, diff --git a/net/core/sysctl_net_core.c b/net/core/sysctl_net_core.c index d714f65782b7..4f47f92459cc 100644 --- a/net/core/sysctl_net_core.c +++ b/net/core/sysctl_net_core.c @@ -32,6 +32,9 @@ static int max_skb_frags = MAX_SKB_FRAGS; static int net_msg_warn; /* Unused, but still a sysctl */ +int sysctl_fb_tunnels_only_for_init_net __read_mostly = 0; +EXPORT_SYMBOL(sysctl_fb_tunnels_only_for_init_net); + #ifdef CONFIG_RPS static int rps_sock_flow_sysctl(struct ctl_table *table, int write, void __user *buffer, size_t *lenp, loff_t *ppos) @@ -513,6 +516,15 @@ static struct ctl_table net_core_table[] = { .proc_handler = proc_dointvec_minmax, .extra1 = &zero, }, + { + .procname = "fb_tunnels_only_for_init_net", + .data = &sysctl_fb_tunnels_only_for_init_net, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &one, + }, { } }; diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c index 602597dfc395..5fcb17cb426b 100644 --- a/net/ipv4/ip_tunnel.c +++ b/net/ipv4/ip_tunnel.c @@ -347,8 +347,7 @@ static struct ip_tunnel *ip_tunnel_create(struct net *net, struct net_device *dev; int t_hlen; - BUG_ON(!itn->fb_tunnel_dev); - dev = __ip_tunnel_create(net, itn->fb_tunnel_dev->rtnl_link_ops, parms); + dev = __ip_tunnel_create(net, itn->rtnl_link_ops, parms); if (IS_ERR(dev)) return ERR_CAST(dev); @@ -822,7 +821,6 @@ int ip_tunnel_ioctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd) struct net *net = t->net; struct ip_tunnel_net *itn = net_generic(net, t->ip_tnl_net_id); - BUG_ON(!itn->fb_tunnel_dev); switch (cmd) { case SIOCGETTUNNEL: if (dev == itn->fb_tunnel_dev) { @@ -847,7 +845,7 @@ int ip_tunnel_ioctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd) p->o_key = 0; } - t = ip_tunnel_find(itn, p, itn->fb_tunnel_dev->type); + t = ip_tunnel_find(itn, p, itn->type); if (cmd == SIOCADDTUNNEL) { if (!t) { @@ -991,10 +989,15 @@ int ip_tunnel_init_net(struct net *net, unsigned int ip_tnl_net_id, struct ip_tunnel_parm parms; unsigned int i; + itn->rtnl_link_ops = ops; for (i = 0; i < IP_TNL_HASH_SIZE; i++) INIT_HLIST_HEAD(&itn->tunnels[i]); - if (!ops) { + if (!ops || !net_has_fallback_tunnels(net)) { + struct ip_tunnel_net *it_init_net; + + it_init_net = net_generic(&init_net, ip_tnl_net_id); + itn->type = it_init_net->type; itn->fb_tunnel_dev = NULL; return 0; } @@ -1012,6 +1015,7 @@ int ip_tunnel_init_net(struct net *net, unsigned int ip_tnl_net_id, itn->fb_tunnel_dev->features |= NETIF_F_NETNS_LOCAL; itn->fb_tunnel_dev->mtu = ip_tunnel_bind_dev(itn->fb_tunnel_dev); ip_tunnel_add(itn, netdev_priv(itn->fb_tunnel_dev)); + itn->type = itn->fb_tunnel_dev->type; } rtnl_unlock(); @@ -1019,10 +1023,10 @@ int ip_tunnel_init_net(struct net *net, unsigned int ip_tnl_net_id, } EXPORT_SYMBOL_GPL(ip_tunnel_init_net); -static void ip_tunnel_destroy(struct ip_tunnel_net *itn, struct list_head *head, +static void ip_tunnel_destroy(struct net *net, struct ip_tunnel_net *itn, + struct list_head *head, struct rtnl_link_ops *ops) { - struct net *net = dev_net(itn->fb_tunnel_dev); struct net_device *dev, *aux; int h; @@ -1054,7 +1058,7 @@ void ip_tunnel_delete_nets(struct list_head *net_list, unsigned int id, rtnl_lock(); list_for_each_entry(net, net_list, exit_list) { itn = net_generic(net, id); - ip_tunnel_destroy(itn, &list, ops); + ip_tunnel_destroy(net, itn, &list, ops); } unregister_netdevice_many(&list); rtnl_unlock(); diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index 18a3dfbd0300..7d8775c9570d 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -236,7 +236,7 @@ static struct ip6_tnl *ip6gre_tunnel_lookup(struct net_device *dev, return t; dev = ign->fb_tunnel_dev; - if (dev->flags & IFF_UP) + if (dev && dev->flags & IFF_UP) return netdev_priv(dev); return NULL; @@ -1472,6 +1472,8 @@ static int __net_init ip6gre_init_net(struct net *net) struct ip6gre_net *ign = net_generic(net, ip6gre_net_id); int err; + if (!net_has_fallback_tunnels(net)) + return 0; ign->fb_tunnel_dev = alloc_netdev(sizeof(struct ip6_tnl), "ip6gre0", NET_NAME_UNKNOWN, ip6gre_tunnel_setup); diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c index 56c4967f1868..5c045fa407da 100644 --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c @@ -2205,6 +2205,8 @@ static int __net_init ip6_tnl_init_net(struct net *net) ip6n->tnls[0] = ip6n->tnls_wc; ip6n->tnls[1] = ip6n->tnls_r_l; + if (!net_has_fallback_tunnels(net)) + return 0; err = -ENOMEM; ip6n->fb_tnl_dev = alloc_netdev(sizeof(struct ip6_tnl), "ip6tnl0", NET_NAME_UNKNOWN, ip6_tnl_dev_setup); diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c index a9c4ac6efe22..8a4f8fddd812 100644 --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c @@ -182,7 +182,7 @@ static void ipip6_tunnel_clone_6rd(struct net_device *dev, struct sit_net *sitn) #ifdef CONFIG_IPV6_SIT_6RD struct ip_tunnel *t = netdev_priv(dev); - if (dev == sitn->fb_tunnel_dev) { + if (dev == sitn->fb_tunnel_dev || !sitn->fb_tunnel_dev) { ipv6_addr_set(&t->ip6rd.prefix, htonl(0x20020000), 0, 0, 0); t->ip6rd.relay_prefix = 0; t->ip6rd.prefixlen = 16; @@ -1835,6 +1835,9 @@ static int __net_init sit_init_net(struct net *net) sitn->tunnels[2] = sitn->tunnels_r; sitn->tunnels[3] = sitn->tunnels_r_l; + if (!net_has_fallback_tunnels(net)) + return 0; + sitn->fb_tunnel_dev = alloc_netdev(sizeof(struct ip_tunnel), "sit0", NET_NAME_UNKNOWN, ipip6_tunnel_setup); -- cgit v1.2.3 From 3a4030761ea88ff439030ca98e3094b9900e96b7 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Fri, 9 Mar 2018 14:50:34 +0800 Subject: vhost_net: examine pointer types during un-producing After commit fc72d1d54dd9 ("tuntap: XDP transmission"), we can actually queueing XDP pointers in the pointer ring, so we should examine the pointer type before freeing the pointer. Fixes: fc72d1d54dd9 ("tuntap: XDP transmission") Reported-by: Michael S. Tsirkin Acked-by: Michael S. Tsirkin Signed-off-by: Jason Wang Signed-off-by: David S. Miller --- drivers/net/tun.c | 3 ++- drivers/vhost/net.c | 2 +- include/linux/if_tun.h | 4 ++++ 3 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 7433bb2e4451..28cfa642e39a 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -655,7 +655,7 @@ static struct tun_struct *tun_enable_queue(struct tun_file *tfile) return tun; } -static void tun_ptr_free(void *ptr) +void tun_ptr_free(void *ptr) { if (!ptr) return; @@ -667,6 +667,7 @@ static void tun_ptr_free(void *ptr) __skb_array_destroy_skb(ptr); } } +EXPORT_SYMBOL_GPL(tun_ptr_free); static void tun_queue_purge(struct tun_file *tfile) { diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c index efb93063fda1..8139bc70ad7d 100644 --- a/drivers/vhost/net.c +++ b/drivers/vhost/net.c @@ -170,7 +170,7 @@ static void vhost_net_buf_unproduce(struct vhost_net_virtqueue *nvq) if (nvq->rx_ring && !vhost_net_buf_is_empty(rxq)) { ptr_ring_unconsume(nvq->rx_ring, rxq->queue + rxq->head, vhost_net_buf_get_size(rxq), - __skb_array_destroy_skb); + tun_ptr_free); rxq->head = rxq->tail = 0; } } diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h index c5b0a75a7812..fd00170b494f 100644 --- a/include/linux/if_tun.h +++ b/include/linux/if_tun.h @@ -25,6 +25,7 @@ struct ptr_ring *tun_get_tx_ring(struct file *file); bool tun_is_xdp_buff(void *ptr); void *tun_xdp_to_ptr(void *ptr); void *tun_ptr_to_xdp(void *ptr); +void tun_ptr_free(void *ptr); #else #include #include @@ -50,5 +51,8 @@ static inline void *tun_ptr_to_xdp(void *ptr) { return NULL; } +static inline void tun_ptr_free(void *ptr) +{ +} #endif /* CONFIG_TUN */ #endif /* __IF_TUN_H */ -- cgit v1.2.3 From ccefd976f921a280327b17b2896bc809baa7b672 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 2 Jan 2018 15:50:49 +0000 Subject: typec: tcpm: Add PD Rev 3.0 definitions to PD header This commit adds definitions for PD Rev 3.0 messages, including APDO PPS and extended message support for TCPM. Signed-off-by: Adam Thomson Acked-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- include/linux/usb/pd.h | 185 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 174 insertions(+), 11 deletions(-) (limited to 'include/linux') diff --git a/include/linux/usb/pd.h b/include/linux/usb/pd.h index b3d41d7409b3..ff359bdfdc7b 100644 --- a/include/linux/usb/pd.h +++ b/include/linux/usb/pd.h @@ -35,6 +35,13 @@ enum pd_ctrl_msg_type { PD_CTRL_WAIT = 12, PD_CTRL_SOFT_RESET = 13, /* 14-15 Reserved */ + PD_CTRL_NOT_SUPP = 16, + PD_CTRL_GET_SOURCE_CAP_EXT = 17, + PD_CTRL_GET_STATUS = 18, + PD_CTRL_FR_SWAP = 19, + PD_CTRL_GET_PPS_STATUS = 20, + PD_CTRL_GET_COUNTRY_CODES = 21, + /* 22-31 Reserved */ }; enum pd_data_msg_type { @@ -43,13 +50,39 @@ enum pd_data_msg_type { PD_DATA_REQUEST = 2, PD_DATA_BIST = 3, PD_DATA_SINK_CAP = 4, - /* 5-14 Reserved */ + PD_DATA_BATT_STATUS = 5, + PD_DATA_ALERT = 6, + PD_DATA_GET_COUNTRY_INFO = 7, + /* 8-14 Reserved */ PD_DATA_VENDOR_DEF = 15, + /* 16-31 Reserved */ +}; + +enum pd_ext_msg_type { + /* 0 Reserved */ + PD_EXT_SOURCE_CAP_EXT = 1, + PD_EXT_STATUS = 2, + PD_EXT_GET_BATT_CAP = 3, + PD_EXT_GET_BATT_STATUS = 4, + PD_EXT_BATT_CAP = 5, + PD_EXT_GET_MANUFACTURER_INFO = 6, + PD_EXT_MANUFACTURER_INFO = 7, + PD_EXT_SECURITY_REQUEST = 8, + PD_EXT_SECURITY_RESPONSE = 9, + PD_EXT_FW_UPDATE_REQUEST = 10, + PD_EXT_FW_UPDATE_RESPONSE = 11, + PD_EXT_PPS_STATUS = 12, + PD_EXT_COUNTRY_INFO = 13, + PD_EXT_COUNTRY_CODES = 14, + /* 15-31 Reserved */ }; #define PD_REV10 0x0 #define PD_REV20 0x1 +#define PD_REV30 0x2 +#define PD_MAX_REV PD_REV30 +#define PD_HEADER_EXT_HDR BIT(15) #define PD_HEADER_CNT_SHIFT 12 #define PD_HEADER_CNT_MASK 0x7 #define PD_HEADER_ID_SHIFT 9 @@ -59,18 +92,19 @@ enum pd_data_msg_type { #define PD_HEADER_REV_MASK 0x3 #define PD_HEADER_DATA_ROLE BIT(5) #define PD_HEADER_TYPE_SHIFT 0 -#define PD_HEADER_TYPE_MASK 0xf +#define PD_HEADER_TYPE_MASK 0x1f -#define PD_HEADER(type, pwr, data, id, cnt) \ +#define PD_HEADER(type, pwr, data, rev, id, cnt, ext_hdr) \ ((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) | \ ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) | \ ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) | \ - (PD_REV20 << PD_HEADER_REV_SHIFT) | \ + (rev << PD_HEADER_REV_SHIFT) | \ (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) | \ - (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT)) + (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT) | \ + ((ext_hdr) ? PD_HEADER_EXT_HDR : 0)) #define PD_HEADER_LE(type, pwr, data, id, cnt) \ - cpu_to_le16(PD_HEADER((type), (pwr), (data), (id), (cnt))) + cpu_to_le16(PD_HEADER((type), (pwr), (data), PD_REV20, (id), (cnt), (0))) static inline unsigned int pd_header_cnt(u16 header) { @@ -102,16 +136,75 @@ static inline unsigned int pd_header_msgid_le(__le16 header) return pd_header_msgid(le16_to_cpu(header)); } +static inline unsigned int pd_header_rev(u16 header) +{ + return (header >> PD_HEADER_REV_SHIFT) & PD_HEADER_REV_MASK; +} + +static inline unsigned int pd_header_rev_le(__le16 header) +{ + return pd_header_rev(le16_to_cpu(header)); +} + +#define PD_EXT_HDR_CHUNKED BIT(15) +#define PD_EXT_HDR_CHUNK_NUM_SHIFT 11 +#define PD_EXT_HDR_CHUNK_NUM_MASK 0xf +#define PD_EXT_HDR_REQ_CHUNK BIT(10) +#define PD_EXT_HDR_DATA_SIZE_SHIFT 0 +#define PD_EXT_HDR_DATA_SIZE_MASK 0x1ff + +#define PD_EXT_HDR(data_size, req_chunk, chunk_num, chunked) \ + ((((data_size) & PD_EXT_HDR_DATA_SIZE_MASK) << PD_EXT_HDR_DATA_SIZE_SHIFT) | \ + ((req_chunk) ? PD_EXT_HDR_REQ_CHUNK : 0) | \ + (((chunk_num) & PD_EXT_HDR_CHUNK_NUM_MASK) << PD_EXT_HDR_CHUNK_NUM_SHIFT) | \ + ((chunked) ? PD_EXT_HDR_CHUNKED : 0)) + +#define PD_EXT_HDR_LE(data_size, req_chunk, chunk_num, chunked) \ + cpu_to_le16(PD_EXT_HDR((data_size), (req_chunk), (chunk_num), (chunked))) + +static inline unsigned int pd_ext_header_chunk_num(u16 ext_header) +{ + return (ext_header >> PD_EXT_HDR_CHUNK_NUM_SHIFT) & + PD_EXT_HDR_CHUNK_NUM_MASK; +} + +static inline unsigned int pd_ext_header_data_size(u16 ext_header) +{ + return (ext_header >> PD_EXT_HDR_DATA_SIZE_SHIFT) & + PD_EXT_HDR_DATA_SIZE_MASK; +} + +static inline unsigned int pd_ext_header_data_size_le(__le16 ext_header) +{ + return pd_ext_header_data_size(le16_to_cpu(ext_header)); +} + #define PD_MAX_PAYLOAD 7 +#define PD_EXT_MAX_CHUNK_DATA 26 /** - * struct pd_message - PD message as seen on wire - * @header: PD message header - * @payload: PD message payload - */ + * struct pd_chunked_ext_message_data - PD chunked extended message data as + * seen on wire + * @header: PD extended message header + * @data: PD extended message data + */ +struct pd_chunked_ext_message_data { + __le16 header; + u8 data[PD_EXT_MAX_CHUNK_DATA]; +} __packed; + +/** + * struct pd_message - PD message as seen on wire + * @header: PD message header + * @payload: PD message payload + * @ext_msg: PD message chunked extended message data + */ struct pd_message { __le16 header; - __le32 payload[PD_MAX_PAYLOAD]; + union { + __le32 payload[PD_MAX_PAYLOAD]; + struct pd_chunked_ext_message_data ext_msg; + }; } __packed; /* PDO: Power Data Object */ @@ -121,6 +214,7 @@ enum pd_pdo_type { PDO_TYPE_FIXED = 0, PDO_TYPE_BATT = 1, PDO_TYPE_VAR = 2, + PDO_TYPE_APDO = 3, }; #define PDO_TYPE_SHIFT 30 @@ -174,6 +268,34 @@ enum pd_pdo_type { (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) +enum pd_apdo_type { + APDO_TYPE_PPS = 0, +}; + +#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ +#define PDO_APDO_TYPE_MASK 0x3 + +#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) + +#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ +#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ +#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ + +#define PDO_PPS_APDO_VOLT_MASK 0xff +#define PDO_PPS_APDO_CURR_MASK 0x7f + +#define PDO_PPS_APDO_MIN_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_CURR(ma) \ + ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) + +#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ + PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ + PDO_PPS_APDO_MAX_CURR(max_ma)) + static inline enum pd_pdo_type pdo_type(u32 pdo) { return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK; @@ -204,6 +326,29 @@ static inline unsigned int pdo_max_power(u32 pdo) return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250; } +static inline enum pd_apdo_type pdo_apdo_type(u32 pdo) +{ + return (pdo >> PDO_APDO_TYPE_SHIFT) & PDO_APDO_TYPE_MASK; +} + +static inline unsigned int pdo_pps_apdo_min_voltage(u32 pdo) +{ + return ((pdo >> PDO_PPS_APDO_MIN_VOLT_SHIFT) & + PDO_PPS_APDO_VOLT_MASK) * 100; +} + +static inline unsigned int pdo_pps_apdo_max_voltage(u32 pdo) +{ + return ((pdo >> PDO_PPS_APDO_MAX_VOLT_SHIFT) & + PDO_PPS_APDO_VOLT_MASK) * 100; +} + +static inline unsigned int pdo_pps_apdo_max_current(u32 pdo) +{ + return ((pdo >> PDO_PPS_APDO_MAX_CURR_SHIFT) & + PDO_PPS_APDO_CURR_MASK) * 50; +} + /* RDO: Request Data Object */ #define RDO_OBJ_POS_SHIFT 28 #define RDO_OBJ_POS_MASK 0x7 @@ -237,6 +382,24 @@ static inline unsigned int pdo_max_power(u32 pdo) (RDO_OBJ(idx) | (flags) | \ RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw)) +#define RDO_PROG_VOLT_MASK 0x7ff +#define RDO_PROG_CURR_MASK 0x7f + +#define RDO_PROG_VOLT_SHIFT 9 +#define RDO_PROG_CURR_SHIFT 0 + +#define RDO_PROG_VOLT_MV_STEP 20 +#define RDO_PROG_CURR_MA_STEP 50 + +#define PDO_PROG_OUT_VOLT(mv) \ + ((((mv) / RDO_PROG_VOLT_MV_STEP) & RDO_PROG_VOLT_MASK) << RDO_PROG_VOLT_SHIFT) +#define PDO_PROG_OP_CURR(ma) \ + ((((ma) / RDO_PROG_CURR_MA_STEP) & RDO_PROG_CURR_MASK) << RDO_PROG_CURR_SHIFT) + +#define RDO_PROG(idx, out_mv, op_ma, flags) \ + (RDO_OBJ(idx) | (flags) | \ + PDO_PROG_OUT_VOLT(out_mv) | PDO_PROG_OP_CURR(op_ma)) + static inline unsigned int rdo_index(u32 rdo) { return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK; -- cgit v1.2.3 From 456ebb4f221e98f507cc945690a670a79682c029 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 2 Jan 2018 15:50:50 +0000 Subject: typec: tcpm: Add ADO header for Alert message handling This commit adds a header providing definitions for handling Alert messages. Currently the header only focuses on handling incoming alerts. Signed-off-by: Adam Thomson Acked-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- include/linux/usb/pd_ado.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 include/linux/usb/pd_ado.h (limited to 'include/linux') diff --git a/include/linux/usb/pd_ado.h b/include/linux/usb/pd_ado.h new file mode 100644 index 000000000000..9aa1cf31c93c --- /dev/null +++ b/include/linux/usb/pd_ado.h @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 Dialog Semiconductor + * + * Author: Adam Thomson + */ + +#ifndef __LINUX_USB_PD_ADO_H +#define __LINUX_USB_PD_ADO_H + +/* ADO : Alert Data Object */ +#define USB_PD_ADO_TYPE_SHIFT 24 +#define USB_PD_ADO_TYPE_MASK 0xff +#define USB_PD_ADO_FIXED_BATT_SHIFT 20 +#define USB_PD_ADO_FIXED_BATT_MASK 0xf +#define USB_PD_ADO_HOT_SWAP_BATT_SHIFT 16 +#define USB_PD_ADO_HOT_SWAP_BATT_MASK 0xf + +#define USB_PD_ADO_TYPE_BATT_STATUS_CHANGE BIT(1) +#define USB_PD_ADO_TYPE_OCP BIT(2) +#define USB_PD_ADO_TYPE_OTP BIT(3) +#define USB_PD_ADO_TYPE_OP_COND_CHANGE BIT(4) +#define USB_PD_ADO_TYPE_SRC_INPUT_CHANGE BIT(5) +#define USB_PD_ADO_TYPE_OVP BIT(6) + +static inline unsigned int usb_pd_ado_type(u32 ado) +{ + return (ado >> USB_PD_ADO_TYPE_SHIFT) & USB_PD_ADO_TYPE_MASK; +} + +static inline unsigned int usb_pd_ado_fixed_batt(u32 ado) +{ + return (ado >> USB_PD_ADO_FIXED_BATT_SHIFT) & + USB_PD_ADO_FIXED_BATT_MASK; +} + +static inline unsigned int usb_pd_ado_hot_swap_batt(u32 ado) +{ + return (ado >> USB_PD_ADO_HOT_SWAP_BATT_SHIFT) & + USB_PD_ADO_HOT_SWAP_BATT_MASK; +} +#endif /* __LINUX_USB_PD_ADO_H */ -- cgit v1.2.3 From 02cad961cae556357e4a63b11f849e80418c1ffc Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 2 Jan 2018 15:50:51 +0000 Subject: typec: tcpm: Add SDB header for Status message handling This commit adds a header providing definitions for handling Status messages. Currently the header only focuses on handling incoming Status messages. Signed-off-by: Adam Thomson Acked-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- include/linux/usb/pd_ext_sdb.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 include/linux/usb/pd_ext_sdb.h (limited to 'include/linux') diff --git a/include/linux/usb/pd_ext_sdb.h b/include/linux/usb/pd_ext_sdb.h new file mode 100644 index 000000000000..0eb83ce19597 --- /dev/null +++ b/include/linux/usb/pd_ext_sdb.h @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 Dialog Semiconductor + * + * Author: Adam Thomson + */ + +#ifndef __LINUX_USB_PD_EXT_SDB_H +#define __LINUX_USB_PD_EXT_SDB_H + +/* SDB : Status Data Block */ +enum usb_pd_ext_sdb_fields { + USB_PD_EXT_SDB_INTERNAL_TEMP = 0, + USB_PD_EXT_SDB_PRESENT_INPUT, + USB_PD_EXT_SDB_PRESENT_BATT_INPUT, + USB_PD_EXT_SDB_EVENT_FLAGS, + USB_PD_EXT_SDB_TEMP_STATUS, + USB_PD_EXT_SDB_DATA_SIZE, +}; + +/* Event Flags */ +#define USB_PD_EXT_SDB_EVENT_OCP BIT(1) +#define USB_PD_EXT_SDB_EVENT_OTP BIT(2) +#define USB_PD_EXT_SDB_EVENT_OVP BIT(3) +#define USB_PD_EXT_SDB_EVENT_CF_CV_MODE BIT(4) + +#define USB_PD_EXT_SDB_PPS_EVENTS (USB_PD_EXT_SDB_EVENT_OCP | \ + USB_PD_EXT_SDB_EVENT_OTP | \ + USB_PD_EXT_SDB_EVENT_OVP) + +#endif /* __LINUX_USB_PD_EXT_SDB_H */ -- cgit v1.2.3 From 4e88d4c083016454f179686529ae65d70b933b58 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 3 Mar 2018 22:43:03 +0100 Subject: usb: add a flag to skip PHY initialization to struct usb_hcd The USB HCD core driver parses the device-tree node for "phys" and "usb-phys" properties. It also manages the power state of these PHYs automatically. However, drivers may opt-out of this behavior by setting "phy" or "usb_phy" in struct usb_hcd to a non-null value. An example where this is required is the "Qualcomm USB2 controller", implemented by the chipidea driver. The hardware requires that the PHY is only powered on after the "reset completed" event from the controller is received. A follow-up patch will allow the USB HCD core driver to manage more than one PHY. Add a new "skip_phy_initialization" bitflag to struct usb_hcd so drivers can opt-out of any PHY management provided by the USB HCD core driver. This also updates the existing drivers so they use the new flag if they want to opt out of the PHY management provided by the USB HCD core driver. This means that for these drivers the new "multiple PHY" handling (which will be added in a follow-up patch) will be disabled as well. Signed-off-by: Martin Blumenstingl Acked-by: Peter Chen Tested-by: Neil Armstrong Signed-off-by: Greg Kroah-Hartman --- drivers/usb/chipidea/host.c | 6 ++---- drivers/usb/core/hcd.c | 4 ++-- drivers/usb/host/ehci-fsl.c | 2 ++ drivers/usb/host/ehci-platform.c | 4 ++-- drivers/usb/host/ehci-tegra.c | 1 + drivers/usb/host/ohci-omap.c | 1 + drivers/usb/host/ohci-platform.c | 4 ++-- drivers/usb/host/xhci-plat.c | 1 + include/linux/usb/hcd.h | 6 ++++++ 9 files changed, 19 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c index 19d60ed7e41f..af45aa3222b5 100644 --- a/drivers/usb/chipidea/host.c +++ b/drivers/usb/chipidea/host.c @@ -124,10 +124,8 @@ static int host_start(struct ci_hdrc *ci) hcd->power_budget = ci->platdata->power_budget; hcd->tpl_support = ci->platdata->tpl_support; - if (ci->phy) - hcd->phy = ci->phy; - else - hcd->usb_phy = ci->usb_phy; + if (ci->phy || ci->usb_phy) + hcd->skip_phy_initialization = 1; ehci = hcd_to_ehci(hcd); ehci->caps = ci->hw_bank.cap; diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c index fc32391a34d5..f2307470a31e 100644 --- a/drivers/usb/core/hcd.c +++ b/drivers/usb/core/hcd.c @@ -2727,7 +2727,7 @@ int usb_add_hcd(struct usb_hcd *hcd, int retval; struct usb_device *rhdev; - if (IS_ENABLED(CONFIG_USB_PHY) && !hcd->usb_phy) { + if (IS_ENABLED(CONFIG_USB_PHY) && !hcd->skip_phy_initialization) { struct usb_phy *phy = usb_get_phy_dev(hcd->self.sysdev, 0); if (IS_ERR(phy)) { @@ -2745,7 +2745,7 @@ int usb_add_hcd(struct usb_hcd *hcd, } } - if (IS_ENABLED(CONFIG_GENERIC_PHY) && !hcd->phy) { + if (IS_ENABLED(CONFIG_GENERIC_PHY) && !hcd->skip_phy_initialization) { struct phy *phy = phy_get(hcd->self.sysdev, "usb"); if (IS_ERR(phy)) { diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index c5094cb88cd5..0a9fd2022acf 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -155,6 +155,8 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) retval = -ENODEV; goto err2; } + + hcd->skip_phy_initialization = 1; } #endif return retval; diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c index b065a960adc2..b91eea8c73ae 100644 --- a/drivers/usb/host/ehci-platform.c +++ b/drivers/usb/host/ehci-platform.c @@ -219,9 +219,9 @@ static int ehci_platform_probe(struct platform_device *dev) if (IS_ERR(priv->phys[phy_num])) { err = PTR_ERR(priv->phys[phy_num]); goto err_put_hcd; - } else if (!hcd->phy) { + } else { /* Avoiding phy_get() in usb_add_hcd() */ - hcd->phy = priv->phys[phy_num]; + hcd->skip_phy_initialization = 1; } } diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index c809f7d2f08f..a6f4389f7e88 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -461,6 +461,7 @@ static int tegra_ehci_probe(struct platform_device *pdev) goto cleanup_clk_en; } hcd->usb_phy = u_phy; + hcd->skip_phy_initialization = 1; tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node, "nvidia,needs-double-reset"); diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index 0201c49bc4fc..d8d35d456456 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -230,6 +230,7 @@ static int ohci_omap_reset(struct usb_hcd *hcd) } else { return -EPROBE_DEFER; } + hcd->skip_phy_initialization = 1; ohci->start_hnp = start_hnp; } #endif diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c index 1e6c954f4b3f..62ef36a9333f 100644 --- a/drivers/usb/host/ohci-platform.c +++ b/drivers/usb/host/ohci-platform.c @@ -186,9 +186,9 @@ static int ohci_platform_probe(struct platform_device *dev) if (IS_ERR(priv->phys[phy_num])) { err = PTR_ERR(priv->phys[phy_num]); goto err_put_hcd; - } else if (!hcd->phy) { + } else { /* Avoiding phy_get() in usb_add_hcd() */ - hcd->phy = priv->phys[phy_num]; + hcd->skip_phy_initialization = 1; } } diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index 6f038306c14d..6700e5ee82ad 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -284,6 +284,7 @@ static int xhci_plat_probe(struct platform_device *pdev) ret = usb_phy_init(hcd->usb_phy); if (ret) goto put_usb3_hcd; + hcd->skip_phy_initialization = 1; } ret = usb_add_hcd(hcd, irq, IRQF_SHARED); diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index 176900528822..693502c84c04 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -151,6 +151,12 @@ struct usb_hcd { unsigned msix_enabled:1; /* driver has MSI-X enabled? */ unsigned msi_enabled:1; /* driver has MSI enabled? */ unsigned remove_phy:1; /* auto-remove USB phy */ + /* + * do not manage the PHY state in the HCD core, instead let the driver + * handle this (for example if the PHY can only be turned on after a + * specific event) + */ + unsigned skip_phy_initialization:1; /* The next flag is a stopgap, to be removed when all the HCDs * support the new root-hub polling mechanism. */ -- cgit v1.2.3 From 178a0bce05cbc17a27f9cba78258c5d12adc980c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 3 Mar 2018 22:43:05 +0100 Subject: usb: core: hcd: integrate the PHY wrapper into the HCD core This integrates the PHY wrapper into the core hcd infrastructure. Multiple PHYs which are part of the HCD's device tree node are now managed (= powered on/off when needed), by the new usb_phy_roothub code. Suspend and resume is also supported, however not for runtime/auto-suspend (which is triggered for example when no devices are connected to the USB bus). This is needed on some SoCs (for example Amlogic Meson GXL) because if the PHYs are disabled during auto-suspend then devices which are plugged in afterwards are not seen by the host. One example where this is required is the Amlogic GXL and GXM SoCs: They are using a dwc3 USB controller with up to three ports enabled on the internal roothub. Each port has it's own PHY which must be enabled (if one of the PHYs is left disabled then none of the USB ports works at all). The new logic works on the Amlogic GXL and GXM SoCs because the dwc3 driver internally creates a xhci-hcd which then registers a HCD which then triggers our new PHY wrapper. USB controller drivers can opt out of this by setting "skip_phy_initialization" in struct usb_hcd to true. This is identical to how it works for a single USB PHY, so the "multiple PHY" handling is disabled for drivers that opted out of the management logic of a single PHY. Signed-off-by: Martin Blumenstingl Acked-by: Alan Stern Acked-by: Chunfeng Yun Tested-by: Yixun Lan Tested-by: Neil Armstrong Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/hcd.c | 31 +++++++++++++++++++++++++++++++ include/linux/usb/hcd.h | 1 + 2 files changed, 32 insertions(+) (limited to 'include/linux') diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c index f2307470a31e..32797c25ac3b 100644 --- a/drivers/usb/core/hcd.c +++ b/drivers/usb/core/hcd.c @@ -37,6 +37,7 @@ #include #include "usb.h" +#include "phy.h" /*-------------------------------------------------------------------------*/ @@ -2260,6 +2261,9 @@ int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg) usb_set_device_state(rhdev, USB_STATE_SUSPENDED); hcd->state = HC_STATE_SUSPENDED; + if (!PMSG_IS_AUTO(msg)) + usb_phy_roothub_power_off(hcd->phy_roothub); + /* Did we race with a root-hub wakeup event? */ if (rhdev->do_remote_wakeup) { char buffer[6]; @@ -2296,6 +2300,13 @@ int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg) dev_dbg(&rhdev->dev, "skipped %s of dead bus\n", "resume"); return 0; } + + if (!PMSG_IS_AUTO(msg)) { + status = usb_phy_roothub_power_on(hcd->phy_roothub); + if (status) + return status; + } + if (!hcd->driver->bus_resume) return -ENOENT; if (HCD_RH_RUNNING(hcd)) @@ -2333,6 +2344,7 @@ int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg) } } else { hcd->state = old_state; + usb_phy_roothub_power_off(hcd->phy_roothub); dev_dbg(&rhdev->dev, "bus %s fail, err %d\n", "resume", status); if (status != -ESHUTDOWN) @@ -2769,6 +2781,18 @@ int usb_add_hcd(struct usb_hcd *hcd, } } + if (!hcd->skip_phy_initialization) { + hcd->phy_roothub = usb_phy_roothub_init(hcd->self.sysdev); + if (IS_ERR(hcd->phy_roothub)) { + retval = PTR_ERR(hcd->phy_roothub); + goto err_phy_roothub_init; + } + + retval = usb_phy_roothub_power_on(hcd->phy_roothub); + if (retval) + goto err_usb_phy_roothub_power_on; + } + dev_info(hcd->self.controller, "%s\n", hcd->product_desc); /* Keep old behaviour if authorized_default is not in [0, 1]. */ @@ -2933,6 +2957,10 @@ err_allocate_root_hub: err_register_bus: hcd_buffer_destroy(hcd); err_create_buf: + usb_phy_roothub_power_off(hcd->phy_roothub); +err_usb_phy_roothub_power_on: + usb_phy_roothub_exit(hcd->phy_roothub); +err_phy_roothub_init: if (IS_ENABLED(CONFIG_GENERIC_PHY) && hcd->remove_phy && hcd->phy) { phy_power_off(hcd->phy); phy_exit(hcd->phy); @@ -3017,6 +3045,9 @@ void usb_remove_hcd(struct usb_hcd *hcd) usb_deregister_bus(&hcd->self); hcd_buffer_destroy(hcd); + usb_phy_roothub_power_off(hcd->phy_roothub); + usb_phy_roothub_exit(hcd->phy_roothub); + if (IS_ENABLED(CONFIG_GENERIC_PHY) && hcd->remove_phy && hcd->phy) { phy_power_off(hcd->phy); phy_exit(hcd->phy); diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index 693502c84c04..a042675e03ba 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -104,6 +104,7 @@ struct usb_hcd { */ struct usb_phy *usb_phy; struct phy *phy; + struct usb_phy_roothub *phy_roothub; /* Flags that need to be manipulated atomically because they can * change while the host controller is running. Always use -- cgit v1.2.3 From ad70f937e9d0bdc580e390db3a047f9e58863b6e Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 3 Mar 2018 22:43:09 +0100 Subject: usb: core: hcd: remove support for initializing a single PHY With the new PHY wrapper in place we can now handle multiple PHYs. Remove the code which handles only one generic PHY as this is now covered (with support for multiple PHYs as well as suspend/resume support) by the new PHY wrapper. Signed-off-by: Martin Blumenstingl Tested-by: Neil Armstrong Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/hcd.c | 37 ------------------------------------- include/linux/usb/hcd.h | 1 - 2 files changed, 38 deletions(-) (limited to 'include/linux') diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c index 32797c25ac3b..5a92d8f7c484 100644 --- a/drivers/usb/core/hcd.c +++ b/drivers/usb/core/hcd.c @@ -2757,30 +2757,6 @@ int usb_add_hcd(struct usb_hcd *hcd, } } - if (IS_ENABLED(CONFIG_GENERIC_PHY) && !hcd->skip_phy_initialization) { - struct phy *phy = phy_get(hcd->self.sysdev, "usb"); - - if (IS_ERR(phy)) { - retval = PTR_ERR(phy); - if (retval == -EPROBE_DEFER) - goto err_phy; - } else { - retval = phy_init(phy); - if (retval) { - phy_put(phy); - goto err_phy; - } - retval = phy_power_on(phy); - if (retval) { - phy_exit(phy); - phy_put(phy); - goto err_phy; - } - hcd->phy = phy; - hcd->remove_phy = 1; - } - } - if (!hcd->skip_phy_initialization) { hcd->phy_roothub = usb_phy_roothub_init(hcd->self.sysdev); if (IS_ERR(hcd->phy_roothub)) { @@ -2961,13 +2937,6 @@ err_create_buf: err_usb_phy_roothub_power_on: usb_phy_roothub_exit(hcd->phy_roothub); err_phy_roothub_init: - if (IS_ENABLED(CONFIG_GENERIC_PHY) && hcd->remove_phy && hcd->phy) { - phy_power_off(hcd->phy); - phy_exit(hcd->phy); - phy_put(hcd->phy); - hcd->phy = NULL; - } -err_phy: if (hcd->remove_phy && hcd->usb_phy) { usb_phy_shutdown(hcd->usb_phy); usb_put_phy(hcd->usb_phy); @@ -3048,12 +3017,6 @@ void usb_remove_hcd(struct usb_hcd *hcd) usb_phy_roothub_power_off(hcd->phy_roothub); usb_phy_roothub_exit(hcd->phy_roothub); - if (IS_ENABLED(CONFIG_GENERIC_PHY) && hcd->remove_phy && hcd->phy) { - phy_power_off(hcd->phy); - phy_exit(hcd->phy); - phy_put(hcd->phy); - hcd->phy = NULL; - } if (hcd->remove_phy && hcd->usb_phy) { usb_phy_shutdown(hcd->usb_phy); usb_put_phy(hcd->usb_phy); diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index a042675e03ba..aef50cb2ed1b 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -103,7 +103,6 @@ struct usb_hcd { * other external phys should be software-transparent */ struct usb_phy *usb_phy; - struct phy *phy; struct usb_phy_roothub *phy_roothub; /* Flags that need to be manipulated atomically because they can -- cgit v1.2.3 From f5426250a6ecfd1e9b2d5e0daf07565f664aa67d Mon Sep 17 00:00:00 2001 From: Paolo Abeni Date: Fri, 9 Mar 2018 10:39:24 +0100 Subject: net: introduce IFF_NO_RX_HANDLER Some network devices - notably ipvlan slave - are not compatible with any kind of rx_handler. Currently the hook can be installed but any configuration (bridge, bond, macsec, ...) is nonfunctional. This change allocates a priv_flag bit to mark such devices and explicitly forbid installing a rx_handler if such bit is set. The new bit is used by ipvlan slave device. Signed-off-by: Paolo Abeni Signed-off-by: David S. Miller --- drivers/net/ipvlan/ipvlan_main.c | 2 ++ include/linux/netdevice.h | 3 +++ net/core/dev.c | 3 +++ 3 files changed, 8 insertions(+) (limited to 'include/linux') diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c index 23fd5ab180e8..743d37fb034a 100644 --- a/drivers/net/ipvlan/ipvlan_main.c +++ b/drivers/net/ipvlan/ipvlan_main.c @@ -604,6 +604,8 @@ int ipvlan_link_new(struct net *src_net, struct net_device *dev, */ memcpy(dev->dev_addr, phy_dev->dev_addr, ETH_ALEN); + dev->priv_flags |= IFF_NO_RX_HANDLER; + err = register_netdevice(dev); if (err < 0) return err; diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 9711108c3916..5fbb9f1da7fd 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1397,6 +1397,7 @@ struct net_device_ops { * @IFF_PHONY_HEADROOM: the headroom value is controlled by an external * entity (i.e. the master device for bridged veth) * @IFF_MACSEC: device is a MACsec device + * @IFF_NO_RX_HANDLER: device doesn't support the rx_handler hook */ enum netdev_priv_flags { IFF_802_1Q_VLAN = 1<<0, @@ -1425,6 +1426,7 @@ enum netdev_priv_flags { IFF_RXFH_CONFIGURED = 1<<23, IFF_PHONY_HEADROOM = 1<<24, IFF_MACSEC = 1<<25, + IFF_NO_RX_HANDLER = 1<<26, }; #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN @@ -1452,6 +1454,7 @@ enum netdev_priv_flags { #define IFF_TEAM IFF_TEAM #define IFF_RXFH_CONFIGURED IFF_RXFH_CONFIGURED #define IFF_MACSEC IFF_MACSEC +#define IFF_NO_RX_HANDLER IFF_NO_RX_HANDLER /** * struct net_device - The DEVICE structure. diff --git a/net/core/dev.c b/net/core/dev.c index e5b8d42b6410..259abb1515d0 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -4351,6 +4351,9 @@ int netdev_rx_handler_register(struct net_device *dev, if (netdev_is_rx_handler_busy(dev)) return -EBUSY; + if (dev->priv_flags & IFF_NO_RX_HANDLER) + return -EINVAL; + /* Note: rx_handler_data must be set before rx_handler */ rcu_assign_pointer(dev->rx_handler_data, rx_handler_data); rcu_assign_pointer(dev->rx_handler, rx_handler); -- cgit v1.2.3 From 739d875dd6982618020d30f58f8acf10f6076e6d Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 8 Mar 2018 09:48:46 +0000 Subject: mn10300: Remove the architecture Remove the MN10300 arch as the hardware is defunct. Suggested-by: Arnd Bergmann Signed-off-by: David Howells cc: Masahiro Yamada cc: linux-am33-list@redhat.com Signed-off-by: Arnd Bergmann --- Documentation/00-INDEX | 2 - .../features/core/BPF-JIT/arch-support.txt | 1 - .../core/generic-idle-thread/arch-support.txt | 1 - .../features/core/jump-labels/arch-support.txt | 1 - .../features/core/tracehook/arch-support.txt | 1 - .../features/debug/KASAN/arch-support.txt | 1 - .../debug/gcov-profile-all/arch-support.txt | 1 - Documentation/features/debug/kgdb/arch-support.txt | 1 - .../debug/kprobes-on-ftrace/arch-support.txt | 1 - .../features/debug/kprobes/arch-support.txt | 1 - .../features/debug/kretprobes/arch-support.txt | 1 - .../features/debug/optprobes/arch-support.txt | 1 - .../features/debug/stackprotector/arch-support.txt | 1 - .../features/debug/uprobes/arch-support.txt | 1 - .../debug/user-ret-profiler/arch-support.txt | 1 - .../features/io/dma-api-debug/arch-support.txt | 1 - .../features/io/dma-contiguous/arch-support.txt | 1 - .../features/io/sg-chain/arch-support.txt | 1 - .../features/lib/strncasecmp/arch-support.txt | 1 - .../locking/cmpxchg-local/arch-support.txt | 1 - .../features/locking/lockdep/arch-support.txt | 1 - .../locking/queued-rwlocks/arch-support.txt | 1 - .../locking/queued-spinlocks/arch-support.txt | 1 - .../locking/rwsem-optimized/arch-support.txt | 1 - .../features/perf/kprobes-event/arch-support.txt | 1 - .../features/perf/perf-regs/arch-support.txt | 1 - .../features/perf/perf-stackdump/arch-support.txt | 1 - .../sched/membarrier-sync-core/arch-support.txt | 1 - .../features/sched/numa-balancing/arch-support.txt | 1 - .../seccomp/seccomp-filter/arch-support.txt | 1 - .../time/arch-tick-broadcast/arch-support.txt | 1 - .../features/time/clockevents/arch-support.txt | 1 - .../time/context-tracking/arch-support.txt | 1 - .../features/time/irq-time-acct/arch-support.txt | 1 - .../time/modern-timekeeping/arch-support.txt | 1 - .../features/time/virt-cpuacct/arch-support.txt | 1 - .../features/vm/ELF-ASLR/arch-support.txt | 1 - .../features/vm/PG_uncached/arch-support.txt | 1 - Documentation/features/vm/THP/arch-support.txt | 1 - Documentation/features/vm/TLB/arch-support.txt | 1 - .../features/vm/huge-vmap/arch-support.txt | 1 - .../features/vm/ioremap_prot/arch-support.txt | 1 - .../features/vm/numa-memblock/arch-support.txt | 1 - .../features/vm/pte_special/arch-support.txt | 1 - Documentation/mn10300/ABI.txt | 149 -- Documentation/mn10300/compartmentalisation.txt | 60 - MAINTAINERS | 8 - arch/mn10300/Kconfig | 499 ----- arch/mn10300/Kconfig.debug | 156 -- arch/mn10300/Makefile | 99 - arch/mn10300/boot/.gitignore | 1 - arch/mn10300/boot/Makefile | 28 - arch/mn10300/boot/compressed/Makefile | 22 - arch/mn10300/boot/compressed/head.S | 151 -- arch/mn10300/boot/compressed/misc.c | 393 ---- arch/mn10300/boot/compressed/misc.h | 18 - arch/mn10300/boot/compressed/vmlinux.lds | 9 - arch/mn10300/boot/install.sh | 67 - arch/mn10300/boot/tools/build.c | 191 -- arch/mn10300/configs/asb2303_defconfig | 67 - arch/mn10300/configs/asb2364_defconfig | 87 - arch/mn10300/include/asm/Kbuild | 13 - arch/mn10300/include/asm/asm-offsets.h | 1 - arch/mn10300/include/asm/atomic.h | 161 -- arch/mn10300/include/asm/bitops.h | 232 --- arch/mn10300/include/asm/bug.h | 37 - arch/mn10300/include/asm/bugs.h | 20 - arch/mn10300/include/asm/busctl-regs.h | 151 -- arch/mn10300/include/asm/cache.h | 60 - arch/mn10300/include/asm/cacheflush.h | 164 -- arch/mn10300/include/asm/checksum.h | 79 - arch/mn10300/include/asm/cmpxchg.h | 115 -- arch/mn10300/include/asm/cpu-regs.h | 353 ---- arch/mn10300/include/asm/current.h | 37 - arch/mn10300/include/asm/debugger.h | 43 - arch/mn10300/include/asm/delay.h | 19 - arch/mn10300/include/asm/div64.h | 115 -- arch/mn10300/include/asm/dma-mapping.h | 21 - arch/mn10300/include/asm/dma.h | 117 -- arch/mn10300/include/asm/dmactl-regs.h | 16 - arch/mn10300/include/asm/elf.h | 153 -- arch/mn10300/include/asm/emergency-restart.h | 1 - arch/mn10300/include/asm/exceptions.h | 121 -- arch/mn10300/include/asm/fpu.h | 132 -- arch/mn10300/include/asm/frame.inc | 97 - arch/mn10300/include/asm/ftrace.h | 1 - arch/mn10300/include/asm/futex.h | 1 - arch/mn10300/include/asm/gdb-stub.h | 182 -- arch/mn10300/include/asm/hardirq.h | 49 - arch/mn10300/include/asm/highmem.h | 131 -- arch/mn10300/include/asm/hw_irq.h | 14 - arch/mn10300/include/asm/intctl-regs.h | 71 - arch/mn10300/include/asm/io.h | 325 ---- arch/mn10300/include/asm/irq.h | 40 - arch/mn10300/include/asm/irq_regs.h | 28 - arch/mn10300/include/asm/irqflags.h | 215 --- arch/mn10300/include/asm/kdebug.h | 22 - arch/mn10300/include/asm/kgdb.h | 81 - arch/mn10300/include/asm/kmap_types.h | 7 - arch/mn10300/include/asm/kprobes.h | 55 - arch/mn10300/include/asm/linkage.h | 20 - arch/mn10300/include/asm/local.h | 1 - arch/mn10300/include/asm/local64.h | 1 - arch/mn10300/include/asm/mc146818rtc.h | 1 - arch/mn10300/include/asm/mmu.h | 20 - arch/mn10300/include/asm/mmu_context.h | 163 -- arch/mn10300/include/asm/module.h | 22 - arch/mn10300/include/asm/nmi.h | 16 - arch/mn10300/include/asm/page.h | 130 -- arch/mn10300/include/asm/page_offset.h | 12 - arch/mn10300/include/asm/pci.h | 84 - arch/mn10300/include/asm/percpu.h | 1 - arch/mn10300/include/asm/pgalloc.h | 56 - arch/mn10300/include/asm/pgtable.h | 494 ----- arch/mn10300/include/asm/pio-regs.h | 233 --- arch/mn10300/include/asm/processor.h | 171 -- arch/mn10300/include/asm/ptrace.h | 26 - arch/mn10300/include/asm/reset-regs.h | 60 - arch/mn10300/include/asm/rtc-regs.h | 86 - arch/mn10300/include/asm/rtc.h | 28 - arch/mn10300/include/asm/rwlock.h | 125 -- arch/mn10300/include/asm/serial-regs.h | 191 -- arch/mn10300/include/asm/serial.h | 36 - arch/mn10300/include/asm/setup.h | 18 - arch/mn10300/include/asm/shmparam.h | 7 - arch/mn10300/include/asm/signal.h | 33 - arch/mn10300/include/asm/smp.h | 109 -- arch/mn10300/include/asm/smsc911x.h | 1 - arch/mn10300/include/asm/spinlock.h | 180 -- arch/mn10300/include/asm/spinlock_types.h | 21 - arch/mn10300/include/asm/string.h | 32 - arch/mn10300/include/asm/switch_to.h | 49 - arch/mn10300/include/asm/syscall.h | 117 -- arch/mn10300/include/asm/termios.h | 14 - arch/mn10300/include/asm/thread_info.h | 160 -- arch/mn10300/include/asm/timer-regs.h | 452 ----- arch/mn10300/include/asm/timex.h | 34 - arch/mn10300/include/asm/tlb.h | 34 - arch/mn10300/include/asm/tlbflush.h | 154 -- arch/mn10300/include/asm/topology.h | 1 - arch/mn10300/include/asm/types.h | 22 - arch/mn10300/include/asm/uaccess.h | 297 --- arch/mn10300/include/asm/ucontext.h | 22 - arch/mn10300/include/asm/unaligned.h | 20 - arch/mn10300/include/asm/unistd.h | 47 - arch/mn10300/include/asm/user.h | 53 - arch/mn10300/include/asm/vga.h | 17 - arch/mn10300/include/asm/xor.h | 1 - arch/mn10300/include/uapi/asm/Kbuild | 6 - arch/mn10300/include/uapi/asm/auxvec.h | 4 - arch/mn10300/include/uapi/asm/bitsperlong.h | 2 - arch/mn10300/include/uapi/asm/byteorder.h | 7 - arch/mn10300/include/uapi/asm/errno.h | 2 - arch/mn10300/include/uapi/asm/fcntl.h | 2 - arch/mn10300/include/uapi/asm/ioctl.h | 2 - arch/mn10300/include/uapi/asm/ioctls.h | 7 - arch/mn10300/include/uapi/asm/ipcbuf.h | 2 - arch/mn10300/include/uapi/asm/kvm_para.h | 2 - arch/mn10300/include/uapi/asm/mman.h | 7 - arch/mn10300/include/uapi/asm/msgbuf.h | 32 - arch/mn10300/include/uapi/asm/param.h | 19 - arch/mn10300/include/uapi/asm/posix_types.h | 46 - arch/mn10300/include/uapi/asm/ptrace.h | 85 - arch/mn10300/include/uapi/asm/resource.h | 2 - arch/mn10300/include/uapi/asm/sembuf.h | 26 - arch/mn10300/include/uapi/asm/setup.h | 5 - arch/mn10300/include/uapi/asm/shmbuf.h | 43 - arch/mn10300/include/uapi/asm/sigcontext.h | 53 - arch/mn10300/include/uapi/asm/signal.h | 126 -- arch/mn10300/include/uapi/asm/socket.h | 108 -- arch/mn10300/include/uapi/asm/sockios.h | 14 - arch/mn10300/include/uapi/asm/stat.h | 79 - arch/mn10300/include/uapi/asm/statfs.h | 1 - arch/mn10300/include/uapi/asm/swab.h | 43 - arch/mn10300/include/uapi/asm/termbits.h | 202 -- arch/mn10300/include/uapi/asm/termios.h | 84 - arch/mn10300/include/uapi/asm/types.h | 12 - arch/mn10300/include/uapi/asm/unistd.h | 355 ---- arch/mn10300/kernel/Makefile | 29 - arch/mn10300/kernel/asm-offsets.c | 108 -- arch/mn10300/kernel/cevt-mn10300.c | 137 -- arch/mn10300/kernel/csrc-mn10300.c | 34 - arch/mn10300/kernel/entry.S | 772 -------- arch/mn10300/kernel/fpu-low.S | 258 --- arch/mn10300/kernel/fpu-nofpu-low.S | 39 - arch/mn10300/kernel/fpu-nofpu.c | 31 - arch/mn10300/kernel/fpu.c | 177 -- arch/mn10300/kernel/gdb-io-serial-low.S | 91 - arch/mn10300/kernel/gdb-io-serial.c | 174 -- arch/mn10300/kernel/gdb-io-ttysm-low.S | 93 - arch/mn10300/kernel/gdb-io-ttysm.c | 303 --- arch/mn10300/kernel/gdb-low.S | 115 -- arch/mn10300/kernel/gdb-stub.c | 1924 -------------------- arch/mn10300/kernel/head.S | 442 ----- arch/mn10300/kernel/internal.h | 40 - arch/mn10300/kernel/io.c | 30 - arch/mn10300/kernel/irq.c | 356 ---- arch/mn10300/kernel/kgdb.c | 502 ----- arch/mn10300/kernel/kprobes.c | 656 ------- arch/mn10300/kernel/mn10300-debug.c | 58 - arch/mn10300/kernel/mn10300-serial-low.S | 194 -- arch/mn10300/kernel/mn10300-serial.c | 1790 ------------------ arch/mn10300/kernel/mn10300-serial.h | 130 -- arch/mn10300/kernel/mn10300-watchdog-low.S | 66 - arch/mn10300/kernel/mn10300-watchdog.c | 205 --- arch/mn10300/kernel/mn10300_ksyms.c | 39 - arch/mn10300/kernel/module.c | 156 -- arch/mn10300/kernel/process.c | 175 -- arch/mn10300/kernel/profile-low.S | 72 - arch/mn10300/kernel/profile.c | 51 - arch/mn10300/kernel/ptrace.c | 386 ---- arch/mn10300/kernel/rtc.c | 46 - arch/mn10300/kernel/setup.c | 283 --- arch/mn10300/kernel/sigframe.h | 33 - arch/mn10300/kernel/signal.c | 431 ----- arch/mn10300/kernel/smp-low.S | 97 - arch/mn10300/kernel/smp.c | 1186 ------------ arch/mn10300/kernel/switch_to.S | 179 -- arch/mn10300/kernel/sys_mn10300.c | 33 - arch/mn10300/kernel/time.c | 125 -- arch/mn10300/kernel/traps.c | 615 ------- arch/mn10300/kernel/vmlinux.lds.S | 94 - arch/mn10300/lib/Makefile | 7 - arch/mn10300/lib/__ashldi3.S | 51 - arch/mn10300/lib/__ashrdi3.S | 52 - arch/mn10300/lib/__lshrdi3.S | 52 - arch/mn10300/lib/__ucmpdi2.S | 43 - arch/mn10300/lib/ashrdi3.c | 61 - arch/mn10300/lib/bitops.c | 50 - arch/mn10300/lib/checksum.c | 100 - arch/mn10300/lib/delay.c | 51 - arch/mn10300/lib/do_csum.S | 157 -- arch/mn10300/lib/internal.h | 15 - arch/mn10300/lib/lshrdi3.c | 60 - arch/mn10300/lib/memcpy.S | 135 -- arch/mn10300/lib/memmove.S | 160 -- arch/mn10300/lib/memset.S | 121 -- arch/mn10300/lib/negdi2.c | 57 - arch/mn10300/lib/usercopy.c | 142 -- arch/mn10300/mm/Kconfig.cache | 148 -- arch/mn10300/mm/Makefile | 32 - arch/mn10300/mm/cache-dbg-flush-by-reg.S | 160 -- arch/mn10300/mm/cache-dbg-flush-by-tag.S | 114 -- arch/mn10300/mm/cache-dbg-inv-by-reg.S | 69 - arch/mn10300/mm/cache-dbg-inv-by-tag.S | 120 -- arch/mn10300/mm/cache-dbg-inv.S | 47 - arch/mn10300/mm/cache-disabled.c | 21 - arch/mn10300/mm/cache-flush-by-reg.S | 308 ---- arch/mn10300/mm/cache-flush-by-tag.S | 250 --- arch/mn10300/mm/cache-flush-icache.c | 155 -- arch/mn10300/mm/cache-inv-by-reg.S | 350 ---- arch/mn10300/mm/cache-inv-by-tag.S | 276 --- arch/mn10300/mm/cache-inv-icache.c | 129 -- arch/mn10300/mm/cache-smp-flush.c | 156 -- arch/mn10300/mm/cache-smp-inv.c | 153 -- arch/mn10300/mm/cache-smp.c | 105 -- arch/mn10300/mm/cache-smp.h | 69 - arch/mn10300/mm/cache.c | 54 - arch/mn10300/mm/cache.inc | 133 -- arch/mn10300/mm/dma-alloc.c | 128 -- arch/mn10300/mm/extable.c | 26 - arch/mn10300/mm/fault.c | 414 ----- arch/mn10300/mm/init.c | 136 -- arch/mn10300/mm/misalignment.c | 966 ---------- arch/mn10300/mm/mmu-context.c | 62 - arch/mn10300/mm/pgtable.c | 174 -- arch/mn10300/mm/tlb-mn10300.S | 220 --- arch/mn10300/mm/tlb-smp.c | 213 --- arch/mn10300/oprofile/Makefile | 14 - arch/mn10300/oprofile/op_model_null.c | 22 - arch/mn10300/proc-mn103e010/Makefile | 5 - arch/mn10300/proc-mn103e010/include/proc/cache.h | 43 - arch/mn10300/proc-mn103e010/include/proc/clock.h | 16 - .../proc-mn103e010/include/proc/dmactl-regs.h | 102 -- .../proc-mn103e010/include/proc/intctl-regs.h | 30 - arch/mn10300/proc-mn103e010/include/proc/irq.h | 34 - arch/mn10300/proc-mn103e010/include/proc/proc.h | 18 - arch/mn10300/proc-mn103e010/proc-init.c | 115 -- arch/mn10300/proc-mn2ws0050/Makefile | 5 - arch/mn10300/proc-mn2ws0050/include/proc/cache.h | 49 - arch/mn10300/proc-mn2ws0050/include/proc/clock.h | 20 - .../proc-mn2ws0050/include/proc/dmactl-regs.h | 103 -- .../proc-mn2ws0050/include/proc/intctl-regs.h | 30 - arch/mn10300/proc-mn2ws0050/include/proc/irq.h | 49 - .../proc-mn2ws0050/include/proc/nand-regs.h | 120 -- arch/mn10300/proc-mn2ws0050/include/proc/proc.h | 18 - .../mn10300/proc-mn2ws0050/include/proc/smp-regs.h | 51 - arch/mn10300/proc-mn2ws0050/proc-init.c | 134 -- arch/mn10300/unit-asb2303/Makefile | 6 - arch/mn10300/unit-asb2303/flash.c | 99 - arch/mn10300/unit-asb2303/include/unit/clock.h | 24 - arch/mn10300/unit-asb2303/include/unit/leds.h | 43 - arch/mn10300/unit-asb2303/include/unit/serial.h | 141 -- arch/mn10300/unit-asb2303/include/unit/smc91111.h | 50 - arch/mn10300/unit-asb2303/include/unit/timex.h | 146 -- arch/mn10300/unit-asb2303/leds.c | 52 - arch/mn10300/unit-asb2303/smc91111.c | 53 - arch/mn10300/unit-asb2303/unit-init.c | 68 - arch/mn10300/unit-asb2305/Makefile | 8 - arch/mn10300/unit-asb2305/include/unit/clock.h | 24 - arch/mn10300/unit-asb2305/include/unit/leds.h | 51 - arch/mn10300/unit-asb2305/include/unit/serial.h | 125 -- arch/mn10300/unit-asb2305/include/unit/timex.h | 146 -- arch/mn10300/unit-asb2305/leds.c | 124 -- arch/mn10300/unit-asb2305/pci-asb2305.c | 212 --- arch/mn10300/unit-asb2305/pci-asb2305.h | 65 - arch/mn10300/unit-asb2305/pci-irq.c | 46 - arch/mn10300/unit-asb2305/pci.c | 505 ----- arch/mn10300/unit-asb2305/unit-init.c | 63 - arch/mn10300/unit-asb2364/Makefile | 12 - arch/mn10300/unit-asb2364/include/unit/clock.h | 29 - arch/mn10300/unit-asb2364/include/unit/fpga-regs.h | 53 - arch/mn10300/unit-asb2364/include/unit/irq.h | 35 - arch/mn10300/unit-asb2364/include/unit/leds.h | 54 - arch/mn10300/unit-asb2364/include/unit/serial.h | 151 -- arch/mn10300/unit-asb2364/include/unit/smsc911x.h | 171 -- arch/mn10300/unit-asb2364/include/unit/timex.h | 155 -- arch/mn10300/unit-asb2364/irq-fpga.c | 108 -- arch/mn10300/unit-asb2364/leds.c | 98 - arch/mn10300/unit-asb2364/smsc911x.c | 58 - arch/mn10300/unit-asb2364/unit-init.c | 132 -- crypto/sha3_generic.c | 2 +- drivers/input/joystick/analog.c | 2 +- drivers/net/ethernet/smsc/Kconfig | 6 +- drivers/net/ethernet/smsc/smc91x.h | 8 - drivers/rtc/Kconfig | 2 +- drivers/rtc/rtc-cmos.c | 2 +- drivers/staging/speakup/Kconfig | 2 +- drivers/video/console/Kconfig | 2 +- include/asm-generic/atomic.h | 2 - include/asm-generic/barrier.h | 2 +- include/asm-generic/exec.h | 2 +- include/asm-generic/io.h | 2 +- include/asm-generic/pci_iomap.h | 2 +- include/asm-generic/switch_to.h | 2 +- include/linux/ide.h | 2 +- init/Kconfig | 2 +- lib/Kconfig.debug | 2 +- lib/test_user_copy.c | 1 - scripts/mod/modpost.c | 7 +- tools/arch/mn10300/include/uapi/asm/bitsperlong.h | 1 - tools/arch/mn10300/include/uapi/asm/mman.h | 7 - tools/include/asm-generic/barrier.h | 2 +- 343 files changed, 21 insertions(+), 34163 deletions(-) delete mode 100644 Documentation/mn10300/ABI.txt delete mode 100644 Documentation/mn10300/compartmentalisation.txt delete mode 100644 arch/mn10300/Kconfig delete mode 100644 arch/mn10300/Kconfig.debug delete mode 100644 arch/mn10300/Makefile delete mode 100644 arch/mn10300/boot/.gitignore delete mode 100644 arch/mn10300/boot/Makefile delete mode 100644 arch/mn10300/boot/compressed/Makefile delete mode 100644 arch/mn10300/boot/compressed/head.S delete mode 100644 arch/mn10300/boot/compressed/misc.c delete mode 100644 arch/mn10300/boot/compressed/misc.h delete mode 100644 arch/mn10300/boot/compressed/vmlinux.lds delete mode 100644 arch/mn10300/boot/install.sh delete mode 100644 arch/mn10300/boot/tools/build.c delete mode 100644 arch/mn10300/configs/asb2303_defconfig delete mode 100644 arch/mn10300/configs/asb2364_defconfig delete mode 100644 arch/mn10300/include/asm/Kbuild delete mode 100644 arch/mn10300/include/asm/asm-offsets.h delete mode 100644 arch/mn10300/include/asm/atomic.h delete mode 100644 arch/mn10300/include/asm/bitops.h delete mode 100644 arch/mn10300/include/asm/bug.h delete mode 100644 arch/mn10300/include/asm/bugs.h delete mode 100644 arch/mn10300/include/asm/busctl-regs.h delete mode 100644 arch/mn10300/include/asm/cache.h delete mode 100644 arch/mn10300/include/asm/cacheflush.h delete mode 100644 arch/mn10300/include/asm/checksum.h delete mode 100644 arch/mn10300/include/asm/cmpxchg.h delete mode 100644 arch/mn10300/include/asm/cpu-regs.h delete mode 100644 arch/mn10300/include/asm/current.h delete mode 100644 arch/mn10300/include/asm/debugger.h delete mode 100644 arch/mn10300/include/asm/delay.h delete mode 100644 arch/mn10300/include/asm/div64.h delete mode 100644 arch/mn10300/include/asm/dma-mapping.h delete mode 100644 arch/mn10300/include/asm/dma.h delete mode 100644 arch/mn10300/include/asm/dmactl-regs.h delete mode 100644 arch/mn10300/include/asm/elf.h delete mode 100644 arch/mn10300/include/asm/emergency-restart.h delete mode 100644 arch/mn10300/include/asm/exceptions.h delete mode 100644 arch/mn10300/include/asm/fpu.h delete mode 100644 arch/mn10300/include/asm/frame.inc delete mode 100644 arch/mn10300/include/asm/ftrace.h delete mode 100644 arch/mn10300/include/asm/futex.h delete mode 100644 arch/mn10300/include/asm/gdb-stub.h delete mode 100644 arch/mn10300/include/asm/hardirq.h delete mode 100644 arch/mn10300/include/asm/highmem.h delete mode 100644 arch/mn10300/include/asm/hw_irq.h delete mode 100644 arch/mn10300/include/asm/intctl-regs.h delete mode 100644 arch/mn10300/include/asm/io.h delete mode 100644 arch/mn10300/include/asm/irq.h delete mode 100644 arch/mn10300/include/asm/irq_regs.h delete mode 100644 arch/mn10300/include/asm/irqflags.h delete mode 100644 arch/mn10300/include/asm/kdebug.h delete mode 100644 arch/mn10300/include/asm/kgdb.h delete mode 100644 arch/mn10300/include/asm/kmap_types.h delete mode 100644 arch/mn10300/include/asm/kprobes.h delete mode 100644 arch/mn10300/include/asm/linkage.h delete mode 100644 arch/mn10300/include/asm/local.h delete mode 100644 arch/mn10300/include/asm/local64.h delete mode 100644 arch/mn10300/include/asm/mc146818rtc.h delete mode 100644 arch/mn10300/include/asm/mmu.h delete mode 100644 arch/mn10300/include/asm/mmu_context.h delete mode 100644 arch/mn10300/include/asm/module.h delete mode 100644 arch/mn10300/include/asm/nmi.h delete mode 100644 arch/mn10300/include/asm/page.h delete mode 100644 arch/mn10300/include/asm/page_offset.h delete mode 100644 arch/mn10300/include/asm/pci.h delete mode 100644 arch/mn10300/include/asm/percpu.h delete mode 100644 arch/mn10300/include/asm/pgalloc.h delete mode 100644 arch/mn10300/include/asm/pgtable.h delete mode 100644 arch/mn10300/include/asm/pio-regs.h delete mode 100644 arch/mn10300/include/asm/processor.h delete mode 100644 arch/mn10300/include/asm/ptrace.h delete mode 100644 arch/mn10300/include/asm/reset-regs.h delete mode 100644 arch/mn10300/include/asm/rtc-regs.h delete mode 100644 arch/mn10300/include/asm/rtc.h delete mode 100644 arch/mn10300/include/asm/rwlock.h delete mode 100644 arch/mn10300/include/asm/serial-regs.h delete mode 100644 arch/mn10300/include/asm/serial.h delete mode 100644 arch/mn10300/include/asm/setup.h delete mode 100644 arch/mn10300/include/asm/shmparam.h delete mode 100644 arch/mn10300/include/asm/signal.h delete mode 100644 arch/mn10300/include/asm/smp.h delete mode 100644 arch/mn10300/include/asm/smsc911x.h delete mode 100644 arch/mn10300/include/asm/spinlock.h delete mode 100644 arch/mn10300/include/asm/spinlock_types.h delete mode 100644 arch/mn10300/include/asm/string.h delete mode 100644 arch/mn10300/include/asm/switch_to.h delete mode 100644 arch/mn10300/include/asm/syscall.h delete mode 100644 arch/mn10300/include/asm/termios.h delete mode 100644 arch/mn10300/include/asm/thread_info.h delete mode 100644 arch/mn10300/include/asm/timer-regs.h delete mode 100644 arch/mn10300/include/asm/timex.h delete mode 100644 arch/mn10300/include/asm/tlb.h delete mode 100644 arch/mn10300/include/asm/tlbflush.h delete mode 100644 arch/mn10300/include/asm/topology.h delete mode 100644 arch/mn10300/include/asm/types.h delete mode 100644 arch/mn10300/include/asm/uaccess.h delete mode 100644 arch/mn10300/include/asm/ucontext.h delete mode 100644 arch/mn10300/include/asm/unaligned.h delete mode 100644 arch/mn10300/include/asm/unistd.h delete mode 100644 arch/mn10300/include/asm/user.h delete mode 100644 arch/mn10300/include/asm/vga.h delete mode 100644 arch/mn10300/include/asm/xor.h delete mode 100644 arch/mn10300/include/uapi/asm/Kbuild delete mode 100644 arch/mn10300/include/uapi/asm/auxvec.h delete mode 100644 arch/mn10300/include/uapi/asm/bitsperlong.h delete mode 100644 arch/mn10300/include/uapi/asm/byteorder.h delete mode 100644 arch/mn10300/include/uapi/asm/errno.h delete mode 100644 arch/mn10300/include/uapi/asm/fcntl.h delete mode 100644 arch/mn10300/include/uapi/asm/ioctl.h delete mode 100644 arch/mn10300/include/uapi/asm/ioctls.h delete mode 100644 arch/mn10300/include/uapi/asm/ipcbuf.h delete mode 100644 arch/mn10300/include/uapi/asm/kvm_para.h delete mode 100644 arch/mn10300/include/uapi/asm/mman.h delete mode 100644 arch/mn10300/include/uapi/asm/msgbuf.h delete mode 100644 arch/mn10300/include/uapi/asm/param.h delete mode 100644 arch/mn10300/include/uapi/asm/posix_types.h delete mode 100644 arch/mn10300/include/uapi/asm/ptrace.h delete mode 100644 arch/mn10300/include/uapi/asm/resource.h delete mode 100644 arch/mn10300/include/uapi/asm/sembuf.h delete mode 100644 arch/mn10300/include/uapi/asm/setup.h delete mode 100644 arch/mn10300/include/uapi/asm/shmbuf.h delete mode 100644 arch/mn10300/include/uapi/asm/sigcontext.h delete mode 100644 arch/mn10300/include/uapi/asm/signal.h delete mode 100644 arch/mn10300/include/uapi/asm/socket.h delete mode 100644 arch/mn10300/include/uapi/asm/sockios.h delete mode 100644 arch/mn10300/include/uapi/asm/stat.h delete mode 100644 arch/mn10300/include/uapi/asm/statfs.h delete mode 100644 arch/mn10300/include/uapi/asm/swab.h delete mode 100644 arch/mn10300/include/uapi/asm/termbits.h delete mode 100644 arch/mn10300/include/uapi/asm/termios.h delete mode 100644 arch/mn10300/include/uapi/asm/types.h delete mode 100644 arch/mn10300/include/uapi/asm/unistd.h delete mode 100644 arch/mn10300/kernel/Makefile delete mode 100644 arch/mn10300/kernel/asm-offsets.c delete mode 100644 arch/mn10300/kernel/cevt-mn10300.c delete mode 100644 arch/mn10300/kernel/csrc-mn10300.c delete mode 100644 arch/mn10300/kernel/entry.S delete mode 100644 arch/mn10300/kernel/fpu-low.S delete mode 100644 arch/mn10300/kernel/fpu-nofpu-low.S delete mode 100644 arch/mn10300/kernel/fpu-nofpu.c delete mode 100644 arch/mn10300/kernel/fpu.c delete mode 100644 arch/mn10300/kernel/gdb-io-serial-low.S delete mode 100644 arch/mn10300/kernel/gdb-io-serial.c delete mode 100644 arch/mn10300/kernel/gdb-io-ttysm-low.S delete mode 100644 arch/mn10300/kernel/gdb-io-ttysm.c delete mode 100644 arch/mn10300/kernel/gdb-low.S delete mode 100644 arch/mn10300/kernel/gdb-stub.c delete mode 100644 arch/mn10300/kernel/head.S delete mode 100644 arch/mn10300/kernel/internal.h delete mode 100644 arch/mn10300/kernel/io.c delete mode 100644 arch/mn10300/kernel/irq.c delete mode 100644 arch/mn10300/kernel/kgdb.c delete mode 100644 arch/mn10300/kernel/kprobes.c delete mode 100644 arch/mn10300/kernel/mn10300-debug.c delete mode 100644 arch/mn10300/kernel/mn10300-serial-low.S delete mode 100644 arch/mn10300/kernel/mn10300-serial.c delete mode 100644 arch/mn10300/kernel/mn10300-serial.h delete mode 100644 arch/mn10300/kernel/mn10300-watchdog-low.S delete mode 100644 arch/mn10300/kernel/mn10300-watchdog.c delete mode 100644 arch/mn10300/kernel/mn10300_ksyms.c delete mode 100644 arch/mn10300/kernel/module.c delete mode 100644 arch/mn10300/kernel/process.c delete mode 100644 arch/mn10300/kernel/profile-low.S delete mode 100644 arch/mn10300/kernel/profile.c delete mode 100644 arch/mn10300/kernel/ptrace.c delete mode 100644 arch/mn10300/kernel/rtc.c delete mode 100644 arch/mn10300/kernel/setup.c delete mode 100644 arch/mn10300/kernel/sigframe.h delete mode 100644 arch/mn10300/kernel/signal.c delete mode 100644 arch/mn10300/kernel/smp-low.S delete mode 100644 arch/mn10300/kernel/smp.c delete mode 100644 arch/mn10300/kernel/switch_to.S delete mode 100644 arch/mn10300/kernel/sys_mn10300.c delete mode 100644 arch/mn10300/kernel/time.c delete mode 100644 arch/mn10300/kernel/traps.c delete mode 100644 arch/mn10300/kernel/vmlinux.lds.S delete mode 100644 arch/mn10300/lib/Makefile delete mode 100644 arch/mn10300/lib/__ashldi3.S delete mode 100644 arch/mn10300/lib/__ashrdi3.S delete mode 100644 arch/mn10300/lib/__lshrdi3.S delete mode 100644 arch/mn10300/lib/__ucmpdi2.S delete mode 100644 arch/mn10300/lib/ashrdi3.c delete mode 100644 arch/mn10300/lib/bitops.c delete mode 100644 arch/mn10300/lib/checksum.c delete mode 100644 arch/mn10300/lib/delay.c delete mode 100644 arch/mn10300/lib/do_csum.S delete mode 100644 arch/mn10300/lib/internal.h delete mode 100644 arch/mn10300/lib/lshrdi3.c delete mode 100644 arch/mn10300/lib/memcpy.S delete mode 100644 arch/mn10300/lib/memmove.S delete mode 100644 arch/mn10300/lib/memset.S delete mode 100644 arch/mn10300/lib/negdi2.c delete mode 100644 arch/mn10300/lib/usercopy.c delete mode 100644 arch/mn10300/mm/Kconfig.cache delete mode 100644 arch/mn10300/mm/Makefile delete mode 100644 arch/mn10300/mm/cache-dbg-flush-by-reg.S delete mode 100644 arch/mn10300/mm/cache-dbg-flush-by-tag.S delete mode 100644 arch/mn10300/mm/cache-dbg-inv-by-reg.S delete mode 100644 arch/mn10300/mm/cache-dbg-inv-by-tag.S delete mode 100644 arch/mn10300/mm/cache-dbg-inv.S delete mode 100644 arch/mn10300/mm/cache-disabled.c delete mode 100644 arch/mn10300/mm/cache-flush-by-reg.S delete mode 100644 arch/mn10300/mm/cache-flush-by-tag.S delete mode 100644 arch/mn10300/mm/cache-flush-icache.c delete mode 100644 arch/mn10300/mm/cache-inv-by-reg.S delete mode 100644 arch/mn10300/mm/cache-inv-by-tag.S delete mode 100644 arch/mn10300/mm/cache-inv-icache.c delete mode 100644 arch/mn10300/mm/cache-smp-flush.c delete mode 100644 arch/mn10300/mm/cache-smp-inv.c delete mode 100644 arch/mn10300/mm/cache-smp.c delete mode 100644 arch/mn10300/mm/cache-smp.h delete mode 100644 arch/mn10300/mm/cache.c delete mode 100644 arch/mn10300/mm/cache.inc delete mode 100644 arch/mn10300/mm/dma-alloc.c delete mode 100644 arch/mn10300/mm/extable.c delete mode 100644 arch/mn10300/mm/fault.c delete mode 100644 arch/mn10300/mm/init.c delete mode 100644 arch/mn10300/mm/misalignment.c delete mode 100644 arch/mn10300/mm/mmu-context.c delete mode 100644 arch/mn10300/mm/pgtable.c delete mode 100644 arch/mn10300/mm/tlb-mn10300.S delete mode 100644 arch/mn10300/mm/tlb-smp.c delete mode 100644 arch/mn10300/oprofile/Makefile delete mode 100644 arch/mn10300/oprofile/op_model_null.c delete mode 100644 arch/mn10300/proc-mn103e010/Makefile delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/cache.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/clock.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/irq.h delete mode 100644 arch/mn10300/proc-mn103e010/include/proc/proc.h delete mode 100644 arch/mn10300/proc-mn103e010/proc-init.c delete mode 100644 arch/mn10300/proc-mn2ws0050/Makefile delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/cache.h delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/clock.h delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/irq.h delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/proc.h delete mode 100644 arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h delete mode 100644 arch/mn10300/proc-mn2ws0050/proc-init.c delete mode 100644 arch/mn10300/unit-asb2303/Makefile delete mode 100644 arch/mn10300/unit-asb2303/flash.c delete mode 100644 arch/mn10300/unit-asb2303/include/unit/clock.h delete mode 100644 arch/mn10300/unit-asb2303/include/unit/leds.h delete mode 100644 arch/mn10300/unit-asb2303/include/unit/serial.h delete mode 100644 arch/mn10300/unit-asb2303/include/unit/smc91111.h delete mode 100644 arch/mn10300/unit-asb2303/include/unit/timex.h delete mode 100644 arch/mn10300/unit-asb2303/leds.c delete mode 100644 arch/mn10300/unit-asb2303/smc91111.c delete mode 100644 arch/mn10300/unit-asb2303/unit-init.c delete mode 100644 arch/mn10300/unit-asb2305/Makefile delete mode 100644 arch/mn10300/unit-asb2305/include/unit/clock.h delete mode 100644 arch/mn10300/unit-asb2305/include/unit/leds.h delete mode 100644 arch/mn10300/unit-asb2305/include/unit/serial.h delete mode 100644 arch/mn10300/unit-asb2305/include/unit/timex.h delete mode 100644 arch/mn10300/unit-asb2305/leds.c delete mode 100644 arch/mn10300/unit-asb2305/pci-asb2305.c delete mode 100644 arch/mn10300/unit-asb2305/pci-asb2305.h delete mode 100644 arch/mn10300/unit-asb2305/pci-irq.c delete mode 100644 arch/mn10300/unit-asb2305/pci.c delete mode 100644 arch/mn10300/unit-asb2305/unit-init.c delete mode 100644 arch/mn10300/unit-asb2364/Makefile delete mode 100644 arch/mn10300/unit-asb2364/include/unit/clock.h delete mode 100644 arch/mn10300/unit-asb2364/include/unit/fpga-regs.h delete mode 100644 arch/mn10300/unit-asb2364/include/unit/irq.h delete mode 100644 arch/mn10300/unit-asb2364/include/unit/leds.h delete mode 100644 arch/mn10300/unit-asb2364/include/unit/serial.h delete mode 100644 arch/mn10300/unit-asb2364/include/unit/smsc911x.h delete mode 100644 arch/mn10300/unit-asb2364/include/unit/timex.h delete mode 100644 arch/mn10300/unit-asb2364/irq-fpga.c delete mode 100644 arch/mn10300/unit-asb2364/leds.c delete mode 100644 arch/mn10300/unit-asb2364/smsc911x.c delete mode 100644 arch/mn10300/unit-asb2364/unit-init.c delete mode 100644 tools/arch/mn10300/include/uapi/asm/bitsperlong.h delete mode 100644 tools/arch/mn10300/include/uapi/asm/mman.h (limited to 'include/linux') diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index eae1e7193f50..bd7e2d08d790 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -284,8 +284,6 @@ misc-devices/ - directory with info about devices using the misc dev subsystem mmc/ - directory with info about the MMC subsystem -mn10300/ - - directory with info about the mn10300 architecture port mtd/ - directory with info about memory technology devices (flash) namespaces/ diff --git a/Documentation/features/core/BPF-JIT/arch-support.txt b/Documentation/features/core/BPF-JIT/arch-support.txt index b0634ec01881..544eb1dd5fe1 100644 --- a/Documentation/features/core/BPF-JIT/arch-support.txt +++ b/Documentation/features/core/BPF-JIT/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/core/generic-idle-thread/arch-support.txt b/Documentation/features/core/generic-idle-thread/arch-support.txt index e2a1a385efd3..c7f8626faca2 100644 --- a/Documentation/features/core/generic-idle-thread/arch-support.txt +++ b/Documentation/features/core/generic-idle-thread/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Documentation/features/core/jump-labels/arch-support.txt index dafcea38fe5e..647b0ab5a78d 100644 --- a/Documentation/features/core/jump-labels/arch-support.txt +++ b/Documentation/features/core/jump-labels/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/core/tracehook/arch-support.txt b/Documentation/features/core/tracehook/arch-support.txt index 3d7886fcb6a9..c95ba6d79cee 100644 --- a/Documentation/features/core/tracehook/arch-support.txt +++ b/Documentation/features/core/tracehook/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | ok | | nios2: | ok | | openrisc: | ok | | parisc: | ok | diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt index 63598b0e8ea6..fbb5afe45848 100644 --- a/Documentation/features/debug/KASAN/arch-support.txt +++ b/Documentation/features/debug/KASAN/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt index 13b3b3dfe7f2..a35c5057585b 100644 --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/kgdb/arch-support.txt b/Documentation/features/debug/kgdb/arch-support.txt index cb4792cf0f98..afb31a2505cb 100644 --- a/Documentation/features/debug/kgdb/arch-support.txt +++ b/Documentation/features/debug/kgdb/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | mn10300: | ok | | nios2: | ok | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt index 2046539489fe..4144979bc022 100644 --- a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt +++ b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/kprobes/arch-support.txt b/Documentation/features/debug/kprobes/arch-support.txt index bfb3546a70d0..7ec1a185e713 100644 --- a/Documentation/features/debug/kprobes/arch-support.txt +++ b/Documentation/features/debug/kprobes/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/kretprobes/arch-support.txt b/Documentation/features/debug/kretprobes/arch-support.txt index cb2213bfadc5..fa9009c08b1f 100644 --- a/Documentation/features/debug/kretprobes/arch-support.txt +++ b/Documentation/features/debug/kretprobes/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/optprobes/arch-support.txt b/Documentation/features/debug/optprobes/arch-support.txt index 219aa64ca3f5..38adefbe2edf 100644 --- a/Documentation/features/debug/optprobes/arch-support.txt +++ b/Documentation/features/debug/optprobes/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/stackprotector/arch-support.txt b/Documentation/features/debug/stackprotector/arch-support.txt index 904864c3f18c..2965ae0ca139 100644 --- a/Documentation/features/debug/stackprotector/arch-support.txt +++ b/Documentation/features/debug/stackprotector/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/uprobes/arch-support.txt b/Documentation/features/debug/uprobes/arch-support.txt index d092f000e6bb..5da0bc2e7e1e 100644 --- a/Documentation/features/debug/uprobes/arch-support.txt +++ b/Documentation/features/debug/uprobes/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/user-ret-profiler/arch-support.txt b/Documentation/features/debug/user-ret-profiler/arch-support.txt index 9e9e195b6d30..a45ced203f32 100644 --- a/Documentation/features/debug/user-ret-profiler/arch-support.txt +++ b/Documentation/features/debug/user-ret-profiler/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/io/dma-api-debug/arch-support.txt b/Documentation/features/io/dma-api-debug/arch-support.txt index ba9e169859c4..411ec941e46c 100644 --- a/Documentation/features/io/dma-api-debug/arch-support.txt +++ b/Documentation/features/io/dma-api-debug/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/io/dma-contiguous/arch-support.txt b/Documentation/features/io/dma-contiguous/arch-support.txt index 35b501f2c117..3b65953a96a9 100644 --- a/Documentation/features/io/dma-contiguous/arch-support.txt +++ b/Documentation/features/io/dma-contiguous/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/io/sg-chain/arch-support.txt b/Documentation/features/io/sg-chain/arch-support.txt index 42c078dff18b..65e9368c69a7 100644 --- a/Documentation/features/io/sg-chain/arch-support.txt +++ b/Documentation/features/io/sg-chain/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/lib/strncasecmp/arch-support.txt b/Documentation/features/lib/strncasecmp/arch-support.txt index b10c21f14739..cee48bd07b08 100644 --- a/Documentation/features/lib/strncasecmp/arch-support.txt +++ b/Documentation/features/lib/strncasecmp/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/locking/cmpxchg-local/arch-support.txt b/Documentation/features/locking/cmpxchg-local/arch-support.txt index 3b87fd37bae8..a83465dc0db5 100644 --- a/Documentation/features/locking/cmpxchg-local/arch-support.txt +++ b/Documentation/features/locking/cmpxchg-local/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/locking/lockdep/arch-support.txt b/Documentation/features/locking/lockdep/arch-support.txt index cefcd720f04e..e5d51c585a90 100644 --- a/Documentation/features/locking/lockdep/arch-support.txt +++ b/Documentation/features/locking/lockdep/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/locking/queued-rwlocks/arch-support.txt b/Documentation/features/locking/queued-rwlocks/arch-support.txt index da6c7e37141c..5cae3a63a44e 100644 --- a/Documentation/features/locking/queued-rwlocks/arch-support.txt +++ b/Documentation/features/locking/queued-rwlocks/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt b/Documentation/features/locking/queued-spinlocks/arch-support.txt index 1e5dbcdd1c76..cb227de0bbf9 100644 --- a/Documentation/features/locking/queued-spinlocks/arch-support.txt +++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/locking/rwsem-optimized/arch-support.txt b/Documentation/features/locking/rwsem-optimized/arch-support.txt index b79e92288112..ee70c9c52627 100644 --- a/Documentation/features/locking/rwsem-optimized/arch-support.txt +++ b/Documentation/features/locking/rwsem-optimized/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt b/Documentation/features/perf/kprobes-event/arch-support.txt index 6418ccc6fc34..52f54e64e993 100644 --- a/Documentation/features/perf/kprobes-event/arch-support.txt +++ b/Documentation/features/perf/kprobes-event/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/perf/perf-regs/arch-support.txt b/Documentation/features/perf/perf-regs/arch-support.txt index 3b3392ac6466..e4294aed38bf 100644 --- a/Documentation/features/perf/perf-regs/arch-support.txt +++ b/Documentation/features/perf/perf-regs/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/perf/perf-stackdump/arch-support.txt b/Documentation/features/perf/perf-stackdump/arch-support.txt index 4594cb28fbc8..b12117a9aa4d 100644 --- a/Documentation/features/perf/perf-stackdump/arch-support.txt +++ b/Documentation/features/perf/perf-stackdump/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt index 42eaab4d439d..0f419ecfbce6 100644 --- a/Documentation/features/sched/membarrier-sync-core/arch-support.txt +++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt @@ -44,7 +44,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/sched/numa-balancing/arch-support.txt b/Documentation/features/sched/numa-balancing/arch-support.txt index 4e67833aae66..045418673368 100644 --- a/Documentation/features/sched/numa-balancing/arch-support.txt +++ b/Documentation/features/sched/numa-balancing/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | .. | | microblaze: | .. | | mips: | TODO | - | mn10300: | .. | | nios2: | .. | | openrisc: | .. | | parisc: | .. | diff --git a/Documentation/features/seccomp/seccomp-filter/arch-support.txt b/Documentation/features/seccomp/seccomp-filter/arch-support.txt index c5d8b397a693..c08a330e51d2 100644 --- a/Documentation/features/seccomp/seccomp-filter/arch-support.txt +++ b/Documentation/features/seccomp/seccomp-filter/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/time/arch-tick-broadcast/arch-support.txt b/Documentation/features/time/arch-tick-broadcast/arch-support.txt index 9e4999136881..da91b576ede8 100644 --- a/Documentation/features/time/arch-tick-broadcast/arch-support.txt +++ b/Documentation/features/time/arch-tick-broadcast/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/time/clockevents/arch-support.txt b/Documentation/features/time/clockevents/arch-support.txt index f90cb64c640b..d76322a76668 100644 --- a/Documentation/features/time/clockevents/arch-support.txt +++ b/Documentation/features/time/clockevents/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | ok | | microblaze: | ok | | mips: | ok | - | mn10300: | ok | | nios2: | ok | | openrisc: | ok | | parisc: | TODO | diff --git a/Documentation/features/time/context-tracking/arch-support.txt b/Documentation/features/time/context-tracking/arch-support.txt index eb4e5d32a2e9..09582d171c84 100644 --- a/Documentation/features/time/context-tracking/arch-support.txt +++ b/Documentation/features/time/context-tracking/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/time/irq-time-acct/arch-support.txt b/Documentation/features/time/irq-time-acct/arch-support.txt index 02b7441f360f..5df0285b6fc4 100644 --- a/Documentation/features/time/irq-time-acct/arch-support.txt +++ b/Documentation/features/time/irq-time-acct/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | .. | diff --git a/Documentation/features/time/modern-timekeeping/arch-support.txt b/Documentation/features/time/modern-timekeeping/arch-support.txt index b3eb6fe6bc27..0f8c7e4084b0 100644 --- a/Documentation/features/time/modern-timekeeping/arch-support.txt +++ b/Documentation/features/time/modern-timekeeping/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | mn10300: | ok | | nios2: | ok | | openrisc: | ok | | parisc: | ok | diff --git a/Documentation/features/time/virt-cpuacct/arch-support.txt b/Documentation/features/time/virt-cpuacct/arch-support.txt index a1bd77fd723a..c0af0a37444d 100644 --- a/Documentation/features/time/virt-cpuacct/arch-support.txt +++ b/Documentation/features/time/virt-cpuacct/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/vm/ELF-ASLR/arch-support.txt b/Documentation/features/vm/ELF-ASLR/arch-support.txt index 3f926177833c..72c3124ffd1f 100644 --- a/Documentation/features/vm/ELF-ASLR/arch-support.txt +++ b/Documentation/features/vm/ELF-ASLR/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/vm/PG_uncached/arch-support.txt b/Documentation/features/vm/PG_uncached/arch-support.txt index 4c8f65d525d7..46c62a1d7dda 100644 --- a/Documentation/features/vm/PG_uncached/arch-support.txt +++ b/Documentation/features/vm/PG_uncached/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/vm/THP/arch-support.txt b/Documentation/features/vm/THP/arch-support.txt index d121dc2e3e5e..eaace2054bb4 100644 --- a/Documentation/features/vm/THP/arch-support.txt +++ b/Documentation/features/vm/THP/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | .. | | microblaze: | .. | | mips: | ok | - | mn10300: | .. | | nios2: | .. | | openrisc: | .. | | parisc: | TODO | diff --git a/Documentation/features/vm/TLB/arch-support.txt b/Documentation/features/vm/TLB/arch-support.txt index af233d2d82cf..b1088eaaff3f 100644 --- a/Documentation/features/vm/TLB/arch-support.txt +++ b/Documentation/features/vm/TLB/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | .. | | microblaze: | .. | | mips: | TODO | - | mn10300: | TODO | | nios2: | .. | | openrisc: | .. | | parisc: | TODO | diff --git a/Documentation/features/vm/huge-vmap/arch-support.txt b/Documentation/features/vm/huge-vmap/arch-support.txt index 45c74fbe6805..6e4e5295ee2a 100644 --- a/Documentation/features/vm/huge-vmap/arch-support.txt +++ b/Documentation/features/vm/huge-vmap/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt index 6cd436af0cc8..185e0654389f 100644 --- a/Documentation/features/vm/ioremap_prot/arch-support.txt +++ b/Documentation/features/vm/ioremap_prot/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/vm/numa-memblock/arch-support.txt b/Documentation/features/vm/numa-memblock/arch-support.txt index 2db895856da6..de7f891fb2a8 100644 --- a/Documentation/features/vm/numa-memblock/arch-support.txt +++ b/Documentation/features/vm/numa-memblock/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | .. | | microblaze: | ok | | mips: | ok | - | mn10300: | TODO | | nios2: | .. | | openrisc: | .. | | parisc: | .. | diff --git a/Documentation/features/vm/pte_special/arch-support.txt b/Documentation/features/vm/pte_special/arch-support.txt index ccb15b6da42f..8587fe975fea 100644 --- a/Documentation/features/vm/pte_special/arch-support.txt +++ b/Documentation/features/vm/pte_special/arch-support.txt @@ -21,7 +21,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/mn10300/ABI.txt b/Documentation/mn10300/ABI.txt deleted file mode 100644 index d3507bad428d..000000000000 --- a/Documentation/mn10300/ABI.txt +++ /dev/null @@ -1,149 +0,0 @@ - ========================= - MN10300 FUNCTION CALL ABI - ========================= - -======= -GENERAL -======= - -The MN10300/AM33 kernel runs in little-endian mode; big-endian mode is not -supported. - -The stack grows downwards, and should always be 32-bit aligned. There are -separate stack pointer registers for userspace and the kernel. - - -================ -ARGUMENT PASSING -================ - -The first two arguments (assuming up to 32-bits per argument) to a function are -passed in the D0 and D1 registers respectively; all other arguments are passed -on the stack. - -If 64-bit arguments are being passed, then they are never split between -registers and the stack. If the first argument is a 64-bit value, it will be -passed in D0:D1. If the first argument is not a 64-bit value, but the second -is, the second will be passed entirely on the stack and D1 will be unused. - -Arguments smaller than 32-bits are not coalesced within a register or a stack -word. For example, two byte-sized arguments will always be passed in separate -registers or word-sized stack slots. - - -================= -CALLING FUNCTIONS -================= - -The caller must allocate twelve bytes on the stack for the callee's use before -it inserts a CALL instruction. The CALL instruction will write into the TOS -word, but won't actually modify the stack pointer; similarly, the RET -instruction reads from the TOS word of the stack, but doesn't move the stack -pointer beyond it. - - - Stack: - | | - | | - |---------------| SP+20 - | 4th Arg | - |---------------| SP+16 - | 3rd Arg | - |---------------| SP+12 - | D1 Save Slot | - |---------------| SP+8 - | D0 Save Slot | - |---------------| SP+4 - | Return Addr | - |---------------| SP - | | - | | - - -The caller must leave space on the stack (hence an allocation of twelve bytes) -in which the callee may store the first two arguments. - - -============ -RETURN VALUE -============ - -The return value is passed in D0 for an integer (or D0:D1 for a 64-bit value), -or A0 for a pointer. - -If the return value is a value larger than 64-bits, or is a structure or an -array, then a hidden first argument will be passed to the callee by the caller: -this will point to a piece of memory large enough to hold the result of the -function. In this case, the callee will return the value in that piece of -memory, and no value will be returned in D0 or A0. - - -=================== -REGISTER CLOBBERING -=================== - -The values in certain registers may be clobbered by the callee, and other -values must be saved: - - Clobber: D0-D1, A0-A1, E0-E3 - Save: D2-D3, A2-A3, E4-E7, SP - -All other non-supervisor-only registers are clobberable (such as MDR, MCRL, -MCRH). - - -================= -SPECIAL REGISTERS -================= - -Certain ordinary registers may carry special usage for the compiler: - - A3: Frame pointer - E2: TLS pointer - - -========== -KERNEL ABI -========== - -The kernel may use a slightly different ABI internally. - - (*) E2 - - If CONFIG_MN10300_CURRENT_IN_E2 is defined, then the current task pointer - will be kept in the E2 register, and that register will be marked - unavailable for the compiler to use as a scratch register. - - Normally the kernel uses something like: - - MOV SP,An - AND 0xFFFFE000,An - MOV (An),Rm // Rm holds current - MOV (yyy,Rm) // Access current->yyy - - To find the address of current; but since this option permits current to - be carried globally in an register, it can use: - - MOV (yyy,E2) // Access current->yyy - - instead. - - -=============== -SYSTEM CALL ABI -=============== - -System calls are called with the following convention: - - REGISTER ENTRY EXIT - =============== ======================= ======================= - D0 Syscall number Return value - A0 1st syscall argument Saved - D1 2nd syscall argument Saved - A3 3rd syscall argument Saved - A2 4th syscall argument Saved - D3 5th syscall argument Saved - D2 6th syscall argument Saved - -All other registers are saved. The layout is a consequence of the way the MOVM -instruction stores registers onto the stack. diff --git a/Documentation/mn10300/compartmentalisation.txt b/Documentation/mn10300/compartmentalisation.txt deleted file mode 100644 index 8958b51dac4b..000000000000 --- a/Documentation/mn10300/compartmentalisation.txt +++ /dev/null @@ -1,60 +0,0 @@ - ========================================= - PART-SPECIFIC SOURCE COMPARTMENTALISATION - ========================================= - -The sources for various parts are compartmentalised at two different levels: - - (1) Processor level - - The "processor level" is a CPU core plus the other on-silicon - peripherals. - - Processor-specific header files are divided among directories in a similar - way to the CPU level: - - (*) include/asm-mn10300/proc-mn103e010/ - - Support for the AM33v2 CPU core. - - The appropriate processor is selected by a CONFIG_MN10300_PROC_YYYY option - from the "Processor support" choice menu in the arch/mn10300/Kconfig file. - - - (2) Unit level - - The "unit level" is a processor plus all the external peripherals - controlled by that processor. - - Unit-specific header files are divided among directories in a similar way - to the CPU level; not only that, but specific sources may also be - segregated into separate directories under the arch directory: - - (*) include/asm-mn10300/unit-asb2303/ - (*) arch/mn10300/unit-asb2303/ - - Support for the ASB2303 board with an ASB2308 daughter board. - - (*) include/asm-mn10300/unit-asb2305/ - (*) arch/mn10300/unit-asb2305/ - - Support for the ASB2305 board. - - The appropriate processor is selected by a CONFIG_MN10300_UNIT_ZZZZ option - from the "Unit type" choice menu in the arch/mn10300/Kconfig file. - - -============ -COMPILE TIME -============ - -When the kernel is compiled, symbolic links will be made in the asm header file -directory for this arch: - - include/asm-mn10300/proc => include/asm-mn10300/proc-YYYY/ - include/asm-mn10300/unit => include/asm-mn10300/unit-ZZZZ/ - -So that the header files contained in those directories can be accessed without -lots of #ifdef-age. - -The appropriate arch/mn10300/unit-ZZZZ directory will also be entered by the -compilation process; all other unit-specific directories will be ignored. diff --git a/MAINTAINERS b/MAINTAINERS index 313754bf39e1..69123be5bb64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10394,14 +10394,6 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/panasonic-laptop.c -PANASONIC MN10300/AM33/AM34 PORT -M: David Howells -L: linux-am33-list@redhat.com (moderated for non-subscribers) -W: ftp://ftp.redhat.com/pub/redhat/gnupro/AM33/ -S: Maintained -F: Documentation/mn10300/ -F: arch/mn10300/ - PARALLEL LCD/KEYPAD PANEL DRIVER M: Willy Tarreau M: Ksenija Stanojevic diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig deleted file mode 100644 index e9d8d60bd28b..000000000000 --- a/arch/mn10300/Kconfig +++ /dev/null @@ -1,499 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config MN10300 - def_bool y - select HAVE_EXIT_THREAD - select HAVE_OPROFILE - select HAVE_UID16 - select GENERIC_IRQ_SHOW - select ARCH_WANT_IPC_PARSE_VERSION - select HAVE_ARCH_TRACEHOOK - select HAVE_ARCH_KGDB - select GENERIC_ATOMIC64 - select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER - select VIRT_TO_BUS - select GENERIC_CLOCKEVENTS - select MODULES_USE_ELF_RELA - select OLD_SIGSUSPEND3 - select OLD_SIGACTION - select HAVE_DEBUG_STACKOVERFLOW - select ARCH_NO_COHERENT_DMA_MMAP - -config AM33_2 - def_bool n - -config AM33_3 - def_bool n - -config AM34_2 - def_bool n - select MN10300_HAS_ATOMIC_OPS_UNIT - select MN10300_HAS_CACHE_SNOOP - -config ERRATUM_NEED_TO_RELOAD_MMUCTR - def_bool y if AM33_3 || AM34_2 - -config MMU - def_bool y - -config HIGHMEM - def_bool n - -config NUMA - def_bool n - -config RWSEM_GENERIC_SPINLOCK - def_bool y - -config RWSEM_XCHGADD_ALGORITHM - bool - -config GENERIC_CALIBRATE_DELAY - def_bool y - -config GENERIC_HWEIGHT - def_bool y - -config GENERIC_BUG - def_bool y - depends on BUG - -config QUICKLIST - def_bool y - -config ARCH_HAS_ILOG2_U32 - def_bool y - -config HOTPLUG_CPU - def_bool n - -source "init/Kconfig" - -source "kernel/Kconfig.freezer" - - -menu "Panasonic MN10300 system setup" - -choice - prompt "Unit type" - default MN10300_UNIT_ASB2303 - help - This option specifies board for which the kernel will be - compiled. It affects the external peripherals catered for. - -config MN10300_UNIT_ASB2303 - bool "ASB2303" - -config MN10300_UNIT_ASB2305 - bool "ASB2305" - -config MN10300_UNIT_ASB2364 - bool "ASB2364" - select SMSC911X_ARCH_HOOKS if SMSC911X - -endchoice - -choice - prompt "Processor support" - default MN10300_PROC_MN103E010 - help - This option specifies the processor for which the kernel will be - compiled. It affects the on-chip peripherals catered for. - -config MN10300_PROC_MN103E010 - bool "MN103E010" - depends on MN10300_UNIT_ASB2303 || MN10300_UNIT_ASB2305 - select AM33_2 - select MN10300_PROC_HAS_TTYSM0 - select MN10300_PROC_HAS_TTYSM1 - select MN10300_PROC_HAS_TTYSM2 - -config MN10300_PROC_MN2WS0050 - bool "MN2WS0050" - depends on MN10300_UNIT_ASB2364 - select AM34_2 - select MN10300_PROC_HAS_TTYSM0 - select MN10300_PROC_HAS_TTYSM1 - select MN10300_PROC_HAS_TTYSM2 - -endchoice - -config MN10300_HAS_ATOMIC_OPS_UNIT - def_bool n - help - This should be enabled if the processor has an atomic ops unit - capable of doing LL/SC equivalent operations. - -config FPU - bool "FPU present" - default y - depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050 - -config LAZY_SAVE_FPU - bool "Save FPU state lazily" - default y - depends on FPU && !SMP - help - Enable this to be lazy in the saving of the FPU state to the owning - task's thread struct. This is useful if most tasks on the system - don't use the FPU as only those tasks that use it will pass it - between them, and the state needn't be saved for a task that isn't - using it. - - This can't be so easily used on SMP as the process that owns the FPU - state on a CPU may be currently running on another CPU, so for the - moment, it is disabled. - -source "arch/mn10300/mm/Kconfig.cache" - -config MN10300_TLB_USE_PIDR - def_bool y - -menu "Memory layout options" - -config KERNEL_RAM_BASE_ADDRESS - hex "Base address of kernel RAM" - default "0x90000000" - -config INTERRUPT_VECTOR_BASE - hex "Base address of vector table" - default "0x90000000" - help - The base address of the vector table will be programmed into - the TBR register. It must be on 16MiB address boundary. - -config KERNEL_TEXT_ADDRESS - hex "Base address of kernel" - default "0x90001000" - -config KERNEL_ZIMAGE_BASE_ADDRESS - hex "Base address of compressed vmlinux image" - default "0x50700000" - -config BOOT_STACK_OFFSET - hex - default "0xF00" if SMP - default "0xFF0" if !SMP - -config BOOT_STACK_SIZE - hex - depends on SMP - default "0x100" -endmenu - -config SMP - bool "Symmetric multi-processing support" - default y - depends on MN10300_PROC_MN2WS0050 - ---help--- - This enables support for systems with more than one CPU. If you have - a system with only one CPU, say N. If you have a system with more - than one CPU, say Y. - - If you say N here, the kernel will run on uni- and multiprocessor - machines, but will use only one CPU of a multiprocessor machine. If - you say Y here, the kernel will run on many, but not all, - uniprocessor machines. On a uniprocessor machine, the kernel - will run faster if you say N here. - - See also , - and the SMP-HOWTO available at - . - - If you don't know what to do here, say N. - -config NR_CPUS - int - depends on SMP - default "2" - -source "kernel/Kconfig.preempt" - -config MN10300_CURRENT_IN_E2 - bool "Hold current task address in E2 register" - depends on !SMP - default y - help - This option removes the E2/R2 register from the set available to gcc - for normal use and instead uses it to store the address of the - current process's task_struct whilst in the kernel. - - This means the kernel doesn't need to calculate the address each time - "current" is used (take SP, AND with mask and dereference pointer - just to get the address), and instead can just use E2+offset - addressing each time. - - This has no effect on userspace. - -config MN10300_USING_JTAG - bool "Using JTAG to debug kernel" - default y - help - This options indicates that JTAG will be used to debug the kernel. It - suppresses the use of certain hardware debugging features, such as - single-stepping, which are taken over completely by the JTAG unit. - -source "kernel/Kconfig.hz" - -config MN10300_RTC - bool "Using MN10300 RTC" - depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050 - select RTC_CLASS - select RTC_DRV_CMOS - select RTC_SYSTOHC - default n - help - This option enables support for the RTC, thus enabling time to be - tracked, even when system is powered down. This is available on-chip - on the MN103E010. - -config MN10300_WD_TIMER - bool "Using MN10300 watchdog timer" - default y - help - This options indicates that the watchdog timer will be used. - -config PCI - bool "Use PCI" - depends on MN10300_UNIT_ASB2305 - default y - select GENERIC_PCI_IOMAP - help - Some systems (such as the ASB2305) have PCI onboard. If you have one - of these boards and you wish to use the PCI facilities, say Y here. - - The PCI-HOWTO, available from - , contains valuable - information about which PCI hardware does work under Linux and which - doesn't. - -source "drivers/pci/Kconfig" - -source "drivers/pcmcia/Kconfig" - -menu "MN10300 internal serial options" - -config MN10300_PROC_HAS_TTYSM0 - bool - default n - -config MN10300_PROC_HAS_TTYSM1 - bool - default n - -config MN10300_PROC_HAS_TTYSM2 - bool - default n - -config MN10300_TTYSM - bool "Support for ttySM serial ports" - depends on MN10300 - default y - select SERIAL_CORE - help - This option enables support for the on-chip serial ports that the - MN10300 has available. - -config MN10300_TTYSM_CONSOLE - bool "Support for console on ttySM serial ports" - depends on MN10300_TTYSM - select SERIAL_CORE_CONSOLE - help - This option enables support for a console on the on-chip serial ports - that the MN10300 has available. - -# -# /dev/ttySM0 -# -config MN10300_TTYSM0 - bool "Enable SIF0 (/dev/ttySM0)" - depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM0 - help - Enable access to SIF0 through /dev/ttySM0 or gdb-stub - -choice - prompt "Select the timer to supply the clock for SIF0" - default MN10300_TTYSM0_TIMER8 - depends on MN10300_TTYSM0 - -config MN10300_TTYSM0_TIMER8 - bool "Use timer 8 (16-bit)" - -config MN10300_TTYSM0_TIMER2 - bool "Use timer 2 (8-bit)" - -endchoice - -# -# /dev/ttySM1 -# -config MN10300_TTYSM1 - bool "Enable SIF1 (/dev/ttySM1)" - depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM1 - help - Enable access to SIF1 through /dev/ttySM1 or gdb-stub - -choice - prompt "Select the timer to supply the clock for SIF1" - default MN10300_TTYSM1_TIMER12 \ - if !(AM33_2 || AM33_3) - default MN10300_TTYSM1_TIMER9 \ - if AM33_2 || AM33_3 - depends on MN10300_TTYSM1 - -config MN10300_TTYSM1_TIMER12 - bool "Use timer 12 (16-bit)" - depends on !(AM33_2 || AM33_3) - -config MN10300_TTYSM1_TIMER9 - bool "Use timer 9 (16-bit)" - depends on AM33_2 || AM33_3 - -config MN10300_TTYSM1_TIMER3 - bool "Use timer 3 (8-bit)" - depends on AM33_2 || AM33_3 - -endchoice - -# -# /dev/ttySM2 -# -config MN10300_TTYSM2 - bool "Enable SIF2 (/dev/ttySM2)" - depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM2 - help - Enable access to SIF2 through /dev/ttySM2 or gdb-stub - -choice - prompt "Select the timer to supply the clock for SIF2" - default MN10300_TTYSM2_TIMER3 \ - if !(AM33_2 || AM33_3) - default MN10300_TTYSM2_TIMER10 \ - if AM33_2 || AM33_3 - depends on MN10300_TTYSM2 - -config MN10300_TTYSM2_TIMER9 - bool "Use timer 9 (16-bit)" - depends on !(AM33_2 || AM33_3) - -config MN10300_TTYSM2_TIMER1 - bool "Use timer 1 (8-bit)" - depends on !(AM33_2 || AM33_3) - -config MN10300_TTYSM2_TIMER3 - bool "Use timer 3 (8-bit)" - depends on !(AM33_2 || AM33_3) - -config MN10300_TTYSM2_TIMER10 - bool "Use timer 10 (16-bit)" - depends on AM33_2 || AM33_3 - -endchoice - -config MN10300_TTYSM2_CTS - bool "Enable the use of the CTS line /dev/ttySM2" - depends on MN10300_TTYSM2 && AM33_2 - -endmenu - -menu "Interrupt request priority options" - -comment "[!] NOTE: A lower number/level indicates a higher priority (0 is highest, 6 is lowest)" - -comment "____Non-maskable interrupt levels____" -comment "The following must be set to a higher priority than local_irq_disable() and on-chip serial" - -config DEBUGGER_IRQ_LEVEL - int "DEBUGGER interrupt priority" - depends on KERNEL_DEBUGGER - range 0 1 if LINUX_CLI_LEVEL = 2 - range 0 2 if LINUX_CLI_LEVEL = 3 - range 0 3 if LINUX_CLI_LEVEL = 4 - range 0 4 if LINUX_CLI_LEVEL = 5 - range 0 5 if LINUX_CLI_LEVEL = 6 - default 0 - -comment "The following must be set to a higher priority than local_irq_disable()" - -config MN10300_SERIAL_IRQ_LEVEL - int "MN10300 on-chip serial interrupt priority" - depends on MN10300_TTYSM - range 1 1 if LINUX_CLI_LEVEL = 2 - range 1 2 if LINUX_CLI_LEVEL = 3 - range 1 3 if LINUX_CLI_LEVEL = 4 - range 1 4 if LINUX_CLI_LEVEL = 5 - range 1 5 if LINUX_CLI_LEVEL = 6 - default 1 - -comment "-" -comment "____Maskable interrupt levels____" - -config LINUX_CLI_LEVEL - int "The highest interrupt priority excluded by local_irq_disable() (2-6)" - range 2 6 - default 2 - help - local_irq_disable() doesn't actually disable maskable interrupts - - what it does is restrict the levels of interrupt which are permitted - (a lower level indicates a higher priority) by lowering the value in - EPSW.IM from 7. Any interrupt is permitted for which the level is - lower than EPSW.IM. - - Certain interrupts, such as DEBUGGER and virtual MN10300 on-chip - serial DMA interrupts are allowed to interrupt normal disabled - sections. - -comment "The following must be set to a equal to or lower priority than LINUX_CLI_LEVEL" - -config TIMER_IRQ_LEVEL - int "Kernel timer interrupt priority" - range LINUX_CLI_LEVEL 6 - default 4 - -config PCI_IRQ_LEVEL - int "PCI interrupt priority" - depends on PCI - range LINUX_CLI_LEVEL 6 - default 5 - -config ETHERNET_IRQ_LEVEL - int "Ethernet interrupt priority" - depends on SMC91X || SMC911X || SMSC911X - range LINUX_CLI_LEVEL 6 - default 6 - -config EXT_SERIAL_IRQ_LEVEL - int "External serial port interrupt priority" - depends on SERIAL_8250 - range LINUX_CLI_LEVEL 6 - default 6 - -endmenu - -source "mm/Kconfig" - -menu "Power management options" -source kernel/power/Kconfig -endmenu - -endmenu - - -menu "Executable formats" - -source "fs/Kconfig.binfmt" - -endmenu - -source "net/Kconfig" - -source "drivers/Kconfig" - -source "fs/Kconfig" - -source "arch/mn10300/Kconfig.debug" - -source "security/Kconfig" - -source "crypto/Kconfig" - -source "lib/Kconfig" diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug deleted file mode 100644 index 37ada651f756..000000000000 --- a/arch/mn10300/Kconfig.debug +++ /dev/null @@ -1,156 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menu "Kernel hacking" - -source "lib/Kconfig.debug" - -config DEBUG_DECOMPRESS_KERNEL - bool "Using serial port during decompressing kernel" - depends on DEBUG_KERNEL - default n - help - If you say Y here you will confirm the start and the end of - decompressing Linux seeing "Uncompressing Linux... " and - "Ok, booting the kernel.\n" on console. - -config TEST_MISALIGNMENT_HANDLER - bool "Run tests on the misalignment handler" - depends on DEBUG_KERNEL - default n - help - If you say Y here the kernel will execute a list of misaligned memory - accesses to make sure the misalignment handler deals them with - correctly. If it does not, the kernel will throw a BUG. - -config KPROBES - bool "Kprobes" - depends on DEBUG_KERNEL - help - Kprobes allows you to trap at almost any kernel address and - execute a callback function. register_kprobe() establishes - a probepoint and specifies the callback. Kprobes is useful - for kernel debugging, non-intrusive instrumentation and testing. - If in doubt, say "N". - -config GDBSTUB - bool "Remote GDB kernel debugging" - depends on DEBUG_KERNEL && DEPRECATED - select DEBUG_INFO - select FRAME_POINTER - help - If you say Y here, it will be possible to remotely debug the kernel - using gdb. This enlarges your kernel ELF image disk size by several - megabytes and requires a machine with more than 16 MB, better 32 MB - RAM to avoid excessive linking time. This is only useful for kernel - hackers. If unsure, say N. - - This is deprecated in favour of KGDB and will be removed in a later - version. - -config GDBSTUB_IMMEDIATE - bool "Break into GDB stub immediately" - depends on GDBSTUB - help - If you say Y here, GDB stub will break into the program as soon as - possible, leaving the program counter at the beginning of - start_kernel() in init/main.c. - -config GDBSTUB_ALLOW_SINGLE_STEP - bool "Allow software single-stepping in GDB stub" - depends on GDBSTUB && !SMP && !PREEMPT - help - Allow GDB stub to perform software single-stepping through the - kernel. This doesn't work very well on SMP or preemptible kernels as - it uses temporary breakpoints to emulate single-stepping. - -config GDB_CONSOLE - bool "Console output to GDB" - depends on GDBSTUB - help - If you are using GDB for remote debugging over a serial port and - would like kernel messages to be formatted into GDB $O packets so - that GDB prints them as program output, say 'Y'. - -config GDBSTUB_DEBUGGING - bool "Debug GDB stub by messages to serial port" - depends on GDBSTUB - help - This causes debugging messages to be displayed at various points - during execution of the GDB stub routines. Such messages will be - displayed on ttyS0 if that isn't the GDB stub's port, or ttySM0 - otherwise. - -config GDBSTUB_DEBUG_ENTRY - bool "Debug GDB stub entry" - depends on GDBSTUB_DEBUGGING - help - This option causes information to be displayed about entry to or exit - from the main GDB stub routine. - -config GDBSTUB_DEBUG_PROTOCOL - bool "Debug GDB stub protocol" - depends on GDBSTUB_DEBUGGING - help - This option causes information to be displayed about the GDB remote - protocol messages generated exchanged with GDB. - -config GDBSTUB_DEBUG_IO - bool "Debug GDB stub I/O" - depends on GDBSTUB_DEBUGGING - help - This option causes information to be displayed about GDB stub's - low-level I/O. - -config GDBSTUB_DEBUG_BREAKPOINT - bool "Debug GDB stub breakpoint management" - depends on GDBSTUB_DEBUGGING - help - This option causes information to be displayed about GDB stub's - breakpoint management. - -choice - prompt "GDB stub port" - default GDBSTUB_ON_TTYSM0 - depends on GDBSTUB - help - Select the serial port used for GDB-stub. - -config GDBSTUB_ON_TTYSM0 - bool "/dev/ttySM0 [SIF0]" - depends on MN10300_TTYSM0 - select GDBSTUB_ON_TTYSMx - -config GDBSTUB_ON_TTYSM1 - bool "/dev/ttySM1 [SIF1]" - depends on MN10300_TTYSM1 - select GDBSTUB_ON_TTYSMx - -config GDBSTUB_ON_TTYSM2 - bool "/dev/ttySM2 [SIF2]" - depends on MN10300_TTYSM2 - select GDBSTUB_ON_TTYSMx - -config GDBSTUB_ON_TTYS0 - bool "/dev/ttyS0" - select GDBSTUB_ON_TTYSx - -config GDBSTUB_ON_TTYS1 - bool "/dev/ttyS1" - select GDBSTUB_ON_TTYSx - -endchoice - -config GDBSTUB_ON_TTYSMx - bool - depends on GDBSTUB_ON_TTYSM0 || GDBSTUB_ON_TTYSM1 || GDBSTUB_ON_TTYSM2 - default y - -config GDBSTUB_ON_TTYSx - bool - depends on GDBSTUB_ON_TTYS0 || GDBSTUB_ON_TTYS1 - default y - -endmenu - -config KERNEL_DEBUGGER - def_bool y - depends on GDBSTUB || KGDB diff --git a/arch/mn10300/Makefile b/arch/mn10300/Makefile deleted file mode 100644 index 3f1ea5ddc402..000000000000 --- a/arch/mn10300/Makefile +++ /dev/null @@ -1,99 +0,0 @@ -############################################################################### -# -# MN10300 Kernel makefile system specifications -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Modified by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### - -KBUILD_DEFCONFIG := asb2303_defconfig - -CCSPECS := $(shell $(CC) -v 2>&1 | grep "^Reading specs from " | head -1 | cut -c20-) -CCDIR := $(strip $(patsubst %/specs,%,$(CCSPECS))) -KBUILD_CPPFLAGS += -nostdinc -I$(CCDIR)/include - -LDFLAGS := -OBJCOPYFLAGS := -O binary -R .note -R .comment -R .GCC-command-line -R .note.gnu.build-id -S -#LDFLAGS_vmlinux := -Map linkmap.txt -CHECKFLAGS += - -PROCESSOR := unset -UNIT := unset - -KBUILD_CFLAGS += -mam33 -DCPU=AM33 $(call cc-option,-mmem-funcs,) -KBUILD_AFLAGS += -mam33 -DCPU=AM33 - -ifeq ($(CONFIG_MN10300_CURRENT_IN_E2),y) -KBUILD_CFLAGS += -ffixed-e2 -fcall-saved-e5 -endif - -ifeq ($(CONFIG_MN10300_PROC_MN103E010),y) -PROCESSOR := mn103e010 -endif -ifeq ($(CONFIG_MN10300_PROC_MN2WS0050),y) -PROCESSOR := mn2ws0050 -endif - -ifeq ($(CONFIG_MN10300_UNIT_ASB2303),y) -UNIT := asb2303 -endif -ifeq ($(CONFIG_MN10300_UNIT_ASB2305),y) -UNIT := asb2305 -endif -ifeq ($(CONFIG_MN10300_UNIT_ASB2364),y) -UNIT := asb2364 -endif - - -head-y := arch/mn10300/kernel/head.o - -core-y += arch/mn10300/kernel/ arch/mn10300/mm/ - -ifneq ($(PROCESSOR),unset) -core-y += arch/mn10300/proc-$(PROCESSOR)/ -endif -ifneq ($(UNIT),unset) -core-y += arch/mn10300/unit-$(UNIT)/ -endif -libs-y += arch/mn10300/lib/ - -drivers-$(CONFIG_OPROFILE) += arch/mn10300/oprofile/ - -boot := arch/mn10300/boot - -.PHONY: zImage - -KBUILD_IMAGE := $(boot)/zImage -CLEAN_FILES += $(boot)/zImage -CLEAN_FILES += $(boot)/compressed/vmlinux -CLEAN_FILES += $(boot)/compressed/vmlinux.bin -CLEAN_FILES += $(boot)/compressed/vmlinux.bin.gz - -zImage: vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ - -all: zImage - -bootstrap: - $(Q)$(MAKEBOOT) bootstrap - -archclean: - $(Q)$(MAKE) $(clean)=arch/mn10300/proc-mn103e010 - $(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2303 - $(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2305 - -define archhelp - echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)' -endef - -# -# include the appropriate processor- and unit-specific headers -# -KBUILD_CPPFLAGS += -I$(srctree)/arch/mn10300/proc-$(PROCESSOR)/include -KBUILD_CPPFLAGS += -I$(srctree)/arch/mn10300/unit-$(UNIT)/include diff --git a/arch/mn10300/boot/.gitignore b/arch/mn10300/boot/.gitignore deleted file mode 100644 index b6718de23693..000000000000 --- a/arch/mn10300/boot/.gitignore +++ /dev/null @@ -1 +0,0 @@ -zImage diff --git a/arch/mn10300/boot/Makefile b/arch/mn10300/boot/Makefile deleted file mode 100644 index 36c9caf8ea0a..000000000000 --- a/arch/mn10300/boot/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# MN10300 kernel compressor and wrapper -# -# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# - -targets := vmlinux.bin zImage - -subdir- := compressed - -# --------------------------------------------------------------------------- - - -$(obj)/zImage: $(obj)/compressed/vmlinux FORCE - $(call if_changed,objcopy) - @echo 'Kernel: $@ is ready' - -$(obj)/vmlinux.bin: $(obj)/compressed/vmlinux FORCE - $(call if_changed,objcopy) - -$(obj)/compressed/vmlinux: FORCE - $(Q)$(MAKE) $(build)=$(obj)/compressed IMAGE_OFFSET=$(IMAGE_OFFSET) $@ diff --git a/arch/mn10300/boot/compressed/Makefile b/arch/mn10300/boot/compressed/Makefile deleted file mode 100644 index 9b9a48fc8e53..000000000000 --- a/arch/mn10300/boot/compressed/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Create a compressed vmlinux image from the original vmlinux -# - -targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o - -LDFLAGS_vmlinux := -Ttext $(CONFIG_KERNEL_ZIMAGE_BASE_ADDRESS) -e startup_32 - -$(obj)/vmlinux: $(obj)/head.o $(obj)/misc.o $(obj)/piggy.o FORCE - $(call if_changed,ld) - -$(obj)/vmlinux.bin: vmlinux FORCE - $(call if_changed,objcopy) - -$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE - $(call if_changed,gzip) - -LDFLAGS_piggy.o := -r --format binary --oformat elf32-am33lin -T - -$(obj)/piggy.o: $(obj)/vmlinux.lds $(obj)/vmlinux.bin.gz FORCE - $(call if_changed,ld) diff --git a/arch/mn10300/boot/compressed/head.S b/arch/mn10300/boot/compressed/head.S deleted file mode 100644 index 7b50345b9e84..000000000000 --- a/arch/mn10300/boot/compressed/head.S +++ /dev/null @@ -1,151 +0,0 @@ -/* Boot entry point for a compressed MN10300 kernel - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - .section .text - -#define DEBUG - -#include -#include -#include -#ifdef CONFIG_SMP -#include -#endif - - .globl startup_32 -startup_32: -#ifdef CONFIG_SMP - # - # Secondary CPUs jump directly to the kernel entry point - # - # Must save primary CPU's D0-D2 registers as they hold boot parameters - # - mov (CPUID), d3 - and CPUID_MASK,d3 - beq startup_primary - mov CONFIG_KERNEL_TEXT_ADDRESS,a0 - jmp (a0) - -startup_primary: -#endif /* CONFIG_SMP */ - - # first save parameters from bootloader - mov param_save_area,a0 - mov d0,(a0) - mov d1,(4,a0) - mov d2,(8,a0) - - mov sp,a3 - mov decomp_stack+0x2000-4,a0 - mov a0,sp - - # invalidate and enable both of the caches - mov CHCTR,a0 - clr d0 - movhu d0,(a0) # turn off first - mov CHCTR_ICINV|CHCTR_DCINV,d0 - movhu d0,(a0) - setlb - mov (a0),d0 - btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy - lne - -#ifdef CONFIG_MN10300_CACHE_ENABLED -#ifdef CONFIG_MN10300_CACHE_WBACK - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 -#else - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 -#endif /* WBACK */ - movhu d0,(a0) # enable -#endif /* !ENABLED */ - - # clear the BSS area - mov __bss_start,a0 - mov _end,a1 - clr d0 -bssclear: - cmp a1,a0 - bge bssclear_end - movbu d0,(a0) - inc a0 - bra bssclear -bssclear_end: - - # decompress the kernel - call decompress_kernel[],0 -#ifdef CONFIG_MN10300_CACHE_WBACK - call mn10300_dcache_flush_inv[],0 -#endif - - # disable caches again - mov CHCTR,a0 - clr d0 - movhu d0,(a0) - setlb - mov (a0),d0 - btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy - lne - - mov param_save_area,a0 - mov (a0),d0 - mov (4,a0),d1 - mov (8,a0),d2 - - # jump to the kernel proper entry point - mov a3,sp - mov CONFIG_KERNEL_TEXT_ADDRESS,a0 - jmp (a0) - - -############################################################################### -# -# Cache flush routines -# -############################################################################### -#ifdef CONFIG_MN10300_CACHE_WBACK -mn10300_dcache_flush_inv: - movhu (CHCTR),d0 - btst CHCTR_DCEN,d0 - beq mn10300_dcache_flush_inv_end - - mov L1_CACHE_NENTRIES,d1 - clr a1 - -mn10300_dcache_flush_inv_loop: - mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge - mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge - mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge - mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge - - add L1_CACHE_BYTES,a1 - add -1,d1 - bne mn10300_dcache_flush_inv_loop - -mn10300_dcache_flush_inv_end: - ret [],0 -#endif /* CONFIG_MN10300_CACHE_WBACK */ - - -############################################################################### -# -# Data areas -# -############################################################################### - .data - .align 4 -param_save_area: - .rept 3 - .word 0 - .endr - - .section .bss - .align 4 -decomp_stack: - .space 0x2000 diff --git a/arch/mn10300/boot/compressed/misc.c b/arch/mn10300/boot/compressed/misc.c deleted file mode 100644 index 42cbd77bd439..000000000000 --- a/arch/mn10300/boot/compressed/misc.c +++ /dev/null @@ -1,393 +0,0 @@ -/* MN10300 Miscellaneous helper routines for kernel decompressor - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - Derived from arch/x86/boot/compressed/misc_32.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include "misc.h" - -#ifndef CONFIG_GDBSTUB_ON_TTYSx -/* display 'Uncompressing Linux... ' messages on ttyS0 or ttyS1 */ -#if 1 /* ttyS0 */ -#define CYG_DEV_BASE 0xA6FB0000 -#else /* ttyS1 */ -#define CYG_DEV_BASE 0xA6FC0000 -#endif - -#define CYG_DEV_THR (*((volatile __u8*)(CYG_DEV_BASE + 0x00))) -#define CYG_DEV_MCR (*((volatile __u8*)(CYG_DEV_BASE + 0x10))) -#define SIO_MCR_DTR 0x01 -#define SIO_MCR_RTS 0x02 -#define CYG_DEV_LSR (*((volatile __u8*)(CYG_DEV_BASE + 0x14))) -#define SIO_LSR_THRE 0x20 /* transmitter holding register empty */ -#define SIO_LSR_TEMT 0x40 /* transmitter register empty */ -#define CYG_DEV_MSR (*((volatile __u8*)(CYG_DEV_BASE + 0x18))) -#define SIO_MSR_CTS 0x10 /* clear to send */ -#define SIO_MSR_DSR 0x20 /* data set ready */ - -#define LSR_WAIT_FOR(STATE) \ - do { while (!(CYG_DEV_LSR & SIO_LSR_##STATE)) {} } while (0) -#define FLOWCTL_QUERY(LINE) \ - ({ CYG_DEV_MSR & SIO_MSR_##LINE; }) -#define FLOWCTL_WAIT_FOR(LINE) \ - do { while (!(CYG_DEV_MSR & SIO_MSR_##LINE)) {} } while (0) -#define FLOWCTL_CLEAR(LINE) \ - do { CYG_DEV_MCR &= ~SIO_MCR_##LINE; } while (0) -#define FLOWCTL_SET(LINE) \ - do { CYG_DEV_MCR |= SIO_MCR_##LINE; } while (0) -#endif - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -#undef memset -#undef memcpy - -static inline void *memset(const void *s, int c, size_t n) -{ - int i; - char *ss = (char *) s; - - for (i = 0; i < n; i++) - ss[i] = c; - return (void *)s; -} - -#define memzero(s, n) memset((s), 0, (n)) - -static inline void *memcpy(void *__dest, const void *__src, size_t __n) -{ - int i; - const char *s = __src; - char *d = __dest; - - for (i = 0; i < __n; i++) - d[i] = s[i]; - return __dest; -} - -typedef unsigned char uch; -typedef unsigned short ush; -typedef unsigned long ulg; - -#define WSIZE 0x8000 /* Window size must be at least 32k, and a power of - * two */ - -static uch *inbuf; /* input buffer */ -static uch window[WSIZE]; /* sliding window buffer */ - -static unsigned insize; /* valid bytes in inbuf */ -static unsigned inptr; /* index of next byte to be processed in inbuf */ -static unsigned outcnt; /* bytes in output buffer */ - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -/* Diagnostic functions */ -#ifdef DEBUG -# define Assert(cond, msg) { if (!(cond)) error(msg); } -# define Trace(x) fprintf x -# define Tracev(x) { if (verbose) fprintf x ; } -# define Tracevv(x) { if (verbose > 1) fprintf x ; } -# define Tracec(c, x) { if (verbose && (c)) fprintf x ; } -# define Tracecv(c, x) { if (verbose > 1 && (c)) fprintf x ; } -#else -# define Assert(cond, msg) -# define Trace(x) -# define Tracev(x) -# define Tracevv(x) -# define Tracec(c, x) -# define Tracecv(c, x) -#endif - -static int fill_inbuf(void); -static void flush_window(void); -static void error(const char *) __attribute__((noreturn)); -static void kputs(const char *); - -static inline unsigned char get_byte(void) -{ - unsigned char ch = inptr < insize ? inbuf[inptr++] : fill_inbuf(); - -#if 0 - char hex[3]; - hex[0] = ((ch & 0x0f) > 9) ? - ((ch & 0x0f) + 'A' - 0xa) : ((ch & 0x0f) + '0'); - hex[1] = ((ch >> 4) > 9) ? - ((ch >> 4) + 'A' - 0xa) : ((ch >> 4) + '0'); - hex[2] = 0; - kputs(hex); -#endif - return ch; -} - -/* - * This is set up by the setup-routine at boot-time - */ -#define EXT_MEM_K (*(unsigned short *)0x90002) -#ifndef STANDARD_MEMORY_BIOS_CALL -#define ALT_MEM_K (*(unsigned long *) 0x901e0) -#endif -#define SCREEN_INFO (*(struct screen_info *)0x90000) - -static long bytes_out; -static uch *output_data; -static unsigned long output_ptr; - - -static unsigned long free_mem_ptr = (unsigned long) &end; -static unsigned long free_mem_end_ptr = (unsigned long) &end + 0x90000; - -#define INPLACE_MOVE_ROUTINE 0x1000 -#define LOW_BUFFER_START 0x2000 -#define LOW_BUFFER_END 0x90000 -#define LOW_BUFFER_SIZE (LOW_BUFFER_END - LOW_BUFFER_START) -#define HEAP_SIZE 0x3000 -static int high_loaded; -static uch *high_buffer_start /* = (uch *)(((ulg)&end) + HEAP_SIZE)*/; - -static char *vidmem = (char *)0xb8000; -static int lines, cols; - -#define BOOTLOADER_INFLATE -#include "../../../../lib/inflate.c" - -static inline void scroll(void) -{ - int i; - - memcpy(vidmem, vidmem + cols * 2, (lines - 1) * cols * 2); - for (i = (lines - 1) * cols * 2; i < lines * cols * 2; i += 2) - vidmem[i] = ' '; -} - -static inline void kputchar(unsigned char ch) -{ -#ifdef CONFIG_MN10300_UNIT_ASB2305 - while (SC0STR & SC01STR_TBF) - continue; - - if (ch == 0x0a) { - SC0TXB = 0x0d; - while (SC0STR & SC01STR_TBF) - continue; - } - - SC0TXB = ch; - -#else - while (SC1STR & SC01STR_TBF) - continue; - - if (ch == 0x0a) { - SC1TXB = 0x0d; - while (SC1STR & SC01STR_TBF) - continue; - } - - SC1TXB = ch; - -#endif -} - -static void kputs(const char *s) -{ -#ifdef CONFIG_DEBUG_DECOMPRESS_KERNEL -#ifndef CONFIG_GDBSTUB_ON_TTYSx - char ch; - - FLOWCTL_SET(DTR); - - while (*s) { - LSR_WAIT_FOR(THRE); - - ch = *s++; - if (ch == 0x0a) { - CYG_DEV_THR = 0x0d; - LSR_WAIT_FOR(THRE); - } - CYG_DEV_THR = ch; - } - - FLOWCTL_CLEAR(DTR); -#else - - for (; *s; s++) - kputchar(*s); - -#endif -#endif /* CONFIG_DEBUG_DECOMPRESS_KERNEL */ -} - -/* =========================================================================== - * Fill the input buffer. This is called only when the buffer is empty - * and at least one byte is really needed. - */ -static int fill_inbuf() -{ - if (insize != 0) - error("ran out of input data\n"); - - inbuf = input_data; - insize = input_len; - inptr = 1; - return inbuf[0]; -} - -/* =========================================================================== - * Write the output window window[0..outcnt-1] and update crc and bytes_out. - * (Used for the decompressed data only.) - */ -static void flush_window_low(void) -{ - ulg c = crc; /* temporary variable */ - unsigned n; - uch *in, *out, ch; - - in = window; - out = &output_data[output_ptr]; - for (n = 0; n < outcnt; n++) { - ch = *out++ = *in++; - c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; -} - -static void flush_window_high(void) -{ - ulg c = crc; /* temporary variable */ - unsigned n; - uch *in, ch; - in = window; - for (n = 0; n < outcnt; n++) { - ch = *output_data++ = *in++; - if ((ulg) output_data == LOW_BUFFER_END) - output_data = high_buffer_start; - c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - outcnt = 0; -} - -static void flush_window(void) -{ - if (high_loaded) - flush_window_high(); - else - flush_window_low(); -} - -static void error(const char *x) -{ - kputs("\n\n"); - kputs(x); - kputs("\n\n -- System halted"); - - while (1) - /* Halt */; -} - -#define STACK_SIZE (4096) - -long user_stack[STACK_SIZE]; - -struct { - long *a; - short b; -} stack_start = { &user_stack[STACK_SIZE], 0 }; - -void setup_normal_output_buffer(void) -{ -#ifdef STANDARD_MEMORY_BIOS_CALL - if (EXT_MEM_K < 1024) - error("Less than 2MB of memory.\n"); -#else - if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < 1024) - error("Less than 2MB of memory.\n"); -#endif - output_data = (char *) 0x100000; /* Points to 1M */ -} - -struct moveparams { - uch *low_buffer_start; - int lcount; - uch *high_buffer_start; - int hcount; -}; - -void setup_output_buffer_if_we_run_high(struct moveparams *mv) -{ - high_buffer_start = (uch *)(((ulg) &end) + HEAP_SIZE); -#ifdef STANDARD_MEMORY_BIOS_CALL - if (EXT_MEM_K < (3 * 1024)) - error("Less than 4MB of memory.\n"); -#else - if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < (3 * 1024)) - error("Less than 4MB of memory.\n"); -#endif - mv->low_buffer_start = output_data = (char *) LOW_BUFFER_START; - high_loaded = 1; - free_mem_end_ptr = (long) high_buffer_start; - if (0x100000 + LOW_BUFFER_SIZE > (ulg) high_buffer_start) { - high_buffer_start = (uch *)(0x100000 + LOW_BUFFER_SIZE); - mv->hcount = 0; /* say: we need not to move high_buffer */ - } else { - mv->hcount = -1; - } - mv->high_buffer_start = high_buffer_start; -} - -void close_output_buffer_if_we_run_high(struct moveparams *mv) -{ - mv->lcount = bytes_out; - if (bytes_out > LOW_BUFFER_SIZE) { - mv->lcount = LOW_BUFFER_SIZE; - if (mv->hcount) - mv->hcount = bytes_out - LOW_BUFFER_SIZE; - } else { - mv->hcount = 0; - } -} - -#undef DEBUGFLAG -#ifdef DEBUGFLAG -int debugflag; -#endif - -int decompress_kernel(struct moveparams *mv) -{ -#ifdef DEBUGFLAG - while (!debugflag) - barrier(); -#endif - - output_data = (char *) CONFIG_KERNEL_TEXT_ADDRESS; - - makecrc(); - kputs("Uncompressing Linux... "); - gunzip(); - kputs("Ok, booting the kernel.\n"); - return 0; -} diff --git a/arch/mn10300/boot/compressed/misc.h b/arch/mn10300/boot/compressed/misc.h deleted file mode 100644 index da921cd172fb..000000000000 --- a/arch/mn10300/boot/compressed/misc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Internal definitions for the MN10300 kernel decompressor - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -extern int end; - -/* - * vmlinux.lds - */ -extern char input_data[]; -extern int input_len; diff --git a/arch/mn10300/boot/compressed/vmlinux.lds b/arch/mn10300/boot/compressed/vmlinux.lds deleted file mode 100644 index a084903603fe..000000000000 --- a/arch/mn10300/boot/compressed/vmlinux.lds +++ /dev/null @@ -1,9 +0,0 @@ -SECTIONS -{ - .data : { - input_len = .; - LONG(input_data_end - input_data) input_data = .; - *(.data) - input_data_end = .; - } -} diff --git a/arch/mn10300/boot/install.sh b/arch/mn10300/boot/install.sh deleted file mode 100644 index abba30971191..000000000000 --- a/arch/mn10300/boot/install.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh -# -# arch/mn10300/boot/install -c.sh -# -# This file is subject to the terms and conditions of the GNU General Public -# Licence. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 1995 by Linus Torvalds -# -# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin -# -# "make install -c" script for i386 architecture -# -# Arguments: -# $1 - kernel version -# $2 - kernel image file -# $3 - kernel map file -# $4 - default install -c path (blank if root directory) -# $5 - boot rom file -# - -# User may have a custom install -c script - -rm -fr $4/../usr/include/linux $4/../usr/include/asm -install -c -m 0755 $2 $4/vmlinuz -install -c -m 0755 $5 $4/boot.rom -install -c -m 0755 -d $4/../usr/include/linux -cd ${srctree}/include/linux -for i in `find . -maxdepth 1 -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/linux -done -install -c -m 0755 -d $4/../usr/include/linux/byteorder -cd ${srctree}/include/linux/byteorder -for i in `find . -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/linux/byteorder -done -install -c -m 0755 -d $4/../usr/include/linux/lockd -cd ${srctree}/include/linux/lockd -for i in `find . -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/linux/lockd -done -install -c -m 0755 -d $4/../usr/include/linux/netfilter_ipv4 -cd ${srctree}/include/linux/netfilter_ipv4 -for i in `find . -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/linux/netfilter_ipv4 -done -install -c -m 0755 -d $4/../usr/include/linux/nfsd -cd ${srctree}/include/linux/nfsd -for i in `find . -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/linux/nfsd/$i -done -install -c -m 0755 -d $4/../usr/include/linux/raid -cd ${srctree}/include/linux/raid -for i in `find . -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/linux/raid -done -install -c -m 0755 -d $4/../usr/include/linux/sunrpc -cd ${srctree}/include/linux/sunrpc -for i in `find . -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/linux/sunrpc -done -install -c -m 0755 -d $4/../usr/include/asm -cd ${srctree}/include/asm -for i in `find . -name '*.h' -print`; do - install -c -m 0644 $i $4/../usr/include/asm -done diff --git a/arch/mn10300/boot/tools/build.c b/arch/mn10300/boot/tools/build.c deleted file mode 100644 index 3ce158fe07b0..000000000000 --- a/arch/mn10300/boot/tools/build.c +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright (C) 1997 Martin Mares - */ - -/* - * This file builds a disk-image from three different files: - * - * - bootsect: exactly 512 bytes of 8086 machine code, loads the rest - * - setup: 8086 machine code, sets up system parm - * - system: 80386 code for actual system - * - * It does some checking that all files are of the correct type, and - * just writes the result to stdout, removing headers and padding to - * the right amount. It also writes some system data to stderr. - */ - -/* - * Changes by tytso to allow root device specification - * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996 - * Cross compiling fixes by Gertjan van Wingerde, July 1996 - * Rewritten by Martin Mares, April 1997 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DEFAULT_MAJOR_ROOT 0 -#define DEFAULT_MINOR_ROOT 0 - -/* Minimal number of setup sectors (see also bootsect.S) */ -#define SETUP_SECTS 4 - -uint8_t buf[1024]; -int fd; -int is_big_kernel; - -__attribute__((noreturn)) -void die(const char *str, ...) -{ - va_list args; - va_start(args, str); - vfprintf(stderr, str, args); - fputc('\n', stderr); - exit(1); -} - -void file_open(const char *name) -{ - fd = open(name, O_RDONLY, 0); - if (fd < 0) - die("Unable to open `%s': %m", name); -} - -__attribute__((noreturn)) -void usage(void) -{ - die("Usage: build [-b] bootsect setup system [rootdev] [> image]"); -} - -int main(int argc, char **argv) -{ - unsigned int i, c, sz, setup_sectors; - uint32_t sys_size; - uint8_t major_root, minor_root; - struct stat sb; - - if (argc > 2 && !strcmp(argv[1], "-b")) { - is_big_kernel = 1; - argc--, argv++; - } - if ((argc < 4) || (argc > 5)) - usage(); - if (argc > 4) { - if (!strcmp(argv[4], "CURRENT")) { - if (stat("/", &sb)) { - perror("/"); - die("Couldn't stat /"); - } - major_root = major(sb.st_dev); - minor_root = minor(sb.st_dev); - } else if (strcmp(argv[4], "FLOPPY")) { - if (stat(argv[4], &sb)) { - perror(argv[4]); - die("Couldn't stat root device."); - } - major_root = major(sb.st_rdev); - minor_root = minor(sb.st_rdev); - } else { - major_root = 0; - minor_root = 0; - } - } else { - major_root = DEFAULT_MAJOR_ROOT; - minor_root = DEFAULT_MINOR_ROOT; - } - fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root); - - file_open(argv[1]); - i = read(fd, buf, sizeof(buf)); - fprintf(stderr, "Boot sector %d bytes.\n", i); - if (i != 512) - die("Boot block must be exactly 512 bytes"); - if (buf[510] != 0x55 || buf[511] != 0xaa) - die("Boot block hasn't got boot flag (0xAA55)"); - buf[508] = minor_root; - buf[509] = major_root; - if (write(1, buf, 512) != 512) - die("Write call failed"); - close(fd); - - /* Copy the setup code */ - file_open(argv[2]); - for (i = 0; (c = read(fd, buf, sizeof(buf))) > 0; i += c) - if (write(1, buf, c) != c) - die("Write call failed"); - if (c != 0) - die("read-error on `setup'"); - close(fd); - - /* Pad unused space with zeros */ - setup_sectors = (i + 511) / 512; - /* for compatibility with ancient versions of LILO. */ - if (setup_sectors < SETUP_SECTS) - setup_sectors = SETUP_SECTS; - fprintf(stderr, "Setup is %d bytes.\n", i); - memset(buf, 0, sizeof(buf)); - while (i < setup_sectors * 512) { - c = setup_sectors * 512 - i; - if (c > sizeof(buf)) - c = sizeof(buf); - if (write(1, buf, c) != c) - die("Write call failed"); - i += c; - } - - file_open(argv[3]); - if (fstat(fd, &sb)) - die("Unable to stat `%s': %m", argv[3]); - sz = sb.st_size; - fprintf(stderr, "System is %d kB\n", sz / 1024); - sys_size = (sz + 15) / 16; - /* 0x28000*16 = 2.5 MB, conservative estimate for the current maximum */ - if (sys_size > (is_big_kernel ? 0x28000 : DEF_SYSSIZE)) - die("System is too big. Try using %smodules.", - is_big_kernel ? "" : "bzImage or "); - if (sys_size > 0xffff) - fprintf(stderr, - "warning: kernel is too big for standalone boot " - "from floppy\n"); - while (sz > 0) { - int l, n; - - l = (sz > sizeof(buf)) ? sizeof(buf) : sz; - n = read(fd, buf, l); - if (n != l) { - if (n < 0) - die("Error reading %s: %m", argv[3]); - else - die("%s: Unexpected EOF", argv[3]); - } - if (write(1, buf, l) != l) - die("Write failed"); - sz -= l; - } - close(fd); - - /* Write sizes to the bootsector */ - if (lseek(1, 497, SEEK_SET) != 497) - die("Output: seek failed"); - buf[0] = setup_sectors; - if (write(1, buf, 1) != 1) - die("Write of setup sector count failed"); - if (lseek(1, 500, SEEK_SET) != 500) - die("Output: seek failed"); - buf[0] = (sys_size & 0xff); - buf[1] = ((sys_size >> 8) & 0xff); - if (write(1, buf, 2) != 2) - die("Write of image length failed"); - - return 0; -} diff --git a/arch/mn10300/configs/asb2303_defconfig b/arch/mn10300/configs/asb2303_defconfig deleted file mode 100644 index d06dae131139..000000000000 --- a/arch/mn10300/configs/asb2303_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_HOTPLUG is not set -# CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y -CONFIG_PROFILING=y -# CONFIG_BLOCK is not set -CONFIG_PREEMPT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_MN10300_RTC=y -CONFIG_MN10300_TTYSM_CONSOLE=y -CONFIG_MN10300_TTYSM0=y -CONFIG_MN10300_TTYSM1=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_I4=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -# CONFIG_HW_RANDOM is not set -CONFIG_RTC=y -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_PROC_KCORE=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_STRIP_ASM_SYMS=y diff --git a/arch/mn10300/configs/asb2364_defconfig b/arch/mn10300/configs/asb2364_defconfig deleted file mode 100644 index a84c3153f22a..000000000000 --- a/arch/mn10300/configs/asb2364_defconfig +++ /dev/null @@ -1,87 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CGROUPS=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_RELAY=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_SLAB=y -CONFIG_PROFILING=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLOCK is not set -CONFIG_MN10300_UNIT_ASB2364=y -CONFIG_PREEMPT=y -# CONFIG_MN10300_USING_JTAG is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_MN10300_TTYSM_CONSOLE=y -CONFIG_MN10300_TTYSM0=y -CONFIG_MN10300_TTYSM0_TIMER2=y -CONFIG_MN10300_TTYSM1=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -CONFIG_CONNECTOR=y -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_I4=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_PROC_KCORE=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y diff --git a/arch/mn10300/include/asm/Kbuild b/arch/mn10300/include/asm/Kbuild deleted file mode 100644 index 509c45a75d1f..000000000000 --- a/arch/mn10300/include/asm/Kbuild +++ /dev/null @@ -1,13 +0,0 @@ - -generic-y += barrier.h -generic-y += device.h -generic-y += exec.h -generic-y += extable.h -generic-y += fb.h -generic-y += irq_work.h -generic-y += mcs_spinlock.h -generic-y += mm-arch-hooks.h -generic-y += preempt.h -generic-y += sections.h -generic-y += trace_clock.h -generic-y += word-at-a-time.h diff --git a/arch/mn10300/include/asm/asm-offsets.h b/arch/mn10300/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/arch/mn10300/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/atomic.h b/arch/mn10300/include/asm/atomic.h deleted file mode 100644 index 36389efd45e8..000000000000 --- a/arch/mn10300/include/asm/atomic.h +++ /dev/null @@ -1,161 +0,0 @@ -/* MN10300 Atomic counter operations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_ATOMIC_H -#define _ASM_ATOMIC_H - -#include -#include -#include - -#ifndef CONFIG_SMP -#include -#else - -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - */ - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ - -/** - * atomic_read - read atomic variable - * @v: pointer of type atomic_t - * - * Atomically reads the value of @v. Note that the guaranteed - */ -#define atomic_read(v) READ_ONCE((v)->counter) - -/** - * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value - * - * Atomically sets the value of @v to @i. Note that the guaranteed - */ -#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) - -#define ATOMIC_OP(op) \ -static inline void atomic_##op(int i, atomic_t *v) \ -{ \ - int retval, status; \ - \ - asm volatile( \ - "1: mov %4,(_AAR,%3) \n" \ - " mov (_ADR,%3),%1 \n" \ - " " #op " %5,%1 \n" \ - " mov %1,(_ADR,%3) \n" \ - " mov (_ADR,%3),%0 \n" /* flush */ \ - " mov (_ASR,%3),%0 \n" \ - " or %0,%0 \n" \ - " bne 1b \n" \ - : "=&r"(status), "=&r"(retval), "=m"(v->counter) \ - : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \ - : "memory", "cc"); \ -} - -#define ATOMIC_OP_RETURN(op) \ -static inline int atomic_##op##_return(int i, atomic_t *v) \ -{ \ - int retval, status; \ - \ - asm volatile( \ - "1: mov %4,(_AAR,%3) \n" \ - " mov (_ADR,%3),%1 \n" \ - " " #op " %5,%1 \n" \ - " mov %1,(_ADR,%3) \n" \ - " mov (_ADR,%3),%0 \n" /* flush */ \ - " mov (_ASR,%3),%0 \n" \ - " or %0,%0 \n" \ - " bne 1b \n" \ - : "=&r"(status), "=&r"(retval), "=m"(v->counter) \ - : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \ - : "memory", "cc"); \ - return retval; \ -} - -#define ATOMIC_FETCH_OP(op) \ -static inline int atomic_fetch_##op(int i, atomic_t *v) \ -{ \ - int retval, status; \ - \ - asm volatile( \ - "1: mov %4,(_AAR,%3) \n" \ - " mov (_ADR,%3),%1 \n" \ - " mov %1,%0 \n" \ - " " #op " %5,%0 \n" \ - " mov %0,(_ADR,%3) \n" \ - " mov (_ADR,%3),%0 \n" /* flush */ \ - " mov (_ASR,%3),%0 \n" \ - " or %0,%0 \n" \ - " bne 1b \n" \ - : "=&r"(status), "=&r"(retval), "=m"(v->counter) \ - : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \ - : "memory", "cc"); \ - return retval; \ -} - -#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op) - -ATOMIC_OPS(add) -ATOMIC_OPS(sub) - -#undef ATOMIC_OPS -#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) - -ATOMIC_OPS(and) -ATOMIC_OPS(or) -ATOMIC_OPS(xor) - -#undef ATOMIC_OPS -#undef ATOMIC_FETCH_OP -#undef ATOMIC_OP_RETURN -#undef ATOMIC_OP - -static inline int atomic_add_negative(int i, atomic_t *v) -{ - return atomic_add_return(i, v) < 0; -} - -static inline void atomic_inc(atomic_t *v) -{ - atomic_add_return(1, v); -} - -static inline void atomic_dec(atomic_t *v) -{ - atomic_sub_return(1, v); -} - -#define atomic_dec_return(v) atomic_sub_return(1, (v)) -#define atomic_inc_return(v) atomic_add_return(1, (v)) - -#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) -#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) -#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) - -#define __atomic_add_unless(v, a, u) \ -({ \ - int c, old; \ - c = atomic_read(v); \ - while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ - c = old; \ - c; \ -}) - -#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v))) -#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new))) - -#endif /* __KERNEL__ */ -#endif /* CONFIG_SMP */ -#endif /* _ASM_ATOMIC_H */ diff --git a/arch/mn10300/include/asm/bitops.h b/arch/mn10300/include/asm/bitops.h deleted file mode 100644 index fe6f8e2c3617..000000000000 --- a/arch/mn10300/include/asm/bitops.h +++ /dev/null @@ -1,232 +0,0 @@ -/* MN10300 bit operations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - * - * These have to be done with inline assembly: that way the bit-setting - * is guaranteed to be atomic. All bit operations return 0 if the bit - * was cleared before the operation and != 0 if it was not. - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - */ -#ifndef __ASM_BITOPS_H -#define __ASM_BITOPS_H - -#include -#include - -/* - * set bit - */ -#define __set_bit(nr, addr) \ -({ \ - volatile unsigned char *_a = (unsigned char *)(addr); \ - const unsigned shift = (nr) & 7; \ - _a += (nr) >> 3; \ - \ - asm volatile("bset %2,(%1) # set_bit reg" \ - : "=m"(*_a) \ - : "a"(_a), "d"(1 << shift), "m"(*_a) \ - : "memory", "cc"); \ -}) - -#define set_bit(nr, addr) __set_bit((nr), (addr)) - -/* - * clear bit - */ -#define ___clear_bit(nr, addr) \ -({ \ - volatile unsigned char *_a = (unsigned char *)(addr); \ - const unsigned shift = (nr) & 7; \ - _a += (nr) >> 3; \ - \ - asm volatile("bclr %2,(%1) # clear_bit reg" \ - : "=m"(*_a) \ - : "a"(_a), "d"(1 << shift), "m"(*_a) \ - : "memory", "cc"); \ -}) - -#define clear_bit(nr, addr) ___clear_bit((nr), (addr)) - - -static inline void __clear_bit(unsigned long nr, volatile void *addr) -{ - unsigned int *a = (unsigned int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a &= ~mask; -} - -/* - * test bit - */ -static inline int test_bit(unsigned long nr, const volatile void *addr) -{ - return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31)); -} - -/* - * change bit - */ -static inline void __change_bit(unsigned long nr, volatile void *addr) -{ - int mask; - unsigned int *a = (unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a ^= mask; -} - -extern void change_bit(unsigned long nr, volatile void *addr); - -/* - * test and set bit - */ -#define __test_and_set_bit(nr,addr) \ -({ \ - volatile unsigned char *_a = (unsigned char *)(addr); \ - const unsigned shift = (nr) & 7; \ - unsigned epsw; \ - _a += (nr) >> 3; \ - \ - asm volatile("bset %3,(%2) # test_set_bit reg\n" \ - "mov epsw,%1" \ - : "=m"(*_a), "=d"(epsw) \ - : "a"(_a), "d"(1 << shift), "m"(*_a) \ - : "memory", "cc"); \ - \ - !(epsw & EPSW_FLAG_Z); \ -}) - -#define test_and_set_bit(nr, addr) __test_and_set_bit((nr), (addr)) - -/* - * test and clear bit - */ -#define __test_and_clear_bit(nr, addr) \ -({ \ - volatile unsigned char *_a = (unsigned char *)(addr); \ - const unsigned shift = (nr) & 7; \ - unsigned epsw; \ - _a += (nr) >> 3; \ - \ - asm volatile("bclr %3,(%2) # test_clear_bit reg\n" \ - "mov epsw,%1" \ - : "=m"(*_a), "=d"(epsw) \ - : "a"(_a), "d"(1 << shift), "m"(*_a) \ - : "memory", "cc"); \ - \ - !(epsw & EPSW_FLAG_Z); \ -}) - -#define test_and_clear_bit(nr, addr) __test_and_clear_bit((nr), (addr)) - -/* - * test and change bit - */ -static inline int __test_and_change_bit(unsigned long nr, volatile void *addr) -{ - int mask, retval; - unsigned int *a = (unsigned int *)addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - - return retval; -} - -extern int test_and_change_bit(unsigned long nr, volatile void *addr); - -#include - -#ifdef __KERNEL__ - -/** - * __ffs - find first bit set - * @x: the word to search - * - * - return 31..0 to indicate bit 31..0 most least significant bit set - * - if no bits are set in x, the result is undefined - */ -static inline __attribute__((const)) -unsigned long __ffs(unsigned long x) -{ - int bit; - asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x) : "cc"); - return bit; -} - -/* - * special slimline version of fls() for calculating ilog2_u32() - * - note: no protection against n == 0 - */ -static inline __attribute__((const)) -int __ilog2_u32(u32 n) -{ - int bit; - asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n) : "cc"); - return bit; -} - -/** - * fls - find last bit set - * @x: the word to search - * - * This is defined the same way as ffs: - * - return 32..1 to indicate bit 31..0 most significant bit set - * - return 0 to indicate no bits set - */ -static inline __attribute__((const)) -int fls(int x) -{ - return (x != 0) ? __ilog2_u32(x) + 1 : 0; -} - -/** - * __fls - find last (most-significant) set bit in a long word - * @word: the word to search - * - * Undefined if no set bit exists, so code should check against 0 first. - */ -static inline unsigned long __fls(unsigned long word) -{ - return __ilog2_u32(word); -} - -/** - * ffs - find first bit set - * @x: the word to search - * - * - return 32..1 to indicate bit 31..0 most least significant bit set - * - return 0 to indicate no bits set - */ -static inline __attribute__((const)) -int ffs(int x) -{ - /* Note: (x & -x) gives us a mask that is the least significant - * (rightmost) 1-bit of the value in x. - */ - return fls(x & -x); -} - -#include -#include -#include -#include -#include -#include -#include - -#endif /* __KERNEL__ */ -#endif /* __ASM_BITOPS_H */ diff --git a/arch/mn10300/include/asm/bug.h b/arch/mn10300/include/asm/bug.h deleted file mode 100644 index 811414fb002d..000000000000 --- a/arch/mn10300/include/asm/bug.h +++ /dev/null @@ -1,37 +0,0 @@ -/* MN10300 Kernel bug reporting - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_BUG_H -#define _ASM_BUG_H - -#ifdef CONFIG_BUG - -/* - * Tell the user there is some problem. - */ -#define BUG() \ -do { \ - asm volatile( \ - " syscall 15 \n" \ - "0: \n" \ - " .section __bug_table,\"aw\" \n" \ - " .long 0b,%0,%1 \n" \ - " .previous \n" \ - : \ - : "i"(__FILE__), "i"(__LINE__) \ - ); \ -} while (1) - -#define HAVE_ARCH_BUG -#endif /* CONFIG_BUG */ - -#include - -#endif /* _ASM_BUG_H */ diff --git a/arch/mn10300/include/asm/bugs.h b/arch/mn10300/include/asm/bugs.h deleted file mode 100644 index 31c8bc592b47..000000000000 --- a/arch/mn10300/include/asm/bugs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* MN10300 Checks for architecture-dependent bugs - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_BUGS_H -#define _ASM_BUGS_H - -#include - -static inline void __init check_bugs(void) -{ -} - -#endif /* _ASM_BUGS_H */ diff --git a/arch/mn10300/include/asm/busctl-regs.h b/arch/mn10300/include/asm/busctl-regs.h deleted file mode 100644 index 1632aef73401..000000000000 --- a/arch/mn10300/include/asm/busctl-regs.h +++ /dev/null @@ -1,151 +0,0 @@ -/* AM33v2 on-board bus controller registers - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_BUSCTL_REGS_H -#define _ASM_BUSCTL_REGS_H - -#include - -#ifdef __KERNEL__ - -/* bus controller registers */ -#define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */ -#define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */ -#define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */ -#define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */ -#define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */ -#define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */ -#define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */ -#define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */ -#define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */ -#define BCCR_BxAD_EXBUS 0x0 /* - direct to system bus controller */ -#define BCCR_BxAD_OPEXBUS 0x1 /* - direct to memory bus controller */ -#define BCCR_BxAD_OCMBUS 0x2 /* - direct to on chip memory */ -#define BCCR_API 0x00070000 /* bus arbitration priority */ -#define BCCR_API_DMACICD 0x00000000 /* - DMA > CI > CD */ -#define BCCR_API_DMACDCI 0x00010000 /* - DMA > CD > CI */ -#define BCCR_API_CICDDMA 0x00020000 /* - CI > CD > DMA */ -#define BCCR_API_CDCIDMA 0x00030000 /* - CD > CI > DMA */ -#define BCCR_API_ROUNDROBIN 0x00040000 /* - round robin */ -#define BCCR_BEPRI_DMACICD 0x00c00000 /* bus error address priority */ -#define BCCR_BEPRI_DMACDCI 0x00000000 /* - DMA > CI > CD */ -#define BCCR_BEPRI_CICDDMA 0x00400000 /* - DMA > CD > CI */ -#define BCCR_BEPRI_CDCIDMA 0x00800000 /* - CI > CD > DMA */ -#define BCCR_BEPRI 0x00c00000 /* - CD > CI > DMA */ -#define BCCR_TMON 0x03000000 /* timeout value settings */ -#define BCCR_TMON_16IOCLK 0x00000000 /* - 16 IOCLK cycles */ -#define BCCR_TMON_256IOCLK 0x01000000 /* - 256 IOCLK cycles */ -#define BCCR_TMON_4096IOCLK 0x02000000 /* - 4096 IOCLK cycles */ -#define BCCR_TMON_65536IOCLK 0x03000000 /* - 65536 IOCLK cycles */ -#define BCCR_TMOE 0x10000000 /* timeout detection enable */ - -#define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */ -#define BCBERR_BESB 0x0000001f /* erroneous access destination space */ -#define BCBERR_BESB_MON 0x00000001 /* - monitor space */ -#define BCBERR_BESB_IO 0x00000002 /* - IO bus */ -#define BCBERR_BESB_EX 0x00000004 /* - EX bus */ -#define BCBERR_BESB_OPEX 0x00000008 /* - OpEX bus */ -#define BCBERR_BESB_OCM 0x00000010 /* - on chip memory */ -#define BCBERR_BERW 0x00000100 /* type of access */ -#define BCBERR_BERW_WRITE 0x00000000 /* - write */ -#define BCBERR_BERW_READ 0x00000100 /* - read */ -#define BCBERR_BESD 0x00000200 /* error detector */ -#define BCBERR_BESD_BCU 0x00000000 /* - BCU detected error */ -#define BCBERR_BESD_SLAVE_BUS 0x00000200 /* - slave bus detected error */ -#define BCBERR_BEBST 0x00000400 /* type of access */ -#define BCBERR_BEBST_SINGLE 0x00000000 /* - single */ -#define BCBERR_BEBST_BURST 0x00000400 /* - burst */ -#define BCBERR_BEME 0x00000800 /* multiple bus error flag */ -#define BCBERR_BEMR 0x00007000 /* master bus that caused the error */ -#define BCBERR_BEMR_NOERROR 0x00000000 /* - no error */ -#define BCBERR_BEMR_CI 0x00001000 /* - CPU instruction fetch bus caused error */ -#define BCBERR_BEMR_CD 0x00002000 /* - CPU data bus caused error */ -#define BCBERR_BEMR_DMA 0x00004000 /* - DMA bus caused error */ - -#define BCBEAR __SYSREGC(0xc0002020, u32) /* bus error address reg */ - -/* system bus controller registers */ -#define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */ -#define SBBASE_BE 0x00000001 /* bank enable */ -#define SBBASE_BAM 0x0000fffe /* bank address mask [31:17] */ -#define SBBASE_BBA 0xfffe0000 /* bank base address [31:17] */ - -#define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */ -#define SBCNTRL0_WEH 0x00000f00 /* write enable hold */ -#define SBCNTRL0_REH 0x0000f000 /* read enable hold */ -#define SBCNTRL0_RWH 0x000f0000 /* SRW signal hold */ -#define SBCNTRL0_CSH 0x00f00000 /* chip select hold */ -#define SBCNTRL0_DAH 0x0f000000 /* data hold */ -#define SBCNTRL0_ADH 0xf0000000 /* address hold */ - -#define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */ -#define SBCNTRL1_WED 0x00000f00 /* write enable delay */ -#define SBCNTRL1_RED 0x0000f000 /* read enable delay */ -#define SBCNTRL1_RWD 0x000f0000 /* SRW signal delay */ -#define SBCNTRL1_ASW 0x00f00000 /* address strobe width */ -#define SBCNTRL1_CSD 0x0f000000 /* chip select delay */ -#define SBCNTRL1_ASD 0xf0000000 /* address strobe delay */ - -#define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */ -#define SBCNTRL2_WC 0x000000ff /* wait count */ -#define SBCNTRL2_BWC 0x00000f00 /* burst wait count */ -#define SBCNTRL2_WM 0x01000000 /* wait mode setting */ -#define SBCNTRL2_WM_FIXEDWAIT 0x00000000 /* - fixed wait access */ -#define SBCNTRL2_WM_HANDSHAKE 0x01000000 /* - handshake access */ -#define SBCNTRL2_BM 0x02000000 /* bus synchronisation mode */ -#define SBCNTRL2_BM_SYNC 0x00000000 /* - synchronous mode */ -#define SBCNTRL2_BM_ASYNC 0x02000000 /* - asynchronous mode */ -#define SBCNTRL2_BW 0x04000000 /* bus width */ -#define SBCNTRL2_BW_32 0x00000000 /* - 32 bits */ -#define SBCNTRL2_BW_16 0x04000000 /* - 16 bits */ -#define SBCNTRL2_RWINV 0x08000000 /* R/W signal invert polarity */ -#define SBCNTRL2_RWINV_NORM 0x00000000 /* - normal (read high) */ -#define SBCNTRL2_RWINV_INV 0x08000000 /* - inverted (read low) */ -#define SBCNTRL2_BT 0x70000000 /* bus type setting */ -#define SBCNTRL2_BT_SRAM 0x00000000 /* - SRAM interface */ -#define SBCNTRL2_BT_ADMUX 0x00000000 /* - addr/data multiplexed interface */ -#define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */ -#define SBCNTRL2_BTSE 0x80000000 /* burst enable */ - -/* memory bus controller */ -#define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */ -#define SDBASE_CE 0x00000001 /* chip enable */ -#define SDBASE_CBAM 0x0000fff0 /* chip base address mask [31:20] */ -#define SDBASE_CBAM_SHIFT 16 -#define SDBASE_CBA 0xfff00000 /* chip base address [31:20] */ - -#define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */ -#define SDRAMBUS_REFEN 0x00000004 /* refresh enable */ -#define SDRAMBUS_TRC 0x00000018 /* refresh command delay time */ -#define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */ -#define SDRAMBUS_PONSEQ 0x00000040 /* power on sequence */ -#define SDRAMBUS_SELFREQ 0x00000080 /* self-refresh mode request */ -#define SDRAMBUS_SELFON 0x00000100 /* self-refresh mode on */ -#define SDRAMBUS_SIZE 0x00030000 /* SDRAM size */ -#define SDRAMBUS_SIZE_64Mbit 0x00010000 /* 64Mbit SDRAM (x16) */ -#define SDRAMBUS_SIZE_128Mbit 0x00020000 /* 128Mbit SDRAM (x16) */ -#define SDRAMBUS_SIZE_256Mbit 0x00030000 /* 256Mbit SDRAM (x16) */ -#define SDRAMBUS_TRASWAIT 0x000c0000 /* row address precharge command cycle number */ -#define SDRAMBUS_REFNUM 0x00300000 /* refresh command number */ -#define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */ -#define SDRAMBUS_SETWAIT 0x03000000 /* mode register setting command cycle */ -#define SDRAMBUS_PREWAIT 0x0c000000 /* precharge command cycle */ -#define SDRAMBUS_RASLATE 0x30000000 /* RAS latency */ -#define SDRAMBUS_CASLATE 0xc0000000 /* CAS latency */ - -#define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */ -#define SDREFCNT_PERI 0x00000fff /* refresh period */ - -#define SDSHDW __SYSREG(0xda000010, u32) /* test reg */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_BUSCTL_REGS_H */ diff --git a/arch/mn10300/include/asm/cache.h b/arch/mn10300/include/asm/cache.h deleted file mode 100644 index f29cde2cfc91..000000000000 --- a/arch/mn10300/include/asm/cache.h +++ /dev/null @@ -1,60 +0,0 @@ -/* MN10300 cache management registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include -#include - -#ifndef __ASSEMBLY__ -#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES) -#else -#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES -#endif - -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES - -/* data cache purge registers - * - read from the register to unconditionally purge that cache line - * - write address & 0xffffff00 to conditionally purge that cache line - * - clear LSB to request invalidation as well - */ -#define DCACHE_PURGE(WAY, ENTRY) \ - __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES, u32) - -#define DCACHE_PURGE_WAY0(ENTRY) \ - __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) -#define DCACHE_PURGE_WAY1(ENTRY) \ - __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) -#define DCACHE_PURGE_WAY2(ENTRY) \ - __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) -#define DCACHE_PURGE_WAY3(ENTRY) \ - __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) - -/* instruction cache access registers */ -#define ICACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) -#define ICACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES, u32) - -/* data cache access registers */ -#define DCACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) -#define DCACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES, u32) - -#endif /* _ASM_CACHE_H */ diff --git a/arch/mn10300/include/asm/cacheflush.h b/arch/mn10300/include/asm/cacheflush.h deleted file mode 100644 index 6d6df839948f..000000000000 --- a/arch/mn10300/include/asm/cacheflush.h +++ /dev/null @@ -1,164 +0,0 @@ -/* MN10300 Cache flushing - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_CACHEFLUSH_H -#define _ASM_CACHEFLUSH_H - -#ifndef __ASSEMBLY__ - -/* Keep includes the same across arches. */ -#include - -/* - * Primitive routines - */ -#ifdef CONFIG_MN10300_CACHE_ENABLED -extern void mn10300_local_icache_inv(void); -extern void mn10300_local_icache_inv_page(unsigned long start); -extern void mn10300_local_icache_inv_range(unsigned long start, unsigned long end); -extern void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size); -extern void mn10300_local_dcache_inv(void); -extern void mn10300_local_dcache_inv_page(unsigned long start); -extern void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end); -extern void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size); -extern void mn10300_icache_inv(void); -extern void mn10300_icache_inv_page(unsigned long start); -extern void mn10300_icache_inv_range(unsigned long start, unsigned long end); -extern void mn10300_icache_inv_range2(unsigned long start, unsigned long size); -extern void mn10300_dcache_inv(void); -extern void mn10300_dcache_inv_page(unsigned long start); -extern void mn10300_dcache_inv_range(unsigned long start, unsigned long end); -extern void mn10300_dcache_inv_range2(unsigned long start, unsigned long size); -#ifdef CONFIG_MN10300_CACHE_WBACK -extern void mn10300_local_dcache_flush(void); -extern void mn10300_local_dcache_flush_page(unsigned long start); -extern void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end); -extern void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size); -extern void mn10300_local_dcache_flush_inv(void); -extern void mn10300_local_dcache_flush_inv_page(unsigned long start); -extern void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end); -extern void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size); -extern void mn10300_dcache_flush(void); -extern void mn10300_dcache_flush_page(unsigned long start); -extern void mn10300_dcache_flush_range(unsigned long start, unsigned long end); -extern void mn10300_dcache_flush_range2(unsigned long start, unsigned long size); -extern void mn10300_dcache_flush_inv(void); -extern void mn10300_dcache_flush_inv_page(unsigned long start); -extern void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end); -extern void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size); -#else -#define mn10300_local_dcache_flush() do {} while (0) -#define mn10300_local_dcache_flush_page(start) do {} while (0) -#define mn10300_local_dcache_flush_range(start, end) do {} while (0) -#define mn10300_local_dcache_flush_range2(start, size) do {} while (0) -#define mn10300_local_dcache_flush_inv() \ - mn10300_local_dcache_inv() -#define mn10300_local_dcache_flush_inv_page(start) \ - mn10300_local_dcache_inv_page(start) -#define mn10300_local_dcache_flush_inv_range(start, end) \ - mn10300_local_dcache_inv_range(start, end) -#define mn10300_local_dcache_flush_inv_range2(start, size) \ - mn10300_local_dcache_inv_range2(start, size) -#define mn10300_dcache_flush() do {} while (0) -#define mn10300_dcache_flush_page(start) do {} while (0) -#define mn10300_dcache_flush_range(start, end) do {} while (0) -#define mn10300_dcache_flush_range2(start, size) do {} while (0) -#define mn10300_dcache_flush_inv() mn10300_dcache_inv() -#define mn10300_dcache_flush_inv_page(start) \ - mn10300_dcache_inv_page((start)) -#define mn10300_dcache_flush_inv_range(start, end) \ - mn10300_dcache_inv_range((start), (end)) -#define mn10300_dcache_flush_inv_range2(start, size) \ - mn10300_dcache_inv_range2((start), (size)) -#endif /* CONFIG_MN10300_CACHE_WBACK */ -#else -#define mn10300_local_icache_inv() do {} while (0) -#define mn10300_local_icache_inv_page(start) do {} while (0) -#define mn10300_local_icache_inv_range(start, end) do {} while (0) -#define mn10300_local_icache_inv_range2(start, size) do {} while (0) -#define mn10300_local_dcache_inv() do {} while (0) -#define mn10300_local_dcache_inv_page(start) do {} while (0) -#define mn10300_local_dcache_inv_range(start, end) do {} while (0) -#define mn10300_local_dcache_inv_range2(start, size) do {} while (0) -#define mn10300_local_dcache_flush() do {} while (0) -#define mn10300_local_dcache_flush_inv_page(start) do {} while (0) -#define mn10300_local_dcache_flush_inv() do {} while (0) -#define mn10300_local_dcache_flush_inv_range(start, end)do {} while (0) -#define mn10300_local_dcache_flush_inv_range2(start, size) do {} while (0) -#define mn10300_local_dcache_flush_page(start) do {} while (0) -#define mn10300_local_dcache_flush_range(start, end) do {} while (0) -#define mn10300_local_dcache_flush_range2(start, size) do {} while (0) -#define mn10300_icache_inv() do {} while (0) -#define mn10300_icache_inv_page(start) do {} while (0) -#define mn10300_icache_inv_range(start, end) do {} while (0) -#define mn10300_icache_inv_range2(start, size) do {} while (0) -#define mn10300_dcache_inv() do {} while (0) -#define mn10300_dcache_inv_page(start) do {} while (0) -#define mn10300_dcache_inv_range(start, end) do {} while (0) -#define mn10300_dcache_inv_range2(start, size) do {} while (0) -#define mn10300_dcache_flush() do {} while (0) -#define mn10300_dcache_flush_inv_page(start) do {} while (0) -#define mn10300_dcache_flush_inv() do {} while (0) -#define mn10300_dcache_flush_inv_range(start, end) do {} while (0) -#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0) -#define mn10300_dcache_flush_page(start) do {} while (0) -#define mn10300_dcache_flush_range(start, end) do {} while (0) -#define mn10300_dcache_flush_range2(start, size) do {} while (0) -#endif /* CONFIG_MN10300_CACHE_ENABLED */ - -/* - * Virtually-indexed cache management (our cache is physically indexed) - */ -#define flush_cache_all() do {} while (0) -#define flush_cache_mm(mm) do {} while (0) -#define flush_cache_dup_mm(mm) do {} while (0) -#define flush_cache_range(mm, start, end) do {} while (0) -#define flush_cache_page(vma, vmaddr, pfn) do {} while (0) -#define flush_cache_vmap(start, end) do {} while (0) -#define flush_cache_vunmap(start, end) do {} while (0) -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 -#define flush_dcache_page(page) do {} while (0) -#define flush_dcache_mmap_lock(mapping) do {} while (0) -#define flush_dcache_mmap_unlock(mapping) do {} while (0) - -/* - * Physically-indexed cache management - */ -#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) -extern void flush_icache_page(struct vm_area_struct *vma, struct page *page); -extern void flush_icache_range(unsigned long start, unsigned long end); -#elif defined(CONFIG_MN10300_CACHE_INV_ICACHE) -static inline void flush_icache_page(struct vm_area_struct *vma, - struct page *page) -{ - mn10300_icache_inv_page(page_to_phys(page)); -} -extern void flush_icache_range(unsigned long start, unsigned long end); -#else -#define flush_icache_range(start, end) do {} while (0) -#define flush_icache_page(vma, pg) do {} while (0) -#endif - - -#define flush_icache_user_range(vma, pg, adr, len) \ - flush_icache_range(adr, adr + len) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - do { \ - memcpy(dst, src, len); \ - flush_icache_page(vma, page); \ - } while (0) - -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_CACHEFLUSH_H */ diff --git a/arch/mn10300/include/asm/checksum.h b/arch/mn10300/include/asm/checksum.h deleted file mode 100644 index c80df5b504ac..000000000000 --- a/arch/mn10300/include/asm/checksum.h +++ /dev/null @@ -1,79 +0,0 @@ -/* MN10300 Optimised checksumming code - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_CHECKSUM_H -#define _ASM_CHECKSUM_H - -extern __wsum csum_partial(const void *buff, int len, __wsum sum); -extern __wsum csum_partial_copy_nocheck(const void *src, void *dst, - int len, __wsum sum); -extern __wsum csum_partial_copy_from_user(const void *src, void *dst, - int len, __wsum sum, - int *err_ptr); -extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl); -extern __wsum csum_partial(const void *buff, int len, __wsum sum); -extern __sum16 ip_compute_csum(const void *buff, int len); - -#define csum_partial_copy_fromuser csum_partial_copy -extern __wsum csum_partial_copy(const void *src, void *dst, int len, - __wsum sum); - -static inline __sum16 csum_fold(__wsum sum) -{ - asm( - " add %1,%0 \n" - " addc 0xffff,%0 \n" - : "=r" (sum) - : "r" (sum << 16), "0" (sum & 0xffff0000) - : "cc" - ); - return (~sum) >> 16; -} - -static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, - __u32 len, __u8 proto, - __wsum sum) -{ - __wsum tmp = (__wsum)((len + proto) << 8); - - asm( - " add %1,%0 \n" - " addc %2,%0 \n" - " addc %3,%0 \n" - " addc 0,%0 \n" - : "=r" (sum) - : "r" (daddr), "r"(saddr), "r"(tmp), "0"(sum) - : "cc" - ); - return sum; -} - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ -static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, - __u32 len, __u8 proto, - __wsum sum) -{ - return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); -} - -#undef _HAVE_ARCH_IPV6_CSUM - -/* - * Copy and checksum to user - */ -#define HAVE_CSUM_COPY_USER -extern __wsum csum_and_copy_to_user(const void *src, void *dst, int len, - __wsum sum, int *err_ptr); - - -#endif /* _ASM_CHECKSUM_H */ diff --git a/arch/mn10300/include/asm/cmpxchg.h b/arch/mn10300/include/asm/cmpxchg.h deleted file mode 100644 index 97a4aaf387a6..000000000000 --- a/arch/mn10300/include/asm/cmpxchg.h +++ /dev/null @@ -1,115 +0,0 @@ -/* MN10300 Atomic xchg/cmpxchg operations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_CMPXCHG_H -#define _ASM_CMPXCHG_H - -#include - -#ifdef CONFIG_SMP -#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT -static inline -unsigned long __xchg(volatile unsigned long *m, unsigned long val) -{ - unsigned long status; - unsigned long oldval; - - asm volatile( - "1: mov %4,(_AAR,%3) \n" - " mov (_ADR,%3),%1 \n" - " mov %5,(_ADR,%3) \n" - " mov (_ADR,%3),%0 \n" /* flush */ - " mov (_ASR,%3),%0 \n" - " or %0,%0 \n" - " bne 1b \n" - : "=&r"(status), "=&r"(oldval), "=m"(*m) - : "a"(ATOMIC_OPS_BASE_ADDR), "r"(m), "r"(val) - : "memory", "cc"); - - return oldval; -} - -static inline unsigned long __cmpxchg(volatile unsigned long *m, - unsigned long old, unsigned long new) -{ - unsigned long status; - unsigned long oldval; - - asm volatile( - "1: mov %4,(_AAR,%3) \n" - " mov (_ADR,%3),%1 \n" - " cmp %5,%1 \n" - " bne 2f \n" - " mov %6,(_ADR,%3) \n" - "2: mov (_ADR,%3),%0 \n" /* flush */ - " mov (_ASR,%3),%0 \n" - " or %0,%0 \n" - " bne 1b \n" - : "=&r"(status), "=&r"(oldval), "=m"(*m) - : "a"(ATOMIC_OPS_BASE_ADDR), "r"(m), - "r"(old), "r"(new) - : "memory", "cc"); - - return oldval; -} -#else /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */ -#error "No SMP atomic operation support!" -#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */ - -#else /* CONFIG_SMP */ - -/* - * Emulate xchg for non-SMP MN10300 - */ -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -static inline -unsigned long __xchg(volatile unsigned long *m, unsigned long val) -{ - unsigned long oldval; - unsigned long flags; - - flags = arch_local_cli_save(); - oldval = *m; - *m = val; - arch_local_irq_restore(flags); - return oldval; -} - -/* - * Emulate cmpxchg for non-SMP MN10300 - */ -static inline unsigned long __cmpxchg(volatile unsigned long *m, - unsigned long old, unsigned long new) -{ - unsigned long oldval; - unsigned long flags; - - flags = arch_local_cli_save(); - oldval = *m; - if (oldval == old) - *m = new; - arch_local_irq_restore(flags); - return oldval; -} - -#endif /* CONFIG_SMP */ - -#define xchg(ptr, v) \ - ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \ - (unsigned long)(v))) - -#define cmpxchg(ptr, o, n) \ - ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \ - (unsigned long)(o), \ - (unsigned long)(n))) - -#endif /* _ASM_CMPXCHG_H */ diff --git a/arch/mn10300/include/asm/cpu-regs.h b/arch/mn10300/include/asm/cpu-regs.h deleted file mode 100644 index c54effae2202..000000000000 --- a/arch/mn10300/include/asm/cpu-regs.h +++ /dev/null @@ -1,353 +0,0 @@ -/* MN10300 Core system registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_CPU_REGS_H -#define _ASM_CPU_REGS_H - -#ifndef __ASSEMBLY__ -#include -#endif - -/* we tell the compiler to pretend to be AM33 so that it doesn't try and use - * the FP regs, but tell the assembler that we're actually allowed AM33v2 - * instructions */ -#ifndef __ASSEMBLY__ -asm(" .am33_2\n"); -#else -.am33_2 -#endif - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -#define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) -#define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR)) -#else -#define __SYSREG(ADDR, TYPE) ADDR -#define __SYSREGC(ADDR, TYPE) ADDR -#endif - -/* CPU registers */ -#define EPSW_FLAG_Z 0x00000001 /* zero flag */ -#define EPSW_FLAG_N 0x00000002 /* negative flag */ -#define EPSW_FLAG_C 0x00000004 /* carry flag */ -#define EPSW_FLAG_V 0x00000008 /* overflow flag */ -#define EPSW_IM 0x00000700 /* interrupt mode */ -#define EPSW_IM_0 0x00000000 /* interrupt mode 0 */ -#define EPSW_IM_1 0x00000100 /* interrupt mode 1 */ -#define EPSW_IM_2 0x00000200 /* interrupt mode 2 */ -#define EPSW_IM_3 0x00000300 /* interrupt mode 3 */ -#define EPSW_IM_4 0x00000400 /* interrupt mode 4 */ -#define EPSW_IM_5 0x00000500 /* interrupt mode 5 */ -#define EPSW_IM_6 0x00000600 /* interrupt mode 6 */ -#define EPSW_IM_7 0x00000700 /* interrupt mode 7 */ -#define EPSW_IE 0x00000800 /* interrupt enable */ -#define EPSW_S 0x00003000 /* software auxiliary bits */ -#define EPSW_T 0x00008000 /* trace enable */ -#define EPSW_nSL 0x00010000 /* not supervisor level */ -#define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */ -#define EPSW_nAR 0x00040000 /* register bank control */ -#define EPSW_ML 0x00080000 /* monitor level */ -#define EPSW_FE 0x00100000 /* FPU enable */ -#define EPSW_IM_SHIFT 8 /* EPSW_IM_SHIFT determines the interrupt mode */ - -#define NUM2EPSW_IM(num) ((num) << EPSW_IM_SHIFT) - -/* FPU registers */ -#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */ -#define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */ -#define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */ -#define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */ -#define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */ -#define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */ -#define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */ -#define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */ -#define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */ -#define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */ -#define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */ -#define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */ -#define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */ -#define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */ -#define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */ -#define FPCR_RM 0x00030000 /* rounding mode */ -#define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */ -#define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */ -#define FPCR_FCC_E 0x00080000 /* FPU equal condition code */ -#define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */ -#define FPCR_FCC_L 0x00200000 /* FPU less than condition code */ -#define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */ - -/* CPU control registers */ -#define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */ -#define CPUP_DWBD 0x0020 /* write buffer disable flag */ -#define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */ -#define CPUP_EXM 0x0080 /* exception operation mode */ -#define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */ -#define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */ - -#define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */ -#define CPUM_SLEEP 0x0004 /* set to enter sleep state */ -#define CPUM_HALT 0x0008 /* set to enter halt state */ -#define CPUM_STOP 0x0010 /* set to enter stop state */ - -#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */ -#define CPUREV_TYPE 0x0000000f /* CPU type */ -#define CPUREV_TYPE_S 0 -#define CPUREV_TYPE_AM33_1 0x00000000 /* - AM33-1 core, AM33/1.00 arch */ -#define CPUREV_TYPE_AM33_2 0x00000001 /* - AM33-2 core, AM33/2.00 arch */ -#define CPUREV_TYPE_AM34_1 0x00000002 /* - AM34-1 core, AM33/2.00 arch */ -#define CPUREV_TYPE_AM33_3 0x00000003 /* - AM33-3 core, AM33/2.00 arch */ -#define CPUREV_TYPE_AM34_2 0x00000004 /* - AM34-2 core, AM33/3.00 arch */ -#define CPUREV_REVISION 0x000000f0 /* CPU revision */ -#define CPUREV_REVISION_S 4 -#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */ -#define CPUREV_ICWAY_S 8 -#define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */ -#define CPUREV_ICSIZE_S 12 -#define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */ -#define CPUREV_DCWAY_S 16 -#define CPUREV_DCSIZE 0x00f00000 /* data cache way size */ -#define CPUREV_DCSIZE_S 20 -#define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */ -#define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */ -#define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */ - -#define DCR __SYSREG(0xc0000030, u16) /* Debug control register */ - -/* interrupt/exception control registers */ -#define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */ -#define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */ -#define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */ -#define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */ -#define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */ -#define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */ -#define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */ - -#define TBR __SYSREG(0xc0000024, u32) /* Trap table base */ -#define TBR_TB 0xff000000 /* table base address bits 31-24 */ -#define TBR_INT_CODE 0x00ffffff /* interrupt code */ - -#define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */ - -#define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */ -#define sISR_IRQICE 0x00000001 /* ICE interrupt */ -#define sISR_ISTEP 0x00000002 /* single step interrupt */ -#define sISR_MISSA 0x00000004 /* memory access address misalignment fault */ -#define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */ -#define sISR_PIEXE 0x00000010 /* program interrupt */ -#define sISR_MEMERR 0x00000020 /* illegal memory access fault */ -#define sISR_IBREAK 0x00000040 /* instraction break interrupt */ -#define sISR_DBSRL 0x00000080 /* debug serial interrupt */ -#define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */ -#define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */ -#define sISR_OBREAK 0x00000400 /* operand break interrupt */ -#define sISR_PRIV 0x00000800 /* privileged instruction execution fault */ -#define sISR_BUSERR 0x00001000 /* bus error fault */ -#define sISR_DBLFT 0x00002000 /* double fault */ -#define sISR_DBG 0x00008000 /* debug reserved interrupt */ -#define sISR_ITMISS 0x00010000 /* instruction TLB miss */ -#define sISR_DTMISS 0x00020000 /* data TLB miss */ -#define sISR_ITEX 0x00040000 /* instruction TLB access exception */ -#define sISR_DTEX 0x00080000 /* data TLB access exception */ -#define sISR_ILGIA 0x00100000 /* illegal instruction access exception */ -#define sISR_ILGDA 0x00200000 /* illegal data access exception */ -#define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */ -#define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */ -#define sISR_PRIDA 0x01000000 /* privileged space data access excep */ -#define sISR_DISA 0x02000000 /* data space instruction access excep */ -#define sISR_SYSC 0x04000000 /* system call instruction excep */ -#define sISR_FPUD 0x08000000 /* FPU disabled excep */ -#define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */ -#define sISR_FPUOP 0x20000000 /* FPU operation excep */ -#define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */ - -/* cache control registers */ -#define CHCTR __SYSREG(0xc0000070, u16) /* cache control */ -#define CHCTR_ICEN 0x0001 /* instruction cache enable */ -#define CHCTR_DCEN 0x0002 /* data cache enable */ -#define CHCTR_ICBUSY 0x0004 /* instruction cache busy */ -#define CHCTR_DCBUSY 0x0008 /* data cache busy */ -#define CHCTR_ICINV 0x0010 /* instruction cache invalidate */ -#define CHCTR_DCINV 0x0020 /* data cache invalidate */ -#define CHCTR_DCWTMD 0x0040 /* data cache writing mode */ -#define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */ -#define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */ -#define CHCTR_DCALMD 0x0080 /* data cache allocation mode */ -#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */ -#define CHCTR_DCWMD 0xf000 /* data cache way mode */ - -#ifdef CONFIG_AM34_2 -#define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */ -#define ICIVCR_ICIVBSY 0x00000008 /* icache area invalidate busy */ -#define ICIVCR_ICI 0x00000001 /* icache area invalidate */ - -#define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */ - -#define DCPGCR __SYSREG(0xc0000c10, u32) /* data cache area purge control */ -#define DCPGCR_DCPGBSY 0x00000008 /* data cache area purge busy */ -#define DCPGCR_DCP 0x00000002 /* data cache area purge */ -#define DCPGCR_DCI 0x00000001 /* data cache area invalidate */ - -#define DCPGMR __SYSREG(0xc0000c14, u32) /* data cache area purge mask */ -#endif /* CONFIG_AM34_2 */ - -/* MMU control registers */ -#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */ -#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */ -#define MMUCTR_ITE 0x00000040 /* instruction TLB enable */ -#define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */ -#define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */ -#define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */ -#define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */ -#define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */ -#define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */ -#define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */ -#define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */ -#define MMUCTR_CE 0x00008000 /* cacheable bit enable */ -#define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */ -#define MMUCTR_DTE 0x00400000 /* data TLB enable */ -#define MMUCTR_DIV 0x00800000 /* data TLB invalidate */ -#define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */ -#define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */ -#define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */ -#define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */ -#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */ -#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */ -#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */ -#ifdef CONFIG_AM34_2 -#define MMUCTR_WTE 0x80000000 /* write-through cache TLB entry bit enable */ -#endif - -#define PIDR __SYSREG(0xc0000094, u16) /* PID register */ -#define PIDR_PID 0x00ff /* process identifier */ - -#define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */ - -#define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */ -#define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */ -#define xPTEL_V 0x00000001 /* TLB entry valid */ -#define xPTEL_UNUSED1 0x00000002 /* unused bit */ -#define xPTEL_UNUSED2 0x00000004 /* unused bit */ -#define xPTEL_C 0x00000008 /* cached if set */ -#define xPTEL_PV 0x00000010 /* page valid */ -#define xPTEL_D 0x00000020 /* dirty */ -#define xPTEL_PR 0x000001c0 /* page protection */ -#define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */ -#define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */ -#define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */ -#define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */ -#define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */ -#define xPTEL_G 0x00000200 /* global (use PID if 0) */ -#define xPTEL_PS 0x00000c00 /* page size */ -#define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */ -#define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */ -#define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */ -#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */ -#define xPTEL_PPN 0xfffff006 /* physical page number */ - -#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */ -#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */ -#define xPTEU_VPN 0xfffffc00 /* virtual page number */ -#define xPTEU_PID 0x000000ff /* process identifier to which applicable */ - -#define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */ -#define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */ -#define xPTEL2_V 0x00000001 /* TLB entry valid */ -#define xPTEL2_C 0x00000002 /* cacheable */ -#define xPTEL2_PV 0x00000004 /* page valid */ -#define xPTEL2_D 0x00000008 /* dirty */ -#define xPTEL2_PR 0x00000070 /* page protection */ -#define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */ -#define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */ -#define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */ -#define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */ -#define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */ -#define xPTEL2_G 0x00000080 /* global (use PID if 0) */ -#define xPTEL2_PS 0x00000300 /* page size */ -#define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */ -#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */ -#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */ -#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */ -#define xPTEL2_CWT 0x00000400 /* cacheable write-through */ -#define xPTEL2_UNUSED1 0x00000800 /* unused bit (broadcast mask) */ -#define xPTEL2_PPN 0xfffff000 /* physical page number */ - -#define xPTEL2_V_BIT 0 /* bit numbers corresponding to above masks */ -#define xPTEL2_C_BIT 1 -#define xPTEL2_PV_BIT 2 -#define xPTEL2_D_BIT 3 -#define xPTEL2_G_BIT 7 -#define xPTEL2_UNUSED1_BIT 11 - -#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */ -#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */ -#define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */ -#define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */ -#define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */ -#define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */ -#define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */ -#define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */ -#define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */ -#define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */ -#define MMUFCR_xFC_TYPE 0x0020 /* access type flag */ -#define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */ -#define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */ -#define MMUFCR_xFC_PR 0x01c0 /* page protection flag */ -#define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */ -#define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */ -#define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */ -#define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */ -#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */ -#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */ - -#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT -/* atomic operation registers */ -#define AAR __SYSREG(0xc0000a00, u32) /* cacheable address */ -#define AAR2 __SYSREG(0xc0000a04, u32) /* uncacheable address */ -#define ADR __SYSREG(0xc0000a08, u32) /* data */ -#define ASR __SYSREG(0xc0000a0c, u32) /* status */ -#define AARU __SYSREG(0xd400aa00, u32) /* user address */ -#define ADRU __SYSREG(0xd400aa08, u32) /* user data */ -#define ASRU __SYSREG(0xd400aa0c, u32) /* user status */ - -#define ASR_RW 0x00000008 /* read */ -#define ASR_BW 0x00000004 /* bus error */ -#define ASR_IW 0x00000002 /* interrupt */ -#define ASR_LW 0x00000001 /* bus lock */ - -#define ASRU_RW ASR_RW /* read */ -#define ASRU_BW ASR_BW /* bus error */ -#define ASRU_IW ASR_IW /* interrupt */ -#define ASRU_LW ASR_LW /* bus lock */ - -/* in inline ASM, we stick the base pointer in to a reg and use offsets from - * it */ -#define ATOMIC_OPS_BASE_ADDR 0xc0000a00 -#ifndef __ASSEMBLY__ -asm( - "_AAR = 0\n" - "_AAR2 = 4\n" - "_ADR = 8\n" - "_ASR = 12\n"); -#else -#define _AAR 0 -#define _AAR2 4 -#define _ADR 8 -#define _ASR 12 -#endif - -/* physical page address for userspace atomic operations registers */ -#define USER_ATOMIC_OPS_PAGE_ADDR 0xd400a000 - -#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_CPU_REGS_H */ diff --git a/arch/mn10300/include/asm/current.h b/arch/mn10300/include/asm/current.h deleted file mode 100644 index ca6027d83743..000000000000 --- a/arch/mn10300/include/asm/current.h +++ /dev/null @@ -1,37 +0,0 @@ -/* MN10300 Current task structure accessor - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_CURRENT_H -#define _ASM_CURRENT_H - -#include - -/* - * dedicate E2 to keeping the current task pointer - */ -#ifdef CONFIG_MN10300_CURRENT_IN_E2 - -register struct task_struct *const current asm("e2") __attribute__((used)); - -#define get_current() current - -extern struct task_struct *__current; - -#else -static inline __attribute__((const)) -struct task_struct *get_current(void) -{ - return current_thread_info()->task; -} - -#define current get_current() -#endif - -#endif /* _ASM_CURRENT_H */ diff --git a/arch/mn10300/include/asm/debugger.h b/arch/mn10300/include/asm/debugger.h deleted file mode 100644 index e1d3b083696c..000000000000 --- a/arch/mn10300/include/asm/debugger.h +++ /dev/null @@ -1,43 +0,0 @@ -/* Kernel debugger for MN10300 - * - * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_DEBUGGER_H -#define _ASM_DEBUGGER_H - -#if defined(CONFIG_KERNEL_DEBUGGER) - -extern int debugger_intercept(enum exception_code, int, int, struct pt_regs *); -extern int at_debugger_breakpoint(struct pt_regs *); - -#ifndef CONFIG_MN10300_DEBUGGER_CACHE_NO_FLUSH -extern void debugger_local_cache_flushinv(void); -extern void debugger_local_cache_flushinv_one(u8 *); -#else -static inline void debugger_local_cache_flushinv(void) {} -static inline void debugger_local_cache_flushinv_one(u8 *addr) {} -#endif - -#else /* CONFIG_KERNEL_DEBUGGER */ - -static inline int debugger_intercept(enum exception_code excep, - int signo, int si_code, - struct pt_regs *regs) -{ - return 0; -} - -static inline int at_debugger_breakpoint(struct pt_regs *regs) -{ - return 0; -} - -#endif /* CONFIG_KERNEL_DEBUGGER */ -#endif /* _ASM_DEBUGGER_H */ diff --git a/arch/mn10300/include/asm/delay.h b/arch/mn10300/include/asm/delay.h deleted file mode 100644 index 34517b359399..000000000000 --- a/arch/mn10300/include/asm/delay.h +++ /dev/null @@ -1,19 +0,0 @@ -/* MN10300 Uninterruptible delay routines - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_DELAY_H -#define _ASM_DELAY_H - -extern void __udelay(unsigned long usecs); -extern void __delay(unsigned long loops); - -#define udelay(n) __udelay(n) - -#endif /* _ASM_DELAY_H */ diff --git a/arch/mn10300/include/asm/div64.h b/arch/mn10300/include/asm/div64.h deleted file mode 100644 index 503efab2a516..000000000000 --- a/arch/mn10300/include/asm/div64.h +++ /dev/null @@ -1,115 +0,0 @@ -/* MN10300 64-bit division - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_DIV64 -#define _ASM_DIV64 - -#include - -extern void ____unhandled_size_in_do_div___(void); - -/* - * Beginning with gcc 4.6, the MDR register is represented explicitly. We - * must, therefore, at least explicitly clobber the register when we make - * changes to it. The following assembly fragments *could* be rearranged in - * order to leave the moves to/from the MDR register to the compiler, but the - * gains would be minimal at best. - */ -#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) -# define CLOBBER_MDR_CC "mdr", "cc" -#else -# define CLOBBER_MDR_CC "cc" -#endif - -/* - * divide n by base, leaving the result in n and returning the remainder - * - we can do this quite efficiently on the MN10300 by cascading the divides - * through the MDR register - */ -#define do_div(n, base) \ -({ \ - unsigned __rem = 0; \ - if (sizeof(n) <= 4) { \ - asm("mov %1,mdr \n" \ - "divu %2,%0 \n" \ - "mov mdr,%1 \n" \ - : "+r"(n), "=d"(__rem) \ - : "r"(base), "1"(__rem) \ - : CLOBBER_MDR_CC \ - ); \ - } else if (sizeof(n) <= 8) { \ - union { \ - unsigned long long l; \ - u32 w[2]; \ - } __quot; \ - __quot.l = n; \ - asm("mov %0,mdr \n" /* MDR = 0 */ \ - "divu %3,%1 \n" \ - /* __quot.MSL = __div.MSL / base, */ \ - /* MDR = MDR:__div.MSL % base */ \ - "divu %3,%2 \n" \ - /* __quot.LSL = MDR:__div.LSL / base, */ \ - /* MDR = MDR:__div.LSL % base */ \ - "mov mdr,%0 \n" \ - : "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \ - : "r"(base), "0"(__rem), "1"(__quot.w[1]), \ - "2"(__quot.w[0]) \ - : CLOBBER_MDR_CC \ - ); \ - n = __quot.l; \ - } else { \ - ____unhandled_size_in_do_div___(); \ - } \ - __rem; \ -}) - -/* - * do an unsigned 32-bit multiply and divide with intermediate 64-bit product - * so as not to lose accuracy - * - we use the MDR register to hold the MSW of the product - */ -static inline __attribute__((const)) -unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) -{ - unsigned result; - - asm("mulu %2,%0 \n" /* MDR:val = val*mult */ - "divu %3,%0 \n" /* val = MDR:val/div; - * MDR = MDR:val%div */ - : "=r"(result) - : "0"(val), "ir"(mult), "r"(div) - : CLOBBER_MDR_CC - ); - - return result; -} - -/* - * do a signed 32-bit multiply and divide with intermediate 64-bit product so - * as not to lose accuracy - * - we use the MDR register to hold the MSW of the product - */ -static inline __attribute__((const)) -signed __muldiv64s(signed val, signed mult, signed div) -{ - signed result; - - asm("mul %2,%0 \n" /* MDR:val = val*mult */ - "div %3,%0 \n" /* val = MDR:val/div; - * MDR = MDR:val%div */ - : "=r"(result) - : "0"(val), "ir"(mult), "r"(div) - : CLOBBER_MDR_CC - ); - - return result; -} - -#endif /* _ASM_DIV64 */ diff --git a/arch/mn10300/include/asm/dma-mapping.h b/arch/mn10300/include/asm/dma-mapping.h deleted file mode 100644 index 439e474ed6d7..000000000000 --- a/arch/mn10300/include/asm/dma-mapping.h +++ /dev/null @@ -1,21 +0,0 @@ -/* DMA mapping routines for the MN10300 arch - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_DMA_MAPPING_H -#define _ASM_DMA_MAPPING_H - -extern const struct dma_map_ops mn10300_dma_ops; - -static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) -{ - return &mn10300_dma_ops; -} - -#endif diff --git a/arch/mn10300/include/asm/dma.h b/arch/mn10300/include/asm/dma.h deleted file mode 100644 index 10b77d4628c2..000000000000 --- a/arch/mn10300/include/asm/dma.h +++ /dev/null @@ -1,117 +0,0 @@ -/* MN10300 ISA DMA handlers and definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_DMA_H -#define _ASM_DMA_H - -#include -#include -#include - -#undef MAX_DMA_CHANNELS /* switch off linux/kernel/dma.c */ -#define MAX_DMA_ADDRESS 0xbfffffff - -extern spinlock_t dma_spin_lock; - -static inline unsigned long claim_dma_lock(void) -{ - unsigned long flags; - spin_lock_irqsave(&dma_spin_lock, flags); - return flags; -} - -static inline void release_dma_lock(unsigned long flags) -{ - spin_unlock_irqrestore(&dma_spin_lock, flags); -} - -/* enable/disable a specific DMA channel */ -static inline void enable_dma(unsigned int dmanr) -{ -} - -static inline void disable_dma(unsigned int dmanr) -{ -} - -/* Clear the 'DMA Pointer Flip Flop'. - * Write 0 for LSB/MSB, 1 for MSB/LSB access. - * Use this once to initialize the FF to a known state. - * After that, keep track of it. :-) - * --- In order to do that, the DMA routines below should --- - * --- only be used while holding the DMA lock ! --- - */ -static inline void clear_dma_ff(unsigned int dmanr) -{ -} - -/* set mode (above) for a specific DMA channel */ -static inline void set_dma_mode(unsigned int dmanr, char mode) -{ -} - -/* Set only the page register bits of the transfer address. - * This is used for successive transfers when we know the contents of - * the lower 16 bits of the DMA current address register, but a 64k boundary - * may have been crossed. - */ -static inline void set_dma_page(unsigned int dmanr, char pagenr) -{ -} - - -/* Set transfer address & page bits for specific DMA channel. - * Assumes dma flipflop is clear. - */ -static inline void set_dma_addr(unsigned int dmanr, unsigned int a) -{ -} - - -/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for - * a specific DMA channel. - * You must ensure the parameters are valid. - * NOTE: from a manual: "the number of transfers is one more - * than the initial word count"! This is taken into account. - * Assumes dma flip-flop is clear. - * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. - */ -static inline void set_dma_count(unsigned int dmanr, unsigned int count) -{ -} - - -/* Get DMA residue count. After a DMA transfer, this - * should return zero. Reading this while a DMA transfer is - * still in progress will return unpredictable results. - * If called before the channel has been used, it may return 1. - * Otherwise, it returns the number of _bytes_ left to transfer. - * - * Assumes DMA flip-flop is clear. - */ -static inline int get_dma_residue(unsigned int dmanr) -{ - return 0; -} - - -/* These are in kernel/dma.c: */ -extern int request_dma(unsigned int dmanr, const char *device_id); -extern void free_dma(unsigned int dmanr); - -/* From PCI */ - -#ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) -#endif - -#endif /* _ASM_DMA_H */ diff --git a/arch/mn10300/include/asm/dmactl-regs.h b/arch/mn10300/include/asm/dmactl-regs.h deleted file mode 100644 index 80337b339c90..000000000000 --- a/arch/mn10300/include/asm/dmactl-regs.h +++ /dev/null @@ -1,16 +0,0 @@ -/* MN10300 on-board DMA controller registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_DMACTL_REGS_H -#define _ASM_DMACTL_REGS_H - -#include - -#endif /* _ASM_DMACTL_REGS_H */ diff --git a/arch/mn10300/include/asm/elf.h b/arch/mn10300/include/asm/elf.h deleted file mode 100644 index f592d7a9f032..000000000000 --- a/arch/mn10300/include/asm/elf.h +++ /dev/null @@ -1,153 +0,0 @@ -/* MN10300 ELF constant and register definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_ELF_H -#define _ASM_ELF_H - -#include -#include -#include - -/* - * AM33 relocations - */ -#define R_MN10300_NONE 0 /* No reloc. */ -#define R_MN10300_32 1 /* Direct 32 bit. */ -#define R_MN10300_16 2 /* Direct 16 bit. */ -#define R_MN10300_8 3 /* Direct 8 bit. */ -#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ -#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ -#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ -#define R_MN10300_24 9 /* Direct 24 bit. */ -#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ -#define R_MN10300_SYM_DIFF 33 /* Adjustment when relaxing. */ -#define R_MN10300_ALIGN 34 /* Alignment requirement. */ - -/* - * AM33/AM34 HW Capabilities - */ -#define HWCAP_MN10300_ATOMIC_OP_UNIT 1 /* Has AM34 Atomic Operations */ - - -/* - * ELF register definitions.. - */ -typedef unsigned long elf_greg_t; - -#define ELF_NGREG ((sizeof(struct pt_regs) / sizeof(elf_greg_t)) - 1) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -#define ELF_NFPREG 32 -typedef float elf_fpreg_t; - -typedef struct { - elf_fpreg_t fpregs[ELF_NFPREG]; - u_int32_t fpcr; -} elf_fpregset_t; - -/* - * This is used to ensure we don't load something for the wrong architecture - */ -#define elf_check_arch(x) \ - (((x)->e_machine == EM_CYGNUS_MN10300) || \ - ((x)->e_machine == EM_MN10300)) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_MN10300 - -/* - * ELF process initialiser - */ -#define ELF_PLAT_INIT(_r, load_addr) \ -do { \ - struct pt_regs *_ur = current->thread.uregs; \ - _ur->a3 = 0; _ur->a2 = 0; _ur->d3 = 0; _ur->d2 = 0; \ - _ur->mcvf = 0; _ur->mcrl = 0; _ur->mcrh = 0; _ur->mdrq = 0; \ - _ur->e1 = 0; _ur->e0 = 0; _ur->e7 = 0; _ur->e6 = 0; \ - _ur->e5 = 0; _ur->e4 = 0; _ur->e3 = 0; _ur->e2 = 0; \ - _ur->lar = 0; _ur->lir = 0; _ur->mdr = 0; \ - _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \ -} while (0) - -#define CORE_DUMP_USE_REGSET -#define ELF_EXEC_PAGESIZE 4096 - -/* - * This is the location that an ET_DYN program is loaded if exec'ed. Typical - * use of this is to invoke "./ld.so someprog" to test out a new version of - * the loader. We need to make sure that it is out of the way of the program - * that it will "exec", and that there is sufficient room for the brk. - * - must clear the VMALLOC area - */ -#define ELF_ET_DYN_BASE 0x04000000 - -/* - * regs is struct pt_regs, pr_reg is elf_gregset_t (which is - * now struct user_regs, they are different) - * - ELF_CORE_COPY_REGS has been guessed, and may be wrong - */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ -do { \ - pr_reg[0] = regs->a3; \ - pr_reg[1] = regs->a2; \ - pr_reg[2] = regs->d3; \ - pr_reg[3] = regs->d2; \ - pr_reg[4] = regs->mcvf; \ - pr_reg[5] = regs->mcrl; \ - pr_reg[6] = regs->mcrh; \ - pr_reg[7] = regs->mdrq; \ - pr_reg[8] = regs->e1; \ - pr_reg[9] = regs->e0; \ - pr_reg[10] = regs->e7; \ - pr_reg[11] = regs->e6; \ - pr_reg[12] = regs->e5; \ - pr_reg[13] = regs->e4; \ - pr_reg[14] = regs->e3; \ - pr_reg[15] = regs->e2; \ - pr_reg[16] = regs->sp; \ - pr_reg[17] = regs->lar; \ - pr_reg[18] = regs->lir; \ - pr_reg[19] = regs->mdr; \ - pr_reg[20] = regs->a1; \ - pr_reg[21] = regs->a0; \ - pr_reg[22] = regs->d1; \ - pr_reg[23] = regs->d0; \ - pr_reg[24] = regs->orig_d0; \ - pr_reg[25] = regs->epsw; \ - pr_reg[26] = regs->pc; \ -} while (0); - -/* - * This yields a mask that user programs can use to figure out what - * instruction set this CPU supports. This could be done in user space, - * but it's not easy, and we've already done it here. - */ -#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT -#define ELF_HWCAP (HWCAP_MN10300_ATOMIC_OP_UNIT) -#else -#define ELF_HWCAP (0) -#endif - -/* - * This yields a string that ld.so will use to load implementation - * specific libraries for optimization. This is more specific in - * intent than poking at uname or /proc/cpuinfo. - * - * For the moment, we have only optimizations for the Intel generations, - * but that could change... - */ -#define ELF_PLATFORM (NULL) - -#endif /* _ASM_ELF_H */ diff --git a/arch/mn10300/include/asm/emergency-restart.h b/arch/mn10300/include/asm/emergency-restart.h deleted file mode 100644 index 3711bd9d50bd..000000000000 --- a/arch/mn10300/include/asm/emergency-restart.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/exceptions.h b/arch/mn10300/include/asm/exceptions.h deleted file mode 100644 index 95a4d42c3a06..000000000000 --- a/arch/mn10300/include/asm/exceptions.h +++ /dev/null @@ -1,121 +0,0 @@ -/* MN10300 Microcontroller core exceptions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_EXCEPTIONS_H -#define _ASM_EXCEPTIONS_H - -#include - -/* - * define the breakpoint instruction opcode to use - * - note that the JTAG unit steals 0xFF, so you can't use JTAG and GDBSTUB at - * the same time. - */ -#define GDBSTUB_BKPT 0xFF - -#ifndef __ASSEMBLY__ - -/* - * enumeration of exception codes (as extracted from TBR MSW) - */ -enum exception_code { - EXCEP_RESET = 0x000000, /* reset */ - - /* MMU exceptions */ - EXCEP_ITLBMISS = 0x000100, /* instruction TLB miss */ - EXCEP_DTLBMISS = 0x000108, /* data TLB miss */ - EXCEP_IAERROR = 0x000110, /* instruction address */ - EXCEP_DAERROR = 0x000118, /* data address */ - - /* system exceptions */ - EXCEP_TRAP = 0x000128, /* program interrupt (PI instruction) */ - EXCEP_ISTEP = 0x000130, /* single step */ - EXCEP_IBREAK = 0x000150, /* instruction breakpoint */ - EXCEP_OBREAK = 0x000158, /* operand breakpoint */ - EXCEP_PRIVINS = 0x000160, /* privileged instruction execution */ - EXCEP_UNIMPINS = 0x000168, /* unimplemented instruction execution */ - EXCEP_UNIMPEXINS = 0x000170, /* unimplemented extended instruction execution */ - EXCEP_MEMERR = 0x000178, /* illegal memory access */ - EXCEP_MISALIGN = 0x000180, /* misalignment */ - EXCEP_BUSERROR = 0x000188, /* bus error */ - EXCEP_ILLINSACC = 0x000190, /* illegal instruction access */ - EXCEP_ILLDATACC = 0x000198, /* illegal data access */ - EXCEP_IOINSACC = 0x0001a0, /* I/O space instruction access */ - EXCEP_PRIVINSACC = 0x0001a8, /* privileged space instruction access */ - EXCEP_PRIVDATACC = 0x0001b0, /* privileged space data access */ - EXCEP_DATINSACC = 0x0001b8, /* data space instruction access */ - EXCEP_DOUBLE_FAULT = 0x000200, /* double fault */ - - /* FPU exceptions */ - EXCEP_FPU_DISABLED = 0x0001c0, /* FPU disabled */ - EXCEP_FPU_UNIMPINS = 0x0001c8, /* FPU unimplemented operation */ - EXCEP_FPU_OPERATION = 0x0001d0, /* FPU operation */ - - /* interrupts */ - EXCEP_WDT = 0x000240, /* watchdog timer overflow */ - EXCEP_NMI = 0x000248, /* non-maskable interrupt */ - EXCEP_IRQ_LEVEL0 = 0x000280, /* level 0 maskable interrupt */ - EXCEP_IRQ_LEVEL1 = 0x000288, /* level 1 maskable interrupt */ - EXCEP_IRQ_LEVEL2 = 0x000290, /* level 2 maskable interrupt */ - EXCEP_IRQ_LEVEL3 = 0x000298, /* level 3 maskable interrupt */ - EXCEP_IRQ_LEVEL4 = 0x0002a0, /* level 4 maskable interrupt */ - EXCEP_IRQ_LEVEL5 = 0x0002a8, /* level 5 maskable interrupt */ - EXCEP_IRQ_LEVEL6 = 0x0002b0, /* level 6 maskable interrupt */ - - /* system calls */ - EXCEP_SYSCALL0 = 0x000300, /* system call 0 */ - EXCEP_SYSCALL1 = 0x000308, /* system call 1 */ - EXCEP_SYSCALL2 = 0x000310, /* system call 2 */ - EXCEP_SYSCALL3 = 0x000318, /* system call 3 */ - EXCEP_SYSCALL4 = 0x000320, /* system call 4 */ - EXCEP_SYSCALL5 = 0x000328, /* system call 5 */ - EXCEP_SYSCALL6 = 0x000330, /* system call 6 */ - EXCEP_SYSCALL7 = 0x000338, /* system call 7 */ - EXCEP_SYSCALL8 = 0x000340, /* system call 8 */ - EXCEP_SYSCALL9 = 0x000348, /* system call 9 */ - EXCEP_SYSCALL10 = 0x000350, /* system call 10 */ - EXCEP_SYSCALL11 = 0x000358, /* system call 11 */ - EXCEP_SYSCALL12 = 0x000360, /* system call 12 */ - EXCEP_SYSCALL13 = 0x000368, /* system call 13 */ - EXCEP_SYSCALL14 = 0x000370, /* system call 14 */ - EXCEP_SYSCALL15 = 0x000378, /* system call 15 */ -}; - -extern void __set_intr_stub(enum exception_code code, void *handler); -extern void set_intr_stub(enum exception_code code, void *handler); - -struct pt_regs; - -extern asmlinkage void __common_exception(void); -extern asmlinkage void itlb_miss(void); -extern asmlinkage void dtlb_miss(void); -extern asmlinkage void itlb_aerror(void); -extern asmlinkage void dtlb_aerror(void); -extern asmlinkage void raw_bus_error(void); -extern asmlinkage void double_fault(void); -extern asmlinkage int system_call(struct pt_regs *); -extern asmlinkage void nmi(struct pt_regs *, enum exception_code); -extern asmlinkage void uninitialised_exception(struct pt_regs *, - enum exception_code); -extern asmlinkage void irq_handler(void); -extern asmlinkage void profile_handler(void); -extern asmlinkage void nmi_handler(void); -extern asmlinkage void misalignment(struct pt_regs *, enum exception_code); - -extern void die(const char *, struct pt_regs *, enum exception_code) - __noreturn; - -extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code); - -#define NUM2EXCEP_IRQ_LEVEL(num) (EXCEP_IRQ_LEVEL0 + (num) * 8) - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_EXCEPTIONS_H */ diff --git a/arch/mn10300/include/asm/fpu.h b/arch/mn10300/include/asm/fpu.h deleted file mode 100644 index a47e995d45f3..000000000000 --- a/arch/mn10300/include/asm/fpu.h +++ /dev/null @@ -1,132 +0,0 @@ -/* MN10300 FPU definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * Derived from include/asm-i386/i387.h: Copyright (C) 1994 Linus Torvalds - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_FPU_H -#define _ASM_FPU_H - -#ifndef __ASSEMBLY__ - -#include -#include -#include - -#ifdef __KERNEL__ - -extern asmlinkage void fpu_disabled(void); - -#ifdef CONFIG_FPU - -#ifdef CONFIG_LAZY_SAVE_FPU -/* the task that currently owns the FPU state */ -extern struct task_struct *fpu_state_owner; -#endif - -#if (THREAD_USING_FPU & ~0xff) -#error THREAD_USING_FPU must be smaller than 0x100. -#endif - -static inline void set_using_fpu(struct task_struct *tsk) -{ - asm volatile( - "bset %0,(0,%1)" - : - : "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags) - : "memory", "cc"); -} - -static inline void clear_using_fpu(struct task_struct *tsk) -{ - asm volatile( - "bclr %0,(0,%1)" - : - : "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags) - : "memory", "cc"); -} - -#define is_using_fpu(tsk) ((tsk)->thread.fpu_flags & THREAD_USING_FPU) - -extern asmlinkage void fpu_kill_state(struct task_struct *); -extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code); -extern asmlinkage void fpu_init_state(void); -extern asmlinkage void fpu_save(struct fpu_state_struct *); -extern int fpu_setup_sigcontext(struct fpucontext *buf); -extern int fpu_restore_sigcontext(struct fpucontext *buf); - -static inline void unlazy_fpu(struct task_struct *tsk) -{ - preempt_disable(); -#ifndef CONFIG_LAZY_SAVE_FPU - if (tsk->thread.fpu_flags & THREAD_HAS_FPU) { - fpu_save(&tsk->thread.fpu_state); - tsk->thread.fpu_flags &= ~THREAD_HAS_FPU; - tsk->thread.uregs->epsw &= ~EPSW_FE; - } -#else - if (fpu_state_owner == tsk) - fpu_save(&tsk->thread.fpu_state); -#endif - preempt_enable(); -} - -static inline void exit_fpu(struct task_struct *tsk) -{ -#ifdef CONFIG_LAZY_SAVE_FPU - preempt_disable(); - if (fpu_state_owner == tsk) - fpu_state_owner = NULL; - preempt_enable(); -#endif -} - -static inline void flush_fpu(void) -{ - struct task_struct *tsk = current; - - preempt_disable(); -#ifndef CONFIG_LAZY_SAVE_FPU - if (tsk->thread.fpu_flags & THREAD_HAS_FPU) { - tsk->thread.fpu_flags &= ~THREAD_HAS_FPU; - tsk->thread.uregs->epsw &= ~EPSW_FE; - } -#else - if (fpu_state_owner == tsk) { - fpu_state_owner = NULL; - tsk->thread.uregs->epsw &= ~EPSW_FE; - } -#endif - preempt_enable(); - clear_using_fpu(tsk); -} - -#else /* CONFIG_FPU */ - -extern asmlinkage -void unexpected_fpu_exception(struct pt_regs *, enum exception_code); -#define fpu_exception unexpected_fpu_exception - -struct task_struct; -struct fpu_state_struct; -static inline bool is_using_fpu(struct task_struct *tsk) { return false; } -static inline void set_using_fpu(struct task_struct *tsk) {} -static inline void clear_using_fpu(struct task_struct *tsk) {} -static inline void fpu_init_state(void) {} -static inline void fpu_save(struct fpu_state_struct *s) {} -static inline void fpu_kill_state(struct task_struct *tsk) {} -static inline void unlazy_fpu(struct task_struct *tsk) {} -static inline void exit_fpu(struct task_struct *tsk) {} -static inline void flush_fpu(void) {} -static inline int fpu_setup_sigcontext(struct fpucontext *buf) { return 0; } -static inline int fpu_restore_sigcontext(struct fpucontext *buf) { return 0; } -#endif /* CONFIG_FPU */ - -#endif /* __KERNEL__ */ -#endif /* !__ASSEMBLY__ */ -#endif /* _ASM_FPU_H */ diff --git a/arch/mn10300/include/asm/frame.inc b/arch/mn10300/include/asm/frame.inc deleted file mode 100644 index 1c3eb4fda958..000000000000 --- a/arch/mn10300/include/asm/frame.inc +++ /dev/null @@ -1,97 +0,0 @@ -/* MN10300 Microcontroller core system register definitions -*- asm -*- - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_FRAME_INC -#define _ASM_FRAME_INC - -#ifndef __ASSEMBLY__ -#error not for use in C files -#endif - -#ifndef __ASM_OFFSETS_H__ -#include -#endif -#include - -#define pi break - -#define fp a3 - -############################################################################### -# -# build a stack frame from the registers -# - the caller has subtracted 4 from SP before coming here -# -############################################################################### -.macro SAVE_ALL - add -4,sp # next exception frame ptr save area - movm [other],(sp) - mov usp,a1 - mov a1,(sp) # USP in MOVM[other] dummy slot - movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp) - mov sp,fp # FRAME pointer in A3 - add -12,sp # allow for calls to be made - - # push the exception frame onto the front of the list - GET_THREAD_INFO a1 - mov (TI_frame,a1),a0 - mov a0,(REG_NEXT,fp) - mov fp,(TI_frame,a1) - - # disable the FPU inside the kernel - and ~EPSW_FE,epsw - - # we may be holding current in E2 -#ifdef CONFIG_MN10300_CURRENT_IN_E2 - mov (__current),e2 -#endif -.endm - -############################################################################### -# -# restore the registers from a stack frame -# -############################################################################### -.macro RESTORE_ALL - # peel back the stack to the calling frame - # - we need that when returning from interrupts to kernel mode - GET_THREAD_INFO a0 - mov (TI_frame,a0),fp - mov fp,sp - mov (REG_NEXT,fp),d0 - mov d0,(TI_frame,a0) # userspace has regs->next == 0 - -#ifndef CONFIG_MN10300_USING_JTAG - mov (REG_EPSW,fp),d0 - btst EPSW_T,d0 - beq 99f - - or EPSW_NMID,epsw - movhu (DCR),d1 - or 0x0001, d1 - movhu d1,(DCR) - -99: -#endif - movm (sp),[d2,d3,a2,a3,exreg0,exreg1,exother] - - # must restore usp even if returning to kernel space, - # when CONFIG_PREEMPT is enabled. - mov (sp),a1 # USP in MOVM[other] dummy slot - mov a1,usp - - movm (sp),[other] - add 8,sp - rti - -.endm - - -#endif /* _ASM_FRAME_INC */ diff --git a/arch/mn10300/include/asm/ftrace.h b/arch/mn10300/include/asm/ftrace.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/arch/mn10300/include/asm/ftrace.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/mn10300/include/asm/futex.h b/arch/mn10300/include/asm/futex.h deleted file mode 100644 index 0b745828f42b..000000000000 --- a/arch/mn10300/include/asm/futex.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/gdb-stub.h b/arch/mn10300/include/asm/gdb-stub.h deleted file mode 100644 index f5495ad82b77..000000000000 --- a/arch/mn10300/include/asm/gdb-stub.h +++ /dev/null @@ -1,182 +0,0 @@ -/* MN10300 Kernel GDB stub definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_GDB_STUB_H -#define _ASM_GDB_STUB_H - -#include - -/* - * register ID numbers in GDB remote protocol - */ - -#define GDB_REGID_PC 9 -#define GDB_REGID_FP 7 -#define GDB_REGID_SP 8 - -/* - * virtual stack layout for the GDB exception handler - */ -#define NUMREGS 64 - -#define GDB_FR_D0 (0 * 4) -#define GDB_FR_D1 (1 * 4) -#define GDB_FR_D2 (2 * 4) -#define GDB_FR_D3 (3 * 4) -#define GDB_FR_A0 (4 * 4) -#define GDB_FR_A1 (5 * 4) -#define GDB_FR_A2 (6 * 4) -#define GDB_FR_A3 (7 * 4) - -#define GDB_FR_SP (8 * 4) -#define GDB_FR_PC (9 * 4) -#define GDB_FR_MDR (10 * 4) -#define GDB_FR_EPSW (11 * 4) -#define GDB_FR_LIR (12 * 4) -#define GDB_FR_LAR (13 * 4) -#define GDB_FR_MDRQ (14 * 4) - -#define GDB_FR_E0 (15 * 4) -#define GDB_FR_E1 (16 * 4) -#define GDB_FR_E2 (17 * 4) -#define GDB_FR_E3 (18 * 4) -#define GDB_FR_E4 (19 * 4) -#define GDB_FR_E5 (20 * 4) -#define GDB_FR_E6 (21 * 4) -#define GDB_FR_E7 (22 * 4) - -#define GDB_FR_SSP (23 * 4) -#define GDB_FR_MSP (24 * 4) -#define GDB_FR_USP (25 * 4) -#define GDB_FR_MCRH (26 * 4) -#define GDB_FR_MCRL (27 * 4) -#define GDB_FR_MCVF (28 * 4) - -#define GDB_FR_FPCR (29 * 4) -#define GDB_FR_DUMMY0 (30 * 4) -#define GDB_FR_DUMMY1 (31 * 4) - -#define GDB_FR_FS0 (32 * 4) - -#define GDB_FR_SIZE (NUMREGS * 4) - -#ifndef __ASSEMBLY__ - -/* - * This is the same as above, but for the high-level - * part of the GDB stub. - */ - -struct gdb_regs { - /* saved main processor registers */ - u32 d0, d1, d2, d3, a0, a1, a2, a3; - u32 sp, pc, mdr, epsw, lir, lar, mdrq; - u32 e0, e1, e2, e3, e4, e5, e6, e7; - u32 ssp, msp, usp, mcrh, mcrl, mcvf; - - /* saved floating point registers */ - u32 fpcr, _dummy0, _dummy1; - u32 fs0, fs1, fs2, fs3, fs4, fs5, fs6, fs7; - u32 fs8, fs9, fs10, fs11, fs12, fs13, fs14, fs15; - u32 fs16, fs17, fs18, fs19, fs20, fs21, fs22, fs23; - u32 fs24, fs25, fs26, fs27, fs28, fs29, fs30, fs31; -}; - -/* - * Prototypes - */ -extern void show_registers_only(struct pt_regs *regs); - -extern asmlinkage void gdbstub_init(void); -extern asmlinkage void gdbstub_exit(int status); -extern asmlinkage void gdbstub_io_init(void); -extern asmlinkage void gdbstub_io_set_baud(unsigned baud); -extern asmlinkage int gdbstub_io_rx_char(unsigned char *_ch, int nonblock); -extern asmlinkage void gdbstub_io_tx_char(unsigned char ch); -extern asmlinkage void gdbstub_io_tx_flush(void); - -extern asmlinkage void gdbstub_io_rx_handler(void); -extern asmlinkage void gdbstub_rx_irq(struct pt_regs *, enum exception_code); -extern asmlinkage int gdbstub_intercept(struct pt_regs *, enum exception_code); -extern asmlinkage void gdbstub_exception(struct pt_regs *, enum exception_code); -extern asmlinkage void __gdbstub_bug_trap(void); -extern asmlinkage void __gdbstub_pause(void); - -#ifdef CONFIG_MN10300_CACHE_ENABLED -extern asmlinkage void gdbstub_purge_cache(void); -#else -#define gdbstub_purge_cache() do {} while (0) -#endif - -/* Used to prevent crashes in memory access */ -extern asmlinkage int gdbstub_read_byte(const u8 *, u8 *); -extern asmlinkage int gdbstub_read_word(const u8 *, u8 *); -extern asmlinkage int gdbstub_read_dword(const u8 *, u8 *); -extern asmlinkage int gdbstub_write_byte(u32, u8 *); -extern asmlinkage int gdbstub_write_word(u32, u8 *); -extern asmlinkage int gdbstub_write_dword(u32, u8 *); - -extern asmlinkage void gdbstub_read_byte_guard(void); -extern asmlinkage void gdbstub_read_byte_cont(void); -extern asmlinkage void gdbstub_read_word_guard(void); -extern asmlinkage void gdbstub_read_word_cont(void); -extern asmlinkage void gdbstub_read_dword_guard(void); -extern asmlinkage void gdbstub_read_dword_cont(void); -extern asmlinkage void gdbstub_write_byte_guard(void); -extern asmlinkage void gdbstub_write_byte_cont(void); -extern asmlinkage void gdbstub_write_word_guard(void); -extern asmlinkage void gdbstub_write_word_cont(void); -extern asmlinkage void gdbstub_write_dword_guard(void); -extern asmlinkage void gdbstub_write_dword_cont(void); - -extern u8 gdbstub_rx_buffer[PAGE_SIZE]; -extern u32 gdbstub_rx_inp; -extern u32 gdbstub_rx_outp; -extern u8 gdbstub_rx_overflow; -extern u8 gdbstub_busy; -extern u8 gdbstub_rx_unget; - -#ifdef CONFIG_GDBSTUB_DEBUGGING -extern void gdbstub_printk(const char *fmt, ...) - __attribute__((format(printf, 1, 2))); -#else -static inline __attribute__((format(printf, 1, 2))) -void gdbstub_printk(const char *fmt, ...) -{ -} -#endif - -#ifdef CONFIG_GDBSTUB_DEBUG_ENTRY -#define gdbstub_entry(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) -#else -#define gdbstub_entry(FMT, ...) no_printk(FMT, ##__VA_ARGS__) -#endif - -#ifdef CONFIG_GDBSTUB_DEBUG_PROTOCOL -#define gdbstub_proto(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) -#else -#define gdbstub_proto(FMT, ...) no_printk(FMT, ##__VA_ARGS__) -#endif - -#ifdef CONFIG_GDBSTUB_DEBUG_IO -#define gdbstub_io(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) -#else -#define gdbstub_io(FMT, ...) no_printk(FMT, ##__VA_ARGS__) -#endif - -#ifdef CONFIG_GDBSTUB_DEBUG_BREAKPOINT -#define gdbstub_bkpt(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) -#else -#define gdbstub_bkpt(FMT, ...) no_printk(FMT, ##__VA_ARGS__) -#endif - -#endif /* !__ASSEMBLY__ */ -#endif /* _ASM_GDB_STUB_H */ diff --git a/arch/mn10300/include/asm/hardirq.h b/arch/mn10300/include/asm/hardirq.h deleted file mode 100644 index 0000d650b55f..000000000000 --- a/arch/mn10300/include/asm/hardirq.h +++ /dev/null @@ -1,49 +0,0 @@ -/* MN10300 Hardware IRQ statistics and management - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_HARDIRQ_H -#define _ASM_HARDIRQ_H - -#include -#include -#include - -/* assembly code in softirq.h is sensitive to the offsets of these fields */ -typedef struct { - unsigned int __softirq_pending; -#ifdef CONFIG_MN10300_WD_TIMER - unsigned int __nmi_count; /* arch dependent */ - unsigned int __irq_count; /* arch dependent */ -#endif -} ____cacheline_aligned irq_cpustat_t; - -#include /* Standard mappings for irq_cpustat_t above */ - -extern void ack_bad_irq(int irq); - -/* - * manipulate stubs in the MN10300 CPU Trap/Interrupt Vector table - * - these should jump to __common_exception in entry.S unless there's a good - * reason to do otherwise (see trap_preinit() in traps.c) - */ -typedef void (*intr_stub_fnx)(struct pt_regs *regs, - enum exception_code intcode); - -/* - * manipulate pointers in the Exception table (see entry.S) - * - these are indexed by decoding the lower 24 bits of the TBR register - * - note that the MN103E010 doesn't always trap through the correct vector, - * but does always set the TBR correctly - */ -extern asmlinkage void set_excp_vector(enum exception_code code, - intr_stub_fnx handler); - -#endif /* _ASM_HARDIRQ_H */ diff --git a/arch/mn10300/include/asm/highmem.h b/arch/mn10300/include/asm/highmem.h deleted file mode 100644 index 1ddea5afba09..000000000000 --- a/arch/mn10300/include/asm/highmem.h +++ /dev/null @@ -1,131 +0,0 @@ -/* MN10300 Virtual kernel memory mappings for high memory - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - Derived from include/asm-i386/highmem.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_HIGHMEM_H -#define _ASM_HIGHMEM_H - -#ifdef __KERNEL__ - -#include -#include -#include -#include -#include - -/* undef for production */ -#undef HIGHMEM_DEBUG - -/* declarations for highmem.c */ -extern unsigned long highstart_pfn, highend_pfn; - -extern pte_t *kmap_pte; -extern pgprot_t kmap_prot; -extern pte_t *pkmap_page_table; - -extern void __init kmap_init(void); - -/* - * Right now we initialize only a single pte table. It can be extended - * easily, subsequent pte tables have to be allocated in one physical - * chunk of RAM. - */ -#define PKMAP_BASE 0xfe000000UL -#define LAST_PKMAP 1024 -#define LAST_PKMAP_MASK (LAST_PKMAP - 1) -#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT) -#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) - -extern unsigned long kmap_high(struct page *page); -extern void kunmap_high(struct page *page); - -static inline unsigned long kmap(struct page *page) -{ - if (in_interrupt()) - BUG(); - if (page < highmem_start_page) - return page_address(page); - return kmap_high(page); -} - -static inline void kunmap(struct page *page) -{ - if (in_interrupt()) - BUG(); - if (page < highmem_start_page) - return; - kunmap_high(page); -} - -/* - * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap - * gives a more generic (and caching) interface. But kmap_atomic can - * be used in IRQ contexts, so in some (very limited) cases we need - * it. - */ -static inline void *kmap_atomic(struct page *page) -{ - unsigned long vaddr; - int idx, type; - - preempt_disable(); - pagefault_disable(); - if (page < highmem_start_page) - return page_address(page); - - type = kmap_atomic_idx_push(); - idx = type + KM_TYPE_NR * smp_processor_id(); - vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); -#if HIGHMEM_DEBUG - if (!pte_none(*(kmap_pte - idx))) - BUG(); -#endif - set_pte(kmap_pte - idx, mk_pte(page, kmap_prot)); - local_flush_tlb_one(vaddr); - - return (void *)vaddr; -} - -static inline void __kunmap_atomic(unsigned long vaddr) -{ - int type; - - if (vaddr < FIXADDR_START) { /* FIXME */ - pagefault_enable(); - preempt_enable(); - return; - } - - type = kmap_atomic_idx(); - -#if HIGHMEM_DEBUG - { - unsigned int idx; - idx = type + KM_TYPE_NR * smp_processor_id(); - - if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)) - BUG(); - - /* - * force other mappings to Oops if they'll try to access - * this pte without first remap it - */ - pte_clear(kmap_pte - idx); - local_flush_tlb_one(vaddr); - } -#endif - - kmap_atomic_idx_pop(); - pagefault_enable(); - preempt_enable(); -} -#endif /* __KERNEL__ */ - -#endif /* _ASM_HIGHMEM_H */ diff --git a/arch/mn10300/include/asm/hw_irq.h b/arch/mn10300/include/asm/hw_irq.h deleted file mode 100644 index 70619901098e..000000000000 --- a/arch/mn10300/include/asm/hw_irq.h +++ /dev/null @@ -1,14 +0,0 @@ -/* MN10300 Hardware interrupt definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_HW_IRQ_H -#define _ASM_HW_IRQ_H - -#endif /* _ASM_HW_IRQ_H */ diff --git a/arch/mn10300/include/asm/intctl-regs.h b/arch/mn10300/include/asm/intctl-regs.h deleted file mode 100644 index d65bbeebe50a..000000000000 --- a/arch/mn10300/include/asm/intctl-regs.h +++ /dev/null @@ -1,71 +0,0 @@ -/* MN10300 On-board interrupt controller registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_INTCTL_REGS_H -#define _ASM_INTCTL_REGS_H - -#include - -#ifdef __KERNEL__ - -/* - * Interrupt controller registers - * - Registers 64-191 are at addresses offset from the main array - */ -#define GxICR(X) \ - __SYSREG(0xd4000000 + (X) * 4 + \ - (((X) >= 64) && ((X) < 192)) * 0xf00, u16) - -#define GxICR_u8(X) \ - __SYSREG(0xd4000000 + (X) * 4 + \ - (((X) >= 64) && ((X) < 192)) * 0xf00, u8) - -#include - -#define XIRQ_TRIGGER_LOWLEVEL 0 -#define XIRQ_TRIGGER_HILEVEL 1 -#define XIRQ_TRIGGER_NEGEDGE 2 -#define XIRQ_TRIGGER_POSEDGE 3 - -/* non-maskable interrupt control */ -#define NMIIRQ 0 -#define NMICR GxICR(NMIIRQ) /* NMI control register */ -#define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */ -#define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */ -#define NMICR_ABUSERR 0x0008 /* async bus error flag */ - -/* maskable interrupt control */ -#define GxICR_DETECT 0x0001 /* interrupt detect flag */ -#define GxICR_REQUEST 0x0010 /* interrupt request flag */ -#define GxICR_ENABLE 0x0100 /* interrupt enable flag */ -#define GxICR_LEVEL 0x7000 /* interrupt priority level */ -#define GxICR_LEVEL_0 0x0000 /* - level 0 */ -#define GxICR_LEVEL_1 0x1000 /* - level 1 */ -#define GxICR_LEVEL_2 0x2000 /* - level 2 */ -#define GxICR_LEVEL_3 0x3000 /* - level 3 */ -#define GxICR_LEVEL_4 0x4000 /* - level 4 */ -#define GxICR_LEVEL_5 0x5000 /* - level 5 */ -#define GxICR_LEVEL_6 0x6000 /* - level 6 */ -#define GxICR_LEVEL_SHIFT 12 -#define GxICR_NMI 0x8000 /* nmi request flag */ - -#define NUM2GxICR_LEVEL(num) ((num) << GxICR_LEVEL_SHIFT) - -#ifndef __ASSEMBLY__ -extern void set_intr_level(int irq, u16 level); -extern void mn10300_set_lateack_irq_type(int irq); -#endif - -/* external interrupts */ -#define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_INTCTL_REGS_H */ diff --git a/arch/mn10300/include/asm/io.h b/arch/mn10300/include/asm/io.h deleted file mode 100644 index 62189353d2f6..000000000000 --- a/arch/mn10300/include/asm/io.h +++ /dev/null @@ -1,325 +0,0 @@ -/* MN10300 I/O port emulation and memory-mapped I/O - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_IO_H -#define _ASM_IO_H - -#include /* I/O is all done through memory accesses */ -#include -#include -#include - -#define mmiowb() do {} while (0) - -/*****************************************************************************/ -/* - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the x86 architecture, we just read/write the - * memory location directly. - */ -static inline u8 readb(const volatile void __iomem *addr) -{ - return *(const volatile u8 *) addr; -} - -static inline u16 readw(const volatile void __iomem *addr) -{ - return *(const volatile u16 *) addr; -} - -static inline u32 readl(const volatile void __iomem *addr) -{ - return *(const volatile u32 *) addr; -} - -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - -#define readb_relaxed readb -#define readw_relaxed readw -#define readl_relaxed readl - -static inline void writeb(u8 b, volatile void __iomem *addr) -{ - *(volatile u8 *) addr = b; -} - -static inline void writew(u16 b, volatile void __iomem *addr) -{ - *(volatile u16 *) addr = b; -} - -static inline void writel(u32 b, volatile void __iomem *addr) -{ - *(volatile u32 *) addr = b; -} - -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -#define writeb_relaxed writeb -#define writew_relaxed writew -#define writel_relaxed writel - -/*****************************************************************************/ -/* - * traditional input/output functions - */ -static inline u8 inb_local(unsigned long addr) -{ - return readb((volatile void __iomem *) addr); -} - -static inline void outb_local(u8 b, unsigned long addr) -{ - return writeb(b, (volatile void __iomem *) addr); -} - -static inline u8 inb(unsigned long addr) -{ - return readb((volatile void __iomem *) addr); -} - -static inline u16 inw(unsigned long addr) -{ - return readw((volatile void __iomem *) addr); -} - -static inline u32 inl(unsigned long addr) -{ - return readl((volatile void __iomem *) addr); -} - -static inline void outb(u8 b, unsigned long addr) -{ - return writeb(b, (volatile void __iomem *) addr); -} - -static inline void outw(u16 b, unsigned long addr) -{ - return writew(b, (volatile void __iomem *) addr); -} - -static inline void outl(u32 b, unsigned long addr) -{ - return writel(b, (volatile void __iomem *) addr); -} - -#define inb_p(addr) inb(addr) -#define inw_p(addr) inw(addr) -#define inl_p(addr) inl(addr) -#define outb_p(x, addr) outb((x), (addr)) -#define outw_p(x, addr) outw((x), (addr)) -#define outl_p(x, addr) outl((x), (addr)) - -static inline void insb(unsigned long addr, void *buffer, int count) -{ - if (count) { - u8 *buf = buffer; - do { - u8 x = inb(addr); - *buf++ = x; - } while (--count); - } -} - -static inline void insw(unsigned long addr, void *buffer, int count) -{ - if (count) { - u16 *buf = buffer; - do { - u16 x = inw(addr); - *buf++ = x; - } while (--count); - } -} - -static inline void insl(unsigned long addr, void *buffer, int count) -{ - if (count) { - u32 *buf = buffer; - do { - u32 x = inl(addr); - *buf++ = x; - } while (--count); - } -} - -static inline void outsb(unsigned long addr, const void *buffer, int count) -{ - if (count) { - const u8 *buf = buffer; - do { - outb(*buf++, addr); - } while (--count); - } -} - -static inline void outsw(unsigned long addr, const void *buffer, int count) -{ - if (count) { - const u16 *buf = buffer; - do { - outw(*buf++, addr); - } while (--count); - } -} - -extern void __outsl(unsigned long addr, const void *buffer, int count); -static inline void outsl(unsigned long addr, const void *buffer, int count) -{ - if ((unsigned long) buffer & 0x3) - return __outsl(addr, buffer, count); - - if (count) { - const u32 *buf = buffer; - do { - outl(*buf++, addr); - } while (--count); - } -} - -#define ioread8(addr) readb(addr) -#define ioread16(addr) readw(addr) -#define ioread32(addr) readl(addr) - -#define iowrite8(v, addr) writeb((v), (addr)) -#define iowrite16(v, addr) writew((v), (addr)) -#define iowrite32(v, addr) writel((v), (addr)) - -#define ioread16be(addr) be16_to_cpu(readw(addr)) -#define ioread32be(addr) be32_to_cpu(readl(addr)) -#define iowrite16be(v, addr) writew(cpu_to_be16(v), (addr)) -#define iowrite32be(v, addr) writel(cpu_to_be32(v), (addr)) - -#define ioread8_rep(p, dst, count) \ - insb((unsigned long) (p), (dst), (count)) -#define ioread16_rep(p, dst, count) \ - insw((unsigned long) (p), (dst), (count)) -#define ioread32_rep(p, dst, count) \ - insl((unsigned long) (p), (dst), (count)) - -#define iowrite8_rep(p, src, count) \ - outsb((unsigned long) (p), (src), (count)) -#define iowrite16_rep(p, src, count) \ - outsw((unsigned long) (p), (src), (count)) -#define iowrite32_rep(p, src, count) \ - outsl((unsigned long) (p), (src), (count)) - -#define readsb(p, dst, count) \ - insb((unsigned long) (p), (dst), (count)) -#define readsw(p, dst, count) \ - insw((unsigned long) (p), (dst), (count)) -#define readsl(p, dst, count) \ - insl((unsigned long) (p), (dst), (count)) - -#define writesb(p, src, count) \ - outsb((unsigned long) (p), (src), (count)) -#define writesw(p, src, count) \ - outsw((unsigned long) (p), (src), (count)) -#define writesl(p, src, count) \ - outsl((unsigned long) (p), (src), (count)) - -#define IO_SPACE_LIMIT 0xffffffff - -#ifdef __KERNEL__ - -#include -#define __io_virt(x) ((void *) (x)) - -/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ -struct pci_dev; -static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) -{ -} - -/* - * Change virtual addresses to physical addresses and vv. - * These are pretty trivial - */ -static inline unsigned long virt_to_phys(volatile void *address) -{ - return __pa(address); -} - -static inline void *phys_to_virt(unsigned long address) -{ - return __va(address); -} - -/* - * Change "struct page" to physical address. - */ -static inline void __iomem *__ioremap(unsigned long offset, unsigned long size, - unsigned long flags) -{ - return (void __iomem *) offset; -} - -static inline void __iomem *ioremap(unsigned long offset, unsigned long size) -{ - return (void __iomem *)(offset & ~0x20000000); -} - -/* - * This one maps high address device memory and turns off caching for that - * area. it's useful if some control registers are in such an area and write - * combining or read caching is not desirable: - */ -static inline void __iomem *ioremap_nocache(unsigned long offset, unsigned long size) -{ - return (void __iomem *) (offset | 0x20000000); -} - -#define ioremap_wc ioremap_nocache -#define ioremap_wt ioremap_nocache -#define ioremap_uc ioremap_nocache - -static inline void iounmap(void __iomem *addr) -{ -} - -static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) -{ - return (void __iomem *) port; -} - -static inline void ioport_unmap(void __iomem *p) -{ -} - -#define xlate_dev_kmem_ptr(p) ((void *) (p)) -#define xlate_dev_mem_ptr(p) ((void *) (p)) - -/* - * PCI bus iomem addresses must be in the region 0x80000000-0x9fffffff - */ -static inline unsigned long virt_to_bus(volatile void *address) -{ - return ((unsigned long) address) & ~0x20000000; -} - -static inline void *bus_to_virt(unsigned long address) -{ - return (void *) address; -} - -#define page_to_bus page_to_phys - -#define memset_io(a, b, c) memset(__io_virt(a), (b), (c)) -#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c)) -#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c)) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IO_H */ diff --git a/arch/mn10300/include/asm/irq.h b/arch/mn10300/include/asm/irq.h deleted file mode 100644 index 1a73fb3f60c6..000000000000 --- a/arch/mn10300/include/asm/irq.h +++ /dev/null @@ -1,40 +0,0 @@ -/* MN10300 Hardware interrupt definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - Derived from include/asm-i386/irq.h: - * - (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -#include -#include -#include - -/* this number is used when no interrupt has been assigned */ -#define NO_IRQ INT_MAX - -/* - * hardware irq numbers - * - the ASB2364 has an FPGA with an IRQ multiplexer on it - */ -#ifdef CONFIG_MN10300_UNIT_ASB2364 -#include -#else -#define NR_CPU_IRQS GxICR_NUM_IRQS -#define NR_IRQS NR_CPU_IRQS -#endif - -/* external hardware irq numbers */ -#define NR_XIRQS GxICR_NUM_XIRQS - -#define irq_canonicalize(IRQ) (IRQ) - -#endif /* _ASM_IRQ_H */ diff --git a/arch/mn10300/include/asm/irq_regs.h b/arch/mn10300/include/asm/irq_regs.h deleted file mode 100644 index 97d0cb5af807..000000000000 --- a/arch/mn10300/include/asm/irq_regs.h +++ /dev/null @@ -1,28 +0,0 @@ -/* MN10300 IRQ registers pointer definition - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_IRQ_REGS_H -#define _ASM_IRQ_REGS_H - -/* - * Per-cpu current frame pointer - the location of the last exception frame on - * the stack - */ -#define ARCH_HAS_OWN_IRQ_REGS - -#ifndef __ASSEMBLY__ -static inline __attribute__((const)) -struct pt_regs *get_irq_regs(void) -{ - return current_frame(); -} -#endif - -#endif /* _ASM_IRQ_REGS_H */ diff --git a/arch/mn10300/include/asm/irqflags.h b/arch/mn10300/include/asm/irqflags.h deleted file mode 100644 index 8730c0a3c37d..000000000000 --- a/arch/mn10300/include/asm/irqflags.h +++ /dev/null @@ -1,215 +0,0 @@ -/* MN10300 IRQ flag handling - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_IRQFLAGS_H -#define _ASM_IRQFLAGS_H - -#include -/* linux/smp.h <- linux/irqflags.h needs asm/smp.h first */ -#include - -/* - * interrupt control - * - "disabled": run in IM1/2 - * - level 0 - kernel debugger - * - level 1 - virtual serial DMA (if present) - * - level 5 - normal interrupt priority - * - level 6 - timer interrupt - * - "enabled": run in IM7 - */ -#define MN10300_CLI_LEVEL (CONFIG_LINUX_CLI_LEVEL << EPSW_IM_SHIFT) - -#ifndef __ASSEMBLY__ - -static inline unsigned long arch_local_save_flags(void) -{ - unsigned long flags; - - asm volatile("mov epsw,%0" : "=d"(flags)); - return flags; -} - -static inline void arch_local_irq_disable(void) -{ - asm volatile( - " and %0,epsw \n" - " or %1,epsw \n" - " nop \n" - " nop \n" - " nop \n" - : - : "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL) - : "memory"); -} - -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - - flags = arch_local_save_flags(); - arch_local_irq_disable(); - return flags; -} - -/* - * we make sure arch_irq_enable() doesn't cause priority inversion - */ -extern unsigned long __mn10300_irq_enabled_epsw[]; - -static inline void arch_local_irq_enable(void) -{ - unsigned long tmp; - int cpu = raw_smp_processor_id(); - - asm volatile( - " mov epsw,%0 \n" - " and %1,%0 \n" - " or %2,%0 \n" - " mov %0,epsw \n" - : "=&d"(tmp) - : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw[cpu]) - : "memory", "cc"); -} - -static inline void arch_local_irq_restore(unsigned long flags) -{ - asm volatile( - " mov %0,epsw \n" - " nop \n" - " nop \n" - " nop \n" - : - : "d"(flags) - : "memory", "cc"); -} - -static inline bool arch_irqs_disabled_flags(unsigned long flags) -{ - return (flags & (EPSW_IE | EPSW_IM)) != (EPSW_IE | EPSW_IM_7); -} - -static inline bool arch_irqs_disabled(void) -{ - return arch_irqs_disabled_flags(arch_local_save_flags()); -} - -/* - * Hook to save power by halting the CPU - * - called from the idle loop - * - must reenable interrupts (which takes three instruction cycles to complete) - */ -static inline void arch_safe_halt(void) -{ -#ifdef CONFIG_SMP - arch_local_irq_enable(); -#else - asm volatile( - " or %0,epsw \n" - " nop \n" - " nop \n" - " bset %2,(%1) \n" - : - : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP) - : "cc"); -#endif -} - -#define __sleep_cpu() \ -do { \ - asm volatile( \ - " bset %1,(%0)\n" \ - "1: btst %1,(%0)\n" \ - " bne 1b\n" \ - : \ - : "i"(&CPUM), "i"(CPUM_SLEEP) \ - : "cc" \ - ); \ -} while (0) - -static inline void arch_local_cli(void) -{ - asm volatile( - " and %0,epsw \n" - " nop \n" - " nop \n" - " nop \n" - : - : "i"(~EPSW_IE) - : "memory" - ); -} - -static inline unsigned long arch_local_cli_save(void) -{ - unsigned long flags = arch_local_save_flags(); - arch_local_cli(); - return flags; -} - -static inline void arch_local_sti(void) -{ - asm volatile( - " or %0,epsw \n" - : - : "i"(EPSW_IE) - : "memory"); -} - -static inline void arch_local_change_intr_mask_level(unsigned long level) -{ - asm volatile( - " and %0,epsw \n" - " or %1,epsw \n" - : - : "i"(~EPSW_IM), "i"(EPSW_IE | level) - : "cc", "memory"); -} - -#else /* !__ASSEMBLY__ */ - -#define LOCAL_SAVE_FLAGS(reg) \ - mov epsw,reg - -#define LOCAL_IRQ_DISABLE \ - and ~EPSW_IM,epsw; \ - or EPSW_IE|MN10300_CLI_LEVEL,epsw; \ - nop; \ - nop; \ - nop - -#define LOCAL_IRQ_ENABLE \ - or EPSW_IE|EPSW_IM_7,epsw - -#define LOCAL_IRQ_RESTORE(reg) \ - mov reg,epsw - -#define LOCAL_CLI_SAVE(reg) \ - mov epsw,reg; \ - and ~EPSW_IE,epsw; \ - nop; \ - nop; \ - nop - -#define LOCAL_CLI \ - and ~EPSW_IE,epsw; \ - nop; \ - nop; \ - nop - -#define LOCAL_STI \ - or EPSW_IE,epsw - -#define LOCAL_CHANGE_INTR_MASK_LEVEL(level) \ - and ~EPSW_IM,epsw; \ - or EPSW_IE|(level),epsw - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_IRQFLAGS_H */ diff --git a/arch/mn10300/include/asm/kdebug.h b/arch/mn10300/include/asm/kdebug.h deleted file mode 100644 index 0f47e112190c..000000000000 --- a/arch/mn10300/include/asm/kdebug.h +++ /dev/null @@ -1,22 +0,0 @@ -/* MN10300 In-kernel death knells - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_KDEBUG_H -#define _ASM_KDEBUG_H - -/* Grossly misnamed. */ -enum die_val { - DIE_OOPS = 1, - DIE_BREAKPOINT, - DIE_GPF, -}; - -#endif /* _ASM_KDEBUG_H */ diff --git a/arch/mn10300/include/asm/kgdb.h b/arch/mn10300/include/asm/kgdb.h deleted file mode 100644 index eb245f18a708..000000000000 --- a/arch/mn10300/include/asm/kgdb.h +++ /dev/null @@ -1,81 +0,0 @@ -/* Kernel debugger for MN10300 - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_KGDB_H -#define _ASM_KGDB_H - -/* - * BUFMAX defines the maximum number of characters in inbound/outbound - * buffers at least NUMREGBYTES*2 are needed for register packets - * Longer buffer is needed to list all threads - */ -#define BUFMAX 1024 - -/* - * Note that this register image is in a different order than the register - * image that Linux produces at interrupt time. - */ -enum regnames { - GDB_FR_D0 = 0, - GDB_FR_D1 = 1, - GDB_FR_D2 = 2, - GDB_FR_D3 = 3, - GDB_FR_A0 = 4, - GDB_FR_A1 = 5, - GDB_FR_A2 = 6, - GDB_FR_A3 = 7, - - GDB_FR_SP = 8, - GDB_FR_PC = 9, - GDB_FR_MDR = 10, - GDB_FR_EPSW = 11, - GDB_FR_LIR = 12, - GDB_FR_LAR = 13, - GDB_FR_MDRQ = 14, - - GDB_FR_E0 = 15, - GDB_FR_E1 = 16, - GDB_FR_E2 = 17, - GDB_FR_E3 = 18, - GDB_FR_E4 = 19, - GDB_FR_E5 = 20, - GDB_FR_E6 = 21, - GDB_FR_E7 = 22, - - GDB_FR_SSP = 23, - GDB_FR_MSP = 24, - GDB_FR_USP = 25, - GDB_FR_MCRH = 26, - GDB_FR_MCRL = 27, - GDB_FR_MCVF = 28, - - GDB_FR_FPCR = 29, - GDB_FR_DUMMY0 = 30, - GDB_FR_DUMMY1 = 31, - - GDB_FR_FS0 = 32, - - GDB_FR_SIZE = 64, -}; - -#define GDB_ORIG_D0 41 -#define NUMREGBYTES (GDB_FR_SIZE*4) - -static inline void arch_kgdb_breakpoint(void) -{ - asm(".globl __arch_kgdb_breakpoint; __arch_kgdb_breakpoint: break"); -} -extern u8 __arch_kgdb_breakpoint; - -#define BREAK_INSTR_SIZE 1 -#define CACHE_FLUSH_IS_SAFE 1 - -#endif /* _ASM_KGDB_H */ diff --git a/arch/mn10300/include/asm/kmap_types.h b/arch/mn10300/include/asm/kmap_types.h deleted file mode 100644 index f444d7ffa766..000000000000 --- a/arch/mn10300/include/asm/kmap_types.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - -#include - -#endif /* _ASM_KMAP_TYPES_H */ diff --git a/arch/mn10300/include/asm/kprobes.h b/arch/mn10300/include/asm/kprobes.h deleted file mode 100644 index 7abea0bdb549..000000000000 --- a/arch/mn10300/include/asm/kprobes.h +++ /dev/null @@ -1,55 +0,0 @@ -/* MN10300 Kernel Probes support - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by Mark Salter (msalter@redhat.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public Licence as published by - * the Free Software Foundation; either version 2 of the Licence, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public Licence for more details. - * - * You should have received a copy of the GNU General Public Licence - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ -#ifndef _ASM_KPROBES_H -#define _ASM_KPROBES_H - -#include - -#define BREAKPOINT_INSTRUCTION 0xff - -#ifdef CONFIG_KPROBES -#include -#include - -struct kprobe; - -typedef unsigned char kprobe_opcode_t; -#define MAX_INSN_SIZE 8 -#define MAX_STACK_SIZE 128 - -/* Architecture specific copy of original instruction */ -struct arch_specific_insn { - /* copy of original instruction - */ - kprobe_opcode_t insn[MAX_INSN_SIZE]; -}; - -extern const int kretprobe_blacklist_size; - -extern int kprobe_exceptions_notify(struct notifier_block *self, - unsigned long val, void *data); - -#define flush_insn_slot(p) do {} while (0) - -extern void arch_remove_kprobe(struct kprobe *p); - -#endif /* CONFIG_KPROBES */ -#endif /* _ASM_KPROBES_H */ diff --git a/arch/mn10300/include/asm/linkage.h b/arch/mn10300/include/asm/linkage.h deleted file mode 100644 index dda3002a5dfa..000000000000 --- a/arch/mn10300/include/asm/linkage.h +++ /dev/null @@ -1,20 +0,0 @@ -/* MN10300 Linkage and calling-convention overrides - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_LINKAGE_H -#define _ASM_LINKAGE_H - -/* don't override anything */ -#define asmlinkage - -#define __ALIGN .align 4,0xcb -#define __ALIGN_STR ".align 4,0xcb" - -#endif diff --git a/arch/mn10300/include/asm/local.h b/arch/mn10300/include/asm/local.h deleted file mode 100644 index c11c530f74d0..000000000000 --- a/arch/mn10300/include/asm/local.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/local64.h b/arch/mn10300/include/asm/local64.h deleted file mode 100644 index 36c93b5cc239..000000000000 --- a/arch/mn10300/include/asm/local64.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/mc146818rtc.h b/arch/mn10300/include/asm/mc146818rtc.h deleted file mode 100644 index df6bc6e0e8c6..000000000000 --- a/arch/mn10300/include/asm/mc146818rtc.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/mmu.h b/arch/mn10300/include/asm/mmu.h deleted file mode 100644 index b9d6d41adace..000000000000 --- a/arch/mn10300/include/asm/mmu.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* MN10300 Memory management context - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - Derived from include/asm-frv/mmu.h - */ - -#ifndef _ASM_MMU_H -#define _ASM_MMU_H - -/* - * MMU context - */ -typedef struct { - unsigned long tlbpid[NR_CPUS]; /* TLB PID for this process on - * each CPU */ -} mm_context_t; - -#endif /* _ASM_MMU_H */ diff --git a/arch/mn10300/include/asm/mmu_context.h b/arch/mn10300/include/asm/mmu_context.h deleted file mode 100644 index d2034f5e6eda..000000000000 --- a/arch/mn10300/include/asm/mmu_context.h +++ /dev/null @@ -1,163 +0,0 @@ -/* MN10300 MMU context management - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - Derived from include/asm-m32r/mmu_context.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - * - * - * This implements an algorithm to provide TLB PID mappings to provide - * selective access to the TLB for processes, thus reducing the number of TLB - * flushes required. - * - * Note, however, that the M32R algorithm is technically broken as it does not - * handle version wrap-around, and could, theoretically, have a problem with a - * very long lived program that sleeps long enough for the version number to - * wrap all the way around so that its TLB mappings appear valid once again. - */ -#ifndef _ASM_MMU_CONTEXT_H -#define _ASM_MMU_CONTEXT_H - -#include -#include - -#include -#include -#include - -#define MMU_CONTEXT_TLBPID_NR 256 -#define MMU_CONTEXT_TLBPID_MASK 0x000000ffUL -#define MMU_CONTEXT_VERSION_MASK 0xffffff00UL -#define MMU_CONTEXT_FIRST_VERSION 0x00000100UL -#define MMU_NO_CONTEXT 0x00000000UL -#define MMU_CONTEXT_TLBPID_LOCK_NR 0 - -#define enter_lazy_tlb(mm, tsk) do {} while (0) - -static inline void cpu_ran_vm(int cpu, struct mm_struct *mm) -{ -#ifdef CONFIG_SMP - cpumask_set_cpu(cpu, mm_cpumask(mm)); -#endif -} - -static inline bool cpu_maybe_ran_vm(int cpu, struct mm_struct *mm) -{ -#ifdef CONFIG_SMP - return cpumask_test_and_set_cpu(cpu, mm_cpumask(mm)); -#else - return true; -#endif -} - -#ifdef CONFIG_MN10300_TLB_USE_PIDR -extern unsigned long mmu_context_cache[NR_CPUS]; -#define mm_context(mm) (mm->context.tlbpid[smp_processor_id()]) - -/** - * allocate_mmu_context - Allocate storage for the arch-specific MMU data - * @mm: The userspace VM context being set up - */ -static inline unsigned long allocate_mmu_context(struct mm_struct *mm) -{ - unsigned long *pmc = &mmu_context_cache[smp_processor_id()]; - unsigned long mc = ++(*pmc); - - if (!(mc & MMU_CONTEXT_TLBPID_MASK)) { - /* we exhausted the TLB PIDs of this version on this CPU, so we - * flush this CPU's TLB in its entirety and start new cycle */ - local_flush_tlb_all(); - - /* fix the TLB version if needed (we avoid version #0 so as to - * distinguish MMU_NO_CONTEXT) */ - if (!mc) - *pmc = mc = MMU_CONTEXT_FIRST_VERSION; - } - mm_context(mm) = mc; - return mc; -} - -/* - * get an MMU context if one is needed - */ -static inline unsigned long get_mmu_context(struct mm_struct *mm) -{ - unsigned long mc = MMU_NO_CONTEXT, cache; - - if (mm) { - cache = mmu_context_cache[smp_processor_id()]; - mc = mm_context(mm); - - /* if we have an old version of the context, replace it */ - if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK) - mc = allocate_mmu_context(mm); - } - return mc; -} - -/* - * initialise the context related info for a new mm_struct instance - */ -static inline int init_new_context(struct task_struct *tsk, - struct mm_struct *mm) -{ - int num_cpus = NR_CPUS, i; - - for (i = 0; i < num_cpus; i++) - mm->context.tlbpid[i] = MMU_NO_CONTEXT; - return 0; -} - -/* - * after we have set current->mm to a new value, this activates the context for - * the new mm so we see the new mappings. - */ -static inline void activate_context(struct mm_struct *mm) -{ - PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK; -} -#else /* CONFIG_MN10300_TLB_USE_PIDR */ - -#define init_new_context(tsk, mm) (0) -#define activate_context(mm) local_flush_tlb() - -#endif /* CONFIG_MN10300_TLB_USE_PIDR */ - -/** - * destroy_context - Destroy mm context information - * @mm: The MM being destroyed. - * - * Destroy context related info for an mm_struct that is about to be put to - * rest - */ -#define destroy_context(mm) do {} while (0) - -/** - * switch_mm - Change between userspace virtual memory contexts - * @prev: The outgoing MM context. - * @next: The incoming MM context. - * @tsk: The incoming task. - */ -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - int cpu = smp_processor_id(); - - if (prev != next) { -#ifdef CONFIG_SMP - per_cpu(cpu_tlbstate, cpu).active_mm = next; -#endif - cpu_ran_vm(cpu, next); - PTBR = (unsigned long) next->pgd; - activate_context(next); - } -} - -#define deactivate_mm(tsk, mm) do {} while (0) -#define activate_mm(prev, next) switch_mm((prev), (next), NULL) - -#endif /* _ASM_MMU_CONTEXT_H */ diff --git a/arch/mn10300/include/asm/module.h b/arch/mn10300/include/asm/module.h deleted file mode 100644 index 6571103b0518..000000000000 --- a/arch/mn10300/include/asm/module.h +++ /dev/null @@ -1,22 +0,0 @@ -/* MN10300 Arch-specific module definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by Mark Salter (msalter@redhat.com) - * Derived from include/asm-i386/module.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_MODULE_H -#define _ASM_MODULE_H - -#include - -/* - * Include the MN10300 architecture version. - */ -#define MODULE_ARCH_VERMAGIC __stringify(PROCESSOR_MODEL_NAME) " " - -#endif /* _ASM_MODULE_H */ diff --git a/arch/mn10300/include/asm/nmi.h b/arch/mn10300/include/asm/nmi.h deleted file mode 100644 index b05627597b1b..000000000000 --- a/arch/mn10300/include/asm/nmi.h +++ /dev/null @@ -1,16 +0,0 @@ -/* MN10300 NMI handling - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_NMI_H -#define _ASM_NMI_H - -extern void arch_touch_nmi_watchdog(void); - -#endif /* _ASM_NMI_H */ diff --git a/arch/mn10300/include/asm/page.h b/arch/mn10300/include/asm/page.h deleted file mode 100644 index dfe730a5ede0..000000000000 --- a/arch/mn10300/include/asm/page.h +++ /dev/null @@ -1,130 +0,0 @@ -/* MN10300 Page table definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PAGE_H -#define _ASM_PAGE_H - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 12 - -#ifndef __ASSEMBLY__ -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE - 1)) -#else -#define PAGE_SIZE +(1 << PAGE_SHIFT) /* unary plus marks an - * immediate val not an addr */ -#define PAGE_MASK +(~(PAGE_SIZE - 1)) -#endif - -#ifdef __KERNEL__ -#ifndef __ASSEMBLY__ - -#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) -#define copy_page(to, from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) - -#define clear_user_page(addr, vaddr, page) clear_page(addr) -#define copy_user_page(vto, vfrom, vaddr, to) copy_page(vto, vfrom) - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; - -#define PTE_MASK PAGE_MASK -#define HPAGE_SHIFT 22 - -#ifdef CONFIG_HUGETLB_PAGE -#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) -#define HPAGE_MASK (~(HPAGE_SIZE - 1)) -#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) -#endif - -#define pte_val(x) ((x).pte) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) }) -#define __pgd(x) ((pgd_t) { (x) }) -#define __pgprot(x) ((pgprot_t) { (x) }) - -#define __ARCH_USE_5LEVEL_HACK -#include - -#endif /* !__ASSEMBLY__ */ - -/* - * This handles the memory map.. We could make this a config - * option, but too many people screw it up, and too few need - * it. - * - * A __PAGE_OFFSET of 0xC0000000 means that the kernel has - * a virtual address space of one gigabyte, which limits the - * amount of physical memory you can use to about 950MB. - */ - -#ifndef __ASSEMBLY__ - -/* Pure 2^n version of get_order */ -static inline int get_order(unsigned long size) __attribute__((const)); -static inline int get_order(unsigned long size) -{ - int order; - - size = (size - 1) >> (PAGE_SHIFT - 1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif /* __ASSEMBLY__ */ - -#include - -#define __PAGE_OFFSET (PAGE_OFFSET_RAW) -#define PAGE_OFFSET ((unsigned long) __PAGE_OFFSET) - -/* - * main RAM and kernel working space are coincident at 0x90000000, but to make - * life more interesting, there's also an uncached virtual shadow at 0xb0000000 - * - these mappings are fixed in the MMU - */ -#define __pfn_disp (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT) - -#define __pa(x) ((unsigned long)(x)) -#define __va(x) ((void *)(unsigned long)(x)) -#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) -#define pfn_to_page(pfn) (mem_map + ((pfn) - __pfn_disp)) -#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + __pfn_disp) -#define __pfn_to_phys(pfn) PFN_PHYS(pfn) - -#define pfn_valid(pfn) \ -({ \ - unsigned long __pfn = (pfn) - __pfn_disp; \ - __pfn < max_mapnr; \ -}) - -#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) -#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) - -#define VM_DATA_DEFAULT_FLAGS \ - (VM_READ | VM_WRITE | \ - ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PAGE_H */ diff --git a/arch/mn10300/include/asm/page_offset.h b/arch/mn10300/include/asm/page_offset.h deleted file mode 100644 index 1e869aa09418..000000000000 --- a/arch/mn10300/include/asm/page_offset.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* MN10300 Kernel base address - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - */ -#ifndef _ASM_PAGE_OFFSET_H -#define _ASM_PAGE_OFFSET_H - -#define PAGE_OFFSET_RAW CONFIG_KERNEL_RAM_BASE_ADDRESS - -#endif diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h deleted file mode 100644 index 5b75a1b2c4f6..000000000000 --- a/arch/mn10300/include/asm/pci.h +++ /dev/null @@ -1,84 +0,0 @@ -/* MN10300 PCI definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PCI_H -#define _ASM_PCI_H - -#ifdef __KERNEL__ -#include /* for struct page */ - -#if 0 -#define __pcbdebug(FMT, ADDR, ...) \ - printk(KERN_DEBUG "PCIBRIDGE[%08x]: "FMT"\n", \ - (u32)(ADDR), ##__VA_ARGS__) - -#define __pcidebug(FMT, BUS, DEVFN, WHERE,...) \ -do { \ - printk(KERN_DEBUG "PCI[%02x:%02x.%x + %02x]: "FMT"\n", \ - (BUS)->number, \ - PCI_SLOT(DEVFN), \ - PCI_FUNC(DEVFN), \ - (u32)(WHERE), ##__VA_ARGS__); \ -} while (0) - -#else -#define __pcbdebug(FMT, ADDR, ...) do {} while (0) -#define __pcidebug(FMT, BUS, DEVFN, WHERE, ...) do {} while (0) -#endif - -/* Can be used to override the logic in pci_scan_bus for skipping - * already-configured bus numbers - to be used for buggy BIOSes or - * architectures with incomplete PCI setup by the loader */ - -#ifdef CONFIG_PCI -#define pcibios_assign_all_busses() 1 -extern void unit_pci_init(void); -#else -#define pcibios_assign_all_busses() 0 -#endif - -#define PCIBIOS_MIN_IO 0xBE000004 -#define PCIBIOS_MIN_MEM 0xB8000000 - -/* Dynamic DMA mapping stuff. - * i386 has everything mapped statically. - */ - -#include -#include -#include -#include -#include - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -/* Return the index of the PCI controller for device. */ -static inline int pci_controller_num(struct pci_dev *dev) -{ - return 0; -} - -#define HAVE_PCI_MMAP -#define ARCH_GENERIC_PCI_MMAP_RESOURCE - -#endif /* __KERNEL__ */ - -static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) -{ - return channel ? 15 : 14; -} - -#include - -#endif /* _ASM_PCI_H */ diff --git a/arch/mn10300/include/asm/percpu.h b/arch/mn10300/include/asm/percpu.h deleted file mode 100644 index 06a959d67234..000000000000 --- a/arch/mn10300/include/asm/percpu.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/pgalloc.h b/arch/mn10300/include/asm/pgalloc.h deleted file mode 100644 index 0f25d5fa86f3..000000000000 --- a/arch/mn10300/include/asm/pgalloc.h +++ /dev/null @@ -1,56 +0,0 @@ -/* MN10300 Page and page table/directory allocation - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PGALLOC_H -#define _ASM_PGALLOC_H - -#include -#include -#include /* for struct page */ - -struct mm_struct; -struct page; - -/* attach a page table to a PMD entry */ -#define pmd_populate_kernel(mm, pmd, pte) \ - set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE)) - -static inline -void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) -{ - set_pmd(pmd, __pmd((page_to_pfn(pte) << PAGE_SHIFT) | _PAGE_TABLE)); -} -#define pmd_pgtable(pmd) pmd_page(pmd) - -/* - * Allocate and free page tables. - */ - -extern pgd_t *pgd_alloc(struct mm_struct *); -extern void pgd_free(struct mm_struct *, pgd_t *); - -extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); -extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); - -static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ - free_page((unsigned long) pte); -} - -static inline void pte_free(struct mm_struct *mm, struct page *pte) -{ - pgtable_page_dtor(pte); - __free_page(pte); -} - - -#define __pte_free_tlb(tlb, pte, addr) tlb_remove_page((tlb), (pte)) - -#endif /* _ASM_PGALLOC_H */ diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h deleted file mode 100644 index 96d3f9deb59c..000000000000 --- a/arch/mn10300/include/asm/pgtable.h +++ /dev/null @@ -1,494 +0,0 @@ -/* MN10300 Page table manipulators and constants - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - * - * - * The Linux memory management assumes a three-level page table setup. On - * the i386, we use that, but "fold" the mid level into the top-level page - * table, so that we physically have the same two-level page table as the - * i386 mmu expects. - * - * This file contains the functions and defines necessary to modify and use - * the i386 page table tree for the purposes of the MN10300 TLB handler - * functions. - */ -#ifndef _ASM_PGTABLE_H -#define _ASM_PGTABLE_H - -#include - -#ifndef __ASSEMBLY__ -#include -#include -#include - -#include - -#include -#include -#include - -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) -extern unsigned long empty_zero_page[1024]; -extern spinlock_t pgd_lock; -extern struct page *pgd_list; - -extern void pmd_ctor(void *, struct kmem_cache *, unsigned long); -extern void pgtable_cache_init(void); -extern void paging_init(void); - -#endif /* !__ASSEMBLY__ */ - -/* - * The Linux mn10300 paging architecture only implements both the traditional - * 2-level page tables - */ -#define PGDIR_SHIFT 22 -#define PTRS_PER_PGD 1024 -#define PTRS_PER_PUD 1 /* we don't really have any PUD physically */ -#define __PAGETABLE_PUD_FOLDED -#define PTRS_PER_PMD 1 /* we don't really have any PMD physically */ -#define __PAGETABLE_PMD_FOLDED -#define PTRS_PER_PTE 1024 - -#define PGD_SIZE PAGE_SIZE -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE - 1)) - -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL - -#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) -#define KERNEL_PGD_PTRS (PTRS_PER_PGD - USER_PGD_PTRS) - -#define TWOLEVEL_PGDIR_SHIFT 22 -#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT) -#define BOOT_KERNEL_PGD_PTRS (1024 - BOOT_USER_PGD_PTRS) - -#ifndef __ASSEMBLY__ -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; -#endif - -/* - * Unfortunately, due to the way the MMU works on the MN10300, the vmalloc VM - * area has to be in the lower half of the virtual address range (the upper - * half is not translated through the TLB). - * - * So in this case, the vmalloc area goes at the bottom of the address map - * (leaving a hole at the very bottom to catch addressing errors), and - * userspace starts immediately above. - * - * The vmalloc() routines also leaves a hole of 4kB between each vmalloced - * area to catch addressing errors. - */ -#ifndef __ASSEMBLY__ -#define VMALLOC_OFFSET (8UL * 1024 * 1024) -#define VMALLOC_START (0x70000000UL) -#define VMALLOC_END (0x7C000000UL) -#else -#define VMALLOC_OFFSET (8 * 1024 * 1024) -#define VMALLOC_START (0x70000000) -#define VMALLOC_END (0x7C000000) -#endif - -#ifndef __ASSEMBLY__ -extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE]; -#endif - -/* IPTEL2/DPTEL2 bit assignments */ -#define _PAGE_BIT_VALID xPTEL2_V_BIT -#define _PAGE_BIT_CACHE xPTEL2_C_BIT -#define _PAGE_BIT_PRESENT xPTEL2_PV_BIT -#define _PAGE_BIT_DIRTY xPTEL2_D_BIT -#define _PAGE_BIT_GLOBAL xPTEL2_G_BIT -#define _PAGE_BIT_ACCESSED xPTEL2_UNUSED1_BIT /* mustn't be loaded into IPTEL2/DPTEL2 */ - -#define _PAGE_VALID xPTEL2_V -#define _PAGE_CACHE xPTEL2_C -#define _PAGE_PRESENT xPTEL2_PV -#define _PAGE_DIRTY xPTEL2_D -#define _PAGE_PROT xPTEL2_PR -#define _PAGE_PROT_RKNU xPTEL2_PR_ROK -#define _PAGE_PROT_WKNU xPTEL2_PR_RWK -#define _PAGE_PROT_RKRU xPTEL2_PR_ROK_ROU -#define _PAGE_PROT_WKRU xPTEL2_PR_RWK_ROU -#define _PAGE_PROT_WKWU xPTEL2_PR_RWK_RWU -#define _PAGE_GLOBAL xPTEL2_G -#define _PAGE_PS_MASK xPTEL2_PS -#define _PAGE_PS_4Kb xPTEL2_PS_4Kb -#define _PAGE_PS_128Kb xPTEL2_PS_128Kb -#define _PAGE_PS_1Kb xPTEL2_PS_1Kb -#define _PAGE_PS_4Mb xPTEL2_PS_4Mb -#define _PAGE_PSE xPTEL2_PS_4Mb /* 4MB page */ -#define _PAGE_CACHE_WT xPTEL2_CWT -#define _PAGE_ACCESSED xPTEL2_UNUSED1 -#define _PAGE_NX 0 /* no-execute bit */ - -/* If _PAGE_VALID is clear, we use these: */ -#define _PAGE_PROTNONE 0x000 /* If not present */ - -#define __PAGE_PROT_UWAUX 0x010 -#define __PAGE_PROT_USER 0x020 -#define __PAGE_PROT_WRITE 0x040 - -#define _PAGE_PRESENTV (_PAGE_PRESENT|_PAGE_VALID) - -#ifndef __ASSEMBLY__ - -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) - -#define _PAGE_TABLE (_PAGE_PRESENTV | _PAGE_PROT_WKNU | _PAGE_ACCESSED | _PAGE_DIRTY) -#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) - -#define __PAGE_NONE (_PAGE_PRESENTV | _PAGE_PROT_RKNU | _PAGE_ACCESSED | _PAGE_CACHE) -#define __PAGE_SHARED (_PAGE_PRESENTV | _PAGE_PROT_WKWU | _PAGE_ACCESSED | _PAGE_CACHE) -#define __PAGE_COPY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE) -#define __PAGE_READONLY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE) - -#define PAGE_NONE __pgprot(__PAGE_NONE | _PAGE_NX) -#define PAGE_SHARED_NOEXEC __pgprot(__PAGE_SHARED | _PAGE_NX) -#define PAGE_COPY_NOEXEC __pgprot(__PAGE_COPY | _PAGE_NX) -#define PAGE_READONLY_NOEXEC __pgprot(__PAGE_READONLY | _PAGE_NX) -#define PAGE_SHARED_EXEC __pgprot(__PAGE_SHARED) -#define PAGE_COPY_EXEC __pgprot(__PAGE_COPY) -#define PAGE_READONLY_EXEC __pgprot(__PAGE_READONLY) -#define PAGE_COPY PAGE_COPY_NOEXEC -#define PAGE_READONLY PAGE_READONLY_NOEXEC -#define PAGE_SHARED PAGE_SHARED_EXEC - -#define __PAGE_KERNEL_BASE (_PAGE_PRESENTV | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL) - -#define __PAGE_KERNEL (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_CACHE | _PAGE_NX) -#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_NX) -#define __PAGE_KERNEL_EXEC (__PAGE_KERNEL & ~_PAGE_NX) -#define __PAGE_KERNEL_RO (__PAGE_KERNEL_BASE | _PAGE_PROT_RKNU | _PAGE_CACHE | _PAGE_NX) -#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE) -#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE) - -#define PAGE_KERNEL __pgprot(__PAGE_KERNEL) -#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO) -#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC) -#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE) -#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE) -#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC) - -#define __PAGE_USERIO (__PAGE_KERNEL_BASE | _PAGE_PROT_WKWU | _PAGE_NX) -#define PAGE_USERIO __pgprot(__PAGE_USERIO) - -/* - * Whilst the MN10300 can do page protection for execute (given separate data - * and insn TLBs), we are not supporting it at the moment. Write permission, - * however, always implies read permission (but not execute permission). - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY_NOEXEC -#define __P010 PAGE_COPY_NOEXEC -#define __P011 PAGE_COPY_NOEXEC -#define __P100 PAGE_READONLY_EXEC -#define __P101 PAGE_READONLY_EXEC -#define __P110 PAGE_COPY_EXEC -#define __P111 PAGE_COPY_EXEC - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY_NOEXEC -#define __S010 PAGE_SHARED_NOEXEC -#define __S011 PAGE_SHARED_NOEXEC -#define __S100 PAGE_READONLY_EXEC -#define __S101 PAGE_READONLY_EXEC -#define __S110 PAGE_SHARED_EXEC -#define __S111 PAGE_SHARED_EXEC - -/* - * Define this to warn about kernel memory accesses that are - * done without a 'verify_area(VERIFY_WRITE,..)' - */ -#undef TEST_VERIFY_AREA - -#define pte_present(x) (pte_val(x) & _PAGE_VALID) -#define pte_clear(mm, addr, xp) \ -do { \ - set_pte_at((mm), (addr), (xp), __pte(0)); \ -} while (0) - -#define pmd_none(x) (!pmd_val(x)) -#define pmd_present(x) (!pmd_none(x)) -#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) -#define pmd_bad(x) 0 - - -#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) - -#ifndef __ASSEMBLY__ - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ -static inline int pte_user(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; } -static inline int pte_read(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_write(pte_t pte) { return pte_val(pte) & __PAGE_PROT_WRITE; } -static inline int pte_special(pte_t pte){ return 0; } - -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte_val(pte) &= ~(__PAGE_PROT_USER|__PAGE_PROT_UWAUX); return pte; -} -static inline pte_t pte_exprotect(pte_t pte) -{ - pte_val(pte) |= _PAGE_NX; return pte; -} - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte_val(pte) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); return pte; -} - -static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } -static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } -static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_NX; return pte; } - -static inline pte_t pte_mkread(pte_t pte) -{ - pte_val(pte) |= __PAGE_PROT_USER; - if (pte_write(pte)) - pte_val(pte) |= __PAGE_PROT_UWAUX; - return pte; -} -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte_val(pte) |= __PAGE_PROT_WRITE; - if (pte_val(pte) & __PAGE_PROT_USER) - pte_val(pte) |= __PAGE_PROT_UWAUX; - return pte; -} - -static inline pte_t pte_mkspecial(pte_t pte) { return pte; } - -#define pte_ERROR(e) \ - printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ - __FILE__, __LINE__, pte_val(e)) -#define pgd_ERROR(e) \ - printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ - __FILE__, __LINE__, pgd_val(e)) - -/* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) - */ -#define pgd_clear(xp) do { } while (0) - -/* - * Certain architectures need to do special things when PTEs - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -#define set_pte(pteptr, pteval) (*(pteptr) = pteval) -#define set_pte_at(mm, addr, ptep, pteval) set_pte((ptep), (pteval)) -#define set_pte_atomic(pteptr, pteval) set_pte((pteptr), (pteval)) - -/* - * (pmds are folded into pgds so this doesn't get actually called, - * but the define is needed for a generic inline function.) - */ -#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) - -#define ptep_get_and_clear(mm, addr, ptep) \ - __pte(xchg(&(ptep)->pte, 0)) -#define pte_same(a, b) (pte_val(a) == pte_val(b)) -#define pte_page(x) pfn_to_page(pte_pfn(x)) -#define pte_none(x) (!pte_val(x)) -#define pte_pfn(x) ((unsigned long) (pte_val(x) >> PAGE_SHIFT)) -#define __pfn_addr(pfn) ((pfn) << PAGE_SHIFT) -#define pfn_pte(pfn, prot) __pte(__pfn_addr(pfn) | pgprot_val(prot)) -#define pfn_pmd(pfn, prot) __pmd(__pfn_addr(pfn) | pgprot_val(prot)) - -/* - * All present user pages are user-executable: - */ -static inline int pte_exec(pte_t pte) -{ - return pte_user(pte); -} - -/* - * All present pages are kernel-executable: - */ -static inline int pte_exec_kernel(pte_t pte) -{ - return 1; -} - -/* Encode and de-code a swap entry */ -#define __swp_type(x) (((x).val >> 1) & 0x3f) -#define __swp_offset(x) ((x).val >> 7) -#define __swp_entry(type, offset) \ - ((swp_entry_t) { ((type) << 1) | ((offset) << 7) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) __pte((x).val) - -static inline -int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, - pte_t *ptep) -{ - if (!pte_dirty(*ptep)) - return 0; - return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte); -} - -static inline -int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, - pte_t *ptep) -{ - if (!pte_young(*ptep)) - return 0; - return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte); -} - -static inline -void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) -{ - pte_val(*ptep) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); -} - -static inline void ptep_mkdirty(pte_t *ptep) -{ - set_bit(_PAGE_BIT_DIRTY, &ptep->pte); -} - -/* - * Macro to mark a page protection value as "uncacheable". On processors which - * do not support it, this is a no-op. - */ -#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHE) - -/* - * Macro to mark a page protection value as "Write-Through". - * On processors which do not support it, this is a no-op. - */ -#define pgprot_through(prot) __pgprot(pgprot_val(prot) | _PAGE_CACHE_WT) - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ - -#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) -#define mk_pte_huge(entry) \ - ((entry).pte |= _PAGE_PRESENT | _PAGE_PSE | _PAGE_VALID) - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - pte_val(pte) &= _PAGE_CHG_MASK; - pte_val(pte) |= pgprot_val(newprot); - return pte; -} - -#define page_pte(page) page_pte_prot((page), __pgprot(0)) - -#define pmd_page_kernel(pmd) \ - ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) - -#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) - -#define pmd_large(pmd) \ - ((pmd_val(pmd) & (_PAGE_PSE | _PAGE_PRESENT)) == \ - (_PAGE_PSE | _PAGE_PRESENT)) - -/* - * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD] - * - * this macro returns the index of the entry in the pgd page which would - * control the given virtual address - */ -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) - -/* - * pgd_offset() returns a (pgd_t *) - * pgd_index() is used get the offset into the pgd page's array of pgd_t's; - */ -#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) - -/* - * a shortcut which implies the use of the kernel's pgd, instead - * of a process's - */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* - * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD] - * - * this macro returns the index of the entry in the pmd page which would - * control the given virtual address - */ -#define pmd_index(address) \ - (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) - -/* - * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE] - * - * this macro returns the index of the entry in the pte page which would - * control the given virtual address - */ -#define pte_index(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) - -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address)) - -/* - * Make a given kernel text page executable/non-executable. - * Returns the previous executability setting of that page (which - * is used to restore the previous state). Used by the SMP bootup code. - * NOTE: this is an __init function for security reasons. - */ -static inline int set_kernel_exec(unsigned long vaddr, int enable) -{ - return 0; -} - -#define pte_offset_map(dir, address) \ - ((pte_t *) page_address(pmd_page(*(dir))) + pte_index(address)) -#define pte_unmap(pte) do {} while (0) - -/* - * The MN10300 has external MMU info in the form of a TLB: this is adapted from - * the kernel page tables containing the necessary information by tlb-mn10300.S - */ -extern void update_mmu_cache(struct vm_area_struct *vma, - unsigned long address, pte_t *ptep); - -#endif /* !__ASSEMBLY__ */ - -#define kern_addr_valid(addr) (1) - -#define MK_IOSPACE_PFN(space, pfn) (pfn) -#define GET_IOSPACE(pfn) 0 -#define GET_PFN(pfn) (pfn) - -#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG -#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -#define __HAVE_ARCH_PTEP_SET_WRPROTECT -#define __HAVE_ARCH_PTEP_MKDIRTY -#define __HAVE_ARCH_PTE_SAME -#include - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_PGTABLE_H */ diff --git a/arch/mn10300/include/asm/pio-regs.h b/arch/mn10300/include/asm/pio-regs.h deleted file mode 100644 index 96bc8182d0ba..000000000000 --- a/arch/mn10300/include/asm/pio-regs.h +++ /dev/null @@ -1,233 +0,0 @@ -/* MN10300 On-board I/O port module registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PIO_REGS_H -#define _ASM_PIO_REGS_H - -#include -#include - -#ifdef __KERNEL__ - -/* I/O port 0 */ -#define P0MD __SYSREG(0xdb000000, u16) /* mode reg */ -#define P0MD_0 0x0003 /* mask */ -#define P0MD_0_IN 0x0000 /* input mode */ -#define P0MD_0_OUT 0x0001 /* output mode */ -#define P0MD_0_TM0IO 0x0002 /* timer 0 I/O mode */ -#define P0MD_0_EYECLK 0x0003 /* test signal output (clock) */ -#define P0MD_1 0x000c -#define P0MD_1_IN 0x0000 -#define P0MD_1_OUT 0x0004 -#define P0MD_1_TM1IO 0x0008 /* timer 1 I/O mode */ -#define P0MD_1_EYED 0x000c /* test signal output (data) */ -#define P0MD_2 0x0030 -#define P0MD_2_IN 0x0000 -#define P0MD_2_OUT 0x0010 -#define P0MD_2_TM2IO 0x0020 /* timer 2 I/O mode */ -#define P0MD_3 0x00c0 -#define P0MD_3_IN 0x0000 -#define P0MD_3_OUT 0x0040 -#define P0MD_3_TM3IO 0x0080 /* timer 3 I/O mode */ -#define P0MD_4 0x0300 -#define P0MD_4_IN 0x0000 -#define P0MD_4_OUT 0x0100 -#define P0MD_4_TM4IO 0x0200 /* timer 4 I/O mode */ -#define P0MD_4_XCTS 0x0300 /* XCTS input for serial port 2 */ -#define P0MD_5 0x0c00 -#define P0MD_5_IN 0x0000 -#define P0MD_5_OUT 0x0400 -#define P0MD_5_TM5IO 0x0800 /* timer 5 I/O mode */ -#define P0MD_6 0x3000 -#define P0MD_6_IN 0x0000 -#define P0MD_6_OUT 0x1000 -#define P0MD_6_TM6IOA 0x2000 /* timer 6 I/O mode A */ -#define P0MD_7 0xc000 -#define P0MD_7_IN 0x0000 -#define P0MD_7_OUT 0x4000 -#define P0MD_7_TM6IOB 0x8000 /* timer 6 I/O mode B */ - -#define P0IN __SYSREG(0xdb000004, u8) /* in reg */ -#define P0OUT __SYSREG(0xdb000008, u8) /* out reg */ - -#define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */ -#define P0TMIO_TM0_IN 0x00 -#define P0TMIO_TM0_OUT 0x01 -#define P0TMIO_TM1_IN 0x00 -#define P0TMIO_TM1_OUT 0x02 -#define P0TMIO_TM2_IN 0x00 -#define P0TMIO_TM2_OUT 0x04 -#define P0TMIO_TM3_IN 0x00 -#define P0TMIO_TM3_OUT 0x08 -#define P0TMIO_TM4_IN 0x00 -#define P0TMIO_TM4_OUT 0x10 -#define P0TMIO_TM5_IN 0x00 -#define P0TMIO_TM5_OUT 0x20 -#define P0TMIO_TM6A_IN 0x00 -#define P0TMIO_TM6A_OUT 0x40 -#define P0TMIO_TM6B_IN 0x00 -#define P0TMIO_TM6B_OUT 0x80 - -/* I/O port 1 */ -#define P1MD __SYSREG(0xdb000100, u16) /* mode reg */ -#define P1MD_0 0x0003 /* mask */ -#define P1MD_0_IN 0x0000 /* input mode */ -#define P1MD_0_OUT 0x0001 /* output mode */ -#define P1MD_0_TM7IO 0x0002 /* timer 7 I/O mode */ -#define P1MD_0_ADTRG 0x0003 /* A/D converter trigger mode */ -#define P1MD_1 0x000c -#define P1MD_1_IN 0x0000 -#define P1MD_1_OUT 0x0004 -#define P1MD_1_TM8IO 0x0008 /* timer 8 I/O mode */ -#define P1MD_1_XDMR0 0x000c /* DMA request input 0 mode */ -#define P1MD_2 0x0030 -#define P1MD_2_IN 0x0000 -#define P1MD_2_OUT 0x0010 -#define P1MD_2_TM9IO 0x0020 /* timer 9 I/O mode */ -#define P1MD_2_XDMR1 0x0030 /* DMA request input 1 mode */ -#define P1MD_3 0x00c0 -#define P1MD_3_IN 0x0000 -#define P1MD_3_OUT 0x0040 -#define P1MD_3_TM10IO 0x0080 /* timer 10 I/O mode */ -#define P1MD_3_FRQS0 0x00c0 /* CPU clock multiplier setting input 0 mode */ -#define P1MD_4 0x0300 -#define P1MD_4_IN 0x0000 -#define P1MD_4_OUT 0x0100 -#define P1MD_4_TM11IO 0x0200 /* timer 11 I/O mode */ -#define P1MD_4_FRQS1 0x0300 /* CPU clock multiplier setting input 1 mode */ - -#define P1IN __SYSREG(0xdb000104, u8) /* in reg */ -#define P1OUT __SYSREG(0xdb000108, u8) /* out reg */ -#define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */ -#define P1TMIO_TM11_IN 0x00 -#define P1TMIO_TM11_OUT 0x01 -#define P1TMIO_TM10_IN 0x00 -#define P1TMIO_TM10_OUT 0x02 -#define P1TMIO_TM9_IN 0x00 -#define P1TMIO_TM9_OUT 0x04 -#define P1TMIO_TM8_IN 0x00 -#define P1TMIO_TM8_OUT 0x08 -#define P1TMIO_TM7_IN 0x00 -#define P1TMIO_TM7_OUT 0x10 - -/* I/O port 2 */ -#define P2MD __SYSREG(0xdb000200, u16) /* mode reg */ -#define P2MD_0 0x0003 /* mask */ -#define P2MD_0_IN 0x0000 /* input mode */ -#define P2MD_0_OUT 0x0001 /* output mode */ -#define P2MD_0_BOOTBW 0x0003 /* boot bus width selector mode */ -#define P2MD_1 0x000c -#define P2MD_1_IN 0x0000 -#define P2MD_1_OUT 0x0004 -#define P2MD_1_BOOTSEL 0x000c /* boot device selector mode */ -#define P2MD_2 0x0030 -#define P2MD_2_IN 0x0000 -#define P2MD_2_OUT 0x0010 -#define P2MD_3 0x00c0 -#define P2MD_3_IN 0x0000 -#define P2MD_3_OUT 0x0040 -#define P2MD_3_CKIO 0x00c0 /* mode */ -#define P2MD_4 0x0300 -#define P2MD_4_IN 0x0000 -#define P2MD_4_OUT 0x0100 -#define P2MD_4_CMOD 0x0300 /* mode */ - -#define P2IN __SYSREG(0xdb000204, u8) /* in reg */ -#define P2OUT __SYSREG(0xdb000208, u8) /* out reg */ -#define P2TMIO __SYSREG(0xdb00020c, u8) /* TM pin I/O control reg */ - -/* I/O port 3 */ -#define P3MD __SYSREG(0xdb000300, u16) /* mode reg */ -#define P3MD_0 0x0003 /* mask */ -#define P3MD_0_IN 0x0000 /* input mode */ -#define P3MD_0_OUT 0x0001 /* output mode */ -#define P3MD_0_AFRXD 0x0002 /* AFR interface mode */ -#define P3MD_1 0x000c -#define P3MD_1_IN 0x0000 -#define P3MD_1_OUT 0x0004 -#define P3MD_1_AFTXD 0x0008 /* AFR interface mode */ -#define P3MD_2 0x0030 -#define P3MD_2_IN 0x0000 -#define P3MD_2_OUT 0x0010 -#define P3MD_2_AFSCLK 0x0020 /* AFR interface mode */ -#define P3MD_3 0x00c0 -#define P3MD_3_IN 0x0000 -#define P3MD_3_OUT 0x0040 -#define P3MD_3_AFFS 0x0080 /* AFR interface mode */ -#define P3MD_4 0x0300 -#define P3MD_4_IN 0x0000 -#define P3MD_4_OUT 0x0100 -#define P3MD_4_AFEHC 0x0200 /* AFR interface mode */ - -#define P3IN __SYSREG(0xdb000304, u8) /* in reg */ -#define P3OUT __SYSREG(0xdb000308, u8) /* out reg */ - -/* I/O port 4 */ -#define P4MD __SYSREG(0xdb000400, u16) /* mode reg */ -#define P4MD_0 0x0003 /* mask */ -#define P4MD_0_IN 0x0000 /* input mode */ -#define P4MD_0_OUT 0x0001 /* output mode */ -#define P4MD_0_SCL0 0x0002 /* I2C/serial mode */ -#define P4MD_1 0x000c -#define P4MD_1_IN 0x0000 -#define P4MD_1_OUT 0x0004 -#define P4MD_1_SDA0 0x0008 -#define P4MD_2 0x0030 -#define P4MD_2_IN 0x0000 -#define P4MD_2_OUT 0x0010 -#define P4MD_2_SCL1 0x0020 -#define P4MD_3 0x00c0 -#define P4MD_3_IN 0x0000 -#define P4MD_3_OUT 0x0040 -#define P4MD_3_SDA1 0x0080 -#define P4MD_4 0x0300 -#define P4MD_4_IN 0x0000 -#define P4MD_4_OUT 0x0100 -#define P4MD_4_SBO0 0x0200 -#define P4MD_5 0x0c00 -#define P4MD_5_IN 0x0000 -#define P4MD_5_OUT 0x0400 -#define P4MD_5_SBO1 0x0800 -#define P4MD_6 0x3000 -#define P4MD_6_IN 0x0000 -#define P4MD_6_OUT 0x1000 -#define P4MD_6_SBT0 0x2000 -#define P4MD_7 0xc000 -#define P4MD_7_IN 0x0000 -#define P4MD_7_OUT 0x4000 -#define P4MD_7_SBT1 0x8000 - -#define P4IN __SYSREG(0xdb000404, u8) /* in reg */ -#define P4OUT __SYSREG(0xdb000408, u8) /* out reg */ - -/* I/O port 5 */ -#define P5MD __SYSREG(0xdb000500, u16) /* mode reg */ -#define P5MD_0 0x0003 /* mask */ -#define P5MD_0_IN 0x0000 /* input mode */ -#define P5MD_0_OUT 0x0001 /* output mode */ -#define P5MD_0_IRTXD 0x0002 /* IrDA mode */ -#define P5MD_0_SOUT 0x0004 /* serial mode */ -#define P5MD_1 0x000c -#define P5MD_1_IN 0x0000 -#define P5MD_1_OUT 0x0004 -#define P5MD_1_IRRXDS 0x0008 /* IrDA mode */ -#define P5MD_1_SIN 0x000c /* serial mode */ -#define P5MD_2 0x0030 -#define P5MD_2_IN 0x0000 -#define P5MD_2_OUT 0x0010 -#define P5MD_2_IRRXDF 0x0020 /* IrDA mode */ - -#define P5IN __SYSREG(0xdb000504, u8) /* in reg */ -#define P5OUT __SYSREG(0xdb000508, u8) /* out reg */ - - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PIO_REGS_H */ diff --git a/arch/mn10300/include/asm/processor.h b/arch/mn10300/include/asm/processor.h deleted file mode 100644 index 3ae479117b42..000000000000 --- a/arch/mn10300/include/asm/processor.h +++ /dev/null @@ -1,171 +0,0 @@ -/* MN10300 Processor specifics - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_PROCESSOR_H -#define _ASM_PROCESSOR_H - -#include -#include -#include -#include -#include -#include - -/* Forward declaration, a strange C thing */ -struct task_struct; -struct mm_struct; - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() \ -({ \ - void *__pc; \ - asm("mov pc,%0" : "=a"(__pc)); \ - __pc; \ -}) - -extern void get_mem_info(unsigned long *mem_base, unsigned long *mem_size); - -extern void show_registers(struct pt_regs *regs); - -/* - * CPU type and hardware bug flags. Kept separately for each CPU. - * Members of this structure are referenced in head.S, so think twice - * before touching them. [mj] - */ - -struct mn10300_cpuinfo { - int type; - unsigned long loops_per_jiffy; - char hard_math; -}; - -extern struct mn10300_cpuinfo boot_cpu_data; - -#ifdef CONFIG_SMP -#if CONFIG_NR_CPUS < 2 || CONFIG_NR_CPUS > 8 -# error Sorry, NR_CPUS should be 2 to 8 -#endif -extern struct mn10300_cpuinfo cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] -#else /* CONFIG_SMP */ -#define cpu_data &boot_cpu_data -#define current_cpu_data boot_cpu_data -#endif /* CONFIG_SMP */ - -extern void identify_cpu(struct mn10300_cpuinfo *); -extern void print_cpu_info(struct mn10300_cpuinfo *); -extern void dodgy_tsc(void); - -#define cpu_relax() barrier() - -/* - * User space process size: 1.75GB (default). - */ -#define TASK_SIZE 0x70000000 - -/* - * Where to put the userspace stack by default - */ -#define STACK_TOP 0x70000000 -#define STACK_TOP_MAX STACK_TOP - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE 0x30000000 - -struct fpu_state_struct { - unsigned long fs[32]; /* fpu registers */ - unsigned long fpcr; /* fpu control register */ -}; - -struct thread_struct { - struct pt_regs *uregs; /* userspace register frame */ - unsigned long pc; /* kernel PC */ - unsigned long sp; /* kernel SP */ - unsigned long a3; /* kernel FP */ - unsigned long wchan; - unsigned long usp; - unsigned long fpu_flags; -#define THREAD_USING_FPU 0x00000001 /* T if this task is using the FPU */ -#define THREAD_HAS_FPU 0x00000002 /* T if this task owns the FPU right now */ - struct fpu_state_struct fpu_state; -}; - -#define INIT_THREAD \ -{ \ - .uregs = init_uregs, \ - .pc = 0, \ - .sp = 0, \ - .a3 = 0, \ - .wchan = 0, \ -} - -#define INIT_MMAP \ -{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, \ - NULL, NULL } - -/* - * do necessary setup to start up a newly executed thread - */ -static inline void start_thread(struct pt_regs *regs, - unsigned long new_pc, unsigned long new_sp) -{ - regs->epsw = EPSW_nSL | EPSW_IE | EPSW_IM; - regs->pc = new_pc; - regs->sp = new_sp; -} - - -/* Free all resources held by a thread. */ -extern void release_thread(struct task_struct *); - -unsigned long get_wchan(struct task_struct *p); - -#define task_pt_regs(task) ((task)->thread.uregs) -#define KSTK_EIP(task) (task_pt_regs(task)->pc) -#define KSTK_ESP(task) (task_pt_regs(task)->sp) - -#define KSTK_TOP(info) \ -({ \ - (unsigned long)(info) + THREAD_SIZE; \ -}) - -#define ARCH_HAS_PREFETCH -#define ARCH_HAS_PREFETCHW - -static inline void prefetch(const void *x) -{ -#ifdef CONFIG_MN10300_CACHE_ENABLED -#ifdef CONFIG_MN10300_PROC_MN103E010 - asm volatile ("nop; nop; dcpf (%0)" : : "r"(x)); -#else - asm volatile ("dcpf (%0)" : : "r"(x)); -#endif -#endif -} - -static inline void prefetchw(const void *x) -{ -#ifdef CONFIG_MN10300_CACHE_ENABLED -#ifdef CONFIG_MN10300_PROC_MN103E010 - asm volatile ("nop; nop; dcpf (%0)" : : "r"(x)); -#else - asm volatile ("dcpf (%0)" : : "r"(x)); -#endif -#endif -} - -#endif /* _ASM_PROCESSOR_H */ diff --git a/arch/mn10300/include/asm/ptrace.h b/arch/mn10300/include/asm/ptrace.h deleted file mode 100644 index 838a3830010e..000000000000 --- a/arch/mn10300/include/asm/ptrace.h +++ /dev/null @@ -1,26 +0,0 @@ -/* MN10300 Exception frame layout and ptrace constants - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PTRACE_H -#define _ASM_PTRACE_H - -#include - - -#define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL) -#define instruction_pointer(regs) ((regs)->pc) -#define user_stack_pointer(regs) ((regs)->sp) -#define current_pt_regs() current_frame() - -#define arch_has_single_step() (1) - -#define profile_pc(regs) ((regs)->pc) - -#endif /* _ASM_PTRACE_H */ diff --git a/arch/mn10300/include/asm/reset-regs.h b/arch/mn10300/include/asm/reset-regs.h deleted file mode 100644 index 8ca2a42d365b..000000000000 --- a/arch/mn10300/include/asm/reset-regs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* MN10300 Reset controller and watchdog timer definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_RESET_REGS_H -#define _ASM_RESET_REGS_H - -#include -#include - -#ifdef __KERNEL__ - -/* - * watchdog timer registers - */ -#define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */ - -#define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */ -#define WDCTR_WDCK 0x07 /* clock source selection */ -#define WDCTR_WDCK_256th 0x00 /* - OSCI/256 */ -#define WDCTR_WDCK_1024th 0x01 /* - OSCI/1024 */ -#define WDCTR_WDCK_2048th 0x02 /* - OSCI/2048 */ -#define WDCTR_WDCK_16384th 0x03 /* - OSCI/16384 */ -#define WDCTR_WDCK_65536th 0x04 /* - OSCI/65536 */ -#define WDCTR_WDRST 0x40 /* binary counter reset */ -#define WDCTR_WDCNE 0x80 /* watchdog timer enable */ - -#define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */ -#define RSTCTR_CHIPRST 0x01 /* chip reset */ -#define RSTCTR_DBFRST 0x02 /* double fault reset flag */ -#define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */ -#define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */ - -#ifndef __ASSEMBLY__ - -static inline void mn10300_proc_hard_reset(void) -{ - RSTCTR &= ~RSTCTR_CHIPRST; - RSTCTR |= RSTCTR_CHIPRST; -} - -extern unsigned int watchdog_alert_counter[]; - -extern void watchdog_go(void); -extern asmlinkage void watchdog_handler(void); -extern asmlinkage -void watchdog_interrupt(struct pt_regs *, enum exception_code); - -#endif - -#endif /* __KERNEL__ */ - -#endif /* _ASM_RESET_REGS_H */ diff --git a/arch/mn10300/include/asm/rtc-regs.h b/arch/mn10300/include/asm/rtc-regs.h deleted file mode 100644 index c81cacecb6e3..000000000000 --- a/arch/mn10300/include/asm/rtc-regs.h +++ /dev/null @@ -1,86 +0,0 @@ -/* MN10300 on-chip Real-Time Clock registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_RTC_REGS_H -#define _ASM_RTC_REGS_H - -#include - -#ifdef __KERNEL__ - -#define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */ -#define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */ -#define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */ -#define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */ -#define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */ -#define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */ -#define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */ -#define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */ -#define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */ -#define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */ - -#define RTCRA __SYSREG(0xd860000a, u8)/* RTC control reg A */ -#define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */ -#define RTCRA_RS_NONE 0x00 /* - off */ -#define RTCRA_RS_3_90625ms 0x01 /* - 3.90625ms (1/256s) */ -#define RTCRA_RS_7_8125ms 0x02 /* - 7.8125ms (1/128s) */ -#define RTCRA_RS_122_070us 0x03 /* - 122.070us (1/8192s) */ -#define RTCRA_RS_244_141us 0x04 /* - 244.141us (1/4096s) */ -#define RTCRA_RS_488_281us 0x05 /* - 488.281us (1/2048s) */ -#define RTCRA_RS_976_5625us 0x06 /* - 976.5625us (1/1024s) */ -#define RTCRA_RS_1_953125ms 0x07 /* - 1.953125ms (1/512s) */ -#define RTCRA_RS_3_90624ms 0x08 /* - 3.90624ms (1/256s) */ -#define RTCRA_RS_7_8125ms_b 0x09 /* - 7.8125ms (1/128s) */ -#define RTCRA_RS_15_625ms 0x0a /* - 15.625ms (1/64s) */ -#define RTCRA_RS_31_25ms 0x0b /* - 31.25ms (1/32s) */ -#define RTCRA_RS_62_5ms 0x0c /* - 62.5ms (1/16s) */ -#define RTCRA_RS_125ms 0x0d /* - 125ms (1/8s) */ -#define RTCRA_RS_250ms 0x0e /* - 250ms (1/4s) */ -#define RTCRA_RS_500ms 0x0f /* - 500ms (1/2s) */ -#define RTCRA_DVR 0x40 /* divider reset */ -#define RTCRA_UIP 0x80 /* clock update flag */ - -#define RTCRB __SYSREG(0xd860000b, u8) /* RTC control reg B */ -#define RTCRB_DSE 0x01 /* daylight savings time enable */ -#define RTCRB_TM 0x02 /* time format */ -#define RTCRB_TM_12HR 0x00 /* - 12 hour format */ -#define RTCRB_TM_24HR 0x02 /* - 24 hour format */ -#define RTCRB_DM 0x04 /* numeric value format */ -#define RTCRB_DM_BCD 0x00 /* - BCD */ -#define RTCRB_DM_BINARY 0x04 /* - binary */ -#define RTCRB_UIE 0x10 /* update interrupt disable */ -#define RTCRB_AIE 0x20 /* alarm interrupt disable */ -#define RTCRB_PIE 0x40 /* periodic interrupt disable */ -#define RTCRB_SET 0x80 /* clock update enable */ - -#define RTSRC __SYSREG(0xd860000c, u8) /* RTC status reg C */ -#define RTSRC_UF 0x10 /* update end interrupt flag */ -#define RTSRC_AF 0x20 /* alarm interrupt flag */ -#define RTSRC_PF 0x40 /* periodic interrupt flag */ -#define RTSRC_IRQF 0x80 /* interrupt flag */ - -#define RTIRQ 32 -#define RTICR GxICR(RTIRQ) - -/* - * MC146818 RTC compatibility defs for the MN10300 on-chip RTC - */ -#define RTC_PORT(x) 0xd8600000 -#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ - -#define CMOS_READ(addr) __SYSREG(0xd8600000 + (u32)(addr), u8) -#define CMOS_WRITE(val, addr) \ - do { __SYSREG(0xd8600000 + (u32)(addr), u8) = val; } while (0) - -#define RTC_IRQ RTIRQ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_RTC_REGS_H */ diff --git a/arch/mn10300/include/asm/rtc.h b/arch/mn10300/include/asm/rtc.h deleted file mode 100644 index 07dc87656197..000000000000 --- a/arch/mn10300/include/asm/rtc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* MN10300 Real time clock definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_RTC_H -#define _ASM_RTC_H - -#ifdef CONFIG_MN10300_RTC - -#include - -extern void __init calibrate_clock(void); - -#else /* !CONFIG_MN10300_RTC */ - -static inline void calibrate_clock(void) -{ -} - -#endif /* !CONFIG_MN10300_RTC */ - -#endif /* _ASM_RTC_H */ diff --git a/arch/mn10300/include/asm/rwlock.h b/arch/mn10300/include/asm/rwlock.h deleted file mode 100644 index 6d594d4a0e10..000000000000 --- a/arch/mn10300/include/asm/rwlock.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Helpers used by both rw spinlocks and rw semaphores. - * - * Based in part on code from semaphore.h and - * spinlock.h Copyright 1996 Linus Torvalds. - * - * Copyright 1999 Red Hat, Inc. - * - * Written by Benjamin LaHaise. - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 13-Nov-2006 MEI Temporarily delete lock functions for SMP support. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - */ -#ifndef _ASM_RWLOCK_H -#define _ASM_RWLOCK_H - -#define RW_LOCK_BIAS 0x01000000 - -#ifndef CONFIG_SMP - -typedef struct { unsigned long a[100]; } __dummy_lock_t; -#define __dummy_lock(lock) (*(__dummy_lock_t *)(lock)) - -#define RW_LOCK_BIAS_STR "0x01000000" - -#define __build_read_lock_ptr(rw, helper) \ - do { \ - asm volatile( \ - " mov (%0),d3 \n" \ - " sub 1,d3 \n" \ - " mov d3,(%0) \n" \ - " blt 1f \n" \ - " bra 2f \n" \ - "1: jmp 3f \n" \ - "2: \n" \ - " .section .text.lock,\"ax\" \n" \ - "3: call "helper"[],0 \n" \ - " jmp 2b \n" \ - " .previous" \ - : \ - : "d" (rw) \ - : "memory", "d3", "cc"); \ - } while (0) - -#define __build_read_lock_const(rw, helper) \ - do { \ - asm volatile( \ - " mov (%0),d3 \n" \ - " sub 1,d3 \n" \ - " mov d3,(%0) \n" \ - " blt 1f \n" \ - " bra 2f \n" \ - "1: jmp 3f \n" \ - "2: \n" \ - " .section .text.lock,\"ax\" \n" \ - "3: call "helper"[],0 \n" \ - " jmp 2b \n" \ - " .previous" \ - : \ - : "d" (rw) \ - : "memory", "d3", "cc"); \ - } while (0) - -#define __build_read_lock(rw, helper) \ - do { \ - if (__builtin_constant_p(rw)) \ - __build_read_lock_const(rw, helper); \ - else \ - __build_read_lock_ptr(rw, helper); \ - } while (0) - -#define __build_write_lock_ptr(rw, helper) \ - do { \ - asm volatile( \ - " mov (%0),d3 \n" \ - " sub 1,d3 \n" \ - " mov d3,(%0) \n" \ - " blt 1f \n" \ - " bra 2f \n" \ - "1: jmp 3f \n" \ - "2: \n" \ - " .section .text.lock,\"ax\" \n" \ - "3: call "helper"[],0 \n" \ - " jmp 2b \n" \ - " .previous" \ - : \ - : "d" (rw) \ - : "memory", "d3", "cc"); \ - } while (0) - -#define __build_write_lock_const(rw, helper) \ - do { \ - asm volatile( \ - " mov (%0),d3 \n" \ - " sub 1,d3 \n" \ - " mov d3,(%0) \n" \ - " blt 1f \n" \ - " bra 2f \n" \ - "1: jmp 3f \n" \ - "2: \n" \ - " .section .text.lock,\"ax\" \n" \ - "3: call "helper"[],0 \n" \ - " jmp 2b \n" \ - " .previous" \ - : \ - : "d" (rw) \ - : "memory", "d3", "cc"); \ - } while (0) - -#define __build_write_lock(rw, helper) \ - do { \ - if (__builtin_constant_p(rw)) \ - __build_write_lock_const(rw, helper); \ - else \ - __build_write_lock_ptr(rw, helper); \ - } while (0) - -#endif /* CONFIG_SMP */ -#endif /* _ASM_RWLOCK_H */ diff --git a/arch/mn10300/include/asm/serial-regs.h b/arch/mn10300/include/asm/serial-regs.h deleted file mode 100644 index 8320cda32f5a..000000000000 --- a/arch/mn10300/include/asm/serial-regs.h +++ /dev/null @@ -1,191 +0,0 @@ -/* MN10300 on-board serial port module registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_SERIAL_REGS_H -#define _ASM_SERIAL_REGS_H - -#include -#include - -#ifdef __KERNEL__ - -/* serial port 0 */ -#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */ -#define SC01CTR_CK 0x0007 /* clock source select */ -#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */ -#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */ -#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */ -#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */ -#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) -#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */ -#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */ -#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */ -#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */ -#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */ -#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */ -#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 1 only) */ -#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */ -#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ -#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */ -#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */ -#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */ -#define SC1CTR_CK_TM12UFLOW_8 0x0000 /* - 1/8 timer 12 underflow (serial port 1 only) */ -#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ -#define SC01CTR_STB 0x0008 /* stop bit select */ -#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */ -#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */ -#define SC01CTR_PB 0x0070 /* parity bit select */ -#define SC01CTR_PB_NONE 0x0000 /* - no parity */ -#define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ -#define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ -#define SC01CTR_PB_EVEN 0x0060 /* - even parity */ -#define SC01CTR_PB_ODD 0x0070 /* - odd parity */ -#define SC01CTR_CLN 0x0080 /* character length */ -#define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ -#define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ -#define SC01CTR_TOE 0x0100 /* T input output enable */ -#define SC01CTR_OD 0x0200 /* bit order select */ -#define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */ -#define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */ -#define SC01CTR_MD 0x0c00 /* mode select */ -#define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */ -#define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */ -#define SC01CTR_MD_I2C 0x0800 /* - I2C mode */ -#define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */ -#define SC01CTR_IIC 0x1000 /* I2C mode select */ -#define SC01CTR_BKE 0x2000 /* break transmit enable */ -#define SC01CTR_RXE 0x4000 /* receive enable */ -#define SC01CTR_TXE 0x8000 /* transmit enable */ - -#define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */ -#define SC01ICR_DMD 0x80 /* output data mode */ -#define SC01ICR_TD 0x20 /* transmit DMA trigger cause */ -#define SC01ICR_TI 0x10 /* transmit interrupt cause */ -#define SC01ICR_RES 0x04 /* receive error select */ -#define SC01ICR_RI 0x01 /* receive interrupt cause */ - -#define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */ -#define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */ - -#define SC0STR __SYSREG(0xd400200c, u16) /* status reg */ -#define SC01STR_OEF 0x0001 /* overrun error found */ -#define SC01STR_PEF 0x0002 /* parity error found */ -#define SC01STR_FEF 0x0004 /* framing error found */ -#define SC01STR_RBF 0x0010 /* receive buffer status */ -#define SC01STR_TBF 0x0020 /* transmit buffer status */ -#define SC01STR_RXF 0x0040 /* receive status */ -#define SC01STR_TXF 0x0080 /* transmit status */ -#define SC01STR_STF 0x0100 /* I2C start sequence found */ -#define SC01STR_SPF 0x0200 /* I2C stop sequence found */ - -#define SC0RXIRQ 20 /* timer 0 Receive IRQ */ -#define SC0TXIRQ 21 /* timer 0 Transmit IRQ */ - -#define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */ -#define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */ - -/* serial port 1 */ -#define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */ -#define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */ -#define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */ -#define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */ -#define SC1STR __SYSREG(0xd400201c, u16) /* status reg */ - -#define SC1RXIRQ 22 /* timer 1 Receive IRQ */ -#define SC1TXIRQ 23 /* timer 1 Transmit IRQ */ - -#define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */ -#define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */ - -/* serial port 2 */ -#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */ -#ifdef CONFIG_AM33_2 -#define SC2CTR_CK 0x0003 /* clock source select */ -#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */ -#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */ -#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */ -#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */ -#else /* CONFIG_AM33_2 */ -#define SC2CTR_CK 0x0007 /* clock source select */ -#define SC2CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow */ -#define SC2CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */ -#define SC2CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */ -#define SC2CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow */ -#define SC2CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow */ -#define SC2CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow */ -#define SC2CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */ -#define SC2CTR_CK_EXTERN 0x0007 /* - external closk */ -#endif /* CONFIG_AM33_2 */ -#define SC2CTR_STB 0x0008 /* stop bit select */ -#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */ -#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */ -#define SC2CTR_PB 0x0070 /* parity bit select */ -#define SC2CTR_PB_NONE 0x0000 /* - no parity */ -#define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ -#define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ -#define SC2CTR_PB_EVEN 0x0060 /* - even parity */ -#define SC2CTR_PB_ODD 0x0070 /* - odd parity */ -#define SC2CTR_CLN 0x0080 /* character length */ -#define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ -#define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ -#define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */ -#define SC2CTR_OD 0x0200 /* bit order select */ -#define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */ -#define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */ -#define SC2CTR_TWS 0x1000 /* transmit wait select */ -#define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */ -#define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */ -#define SC2CTR_BKE 0x2000 /* break transmit enable */ -#define SC2CTR_RXE 0x4000 /* receive enable */ -#define SC2CTR_TXE 0x8000 /* transmit enable */ - -#define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */ -#define SC2ICR_TD 0x20 /* transmit DMA trigger cause */ -#define SC2ICR_TI 0x10 /* transmit interrupt cause */ -#define SC2ICR_RES 0x04 /* receive error select */ -#define SC2ICR_RI 0x01 /* receive interrupt cause */ - -#define SC2TXB __SYSREG(0xd4002028, u8) /* transmit buffer reg */ -#define SC2RXB __SYSREG(0xd4002029, u8) /* receive buffer reg */ - -#ifdef CONFIG_AM33_2 -#define SC2STR __SYSREG(0xd400202c, u8) /* status reg */ -#else /* CONFIG_AM33_2 */ -#define SC2STR __SYSREG(0xd400202c, u16) /* status reg */ -#endif /* CONFIG_AM33_2 */ -#define SC2STR_OEF 0x0001 /* overrun error found */ -#define SC2STR_PEF 0x0002 /* parity error found */ -#define SC2STR_FEF 0x0004 /* framing error found */ -#define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */ -#define SC2STR_RBF 0x0010 /* receive buffer status */ -#define SC2STR_TBF 0x0020 /* transmit buffer status */ -#define SC2STR_RXF 0x0040 /* receive status */ -#define SC2STR_TXF 0x0080 /* transmit status */ - -#ifdef CONFIG_AM33_2 -#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */ -#endif - -#ifdef CONFIG_AM33_2 -#define SC2RXIRQ 24 /* serial 2 Receive IRQ */ -#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */ -#else /* CONFIG_AM33_2 */ -#define SC2RXIRQ 68 /* serial 2 Receive IRQ */ -#define SC2TXIRQ 69 /* serial 2 Transmit IRQ */ -#endif /* CONFIG_AM33_2 */ - -#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */ -#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */ - - -#endif /* __KERNEL__ */ - -#endif /* _ASM_SERIAL_REGS_H */ diff --git a/arch/mn10300/include/asm/serial.h b/arch/mn10300/include/asm/serial.h deleted file mode 100644 index 594ebff15d3f..000000000000 --- a/arch/mn10300/include/asm/serial.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Standard UART definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_SERIAL_H -#define _ASM_SERIAL_H - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_8250_DETECT_IRQ -#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ) -#define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | UPF_AUTO_IRQ) -#else -#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST) -#define STD_COM4_FLAGS UPF_BOOT_AUTOCONF -#endif - -#ifdef CONFIG_SERIAL_8250_MANY_PORTS -#define FOURPORT_FLAGS UPF_FOURPORT -#define ACCENT_FLAGS 0 -#define BOCA_FLAGS 0 -#define HUB6_FLAGS 0 -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE -#endif - -#include - -#endif /* _ASM_SERIAL_H */ diff --git a/arch/mn10300/include/asm/setup.h b/arch/mn10300/include/asm/setup.h deleted file mode 100644 index fb024555d2a9..000000000000 --- a/arch/mn10300/include/asm/setup.h +++ /dev/null @@ -1,18 +0,0 @@ -/* MN10300 Setup declarations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_SETUP_H -#define _ASM_SETUP_H - -#include - -extern void __init unit_setup(void); -extern void __init unit_init_IRQ(void); -#endif /* _ASM_SETUP_H */ diff --git a/arch/mn10300/include/asm/shmparam.h b/arch/mn10300/include/asm/shmparam.h deleted file mode 100644 index 3a31faaa4353..000000000000 --- a/arch/mn10300/include/asm/shmparam.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_SHMPARAM_H -#define _ASM_SHMPARAM_H - -#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ - -#endif /* _ASM_SHMPARAM_H */ diff --git a/arch/mn10300/include/asm/signal.h b/arch/mn10300/include/asm/signal.h deleted file mode 100644 index 214ff5e9fe60..000000000000 --- a/arch/mn10300/include/asm/signal.h +++ /dev/null @@ -1,33 +0,0 @@ -/* MN10300 Signal definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_SIGNAL_H -#define _ASM_SIGNAL_H - -#include - -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#define __ARCH_HAS_SA_RESTORER - -#include - -#endif /* _ASM_SIGNAL_H */ diff --git a/arch/mn10300/include/asm/smp.h b/arch/mn10300/include/asm/smp.h deleted file mode 100644 index 56c42417d428..000000000000 --- a/arch/mn10300/include/asm/smp.h +++ /dev/null @@ -1,109 +0,0 @@ -/* MN10300 SMP support - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 13-Nov-2006 MEI Define IPI-IRQ number and add inline/macro function - * for SMP support. - * 22-Jan-2007 MEI Add the define related to SMP_BOOT_IRQ. - * 23-Feb-2007 MEI Add the define related to SMP icahce invalidate. - * 23-Jun-2008 MEI Delete INTC_IPI. - * 22-Jul-2008 MEI Add smp_nmi_call_function and related defines. - * 04-Aug-2008 MEI Delete USE_DOIRQ_CACHE_IPI. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_SMP_H -#define _ASM_SMP_H - -#ifndef __ASSEMBLY__ -#include -#include -#include -#endif - -#ifdef CONFIG_SMP -#include - -#define RESCHEDULE_IPI 63 -#define CALL_FUNC_SINGLE_IPI 192 -#define LOCAL_TIMER_IPI 193 -#define FLUSH_CACHE_IPI 194 -#define CALL_FUNCTION_NMI_IPI 195 -#define DEBUGGER_NMI_IPI 196 - -#define SMP_BOOT_IRQ 195 - -#define RESCHEDULE_GxICR_LV GxICR_LEVEL_6 -#define CALL_FUNCTION_GxICR_LV GxICR_LEVEL_4 -#define LOCAL_TIMER_GxICR_LV GxICR_LEVEL_4 -#define FLUSH_CACHE_GxICR_LV GxICR_LEVEL_0 -#define SMP_BOOT_GxICR_LV GxICR_LEVEL_0 -#define DEBUGGER_GxICR_LV CONFIG_DEBUGGER_IRQ_LEVEL - -#define TIME_OUT_COUNT_BOOT_IPI 100 -#define DELAY_TIME_BOOT_IPI 75000 - - -#ifndef __ASSEMBLY__ - -/** - * raw_smp_processor_id - Determine the raw CPU ID of the CPU running it - * - * What we really want to do is to use the CPUID hardware CPU register to get - * this information, but accesses to that aren't cached, and run at system bus - * speed, not CPU speed. A copy of this value is, however, stored in the - * thread_info struct, and that can be cached. - * - * An alternate way of dealing with this could be to use the EPSW.S bits to - * cache this information for systems with up to four CPUs. - */ -#define arch_smp_processor_id() (CPUID) -#if 0 -#define raw_smp_processor_id() (arch_smp_processor_id()) -#else -#define raw_smp_processor_id() (current_thread_info()->cpu) -#endif - -static inline int cpu_logical_map(int cpu) -{ - return cpu; -} - -static inline int cpu_number_map(int cpu) -{ - return cpu; -} - - -extern cpumask_t cpu_boot_map; - -extern void smp_init_cpus(void); -extern void smp_cache_interrupt(void); -extern void send_IPI_allbutself(int irq); -extern int smp_nmi_call_function(void (*func)(void *), void *info, int wait); - -extern void arch_send_call_function_single_ipi(int cpu); -extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); - -#ifdef CONFIG_HOTPLUG_CPU -extern int __cpu_disable(void); -extern void __cpu_die(unsigned int cpu); -#endif /* CONFIG_HOTPLUG_CPU */ - -#endif /* __ASSEMBLY__ */ -#else /* CONFIG_SMP */ -#ifndef __ASSEMBLY__ - -static inline void smp_init_cpus(void) {} -#define raw_smp_processor_id() 0 - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_SMP */ - -#endif /* _ASM_SMP_H */ diff --git a/arch/mn10300/include/asm/smsc911x.h b/arch/mn10300/include/asm/smsc911x.h deleted file mode 100644 index 2fcd1080322b..000000000000 --- a/arch/mn10300/include/asm/smsc911x.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/spinlock.h b/arch/mn10300/include/asm/spinlock.h deleted file mode 100644 index 879cd0df53ba..000000000000 --- a/arch/mn10300/include/asm/spinlock.h +++ /dev/null @@ -1,180 +0,0 @@ -/* MN10300 spinlock support - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_SPINLOCK_H -#define _ASM_SPINLOCK_H - -#include -#include -#include -#include -#include - -/* - * Simple spin lock operations. There are two variants, one clears IRQ's - * on the local processor, one does not. - * - * We make no fairness assumptions. They have a cost. - */ - -#define arch_spin_is_locked(x) (*(volatile signed char *)(&(x)->slock) != 0) - -static inline void arch_spin_unlock(arch_spinlock_t *lock) -{ - asm volatile( - " bclr 1,(0,%0) \n" - : - : "a"(&lock->slock) - : "memory", "cc"); -} - -static inline int arch_spin_trylock(arch_spinlock_t *lock) -{ - int ret; - - asm volatile( - " mov 1,%0 \n" - " bset %0,(%1) \n" - " bne 1f \n" - " clr %0 \n" - "1: xor 1,%0 \n" - : "=d"(ret) - : "a"(&lock->slock) - : "memory", "cc"); - - return ret; -} - -static inline void arch_spin_lock(arch_spinlock_t *lock) -{ - asm volatile( - "1: bset 1,(0,%0) \n" - " bne 1b \n" - : - : "a"(&lock->slock) - : "memory", "cc"); -} - -static inline void arch_spin_lock_flags(arch_spinlock_t *lock, - unsigned long flags) -{ - int temp; - - asm volatile( - "1: bset 1,(0,%2) \n" - " beq 3f \n" - " mov %1,epsw \n" - "2: mov (0,%2),%0 \n" - " or %0,%0 \n" - " bne 2b \n" - " mov %3,%0 \n" - " mov %0,epsw \n" - " nop \n" - " nop \n" - " bra 1b\n" - "3: \n" - : "=&d" (temp) - : "d" (flags), "a"(&lock->slock), "i"(EPSW_IE | MN10300_CLI_LEVEL) - : "memory", "cc"); -} -#define arch_spin_lock_flags arch_spin_lock_flags - -#ifdef __KERNEL__ - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - */ - -/* - * On mn10300, we implement read-write locks as a 32-bit counter - * with the high bit (sign) being the "contended" bit. - */ -static inline void arch_read_lock(arch_rwlock_t *rw) -{ -#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT - __build_read_lock(rw, "__read_lock_failed"); -#else - { - atomic_t *count = (atomic_t *)rw; - while (atomic_dec_return(count) < 0) - atomic_inc(count); - } -#endif -} - -static inline void arch_write_lock(arch_rwlock_t *rw) -{ -#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT - __build_write_lock(rw, "__write_lock_failed"); -#else - { - atomic_t *count = (atomic_t *)rw; - while (!atomic_sub_and_test(RW_LOCK_BIAS, count)) - atomic_add(RW_LOCK_BIAS, count); - } -#endif -} - -static inline void arch_read_unlock(arch_rwlock_t *rw) -{ -#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT - __build_read_unlock(rw); -#else - { - atomic_t *count = (atomic_t *)rw; - atomic_inc(count); - } -#endif -} - -static inline void arch_write_unlock(arch_rwlock_t *rw) -{ -#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT - __build_write_unlock(rw); -#else - { - atomic_t *count = (atomic_t *)rw; - atomic_add(RW_LOCK_BIAS, count); - } -#endif -} - -static inline int arch_read_trylock(arch_rwlock_t *lock) -{ - atomic_t *count = (atomic_t *)lock; - atomic_dec(count); - if (atomic_read(count) >= 0) - return 1; - atomic_inc(count); - return 0; -} - -static inline int arch_write_trylock(arch_rwlock_t *lock) -{ - atomic_t *count = (atomic_t *)lock; - if (atomic_sub_and_test(RW_LOCK_BIAS, count)) - return 1; - atomic_add(RW_LOCK_BIAS, count); - return 0; -} - -#define _raw_spin_relax(lock) cpu_relax() -#define _raw_read_relax(lock) cpu_relax() -#define _raw_write_relax(lock) cpu_relax() - -#endif /* __KERNEL__ */ -#endif /* _ASM_SPINLOCK_H */ diff --git a/arch/mn10300/include/asm/spinlock_types.h b/arch/mn10300/include/asm/spinlock_types.h deleted file mode 100644 index 32abdc89bbc7..000000000000 --- a/arch/mn10300/include/asm/spinlock_types.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_SPINLOCK_TYPES_H -#define _ASM_SPINLOCK_TYPES_H - -#ifndef __LINUX_SPINLOCK_TYPES_H -# error "please don't include this file directly" -#endif - -typedef struct arch_spinlock { - unsigned int slock; -} arch_spinlock_t; - -#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } - -typedef struct { - unsigned int lock; -} arch_rwlock_t; - -#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } - -#endif /* _ASM_SPINLOCK_TYPES_H */ diff --git a/arch/mn10300/include/asm/string.h b/arch/mn10300/include/asm/string.h deleted file mode 100644 index 47dbd4346c32..000000000000 --- a/arch/mn10300/include/asm/string.h +++ /dev/null @@ -1,32 +0,0 @@ -/* MN10300 Optimised string functions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_STRING_H -#define _ASM_STRING_H - -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE - -extern void *memset(void *dest, int ch, size_t count); -extern void *memcpy(void *dest, const void *src, size_t count); -extern void *memmove(void *dest, const void *src, size_t count); - - -extern void __struct_cpy_bug(void); -#define struct_cpy(x, y) \ -({ \ - if (sizeof(*(x)) != sizeof(*(y))) \ - __struct_cpy_bug; \ - memcpy(x, y, sizeof(*(x))); \ -}) - -#endif /* _ASM_STRING_H */ diff --git a/arch/mn10300/include/asm/switch_to.h b/arch/mn10300/include/asm/switch_to.h deleted file mode 100644 index 67e333aa7629..000000000000 --- a/arch/mn10300/include/asm/switch_to.h +++ /dev/null @@ -1,49 +0,0 @@ -/* MN10300 task switching definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_SWITCH_TO_H -#define _ASM_SWITCH_TO_H - -#include - -struct task_struct; -struct thread_struct; - -#if defined(CONFIG_FPU) && !defined(CONFIG_LAZY_SAVE_FPU) -struct fpu_state_struct; -extern asmlinkage void fpu_save(struct fpu_state_struct *); -#define switch_fpu(prev, next) \ - do { \ - if ((prev)->thread.fpu_flags & THREAD_HAS_FPU) { \ - (prev)->thread.fpu_flags &= ~THREAD_HAS_FPU; \ - (prev)->thread.uregs->epsw &= ~EPSW_FE; \ - fpu_save(&(prev)->thread.fpu_state); \ - } \ - } while (0) -#else -#define switch_fpu(prev, next) do {} while (0) -#endif - -/* context switching is now performed out-of-line in switch_to.S */ -extern asmlinkage -struct task_struct *__switch_to(struct thread_struct *prev, - struct thread_struct *next, - struct task_struct *prev_task); - -#define switch_to(prev, next, last) \ -do { \ - switch_fpu(prev, next); \ - current->thread.wchan = (u_long) __builtin_return_address(0); \ - (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \ - mb(); \ - current->thread.wchan = 0; \ -} while (0) - -#endif /* _ASM_SWITCH_TO_H */ diff --git a/arch/mn10300/include/asm/syscall.h b/arch/mn10300/include/asm/syscall.h deleted file mode 100644 index b44b0bb75a01..000000000000 --- a/arch/mn10300/include/asm/syscall.h +++ /dev/null @@ -1,117 +0,0 @@ -/* Access to user system call parameters and results - * - * See asm-generic/syscall.h for function descriptions. - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_SYSCALL_H -#define _ASM_SYSCALL_H - -#include -#include - -extern const unsigned long sys_call_table[]; - -static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs) -{ - return regs->orig_d0; -} - -static inline void syscall_rollback(struct task_struct *task, - struct pt_regs *regs) -{ - regs->d0 = regs->orig_d0; -} - -static inline long syscall_get_error(struct task_struct *task, - struct pt_regs *regs) -{ - unsigned long error = regs->d0; - return IS_ERR_VALUE(error) ? error : 0; -} - -static inline long syscall_get_return_value(struct task_struct *task, - struct pt_regs *regs) -{ - return regs->d0; -} - -static inline void syscall_set_return_value(struct task_struct *task, - struct pt_regs *regs, - int error, long val) -{ - regs->d0 = (long) error ?: val; -} - -static inline void syscall_get_arguments(struct task_struct *task, - struct pt_regs *regs, - unsigned int i, unsigned int n, - unsigned long *args) -{ - switch (i) { - case 0: - if (!n--) break; - *args++ = regs->a0; - case 1: - if (!n--) break; - *args++ = regs->d1; - case 2: - if (!n--) break; - *args++ = regs->a3; - case 3: - if (!n--) break; - *args++ = regs->a2; - case 4: - if (!n--) break; - *args++ = regs->d3; - case 5: - if (!n--) break; - *args++ = regs->d2; - case 6: - if (!n--) break; - default: - BUG(); - break; - } -} - -static inline void syscall_set_arguments(struct task_struct *task, - struct pt_regs *regs, - unsigned int i, unsigned int n, - const unsigned long *args) -{ - switch (i) { - case 0: - if (!n--) break; - regs->a0 = *args++; - case 1: - if (!n--) break; - regs->d1 = *args++; - case 2: - if (!n--) break; - regs->a3 = *args++; - case 3: - if (!n--) break; - regs->a2 = *args++; - case 4: - if (!n--) break; - regs->d3 = *args++; - case 5: - if (!n--) break; - regs->d2 = *args++; - case 6: - if (!n--) break; - default: - BUG(); - break; - } -} - -#endif /* _ASM_SYSCALL_H */ diff --git a/arch/mn10300/include/asm/termios.h b/arch/mn10300/include/asm/termios.h deleted file mode 100644 index 4010edcaa08e..000000000000 --- a/arch/mn10300/include/asm/termios.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_TERMIOS_H -#define _ASM_TERMIOS_H - -#include - -/* intr=^C quit=^| erase=del kill=^U - eof=^D vtime=\0 vmin=\1 sxtc=\0 - start=^Q stop=^S susp=^Z eol=\0 - reprint=^R discard=^U werase=^W lnext=^V - eol2=\0 -*/ -#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" -#endif /* _ASM_TERMIOS_H */ diff --git a/arch/mn10300/include/asm/thread_info.h b/arch/mn10300/include/asm/thread_info.h deleted file mode 100644 index 1748a7b25bf8..000000000000 --- a/arch/mn10300/include/asm/thread_info.h +++ /dev/null @@ -1,160 +0,0 @@ -/* MN10300 Low-level thread information - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#include - -#ifdef CONFIG_4KSTACKS -#define THREAD_SIZE (4096) -#define THREAD_SIZE_ORDER (0) -#else -#define THREAD_SIZE (8192) -#define THREAD_SIZE_ORDER (1) -#endif - -#define STACK_WARN (THREAD_SIZE / 8) - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - * - if the contents of this structure are changed, the assembly constants - * must also be changed - */ -#ifndef __ASSEMBLY__ -typedef struct { - unsigned long seg; -} mm_segment_t; - -struct thread_info { - struct task_struct *task; /* main task structure */ - struct pt_regs *frame; /* current exception frame */ - unsigned long flags; /* low level flags */ - __u32 cpu; /* current CPU */ - __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ - - mm_segment_t addr_limit; /* thread address space: - 0-0xBFFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ - - __u8 supervisor_stack[0]; -}; - -#define thread_info_to_uregs(ti) \ - ((struct pt_regs *) \ - ((unsigned long)ti + THREAD_SIZE - sizeof(struct pt_regs))) - -#else /* !__ASSEMBLY__ */ - -#ifndef __ASM_OFFSETS_H__ -#include -#endif - -#endif - -/* - * macros/functions for gaining access to the thread information structure - */ -#ifndef __ASSEMBLY__ - -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ -} - -#define init_uregs \ - ((struct pt_regs *) \ - ((unsigned long) init_stack + THREAD_SIZE - sizeof(struct pt_regs))) - -extern struct thread_info *__current_ti; - -/* how to get the thread information struct from C */ -static inline __attribute__((const)) -struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - asm("mov sp,%0\n" - "and %1,%0\n" - : "=d" (ti) - : "i" (~(THREAD_SIZE - 1)) - : "cc"); - return ti; -} - -static inline __attribute__((const)) -struct pt_regs *current_frame(void) -{ - return current_thread_info()->frame; -} - -/* how to get the current stack pointer from C */ -static inline unsigned long current_stack_pointer(void) -{ - unsigned long sp; - asm("mov sp,%0; ":"=r" (sp)); - return sp; -} - -#ifndef CONFIG_KGDB -void arch_release_thread_stack(unsigned long *stack); -#endif -#define get_thread_info(ti) get_task_struct((ti)->task) -#define put_thread_info(ti) put_task_struct((ti)->task) - -#else /* !__ASSEMBLY__ */ - -#ifndef __VMLINUX_LDS__ -/* how to get the thread information struct from ASM */ -.macro GET_THREAD_INFO reg - mov sp,\reg - and -THREAD_SIZE,\reg -.endm -#endif -#endif - -/* - * thread information flags - * - these are process state flags that various assembly files may need to - * access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ -#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ -#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_MEMDIE 17 /* is terminating due to OOM killer */ - -#define _TIF_SYSCALL_TRACE +(1 << TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME +(1 << TIF_NOTIFY_RESUME) -#define _TIF_SIGPENDING +(1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED +(1 << TIF_NEED_RESCHED) -#define _TIF_SINGLESTEP +(1 << TIF_SINGLESTEP) -#define _TIF_POLLING_NRFLAG +(1 << TIF_POLLING_NRFLAG) - -#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ -#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/mn10300/include/asm/timer-regs.h b/arch/mn10300/include/asm/timer-regs.h deleted file mode 100644 index c634977caf66..000000000000 --- a/arch/mn10300/include/asm/timer-regs.h +++ /dev/null @@ -1,452 +0,0 @@ -/* AM33v2 on-board timer module registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_TIMER_REGS_H -#define _ASM_TIMER_REGS_H - -#include -#include - -#ifdef __KERNEL__ - -/* - * Timer prescalar control - */ -#define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */ -#define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */ -#define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */ - -/* - * 8-bit timers - */ -#define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */ -#define TM0MD_SRC 0x07 /* timer source */ -#define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */ -#define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */ -#endif /* CONFIG_AM33_2 */ -#define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */ -#define TM1MD_SRC 0x07 /* timer source */ -#define TM1MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM1MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM1MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */ -#define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */ -#endif /* CONFIG_AM33_2 */ -#define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */ -#define TM2MD_SRC 0x07 /* timer source */ -#define TM2MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM2MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM2MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */ -#define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#if defined(CONFIG_AM33_2) -#define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */ -#endif /* CONFIG_AM33_2 */ -#define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */ -#define TM3MD_SRC 0x07 /* timer source */ -#define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM3MD_SRC_TM2CASCADE 0x03 /* - cascade with timer 2 */ -#define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */ -#endif /* CONFIG_AM33_2 */ -#define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */ - -#define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */ -#define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */ -#define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */ -#define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */ -#define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */ - -#define TM0BC __SYSREGC(0xd4003020, u8) /* timer 0 binary counter */ -#define TM1BC __SYSREGC(0xd4003021, u8) /* timer 1 binary counter */ -#define TM2BC __SYSREGC(0xd4003022, u8) /* timer 2 binary counter */ -#define TM3BC __SYSREGC(0xd4003023, u8) /* timer 3 binary counter */ -#define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */ - -#define TM0IRQ 2 /* timer 0 IRQ */ -#define TM1IRQ 3 /* timer 1 IRQ */ -#define TM2IRQ 4 /* timer 2 IRQ */ -#define TM3IRQ 5 /* timer 3 IRQ */ - -#define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */ -#define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */ -#define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */ -#define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */ - -/* - * 16-bit timers 4,5 & 7-15 - */ -#define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */ -#define TM4MD_SRC 0x07 /* timer source */ -#define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM4MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM4MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */ -#endif /* CONFIG_AM33_2 */ -#define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM5MD __SYSREG(0xd4003082, u8) /* timer 5 mode register */ -#define TM5MD_SRC 0x07 /* timer source */ -#define TM5MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM5MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM5MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM5MD_SRC_TM4CASCADE 0x03 /* - cascade with timer 4 */ -#define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */ -#else /* !CONFIG_AM33_2 */ -#define TM5MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#endif /* CONFIG_AM33_2 */ -#define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM7MD __SYSREG(0xd4003086, u8) /* timer 7 mode register */ -#define TM7MD_SRC 0x07 /* timer source */ -#define TM7MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM7MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM7MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */ -#endif /* CONFIG_AM33_2 */ -#define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM8MD __SYSREG(0xd4003088, u8) /* timer 8 mode register */ -#define TM8MD_SRC 0x07 /* timer source */ -#define TM8MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM8MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM8MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM8MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */ -#define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */ -#else /* !CONFIG_AM33_2 */ -#define TM8MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#endif /* CONFIG_AM33_2 */ -#define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM9MD __SYSREG(0xd400308a, u8) /* timer 9 mode register */ -#define TM9MD_SRC 0x07 /* timer source */ -#define TM9MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM9MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM9MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM9MD_SRC_TM8CASCADE 0x03 /* - cascade with timer 8 */ -#define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */ -#else /* !CONFIG_AM33_2 */ -#define TM9MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#endif /* CONFIG_AM33_2 */ -#define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM10MD __SYSREG(0xd400308c, u8) /* timer 10 mode register */ -#define TM10MD_SRC 0x07 /* timer source */ -#define TM10MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM10MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM10MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM10MD_SRC_TM9CASCADE 0x03 /* - cascade with timer 9 */ -#define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */ -#else /* !CONFIG_AM33_2 */ -#define TM10MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#endif /* CONFIG_AM33_2 */ -#define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM11MD __SYSREG(0xd400308e, u8) /* timer 11 mode register */ -#define TM11MD_SRC 0x07 /* timer source */ -#define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -#define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */ -#else /* !CONFIG_AM33_2 */ -#define TM11MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#endif /* CONFIG_AM33_2 */ -#define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#if defined(CONFIG_AM34_2) -#define TM12MD __SYSREG(0xd4003180, u8) /* timer 11 mode register */ -#define TM12MD_SRC 0x07 /* timer source */ -#define TM12MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM12MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM12MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM12MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM12MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM12MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#define TM12MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#define TM12MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM12MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM13MD __SYSREG(0xd4003182, u8) /* timer 11 mode register */ -#define TM13MD_SRC 0x07 /* timer source */ -#define TM13MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM13MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM13MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM13MD_SRC_TM12CASCADE 0x03 /* - cascade with timer 12 */ -#define TM13MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM13MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM13MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#define TM13MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#define TM13MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM13MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM14MD __SYSREG(0xd4003184, u8) /* timer 11 mode register */ -#define TM14MD_SRC 0x07 /* timer source */ -#define TM14MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM14MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM14MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM14MD_SRC_TM13CASCADE 0x03 /* - cascade with timer 13 */ -#define TM14MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM14MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM14MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#define TM14MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#define TM14MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM14MD_COUNT_ENABLE 0x80 /* timer count enable */ - -#define TM15MD __SYSREG(0xd4003186, u8) /* timer 11 mode register */ -#define TM15MD_SRC 0x07 /* timer source */ -#define TM15MD_SRC_IOCLK 0x00 /* - IOCLK */ -#define TM15MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ -#define TM15MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ -#define TM15MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ -#define TM15MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ -#define TM15MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ -#define TM15MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */ -#define TM15MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ -#define TM15MD_COUNT_ENABLE 0x80 /* timer count enable */ -#endif /* CONFIG_AM34_2 */ - - -#define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */ -#define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */ -#define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */ -#define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */ -#define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */ -#define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */ -#define TM89BR __SYSREG(0xd4003098, u32) /* timer 8:9 base register */ -#define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */ -#define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */ -#if defined(CONFIG_AM34_2) -#define TM12BR __SYSREG(0xd4003190, u16) /* timer 12 base register */ -#define TM13BR __SYSREG(0xd4003192, u16) /* timer 13 base register */ -#define TM14BR __SYSREG(0xd4003194, u16) /* timer 14 base register */ -#define TM15BR __SYSREG(0xd4003196, u16) /* timer 15 base register */ -#endif /* CONFIG_AM34_2 */ - -#define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */ -#define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */ -#define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */ -#define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */ -#define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */ -#define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */ -#define TM89BC __SYSREG(0xd40030a8, u32) /* timer 8:9 binary counter */ -#define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */ -#define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */ -#if defined(CONFIG_AM34_2) -#define TM12BC __SYSREG(0xd40031a0, u16) /* timer 12 binary counter */ -#define TM13BC __SYSREG(0xd40031a2, u16) /* timer 13 binary counter */ -#define TM14BC __SYSREG(0xd40031a4, u16) /* timer 14 binary counter */ -#define TM15BC __SYSREG(0xd40031a6, u16) /* timer 15 binary counter */ -#endif /* CONFIG_AM34_2 */ - -#define TM4IRQ 6 /* timer 4 IRQ */ -#define TM5IRQ 7 /* timer 5 IRQ */ -#define TM7IRQ 11 /* timer 7 IRQ */ -#define TM8IRQ 12 /* timer 8 IRQ */ -#define TM9IRQ 13 /* timer 9 IRQ */ -#define TM10IRQ 14 /* timer 10 IRQ */ -#define TM11IRQ 15 /* timer 11 IRQ */ -#if defined(CONFIG_AM34_2) -#define TM12IRQ 64 /* timer 12 IRQ */ -#define TM13IRQ 65 /* timer 13 IRQ */ -#define TM14IRQ 66 /* timer 14 IRQ */ -#define TM15IRQ 67 /* timer 15 IRQ */ -#endif /* CONFIG_AM34_2 */ - -#define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */ -#define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */ -#define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */ -#define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */ -#define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */ -#define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */ -#define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */ -#if defined(CONFIG_AM34_2) -#define TM12ICR GxICR(TM12IRQ) /* timer 12 uflow intr ctrl reg */ -#define TM13ICR GxICR(TM13IRQ) /* timer 13 uflow intr ctrl reg */ -#define TM14ICR GxICR(TM14IRQ) /* timer 14 uflow intr ctrl reg */ -#define TM15ICR GxICR(TM15IRQ) /* timer 15 uflow intr ctrl reg */ -#endif /* CONFIG_AM34_2 */ - -/* - * 16-bit timer 6 - */ -#define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */ -#define TM6MD_SRC 0x0007 /* timer source */ -#define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */ -#define TM6MD_SRC_IOCLK_8 0x0001 /* - 1/8 IOCLK */ -#define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */ -#define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */ -#define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */ -#define TM6MD_SRC_TM2UFLOW 0x0006 /* - timer 2 underflow */ -#if defined(CONFIG_AM33_2) -/* #define TM6MD_SRC_TM6IOB_BOTH 0x0006 */ /* - TM6IOB pin input (both edges) */ -#define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */ -#endif /* CONFIG_AM33_2 */ -#define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */ -#define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */ -#if defined(CONFIG_AM33_2) -#define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */ -#define TM6MD_PWM 0x3800 /* PWM output mode */ -#define TM6MD_PWM_DIS 0x0000 /* - disabled */ -#define TM6MD_PWM_10BIT 0x1000 /* - 10 bits mode */ -#define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */ -#define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */ -#define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */ -#endif /* CONFIG_AM33_2 */ - -#define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */ -#define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */ - -#define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */ -#define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */ -#define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */ -#if defined(CONFIG_AM33_2) -#define TM6MDA_OUT 0x07 /* output select */ -#define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */ -#define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */ -#define TM6MDA_OUT_SETA 0x02 /* - set at match A */ -#define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */ -#define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */ -#define TM6MDA_MODE 0xc0 /* compare A register mode */ -#define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ -#define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ -#define TM6MDA_EDGE 0x20 /* compare A edge select */ -#define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */ -#define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */ -#define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */ -#else /* !CONFIG_AM33_2 */ -#define TM6MDA_MODE 0x40 /* compare A register mode */ -#endif /* CONFIG_AM33_2 */ - -#define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */ -#define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */ -#define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */ -#if defined(CONFIG_AM33_2) -#define TM6MDB_OUT 0x07 /* output select */ -#define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */ -#define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */ -#define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */ -#define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */ -#define TM6MDB_MODE 0xc0 /* compare B register mode */ -#define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ -#define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ -#define TM6MDB_EDGE 0x20 /* compare B edge select */ -#define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */ -#define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */ -#define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */ -#else /* !CONFIG_AM33_2 */ -#define TM6MDB_MODE 0x40 /* compare B register mode */ -#endif /* CONFIG_AM33_2 */ - -#define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */ -#define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */ -#define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */ - -#define TM6IRQ 6 /* timer 6 IRQ */ -#define TM6AIRQ 9 /* timer 6A IRQ */ -#define TM6BIRQ 10 /* timer 6B IRQ */ - -#define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */ -#define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */ -#define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */ - -#if defined(CONFIG_AM34_2) -/* - * MTM: OS Tick-Timer - */ -#define TMTMD __SYSREG(0xd4004100, u8) /* Tick Timer mode register */ -#define TMTMD_TMTLDE 0x40 /* initialize TMTBC = TMTBR */ -#define TMTMD_TMTCNE 0x80 /* timer count enable */ - -#define TMTBR __SYSREG(0xd4004110, u32) /* Tick Timer mode reg */ -#define TMTBC __SYSREG(0xd4004120, u32) /* Tick Timer mode reg */ - -/* - * MTM: OS Timestamp-Timer - */ -#define TMSMD __SYSREG(0xd4004140, u8) /* Tick Timer mode register */ -#define TMSMD_TMSLDE 0x40 /* initialize TMSBC = TMSBR */ -#define TMSMD_TMSCNE 0x80 /* timer count enable */ - -#define TMSBR __SYSREG(0xd4004150, u32) /* Tick Timer mode register */ -#define TMSBC __SYSREG(0xd4004160, u32) /* Tick Timer mode register */ - -#define TMTIRQ 119 /* OS Tick timer IRQ */ -#define TMSIRQ 120 /* Timestamp timer IRQ */ - -#define TMTICR GxICR(TMTIRQ) /* OS Tick timer uflow intr ctrl reg */ -#define TMSICR GxICR(TMSIRQ) /* Timestamp timer uflow intr ctrl reg */ -#endif /* CONFIG_AM34_2 */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_TIMER_REGS_H */ diff --git a/arch/mn10300/include/asm/timex.h b/arch/mn10300/include/asm/timex.h deleted file mode 100644 index f8e66425cbf8..000000000000 --- a/arch/mn10300/include/asm/timex.h +++ /dev/null @@ -1,34 +0,0 @@ -/* MN10300 Architecture time management specifications - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_TIMEX_H -#define _ASM_TIMEX_H - -#include - -#define TICK_SIZE (tick_nsec / 1000) - -#define CLOCK_TICK_RATE MN10300_JCCLK /* Underlying HZ */ - -#ifdef __KERNEL__ - -extern cycles_t cacheflush_time; - -static inline cycles_t get_cycles(void) -{ - return read_timestamp_counter(); -} - -extern int init_clockevents(void); -extern int init_clocksource(void); - -#endif /* __KERNEL__ */ - -#endif /* _ASM_TIMEX_H */ diff --git a/arch/mn10300/include/asm/tlb.h b/arch/mn10300/include/asm/tlb.h deleted file mode 100644 index 65d232b96613..000000000000 --- a/arch/mn10300/include/asm/tlb.h +++ /dev/null @@ -1,34 +0,0 @@ -/* MN10300 TLB definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_TLB_H -#define _ASM_TLB_H - -#include - -extern void check_pgt_cache(void); - -/* - * we don't need any special per-pte or per-vma handling... - */ -#define tlb_start_vma(tlb, vma) do { } while (0) -#define tlb_end_vma(tlb, vma) do { } while (0) -#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) - -/* - * .. because we flush the whole mm when it fills up - */ -#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) - -/* for now, just use the generic stuff */ -#include - -#endif /* _ASM_TLB_H */ diff --git a/arch/mn10300/include/asm/tlbflush.h b/arch/mn10300/include/asm/tlbflush.h deleted file mode 100644 index efddd6e1adea..000000000000 --- a/arch/mn10300/include/asm/tlbflush.h +++ /dev/null @@ -1,154 +0,0 @@ -/* MN10300 TLB flushing functions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_TLBFLUSH_H -#define _ASM_TLBFLUSH_H - -#include -#include - -struct tlb_state { - struct mm_struct *active_mm; - int state; -}; -DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate); - -/** - * local_flush_tlb - Flush the current MM's entries from the local CPU's TLBs - */ -static inline void local_flush_tlb(void) -{ - int w; - asm volatile( - " mov %1,%0 \n" - " or %2,%0 \n" - " mov %0,%1 \n" - : "=d"(w) - : "m"(MMUCTR), "i"(MMUCTR_IIV|MMUCTR_DIV) - : "cc", "memory"); -} - -/** - * local_flush_tlb_all - Flush all entries from the local CPU's TLBs - */ -static inline void local_flush_tlb_all(void) -{ - local_flush_tlb(); -} - -/** - * local_flush_tlb_one - Flush one entry from the local CPU's TLBs - */ -static inline void local_flush_tlb_one(unsigned long addr) -{ - local_flush_tlb(); -} - -/** - * local_flush_tlb_page - Flush a page's entry from the local CPU's TLBs - * @mm: The MM to flush for - * @addr: The address of the target page in RAM (not its page struct) - */ -static inline -void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr) -{ - unsigned long pteu, flags, cnx; - - addr &= PAGE_MASK; - - local_irq_save(flags); - - cnx = 1; -#ifdef CONFIG_MN10300_TLB_USE_PIDR - cnx = mm->context.tlbpid[smp_processor_id()]; -#endif - if (cnx) { - pteu = addr; -#ifdef CONFIG_MN10300_TLB_USE_PIDR - pteu |= cnx & xPTEU_PID; -#endif - IPTEU = pteu; - DPTEU = pteu; - if (IPTEL & xPTEL_V) - IPTEL = 0; - if (DPTEL & xPTEL_V) - DPTEL = 0; - } - local_irq_restore(flags); -} - -/* - * TLB flushing: - * - * - flush_tlb() flushes the current mm struct TLBs - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(mm, start, end) flushes a range of pages - * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables - */ -#ifdef CONFIG_SMP - -#include - -extern void flush_tlb_all(void); -extern void flush_tlb_current_task(void); -extern void flush_tlb_mm(struct mm_struct *); -extern void flush_tlb_page(struct vm_area_struct *, unsigned long); - -#define flush_tlb() flush_tlb_current_task() - -static inline void flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - flush_tlb_mm(vma->vm_mm); -} - -#else /* CONFIG_SMP */ - -static inline void flush_tlb_all(void) -{ - preempt_disable(); - local_flush_tlb_all(); - preempt_enable(); -} - -static inline void flush_tlb_mm(struct mm_struct *mm) -{ - preempt_disable(); - local_flush_tlb_all(); - preempt_enable(); -} - -static inline void flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - preempt_disable(); - local_flush_tlb_all(); - preempt_enable(); -} - -#define flush_tlb_page(vma, addr) local_flush_tlb_page((vma)->vm_mm, addr) -#define flush_tlb() flush_tlb_all() - -#endif /* CONFIG_SMP */ - -static inline void flush_tlb_kernel_range(unsigned long start, - unsigned long end) -{ - flush_tlb_all(); -} - -static inline void flush_tlb_pgtables(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ -} - -#endif /* _ASM_TLBFLUSH_H */ diff --git a/arch/mn10300/include/asm/topology.h b/arch/mn10300/include/asm/topology.h deleted file mode 100644 index 5428f333a02c..000000000000 --- a/arch/mn10300/include/asm/topology.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/asm/types.h b/arch/mn10300/include/asm/types.h deleted file mode 100644 index 3d6e48311bef..000000000000 --- a/arch/mn10300/include/asm/types.h +++ /dev/null @@ -1,22 +0,0 @@ -/* MN10300 Basic type definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_TYPES_H -#define _ASM_TYPES_H - -#include - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ - -#define BITS_PER_LONG 32 - -#endif /* _ASM_TYPES_H */ diff --git a/arch/mn10300/include/asm/uaccess.h b/arch/mn10300/include/asm/uaccess.h deleted file mode 100644 index 5af468fd1359..000000000000 --- a/arch/mn10300/include/asm/uaccess.h +++ /dev/null @@ -1,297 +0,0 @@ -/* MN10300 userspace access functions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_UACCESS_H -#define _ASM_UACCESS_H - -/* - * User space memory access functions - */ -#include -#include - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - */ -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -#define KERNEL_XDS MAKE_MM_SEG(0xBFFFFFFF) -#define KERNEL_DS MAKE_MM_SEG(0x9FFFFFFF) -#define USER_DS MAKE_MM_SEG(TASK_SIZE) - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define segment_eq(a, b) ((a).seg == (b).seg) - -#define __addr_ok(addr) \ - ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg)) - -/* - * check that a range of addresses falls within the current address limit - */ -static inline int ___range_ok(unsigned long addr, unsigned int size) -{ - int flag = 1, tmp; - - asm(" add %3,%1 \n" /* set C-flag if addr + size > 4Gb */ - " bcs 0f \n" - " cmp %4,%1 \n" /* jump if addr+size>limit (error) */ - " bhi 0f \n" - " clr %0 \n" /* mark okay */ - "0: \n" - : "=r"(flag), "=&r"(tmp) - : "1"(addr), "ir"(size), - "r"(current_thread_info()->addr_limit.seg), "0"(flag) - : "cc" - ); - - return flag; -} - -#define __range_ok(addr, size) ___range_ok((unsigned long)(addr), (u32)(size)) - -#define access_ok(type, addr, size) (__range_ok((addr), (size)) == 0) -#define __access_ok(addr, size) (__range_ok((addr), (size)) == 0) - -#include - -#define put_user(x, ptr) __put_user_check((x), (ptr), sizeof(*(ptr))) -#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) - -/* - * The "__xxx" versions do not do address space checking, useful when - * doing multiple accesses to the same area (the user has to do the - * checks by hand with "access_ok()") - */ -#define __put_user(x, ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr))) -#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) - -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) - -#define __get_user_nocheck(x, ptr, size) \ -({ \ - unsigned long __gu_addr; \ - int __gu_err; \ - __gu_addr = (unsigned long) (ptr); \ - switch (size) { \ - case 1: { \ - unsigned char __gu_val; \ - __get_user_asm("bu"); \ - (x) = *(__force __typeof__(*(ptr))*) &__gu_val; \ - break; \ - } \ - case 2: { \ - unsigned short __gu_val; \ - __get_user_asm("hu"); \ - (x) = *(__force __typeof__(*(ptr))*) &__gu_val; \ - break; \ - } \ - case 4: { \ - unsigned int __gu_val; \ - __get_user_asm(""); \ - (x) = *(__force __typeof__(*(ptr))*) &__gu_val; \ - break; \ - } \ - default: \ - __get_user_unknown(); \ - break; \ - } \ - __gu_err; \ -}) - -#define __get_user_check(x, ptr, size) \ -({ \ - const __typeof__(*(ptr))* __guc_ptr = (ptr); \ - int _e; \ - if (likely(__access_ok((unsigned long) __guc_ptr, (size)))) \ - _e = __get_user_nocheck((x), __guc_ptr, (size)); \ - else { \ - _e = -EFAULT; \ - (x) = (__typeof__(x))0; \ - } \ - _e; \ -}) - -#define __get_user_asm(INSN) \ -({ \ - asm volatile( \ - "1:\n" \ - " mov"INSN" %2,%1\n" \ - " mov 0,%0\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3:\n\t" \ - " mov 0,%1\n" \ - " mov %3,%0\n" \ - " jmp 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign 4\n" \ - " .long 1b, 3b\n" \ - " .previous" \ - : "=&r" (__gu_err), "=&r" (__gu_val) \ - : "m" (__m(__gu_addr)), "i" (-EFAULT)); \ -}) - -extern int __get_user_unknown(void); - -#define __put_user_nocheck(x, ptr, size) \ -({ \ - union { \ - __typeof__(*(ptr)) val; \ - u32 bits[2]; \ - } __pu_val; \ - unsigned long __pu_addr; \ - int __pu_err; \ - __pu_val.val = (x); \ - __pu_addr = (unsigned long) (ptr); \ - switch (size) { \ - case 1: __put_user_asm("bu"); break; \ - case 2: __put_user_asm("hu"); break; \ - case 4: __put_user_asm("" ); break; \ - case 8: __put_user_asm8(); break; \ - default: __pu_err = __put_user_unknown(); break; \ - } \ - __pu_err; \ -}) - -#define __put_user_check(x, ptr, size) \ -({ \ - union { \ - __typeof__(*(ptr)) val; \ - u32 bits[2]; \ - } __pu_val; \ - unsigned long __pu_addr; \ - int __pu_err; \ - __pu_val.val = (x); \ - __pu_addr = (unsigned long) (ptr); \ - if (likely(__access_ok(__pu_addr, size))) { \ - switch (size) { \ - case 1: __put_user_asm("bu"); break; \ - case 2: __put_user_asm("hu"); break; \ - case 4: __put_user_asm("" ); break; \ - case 8: __put_user_asm8(); break; \ - default: __pu_err = __put_user_unknown(); break; \ - } \ - } \ - else { \ - __pu_err = -EFAULT; \ - } \ - __pu_err; \ -}) - -#define __put_user_asm(INSN) \ -({ \ - asm volatile( \ - "1:\n" \ - " mov"INSN" %1,%2\n" \ - " mov 0,%0\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3:\n" \ - " mov %3,%0\n" \ - " jmp 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign 4\n" \ - " .long 1b, 3b\n" \ - " .previous" \ - : "=&r" (__pu_err) \ - : "r" (__pu_val.val), "m" (__m(__pu_addr)), \ - "i" (-EFAULT) \ - ); \ -}) - -#define __put_user_asm8() \ -({ \ - asm volatile( \ - "1: mov %1,%3 \n" \ - "2: mov %2,%4 \n" \ - " mov 0,%0 \n" \ - "3: \n" \ - " .section .fixup,\"ax\" \n" \ - "4: \n" \ - " mov %5,%0 \n" \ - " jmp 3b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\"\n" \ - " .balign 4 \n" \ - " .long 1b, 4b \n" \ - " .long 2b, 4b \n" \ - " .previous \n" \ - : "=&r" (__pu_err) \ - : "r" (__pu_val.bits[0]), "r" (__pu_val.bits[1]), \ - "m" (__m(__pu_addr)), "m" (__m(__pu_addr+4)), \ - "i" (-EFAULT) \ - ); \ -}) - -extern int __put_user_unknown(void); - - -/* - * Copy To/From Userspace - */ -/* Generic arbitrary sized copy. */ -#define __copy_user(to, from, size) \ -do { \ - if (size) { \ - void *__to = to; \ - const void *__from = from; \ - int w; \ - asm volatile( \ - "0: movbu (%0),%3;\n" \ - "1: movbu %3,(%1);\n" \ - " inc %0;\n" \ - " inc %1;\n" \ - " add -1,%2;\n" \ - " bne 0b;\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: jmp 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign 4\n" \ - " .long 0b,3b\n" \ - " .long 1b,3b\n" \ - " .previous\n" \ - : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\ - : "0"(__from), "1"(__to), "2"(size) \ - : "cc", "memory"); \ - } \ -} while (0) - -static inline unsigned long -raw_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - __copy_user(to, from, n); - return n; -} - -static inline unsigned long -raw_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - __copy_user(to, from, n); - return n; -} - -extern long strncpy_from_user(char *dst, const char __user *src, long count); -extern long strnlen_user(const char __user *str, long n); -extern unsigned long clear_user(void __user *mem, unsigned long len); -extern unsigned long __clear_user(void __user *mem, unsigned long len); - -#endif /* _ASM_UACCESS_H */ diff --git a/arch/mn10300/include/asm/ucontext.h b/arch/mn10300/include/asm/ucontext.h deleted file mode 100644 index fcab5c1d8e18..000000000000 --- a/arch/mn10300/include/asm/ucontext.h +++ /dev/null @@ -1,22 +0,0 @@ -/* MN10300 User context - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_UCONTEXT_H -#define _ASM_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* _ASM_UCONTEXT_H */ diff --git a/arch/mn10300/include/asm/unaligned.h b/arch/mn10300/include/asm/unaligned.h deleted file mode 100644 index 0df671318ae4..000000000000 --- a/arch/mn10300/include/asm/unaligned.h +++ /dev/null @@ -1,20 +0,0 @@ -/* MN10300 Unaligned memory access handling - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_MN10300_UNALIGNED_H -#define _ASM_MN10300_UNALIGNED_H - -#include -#include - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_MN10300_UNALIGNED_H */ diff --git a/arch/mn10300/include/asm/unistd.h b/arch/mn10300/include/asm/unistd.h deleted file mode 100644 index 0522468f488b..000000000000 --- a/arch/mn10300/include/asm/unistd.h +++ /dev/null @@ -1,47 +0,0 @@ -/* MN10300 System call number list - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_UNISTD_H -#define _ASM_UNISTD_H - -#include - - -#define NR_syscalls 340 - -/* - * specify the deprecated syscalls we want to support on this arch - */ -#define __ARCH_WANT_OLD_READDIR -#define __ARCH_WANT_OLD_STAT -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_IPC -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_SIGNAL -#define __ARCH_WANT_SYS_TIME -#define __ARCH_WANT_SYS_UTIME -#define __ARCH_WANT_SYS_WAITPID -#define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_OLD_GETRLIMIT -#define __ARCH_WANT_SYS_OLD_SELECT -#define __ARCH_WANT_SYS_OLDUMOUNT -#define __ARCH_WANT_SYS_SIGPENDING -#define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_FORK -#define __ARCH_WANT_SYS_VFORK -#define __ARCH_WANT_SYS_CLONE - -#endif /* _ASM_UNISTD_H */ diff --git a/arch/mn10300/include/asm/user.h b/arch/mn10300/include/asm/user.h deleted file mode 100644 index e1193908b78c..000000000000 --- a/arch/mn10300/include/asm/user.h +++ /dev/null @@ -1,53 +0,0 @@ -/* MN10300 User process data - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_USER_H -#define _ASM_USER_H - -#include -#include - -#ifndef __ASSEMBLY__ -/* - * When the kernel dumps core, it starts by dumping the user struct - this will - * be used by gdb to figure out where the data and stack segments are within - * the file, and what virtual addresses to use. - */ -struct user { - /* We start with the registers, to mimic the way that "memory" is - * returned from the ptrace(3,...) function. - */ - struct pt_regs regs; /* Where the registers are actually stored */ - - /* The rest of this junk is to help gdb figure out what goes where */ - unsigned long int u_tsize; /* Text segment size (pages). */ - unsigned long int u_dsize; /* Data segment size (pages). */ - unsigned long int u_ssize; /* Stack segment size (pages). */ - unsigned long start_code; /* Starting virtual address of text. */ - unsigned long start_stack; /* Starting virtual address of stack area. - This is actually the bottom of the stack, - the top of the stack is always found in the - esp register. */ - long int signal; /* Signal that caused the core dump. */ - int reserved; /* No longer used */ - struct user_pt_regs *u_ar0; /* Used by gdb to help find the values for */ - - /* the registers */ - unsigned long magic; /* To uniquely identify a core file */ - char u_comm[32]; /* User command that was responsible */ -}; -#endif - -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR +(u.start_code) -#define HOST_STACK_END_ADDR +(u.start_stack + u.u_ssize * NBPG) - -#endif /* _ASM_USER_H */ diff --git a/arch/mn10300/include/asm/vga.h b/arch/mn10300/include/asm/vga.h deleted file mode 100644 index 0163e50a3459..000000000000 --- a/arch/mn10300/include/asm/vga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* MN10300 VGA register definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_VGA_H -#define _ASM_VGA_H - - - -#endif /* _ASM_VGA_H */ diff --git a/arch/mn10300/include/asm/xor.h b/arch/mn10300/include/asm/xor.h deleted file mode 100644 index c82eb12a5b18..000000000000 --- a/arch/mn10300/include/asm/xor.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/uapi/asm/Kbuild b/arch/mn10300/include/uapi/asm/Kbuild deleted file mode 100644 index b04fd1632051..000000000000 --- a/arch/mn10300/include/uapi/asm/Kbuild +++ /dev/null @@ -1,6 +0,0 @@ -# UAPI Header export list -include include/uapi/asm-generic/Kbuild.asm - -generic-y += bpf_perf_event.h -generic-y += poll.h -generic-y += siginfo.h diff --git a/arch/mn10300/include/uapi/asm/auxvec.h b/arch/mn10300/include/uapi/asm/auxvec.h deleted file mode 100644 index 4fdb60b2ae39..000000000000 --- a/arch/mn10300/include/uapi/asm/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_AUXVEC_H -#define _ASM_AUXVEC_H - -#endif diff --git a/arch/mn10300/include/uapi/asm/bitsperlong.h b/arch/mn10300/include/uapi/asm/bitsperlong.h deleted file mode 100644 index 76da34b10f59..000000000000 --- a/arch/mn10300/include/uapi/asm/bitsperlong.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include diff --git a/arch/mn10300/include/uapi/asm/byteorder.h b/arch/mn10300/include/uapi/asm/byteorder.h deleted file mode 100644 index 3467df91216c..000000000000 --- a/arch/mn10300/include/uapi/asm/byteorder.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_BYTEORDER_H -#define _ASM_BYTEORDER_H - -#include - -#endif /* _ASM_BYTEORDER_H */ diff --git a/arch/mn10300/include/uapi/asm/errno.h b/arch/mn10300/include/uapi/asm/errno.h deleted file mode 100644 index 9addba592646..000000000000 --- a/arch/mn10300/include/uapi/asm/errno.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include diff --git a/arch/mn10300/include/uapi/asm/fcntl.h b/arch/mn10300/include/uapi/asm/fcntl.h deleted file mode 100644 index a77648c505d1..000000000000 --- a/arch/mn10300/include/uapi/asm/fcntl.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include diff --git a/arch/mn10300/include/uapi/asm/ioctl.h b/arch/mn10300/include/uapi/asm/ioctl.h deleted file mode 100644 index b809c4566e5f..000000000000 --- a/arch/mn10300/include/uapi/asm/ioctl.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include diff --git a/arch/mn10300/include/uapi/asm/ioctls.h b/arch/mn10300/include/uapi/asm/ioctls.h deleted file mode 100644 index 0955d4f854e9..000000000000 --- a/arch/mn10300/include/uapi/asm/ioctls.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_IOCTLS_H -#define _ASM_IOCTLS_H - -#include - -#endif /* _ASM_IOCTLS_H */ diff --git a/arch/mn10300/include/uapi/asm/ipcbuf.h b/arch/mn10300/include/uapi/asm/ipcbuf.h deleted file mode 100644 index 90d6445a14df..000000000000 --- a/arch/mn10300/include/uapi/asm/ipcbuf.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include diff --git a/arch/mn10300/include/uapi/asm/kvm_para.h b/arch/mn10300/include/uapi/asm/kvm_para.h deleted file mode 100644 index baacc4996d18..000000000000 --- a/arch/mn10300/include/uapi/asm/kvm_para.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include diff --git a/arch/mn10300/include/uapi/asm/mman.h b/arch/mn10300/include/uapi/asm/mman.h deleted file mode 100644 index eb7f4798c036..000000000000 --- a/arch/mn10300/include/uapi/asm/mman.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include - -#define MIN_MAP_ADDR PAGE_SIZE /* minimum fixed mmap address */ - -#define arch_mmap_check(addr, len, flags) \ - (((flags) & MAP_FIXED && (addr) < MIN_MAP_ADDR) ? -EINVAL : 0) diff --git a/arch/mn10300/include/uapi/asm/msgbuf.h b/arch/mn10300/include/uapi/asm/msgbuf.h deleted file mode 100644 index 5982def83355..000000000000 --- a/arch/mn10300/include/uapi/asm/msgbuf.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_MSGBUF_H -#define _ASM_MSGBUF_H - -/* - * The msqid64_ds structure for MN10300 architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _ASM_MSGBUF_H */ diff --git a/arch/mn10300/include/uapi/asm/param.h b/arch/mn10300/include/uapi/asm/param.h deleted file mode 100644 index e0020d7742bd..000000000000 --- a/arch/mn10300/include/uapi/asm/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 Kernel parameters - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PARAM_H -#define _ASM_PARAM_H - -#include - -#define COMMAND_LINE_SIZE 256 - -#endif /* _ASM_PARAM_H */ diff --git a/arch/mn10300/include/uapi/asm/posix_types.h b/arch/mn10300/include/uapi/asm/posix_types.h deleted file mode 100644 index 6b4cfc7136e9..000000000000 --- a/arch/mn10300/include/uapi/asm/posix_types.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 POSIX types - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_POSIX_TYPES_H -#define _ASM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_mode_t; -#define __kernel_mode_t __kernel_mode_t - -typedef unsigned short __kernel_ipc_pid_t; -#define __kernel_ipc_pid_t __kernel_ipc_pid_t - -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -#define __kernel_uid_t __kernel_uid_t - -#if __GNUC__ == 4 -typedef unsigned int __kernel_size_t; -typedef signed int __kernel_ssize_t; -#else -typedef unsigned long __kernel_size_t; -typedef signed long __kernel_ssize_t; -#endif -typedef int __kernel_ptrdiff_t; -#define __kernel_size_t __kernel_size_t - -typedef unsigned short __kernel_old_dev_t; -#define __kernel_old_dev_t __kernel_old_dev_t - -#include - -#endif /* _ASM_POSIX_TYPES_H */ diff --git a/arch/mn10300/include/uapi/asm/ptrace.h b/arch/mn10300/include/uapi/asm/ptrace.h deleted file mode 100644 index f485c481a266..000000000000 --- a/arch/mn10300/include/uapi/asm/ptrace.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 Exception frame layout and ptrace constants - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _UAPI_ASM_PTRACE_H -#define _UAPI_ASM_PTRACE_H - -#define PT_A3 0 -#define PT_A2 1 -#define PT_D3 2 -#define PT_D2 3 -#define PT_MCVF 4 -#define PT_MCRL 5 -#define PT_MCRH 6 -#define PT_MDRQ 7 -#define PT_E1 8 -#define PT_E0 9 -#define PT_E7 10 -#define PT_E6 11 -#define PT_E5 12 -#define PT_E4 13 -#define PT_E3 14 -#define PT_E2 15 -#define PT_SP 16 -#define PT_LAR 17 -#define PT_LIR 18 -#define PT_MDR 19 -#define PT_A1 20 -#define PT_A0 21 -#define PT_D1 22 -#define PT_D0 23 -#define PT_ORIG_D0 24 -#define PT_EPSW 25 -#define PT_PC 26 -#define NR_PTREGS 27 - -/* - * This defines the way registers are stored in the event of an exception - * - the strange order is due to the MOVM instruction - */ -struct pt_regs { - unsigned long a3; /* syscall arg 3 */ - unsigned long a2; /* syscall arg 4 */ - unsigned long d3; /* syscall arg 5 */ - unsigned long d2; /* syscall arg 6 */ - unsigned long mcvf; - unsigned long mcrl; - unsigned long mcrh; - unsigned long mdrq; - unsigned long e1; - unsigned long e0; - unsigned long e7; - unsigned long e6; - unsigned long e5; - unsigned long e4; - unsigned long e3; - unsigned long e2; - unsigned long sp; - unsigned long lar; - unsigned long lir; - unsigned long mdr; - unsigned long a1; - unsigned long a0; /* syscall arg 1 */ - unsigned long d1; /* syscall arg 2 */ - unsigned long d0; /* syscall ret */ - struct pt_regs *next; /* next frame pointer */ - unsigned long orig_d0; /* syscall number */ - unsigned long epsw; - unsigned long pc; -}; - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#endif /* _UAPI_ASM_PTRACE_H */ diff --git a/arch/mn10300/include/uapi/asm/resource.h b/arch/mn10300/include/uapi/asm/resource.h deleted file mode 100644 index 49a81fbab43d..000000000000 --- a/arch/mn10300/include/uapi/asm/resource.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include diff --git a/arch/mn10300/include/uapi/asm/sembuf.h b/arch/mn10300/include/uapi/asm/sembuf.h deleted file mode 100644 index ef44c42c7e0f..000000000000 --- a/arch/mn10300/include/uapi/asm/sembuf.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_SEMBUF_H -#define _ASM_SEMBUF_H - -/* - * The semid64_ds structure for MN10300 architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - unsigned long __unused1; - __kernel_time_t sem_ctime; /* last change time */ - unsigned long __unused2; - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASM_SEMBUF_H */ diff --git a/arch/mn10300/include/uapi/asm/setup.h b/arch/mn10300/include/uapi/asm/setup.h deleted file mode 100644 index 043dd4b92026..000000000000 --- a/arch/mn10300/include/uapi/asm/setup.h +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * There isn't anything here anymore, but the file must not be empty or patch - * will delete it. - */ diff --git a/arch/mn10300/include/uapi/asm/shmbuf.h b/arch/mn10300/include/uapi/asm/shmbuf.h deleted file mode 100644 index 6e81f74f51c6..000000000000 --- a/arch/mn10300/include/uapi/asm/shmbuf.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_SHMBUF_H -#define _ASM_SHMBUF_H - -/* - * The shmid64_ds structure for MN10300 architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - unsigned long __unused1; - __kernel_time_t shm_dtime; /* last detach time */ - unsigned long __unused2; - __kernel_time_t shm_ctime; /* last change time */ - unsigned long __unused3; - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused4; - unsigned long __unused5; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASM_SHMBUF_H */ diff --git a/arch/mn10300/include/uapi/asm/sigcontext.h b/arch/mn10300/include/uapi/asm/sigcontext.h deleted file mode 100644 index 1c361fabb977..000000000000 --- a/arch/mn10300/include/uapi/asm/sigcontext.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 Userspace signal context - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_SIGCONTEXT_H -#define _ASM_SIGCONTEXT_H - -struct fpucontext { - /* Regular FPU environment */ - unsigned long fs[32]; /* fpu registers */ - unsigned long fpcr; /* fpu control register */ -}; - -struct sigcontext { - unsigned long d0; - unsigned long d1; - unsigned long d2; - unsigned long d3; - unsigned long a0; - unsigned long a1; - unsigned long a2; - unsigned long a3; - unsigned long e0; - unsigned long e1; - unsigned long e2; - unsigned long e3; - unsigned long e4; - unsigned long e5; - unsigned long e6; - unsigned long e7; - unsigned long lar; - unsigned long lir; - unsigned long mdr; - unsigned long mcvf; - unsigned long mcrl; - unsigned long mcrh; - unsigned long mdrq; - unsigned long sp; - unsigned long epsw; - unsigned long pc; - struct fpucontext *fpucontext; - unsigned long oldmask; -}; - - -#endif /* _ASM_SIGCONTEXT_H */ diff --git a/arch/mn10300/include/uapi/asm/signal.h b/arch/mn10300/include/uapi/asm/signal.h deleted file mode 100644 index 566cb199d5ac..000000000000 --- a/arch/mn10300/include/uapi/asm/signal.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 Signal definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _UAPI_ASM_SIGNAL_H -#define _UAPI_ASM_SIGNAL_H - -#include - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001U -#define SA_NOCLDWAIT 0x00000002U -#define SA_SIGINFO 0x00000004U -#define SA_ONSTACK 0x08000000U -#define SA_RESTART 0x10000000U -#define SA_NODEFER 0x40000000U -#define SA_RESETHAND 0x80000000U - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -#define SA_RESTORER 0x04000000 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void __user *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - - -#endif /* _UAPI_ASM_SIGNAL_H */ diff --git a/arch/mn10300/include/uapi/asm/socket.h b/arch/mn10300/include/uapi/asm/socket.h deleted file mode 100644 index b35eee132142..000000000000 --- a/arch/mn10300/include/uapi/asm/socket.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -#include - -/* For setsockopt(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -#define SO_REUSEPORT 15 -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 -#define SO_GET_FILTER SO_ATTACH_FILTER - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 - -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#define SO_MARK 36 - -#define SO_TIMESTAMPING 37 -#define SCM_TIMESTAMPING SO_TIMESTAMPING - -#define SO_PROTOCOL 38 -#define SO_DOMAIN 39 - -#define SO_RXQ_OVFL 40 - -#define SO_WIFI_STATUS 41 -#define SCM_WIFI_STATUS SO_WIFI_STATUS -#define SO_PEEK_OFF 42 - -/* Instruct lower device to use last 4-bytes of skb data as FCS */ -#define SO_NOFCS 43 - -#define SO_LOCK_FILTER 44 - -#define SO_SELECT_ERR_QUEUE 45 - -#define SO_BUSY_POLL 46 - -#define SO_MAX_PACING_RATE 47 - -#define SO_BPF_EXTENSIONS 48 - -#define SO_INCOMING_CPU 49 - -#define SO_ATTACH_BPF 50 -#define SO_DETACH_BPF SO_DETACH_FILTER - -#define SO_ATTACH_REUSEPORT_CBPF 51 -#define SO_ATTACH_REUSEPORT_EBPF 52 - -#define SO_CNX_ADVICE 53 - -#define SCM_TIMESTAMPING_OPT_STATS 54 - -#define SO_MEMINFO 55 - -#define SO_INCOMING_NAPI_ID 56 - -#define SO_COOKIE 57 - -#define SCM_TIMESTAMPING_PKTINFO 58 - -#define SO_PEERGROUPS 59 - -#define SO_ZEROCOPY 60 - -#endif /* _ASM_SOCKET_H */ diff --git a/arch/mn10300/include/uapi/asm/sockios.h b/arch/mn10300/include/uapi/asm/sockios.h deleted file mode 100644 index 5706baa3cd0d..000000000000 --- a/arch/mn10300/include/uapi/asm/sockios.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_SOCKIOS_H -#define _ASM_SOCKIOS_H - -/* Socket-level I/O control calls. */ -#define FIOSETOWN 0x8901 -#define SIOCSPGRP 0x8902 -#define FIOGETOWN 0x8903 -#define SIOCGPGRP 0x8904 -#define SIOCATMARK 0x8905 -#define SIOCGSTAMP 0x8906 /* Get stamp */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif /* _ASM_SOCKIOS_H */ diff --git a/arch/mn10300/include/uapi/asm/stat.h b/arch/mn10300/include/uapi/asm/stat.h deleted file mode 100644 index 769f5f8829d4..000000000000 --- a/arch/mn10300/include/uapi/asm/stat.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_STAT_H -#define _ASM_STAT_H - -struct __old_kernel_stat { - unsigned short st_dev; - unsigned short st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned long st_size; - unsigned long st_atime; - unsigned long st_mtime; - unsigned long st_ctime; -}; - -struct stat { - unsigned long st_dev; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned long st_rdev; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long st_atime_nsec; - unsigned long st_mtime; - unsigned long st_mtime_nsec; - unsigned long st_ctime; - unsigned long st_ctime_nsec; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad0[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad3[4]; - - long long st_size; - unsigned long st_blksize; - - unsigned long st_blocks; /* Number 512-byte blocks allocated. */ - unsigned long __pad4; /* future possible st_blocks high bits */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned int st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; - - unsigned long long st_ino; -}; - -#define STAT_HAVE_NSEC 1 - -#endif /* _ASM_STAT_H */ diff --git a/arch/mn10300/include/uapi/asm/statfs.h b/arch/mn10300/include/uapi/asm/statfs.h deleted file mode 100644 index 0b91fe198c20..000000000000 --- a/arch/mn10300/include/uapi/asm/statfs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/mn10300/include/uapi/asm/swab.h b/arch/mn10300/include/uapi/asm/swab.h deleted file mode 100644 index d2284dd27ad4..000000000000 --- a/arch/mn10300/include/uapi/asm/swab.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 Byte-order primitive construction - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_SWAB_H -#define _ASM_SWAB_H - -#include - -#ifdef __GNUC__ - -static inline __attribute__((const)) -__u32 __arch_swab32(__u32 x) -{ - __u32 ret; - asm("swap %1,%0" : "=r" (ret) : "r" (x)); - return ret; -} -#define __arch_swab32 __arch_swab32 - -static inline __attribute__((const)) -__u16 __arch_swab16(__u16 x) -{ - __u16 ret; - asm("swaph %1,%0" : "=r" (ret) : "r" (x)); - return ret; -} -#define __arch_swab32 __arch_swab32 - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#endif /* _ASM_SWAB_H */ diff --git a/arch/mn10300/include/uapi/asm/termbits.h b/arch/mn10300/include/uapi/asm/termbits.h deleted file mode 100644 index fca82ea2ca2c..000000000000 --- a/arch/mn10300/include/uapi/asm/termbits.h +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_TERMBITS_H -#define _ASM_TERMBITS_H - -#include - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 -#define B500000 0010005 -#define B576000 0010006 -#define B921600 0010007 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ -#define CTVB 004000000000 /* VisioBraille Terminal flow control */ -#define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ - -#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 -#define EXTPROC 0200000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif /* _ASM_TERMBITS_H */ diff --git a/arch/mn10300/include/uapi/asm/termios.h b/arch/mn10300/include/uapi/asm/termios.h deleted file mode 100644 index 25981aadb8cd..000000000000 --- a/arch/mn10300/include/uapi/asm/termios.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_ASM_TERMIOS_H -#define _UAPI_ASM_TERMIOS_H - -#include -#include - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -#define TIOCM_MODEM_BITS TIOCM_OUT2 /* IRDA support */ - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ - unsigned short __tmp; \ - get_user(__tmp, &(termio)->x); \ - *(unsigned short *) &(termios)->x = __tmp; \ -} - -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) \ - copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) \ - copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) \ - copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) \ - copy_to_user(u, k, sizeof(struct termios)) - -#endif /* _UAPI_ASM_TERMIOS_H */ diff --git a/arch/mn10300/include/uapi/asm/types.h b/arch/mn10300/include/uapi/asm/types.h deleted file mode 100644 index 7d2a697e2937..000000000000 --- a/arch/mn10300/include/uapi/asm/types.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 Basic type definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include diff --git a/arch/mn10300/include/uapi/asm/unistd.h b/arch/mn10300/include/uapi/asm/unistd.h deleted file mode 100644 index c0c96b650692..000000000000 --- a/arch/mn10300/include/uapi/asm/unistd.h +++ /dev/null @@ -1,355 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* MN10300 System call number list - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _UAPI_ASM_UNISTD_H -#define _UAPI_ASM_UNISTD_H - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */ -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86old 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 -#define __NR_vm86 166 -#define __NR_query_module 167 -#define __NR_poll 168 -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread64 180 -#define __NR_pwrite64 181 -#define __NR_chown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ -#define __NR_vfork 190 -#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_lchown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_chown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 -#define __NR_mincore 218 -#define __NR_madvise 219 -#define __NR_madvise1 219 /* delete when C lib stub is removed */ -#define __NR_getdents64 220 -#define __NR_fcntl64 221 -/* 223 is unused */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 -#define __NR_set_thread_area 243 -#define __NR_get_thread_area 244 -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 -#define __NR_fadvise64 250 - -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_epoll_create 254 -#define __NR_epoll_ctl 255 -#define __NR_epoll_wait 256 -#define __NR_remap_file_pages 257 -#define __NR_set_tid_address 258 -#define __NR_timer_create 259 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) -#define __NR_statfs64 268 -#define __NR_fstatfs64 269 -#define __NR_tgkill 270 -#define __NR_utimes 271 -#define __NR_fadvise64_64 272 -#define __NR_vserver 273 -#define __NR_mbind 274 -#define __NR_get_mempolicy 275 -#define __NR_set_mempolicy 276 -#define __NR_mq_open 277 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) -#define __NR_kexec_load 283 -#define __NR_waitid 284 -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_cacheflush 289 -#define __NR_ioprio_set 290 -#define __NR_ioprio_get 291 -#define __NR_inotify_init 292 -#define __NR_inotify_add_watch 293 -#define __NR_inotify_rm_watch 294 -#define __NR_migrate_pages 295 -#define __NR_openat 296 -#define __NR_mkdirat 297 -#define __NR_mknodat 298 -#define __NR_fchownat 299 -#define __NR_futimesat 300 -#define __NR_fstatat64 301 -#define __NR_unlinkat 302 -#define __NR_renameat 303 -#define __NR_linkat 304 -#define __NR_symlinkat 305 -#define __NR_readlinkat 306 -#define __NR_fchmodat 307 -#define __NR_faccessat 308 -#define __NR_pselect6 309 -#define __NR_ppoll 310 -#define __NR_unshare 311 -#define __NR_set_robust_list 312 -#define __NR_get_robust_list 313 -#define __NR_splice 314 -#define __NR_sync_file_range 315 -#define __NR_tee 316 -#define __NR_vmsplice 317 -#define __NR_move_pages 318 -#define __NR_getcpu 319 -#define __NR_epoll_pwait 320 -#define __NR_utimensat 321 -#define __NR_signalfd 322 -#define __NR_timerfd_create 323 -#define __NR_eventfd 324 -#define __NR_fallocate 325 -#define __NR_timerfd_settime 326 -#define __NR_timerfd_gettime 327 -#define __NR_signalfd4 328 -#define __NR_eventfd2 329 -#define __NR_epoll_create1 330 -#define __NR_dup3 331 -#define __NR_pipe2 332 -#define __NR_inotify_init1 333 -#define __NR_preadv 334 -#define __NR_pwritev 335 -#define __NR_rt_tgsigqueueinfo 336 -#define __NR_perf_event_open 337 -#define __NR_recvmmsg 338 -#define __NR_setns 339 - -#endif /* _UAPI_ASM_UNISTD_H */ diff --git a/arch/mn10300/kernel/Makefile b/arch/mn10300/kernel/Makefile deleted file mode 100644 index de32af0e4b6e..000000000000 --- a/arch/mn10300/kernel/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the MN10300-specific core kernel code -# -extra-y := head.o vmlinux.lds - -fpu-obj-y := fpu-nofpu.o fpu-nofpu-low.o -fpu-obj-$(CONFIG_FPU) := fpu.o fpu-low.o - -obj-y := process.o signal.o entry.o traps.o irq.o \ - ptrace.o setup.o time.o sys_mn10300.o io.o \ - switch_to.o mn10300_ksyms.o $(fpu-obj-y) \ - csrc-mn10300.o cevt-mn10300.o - -obj-$(CONFIG_SMP) += smp.o smp-low.o - -obj-$(CONFIG_MN10300_WD_TIMER) += mn10300-watchdog.o mn10300-watchdog-low.o - -obj-$(CONFIG_MN10300_TTYSM) += mn10300-serial.o mn10300-serial-low.o \ - mn10300-debug.o -obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-low.o -obj-$(CONFIG_GDBSTUB_ON_TTYSx) += gdb-io-serial.o gdb-io-serial-low.o -obj-$(CONFIG_GDBSTUB_ON_TTYSMx) += gdb-io-ttysm.o gdb-io-ttysm-low.o - -obj-$(CONFIG_MN10300_RTC) += rtc.o -obj-$(CONFIG_PROFILE) += profile.o profile-low.o -obj-$(CONFIG_MODULES) += module.o -obj-$(CONFIG_KPROBES) += kprobes.o -obj-$(CONFIG_KGDB) += kgdb.o diff --git a/arch/mn10300/kernel/asm-offsets.c b/arch/mn10300/kernel/asm-offsets.c deleted file mode 100644 index 57e6cc96267b..000000000000 --- a/arch/mn10300/kernel/asm-offsets.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed - * to extract and format the required data. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "sigframe.h" -#include "mn10300-serial.h" - -void foo(void) -{ - OFFSET(SIGCONTEXT_d0, sigcontext, d0); - OFFSET(SIGCONTEXT_d1, sigcontext, d1); - BLANK(); - - OFFSET(TI_task, thread_info, task); - OFFSET(TI_frame, thread_info, frame); - OFFSET(TI_flags, thread_info, flags); - OFFSET(TI_cpu, thread_info, cpu); - OFFSET(TI_preempt_count, thread_info, preempt_count); - OFFSET(TI_addr_limit, thread_info, addr_limit); - BLANK(); - - OFFSET(REG_D0, pt_regs, d0); - OFFSET(REG_D1, pt_regs, d1); - OFFSET(REG_D2, pt_regs, d2); - OFFSET(REG_D3, pt_regs, d3); - OFFSET(REG_A0, pt_regs, a0); - OFFSET(REG_A1, pt_regs, a1); - OFFSET(REG_A2, pt_regs, a2); - OFFSET(REG_A3, pt_regs, a3); - OFFSET(REG_E0, pt_regs, e0); - OFFSET(REG_E1, pt_regs, e1); - OFFSET(REG_E2, pt_regs, e2); - OFFSET(REG_E3, pt_regs, e3); - OFFSET(REG_E4, pt_regs, e4); - OFFSET(REG_E5, pt_regs, e5); - OFFSET(REG_E6, pt_regs, e6); - OFFSET(REG_E7, pt_regs, e7); - OFFSET(REG_SP, pt_regs, sp); - OFFSET(REG_EPSW, pt_regs, epsw); - OFFSET(REG_PC, pt_regs, pc); - OFFSET(REG_LAR, pt_regs, lar); - OFFSET(REG_LIR, pt_regs, lir); - OFFSET(REG_MDR, pt_regs, mdr); - OFFSET(REG_MCVF, pt_regs, mcvf); - OFFSET(REG_MCRL, pt_regs, mcrl); - OFFSET(REG_MCRH, pt_regs, mcrh); - OFFSET(REG_MDRQ, pt_regs, mdrq); - OFFSET(REG_ORIG_D0, pt_regs, orig_d0); - OFFSET(REG_NEXT, pt_regs, next); - DEFINE(REG__END, sizeof(struct pt_regs)); - BLANK(); - - OFFSET(THREAD_UREGS, thread_struct, uregs); - OFFSET(THREAD_PC, thread_struct, pc); - OFFSET(THREAD_SP, thread_struct, sp); - OFFSET(THREAD_A3, thread_struct, a3); - OFFSET(THREAD_USP, thread_struct, usp); -#ifdef CONFIG_FPU - OFFSET(THREAD_FPU_FLAGS, thread_struct, fpu_flags); - OFFSET(THREAD_FPU_STATE, thread_struct, fpu_state); - DEFINE(__THREAD_USING_FPU, THREAD_USING_FPU); - DEFINE(__THREAD_HAS_FPU, THREAD_HAS_FPU); -#endif /* CONFIG_FPU */ - BLANK(); - - OFFSET(TASK_THREAD, task_struct, thread); - BLANK(); - - DEFINE(CLONE_VM_asm, CLONE_VM); - DEFINE(CLONE_FS_asm, CLONE_FS); - DEFINE(CLONE_FILES_asm, CLONE_FILES); - DEFINE(CLONE_SIGHAND_asm, CLONE_SIGHAND); - DEFINE(CLONE_UNTRACED_asm, CLONE_UNTRACED); - DEFINE(SIGCHLD_asm, SIGCHLD); - BLANK(); - - OFFSET(RT_SIGFRAME_sigcontext, rt_sigframe, uc.uc_mcontext); - - DEFINE(PAGE_SIZE_asm, PAGE_SIZE); - - OFFSET(__rx_buffer, mn10300_serial_port, rx_buffer); - OFFSET(__rx_inp, mn10300_serial_port, rx_inp); - OFFSET(__rx_outp, mn10300_serial_port, rx_outp); - OFFSET(__uart_state, mn10300_serial_port, uart.state); - OFFSET(__tx_xchar, mn10300_serial_port, tx_xchar); - OFFSET(__tx_flags, mn10300_serial_port, tx_flags); - OFFSET(__intr_flags, mn10300_serial_port, intr_flags); - OFFSET(__rx_icr, mn10300_serial_port, rx_icr); - OFFSET(__tx_icr, mn10300_serial_port, tx_icr); - OFFSET(__tm_icr, mn10300_serial_port, _tmicr); - OFFSET(__iobase, mn10300_serial_port, _iobase); - - DEFINE(__UART_XMIT_SIZE, UART_XMIT_SIZE); - OFFSET(__xmit_buffer, uart_state, xmit.buf); - OFFSET(__xmit_head, uart_state, xmit.head); - OFFSET(__xmit_tail, uart_state, xmit.tail); -} diff --git a/arch/mn10300/kernel/cevt-mn10300.c b/arch/mn10300/kernel/cevt-mn10300.c deleted file mode 100644 index 2b21bbc9efa4..000000000000 --- a/arch/mn10300/kernel/cevt-mn10300.c +++ /dev/null @@ -1,137 +0,0 @@ -/* MN10300 clockevents - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by Mark Salter (msalter@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include "internal.h" - -#ifdef CONFIG_SMP -#if (CONFIG_NR_CPUS > 2) && !defined(CONFIG_GEENERIC_CLOCKEVENTS_BROADCAST) -#error "This doesn't scale well! Need per-core local timers." -#endif -#else /* CONFIG_SMP */ -#define stop_jiffies_counter1() -#define reload_jiffies_counter1(x) -#define TMJC1IRQ TMJCIRQ -#endif - - -static int next_event(unsigned long delta, - struct clock_event_device *evt) -{ - unsigned int cpu = smp_processor_id(); - - if (cpu == 0) { - stop_jiffies_counter(); - reload_jiffies_counter(delta - 1); - } else { - stop_jiffies_counter1(); - reload_jiffies_counter1(delta - 1); - } - return 0; -} - -static DEFINE_PER_CPU(struct clock_event_device, mn10300_clockevent_device); -static DEFINE_PER_CPU(struct irqaction, timer_irq); - -static irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *cd; - unsigned int cpu = smp_processor_id(); - - if (cpu == 0) - stop_jiffies_counter(); - else - stop_jiffies_counter1(); - - cd = &per_cpu(mn10300_clockevent_device, cpu); - cd->event_handler(cd); - - return IRQ_HANDLED; -} - -static void event_handler(struct clock_event_device *dev) -{ -} - -static inline void setup_jiffies_interrupt(int irq, - struct irqaction *action) -{ - u16 tmp; - setup_irq(irq, action); - set_intr_level(irq, NUM2GxICR_LEVEL(CONFIG_TIMER_IRQ_LEVEL)); - GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; - tmp = GxICR(irq); -} - -int __init init_clockevents(void) -{ - struct clock_event_device *cd; - struct irqaction *iact; - unsigned int cpu = smp_processor_id(); - - cd = &per_cpu(mn10300_clockevent_device, cpu); - - if (cpu == 0) { - stop_jiffies_counter(); - cd->irq = TMJCIRQ; - } else { - stop_jiffies_counter1(); - cd->irq = TMJC1IRQ; - } - - cd->name = "Timestamp"; - cd->features = CLOCK_EVT_FEAT_ONESHOT; - - /* Calculate shift/mult. We want to spawn at least 1 second */ - clockevents_calc_mult_shift(cd, MN10300_JCCLK, 1); - - /* Calculate the min / max delta */ - cd->max_delta_ns = clockevent_delta2ns(TMJCBR_MAX, cd); - cd->max_delta_ticks = TMJCBR_MAX; - cd->min_delta_ns = clockevent_delta2ns(100, cd); - cd->min_delta_ticks = 100; - - cd->rating = 200; - cd->cpumask = cpumask_of(smp_processor_id()); - cd->event_handler = event_handler; - cd->set_next_event = next_event; - - iact = &per_cpu(timer_irq, cpu); - iact->flags = IRQF_SHARED | IRQF_TIMER; - iact->handler = timer_interrupt; - - clockevents_register_device(cd); - -#if defined(CONFIG_SMP) && !defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) - /* setup timer irq affinity so it only runs on this cpu */ - { - struct irq_data *data; - data = irq_get_irq_data(cd->irq); - cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu)); - iact->flags |= IRQF_NOBALANCING; - } -#endif - - if (cpu == 0) { - reload_jiffies_counter(MN10300_JC_PER_HZ - 1); - iact->name = "CPU0 Timer"; - } else { - reload_jiffies_counter1(MN10300_JC_PER_HZ - 1); - iact->name = "CPU1 Timer"; - } - - setup_jiffies_interrupt(cd->irq, iact); - - return 0; -} diff --git a/arch/mn10300/kernel/csrc-mn10300.c b/arch/mn10300/kernel/csrc-mn10300.c deleted file mode 100644 index 6b74df3661f2..000000000000 --- a/arch/mn10300/kernel/csrc-mn10300.c +++ /dev/null @@ -1,34 +0,0 @@ -/* MN10300 clocksource - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by Mark Salter (msalter@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include "internal.h" - -static u64 mn10300_read(struct clocksource *cs) -{ - return read_timestamp_counter(); -} - -static struct clocksource clocksource_mn10300 = { - .name = "TSC", - .rating = 200, - .read = mn10300_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -int __init init_clocksource(void) -{ - startup_timestamp_counter(); - clocksource_register_hz(&clocksource_mn10300, MN10300_TSCCLK); - return 0; -} diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S deleted file mode 100644 index 177d61de51c9..000000000000 --- a/arch/mn10300/kernel/entry.S +++ /dev/null @@ -1,772 +0,0 @@ -############################################################################### -# -# MN10300 Exception and interrupt entry points -# -# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Modified by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SMP) && defined(CONFIG_GDBSTUB) -#include -#endif /* CONFIG_SMP && CONFIG_GDBSTUB */ - -#ifdef CONFIG_PREEMPT -#define preempt_stop LOCAL_IRQ_DISABLE -#else -#define preempt_stop -#define resume_kernel restore_all -#endif - - .am33_2 - -############################################################################### -# -# the return path for a forked child -# - on entry, D0 holds the address of the previous task to run -# -############################################################################### -ENTRY(ret_from_fork) - call schedule_tail[],0 - GET_THREAD_INFO a2 - - # return 0 to indicate child process - clr d0 - mov d0,(REG_D0,fp) - jmp syscall_exit - -ENTRY(ret_from_kernel_thread) - call schedule_tail[],0 - mov (REG_D0,fp),d0 - mov (REG_A0,fp),a0 - calls (a0) - GET_THREAD_INFO a2 # A2 must be set on return from sys_exit() - clr d0 - mov d0,(REG_D0,fp) - jmp syscall_exit - -############################################################################### -# -# system call handler -# -############################################################################### -ENTRY(system_call) - add -4,sp - SAVE_ALL - mov d0,(REG_ORIG_D0,fp) - GET_THREAD_INFO a2 - cmp nr_syscalls,d0 - bcc syscall_badsys - btst _TIF_SYSCALL_TRACE,(TI_flags,a2) - bne syscall_entry_trace -syscall_call: - add d0,d0,a1 - add a1,a1 - mov (REG_A0,fp),d0 - mov (sys_call_table,a1),a0 - calls (a0) - mov d0,(REG_D0,fp) -syscall_exit: - # make sure we don't miss an interrupt setting need_resched or - # sigpending between sampling and the rti - LOCAL_IRQ_DISABLE - mov (TI_flags,a2),d2 - btst _TIF_ALLWORK_MASK,d2 - bne syscall_exit_work -restore_all: - RESTORE_ALL - -############################################################################### -# -# perform work that needs to be done immediately before resumption and syscall -# tracing -# -############################################################################### - ALIGN -syscall_exit_work: - mov (REG_EPSW,fp),d0 - and EPSW_nSL,d0 - beq resume_kernel # returning to supervisor mode - - LOCAL_IRQ_ENABLE # could let syscall_trace_exit() call - # schedule() instead - btst _TIF_SYSCALL_TRACE,d2 - beq work_pending - mov fp,d0 - call syscall_trace_exit[],0 # do_syscall_trace(regs) - jmp resume_userspace - - ALIGN -work_pending: - btst _TIF_NEED_RESCHED,d2 - beq work_notifysig - -work_resched: - call schedule[],0 - -resume_userspace: - # make sure we don't miss an interrupt setting need_resched or - # sigpending between sampling and the rti - LOCAL_IRQ_DISABLE - - # is there any work to be done other than syscall tracing? - mov (TI_flags,a2),d2 - btst _TIF_WORK_MASK,d2 - beq restore_all - - LOCAL_IRQ_ENABLE - btst _TIF_NEED_RESCHED,d2 - bne work_resched - - # deal with pending signals and notify-resume requests -work_notifysig: - mov fp,d0 - mov d2,d1 - call do_notify_resume[],0 - jmp resume_userspace - - # perform syscall entry tracing -syscall_entry_trace: - mov -ENOSYS,d0 - mov d0,(REG_D0,fp) - mov fp,d0 - call syscall_trace_entry[],0 # returns the syscall number to actually use - mov (REG_D1,fp),d1 - cmp nr_syscalls,d0 - bcs syscall_call - jmp syscall_exit - -syscall_badsys: - mov -ENOSYS,d0 - mov d0,(REG_D0,fp) - jmp resume_userspace - - # userspace resumption stub bypassing syscall exit tracing - .globl ret_from_exception, ret_from_intr - ALIGN -ret_from_exception: - preempt_stop -ret_from_intr: - GET_THREAD_INFO a2 - mov (REG_EPSW,fp),d0 # need to deliver signals before - # returning to userspace - and EPSW_nSL,d0 - bne resume_userspace # returning to userspace - -#ifdef CONFIG_PREEMPT -resume_kernel: - LOCAL_IRQ_DISABLE - mov (TI_preempt_count,a2),d0 # non-zero preempt_count ? - cmp 0,d0 - bne restore_all - -need_resched: - btst _TIF_NEED_RESCHED,(TI_flags,a2) - beq restore_all - mov (REG_EPSW,fp),d0 - and EPSW_IM,d0 - cmp EPSW_IM_7,d0 # interrupts off (exception path) ? - bne restore_all - call preempt_schedule_irq[],0 - jmp need_resched -#else - jmp resume_kernel -#endif - - -############################################################################### -# -# IRQ handler entry point -# - intended to be entered at multiple priorities -# -############################################################################### -ENTRY(irq_handler) - add -4,sp - SAVE_ALL - - # it's not a syscall - mov 0xffffffff,d0 - mov d0,(REG_ORIG_D0,fp) - - mov fp,d0 - call do_IRQ[],0 # do_IRQ(regs) - - jmp ret_from_intr - -############################################################################### -# -# Double Fault handler entry point -# - note that there will not be a stack, D0/A0 will hold EPSW/PC as were -# -############################################################################### - .section .bss - .balign THREAD_SIZE - .space THREAD_SIZE -__df_stack: - .previous - -ENTRY(double_fault) - mov a0,(__df_stack-4) # PC as was - mov d0,(__df_stack-8) # EPSW as was - mn10300_set_dbfleds # display 'db-f' on the LEDs - mov 0xaa55aa55,d0 - mov d0,(__df_stack-12) # no ORIG_D0 - mov sp,a0 # save corrupted SP - mov __df_stack-12,sp # emergency supervisor stack - SAVE_ALL - mov a0,(REG_A0,fp) # save corrupted SP as A0 (which got - # clobbered by the CPU) - mov fp,d0 - calls do_double_fault -double_fault_loop: - bra double_fault_loop - -############################################################################### -# -# Bus Error handler entry point -# - handle external (async) bus errors separately -# -############################################################################### -ENTRY(raw_bus_error) - add -4,sp - mov d0,(sp) -#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR) - mov (MMUCTR),d0 - mov d0,(MMUCTR) -#endif - mov (BCBERR),d0 # what - btst BCBERR_BEMR_DMA,d0 # see if it was an external bus error - beq __common_exception_aux # it wasn't - - SAVE_ALL - mov (BCBEAR),d1 # destination of erroneous access - - mov (REG_ORIG_D0,fp),d2 - mov d2,(REG_D0,fp) - mov -1,d2 - mov d2,(REG_ORIG_D0,fp) - - add -4,sp - mov fp,(12,sp) # frame pointer - call io_bus_error[],0 - jmp restore_all - -############################################################################### -# -# NMI exception entry points -# -# This is used by ordinary interrupt channels that have the GxICR_NMI bit set -# in addition to the main NMI and Watchdog channels. SMP NMI IPIs use this -# facility. -# -############################################################################### -ENTRY(nmi_handler) - add -4,sp - mov d0,(sp) - mov (TBR),d0 - -#ifdef CONFIG_SMP - add -4,sp - mov d0,(sp) # save d0(TBR) - movhu (NMIAGR),d0 - and NMIAGR_GN,d0 - lsr 0x2,d0 - cmp CALL_FUNCTION_NMI_IPI,d0 - bne nmi_not_smp_callfunc # if not call function, jump - - # function call nmi ipi - add 4,sp # no need to store TBR - mov GxICR_DETECT,d0 # clear NMI request - movbu d0,(GxICR(CALL_FUNCTION_NMI_IPI)) - movhu (GxICR(CALL_FUNCTION_NMI_IPI)),d0 - and ~EPSW_NMID,epsw # enable NMI - - mov (sp),d0 # restore d0 - SAVE_ALL - call smp_nmi_call_function_interrupt[],0 - RESTORE_ALL - -nmi_not_smp_callfunc: -#ifdef CONFIG_KERNEL_DEBUGGER - cmp DEBUGGER_NMI_IPI,d0 - bne nmi_not_debugger # if not kernel debugger NMI IPI, jump - - # kernel debugger NMI IPI - add 4,sp # no need to store TBR - mov GxICR_DETECT,d0 # clear NMI - movbu d0,(GxICR(DEBUGGER_NMI_IPI)) - movhu (GxICR(DEBUGGER_NMI_IPI)),d0 - and ~EPSW_NMID,epsw # enable NMI - - mov (sp),d0 - SAVE_ALL - mov fp,d0 # arg 0: stacked register file - mov a2,d1 # arg 1: exception number - call debugger_nmi_interrupt[],0 - RESTORE_ALL - -nmi_not_debugger: -#endif /* CONFIG_KERNEL_DEBUGGER */ - mov (sp),d0 # restore TBR to d0 - add 4,sp -#endif /* CONFIG_SMP */ - - bra __common_exception_nonmi - -############################################################################### -# -# General exception entry point -# -############################################################################### -ENTRY(__common_exception) - add -4,sp - mov d0,(sp) -#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR) - mov (MMUCTR),d0 - mov d0,(MMUCTR) -#endif - -__common_exception_aux: - mov (TBR),d0 - and ~EPSW_NMID,epsw # turn NMIs back on if not NMI - or EPSW_IE,epsw - -__common_exception_nonmi: - and 0x0000FFFF,d0 # turn the exception code into a vector - # table index - - btst 0x00000007,d0 - bne 1f - cmp 0x00000400,d0 - bge 1f - - SAVE_ALL # build the stack frame - - mov (REG_D0,fp),a2 # get the exception number - mov (REG_ORIG_D0,fp),d0 - mov d0,(REG_D0,fp) - mov -1,d0 - mov d0,(REG_ORIG_D0,fp) - -#ifdef CONFIG_GDBSTUB -#ifdef CONFIG_SMP - call gdbstub_busy_check[],0 - and d0,d0 # check return value - beq 2f -#else /* CONFIG_SMP */ - btst 0x01,(gdbstub_busy) - beq 2f -#endif /* CONFIG_SMP */ - and ~EPSW_IE,epsw - mov fp,d0 - mov a2,d1 - call gdbstub_exception[],0 # gdbstub itself caused an exception - bra restore_all -2: -#endif /* CONFIG_GDBSTUB */ - - mov fp,d0 # arg 0: stacked register file - mov a2,d1 # arg 1: exception number - lsr 1,a2 - - mov (exception_table,a2),a2 - calls (a2) - jmp ret_from_exception - -1: pi # BUG() equivalent - -############################################################################### -# -# Exception handler functions table -# -############################################################################### - .data -ENTRY(exception_table) - .rept 0x400>>1 - .long uninitialised_exception - .endr - .previous - -############################################################################### -# -# Change an entry in the exception table -# - D0 exception code, D1 handler -# -############################################################################### -ENTRY(set_excp_vector) - lsr 1,d0 - add exception_table,d0 - mov d1,(d0) - mov 4,d1 - ret [],0 - -############################################################################### -# -# System call table -# -############################################################################### - .data -ENTRY(sys_call_table) - .long sys_restart_syscall /* 0 */ - .long sys_exit - .long sys_fork - .long sys_read - .long sys_write - .long sys_open /* 5 */ - .long sys_close - .long sys_waitpid - .long sys_creat - .long sys_link - .long sys_unlink /* 10 */ - .long sys_execve - .long sys_chdir - .long sys_time - .long sys_mknod - .long sys_chmod /* 15 */ - .long sys_lchown16 - .long sys_ni_syscall /* old break syscall holder */ - .long sys_stat - .long sys_lseek - .long sys_getpid /* 20 */ - .long sys_mount - .long sys_oldumount - .long sys_setuid16 - .long sys_getuid16 - .long sys_stime /* 25 */ - .long sys_ptrace - .long sys_alarm - .long sys_fstat - .long sys_pause - .long sys_utime /* 30 */ - .long sys_ni_syscall /* old stty syscall holder */ - .long sys_ni_syscall /* old gtty syscall holder */ - .long sys_access - .long sys_nice - .long sys_ni_syscall /* 35 - old ftime syscall holder */ - .long sys_sync - .long sys_kill - .long sys_rename - .long sys_mkdir - .long sys_rmdir /* 40 */ - .long sys_dup - .long sys_pipe - .long sys_times - .long sys_ni_syscall /* old prof syscall holder */ - .long sys_brk /* 45 */ - .long sys_setgid16 - .long sys_getgid16 - .long sys_signal - .long sys_geteuid16 - .long sys_getegid16 /* 50 */ - .long sys_acct - .long sys_umount /* recycled never used phys() */ - .long sys_ni_syscall /* old lock syscall holder */ - .long sys_ioctl - .long sys_fcntl /* 55 */ - .long sys_ni_syscall /* old mpx syscall holder */ - .long sys_setpgid - .long sys_ni_syscall /* old ulimit syscall holder */ - .long sys_ni_syscall /* old sys_olduname */ - .long sys_umask /* 60 */ - .long sys_chroot - .long sys_ustat - .long sys_dup2 - .long sys_getppid - .long sys_getpgrp /* 65 */ - .long sys_setsid - .long sys_sigaction - .long sys_sgetmask - .long sys_ssetmask - .long sys_setreuid16 /* 70 */ - .long sys_setregid16 - .long sys_sigsuspend - .long sys_sigpending - .long sys_sethostname - .long sys_setrlimit /* 75 */ - .long sys_old_getrlimit - .long sys_getrusage - .long sys_gettimeofday - .long sys_settimeofday - .long sys_getgroups16 /* 80 */ - .long sys_setgroups16 - .long sys_old_select - .long sys_symlink - .long sys_lstat - .long sys_readlink /* 85 */ - .long sys_uselib - .long sys_swapon - .long sys_reboot - .long sys_old_readdir - .long old_mmap /* 90 */ - .long sys_munmap - .long sys_truncate - .long sys_ftruncate - .long sys_fchmod - .long sys_fchown16 /* 95 */ - .long sys_getpriority - .long sys_setpriority - .long sys_ni_syscall /* old profil syscall holder */ - .long sys_statfs - .long sys_fstatfs /* 100 */ - .long sys_ni_syscall /* ioperm */ - .long sys_socketcall - .long sys_syslog - .long sys_setitimer - .long sys_getitimer /* 105 */ - .long sys_newstat - .long sys_newlstat - .long sys_newfstat - .long sys_ni_syscall /* old sys_uname */ - .long sys_ni_syscall /* 110 - iopl */ - .long sys_vhangup - .long sys_ni_syscall /* old "idle" system call */ - .long sys_ni_syscall /* vm86old */ - .long sys_wait4 - .long sys_swapoff /* 115 */ - .long sys_sysinfo - .long sys_ipc - .long sys_fsync - .long sys_sigreturn - .long sys_clone /* 120 */ - .long sys_setdomainname - .long sys_newuname - .long sys_ni_syscall /* modify_ldt */ - .long sys_adjtimex - .long sys_mprotect /* 125 */ - .long sys_sigprocmask - .long sys_ni_syscall /* old "create_module" */ - .long sys_init_module - .long sys_delete_module - .long sys_ni_syscall /* 130: old "get_kernel_syms" */ - .long sys_quotactl - .long sys_getpgid - .long sys_fchdir - .long sys_bdflush - .long sys_sysfs /* 135 */ - .long sys_personality - .long sys_ni_syscall /* reserved for afs_syscall */ - .long sys_setfsuid16 - .long sys_setfsgid16 - .long sys_llseek /* 140 */ - .long sys_getdents - .long sys_select - .long sys_flock - .long sys_msync - .long sys_readv /* 145 */ - .long sys_writev - .long sys_getsid - .long sys_fdatasync - .long sys_sysctl - .long sys_mlock /* 150 */ - .long sys_munlock - .long sys_mlockall - .long sys_munlockall - .long sys_sched_setparam - .long sys_sched_getparam /* 155 */ - .long sys_sched_setscheduler - .long sys_sched_getscheduler - .long sys_sched_yield - .long sys_sched_get_priority_max - .long sys_sched_get_priority_min /* 160 */ - .long sys_sched_rr_get_interval - .long sys_nanosleep - .long sys_mremap - .long sys_setresuid16 - .long sys_getresuid16 /* 165 */ - .long sys_ni_syscall /* vm86 */ - .long sys_ni_syscall /* Old sys_query_module */ - .long sys_poll - .long sys_ni_syscall /* was nfsservctl */ - .long sys_setresgid16 /* 170 */ - .long sys_getresgid16 - .long sys_prctl - .long sys_rt_sigreturn - .long sys_rt_sigaction - .long sys_rt_sigprocmask /* 175 */ - .long sys_rt_sigpending - .long sys_rt_sigtimedwait - .long sys_rt_sigqueueinfo - .long sys_rt_sigsuspend - .long sys_pread64 /* 180 */ - .long sys_pwrite64 - .long sys_chown16 - .long sys_getcwd - .long sys_capget - .long sys_capset /* 185 */ - .long sys_sigaltstack - .long sys_sendfile - .long sys_ni_syscall /* reserved for streams1 */ - .long sys_ni_syscall /* reserved for streams2 */ - .long sys_vfork /* 190 */ - .long sys_getrlimit - .long sys_mmap_pgoff - .long sys_truncate64 - .long sys_ftruncate64 - .long sys_stat64 /* 195 */ - .long sys_lstat64 - .long sys_fstat64 - .long sys_lchown - .long sys_getuid - .long sys_getgid /* 200 */ - .long sys_geteuid - .long sys_getegid - .long sys_setreuid - .long sys_setregid - .long sys_getgroups /* 205 */ - .long sys_setgroups - .long sys_fchown - .long sys_setresuid - .long sys_getresuid - .long sys_setresgid /* 210 */ - .long sys_getresgid - .long sys_chown - .long sys_setuid - .long sys_setgid - .long sys_setfsuid /* 215 */ - .long sys_setfsgid - .long sys_pivot_root - .long sys_mincore - .long sys_madvise - .long sys_getdents64 /* 220 */ - .long sys_fcntl64 - .long sys_ni_syscall /* reserved for TUX */ - .long sys_ni_syscall - .long sys_gettid - .long sys_readahead /* 225 */ - .long sys_setxattr - .long sys_lsetxattr - .long sys_fsetxattr - .long sys_getxattr - .long sys_lgetxattr /* 230 */ - .long sys_fgetxattr - .long sys_listxattr - .long sys_llistxattr - .long sys_flistxattr - .long sys_removexattr /* 235 */ - .long sys_lremovexattr - .long sys_fremovexattr - .long sys_tkill - .long sys_sendfile64 - .long sys_futex /* 240 */ - .long sys_sched_setaffinity - .long sys_sched_getaffinity - .long sys_ni_syscall /* sys_set_thread_area */ - .long sys_ni_syscall /* sys_get_thread_area */ - .long sys_io_setup /* 245 */ - .long sys_io_destroy - .long sys_io_getevents - .long sys_io_submit - .long sys_io_cancel - .long sys_fadvise64 /* 250 */ - .long sys_ni_syscall - .long sys_exit_group - .long sys_lookup_dcookie - .long sys_epoll_create - .long sys_epoll_ctl /* 255 */ - .long sys_epoll_wait - .long sys_remap_file_pages - .long sys_set_tid_address - .long sys_timer_create - .long sys_timer_settime /* 260 */ - .long sys_timer_gettime - .long sys_timer_getoverrun - .long sys_timer_delete - .long sys_clock_settime - .long sys_clock_gettime /* 265 */ - .long sys_clock_getres - .long sys_clock_nanosleep - .long sys_statfs64 - .long sys_fstatfs64 - .long sys_tgkill /* 270 */ - .long sys_utimes - .long sys_fadvise64_64 - .long sys_ni_syscall /* sys_vserver */ - .long sys_mbind - .long sys_get_mempolicy /* 275 */ - .long sys_set_mempolicy - .long sys_mq_open - .long sys_mq_unlink - .long sys_mq_timedsend - .long sys_mq_timedreceive /* 280 */ - .long sys_mq_notify - .long sys_mq_getsetattr - .long sys_kexec_load - .long sys_waitid - .long sys_ni_syscall /* 285 */ /* available */ - .long sys_add_key - .long sys_request_key - .long sys_keyctl - .long sys_cacheflush - .long sys_ioprio_set /* 290 */ - .long sys_ioprio_get - .long sys_inotify_init - .long sys_inotify_add_watch - .long sys_inotify_rm_watch - .long sys_migrate_pages /* 295 */ - .long sys_openat - .long sys_mkdirat - .long sys_mknodat - .long sys_fchownat - .long sys_futimesat /* 300 */ - .long sys_fstatat64 - .long sys_unlinkat - .long sys_renameat - .long sys_linkat - .long sys_symlinkat /* 305 */ - .long sys_readlinkat - .long sys_fchmodat - .long sys_faccessat - .long sys_pselect6 - .long sys_ppoll /* 310 */ - .long sys_unshare - .long sys_set_robust_list - .long sys_get_robust_list - .long sys_splice - .long sys_sync_file_range /* 315 */ - .long sys_tee - .long sys_vmsplice - .long sys_move_pages - .long sys_getcpu - .long sys_epoll_pwait /* 320 */ - .long sys_utimensat - .long sys_signalfd - .long sys_timerfd_create - .long sys_eventfd - .long sys_fallocate /* 325 */ - .long sys_timerfd_settime - .long sys_timerfd_gettime - .long sys_signalfd4 - .long sys_eventfd2 - .long sys_epoll_create1 /* 330 */ - .long sys_dup3 - .long sys_pipe2 - .long sys_inotify_init1 - .long sys_preadv - .long sys_pwritev /* 335 */ - .long sys_rt_tgsigqueueinfo - .long sys_perf_event_open - .long sys_recvmmsg - .long sys_setns - - -nr_syscalls=(.-sys_call_table)/4 diff --git a/arch/mn10300/kernel/fpu-low.S b/arch/mn10300/kernel/fpu-low.S deleted file mode 100644 index 78df25cfae29..000000000000 --- a/arch/mn10300/kernel/fpu-low.S +++ /dev/null @@ -1,258 +0,0 @@ -/* MN10300 Low level FPU management operations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include - -.macro FPU_INIT_STATE_ALL - fmov 0,fs0 - fmov fs0,fs1 - fmov fs0,fs2 - fmov fs0,fs3 - fmov fs0,fs4 - fmov fs0,fs5 - fmov fs0,fs6 - fmov fs0,fs7 - fmov fs0,fs8 - fmov fs0,fs9 - fmov fs0,fs10 - fmov fs0,fs11 - fmov fs0,fs12 - fmov fs0,fs13 - fmov fs0,fs14 - fmov fs0,fs15 - fmov fs0,fs16 - fmov fs0,fs17 - fmov fs0,fs18 - fmov fs0,fs19 - fmov fs0,fs20 - fmov fs0,fs21 - fmov fs0,fs22 - fmov fs0,fs23 - fmov fs0,fs24 - fmov fs0,fs25 - fmov fs0,fs26 - fmov fs0,fs27 - fmov fs0,fs28 - fmov fs0,fs29 - fmov fs0,fs30 - fmov fs0,fs31 - fmov FPCR_INIT,fpcr -.endm - -.macro FPU_SAVE_ALL areg,dreg - fmov fs0,(\areg+) - fmov fs1,(\areg+) - fmov fs2,(\areg+) - fmov fs3,(\areg+) - fmov fs4,(\areg+) - fmov fs5,(\areg+) - fmov fs6,(\areg+) - fmov fs7,(\areg+) - fmov fs8,(\areg+) - fmov fs9,(\areg+) - fmov fs10,(\areg+) - fmov fs11,(\areg+) - fmov fs12,(\areg+) - fmov fs13,(\areg+) - fmov fs14,(\areg+) - fmov fs15,(\areg+) - fmov fs16,(\areg+) - fmov fs17,(\areg+) - fmov fs18,(\areg+) - fmov fs19,(\areg+) - fmov fs20,(\areg+) - fmov fs21,(\areg+) - fmov fs22,(\areg+) - fmov fs23,(\areg+) - fmov fs24,(\areg+) - fmov fs25,(\areg+) - fmov fs26,(\areg+) - fmov fs27,(\areg+) - fmov fs28,(\areg+) - fmov fs29,(\areg+) - fmov fs30,(\areg+) - fmov fs31,(\areg+) - fmov fpcr,\dreg - mov \dreg,(\areg) -.endm - -.macro FPU_RESTORE_ALL areg,dreg - fmov (\areg+),fs0 - fmov (\areg+),fs1 - fmov (\areg+),fs2 - fmov (\areg+),fs3 - fmov (\areg+),fs4 - fmov (\areg+),fs5 - fmov (\areg+),fs6 - fmov (\areg+),fs7 - fmov (\areg+),fs8 - fmov (\areg+),fs9 - fmov (\areg+),fs10 - fmov (\areg+),fs11 - fmov (\areg+),fs12 - fmov (\areg+),fs13 - fmov (\areg+),fs14 - fmov (\areg+),fs15 - fmov (\areg+),fs16 - fmov (\areg+),fs17 - fmov (\areg+),fs18 - fmov (\areg+),fs19 - fmov (\areg+),fs20 - fmov (\areg+),fs21 - fmov (\areg+),fs22 - fmov (\areg+),fs23 - fmov (\areg+),fs24 - fmov (\areg+),fs25 - fmov (\areg+),fs26 - fmov (\areg+),fs27 - fmov (\areg+),fs28 - fmov (\areg+),fs29 - fmov (\areg+),fs30 - fmov (\areg+),fs31 - mov (\areg),\dreg - fmov \dreg,fpcr -.endm - -############################################################################### -# -# void fpu_init_state(void) -# - initialise the FPU -# -############################################################################### - .globl fpu_init_state - .type fpu_init_state,@function -fpu_init_state: - mov epsw,d0 - or EPSW_FE,epsw - -#ifdef CONFIG_MN10300_PROC_MN103E010 - nop - nop - nop -#endif - FPU_INIT_STATE_ALL -#ifdef CONFIG_MN10300_PROC_MN103E010 - nop - nop - nop -#endif - mov d0,epsw - ret [],0 - - .size fpu_init_state,.-fpu_init_state - -############################################################################### -# -# void fpu_save(struct fpu_state_struct *) -# - save the fpu state -# - note that an FPU Operational exception might occur during this process -# -############################################################################### - .globl fpu_save - .type fpu_save,@function -fpu_save: - mov epsw,d1 - or EPSW_FE,epsw /* enable the FPU so we can access it */ - -#ifdef CONFIG_MN10300_PROC_MN103E010 - nop - nop -#endif - mov d0,a0 - FPU_SAVE_ALL a0,d0 -#ifdef CONFIG_MN10300_PROC_MN103E010 - nop - nop -#endif - - mov d1,epsw - ret [],0 - - .size fpu_save,.-fpu_save - -############################################################################### -# -# void fpu_disabled(void) -# - handle an exception due to the FPU being disabled -# when CONFIG_FPU is enabled -# -############################################################################### - .type fpu_disabled,@function - .globl fpu_disabled -fpu_disabled: - or EPSW_nAR|EPSW_FE,epsw - nop - nop - nop - - mov sp,a1 - mov (a1),d1 /* get epsw of user context */ - and ~(THREAD_SIZE-1),a1 /* a1: (thread_info *ti) */ - mov (TI_task,a1),a2 /* a2: (task_struct *tsk) */ - btst EPSW_nSL,d1 - beq fpu_used_in_kernel - - or EPSW_FE,d1 - mov d1,(sp) - mov (TASK_THREAD+THREAD_FPU_FLAGS,a2),d1 -#ifndef CONFIG_LAZY_SAVE_FPU - or __THREAD_HAS_FPU,d1 - mov d1,(TASK_THREAD+THREAD_FPU_FLAGS,a2) -#else /* !CONFIG_LAZY_SAVE_FPU */ - mov (fpu_state_owner),a0 - cmp 0,a0 - beq fpu_regs_save_end - - mov (TASK_THREAD+THREAD_UREGS,a0),a1 - add TASK_THREAD+THREAD_FPU_STATE,a0 - FPU_SAVE_ALL a0,d0 - - mov (REG_EPSW,a1),d0 - and ~EPSW_FE,d0 - mov d0,(REG_EPSW,a1) - -fpu_regs_save_end: - mov a2,(fpu_state_owner) -#endif /* !CONFIG_LAZY_SAVE_FPU */ - - btst __THREAD_USING_FPU,d1 - beq fpu_regs_init - add TASK_THREAD+THREAD_FPU_STATE,a2 - FPU_RESTORE_ALL a2,d0 - rti - -fpu_regs_init: - FPU_INIT_STATE_ALL - add TASK_THREAD+THREAD_FPU_FLAGS,a2 - bset __THREAD_USING_FPU,(0,a2) - rti - -fpu_used_in_kernel: - and ~(EPSW_nAR|EPSW_FE),epsw - nop - nop - - add -4,sp - SAVE_ALL - mov -1,d0 - mov d0,(REG_ORIG_D0,fp) - - and ~EPSW_NMID,epsw - - mov fp,d0 - call fpu_disabled_in_kernel[],0 - jmp ret_from_exception - - .size fpu_disabled,.-fpu_disabled diff --git a/arch/mn10300/kernel/fpu-nofpu-low.S b/arch/mn10300/kernel/fpu-nofpu-low.S deleted file mode 100644 index 7ea087a549f4..000000000000 --- a/arch/mn10300/kernel/fpu-nofpu-low.S +++ /dev/null @@ -1,39 +0,0 @@ -/* MN10300 Low level FPU management operations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include - -############################################################################### -# -# void fpu_disabled(void) -# - handle an exception due to the FPU being disabled -# when CONFIG_FPU is disabled -# -############################################################################### - .type fpu_disabled,@function - .globl fpu_disabled -fpu_disabled: - add -4,sp - SAVE_ALL - mov -1,d0 - mov d0,(REG_ORIG_D0,fp) - - and ~EPSW_NMID,epsw - - mov fp,d0 - call unexpected_fpu_exception[],0 - jmp ret_from_exception - - .size fpu_disabled,.-fpu_disabled diff --git a/arch/mn10300/kernel/fpu-nofpu.c b/arch/mn10300/kernel/fpu-nofpu.c deleted file mode 100644 index 8d0e041aa798..000000000000 --- a/arch/mn10300/kernel/fpu-nofpu.c +++ /dev/null @@ -1,31 +0,0 @@ -/* MN10300 FPU management - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include - -/* - * handle an FPU operational exception - * - there's a possibility that if the FPU is asynchronous, the signal might - * be meant for a process other than the current one - */ -asmlinkage -void unexpected_fpu_exception(struct pt_regs *regs, enum exception_code code) -{ - panic("An FPU exception was received, but there's no FPU enabled."); -} - -/* - * fill in the FPU structure for a core dump - */ -int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpreg) -{ - return 0; /* not valid */ -} diff --git a/arch/mn10300/kernel/fpu.c b/arch/mn10300/kernel/fpu.c deleted file mode 100644 index 50ce7b447fed..000000000000 --- a/arch/mn10300/kernel/fpu.c +++ /dev/null @@ -1,177 +0,0 @@ -/* MN10300 FPU management - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include - -#include -#include -#include - -#ifdef CONFIG_LAZY_SAVE_FPU -struct task_struct *fpu_state_owner; -#endif - -/* - * error functions in FPU disabled exception - */ -asmlinkage void fpu_disabled_in_kernel(struct pt_regs *regs) -{ - die_if_no_fixup("An FPU Disabled exception happened in kernel space\n", - regs, EXCEP_FPU_DISABLED); -} - -/* - * handle an FPU operational exception - * - there's a possibility that if the FPU is asynchronous, the signal might - * be meant for a process other than the current one - */ -asmlinkage void fpu_exception(struct pt_regs *regs, enum exception_code code) -{ - struct task_struct *tsk = current; - siginfo_t info; - u32 fpcr; - - if (!user_mode(regs)) - die_if_no_fixup("An FPU Operation exception happened in" - " kernel space\n", - regs, code); - - if (!is_using_fpu(tsk)) - die_if_no_fixup("An FPU Operation exception happened," - " but the FPU is not in use", - regs, code); - - info.si_signo = SIGFPE; - info.si_errno = 0; - info.si_addr = (void *) tsk->thread.uregs->pc; - info.si_code = FPE_FLTINV; - - unlazy_fpu(tsk); - - fpcr = tsk->thread.fpu_state.fpcr; - - if (fpcr & FPCR_EC_Z) - info.si_code = FPE_FLTDIV; - else if (fpcr & FPCR_EC_O) - info.si_code = FPE_FLTOVF; - else if (fpcr & FPCR_EC_U) - info.si_code = FPE_FLTUND; - else if (fpcr & FPCR_EC_I) - info.si_code = FPE_FLTRES; - - force_sig_info(SIGFPE, &info, tsk); -} - -/* - * save the FPU state to a signal context - */ -int fpu_setup_sigcontext(struct fpucontext *fpucontext) -{ - struct task_struct *tsk = current; - - if (!is_using_fpu(tsk)) - return 0; - - /* transfer the current FPU state to memory and cause fpu_init() to be - * triggered by the next attempted FPU operation by the current - * process. - */ - preempt_disable(); - -#ifndef CONFIG_LAZY_SAVE_FPU - if (tsk->thread.fpu_flags & THREAD_HAS_FPU) { - fpu_save(&tsk->thread.fpu_state); - tsk->thread.uregs->epsw &= ~EPSW_FE; - tsk->thread.fpu_flags &= ~THREAD_HAS_FPU; - } -#else /* !CONFIG_LAZY_SAVE_FPU */ - if (fpu_state_owner == tsk) { - fpu_save(&tsk->thread.fpu_state); - fpu_state_owner->thread.uregs->epsw &= ~EPSW_FE; - fpu_state_owner = NULL; - } -#endif /* !CONFIG_LAZY_SAVE_FPU */ - - preempt_enable(); - - /* we no longer have a valid current FPU state */ - clear_using_fpu(tsk); - - /* transfer the saved FPU state onto the userspace stack */ - if (copy_to_user(fpucontext, - &tsk->thread.fpu_state, - min(sizeof(struct fpu_state_struct), - sizeof(struct fpucontext)))) - return -1; - - return 1; -} - -/* - * kill a process's FPU state during restoration after signal handling - */ -void fpu_kill_state(struct task_struct *tsk) -{ - /* disown anything left in the FPU */ - preempt_disable(); - -#ifndef CONFIG_LAZY_SAVE_FPU - if (tsk->thread.fpu_flags & THREAD_HAS_FPU) { - tsk->thread.uregs->epsw &= ~EPSW_FE; - tsk->thread.fpu_flags &= ~THREAD_HAS_FPU; - } -#else /* !CONFIG_LAZY_SAVE_FPU */ - if (fpu_state_owner == tsk) { - fpu_state_owner->thread.uregs->epsw &= ~EPSW_FE; - fpu_state_owner = NULL; - } -#endif /* !CONFIG_LAZY_SAVE_FPU */ - - preempt_enable(); - - /* we no longer have a valid current FPU state */ - clear_using_fpu(tsk); -} - -/* - * restore the FPU state from a signal context - */ -int fpu_restore_sigcontext(struct fpucontext *fpucontext) -{ - struct task_struct *tsk = current; - int ret; - - /* load up the old FPU state */ - ret = copy_from_user(&tsk->thread.fpu_state, fpucontext, - min(sizeof(struct fpu_state_struct), - sizeof(struct fpucontext))); - if (!ret) - set_using_fpu(tsk); - - return ret; -} - -/* - * fill in the FPU structure for a core dump - */ -int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpreg) -{ - struct task_struct *tsk = current; - int fpvalid; - - fpvalid = is_using_fpu(tsk); - if (fpvalid) { - unlazy_fpu(tsk); - memcpy(fpreg, &tsk->thread.fpu_state, sizeof(*fpreg)); - } - - return fpvalid; -} diff --git a/arch/mn10300/kernel/gdb-io-serial-low.S b/arch/mn10300/kernel/gdb-io-serial-low.S deleted file mode 100644 index b1d0152e96cb..000000000000 --- a/arch/mn10300/kernel/gdb-io-serial-low.S +++ /dev/null @@ -1,91 +0,0 @@ -############################################################################### -# -# 16550 serial Rx interrupt handler for gdbstub I/O -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include -#include -#include -#include - - .text - -############################################################################### -# -# GDB stub serial receive interrupt entry point -# - intended to run at interrupt priority 0 -# -############################################################################### - .globl gdbstub_io_rx_handler - .type gdbstub_io_rx_handler,@function -gdbstub_io_rx_handler: - movm [d2,d3,a2,a3],(sp) - -#if 1 - movbu (GDBPORT_SERIAL_IIR),d2 -#endif - - mov (gdbstub_rx_inp),a3 -gdbstub_io_rx_more: - mov a3,a2 - add 2,a3 - and 0x00000fff,a3 - mov (gdbstub_rx_outp),d3 - cmp a3,d3 - beq gdbstub_io_rx_overflow - - movbu (GDBPORT_SERIAL_LSR),d3 - btst UART_LSR_DR,d3 - beq gdbstub_io_rx_done - movbu (GDBPORT_SERIAL_RX),d2 - movbu d3,(gdbstub_rx_buffer+1,a2) - movbu d2,(gdbstub_rx_buffer,a2) - mov a3,(gdbstub_rx_inp) - bra gdbstub_io_rx_more - -gdbstub_io_rx_done: - mov GxICR_DETECT,d2 - movbu d2,(XIRQxICR(GDBPORT_SERIAL_IRQ)) # ACK the interrupt - movhu (XIRQxICR(GDBPORT_SERIAL_IRQ)),d2 # flush - movm (sp),[d2,d3,a2,a3] - bset 0x01,(gdbstub_busy) - beq gdbstub_io_rx_enter - rti - -gdbstub_io_rx_overflow: - bset 0x01,(gdbstub_rx_overflow) - bra gdbstub_io_rx_done - -gdbstub_io_rx_enter: - LOCAL_CHANGE_INTR_MASK_LEVEL(NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL+1)) - add -4,sp - SAVE_ALL - - mov 0xffffffff,d0 - mov d0,(REG_ORIG_D0,fp) - mov 0x280,d1 - - mov fp,d0 - call gdbstub_rx_irq[],0 # gdbstub_rx_irq(regs,excep) - - LOCAL_CLI - bclr 0x01,(gdbstub_busy) - - .globl gdbstub_return -gdbstub_return: - RESTORE_ALL - - .size gdbstub_io_rx_handler,.-gdbstub_io_rx_handler diff --git a/arch/mn10300/kernel/gdb-io-serial.c b/arch/mn10300/kernel/gdb-io-serial.c deleted file mode 100644 index df51242744cc..000000000000 --- a/arch/mn10300/kernel/gdb-io-serial.c +++ /dev/null @@ -1,174 +0,0 @@ -/* 16550 serial driver for gdbstub I/O - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* - * initialise the GDB stub - */ -void gdbstub_io_init(void) -{ - u16 tmp; - - /* set up the serial port */ - GDBPORT_SERIAL_LCR = UART_LCR_WLEN8; /* 1N8 */ - GDBPORT_SERIAL_FCR = (UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT); - - FLOWCTL_CLEAR(DTR); - FLOWCTL_SET(RTS); - - gdbstub_io_set_baud(115200); - - /* we want to get serial receive interrupts */ - XIRQxICR(GDBPORT_SERIAL_IRQ) = 0; - tmp = XIRQxICR(GDBPORT_SERIAL_IRQ); - -#if CONFIG_GDBSTUB_IRQ_LEVEL == 0 - IVAR0 = EXCEP_IRQ_LEVEL0; -#elif CONFIG_GDBSTUB_IRQ_LEVEL == 1 - IVAR1 = EXCEP_IRQ_LEVEL1; -#elif CONFIG_GDBSTUB_IRQ_LEVEL == 2 - IVAR2 = EXCEP_IRQ_LEVEL2; -#elif CONFIG_GDBSTUB_IRQ_LEVEL == 3 - IVAR3 = EXCEP_IRQ_LEVEL3; -#elif CONFIG_GDBSTUB_IRQ_LEVEL == 4 - IVAR4 = EXCEP_IRQ_LEVEL4; -#elif CONFIG_GDBSTUB_IRQ_LEVEL == 5 - IVAR5 = EXCEP_IRQ_LEVEL5; -#else -#error "Unknown irq level for gdbstub." -#endif - - set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL), - gdbstub_io_rx_handler); - - XIRQxICR(GDBPORT_SERIAL_IRQ) &= ~GxICR_REQUEST; - XIRQxICR(GDBPORT_SERIAL_IRQ) = - GxICR_ENABLE | NUM2GxICR_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL); - tmp = XIRQxICR(GDBPORT_SERIAL_IRQ); - - GDBPORT_SERIAL_IER = UART_IER_RDI | UART_IER_RLSI; - - /* permit level 0 IRQs to take place */ - arch_local_change_intr_mask_level( - NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1)); -} - -/* - * set up the GDB stub serial port baud rate timers - */ -void gdbstub_io_set_baud(unsigned baud) -{ - unsigned value; - u8 lcr; - - value = 18432000 / 16 / baud; - - lcr = GDBPORT_SERIAL_LCR; - GDBPORT_SERIAL_LCR |= UART_LCR_DLAB; - GDBPORT_SERIAL_DLL = value & 0xff; - GDBPORT_SERIAL_DLM = (value >> 8) & 0xff; - GDBPORT_SERIAL_LCR = lcr; -} - -/* - * wait for a character to come from the debugger - */ -int gdbstub_io_rx_char(unsigned char *_ch, int nonblock) -{ - unsigned ix; - u8 ch, st; -#if defined(CONFIG_MN10300_WD_TIMER) - int cpu; -#endif - - *_ch = 0xff; - - if (gdbstub_rx_unget) { - *_ch = gdbstub_rx_unget; - gdbstub_rx_unget = 0; - return 0; - } - - try_again: - /* pull chars out of the buffer */ - ix = gdbstub_rx_outp; - barrier(); - if (ix == gdbstub_rx_inp) { - if (nonblock) - return -EAGAIN; -#ifdef CONFIG_MN10300_WD_TIMER - for (cpu = 0; cpu < NR_CPUS; cpu++) - watchdog_alert_counter[cpu] = 0; -#endif - goto try_again; - } - - ch = gdbstub_rx_buffer[ix++]; - st = gdbstub_rx_buffer[ix++]; - barrier(); - gdbstub_rx_outp = ix & 0x00000fff; - - if (st & UART_LSR_BI) { - gdbstub_proto("### GDB Rx Break Detected ###\n"); - return -EINTR; - } else if (st & (UART_LSR_FE | UART_LSR_OE | UART_LSR_PE)) { - gdbstub_proto("### GDB Rx Error (st=%02x) ###\n", st); - return -EIO; - } else { - gdbstub_proto("### GDB Rx %02x (st=%02x) ###\n", ch, st); - *_ch = ch & 0x7f; - return 0; - } -} - -/* - * send a character to the debugger - */ -void gdbstub_io_tx_char(unsigned char ch) -{ - FLOWCTL_SET(DTR); - LSR_WAIT_FOR(THRE); - /* FLOWCTL_WAIT_FOR(CTS); */ - - if (ch == 0x0a) { - GDBPORT_SERIAL_TX = 0x0d; - LSR_WAIT_FOR(THRE); - /* FLOWCTL_WAIT_FOR(CTS); */ - } - GDBPORT_SERIAL_TX = ch; - - FLOWCTL_CLEAR(DTR); -} - -/* - * send a character to the debugger - */ -void gdbstub_io_tx_flush(void) -{ - LSR_WAIT_FOR(TEMT); - LSR_WAIT_FOR(THRE); - FLOWCTL_CLEAR(DTR); -} diff --git a/arch/mn10300/kernel/gdb-io-ttysm-low.S b/arch/mn10300/kernel/gdb-io-ttysm-low.S deleted file mode 100644 index 060b7cca735d..000000000000 --- a/arch/mn10300/kernel/gdb-io-ttysm-low.S +++ /dev/null @@ -1,93 +0,0 @@ -############################################################################### -# -# MN10300 On-chip serial Rx interrupt handler for GDB stub I/O -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include -#include -#include -#include "mn10300-serial.h" - - .text - -############################################################################### -# -# GDB stub serial receive interrupt entry point -# - intended to run at interrupt priority 0 -# -############################################################################### - .globl gdbstub_io_rx_handler - .type gdbstub_io_rx_handler,@function -gdbstub_io_rx_handler: - movm [d2,d3,a2,a3],(sp) - - mov (gdbstub_rx_inp),a3 -gdbstub_io_rx_more: - mov a3,a2 - add 2,a3 - and PAGE_SIZE_asm-1,a3 - mov (gdbstub_rx_outp),d3 - cmp a3,d3 - beq gdbstub_io_rx_overflow - - movbu (SCgSTR),d3 - btst SC01STR_RBF,d3 - beq gdbstub_io_rx_done - movbu (SCgRXB),d2 - movbu d3,(gdbstub_rx_buffer+1,a2) - movbu d2,(gdbstub_rx_buffer,a2) - mov a3,(gdbstub_rx_inp) - bra gdbstub_io_rx_more - -gdbstub_io_rx_done: - mov GxICR_DETECT,d2 - movbu d2,(GxICR(SCgRXIRQ)) # ACK the interrupt - movhu (GxICR(SCgRXIRQ)),d2 # flush - - movm (sp),[d2,d3,a2,a3] - bset 0x01,(gdbstub_busy) - beq gdbstub_io_rx_enter - rti - -gdbstub_io_rx_overflow: - bset 0x01,(gdbstub_rx_overflow) - bra gdbstub_io_rx_done - -############################################################################### -# -# debugging interrupt - enter the GDB stub proper -# -############################################################################### -gdbstub_io_rx_enter: - or EPSW_IE|EPSW_IM_1,epsw - add -4,sp - SAVE_ALL - - mov 0xffffffff,d0 - mov d0,(REG_ORIG_D0,fp) - mov 0x280,d1 - - mov fp,d0 - call gdbstub_rx_irq[],0 # gdbstub_io_rx_irq(regs,excep) - - and ~EPSW_IE,epsw - bclr 0x01,(gdbstub_busy) - - .globl gdbstub_return -gdbstub_return: - RESTORE_ALL - - .size gdbstub_io_rx_handler,.-gdbstub_io_rx_handler diff --git a/arch/mn10300/kernel/gdb-io-ttysm.c b/arch/mn10300/kernel/gdb-io-ttysm.c deleted file mode 100644 index caae8cac9db1..000000000000 --- a/arch/mn10300/kernel/gdb-io-ttysm.c +++ /dev/null @@ -1,303 +0,0 @@ -/* MN10300 On-chip serial driver for gdbstub I/O - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mn10300-serial.h" - -#if defined(CONFIG_GDBSTUB_ON_TTYSM0) -struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif0; -#elif defined(CONFIG_GDBSTUB_ON_TTYSM1) -struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif1; -#else -struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif2; -#endif - - -/* - * initialise the GDB stub I/O routines - */ -void __init gdbstub_io_init(void) -{ - uint16_t scxctr; - int tmp; - - switch (gdbstub_port->clock_src) { - case MNSCx_CLOCK_SRC_IOCLK: - gdbstub_port->ioclk = MN10300_IOCLK; - break; - -#ifdef MN10300_IOBCLK - case MNSCx_CLOCK_SRC_IOBCLK: - gdbstub_port->ioclk = MN10300_IOBCLK; - break; -#endif - default: - BUG(); - } - - /* set up the serial port */ - gdbstub_io_set_baud(115200); - - /* we want to get serial receive interrupts */ - set_intr_level(gdbstub_port->rx_irq, - NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL)); - set_intr_level(gdbstub_port->tx_irq, - NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL)); - set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL), - gdbstub_io_rx_handler); - - *gdbstub_port->rx_icr |= GxICR_ENABLE; - tmp = *gdbstub_port->rx_icr; - - /* enable the device */ - scxctr = SC01CTR_CLN_8BIT; /* 1N8 */ - switch (gdbstub_port->div_timer) { - case MNSCx_DIV_TIMER_16BIT: - scxctr |= SC0CTR_CK_TM8UFLOW_8; /* == SC1CTR_CK_TM9UFLOW_8 - == SC2CTR_CK_TM10UFLOW_8 */ - break; - - case MNSCx_DIV_TIMER_8BIT: - scxctr |= SC0CTR_CK_TM2UFLOW_8; - break; - } - - scxctr |= SC01CTR_TXE | SC01CTR_RXE; - - *gdbstub_port->_control = scxctr; - tmp = *gdbstub_port->_control; - - /* permit level 0 IRQs only */ - arch_local_change_intr_mask_level( - NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1)); -} - -/* - * set up the GDB stub serial port baud rate timers - */ -void gdbstub_io_set_baud(unsigned baud) -{ - const unsigned bits = 10; /* 1 [start] + 8 [data] + 0 [parity] + - * 1 [stop] */ - unsigned long ioclk = gdbstub_port->ioclk; - unsigned xdiv, tmp; - uint16_t tmxbr; - uint8_t tmxmd; - - if (!baud) { - baud = 9600; - } else if (baud == 134) { - baud = 269; /* 134 is really 134.5 */ - xdiv = 2; - } - -try_alternative: - xdiv = 1; - - switch (gdbstub_port->div_timer) { - case MNSCx_DIV_TIMER_16BIT: - tmxmd = TM8MD_SRC_IOCLK; - tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 65535) - goto timer_okay; - - tmxmd = TM8MD_SRC_IOCLK_8; - tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 65535) - goto timer_okay; - - tmxmd = TM8MD_SRC_IOCLK_32; - tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 65535) - goto timer_okay; - - break; - - case MNSCx_DIV_TIMER_8BIT: - tmxmd = TM2MD_SRC_IOCLK; - tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 255) - goto timer_okay; - - tmxmd = TM2MD_SRC_IOCLK_8; - tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 255) - goto timer_okay; - - tmxmd = TM2MD_SRC_IOCLK_32; - tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 255) - goto timer_okay; - break; - } - - /* as a last resort, if the quotient is zero, default to 9600 bps */ - baud = 9600; - goto try_alternative; - -timer_okay: - gdbstub_port->uart.timeout = (2 * bits * HZ) / baud; - gdbstub_port->uart.timeout += HZ / 50; - - /* set the timer to produce the required baud rate */ - switch (gdbstub_port->div_timer) { - case MNSCx_DIV_TIMER_16BIT: - *gdbstub_port->_tmxmd = 0; - *gdbstub_port->_tmxbr = tmxbr; - *gdbstub_port->_tmxmd = TM8MD_INIT_COUNTER; - *gdbstub_port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE; - break; - - case MNSCx_DIV_TIMER_8BIT: - *gdbstub_port->_tmxmd = 0; - *(volatile u8 *) gdbstub_port->_tmxbr = (u8)tmxbr; - *gdbstub_port->_tmxmd = TM2MD_INIT_COUNTER; - *gdbstub_port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE; - break; - } -} - -/* - * wait for a character to come from the debugger - */ -int gdbstub_io_rx_char(unsigned char *_ch, int nonblock) -{ - unsigned ix; - u8 ch, st; -#if defined(CONFIG_MN10300_WD_TIMER) - int cpu; -#endif - - *_ch = 0xff; - - if (gdbstub_rx_unget) { - *_ch = gdbstub_rx_unget; - gdbstub_rx_unget = 0; - return 0; - } - -try_again: - /* pull chars out of the buffer */ - ix = gdbstub_rx_outp; - barrier(); - if (ix == gdbstub_rx_inp) { - if (nonblock) - return -EAGAIN; -#ifdef CONFIG_MN10300_WD_TIMER - for (cpu = 0; cpu < NR_CPUS; cpu++) - watchdog_alert_counter[cpu] = 0; -#endif - goto try_again; - } - - ch = gdbstub_rx_buffer[ix++]; - st = gdbstub_rx_buffer[ix++]; - barrier(); - gdbstub_rx_outp = ix & (PAGE_SIZE - 1); - - st &= SC01STR_RXF | SC01STR_RBF | SC01STR_FEF | SC01STR_PEF | - SC01STR_OEF; - - /* deal with what we've got - * - note that the UART doesn't do BREAK-detection for us - */ - if (st & SC01STR_FEF && ch == 0) { - switch (gdbstub_port->rx_brk) { - case 0: gdbstub_port->rx_brk = 1; goto try_again; - case 1: gdbstub_port->rx_brk = 2; goto try_again; - case 2: - gdbstub_port->rx_brk = 3; - gdbstub_proto("### GDB MNSERIAL Rx Break Detected" - " ###\n"); - return -EINTR; - default: - goto try_again; - } - } else if (st & SC01STR_FEF) { - if (gdbstub_port->rx_brk) - goto try_again; - - gdbstub_proto("### GDB MNSERIAL Framing Error ###\n"); - return -EIO; - } else if (st & SC01STR_OEF) { - if (gdbstub_port->rx_brk) - goto try_again; - - gdbstub_proto("### GDB MNSERIAL Overrun Error ###\n"); - return -EIO; - } else if (st & SC01STR_PEF) { - if (gdbstub_port->rx_brk) - goto try_again; - - gdbstub_proto("### GDB MNSERIAL Parity Error ###\n"); - return -EIO; - } else { - /* look for the tail-end char on a break run */ - if (gdbstub_port->rx_brk == 3) { - switch (ch) { - case 0xFF: - case 0xFE: - case 0xFC: - case 0xF8: - case 0xF0: - case 0xE0: - case 0xC0: - case 0x80: - case 0x00: - gdbstub_port->rx_brk = 0; - goto try_again; - default: - break; - } - } - - gdbstub_port->rx_brk = 0; - gdbstub_io("### GDB Rx %02x (st=%02x) ###\n", ch, st); - *_ch = ch & 0x7f; - return 0; - } -} - -/* - * send a character to the debugger - */ -void gdbstub_io_tx_char(unsigned char ch) -{ - while (*gdbstub_port->_status & SC01STR_TBF) - continue; - - if (ch == 0x0a) { - *(u8 *) gdbstub_port->_txb = 0x0d; - while (*gdbstub_port->_status & SC01STR_TBF) - continue; - } - - *(u8 *) gdbstub_port->_txb = ch; -} - -/* - * flush the transmission buffers - */ -void gdbstub_io_tx_flush(void) -{ - while (*gdbstub_port->_status & (SC01STR_TBF | SC01STR_TXF)) - continue; -} diff --git a/arch/mn10300/kernel/gdb-low.S b/arch/mn10300/kernel/gdb-low.S deleted file mode 100644 index e2725552cd82..000000000000 --- a/arch/mn10300/kernel/gdb-low.S +++ /dev/null @@ -1,115 +0,0 @@ -############################################################################### -# -# MN10300 Low-level gdbstub routines -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include -#include -#include - - .text - -############################################################################### -# -# GDB stub read memory with guard -# - D0 holds the memory address to read -# - D1 holds the address to store the byte into -# -############################################################################### - .globl gdbstub_read_byte_guard - .globl gdbstub_read_byte_cont -ENTRY(gdbstub_read_byte) - mov d0,a0 - mov d1,a1 - clr d0 -gdbstub_read_byte_guard: - movbu (a0),d1 -gdbstub_read_byte_cont: - movbu d1,(a1) - ret [],0 - - .globl gdbstub_read_word_guard - .globl gdbstub_read_word_cont -ENTRY(gdbstub_read_word) - mov d0,a0 - mov d1,a1 - clr d0 -gdbstub_read_word_guard: - movhu (a0),d1 -gdbstub_read_word_cont: - movhu d1,(a1) - ret [],0 - - .globl gdbstub_read_dword_guard - .globl gdbstub_read_dword_cont -ENTRY(gdbstub_read_dword) - mov d0,a0 - mov d1,a1 - clr d0 -gdbstub_read_dword_guard: - mov (a0),d1 -gdbstub_read_dword_cont: - mov d1,(a1) - ret [],0 - -############################################################################### -# -# GDB stub write memory with guard -# - D0 holds the byte to store -# - D1 holds the memory address to write -# -############################################################################### - .globl gdbstub_write_byte_guard - .globl gdbstub_write_byte_cont -ENTRY(gdbstub_write_byte) - mov d0,a0 - mov d1,a1 - clr d0 -gdbstub_write_byte_guard: - movbu a0,(a1) -gdbstub_write_byte_cont: - ret [],0 - - .globl gdbstub_write_word_guard - .globl gdbstub_write_word_cont -ENTRY(gdbstub_write_word) - mov d0,a0 - mov d1,a1 - clr d0 -gdbstub_write_word_guard: - movhu a0,(a1) -gdbstub_write_word_cont: - ret [],0 - - .globl gdbstub_write_dword_guard - .globl gdbstub_write_dword_cont -ENTRY(gdbstub_write_dword) - mov d0,a0 - mov d1,a1 - clr d0 -gdbstub_write_dword_guard: - mov a0,(a1) -gdbstub_write_dword_cont: - ret [],0 - -############################################################################### -# -# GDB stub BUG() trap -# -############################################################################### -ENTRY(__gdbstub_bug_trap) - .byte 0xF7,0xF7 # don't use 0xFF as the JTAG unit preempts that - ret [],0 diff --git a/arch/mn10300/kernel/gdb-stub.c b/arch/mn10300/kernel/gdb-stub.c deleted file mode 100644 index 3399d5699804..000000000000 --- a/arch/mn10300/kernel/gdb-stub.c +++ /dev/null @@ -1,1924 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* MN10300 GDB stub - * - * Originally written by Glenn Engel, Lake Stevens Instrument Division - * - * Contributed by HP Systems - * - * Modified for SPARC by Stu Grossman, Cygnus Support. - * - * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse - * Send complaints, suggestions etc. to - * - * Copyright (C) 1995 Andreas Busse - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified for Linux/mn10300 by David Howells - */ - -/* - * To enable debugger support, two things need to happen. One, a - * call to set_debug_traps() is necessary in order to allow any breakpoints - * or error conditions to be properly intercepted and reported to gdb. - * Two, a breakpoint needs to be generated to begin communication. This - * is most easily accomplished by a call to breakpoint(). Breakpoint() - * simulates a breakpoint by executing a BREAK instruction. - * - * - * The following gdb commands are supported: - * - * command function Return value - * - * g return the value of the CPU registers hex data or ENN - * G set the value of the CPU registers OK or ENN - * - * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN - * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN - * - * c Resume at current address SNN ( signal NN) - * cAA..AA Continue at address AA..AA SNN - * - * s Step one instruction SNN - * sAA..AA Step one instruction from AA..AA SNN - * - * k kill - * - * ? What was the last sigval ? SNN (signal NN) - * - * bBB..BB Set baud rate to BB..BB OK or BNN, then sets - * baud rate - * - * All commands and responses are sent with a packet which includes a - * checksum. A packet consists of - * - * $#. - * - * where - * :: - * :: < two hex digits computed as modulo 256 sum of > - * - * When a packet is received, it is first acknowledged with either '+' or '-'. - * '+' indicates a successful transfer. '-' indicates a failed transfer. - * - * Example: - * - * Host: Reply: - * $m0,10#2a +$00010203040506070809101112131415#42 - * - * - * ============== - * MORE EXAMPLES: - * ============== - * - * For reference -- the following are the steps that one - * company took (RidgeRun Inc) to get remote gdb debugging - * going. In this scenario the host machine was a PC and the - * target platform was a Galileo EVB64120A MIPS evaluation - * board. - * - * Step 1: - * First download gdb-5.0.tar.gz from the internet. - * and then build/install the package. - * - * Example: - * $ tar zxf gdb-5.0.tar.gz - * $ cd gdb-5.0 - * $ ./configure --target=am33_2.0-linux-gnu - * $ make - * $ install - * am33_2.0-linux-gnu-gdb - * - * Step 2: - * Configure linux for remote debugging and build it. - * - * Example: - * $ cd ~/linux - * $ make menuconfig - * $ make dep; make vmlinux - * - * Step 3: - * Download the kernel to the remote target and start - * the kernel running. It will promptly halt and wait - * for the host gdb session to connect. It does this - * since the "Kernel Hacking" option has defined - * CONFIG_REMOTE_DEBUG which in turn enables your calls - * to: - * set_debug_traps(); - * breakpoint(); - * - * Step 4: - * Start the gdb session on the host. - * - * Example: - * $ am33_2.0-linux-gnu-gdb vmlinux - * (gdb) set remotebaud 115200 - * (gdb) target remote /dev/ttyS1 - * ...at this point you are connected to - * the remote target and can use gdb - * in the normal fasion. Setting - * breakpoints, single stepping, - * printing variables, etc. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* define to use F7F7 rather than FF which is subverted by JTAG debugger */ -#undef GDBSTUB_USE_F7F7_AS_BREAKPOINT - -/* - * BUFMAX defines the maximum number of characters in inbound/outbound buffers - * at least NUMREGBYTES*2 are needed for register packets - */ -#define BUFMAX 2048 - -static const char gdbstub_banner[] = - "Linux/MN10300 GDB Stub (c) RedHat 2007\n"; - -u8 gdbstub_rx_buffer[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE))); -u32 gdbstub_rx_inp; -u32 gdbstub_rx_outp; -u8 gdbstub_busy; -u8 gdbstub_rx_overflow; -u8 gdbstub_rx_unget; - -static u8 gdbstub_flush_caches; -static char input_buffer[BUFMAX]; -static char output_buffer[BUFMAX]; -static char trans_buffer[BUFMAX]; - -struct gdbstub_bkpt { - u8 *addr; /* address of breakpoint */ - u8 len; /* size of breakpoint */ - u8 origbytes[7]; /* original bytes */ -}; - -static struct gdbstub_bkpt gdbstub_bkpts[256]; - -/* - * local prototypes - */ -static void getpacket(char *buffer); -static int putpacket(char *buffer); -static int computeSignal(enum exception_code excep); -static int hex(unsigned char ch); -static int hexToInt(char **ptr, int *intValue); -static unsigned char *mem2hex(const void *mem, char *buf, int count, - int may_fault); -static const char *hex2mem(const char *buf, void *_mem, int count, - int may_fault); - -/* - * Convert ch from a hex digit to an int - */ -static int hex(unsigned char ch) -{ - if (ch >= 'a' && ch <= 'f') - return ch - 'a' + 10; - if (ch >= '0' && ch <= '9') - return ch - '0'; - if (ch >= 'A' && ch <= 'F') - return ch - 'A' + 10; - return -1; -} - -#ifdef CONFIG_GDBSTUB_DEBUGGING - -void debug_to_serial(const char *p, int n) -{ - __debug_to_serial(p, n); - /* gdbstub_console_write(NULL, p, n); */ -} - -void gdbstub_printk(const char *fmt, ...) -{ - va_list args; - int len; - - /* Emit the output into the temporary buffer */ - va_start(args, fmt); - len = vsnprintf(trans_buffer, sizeof(trans_buffer), fmt, args); - va_end(args); - debug_to_serial(trans_buffer, len); -} - -#endif - -static inline char *gdbstub_strcpy(char *dst, const char *src) -{ - int loop = 0; - while ((dst[loop] = src[loop])) - loop++; - return dst; -} - -/* - * scan for the sequence $# - */ -static void getpacket(char *buffer) -{ - unsigned char checksum; - unsigned char xmitcsum; - unsigned char ch; - int count, i, ret, error; - - for (;;) { - /* - * wait around for the start character, - * ignore all other characters - */ - do { - gdbstub_io_rx_char(&ch, 0); - } while (ch != '$'); - - checksum = 0; - xmitcsum = -1; - count = 0; - error = 0; - - /* - * now, read until a # or end of buffer is found - */ - while (count < BUFMAX) { - ret = gdbstub_io_rx_char(&ch, 0); - if (ret < 0) - error = ret; - - if (ch == '#') - break; - checksum += ch; - buffer[count] = ch; - count++; - } - - if (error == -EIO) { - gdbstub_proto("### GDB Rx Error - Skipping packet" - " ###\n"); - gdbstub_proto("### GDB Tx NAK\n"); - gdbstub_io_tx_char('-'); - continue; - } - - if (count >= BUFMAX || error) - continue; - - buffer[count] = 0; - - /* read the checksum */ - ret = gdbstub_io_rx_char(&ch, 0); - if (ret < 0) - error = ret; - xmitcsum = hex(ch) << 4; - - ret = gdbstub_io_rx_char(&ch, 0); - if (ret < 0) - error = ret; - xmitcsum |= hex(ch); - - if (error) { - if (error == -EIO) - gdbstub_io("### GDB Rx Error -" - " Skipping packet\n"); - gdbstub_io("### GDB Tx NAK\n"); - gdbstub_io_tx_char('-'); - continue; - } - - /* check the checksum */ - if (checksum != xmitcsum) { - gdbstub_io("### GDB Tx NAK\n"); - gdbstub_io_tx_char('-'); /* failed checksum */ - continue; - } - - gdbstub_proto("### GDB Rx '$%s#%02x' ###\n", buffer, checksum); - gdbstub_io("### GDB Tx ACK\n"); - gdbstub_io_tx_char('+'); /* successful transfer */ - - /* - * if a sequence char is present, - * reply the sequence ID - */ - if (buffer[2] == ':') { - gdbstub_io_tx_char(buffer[0]); - gdbstub_io_tx_char(buffer[1]); - - /* - * remove sequence chars from buffer - */ - count = 0; - while (buffer[count]) - count++; - for (i = 3; i <= count; i++) - buffer[i - 3] = buffer[i]; - } - - break; - } -} - -/* - * send the packet in buffer. - * - return 0 if successfully ACK'd - * - return 1 if abandoned due to new incoming packet - */ -static int putpacket(char *buffer) -{ - unsigned char checksum; - unsigned char ch; - int count; - - /* - * $#. - */ - gdbstub_proto("### GDB Tx $'%s'#?? ###\n", buffer); - - do { - gdbstub_io_tx_char('$'); - checksum = 0; - count = 0; - - while ((ch = buffer[count]) != 0) { - gdbstub_io_tx_char(ch); - checksum += ch; - count += 1; - } - - gdbstub_io_tx_char('#'); - gdbstub_io_tx_char(hex_asc_hi(checksum)); - gdbstub_io_tx_char(hex_asc_lo(checksum)); - - } while (gdbstub_io_rx_char(&ch, 0), - ch == '-' && (gdbstub_io("### GDB Rx NAK\n"), 0), - ch != '-' && ch != '+' && - (gdbstub_io("### GDB Rx ??? %02x\n", ch), 0), - ch != '+' && ch != '$'); - - if (ch == '+') { - gdbstub_io("### GDB Rx ACK\n"); - return 0; - } - - gdbstub_io("### GDB Tx Abandoned\n"); - gdbstub_rx_unget = ch; - return 1; -} - -/* - * While we find nice hex chars, build an int. - * Return number of chars processed. - */ -static int hexToInt(char **ptr, int *intValue) -{ - int numChars = 0; - int hexValue; - - *intValue = 0; - - while (**ptr) { - hexValue = hex(**ptr); - if (hexValue < 0) - break; - - *intValue = (*intValue << 4) | hexValue; - numChars++; - - (*ptr)++; - } - - return (numChars); -} - -#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP -/* - * We single-step by setting breakpoints. When an exception - * is handled, we need to restore the instructions hoisted - * when the breakpoints were set. - * - * This is where we save the original instructions. - */ -static struct gdb_bp_save { - u8 *addr; - u8 opcode[2]; -} step_bp[2]; - -static const unsigned char gdbstub_insn_sizes[256] = -{ - /* 1 2 3 4 5 6 7 8 9 a b c d e f */ - 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */ - 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */ - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */ - 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */ - 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */ - 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */ -}; - -static int __gdbstub_mark_bp(u8 *addr, int ix) -{ - /* vmalloc area */ - if (((u8 *) VMALLOC_START <= addr) && (addr < (u8 *) VMALLOC_END)) - goto okay; - /* SRAM, SDRAM */ - if (((u8 *) 0x80000000UL <= addr) && (addr < (u8 *) 0xa0000000UL)) - goto okay; - return 0; - -okay: - if (gdbstub_read_byte(addr + 0, &step_bp[ix].opcode[0]) < 0 || - gdbstub_read_byte(addr + 1, &step_bp[ix].opcode[1]) < 0) - return 0; - - step_bp[ix].addr = addr; - return 1; -} - -static inline void __gdbstub_restore_bp(void) -{ -#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT - if (step_bp[0].addr) { - gdbstub_write_byte(step_bp[0].opcode[0], step_bp[0].addr + 0); - gdbstub_write_byte(step_bp[0].opcode[1], step_bp[0].addr + 1); - } - if (step_bp[1].addr) { - gdbstub_write_byte(step_bp[1].opcode[0], step_bp[1].addr + 0); - gdbstub_write_byte(step_bp[1].opcode[1], step_bp[1].addr + 1); - } -#else - if (step_bp[0].addr) - gdbstub_write_byte(step_bp[0].opcode[0], step_bp[0].addr + 0); - if (step_bp[1].addr) - gdbstub_write_byte(step_bp[1].opcode[0], step_bp[1].addr + 0); -#endif - - gdbstub_flush_caches = 1; - - step_bp[0].addr = NULL; - step_bp[0].opcode[0] = 0; - step_bp[0].opcode[1] = 0; - step_bp[1].addr = NULL; - step_bp[1].opcode[0] = 0; - step_bp[1].opcode[1] = 0; -} - -/* - * emulate single stepping by means of breakpoint instructions - */ -static int gdbstub_single_step(struct pt_regs *regs) -{ - unsigned size; - uint32_t x; - uint8_t cur, *pc, *sp; - - step_bp[0].addr = NULL; - step_bp[0].opcode[0] = 0; - step_bp[0].opcode[1] = 0; - step_bp[1].addr = NULL; - step_bp[1].opcode[0] = 0; - step_bp[1].opcode[1] = 0; - x = 0; - - pc = (u8 *) regs->pc; - sp = (u8 *) (regs + 1); - if (gdbstub_read_byte(pc, &cur) < 0) - return -EFAULT; - - gdbstub_bkpt("Single Step from %p { %02x }\n", pc, cur); - - gdbstub_flush_caches = 1; - - size = gdbstub_insn_sizes[cur]; - if (size > 0) { - if (!__gdbstub_mark_bp(pc + size, 0)) - goto fault; - } else { - switch (cur) { - /* Bxx (d8,PC) */ - case 0xc0 ... 0xca: - if (gdbstub_read_byte(pc + 1, (u8 *) &x) < 0) - goto fault; - if (!__gdbstub_mark_bp(pc + 2, 0)) - goto fault; - if ((x < 0 || x > 2) && - !__gdbstub_mark_bp(pc + (s8) x, 1)) - goto fault; - break; - - /* LXX (d8,PC) */ - case 0xd0 ... 0xda: - if (!__gdbstub_mark_bp(pc + 1, 0)) - goto fault; - if (regs->pc != regs->lar && - !__gdbstub_mark_bp((u8 *) regs->lar, 1)) - goto fault; - break; - - /* SETLB - loads the next for bytes into the LIR - * register */ - case 0xdb: - if (!__gdbstub_mark_bp(pc + 1, 0)) - goto fault; - break; - - /* JMP (d16,PC) or CALL (d16,PC) */ - case 0xcc: - case 0xcd: - if (gdbstub_read_byte(pc + 1, ((u8 *) &x) + 0) < 0 || - gdbstub_read_byte(pc + 2, ((u8 *) &x) + 1) < 0) - goto fault; - if (!__gdbstub_mark_bp(pc + (s16) x, 0)) - goto fault; - break; - - /* JMP (d32,PC) or CALL (d32,PC) */ - case 0xdc: - case 0xdd: - if (gdbstub_read_byte(pc + 1, ((u8 *) &x) + 0) < 0 || - gdbstub_read_byte(pc + 2, ((u8 *) &x) + 1) < 0 || - gdbstub_read_byte(pc + 3, ((u8 *) &x) + 2) < 0 || - gdbstub_read_byte(pc + 4, ((u8 *) &x) + 3) < 0) - goto fault; - if (!__gdbstub_mark_bp(pc + (s32) x, 0)) - goto fault; - break; - - /* RETF */ - case 0xde: - if (!__gdbstub_mark_bp((u8 *) regs->mdr, 0)) - goto fault; - break; - - /* RET */ - case 0xdf: - if (gdbstub_read_byte(pc + 2, (u8 *) &x) < 0) - goto fault; - sp += (s8)x; - if (gdbstub_read_byte(sp + 0, ((u8 *) &x) + 0) < 0 || - gdbstub_read_byte(sp + 1, ((u8 *) &x) + 1) < 0 || - gdbstub_read_byte(sp + 2, ((u8 *) &x) + 2) < 0 || - gdbstub_read_byte(sp + 3, ((u8 *) &x) + 3) < 0) - goto fault; - if (!__gdbstub_mark_bp((u8 *) x, 0)) - goto fault; - break; - - case 0xf0: - if (gdbstub_read_byte(pc + 1, &cur) < 0) - goto fault; - - if (cur >= 0xf0 && cur <= 0xf7) { - /* JMP (An) / CALLS (An) */ - switch (cur & 3) { - case 0: x = regs->a0; break; - case 1: x = regs->a1; break; - case 2: x = regs->a2; break; - case 3: x = regs->a3; break; - } - if (!__gdbstub_mark_bp((u8 *) x, 0)) - goto fault; - } else if (cur == 0xfc) { - /* RETS */ - if (gdbstub_read_byte( - sp + 0, ((u8 *) &x) + 0) < 0 || - gdbstub_read_byte( - sp + 1, ((u8 *) &x) + 1) < 0 || - gdbstub_read_byte( - sp + 2, ((u8 *) &x) + 2) < 0 || - gdbstub_read_byte( - sp + 3, ((u8 *) &x) + 3) < 0) - goto fault; - if (!__gdbstub_mark_bp((u8 *) x, 0)) - goto fault; - } else if (cur == 0xfd) { - /* RTI */ - if (gdbstub_read_byte( - sp + 4, ((u8 *) &x) + 0) < 0 || - gdbstub_read_byte( - sp + 5, ((u8 *) &x) + 1) < 0 || - gdbstub_read_byte( - sp + 6, ((u8 *) &x) + 2) < 0 || - gdbstub_read_byte( - sp + 7, ((u8 *) &x) + 3) < 0) - goto fault; - if (!__gdbstub_mark_bp((u8 *) x, 0)) - goto fault; - } else { - if (!__gdbstub_mark_bp(pc + 2, 0)) - goto fault; - } - - break; - - /* potential 3-byte conditional branches */ - case 0xf8: - if (gdbstub_read_byte(pc + 1, &cur) < 0) - goto fault; - if (!__gdbstub_mark_bp(pc + 3, 0)) - goto fault; - - if (cur >= 0xe8 && cur <= 0xeb) { - if (gdbstub_read_byte( - pc + 2, ((u8 *) &x) + 0) < 0) - goto fault; - if ((x < 0 || x > 3) && - !__gdbstub_mark_bp(pc + (s8) x, 1)) - goto fault; - } - break; - - case 0xfa: - if (gdbstub_read_byte(pc + 1, &cur) < 0) - goto fault; - - if (cur == 0xff) { - /* CALLS (d16,PC) */ - if (gdbstub_read_byte( - pc + 2, ((u8 *) &x) + 0) < 0 || - gdbstub_read_byte( - pc + 3, ((u8 *) &x) + 1) < 0) - goto fault; - if (!__gdbstub_mark_bp(pc + (s16) x, 0)) - goto fault; - } else { - if (!__gdbstub_mark_bp(pc + 4, 0)) - goto fault; - } - break; - - case 0xfc: - if (gdbstub_read_byte(pc + 1, &cur) < 0) - goto fault; - if (cur == 0xff) { - /* CALLS (d32,PC) */ - if (gdbstub_read_byte( - pc + 2, ((u8 *) &x) + 0) < 0 || - gdbstub_read_byte( - pc + 3, ((u8 *) &x) + 1) < 0 || - gdbstub_read_byte( - pc + 4, ((u8 *) &x) + 2) < 0 || - gdbstub_read_byte( - pc + 5, ((u8 *) &x) + 3) < 0) - goto fault; - if (!__gdbstub_mark_bp( - pc + (s32) x, 0)) - goto fault; - } else { - if (!__gdbstub_mark_bp( - pc + 6, 0)) - goto fault; - } - break; - - } - } - - gdbstub_bkpt("Step: %02x at %p; %02x at %p\n", - step_bp[0].opcode[0], step_bp[0].addr, - step_bp[1].opcode[0], step_bp[1].addr); - - if (step_bp[0].addr) { -#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT - if (gdbstub_write_byte(0xF7, step_bp[0].addr + 0) < 0 || - gdbstub_write_byte(0xF7, step_bp[0].addr + 1) < 0) - goto fault; -#else - if (gdbstub_write_byte(0xFF, step_bp[0].addr + 0) < 0) - goto fault; -#endif - } - - if (step_bp[1].addr) { -#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT - if (gdbstub_write_byte(0xF7, step_bp[1].addr + 0) < 0 || - gdbstub_write_byte(0xF7, step_bp[1].addr + 1) < 0) - goto fault; -#else - if (gdbstub_write_byte(0xFF, step_bp[1].addr + 0) < 0) - goto fault; -#endif - } - - return 0; - - fault: - /* uh-oh - silly address alert, try and restore things */ - __gdbstub_restore_bp(); - return -EFAULT; -} -#endif /* CONFIG_GDBSTUB_ALLOW_SINGLE_STEP */ - -#ifdef CONFIG_GDBSTUB_CONSOLE - -void gdbstub_console_write(struct console *con, const char *p, unsigned n) -{ - static const char gdbstub_cr[] = { 0x0d }; - char outbuf[26]; - int qty; - u8 busy; - - busy = gdbstub_busy; - gdbstub_busy = 1; - - outbuf[0] = 'O'; - - while (n > 0) { - qty = 1; - - while (n > 0 && qty < 20) { - mem2hex(p, outbuf + qty, 2, 0); - qty += 2; - if (*p == 0x0a) { - mem2hex(gdbstub_cr, outbuf + qty, 2, 0); - qty += 2; - } - p++; - n--; - } - - outbuf[qty] = 0; - putpacket(outbuf); - } - - gdbstub_busy = busy; -} - -static kdev_t gdbstub_console_dev(struct console *con) -{ - return MKDEV(1, 3); /* /dev/null */ -} - -static struct console gdbstub_console = { - .name = "gdb", - .write = gdbstub_console_write, - .device = gdbstub_console_dev, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -#endif - -/* - * Convert the memory pointed to by mem into hex, placing result in buf. - * - if successful, return a pointer to the last char put in buf (NUL) - * - in case of mem fault, return NULL - * may_fault is non-zero if we are reading from arbitrary memory, but is - * currently not used. - */ -static -unsigned char *mem2hex(const void *_mem, char *buf, int count, int may_fault) -{ - const u8 *mem = _mem; - u8 ch[4]; - - if ((u32) mem & 1 && count >= 1) { - if (gdbstub_read_byte(mem, ch) != 0) - return 0; - buf = hex_byte_pack(buf, ch[0]); - mem++; - count--; - } - - if ((u32) mem & 3 && count >= 2) { - if (gdbstub_read_word(mem, ch) != 0) - return 0; - buf = hex_byte_pack(buf, ch[0]); - buf = hex_byte_pack(buf, ch[1]); - mem += 2; - count -= 2; - } - - while (count >= 4) { - if (gdbstub_read_dword(mem, ch) != 0) - return 0; - buf = hex_byte_pack(buf, ch[0]); - buf = hex_byte_pack(buf, ch[1]); - buf = hex_byte_pack(buf, ch[2]); - buf = hex_byte_pack(buf, ch[3]); - mem += 4; - count -= 4; - } - - if (count >= 2) { - if (gdbstub_read_word(mem, ch) != 0) - return 0; - buf = hex_byte_pack(buf, ch[0]); - buf = hex_byte_pack(buf, ch[1]); - mem += 2; - count -= 2; - } - - if (count >= 1) { - if (gdbstub_read_byte(mem, ch) != 0) - return 0; - buf = hex_byte_pack(buf, ch[0]); - } - - *buf = 0; - return buf; -} - -/* - * convert the hex array pointed to by buf into binary to be placed in mem - * return a pointer to the character AFTER the last byte written - * may_fault is non-zero if we are reading from arbitrary memory, but is - * currently not used. - */ -static -const char *hex2mem(const char *buf, void *_mem, int count, int may_fault) -{ - u8 *mem = _mem; - union { - u32 val; - u8 b[4]; - } ch; - - if ((u32) mem & 1 && count >= 1) { - ch.b[0] = hex(*buf++) << 4; - ch.b[0] |= hex(*buf++); - if (gdbstub_write_byte(ch.val, mem) != 0) - return 0; - mem++; - count--; - } - - if ((u32) mem & 3 && count >= 2) { - ch.b[0] = hex(*buf++) << 4; - ch.b[0] |= hex(*buf++); - ch.b[1] = hex(*buf++) << 4; - ch.b[1] |= hex(*buf++); - if (gdbstub_write_word(ch.val, mem) != 0) - return 0; - mem += 2; - count -= 2; - } - - while (count >= 4) { - ch.b[0] = hex(*buf++) << 4; - ch.b[0] |= hex(*buf++); - ch.b[1] = hex(*buf++) << 4; - ch.b[1] |= hex(*buf++); - ch.b[2] = hex(*buf++) << 4; - ch.b[2] |= hex(*buf++); - ch.b[3] = hex(*buf++) << 4; - ch.b[3] |= hex(*buf++); - if (gdbstub_write_dword(ch.val, mem) != 0) - return 0; - mem += 4; - count -= 4; - } - - if (count >= 2) { - ch.b[0] = hex(*buf++) << 4; - ch.b[0] |= hex(*buf++); - ch.b[1] = hex(*buf++) << 4; - ch.b[1] |= hex(*buf++); - if (gdbstub_write_word(ch.val, mem) != 0) - return 0; - mem += 2; - count -= 2; - } - - if (count >= 1) { - ch.b[0] = hex(*buf++) << 4; - ch.b[0] |= hex(*buf++); - if (gdbstub_write_byte(ch.val, mem) != 0) - return 0; - } - - return buf; -} - -/* - * This table contains the mapping between MN10300 exception codes, and - * signals, which are primarily what GDB understands. It also indicates - * which hardware traps we need to commandeer when initializing the stub. - */ -static const struct excep_to_sig_map { - enum exception_code excep; /* MN10300 exception code */ - unsigned char signo; /* Signal that we map this into */ -} excep_to_sig_map[] = { - { EXCEP_ITLBMISS, SIGSEGV }, - { EXCEP_DTLBMISS, SIGSEGV }, - { EXCEP_TRAP, SIGTRAP }, - { EXCEP_ISTEP, SIGTRAP }, - { EXCEP_IBREAK, SIGTRAP }, - { EXCEP_OBREAK, SIGTRAP }, - { EXCEP_UNIMPINS, SIGILL }, - { EXCEP_UNIMPEXINS, SIGILL }, - { EXCEP_MEMERR, SIGSEGV }, - { EXCEP_MISALIGN, SIGSEGV }, - { EXCEP_BUSERROR, SIGBUS }, - { EXCEP_ILLINSACC, SIGSEGV }, - { EXCEP_ILLDATACC, SIGSEGV }, - { EXCEP_IOINSACC, SIGSEGV }, - { EXCEP_PRIVINSACC, SIGSEGV }, - { EXCEP_PRIVDATACC, SIGSEGV }, - { EXCEP_FPU_DISABLED, SIGFPE }, - { EXCEP_FPU_UNIMPINS, SIGFPE }, - { EXCEP_FPU_OPERATION, SIGFPE }, - { EXCEP_WDT, SIGALRM }, - { EXCEP_NMI, SIGQUIT }, - { EXCEP_IRQ_LEVEL0, SIGINT }, - { EXCEP_IRQ_LEVEL1, SIGINT }, - { EXCEP_IRQ_LEVEL2, SIGINT }, - { EXCEP_IRQ_LEVEL3, SIGINT }, - { EXCEP_IRQ_LEVEL4, SIGINT }, - { EXCEP_IRQ_LEVEL5, SIGINT }, - { EXCEP_IRQ_LEVEL6, SIGINT }, - { 0, 0} -}; - -/* - * convert the MN10300 exception code into a UNIX signal number - */ -static int computeSignal(enum exception_code excep) -{ - const struct excep_to_sig_map *map; - - for (map = excep_to_sig_map; map->signo; map++) - if (map->excep == excep) - return map->signo; - - return SIGHUP; /* default for things we don't know about */ -} - -static u32 gdbstub_fpcr, gdbstub_fpufs_array[32]; - -/* - * - */ -static void gdbstub_store_fpu(void) -{ -#ifdef CONFIG_FPU - - asm volatile( - "or %2,epsw\n" -#ifdef CONFIG_MN10300_PROC_MN103E010 - "nop\n" - "nop\n" -#endif - "mov %1, a1\n" - "fmov fs0, (a1+)\n" - "fmov fs1, (a1+)\n" - "fmov fs2, (a1+)\n" - "fmov fs3, (a1+)\n" - "fmov fs4, (a1+)\n" - "fmov fs5, (a1+)\n" - "fmov fs6, (a1+)\n" - "fmov fs7, (a1+)\n" - "fmov fs8, (a1+)\n" - "fmov fs9, (a1+)\n" - "fmov fs10, (a1+)\n" - "fmov fs11, (a1+)\n" - "fmov fs12, (a1+)\n" - "fmov fs13, (a1+)\n" - "fmov fs14, (a1+)\n" - "fmov fs15, (a1+)\n" - "fmov fs16, (a1+)\n" - "fmov fs17, (a1+)\n" - "fmov fs18, (a1+)\n" - "fmov fs19, (a1+)\n" - "fmov fs20, (a1+)\n" - "fmov fs21, (a1+)\n" - "fmov fs22, (a1+)\n" - "fmov fs23, (a1+)\n" - "fmov fs24, (a1+)\n" - "fmov fs25, (a1+)\n" - "fmov fs26, (a1+)\n" - "fmov fs27, (a1+)\n" - "fmov fs28, (a1+)\n" - "fmov fs29, (a1+)\n" - "fmov fs30, (a1+)\n" - "fmov fs31, (a1+)\n" - "fmov fpcr, %0\n" - : "=d"(gdbstub_fpcr) - : "g" (&gdbstub_fpufs_array), "i"(EPSW_FE) - : "a1" - ); -#endif -} - -/* - * - */ -static void gdbstub_load_fpu(void) -{ -#ifdef CONFIG_FPU - - asm volatile( - "or %1,epsw\n" -#ifdef CONFIG_MN10300_PROC_MN103E010 - "nop\n" - "nop\n" -#endif - "mov %0, a1\n" - "fmov (a1+), fs0\n" - "fmov (a1+), fs1\n" - "fmov (a1+), fs2\n" - "fmov (a1+), fs3\n" - "fmov (a1+), fs4\n" - "fmov (a1+), fs5\n" - "fmov (a1+), fs6\n" - "fmov (a1+), fs7\n" - "fmov (a1+), fs8\n" - "fmov (a1+), fs9\n" - "fmov (a1+), fs10\n" - "fmov (a1+), fs11\n" - "fmov (a1+), fs12\n" - "fmov (a1+), fs13\n" - "fmov (a1+), fs14\n" - "fmov (a1+), fs15\n" - "fmov (a1+), fs16\n" - "fmov (a1+), fs17\n" - "fmov (a1+), fs18\n" - "fmov (a1+), fs19\n" - "fmov (a1+), fs20\n" - "fmov (a1+), fs21\n" - "fmov (a1+), fs22\n" - "fmov (a1+), fs23\n" - "fmov (a1+), fs24\n" - "fmov (a1+), fs25\n" - "fmov (a1+), fs26\n" - "fmov (a1+), fs27\n" - "fmov (a1+), fs28\n" - "fmov (a1+), fs29\n" - "fmov (a1+), fs30\n" - "fmov (a1+), fs31\n" - "fmov %2, fpcr\n" - : - : "g" (&gdbstub_fpufs_array), "i"(EPSW_FE), "d"(gdbstub_fpcr) - : "a1" - ); -#endif -} - -/* - * set a software breakpoint - */ -int gdbstub_set_breakpoint(u8 *addr, int len) -{ - int bkpt, loop, xloop; - -#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT - len = (len + 1) & ~1; -#endif - - gdbstub_bkpt("setbkpt(%p,%d)\n", addr, len); - - for (bkpt = 255; bkpt >= 0; bkpt--) - if (!gdbstub_bkpts[bkpt].addr) - break; - if (bkpt < 0) - return -ENOSPC; - - for (loop = 0; loop < len; loop++) - if (gdbstub_read_byte(&addr[loop], - &gdbstub_bkpts[bkpt].origbytes[loop] - ) < 0) - return -EFAULT; - - gdbstub_flush_caches = 1; - -#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT - for (loop = 0; loop < len; loop++) - if (gdbstub_write_byte(0xF7, &addr[loop]) < 0) - goto restore; -#else - for (loop = 0; loop < len; loop++) - if (gdbstub_write_byte(0xFF, &addr[loop]) < 0) - goto restore; -#endif - - gdbstub_bkpts[bkpt].addr = addr; - gdbstub_bkpts[bkpt].len = len; - - gdbstub_bkpt("Set BKPT[%02x]: %p-%p {%02x%02x%02x%02x%02x%02x%02x}\n", - bkpt, - gdbstub_bkpts[bkpt].addr, - gdbstub_bkpts[bkpt].addr + gdbstub_bkpts[bkpt].len - 1, - gdbstub_bkpts[bkpt].origbytes[0], - gdbstub_bkpts[bkpt].origbytes[1], - gdbstub_bkpts[bkpt].origbytes[2], - gdbstub_bkpts[bkpt].origbytes[3], - gdbstub_bkpts[bkpt].origbytes[4], - gdbstub_bkpts[bkpt].origbytes[5], - gdbstub_bkpts[bkpt].origbytes[6] - ); - - return 0; - -restore: - for (xloop = 0; xloop < loop; xloop++) - gdbstub_write_byte(gdbstub_bkpts[bkpt].origbytes[xloop], - addr + xloop); - return -EFAULT; -} - -/* - * clear a software breakpoint - */ -int gdbstub_clear_breakpoint(u8 *addr, int len) -{ - int bkpt, loop; - -#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT - len = (len + 1) & ~1; -#endif - - gdbstub_bkpt("clearbkpt(%p,%d)\n", addr, len); - - for (bkpt = 255; bkpt >= 0; bkpt--) - if (gdbstub_bkpts[bkpt].addr == addr && - gdbstub_bkpts[bkpt].len == len) - break; - if (bkpt < 0) - return -ENOENT; - - gdbstub_bkpts[bkpt].addr = NULL; - - gdbstub_flush_caches = 1; - - for (loop = 0; loop < len; loop++) - if (gdbstub_write_byte(gdbstub_bkpts[bkpt].origbytes[loop], - addr + loop) < 0) - return -EFAULT; - - return 0; -} - -/* - * This function does all command processing for interfacing to gdb - * - returns 0 if the exception should be skipped, -ERROR otherwise. - */ -static int gdbstub(struct pt_regs *regs, enum exception_code excep) -{ - unsigned long *stack; - unsigned long epsw, mdr; - uint32_t zero, ssp; - uint8_t broke; - char *ptr; - int sigval; - int addr; - int length; - int loop; - - if (excep == EXCEP_FPU_DISABLED) - return -ENOTSUPP; - - gdbstub_flush_caches = 0; - - mn10300_set_gdbleds(1); - - asm volatile("mov mdr,%0" : "=d"(mdr)); - local_save_flags(epsw); - arch_local_change_intr_mask_level( - NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1)); - - gdbstub_store_fpu(); - -#ifdef CONFIG_GDBSTUB_IMMEDIATE - /* skip the initial pause loop */ - if (regs->pc == (unsigned long) __gdbstub_pause) - regs->pc = (unsigned long) start_kernel; -#endif - - /* if we were single stepping, restore the opcodes hoisted for the - * breakpoint[s] */ - broke = 0; -#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP - if ((step_bp[0].addr && step_bp[0].addr == (u8 *) regs->pc) || - (step_bp[1].addr && step_bp[1].addr == (u8 *) regs->pc)) - broke = 1; - - __gdbstub_restore_bp(); -#endif - - if (gdbstub_rx_unget) { - sigval = SIGINT; - if (gdbstub_rx_unget != 3) - goto packet_waiting; - gdbstub_rx_unget = 0; - } - - stack = (unsigned long *) regs->sp; - sigval = broke ? SIGTRAP : computeSignal(excep); - - /* send information about a BUG() */ - if (!user_mode(regs) && excep == EXCEP_SYSCALL15) { - const struct bug_entry *bug; - - bug = find_bug(regs->pc); - if (bug) - goto found_bug; - length = snprintf(trans_buffer, sizeof(trans_buffer), - "BUG() at address %lx\n", regs->pc); - goto send_bug_pkt; - - found_bug: - length = snprintf(trans_buffer, sizeof(trans_buffer), - "BUG() at address %lx (%s:%d)\n", - regs->pc, bug->file, bug->line); - - send_bug_pkt: - ptr = output_buffer; - *ptr++ = 'O'; - ptr = mem2hex(trans_buffer, ptr, length, 0); - *ptr = 0; - putpacket(output_buffer); - - regs->pc -= 2; - sigval = SIGABRT; - } else if (regs->pc == (unsigned long) __gdbstub_bug_trap) { - regs->pc = regs->mdr; - sigval = SIGABRT; - } - - /* - * send a message to the debugger's user saying what happened if it may - * not be clear cut (we can't map exceptions onto signals properly) - */ - if (sigval != SIGINT && sigval != SIGTRAP && sigval != SIGILL) { - static const char title[] = "Excep ", tbcberr[] = "BCBERR "; - static const char crlf[] = "\r\n"; - char hx; - u32 bcberr = BCBERR; - - ptr = output_buffer; - *ptr++ = 'O'; - ptr = mem2hex(title, ptr, sizeof(title) - 1, 0); - - hx = hex_asc_hi(excep >> 8); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_lo(excep >> 8); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_hi(excep); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_lo(excep); - ptr = hex_byte_pack(ptr, hx); - - ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0); - *ptr = 0; - putpacket(output_buffer); /* send it off... */ - - /* BCBERR */ - ptr = output_buffer; - *ptr++ = 'O'; - ptr = mem2hex(tbcberr, ptr, sizeof(tbcberr) - 1, 0); - - hx = hex_asc_hi(bcberr >> 24); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_lo(bcberr >> 24); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_hi(bcberr >> 16); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_lo(bcberr >> 16); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_hi(bcberr >> 8); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_lo(bcberr >> 8); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_hi(bcberr); - ptr = hex_byte_pack(ptr, hx); - hx = hex_asc_lo(bcberr); - ptr = hex_byte_pack(ptr, hx); - - ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0); - *ptr = 0; - putpacket(output_buffer); /* send it off... */ - } - - /* - * tell the debugger that an exception has occurred - */ - ptr = output_buffer; - - /* - * Send trap type (converted to signal) - */ - *ptr++ = 'T'; - ptr = hex_byte_pack(ptr, sigval); - - /* - * Send Error PC - */ - ptr = hex_byte_pack(ptr, GDB_REGID_PC); - *ptr++ = ':'; - ptr = mem2hex(®s->pc, ptr, 4, 0); - *ptr++ = ';'; - - /* - * Send frame pointer - */ - ptr = hex_byte_pack(ptr, GDB_REGID_FP); - *ptr++ = ':'; - ptr = mem2hex(®s->a3, ptr, 4, 0); - *ptr++ = ';'; - - /* - * Send stack pointer - */ - ssp = (unsigned long) (regs + 1); - ptr = hex_byte_pack(ptr, GDB_REGID_SP); - *ptr++ = ':'; - ptr = mem2hex(&ssp, ptr, 4, 0); - *ptr++ = ';'; - - *ptr++ = 0; - putpacket(output_buffer); /* send it off... */ - -packet_waiting: - /* - * Wait for input from remote GDB - */ - while (1) { - output_buffer[0] = 0; - getpacket(input_buffer); - - switch (input_buffer[0]) { - /* request repeat of last signal number */ - case '?': - output_buffer[0] = 'S'; - output_buffer[1] = hex_asc_hi(sigval); - output_buffer[2] = hex_asc_lo(sigval); - output_buffer[3] = 0; - break; - - case 'd': - /* toggle debug flag */ - break; - - /* - * Return the value of the CPU registers - */ - case 'g': - zero = 0; - ssp = (u32) (regs + 1); - ptr = output_buffer; - ptr = mem2hex(®s->d0, ptr, 4, 0); - ptr = mem2hex(®s->d1, ptr, 4, 0); - ptr = mem2hex(®s->d2, ptr, 4, 0); - ptr = mem2hex(®s->d3, ptr, 4, 0); - ptr = mem2hex(®s->a0, ptr, 4, 0); - ptr = mem2hex(®s->a1, ptr, 4, 0); - ptr = mem2hex(®s->a2, ptr, 4, 0); - ptr = mem2hex(®s->a3, ptr, 4, 0); - - ptr = mem2hex(&ssp, ptr, 4, 0); /* 8 */ - ptr = mem2hex(®s->pc, ptr, 4, 0); - ptr = mem2hex(®s->mdr, ptr, 4, 0); - ptr = mem2hex(®s->epsw, ptr, 4, 0); - ptr = mem2hex(®s->lir, ptr, 4, 0); - ptr = mem2hex(®s->lar, ptr, 4, 0); - ptr = mem2hex(®s->mdrq, ptr, 4, 0); - - ptr = mem2hex(®s->e0, ptr, 4, 0); /* 15 */ - ptr = mem2hex(®s->e1, ptr, 4, 0); - ptr = mem2hex(®s->e2, ptr, 4, 0); - ptr = mem2hex(®s->e3, ptr, 4, 0); - ptr = mem2hex(®s->e4, ptr, 4, 0); - ptr = mem2hex(®s->e5, ptr, 4, 0); - ptr = mem2hex(®s->e6, ptr, 4, 0); - ptr = mem2hex(®s->e7, ptr, 4, 0); - - ptr = mem2hex(&ssp, ptr, 4, 0); - ptr = mem2hex(®s, ptr, 4, 0); - ptr = mem2hex(®s->sp, ptr, 4, 0); - ptr = mem2hex(®s->mcrh, ptr, 4, 0); /* 26 */ - ptr = mem2hex(®s->mcrl, ptr, 4, 0); - ptr = mem2hex(®s->mcvf, ptr, 4, 0); - - ptr = mem2hex(&gdbstub_fpcr, ptr, 4, 0); /* 29 - FPCR */ - ptr = mem2hex(&zero, ptr, 4, 0); - ptr = mem2hex(&zero, ptr, 4, 0); - for (loop = 0; loop < 32; loop++) - ptr = mem2hex(&gdbstub_fpufs_array[loop], - ptr, 4, 0); /* 32 - FS0-31 */ - - break; - - /* - * set the value of the CPU registers - return OK - */ - case 'G': - { - const char *ptr; - - ptr = &input_buffer[1]; - ptr = hex2mem(ptr, ®s->d0, 4, 0); - ptr = hex2mem(ptr, ®s->d1, 4, 0); - ptr = hex2mem(ptr, ®s->d2, 4, 0); - ptr = hex2mem(ptr, ®s->d3, 4, 0); - ptr = hex2mem(ptr, ®s->a0, 4, 0); - ptr = hex2mem(ptr, ®s->a1, 4, 0); - ptr = hex2mem(ptr, ®s->a2, 4, 0); - ptr = hex2mem(ptr, ®s->a3, 4, 0); - - ptr = hex2mem(ptr, &ssp, 4, 0); /* 8 */ - ptr = hex2mem(ptr, ®s->pc, 4, 0); - ptr = hex2mem(ptr, ®s->mdr, 4, 0); - ptr = hex2mem(ptr, ®s->epsw, 4, 0); - ptr = hex2mem(ptr, ®s->lir, 4, 0); - ptr = hex2mem(ptr, ®s->lar, 4, 0); - ptr = hex2mem(ptr, ®s->mdrq, 4, 0); - - ptr = hex2mem(ptr, ®s->e0, 4, 0); /* 15 */ - ptr = hex2mem(ptr, ®s->e1, 4, 0); - ptr = hex2mem(ptr, ®s->e2, 4, 0); - ptr = hex2mem(ptr, ®s->e3, 4, 0); - ptr = hex2mem(ptr, ®s->e4, 4, 0); - ptr = hex2mem(ptr, ®s->e5, 4, 0); - ptr = hex2mem(ptr, ®s->e6, 4, 0); - ptr = hex2mem(ptr, ®s->e7, 4, 0); - - ptr = hex2mem(ptr, &ssp, 4, 0); - ptr = hex2mem(ptr, &zero, 4, 0); - ptr = hex2mem(ptr, ®s->sp, 4, 0); - ptr = hex2mem(ptr, ®s->mcrh, 4, 0); /* 26 */ - ptr = hex2mem(ptr, ®s->mcrl, 4, 0); - ptr = hex2mem(ptr, ®s->mcvf, 4, 0); - - ptr = hex2mem(ptr, &zero, 4, 0); /* 29 - FPCR */ - ptr = hex2mem(ptr, &zero, 4, 0); - ptr = hex2mem(ptr, &zero, 4, 0); - for (loop = 0; loop < 32; loop++) /* 32 - FS0-31 */ - ptr = hex2mem(ptr, &zero, 4, 0); - -#if 0 - /* - * See if the stack pointer has moved. If so, then copy - * the saved locals and ins to the new location. - */ - unsigned long *newsp = (unsigned long *) registers[SP]; - if (sp != newsp) - sp = memcpy(newsp, sp, 16 * 4); -#endif - - gdbstub_strcpy(output_buffer, "OK"); - } - break; - - /* - * mAA..AA,LLLL Read LLLL bytes at address AA..AA - */ - case 'm': - ptr = &input_buffer[1]; - - if (hexToInt(&ptr, &addr) && - *ptr++ == ',' && - hexToInt(&ptr, &length) - ) { - if (mem2hex((char *) addr, output_buffer, - length, 1)) - break; - gdbstub_strcpy(output_buffer, "E03"); - } else { - gdbstub_strcpy(output_buffer, "E01"); - } - break; - - /* - * MAA..AA,LLLL: Write LLLL bytes at address AA.AA - * return OK - */ - case 'M': - ptr = &input_buffer[1]; - - if (hexToInt(&ptr, &addr) && - *ptr++ == ',' && - hexToInt(&ptr, &length) && - *ptr++ == ':' - ) { - if (hex2mem(ptr, (char *) addr, length, 1)) - gdbstub_strcpy(output_buffer, "OK"); - else - gdbstub_strcpy(output_buffer, "E03"); - - gdbstub_flush_caches = 1; - } else { - gdbstub_strcpy(output_buffer, "E02"); - } - break; - - /* - * cAA..AA Continue at address AA..AA(optional) - */ - case 'c': - /* try to read optional parameter, pc unchanged if no - * parm */ - - ptr = &input_buffer[1]; - if (hexToInt(&ptr, &addr)) - regs->pc = addr; - goto done; - - /* - * kill the program - */ - case 'k' : - goto done; /* just continue */ - - /* - * Reset the whole machine (FIXME: system dependent) - */ - case 'r': - break; - - /* - * Step to next instruction - */ - case 's': - /* Using the T flag doesn't seem to perform single - * stepping (it seems to wind up being caught by the - * JTAG unit), so we have to use breakpoints and - * continue instead. - */ -#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP - if (gdbstub_single_step(regs) < 0) - /* ignore any fault error for now */ - gdbstub_printk("unable to set single-step" - " bp\n"); - goto done; -#else - gdbstub_strcpy(output_buffer, "E01"); - break; -#endif - - /* - * Set baud rate (bBB) - */ - case 'b': - do { - int baudrate; - - ptr = &input_buffer[1]; - if (!hexToInt(&ptr, &baudrate)) { - gdbstub_strcpy(output_buffer, "B01"); - break; - } - - if (baudrate) { - /* ACK before changing speed */ - putpacket("OK"); - gdbstub_io_set_baud(baudrate); - } - } while (0); - break; - - /* - * Set breakpoint - */ - case 'Z': - ptr = &input_buffer[1]; - - if (!hexToInt(&ptr, &loop) || *ptr++ != ',' || - !hexToInt(&ptr, &addr) || *ptr++ != ',' || - !hexToInt(&ptr, &length) - ) { - gdbstub_strcpy(output_buffer, "E01"); - break; - } - - /* only support software breakpoints */ - gdbstub_strcpy(output_buffer, "E03"); - if (loop != 0 || - length < 1 || - length > 7 || - (unsigned long) addr < 4096) - break; - - if (gdbstub_set_breakpoint((u8 *) addr, length) < 0) - break; - - gdbstub_strcpy(output_buffer, "OK"); - break; - - /* - * Clear breakpoint - */ - case 'z': - ptr = &input_buffer[1]; - - if (!hexToInt(&ptr, &loop) || *ptr++ != ',' || - !hexToInt(&ptr, &addr) || *ptr++ != ',' || - !hexToInt(&ptr, &length) - ) { - gdbstub_strcpy(output_buffer, "E01"); - break; - } - - /* only support software breakpoints */ - gdbstub_strcpy(output_buffer, "E03"); - if (loop != 0 || - length < 1 || - length > 7 || - (unsigned long) addr < 4096) - break; - - if (gdbstub_clear_breakpoint((u8 *) addr, length) < 0) - break; - - gdbstub_strcpy(output_buffer, "OK"); - break; - - default: - gdbstub_proto("### GDB Unsupported Cmd '%s'\n", - input_buffer); - break; - } - - /* reply to the request */ - putpacket(output_buffer); - } - -done: - /* - * Need to flush the instruction cache here, as we may - * have deposited a breakpoint, and the icache probably - * has no way of knowing that a data ref to some location - * may have changed something that is in the instruction - * cache. - * NB: We flush both caches, just to be sure... - */ - if (gdbstub_flush_caches) - debugger_local_cache_flushinv(); - - gdbstub_load_fpu(); - mn10300_set_gdbleds(0); - if (excep == EXCEP_NMI) - NMICR = NMICR_NMIF; - - touch_softlockup_watchdog(); - - local_irq_restore(epsw); - return 0; -} - -/* - * Determine if we hit a debugger special breakpoint that needs skipping over - * automatically. - */ -int at_debugger_breakpoint(struct pt_regs *regs) -{ - return 0; -} - -/* - * handle event interception - */ -asmlinkage int debugger_intercept(enum exception_code excep, - int signo, int si_code, struct pt_regs *regs) -{ - static u8 notfirst = 1; - int ret; - - if (gdbstub_busy) - gdbstub_printk("--> gdbstub reentered itself\n"); - gdbstub_busy = 1; - - if (notfirst) { - unsigned long mdr; - asm("mov mdr,%0" : "=d"(mdr)); - - gdbstub_entry( - "--> debugger_intercept(%p,%04x) [MDR=%lx PC=%lx]\n", - regs, excep, mdr, regs->pc); - - gdbstub_entry( - "PC: %08lx EPSW: %08lx SSP: %08lx mode: %s\n", - regs->pc, regs->epsw, (unsigned long) &ret, - user_mode(regs) ? "User" : "Super"); - gdbstub_entry( - "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", - regs->d0, regs->d1, regs->d2, regs->d3); - gdbstub_entry( - "a0: %08lx a1: %08lx a2: %08lx a3: %08lx\n", - regs->a0, regs->a1, regs->a2, regs->a3); - gdbstub_entry( - "e0: %08lx e1: %08lx e2: %08lx e3: %08lx\n", - regs->e0, regs->e1, regs->e2, regs->e3); - gdbstub_entry( - "e4: %08lx e5: %08lx e6: %08lx e7: %08lx\n", - regs->e4, regs->e5, regs->e6, regs->e7); - gdbstub_entry( - "lar: %08lx lir: %08lx mdr: %08lx usp: %08lx\n", - regs->lar, regs->lir, regs->mdr, regs->sp); - gdbstub_entry( - "cvf: %08lx crl: %08lx crh: %08lx drq: %08lx\n", - regs->mcvf, regs->mcrl, regs->mcrh, regs->mdrq); - gdbstub_entry( - "threadinfo=%p task=%p)\n", - current_thread_info(), current); - } else { - notfirst = 1; - } - - ret = gdbstub(regs, excep); - - gdbstub_entry("<-- debugger_intercept()\n"); - gdbstub_busy = 0; - return ret; -} - -/* - * handle the GDB stub itself causing an exception - */ -asmlinkage void gdbstub_exception(struct pt_regs *regs, - enum exception_code excep) -{ - unsigned long mdr; - - asm("mov mdr,%0" : "=d"(mdr)); - gdbstub_entry("--> gdbstub exception({%p},%04x) [MDR=%lx]\n", - regs, excep, mdr); - - while ((unsigned long) regs == 0xffffffff) {} - - /* handle guarded memory accesses where we know it might fault */ - if (regs->pc == (unsigned) gdbstub_read_byte_guard) { - regs->pc = (unsigned) gdbstub_read_byte_cont; - goto fault; - } - - if (regs->pc == (unsigned) gdbstub_read_word_guard) { - regs->pc = (unsigned) gdbstub_read_word_cont; - goto fault; - } - - if (regs->pc == (unsigned) gdbstub_read_dword_guard) { - regs->pc = (unsigned) gdbstub_read_dword_cont; - goto fault; - } - - if (regs->pc == (unsigned) gdbstub_write_byte_guard) { - regs->pc = (unsigned) gdbstub_write_byte_cont; - goto fault; - } - - if (regs->pc == (unsigned) gdbstub_write_word_guard) { - regs->pc = (unsigned) gdbstub_write_word_cont; - goto fault; - } - - if (regs->pc == (unsigned) gdbstub_write_dword_guard) { - regs->pc = (unsigned) gdbstub_write_dword_cont; - goto fault; - } - - gdbstub_printk("\n### GDB stub caused an exception ###\n"); - - /* something went horribly wrong */ - console_verbose(); - show_registers(regs); - - panic("GDB Stub caused an unexpected exception - can't continue\n"); - - /* we caught an attempt by the stub to access silly memory */ -fault: - gdbstub_entry("<-- gdbstub exception() = EFAULT\n"); - regs->d0 = -EFAULT; - return; -} - -/* - * send an exit message to GDB - */ -void gdbstub_exit(int status) -{ - unsigned char checksum; - unsigned char ch; - int count; - - gdbstub_busy = 1; - output_buffer[0] = 'W'; - output_buffer[1] = hex_asc_hi(status); - output_buffer[2] = hex_asc_lo(status); - output_buffer[3] = 0; - - gdbstub_io_tx_char('$'); - checksum = 0; - count = 0; - - while ((ch = output_buffer[count]) != 0) { - gdbstub_io_tx_char(ch); - checksum += ch; - count += 1; - } - - gdbstub_io_tx_char('#'); - gdbstub_io_tx_char(hex_asc_hi(checksum)); - gdbstub_io_tx_char(hex_asc_lo(checksum)); - - /* make sure the output is flushed, or else RedBoot might clobber it */ - gdbstub_io_tx_flush(); - - gdbstub_busy = 0; -} - -/* - * initialise the GDB stub - */ -asmlinkage void __init gdbstub_init(void) -{ -#ifdef CONFIG_GDBSTUB_IMMEDIATE - unsigned char ch; - int ret; -#endif - - gdbstub_busy = 1; - - printk(KERN_INFO "%s", gdbstub_banner); - - gdbstub_io_init(); - - gdbstub_entry("--> gdbstub_init\n"); - - /* try to talk to GDB (or anyone insane enough to want to type GDB - * protocol by hand) */ - gdbstub_io("### GDB Tx ACK\n"); - gdbstub_io_tx_char('+'); /* 'hello world' */ - -#ifdef CONFIG_GDBSTUB_IMMEDIATE - gdbstub_printk("GDB Stub waiting for packet\n"); - - /* in case GDB is started before us, ACK any packets that are already - * sitting there (presumably "$?#xx") - */ - do { gdbstub_io_rx_char(&ch, 0); } while (ch != '$'); - do { gdbstub_io_rx_char(&ch, 0); } while (ch != '#'); - /* eat first csum byte */ - do { ret = gdbstub_io_rx_char(&ch, 0); } while (ret != 0); - /* eat second csum byte */ - do { ret = gdbstub_io_rx_char(&ch, 0); } while (ret != 0); - - gdbstub_io("### GDB Tx NAK\n"); - gdbstub_io_tx_char('-'); /* NAK it */ - -#else - printk("GDB Stub ready\n"); -#endif - - gdbstub_busy = 0; - gdbstub_entry("<-- gdbstub_init\n"); -} - -/* - * register the console at a more appropriate time - */ -#ifdef CONFIG_GDBSTUB_CONSOLE -static int __init gdbstub_postinit(void) -{ - printk(KERN_NOTICE "registering console\n"); - register_console(&gdbstub_console); - return 0; -} - -__initcall(gdbstub_postinit); -#endif - -/* - * handle character reception on GDB serial port - * - jump into the GDB stub if BREAK is detected on the serial line - */ -asmlinkage void gdbstub_rx_irq(struct pt_regs *regs, enum exception_code excep) -{ - char ch; - int ret; - - gdbstub_entry("--> gdbstub_rx_irq\n"); - - do { - ret = gdbstub_io_rx_char(&ch, 1); - if (ret != -EIO && ret != -EAGAIN) { - if (ret != -EINTR) - gdbstub_rx_unget = ch; - gdbstub(regs, excep); - } - } while (ret != -EAGAIN); - - gdbstub_entry("<-- gdbstub_rx_irq\n"); -} diff --git a/arch/mn10300/kernel/head.S b/arch/mn10300/kernel/head.S deleted file mode 100644 index 0b15f759e0d2..000000000000 --- a/arch/mn10300/kernel/head.S +++ /dev/null @@ -1,442 +0,0 @@ -/* Boot entry point for MN10300 kernel - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SMP -#include -#include -#include -#include -#endif /* CONFIG_SMP */ - - __HEAD - -############################################################################### -# -# bootloader entry point -# -############################################################################### - .globl _start - .type _start,@function -_start: -#ifdef CONFIG_SMP - # - # If this is a secondary CPU (AP), then deal with that elsewhere - # - mov (CPUID),d3 - and CPUID_MASK,d3 - bne startup_secondary - - # - # We're dealing with the primary CPU (BP) here, then. - # Keep BP's D0,D1,D2 register for boot check. - # - - # Set up the Boot IPI for each secondary CPU - mov 0x1,a0 -loop_set_secondary_icr: - mov a0,a1 - asl CROSS_ICR_CPU_SHIFT,a1 - add CROSS_GxICR(SMP_BOOT_IRQ,0),a1 - movhu (a1),d3 - or GxICR_ENABLE|GxICR_LEVEL_0,d3 - movhu d3,(a1) - movhu (a1),d3 # flush - inc a0 - cmp NR_CPUS,a0 - bne loop_set_secondary_icr -#endif /* CONFIG_SMP */ - - # save commandline pointer - mov d0,a3 - - # preload the PGD pointer register - mov swapper_pg_dir,d0 - mov d0,(PTBR) - clr d0 - movbu d0,(PIDR) - - # turn on the TLBs - mov MMUCTR_IIV|MMUCTR_DIV,d0 - mov d0,(MMUCTR) -#ifdef CONFIG_AM34_2 - mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0 -#else - mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0 -#endif - mov d0,(MMUCTR) - - # turn on AM33v2 exception handling mode and set the trap table base - movhu (CPUP),d0 - or CPUP_EXM_AM33V2,d0 - movhu d0,(CPUP) - mov CONFIG_INTERRUPT_VECTOR_BASE,d0 - mov d0,(TBR) - - # invalidate and enable both of the caches -#ifdef CONFIG_SMP - mov ECHCTR,a0 - clr d0 - mov d0,(a0) -#endif - mov CHCTR,a0 - clr d0 - movhu d0,(a0) # turn off first - mov CHCTR_ICINV|CHCTR_DCINV,d0 - movhu d0,(a0) - setlb - mov (a0),d0 - btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy - lne - -#ifdef CONFIG_MN10300_CACHE_ENABLED -#ifdef CONFIG_MN10300_CACHE_WBACK -#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 -#else - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0 -#endif /* NOWRALLOC */ -#else - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 -#endif /* WBACK */ - movhu d0,(a0) # enable -#endif /* ENABLED */ - - # turn on RTS on the debug serial port if applicable -#ifdef CONFIG_MN10300_UNIT_ASB2305 - bset UART_MCR_RTS,(ASB2305_DEBUG_MCR) -#endif - - # clear the BSS area - mov __bss_start,a0 - mov __bss_stop,a1 - clr d0 -bssclear: - cmp a1,a0 - bge bssclear_end - mov d0,(a0) - inc4 a0 - bra bssclear -bssclear_end: - - # retrieve the parameters (including command line) before we overwrite - # them - cmp 0xabadcafe,d1 - bne __no_parameters - -__copy_parameters: - mov redboot_command_line,a0 - mov a0,a1 - add COMMAND_LINE_SIZE,a1 -1: - movbu (a3),d0 - inc a3 - movbu d0,(a0) - inc a0 - cmp a1,a0 - blt 1b - - mov redboot_platform_name,a0 - mov a0,a1 - add COMMAND_LINE_SIZE,a1 - mov d2,a3 -1: - movbu (a3),d0 - inc a3 - movbu d0,(a0) - inc a0 - cmp a1,a0 - blt 1b - -__no_parameters: - - # set up the registers with recognisable rubbish in them - mov init_thread_union+THREAD_SIZE-12,sp - - mov 0xea01eaea,d0 - mov d0,(4,sp) # EPSW save area - mov 0xea02eaea,d0 - mov d0,(8,sp) # PC save area - - mov 0xeb0060ed,d0 - mov d0,mdr - mov 0xeb0061ed,d0 - mov d0,mdrq - mov 0xeb0062ed,d0 - mov d0,mcrh - mov 0xeb0063ed,d0 - mov d0,mcrl - mov 0xeb0064ed,d0 - mov d0,mcvf - mov 0xed0065ed,a3 - mov a3,usp - - mov 0xed00e0ed,e0 - mov 0xed00e1ed,e1 - mov 0xed00e2ed,e2 - mov 0xed00e3ed,e3 - mov 0xed00e4ed,e4 - mov 0xed00e5ed,e5 - mov 0xed00e6ed,e6 - mov 0xed00e7ed,e7 - - mov 0xed00d0ed,d0 - mov 0xed00d1ed,d1 - mov 0xed00d2ed,d2 - mov 0xed00d3ed,d3 - mov 0xed00a0ed,a0 - mov 0xed00a1ed,a1 - mov 0xed00a2ed,a2 - mov 0,a3 - - # set up the initial kernel stack - SAVE_ALL - mov 0xffffffff,d0 - mov d0,(REG_ORIG_D0,fp) - - # put different recognisable rubbish in the regs - mov 0xfb0060ed,d0 - mov d0,mdr - mov 0xfb0061ed,d0 - mov d0,mdrq - mov 0xfb0062ed,d0 - mov d0,mcrh - mov 0xfb0063ed,d0 - mov d0,mcrl - mov 0xfb0064ed,d0 - mov d0,mcvf - mov 0xfd0065ed,a0 - mov a0,usp - - mov 0xfd00e0ed,e0 - mov 0xfd00e1ed,e1 - mov 0xfd00e2ed,e2 - mov 0xfd00e3ed,e3 - mov 0xfd00e4ed,e4 - mov 0xfd00e5ed,e5 - mov 0xfd00e6ed,e6 - mov 0xfd00e7ed,e7 - - mov 0xfd00d0ed,d0 - mov 0xfd00d1ed,d1 - mov 0xfd00d2ed,d2 - mov 0xfd00d3ed,d3 - mov 0xfd00a0ed,a0 - mov 0xfd00a1ed,a1 - mov 0xfd00a2ed,a2 - - # we may be holding current in E2 -#ifdef CONFIG_MN10300_CURRENT_IN_E2 - mov init_task,e2 -#endif - - # initialise the processor and the unit - call processor_init[],0 - call unit_init[],0 - -#ifdef CONFIG_SMP - # mark the primary CPU in cpu_boot_map - mov cpu_boot_map,a0 - mov 0x1,d0 - mov d0,(a0) - - # signal each secondary CPU to begin booting - mov 0x1,d2 # CPU ID - -loop_request_boot_secondary: - mov d2,a0 - # send SMP_BOOT_IPI to secondary CPU - asl CROSS_ICR_CPU_SHIFT,a0 - add CROSS_GxICR(SMP_BOOT_IRQ,0),a0 - movhu (a0),d0 - or GxICR_REQUEST|GxICR_DETECT,d0 - movhu d0,(a0) - movhu (a0),d0 # flush - - # wait up to 100ms for AP's IPI to be received - clr d3 -wait_on_secondary_boot: - mov DELAY_TIME_BOOT_IPI,d0 - call __delay[],0 - inc d3 - mov cpu_boot_map,a0 - mov (a0),d0 - lsr d2,d0 - btst 0x1,d0 - bne 1f - cmp TIME_OUT_COUNT_BOOT_IPI,d3 - bne wait_on_secondary_boot -1: - inc d2 - cmp NR_CPUS,d2 - bne loop_request_boot_secondary -#endif /* CONFIG_SMP */ - -#ifdef CONFIG_GDBSTUB - call gdbstub_init[],0 - -#ifdef CONFIG_GDBSTUB_IMMEDIATE - .globl __gdbstub_pause -__gdbstub_pause: - bra __gdbstub_pause -#endif -#endif - - jmp start_kernel - .size _start,.-_start - -############################################################################### -# -# Secondary CPU boot point -# -############################################################################### -#ifdef CONFIG_SMP -startup_secondary: - # preload the PGD pointer register - mov swapper_pg_dir,d0 - mov d0,(PTBR) - clr d0 - movbu d0,(PIDR) - - # turn on the TLBs - mov MMUCTR_IIV|MMUCTR_DIV,d0 - mov d0,(MMUCTR) -#ifdef CONFIG_AM34_2 - mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0 -#else - mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0 -#endif - mov d0,(MMUCTR) - - # turn on AM33v2 exception handling mode and set the trap table base - movhu (CPUP),d0 - or CPUP_EXM_AM33V2,d0 - movhu d0,(CPUP) - - # set the interrupt vector table - mov CONFIG_INTERRUPT_VECTOR_BASE,d0 - mov d0,(TBR) - - # invalidate and enable both of the caches - mov ECHCTR,a0 - clr d0 - mov d0,(a0) - mov CHCTR,a0 - clr d0 - movhu d0,(a0) # turn off first - mov CHCTR_ICINV|CHCTR_DCINV,d0 - movhu d0,(a0) - setlb - mov (a0),d0 - btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer) - lne - -#ifdef CONFIG_MN10300_CACHE_ENABLED -#ifdef CONFIG_MN10300_CACHE_WBACK -#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 -#else - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0 -#endif /* !NOWRALLOC */ -#else - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 -#endif /* WBACK */ - movhu d0,(a0) # enable -#endif /* ENABLED */ - - # Clear the boot IPI interrupt for this CPU - movhu (GxICR(SMP_BOOT_IRQ)),d0 - and ~GxICR_REQUEST,d0 - movhu d0,(GxICR(SMP_BOOT_IRQ)) - movhu (GxICR(SMP_BOOT_IRQ)),d0 # flush - - /* get stack */ - mov CONFIG_INTERRUPT_VECTOR_BASE + CONFIG_BOOT_STACK_OFFSET,a0 - mov (CPUID),d0 - and CPUID_MASK,d0 - mulu CONFIG_BOOT_STACK_SIZE,d0 - sub d0,a0 - mov a0,sp - - # init interrupt for AP - call smp_prepare_cpu_init[],0 - - # mark this secondary CPU in cpu_boot_map - mov (CPUID),d0 - mov 0x1,d1 - asl d0,d1 - mov cpu_boot_map,a0 - bset d1,(a0) - - or EPSW_IE|EPSW_IM_1,epsw # permit level 0 interrupts - nop - nop -#ifdef CONFIG_MN10300_CACHE_WBACK - # flush the local cache if it's in writeback mode - call mn10300_local_dcache_flush_inv[],0 - setlb - mov (CHCTR),d0 - btst CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer) - lne -#endif - - # now sleep waiting for further instructions -secondary_sleep: - mov CPUM_SLEEP,d0 - movhu d0,(CPUM) - nop - nop - bra secondary_sleep - .size startup_secondary,.-startup_secondary -#endif /* CONFIG_SMP */ - -############################################################################### -# -# -# -############################################################################### -ENTRY(__head_end) - -/* - * This is initialized to disallow all access to the low 2G region - * - the high 2G region is managed directly by the MMU - * - range 0x70000000-0x7C000000 are initialised for use by VMALLOC - */ - .section .bss - .balign PAGE_SIZE -ENTRY(swapper_pg_dir) - .space PTRS_PER_PGD*4 - -/* - * The page tables are initialized to only 8MB here - the final page - * tables are set up later depending on memory size. - */ - - .balign PAGE_SIZE -ENTRY(empty_zero_page) - .space PAGE_SIZE - - .balign PAGE_SIZE -ENTRY(large_page_table) - .space PAGE_SIZE - - .balign PAGE_SIZE -ENTRY(kernel_vmalloc_ptes) - .space ((VMALLOC_END-VMALLOC_START)/PAGE_SIZE)*4 diff --git a/arch/mn10300/kernel/internal.h b/arch/mn10300/kernel/internal.h deleted file mode 100644 index 561785581f6c..000000000000 --- a/arch/mn10300/kernel/internal.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Internal definitions for the arch part of the core kernel - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include - -struct clocksource; -struct clock_event_device; - -/* - * entry.S - */ -extern void ret_from_fork(struct task_struct *) __attribute__((noreturn)); -extern void ret_from_kernel_thread(struct task_struct *) __attribute__((noreturn)); - -/* - * smp-low.S - */ -#ifdef CONFIG_SMP -extern void mn10300_low_ipi_handler(void); -#endif - -/* - * smp.c - */ -#ifdef CONFIG_SMP -extern void smp_jump_to_debugger(void); -#endif - -/* - * time.c - */ -extern irqreturn_t local_timer_interrupt(void); diff --git a/arch/mn10300/kernel/io.c b/arch/mn10300/kernel/io.c deleted file mode 100644 index e96fdf6bb542..000000000000 --- a/arch/mn10300/kernel/io.c +++ /dev/null @@ -1,30 +0,0 @@ -/* MN10300 Misaligned multibyte-word I/O - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include - -/* - * output data from a potentially misaligned buffer - */ -void __outsl(unsigned long addr, const void *buffer, int count) -{ - const unsigned char *buf = buffer; - unsigned long val; - - while (count--) { - memcpy(&val, buf, 4); - outl(val, addr); - buf += 4; - } -} -EXPORT_SYMBOL(__outsl); diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c deleted file mode 100644 index c716437baa2c..000000000000 --- a/arch/mn10300/kernel/irq.c +++ /dev/null @@ -1,356 +0,0 @@ -/* MN10300 Arch-specific interrupt handling - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include - -unsigned long __mn10300_irq_enabled_epsw[NR_CPUS] __cacheline_aligned_in_smp = { - [0 ... NR_CPUS - 1] = EPSW_IE | EPSW_IM_7 -}; -EXPORT_SYMBOL(__mn10300_irq_enabled_epsw); - -#ifdef CONFIG_SMP -static char irq_affinity_online[NR_IRQS] = { - [0 ... NR_IRQS - 1] = 0 -}; - -#define NR_IRQ_WORDS ((NR_IRQS + 31) / 32) -static unsigned long irq_affinity_request[NR_IRQ_WORDS] = { - [0 ... NR_IRQ_WORDS - 1] = 0 -}; -#endif /* CONFIG_SMP */ - -atomic_t irq_err_count; - -/* - * MN10300 interrupt controller operations - */ -static void mn10300_cpupic_ack(struct irq_data *d) -{ - unsigned int irq = d->irq; - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - GxICR_u8(irq) = GxICR_DETECT; - tmp = GxICR(irq); - arch_local_irq_restore(flags); -} - -static void __mask_and_set_icr(unsigned int irq, - unsigned int mask, unsigned int set) -{ - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - tmp = GxICR(irq); - GxICR(irq) = (tmp & mask) | set; - tmp = GxICR(irq); - arch_local_irq_restore(flags); -} - -static void mn10300_cpupic_mask(struct irq_data *d) -{ - __mask_and_set_icr(d->irq, GxICR_LEVEL, 0); -} - -static void mn10300_cpupic_mask_ack(struct irq_data *d) -{ - unsigned int irq = d->irq; -#ifdef CONFIG_SMP - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - - if (!test_and_clear_bit(irq, irq_affinity_request)) { - tmp = GxICR(irq); - GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; - tmp = GxICR(irq); - } else { - u16 tmp2; - tmp = GxICR(irq); - GxICR(irq) = (tmp & GxICR_LEVEL); - tmp2 = GxICR(irq); - - irq_affinity_online[irq] = - cpumask_any_and(irq_data_get_affinity_mask(d), - cpu_online_mask); - CROSS_GxICR(irq, irq_affinity_online[irq]) = - (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT; - tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); - } - - arch_local_irq_restore(flags); -#else /* CONFIG_SMP */ - __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_DETECT); -#endif /* CONFIG_SMP */ -} - -static void mn10300_cpupic_unmask(struct irq_data *d) -{ - __mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE); -} - -static void mn10300_cpupic_unmask_clear(struct irq_data *d) -{ - unsigned int irq = d->irq; - /* the MN10300 PIC latches its interrupt request bit, even after the - * device has ceased to assert its interrupt line and the interrupt - * channel has been disabled in the PIC, so for level-triggered - * interrupts we need to clear the request bit when we re-enable */ -#ifdef CONFIG_SMP - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - - if (!test_and_clear_bit(irq, irq_affinity_request)) { - tmp = GxICR(irq); - GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; - tmp = GxICR(irq); - } else { - tmp = GxICR(irq); - - irq_affinity_online[irq] = cpumask_any_and(irq_data_get_affinity_mask(d), - cpu_online_mask); - CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; - tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); - } - - arch_local_irq_restore(flags); -#else /* CONFIG_SMP */ - __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE | GxICR_DETECT); -#endif /* CONFIG_SMP */ -} - -#ifdef CONFIG_SMP -static int -mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask, - bool force) -{ - unsigned long flags; - - flags = arch_local_cli_save(); - set_bit(d->irq, irq_affinity_request); - arch_local_irq_restore(flags); - return 0; -} -#endif /* CONFIG_SMP */ - -/* - * MN10300 PIC level-triggered IRQ handling. - * - * The PIC has no 'ACK' function per se. It is possible to clear individual - * channel latches, but each latch relatches whether or not the channel is - * masked, so we need to clear the latch when we unmask the channel. - * - * Also for this reason, we don't supply an ack() op (it's unused anyway if - * mask_ack() is provided), and mask_ack() just masks. - */ -static struct irq_chip mn10300_cpu_pic_level = { - .name = "cpu_l", - .irq_disable = mn10300_cpupic_mask, - .irq_enable = mn10300_cpupic_unmask_clear, - .irq_ack = NULL, - .irq_mask = mn10300_cpupic_mask, - .irq_mask_ack = mn10300_cpupic_mask, - .irq_unmask = mn10300_cpupic_unmask_clear, -#ifdef CONFIG_SMP - .irq_set_affinity = mn10300_cpupic_setaffinity, -#endif -}; - -/* - * MN10300 PIC edge-triggered IRQ handling. - * - * We use the latch clearing function of the PIC as the 'ACK' function. - */ -static struct irq_chip mn10300_cpu_pic_edge = { - .name = "cpu_e", - .irq_disable = mn10300_cpupic_mask, - .irq_enable = mn10300_cpupic_unmask, - .irq_ack = mn10300_cpupic_ack, - .irq_mask = mn10300_cpupic_mask, - .irq_mask_ack = mn10300_cpupic_mask_ack, - .irq_unmask = mn10300_cpupic_unmask, -#ifdef CONFIG_SMP - .irq_set_affinity = mn10300_cpupic_setaffinity, -#endif -}; - -/* - * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves. - */ -void ack_bad_irq(int irq) -{ - printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq); -} - -/* - * change the level at which an IRQ executes - * - must not be called whilst interrupts are being processed! - */ -void set_intr_level(int irq, u16 level) -{ - BUG_ON(in_interrupt()); - - __mask_and_set_icr(irq, GxICR_ENABLE, level); -} - -/* - * mark an interrupt to be ACK'd after interrupt handlers have been run rather - * than before - */ -void mn10300_set_lateack_irq_type(int irq) -{ - irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level, - handle_level_irq); -} - -/* - * initialise the interrupt system - */ -void __init init_IRQ(void) -{ - int irq; - - for (irq = 0; irq < NR_IRQS; irq++) - if (irq_get_chip(irq) == &no_irq_chip) - /* due to the PIC latching interrupt requests, even - * when the IRQ is disabled, IRQ_PENDING is superfluous - * and we can use handle_level_irq() for edge-triggered - * interrupts */ - irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge, - handle_level_irq); - - unit_init_IRQ(); -} - -/* - * handle normal device IRQs - */ -asmlinkage void do_IRQ(void) -{ - unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw; - unsigned int cpu_id = smp_processor_id(); - int irq; - - sp = current_stack_pointer(); - BUG_ON(sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN); - - /* make sure local_irq_enable() doesn't muck up the interrupt priority - * setting in EPSW */ - old_irq_enabled_epsw = __mn10300_irq_enabled_epsw[cpu_id]; - local_save_flags(epsw); - __mn10300_irq_enabled_epsw[cpu_id] = EPSW_IE | (EPSW_IM & epsw); - irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL; - -#ifdef CONFIG_MN10300_WD_TIMER - __IRQ_STAT(cpu_id, __irq_count)++; -#endif - - irq_enter(); - - for (;;) { - /* ask the interrupt controller for the next IRQ to process - * - the result we get depends on EPSW.IM - */ - irq = IAGR & IAGR_GN; - if (!irq) - break; - - local_irq_restore(irq_disabled_epsw); - - generic_handle_irq(irq >> 2); - - /* restore IRQ controls for IAGR access */ - local_irq_restore(epsw); - } - - __mn10300_irq_enabled_epsw[cpu_id] = old_irq_enabled_epsw; - - irq_exit(); -} - -/* - * Display interrupt management information through /proc/interrupts - */ -int arch_show_interrupts(struct seq_file *p, int prec) -{ -#ifdef CONFIG_MN10300_WD_TIMER - int j; - - seq_printf(p, "%*s: ", prec, "NMI"); - for (j = 0; j < NR_CPUS; j++) - if (cpu_online(j)) - seq_printf(p, "%10u ", nmi_count(j)); - seq_putc(p, '\n'); -#endif - - seq_printf(p, "%*s: ", prec, "ERR"); - seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); - return 0; -} - -#ifdef CONFIG_HOTPLUG_CPU -void migrate_irqs(void) -{ - int irq; - unsigned int self, new; - unsigned long flags; - - self = smp_processor_id(); - for (irq = 0; irq < NR_IRQS; irq++) { - struct irq_data *data = irq_get_irq_data(irq); - struct cpumask *mask = irq_data_get_affinity_mask(data); - - if (irqd_is_per_cpu(data)) - continue; - - if (cpumask_test_cpu(self, mask) && - !cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) { - int cpu_id; - cpu_id = cpumask_first(cpu_online_mask); - cpumask_set_cpu(cpu_id, mask); - } - /* We need to operate irq_affinity_online atomically. */ - arch_local_cli_save(flags); - if (irq_affinity_online[irq] == self) { - u16 x, tmp; - - x = GxICR(irq); - GxICR(irq) = x & GxICR_LEVEL; - tmp = GxICR(irq); - - new = cpumask_any_and(mask, cpu_online_mask); - irq_affinity_online[irq] = new; - - CROSS_GxICR(irq, new) = - (x & GxICR_LEVEL) | GxICR_DETECT; - tmp = CROSS_GxICR(irq, new); - - x &= GxICR_LEVEL | GxICR_ENABLE; - if (GxICR(irq) & GxICR_REQUEST) - x |= GxICR_REQUEST | GxICR_DETECT; - CROSS_GxICR(irq, new) = x; - tmp = CROSS_GxICR(irq, new); - } - arch_local_irq_restore(flags); - } -} -#endif /* CONFIG_HOTPLUG_CPU */ diff --git a/arch/mn10300/kernel/kgdb.c b/arch/mn10300/kernel/kgdb.c deleted file mode 100644 index 2d7986c386fe..000000000000 --- a/arch/mn10300/kernel/kgdb.c +++ /dev/null @@ -1,502 +0,0 @@ -/* kgdb support for MN10300 - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -/* - * Software single-stepping breakpoint save (used by __switch_to()) - */ -static struct thread_info *kgdb_sstep_thread; -u8 *kgdb_sstep_bp_addr[2]; -u8 kgdb_sstep_bp[2]; - -/* - * Copy kernel exception frame registers to the GDB register file - */ -void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - unsigned long ssp = (unsigned long) (regs + 1); - - gdb_regs[GDB_FR_D0] = regs->d0; - gdb_regs[GDB_FR_D1] = regs->d1; - gdb_regs[GDB_FR_D2] = regs->d2; - gdb_regs[GDB_FR_D3] = regs->d3; - gdb_regs[GDB_FR_A0] = regs->a0; - gdb_regs[GDB_FR_A1] = regs->a1; - gdb_regs[GDB_FR_A2] = regs->a2; - gdb_regs[GDB_FR_A3] = regs->a3; - gdb_regs[GDB_FR_SP] = (regs->epsw & EPSW_nSL) ? regs->sp : ssp; - gdb_regs[GDB_FR_PC] = regs->pc; - gdb_regs[GDB_FR_MDR] = regs->mdr; - gdb_regs[GDB_FR_EPSW] = regs->epsw; - gdb_regs[GDB_FR_LIR] = regs->lir; - gdb_regs[GDB_FR_LAR] = regs->lar; - gdb_regs[GDB_FR_MDRQ] = regs->mdrq; - gdb_regs[GDB_FR_E0] = regs->e0; - gdb_regs[GDB_FR_E1] = regs->e1; - gdb_regs[GDB_FR_E2] = regs->e2; - gdb_regs[GDB_FR_E3] = regs->e3; - gdb_regs[GDB_FR_E4] = regs->e4; - gdb_regs[GDB_FR_E5] = regs->e5; - gdb_regs[GDB_FR_E6] = regs->e6; - gdb_regs[GDB_FR_E7] = regs->e7; - gdb_regs[GDB_FR_SSP] = ssp; - gdb_regs[GDB_FR_MSP] = 0; - gdb_regs[GDB_FR_USP] = regs->sp; - gdb_regs[GDB_FR_MCRH] = regs->mcrh; - gdb_regs[GDB_FR_MCRL] = regs->mcrl; - gdb_regs[GDB_FR_MCVF] = regs->mcvf; - gdb_regs[GDB_FR_DUMMY0] = 0; - gdb_regs[GDB_FR_DUMMY1] = 0; - gdb_regs[GDB_FR_FS0] = 0; -} - -/* - * Extracts kernel SP/PC values understandable by gdb from the values - * saved by switch_to(). - */ -void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) -{ - gdb_regs[GDB_FR_SSP] = p->thread.sp; - gdb_regs[GDB_FR_PC] = p->thread.pc; - gdb_regs[GDB_FR_A3] = p->thread.a3; - gdb_regs[GDB_FR_USP] = p->thread.usp; - gdb_regs[GDB_FR_FPCR] = p->thread.fpu_state.fpcr; -} - -/* - * Fill kernel exception frame registers from the GDB register file - */ -void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - regs->d0 = gdb_regs[GDB_FR_D0]; - regs->d1 = gdb_regs[GDB_FR_D1]; - regs->d2 = gdb_regs[GDB_FR_D2]; - regs->d3 = gdb_regs[GDB_FR_D3]; - regs->a0 = gdb_regs[GDB_FR_A0]; - regs->a1 = gdb_regs[GDB_FR_A1]; - regs->a2 = gdb_regs[GDB_FR_A2]; - regs->a3 = gdb_regs[GDB_FR_A3]; - regs->sp = gdb_regs[GDB_FR_SP]; - regs->pc = gdb_regs[GDB_FR_PC]; - regs->mdr = gdb_regs[GDB_FR_MDR]; - regs->epsw = gdb_regs[GDB_FR_EPSW]; - regs->lir = gdb_regs[GDB_FR_LIR]; - regs->lar = gdb_regs[GDB_FR_LAR]; - regs->mdrq = gdb_regs[GDB_FR_MDRQ]; - regs->e0 = gdb_regs[GDB_FR_E0]; - regs->e1 = gdb_regs[GDB_FR_E1]; - regs->e2 = gdb_regs[GDB_FR_E2]; - regs->e3 = gdb_regs[GDB_FR_E3]; - regs->e4 = gdb_regs[GDB_FR_E4]; - regs->e5 = gdb_regs[GDB_FR_E5]; - regs->e6 = gdb_regs[GDB_FR_E6]; - regs->e7 = gdb_regs[GDB_FR_E7]; - regs->sp = gdb_regs[GDB_FR_SSP]; - /* gdb_regs[GDB_FR_MSP]; */ - // regs->usp = gdb_regs[GDB_FR_USP]; - regs->mcrh = gdb_regs[GDB_FR_MCRH]; - regs->mcrl = gdb_regs[GDB_FR_MCRL]; - regs->mcvf = gdb_regs[GDB_FR_MCVF]; - /* gdb_regs[GDB_FR_DUMMY0]; */ - /* gdb_regs[GDB_FR_DUMMY1]; */ - - // regs->fpcr = gdb_regs[GDB_FR_FPCR]; - // regs->fs0 = gdb_regs[GDB_FR_FS0]; -} - -struct kgdb_arch arch_kgdb_ops = { - .gdb_bpt_instr = { 0xff }, - .flags = KGDB_HW_BREAKPOINT, -}; - -static const unsigned char mn10300_kgdb_insn_sizes[256] = -{ - /* 1 2 3 4 5 6 7 8 9 a b c d e f */ - 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */ - 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */ - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */ - 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */ - 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */ - 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */ -}; - -/* - * Attempt to emulate single stepping by means of breakpoint instructions. - * Although there is a single-step trace flag in EPSW, its use is not - * sufficiently documented and is only intended for use with the JTAG debugger. - */ -static int kgdb_arch_do_singlestep(struct pt_regs *regs) -{ - unsigned long arg; - unsigned size; - u8 *pc = (u8 *)regs->pc, *sp = (u8 *)(regs + 1), cur; - u8 *x = NULL, *y = NULL; - int ret; - - ret = probe_kernel_read(&cur, pc, 1); - if (ret < 0) - return ret; - - size = mn10300_kgdb_insn_sizes[cur]; - if (size > 0) { - x = pc + size; - goto set_x; - } - - switch (cur) { - /* Bxx (d8,PC) */ - case 0xc0 ... 0xca: - ret = probe_kernel_read(&arg, pc + 1, 1); - if (ret < 0) - return ret; - x = pc + 2; - if (arg >= 0 && arg <= 2) - goto set_x; - y = pc + (s8)arg; - goto set_x_and_y; - - /* LXX (d8,PC) */ - case 0xd0 ... 0xda: - x = pc + 1; - if (regs->pc == regs->lar) - goto set_x; - y = (u8 *)regs->lar; - goto set_x_and_y; - - /* SETLB - loads the next four bytes into the LIR register - * (which mustn't include a breakpoint instruction) */ - case 0xdb: - x = pc + 5; - goto set_x; - - /* JMP (d16,PC) or CALL (d16,PC) */ - case 0xcc: - case 0xcd: - ret = probe_kernel_read(&arg, pc + 1, 2); - if (ret < 0) - return ret; - x = pc + (s16)arg; - goto set_x; - - /* JMP (d32,PC) or CALL (d32,PC) */ - case 0xdc: - case 0xdd: - ret = probe_kernel_read(&arg, pc + 1, 4); - if (ret < 0) - return ret; - x = pc + (s32)arg; - goto set_x; - - /* RETF */ - case 0xde: - x = (u8 *)regs->mdr; - goto set_x; - - /* RET */ - case 0xdf: - ret = probe_kernel_read(&arg, pc + 2, 1); - if (ret < 0) - return ret; - ret = probe_kernel_read(&x, sp + (s8)arg, 4); - if (ret < 0) - return ret; - goto set_x; - - case 0xf0: - ret = probe_kernel_read(&cur, pc + 1, 1); - if (ret < 0) - return ret; - - if (cur >= 0xf0 && cur <= 0xf7) { - /* JMP (An) / CALLS (An) */ - switch (cur & 3) { - case 0: x = (u8 *)regs->a0; break; - case 1: x = (u8 *)regs->a1; break; - case 2: x = (u8 *)regs->a2; break; - case 3: x = (u8 *)regs->a3; break; - } - goto set_x; - } else if (cur == 0xfc) { - /* RETS */ - ret = probe_kernel_read(&x, sp, 4); - if (ret < 0) - return ret; - goto set_x; - } else if (cur == 0xfd) { - /* RTI */ - ret = probe_kernel_read(&x, sp + 4, 4); - if (ret < 0) - return ret; - goto set_x; - } else { - x = pc + 2; - goto set_x; - } - break; - - /* potential 3-byte conditional branches */ - case 0xf8: - ret = probe_kernel_read(&cur, pc + 1, 1); - if (ret < 0) - return ret; - x = pc + 3; - - if (cur >= 0xe8 && cur <= 0xeb) { - ret = probe_kernel_read(&arg, pc + 2, 1); - if (ret < 0) - return ret; - if (arg >= 0 && arg <= 3) - goto set_x; - y = pc + (s8)arg; - goto set_x_and_y; - } - goto set_x; - - case 0xfa: - ret = probe_kernel_read(&cur, pc + 1, 1); - if (ret < 0) - return ret; - - if (cur == 0xff) { - /* CALLS (d16,PC) */ - ret = probe_kernel_read(&arg, pc + 2, 2); - if (ret < 0) - return ret; - x = pc + (s16)arg; - goto set_x; - } - - x = pc + 4; - goto set_x; - - case 0xfc: - ret = probe_kernel_read(&cur, pc + 1, 1); - if (ret < 0) - return ret; - - if (cur == 0xff) { - /* CALLS (d32,PC) */ - ret = probe_kernel_read(&arg, pc + 2, 4); - if (ret < 0) - return ret; - x = pc + (s32)arg; - goto set_x; - } - - x = pc + 6; - goto set_x; - } - - return 0; - -set_x: - kgdb_sstep_bp_addr[0] = x; - kgdb_sstep_bp_addr[1] = NULL; - ret = probe_kernel_read(&kgdb_sstep_bp[0], x, 1); - if (ret < 0) - return ret; - ret = probe_kernel_write(x, &arch_kgdb_ops.gdb_bpt_instr, 1); - if (ret < 0) - return ret; - kgdb_sstep_thread = current_thread_info(); - debugger_local_cache_flushinv_one(x); - return ret; - -set_x_and_y: - kgdb_sstep_bp_addr[0] = x; - kgdb_sstep_bp_addr[1] = y; - ret = probe_kernel_read(&kgdb_sstep_bp[0], x, 1); - if (ret < 0) - return ret; - ret = probe_kernel_read(&kgdb_sstep_bp[1], y, 1); - if (ret < 0) - return ret; - ret = probe_kernel_write(x, &arch_kgdb_ops.gdb_bpt_instr, 1); - if (ret < 0) - return ret; - ret = probe_kernel_write(y, &arch_kgdb_ops.gdb_bpt_instr, 1); - if (ret < 0) { - probe_kernel_write(kgdb_sstep_bp_addr[0], - &kgdb_sstep_bp[0], 1); - } else { - kgdb_sstep_thread = current_thread_info(); - } - debugger_local_cache_flushinv_one(x); - debugger_local_cache_flushinv_one(y); - return ret; -} - -/* - * Remove emplaced single-step breakpoints, returning true if we hit one of - * them. - */ -static bool kgdb_arch_undo_singlestep(struct pt_regs *regs) -{ - bool hit = false; - u8 *x = kgdb_sstep_bp_addr[0], *y = kgdb_sstep_bp_addr[1]; - u8 opcode; - - if (kgdb_sstep_thread == current_thread_info()) { - if (x) { - if (x == (u8 *)regs->pc) - hit = true; - if (probe_kernel_read(&opcode, x, - 1) < 0 || - opcode != 0xff) - BUG(); - probe_kernel_write(x, &kgdb_sstep_bp[0], 1); - debugger_local_cache_flushinv_one(x); - } - if (y) { - if (y == (u8 *)regs->pc) - hit = true; - if (probe_kernel_read(&opcode, y, - 1) < 0 || - opcode != 0xff) - BUG(); - probe_kernel_write(y, &kgdb_sstep_bp[1], 1); - debugger_local_cache_flushinv_one(y); - } - } - - kgdb_sstep_bp_addr[0] = NULL; - kgdb_sstep_bp_addr[1] = NULL; - kgdb_sstep_thread = NULL; - return hit; -} - -/* - * Catch a single-step-pending thread being deleted and make sure the global - * single-step state is cleared. At this point the breakpoints should have - * been removed by __switch_to(). - */ -void arch_release_thread_stack(unsigned long *stack) -{ - struct thread_info *ti = (void *)stack; - if (kgdb_sstep_thread == ti) { - kgdb_sstep_thread = NULL; - - /* However, we may now be running in degraded mode, with most - * of the CPUs disabled until such a time as KGDB is reentered, - * so force immediate reentry */ - kgdb_breakpoint(); - } -} - -/* - * Handle unknown packets and [CcsDk] packets - * - at this point breakpoints have been installed - */ -int kgdb_arch_handle_exception(int vector, int signo, int err_code, - char *remcom_in_buffer, char *remcom_out_buffer, - struct pt_regs *regs) -{ - long addr; - char *ptr; - - switch (remcom_in_buffer[0]) { - case 'c': - case 's': - /* try to read optional parameter, pc unchanged if no parm */ - ptr = &remcom_in_buffer[1]; - if (kgdb_hex2long(&ptr, &addr)) - regs->pc = addr; - case 'D': - case 'k': - atomic_set(&kgdb_cpu_doing_single_step, -1); - - if (remcom_in_buffer[0] == 's') { - kgdb_arch_do_singlestep(regs); - kgdb_single_step = 1; - atomic_set(&kgdb_cpu_doing_single_step, - raw_smp_processor_id()); - } - return 0; - } - return -1; /* this means that we do not want to exit from the handler */ -} - -/* - * Handle event interception - * - returns 0 if the exception should be skipped, -ERROR otherwise. - */ -int debugger_intercept(enum exception_code excep, int signo, int si_code, - struct pt_regs *regs) -{ - int ret; - - if (kgdb_arch_undo_singlestep(regs)) { - excep = EXCEP_TRAP; - signo = SIGTRAP; - si_code = TRAP_TRACE; - } - - ret = kgdb_handle_exception(excep, signo, si_code, regs); - - debugger_local_cache_flushinv(); - - return ret; -} - -/* - * Determine if we've hit a debugger special breakpoint - */ -int at_debugger_breakpoint(struct pt_regs *regs) -{ - return regs->pc == (unsigned long)&__arch_kgdb_breakpoint; -} - -/* - * Initialise kgdb - */ -int kgdb_arch_init(void) -{ - return 0; -} - -/* - * Do something, perhaps, but don't know what. - */ -void kgdb_arch_exit(void) -{ -} - -#ifdef CONFIG_SMP -void debugger_nmi_interrupt(struct pt_regs *regs, enum exception_code code) -{ - kgdb_nmicallback(arch_smp_processor_id(), regs); - debugger_local_cache_flushinv(); -} - -void kgdb_roundup_cpus(unsigned long flags) -{ - smp_jump_to_debugger(); -} -#endif diff --git a/arch/mn10300/kernel/kprobes.c b/arch/mn10300/kernel/kprobes.c deleted file mode 100644 index 0311a7fcea16..000000000000 --- a/arch/mn10300/kernel/kprobes.c +++ /dev/null @@ -1,656 +0,0 @@ -/* MN10300 Kernel probes implementation - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by Mark Salter (msalter@redhat.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public Licence as published by - * the Free Software Foundation; either version 2 of the Licence, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public Licence for more details. - * - * You should have received a copy of the GNU General Public Licence - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include - -struct kretprobe_blackpoint kretprobe_blacklist[] = { { NULL, NULL } }; -const int kretprobe_blacklist_size = ARRAY_SIZE(kretprobe_blacklist); - -/* kprobe_status settings */ -#define KPROBE_HIT_ACTIVE 0x00000001 -#define KPROBE_HIT_SS 0x00000002 - -static struct kprobe *cur_kprobe; -static unsigned long cur_kprobe_orig_pc; -static unsigned long cur_kprobe_next_pc; -static int cur_kprobe_ss_flags; -static unsigned long kprobe_status; -static kprobe_opcode_t cur_kprobe_ss_buf[MAX_INSN_SIZE + 2]; -static unsigned long cur_kprobe_bp_addr; - -DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; - - -/* singlestep flag bits */ -#define SINGLESTEP_BRANCH 1 -#define SINGLESTEP_PCREL 2 - -#define READ_BYTE(p, valp) \ - do { *(u8 *)(valp) = *(u8 *)(p); } while (0) - -#define READ_WORD16(p, valp) \ - do { \ - READ_BYTE((p), (valp)); \ - READ_BYTE((u8 *)(p) + 1, (u8 *)(valp) + 1); \ - } while (0) - -#define READ_WORD32(p, valp) \ - do { \ - READ_BYTE((p), (valp)); \ - READ_BYTE((u8 *)(p) + 1, (u8 *)(valp) + 1); \ - READ_BYTE((u8 *)(p) + 2, (u8 *)(valp) + 2); \ - READ_BYTE((u8 *)(p) + 3, (u8 *)(valp) + 3); \ - } while (0) - - -static const u8 mn10300_insn_sizes[256] = -{ - /* 1 2 3 4 5 6 7 8 9 a b c d e f */ - 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */ - 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */ - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */ - 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */ - 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */ - 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */ - 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */ -}; - -#define LT (1 << 0) -#define GT (1 << 1) -#define GE (1 << 2) -#define LE (1 << 3) -#define CS (1 << 4) -#define HI (1 << 5) -#define CC (1 << 6) -#define LS (1 << 7) -#define EQ (1 << 8) -#define NE (1 << 9) -#define RA (1 << 10) -#define VC (1 << 11) -#define VS (1 << 12) -#define NC (1 << 13) -#define NS (1 << 14) - -static const u16 cond_table[] = { - /* V C N Z */ - /* 0 0 0 0 */ (NE | NC | CC | VC | GE | GT | HI), - /* 0 0 0 1 */ (EQ | NC | CC | VC | GE | LE | LS), - /* 0 0 1 0 */ (NE | NS | CC | VC | LT | LE | HI), - /* 0 0 1 1 */ (EQ | NS | CC | VC | LT | LE | LS), - /* 0 1 0 0 */ (NE | NC | CS | VC | GE | GT | LS), - /* 0 1 0 1 */ (EQ | NC | CS | VC | GE | LE | LS), - /* 0 1 1 0 */ (NE | NS | CS | VC | LT | LE | LS), - /* 0 1 1 1 */ (EQ | NS | CS | VC | LT | LE | LS), - /* 1 0 0 0 */ (NE | NC | CC | VS | LT | LE | HI), - /* 1 0 0 1 */ (EQ | NC | CC | VS | LT | LE | LS), - /* 1 0 1 0 */ (NE | NS | CC | VS | GE | GT | HI), - /* 1 0 1 1 */ (EQ | NS | CC | VS | GE | LE | LS), - /* 1 1 0 0 */ (NE | NC | CS | VS | LT | LE | LS), - /* 1 1 0 1 */ (EQ | NC | CS | VS | LT | LE | LS), - /* 1 1 1 0 */ (NE | NS | CS | VS | GE | GT | LS), - /* 1 1 1 1 */ (EQ | NS | CS | VS | GE | LE | LS), -}; - -/* - * Calculate what the PC will be after executing next instruction - */ -static unsigned find_nextpc(struct pt_regs *regs, int *flags) -{ - unsigned size; - s8 x8; - s16 x16; - s32 x32; - u8 opc, *pc, *sp, *next; - - next = 0; - *flags = SINGLESTEP_PCREL; - - pc = (u8 *) regs->pc; - sp = (u8 *) (regs + 1); - opc = *pc; - - size = mn10300_insn_sizes[opc]; - if (size > 0) { - next = pc + size; - } else { - switch (opc) { - /* Bxx (d8,PC) */ - case 0xc0 ... 0xca: - x8 = 2; - if (cond_table[regs->epsw & 0xf] & (1 << (opc & 0xf))) - x8 = (s8)pc[1]; - next = pc + x8; - *flags |= SINGLESTEP_BRANCH; - break; - - /* JMP (d16,PC) or CALL (d16,PC) */ - case 0xcc: - case 0xcd: - READ_WORD16(pc + 1, &x16); - next = pc + x16; - *flags |= SINGLESTEP_BRANCH; - break; - - /* JMP (d32,PC) or CALL (d32,PC) */ - case 0xdc: - case 0xdd: - READ_WORD32(pc + 1, &x32); - next = pc + x32; - *flags |= SINGLESTEP_BRANCH; - break; - - /* RETF */ - case 0xde: - next = (u8 *)regs->mdr; - *flags &= ~SINGLESTEP_PCREL; - *flags |= SINGLESTEP_BRANCH; - break; - - /* RET */ - case 0xdf: - sp += pc[2]; - READ_WORD32(sp, &x32); - next = (u8 *)x32; - *flags &= ~SINGLESTEP_PCREL; - *flags |= SINGLESTEP_BRANCH; - break; - - case 0xf0: - next = pc + 2; - opc = pc[1]; - if (opc >= 0xf0 && opc <= 0xf7) { - /* JMP (An) / CALLS (An) */ - switch (opc & 3) { - case 0: - next = (u8 *)regs->a0; - break; - case 1: - next = (u8 *)regs->a1; - break; - case 2: - next = (u8 *)regs->a2; - break; - case 3: - next = (u8 *)regs->a3; - break; - } - *flags &= ~SINGLESTEP_PCREL; - *flags |= SINGLESTEP_BRANCH; - } else if (opc == 0xfc) { - /* RETS */ - READ_WORD32(sp, &x32); - next = (u8 *)x32; - *flags &= ~SINGLESTEP_PCREL; - *flags |= SINGLESTEP_BRANCH; - } else if (opc == 0xfd) { - /* RTI */ - READ_WORD32(sp + 4, &x32); - next = (u8 *)x32; - *flags &= ~SINGLESTEP_PCREL; - *flags |= SINGLESTEP_BRANCH; - } - break; - - /* potential 3-byte conditional branches */ - case 0xf8: - next = pc + 3; - opc = pc[1]; - if (opc >= 0xe8 && opc <= 0xeb && - (cond_table[regs->epsw & 0xf] & - (1 << ((opc & 0xf) + 3))) - ) { - READ_BYTE(pc+2, &x8); - next = pc + x8; - *flags |= SINGLESTEP_BRANCH; - } - break; - - case 0xfa: - if (pc[1] == 0xff) { - /* CALLS (d16,PC) */ - READ_WORD16(pc + 2, &x16); - next = pc + x16; - } else - next = pc + 4; - *flags |= SINGLESTEP_BRANCH; - break; - - case 0xfc: - x32 = 6; - if (pc[1] == 0xff) { - /* CALLS (d32,PC) */ - READ_WORD32(pc + 2, &x32); - } - next = pc + x32; - *flags |= SINGLESTEP_BRANCH; - break; - /* LXX (d8,PC) */ - /* SETLB - loads the next four bytes into the LIR reg */ - case 0xd0 ... 0xda: - case 0xdb: - panic("Can't singlestep Lxx/SETLB\n"); - break; - } - } - return (unsigned)next; - -} - -/* - * set up out of place singlestep of some branching instructions - */ -static unsigned __kprobes singlestep_branch_setup(struct pt_regs *regs) -{ - u8 opc, *pc, *sp, *next; - - next = NULL; - pc = (u8 *) regs->pc; - sp = (u8 *) (regs + 1); - - switch (pc[0]) { - case 0xc0 ... 0xca: /* Bxx (d8,PC) */ - case 0xcc: /* JMP (d16,PC) */ - case 0xdc: /* JMP (d32,PC) */ - case 0xf8: /* Bxx (d8,PC) 3-byte version */ - /* don't really need to do anything except cause trap */ - next = pc; - break; - - case 0xcd: /* CALL (d16,PC) */ - pc[1] = 5; - pc[2] = 0; - next = pc + 5; - break; - - case 0xdd: /* CALL (d32,PC) */ - pc[1] = 7; - pc[2] = 0; - pc[3] = 0; - pc[4] = 0; - next = pc + 7; - break; - - case 0xde: /* RETF */ - next = pc + 3; - regs->mdr = (unsigned) next; - break; - - case 0xdf: /* RET */ - sp += pc[2]; - next = pc + 3; - *(unsigned *)sp = (unsigned) next; - break; - - case 0xf0: - next = pc + 2; - opc = pc[1]; - if (opc >= 0xf0 && opc <= 0xf3) { - /* CALLS (An) */ - /* use CALLS (d16,PC) to avoid mucking with An */ - pc[0] = 0xfa; - pc[1] = 0xff; - pc[2] = 4; - pc[3] = 0; - next = pc + 4; - } else if (opc >= 0xf4 && opc <= 0xf7) { - /* JMP (An) */ - next = pc; - } else if (opc == 0xfc) { - /* RETS */ - next = pc + 2; - *(unsigned *) sp = (unsigned) next; - } else if (opc == 0xfd) { - /* RTI */ - next = pc + 2; - *(unsigned *)(sp + 4) = (unsigned) next; - } - break; - - case 0xfa: /* CALLS (d16,PC) */ - pc[2] = 4; - pc[3] = 0; - next = pc + 4; - break; - - case 0xfc: /* CALLS (d32,PC) */ - pc[2] = 6; - pc[3] = 0; - pc[4] = 0; - pc[5] = 0; - next = pc + 6; - break; - - case 0xd0 ... 0xda: /* LXX (d8,PC) */ - case 0xdb: /* SETLB */ - panic("Can't singlestep Lxx/SETLB\n"); - } - - return (unsigned) next; -} - -int __kprobes arch_prepare_kprobe(struct kprobe *p) -{ - return 0; -} - -void __kprobes arch_copy_kprobe(struct kprobe *p) -{ - memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE); -} - -void __kprobes arch_arm_kprobe(struct kprobe *p) -{ - *p->addr = BREAKPOINT_INSTRUCTION; - flush_icache_range((unsigned long) p->addr, - (unsigned long) p->addr + sizeof(kprobe_opcode_t)); -} - -void __kprobes arch_disarm_kprobe(struct kprobe *p) -{ -#ifndef CONFIG_MN10300_CACHE_SNOOP - mn10300_dcache_flush(); - mn10300_icache_inv(); -#endif -} - -void arch_remove_kprobe(struct kprobe *p) -{ -} - -static inline -void __kprobes disarm_kprobe(struct kprobe *p, struct pt_regs *regs) -{ - *p->addr = p->opcode; - regs->pc = (unsigned long) p->addr; -#ifndef CONFIG_MN10300_CACHE_SNOOP - mn10300_dcache_flush(); - mn10300_icache_inv(); -#endif -} - -static inline -void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs) -{ - unsigned long nextpc; - - cur_kprobe_orig_pc = regs->pc; - memcpy(cur_kprobe_ss_buf, &p->ainsn.insn[0], MAX_INSN_SIZE); - regs->pc = (unsigned long) cur_kprobe_ss_buf; - - nextpc = find_nextpc(regs, &cur_kprobe_ss_flags); - if (cur_kprobe_ss_flags & SINGLESTEP_PCREL) - cur_kprobe_next_pc = cur_kprobe_orig_pc + (nextpc - regs->pc); - else - cur_kprobe_next_pc = nextpc; - - /* branching instructions need special handling */ - if (cur_kprobe_ss_flags & SINGLESTEP_BRANCH) - nextpc = singlestep_branch_setup(regs); - - cur_kprobe_bp_addr = nextpc; - - *(u8 *) nextpc = BREAKPOINT_INSTRUCTION; - mn10300_dcache_flush_range2((unsigned) cur_kprobe_ss_buf, - sizeof(cur_kprobe_ss_buf)); - mn10300_icache_inv(); -} - -static inline int __kprobes kprobe_handler(struct pt_regs *regs) -{ - struct kprobe *p; - int ret = 0; - unsigned int *addr = (unsigned int *) regs->pc; - - /* We're in an interrupt, but this is clear and BUG()-safe. */ - preempt_disable(); - - /* Check we're not actually recursing */ - if (kprobe_running()) { - /* We *are* holding lock here, so this is safe. - Disarm the probe we just hit, and ignore it. */ - p = get_kprobe(addr); - if (p) { - disarm_kprobe(p, regs); - ret = 1; - } else { - p = cur_kprobe; - if (p->break_handler && p->break_handler(p, regs)) - goto ss_probe; - } - /* If it's not ours, can't be delete race, (we hold lock). */ - goto no_kprobe; - } - - p = get_kprobe(addr); - if (!p) { - if (*addr != BREAKPOINT_INSTRUCTION) { - /* The breakpoint instruction was removed right after - * we hit it. Another cpu has removed either a - * probepoint or a debugger breakpoint at this address. - * In either case, no further handling of this - * interrupt is appropriate. - */ - ret = 1; - } - /* Not one of ours: let kernel handle it */ - goto no_kprobe; - } - - kprobe_status = KPROBE_HIT_ACTIVE; - cur_kprobe = p; - if (p->pre_handler(p, regs)) { - /* handler has already set things up, so skip ss setup */ - return 1; - } - -ss_probe: - prepare_singlestep(p, regs); - kprobe_status = KPROBE_HIT_SS; - return 1; - -no_kprobe: - preempt_enable_no_resched(); - return ret; -} - -/* - * Called after single-stepping. p->addr is the address of the - * instruction whose first byte has been replaced by the "breakpoint" - * instruction. To avoid the SMP problems that can occur when we - * temporarily put back the original opcode to single-step, we - * single-stepped a copy of the instruction. The address of this - * copy is p->ainsn.insn. - */ -static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs) -{ - /* we may need to fixup regs/stack after singlestepping a call insn */ - if (cur_kprobe_ss_flags & SINGLESTEP_BRANCH) { - regs->pc = cur_kprobe_orig_pc; - switch (p->ainsn.insn[0]) { - case 0xcd: /* CALL (d16,PC) */ - *(unsigned *) regs->sp = regs->mdr = regs->pc + 5; - break; - case 0xdd: /* CALL (d32,PC) */ - /* fixup mdr and return address on stack */ - *(unsigned *) regs->sp = regs->mdr = regs->pc + 7; - break; - case 0xf0: - if (p->ainsn.insn[1] >= 0xf0 && - p->ainsn.insn[1] <= 0xf3) { - /* CALLS (An) */ - /* fixup MDR and return address on stack */ - regs->mdr = regs->pc + 2; - *(unsigned *) regs->sp = regs->mdr; - } - break; - - case 0xfa: /* CALLS (d16,PC) */ - /* fixup MDR and return address on stack */ - *(unsigned *) regs->sp = regs->mdr = regs->pc + 4; - break; - - case 0xfc: /* CALLS (d32,PC) */ - /* fixup MDR and return address on stack */ - *(unsigned *) regs->sp = regs->mdr = regs->pc + 6; - break; - } - } - - regs->pc = cur_kprobe_next_pc; - cur_kprobe_bp_addr = 0; -} - -static inline int __kprobes post_kprobe_handler(struct pt_regs *regs) -{ - if (!kprobe_running()) - return 0; - - if (cur_kprobe->post_handler) - cur_kprobe->post_handler(cur_kprobe, regs, 0); - - resume_execution(cur_kprobe, regs); - reset_current_kprobe(); - preempt_enable_no_resched(); - return 1; -} - -/* Interrupts disabled, kprobe_lock held. */ -static inline -int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr) -{ - if (cur_kprobe->fault_handler && - cur_kprobe->fault_handler(cur_kprobe, regs, trapnr)) - return 1; - - if (kprobe_status & KPROBE_HIT_SS) { - resume_execution(cur_kprobe, regs); - reset_current_kprobe(); - preempt_enable_no_resched(); - } - return 0; -} - -/* - * Wrapper routine to for handling exceptions. - */ -int __kprobes kprobe_exceptions_notify(struct notifier_block *self, - unsigned long val, void *data) -{ - struct die_args *args = data; - - switch (val) { - case DIE_BREAKPOINT: - if (cur_kprobe_bp_addr != args->regs->pc) { - if (kprobe_handler(args->regs)) - return NOTIFY_STOP; - } else { - if (post_kprobe_handler(args->regs)) - return NOTIFY_STOP; - } - break; - case DIE_GPF: - if (kprobe_running() && - kprobe_fault_handler(args->regs, args->trapnr)) - return NOTIFY_STOP; - break; - default: - break; - } - return NOTIFY_DONE; -} - -/* Jprobes support. */ -static struct pt_regs jprobe_saved_regs; -static struct pt_regs *jprobe_saved_regs_location; -static kprobe_opcode_t jprobe_saved_stack[MAX_STACK_SIZE]; - -int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs) -{ - struct jprobe *jp = container_of(p, struct jprobe, kp); - - jprobe_saved_regs_location = regs; - memcpy(&jprobe_saved_regs, regs, sizeof(struct pt_regs)); - - /* Save a whole stack frame, this gets arguments - * pushed onto the stack after using up all the - * arg registers. - */ - memcpy(&jprobe_saved_stack, regs + 1, sizeof(jprobe_saved_stack)); - - /* setup return addr to the jprobe handler routine */ - regs->pc = (unsigned long) jp->entry; - return 1; -} - -void __kprobes jprobe_return(void) -{ - void *orig_sp = jprobe_saved_regs_location + 1; - - preempt_enable_no_resched(); - asm volatile(" mov %0,sp\n" - ".globl jprobe_return_bp_addr\n" - "jprobe_return_bp_addr:\n\t" - " .byte 0xff\n" - : : "d" (orig_sp)); -} - -extern void jprobe_return_bp_addr(void); - -int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs) -{ - u8 *addr = (u8 *) regs->pc; - - if (addr == (u8 *) jprobe_return_bp_addr) { - if (jprobe_saved_regs_location != regs) { - printk(KERN_ERR"JPROBE:" - " Current regs (%p) does not match saved regs" - " (%p).\n", - regs, jprobe_saved_regs_location); - BUG(); - } - - /* Restore old register state. - */ - memcpy(regs, &jprobe_saved_regs, sizeof(struct pt_regs)); - - memcpy(regs + 1, &jprobe_saved_stack, - sizeof(jprobe_saved_stack)); - return 1; - } - return 0; -} - -int __init arch_init_kprobes(void) -{ - return 0; -} diff --git a/arch/mn10300/kernel/mn10300-debug.c b/arch/mn10300/kernel/mn10300-debug.c deleted file mode 100644 index bd8196478cbc..000000000000 --- a/arch/mn10300/kernel/mn10300-debug.c +++ /dev/null @@ -1,58 +0,0 @@ -/* Debugging stuff for the MN10300-based processors - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include - -#undef MN10300_CONSOLE_ON_SERIO - -/* - * write a string directly through one of the serial ports on-board the MN10300 - */ -#ifdef MN10300_CONSOLE_ON_SERIO -void debug_to_serial_mnser(const char *p, int n) -{ - char ch; - - for (; n > 0; n--) { - ch = *p++; - -#if MN10300_CONSOLE_ON_SERIO == 0 - while (SC0STR & (SC01STR_TBF)) continue; - SC0TXB = ch; - while (SC0STR & (SC01STR_TBF)) continue; - if (ch == 0x0a) { - SC0TXB = 0x0d; - while (SC0STR & (SC01STR_TBF)) continue; - } - -#elif MN10300_CONSOLE_ON_SERIO == 1 - while (SC1STR & (SC01STR_TBF)) continue; - SC1TXB = ch; - while (SC1STR & (SC01STR_TBF)) continue; - if (ch == 0x0a) { - SC1TXB = 0x0d; - while (SC1STR & (SC01STR_TBF)) continue; - } - -#elif MN10300_CONSOLE_ON_SERIO == 2 - while (SC2STR & (SC2STR_TBF)) continue; - SC2TXB = ch; - while (SC2STR & (SC2STR_TBF)) continue; - if (ch == 0x0a) { - SC2TXB = 0x0d; - while (SC2STR & (SC2STR_TBF)) continue; - } - -#endif - } -} -#endif - diff --git a/arch/mn10300/kernel/mn10300-serial-low.S b/arch/mn10300/kernel/mn10300-serial-low.S deleted file mode 100644 index b95e76caf4fa..000000000000 --- a/arch/mn10300/kernel/mn10300-serial-low.S +++ /dev/null @@ -1,194 +0,0 @@ -############################################################################### -# -# Virtual DMA driver for MN10300 serial ports -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mn10300-serial.h" - -#define SCxCTR 0x00 -#define SCxICR 0x04 -#define SCxTXB 0x08 -#define SCxRXB 0x09 -#define SCxSTR 0x0c -#define SCxTIM 0x0d - - .text - -############################################################################### -# -# serial port interrupt virtual DMA entry point -# - intended to run at interrupt priority 1 (not affected by local_irq_disable) -# -############################################################################### - .balign L1_CACHE_BYTES -ENTRY(mn10300_serial_vdma_interrupt) -# or EPSW_IE,psw # permit overriding by - # debugging interrupts - movm [d2,d3,a2,a3,exreg0],(sp) - - movhu (IAGR),a2 # see if which interrupt is - # pending - and IAGR_GN,a2 - add a2,a2 - add mn10300_serial_int_tbl,a2 - - mov (a2+),a3 - mov (__iobase,a3),e2 - mov (a2),a2 - jmp (a2) - -############################################################################### -# -# serial port receive interrupt virtual DMA entry point -# - intended to run at interrupt priority 1 (not affected by local_irq_disable) -# - stores data/status byte pairs in the ring buffer -# - induces a scheduler tick timer interrupt when done, which we then subvert -# on entry: -# A3 struct mn10300_serial_port * -# E2 I/O port base -# -############################################################################### -ENTRY(mn10300_serial_vdma_rx_handler) - mov (__rx_icr,a3),e3 - mov GxICR_DETECT,d2 - movbu d2,(e3) # ACK the interrupt - movhu (e3),d2 # flush - - mov (__rx_inp,a3),d3 - mov d3,a2 - add 2,d3 - and MNSC_BUFFER_SIZE-1,d3 - mov (__rx_outp,a3),d2 - cmp d3,d2 - beq mnsc_vdma_rx_overflow - - mov (__rx_buffer,a3),d2 - add d2,a2 - movhu (SCxSTR,e2),d2 - movbu d2,(1,a2) - movbu (SCxRXB,e2),d2 - movbu d2,(a2) - mov d3,(__rx_inp,a3) - bset MNSCx_RX_AVAIL,(__intr_flags,a3) - -mnsc_vdma_rx_done: - mov (__tm_icr,a3),a2 - mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2 - movhu d2,(a2) # request a slow interrupt - movhu (a2),d2 # flush - - movm (sp),[d2,d3,a2,a3,exreg0] - rti - -mnsc_vdma_rx_overflow: - bset MNSCx_RX_OVERF,(__intr_flags,a3) - bra mnsc_vdma_rx_done - -############################################################################### -# -# serial port transmit interrupt virtual DMA entry point -# - intended to run at interrupt priority 1 (not affected by local_irq_disable) -# - retrieves data bytes from the ring buffer and passes them to the serial port -# - induces a scheduler tick timer interrupt when done, which we then subvert -# A3 struct mn10300_serial_port * -# E2 I/O port base -# -############################################################################### - .balign L1_CACHE_BYTES -ENTRY(mn10300_serial_vdma_tx_handler) - mov (__tx_icr,a3),e3 - mov GxICR_DETECT,d2 - movbu d2,(e3) # ACK the interrupt - movhu (e3),d2 # flush - - btst 0xFF,(__tx_flags,a3) # handle transmit flags - bne mnsc_vdma_tx_flags - - movbu (SCxSTR,e2),d2 # don't try and transmit a char if the - # buffer is not empty - btst SC01STR_TBF,d2 # (may have tried to jumpstart) - bne mnsc_vdma_tx_noint - - movbu (__tx_xchar,a3),d2 # handle hi-pri XON/XOFF - or d2,d2 - bne mnsc_vdma_tx_xchar - - mov (__uart_state,a3),a2 # see if the TTY Tx queue has anything in it - mov (__xmit_tail,a2),d3 - mov (__xmit_head,a2),d2 - cmp d3,d2 - beq mnsc_vdma_tx_empty - - mov (__xmit_buffer,a2),d2 # get a char from the buffer and - # transmit it - movbu (d3,d2),d2 - movbu d2,(SCxTXB,e2) # Tx - - inc d3 # advance the buffer pointer - and __UART_XMIT_SIZE-1,d3 - mov (__xmit_head,a2),d2 - mov d3,(__xmit_tail,a2) - - sub d3,d2 # see if we've written everything - beq mnsc_vdma_tx_empty - - and __UART_XMIT_SIZE-1,d2 # see if we just made a hole - cmp __UART_XMIT_SIZE-2,d2 - beq mnsc_vdma_tx_made_hole - -mnsc_vdma_tx_done: - mov (__tm_icr,a3),a2 - mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2 - movhu d2,(a2) # request a slow interrupt - movhu (a2),d2 # flush - -mnsc_vdma_tx_noint: - movm (sp),[d2,d3,a2,a3,exreg0] - rti - -mnsc_vdma_tx_empty: - mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2 - movhu d2,(e3) # disable the interrupt - movhu (e3),d2 # flush - - bset MNSCx_TX_EMPTY,(__intr_flags,a3) - bra mnsc_vdma_tx_done - -mnsc_vdma_tx_flags: - btst MNSCx_TX_STOP,(__tx_flags,a3) - bne mnsc_vdma_tx_stop - movhu (SCxCTR,e2),d2 # turn on break mode - or SC01CTR_BKE,d2 - movhu d2,(SCxCTR,e2) -mnsc_vdma_tx_stop: - mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2 - movhu d2,(e3) # disable transmit interrupts on this - # channel - movhu (e3),d2 # flush - bra mnsc_vdma_tx_noint - -mnsc_vdma_tx_xchar: - bclr 0xff,(__tx_xchar,a3) - movbu d2,(SCxTXB,e2) - bra mnsc_vdma_tx_done - -mnsc_vdma_tx_made_hole: - bset MNSCx_TX_SPACE,(__intr_flags,a3) - bra mnsc_vdma_tx_done diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c deleted file mode 100644 index 4994b570dfd9..000000000000 --- a/arch/mn10300/kernel/mn10300-serial.c +++ /dev/null @@ -1,1790 +0,0 @@ -/* MN10300 On-chip serial port UART driver - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -static const char serial_name[] = "MN10300 Serial driver"; -static const char serial_version[] = "mn10300_serial-1.0"; -static const char serial_revdate[] = "2007-11-06"; - -#if defined(CONFIG_MN10300_TTYSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) -#define SUPPORT_SYSRQ -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include "mn10300-serial.h" - -#ifdef CONFIG_SMP -#undef GxICR -#define GxICR(X) CROSS_GxICR(X, 0) -#endif /* CONFIG_SMP */ - -#define kenter(FMT, ...) \ - printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__) -#define _enter(FMT, ...) \ - no_printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__) -#define kdebug(FMT, ...) \ - printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__) -#define _debug(FMT, ...) \ - no_printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__) -#define kproto(FMT, ...) \ - printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__) -#define _proto(FMT, ...) \ - no_printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__) - -#ifndef CODMSB -/* c_cflag bit meaning */ -#define CODMSB 004000000000 /* change Transfer bit-order */ -#endif - -#define NR_UARTS 3 - -#ifdef CONFIG_MN10300_TTYSM_CONSOLE -static void mn10300_serial_console_write(struct console *co, - const char *s, unsigned count); -static int __init mn10300_serial_console_setup(struct console *co, - char *options); - -static struct uart_driver mn10300_serial_driver; -static struct console mn10300_serial_console = { - .name = "ttySM", - .write = mn10300_serial_console_write, - .device = uart_console_device, - .setup = mn10300_serial_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, - .data = &mn10300_serial_driver, -}; -#endif - -static struct uart_driver mn10300_serial_driver = { - .owner = NULL, - .driver_name = "mn10300-serial", - .dev_name = "ttySM", - .major = TTY_MAJOR, - .minor = 128, - .nr = NR_UARTS, -#ifdef CONFIG_MN10300_TTYSM_CONSOLE - .cons = &mn10300_serial_console, -#endif -}; - -static unsigned int mn10300_serial_tx_empty(struct uart_port *); -static void mn10300_serial_set_mctrl(struct uart_port *, unsigned int mctrl); -static unsigned int mn10300_serial_get_mctrl(struct uart_port *); -static void mn10300_serial_stop_tx(struct uart_port *); -static void mn10300_serial_start_tx(struct uart_port *); -static void mn10300_serial_send_xchar(struct uart_port *, char ch); -static void mn10300_serial_stop_rx(struct uart_port *); -static void mn10300_serial_enable_ms(struct uart_port *); -static void mn10300_serial_break_ctl(struct uart_port *, int ctl); -static int mn10300_serial_startup(struct uart_port *); -static void mn10300_serial_shutdown(struct uart_port *); -static void mn10300_serial_set_termios(struct uart_port *, - struct ktermios *new, - struct ktermios *old); -static const char *mn10300_serial_type(struct uart_port *); -static void mn10300_serial_release_port(struct uart_port *); -static int mn10300_serial_request_port(struct uart_port *); -static void mn10300_serial_config_port(struct uart_port *, int); -static int mn10300_serial_verify_port(struct uart_port *, - struct serial_struct *); -#ifdef CONFIG_CONSOLE_POLL -static void mn10300_serial_poll_put_char(struct uart_port *, unsigned char); -static int mn10300_serial_poll_get_char(struct uart_port *); -#endif - -static const struct uart_ops mn10300_serial_ops = { - .tx_empty = mn10300_serial_tx_empty, - .set_mctrl = mn10300_serial_set_mctrl, - .get_mctrl = mn10300_serial_get_mctrl, - .stop_tx = mn10300_serial_stop_tx, - .start_tx = mn10300_serial_start_tx, - .send_xchar = mn10300_serial_send_xchar, - .stop_rx = mn10300_serial_stop_rx, - .enable_ms = mn10300_serial_enable_ms, - .break_ctl = mn10300_serial_break_ctl, - .startup = mn10300_serial_startup, - .shutdown = mn10300_serial_shutdown, - .set_termios = mn10300_serial_set_termios, - .type = mn10300_serial_type, - .release_port = mn10300_serial_release_port, - .request_port = mn10300_serial_request_port, - .config_port = mn10300_serial_config_port, - .verify_port = mn10300_serial_verify_port, -#ifdef CONFIG_CONSOLE_POLL - .poll_put_char = mn10300_serial_poll_put_char, - .poll_get_char = mn10300_serial_poll_get_char, -#endif -}; - -static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id); - -/* - * the first on-chip serial port: ttySM0 (aka SIF0) - */ -#ifdef CONFIG_MN10300_TTYSM0 -struct mn10300_serial_port mn10300_serial_port_sif0 = { - .uart.ops = &mn10300_serial_ops, - .uart.membase = (void __iomem *) &SC0CTR, - .uart.mapbase = (unsigned long) &SC0CTR, - .uart.iotype = UPIO_MEM, - .uart.irq = 0, - .uart.uartclk = 0, /* MN10300_IOCLK, */ - .uart.fifosize = 1, - .uart.flags = UPF_BOOT_AUTOCONF, - .uart.line = 0, - .uart.type = PORT_MN10300, - .uart.lock = - __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif0.uart.lock), - .name = "ttySM0", - ._iobase = &SC0CTR, - ._control = &SC0CTR, - ._status = (volatile u8 *)&SC0STR, - ._intr = &SC0ICR, - ._rxb = &SC0RXB, - ._txb = &SC0TXB, - .rx_name = "ttySM0:Rx", - .tx_name = "ttySM0:Tx", -#if defined(CONFIG_MN10300_TTYSM0_TIMER8) - .tm_name = "ttySM0:Timer8", - ._tmxmd = &TM8MD, - ._tmxbr = &TM8BR, - ._tmicr = &TM8ICR, - .tm_irq = TM8IRQ, - .div_timer = MNSCx_DIV_TIMER_16BIT, -#elif defined(CONFIG_MN10300_TTYSM0_TIMER0) - .tm_name = "ttySM0:Timer0", - ._tmxmd = &TM0MD, - ._tmxbr = (volatile u16 *)&TM0BR, - ._tmicr = &TM0ICR, - .tm_irq = TM0IRQ, - .div_timer = MNSCx_DIV_TIMER_8BIT, -#elif defined(CONFIG_MN10300_TTYSM0_TIMER2) - .tm_name = "ttySM0:Timer2", - ._tmxmd = &TM2MD, - ._tmxbr = (volatile u16 *)&TM2BR, - ._tmicr = &TM2ICR, - .tm_irq = TM2IRQ, - .div_timer = MNSCx_DIV_TIMER_8BIT, -#else -#error "Unknown config for ttySM0" -#endif - .rx_irq = SC0RXIRQ, - .tx_irq = SC0TXIRQ, - .rx_icr = &GxICR(SC0RXIRQ), - .tx_icr = &GxICR(SC0TXIRQ), - .clock_src = MNSCx_CLOCK_SRC_IOCLK, - .options = 0, -#ifdef CONFIG_GDBSTUB_ON_TTYSM0 - .gdbstub = 1, -#endif -}; -#endif /* CONFIG_MN10300_TTYSM0 */ - -/* - * the second on-chip serial port: ttySM1 (aka SIF1) - */ -#ifdef CONFIG_MN10300_TTYSM1 -struct mn10300_serial_port mn10300_serial_port_sif1 = { - .uart.ops = &mn10300_serial_ops, - .uart.membase = (void __iomem *) &SC1CTR, - .uart.mapbase = (unsigned long) &SC1CTR, - .uart.iotype = UPIO_MEM, - .uart.irq = 0, - .uart.uartclk = 0, /* MN10300_IOCLK, */ - .uart.fifosize = 1, - .uart.flags = UPF_BOOT_AUTOCONF, - .uart.line = 1, - .uart.type = PORT_MN10300, - .uart.lock = - __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif1.uart.lock), - .name = "ttySM1", - ._iobase = &SC1CTR, - ._control = &SC1CTR, - ._status = (volatile u8 *)&SC1STR, - ._intr = &SC1ICR, - ._rxb = &SC1RXB, - ._txb = &SC1TXB, - .rx_name = "ttySM1:Rx", - .tx_name = "ttySM1:Tx", -#if defined(CONFIG_MN10300_TTYSM1_TIMER9) - .tm_name = "ttySM1:Timer9", - ._tmxmd = &TM9MD, - ._tmxbr = &TM9BR, - ._tmicr = &TM9ICR, - .tm_irq = TM9IRQ, - .div_timer = MNSCx_DIV_TIMER_16BIT, -#elif defined(CONFIG_MN10300_TTYSM1_TIMER3) - .tm_name = "ttySM1:Timer3", - ._tmxmd = &TM3MD, - ._tmxbr = (volatile u16 *)&TM3BR, - ._tmicr = &TM3ICR, - .tm_irq = TM3IRQ, - .div_timer = MNSCx_DIV_TIMER_8BIT, -#elif defined(CONFIG_MN10300_TTYSM1_TIMER12) - .tm_name = "ttySM1/Timer12", - ._tmxmd = &TM12MD, - ._tmxbr = &TM12BR, - ._tmicr = &TM12ICR, - .tm_irq = TM12IRQ, - .div_timer = MNSCx_DIV_TIMER_16BIT, -#else -#error "Unknown config for ttySM1" -#endif - .rx_irq = SC1RXIRQ, - .tx_irq = SC1TXIRQ, - .rx_icr = &GxICR(SC1RXIRQ), - .tx_icr = &GxICR(SC1TXIRQ), - .clock_src = MNSCx_CLOCK_SRC_IOCLK, - .options = 0, -#ifdef CONFIG_GDBSTUB_ON_TTYSM1 - .gdbstub = 1, -#endif -}; -#endif /* CONFIG_MN10300_TTYSM1 */ - -/* - * the third on-chip serial port: ttySM2 (aka SIF2) - */ -#ifdef CONFIG_MN10300_TTYSM2 -struct mn10300_serial_port mn10300_serial_port_sif2 = { - .uart.ops = &mn10300_serial_ops, - .uart.membase = (void __iomem *) &SC2CTR, - .uart.mapbase = (unsigned long) &SC2CTR, - .uart.iotype = UPIO_MEM, - .uart.irq = 0, - .uart.uartclk = 0, /* MN10300_IOCLK, */ - .uart.fifosize = 1, - .uart.flags = UPF_BOOT_AUTOCONF, - .uart.line = 2, -#ifdef CONFIG_MN10300_TTYSM2_CTS - .uart.type = PORT_MN10300_CTS, -#else - .uart.type = PORT_MN10300, -#endif - .uart.lock = - __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif2.uart.lock), - .name = "ttySM2", - ._iobase = &SC2CTR, - ._control = &SC2CTR, - ._status = (volatile u8 *)&SC2STR, - ._intr = &SC2ICR, - ._rxb = &SC2RXB, - ._txb = &SC2TXB, - .rx_name = "ttySM2:Rx", - .tx_name = "ttySM2:Tx", -#if defined(CONFIG_MN10300_TTYSM2_TIMER10) - .tm_name = "ttySM2/Timer10", - ._tmxmd = &TM10MD, - ._tmxbr = &TM10BR, - ._tmicr = &TM10ICR, - .tm_irq = TM10IRQ, - .div_timer = MNSCx_DIV_TIMER_16BIT, -#elif defined(CONFIG_MN10300_TTYSM2_TIMER9) - .tm_name = "ttySM2/Timer9", - ._tmxmd = &TM9MD, - ._tmxbr = &TM9BR, - ._tmicr = &TM9ICR, - .tm_irq = TM9IRQ, - .div_timer = MNSCx_DIV_TIMER_16BIT, -#elif defined(CONFIG_MN10300_TTYSM2_TIMER1) - .tm_name = "ttySM2/Timer1", - ._tmxmd = &TM1MD, - ._tmxbr = (volatile u16 *)&TM1BR, - ._tmicr = &TM1ICR, - .tm_irq = TM1IRQ, - .div_timer = MNSCx_DIV_TIMER_8BIT, -#elif defined(CONFIG_MN10300_TTYSM2_TIMER3) - .tm_name = "ttySM2/Timer3", - ._tmxmd = &TM3MD, - ._tmxbr = (volatile u16 *)&TM3BR, - ._tmicr = &TM3ICR, - .tm_irq = TM3IRQ, - .div_timer = MNSCx_DIV_TIMER_8BIT, -#else -#error "Unknown config for ttySM2" -#endif - .rx_irq = SC2RXIRQ, - .tx_irq = SC2TXIRQ, - .rx_icr = &GxICR(SC2RXIRQ), - .tx_icr = &GxICR(SC2TXIRQ), - .clock_src = MNSCx_CLOCK_SRC_IOCLK, -#ifdef CONFIG_MN10300_TTYSM2_CTS - .options = MNSCx_OPT_CTS, -#else - .options = 0, -#endif -#ifdef CONFIG_GDBSTUB_ON_TTYSM2 - .gdbstub = 1, -#endif -}; -#endif /* CONFIG_MN10300_TTYSM2 */ - - -/* - * list of available serial ports - */ -struct mn10300_serial_port *mn10300_serial_ports[NR_UARTS + 1] = { -#ifdef CONFIG_MN10300_TTYSM0 - [0] = &mn10300_serial_port_sif0, -#endif -#ifdef CONFIG_MN10300_TTYSM1 - [1] = &mn10300_serial_port_sif1, -#endif -#ifdef CONFIG_MN10300_TTYSM2 - [2] = &mn10300_serial_port_sif2, -#endif - [NR_UARTS] = NULL, -}; - - -/* - * we abuse the serial ports' baud timers' interrupt lines to get the ability - * to deliver interrupts to userspace as we use the ports' interrupt lines to - * do virtual DMA on account of the ports having no hardware FIFOs - * - * we can generate an interrupt manually in the assembly stubs by writing to - * the enable and detect bits in the interrupt control register, so all we need - * to do here is disable the interrupt line - * - * note that we can't just leave the line enabled as the baud rate timer *also* - * generates interrupts - */ -static void mn10300_serial_mask_ack(unsigned int irq) -{ - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - GxICR(irq) = GxICR_LEVEL_6; - tmp = GxICR(irq); /* flush write buffer */ - arch_local_irq_restore(flags); -} - -static void mn10300_serial_chip_mask_ack(struct irq_data *d) -{ - mn10300_serial_mask_ack(d->irq); -} - -static void mn10300_serial_nop(struct irq_data *d) -{ -} - -static struct irq_chip mn10300_serial_pic = { - .name = "mnserial", - .irq_ack = mn10300_serial_chip_mask_ack, - .irq_mask = mn10300_serial_chip_mask_ack, - .irq_mask_ack = mn10300_serial_chip_mask_ack, - .irq_unmask = mn10300_serial_nop, -}; - -static void mn10300_serial_low_mask(struct irq_data *d) -{ - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - GxICR(d->irq) = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL); - tmp = GxICR(d->irq); /* flush write buffer */ - arch_local_irq_restore(flags); -} - -static void mn10300_serial_low_unmask(struct irq_data *d) -{ - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - GxICR(d->irq) = - NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL) | GxICR_ENABLE; - tmp = GxICR(d->irq); /* flush write buffer */ - arch_local_irq_restore(flags); -} - -static struct irq_chip mn10300_serial_low_pic = { - .name = "mnserial-low", - .irq_mask = mn10300_serial_low_mask, - .irq_unmask = mn10300_serial_low_unmask, -}; - -/* - * serial virtual DMA interrupt jump table - */ -struct mn10300_serial_int mn10300_serial_int_tbl[NR_IRQS]; - -static void mn10300_serial_dis_tx_intr(struct mn10300_serial_port *port) -{ - int retries = 100; - u16 x; - - /* nothing to do if irq isn't set up */ - if (!mn10300_serial_int_tbl[port->tx_irq].port) - return; - - port->tx_flags |= MNSCx_TX_STOP; - mb(); - - /* - * Here we wait for the irq to be disabled. Either it already is - * disabled or we wait some number of retries for the VDMA handler - * to disable it. The retries give the VDMA handler enough time to - * run to completion if it was already in progress. If the VDMA IRQ - * is enabled but the handler is not yet running when arrive here, - * the STOP flag will prevent the handler from conflicting with the - * driver code following this loop. - */ - while ((*port->tx_icr & GxICR_ENABLE) && retries-- > 0) - ; - if (retries <= 0) { - *port->tx_icr = - NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL); - x = *port->tx_icr; - } -} - -static void mn10300_serial_en_tx_intr(struct mn10300_serial_port *port) -{ - u16 x; - - /* nothing to do if irq isn't set up */ - if (!mn10300_serial_int_tbl[port->tx_irq].port) - return; - - /* stop vdma irq if not already stopped */ - if (!(port->tx_flags & MNSCx_TX_STOP)) - mn10300_serial_dis_tx_intr(port); - - port->tx_flags &= ~MNSCx_TX_STOP; - mb(); - - *port->tx_icr = - NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL) | - GxICR_ENABLE | GxICR_REQUEST | GxICR_DETECT; - x = *port->tx_icr; -} - -static void mn10300_serial_dis_rx_intr(struct mn10300_serial_port *port) -{ - unsigned long flags; - u16 x; - - flags = arch_local_cli_save(); - *port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL); - x = *port->rx_icr; - arch_local_irq_restore(flags); -} - -/* - * multi-bit equivalent of test_and_clear_bit() - */ -static int mask_test_and_clear(volatile u8 *ptr, u8 mask) -{ - u32 epsw; - asm volatile(" bclr %1,(%2) \n" - " mov epsw,%0 \n" - : "=d"(epsw) : "d"(mask), "a"(ptr) - : "cc", "memory"); - return !(epsw & EPSW_FLAG_Z); -} - -/* - * receive chars from the ring buffer for this serial port - * - must do break detection here (not done in the UART) - */ -static void mn10300_serial_receive_interrupt(struct mn10300_serial_port *port) -{ - struct uart_icount *icount = &port->uart.icount; - struct tty_port *tport = &port->uart.state->port; - unsigned ix; - int count; - u8 st, ch, push, status, overrun; - - _enter("%s", port->name); - - push = 0; - - count = CIRC_CNT(port->rx_inp, port->rx_outp, MNSC_BUFFER_SIZE); - count = tty_buffer_request_room(tport, count); - if (count == 0) { - if (!tport->low_latency) - tty_flip_buffer_push(tport); - return; - } - -try_again: - /* pull chars out of the hat */ - ix = READ_ONCE(port->rx_outp); - if (CIRC_CNT(port->rx_inp, ix, MNSC_BUFFER_SIZE) == 0) { - if (push && !tport->low_latency) - tty_flip_buffer_push(tport); - return; - } - - /* READ_ONCE() enforces dependency, but dangerous through integer!!! */ - ch = port->rx_buffer[ix++]; - st = port->rx_buffer[ix++]; - smp_mb(); - port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1); - port->uart.icount.rx++; - - st &= SC01STR_FEF | SC01STR_PEF | SC01STR_OEF; - status = 0; - overrun = 0; - - /* the UART doesn't detect BREAK, so we have to do that ourselves - * - it starts as a framing error on a NUL character - * - then we count another two NUL characters before issuing TTY_BREAK - * - then we end on a normal char or one that has all the bottom bits - * zero and the top bits set - */ - switch (port->rx_brk) { - case 0: - /* not breaking at the moment */ - break; - - case 1: - if (st & SC01STR_FEF && ch == 0) { - port->rx_brk = 2; - goto try_again; - } - goto not_break; - - case 2: - if (st & SC01STR_FEF && ch == 0) { - port->rx_brk = 3; - _proto("Rx Break Detected"); - icount->brk++; - if (uart_handle_break(&port->uart)) - goto ignore_char; - status |= 1 << TTY_BREAK; - goto insert; - } - goto not_break; - - default: - if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF)) - goto try_again; /* still breaking */ - - port->rx_brk = 0; /* end of the break */ - - switch (ch) { - case 0xFF: - case 0xFE: - case 0xFC: - case 0xF8: - case 0xF0: - case 0xE0: - case 0xC0: - case 0x80: - case 0x00: - /* discard char at probable break end */ - goto try_again; - } - break; - } - -process_errors: - /* handle framing error */ - if (st & SC01STR_FEF) { - if (ch == 0) { - /* framing error with NUL char is probably a BREAK */ - port->rx_brk = 1; - goto try_again; - } - - _proto("Rx Framing Error"); - icount->frame++; - status |= 1 << TTY_FRAME; - } - - /* handle parity error */ - if (st & SC01STR_PEF) { - _proto("Rx Parity Error"); - icount->parity++; - status = TTY_PARITY; - } - - /* handle normal char */ - if (status == 0) { - if (uart_handle_sysrq_char(&port->uart, ch)) - goto ignore_char; - status = (1 << TTY_NORMAL); - } - - /* handle overrun error */ - if (st & SC01STR_OEF) { - if (port->rx_brk) - goto try_again; - - _proto("Rx Overrun Error"); - icount->overrun++; - overrun = 1; - } - -insert: - status &= port->uart.read_status_mask; - - if (!overrun && !(status & port->uart.ignore_status_mask)) { - int flag; - - if (status & (1 << TTY_BREAK)) - flag = TTY_BREAK; - else if (status & (1 << TTY_PARITY)) - flag = TTY_PARITY; - else if (status & (1 << TTY_FRAME)) - flag = TTY_FRAME; - else - flag = TTY_NORMAL; - - tty_insert_flip_char(tport, ch, flag); - } - - /* overrun is special, since it's reported immediately, and doesn't - * affect the current character - */ - if (overrun) - tty_insert_flip_char(tport, 0, TTY_OVERRUN); - - count--; - if (count <= 0) { - if (!tport->low_latency) - tty_flip_buffer_push(tport); - return; - } - -ignore_char: - push = 1; - goto try_again; - -not_break: - port->rx_brk = 0; - goto process_errors; -} - -/* - * handle an interrupt from the serial transmission "virtual DMA" driver - * - note: the interrupt routine will disable its own interrupts when the Tx - * buffer is empty - */ -static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port) -{ - _enter("%s", port->name); - - if (!port->uart.state || !port->uart.state->port.tty) { - mn10300_serial_dis_tx_intr(port); - return; - } - - if (uart_tx_stopped(&port->uart) || - uart_circ_empty(&port->uart.state->xmit)) - mn10300_serial_dis_tx_intr(port); - - if (uart_circ_chars_pending(&port->uart.state->xmit) < WAKEUP_CHARS) - uart_write_wakeup(&port->uart); -} - -/* - * deal with a change in the status of the CTS line - */ -static void mn10300_serial_cts_changed(struct mn10300_serial_port *port, u8 st) -{ - u16 ctr; - - port->tx_cts = st; - port->uart.icount.cts++; - - /* flip the CTS state selector flag to interrupt when it changes - * back */ - ctr = *port->_control; - ctr ^= SC2CTR_TWS; - *port->_control = ctr; - - uart_handle_cts_change(&port->uart, st & SC2STR_CTS); - wake_up_interruptible(&port->uart.state->port.delta_msr_wait); -} - -/* - * handle a virtual interrupt generated by the lower level "virtual DMA" - * routines (irq is the baud timer interrupt) - */ -static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id) -{ - struct mn10300_serial_port *port = dev_id; - u8 st; - - spin_lock(&port->uart.lock); - - if (port->intr_flags) { - _debug("INT %s: %x", port->name, port->intr_flags); - - if (mask_test_and_clear(&port->intr_flags, MNSCx_RX_AVAIL)) - mn10300_serial_receive_interrupt(port); - - if (mask_test_and_clear(&port->intr_flags, - MNSCx_TX_SPACE | MNSCx_TX_EMPTY)) - mn10300_serial_transmit_interrupt(port); - } - - /* the only modem control line amongst the whole lot is CTS on - * serial port 2 */ - if (port->type == PORT_MN10300_CTS) { - st = *port->_status; - if ((port->tx_cts ^ st) & SC2STR_CTS) - mn10300_serial_cts_changed(port, st); - } - - spin_unlock(&port->uart.lock); - - return IRQ_HANDLED; -} - -/* - * return indication of whether the hardware transmit buffer is empty - */ -static unsigned int mn10300_serial_tx_empty(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s", port->name); - - return (*port->_status & (SC01STR_TXF | SC01STR_TBF)) ? - 0 : TIOCSER_TEMT; -} - -/* - * set the modem control lines (we don't have any) - */ -static void mn10300_serial_set_mctrl(struct uart_port *_port, - unsigned int mctrl) -{ - struct mn10300_serial_port *port __attribute__ ((unused)) = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s,%x", port->name, mctrl); -} - -/* - * get the modem control line statuses - */ -static unsigned int mn10300_serial_get_mctrl(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s", port->name); - - if (port->type == PORT_MN10300_CTS && !(*port->_status & SC2STR_CTS)) - return TIOCM_CAR | TIOCM_DSR; - - return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; -} - -/* - * stop transmitting characters - */ -static void mn10300_serial_stop_tx(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s", port->name); - - /* disable the virtual DMA */ - mn10300_serial_dis_tx_intr(port); -} - -/* - * start transmitting characters - * - jump-start transmission if it has stalled - * - enable the serial Tx interrupt (used by the virtual DMA controller) - * - force an interrupt to happen if necessary - */ -static void mn10300_serial_start_tx(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s{%lu}", - port->name, - CIRC_CNT(&port->uart.state->xmit.head, - &port->uart.state->xmit.tail, - UART_XMIT_SIZE)); - - /* kick the virtual DMA controller */ - mn10300_serial_en_tx_intr(port); - - _debug("CTR=%04hx ICR=%02hx STR=%04x TMD=%02hx TBR=%04hx ICR=%04hx", - *port->_control, *port->_intr, *port->_status, - *port->_tmxmd, - (port->div_timer == MNSCx_DIV_TIMER_8BIT) ? - *(volatile u8 *)port->_tmxbr : *port->_tmxbr, - *port->tx_icr); -} - -/* - * transmit a high-priority XON/XOFF character - */ -static void mn10300_serial_send_xchar(struct uart_port *_port, char ch) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - unsigned long flags; - - _enter("%s,%02x", port->name, ch); - - if (likely(port->gdbstub)) { - port->tx_xchar = ch; - if (ch) { - spin_lock_irqsave(&port->uart.lock, flags); - mn10300_serial_en_tx_intr(port); - spin_unlock_irqrestore(&port->uart.lock, flags); - } - } -} - -/* - * stop receiving characters - * - called whilst the port is being closed - */ -static void mn10300_serial_stop_rx(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - u16 ctr; - - _enter("%s", port->name); - - ctr = *port->_control; - ctr &= ~SC01CTR_RXE; - *port->_control = ctr; - - mn10300_serial_dis_rx_intr(port); -} - -/* - * enable modem status interrupts - */ -static void mn10300_serial_enable_ms(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - u16 ctr, cts; - - _enter("%s", port->name); - - if (port->type == PORT_MN10300_CTS) { - /* want to interrupt when CTS goes low if CTS is now high and - * vice versa - */ - port->tx_cts = *port->_status; - - cts = (port->tx_cts & SC2STR_CTS) ? - SC2CTR_TWE : SC2CTR_TWE | SC2CTR_TWS; - - ctr = *port->_control; - ctr &= ~SC2CTR_TWS; - ctr |= cts; - *port->_control = ctr; - - mn10300_serial_en_tx_intr(port); - } -} - -/* - * transmit or cease transmitting a break signal - */ -static void mn10300_serial_break_ctl(struct uart_port *_port, int ctl) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - unsigned long flags; - - _enter("%s,%d", port->name, ctl); - - spin_lock_irqsave(&port->uart.lock, flags); - if (ctl) { - /* tell the virtual DMA handler to assert BREAK */ - port->tx_flags |= MNSCx_TX_BREAK; - mn10300_serial_en_tx_intr(port); - } else { - port->tx_flags &= ~MNSCx_TX_BREAK; - *port->_control &= ~SC01CTR_BKE; - mn10300_serial_en_tx_intr(port); - } - spin_unlock_irqrestore(&port->uart.lock, flags); -} - -/* - * grab the interrupts and enable the port for reception - */ -static int mn10300_serial_startup(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - struct mn10300_serial_int *pint; - - _enter("%s{%d}", port->name, port->gdbstub); - - if (unlikely(port->gdbstub)) - return -EBUSY; - - /* allocate an Rx buffer for the virtual DMA handler */ - port->rx_buffer = kmalloc(MNSC_BUFFER_SIZE, GFP_KERNEL); - if (!port->rx_buffer) - return -ENOMEM; - - port->rx_inp = port->rx_outp = 0; - port->tx_flags = 0; - - /* finally, enable the device */ - *port->_intr = SC01ICR_TI; - *port->_control |= SC01CTR_TXE | SC01CTR_RXE; - - pint = &mn10300_serial_int_tbl[port->rx_irq]; - pint->port = port; - pint->vdma = mn10300_serial_vdma_rx_handler; - pint = &mn10300_serial_int_tbl[port->tx_irq]; - pint->port = port; - pint->vdma = mn10300_serial_vdma_tx_handler; - - irq_set_chip(port->rx_irq, &mn10300_serial_low_pic); - irq_set_chip(port->tx_irq, &mn10300_serial_low_pic); - irq_set_chip(port->tm_irq, &mn10300_serial_pic); - - if (request_irq(port->rx_irq, mn10300_serial_interrupt, - IRQF_NOBALANCING, - port->rx_name, port) < 0) - goto error; - - if (request_irq(port->tx_irq, mn10300_serial_interrupt, - IRQF_NOBALANCING, - port->tx_name, port) < 0) - goto error2; - - if (request_irq(port->tm_irq, mn10300_serial_interrupt, - IRQF_NOBALANCING, - port->tm_name, port) < 0) - goto error3; - mn10300_serial_mask_ack(port->tm_irq); - - return 0; - -error3: - free_irq(port->tx_irq, port); -error2: - free_irq(port->rx_irq, port); -error: - kfree(port->rx_buffer); - port->rx_buffer = NULL; - return -EBUSY; -} - -/* - * shutdown the port and release interrupts - */ -static void mn10300_serial_shutdown(struct uart_port *_port) -{ - unsigned long flags; - u16 x; - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s", port->name); - - spin_lock_irqsave(&_port->lock, flags); - mn10300_serial_dis_tx_intr(port); - - *port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL); - x = *port->rx_icr; - port->tx_flags = 0; - spin_unlock_irqrestore(&_port->lock, flags); - - /* disable the serial port and its baud rate timer */ - *port->_control &= ~(SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE); - *port->_tmxmd = 0; - - if (port->rx_buffer) { - void *buf = port->rx_buffer; - port->rx_buffer = NULL; - kfree(buf); - } - - /* disable all intrs */ - free_irq(port->tm_irq, port); - free_irq(port->rx_irq, port); - free_irq(port->tx_irq, port); - - mn10300_serial_int_tbl[port->tx_irq].port = NULL; - mn10300_serial_int_tbl[port->rx_irq].port = NULL; -} - -/* - * this routine is called to set the UART divisor registers to match the - * specified baud rate for a serial port. - */ -static void mn10300_serial_change_speed(struct mn10300_serial_port *port, - struct ktermios *new, - struct ktermios *old) -{ - unsigned long flags; - unsigned long ioclk = port->ioclk; - unsigned cflag; - int baud, bits, xdiv, tmp; - u16 tmxbr, scxctr; - u8 tmxmd, battempt; - u8 div_timer = port->div_timer; - - _enter("%s{%lu}", port->name, ioclk); - - /* byte size and parity */ - cflag = new->c_cflag; - switch (cflag & CSIZE) { - case CS7: scxctr = SC01CTR_CLN_7BIT; bits = 9; break; - case CS8: scxctr = SC01CTR_CLN_8BIT; bits = 10; break; - default: scxctr = SC01CTR_CLN_8BIT; bits = 10; break; - } - - if (cflag & CSTOPB) { - scxctr |= SC01CTR_STB_2BIT; - bits++; - } - - if (cflag & PARENB) { - bits++; - if (cflag & PARODD) - scxctr |= SC01CTR_PB_ODD; -#ifdef CMSPAR - else if (cflag & CMSPAR) - scxctr |= SC01CTR_PB_FIXED0; -#endif - else - scxctr |= SC01CTR_PB_EVEN; - } - - /* Determine divisor based on baud rate */ - battempt = 0; - - switch (port->uart.line) { -#ifdef CONFIG_MN10300_TTYSM0 - case 0: /* ttySM0 */ -#if defined(CONFIG_MN10300_TTYSM0_TIMER8) - scxctr |= SC0CTR_CK_TM8UFLOW_8; -#elif defined(CONFIG_MN10300_TTYSM0_TIMER0) - scxctr |= SC0CTR_CK_TM0UFLOW_8; -#elif defined(CONFIG_MN10300_TTYSM0_TIMER2) - scxctr |= SC0CTR_CK_TM2UFLOW_8; -#else -#error "Unknown config for ttySM0" -#endif - break; -#endif /* CONFIG_MN10300_TTYSM0 */ - -#ifdef CONFIG_MN10300_TTYSM1 - case 1: /* ttySM1 */ -#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) -#if defined(CONFIG_MN10300_TTYSM1_TIMER9) - scxctr |= SC1CTR_CK_TM9UFLOW_8; -#elif defined(CONFIG_MN10300_TTYSM1_TIMER3) - scxctr |= SC1CTR_CK_TM3UFLOW_8; -#else -#error "Unknown config for ttySM1" -#endif -#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ -#if defined(CONFIG_MN10300_TTYSM1_TIMER12) - scxctr |= SC1CTR_CK_TM12UFLOW_8; -#else -#error "Unknown config for ttySM1" -#endif -#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ - break; -#endif /* CONFIG_MN10300_TTYSM1 */ - -#ifdef CONFIG_MN10300_TTYSM2 - case 2: /* ttySM2 */ -#if defined(CONFIG_AM33_2) -#if defined(CONFIG_MN10300_TTYSM2_TIMER10) - scxctr |= SC2CTR_CK_TM10UFLOW; -#else -#error "Unknown config for ttySM2" -#endif -#else /* CONFIG_AM33_2 */ -#if defined(CONFIG_MN10300_TTYSM2_TIMER9) - scxctr |= SC2CTR_CK_TM9UFLOW_8; -#elif defined(CONFIG_MN10300_TTYSM2_TIMER1) - scxctr |= SC2CTR_CK_TM1UFLOW_8; -#elif defined(CONFIG_MN10300_TTYSM2_TIMER3) - scxctr |= SC2CTR_CK_TM3UFLOW_8; -#else -#error "Unknown config for ttySM2" -#endif -#endif /* CONFIG_AM33_2 */ - break; -#endif /* CONFIG_MN10300_TTYSM2 */ - - default: - break; - } - -try_alternative: - baud = uart_get_baud_rate(&port->uart, new, old, 0, - port->ioclk / 8); - - _debug("ALT %d [baud %d]", battempt, baud); - - if (!baud) - baud = 9600; /* B0 transition handled in rs_set_termios */ - xdiv = 1; - if (baud == 134) { - baud = 269; /* 134 is really 134.5 */ - xdiv = 2; - } - - if (baud == 38400 && - (port->uart.flags & UPF_SPD_MASK) == UPF_SPD_CUST - ) { - _debug("CUSTOM %u", port->uart.custom_divisor); - - if (div_timer == MNSCx_DIV_TIMER_16BIT) { - if (port->uart.custom_divisor <= 65535) { - tmxmd = TM8MD_SRC_IOCLK; - tmxbr = port->uart.custom_divisor; - port->uart.uartclk = ioclk; - goto timer_okay; - } - if (port->uart.custom_divisor / 8 <= 65535) { - tmxmd = TM8MD_SRC_IOCLK_8; - tmxbr = port->uart.custom_divisor / 8; - port->uart.custom_divisor = tmxbr * 8; - port->uart.uartclk = ioclk / 8; - goto timer_okay; - } - if (port->uart.custom_divisor / 32 <= 65535) { - tmxmd = TM8MD_SRC_IOCLK_32; - tmxbr = port->uart.custom_divisor / 32; - port->uart.custom_divisor = tmxbr * 32; - port->uart.uartclk = ioclk / 32; - goto timer_okay; - } - - } else if (div_timer == MNSCx_DIV_TIMER_8BIT) { - if (port->uart.custom_divisor <= 255) { - tmxmd = TM2MD_SRC_IOCLK; - tmxbr = port->uart.custom_divisor; - port->uart.uartclk = ioclk; - goto timer_okay; - } - if (port->uart.custom_divisor / 8 <= 255) { - tmxmd = TM2MD_SRC_IOCLK_8; - tmxbr = port->uart.custom_divisor / 8; - port->uart.custom_divisor = tmxbr * 8; - port->uart.uartclk = ioclk / 8; - goto timer_okay; - } - if (port->uart.custom_divisor / 32 <= 255) { - tmxmd = TM2MD_SRC_IOCLK_32; - tmxbr = port->uart.custom_divisor / 32; - port->uart.custom_divisor = tmxbr * 32; - port->uart.uartclk = ioclk / 32; - goto timer_okay; - } - } - } - - switch (div_timer) { - case MNSCx_DIV_TIMER_16BIT: - port->uart.uartclk = ioclk; - tmxmd = TM8MD_SRC_IOCLK; - tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 65535) - goto timer_okay; - - port->uart.uartclk = ioclk / 8; - tmxmd = TM8MD_SRC_IOCLK_8; - tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 65535) - goto timer_okay; - - port->uart.uartclk = ioclk / 32; - tmxmd = TM8MD_SRC_IOCLK_32; - tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 65535) - goto timer_okay; - break; - - case MNSCx_DIV_TIMER_8BIT: - port->uart.uartclk = ioclk; - tmxmd = TM2MD_SRC_IOCLK; - tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 255) - goto timer_okay; - - port->uart.uartclk = ioclk / 8; - tmxmd = TM2MD_SRC_IOCLK_8; - tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 255) - goto timer_okay; - - port->uart.uartclk = ioclk / 32; - tmxmd = TM2MD_SRC_IOCLK_32; - tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1; - if (tmp > 0 && tmp <= 255) - goto timer_okay; - break; - - default: - BUG(); - return; - } - - /* refuse to change to a baud rate we can't support */ - _debug("CAN'T SUPPORT"); - - switch (battempt) { - case 0: - if (old) { - new->c_cflag &= ~CBAUD; - new->c_cflag |= (old->c_cflag & CBAUD); - battempt = 1; - goto try_alternative; - } - - case 1: - /* as a last resort, if the quotient is zero, default to 9600 - * bps */ - new->c_cflag &= ~CBAUD; - new->c_cflag |= B9600; - battempt = 2; - goto try_alternative; - - default: - /* hmmm... can't seem to support 9600 either - * - we could try iterating through the speeds we know about to - * find the lowest - */ - new->c_cflag &= ~CBAUD; - new->c_cflag |= B0; - - if (div_timer == MNSCx_DIV_TIMER_16BIT) - tmxmd = TM8MD_SRC_IOCLK_32; - else if (div_timer == MNSCx_DIV_TIMER_8BIT) - tmxmd = TM2MD_SRC_IOCLK_32; - tmxbr = 1; - - port->uart.uartclk = ioclk / 32; - break; - } -timer_okay: - - _debug("UARTCLK: %u / %hu", port->uart.uartclk, tmxbr); - - /* make the changes */ - spin_lock_irqsave(&port->uart.lock, flags); - - uart_update_timeout(&port->uart, new->c_cflag, baud); - - /* set the timer to produce the required baud rate */ - switch (div_timer) { - case MNSCx_DIV_TIMER_16BIT: - *port->_tmxmd = 0; - *port->_tmxbr = tmxbr; - *port->_tmxmd = TM8MD_INIT_COUNTER; - *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE; - break; - - case MNSCx_DIV_TIMER_8BIT: - *port->_tmxmd = 0; - *(volatile u8 *) port->_tmxbr = (u8) tmxbr; - *port->_tmxmd = TM2MD_INIT_COUNTER; - *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE; - break; - } - - /* CTS flow control flag and modem status interrupts */ - scxctr &= ~(SC2CTR_TWE | SC2CTR_TWS); - - if (port->type == PORT_MN10300_CTS && cflag & CRTSCTS) { - /* want to interrupt when CTS goes low if CTS is now - * high and vice versa - */ - port->tx_cts = *port->_status; - - if (port->tx_cts & SC2STR_CTS) - scxctr |= SC2CTR_TWE; - else - scxctr |= SC2CTR_TWE | SC2CTR_TWS; - } - - /* set up parity check flag */ - port->uart.read_status_mask = (1 << TTY_NORMAL) | (1 << TTY_OVERRUN); - if (new->c_iflag & INPCK) - port->uart.read_status_mask |= - (1 << TTY_PARITY) | (1 << TTY_FRAME); - if (new->c_iflag & (BRKINT | PARMRK)) - port->uart.read_status_mask |= (1 << TTY_BREAK); - - /* characters to ignore */ - port->uart.ignore_status_mask = 0; - if (new->c_iflag & IGNPAR) - port->uart.ignore_status_mask |= - (1 << TTY_PARITY) | (1 << TTY_FRAME); - if (new->c_iflag & IGNBRK) { - port->uart.ignore_status_mask |= (1 << TTY_BREAK); - /* - * If we're ignoring parity and break indicators, - * ignore overruns to (for real raw support). - */ - if (new->c_iflag & IGNPAR) - port->uart.ignore_status_mask |= (1 << TTY_OVERRUN); - } - - /* Ignore all characters if CREAD is not set */ - if ((new->c_cflag & CREAD) == 0) - port->uart.ignore_status_mask |= (1 << TTY_NORMAL); - - scxctr |= SC01CTR_TXE | SC01CTR_RXE; - scxctr |= *port->_control & SC01CTR_BKE; - *port->_control = scxctr; - - spin_unlock_irqrestore(&port->uart.lock, flags); -} - -/* - * set the terminal I/O parameters - */ -static void mn10300_serial_set_termios(struct uart_port *_port, - struct ktermios *new, - struct ktermios *old) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s,%p,%p", port->name, new, old); - - mn10300_serial_change_speed(port, new, old); - - /* handle turning off CRTSCTS */ - if (!(new->c_cflag & CRTSCTS)) { - u16 ctr = *port->_control; - ctr &= ~SC2CTR_TWE; - *port->_control = ctr; - } - - /* change Transfer bit-order (LSB/MSB) */ - if (new->c_cflag & CODMSB) - *port->_control |= SC01CTR_OD_MSBFIRST; /* MSB MODE */ - else - *port->_control &= ~SC01CTR_OD_MSBFIRST; /* LSB MODE */ -} - -/* - * return description of port type - */ -static const char *mn10300_serial_type(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - if (port->uart.type == PORT_MN10300_CTS) - return "MN10300 SIF_CTS"; - - return "MN10300 SIF"; -} - -/* - * release I/O and memory regions in use by port - */ -static void mn10300_serial_release_port(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s", port->name); - - release_mem_region((unsigned long) port->_iobase, 16); -} - -/* - * request I/O and memory regions for port - */ -static int mn10300_serial_request_port(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s", port->name); - - request_mem_region((unsigned long) port->_iobase, 16, port->name); - return 0; -} - -/* - * configure the type and reserve the ports - */ -static void mn10300_serial_config_port(struct uart_port *_port, int type) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - - _enter("%s", port->name); - - port->uart.type = PORT_MN10300; - - if (port->options & MNSCx_OPT_CTS) - port->uart.type = PORT_MN10300_CTS; - - mn10300_serial_request_port(_port); -} - -/* - * verify serial parameters are suitable for this port type - */ -static int mn10300_serial_verify_port(struct uart_port *_port, - struct serial_struct *ss) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - void *mapbase = (void *) (unsigned long) port->uart.mapbase; - - _enter("%s", port->name); - - /* these things may not be changed */ - if (ss->irq != port->uart.irq || - ss->port != port->uart.iobase || - ss->io_type != port->uart.iotype || - ss->iomem_base != mapbase || - ss->iomem_reg_shift != port->uart.regshift || - ss->hub6 != port->uart.hub6 || - ss->xmit_fifo_size != port->uart.fifosize) - return -EINVAL; - - /* type may be changed on a port that supports CTS */ - if (ss->type != port->uart.type) { - if (!(port->options & MNSCx_OPT_CTS)) - return -EINVAL; - - if (ss->type != PORT_MN10300 && - ss->type != PORT_MN10300_CTS) - return -EINVAL; - } - - return 0; -} - -/* - * initialise the MN10300 on-chip UARTs - */ -static int __init mn10300_serial_init(void) -{ - struct mn10300_serial_port *port; - int ret, i; - - printk(KERN_INFO "%s version %s (%s)\n", - serial_name, serial_version, serial_revdate); - -#if defined(CONFIG_MN10300_TTYSM2) && defined(CONFIG_AM33_2) - { - int tmp; - SC2TIM = 8; /* make the baud base of timer 2 IOCLK/8 */ - tmp = SC2TIM; - } -#endif - - set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL), - mn10300_serial_vdma_interrupt); - - ret = uart_register_driver(&mn10300_serial_driver); - if (!ret) { - for (i = 0 ; i < NR_PORTS ; i++) { - port = mn10300_serial_ports[i]; - if (!port || port->gdbstub) - continue; - - switch (port->clock_src) { - case MNSCx_CLOCK_SRC_IOCLK: - port->ioclk = MN10300_IOCLK; - break; - -#ifdef MN10300_IOBCLK - case MNSCx_CLOCK_SRC_IOBCLK: - port->ioclk = MN10300_IOBCLK; - break; -#endif - default: - BUG(); - } - - ret = uart_add_one_port(&mn10300_serial_driver, - &port->uart); - - if (ret < 0) { - _debug("ERROR %d", -ret); - break; - } - } - - if (ret) - uart_unregister_driver(&mn10300_serial_driver); - } - - return ret; -} - -__initcall(mn10300_serial_init); - - -#ifdef CONFIG_MN10300_TTYSM_CONSOLE - -/* - * print a string to the serial port without disturbing the real user of the - * port too much - * - the console must be locked by the caller - */ -static void mn10300_serial_console_write(struct console *co, - const char *s, unsigned count) -{ - struct mn10300_serial_port *port; - unsigned i; - u16 scxctr; - u8 tmxmd; - unsigned long flags; - int locked = 1; - - port = mn10300_serial_ports[co->index]; - - local_irq_save(flags); - if (port->uart.sysrq) { - /* mn10300_serial_interrupt() already took the lock */ - locked = 0; - } else if (oops_in_progress) { - locked = spin_trylock(&port->uart.lock); - } else - spin_lock(&port->uart.lock); - - /* firstly hijack the serial port from the "virtual DMA" controller */ - mn10300_serial_dis_tx_intr(port); - - /* the transmitter may be disabled */ - scxctr = *port->_control; - if (!(scxctr & SC01CTR_TXE)) { - /* restart the UART clock */ - tmxmd = *port->_tmxmd; - - switch (port->div_timer) { - case MNSCx_DIV_TIMER_16BIT: - *port->_tmxmd = 0; - *port->_tmxmd = TM8MD_INIT_COUNTER; - *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE; - break; - - case MNSCx_DIV_TIMER_8BIT: - *port->_tmxmd = 0; - *port->_tmxmd = TM2MD_INIT_COUNTER; - *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE; - break; - } - - /* enable the transmitter */ - *port->_control = (scxctr & ~SC01CTR_BKE) | SC01CTR_TXE; - - } else if (scxctr & SC01CTR_BKE) { - /* stop transmitting BREAK */ - *port->_control = (scxctr & ~SC01CTR_BKE); - } - - /* send the chars into the serial port (with LF -> LFCR conversion) */ - for (i = 0; i < count; i++) { - char ch = *s++; - - while (*port->_status & SC01STR_TBF) - continue; - *port->_txb = ch; - - if (ch == 0x0a) { - while (*port->_status & SC01STR_TBF) - continue; - *port->_txb = 0xd; - } - } - - /* can't let the transmitter be turned off if it's actually - * transmitting */ - while (*port->_status & (SC01STR_TXF | SC01STR_TBF)) - continue; - - /* disable the transmitter if we re-enabled it */ - if (!(scxctr & SC01CTR_TXE)) - *port->_control = scxctr; - - mn10300_serial_en_tx_intr(port); - - if (locked) - spin_unlock(&port->uart.lock); - local_irq_restore(flags); -} - -/* - * set up a serial port as a console - * - construct a cflag setting for the first rs_open() - * - initialize the serial port - * - return non-zero if we didn't find a serial port. - */ -static int __init mn10300_serial_console_setup(struct console *co, - char *options) -{ - struct mn10300_serial_port *port; - int i, parity = 'n', baud = 9600, bits = 8, flow = 0; - - for (i = 0 ; i < NR_PORTS ; i++) { - port = mn10300_serial_ports[i]; - if (port && !port->gdbstub && port->uart.line == co->index) - goto found_device; - } - - return -ENODEV; - -found_device: - switch (port->clock_src) { - case MNSCx_CLOCK_SRC_IOCLK: - port->ioclk = MN10300_IOCLK; - break; - -#ifdef MN10300_IOBCLK - case MNSCx_CLOCK_SRC_IOBCLK: - port->ioclk = MN10300_IOBCLK; - break; -#endif - default: - BUG(); - } - - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - - return uart_set_options(&port->uart, co, baud, parity, bits, flow); -} - -/* - * register console - */ -static int __init mn10300_serial_console_init(void) -{ - register_console(&mn10300_serial_console); - return 0; -} - -console_initcall(mn10300_serial_console_init); -#endif - -#ifdef CONFIG_CONSOLE_POLL -/* - * Polled character reception for the kernel debugger - */ -static int mn10300_serial_poll_get_char(struct uart_port *_port) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - unsigned ix; - u8 st, ch; - - _enter("%s", port->name); - - if (mn10300_serial_int_tbl[port->rx_irq].port != NULL) { - do { - /* pull chars out of the hat */ - ix = READ_ONCE(port->rx_outp); - if (CIRC_CNT(port->rx_inp, ix, MNSC_BUFFER_SIZE) == 0) - return NO_POLL_CHAR; - - /* - * READ_ONCE() enforces dependency, but dangerous - * through integer!!! - */ - ch = port->rx_buffer[ix++]; - st = port->rx_buffer[ix++]; - smp_mb(); - port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1); - - } while (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF)); - } else { - do { - st = *port->_status; - if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF)) - continue; - } while (!(st & SC01STR_RBF)); - - ch = *port->_rxb; - } - - return ch; -} - - -/* - * Polled character transmission for the kernel debugger - */ -static void mn10300_serial_poll_put_char(struct uart_port *_port, - unsigned char ch) -{ - struct mn10300_serial_port *port = - container_of(_port, struct mn10300_serial_port, uart); - u8 intr, tmp; - - /* wait for the transmitter to finish anything it might be doing (and - * this includes the virtual DMA handler, so it might take a while) */ - while (*port->_status & (SC01STR_TBF | SC01STR_TXF)) - continue; - - /* disable the Tx ready interrupt */ - intr = *port->_intr; - *port->_intr = intr & ~SC01ICR_TI; - tmp = *port->_intr; - - if (ch == 0x0a) { - *port->_txb = 0x0d; - while (*port->_status & SC01STR_TBF) - continue; - } - - *port->_txb = ch; - while (*port->_status & SC01STR_TBF) - continue; - - /* restore the Tx interrupt flag */ - *port->_intr = intr; - tmp = *port->_intr; -} - -#endif /* CONFIG_CONSOLE_POLL */ diff --git a/arch/mn10300/kernel/mn10300-serial.h b/arch/mn10300/kernel/mn10300-serial.h deleted file mode 100644 index 01791c68ea1f..000000000000 --- a/arch/mn10300/kernel/mn10300-serial.h +++ /dev/null @@ -1,130 +0,0 @@ -/* MN10300 On-chip serial port driver definitions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _MN10300_SERIAL_H -#define _MN10300_SERIAL_H - -#ifndef __ASSEMBLY__ -#include -#include -#endif - -#include -#include - -#define NR_PORTS 3 /* should be set 3 or 9 or 16 */ - -#define MNSC_BUFFER_SIZE +(PAGE_SIZE / 2) - -/* intr_flags bits */ -#define MNSCx_RX_AVAIL 0x01 -#define MNSCx_RX_OVERF 0x02 -#define MNSCx_TX_SPACE 0x04 -#define MNSCx_TX_EMPTY 0x08 - -/* tx_flags bits */ -#define MNSCx_TX_BREAK 0x01 -#define MNSCx_TX_STOP 0x02 - -#ifndef __ASSEMBLY__ - -struct mn10300_serial_port { - char *rx_buffer; /* reception buffer base */ - unsigned rx_inp; /* pointer to rx input offset */ - unsigned rx_outp; /* pointer to rx output offset */ - u8 tx_xchar; /* high-priority XON/XOFF buffer */ - u8 tx_flags; /* transmit break/stop request */ - u8 intr_flags; /* interrupt flags */ - volatile u16 *rx_icr; /* Rx interrupt control register */ - volatile u16 *tx_icr; /* Tx interrupt control register */ - int rx_irq; /* reception IRQ */ - int tx_irq; /* transmission IRQ */ - int tm_irq; /* timer IRQ */ - - const char *name; /* name of serial port */ - const char *rx_name; /* Rx interrupt handler name of serial port */ - const char *tx_name; /* Tx interrupt handler name of serial port */ - const char *tm_name; /* Timer interrupt handler name */ - unsigned short type; /* type of serial port */ - unsigned char isconsole; /* T if it's a console */ - volatile void *_iobase; /* pointer to base of I/O control regs */ - volatile u16 *_control; /* control register pointer */ - volatile u8 *_status; /* status register pointer */ - volatile u8 *_intr; /* interrupt register pointer */ - volatile u8 *_rxb; /* receive buffer register pointer */ - volatile u8 *_txb; /* transmit buffer register pointer */ - volatile u16 *_tmicr; /* timer interrupt control register */ - volatile u8 *_tmxmd; /* baud rate timer mode register */ - volatile u16 *_tmxbr; /* baud rate timer base register */ - - /* this must come down here so that assembly can use BSET to access the - * above fields */ - struct uart_port uart; - - unsigned short rx_brk; /* current break reception status */ - u16 tx_cts; /* current CTS status */ - int gdbstub; /* preemptively stolen by GDB stub */ - - u8 clock_src; /* clock source */ -#define MNSCx_CLOCK_SRC_IOCLK 0 -#define MNSCx_CLOCK_SRC_IOBCLK 1 - - u8 div_timer; /* timer used as divisor */ -#define MNSCx_DIV_TIMER_16BIT 0 -#define MNSCx_DIV_TIMER_8BIT 1 - - u16 options; /* options */ -#define MNSCx_OPT_CTS 0x0001 - - unsigned long ioclk; /* base clock rate */ -}; - -#ifdef CONFIG_MN10300_TTYSM0 -extern struct mn10300_serial_port mn10300_serial_port_sif0; -#endif - -#ifdef CONFIG_MN10300_TTYSM1 -extern struct mn10300_serial_port mn10300_serial_port_sif1; -#endif - -#ifdef CONFIG_MN10300_TTYSM2 -extern struct mn10300_serial_port mn10300_serial_port_sif2; -#endif - -extern struct mn10300_serial_port *mn10300_serial_ports[]; - -struct mn10300_serial_int { - struct mn10300_serial_port *port; - asmlinkage void (*vdma)(void); -}; - -extern struct mn10300_serial_int mn10300_serial_int_tbl[]; - -extern asmlinkage void mn10300_serial_vdma_interrupt(void); -extern asmlinkage void mn10300_serial_vdma_rx_handler(void); -extern asmlinkage void mn10300_serial_vdma_tx_handler(void); - -#endif /* __ASSEMBLY__ */ - -#if defined(CONFIG_GDBSTUB_ON_TTYSM0) -#define SCgSTR SC0STR -#define SCgRXB SC0RXB -#define SCgRXIRQ SC0RXIRQ -#elif defined(CONFIG_GDBSTUB_ON_TTYSM1) -#define SCgSTR SC1STR -#define SCgRXB SC1RXB -#define SCgRXIRQ SC1RXIRQ -#elif defined(CONFIG_GDBSTUB_ON_TTYSM2) -#define SCgSTR SC2STR -#define SCgRXB SC2RXB -#define SCgRXIRQ SC2RXIRQ -#endif - -#endif /* _MN10300_SERIAL_H */ diff --git a/arch/mn10300/kernel/mn10300-watchdog-low.S b/arch/mn10300/kernel/mn10300-watchdog-low.S deleted file mode 100644 index 34f8773de7d0..000000000000 --- a/arch/mn10300/kernel/mn10300-watchdog-low.S +++ /dev/null @@ -1,66 +0,0 @@ -############################################################################### -# -# MN10300 Watchdog interrupt handler -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include - - .text - -############################################################################### -# -# Watchdog handler entry point -# - special non-maskable interrupt -# -############################################################################### - .globl watchdog_handler - .type watchdog_handler,@function -watchdog_handler: - add -4,sp - SAVE_ALL - - mov 0xffffffff,d0 - mov d0,(REG_ORIG_D0,fp) - - mov fp,d0 - lsr 2,d1 - call watchdog_interrupt[],0 # watchdog_interrupt(regs,irq) - - jmp ret_from_intr - - .size watchdog_handler,.-watchdog_handler - -############################################################################### -# -# Watchdog touch entry point -# - kept to absolute minimum (unfortunately, it's prototyped in linux/nmi.h so -# we can't inline it) -# -############################################################################### - .globl arch_touch_nmi_watchdog - .type arch_touch_nmi_watchdog,@function -arch_touch_nmi_watchdog: - clr d0 - clr d1 - mov watchdog_alert_counter, a0 - setlb - mov d0, (a0+) - inc d1 - cmp NR_CPUS, d1 - lne - ret [],0 - - .size arch_touch_nmi_watchdog,.-arch_touch_nmi_watchdog diff --git a/arch/mn10300/kernel/mn10300-watchdog.c b/arch/mn10300/kernel/mn10300-watchdog.c deleted file mode 100644 index 0d5641beadf5..000000000000 --- a/arch/mn10300/kernel/mn10300-watchdog.c +++ /dev/null @@ -1,205 +0,0 @@ -/* MN10300 Watchdog timer - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - Derived from arch/i386/kernel/nmi.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static DEFINE_SPINLOCK(watchdog_print_lock); -static unsigned int watchdog; -static unsigned int watchdog_hz = 1; -unsigned int watchdog_alert_counter[NR_CPUS]; - -EXPORT_SYMBOL(arch_touch_nmi_watchdog); - -/* - * the best way to detect whether a CPU has a 'hard lockup' problem - * is to check its timer makes IRQ counts. If they are not - * changing then that CPU has some problem. - * - * since NMIs dont listen to _any_ locks, we have to be extremely - * careful not to rely on unsafe variables. The printk might lock - * up though, so we have to break up any console locks first ... - * [when there will be more tty-related locks, break them up - * here too!] - */ -static unsigned int last_irq_sums[NR_CPUS]; - -int __init check_watchdog(void) -{ - irq_cpustat_t tmp[1]; - - printk(KERN_INFO "Testing Watchdog... "); - - memcpy(tmp, irq_stat, sizeof(tmp)); - local_irq_enable(); - mdelay((10 * 1000) / watchdog_hz); /* wait 10 ticks */ - local_irq_disable(); - - if (nmi_count(0) - tmp[0].__nmi_count <= 5) { - printk(KERN_WARNING "CPU#%d: Watchdog appears to be stuck!\n", - 0); - return -1; - } - - printk(KERN_INFO "OK.\n"); - - /* now that we know it works we can reduce NMI frequency to something - * more reasonable; makes a difference in some configs - */ - watchdog_hz = 1; - - return 0; -} - -static int __init setup_watchdog(char *str) -{ - unsigned tmp; - int opt; - u8 ctr; - - get_option(&str, &opt); - if (opt != 1) - return 0; - - watchdog = opt; - if (watchdog) { - set_intr_stub(EXCEP_WDT, watchdog_handler); - ctr = WDCTR_WDCK_65536th; - WDCTR = WDCTR_WDRST | ctr; - WDCTR = ctr; - tmp = WDCTR; - - tmp = __muldiv64u(1 << (16 + ctr * 2), 1000000, MN10300_WDCLK); - tmp = 1000000000 / tmp; - watchdog_hz = (tmp + 500) / 1000; - } - - return 1; -} - -__setup("watchdog=", setup_watchdog); - -void __init watchdog_go(void) -{ - u8 wdt; - - if (watchdog) { - printk(KERN_INFO "Watchdog: running at %uHz\n", watchdog_hz); - wdt = WDCTR & ~WDCTR_WDCNE; - WDCTR = wdt | WDCTR_WDRST; - wdt = WDCTR; - WDCTR = wdt | WDCTR_WDCNE; - wdt = WDCTR; - - check_watchdog(); - } -} - -#ifdef CONFIG_SMP -static void watchdog_dump_register(void *dummy) -{ - printk(KERN_ERR "--- Register Dump (CPU%d) ---\n", CPUID); - show_registers(current_frame()); -} -#endif - -asmlinkage -void watchdog_interrupt(struct pt_regs *regs, enum exception_code excep) -{ - /* - * Since current-> is always on the stack, and we always switch - * the stack NMI-atomically, it's safe to use smp_processor_id(). - */ - int sum, cpu; - int irq = NMIIRQ; - u8 wdt, tmp; - - wdt = WDCTR & ~WDCTR_WDCNE; - WDCTR = wdt; - tmp = WDCTR; - NMICR = NMICR_WDIF; - - nmi_count(smp_processor_id())++; - kstat_incr_irq_this_cpu(irq); - - for_each_online_cpu(cpu) { - - sum = irq_stat[cpu].__irq_count; - - if ((last_irq_sums[cpu] == sum) -#if defined(CONFIG_GDBSTUB) && defined(CONFIG_SMP) - && !(CHK_GDBSTUB_BUSY() - || atomic_read(&cpu_doing_single_step)) -#endif - ) { - /* - * Ayiee, looks like this CPU is stuck ... - * wait a few IRQs (5 seconds) before doing the oops ... - */ - watchdog_alert_counter[cpu]++; - if (watchdog_alert_counter[cpu] == 5 * watchdog_hz) { - spin_lock(&watchdog_print_lock); - /* - * We are in trouble anyway, lets at least try - * to get a message out. - */ - bust_spinlocks(1); - printk(KERN_ERR - "NMI Watchdog detected LOCKUP on CPU%d," - " pc %08lx, registers:\n", - cpu, regs->pc); -#ifdef CONFIG_SMP - printk(KERN_ERR - "--- Register Dump (CPU%d) ---\n", - CPUID); -#endif - show_registers(regs); -#ifdef CONFIG_SMP - smp_nmi_call_function(watchdog_dump_register, - NULL, 1); -#endif - printk(KERN_NOTICE "console shuts up ...\n"); - console_silent(); - spin_unlock(&watchdog_print_lock); - bust_spinlocks(0); -#ifdef CONFIG_GDBSTUB - if (CHK_GDBSTUB_BUSY_AND_ACTIVE()) - gdbstub_exception(regs, excep); - else - gdbstub_intercept(regs, excep); -#endif - do_exit(SIGSEGV); - } - } else { - last_irq_sums[cpu] = sum; - watchdog_alert_counter[cpu] = 0; - } - } - - WDCTR = wdt | WDCTR_WDRST; - tmp = WDCTR; - WDCTR = wdt | WDCTR_WDCNE; - tmp = WDCTR; -} diff --git a/arch/mn10300/kernel/mn10300_ksyms.c b/arch/mn10300/kernel/mn10300_ksyms.c deleted file mode 100644 index 66fb68d0ca8a..000000000000 --- a/arch/mn10300/kernel/mn10300_ksyms.c +++ /dev/null @@ -1,39 +0,0 @@ -/* MN10300 Miscellaneous and library kernel exports - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include - - -EXPORT_SYMBOL(empty_zero_page); - -EXPORT_SYMBOL(change_bit); -EXPORT_SYMBOL(test_and_change_bit); - -EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(memmove); -EXPORT_SYMBOL(memset); - -EXPORT_SYMBOL(strncpy_from_user); -EXPORT_SYMBOL(clear_user); -EXPORT_SYMBOL(__clear_user); -EXPORT_SYMBOL(strnlen_user); - -extern u64 __ashrdi3(u64, unsigned); -extern u64 __ashldi3(u64, unsigned); -extern u64 __lshrdi3(u64, unsigned); -extern s64 __negdi2(s64); -extern int __ucmpdi2(u64, u64); -EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__ashldi3); -EXPORT_SYMBOL(__lshrdi3); -EXPORT_SYMBOL(__negdi2); -EXPORT_SYMBOL(__ucmpdi2); diff --git a/arch/mn10300/kernel/module.c b/arch/mn10300/kernel/module.c deleted file mode 100644 index 216ad23c9570..000000000000 --- a/arch/mn10300/kernel/module.c +++ /dev/null @@ -1,156 +0,0 @@ -/* MN10300 Kernel module helper routines - * - * Copyright (C) 2007, 2008, 2009 Red Hat, Inc. All Rights Reserved. - * Written by Mark Salter (msalter@redhat.com) - * - Derived from arch/i386/kernel/module.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public Licence as published by - * the Free Software Foundation; either version 2 of the Licence, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public Licence for more details. - * - * You should have received a copy of the GNU General Public Licence - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include - -#if 0 -#define DEBUGP printk -#else -#define DEBUGP(fmt, ...) -#endif - -static void reloc_put16(uint8_t *p, uint32_t val) -{ - p[0] = val & 0xff; - p[1] = (val >> 8) & 0xff; -} - -static void reloc_put24(uint8_t *p, uint32_t val) -{ - reloc_put16(p, val); - p[2] = (val >> 16) & 0xff; -} - -static void reloc_put32(uint8_t *p, uint32_t val) -{ - reloc_put16(p, val); - reloc_put16(p+2, val >> 16); -} - -/* - * apply a RELA relocation - */ -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i, sym_diff_seen = 0; - Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - Elf32_Addr relocation, sym_diff_val = 0; - uint8_t *location; - uint32_t value; - - DEBUGP("Applying relocate section %u to %u\n", - relsec, sechdrs[relsec].sh_info); - - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* this is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - - /* this is the symbol the relocation is referring to (note that - * all undefined symbols have been resolved by the caller) */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - /* this is the adjustment to be made */ - relocation = sym->st_value + rel[i].r_addend; - - if (sym_diff_seen) { - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_MN10300_32: - case R_MN10300_24: - case R_MN10300_16: - case R_MN10300_8: - relocation -= sym_diff_val; - sym_diff_seen = 0; - break; - default: - printk(KERN_ERR "module %s: Unexpected SYM_DIFF relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - - switch (ELF32_R_TYPE(rel[i].r_info)) { - /* for the first four relocation types, we simply - * store the adjustment at the location given */ - case R_MN10300_32: - reloc_put32(location, relocation); - break; - case R_MN10300_24: - reloc_put24(location, relocation); - break; - case R_MN10300_16: - reloc_put16(location, relocation); - break; - case R_MN10300_8: - *location = relocation; - break; - - /* for the next three relocation types, we write the - * adjustment with the address subtracted over the - * value at the location given */ - case R_MN10300_PCREL32: - value = relocation - (uint32_t) location; - reloc_put32(location, value); - break; - case R_MN10300_PCREL16: - value = relocation - (uint32_t) location; - reloc_put16(location, value); - break; - case R_MN10300_PCREL8: - *location = relocation - (uint32_t) location; - break; - - case R_MN10300_SYM_DIFF: - /* This is used to adjust the next reloc as required - * by relaxation. */ - sym_diff_seen = 1; - sym_diff_val = sym->st_value; - break; - - case R_MN10300_ALIGN: - /* Just ignore the ALIGN relocs. - * Only interesting if kernel performed relaxation. */ - continue; - - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - if (sym_diff_seen) { - printk(KERN_ERR "module %s: Nothing follows SYM_DIFF relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - return 0; -} diff --git a/arch/mn10300/kernel/process.c b/arch/mn10300/kernel/process.c deleted file mode 100644 index 7c475fd99c46..000000000000 --- a/arch/mn10300/kernel/process.c +++ /dev/null @@ -1,175 +0,0 @@ -/* MN10300 Process handling code - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -/* - * power off function, if any - */ -void (*pm_power_off)(void); -EXPORT_SYMBOL(pm_power_off); - -/* - * On SMP it's slightly faster (but much more power-consuming!) - * to poll the ->work.need_resched flag instead of waiting for the - * cross-CPU IPI to arrive. Use this option with caution. - * - * tglx: No idea why this depends on HOTPLUG_CPU !?! - */ -#if !defined(CONFIG_SMP) || defined(CONFIG_HOTPLUG_CPU) -void arch_cpu_idle(void) -{ - safe_halt(); -} -#endif - -void machine_restart(char *cmd) -{ -#ifdef CONFIG_KERNEL_DEBUGGER - gdbstub_exit(0); -#endif - -#ifdef mn10300_unit_hard_reset - mn10300_unit_hard_reset(); -#else - mn10300_proc_hard_reset(); -#endif -} - -void machine_halt(void) -{ -#ifdef CONFIG_KERNEL_DEBUGGER - gdbstub_exit(0); -#endif -} - -void machine_power_off(void) -{ -#ifdef CONFIG_KERNEL_DEBUGGER - gdbstub_exit(0); -#endif -} - -void show_regs(struct pt_regs *regs) -{ - show_regs_print_info(KERN_DEFAULT); -} - -/* - * free current thread data structures etc.. - */ -void exit_thread(struct task_struct *tsk) -{ - exit_fpu(tsk); -} - -void flush_thread(void) -{ - flush_fpu(); -} - -void release_thread(struct task_struct *dead_task) -{ -} - -/* - * this gets called so that we can store lazy state into memory and copy the - * current task into the new thread. - */ -int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) -{ - unlazy_fpu(src); - *dst = *src; - return 0; -} - -/* - * set up the kernel stack for a new thread and copy arch-specific thread - * control information - */ -int copy_thread(unsigned long clone_flags, - unsigned long c_usp, unsigned long ustk_size, - struct task_struct *p) -{ - struct thread_info *ti = task_thread_info(p); - struct pt_regs *c_regs; - unsigned long c_ksp; - - c_ksp = (unsigned long) task_stack_page(p) + THREAD_SIZE; - - /* allocate the userspace exception frame and set it up */ - c_ksp -= sizeof(struct pt_regs); - c_regs = (struct pt_regs *) c_ksp; - c_ksp -= 12; /* allocate function call ABI slack */ - - /* set up things up so the scheduler can start the new task */ - p->thread.uregs = c_regs; - ti->frame = c_regs; - p->thread.a3 = (unsigned long) c_regs; - p->thread.sp = c_ksp; - p->thread.wchan = p->thread.pc; - p->thread.usp = c_usp; - - if (unlikely(p->flags & PF_KTHREAD)) { - memset(c_regs, 0, sizeof(struct pt_regs)); - c_regs->a0 = c_usp; /* function */ - c_regs->d0 = ustk_size; /* argument */ - local_save_flags(c_regs->epsw); - c_regs->epsw |= EPSW_IE | EPSW_IM_7; - p->thread.pc = (unsigned long) ret_from_kernel_thread; - return 0; - } - *c_regs = *current_pt_regs(); - if (c_usp) - c_regs->sp = c_usp; - c_regs->epsw &= ~EPSW_FE; /* my FPU */ - - /* the new TLS pointer is passed in as arg #5 to sys_clone() */ - if (clone_flags & CLONE_SETTLS) - c_regs->e2 = current_frame()->d3; - - p->thread.pc = (unsigned long) ret_from_fork; - - return 0; -} - -unsigned long get_wchan(struct task_struct *p) -{ - return p->thread.wchan; -} diff --git a/arch/mn10300/kernel/profile-low.S b/arch/mn10300/kernel/profile-low.S deleted file mode 100644 index 94ffac12d02d..000000000000 --- a/arch/mn10300/kernel/profile-low.S +++ /dev/null @@ -1,72 +0,0 @@ -############################################################################### -# -# Fast profiling interrupt handler -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include - -#define pi break - - .balign 4 -counter: - .long -1 - -############################################################################### -# -# Profiling interrupt entry point -# - intended to run at interrupt priority 1 -# -############################################################################### -ENTRY(profile_handler) - movm [d2,d3,a2],(sp) - - # ignore userspace - mov (12,sp),d2 - and EPSW_nSL,d2 - bne out - - # do nothing if there's no buffer - mov (prof_buffer),a2 - and a2,a2 - beq out - or 0x20000000,a2 - - # calculate relative position in text segment - mov (16,sp),d2 - sub _stext,d2 - mov (prof_shift),d3 - lsr d3,d2 - mov (prof_len),d3 - cmp d3,d2 - bcc outside_text - - # increment the appropriate profile bucket -do_inc: - asl2 d2 - mov (a2,d2),d3 - inc d3 - mov d3,(a2,d2) -out: - mov GxICR_DETECT,d2 - movbu d2,(TM11ICR) # ACK the interrupt - movbu (TM11ICR),d2 - movm (sp),[d2,d3,a2] - rti - -outside_text: - sub 1,d3 - mov d3,d2 - bra do_inc diff --git a/arch/mn10300/kernel/profile.c b/arch/mn10300/kernel/profile.c deleted file mode 100644 index 4f342f75d00c..000000000000 --- a/arch/mn10300/kernel/profile.c +++ /dev/null @@ -1,51 +0,0 @@ -/* MN10300 Profiling setup - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -/* - * initialise the profiling if enabled - * - using with gdbstub will give anomalous results - * - can't be used with gdbstub if running at IRQ priority 0 - */ -static __init int profile_init(void) -{ - u16 tmp; - - if (!prof_buffer) - return 0; - - /* use timer 11 to drive the profiling interrupts */ - set_intr_stub(EXCEP_IRQ_LEVEL0, profile_handler); - - /* set IRQ priority at which to run */ - set_intr_level(TM11IRQ, GxICR_LEVEL_0); - - /* set up timer 11 - * - source: (IOCLK 33MHz)*2 = 66MHz - * - frequency: (33330000*2) / 8 / 20625 = 202Hz - */ - TM11BR = 20625 - 1; - TM11MD = TM8MD_SRC_IOCLK_8; - TM11MD |= TM8MD_INIT_COUNTER; - TM11MD &= ~TM8MD_INIT_COUNTER; - TM11MD |= TM8MD_COUNT_ENABLE; - - TM11ICR |= GxICR_ENABLE; - tmp = TM11ICR; - - printk(KERN_INFO "Profiling initiated on timer 11, priority 0, %uHz\n", - MN10300_IOCLK / 8 / (TM11BR + 1)); - printk(KERN_INFO "Profile histogram stored %p-%p\n", - prof_buffer, (u8 *)(prof_buffer + prof_len) - 1); - - return 0; -} - -__initcall(profile_init); diff --git a/arch/mn10300/kernel/ptrace.c b/arch/mn10300/kernel/ptrace.c deleted file mode 100644 index 8009876a7ac4..000000000000 --- a/arch/mn10300/kernel/ptrace.c +++ /dev/null @@ -1,386 +0,0 @@ -/* MN10300 Process tracing - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * translate ptrace register IDs into struct pt_regs offsets - */ -static const u8 ptrace_regid_to_frame[] = { - [PT_A3 << 2] = REG_A3, - [PT_A2 << 2] = REG_A2, - [PT_D3 << 2] = REG_D3, - [PT_D2 << 2] = REG_D2, - [PT_MCVF << 2] = REG_MCVF, - [PT_MCRL << 2] = REG_MCRL, - [PT_MCRH << 2] = REG_MCRH, - [PT_MDRQ << 2] = REG_MDRQ, - [PT_E1 << 2] = REG_E1, - [PT_E0 << 2] = REG_E0, - [PT_E7 << 2] = REG_E7, - [PT_E6 << 2] = REG_E6, - [PT_E5 << 2] = REG_E5, - [PT_E4 << 2] = REG_E4, - [PT_E3 << 2] = REG_E3, - [PT_E2 << 2] = REG_E2, - [PT_SP << 2] = REG_SP, - [PT_LAR << 2] = REG_LAR, - [PT_LIR << 2] = REG_LIR, - [PT_MDR << 2] = REG_MDR, - [PT_A1 << 2] = REG_A1, - [PT_A0 << 2] = REG_A0, - [PT_D1 << 2] = REG_D1, - [PT_D0 << 2] = REG_D0, - [PT_ORIG_D0 << 2] = REG_ORIG_D0, - [PT_EPSW << 2] = REG_EPSW, - [PT_PC << 2] = REG_PC, -}; - -static inline int get_stack_long(struct task_struct *task, int offset) -{ - return *(unsigned long *) - ((unsigned long) task->thread.uregs + offset); -} - -static inline -int put_stack_long(struct task_struct *task, int offset, unsigned long data) -{ - unsigned long stack; - - stack = (unsigned long) task->thread.uregs + offset; - *(unsigned long *) stack = data; - return 0; -} - -/* - * retrieve the contents of MN10300 userspace general registers - */ -static int genregs_get(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - void *kbuf, void __user *ubuf) -{ - const struct pt_regs *regs = task_pt_regs(target); - int ret; - - /* we need to skip regs->next */ - ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, - regs, 0, PT_ORIG_D0 * sizeof(long)); - if (ret < 0) - return ret; - - ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, - ®s->orig_d0, PT_ORIG_D0 * sizeof(long), - NR_PTREGS * sizeof(long)); - if (ret < 0) - return ret; - - return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, - NR_PTREGS * sizeof(long), -1); -} - -/* - * update the contents of the MN10300 userspace general registers - */ -static int genregs_set(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - const void *kbuf, const void __user *ubuf) -{ - struct pt_regs *regs = task_pt_regs(target); - unsigned long tmp; - int ret; - - /* we need to skip regs->next */ - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - regs, 0, PT_ORIG_D0 * sizeof(long)); - if (ret < 0) - return ret; - - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - ®s->orig_d0, PT_ORIG_D0 * sizeof(long), - PT_EPSW * sizeof(long)); - if (ret < 0) - return ret; - - /* we need to mask off changes to EPSW */ - tmp = regs->epsw; - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - &tmp, PT_EPSW * sizeof(long), - PT_PC * sizeof(long)); - tmp &= EPSW_FLAG_V | EPSW_FLAG_C | EPSW_FLAG_N | EPSW_FLAG_Z; - tmp |= regs->epsw & ~(EPSW_FLAG_V | EPSW_FLAG_C | EPSW_FLAG_N | - EPSW_FLAG_Z); - regs->epsw = tmp; - - if (ret < 0) - return ret; - - /* and finally load the PC */ - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - ®s->pc, PT_PC * sizeof(long), - NR_PTREGS * sizeof(long)); - - if (ret < 0) - return ret; - - return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, - NR_PTREGS * sizeof(long), -1); -} - -/* - * retrieve the contents of MN10300 userspace FPU registers - */ -static int fpuregs_get(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - void *kbuf, void __user *ubuf) -{ - const struct fpu_state_struct *fpregs = &target->thread.fpu_state; - int ret; - - unlazy_fpu(target); - - ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, - fpregs, 0, sizeof(*fpregs)); - if (ret < 0) - return ret; - - return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, - sizeof(*fpregs), -1); -} - -/* - * update the contents of the MN10300 userspace FPU registers - */ -static int fpuregs_set(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - const void *kbuf, const void __user *ubuf) -{ - struct fpu_state_struct fpu_state = target->thread.fpu_state; - int ret; - - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - &fpu_state, 0, sizeof(fpu_state)); - if (ret < 0) - return ret; - - fpu_kill_state(target); - target->thread.fpu_state = fpu_state; - set_using_fpu(target); - - return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, - sizeof(fpu_state), -1); -} - -/* - * determine if the FPU registers have actually been used - */ -static int fpuregs_active(struct task_struct *target, - const struct user_regset *regset) -{ - return is_using_fpu(target) ? regset->n : 0; -} - -/* - * Define the register sets available on the MN10300 under Linux - */ -enum mn10300_regset { - REGSET_GENERAL, - REGSET_FPU, -}; - -static const struct user_regset mn10300_regsets[] = { - /* - * General register format is: - * A3, A2, D3, D2, MCVF, MCRL, MCRH, MDRQ - * E1, E0, E7...E2, SP, LAR, LIR, MDR - * A1, A0, D1, D0, ORIG_D0, EPSW, PC - */ - [REGSET_GENERAL] = { - .core_note_type = NT_PRSTATUS, - .n = ELF_NGREG, - .size = sizeof(long), - .align = sizeof(long), - .get = genregs_get, - .set = genregs_set, - }, - /* - * FPU register format is: - * FS0-31, FPCR - */ - [REGSET_FPU] = { - .core_note_type = NT_PRFPREG, - .n = sizeof(struct fpu_state_struct) / sizeof(long), - .size = sizeof(long), - .align = sizeof(long), - .get = fpuregs_get, - .set = fpuregs_set, - .active = fpuregs_active, - }, -}; - -static const struct user_regset_view user_mn10300_native_view = { - .name = "mn10300", - .e_machine = EM_MN10300, - .regsets = mn10300_regsets, - .n = ARRAY_SIZE(mn10300_regsets), -}; - -const struct user_regset_view *task_user_regset_view(struct task_struct *task) -{ - return &user_mn10300_native_view; -} - -/* - * set the single-step bit - */ -void user_enable_single_step(struct task_struct *child) -{ -#ifndef CONFIG_MN10300_USING_JTAG - struct user *dummy = NULL; - long tmp; - - tmp = get_stack_long(child, (unsigned long) &dummy->regs.epsw); - tmp |= EPSW_T; - put_stack_long(child, (unsigned long) &dummy->regs.epsw, tmp); -#endif -} - -/* - * make sure the single-step bit is not set - */ -void user_disable_single_step(struct task_struct *child) -{ -#ifndef CONFIG_MN10300_USING_JTAG - struct user *dummy = NULL; - long tmp; - - tmp = get_stack_long(child, (unsigned long) &dummy->regs.epsw); - tmp &= ~EPSW_T; - put_stack_long(child, (unsigned long) &dummy->regs.epsw, tmp); -#endif -} - -void ptrace_disable(struct task_struct *child) -{ - user_disable_single_step(child); -} - -/* - * handle the arch-specific side of process tracing - */ -long arch_ptrace(struct task_struct *child, long request, - unsigned long addr, unsigned long data) -{ - unsigned long tmp; - int ret; - unsigned long __user *datap = (unsigned long __user *) data; - - switch (request) { - /* read the word at location addr in the USER area. */ - case PTRACE_PEEKUSR: - ret = -EIO; - if ((addr & 3) || addr > sizeof(struct user) - 3) - break; - - tmp = 0; /* Default return condition */ - if (addr < NR_PTREGS << 2) - tmp = get_stack_long(child, - ptrace_regid_to_frame[addr]); - ret = put_user(tmp, datap); - break; - - /* write the word at location addr in the USER area */ - case PTRACE_POKEUSR: - ret = -EIO; - if ((addr & 3) || addr > sizeof(struct user) - 3) - break; - - ret = 0; - if (addr < NR_PTREGS << 2) - ret = put_stack_long(child, ptrace_regid_to_frame[addr], - data); - break; - - case PTRACE_GETREGS: /* Get all integer regs from the child. */ - return copy_regset_to_user(child, &user_mn10300_native_view, - REGSET_GENERAL, - 0, NR_PTREGS * sizeof(long), - datap); - - case PTRACE_SETREGS: /* Set all integer regs in the child. */ - return copy_regset_from_user(child, &user_mn10300_native_view, - REGSET_GENERAL, - 0, NR_PTREGS * sizeof(long), - datap); - - case PTRACE_GETFPREGS: /* Get the child FPU state. */ - return copy_regset_to_user(child, &user_mn10300_native_view, - REGSET_FPU, - 0, sizeof(struct fpu_state_struct), - datap); - - case PTRACE_SETFPREGS: /* Set the child FPU state. */ - return copy_regset_from_user(child, &user_mn10300_native_view, - REGSET_FPU, - 0, sizeof(struct fpu_state_struct), - datap); - - default: - ret = ptrace_request(child, request, addr, data); - break; - } - - return ret; -} - -/* - * handle tracing of system call entry - * - return the revised system call number or ULONG_MAX to cause ENOSYS - */ -asmlinkage unsigned long syscall_trace_entry(struct pt_regs *regs) -{ - if (tracehook_report_syscall_entry(regs)) - /* tracing decided this syscall should not happen, so - * We'll return a bogus call number to get an ENOSYS - * error, but leave the original number in - * regs->orig_d0 - */ - return ULONG_MAX; - - return regs->orig_d0; -} - -/* - * handle tracing of system call exit - */ -asmlinkage void syscall_trace_exit(struct pt_regs *regs) -{ - tracehook_report_syscall_exit(regs, 0); -} diff --git a/arch/mn10300/kernel/rtc.c b/arch/mn10300/kernel/rtc.c deleted file mode 100644 index f81f37025072..000000000000 --- a/arch/mn10300/kernel/rtc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* MN10300 RTC management - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include - -#include -#include - -DEFINE_SPINLOCK(rtc_lock); -EXPORT_SYMBOL(rtc_lock); - -static const __initdata struct resource res[] = { - DEFINE_RES_IO(RTC_PORT(0), RTC_IO_EXTENT), - DEFINE_RES_IRQ(RTC_IRQ), -}; - -/* - * calibrate the TSC clock against the RTC - */ -void __init calibrate_clock(void) -{ - unsigned char status; - - /* make sure the RTC is running and is set to operate in 24hr mode */ - status = RTSRC; - RTCRB |= RTCRB_SET; - RTCRB |= RTCRB_TM_24HR; - RTCRB &= ~RTCRB_DM_BINARY; - RTCRA |= RTCRA_DVR; - RTCRA &= ~RTCRA_DVR; - RTCRB &= ~RTCRB_SET; - - platform_device_register_simple("rtc_cmos", -1, res, ARRAY_SIZE(res)); -} diff --git a/arch/mn10300/kernel/setup.c b/arch/mn10300/kernel/setup.c deleted file mode 100644 index 1b3d80d8a171..000000000000 --- a/arch/mn10300/kernel/setup.c +++ /dev/null @@ -1,283 +0,0 @@ -/* MN10300 Arch-specific initialisation - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct mn10300_cpuinfo boot_cpu_data; - -static char __initdata cmd_line[COMMAND_LINE_SIZE]; -char redboot_command_line[COMMAND_LINE_SIZE] = - "console=ttyS0,115200 root=/dev/mtdblock3 rw"; - -char __initdata redboot_platform_name[COMMAND_LINE_SIZE]; - -static struct resource code_resource = { - .start = 0x100000, - .end = 0, - .name = "Kernel code", -}; - -static struct resource data_resource = { - .start = 0, - .end = 0, - .name = "Kernel data", -}; - -static unsigned long __initdata phys_memory_base; -static unsigned long __initdata phys_memory_end; -static unsigned long __initdata memory_end; -unsigned long memory_size; - -struct thread_info *__current_ti = &init_thread_union.thread_info; -struct task_struct *__current = &init_task; - -#define mn10300_known_cpus 5 -static const char *const mn10300_cputypes[] = { - "am33-1", - "am33-2", - "am34-1", - "am33-3", - "am34-2", - "unknown" -}; - -/* - * Pick out the memory size. We look for mem=size, - * where size is "size[KkMm]" - */ -static int __init early_mem(char *p) -{ - memory_size = memparse(p, &p); - - if (memory_size == 0) - panic("Memory size not known\n"); - - return 0; -} -early_param("mem", early_mem); - -/* - * architecture specific setup - */ -void __init setup_arch(char **cmdline_p) -{ - unsigned long bootmap_size; - unsigned long kstart_pfn, start_pfn, free_pfn, end_pfn; - - cpu_init(); - unit_setup(); - smp_init_cpus(); - - /* save unparsed command line copy for /proc/cmdline */ - strlcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE); - - /* populate cmd_line too for later use, preserving boot_command_line */ - strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); - *cmdline_p = cmd_line; - - parse_early_param(); - - memory_end = (unsigned long) CONFIG_KERNEL_RAM_BASE_ADDRESS + - memory_size; - if (memory_end > phys_memory_end) - memory_end = phys_memory_end; - - init_mm.start_code = (unsigned long)&_text; - init_mm.end_code = (unsigned long) &_etext; - init_mm.end_data = (unsigned long) &_edata; - init_mm.brk = (unsigned long) &_end; - - code_resource.start = virt_to_bus(&_text); - code_resource.end = virt_to_bus(&_etext)-1; - data_resource.start = virt_to_bus(&_etext); - data_resource.end = virt_to_bus(&_edata)-1; - - start_pfn = (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT); - kstart_pfn = PFN_UP(__pa(&_text)); - free_pfn = PFN_UP(__pa(&_end)); - end_pfn = PFN_DOWN(__pa(memory_end)); - - bootmap_size = init_bootmem_node(&contig_page_data, - free_pfn, - start_pfn, - end_pfn); - - if (kstart_pfn > start_pfn) - free_bootmem(PFN_PHYS(start_pfn), - PFN_PHYS(kstart_pfn - start_pfn)); - - free_bootmem(PFN_PHYS(free_pfn), - PFN_PHYS(end_pfn - free_pfn)); - - /* If interrupt vector table is in main ram, then we need to - reserve the page it is occupying. */ - if (CONFIG_INTERRUPT_VECTOR_BASE >= CONFIG_KERNEL_RAM_BASE_ADDRESS && - CONFIG_INTERRUPT_VECTOR_BASE < memory_end) - reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, PAGE_SIZE, - BOOTMEM_DEFAULT); - - reserve_bootmem(PAGE_ALIGN(PFN_PHYS(free_pfn)), bootmap_size, - BOOTMEM_DEFAULT); - -#ifdef CONFIG_VT -#if defined(CONFIG_VGA_CONSOLE) - conswitchp = &vga_con; -#elif defined(CONFIG_DUMMY_CONSOLE) - conswitchp = &dummy_con; -#endif -#endif - - paging_init(); -} - -/* - * perform CPU initialisation - */ -void __init cpu_init(void) -{ - unsigned long cpurev = CPUREV, type; - - type = (CPUREV & CPUREV_TYPE) >> CPUREV_TYPE_S; - if (type > mn10300_known_cpus) - type = mn10300_known_cpus; - - printk(KERN_INFO "Panasonic %s, rev %ld\n", - mn10300_cputypes[type], - (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S); - - get_mem_info(&phys_memory_base, &memory_size); - phys_memory_end = phys_memory_base + memory_size; - - fpu_init_state(); -} - -static struct cpu cpu_devices[NR_CPUS]; - -static int __init topology_init(void) -{ - int i; - - for_each_present_cpu(i) - register_cpu(&cpu_devices[i], i); - - return 0; -} - -subsys_initcall(topology_init); - -/* - * Get CPU information for use by the procfs. - */ -static int show_cpuinfo(struct seq_file *m, void *v) -{ -#ifdef CONFIG_SMP - struct mn10300_cpuinfo *c = v; - unsigned long cpu_id = c - cpu_data; - unsigned long cpurev = c->type, type, icachesz, dcachesz; -#else /* CONFIG_SMP */ - unsigned long cpu_id = 0; - unsigned long cpurev = CPUREV, type, icachesz, dcachesz; -#endif /* CONFIG_SMP */ - -#ifdef CONFIG_SMP - if (!cpu_online(cpu_id)) - return 0; -#endif - - type = (cpurev & CPUREV_TYPE) >> CPUREV_TYPE_S; - if (type > mn10300_known_cpus) - type = mn10300_known_cpus; - - icachesz = - ((cpurev & CPUREV_ICWAY ) >> CPUREV_ICWAY_S) * - ((cpurev & CPUREV_ICSIZE) >> CPUREV_ICSIZE_S) * - 1024; - - dcachesz = - ((cpurev & CPUREV_DCWAY ) >> CPUREV_DCWAY_S) * - ((cpurev & CPUREV_DCSIZE) >> CPUREV_DCSIZE_S) * - 1024; - - seq_printf(m, - "processor : %ld\n" - "vendor_id : " PROCESSOR_VENDOR_NAME "\n" - "cpu core : %s\n" - "cpu rev : %lu\n" - "model name : " PROCESSOR_MODEL_NAME "\n" - "icache size: %lu\n" - "dcache size: %lu\n", - cpu_id, - mn10300_cputypes[type], - (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S, - icachesz, - dcachesz - ); - - seq_printf(m, - "ioclk speed: %lu.%02luMHz\n" - "bogomips : %lu.%02lu\n\n", - MN10300_IOCLK / 1000000, - (MN10300_IOCLK / 10000) % 100, -#ifdef CONFIG_SMP - c->loops_per_jiffy / (500000 / HZ), - (c->loops_per_jiffy / (5000 / HZ)) % 100 -#else /* CONFIG_SMP */ - loops_per_jiffy / (500000 / HZ), - (loops_per_jiffy / (5000 / HZ)) % 100 -#endif /* CONFIG_SMP */ - ); - - return 0; -} - -static void *c_start(struct seq_file *m, loff_t *pos) -{ - return *pos < NR_CPUS ? cpu_data + *pos : NULL; -} - -static void *c_next(struct seq_file *m, void *v, loff_t *pos) -{ - ++*pos; - return c_start(m, pos); -} - -static void c_stop(struct seq_file *m, void *v) -{ -} - -const struct seq_operations cpuinfo_op = { - .start = c_start, - .next = c_next, - .stop = c_stop, - .show = show_cpuinfo, -}; diff --git a/arch/mn10300/kernel/sigframe.h b/arch/mn10300/kernel/sigframe.h deleted file mode 100644 index 0decba28ae84..000000000000 --- a/arch/mn10300/kernel/sigframe.h +++ /dev/null @@ -1,33 +0,0 @@ -/* MN10300 Signal frame definitions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -struct sigframe -{ - void (*pretcode)(void); - int sig; - struct sigcontext *psc; - struct sigcontext sc; - struct fpucontext fpuctx; - unsigned long extramask[_NSIG_WORDS-1]; - char retcode[8]; -}; - -struct rt_sigframe -{ - void (*pretcode)(void); - int sig; - struct siginfo *pinfo; - void *puc; - struct siginfo info; - struct ucontext uc; - struct fpucontext fpuctx; - char retcode[8]; -}; diff --git a/arch/mn10300/kernel/signal.c b/arch/mn10300/kernel/signal.c deleted file mode 100644 index 2f3cb5734235..000000000000 --- a/arch/mn10300/kernel/signal.c +++ /dev/null @@ -1,431 +0,0 @@ -/* MN10300 Signal handling - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "sigframe.h" - -#define DEBUG_SIG 0 - -/* - * do a signal return; undo the signal stack. - */ -static int restore_sigcontext(struct pt_regs *regs, - struct sigcontext __user *sc, long *_d0) -{ - unsigned int err = 0; - - /* Always make any pending restarted system calls return -EINTR */ - current->restart_block.fn = do_no_restart_syscall; - - if (is_using_fpu(current)) - fpu_kill_state(current); - -#define COPY(x) err |= __get_user(regs->x, &sc->x) - COPY(d1); COPY(d2); COPY(d3); - COPY(a0); COPY(a1); COPY(a2); COPY(a3); - COPY(e0); COPY(e1); COPY(e2); COPY(e3); - COPY(e4); COPY(e5); COPY(e6); COPY(e7); - COPY(lar); COPY(lir); - COPY(mdr); COPY(mdrq); - COPY(mcvf); COPY(mcrl); COPY(mcrh); - COPY(sp); COPY(pc); -#undef COPY - - { - unsigned int tmpflags; -#ifndef CONFIG_MN10300_USING_JTAG -#define USER_EPSW (EPSW_FLAG_Z | EPSW_FLAG_N | EPSW_FLAG_C | EPSW_FLAG_V | \ - EPSW_T | EPSW_nAR) -#else -#define USER_EPSW (EPSW_FLAG_Z | EPSW_FLAG_N | EPSW_FLAG_C | EPSW_FLAG_V | \ - EPSW_nAR) -#endif - err |= __get_user(tmpflags, &sc->epsw); - regs->epsw = (regs->epsw & ~USER_EPSW) | - (tmpflags & USER_EPSW); - regs->orig_d0 = -1; /* disable syscall checks */ - } - - { - struct fpucontext *buf; - err |= __get_user(buf, &sc->fpucontext); - if (buf) { - if (!access_ok(VERIFY_READ, buf, sizeof(*buf))) - goto badframe; - err |= fpu_restore_sigcontext(buf); - } - } - - err |= __get_user(*_d0, &sc->d0); - return err; - -badframe: - return 1; -} - -/* - * standard signal return syscall - */ -asmlinkage long sys_sigreturn(void) -{ - struct sigframe __user *frame; - sigset_t set; - long d0; - - frame = (struct sigframe __user *) current_frame()->sp; - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__get_user(set.sig[0], &frame->sc.oldmask)) - goto badframe; - - if (_NSIG_WORDS > 1 && - __copy_from_user(&set.sig[1], &frame->extramask, - sizeof(frame->extramask))) - goto badframe; - - set_current_blocked(&set); - - if (restore_sigcontext(current_frame(), &frame->sc, &d0)) - goto badframe; - - return d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* - * realtime signal return syscall - */ -asmlinkage long sys_rt_sigreturn(void) -{ - struct rt_sigframe __user *frame; - sigset_t set; - long d0; - - frame = (struct rt_sigframe __user *) current_frame()->sp; - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - set_current_blocked(&set); - - if (restore_sigcontext(current_frame(), &frame->uc.uc_mcontext, &d0)) - goto badframe; - - if (restore_altstack(&frame->uc.uc_stack)) - goto badframe; - - return d0; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* - * store the userspace context into a signal frame - */ -static int setup_sigcontext(struct sigcontext __user *sc, - struct fpucontext *fpuctx, - struct pt_regs *regs, - unsigned long mask) -{ - int tmp, err = 0; - -#define COPY(x) err |= __put_user(regs->x, &sc->x) - COPY(d0); COPY(d1); COPY(d2); COPY(d3); - COPY(a0); COPY(a1); COPY(a2); COPY(a3); - COPY(e0); COPY(e1); COPY(e2); COPY(e3); - COPY(e4); COPY(e5); COPY(e6); COPY(e7); - COPY(lar); COPY(lir); - COPY(mdr); COPY(mdrq); - COPY(mcvf); COPY(mcrl); COPY(mcrh); - COPY(sp); COPY(epsw); COPY(pc); -#undef COPY - - tmp = fpu_setup_sigcontext(fpuctx); - if (tmp < 0) - err = 1; - else - err |= __put_user(tmp ? fpuctx : NULL, &sc->fpucontext); - - /* non-iBCS2 extensions.. */ - err |= __put_user(mask, &sc->oldmask); - - return err; -} - -/* - * determine which stack to use.. - */ -static inline void __user *get_sigframe(struct ksignal *ksig, - struct pt_regs *regs, - size_t frame_size) -{ - unsigned long sp = sigsp(regs->sp, ksig); - - return (void __user *) ((sp - frame_size) & ~7UL); -} - -/* - * set up a normal signal frame - */ -static int setup_frame(struct ksignal *ksig, sigset_t *set, - struct pt_regs *regs) -{ - struct sigframe __user *frame; - int sig = ksig->sig; - - frame = get_sigframe(ksig, regs, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - if (__put_user(sig, &frame->sig) < 0 || - __put_user(&frame->sc, &frame->psc) < 0) - return -EFAULT; - - if (setup_sigcontext(&frame->sc, &frame->fpuctx, regs, set->sig[0])) - return -EFAULT; - - if (_NSIG_WORDS > 1) { - if (__copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask))) - return -EFAULT; - } - - /* set up to return from userspace. If provided, use a stub already in - * userspace */ - if (ksig->ka.sa.sa_flags & SA_RESTORER) { - if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode)) - return -EFAULT; - } else { - if (__put_user((void (*)(void))frame->retcode, - &frame->pretcode)) - return -EFAULT; - /* this is mov $,d0; syscall 0 */ - if (__put_user(0x2c, (char *)(frame->retcode + 0)) || - __put_user(__NR_sigreturn, (char *)(frame->retcode + 1)) || - __put_user(0x00, (char *)(frame->retcode + 2)) || - __put_user(0xf0, (char *)(frame->retcode + 3)) || - __put_user(0xe0, (char *)(frame->retcode + 4))) - return -EFAULT; - flush_icache_range((unsigned long) frame->retcode, - (unsigned long) frame->retcode + 5); - } - - /* set up registers for signal handler */ - regs->sp = (unsigned long) frame; - regs->pc = (unsigned long) ksig->ka.sa.sa_handler; - regs->d0 = sig; - regs->d1 = (unsigned long) &frame->sc; - -#if DEBUG_SIG - printk(KERN_DEBUG "SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n", - sig, current->comm, current->pid, frame, regs->pc, - frame->pretcode); -#endif - - return 0; -} - -/* - * set up a realtime signal frame - */ -static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, - struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - int sig = ksig->sig; - - frame = get_sigframe(ksig, regs, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - if (__put_user(sig, &frame->sig) || - __put_user(&frame->info, &frame->pinfo) || - __put_user(&frame->uc, &frame->puc) || - copy_siginfo_to_user(&frame->info, &ksig->info)) - return -EFAULT; - - /* create the ucontext. */ - if (__put_user(0, &frame->uc.uc_flags) || - __put_user(0, &frame->uc.uc_link) || - __save_altstack(&frame->uc.uc_stack, regs->sp) || - setup_sigcontext(&frame->uc.uc_mcontext, - &frame->fpuctx, regs, set->sig[0]) || - __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set))) - return -EFAULT; - - /* set up to return from userspace. If provided, use a stub already in - * userspace */ - if (ksig->ka.sa.sa_flags & SA_RESTORER) { - if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode)) - return -EFAULT; - - } else { - if (__put_user((void(*)(void))frame->retcode, - &frame->pretcode) || - /* This is mov $,d0; syscall 0 */ - __put_user(0x2c, (char *)(frame->retcode + 0)) || - __put_user(__NR_rt_sigreturn, - (char *)(frame->retcode + 1)) || - __put_user(0x00, (char *)(frame->retcode + 2)) || - __put_user(0xf0, (char *)(frame->retcode + 3)) || - __put_user(0xe0, (char *)(frame->retcode + 4))) - return -EFAULT; - - flush_icache_range((u_long) frame->retcode, - (u_long) frame->retcode + 5); - } - - /* Set up registers for signal handler */ - regs->sp = (unsigned long) frame; - regs->pc = (unsigned long) ksig->ka.sa.sa_handler; - regs->d0 = sig; - regs->d1 = (long) &frame->info; - -#if DEBUG_SIG - printk(KERN_DEBUG "SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n", - sig, current->comm, current->pid, frame, regs->pc, - frame->pretcode); -#endif - - return 0; -} - -static inline void stepback(struct pt_regs *regs) -{ - regs->pc -= 2; - regs->orig_d0 = -1; -} - -/* - * handle the actual delivery of a signal to userspace - */ -static int handle_signal(struct ksignal *ksig, struct pt_regs *regs) -{ - sigset_t *oldset = sigmask_to_save(); - int ret; - - /* Are we from a system call? */ - if (regs->orig_d0 >= 0) { - /* If so, check system call restarting.. */ - switch (regs->d0) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - regs->d0 = -EINTR; - break; - - case -ERESTARTSYS: - if (!(ksig->ka.sa.sa_flags & SA_RESTART)) { - regs->d0 = -EINTR; - break; - } - - /* fallthrough */ - case -ERESTARTNOINTR: - regs->d0 = regs->orig_d0; - stepback(regs); - } - } - - /* Set up the stack frame */ - if (ksig->ka.sa.sa_flags & SA_SIGINFO) - ret = setup_rt_frame(ksig, oldset, regs); - else - ret = setup_frame(ksig, oldset, regs); - - signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP)); - return 0; -} - -/* - * handle a potential signal - */ -static void do_signal(struct pt_regs *regs) -{ - struct ksignal ksig; - - if (get_signal(&ksig)) { - handle_signal(&ksig, regs); - return; - } - - /* did we come from a system call? */ - if (regs->orig_d0 >= 0) { - /* restart the system call - no handlers present */ - switch (regs->d0) { - case -ERESTARTNOHAND: - case -ERESTARTSYS: - case -ERESTARTNOINTR: - regs->d0 = regs->orig_d0; - stepback(regs); - break; - - case -ERESTART_RESTARTBLOCK: - regs->d0 = __NR_restart_syscall; - stepback(regs); - break; - } - } - - /* if there's no signal to deliver, we just put the saved sigmask - * back */ - restore_saved_sigmask(); -} - -/* - * notification of userspace execution resumption - * - triggered by current->work.notify_resume - */ -asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags) -{ - /* Pending single-step? */ - if (thread_info_flags & _TIF_SINGLESTEP) { -#ifndef CONFIG_MN10300_USING_JTAG - regs->epsw |= EPSW_T; - clear_thread_flag(TIF_SINGLESTEP); -#else - BUG(); /* no h/w single-step if using JTAG unit */ -#endif - } - - /* deal with pending signal delivery */ - if (thread_info_flags & _TIF_SIGPENDING) - do_signal(regs); - - if (thread_info_flags & _TIF_NOTIFY_RESUME) { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(current_frame()); - } -} diff --git a/arch/mn10300/kernel/smp-low.S b/arch/mn10300/kernel/smp-low.S deleted file mode 100644 index 71f1b2faaa0b..000000000000 --- a/arch/mn10300/kernel/smp-low.S +++ /dev/null @@ -1,97 +0,0 @@ -/* SMP IPI low-level handler - * - * Copyright (C) 2006-2007 Matsushita Electric Industrial Co., Ltd. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - - .am33_2 - -############################################################################### -# -# IPI interrupt handler -# -############################################################################### - .globl mn10300_low_ipi_handler -mn10300_low_ipi_handler: - add -4,sp - mov d0,(sp) - movhu (IAGR),d0 - and IAGR_GN,d0 - lsr 0x2,d0 -#ifdef CONFIG_MN10300_CACHE_ENABLED - cmp FLUSH_CACHE_IPI,d0 - beq mn10300_flush_cache_ipi -#endif - cmp SMP_BOOT_IRQ,d0 - beq mn10300_smp_boot_ipi - /* OTHERS */ - mov (sp),d0 - add 4,sp -#ifdef CONFIG_GDBSTUB - jmp gdbstub_io_rx_handler -#else - jmp end -#endif - -############################################################################### -# -# Cache flush IPI interrupt handler -# -############################################################################### -#ifdef CONFIG_MN10300_CACHE_ENABLED -mn10300_flush_cache_ipi: - mov (sp),d0 - add 4,sp - - /* FLUSH_CACHE_IPI */ - add -4,sp - SAVE_ALL - mov GxICR_DETECT,d2 - movbu d2,(GxICR(FLUSH_CACHE_IPI)) # ACK the interrupt - movhu (GxICR(FLUSH_CACHE_IPI)),d2 - call smp_cache_interrupt[],0 - RESTORE_ALL - jmp end -#endif - -############################################################################### -# -# SMP boot CPU IPI interrupt handler -# -############################################################################### -mn10300_smp_boot_ipi: - /* clear interrupt */ - movhu (GxICR(SMP_BOOT_IRQ)),d0 - and ~GxICR_REQUEST,d0 - movhu d0,(GxICR(SMP_BOOT_IRQ)) - mov (sp),d0 - add 4,sp - - # get stack - mov (CPUID),a0 - add -1,a0 - add a0,a0 - add a0,a0 - mov (start_stack,a0),a0 - mov a0,sp - jmp initialize_secondary - - -# Jump here after RTI to suppress the icache lookahead -end: diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c deleted file mode 100644 index 35d2c3fe6f76..000000000000 --- a/arch/mn10300/kernel/smp.c +++ /dev/null @@ -1,1186 +0,0 @@ -/* SMP support routines. - * - * Copyright (C) 2006-2008 Panasonic Corporation - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -#ifdef CONFIG_HOTPLUG_CPU -#include - -static unsigned long sleep_mode[NR_CPUS]; - -static void run_sleep_cpu(unsigned int cpu); -static void run_wakeup_cpu(unsigned int cpu); -#endif /* CONFIG_HOTPLUG_CPU */ - -/* - * Debug Message function - */ - -#undef DEBUG_SMP -#ifdef DEBUG_SMP -#define Dprintk(fmt, ...) printk(KERN_DEBUG fmt, ##__VA_ARGS__) -#else -#define Dprintk(fmt, ...) no_printk(KERN_DEBUG fmt, ##__VA_ARGS__) -#endif - -/* timeout value in msec for smp_nmi_call_function. zero is no timeout. */ -#define CALL_FUNCTION_NMI_IPI_TIMEOUT 0 - -/* - * Structure and data for smp_nmi_call_function(). - */ -struct nmi_call_data_struct { - smp_call_func_t func; - void *info; - cpumask_t started; - cpumask_t finished; - int wait; - char size_alignment[0] - __attribute__ ((__aligned__(SMP_CACHE_BYTES))); -} __attribute__ ((__aligned__(SMP_CACHE_BYTES))); - -static DEFINE_SPINLOCK(smp_nmi_call_lock); -static struct nmi_call_data_struct *nmi_call_data; - -/* - * Data structures and variables - */ -static cpumask_t cpu_callin_map; /* Bitmask of callin CPUs */ -static cpumask_t cpu_callout_map; /* Bitmask of callout CPUs */ -cpumask_t cpu_boot_map; /* Bitmask of boot APs */ -unsigned long start_stack[NR_CPUS - 1]; - -/* - * Per CPU parameters - */ -struct mn10300_cpuinfo cpu_data[NR_CPUS] __cacheline_aligned; - -static int cpucount; /* The count of boot CPUs */ -static cpumask_t smp_commenced_mask; -cpumask_t cpu_initialized __initdata = CPU_MASK_NONE; - -/* - * Function Prototypes - */ -static int do_boot_cpu(int); -static void smp_show_cpu_info(int cpu_id); -static void smp_callin(void); -static void smp_online(void); -static void smp_store_cpu_info(int); -static void smp_cpu_init(void); -static void smp_tune_scheduling(void); -static void send_IPI_mask(const cpumask_t *cpumask, int irq); -static void init_ipi(void); - -/* - * IPI Initialization interrupt definitions - */ -static void mn10300_ipi_disable(unsigned int irq); -static void mn10300_ipi_enable(unsigned int irq); -static void mn10300_ipi_chip_disable(struct irq_data *d); -static void mn10300_ipi_chip_enable(struct irq_data *d); -static void mn10300_ipi_ack(struct irq_data *d); -static void mn10300_ipi_nop(struct irq_data *d); - -static struct irq_chip mn10300_ipi_type = { - .name = "cpu_ipi", - .irq_disable = mn10300_ipi_chip_disable, - .irq_enable = mn10300_ipi_chip_enable, - .irq_ack = mn10300_ipi_ack, - .irq_eoi = mn10300_ipi_nop -}; - -static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id); -static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id); - -static struct irqaction reschedule_ipi = { - .handler = smp_reschedule_interrupt, - .flags = IRQF_NOBALANCING, - .name = "smp reschedule IPI" -}; -static struct irqaction call_function_ipi = { - .handler = smp_call_function_interrupt, - .flags = IRQF_NOBALANCING, - .name = "smp call function IPI" -}; - -#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) -static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id); -static struct irqaction local_timer_ipi = { - .handler = smp_ipi_timer_interrupt, - .flags = IRQF_NOBALANCING, - .name = "smp local timer IPI" -}; -#endif - -/** - * init_ipi - Initialise the IPI mechanism - */ -static void init_ipi(void) -{ - unsigned long flags; - u16 tmp16; - - /* set up the reschedule IPI */ - irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type, - handle_percpu_irq); - setup_irq(RESCHEDULE_IPI, &reschedule_ipi); - set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV); - mn10300_ipi_enable(RESCHEDULE_IPI); - - /* set up the call function IPI */ - irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type, - handle_percpu_irq); - setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi); - set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV); - mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); - - /* set up the local timer IPI */ -#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ - defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) - irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type, - handle_percpu_irq); - setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi); - set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV); - mn10300_ipi_enable(LOCAL_TIMER_IPI); -#endif - -#ifdef CONFIG_MN10300_CACHE_ENABLED - /* set up the cache flush IPI */ - irq_set_chip(FLUSH_CACHE_IPI, &mn10300_ipi_type); - flags = arch_local_cli_save(); - __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(FLUSH_CACHE_GxICR_LV), - mn10300_low_ipi_handler); - GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT; - mn10300_ipi_enable(FLUSH_CACHE_IPI); - arch_local_irq_restore(flags); -#endif - - /* set up the NMI call function IPI */ - irq_set_chip(CALL_FUNCTION_NMI_IPI, &mn10300_ipi_type); - flags = arch_local_cli_save(); - GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; - tmp16 = GxICR(CALL_FUNCTION_NMI_IPI); - arch_local_irq_restore(flags); - - /* set up the SMP boot IPI */ - flags = arch_local_cli_save(); - __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(SMP_BOOT_GxICR_LV), - mn10300_low_ipi_handler); - arch_local_irq_restore(flags); - -#ifdef CONFIG_KERNEL_DEBUGGER - irq_set_chip(DEBUGGER_NMI_IPI, &mn10300_ipi_type); -#endif -} - -/** - * mn10300_ipi_shutdown - Shut down handling of an IPI - * @irq: The IPI to be shut down. - */ -static void mn10300_ipi_shutdown(unsigned int irq) -{ - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - - tmp = GxICR(irq); - GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; - tmp = GxICR(irq); - - arch_local_irq_restore(flags); -} - -/** - * mn10300_ipi_enable - Enable an IPI - * @irq: The IPI to be enabled. - */ -static void mn10300_ipi_enable(unsigned int irq) -{ - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - - tmp = GxICR(irq); - GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE; - tmp = GxICR(irq); - - arch_local_irq_restore(flags); -} - -static void mn10300_ipi_chip_enable(struct irq_data *d) -{ - mn10300_ipi_enable(d->irq); -} - -/** - * mn10300_ipi_disable - Disable an IPI - * @irq: The IPI to be disabled. - */ -static void mn10300_ipi_disable(unsigned int irq) -{ - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - - tmp = GxICR(irq); - GxICR(irq) = tmp & GxICR_LEVEL; - tmp = GxICR(irq); - - arch_local_irq_restore(flags); -} - -static void mn10300_ipi_chip_disable(struct irq_data *d) -{ - mn10300_ipi_disable(d->irq); -} - - -/** - * mn10300_ipi_ack - Acknowledge an IPI interrupt in the PIC - * @irq: The IPI to be acknowledged. - * - * Clear the interrupt detection flag for the IPI on the appropriate interrupt - * channel in the PIC. - */ -static void mn10300_ipi_ack(struct irq_data *d) -{ - unsigned int irq = d->irq; - unsigned long flags; - u16 tmp; - - flags = arch_local_cli_save(); - GxICR_u8(irq) = GxICR_DETECT; - tmp = GxICR(irq); - arch_local_irq_restore(flags); -} - -/** - * mn10300_ipi_nop - Dummy IPI action - * @irq: The IPI to be acted upon. - */ -static void mn10300_ipi_nop(struct irq_data *d) -{ -} - -/** - * send_IPI_mask - Send IPIs to all CPUs in list - * @cpumask: The list of CPUs to target. - * @irq: The IPI request to be sent. - * - * Send the specified IPI to all the CPUs in the list, not waiting for them to - * finish before returning. The caller is responsible for synchronisation if - * that is needed. - */ -static void send_IPI_mask(const cpumask_t *cpumask, int irq) -{ - int i; - u16 tmp; - - for (i = 0; i < NR_CPUS; i++) { - if (cpumask_test_cpu(i, cpumask)) { - /* send IPI */ - tmp = CROSS_GxICR(irq, i); - CROSS_GxICR(irq, i) = - tmp | GxICR_REQUEST | GxICR_DETECT; - tmp = CROSS_GxICR(irq, i); /* flush write buffer */ - } - } -} - -/** - * send_IPI_self - Send an IPI to this CPU. - * @irq: The IPI request to be sent. - * - * Send the specified IPI to the current CPU. - */ -void send_IPI_self(int irq) -{ - send_IPI_mask(cpumask_of(smp_processor_id()), irq); -} - -/** - * send_IPI_allbutself - Send IPIs to all the other CPUs. - * @irq: The IPI request to be sent. - * - * Send the specified IPI to all CPUs in the system barring the current one, - * not waiting for them to finish before returning. The caller is responsible - * for synchronisation if that is needed. - */ -void send_IPI_allbutself(int irq) -{ - cpumask_t cpumask; - - cpumask_copy(&cpumask, cpu_online_mask); - cpumask_clear_cpu(smp_processor_id(), &cpumask); - send_IPI_mask(&cpumask, irq); -} - -void arch_send_call_function_ipi_mask(const struct cpumask *mask) -{ - BUG(); - /*send_IPI_mask(mask, CALL_FUNCTION_IPI);*/ -} - -void arch_send_call_function_single_ipi(int cpu) -{ - send_IPI_mask(cpumask_of(cpu), CALL_FUNC_SINGLE_IPI); -} - -/** - * smp_send_reschedule - Send reschedule IPI to a CPU - * @cpu: The CPU to target. - */ -void smp_send_reschedule(int cpu) -{ - send_IPI_mask(cpumask_of(cpu), RESCHEDULE_IPI); -} - -/** - * smp_nmi_call_function - Send a call function NMI IPI to all CPUs - * @func: The function to ask to be run. - * @info: The context data to pass to that function. - * @wait: If true, wait (atomically) until function is run on all CPUs. - * - * Send a non-maskable request to all CPUs in the system, requesting them to - * run the specified function with the given context data, and, potentially, to - * wait for completion of that function on all CPUs. - * - * Returns 0 if successful, -ETIMEDOUT if we were asked to wait, but hit the - * timeout. - */ -int smp_nmi_call_function(smp_call_func_t func, void *info, int wait) -{ - struct nmi_call_data_struct data; - unsigned long flags; - unsigned int cnt; - int cpus, ret = 0; - - cpus = num_online_cpus() - 1; - if (cpus < 1) - return 0; - - data.func = func; - data.info = info; - cpumask_copy(&data.started, cpu_online_mask); - cpumask_clear_cpu(smp_processor_id(), &data.started); - data.wait = wait; - if (wait) - data.finished = data.started; - - spin_lock_irqsave(&smp_nmi_call_lock, flags); - nmi_call_data = &data; - smp_mb(); - - /* Send a message to all other CPUs and wait for them to respond */ - send_IPI_allbutself(CALL_FUNCTION_NMI_IPI); - - /* Wait for response */ - if (CALL_FUNCTION_NMI_IPI_TIMEOUT > 0) { - for (cnt = 0; - cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT && - !cpumask_empty(&data.started); - cnt++) - mdelay(1); - - if (wait && cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT) { - for (cnt = 0; - cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT && - !cpumask_empty(&data.finished); - cnt++) - mdelay(1); - } - - if (cnt >= CALL_FUNCTION_NMI_IPI_TIMEOUT) - ret = -ETIMEDOUT; - - } else { - /* If timeout value is zero, wait until cpumask has been - * cleared */ - while (!cpumask_empty(&data.started)) - barrier(); - if (wait) - while (!cpumask_empty(&data.finished)) - barrier(); - } - - spin_unlock_irqrestore(&smp_nmi_call_lock, flags); - return ret; -} - -/** - * smp_jump_to_debugger - Make other CPUs enter the debugger by sending an IPI - * - * Send a non-maskable request to all other CPUs in the system, instructing - * them to jump into the debugger. The caller is responsible for checking that - * the other CPUs responded to the instruction. - * - * The caller should make sure that this CPU's debugger IPI is disabled. - */ -void smp_jump_to_debugger(void) -{ - if (num_online_cpus() > 1) - /* Send a message to all other CPUs */ - send_IPI_allbutself(DEBUGGER_NMI_IPI); -} - -/** - * stop_this_cpu - Callback to stop a CPU. - * @unused: Callback context (ignored). - */ -void stop_this_cpu(void *unused) -{ - static volatile int stopflag; - unsigned long flags; - -#ifdef CONFIG_GDBSTUB - /* In case of single stepping smp_send_stop by other CPU, - * clear procindebug to avoid deadlock. - */ - atomic_set(&procindebug[smp_processor_id()], 0); -#endif /* CONFIG_GDBSTUB */ - - flags = arch_local_cli_save(); - set_cpu_online(smp_processor_id(), false); - - while (!stopflag) - cpu_relax(); - - set_cpu_online(smp_processor_id(), true); - arch_local_irq_restore(flags); -} - -/** - * smp_send_stop - Send a stop request to all CPUs. - */ -void smp_send_stop(void) -{ - smp_nmi_call_function(stop_this_cpu, NULL, 0); -} - -/** - * smp_reschedule_interrupt - Reschedule IPI handler - * @irq: The interrupt number. - * @dev_id: The device ID. - * - * Returns IRQ_HANDLED to indicate we handled the interrupt successfully. - */ -static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id) -{ - scheduler_ipi(); - return IRQ_HANDLED; -} - -/** - * smp_call_function_interrupt - Call function IPI handler - * @irq: The interrupt number. - * @dev_id: The device ID. - * - * Returns IRQ_HANDLED to indicate we handled the interrupt successfully. - */ -static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id) -{ - /* generic_smp_call_function_interrupt(); */ - generic_smp_call_function_single_interrupt(); - return IRQ_HANDLED; -} - -/** - * smp_nmi_call_function_interrupt - Non-maskable call function IPI handler - */ -void smp_nmi_call_function_interrupt(void) -{ - smp_call_func_t func = nmi_call_data->func; - void *info = nmi_call_data->info; - int wait = nmi_call_data->wait; - - /* Notify the initiating CPU that I've grabbed the data and am about to - * execute the function - */ - smp_mb(); - cpumask_clear_cpu(smp_processor_id(), &nmi_call_data->started); - (*func)(info); - - if (wait) { - smp_mb(); - cpumask_clear_cpu(smp_processor_id(), - &nmi_call_data->finished); - } -} - -#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ - defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) -/** - * smp_ipi_timer_interrupt - Local timer IPI handler - * @irq: The interrupt number. - * @dev_id: The device ID. - * - * Returns IRQ_HANDLED to indicate we handled the interrupt successfully. - */ -static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id) -{ - return local_timer_interrupt(); -} -#endif - -void __init smp_init_cpus(void) -{ - int i; - for (i = 0; i < NR_CPUS; i++) { - set_cpu_possible(i, true); - set_cpu_present(i, true); - } -} - -/** - * smp_cpu_init - Initialise AP in start_secondary. - * - * For this Application Processor, set up init_mm, initialise FPU and set - * interrupt level 0-6 setting. - */ -static void __init smp_cpu_init(void) -{ - unsigned long flags; - int cpu_id = smp_processor_id(); - u16 tmp16; - - if (test_and_set_bit(cpu_id, &cpu_initialized)) { - printk(KERN_WARNING "CPU#%d already initialized!\n", cpu_id); - for (;;) - local_irq_enable(); - } - printk(KERN_INFO "Initializing CPU#%d\n", cpu_id); - - mmgrab(&init_mm); - current->active_mm = &init_mm; - BUG_ON(current->mm); - - enter_lazy_tlb(&init_mm, current); - - /* Force FPU initialization */ - clear_using_fpu(current); - - GxICR(CALL_FUNC_SINGLE_IPI) = CALL_FUNCTION_GxICR_LV | GxICR_DETECT; - mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); - - GxICR(LOCAL_TIMER_IPI) = LOCAL_TIMER_GxICR_LV | GxICR_DETECT; - mn10300_ipi_enable(LOCAL_TIMER_IPI); - - GxICR(RESCHEDULE_IPI) = RESCHEDULE_GxICR_LV | GxICR_DETECT; - mn10300_ipi_enable(RESCHEDULE_IPI); - -#ifdef CONFIG_MN10300_CACHE_ENABLED - GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT; - mn10300_ipi_enable(FLUSH_CACHE_IPI); -#endif - - mn10300_ipi_shutdown(SMP_BOOT_IRQ); - - /* Set up the non-maskable call function IPI */ - flags = arch_local_cli_save(); - GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; - tmp16 = GxICR(CALL_FUNCTION_NMI_IPI); - arch_local_irq_restore(flags); -} - -/** - * smp_prepare_cpu_init - Initialise CPU in startup_secondary - * - * Set interrupt level 0-6 setting and init ICR of the kernel debugger. - */ -void smp_prepare_cpu_init(void) -{ - int loop; - - /* Set the interrupt vector registers */ - IVAR0 = EXCEP_IRQ_LEVEL0; - IVAR1 = EXCEP_IRQ_LEVEL1; - IVAR2 = EXCEP_IRQ_LEVEL2; - IVAR3 = EXCEP_IRQ_LEVEL3; - IVAR4 = EXCEP_IRQ_LEVEL4; - IVAR5 = EXCEP_IRQ_LEVEL5; - IVAR6 = EXCEP_IRQ_LEVEL6; - - /* Disable all interrupts and set to priority 6 (lowest) */ - for (loop = 0; loop < GxICR_NUM_IRQS; loop++) - GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; - -#ifdef CONFIG_KERNEL_DEBUGGER - /* initialise the kernel debugger interrupt */ - do { - unsigned long flags; - u16 tmp16; - - flags = arch_local_cli_save(); - GxICR(DEBUGGER_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; - tmp16 = GxICR(DEBUGGER_NMI_IPI); - arch_local_irq_restore(flags); - } while (0); -#endif -} - -/** - * start_secondary - Activate a secondary CPU (AP) - * @unused: Thread parameter (ignored). - */ -int __init start_secondary(void *unused) -{ - smp_cpu_init(); - smp_callin(); - while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask)) - cpu_relax(); - - local_flush_tlb(); - preempt_disable(); - smp_online(); - -#ifdef CONFIG_GENERIC_CLOCKEVENTS - init_clockevents(); -#endif - cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); - return 0; -} - -/** - * smp_prepare_cpus - Boot up secondary CPUs (APs) - * @max_cpus: Maximum number of CPUs to boot. - * - * Call do_boot_cpu, and boot up APs. - */ -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - int phy_id; - - /* Setup boot CPU information */ - smp_store_cpu_info(0); - smp_tune_scheduling(); - - init_ipi(); - - /* If SMP should be disabled, then finish */ - if (max_cpus == 0) { - printk(KERN_INFO "SMP mode deactivated.\n"); - goto smp_done; - } - - /* Boot secondary CPUs (for which phy_id > 0) */ - for (phy_id = 0; phy_id < NR_CPUS; phy_id++) { - /* Don't boot primary CPU */ - if (max_cpus <= cpucount + 1) - continue; - if (phy_id != 0) - do_boot_cpu(phy_id); - set_cpu_possible(phy_id, true); - smp_show_cpu_info(phy_id); - } - -smp_done: - Dprintk("Boot done.\n"); -} - -/** - * smp_store_cpu_info - Save a CPU's information - * @cpu: The CPU to save for. - * - * Save boot_cpu_data and jiffy for the specified CPU. - */ -static void __init smp_store_cpu_info(int cpu) -{ - struct mn10300_cpuinfo *ci = &cpu_data[cpu]; - - *ci = boot_cpu_data; - ci->loops_per_jiffy = loops_per_jiffy; - ci->type = CPUREV; -} - -/** - * smp_tune_scheduling - Set time slice value - * - * Nothing to do here. - */ -static void __init smp_tune_scheduling(void) -{ -} - -/** - * do_boot_cpu: Boot up one CPU - * @phy_id: Physical ID of CPU to boot. - * - * Send an IPI to a secondary CPU to boot it. Returns 0 on success, 1 - * otherwise. - */ -static int __init do_boot_cpu(int phy_id) -{ - struct task_struct *idle; - unsigned long send_status, callin_status; - int timeout, cpu_id; - - send_status = GxICR_REQUEST; - callin_status = 0; - timeout = 0; - cpu_id = phy_id; - - cpucount++; - - /* Create idle thread for this CPU */ - idle = fork_idle(cpu_id); - if (IS_ERR(idle)) - panic("Failed fork for CPU#%d.", cpu_id); - - idle->thread.pc = (unsigned long)start_secondary; - - printk(KERN_NOTICE "Booting CPU#%d\n", cpu_id); - start_stack[cpu_id - 1] = idle->thread.sp; - - task_thread_info(idle)->cpu = cpu_id; - - /* Send boot IPI to AP */ - send_IPI_mask(cpumask_of(phy_id), SMP_BOOT_IRQ); - - Dprintk("Waiting for send to finish...\n"); - - /* Wait for AP's IPI receive in 100[ms] */ - do { - udelay(1000); - send_status = - CROSS_GxICR(SMP_BOOT_IRQ, phy_id) & GxICR_REQUEST; - } while (send_status == GxICR_REQUEST && timeout++ < 100); - - Dprintk("Waiting for cpu_callin_map.\n"); - - if (send_status == 0) { - /* Allow AP to start initializing */ - cpumask_set_cpu(cpu_id, &cpu_callout_map); - - /* Wait for setting cpu_callin_map */ - timeout = 0; - do { - udelay(1000); - callin_status = cpumask_test_cpu(cpu_id, - &cpu_callin_map); - } while (callin_status == 0 && timeout++ < 5000); - - if (callin_status == 0) - Dprintk("Not responding.\n"); - } else { - printk(KERN_WARNING "IPI not delivered.\n"); - } - - if (send_status == GxICR_REQUEST || callin_status == 0) { - cpumask_clear_cpu(cpu_id, &cpu_callout_map); - cpumask_clear_cpu(cpu_id, &cpu_callin_map); - cpumask_clear_cpu(cpu_id, &cpu_initialized); - cpucount--; - return 1; - } - return 0; -} - -/** - * smp_show_cpu_info - Show SMP CPU information - * @cpu: The CPU of interest. - */ -static void __init smp_show_cpu_info(int cpu) -{ - struct mn10300_cpuinfo *ci = &cpu_data[cpu]; - - printk(KERN_INFO - "CPU#%d : ioclk speed: %lu.%02luMHz : bogomips : %lu.%02lu\n", - cpu, - MN10300_IOCLK / 1000000, - (MN10300_IOCLK / 10000) % 100, - ci->loops_per_jiffy / (500000 / HZ), - (ci->loops_per_jiffy / (5000 / HZ)) % 100); -} - -/** - * smp_callin - Set cpu_callin_map of the current CPU ID - */ -static void __init smp_callin(void) -{ - unsigned long timeout; - int cpu; - - cpu = smp_processor_id(); - timeout = jiffies + (2 * HZ); - - if (cpumask_test_cpu(cpu, &cpu_callin_map)) { - printk(KERN_ERR "CPU#%d already present.\n", cpu); - BUG(); - } - Dprintk("CPU#%d waiting for CALLOUT\n", cpu); - - /* Wait for AP startup 2s total */ - while (time_before(jiffies, timeout)) { - if (cpumask_test_cpu(cpu, &cpu_callout_map)) - break; - cpu_relax(); - } - - if (!time_before(jiffies, timeout)) { - printk(KERN_ERR - "BUG: CPU#%d started up but did not get a callout!\n", - cpu); - BUG(); - } - -#ifdef CONFIG_CALIBRATE_DELAY - calibrate_delay(); /* Get our bogomips */ -#endif - - /* Save our processor parameters */ - smp_store_cpu_info(cpu); - - /* Allow the boot processor to continue */ - cpumask_set_cpu(cpu, &cpu_callin_map); -} - -/** - * smp_online - Set cpu_online_mask - */ -static void __init smp_online(void) -{ - int cpu; - - cpu = smp_processor_id(); - - notify_cpu_starting(cpu); - - set_cpu_online(cpu, true); - - local_irq_enable(); -} - -/** - * smp_cpus_done - - * @max_cpus: Maximum CPU count. - * - * Do nothing. - */ -void __init smp_cpus_done(unsigned int max_cpus) -{ -} - -/* - * smp_prepare_boot_cpu - Set up stuff for the boot processor. - * - * Set up the cpu_online_mask, cpu_callout_map and cpu_callin_map of the boot - * processor (CPU 0). - */ -void smp_prepare_boot_cpu(void) -{ - cpumask_set_cpu(0, &cpu_callout_map); - cpumask_set_cpu(0, &cpu_callin_map); - current_thread_info()->cpu = 0; -} - -/* - * initialize_secondary - Initialise a secondary CPU (Application Processor). - * - * Set SP register and jump to thread's PC address. - */ -void initialize_secondary(void) -{ - asm volatile ( - "mov %0,sp \n" - "jmp (%1) \n" - : - : "a"(current->thread.sp), "a"(current->thread.pc)); -} - -/** - * __cpu_up - Set smp_commenced_mask for the nominated CPU - * @cpu: The target CPU. - */ -int __cpu_up(unsigned int cpu, struct task_struct *tidle) -{ - int timeout; - -#ifdef CONFIG_HOTPLUG_CPU - if (sleep_mode[cpu]) - run_wakeup_cpu(cpu); -#endif /* CONFIG_HOTPLUG_CPU */ - - cpumask_set_cpu(cpu, &smp_commenced_mask); - - /* Wait 5s total for a response */ - for (timeout = 0 ; timeout < 5000 ; timeout++) { - if (cpu_online(cpu)) - break; - udelay(1000); - } - - BUG_ON(!cpu_online(cpu)); - return 0; -} - -/** - * setup_profiling_timer - Set up the profiling timer - * @multiplier - The frequency multiplier to use - * - * The frequency of the profiling timer can be changed by writing a multiplier - * value into /proc/profile. - */ -int setup_profiling_timer(unsigned int multiplier) -{ - return -EINVAL; -} - -/* - * CPU hotplug routines - */ -#ifdef CONFIG_HOTPLUG_CPU - -static DEFINE_PER_CPU(struct cpu, cpu_devices); - -static int __init topology_init(void) -{ - int cpu, ret; - - for_each_cpu(cpu) { - ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL); - if (ret) - printk(KERN_WARNING - "topology_init: register_cpu %d failed (%d)\n", - cpu, ret); - } - return 0; -} - -subsys_initcall(topology_init); - -int __cpu_disable(void) -{ - int cpu = smp_processor_id(); - if (cpu == 0) - return -EBUSY; - - migrate_irqs(); - cpumask_clear_cpu(cpu, &mm_cpumask(current->active_mm)); - return 0; -} - -void __cpu_die(unsigned int cpu) -{ - run_sleep_cpu(cpu); -} - -#ifdef CONFIG_MN10300_CACHE_ENABLED -static inline void hotplug_cpu_disable_cache(void) -{ - int tmp; - asm volatile( - " movhu (%1),%0 \n" - " and %2,%0 \n" - " movhu %0,(%1) \n" - "1: movhu (%1),%0 \n" - " btst %3,%0 \n" - " bne 1b \n" - : "=&r"(tmp) - : "a"(&CHCTR), - "i"(~(CHCTR_ICEN | CHCTR_DCEN)), - "i"(CHCTR_ICBUSY | CHCTR_DCBUSY) - : "memory", "cc"); -} - -static inline void hotplug_cpu_enable_cache(void) -{ - int tmp; - asm volatile( - "movhu (%1),%0 \n" - "or %2,%0 \n" - "movhu %0,(%1) \n" - : "=&r"(tmp) - : "a"(&CHCTR), - "i"(CHCTR_ICEN | CHCTR_DCEN) - : "memory", "cc"); -} - -static inline void hotplug_cpu_invalidate_cache(void) -{ - int tmp; - asm volatile ( - "movhu (%1),%0 \n" - "or %2,%0 \n" - "movhu %0,(%1) \n" - : "=&r"(tmp) - : "a"(&CHCTR), - "i"(CHCTR_ICINV | CHCTR_DCINV) - : "cc"); -} - -#else /* CONFIG_MN10300_CACHE_ENABLED */ -#define hotplug_cpu_disable_cache() do {} while (0) -#define hotplug_cpu_enable_cache() do {} while (0) -#define hotplug_cpu_invalidate_cache() do {} while (0) -#endif /* CONFIG_MN10300_CACHE_ENABLED */ - -/** - * hotplug_cpu_nmi_call_function - Call a function on other CPUs for hotplug - * @cpumask: List of target CPUs. - * @func: The function to call on those CPUs. - * @info: The context data for the function to be called. - * @wait: Whether to wait for the calls to complete. - * - * Non-maskably call a function on another CPU for hotplug purposes. - * - * This function must be called with maskable interrupts disabled. - */ -static int hotplug_cpu_nmi_call_function(cpumask_t cpumask, - smp_call_func_t func, void *info, - int wait) -{ - /* - * The address and the size of nmi_call_func_mask_data - * need to be aligned on L1_CACHE_BYTES. - */ - static struct nmi_call_data_struct nmi_call_func_mask_data - __cacheline_aligned; - unsigned long start, end; - - start = (unsigned long)&nmi_call_func_mask_data; - end = start + sizeof(struct nmi_call_data_struct); - - nmi_call_func_mask_data.func = func; - nmi_call_func_mask_data.info = info; - nmi_call_func_mask_data.started = cpumask; - nmi_call_func_mask_data.wait = wait; - if (wait) - nmi_call_func_mask_data.finished = cpumask; - - spin_lock(&smp_nmi_call_lock); - nmi_call_data = &nmi_call_func_mask_data; - mn10300_local_dcache_flush_range(start, end); - smp_wmb(); - - send_IPI_mask(cpumask, CALL_FUNCTION_NMI_IPI); - - do { - mn10300_local_dcache_inv_range(start, end); - barrier(); - } while (!cpumask_empty(&nmi_call_func_mask_data.started)); - - if (wait) { - do { - mn10300_local_dcache_inv_range(start, end); - barrier(); - } while (!cpumask_empty(&nmi_call_func_mask_data.finished)); - } - - spin_unlock(&smp_nmi_call_lock); - return 0; -} - -static void restart_wakeup_cpu(void) -{ - unsigned int cpu = smp_processor_id(); - - cpumask_set_cpu(cpu, &cpu_callin_map); - local_flush_tlb(); - set_cpu_online(cpu, true); - smp_wmb(); -} - -static void prepare_sleep_cpu(void *unused) -{ - sleep_mode[smp_processor_id()] = 1; - smp_mb(); - mn10300_local_dcache_flush_inv(); - hotplug_cpu_disable_cache(); - hotplug_cpu_invalidate_cache(); -} - -/* when this function called, IE=0, NMID=0. */ -static void sleep_cpu(void *unused) -{ - unsigned int cpu_id = smp_processor_id(); - /* - * CALL_FUNCTION_NMI_IPI for wakeup_cpu() shall not be requested, - * before this cpu goes in SLEEP mode. - */ - do { - smp_mb(); - __sleep_cpu(); - } while (sleep_mode[cpu_id]); - restart_wakeup_cpu(); -} - -static void run_sleep_cpu(unsigned int cpu) -{ - unsigned long flags; - cpumask_t cpumask; - - cpumask_copy(&cpumask, &cpumask_of(cpu)); - flags = arch_local_cli_save(); - hotplug_cpu_nmi_call_function(cpumask, prepare_sleep_cpu, NULL, 1); - hotplug_cpu_nmi_call_function(cpumask, sleep_cpu, NULL, 0); - udelay(1); /* delay for the cpu to sleep. */ - arch_local_irq_restore(flags); -} - -static void wakeup_cpu(void) -{ - hotplug_cpu_invalidate_cache(); - hotplug_cpu_enable_cache(); - smp_mb(); - sleep_mode[smp_processor_id()] = 0; -} - -static void run_wakeup_cpu(unsigned int cpu) -{ - unsigned long flags; - - flags = arch_local_cli_save(); -#if NR_CPUS == 2 - mn10300_local_dcache_flush_inv(); -#else - /* - * Before waking up the cpu, - * all online cpus should stop and flush D-Cache for global data. - */ -#error not support NR_CPUS > 2, when CONFIG_HOTPLUG_CPU=y. -#endif - hotplug_cpu_nmi_call_function(cpumask_of(cpu), wakeup_cpu, NULL, 1); - arch_local_irq_restore(flags); -} - -#endif /* CONFIG_HOTPLUG_CPU */ diff --git a/arch/mn10300/kernel/switch_to.S b/arch/mn10300/kernel/switch_to.S deleted file mode 100644 index de3e74fc9ea0..000000000000 --- a/arch/mn10300/kernel/switch_to.S +++ /dev/null @@ -1,179 +0,0 @@ -############################################################################### -# -# MN10300 Context switch operation -# -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Written by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#ifdef CONFIG_SMP -#include -#endif /* CONFIG_SMP */ - - .text - -############################################################################### -# -# struct task_struct *__switch_to(struct thread_struct *prev, -# struct thread_struct *next, -# struct task_struct *prev_task) -# -############################################################################### -ENTRY(__switch_to) - movm [d2,d3,a2,a3,exreg1],(sp) - or EPSW_NMID,epsw - - mov (44,sp),d2 - - mov d0,a0 - mov d1,a1 - - # save prev context - mov __switch_back,d0 - mov sp,a2 - mov a2,(THREAD_SP,a0) - mov a3,(THREAD_A3,a0) - -#ifdef CONFIG_KGDB - btst 0xff,(kgdb_single_step) - bne __switch_to__lift_sstep_bp -__switch_to__continue: -#endif - mov d0,(THREAD_PC,a0) - - mov (THREAD_A3,a1),a3 - mov (THREAD_SP,a1),a2 - - # switch - mov a2,sp - - # load next context - GET_THREAD_INFO a2 - mov a2,(__current_ti) - mov (TI_task,a2),a2 - mov a2,(__current) -#ifdef CONFIG_MN10300_CURRENT_IN_E2 - mov a2,e2 -#endif - - mov (THREAD_PC,a1),a2 - mov d2,d0 # for ret_from_fork - mov d0,a0 # for __switch_to - - jmp (a2) - -__switch_back: - and ~EPSW_NMID,epsw - ret [d2,d3,a2,a3,exreg1],32 - -#ifdef CONFIG_KGDB -############################################################################### -# -# Lift the single-step breakpoints when the task being traced is switched out -# A0 = prev -# A1 = next -# -############################################################################### -__switch_to__lift_sstep_bp: - add -12,sp - mov a0,e4 - mov a1,e5 - - # Clear the single-step flag to prevent us coming this way until we get - # switched back in - bclr 0xff,(kgdb_single_step) - - # Remove first breakpoint - mov (kgdb_sstep_bp_addr),a2 - cmp 0,a2 - beq 1f - movbu (kgdb_sstep_bp),d0 - movbu d0,(a2) -#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) - mov a2,d0 - mov a2,d1 - add 1,d1 - calls flush_icache_range -#endif -1: - - # Remove second breakpoint - mov (kgdb_sstep_bp_addr+4),a2 - cmp 0,a2 - beq 2f - movbu (kgdb_sstep_bp+1),d0 - movbu d0,(a2) -#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) - mov a2,d0 - mov a2,d1 - add 1,d1 - calls flush_icache_range -#endif -2: - - # Change the resumption address and return - mov __switch_back__reinstall_sstep_bp,d0 - mov e4,a0 - mov e5,a1 - add 12,sp - bra __switch_to__continue - -############################################################################### -# -# Reinstall the single-step breakpoints when the task being traced is switched -# back in (A1 points to the new thread_struct). -# -############################################################################### -__switch_back__reinstall_sstep_bp: - add -12,sp - mov a0,e4 # save the return value - mov 0xff,d3 - - # Reinstall first breakpoint - mov (kgdb_sstep_bp_addr),a2 - cmp 0,a2 - beq 1f - movbu (a2),d0 - movbu d0,(kgdb_sstep_bp) - movbu d3,(a2) -#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) - mov a2,d0 - mov a2,d1 - add 1,d1 - calls flush_icache_range -#endif -1: - - # Reinstall second breakpoint - mov (kgdb_sstep_bp_addr+4),a2 - cmp 0,a2 - beq 2f - movbu (a2),d0 - movbu d0,(kgdb_sstep_bp+1) - movbu d3,(a2) -#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE) - mov a2,d0 - mov a2,d1 - add 1,d1 - calls flush_icache_range -#endif -2: - - mov d3,(kgdb_single_step) - - # Restore the return value (the previous thread_struct pointer) - mov e4,a0 - mov a0,d0 - add 12,sp - bra __switch_back - -#endif /* CONFIG_KGDB */ diff --git a/arch/mn10300/kernel/sys_mn10300.c b/arch/mn10300/kernel/sys_mn10300.c deleted file mode 100644 index f999981e55c0..000000000000 --- a/arch/mn10300/kernel/sys_mn10300.c +++ /dev/null @@ -1,33 +0,0 @@ -/* MN10300 Weird system calls - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -asmlinkage long old_mmap(unsigned long addr, unsigned long len, - unsigned long prot, unsigned long flags, - unsigned long fd, unsigned long offset) -{ - if (offset & ~PAGE_MASK) - return -EINVAL; - return sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT); -} diff --git a/arch/mn10300/kernel/time.c b/arch/mn10300/kernel/time.c deleted file mode 100644 index 06b83b17c5f1..000000000000 --- a/arch/mn10300/kernel/time.c +++ /dev/null @@ -1,125 +0,0 @@ -/* MN10300 Low level time management - * - * Copyright (C) 2007-2008 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - Derived from arch/i386/kernel/time.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -static unsigned long mn10300_last_tsc; /* time-stamp counter at last time - * interrupt occurred */ - -static unsigned long sched_clock_multiplier; - -/* - * scheduler clock - returns current time in nanosec units. - */ -unsigned long long sched_clock(void) -{ - union { - unsigned long long ll; - unsigned l[2]; - } tsc64, result; - unsigned long tmp; - unsigned product[3]; /* 96-bit intermediate value */ - - /* cnt32_to_63() is not safe with preemption */ - preempt_disable(); - - /* expand the tsc to 64-bits. - * - sched_clock() must be called once a minute or better or the - * following will go horribly wrong - see cnt32_to_63() - */ - tsc64.ll = cnt32_to_63(get_cycles()) & 0x7fffffffffffffffULL; - - preempt_enable(); - - /* scale the 64-bit TSC value to a nanosecond value via a 96-bit - * intermediate - */ - asm("mulu %2,%0,%3,%0 \n" /* LSW * mult -> 0:%3:%0 */ - "mulu %2,%1,%2,%1 \n" /* MSW * mult -> %2:%1:0 */ - "add %3,%1 \n" - "addc 0,%2 \n" /* result in %2:%1:%0 */ - : "=r"(product[0]), "=r"(product[1]), "=r"(product[2]), "=r"(tmp) - : "0"(tsc64.l[0]), "1"(tsc64.l[1]), "2"(sched_clock_multiplier) - : "cc"); - - result.l[0] = product[1] << 16 | product[0] >> 16; - result.l[1] = product[2] << 16 | product[1] >> 16; - - return result.ll; -} - -/* - * initialise the scheduler clock - */ -static void __init mn10300_sched_clock_init(void) -{ - sched_clock_multiplier = - __muldiv64u(NSEC_PER_SEC, 1 << 16, MN10300_TSCCLK); -} - -/** - * local_timer_interrupt - Local timer interrupt handler - * - * Handle local timer interrupts for this CPU. They may have been propagated - * to this CPU from the CPU that actually gets them by way of an IPI. - */ -irqreturn_t local_timer_interrupt(void) -{ - profile_tick(CPU_PROFILING); - update_process_times(user_mode(get_irq_regs())); - return IRQ_HANDLED; -} - -/* - * initialise the various timers used by the main part of the kernel - */ -void __init time_init(void) -{ - /* we need the prescalar running to be able to use IOCLK/8 - * - IOCLK runs at 1/4 (ST5 open) or 1/8 (ST5 closed) internal CPU clock - * - IOCLK runs at Fosc rate (crystal speed) - */ - TMPSCNT |= TMPSCNT_ENABLE; - - init_clocksource(); - - printk(KERN_INFO - "timestamp counter I/O clock running at %lu.%02lu" - " (calibrated against RTC)\n", - MN10300_TSCCLK / 1000000, (MN10300_TSCCLK / 10000) % 100); - - mn10300_last_tsc = read_timestamp_counter(); - - init_clockevents(); - -#ifdef CONFIG_MN10300_WD_TIMER - /* start the watchdog timer */ - watchdog_go(); -#endif - - mn10300_sched_clock_init(); -} diff --git a/arch/mn10300/kernel/traps.c b/arch/mn10300/kernel/traps.c deleted file mode 100644 index 72d1015b2ae7..000000000000 --- a/arch/mn10300/kernel/traps.c +++ /dev/null @@ -1,615 +0,0 @@ -/* MN10300 Exception handling - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -#if (CONFIG_INTERRUPT_VECTOR_BASE & 0xffffff) -#error "INTERRUPT_VECTOR_BASE not aligned to 16MiB boundary!" -#endif - -int kstack_depth_to_print = 24; - -spinlock_t die_lock = __SPIN_LOCK_UNLOCKED(die_lock); - -struct exception_to_signal_map { - u8 signo; - u32 si_code; -}; - -static const struct exception_to_signal_map exception_to_signal_map[256] = { - /* MMU exceptions */ - [EXCEP_ITLBMISS >> 3] = { 0, 0 }, - [EXCEP_DTLBMISS >> 3] = { 0, 0 }, - [EXCEP_IAERROR >> 3] = { 0, 0 }, - [EXCEP_DAERROR >> 3] = { 0, 0 }, - - /* system exceptions */ - [EXCEP_TRAP >> 3] = { SIGTRAP, TRAP_BRKPT }, - [EXCEP_ISTEP >> 3] = { SIGTRAP, TRAP_TRACE }, /* Monitor */ - [EXCEP_IBREAK >> 3] = { SIGTRAP, TRAP_HWBKPT }, /* Monitor */ - [EXCEP_OBREAK >> 3] = { SIGTRAP, TRAP_HWBKPT }, /* Monitor */ - [EXCEP_PRIVINS >> 3] = { SIGILL, ILL_PRVOPC }, - [EXCEP_UNIMPINS >> 3] = { SIGILL, ILL_ILLOPC }, - [EXCEP_UNIMPEXINS >> 3] = { SIGILL, ILL_ILLOPC }, - [EXCEP_MEMERR >> 3] = { SIGSEGV, SEGV_ACCERR }, - [EXCEP_MISALIGN >> 3] = { SIGBUS, BUS_ADRALN }, - [EXCEP_BUSERROR >> 3] = { SIGBUS, BUS_ADRERR }, - [EXCEP_ILLINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, - [EXCEP_ILLDATACC >> 3] = { SIGSEGV, SEGV_ACCERR }, - [EXCEP_IOINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, - [EXCEP_PRIVINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, /* userspace */ - [EXCEP_PRIVDATACC >> 3] = { SIGSEGV, SEGV_ACCERR }, /* userspace */ - [EXCEP_DATINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, - [EXCEP_DOUBLE_FAULT >> 3] = { SIGILL, ILL_BADSTK }, - - /* FPU exceptions */ - [EXCEP_FPU_DISABLED >> 3] = { SIGILL, ILL_COPROC }, - [EXCEP_FPU_UNIMPINS >> 3] = { SIGILL, ILL_COPROC }, - [EXCEP_FPU_OPERATION >> 3] = { SIGFPE, FPE_INTDIV }, - - /* interrupts */ - [EXCEP_WDT >> 3] = { SIGALRM, 0 }, - [EXCEP_NMI >> 3] = { SIGQUIT, 0 }, - [EXCEP_IRQ_LEVEL0 >> 3] = { SIGINT, 0 }, - [EXCEP_IRQ_LEVEL1 >> 3] = { 0, 0 }, - [EXCEP_IRQ_LEVEL2 >> 3] = { 0, 0 }, - [EXCEP_IRQ_LEVEL3 >> 3] = { 0, 0 }, - [EXCEP_IRQ_LEVEL4 >> 3] = { 0, 0 }, - [EXCEP_IRQ_LEVEL5 >> 3] = { 0, 0 }, - [EXCEP_IRQ_LEVEL6 >> 3] = { 0, 0 }, - - /* system calls */ - [EXCEP_SYSCALL0 >> 3] = { 0, 0 }, - [EXCEP_SYSCALL1 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL2 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL3 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL4 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL5 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL6 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL7 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL8 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL9 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL10 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL11 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL12 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL13 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL14 >> 3] = { SIGILL, ILL_ILLTRP }, - [EXCEP_SYSCALL15 >> 3] = { SIGABRT, 0 }, -}; - -/* - * Handle kernel exceptions. - * - * See if there's a fixup handler we can force a jump to when an exception - * happens due to something kernel code did - */ -int die_if_no_fixup(const char *str, struct pt_regs *regs, - enum exception_code code) -{ - u8 opcode; - int signo, si_code; - - if (user_mode(regs)) - return 0; - - peripheral_leds_display_exception(code); - - signo = exception_to_signal_map[code >> 3].signo; - si_code = exception_to_signal_map[code >> 3].si_code; - - switch (code) { - /* see if we can fixup the kernel accessing memory */ - case EXCEP_ITLBMISS: - case EXCEP_DTLBMISS: - case EXCEP_IAERROR: - case EXCEP_DAERROR: - case EXCEP_MEMERR: - case EXCEP_MISALIGN: - case EXCEP_BUSERROR: - case EXCEP_ILLDATACC: - case EXCEP_IOINSACC: - case EXCEP_PRIVINSACC: - case EXCEP_PRIVDATACC: - case EXCEP_DATINSACC: - if (fixup_exception(regs)) - return 1; - break; - - case EXCEP_TRAP: - case EXCEP_UNIMPINS: - if (probe_kernel_read(&opcode, (u8 *)regs->pc, 1) < 0) - break; - if (opcode == 0xff) { - if (notify_die(DIE_BREAKPOINT, str, regs, code, 0, 0)) - return 1; - if (at_debugger_breakpoint(regs)) - regs->pc++; - signo = SIGTRAP; - si_code = TRAP_BRKPT; - } - break; - - case EXCEP_SYSCALL1 ... EXCEP_SYSCALL14: - /* syscall return addr is _after_ the instruction */ - regs->pc -= 2; - break; - - case EXCEP_SYSCALL15: - if (report_bug(regs->pc, regs) == BUG_TRAP_TYPE_WARN) - return 1; - - /* syscall return addr is _after_ the instruction */ - regs->pc -= 2; - break; - - default: - break; - } - - if (debugger_intercept(code, signo, si_code, regs) == 0) - return 1; - - if (notify_die(DIE_GPF, str, regs, code, 0, 0)) - return 1; - - /* make the process die as the last resort */ - die(str, regs, code); -} - -/* - * General exception handler - */ -asmlinkage void handle_exception(struct pt_regs *regs, u32 intcode) -{ - siginfo_t info; - - /* deal with kernel exceptions here */ - if (die_if_no_fixup(NULL, regs, intcode)) - return; - - /* otherwise it's a userspace exception */ - info.si_signo = exception_to_signal_map[intcode >> 3].signo; - info.si_code = exception_to_signal_map[intcode >> 3].si_code; - info.si_errno = 0; - info.si_addr = (void *) regs->pc; - force_sig_info(info.si_signo, &info, current); -} - -/* - * handle NMI - */ -asmlinkage void nmi(struct pt_regs *regs, enum exception_code code) -{ - /* see if gdbstub wants to deal with it */ - if (debugger_intercept(code, SIGQUIT, 0, regs)) - return; - - printk(KERN_WARNING "--- Register Dump ---\n"); - show_registers(regs); - printk(KERN_WARNING "---------------------\n"); -} - -/* - * show a stack trace from the specified stack pointer - */ -void show_trace(unsigned long *sp) -{ - unsigned long bottom, stack, addr, fp, raslot; - - printk(KERN_EMERG "\nCall Trace:\n"); - - //stack = (unsigned long)sp; - asm("mov sp,%0" : "=a"(stack)); - asm("mov a3,%0" : "=r"(fp)); - - raslot = ULONG_MAX; - bottom = (stack + THREAD_SIZE) & ~(THREAD_SIZE - 1); - for (; stack < bottom; stack += sizeof(addr)) { - addr = *(unsigned long *)stack; - if (stack == fp) { - if (addr > stack && addr < bottom) { - fp = addr; - raslot = stack + sizeof(addr); - continue; - } - fp = 0; - raslot = ULONG_MAX; - } - - if (__kernel_text_address(addr)) { - printk(" [<%08lx>]", addr); - if (stack >= raslot) - raslot = ULONG_MAX; - else - printk(" ?"); - printk(" %pS\n", (void *)addr); - } - } - - printk("\n"); -} - -/* - * show the raw stack from the specified stack pointer - */ -void show_stack(struct task_struct *task, unsigned long *sp) -{ - unsigned long *stack; - int i; - - if (!sp) - sp = (unsigned long *) &sp; - - stack = sp; - printk(KERN_EMERG "Stack:"); - for (i = 0; i < kstack_depth_to_print; i++) { - if (((long) stack & (THREAD_SIZE - 1)) == 0) - break; - if ((i % 8) == 0) - printk(KERN_EMERG " "); - printk("%08lx ", *stack++); - } - - show_trace(sp); -} - -/* - * dump the register file in the specified exception frame - */ -void show_registers_only(struct pt_regs *regs) -{ - unsigned long ssp; - - ssp = (unsigned long) regs + sizeof(*regs); - - printk(KERN_EMERG "PC: %08lx EPSW: %08lx SSP: %08lx mode: %s\n", - regs->pc, regs->epsw, ssp, user_mode(regs) ? "User" : "Super"); - printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", - regs->d0, regs->d1, regs->d2, regs->d3); - printk(KERN_EMERG "a0: %08lx a1: %08lx a2: %08lx a3: %08lx\n", - regs->a0, regs->a1, regs->a2, regs->a3); - printk(KERN_EMERG "e0: %08lx e1: %08lx e2: %08lx e3: %08lx\n", - regs->e0, regs->e1, regs->e2, regs->e3); - printk(KERN_EMERG "e4: %08lx e5: %08lx e6: %08lx e7: %08lx\n", - regs->e4, regs->e5, regs->e6, regs->e7); - printk(KERN_EMERG "lar: %08lx lir: %08lx mdr: %08lx usp: %08lx\n", - regs->lar, regs->lir, regs->mdr, regs->sp); - printk(KERN_EMERG "cvf: %08lx crl: %08lx crh: %08lx drq: %08lx\n", - regs->mcvf, regs->mcrl, regs->mcrh, regs->mdrq); - printk(KERN_EMERG "threadinfo=%p task=%p)\n", - current_thread_info(), current); - - if ((unsigned long) current >= PAGE_OFFSET && - (unsigned long) current < (unsigned long)high_memory) - printk(KERN_EMERG "Process %s (pid: %d)\n", - current->comm, current->pid); - -#ifdef CONFIG_SMP - printk(KERN_EMERG "CPUID: %08x\n", CPUID); -#endif - printk(KERN_EMERG "CPUP: %04hx\n", CPUP); - printk(KERN_EMERG "TBR: %08x\n", TBR); - printk(KERN_EMERG "DEAR: %08x\n", DEAR); - printk(KERN_EMERG "sISR: %08x\n", sISR); - printk(KERN_EMERG "NMICR: %04hx\n", NMICR); - printk(KERN_EMERG "BCBERR: %08x\n", BCBERR); - printk(KERN_EMERG "BCBEAR: %08x\n", BCBEAR); - printk(KERN_EMERG "MMUFCR: %08x\n", MMUFCR); - printk(KERN_EMERG "IPTEU : %08x IPTEL2: %08x\n", IPTEU, IPTEL2); - printk(KERN_EMERG "DPTEU: %08x DPTEL2: %08x\n", DPTEU, DPTEL2); -} - -/* - * dump the registers and the stack - */ -void show_registers(struct pt_regs *regs) -{ - unsigned long sp; - int i; - - show_registers_only(regs); - - if (!user_mode(regs)) - sp = (unsigned long) regs + sizeof(*regs); - else - sp = regs->sp; - - /* when in-kernel, we also print out the stack and code at the - * time of the fault.. - */ - if (!user_mode(regs)) { - printk(KERN_EMERG "\n"); - show_stack(current, (unsigned long *) sp); - -#if 0 - printk(KERN_EMERG "\nCode: "); - if (regs->pc < PAGE_OFFSET) - goto bad; - - for (i = 0; i < 20; i++) { - unsigned char c; - if (__get_user(c, &((unsigned char *) regs->pc)[i])) - goto bad; - printk("%02x ", c); - } -#else - i = 0; -#endif - } - - printk("\n"); - return; - -#if 0 -bad: - printk(KERN_EMERG " Bad PC value."); - break; -#endif -} - -/* - * - */ -void show_trace_task(struct task_struct *tsk) -{ - unsigned long sp = tsk->thread.sp; - - /* User space on another CPU? */ - if ((sp ^ (unsigned long) tsk) & (PAGE_MASK << 1)) - return; - - show_trace((unsigned long *) sp); -} - -/* - * note the untimely death of part of the kernel - */ -void die(const char *str, struct pt_regs *regs, enum exception_code code) -{ - console_verbose(); - spin_lock_irq(&die_lock); - printk(KERN_EMERG "\n%s: %04x\n", - str, code & 0xffff); - show_registers(regs); - - if (regs->pc >= 0x02000000 && regs->pc < 0x04000000 && - (regs->epsw & (EPSW_IM | EPSW_IE)) != (EPSW_IM | EPSW_IE)) { - printk(KERN_EMERG "Exception in usermode interrupt handler\n"); - printk(KERN_EMERG "\nPlease connect to kernel debugger !!\n"); - asm volatile ("0: bra 0b"); - } - - spin_unlock_irq(&die_lock); - do_exit(SIGSEGV); -} - -/* - * display the register file when the stack pointer gets clobbered - */ -asmlinkage void do_double_fault(struct pt_regs *regs) -{ - struct task_struct *tsk = current; - - strcpy(tsk->comm, "emergency tsk"); - tsk->pid = 0; - console_verbose(); - printk(KERN_EMERG "--- double fault ---\n"); - show_registers(regs); -} - -/* - * asynchronous bus error (external, usually I/O DMA) - */ -asmlinkage void io_bus_error(u32 bcberr, u32 bcbear, struct pt_regs *regs) -{ - console_verbose(); - - printk(KERN_EMERG "Asynchronous I/O Bus Error\n"); - printk(KERN_EMERG "==========================\n"); - - if (bcberr & BCBERR_BEME) - printk(KERN_EMERG "- Multiple recorded errors\n"); - - printk(KERN_EMERG "- Faulting Buses:%s%s%s\n", - bcberr & BCBERR_BEMR_CI ? " CPU-Ins-Fetch" : "", - bcberr & BCBERR_BEMR_CD ? " CPU-Data" : "", - bcberr & BCBERR_BEMR_DMA ? " DMA" : ""); - - printk(KERN_EMERG "- %s %s access made to %s at address %08x\n", - bcberr & BCBERR_BEBST ? "Burst" : "Single", - bcberr & BCBERR_BERW ? "Read" : "Write", - bcberr & BCBERR_BESB_MON ? "Monitor Space" : - bcberr & BCBERR_BESB_IO ? "Internal CPU I/O Space" : - bcberr & BCBERR_BESB_EX ? "External I/O Bus" : - bcberr & BCBERR_BESB_OPEX ? "External Memory Bus" : - "On Chip Memory", - bcbear - ); - - printk(KERN_EMERG "- Detected by the %s\n", - bcberr&BCBERR_BESD ? "Bus Control Unit" : "Slave Bus"); - -#ifdef CONFIG_PCI -#define BRIDGEREGB(X) (*(volatile __u8 *)(0xBE040000 + (X))) -#define BRIDGEREGW(X) (*(volatile __u16 *)(0xBE040000 + (X))) -#define BRIDGEREGL(X) (*(volatile __u32 *)(0xBE040000 + (X))) - - printk(KERN_EMERG "- PCI Memory Paging Reg: %08x\n", - *(volatile __u32 *) (0xBFFFFFF4)); - printk(KERN_EMERG "- PCI Bridge Base Address 0: %08x\n", - BRIDGEREGL(PCI_BASE_ADDRESS_0)); - printk(KERN_EMERG "- PCI Bridge AMPCI Base Address: %08x\n", - BRIDGEREGL(0x48)); - printk(KERN_EMERG "- PCI Bridge Command: %04hx\n", - BRIDGEREGW(PCI_COMMAND)); - printk(KERN_EMERG "- PCI Bridge Status: %04hx\n", - BRIDGEREGW(PCI_STATUS)); - printk(KERN_EMERG "- PCI Bridge Int Status: %08hx\n", - BRIDGEREGL(0x4c)); -#endif - - printk(KERN_EMERG "\n"); - show_registers(regs); - - panic("Halted due to asynchronous I/O Bus Error\n"); -} - -/* - * handle an exception for which a handler has not yet been installed - */ -asmlinkage void uninitialised_exception(struct pt_regs *regs, - enum exception_code code) -{ - - /* see if gdbstub wants to deal with it */ - if (debugger_intercept(code, SIGSYS, 0, regs) == 0) - return; - - peripheral_leds_display_exception(code); - printk(KERN_EMERG "Uninitialised Exception 0x%04x\n", code & 0xFFFF); - show_registers(regs); - - for (;;) - continue; -} - -/* - * set an interrupt stub to jump to a handler - * ! NOTE: this does *not* flush the caches - */ -void __init __set_intr_stub(enum exception_code code, void *handler) -{ - unsigned long addr; - u8 *vector = (u8 *)(CONFIG_INTERRUPT_VECTOR_BASE + code); - - addr = (unsigned long) handler - (unsigned long) vector; - vector[0] = 0xdc; /* JMP handler */ - vector[1] = addr; - vector[2] = addr >> 8; - vector[3] = addr >> 16; - vector[4] = addr >> 24; - vector[5] = 0xcb; - vector[6] = 0xcb; - vector[7] = 0xcb; -} - -/* - * set an interrupt stub to jump to a handler - */ -void __init set_intr_stub(enum exception_code code, void *handler) -{ - unsigned long addr; - u8 *vector = (u8 *)(CONFIG_INTERRUPT_VECTOR_BASE + code); - unsigned long flags; - - addr = (unsigned long) handler - (unsigned long) vector; - - flags = arch_local_cli_save(); - - vector[0] = 0xdc; /* JMP handler */ - vector[1] = addr; - vector[2] = addr >> 8; - vector[3] = addr >> 16; - vector[4] = addr >> 24; - vector[5] = 0xcb; - vector[6] = 0xcb; - vector[7] = 0xcb; - - arch_local_irq_restore(flags); - -#ifndef CONFIG_MN10300_CACHE_SNOOP - mn10300_dcache_flush_inv(); - mn10300_icache_inv(); -#endif -} - -/* - * initialise the exception table - */ -void __init trap_init(void) -{ - set_excp_vector(EXCEP_TRAP, handle_exception); - set_excp_vector(EXCEP_ISTEP, handle_exception); - set_excp_vector(EXCEP_IBREAK, handle_exception); - set_excp_vector(EXCEP_OBREAK, handle_exception); - - set_excp_vector(EXCEP_PRIVINS, handle_exception); - set_excp_vector(EXCEP_UNIMPINS, handle_exception); - set_excp_vector(EXCEP_UNIMPEXINS, handle_exception); - set_excp_vector(EXCEP_MEMERR, handle_exception); - set_excp_vector(EXCEP_MISALIGN, misalignment); - set_excp_vector(EXCEP_BUSERROR, handle_exception); - set_excp_vector(EXCEP_ILLINSACC, handle_exception); - set_excp_vector(EXCEP_ILLDATACC, handle_exception); - set_excp_vector(EXCEP_IOINSACC, handle_exception); - set_excp_vector(EXCEP_PRIVINSACC, handle_exception); - set_excp_vector(EXCEP_PRIVDATACC, handle_exception); - set_excp_vector(EXCEP_DATINSACC, handle_exception); - set_excp_vector(EXCEP_FPU_UNIMPINS, handle_exception); - set_excp_vector(EXCEP_FPU_OPERATION, fpu_exception); - - set_excp_vector(EXCEP_NMI, nmi); - - set_excp_vector(EXCEP_SYSCALL1, handle_exception); - set_excp_vector(EXCEP_SYSCALL2, handle_exception); - set_excp_vector(EXCEP_SYSCALL3, handle_exception); - set_excp_vector(EXCEP_SYSCALL4, handle_exception); - set_excp_vector(EXCEP_SYSCALL5, handle_exception); - set_excp_vector(EXCEP_SYSCALL6, handle_exception); - set_excp_vector(EXCEP_SYSCALL7, handle_exception); - set_excp_vector(EXCEP_SYSCALL8, handle_exception); - set_excp_vector(EXCEP_SYSCALL9, handle_exception); - set_excp_vector(EXCEP_SYSCALL10, handle_exception); - set_excp_vector(EXCEP_SYSCALL11, handle_exception); - set_excp_vector(EXCEP_SYSCALL12, handle_exception); - set_excp_vector(EXCEP_SYSCALL13, handle_exception); - set_excp_vector(EXCEP_SYSCALL14, handle_exception); - set_excp_vector(EXCEP_SYSCALL15, handle_exception); -} - -/* - * determine if a program counter value is a valid bug address - */ -int is_valid_bugaddr(unsigned long pc) -{ - return pc >= PAGE_OFFSET; -} diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S deleted file mode 100644 index 2d5f1c3f1afb..000000000000 --- a/arch/mn10300/kernel/vmlinux.lds.S +++ /dev/null @@ -1,94 +0,0 @@ -/* MN10300 Main kernel linker script - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#define __VMLINUX_LDS__ -#include -#include -#include - -OUTPUT_FORMAT("elf32-am33lin", "elf32-am33lin", "elf32-am33lin") -OUTPUT_ARCH(mn10300) -ENTRY(_start) -jiffies = jiffies_64; -#ifndef CONFIG_MN10300_CURRENT_IN_E2 -current = __current; -#endif -SECTIONS -{ - . = CONFIG_KERNEL_TEXT_ADDRESS; - /* read-only */ - _stext = .; - _text = .; /* Text and read-only data */ - .text : { - HEAD_TEXT - TEXT_TEXT - SCHED_TEXT - CPUIDLE_TEXT - LOCK_TEXT - KPROBES_TEXT - *(.fixup) - *(.gnu.warning) - } = 0xcb - - _etext = .; /* End of text section */ - - EXCEPTION_TABLE(16) - BUG_TABLE - - RO_DATA(PAGE_SIZE) - - /* writeable */ - _sdata = .; /* Start of rw data section */ - RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) - _edata = .; - - /* might get freed after init */ - . = ALIGN(PAGE_SIZE); - .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { - __smp_locks = .; - *(.smp_locks) - __smp_locks_end = .; - } - - /* will be freed after init */ - . = ALIGN(PAGE_SIZE); /* Init code and data */ - __init_begin = .; - INIT_TEXT_SECTION(PAGE_SIZE) - INIT_DATA_SECTION(16) - . = ALIGN(4); - __alt_instructions = .; - .altinstructions : { *(.altinstructions) } - __alt_instructions_end = .; - .altinstr_replacement : { *(.altinstr_replacement) } - /* .exit.text is discard at runtime, not link time, to deal with references - from .altinstructions and .eh_frame */ - .exit.text : { EXIT_TEXT; } - .exit.data : { EXIT_DATA; } - - PERCPU_SECTION(32) - . = ALIGN(PAGE_SIZE); - __init_end = .; - /* freed after init ends here */ - - BSS_SECTION(0, PAGE_SIZE, 4) - - _end = . ; - - /* This is where the kernel creates the early boot page tables */ - . = ALIGN(PAGE_SIZE); - pg0 = .; - - STABS_DEBUG - - DWARF_DEBUG - - /* Sections to be discarded */ - DISCARDS -} diff --git a/arch/mn10300/lib/Makefile b/arch/mn10300/lib/Makefile deleted file mode 100644 index 0cd2346f4c13..000000000000 --- a/arch/mn10300/lib/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for the MN10300-specific library files.. -# - -lib-y = delay.o usercopy.o checksum.o bitops.o memcpy.o memmove.o memset.o -lib-y += do_csum.o -lib-y += __ashldi3.o __ashrdi3.o __lshrdi3.o negdi2.o __ucmpdi2.o diff --git a/arch/mn10300/lib/__ashldi3.S b/arch/mn10300/lib/__ashldi3.S deleted file mode 100644 index a51a9506f00c..000000000000 --- a/arch/mn10300/lib/__ashldi3.S +++ /dev/null @@ -1,51 +0,0 @@ -/* MN10300 64-bit arithmetic left shift - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - - .text - .balign L1_CACHE_BYTES - -############################################################################### -# -# unsigned long long __ashldi3(unsigned long long value [D1:D0], -# unsigned by [(12,SP)]) -# -############################################################################### - .globl __ashldi3 - .type __ashldi3,@function -__ashldi3: - mov (12,sp),a0 - and +63,a0 - beq __ashldi3_zero - - cmp +31,a0 - bhi __ashldi3_32plus - - # the count is in the range 1-31 - asl a0,d1 - - mov +32,a1 - sub a0,a1,a1 # a1 = 32 - count - lsr a1,d0,a1 # get overflow from LSW -> MSW - - or_asl a1,d1,a0,d0 # insert overflow into MSW and - # shift the LSW - rets - - .balign L1_CACHE_BYTES - # the count is in the range 32-63 -__ashldi3_32plus: - asl a0,d0,d1 - clr d0 -__ashldi3_zero: - rets - - .size __ashldi3, .-__ashldi3 diff --git a/arch/mn10300/lib/__ashrdi3.S b/arch/mn10300/lib/__ashrdi3.S deleted file mode 100644 index 6f42382728cb..000000000000 --- a/arch/mn10300/lib/__ashrdi3.S +++ /dev/null @@ -1,52 +0,0 @@ -/* MN10300 64-bit arithmetic right shift - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - - .text - .balign L1_CACHE_BYTES - -############################################################################### -# -# unsigned long long __ashrdi3(unsigned long long value [D1:D0], -# unsigned by [(12,SP)]) -# -############################################################################### - .globl __ashrdi3 - .type __ashrdi3,@function -__ashrdi3: - mov (12,sp),a0 - and +63,a0 - beq __ashrdi3_zero - - cmp +31,a0 - bhi __ashrdi3_32plus - - # the count is in the range 1-31 - lsr a0,d0 - - mov +32,a1 - sub a0,a1,a1 # a1 = 32 - count - asl a1,d1,a1 # get underflow from MSW -> LSW - - or_asr a1,d0,a0,d1 # insert underflow into LSW and - # shift the MSW - rets - - .balign L1_CACHE_BYTES - # the count is in the range 32-63 -__ashrdi3_32plus: - asr a0,d1,d0 - ext d0 # sign-extend result through MDR - mov mdr,d1 -__ashrdi3_zero: - rets - - .size __ashrdi3, .-__ashrdi3 diff --git a/arch/mn10300/lib/__lshrdi3.S b/arch/mn10300/lib/__lshrdi3.S deleted file mode 100644 index a686aef31e90..000000000000 --- a/arch/mn10300/lib/__lshrdi3.S +++ /dev/null @@ -1,52 +0,0 @@ -/* MN10300 64-bit logical right shift - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include - - .text - .balign L1_CACHE_BYTES - -############################################################################### -# -# unsigned long long __lshrdi3(unsigned long long value [D1:D0], -# unsigned by [(12,SP)]) -# -############################################################################### - .globl __lshrdi3 - .type __lshrdi3,@function -__lshrdi3: - mov (12,sp),a0 - and +63,a0 - beq __lshrdi3_zero - - cmp +31,a0 - bhi __lshrdi3_32plus - - # the count is in the range 1-31 - lsr a0,d0 - - mov +32,a1 - sub a0,a1,a1 # a1 = 32 - count - asl a1,d1,a1 # get underflow from MSW -> LSW - - or_lsr a1,d0,a0,d1 # insert underflow into LSW and - # shift the MSW - rets - - .balign L1_CACHE_BYTES - # the count is in the range 32-63 -__lshrdi3_32plus: - lsr a0,d1,d0 - clr d1 -__lshrdi3_zero: - rets - - .size __lshrdi3, .-__lshrdi3 diff --git a/arch/mn10300/lib/__ucmpdi2.S b/arch/mn10300/lib/__ucmpdi2.S deleted file mode 100644 index 60dcbdfe386c..000000000000 --- a/arch/mn10300/lib/__ucmpdi2.S +++ /dev/null @@ -1,43 +0,0 @@ -/* __ucmpdi2.S: 64-bit unsigned compare - * - * Copyright (C) 2008 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - - - .text - .p2align 4 - -############################################################################### -# -# int __ucmpdi2(unsigned long long a [D0:D1], -# unsigned long long b [(SP,12),(SP,16)]) -# -# - returns 0, 1, or 2 as a <, =, > b respectively. -# -############################################################################### - .globl __ucmpdi2 - .type __ucmpdi2,@function -__ucmpdi2: - mov (12,sp),a0 # b.lsw - mov (16,sp),a1 # b.msw - - sub a0,d0 - subc a1,d1 # may clear Z, never sets it - bne __ucmpdi2_differ # a.msw != b.msw - mov +1,d0 - rets - -__ucmpdi2_differ: - # C flag is set if LE, clear if GE - subc d0,d0 # -1 if LE, 0 if GE - add +1,d0 # 0 if LE, 1 if GE - add d0,d0 # 0 if LE, 2 if GE - rets - - .size __ucmpdi2, .-__ucmpdi2 diff --git a/arch/mn10300/lib/ashrdi3.c b/arch/mn10300/lib/ashrdi3.c deleted file mode 100644 index c54f61ddf0b5..000000000000 --- a/arch/mn10300/lib/ashrdi3.c +++ /dev/null @@ -1,61 +0,0 @@ -/* ashrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */ -/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public Licence as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public Licence for more details. - -You should have received a copy of the GNU General Public Licence -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define BITS_PER_UNIT 8 - -typedef int SItype __attribute__((mode(SI))); -typedef unsigned int USItype __attribute__((mode(SI))); -typedef int DItype __attribute__((mode(DI))); -typedef int word_type __attribute__((mode(__word__))); - -struct DIstruct { - SItype low; - SItype high; -}; - -union DIunion { - struct DIstruct s; - DItype ll; -}; - -DItype __ashrdi3(DItype u, word_type b) -{ - union DIunion w; - union DIunion uu; - word_type bm; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof(SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) { - /* w.s.high = 1..1 or 0..0 */ - w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1); - w.s.low = uu.s.high >> -bm; - } else { - USItype carries = (USItype)uu.s.high << bm; - w.s.high = uu.s.high >> b; - w.s.low = ((USItype)uu.s.low >> b) | carries; - } - - return w.ll; -} diff --git a/arch/mn10300/lib/bitops.c b/arch/mn10300/lib/bitops.c deleted file mode 100644 index 37309cdb7584..000000000000 --- a/arch/mn10300/lib/bitops.c +++ /dev/null @@ -1,50 +0,0 @@ -/* MN10300 Non-trivial bit operations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include - -/* - * try flipping a bit using BSET and BCLR - */ -void change_bit(unsigned long nr, volatile void *addr) -{ - if (test_bit(nr, addr)) - goto try_clear_bit; - -try_set_bit: - if (!test_and_set_bit(nr, addr)) - return; - -try_clear_bit: - if (test_and_clear_bit(nr, addr)) - return; - - goto try_set_bit; -} - -/* - * try flipping a bit using BSET and BCLR and returning the old value - */ -int test_and_change_bit(unsigned long nr, volatile void *addr) -{ - if (test_bit(nr, addr)) - goto try_clear_bit; - -try_set_bit: - if (!test_and_set_bit(nr, addr)) - return 0; - -try_clear_bit: - if (test_and_clear_bit(nr, addr)) - return 1; - - goto try_set_bit; -} diff --git a/arch/mn10300/lib/checksum.c b/arch/mn10300/lib/checksum.c deleted file mode 100644 index 0f569151ef11..000000000000 --- a/arch/mn10300/lib/checksum.c +++ /dev/null @@ -1,100 +0,0 @@ -/* MN10300 Optimised checksumming wrappers - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include "internal.h" - -static inline unsigned short from32to16(__wsum sum) -{ - asm(" add %1,%0 \n" - " addc 0xffff,%0 \n" - : "=r" (sum) - : "r" (sum << 16), "0" (sum & 0xffff0000) - : "cc" - ); - return sum >> 16; -} - -__sum16 ip_fast_csum(const void *iph, unsigned int ihl) -{ - return ~do_csum(iph, ihl * 4); -} -EXPORT_SYMBOL(ip_fast_csum); - -__wsum csum_partial(const void *buff, int len, __wsum sum) -{ - __wsum result; - - result = do_csum(buff, len); - result += sum; - if (sum > result) - result++; - return result; -} -EXPORT_SYMBOL(csum_partial); - -__sum16 ip_compute_csum(const void *buff, int len) -{ - return ~from32to16(do_csum(buff, len)); -} -EXPORT_SYMBOL(ip_compute_csum); - -__wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum) -{ - copy_from_user(dst, src, len); - return csum_partial(dst, len, sum); -} -EXPORT_SYMBOL(csum_partial_copy); - -__wsum csum_partial_copy_nocheck(const void *src, void *dst, - int len, __wsum sum) -{ - sum = csum_partial(src, len, sum); - memcpy(dst, src, len); - return sum; -} -EXPORT_SYMBOL(csum_partial_copy_nocheck); - -__wsum csum_partial_copy_from_user(const void *src, void *dst, - int len, __wsum sum, - int *err_ptr) -{ - int missing; - - missing = copy_from_user(dst, src, len); - if (missing) { - memset(dst + len - missing, 0, missing); - *err_ptr = -EFAULT; - } - - return csum_partial(dst, len, sum); -} -EXPORT_SYMBOL(csum_partial_copy_from_user); - -__wsum csum_and_copy_to_user(const void *src, void *dst, - int len, __wsum sum, - int *err_ptr) -{ - int missing; - - missing = copy_to_user(dst, src, len); - if (missing) { - memset(dst + len - missing, 0, missing); - *err_ptr = -EFAULT; - } - - return csum_partial(src, len, sum); -} -EXPORT_SYMBOL(csum_and_copy_to_user); diff --git a/arch/mn10300/lib/delay.c b/arch/mn10300/lib/delay.c deleted file mode 100644 index 8e7ceb8ba33d..000000000000 --- a/arch/mn10300/lib/delay.c +++ /dev/null @@ -1,51 +0,0 @@ -/* MN10300 Short delay interpolation routines - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include - -/* - * basic delay loop - */ -void __delay(unsigned long loops) -{ - int d0; - - asm volatile( - " bra 1f \n" - " .align 4 \n" - "1: bra 2f \n" - " .align 4 \n" - "2: add -1,%0 \n" - " bne 2b \n" - : "=&d" (d0) - : "0" (loops) - : "cc"); -} -EXPORT_SYMBOL(__delay); - -/* - * handle a delay specified in terms of microseconds - */ -void __udelay(unsigned long usecs) -{ - unsigned long start, stop, cnt; - - /* usecs * CLK / 1E6 */ - stop = __muldiv64u(usecs, MN10300_TSCCLK, 1000000); - start = TMTSCBC; - - do { - cnt = start - TMTSCBC; - } while (cnt < stop); -} -EXPORT_SYMBOL(__udelay); diff --git a/arch/mn10300/lib/do_csum.S b/arch/mn10300/lib/do_csum.S deleted file mode 100644 index 1d27bba0cd8f..000000000000 --- a/arch/mn10300/lib/do_csum.S +++ /dev/null @@ -1,157 +0,0 @@ -/* Optimised simple memory checksum - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - - .section .text - .balign L1_CACHE_BYTES - -############################################################################### -# -# unsigned int do_csum(const unsigned char *buff, int len) -# -############################################################################### - .globl do_csum - .type do_csum,@function -do_csum: - movm [d2,d3],(sp) - mov d1,d2 # count - mov d0,a0 # buff - mov a0,a1 - clr d1 # accumulator - - cmp +0,d2 - ble do_csum_done # check for zero length or negative - - # 4-byte align the buffer pointer - btst +3,a0 - beq do_csum_now_4b_aligned - - btst +1,a0 - beq do_csum_addr_not_odd - movbu (a0),d0 - inc a0 - asl +8,d0 - add d0,d1 - add -1,d2 - -do_csum_addr_not_odd: - cmp +2,d2 - bcs do_csum_fewer_than_4 - btst +2,a0 - beq do_csum_now_4b_aligned - movhu (a0+),d0 - add d0,d1 - add -2,d2 - cmp +4,d2 - bcs do_csum_fewer_than_4 - -do_csum_now_4b_aligned: - # we want to checksum as much as we can in chunks of 32 bytes - cmp +31,d2 - bls do_csum_remainder # 4-byte aligned remainder - - add -32,d2 - mov +32,d3 - -do_csum_loop: - mov (a0+),d0 - mov (a0+),e0 - mov (a0+),e1 - mov (a0+),e3 - add d0,d1 - addc e0,d1 - addc e1,d1 - addc e3,d1 - mov (a0+),d0 - mov (a0+),e0 - mov (a0+),e1 - mov (a0+),e3 - addc d0,d1 - addc e0,d1 - addc e1,d1 - addc e3,d1 - addc +0,d1 - - sub d3,d2 - bcc do_csum_loop - - add d3,d2 - beq do_csum_done - -do_csum_remainder: - # cut 16-31 bytes down to 0-15 - cmp +16,d2 - bcs do_csum_fewer_than_16 - mov (a0+),d0 - mov (a0+),e0 - mov (a0+),e1 - mov (a0+),e3 - add d0,d1 - addc e0,d1 - addc e1,d1 - addc e3,d1 - addc +0,d1 - add -16,d2 - beq do_csum_done - -do_csum_fewer_than_16: - # copy the remaining whole words - cmp +4,d2 - bcs do_csum_fewer_than_4 - cmp +8,d2 - bcs do_csum_one_word - cmp +12,d2 - bcs do_csum_two_words - mov (a0+),d0 - add d0,d1 - addc +0,d1 -do_csum_two_words: - mov (a0+),d0 - add d0,d1 - addc +0,d1 -do_csum_one_word: - mov (a0+),d0 - add d0,d1 - addc +0,d1 - -do_csum_fewer_than_4: - and +3,d2 - beq do_csum_done - xor_cmp d0,d0,+2,d2 - bcs do_csum_fewer_than_2 - movhu (a0+),d0 - and +1,d2 - beq do_csum_add_last_bit -do_csum_fewer_than_2: - movbu (a0),d3 - add d3,d0 -do_csum_add_last_bit: - add d0,d1 - addc +0,d1 - -do_csum_done: - # compress the checksum down to 16 bits - mov +0xffff0000,d0 - and d1,d0 - asl +16,d1 - add d1,d0 - addc +0xffff,d0 - lsr +16,d0 - - # flip the halves of the word result if the buffer was oddly aligned - and +1,a1 - beq do_csum_not_oddly_aligned - swaph d0,d0 # exchange bits 15:8 with 7:0 - -do_csum_not_oddly_aligned: - ret [d2,d3],8 - - .size do_csum, .-do_csum diff --git a/arch/mn10300/lib/internal.h b/arch/mn10300/lib/internal.h deleted file mode 100644 index 0014eee5f04f..000000000000 --- a/arch/mn10300/lib/internal.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Internal definitions for the arch part of the kernel library - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -/* - * do_csum.S - */ -extern unsigned int do_csum(const unsigned char *, size_t); diff --git a/arch/mn10300/lib/lshrdi3.c b/arch/mn10300/lib/lshrdi3.c deleted file mode 100644 index e05e64e9ce96..000000000000 --- a/arch/mn10300/lib/lshrdi3.c +++ /dev/null @@ -1,60 +0,0 @@ -/* lshrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */ -/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public Licence as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public Licence for more details. - -You should have received a copy of the GNU General Public Licence -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#define BITS_PER_UNIT 8 - -typedef int SItype __attribute__((mode(SI))); -typedef unsigned int USItype __attribute__((mode(SI))); -typedef int DItype __attribute__((mode(DI))); -typedef int word_type __attribute__((mode(__word__))); - -struct DIstruct { - SItype low; - SItype high; -}; - -union DIunion { - struct DIstruct s; - DItype ll; -}; - -DItype __lshrdi3(DItype u, word_type b) -{ - union DIunion w; - word_type bm; - union DIunion uu; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof(SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) { - w.s.high = 0; - w.s.low = (USItype) uu.s.high >> -bm; - } else { - USItype carries = (USItype) uu.s.high << bm; - w.s.high = (USItype) uu.s.high >> b; - w.s.low = ((USItype) uu.s.low >> b) | carries; - } - - return w.ll; -} diff --git a/arch/mn10300/lib/memcpy.S b/arch/mn10300/lib/memcpy.S deleted file mode 100644 index 25fb9bb2604f..000000000000 --- a/arch/mn10300/lib/memcpy.S +++ /dev/null @@ -1,135 +0,0 @@ -/* MN10300 Optimised simple memory to memory copy - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - - .section .text - .balign L1_CACHE_BYTES - -############################################################################### -# -# void *memcpy(void *dst, const void *src, size_t n) -# -############################################################################### - .globl memcpy - .type memcpy,@function -memcpy: - movm [d2,d3],(sp) - mov d0,(12,sp) - mov d1,(16,sp) - mov (20,sp),d2 # count - mov d0,a0 # dst - mov d1,a1 # src - mov d0,e3 # the return value - - cmp +0,d2 - beq memcpy_done # return if zero-length copy - - # see if the three parameters are all four-byte aligned - or d0,d1,d3 - or d2,d3 - and +3,d3 - bne memcpy_1 # jump if not - - # we want to transfer as much as we can in chunks of 32 bytes - cmp +31,d2 - bls memcpy_4_remainder # 4-byte aligned remainder - - movm [exreg1],(sp) - add -32,d2 - mov +32,d3 - -memcpy_4_loop: - mov (a1+),d0 - mov (a1+),d1 - mov (a1+),e0 - mov (a1+),e1 - mov (a1+),e4 - mov (a1+),e5 - mov (a1+),e6 - mov (a1+),e7 - mov d0,(a0+) - mov d1,(a0+) - mov e0,(a0+) - mov e1,(a0+) - mov e4,(a0+) - mov e5,(a0+) - mov e6,(a0+) - mov e7,(a0+) - - sub d3,d2 - bcc memcpy_4_loop - - movm (sp),[exreg1] - add d3,d2 - beq memcpy_4_no_remainder - -memcpy_4_remainder: - # cut 4-7 words down to 0-3 - cmp +16,d2 - bcs memcpy_4_three_or_fewer_words - mov (a1+),d0 - mov (a1+),d1 - mov (a1+),e0 - mov (a1+),e1 - mov d0,(a0+) - mov d1,(a0+) - mov e0,(a0+) - mov e1,(a0+) - add -16,d2 - beq memcpy_4_no_remainder - - # copy the remaining 1, 2 or 3 words -memcpy_4_three_or_fewer_words: - cmp +8,d2 - bcs memcpy_4_one_word - beq memcpy_4_two_words - mov (a1+),d0 - mov d0,(a0+) -memcpy_4_two_words: - mov (a1+),d0 - mov d0,(a0+) -memcpy_4_one_word: - mov (a1+),d0 - mov d0,(a0+) - -memcpy_4_no_remainder: - # check we copied the correct amount - # TODO: REMOVE CHECK - sub e3,a0,d2 - mov (20,sp),d1 - cmp d2,d1 - beq memcpy_done - break - break - break - -memcpy_done: - mov e3,a0 - ret [d2,d3],8 - - # handle misaligned copying -memcpy_1: - add -1,d2 - mov +1,d3 - setlb # setlb requires the next insns - # to occupy exactly 4 bytes - - sub d3,d2 - movbu (a1),d0 - movbu d0,(a0) - add_add d3,a1,d3,a0 - lcc - - mov e3,a0 - ret [d2,d3],8 - -memcpy_end: - .size memcpy, memcpy_end-memcpy diff --git a/arch/mn10300/lib/memmove.S b/arch/mn10300/lib/memmove.S deleted file mode 100644 index 20b07b62b77c..000000000000 --- a/arch/mn10300/lib/memmove.S +++ /dev/null @@ -1,160 +0,0 @@ -/* MN10300 Optimised simple memory to memory copy, with support for overlapping - * regions - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - - .section .text - .balign L1_CACHE_BYTES - -############################################################################### -# -# void *memmove(void *dst, const void *src, size_t n) -# -############################################################################### - .globl memmove - .type memmove,@function -memmove: - # fall back to memcpy if dst < src to work bottom up - cmp d1,d0 - bcs memmove_memcpy - - # work top down - movm [d2,d3],(sp) - mov d0,(12,sp) - mov d1,(16,sp) - mov (20,sp),d2 # count - add d0,d2,a0 # dst end - add d1,d2,a1 # src end - mov d0,e3 # the return value - - cmp +0,d2 - beq memmove_done # return if zero-length copy - - # see if the three parameters are all four-byte aligned - or d0,d1,d3 - or d2,d3 - and +3,d3 - bne memmove_1 # jump if not - - # we want to transfer as much as we can in chunks of 32 bytes - add -4,a1 - cmp +31,d2 - bls memmove_4_remainder # 4-byte aligned remainder - - add -32,d2 - mov +32,d3 - -memmove_4_loop: - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) - mov (a1),d1 - sub_sub +4,a1,+4,a0 - mov d1,(a0) - - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) - mov (a1),d1 - sub_sub +4,a1,+4,a0 - mov d1,(a0) - - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) - mov (a1),d1 - sub_sub +4,a1,+4,a0 - mov d1,(a0) - - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) - mov (a1),d1 - sub_sub +4,a1,+4,a0 - mov d1,(a0) - - sub d3,d2 - bcc memmove_4_loop - - add d3,d2 - beq memmove_4_no_remainder - -memmove_4_remainder: - # cut 4-7 words down to 0-3 - cmp +16,d2 - bcs memmove_4_three_or_fewer_words - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) - mov (a1),d1 - sub_sub +4,a1,+4,a0 - mov d1,(a0) - mov (a1),e0 - sub_sub +4,a1,+4,a0 - mov e0,(a0) - mov (a1),e1 - sub_sub +4,a1,+4,a0 - mov e1,(a0) - add -16,d2 - beq memmove_4_no_remainder - - # copy the remaining 1, 2 or 3 words -memmove_4_three_or_fewer_words: - cmp +8,d2 - bcs memmove_4_one_word - beq memmove_4_two_words - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) -memmove_4_two_words: - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) -memmove_4_one_word: - mov (a1),d0 - sub_sub +4,a1,+4,a0 - mov d0,(a0) - -memmove_4_no_remainder: - # check we copied the correct amount - # TODO: REMOVE CHECK - sub e3,a0,d2 - beq memmove_done - break - break - break - -memmove_done: - mov e3,a0 - ret [d2,d3],8 - - # handle misaligned copying -memmove_1: - add -1,a1 - add -1,d2 - mov +1,d3 - setlb # setlb requires the next insns - # to occupy exactly 4 bytes - - sub d3,d2 - movbu (a1),d0 - sub_sub d3,a1,d3,a0 - movbu d0,(a0) - lcc - - mov e3,a0 - ret [d2,d3],8 - -memmove_memcpy: - jmp memcpy - -memmove_end: - .size memmove, memmove_end-memmove diff --git a/arch/mn10300/lib/memset.S b/arch/mn10300/lib/memset.S deleted file mode 100644 index bc02e39629b7..000000000000 --- a/arch/mn10300/lib/memset.S +++ /dev/null @@ -1,121 +0,0 @@ -/* Optimised simple memory fill - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - - .section .text - .balign L1_CACHE_BYTES - -############################################################################### -# -# void *memset(void *dst, int c, size_t n) -# -############################################################################### - .globl memset - .type memset,@function -memset: - movm [d2,d3],(sp) - mov d0,(12,sp) - mov d1,(16,sp) - mov (20,sp),d2 # count - mov d0,a0 # dst - mov d0,e3 # the return value - - cmp +0,d2 - beq memset_done # return if zero-length fill - - # see if the region parameters are four-byte aligned - or d0,d2,d3 - and +3,d3 - bne memset_1 # jump if not - - extbu d1 - mov_asl d1,d3,8,d1 - or_asl d1,d3,8,d1 - or_asl d1,d3,8,d1 - or d3,d1 - - # we want to transfer as much as we can in chunks of 32 bytes - cmp +31,d2 - bls memset_4_remainder # 4-byte aligned remainder - - add -32,d2 - mov +32,d3 - -memset_4_loop: - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - - sub d3,d2 - bcc memset_4_loop - - add d3,d2 - beq memset_4_no_remainder - -memset_4_remainder: - # cut 4-7 words down to 0-3 - cmp +16,d2 - bcs memset_4_three_or_fewer_words - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - mov d1,(a0+) - add -16,d2 - beq memset_4_no_remainder - - # copy the remaining 1, 2 or 3 words -memset_4_three_or_fewer_words: - cmp +8,d2 - bcs memset_4_one_word - beq memset_4_two_words - mov d1,(a0+) -memset_4_two_words: - mov d1,(a0+) -memset_4_one_word: - mov d1,(a0+) - -memset_4_no_remainder: - # check we set the correct amount - # TODO: REMOVE CHECK - sub e3,a0,d2 - mov (20,sp),d1 - cmp d2,d1 - beq memset_done - break - break - break - -memset_done: - mov e3,a0 - ret [d2,d3],8 - - # handle misaligned copying -memset_1: - add -1,d2 - mov +1,d3 - setlb # setlb requires the next insns - # to occupy exactly 4 bytes - - sub d3,d2 - movbu d1,(a0) - inc a0 - lcc - - mov e3,a0 - ret [d2,d3],8 - -memset_end: - .size memset, memset_end-memset diff --git a/arch/mn10300/lib/negdi2.c b/arch/mn10300/lib/negdi2.c deleted file mode 100644 index eae4ecdd5f69..000000000000 --- a/arch/mn10300/lib/negdi2.c +++ /dev/null @@ -1,57 +0,0 @@ -/* More subroutines needed by GCC output code on some machines. */ -/* Compile this one with gcc. */ -/* Copyright (C) 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001 Free Software Foundation, Inc. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public Licence as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -In addition to the permissions in the GNU General Public Licence, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file into combinations with other programs, -and to distribute those combinations without any restriction coming -from the use of this file. (The General Public Licence restrictions -do apply in other respects; for example, they cover modification of -the file, and distribution when not linked into a combine -executable.) - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public Licence for more details. - -You should have received a copy of the GNU General Public Licence -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* It is incorrect to include config.h here, because this file is being - compiled for the target, and hence definitions concerning only the host - do not apply. */ - -#include - -union DWunion { - s64 ll; - struct { - s32 low; - s32 high; - } s; -}; - -s64 __negdi2(s64 u) -{ - union DWunion w; - union DWunion uu; - - uu.ll = u; - - w.s.low = -uu.s.low; - w.s.high = -uu.s.high - ((u32) w.s.low > 0); - - return w.ll; -} diff --git a/arch/mn10300/lib/usercopy.c b/arch/mn10300/lib/usercopy.c deleted file mode 100644 index 39626912de98..000000000000 --- a/arch/mn10300/lib/usercopy.c +++ /dev/null @@ -1,142 +0,0 @@ -/* MN10300 Userspace accessor functions - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - -/* - * Copy a null terminated string from userspace. - */ -#define __do_strncpy_from_user(dst, src, count, res) \ -do { \ - int w; \ - asm volatile( \ - " mov %1,%0\n" \ - " cmp 0,%1\n" \ - " beq 2f\n" \ - "0:\n" \ - " movbu (%5),%2\n" \ - "1:\n" \ - " movbu %2,(%6)\n" \ - " inc %5\n" \ - " inc %6\n" \ - " cmp 0,%2\n" \ - " beq 2f\n" \ - " add -1,%1\n" \ - " bne 0b\n" \ - "2:\n" \ - " sub %1,%0\n" \ - "3:\n" \ - " .section .fixup,\"ax\"\n" \ - "4:\n" \ - " mov %3,%0\n" \ - " jmp 3b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .balign 4\n" \ - " .long 0b,4b\n" \ - " .long 1b,4b\n" \ - " .previous" \ - :"=&r"(res), "=r"(count), "=&r"(w) \ - :"i"(-EFAULT), "1"(count), "a"(src), "a"(dst) \ - : "memory", "cc"); \ -} while (0) - -long -strncpy_from_user(char *dst, const char *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - __do_strncpy_from_user(dst, src, count, res); - return res; -} - - -/* - * Clear a userspace memory - */ -#define __do_clear_user(addr, size) \ -do { \ - int w; \ - asm volatile( \ - " cmp 0,%0\n" \ - " beq 1f\n" \ - " clr %1\n" \ - "0: movbu %1,(%3,%2)\n" \ - " inc %3\n" \ - " cmp %0,%3\n" \ - " bne 0b\n" \ - "1:\n" \ - " sub %3,%0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: jmp 2b\n" \ - ".previous\n" \ - ".section __ex_table,\"a\"\n" \ - " .balign 4\n" \ - " .long 0b,3b\n" \ - ".previous\n" \ - : "+r"(size), "=&r"(w) \ - : "a"(addr), "d"(0) \ - : "memory", "cc"); \ -} while (0) - -unsigned long -__clear_user(void *to, unsigned long n) -{ - __do_clear_user(to, n); - return n; -} - -unsigned long -clear_user(void *to, unsigned long n) -{ - if (access_ok(VERIFY_WRITE, to, n)) - __do_clear_user(to, n); - return n; -} - -/* - * Return the size of a string (including the ending 0) - * - * Return 0 on exception, a value greater than N if too long - */ -long strnlen_user(const char *s, long n) -{ - unsigned long res, w; - - if (!__addr_ok(s)) - return 0; - - if (n < 0 || n + (u_long) s > current_thread_info()->addr_limit.seg) - n = current_thread_info()->addr_limit.seg - (u_long)s; - - asm volatile( - "0: cmp %4,%0\n" - " beq 2f\n" - "1: movbu (%0,%3),%1\n" - " inc %0\n" - " cmp 0,%1\n" - " beq 3f\n" - " bra 0b\n" - "2: clr %0\n" - "3:\n" - ".section .fixup,\"ax\"\n" - "4: jmp 2b\n" - ".previous\n" - ".section __ex_table,\"a\"\n" - " .balign 4\n" - " .long 1b,4b\n" - ".previous\n" - :"=d"(res), "=&r"(w) - :"0"(0), "a"(s), "r"(n) - : "memory", "cc"); - return res; -} diff --git a/arch/mn10300/mm/Kconfig.cache b/arch/mn10300/mm/Kconfig.cache deleted file mode 100644 index 8cc5d9ec3b6c..000000000000 --- a/arch/mn10300/mm/Kconfig.cache +++ /dev/null @@ -1,148 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# MN10300 CPU cache options -# - -choice - prompt "CPU Caching mode" - default MN10300_CACHE_WBACK - help - This option determines the caching mode for the kernel. - - Write-Back caching mode involves the all reads and writes causing - the affected cacheline to be read into the cache first before being - operated upon. Memory is not then updated by a write until the cache - is filled and a cacheline needs to be displaced from the cache to - make room. Only at that point is it written back. - - Write-Through caching only fetches cachelines from memory on a - read. Writes always get written directly to memory. If the affected - cacheline is also in cache, it will be updated too. - - The final option is to turn of caching entirely. - -config MN10300_CACHE_WBACK - bool "Write-Back" - help - The dcache operates in delayed write-back mode. It must be manually - flushed if writes are made that subsequently need to be executed or - to be DMA'd by a device. - -config MN10300_CACHE_WTHRU - bool "Write-Through" - help - The dcache operates in immediate write-through mode. Writes are - committed to RAM immediately in addition to being stored in the - cache. This means that the written data is immediately available for - execution or DMA. - - This is not available for use with an SMP kernel if cache flushing - and invalidation by automatic purge register is not selected. - -config MN10300_CACHE_DISABLED - bool "Disabled" - help - The icache and dcache are disabled. - -endchoice - -config MN10300_CACHE_ENABLED - def_bool y if !MN10300_CACHE_DISABLED - - -choice - prompt "CPU cache flush/invalidate method" - default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2 - default MN10300_CACHE_MANAGE_BY_REG if AM34_2 - depends on MN10300_CACHE_ENABLED - help - This determines the method by which CPU cache flushing and - invalidation is performed. - -config MN10300_CACHE_MANAGE_BY_TAG - bool "Use the cache tag registers directly" - depends on !(SMP && MN10300_CACHE_WTHRU) - -config MN10300_CACHE_MANAGE_BY_REG - bool "Flush areas by way of automatic purge registers (AM34 only)" - depends on AM34_2 - -endchoice - -config MN10300_CACHE_INV_BY_TAG - def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED - -config MN10300_CACHE_INV_BY_REG - def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED - -config MN10300_CACHE_FLUSH_BY_TAG - def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK - -config MN10300_CACHE_FLUSH_BY_REG - def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK - - -config MN10300_HAS_CACHE_SNOOP - def_bool n - -config MN10300_CACHE_SNOOP - bool "Use CPU Cache Snooping" - depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP - default y - -config MN10300_CACHE_FLUSH_ICACHE - def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP - help - Set if we need the dcache flushing before the icache is invalidated. - -config MN10300_CACHE_INV_ICACHE - def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP - help - Set if we need the icache to be invalidated, even if the dcache is in - write-through mode and doesn't need flushing. - -# -# The kernel debugger gets its own separate cache flushing functions -# -config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG - def_bool y if KERNEL_DEBUGGER && \ - MN10300_CACHE_WBACK && \ - !MN10300_CACHE_SNOOP && \ - MN10300_CACHE_MANAGE_BY_TAG - help - Set if the debugger needs to flush the dcache and invalidate the - icache using the cache tag registers to make breakpoints work. - -config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG - def_bool y if KERNEL_DEBUGGER && \ - MN10300_CACHE_WBACK && \ - !MN10300_CACHE_SNOOP && \ - MN10300_CACHE_MANAGE_BY_REG - help - Set if the debugger needs to flush the dcache and invalidate the - icache using automatic purge registers to make breakpoints work. - -config MN10300_DEBUGGER_CACHE_INV_BY_TAG - def_bool y if KERNEL_DEBUGGER && \ - MN10300_CACHE_WTHRU && \ - !MN10300_CACHE_SNOOP && \ - MN10300_CACHE_MANAGE_BY_TAG - help - Set if the debugger needs to invalidate the icache using the cache - tag registers to make breakpoints work. - -config MN10300_DEBUGGER_CACHE_INV_BY_REG - def_bool y if KERNEL_DEBUGGER && \ - MN10300_CACHE_WTHRU && \ - !MN10300_CACHE_SNOOP && \ - MN10300_CACHE_MANAGE_BY_REG - help - Set if the debugger needs to invalidate the icache using automatic - purge registers to make breakpoints work. - -config MN10300_DEBUGGER_CACHE_NO_FLUSH - def_bool y if KERNEL_DEBUGGER && \ - (MN10300_CACHE_DISABLED || MN10300_CACHE_SNOOP) - help - Set if the debugger does not need to flush the dcache and/or - invalidate the icache to make breakpoints work. diff --git a/arch/mn10300/mm/Makefile b/arch/mn10300/mm/Makefile deleted file mode 100644 index 048ba6f67f9a..000000000000 --- a/arch/mn10300/mm/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the MN10300-specific memory management code -# - -cache-smp-wback-$(CONFIG_MN10300_CACHE_WBACK) := cache-smp-flush.o - -cacheflush-y := cache.o -cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y) -cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o -cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o -cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o -cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o -cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o -cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o - -cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG) += \ - cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o -cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG) += \ - cache-dbg-flush-by-reg.o -cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG) += \ - cache-dbg-inv-by-tag.o cache-dbg-inv.o -cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_REG) += \ - cache-dbg-inv-by-reg.o cache-dbg-inv.o - -cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o - -obj-y := \ - init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \ - misalignment.o dma-alloc.o $(cacheflush-y) - -obj-$(CONFIG_SMP) += tlb-smp.o diff --git a/arch/mn10300/mm/cache-dbg-flush-by-reg.S b/arch/mn10300/mm/cache-dbg-flush-by-reg.S deleted file mode 100644 index a775ea5d7cee..000000000000 --- a/arch/mn10300/mm/cache-dbg-flush-by-reg.S +++ /dev/null @@ -1,160 +0,0 @@ -/* MN10300 CPU cache invalidation routines, using automatic purge registers - * - * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include "cache.inc" - - .am33_2 - -############################################################################### -# -# void debugger_local_cache_flushinv(void) -# Flush the entire data cache back to RAM and invalidate the icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv - .type debugger_local_cache_flushinv,@function -debugger_local_cache_flushinv: - # - # firstly flush the dcache - # - movhu (CHCTR),d0 - btst CHCTR_DCEN|CHCTR_ICEN,d0 - beq debugger_local_cache_flushinv_end - - mov DCPGCR,a0 - - mov epsw,d1 - and ~EPSW_IE,epsw - or EPSW_NMID,epsw - nop - - btst CHCTR_DCEN,d0 - beq debugger_local_cache_flushinv_no_dcache - - # wait for busy bit of area purge - setlb - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - - # set mask - clr d0 - mov d0,(DCPGMR) - - # area purge - # - # DCPGCR = DCPGCR_DCP - # - mov DCPGCR_DCP,d0 - mov d0,(a0) - - # wait for busy bit of area purge - setlb - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - -debugger_local_cache_flushinv_no_dcache: - # - # secondly, invalidate the icache if it is enabled - # - mov CHCTR,a0 - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq debugger_local_cache_flushinv_done - - invalidate_icache 0 - -debugger_local_cache_flushinv_done: - mov d1,epsw - -debugger_local_cache_flushinv_end: - ret [],0 - .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv - -############################################################################### -# -# void debugger_local_cache_flushinv_one(u8 *addr) -# -# Invalidate one particular cacheline if it's in the icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv_one - .type debugger_local_cache_flushinv_one,@function -debugger_local_cache_flushinv_one: - movhu (CHCTR),d1 - btst CHCTR_DCEN|CHCTR_ICEN,d1 - beq debugger_local_cache_flushinv_one_end - btst CHCTR_DCEN,d1 - beq debugger_local_cache_flushinv_one_no_dcache - - # round cacheline addr down - and L1_CACHE_TAG_MASK,d0 - mov d0,a1 - mov d0,d1 - - # determine the dcache purge control reg address - mov DCACHE_PURGE(0,0),a0 - and L1_CACHE_TAG_ENTRY,d0 - add d0,a0 - - # retain valid entries in the cache - or L1_CACHE_TAG_VALID,d1 - - # conditionally purge this line in all ways - mov d1,(L1_CACHE_WAYDISP*0,a0) - -debugger_local_cache_flushinv_one_no_dcache: - # - # now try to flush the icache - # - mov CHCTR,a0 - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq debugger_local_cache_flushinv_one_end - - LOCAL_CLI_SAVE(d1) - - mov ICIVCR,a0 - - # wait for the invalidator to quiesce - setlb - mov (a0),d0 - btst ICIVCR_ICIVBSY,d0 - lne - - # set the mask - mov L1_CACHE_TAG_MASK,d0 - mov d0,(ICIVMR) - - # invalidate the cache line at the given address - or ICIVCR_ICI,a1 - mov a1,(a0) - - # wait for the invalidator to quiesce again - setlb - mov (a0),d0 - btst ICIVCR_ICIVBSY,d0 - lne - - LOCAL_IRQ_RESTORE(d1) - -debugger_local_cache_flushinv_one_end: - ret [],0 - .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one diff --git a/arch/mn10300/mm/cache-dbg-flush-by-tag.S b/arch/mn10300/mm/cache-dbg-flush-by-tag.S deleted file mode 100644 index bf56930e6e70..000000000000 --- a/arch/mn10300/mm/cache-dbg-flush-by-tag.S +++ /dev/null @@ -1,114 +0,0 @@ -/* MN10300 CPU cache invalidation routines, using direct tag flushing - * - * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include "cache.inc" - - .am33_2 - -############################################################################### -# -# void debugger_local_cache_flushinv(void) -# -# Flush the entire data cache back to RAM and invalidate the icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv - .type debugger_local_cache_flushinv,@function -debugger_local_cache_flushinv: - # - # firstly flush the dcache - # - movhu (CHCTR),d0 - btst CHCTR_DCEN|CHCTR_ICEN,d0 - beq debugger_local_cache_flushinv_end - - btst CHCTR_DCEN,d0 - beq debugger_local_cache_flushinv_no_dcache - - # read the addresses tagged in the cache's tag RAM and attempt to flush - # those addresses specifically - # - we rely on the hardware to filter out invalid tag entry addresses - mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address - mov DCACHE_PURGE(0,0),a1 # dcache purge request address - mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,e0 # total number of entries - -mn10300_local_dcache_flush_loop: - mov (a0),d0 - and L1_CACHE_TAG_MASK,d0 - or L1_CACHE_TAG_VALID,d0 # retain valid entries in the - # cache - mov d0,(a1) # conditional purge - - add L1_CACHE_BYTES,a0 - add L1_CACHE_BYTES,a1 - add -1,e0 - bne mn10300_local_dcache_flush_loop - -debugger_local_cache_flushinv_no_dcache: - # - # secondly, invalidate the icache if it is enabled - # - mov CHCTR,a0 - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq debugger_local_cache_flushinv_end - - invalidate_icache 1 - -debugger_local_cache_flushinv_end: - ret [],0 - .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv - -############################################################################### -# -# void debugger_local_cache_flushinv_one(u8 *addr) -# -# Invalidate one particular cacheline if it's in the icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv_one - .type debugger_local_cache_flushinv_one,@function -debugger_local_cache_flushinv_one: - movhu (CHCTR),d1 - btst CHCTR_DCEN|CHCTR_ICEN,d1 - beq debugger_local_cache_flushinv_one_end - btst CHCTR_DCEN,d1 - beq debugger_local_cache_flushinv_one_icache - - # round cacheline addr down - and L1_CACHE_TAG_MASK,d0 - mov d0,a1 - - # determine the dcache purge control reg address - mov DCACHE_PURGE(0,0),a0 - and L1_CACHE_TAG_ENTRY,d0 - add d0,a0 - - # retain valid entries in the cache - or L1_CACHE_TAG_VALID,a1 - - # conditionally purge this line in all ways - mov a1,(L1_CACHE_WAYDISP*0,a0) - - # now go and do the icache - bra debugger_local_cache_flushinv_one_icache - -debugger_local_cache_flushinv_one_end: - ret [],0 - .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one diff --git a/arch/mn10300/mm/cache-dbg-inv-by-reg.S b/arch/mn10300/mm/cache-dbg-inv-by-reg.S deleted file mode 100644 index c4e6252941b1..000000000000 --- a/arch/mn10300/mm/cache-dbg-inv-by-reg.S +++ /dev/null @@ -1,69 +0,0 @@ -/* MN10300 CPU cache invalidation routines, using automatic purge registers - * - * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include "cache.inc" - - .am33_2 - - .globl debugger_local_cache_flushinv_one - -############################################################################### -# -# void debugger_local_cache_flushinv_one(u8 *addr) -# -# Invalidate one particular cacheline if it's in the icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv_one - .type debugger_local_cache_flushinv_one,@function -debugger_local_cache_flushinv_one: - mov d0,a1 - - mov CHCTR,a0 - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq mn10300_local_icache_inv_range_reg_end - - LOCAL_CLI_SAVE(d1) - - mov ICIVCR,a0 - - # wait for the invalidator to quiesce - setlb - mov (a0),d0 - btst ICIVCR_ICIVBSY,d0 - lne - - # set the mask - mov ~L1_CACHE_TAG_MASK,d0 - mov d0,(ICIVMR) - - # invalidate the cache line at the given address - and ~L1_CACHE_TAG_MASK,a1 - or ICIVCR_ICI,a1 - mov a1,(a0) - - # wait for the invalidator to quiesce again - setlb - mov (a0),d0 - btst ICIVCR_ICIVBSY,d0 - lne - - LOCAL_IRQ_RESTORE(d1) - -mn10300_local_icache_inv_range_reg_end: - ret [],0 - .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one diff --git a/arch/mn10300/mm/cache-dbg-inv-by-tag.S b/arch/mn10300/mm/cache-dbg-inv-by-tag.S deleted file mode 100644 index d8ec821e5f88..000000000000 --- a/arch/mn10300/mm/cache-dbg-inv-by-tag.S +++ /dev/null @@ -1,120 +0,0 @@ -/* MN10300 CPU cache invalidation routines, using direct tag flushing - * - * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include "cache.inc" - - .am33_2 - - .globl debugger_local_cache_flushinv_one_icache - -############################################################################### -# -# void debugger_local_cache_flushinv_one(u8 *addr) -# -# Invalidate one particular cacheline if it's in the icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv_one_icache - .type debugger_local_cache_flushinv_one_icache,@function -debugger_local_cache_flushinv_one_icache: - movm [d3,a2],(sp) - - mov CHCTR,a2 - movhu (a2),d0 - btst CHCTR_ICEN,d0 - beq debugger_local_cache_flushinv_one_icache_end - - mov d0,a1 - and L1_CACHE_TAG_MASK,a1 - - # read the tags from the tag RAM, and if they indicate a matching valid - # cache line then we invalidate that line - mov ICACHE_TAG(0,0),a0 - mov a1,d0 - and L1_CACHE_TAG_ENTRY,d0 - add d0,a0 # starting icache tag RAM - # access address - - and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base - or L1_CACHE_TAG_VALID,a1 - mov L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_VALID,d1 - - LOCAL_CLI_SAVE(d3) - - # disable the icache - movhu (a2),d0 - and ~CHCTR_ICEN,d0 - movhu d0,(a2) - - # and wait for it to calm down - setlb - movhu (a2),d0 - btst CHCTR_ICBUSY,d0 - lne - - # check all the way tags for this cache entry - mov (a0),d0 # read the tag in the way 0 slot - xor a1,d0 - and d1,d0 - beq debugger_local_icache_kill # jump if matched - - add L1_CACHE_WAYDISP,a0 - mov (a0),d0 # read the tag in the way 1 slot - xor a1,d0 - and d1,d0 - beq debugger_local_icache_kill # jump if matched - - add L1_CACHE_WAYDISP,a0 - mov (a0),d0 # read the tag in the way 2 slot - xor a1,d0 - and d1,d0 - beq debugger_local_icache_kill # jump if matched - - add L1_CACHE_WAYDISP,a0 - mov (a0),d0 # read the tag in the way 3 slot - xor a1,d0 - and d1,d0 - bne debugger_local_icache_finish # jump if not matched - -debugger_local_icache_kill: - mov d0,(a0) # kill the tag (D0 is 0 at this point) - -debugger_local_icache_finish: - # wait for the cache to finish what it's doing - setlb - movhu (a2),d0 - btst CHCTR_ICBUSY,d0 - lne - - # and reenable it - or CHCTR_ICEN,d0 - movhu d0,(a2) - movhu (a2),d0 - - # re-enable interrupts - LOCAL_IRQ_RESTORE(d3) - -debugger_local_cache_flushinv_one_icache_end: - ret [d3,a2],8 - .size debugger_local_cache_flushinv_one_icache,.-debugger_local_cache_flushinv_one_icache - -#ifdef CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG - .globl debugger_local_cache_flushinv_one - .type debugger_local_cache_flushinv_one,@function -debugger_local_cache_flushinv_one = debugger_local_cache_flushinv_one_icache -#endif diff --git a/arch/mn10300/mm/cache-dbg-inv.S b/arch/mn10300/mm/cache-dbg-inv.S deleted file mode 100644 index eba2d6dca066..000000000000 --- a/arch/mn10300/mm/cache-dbg-inv.S +++ /dev/null @@ -1,47 +0,0 @@ -/* MN10300 CPU cache invalidation routines - * - * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include "cache.inc" - - .am33_2 - - .globl debugger_local_cache_flushinv - -############################################################################### -# -# void debugger_local_cache_flushinv(void) -# -# Invalidate the entire icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv - .type debugger_local_cache_flushinv,@function -debugger_local_cache_flushinv: - # - # we only need to invalidate the icache in this cache mode - # - mov CHCTR,a0 - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq debugger_local_cache_flushinv_end - - invalidate_icache 1 - -debugger_local_cache_flushinv_end: - ret [],0 - .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv diff --git a/arch/mn10300/mm/cache-disabled.c b/arch/mn10300/mm/cache-disabled.c deleted file mode 100644 index f669ea42aba6..000000000000 --- a/arch/mn10300/mm/cache-disabled.c +++ /dev/null @@ -1,21 +0,0 @@ -/* Handle the cache being disabled - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include - -/* - * allow userspace to flush the instruction cache - */ -asmlinkage long sys_cacheflush(unsigned long start, unsigned long end) -{ - if (end < start) - return -EINVAL; - return 0; -} diff --git a/arch/mn10300/mm/cache-flush-by-reg.S b/arch/mn10300/mm/cache-flush-by-reg.S deleted file mode 100644 index 1dcae0211671..000000000000 --- a/arch/mn10300/mm/cache-flush-by-reg.S +++ /dev/null @@ -1,308 +0,0 @@ -/* MN10300 CPU core caching routines, using indirect regs on cache controller - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include - - .am33_2 - -#ifndef CONFIG_SMP - .globl mn10300_dcache_flush - .globl mn10300_dcache_flush_page - .globl mn10300_dcache_flush_range - .globl mn10300_dcache_flush_range2 - .globl mn10300_dcache_flush_inv - .globl mn10300_dcache_flush_inv_page - .globl mn10300_dcache_flush_inv_range - .globl mn10300_dcache_flush_inv_range2 - -mn10300_dcache_flush = mn10300_local_dcache_flush -mn10300_dcache_flush_page = mn10300_local_dcache_flush_page -mn10300_dcache_flush_range = mn10300_local_dcache_flush_range -mn10300_dcache_flush_range2 = mn10300_local_dcache_flush_range2 -mn10300_dcache_flush_inv = mn10300_local_dcache_flush_inv -mn10300_dcache_flush_inv_page = mn10300_local_dcache_flush_inv_page -mn10300_dcache_flush_inv_range = mn10300_local_dcache_flush_inv_range -mn10300_dcache_flush_inv_range2 = mn10300_local_dcache_flush_inv_range2 - -#endif /* !CONFIG_SMP */ - -############################################################################### -# -# void mn10300_local_dcache_flush(void) -# Flush the entire data cache back to RAM -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush - .type mn10300_local_dcache_flush,@function -mn10300_local_dcache_flush: - movhu (CHCTR),d0 - btst CHCTR_DCEN,d0 - beq mn10300_local_dcache_flush_end - - mov DCPGCR,a0 - - LOCAL_CLI_SAVE(d1) - - # wait for busy bit of area purge - setlb - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - - # set mask - clr d0 - mov d0,(DCPGMR) - - # area purge - # - # DCPGCR = DCPGCR_DCP - # - mov DCPGCR_DCP,d0 - mov d0,(a0) - - # wait for busy bit of area purge - setlb - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - - LOCAL_IRQ_RESTORE(d1) - -mn10300_local_dcache_flush_end: - ret [],0 - .size mn10300_local_dcache_flush,.-mn10300_local_dcache_flush - -############################################################################### -# -# void mn10300_local_dcache_flush_page(unsigned long start) -# void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end) -# void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size) -# Flush a range of addresses on a page in the dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush_page - .globl mn10300_local_dcache_flush_range - .globl mn10300_local_dcache_flush_range2 - .type mn10300_local_dcache_flush_page,@function - .type mn10300_local_dcache_flush_range,@function - .type mn10300_local_dcache_flush_range2,@function -mn10300_local_dcache_flush_page: - and ~(PAGE_SIZE-1),d0 - mov PAGE_SIZE,d1 -mn10300_local_dcache_flush_range2: - add d0,d1 -mn10300_local_dcache_flush_range: - movm [d2,d3,a2],(sp) - - movhu (CHCTR),d2 - btst CHCTR_DCEN,d2 - beq mn10300_local_dcache_flush_range_end - - # calculate alignsize - # - # alignsize = L1_CACHE_BYTES; - # for (i = (end - start - 1) / L1_CACHE_BYTES ; i > 0; i >>= 1) - # alignsize <<= 1; - # d2 = alignsize; - # - mov L1_CACHE_BYTES,d2 - sub d0,d1,d3 - add -1,d3 - lsr L1_CACHE_SHIFT,d3 - beq 2f -1: - add d2,d2 - lsr 1,d3 - bne 1b -2: - mov d1,a1 # a1 = end - - LOCAL_CLI_SAVE(d3) - mov DCPGCR,a0 - - # wait for busy bit of area purge - setlb - mov (a0),d1 - btst DCPGCR_DCPGBSY,d1 - lne - - # determine the mask - mov d2,d1 - add -1,d1 - not d1 # d1 = mask = ~(alignsize-1) - mov d1,(DCPGMR) - - and d1,d0,a2 # a2 = mask & start - -dcpgloop: - # area purge - mov a2,d0 - or DCPGCR_DCP,d0 - mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCP - - # wait for busy bit of area purge - setlb - mov (a0),d1 - btst DCPGCR_DCPGBSY,d1 - lne - - # check purge of end address - add d2,a2 # a2 += alignsize - cmp a1,a2 # if (a2 < end) goto dcpgloop - bns dcpgloop - - LOCAL_IRQ_RESTORE(d3) - -mn10300_local_dcache_flush_range_end: - ret [d2,d3,a2],12 - - .size mn10300_local_dcache_flush_page,.-mn10300_local_dcache_flush_page - .size mn10300_local_dcache_flush_range,.-mn10300_local_dcache_flush_range - .size mn10300_local_dcache_flush_range2,.-mn10300_local_dcache_flush_range2 - -############################################################################### -# -# void mn10300_local_dcache_flush_inv(void) -# Flush the entire data cache and invalidate all entries -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush_inv - .type mn10300_local_dcache_flush_inv,@function -mn10300_local_dcache_flush_inv: - movhu (CHCTR),d0 - btst CHCTR_DCEN,d0 - beq mn10300_local_dcache_flush_inv_end - - mov DCPGCR,a0 - - LOCAL_CLI_SAVE(d1) - - # wait for busy bit of area purge & invalidate - setlb - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - - # set the mask to cover everything - clr d0 - mov d0,(DCPGMR) - - # area purge & invalidate - mov DCPGCR_DCP|DCPGCR_DCI,d0 - mov d0,(a0) - - # wait for busy bit of area purge & invalidate - setlb - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - - LOCAL_IRQ_RESTORE(d1) - -mn10300_local_dcache_flush_inv_end: - ret [],0 - .size mn10300_local_dcache_flush_inv,.-mn10300_local_dcache_flush_inv - -############################################################################### -# -# void mn10300_local_dcache_flush_inv_page(unsigned long start) -# void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end) -# void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size) -# Flush and invalidate a range of addresses on a page in the dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush_inv_page - .globl mn10300_local_dcache_flush_inv_range - .globl mn10300_local_dcache_flush_inv_range2 - .type mn10300_local_dcache_flush_inv_page,@function - .type mn10300_local_dcache_flush_inv_range,@function - .type mn10300_local_dcache_flush_inv_range2,@function -mn10300_local_dcache_flush_inv_page: - and ~(PAGE_SIZE-1),d0 - mov PAGE_SIZE,d1 -mn10300_local_dcache_flush_inv_range2: - add d0,d1 -mn10300_local_dcache_flush_inv_range: - movm [d2,d3,a2],(sp) - - movhu (CHCTR),d2 - btst CHCTR_DCEN,d2 - beq mn10300_local_dcache_flush_inv_range_end - - # calculate alignsize - # - # alignsize = L1_CACHE_BYTES; - # for (i = (end - start - 1) / L1_CACHE_BYTES; i > 0; i >>= 1) - # alignsize <<= 1; - # d2 = alignsize - # - mov L1_CACHE_BYTES,d2 - sub d0,d1,d3 - add -1,d3 - lsr L1_CACHE_SHIFT,d3 - beq 2f -1: - add d2,d2 - lsr 1,d3 - bne 1b -2: - mov d1,a1 # a1 = end - - LOCAL_CLI_SAVE(d3) - mov DCPGCR,a0 - - # wait for busy bit of area purge & invalidate - setlb - mov (a0),d1 - btst DCPGCR_DCPGBSY,d1 - lne - - # set the mask - mov d2,d1 - add -1,d1 - not d1 # d1 = mask = ~(alignsize-1) - mov d1,(DCPGMR) - - and d1,d0,a2 # a2 = mask & start - -dcpgivloop: - # area purge & invalidate - mov a2,d0 - or DCPGCR_DCP|DCPGCR_DCI,d0 - mov d0,(a0) # DCPGCR = (mask & start)|DCPGCR_DCP|DCPGCR_DCI - - # wait for busy bit of area purge & invalidate - setlb - mov (a0),d1 - btst DCPGCR_DCPGBSY,d1 - lne - - # check purge & invalidate of end address - add d2,a2 # a2 += alignsize - cmp a1,a2 # if (a2 < end) goto dcpgivloop - bns dcpgivloop - - LOCAL_IRQ_RESTORE(d3) - -mn10300_local_dcache_flush_inv_range_end: - ret [d2,d3,a2],12 - .size mn10300_local_dcache_flush_inv_page,.-mn10300_local_dcache_flush_inv_page - .size mn10300_local_dcache_flush_inv_range,.-mn10300_local_dcache_flush_inv_range - .size mn10300_local_dcache_flush_inv_range2,.-mn10300_local_dcache_flush_inv_range2 diff --git a/arch/mn10300/mm/cache-flush-by-tag.S b/arch/mn10300/mm/cache-flush-by-tag.S deleted file mode 100644 index 1ddc06849242..000000000000 --- a/arch/mn10300/mm/cache-flush-by-tag.S +++ /dev/null @@ -1,250 +0,0 @@ -/* MN10300 CPU core caching routines, using direct tag flushing - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include - - .am33_2 - -#ifndef CONFIG_SMP - .globl mn10300_dcache_flush - .globl mn10300_dcache_flush_page - .globl mn10300_dcache_flush_range - .globl mn10300_dcache_flush_range2 - .globl mn10300_dcache_flush_inv - .globl mn10300_dcache_flush_inv_page - .globl mn10300_dcache_flush_inv_range - .globl mn10300_dcache_flush_inv_range2 - -mn10300_dcache_flush = mn10300_local_dcache_flush -mn10300_dcache_flush_page = mn10300_local_dcache_flush_page -mn10300_dcache_flush_range = mn10300_local_dcache_flush_range -mn10300_dcache_flush_range2 = mn10300_local_dcache_flush_range2 -mn10300_dcache_flush_inv = mn10300_local_dcache_flush_inv -mn10300_dcache_flush_inv_page = mn10300_local_dcache_flush_inv_page -mn10300_dcache_flush_inv_range = mn10300_local_dcache_flush_inv_range -mn10300_dcache_flush_inv_range2 = mn10300_local_dcache_flush_inv_range2 - -#endif /* !CONFIG_SMP */ - -############################################################################### -# -# void mn10300_local_dcache_flush(void) -# Flush the entire data cache back to RAM -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush - .type mn10300_local_dcache_flush,@function -mn10300_local_dcache_flush: - movhu (CHCTR),d0 - btst CHCTR_DCEN,d0 - beq mn10300_local_dcache_flush_end - - # read the addresses tagged in the cache's tag RAM and attempt to flush - # those addresses specifically - # - we rely on the hardware to filter out invalid tag entry addresses - mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address - mov DCACHE_PURGE(0,0),a1 # dcache purge request address - mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries - -mn10300_local_dcache_flush_loop: - mov (a0),d0 - and L1_CACHE_TAG_MASK,d0 - or L1_CACHE_TAG_VALID,d0 # retain valid entries in the - # cache - mov d0,(a1) # conditional purge - - add L1_CACHE_BYTES,a0 - add L1_CACHE_BYTES,a1 - add -1,d1 - bne mn10300_local_dcache_flush_loop - -mn10300_local_dcache_flush_end: - ret [],0 - .size mn10300_local_dcache_flush,.-mn10300_local_dcache_flush - -############################################################################### -# -# void mn10300_local_dcache_flush_page(unsigned long start) -# void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end) -# void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size) -# Flush a range of addresses on a page in the dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush_page - .globl mn10300_local_dcache_flush_range - .globl mn10300_local_dcache_flush_range2 - .type mn10300_local_dcache_flush_page,@function - .type mn10300_local_dcache_flush_range,@function - .type mn10300_local_dcache_flush_range2,@function -mn10300_local_dcache_flush_page: - and ~(PAGE_SIZE-1),d0 - mov PAGE_SIZE,d1 -mn10300_local_dcache_flush_range2: - add d0,d1 -mn10300_local_dcache_flush_range: - movm [d2],(sp) - - movhu (CHCTR),d2 - btst CHCTR_DCEN,d2 - beq mn10300_local_dcache_flush_range_end - - sub d0,d1,a0 - cmp MN10300_DCACHE_FLUSH_BORDER,a0 - ble 1f - - movm (sp),[d2] - bra mn10300_local_dcache_flush -1: - - # round start addr down - and L1_CACHE_TAG_MASK,d0 - mov d0,a1 - - add L1_CACHE_BYTES,d1 # round end addr up - and L1_CACHE_TAG_MASK,d1 - - # write a request to flush all instances of an address from the cache - mov DCACHE_PURGE(0,0),a0 - mov a1,d0 - and L1_CACHE_TAG_ENTRY,d0 - add d0,a0 # starting dcache purge control - # reg address - - sub a1,d1 - lsr L1_CACHE_SHIFT,d1 # total number of entries to - # examine - - or L1_CACHE_TAG_VALID,a1 # retain valid entries in the - # cache - -mn10300_local_dcache_flush_range_loop: - mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line - # all ways - - add L1_CACHE_BYTES,a0 - add L1_CACHE_BYTES,a1 - and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0 - add -1,d1 - bne mn10300_local_dcache_flush_range_loop - -mn10300_local_dcache_flush_range_end: - ret [d2],4 - - .size mn10300_local_dcache_flush_page,.-mn10300_local_dcache_flush_page - .size mn10300_local_dcache_flush_range,.-mn10300_local_dcache_flush_range - .size mn10300_local_dcache_flush_range2,.-mn10300_local_dcache_flush_range2 - -############################################################################### -# -# void mn10300_local_dcache_flush_inv(void) -# Flush the entire data cache and invalidate all entries -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush_inv - .type mn10300_local_dcache_flush_inv,@function -mn10300_local_dcache_flush_inv: - movhu (CHCTR),d0 - btst CHCTR_DCEN,d0 - beq mn10300_local_dcache_flush_inv_end - - mov L1_CACHE_NENTRIES,d1 - clr a1 - -mn10300_local_dcache_flush_inv_loop: - mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge - mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge - mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge - mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge - - add L1_CACHE_BYTES,a1 - add -1,d1 - bne mn10300_local_dcache_flush_inv_loop - -mn10300_local_dcache_flush_inv_end: - ret [],0 - .size mn10300_local_dcache_flush_inv,.-mn10300_local_dcache_flush_inv - -############################################################################### -# -# void mn10300_local_dcache_flush_inv_page(unsigned long start) -# void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end) -# void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size) -# Flush and invalidate a range of addresses on a page in the dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_flush_inv_page - .globl mn10300_local_dcache_flush_inv_range - .globl mn10300_local_dcache_flush_inv_range2 - .type mn10300_local_dcache_flush_inv_page,@function - .type mn10300_local_dcache_flush_inv_range,@function - .type mn10300_local_dcache_flush_inv_range2,@function -mn10300_local_dcache_flush_inv_page: - and ~(PAGE_SIZE-1),d0 - mov PAGE_SIZE,d1 -mn10300_local_dcache_flush_inv_range2: - add d0,d1 -mn10300_local_dcache_flush_inv_range: - movm [d2],(sp) - - movhu (CHCTR),d2 - btst CHCTR_DCEN,d2 - beq mn10300_local_dcache_flush_inv_range_end - - sub d0,d1,a0 - cmp MN10300_DCACHE_FLUSH_INV_BORDER,a0 - ble 1f - - movm (sp),[d2] - bra mn10300_local_dcache_flush_inv -1: - - and L1_CACHE_TAG_MASK,d0 # round start addr down - mov d0,a1 - - add L1_CACHE_BYTES,d1 # round end addr up - and L1_CACHE_TAG_MASK,d1 - - # write a request to flush and invalidate all instances of an address - # from the cache - mov DCACHE_PURGE(0,0),a0 - mov a1,d0 - and L1_CACHE_TAG_ENTRY,d0 - add d0,a0 # starting dcache purge control - # reg address - - sub a1,d1 - lsr L1_CACHE_SHIFT,d1 # total number of entries to - # examine - -mn10300_local_dcache_flush_inv_range_loop: - mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line - # in all ways - - add L1_CACHE_BYTES,a0 - add L1_CACHE_BYTES,a1 - and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0 - add -1,d1 - bne mn10300_local_dcache_flush_inv_range_loop - -mn10300_local_dcache_flush_inv_range_end: - ret [d2],4 - .size mn10300_local_dcache_flush_inv_page,.-mn10300_local_dcache_flush_inv_page - .size mn10300_local_dcache_flush_inv_range,.-mn10300_local_dcache_flush_inv_range - .size mn10300_local_dcache_flush_inv_range2,.-mn10300_local_dcache_flush_inv_range2 diff --git a/arch/mn10300/mm/cache-flush-icache.c b/arch/mn10300/mm/cache-flush-icache.c deleted file mode 100644 index fdb1a9db20f0..000000000000 --- a/arch/mn10300/mm/cache-flush-icache.c +++ /dev/null @@ -1,155 +0,0 @@ -/* Flush dcache and invalidate icache when the dcache is in writeback mode - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include "cache-smp.h" - -/** - * flush_icache_page - Flush a page from the dcache and invalidate the icache - * @vma: The VMA the page is part of. - * @page: The page to be flushed. - * - * Write a page back from the dcache and invalidate the icache so that we can - * run code from it that we've just written into it - */ -void flush_icache_page(struct vm_area_struct *vma, struct page *page) -{ - unsigned long start = page_to_phys(page); - unsigned long flags; - - flags = smp_lock_cache(); - - mn10300_local_dcache_flush_page(start); - mn10300_local_icache_inv_page(start); - - smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, start + PAGE_SIZE); - smp_unlock_cache(flags); -} -EXPORT_SYMBOL(flush_icache_page); - -/** - * flush_icache_page_range - Flush dcache and invalidate icache for part of a - * single page - * @start: The starting virtual address of the page part. - * @end: The ending virtual address of the page part. - * - * Flush the dcache and invalidate the icache for part of a single page, as - * determined by the virtual addresses given. The page must be in the paged - * area. - */ -static void flush_icache_page_range(unsigned long start, unsigned long end) -{ - unsigned long addr, size, off; - struct page *page; - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *ppte, pte; - - /* work out how much of the page to flush */ - off = start & ~PAGE_MASK; - size = end - start; - - /* get the physical address the page is mapped to from the page - * tables */ - pgd = pgd_offset(current->mm, start); - if (!pgd || !pgd_val(*pgd)) - return; - - pud = pud_offset(pgd, start); - if (!pud || !pud_val(*pud)) - return; - - pmd = pmd_offset(pud, start); - if (!pmd || !pmd_val(*pmd)) - return; - - ppte = pte_offset_map(pmd, start); - if (!ppte) - return; - pte = *ppte; - pte_unmap(ppte); - - if (pte_none(pte)) - return; - - page = pte_page(pte); - if (!page) - return; - - addr = page_to_phys(page); - - /* flush the dcache and invalidate the icache coverage on that - * region */ - mn10300_local_dcache_flush_range2(addr + off, size); - mn10300_local_icache_inv_range2(addr + off, size); - smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, end); -} - -/** - * flush_icache_range - Globally flush dcache and invalidate icache for region - * @start: The starting virtual address of the region. - * @end: The ending virtual address of the region. - * - * This is used by the kernel to globally flush some code it has just written - * from the dcache back to RAM and then to globally invalidate the icache over - * that region so that that code can be run on all CPUs in the system. - */ -void flush_icache_range(unsigned long start, unsigned long end) -{ - unsigned long start_page, end_page; - unsigned long flags; - - flags = smp_lock_cache(); - - if (end > 0x80000000UL) { - /* addresses above 0xa0000000 do not go through the cache */ - if (end > 0xa0000000UL) { - end = 0xa0000000UL; - if (start >= end) - goto done; - } - - /* kernel addresses between 0x80000000 and 0x9fffffff do not - * require page tables, so we just map such addresses - * directly */ - start_page = (start >= 0x80000000UL) ? start : 0x80000000UL; - mn10300_local_dcache_flush_range(start_page, end); - mn10300_local_icache_inv_range(start_page, end); - smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start_page, end); - if (start_page == start) - goto done; - end = start_page; - } - - start_page = start & PAGE_MASK; - end_page = (end - 1) & PAGE_MASK; - - if (start_page == end_page) { - /* the first and last bytes are on the same page */ - flush_icache_page_range(start, end); - } else if (start_page + 1 == end_page) { - /* split over two virtually contiguous pages */ - flush_icache_page_range(start, end_page); - flush_icache_page_range(end_page, end); - } else { - /* more than 2 pages; just flush the entire cache */ - mn10300_dcache_flush(); - mn10300_icache_inv(); - smp_cache_call(SMP_IDCACHE_INV_FLUSH, 0, 0); - } - -done: - smp_unlock_cache(flags); -} -EXPORT_SYMBOL(flush_icache_range); diff --git a/arch/mn10300/mm/cache-inv-by-reg.S b/arch/mn10300/mm/cache-inv-by-reg.S deleted file mode 100644 index a60825b91e77..000000000000 --- a/arch/mn10300/mm/cache-inv-by-reg.S +++ /dev/null @@ -1,350 +0,0 @@ -/* MN10300 CPU cache invalidation routines, using automatic purge registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include "cache.inc" - -#define mn10300_local_dcache_inv_range_intr_interval \ - +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1) - -#if mn10300_local_dcache_inv_range_intr_interval > 0xff -#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less -#endif - - .am33_2 - -#ifndef CONFIG_SMP - .globl mn10300_icache_inv - .globl mn10300_icache_inv_page - .globl mn10300_icache_inv_range - .globl mn10300_icache_inv_range2 - .globl mn10300_dcache_inv - .globl mn10300_dcache_inv_page - .globl mn10300_dcache_inv_range - .globl mn10300_dcache_inv_range2 - -mn10300_icache_inv = mn10300_local_icache_inv -mn10300_icache_inv_page = mn10300_local_icache_inv_page -mn10300_icache_inv_range = mn10300_local_icache_inv_range -mn10300_icache_inv_range2 = mn10300_local_icache_inv_range2 -mn10300_dcache_inv = mn10300_local_dcache_inv -mn10300_dcache_inv_page = mn10300_local_dcache_inv_page -mn10300_dcache_inv_range = mn10300_local_dcache_inv_range -mn10300_dcache_inv_range2 = mn10300_local_dcache_inv_range2 - -#endif /* !CONFIG_SMP */ - -############################################################################### -# -# void mn10300_local_icache_inv(void) -# Invalidate the entire icache -# -############################################################################### - ALIGN - .globl mn10300_local_icache_inv - .type mn10300_local_icache_inv,@function -mn10300_local_icache_inv: - mov CHCTR,a0 - - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq mn10300_local_icache_inv_end - - invalidate_icache 1 - -mn10300_local_icache_inv_end: - ret [],0 - .size mn10300_local_icache_inv,.-mn10300_local_icache_inv - -############################################################################### -# -# void mn10300_local_dcache_inv(void) -# Invalidate the entire dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_inv - .type mn10300_local_dcache_inv,@function -mn10300_local_dcache_inv: - mov CHCTR,a0 - - movhu (a0),d0 - btst CHCTR_DCEN,d0 - beq mn10300_local_dcache_inv_end - - invalidate_dcache 1 - -mn10300_local_dcache_inv_end: - ret [],0 - .size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv - -############################################################################### -# -# void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end) -# void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size) -# void mn10300_local_dcache_inv_page(unsigned long start) -# Invalidate a range of addresses on a page in the dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_inv_page - .globl mn10300_local_dcache_inv_range - .globl mn10300_local_dcache_inv_range2 - .type mn10300_local_dcache_inv_page,@function - .type mn10300_local_dcache_inv_range,@function - .type mn10300_local_dcache_inv_range2,@function -mn10300_local_dcache_inv_page: - and ~(PAGE_SIZE-1),d0 - mov PAGE_SIZE,d1 -mn10300_local_dcache_inv_range2: - add d0,d1 -mn10300_local_dcache_inv_range: - # If we are in writeback mode we check the start and end alignments, - # and if they're not cacheline-aligned, we must flush any bits outside - # the range that share cachelines with stuff inside the range -#ifdef CONFIG_MN10300_CACHE_WBACK - btst ~L1_CACHE_TAG_MASK,d0 - bne 1f - btst ~L1_CACHE_TAG_MASK,d1 - beq 2f -1: - bra mn10300_local_dcache_flush_inv_range -2: -#endif /* CONFIG_MN10300_CACHE_WBACK */ - - movm [d2,d3,a2],(sp) - - mov CHCTR,a0 - movhu (a0),d2 - btst CHCTR_DCEN,d2 - beq mn10300_local_dcache_inv_range_end - - # round the addresses out to be full cachelines, unless we're in - # writeback mode, in which case we would be in flush and invalidate by - # now -#ifndef CONFIG_MN10300_CACHE_WBACK - and L1_CACHE_TAG_MASK,d0 # round start addr down - - mov L1_CACHE_BYTES-1,d2 - add d2,d1 - and L1_CACHE_TAG_MASK,d1 # round end addr up -#endif /* !CONFIG_MN10300_CACHE_WBACK */ - - sub d0,d1,d2 # calculate the total size - mov d0,a2 # A2 = start address - mov d1,a1 # A1 = end address - - LOCAL_CLI_SAVE(d3) - - mov DCPGCR,a0 # make sure the purger isn't busy - setlb - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - - # skip initial address alignment calculation if address is zero - mov d2,d1 - cmp 0,a2 - beq 1f - -dcivloop: - /* calculate alignsize - * - * alignsize = L1_CACHE_BYTES; - * while (! start & alignsize) { - * alignsize <<=1; - * } - * d1 = alignsize; - */ - mov L1_CACHE_BYTES,d1 - lsr 1,d1 - setlb - add d1,d1 - mov d1,d0 - and a2,d0 - leq - -1: - /* calculate invsize - * - * if (totalsize > alignsize) { - * invsize = alignsize; - * } else { - * invsize = totalsize; - * tmp = 0x80000000; - * while (! invsize & tmp) { - * tmp >>= 1; - * } - * invsize = tmp; - * } - * d1 = invsize - */ - cmp d2,d1 - bns 2f - mov d2,d1 - - mov 0x80000000,d0 # start from 31bit=1 - setlb - lsr 1,d0 - mov d0,e0 - and d1,e0 - leq - mov d0,d1 - -2: - /* set mask - * - * mask = ~(invsize-1); - * DCPGMR = mask; - */ - mov d1,d0 - add -1,d0 - not d0 - mov d0,(DCPGMR) - - # invalidate area - mov a2,d0 - or DCPGCR_DCI,d0 - mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCI - - setlb # wait for the purge to complete - mov (a0),d0 - btst DCPGCR_DCPGBSY,d0 - lne - - sub d1,d2 # decrease size remaining - add d1,a2 # increase next start address - - /* check invalidating of end address - * - * a2 = a2 + invsize - * if (a2 < end) { - * goto dcivloop; - * } */ - cmp a1,a2 - bns dcivloop - - LOCAL_IRQ_RESTORE(d3) - -mn10300_local_dcache_inv_range_end: - ret [d2,d3,a2],12 - .size mn10300_local_dcache_inv_page,.-mn10300_local_dcache_inv_page - .size mn10300_local_dcache_inv_range,.-mn10300_local_dcache_inv_range - .size mn10300_local_dcache_inv_range2,.-mn10300_local_dcache_inv_range2 - -############################################################################### -# -# void mn10300_local_icache_inv_page(unsigned long start) -# void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size) -# void mn10300_local_icache_inv_range(unsigned long start, unsigned long end) -# Invalidate a range of addresses on a page in the icache -# -############################################################################### - ALIGN - .globl mn10300_local_icache_inv_page - .globl mn10300_local_icache_inv_range - .globl mn10300_local_icache_inv_range2 - .type mn10300_local_icache_inv_page,@function - .type mn10300_local_icache_inv_range,@function - .type mn10300_local_icache_inv_range2,@function -mn10300_local_icache_inv_page: - and ~(PAGE_SIZE-1),d0 - mov PAGE_SIZE,d1 -mn10300_local_icache_inv_range2: - add d0,d1 -mn10300_local_icache_inv_range: - movm [d2,d3,a2],(sp) - - mov CHCTR,a0 - movhu (a0),d2 - btst CHCTR_ICEN,d2 - beq mn10300_local_icache_inv_range_reg_end - - /* calculate alignsize - * - * alignsize = L1_CACHE_BYTES; - * for (i = (end - start - 1) / L1_CACHE_BYTES ; i > 0; i >>= 1) { - * alignsize <<= 1; - * } - * d2 = alignsize; - */ - mov L1_CACHE_BYTES,d2 - sub d0,d1,d3 - add -1,d3 - lsr L1_CACHE_SHIFT,d3 - beq 2f -1: - add d2,d2 - lsr 1,d3 - bne 1b -2: - - /* a1 = end */ - mov d1,a1 - - LOCAL_CLI_SAVE(d3) - - mov ICIVCR,a0 - /* wait for busy bit of area invalidation */ - setlb - mov (a0),d1 - btst ICIVCR_ICIVBSY,d1 - lne - - /* set mask - * - * mask = ~(alignsize-1); - * ICIVMR = mask; - */ - mov d2,d1 - add -1,d1 - not d1 - mov d1,(ICIVMR) - /* a2 = mask & start */ - and d1,d0,a2 - -icivloop: - /* area invalidate - * - * ICIVCR = (mask & start) | ICIVCR_ICI - */ - mov a2,d0 - or ICIVCR_ICI,d0 - mov d0,(a0) - - /* wait for busy bit of area invalidation */ - setlb - mov (a0),d1 - btst ICIVCR_ICIVBSY,d1 - lne - - /* check invalidating of end address - * - * a2 = a2 + alignsize - * if (a2 < end) { - * goto icivloop; - * } */ - add d2,a2 - cmp a1,a2 - bns icivloop - - LOCAL_IRQ_RESTORE(d3) - -mn10300_local_icache_inv_range_reg_end: - ret [d2,d3,a2],12 - .size mn10300_local_icache_inv_page,.-mn10300_local_icache_inv_page - .size mn10300_local_icache_inv_range,.-mn10300_local_icache_inv_range - .size mn10300_local_icache_inv_range2,.-mn10300_local_icache_inv_range2 diff --git a/arch/mn10300/mm/cache-inv-by-tag.S b/arch/mn10300/mm/cache-inv-by-tag.S deleted file mode 100644 index ccedce9c144d..000000000000 --- a/arch/mn10300/mm/cache-inv-by-tag.S +++ /dev/null @@ -1,276 +0,0 @@ -/* MN10300 CPU core caching routines - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include "cache.inc" - -#define mn10300_local_dcache_inv_range_intr_interval \ - +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1) - -#if mn10300_local_dcache_inv_range_intr_interval > 0xff -#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less -#endif - - .am33_2 - - .globl mn10300_local_icache_inv_page - .globl mn10300_local_icache_inv_range - .globl mn10300_local_icache_inv_range2 - -mn10300_local_icache_inv_page = mn10300_local_icache_inv -mn10300_local_icache_inv_range = mn10300_local_icache_inv -mn10300_local_icache_inv_range2 = mn10300_local_icache_inv - -#ifndef CONFIG_SMP - .globl mn10300_icache_inv - .globl mn10300_icache_inv_page - .globl mn10300_icache_inv_range - .globl mn10300_icache_inv_range2 - .globl mn10300_dcache_inv - .globl mn10300_dcache_inv_page - .globl mn10300_dcache_inv_range - .globl mn10300_dcache_inv_range2 - -mn10300_icache_inv = mn10300_local_icache_inv -mn10300_icache_inv_page = mn10300_local_icache_inv_page -mn10300_icache_inv_range = mn10300_local_icache_inv_range -mn10300_icache_inv_range2 = mn10300_local_icache_inv_range2 -mn10300_dcache_inv = mn10300_local_dcache_inv -mn10300_dcache_inv_page = mn10300_local_dcache_inv_page -mn10300_dcache_inv_range = mn10300_local_dcache_inv_range -mn10300_dcache_inv_range2 = mn10300_local_dcache_inv_range2 - -#endif /* !CONFIG_SMP */ - -############################################################################### -# -# void mn10300_local_icache_inv(void) -# Invalidate the entire icache -# -############################################################################### - ALIGN - .globl mn10300_local_icache_inv - .type mn10300_local_icache_inv,@function -mn10300_local_icache_inv: - mov CHCTR,a0 - - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq mn10300_local_icache_inv_end - - invalidate_icache 1 - -mn10300_local_icache_inv_end: - ret [],0 - .size mn10300_local_icache_inv,.-mn10300_local_icache_inv - -############################################################################### -# -# void mn10300_local_dcache_inv(void) -# Invalidate the entire dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_inv - .type mn10300_local_dcache_inv,@function -mn10300_local_dcache_inv: - mov CHCTR,a0 - - movhu (a0),d0 - btst CHCTR_DCEN,d0 - beq mn10300_local_dcache_inv_end - - invalidate_dcache 1 - -mn10300_local_dcache_inv_end: - ret [],0 - .size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv - -############################################################################### -# -# void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end) -# void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size) -# void mn10300_local_dcache_inv_page(unsigned long start) -# Invalidate a range of addresses on a page in the dcache -# -############################################################################### - ALIGN - .globl mn10300_local_dcache_inv_page - .globl mn10300_local_dcache_inv_range - .globl mn10300_local_dcache_inv_range2 - .type mn10300_local_dcache_inv_page,@function - .type mn10300_local_dcache_inv_range,@function - .type mn10300_local_dcache_inv_range2,@function -mn10300_local_dcache_inv_page: - and ~(PAGE_SIZE-1),d0 - mov PAGE_SIZE,d1 -mn10300_local_dcache_inv_range2: - add d0,d1 -mn10300_local_dcache_inv_range: - # If we are in writeback mode we check the start and end alignments, - # and if they're not cacheline-aligned, we must flush any bits outside - # the range that share cachelines with stuff inside the range -#ifdef CONFIG_MN10300_CACHE_WBACK - btst ~L1_CACHE_TAG_MASK,d0 - bne 1f - btst ~L1_CACHE_TAG_MASK,d1 - beq 2f -1: - bra mn10300_local_dcache_flush_inv_range -2: -#endif /* CONFIG_MN10300_CACHE_WBACK */ - - movm [d2,d3,a2],(sp) - - mov CHCTR,a2 - movhu (a2),d2 - btst CHCTR_DCEN,d2 - beq mn10300_local_dcache_inv_range_end - -#ifndef CONFIG_MN10300_CACHE_WBACK - and L1_CACHE_TAG_MASK,d0 # round start addr down - - add L1_CACHE_BYTES,d1 # round end addr up - and L1_CACHE_TAG_MASK,d1 -#endif /* !CONFIG_MN10300_CACHE_WBACK */ - mov d0,a1 - - clr d2 # we're going to clear tag RAM - # entries - - # read the tags from the tag RAM, and if they indicate a valid dirty - # cache line then invalidate that line - mov DCACHE_TAG(0,0),a0 - mov a1,d0 - and L1_CACHE_TAG_ENTRY,d0 - add d0,a0 # starting dcache tag RAM - # access address - - sub a1,d1 - lsr L1_CACHE_SHIFT,d1 # total number of entries to - # examine - - and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base - -mn10300_local_dcache_inv_range_outer_loop: - LOCAL_CLI_SAVE(d3) - - # disable the dcache - movhu (a2),d0 - and ~CHCTR_DCEN,d0 - movhu d0,(a2) - - # and wait for it to calm down - setlb - movhu (a2),d0 - btst CHCTR_DCBUSY,d0 - lne - -mn10300_local_dcache_inv_range_loop: - - # process the way 0 slot - mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot - btst L1_CACHE_TAG_VALID,d0 - beq mn10300_local_dcache_inv_range_skip_0 # jump if this cacheline - # is not valid - - xor a1,d0 - lsr 12,d0 - bne mn10300_local_dcache_inv_range_skip_0 # jump if not this cacheline - - mov d2,(L1_CACHE_WAYDISP*0,a0) # kill the tag - -mn10300_local_dcache_inv_range_skip_0: - - # process the way 1 slot - mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot - btst L1_CACHE_TAG_VALID,d0 - beq mn10300_local_dcache_inv_range_skip_1 # jump if this cacheline - # is not valid - - xor a1,d0 - lsr 12,d0 - bne mn10300_local_dcache_inv_range_skip_1 # jump if not this cacheline - - mov d2,(L1_CACHE_WAYDISP*1,a0) # kill the tag - -mn10300_local_dcache_inv_range_skip_1: - - # process the way 2 slot - mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot - btst L1_CACHE_TAG_VALID,d0 - beq mn10300_local_dcache_inv_range_skip_2 # jump if this cacheline - # is not valid - - xor a1,d0 - lsr 12,d0 - bne mn10300_local_dcache_inv_range_skip_2 # jump if not this cacheline - - mov d2,(L1_CACHE_WAYDISP*2,a0) # kill the tag - -mn10300_local_dcache_inv_range_skip_2: - - # process the way 3 slot - mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot - btst L1_CACHE_TAG_VALID,d0 - beq mn10300_local_dcache_inv_range_skip_3 # jump if this cacheline - # is not valid - - xor a1,d0 - lsr 12,d0 - bne mn10300_local_dcache_inv_range_skip_3 # jump if not this cacheline - - mov d2,(L1_CACHE_WAYDISP*3,a0) # kill the tag - -mn10300_local_dcache_inv_range_skip_3: - - # approx every N steps we re-enable the cache and see if there are any - # interrupts to be processed - # we also break out if we've reached the end of the loop - # (the bottom nibble of the count is zero in both cases) - add L1_CACHE_BYTES,a0 - add L1_CACHE_BYTES,a1 - and ~L1_CACHE_WAYDISP,a0 - add -1,d1 - btst mn10300_local_dcache_inv_range_intr_interval,d1 - bne mn10300_local_dcache_inv_range_loop - - # wait for the cache to finish what it's doing - setlb - movhu (a2),d0 - btst CHCTR_DCBUSY,d0 - lne - - # and reenable it - or CHCTR_DCEN,d0 - movhu d0,(a2) - movhu (a2),d0 - - # re-enable interrupts - # - we don't bother with delay NOPs as we'll have enough instructions - # before we disable interrupts again to give the interrupts a chance - # to happen - LOCAL_IRQ_RESTORE(d3) - - # go around again if the counter hasn't yet reached zero - add 0,d1 - bne mn10300_local_dcache_inv_range_outer_loop - -mn10300_local_dcache_inv_range_end: - ret [d2,d3,a2],12 - .size mn10300_local_dcache_inv_page,.-mn10300_local_dcache_inv_page - .size mn10300_local_dcache_inv_range,.-mn10300_local_dcache_inv_range - .size mn10300_local_dcache_inv_range2,.-mn10300_local_dcache_inv_range2 diff --git a/arch/mn10300/mm/cache-inv-icache.c b/arch/mn10300/mm/cache-inv-icache.c deleted file mode 100644 index a6b63dde603d..000000000000 --- a/arch/mn10300/mm/cache-inv-icache.c +++ /dev/null @@ -1,129 +0,0 @@ -/* Invalidate icache when dcache doesn't need invalidation as it's in - * write-through mode - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include "cache-smp.h" - -/** - * flush_icache_page_range - Flush dcache and invalidate icache for part of a - * single page - * @start: The starting virtual address of the page part. - * @end: The ending virtual address of the page part. - * - * Invalidate the icache for part of a single page, as determined by the - * virtual addresses given. The page must be in the paged area. The dcache is - * not flushed as the cache must be in write-through mode to get here. - */ -static void flush_icache_page_range(unsigned long start, unsigned long end) -{ - unsigned long addr, size, off; - struct page *page; - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *ppte, pte; - - /* work out how much of the page to flush */ - off = start & ~PAGE_MASK; - size = end - start; - - /* get the physical address the page is mapped to from the page - * tables */ - pgd = pgd_offset(current->mm, start); - if (!pgd || !pgd_val(*pgd)) - return; - - pud = pud_offset(pgd, start); - if (!pud || !pud_val(*pud)) - return; - - pmd = pmd_offset(pud, start); - if (!pmd || !pmd_val(*pmd)) - return; - - ppte = pte_offset_map(pmd, start); - if (!ppte) - return; - pte = *ppte; - pte_unmap(ppte); - - if (pte_none(pte)) - return; - - page = pte_page(pte); - if (!page) - return; - - addr = page_to_phys(page); - - /* invalidate the icache coverage on that region */ - mn10300_local_icache_inv_range2(addr + off, size); - smp_cache_call(SMP_ICACHE_INV_RANGE, start, end); -} - -/** - * flush_icache_range - Globally flush dcache and invalidate icache for region - * @start: The starting virtual address of the region. - * @end: The ending virtual address of the region. - * - * This is used by the kernel to globally flush some code it has just written - * from the dcache back to RAM and then to globally invalidate the icache over - * that region so that that code can be run on all CPUs in the system. - */ -void flush_icache_range(unsigned long start, unsigned long end) -{ - unsigned long start_page, end_page; - unsigned long flags; - - flags = smp_lock_cache(); - - if (end > 0x80000000UL) { - /* addresses above 0xa0000000 do not go through the cache */ - if (end > 0xa0000000UL) { - end = 0xa0000000UL; - if (start >= end) - goto done; - } - - /* kernel addresses between 0x80000000 and 0x9fffffff do not - * require page tables, so we just map such addresses - * directly */ - start_page = (start >= 0x80000000UL) ? start : 0x80000000UL; - mn10300_icache_inv_range(start_page, end); - smp_cache_call(SMP_ICACHE_INV_RANGE, start, end); - if (start_page == start) - goto done; - end = start_page; - } - - start_page = start & PAGE_MASK; - end_page = (end - 1) & PAGE_MASK; - - if (start_page == end_page) { - /* the first and last bytes are on the same page */ - flush_icache_page_range(start, end); - } else if (start_page + 1 == end_page) { - /* split over two virtually contiguous pages */ - flush_icache_page_range(start, end_page); - flush_icache_page_range(end_page, end); - } else { - /* more than 2 pages; just flush the entire cache */ - mn10300_local_icache_inv(); - smp_cache_call(SMP_ICACHE_INV, 0, 0); - } - -done: - smp_unlock_cache(flags); -} -EXPORT_SYMBOL(flush_icache_range); diff --git a/arch/mn10300/mm/cache-smp-flush.c b/arch/mn10300/mm/cache-smp-flush.c deleted file mode 100644 index fd51af5eaf70..000000000000 --- a/arch/mn10300/mm/cache-smp-flush.c +++ /dev/null @@ -1,156 +0,0 @@ -/* Functions for global dcache flush when writeback caching in SMP - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include "cache-smp.h" - -/** - * mn10300_dcache_flush - Globally flush data cache - * - * Flush the data cache on all CPUs. - */ -void mn10300_dcache_flush(void) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_flush(); - smp_cache_call(SMP_DCACHE_FLUSH, 0, 0); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_flush_page - Globally flush a page of data cache - * @start: The address of the page of memory to be flushed. - * - * Flush a range of addresses in the data cache on all CPUs covering - * the page that includes the given address. - */ -void mn10300_dcache_flush_page(unsigned long start) -{ - unsigned long flags; - - start &= ~(PAGE_SIZE-1); - - flags = smp_lock_cache(); - mn10300_local_dcache_flush_page(start); - smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, start + PAGE_SIZE); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_flush_range - Globally flush range of data cache - * @start: The start address of the region to be flushed. - * @end: The end address of the region to be flushed. - * - * Flush a range of addresses in the data cache on all CPUs, between start and - * end-1 inclusive. - */ -void mn10300_dcache_flush_range(unsigned long start, unsigned long end) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_flush_range(start, end); - smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, end); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_flush_range2 - Globally flush range of data cache - * @start: The start address of the region to be flushed. - * @size: The size of the region to be flushed. - * - * Flush a range of addresses in the data cache on all CPUs, between start and - * start+size-1 inclusive. - */ -void mn10300_dcache_flush_range2(unsigned long start, unsigned long size) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_flush_range2(start, size); - smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, start + size); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_flush_inv - Globally flush and invalidate data cache - * - * Flush and invalidate the data cache on all CPUs. - */ -void mn10300_dcache_flush_inv(void) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_flush_inv(); - smp_cache_call(SMP_DCACHE_FLUSH_INV, 0, 0); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_flush_inv_page - Globally flush and invalidate a page of data - * cache - * @start: The address of the page of memory to be flushed and invalidated. - * - * Flush and invalidate a range of addresses in the data cache on all CPUs - * covering the page that includes the given address. - */ -void mn10300_dcache_flush_inv_page(unsigned long start) -{ - unsigned long flags; - - start &= ~(PAGE_SIZE-1); - - flags = smp_lock_cache(); - mn10300_local_dcache_flush_inv_page(start); - smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, start + PAGE_SIZE); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_flush_inv_range - Globally flush and invalidate range of data - * cache - * @start: The start address of the region to be flushed and invalidated. - * @end: The end address of the region to be flushed and invalidated. - * - * Flush and invalidate a range of addresses in the data cache on all CPUs, - * between start and end-1 inclusive. - */ -void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_flush_inv_range(start, end); - smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, end); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_flush_inv_range2 - Globally flush and invalidate range of data - * cache - * @start: The start address of the region to be flushed and invalidated. - * @size: The size of the region to be flushed and invalidated. - * - * Flush and invalidate a range of addresses in the data cache on all CPUs, - * between start and start+size-1 inclusive. - */ -void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_flush_inv_range2(start, size); - smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, start + size); - smp_unlock_cache(flags); -} diff --git a/arch/mn10300/mm/cache-smp-inv.c b/arch/mn10300/mm/cache-smp-inv.c deleted file mode 100644 index ff1787358c8e..000000000000 --- a/arch/mn10300/mm/cache-smp-inv.c +++ /dev/null @@ -1,153 +0,0 @@ -/* Functions for global i/dcache invalidation when caching in SMP - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include "cache-smp.h" - -/** - * mn10300_icache_inv - Globally invalidate instruction cache - * - * Invalidate the instruction cache on all CPUs. - */ -void mn10300_icache_inv(void) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_icache_inv(); - smp_cache_call(SMP_ICACHE_INV, 0, 0); - smp_unlock_cache(flags); -} - -/** - * mn10300_icache_inv_page - Globally invalidate a page of instruction cache - * @start: The address of the page of memory to be invalidated. - * - * Invalidate a range of addresses in the instruction cache on all CPUs - * covering the page that includes the given address. - */ -void mn10300_icache_inv_page(unsigned long start) -{ - unsigned long flags; - - start &= ~(PAGE_SIZE-1); - - flags = smp_lock_cache(); - mn10300_local_icache_inv_page(start); - smp_cache_call(SMP_ICACHE_INV_RANGE, start, start + PAGE_SIZE); - smp_unlock_cache(flags); -} - -/** - * mn10300_icache_inv_range - Globally invalidate range of instruction cache - * @start: The start address of the region to be invalidated. - * @end: The end address of the region to be invalidated. - * - * Invalidate a range of addresses in the instruction cache on all CPUs, - * between start and end-1 inclusive. - */ -void mn10300_icache_inv_range(unsigned long start, unsigned long end) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_icache_inv_range(start, end); - smp_cache_call(SMP_ICACHE_INV_RANGE, start, end); - smp_unlock_cache(flags); -} - -/** - * mn10300_icache_inv_range2 - Globally invalidate range of instruction cache - * @start: The start address of the region to be invalidated. - * @size: The size of the region to be invalidated. - * - * Invalidate a range of addresses in the instruction cache on all CPUs, - * between start and start+size-1 inclusive. - */ -void mn10300_icache_inv_range2(unsigned long start, unsigned long size) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_icache_inv_range2(start, size); - smp_cache_call(SMP_ICACHE_INV_RANGE, start, start + size); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_inv - Globally invalidate data cache - * - * Invalidate the data cache on all CPUs. - */ -void mn10300_dcache_inv(void) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_inv(); - smp_cache_call(SMP_DCACHE_INV, 0, 0); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_inv_page - Globally invalidate a page of data cache - * @start: The address of the page of memory to be invalidated. - * - * Invalidate a range of addresses in the data cache on all CPUs covering the - * page that includes the given address. - */ -void mn10300_dcache_inv_page(unsigned long start) -{ - unsigned long flags; - - start &= ~(PAGE_SIZE-1); - - flags = smp_lock_cache(); - mn10300_local_dcache_inv_page(start); - smp_cache_call(SMP_DCACHE_INV_RANGE, start, start + PAGE_SIZE); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_inv_range - Globally invalidate range of data cache - * @start: The start address of the region to be invalidated. - * @end: The end address of the region to be invalidated. - * - * Invalidate a range of addresses in the data cache on all CPUs, between start - * and end-1 inclusive. - */ -void mn10300_dcache_inv_range(unsigned long start, unsigned long end) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_inv_range(start, end); - smp_cache_call(SMP_DCACHE_INV_RANGE, start, end); - smp_unlock_cache(flags); -} - -/** - * mn10300_dcache_inv_range2 - Globally invalidate range of data cache - * @start: The start address of the region to be invalidated. - * @size: The size of the region to be invalidated. - * - * Invalidate a range of addresses in the data cache on all CPUs, between start - * and start+size-1 inclusive. - */ -void mn10300_dcache_inv_range2(unsigned long start, unsigned long size) -{ - unsigned long flags; - - flags = smp_lock_cache(); - mn10300_local_dcache_inv_range2(start, size); - smp_cache_call(SMP_DCACHE_INV_RANGE, start, start + size); - smp_unlock_cache(flags); -} diff --git a/arch/mn10300/mm/cache-smp.c b/arch/mn10300/mm/cache-smp.c deleted file mode 100644 index e80996064d3d..000000000000 --- a/arch/mn10300/mm/cache-smp.c +++ /dev/null @@ -1,105 +0,0 @@ -/* SMP global caching code - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cache-smp.h" - -DEFINE_SPINLOCK(smp_cache_lock); -static unsigned long smp_cache_mask; -static unsigned long smp_cache_start; -static unsigned long smp_cache_end; -static cpumask_t smp_cache_ipi_map; /* Bitmask of cache IPI done CPUs */ - -/** - * smp_cache_interrupt - Handle IPI request to flush caches. - * - * Handle a request delivered by IPI to flush the current CPU's - * caches. The parameters are stored in smp_cache_*. - */ -void smp_cache_interrupt(void) -{ - unsigned long opr_mask = smp_cache_mask; - - switch ((enum smp_dcache_ops)(opr_mask & SMP_DCACHE_OP_MASK)) { - case SMP_DCACHE_NOP: - break; - case SMP_DCACHE_INV: - mn10300_local_dcache_inv(); - break; - case SMP_DCACHE_INV_RANGE: - mn10300_local_dcache_inv_range(smp_cache_start, smp_cache_end); - break; - case SMP_DCACHE_FLUSH: - mn10300_local_dcache_flush(); - break; - case SMP_DCACHE_FLUSH_RANGE: - mn10300_local_dcache_flush_range(smp_cache_start, - smp_cache_end); - break; - case SMP_DCACHE_FLUSH_INV: - mn10300_local_dcache_flush_inv(); - break; - case SMP_DCACHE_FLUSH_INV_RANGE: - mn10300_local_dcache_flush_inv_range(smp_cache_start, - smp_cache_end); - break; - } - - switch ((enum smp_icache_ops)(opr_mask & SMP_ICACHE_OP_MASK)) { - case SMP_ICACHE_NOP: - break; - case SMP_ICACHE_INV: - mn10300_local_icache_inv(); - break; - case SMP_ICACHE_INV_RANGE: - mn10300_local_icache_inv_range(smp_cache_start, smp_cache_end); - break; - } - - cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map); -} - -/** - * smp_cache_call - Issue an IPI to request the other CPUs flush caches - * @opr_mask: Cache operation flags - * @start: Start address of request - * @end: End address of request - * - * Send cache flush IPI to other CPUs. This invokes smp_cache_interrupt() - * above on those other CPUs and then waits for them to finish. - * - * The caller must hold smp_cache_lock. - */ -void smp_cache_call(unsigned long opr_mask, - unsigned long start, unsigned long end) -{ - smp_cache_mask = opr_mask; - smp_cache_start = start; - smp_cache_end = end; - cpumask_copy(&smp_cache_ipi_map, cpu_online_mask); - cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map); - - send_IPI_allbutself(FLUSH_CACHE_IPI); - - while (!cpumask_empty(&smp_cache_ipi_map)) - /* nothing. lockup detection does not belong here */ - mb(); -} diff --git a/arch/mn10300/mm/cache-smp.h b/arch/mn10300/mm/cache-smp.h deleted file mode 100644 index cb52892aa66a..000000000000 --- a/arch/mn10300/mm/cache-smp.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SMP caching definitions - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - - -/* - * Operation requests for smp_cache_call(). - * - * One of smp_icache_ops and one of smp_dcache_ops can be OR'd together. - */ -enum smp_icache_ops { - SMP_ICACHE_NOP = 0x0000, - SMP_ICACHE_INV = 0x0001, - SMP_ICACHE_INV_RANGE = 0x0002, -}; -#define SMP_ICACHE_OP_MASK 0x0003 - -enum smp_dcache_ops { - SMP_DCACHE_NOP = 0x0000, - SMP_DCACHE_INV = 0x0004, - SMP_DCACHE_INV_RANGE = 0x0008, - SMP_DCACHE_FLUSH = 0x000c, - SMP_DCACHE_FLUSH_RANGE = 0x0010, - SMP_DCACHE_FLUSH_INV = 0x0014, - SMP_DCACHE_FLUSH_INV_RANGE = 0x0018, -}; -#define SMP_DCACHE_OP_MASK 0x001c - -#define SMP_IDCACHE_INV_FLUSH (SMP_ICACHE_INV | SMP_DCACHE_FLUSH) -#define SMP_IDCACHE_INV_FLUSH_RANGE (SMP_ICACHE_INV_RANGE | SMP_DCACHE_FLUSH_RANGE) - -/* - * cache-smp.c - */ -#ifdef CONFIG_SMP -extern spinlock_t smp_cache_lock; - -extern void smp_cache_call(unsigned long opr_mask, - unsigned long addr, unsigned long end); - -static inline unsigned long smp_lock_cache(void) - __acquires(&smp_cache_lock) -{ - unsigned long flags; - spin_lock_irqsave(&smp_cache_lock, flags); - return flags; -} - -static inline void smp_unlock_cache(unsigned long flags) - __releases(&smp_cache_lock) -{ - spin_unlock_irqrestore(&smp_cache_lock, flags); -} - -#else -static inline unsigned long smp_lock_cache(void) { return 0; } -static inline void smp_unlock_cache(unsigned long flags) {} -static inline void smp_cache_call(unsigned long opr_mask, - unsigned long addr, unsigned long end) -{ -} -#endif /* CONFIG_SMP */ diff --git a/arch/mn10300/mm/cache.c b/arch/mn10300/mm/cache.c deleted file mode 100644 index 0b925cce2b83..000000000000 --- a/arch/mn10300/mm/cache.c +++ /dev/null @@ -1,54 +0,0 @@ -/* MN10300 Cache flushing routines - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cache-smp.h" - -EXPORT_SYMBOL(mn10300_icache_inv); -EXPORT_SYMBOL(mn10300_icache_inv_range); -EXPORT_SYMBOL(mn10300_icache_inv_range2); -EXPORT_SYMBOL(mn10300_icache_inv_page); -EXPORT_SYMBOL(mn10300_dcache_inv); -EXPORT_SYMBOL(mn10300_dcache_inv_range); -EXPORT_SYMBOL(mn10300_dcache_inv_range2); -EXPORT_SYMBOL(mn10300_dcache_inv_page); - -#ifdef CONFIG_MN10300_CACHE_WBACK -EXPORT_SYMBOL(mn10300_dcache_flush); -EXPORT_SYMBOL(mn10300_dcache_flush_inv); -EXPORT_SYMBOL(mn10300_dcache_flush_inv_range); -EXPORT_SYMBOL(mn10300_dcache_flush_inv_range2); -EXPORT_SYMBOL(mn10300_dcache_flush_inv_page); -EXPORT_SYMBOL(mn10300_dcache_flush_range); -EXPORT_SYMBOL(mn10300_dcache_flush_range2); -EXPORT_SYMBOL(mn10300_dcache_flush_page); -#endif - -/* - * allow userspace to flush the instruction cache - */ -asmlinkage long sys_cacheflush(unsigned long start, unsigned long end) -{ - if (end < start) - return -EINVAL; - - flush_icache_range(start, end); - return 0; -} diff --git a/arch/mn10300/mm/cache.inc b/arch/mn10300/mm/cache.inc deleted file mode 100644 index 394a119b9c73..000000000000 --- a/arch/mn10300/mm/cache.inc +++ /dev/null @@ -1,133 +0,0 @@ -/* MN10300 CPU core caching macros -*- asm -*- - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - - -############################################################################### -# -# Invalidate the instruction cache. -# A0: Should hold CHCTR -# D0: Should have been read from CHCTR -# D1: Will be clobbered -# -# On some cores it is necessary to disable the icache whilst we do this. -# -############################################################################### - .macro invalidate_icache,disable_irq - -#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) - .if \disable_irq - # don't want an interrupt routine seeing a disabled cache - mov epsw,d1 - and ~EPSW_IE,epsw - or EPSW_NMID,epsw - nop - nop - .endif - - # disable the icache - and ~CHCTR_ICEN,d0 - movhu d0,(a0) - - # and wait for it to calm down - setlb - movhu (a0),d0 - btst CHCTR_ICBUSY,d0 - lne - - # invalidate - or CHCTR_ICINV,d0 - movhu d0,(a0) - - # wait for the cache to finish - setlb - movhu (a0),d0 - btst CHCTR_ICBUSY,d0 - lne - - # and reenable it - or CHCTR_ICEN,d0 - movhu d0,(a0) - movhu (a0),d0 - - .if \disable_irq - LOCAL_IRQ_RESTORE(d1) - .endif - -#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ - - # invalidate - or CHCTR_ICINV,d0 - movhu d0,(a0) - movhu (a0),d0 - -#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ - .endm - -############################################################################### -# -# Invalidate the data cache. -# A0: Should hold CHCTR -# D0: Should have been read from CHCTR -# D1: Will be clobbered -# -# On some cores it is necessary to disable the dcache whilst we do this. -# -############################################################################### - .macro invalidate_dcache,disable_irq - -#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) - .if \disable_irq - # don't want an interrupt routine seeing a disabled cache - mov epsw,d1 - and ~EPSW_IE,epsw - or EPSW_NMID,epsw - nop - nop - .endif - - # disable the dcache - and ~CHCTR_DCEN,d0 - movhu d0,(a0) - - # and wait for it to calm down - setlb - movhu (a0),d0 - btst CHCTR_DCBUSY,d0 - lne - - # invalidate - or CHCTR_DCINV,d0 - movhu d0,(a0) - - # wait for the cache to finish - setlb - movhu (a0),d0 - btst CHCTR_DCBUSY,d0 - lne - - # and reenable it - or CHCTR_DCEN,d0 - movhu d0,(a0) - movhu (a0),d0 - - .if \disable_irq - LOCAL_IRQ_RESTORE(d1) - .endif - -#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ - - # invalidate - or CHCTR_DCINV,d0 - movhu d0,(a0) - movhu (a0),d0 - -#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ - .endm diff --git a/arch/mn10300/mm/dma-alloc.c b/arch/mn10300/mm/dma-alloc.c deleted file mode 100644 index e3910d4db102..000000000000 --- a/arch/mn10300/mm/dma-alloc.c +++ /dev/null @@ -1,128 +0,0 @@ -/* MN10300 Dynamic DMA mapping support - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * Derived from: arch/i386/kernel/pci-dma.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -static unsigned long pci_sram_allocated = 0xbc000000; - -static void *mn10300_dma_alloc(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) -{ - unsigned long addr; - void *ret; - - pr_debug("dma_alloc_coherent(%s,%zu,%x)\n", - dev ? dev_name(dev) : "?", size, gfp); - - if (0xbe000000 - pci_sram_allocated >= size) { - size = (size + 255) & ~255; - addr = pci_sram_allocated; - pci_sram_allocated += size; - ret = (void *) addr; - goto done; - } - - if (dev == NULL || dev->coherent_dma_mask < 0xffffffff) - gfp |= GFP_DMA; - - addr = __get_free_pages(gfp, get_order(size)); - if (!addr) - return NULL; - - /* map the coherent memory through the uncached memory window */ - ret = (void *) (addr | 0x20000000); - - /* fill the memory with obvious rubbish */ - memset((void *) addr, 0xfb, size); - - /* write back and evict all cache lines covering this region */ - mn10300_dcache_flush_inv_range2(virt_to_phys((void *) addr), PAGE_SIZE); - -done: - *dma_handle = virt_to_bus((void *) addr); - printk("dma_alloc_coherent() = %p [%x]\n", ret, *dma_handle); - return ret; -} - -static void mn10300_dma_free(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle, unsigned long attrs) -{ - unsigned long addr = (unsigned long) vaddr & ~0x20000000; - - if (addr >= 0x9c000000) - return; - - free_pages(addr, get_order(size)); -} - -static int mn10300_dma_map_sg(struct device *dev, struct scatterlist *sglist, - int nents, enum dma_data_direction direction, - unsigned long attrs) -{ - struct scatterlist *sg; - int i; - - for_each_sg(sglist, sg, nents, i) { - BUG_ON(!sg_page(sg)); - - sg->dma_address = sg_phys(sg); - } - - mn10300_dcache_flush_inv(); - return nents; -} - -static dma_addr_t mn10300_dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction direction, unsigned long attrs) -{ - return page_to_bus(page) + offset; -} - -static void mn10300_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction) -{ - mn10300_dcache_flush_inv(); -} - -static void mn10300_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, - int nelems, enum dma_data_direction direction) -{ - mn10300_dcache_flush_inv(); -} - -static int mn10300_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, so we can't - * guarantee allocations that must be within a tighter range than - * GFP_DMA - */ - if (mask < 0x00ffffff) - return 0; - return 1; -} - -const struct dma_map_ops mn10300_dma_ops = { - .alloc = mn10300_dma_alloc, - .free = mn10300_dma_free, - .map_page = mn10300_dma_map_page, - .map_sg = mn10300_dma_map_sg, - .sync_single_for_device = mn10300_dma_sync_single_for_device, - .sync_sg_for_device = mn10300_dma_sync_sg_for_device, -}; diff --git a/arch/mn10300/mm/extable.c b/arch/mn10300/mm/extable.c deleted file mode 100644 index 045a903ee6b9..000000000000 --- a/arch/mn10300/mm/extable.c +++ /dev/null @@ -1,26 +0,0 @@ -/* MN10300 In-kernel exception handling - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include - -int fixup_exception(struct pt_regs *regs) -{ - const struct exception_table_entry *fixup; - - fixup = search_exception_tables(regs->pc); - if (fixup) { - regs->pc = fixup->fixup; - return 1; - } - - return 0; -} diff --git a/arch/mn10300/mm/fault.c b/arch/mn10300/mm/fault.c deleted file mode 100644 index f0bfa1448744..000000000000 --- a/arch/mn10300/mm/fault.c +++ /dev/null @@ -1,414 +0,0 @@ -/* MN10300 MMU Fault handler - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* For unblank_screen() */ -#include - -#include -#include -#include -#include -#include - -/* - * Unlock any spinlocks which will prevent us from getting the - * message out - */ -void bust_spinlocks(int yes) -{ - if (yes) { - oops_in_progress = 1; - } else { - int loglevel_save = console_loglevel; -#ifdef CONFIG_VT - unblank_screen(); -#endif - oops_in_progress = 0; - /* - * OK, the message is on the console. Now we call printk() - * without oops_in_progress set so that printk will give klogd - * a poke. Hold onto your hats... - */ - console_loglevel = 15; /* NMI oopser may have shut the console - * up */ - printk(" "); - console_loglevel = loglevel_save; - } -} - -void do_BUG(const char *file, int line) -{ - bust_spinlocks(1); - printk(KERN_EMERG CUT_HERE); - printk(KERN_EMERG "kernel BUG at %s:%d!\n", file, line); -} - -#if 0 -static void print_pagetable_entries(pgd_t *pgdir, unsigned long address) -{ - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - pgd = pgdir + __pgd_offset(address); - printk(KERN_DEBUG "pgd entry %p: %016Lx\n", - pgd, (long long) pgd_val(*pgd)); - - if (!pgd_present(*pgd)) { - printk(KERN_DEBUG "... pgd not present!\n"); - return; - } - pmd = pmd_offset(pgd, address); - printk(KERN_DEBUG "pmd entry %p: %016Lx\n", - pmd, (long long)pmd_val(*pmd)); - - if (!pmd_present(*pmd)) { - printk(KERN_DEBUG "... pmd not present!\n"); - return; - } - pte = pte_offset(pmd, address); - printk(KERN_DEBUG "pte entry %p: %016Lx\n", - pte, (long long) pte_val(*pte)); - - if (!pte_present(*pte)) - printk(KERN_DEBUG "... pte not present!\n"); -} -#endif - -/* - * This routine handles page faults. It determines the address, - * and the problem, and then passes it off to one of the appropriate - * routines. - * - * fault_code: - * - LSW: either MMUFCR_IFC or MMUFCR_DFC as appropriate - * - MSW: 0 if data access, 1 if instruction access - * - bit 0: TLB miss flag - * - bit 1: initial write - * - bit 2: page invalid - * - bit 3: protection violation - * - bit 4: accessor (0=user 1=kernel) - * - bit 5: 0=read 1=write - * - bit 6-8: page protection spec - * - bit 9: illegal address - * - bit 16: 0=data 1=ins - * - */ -asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long fault_code, - unsigned long address) -{ - struct vm_area_struct *vma; - struct task_struct *tsk; - struct mm_struct *mm; - unsigned long page; - siginfo_t info; - int fault; - unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; - -#ifdef CONFIG_GDBSTUB - /* handle GDB stub causing a fault */ - if (gdbstub_busy) { - gdbstub_exception(regs, TBR & TBR_INT_CODE); - return; - } -#endif - -#if 0 - printk(KERN_DEBUG "--- do_page_fault(%p,%s:%04lx,%08lx)\n", - regs, - fault_code & 0x10000 ? "ins" : "data", - fault_code & 0xffff, address); -#endif - - tsk = current; - - /* - * We fault-in kernel-space virtual memory on-demand. The - * 'reference' page table is init_mm.pgd. - * - * NOTE! We MUST NOT take any locks for this case. We may - * be in an interrupt or a critical region, and should - * only copy the information from the master page table, - * nothing more. - * - * This verifies that the fault happens in kernel space - * and that the fault was a page not present (invalid) error - */ - if (address >= VMALLOC_START && address < VMALLOC_END && - (fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR && - (fault_code & MMUFCR_xFC_PGINVAL) == MMUFCR_xFC_PGINVAL - ) - goto vmalloc_fault; - - mm = tsk->mm; - info.si_code = SEGV_MAPERR; - - /* - * If we're in an interrupt or have no user - * context, we must not take the fault.. - */ - if (faulthandler_disabled() || !mm) - goto no_context; - - if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) - flags |= FAULT_FLAG_USER; -retry: - down_read(&mm->mmap_sem); - - vma = find_vma(mm, address); - if (!vma) - goto bad_area; - if (vma->vm_start <= address) - goto good_area; - if (!(vma->vm_flags & VM_GROWSDOWN)) - goto bad_area; - - if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) { - /* accessing the stack below the stack pointer is always a - * bug */ - if ((address & PAGE_MASK) + 2 * PAGE_SIZE < regs->sp) { -#if 0 - printk(KERN_WARNING - "[%d] ### Access below stack @%lx (sp=%lx)\n", - current->pid, address, regs->sp); - printk(KERN_WARNING - "vma [%08x - %08x]\n", - vma->vm_start, vma->vm_end); - show_registers(regs); - printk(KERN_WARNING - "[%d] ### Code: [%08lx]" - " %02x %02x %02x %02x %02x %02x %02x %02x\n", - current->pid, - regs->pc, - ((u8 *) regs->pc)[0], - ((u8 *) regs->pc)[1], - ((u8 *) regs->pc)[2], - ((u8 *) regs->pc)[3], - ((u8 *) regs->pc)[4], - ((u8 *) regs->pc)[5], - ((u8 *) regs->pc)[6], - ((u8 *) regs->pc)[7] - ); -#endif - goto bad_area; - } - } - - if (expand_stack(vma, address)) - goto bad_area; - -/* - * Ok, we have a good vm_area for this memory access, so - * we can handle it.. - */ -good_area: - info.si_code = SEGV_ACCERR; - switch (fault_code & (MMUFCR_xFC_PGINVAL|MMUFCR_xFC_TYPE)) { - default: /* 3: write, present */ - case MMUFCR_xFC_TYPE_WRITE: -#ifdef TEST_VERIFY_AREA - if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR) - printk(KERN_DEBUG "WP fault at %08lx\n", regs->pc); -#endif - /* write to absent page */ - case MMUFCR_xFC_PGINVAL | MMUFCR_xFC_TYPE_WRITE: - if (!(vma->vm_flags & VM_WRITE)) - goto bad_area; - flags |= FAULT_FLAG_WRITE; - break; - - /* read from protected page */ - case MMUFCR_xFC_TYPE_READ: - goto bad_area; - - /* read from absent page present */ - case MMUFCR_xFC_PGINVAL | MMUFCR_xFC_TYPE_READ: - if (!(vma->vm_flags & (VM_READ | VM_EXEC))) - goto bad_area; - break; - } - - /* - * If for any reason at all we couldn't handle the fault, - * make sure we exit gracefully rather than endlessly redo - * the fault. - */ - fault = handle_mm_fault(vma, address, flags); - - if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) - return; - - if (unlikely(fault & VM_FAULT_ERROR)) { - if (fault & VM_FAULT_OOM) - goto out_of_memory; - else if (fault & VM_FAULT_SIGSEGV) - goto bad_area; - else if (fault & VM_FAULT_SIGBUS) - goto do_sigbus; - BUG(); - } - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_MAJOR) - current->maj_flt++; - else - current->min_flt++; - if (fault & VM_FAULT_RETRY) { - flags &= ~FAULT_FLAG_ALLOW_RETRY; - - /* No need to up_read(&mm->mmap_sem) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - - goto retry; - } - } - - up_read(&mm->mmap_sem); - return; - -/* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. - */ -bad_area: - up_read(&mm->mmap_sem); - - /* User mode accesses just cause a SIGSEGV */ - if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) { - info.si_signo = SIGSEGV; - info.si_errno = 0; - /* info.si_code has been set above */ - info.si_addr = (void *)address; - force_sig_info(SIGSEGV, &info, tsk); - return; - } - -no_context: - /* Are we prepared to handle this kernel fault? */ - if (fixup_exception(regs)) - return; - -/* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - */ - - bust_spinlocks(1); - - if (address < PAGE_SIZE) - printk(KERN_ALERT - "Unable to handle kernel NULL pointer dereference"); - else - printk(KERN_ALERT - "Unable to handle kernel paging request"); - printk(" at virtual address %08lx\n", address); - printk(" printing pc:\n"); - printk(KERN_ALERT "%08lx\n", regs->pc); - - debugger_intercept(fault_code & 0x00010000 ? EXCEP_IAERROR : EXCEP_DAERROR, - SIGSEGV, SEGV_ACCERR, regs); - - page = PTBR; - page = ((unsigned long *) __va(page))[address >> 22]; - printk(KERN_ALERT "*pde = %08lx\n", page); - if (page & 1) { - page &= PAGE_MASK; - address &= 0x003ff000; - page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT]; - printk(KERN_ALERT "*pte = %08lx\n", page); - } - - die("Oops", regs, fault_code); - do_exit(SIGKILL); - -/* - * We ran out of memory, or some other thing happened to us that made - * us unable to handle the page fault gracefully. - */ -out_of_memory: - up_read(&mm->mmap_sem); - if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) { - pagefault_out_of_memory(); - return; - } - goto no_context; - -do_sigbus: - up_read(&mm->mmap_sem); - - /* - * Send a sigbus, regardless of whether we were in kernel - * or user mode. - */ - info.si_signo = SIGBUS; - info.si_errno = 0; - info.si_code = BUS_ADRERR; - info.si_addr = (void *)address; - force_sig_info(SIGBUS, &info, tsk); - - /* Kernel mode? Handle exceptions or die */ - if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR) - goto no_context; - return; - -vmalloc_fault: - { - /* - * Synchronize this task's top level page-table - * with the 'reference' page table. - * - * Do _not_ use "tsk" here. We might be inside - * an interrupt in the middle of a task switch.. - */ - int index = pgd_index(address); - pgd_t *pgd, *pgd_k; - pud_t *pud, *pud_k; - pmd_t *pmd, *pmd_k; - pte_t *pte_k; - - pgd_k = init_mm.pgd + index; - - if (!pgd_present(*pgd_k)) - goto no_context; - - pud_k = pud_offset(pgd_k, address); - if (!pud_present(*pud_k)) - goto no_context; - - pmd_k = pmd_offset(pud_k, address); - if (!pmd_present(*pmd_k)) - goto no_context; - - pgd = (pgd_t *) PTBR + index; - pud = pud_offset(pgd, address); - pmd = pmd_offset(pud, address); - set_pmd(pmd, *pmd_k); - - pte_k = pte_offset_kernel(pmd_k, address); - if (!pte_present(*pte_k)) - goto no_context; - return; - } -} diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c deleted file mode 100644 index 8ce677d5575e..000000000000 --- a/arch/mn10300/mm/init.c +++ /dev/null @@ -1,136 +0,0 @@ -/* MN10300 Memory management initialisation - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -unsigned long highstart_pfn, highend_pfn; - -#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT -static struct vm_struct user_iomap_vm; -#endif - -/* - * set up paging - */ -void __init paging_init(void) -{ - unsigned long zones_size[MAX_NR_ZONES] = {0,}; - pte_t *ppte; - int loop; - - /* main kernel space -> RAM mapping is handled as 1:1 transparent by - * the MMU */ - memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); - memset(kernel_vmalloc_ptes, 0, sizeof(kernel_vmalloc_ptes)); - - /* load the VMALLOC area PTE table addresses into the kernel PGD */ - ppte = kernel_vmalloc_ptes; - for (loop = VMALLOC_START / (PAGE_SIZE * PTRS_PER_PTE); - loop < VMALLOC_END / (PAGE_SIZE * PTRS_PER_PTE); - loop++ - ) { - set_pgd(swapper_pg_dir + loop, __pgd(__pa(ppte) | _PAGE_TABLE)); - ppte += PAGE_SIZE / sizeof(pte_t); - } - - /* declare the sizes of the RAM zones (only use the normal zone) */ - zones_size[ZONE_NORMAL] = - contig_page_data.bdata->node_low_pfn - - contig_page_data.bdata->node_min_pfn; - - /* pass the memory from the bootmem allocator to the main allocator */ - free_area_init(zones_size); - -#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT - /* The Atomic Operation Unit registers need to be mapped to userspace - * for all processes. The following uses vm_area_register_early() to - * reserve the first page of the vmalloc area and sets the pte for that - * page. - * - * glibc hardcodes this virtual mapping, so we're pretty much stuck with - * it from now on. - */ - user_iomap_vm.flags = VM_USERMAP; - user_iomap_vm.size = 1 << PAGE_SHIFT; - vm_area_register_early(&user_iomap_vm, PAGE_SIZE); - ppte = kernel_vmalloc_ptes; - set_pte(ppte, pfn_pte(USER_ATOMIC_OPS_PAGE_ADDR >> PAGE_SHIFT, - PAGE_USERIO)); -#endif - - local_flush_tlb_all(); -} - -/* - * transfer all the memory from the bootmem allocator to the runtime allocator - */ -void __init mem_init(void) -{ - BUG_ON(!mem_map); - -#define START_PFN (contig_page_data.bdata->node_min_pfn) -#define MAX_LOW_PFN (contig_page_data.bdata->node_low_pfn) - - max_mapnr = MAX_LOW_PFN - START_PFN; - high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE); - - /* clear the zero-page */ - memset(empty_zero_page, 0, PAGE_SIZE); - - /* this will put all low memory onto the freelists */ - free_all_bootmem(); - - mem_init_print_info(NULL); -} - -/* - * recycle memory containing stuff only required for initialisation - */ -void free_initmem(void) -{ - free_initmem_default(POISON_FREE_INITMEM); -} - -/* - * dispose of the memory on which the initial ramdisk resided - */ -#ifdef CONFIG_BLK_DEV_INITRD -void free_initrd_mem(unsigned long start, unsigned long end) -{ - free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM, - "initrd"); -} -#endif diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c deleted file mode 100644 index 8ace89617c1c..000000000000 --- a/arch/mn10300/mm/misalignment.c +++ /dev/null @@ -1,966 +0,0 @@ -/* MN10300 Misalignment fixup handler - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if 0 -#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__) -#else -#define kdebug(FMT, ...) do {} while (0) -#endif - -static int misalignment_addr(unsigned long *registers, unsigned long sp, - unsigned params, unsigned opcode, - unsigned long disp, - void **_address, unsigned long **_postinc, - unsigned long *_inc); - -static int misalignment_reg(unsigned long *registers, unsigned params, - unsigned opcode, unsigned long disp, - unsigned long **_register); - -static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode); - -static const unsigned Dreg_index[] = { - REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2 -}; - -static const unsigned Areg_index[] = { - REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2 -}; - -static const unsigned Rreg_index[] = { - REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2, - REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2, - REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2, - REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2 -}; - -enum format_id { - FMT_S0, - FMT_S1, - FMT_S2, - FMT_S4, - FMT_D0, - FMT_D1, - FMT_D2, - FMT_D4, - FMT_D6, - FMT_D7, - FMT_D8, - FMT_D9, - FMT_D10, -}; - -static const struct { - u_int8_t opsz, dispsz; -} format_tbl[16] = { - [FMT_S0] = { 8, 0 }, - [FMT_S1] = { 8, 8 }, - [FMT_S2] = { 8, 16 }, - [FMT_S4] = { 8, 32 }, - [FMT_D0] = { 16, 0 }, - [FMT_D1] = { 16, 8 }, - [FMT_D2] = { 16, 16 }, - [FMT_D4] = { 16, 32 }, - [FMT_D6] = { 24, 0 }, - [FMT_D7] = { 24, 8 }, - [FMT_D8] = { 24, 24 }, - [FMT_D9] = { 24, 32 }, - [FMT_D10] = { 32, 0 }, -}; - -enum value_id { - DM0, /* data reg in opcode in bits 0-1 */ - DM1, /* data reg in opcode in bits 2-3 */ - DM2, /* data reg in opcode in bits 4-5 */ - AM0, /* addr reg in opcode in bits 0-1 */ - AM1, /* addr reg in opcode in bits 2-3 */ - AM2, /* addr reg in opcode in bits 4-5 */ - RM0, /* reg in opcode in bits 0-3 */ - RM1, /* reg in opcode in bits 2-5 */ - RM2, /* reg in opcode in bits 4-7 */ - RM4, /* reg in opcode in bits 8-11 */ - RM6, /* reg in opcode in bits 12-15 */ - - RD0, /* reg in displacement in bits 0-3 */ - RD2, /* reg in displacement in bits 4-7 */ - - SP, /* stack pointer */ - - SD8, /* 8-bit signed displacement */ - SD16, /* 16-bit signed displacement */ - SD24, /* 24-bit signed displacement */ - SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */ - SIMM8, /* 8-bit signed immediate */ - IMM8, /* 8-bit unsigned immediate */ - IMM16, /* 16-bit unsigned immediate */ - IMM24, /* 24-bit unsigned immediate */ - IMM32, /* 32-bit unsigned immediate */ - IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */ - - IMM32_MEM, /* 32-bit unsigned displacement */ - IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */ - - DN0 = DM0, - DN1 = DM1, - DN2 = DM2, - AN0 = AM0, - AN1 = AM1, - AN2 = AM2, - RN0 = RM0, - RN1 = RM1, - RN2 = RM2, - RN4 = RM4, - RN6 = RM6, - DI = DM1, - RI = RM2, - -}; - -struct mn10300_opcode { - const char name[8]; - u_int32_t opcode; - u_int32_t opmask; - unsigned exclusion; - - enum format_id format; - - unsigned cpu_mask; -#define AM33 330 - - unsigned params[2]; -#define MEM(ADDR) (0x80000000 | (ADDR)) -#define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2)) -#define MEMINC(ADDR) (0x81000000 | (ADDR)) -#define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC)) -}; - -/* LIBOPCODES EXCERPT - Assemble Matsushita MN10300 instructions. - Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public Licence as published by - the Free Software Foundation; either version 2 of the Licence, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public Licence for more details. - - You should have received a copy of the GNU General Public Licence - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -*/ -static const struct mn10300_opcode mn10300_opcodes[] = { -{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, -{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, -{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, -{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, -{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, -{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, -{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, -{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}}, -{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, -{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, -{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}}, -{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}}, -{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, -{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, -{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, -{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, -{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, -{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, -{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, -{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, -{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, -{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, -{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, -{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, -{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, -{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, -{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, -{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, -{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, -{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, -{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, -{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, -{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, -{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, -{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, -{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, -{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, -{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, -{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, -{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, -{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, -{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, -{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, -{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, -{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, -{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, -{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, -{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, -{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, -{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, -{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, -{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, -{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, -{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, -{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, -{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, -{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, -{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, -{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, -{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, -{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, -{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, -{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, -{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, - -{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, -{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, -{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, -{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, -{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, -{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, -{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, -{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, -{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, -{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, -{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, -{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, -{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, -{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, -{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, -{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, -{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, -{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, -{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, -{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, -{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, -{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, -{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, -{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, -{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, -{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, -{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, -{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, -{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, -{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, -{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, -{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, -{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, -{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, -{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, -{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, -{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, -{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, -{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, -{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, -{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, -{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, -{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, -{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, - -{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, - -{ "", 0, 0, 0, 0, 0, {0}}, -}; - -/* - * fix up misalignment problems where possible - */ -asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code) -{ - const struct exception_table_entry *fixup; - const struct mn10300_opcode *pop; - unsigned long *registers = (unsigned long *) regs; - unsigned long data, *store, *postinc, disp, inc, sp; - mm_segment_t seg; - siginfo_t info; - uint32_t opcode, noc, xo, xm; - uint8_t *pc, byte, datasz; - void *address; - unsigned tmp, npop, dispsz, loop; - - /* we don't fix up userspace misalignment faults */ - if (user_mode(regs)) - goto bus_error; - - sp = (unsigned long) regs + sizeof(*regs); - - kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp); - - if (regs->epsw & EPSW_IE) - asm volatile("or %0,epsw" : : "i"(EPSW_IE)); - - seg = get_fs(); - set_fs(KERNEL_DS); - - fixup = search_exception_tables(regs->pc); - - /* first thing to do is to match the opcode */ - pc = (u_int8_t *) regs->pc; - - if (__get_user(byte, pc) != 0) - goto fetch_error; - opcode = byte; - noc = 8; - - for (pop = mn10300_opcodes; pop->name[0]; pop++) { - npop = ilog2(pop->opcode | pop->opmask); - if (npop <= 0 || npop > 31) - continue; - npop = (npop + 8) & ~7; - - got_more_bits: - if (npop == noc) { - if ((opcode & pop->opmask) == pop->opcode) - goto found_opcode; - } else if (npop > noc) { - xo = pop->opcode >> (npop - noc); - xm = pop->opmask >> (npop - noc); - - if ((opcode & xm) != xo) - continue; - - /* we've got a partial match (an exact match on the - * first N bytes), so we need to get some more data */ - pc++; - if (__get_user(byte, pc) != 0) - goto fetch_error; - opcode = opcode << 8 | byte; - noc += 8; - goto got_more_bits; - } else { - /* there's already been a partial match as long as the - * complete match we're now considering, so this one - * should't match */ - continue; - } - } - - /* didn't manage to find a fixup */ - printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n", - regs->pc, opcode); - -failed: - set_fs(seg); - if (die_if_no_fixup("misalignment error", regs, code)) - return; - -bus_error: - info.si_signo = SIGBUS; - info.si_errno = 0; - info.si_code = BUS_ADRALN; - info.si_addr = (void *) regs->pc; - force_sig_info(SIGBUS, &info, current); - return; - - /* error reading opcodes */ -fetch_error: - printk(KERN_CRIT - "MISALIGN: %p: fault whilst reading instruction data\n", - pc); - goto failed; - -bad_addr_mode: - printk(KERN_CRIT - "MISALIGN: %lx: unsupported addressing mode %x\n", - regs->pc, opcode); - goto failed; - -bad_reg_mode: - printk(KERN_CRIT - "MISALIGN: %lx: unsupported register mode %x\n", - regs->pc, opcode); - goto failed; - -unsupported_instruction: - printk(KERN_CRIT - "MISALIGN: %lx: unsupported instruction %x (%s)\n", - regs->pc, opcode, pop->name); - goto failed; - -transfer_failed: - set_fs(seg); - if (fixup) { - regs->pc = fixup->fixup; - return; - } - if (die_if_no_fixup("misalignment fixup", regs, code)) - return; - - info.si_signo = SIGSEGV; - info.si_errno = 0; - info.si_code = SEGV_MAPERR; - info.si_addr = (void *) regs->pc; - force_sig_info(SIGSEGV, &info, current); - return; - - /* we matched the opcode */ -found_opcode: - kdebug("%lx: %x==%x { %x, %x }", - regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]); - - tmp = format_tbl[pop->format].opsz; - BUG_ON(tmp > noc); /* match was less complete than it ought to have been */ - - if (tmp < noc) { - tmp = noc - tmp; - opcode >>= tmp; - pc -= tmp >> 3; - } - - /* grab the extra displacement (note it's LSB first) */ - disp = 0; - dispsz = format_tbl[pop->format].dispsz; - for (loop = 0; loop < dispsz; loop += 8) { - pc++; - if (__get_user(byte, pc) != 0) - goto fetch_error; - disp |= byte << loop; - kdebug("{%p} disp[%02x]=%02x", pc, loop, byte); - } - - kdebug("disp=%lx", disp); - - set_fs(KERNEL_XDS); - if (fixup) - set_fs(seg); - - tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000; - if (!tmp) { - printk(KERN_CRIT - "MISALIGN: %lx: insn not move to/from memory %x\n", - regs->pc, opcode); - goto failed; - } - - /* determine the data transfer size of the move */ - if (pop->name[3] == 0 || /* "mov" */ - pop->name[4] == 'l') /* mov_lcc */ - inc = datasz = 4; - else if (pop->name[3] == 'h') /* movhu */ - inc = datasz = 2; - else - goto unsupported_instruction; - - if (pop->params[0] & 0x80000000) { - /* move memory to register */ - if (!misalignment_addr(registers, sp, - pop->params[0], opcode, disp, - &address, &postinc, &inc)) - goto bad_addr_mode; - - if (!misalignment_reg(registers, pop->params[1], opcode, disp, - &store)) - goto bad_reg_mode; - - kdebug("mov%u (%p),DARn", datasz, address); - if (copy_from_user(&data, (void *) address, datasz) != 0) - goto transfer_failed; - if (pop->params[0] & 0x1000000) { - kdebug("inc=%lx", inc); - *postinc += inc; - } - - *store = data; - kdebug("loaded %lx", data); - } else { - /* move register to memory */ - if (!misalignment_reg(registers, pop->params[0], opcode, disp, - &store)) - goto bad_reg_mode; - - if (!misalignment_addr(registers, sp, - pop->params[1], opcode, disp, - &address, &postinc, &inc)) - goto bad_addr_mode; - - data = *store; - - kdebug("mov%u %lx,(%p)", datasz, data, address); - if (copy_to_user((void *) address, &data, datasz) != 0) - goto transfer_failed; - if (pop->params[1] & 0x1000000) - *postinc += inc; - } - - tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz; - regs->pc += tmp >> 3; - - /* handle MOV_Lcc, which are currently the only FMT_D10 insns that - * access memory */ - if (pop->format == FMT_D10) - misalignment_MOV_Lcc(regs, opcode); - - set_fs(seg); -} - -/* - * determine the address that was being accessed - */ -static int misalignment_addr(unsigned long *registers, unsigned long sp, - unsigned params, unsigned opcode, - unsigned long disp, - void **_address, unsigned long **_postinc, - unsigned long *_inc) -{ - unsigned long *postinc = NULL, address = 0, tmp; - - if (!(params & 0x1000000)) { - kdebug("noinc"); - *_inc = 0; - _inc = NULL; - } - - params &= 0x00ffffff; - - do { - switch (params & 0xff) { - case DM0: - postinc = ®isters[Dreg_index[opcode & 0x03]]; - address += *postinc; - break; - case DM1: - postinc = ®isters[Dreg_index[opcode >> 2 & 0x03]]; - address += *postinc; - break; - case DM2: - postinc = ®isters[Dreg_index[opcode >> 4 & 0x03]]; - address += *postinc; - break; - case AM0: - postinc = ®isters[Areg_index[opcode & 0x03]]; - address += *postinc; - break; - case AM1: - postinc = ®isters[Areg_index[opcode >> 2 & 0x03]]; - address += *postinc; - break; - case AM2: - postinc = ®isters[Areg_index[opcode >> 4 & 0x03]]; - address += *postinc; - break; - case RM0: - postinc = ®isters[Rreg_index[opcode & 0x0f]]; - address += *postinc; - break; - case RM1: - postinc = ®isters[Rreg_index[opcode >> 2 & 0x0f]]; - address += *postinc; - break; - case RM2: - postinc = ®isters[Rreg_index[opcode >> 4 & 0x0f]]; - address += *postinc; - break; - case RM4: - postinc = ®isters[Rreg_index[opcode >> 8 & 0x0f]]; - address += *postinc; - break; - case RM6: - postinc = ®isters[Rreg_index[opcode >> 12 & 0x0f]]; - address += *postinc; - break; - case RD0: - postinc = ®isters[Rreg_index[disp & 0x0f]]; - address += *postinc; - break; - case RD2: - postinc = ®isters[Rreg_index[disp >> 4 & 0x0f]]; - address += *postinc; - break; - case SP: - address += sp; - break; - - /* displacements are either to be added to the address - * before use, or, in the case of post-inc addressing, - * to be added into the base register after use */ - case SD8: - case SIMM8: - disp = (long) (int8_t) (disp & 0xff); - goto displace_or_inc; - case SD16: - disp = (long) (int16_t) (disp & 0xffff); - goto displace_or_inc; - case SD24: - tmp = disp << 8; - asm("asr 8,%0" : "=r"(tmp) : "0"(tmp) : "cc"); - disp = (long) tmp; - goto displace_or_inc; - case SIMM4_2: - tmp = opcode >> 4 & 0x0f; - tmp <<= 28; - asm("asr 28,%0" : "=r"(tmp) : "0"(tmp) : "cc"); - disp = (long) tmp; - goto displace_or_inc; - case IMM8: - disp &= 0x000000ff; - goto displace_or_inc; - case IMM16: - disp &= 0x0000ffff; - goto displace_or_inc; - case IMM24: - disp &= 0x00ffffff; - goto displace_or_inc; - case IMM32: - case IMM32_MEM: - case IMM32_HIGH8: - case IMM32_HIGH8_MEM: - displace_or_inc: - kdebug("%s %lx", _inc ? "incr" : "disp", disp); - if (!_inc) - address += disp; - else - *_inc = disp; - break; - default: - BUG(); - return 0; - } - } while ((params >>= 8)); - - *_address = (void *) address; - *_postinc = postinc; - return 1; -} - -/* - * determine the register that is acting as source/dest - */ -static int misalignment_reg(unsigned long *registers, unsigned params, - unsigned opcode, unsigned long disp, - unsigned long **_register) -{ - params &= 0x7fffffff; - - if (params & 0xffffff00) - return 0; - - switch (params & 0xff) { - case DM0: - *_register = ®isters[Dreg_index[opcode & 0x03]]; - break; - case DM1: - *_register = ®isters[Dreg_index[opcode >> 2 & 0x03]]; - break; - case DM2: - *_register = ®isters[Dreg_index[opcode >> 4 & 0x03]]; - break; - case AM0: - *_register = ®isters[Areg_index[opcode & 0x03]]; - break; - case AM1: - *_register = ®isters[Areg_index[opcode >> 2 & 0x03]]; - break; - case AM2: - *_register = ®isters[Areg_index[opcode >> 4 & 0x03]]; - break; - case RM0: - *_register = ®isters[Rreg_index[opcode & 0x0f]]; - break; - case RM1: - *_register = ®isters[Rreg_index[opcode >> 2 & 0x0f]]; - break; - case RM2: - *_register = ®isters[Rreg_index[opcode >> 4 & 0x0f]]; - break; - case RM4: - *_register = ®isters[Rreg_index[opcode >> 8 & 0x0f]]; - break; - case RM6: - *_register = ®isters[Rreg_index[opcode >> 12 & 0x0f]]; - break; - case RD0: - *_register = ®isters[Rreg_index[disp & 0x0f]]; - break; - case RD2: - *_register = ®isters[Rreg_index[disp >> 4 & 0x0f]]; - break; - case SP: - *_register = ®isters[REG_SP >> 2]; - break; - - default: - BUG(); - return 0; - } - - return 1; -} - -/* - * handle the conditional loop part of the move-and-loop instructions - */ -static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode) -{ - unsigned long epsw = regs->epsw; - unsigned long NxorV; - - kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf); - - /* calculate N^V and shift onto the same bit position as Z */ - NxorV = ((epsw >> 3) ^ epsw >> 1) & 1; - - switch (opcode & 0xf) { - case 0x0: /* MOV_LLT: N^V */ - if (NxorV) - goto take_the_loop; - return; - case 0x1: /* MOV_LGT: ~(Z or (N^V))*/ - if (!((epsw & EPSW_FLAG_Z) | NxorV)) - goto take_the_loop; - return; - case 0x2: /* MOV_LGE: ~(N^V) */ - if (!NxorV) - goto take_the_loop; - return; - case 0x3: /* MOV_LLE: Z or (N^V) */ - if ((epsw & EPSW_FLAG_Z) | NxorV) - goto take_the_loop; - return; - - case 0x4: /* MOV_LCS: C */ - if (epsw & EPSW_FLAG_C) - goto take_the_loop; - return; - case 0x5: /* MOV_LHI: ~(C or Z) */ - if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))) - goto take_the_loop; - return; - case 0x6: /* MOV_LCC: ~C */ - if (!(epsw & EPSW_FLAG_C)) - goto take_the_loop; - return; - case 0x7: /* MOV_LLS: C or Z */ - if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)) - goto take_the_loop; - return; - - case 0x8: /* MOV_LEQ: Z */ - if (epsw & EPSW_FLAG_Z) - goto take_the_loop; - return; - case 0x9: /* MOV_LNE: ~Z */ - if (!(epsw & EPSW_FLAG_Z)) - goto take_the_loop; - return; - case 0xa: /* MOV_LRA: always */ - goto take_the_loop; - - default: - BUG(); - } - -take_the_loop: - /* wind the PC back to just after the SETLB insn */ - kdebug("loop LAR=%lx", regs->lar); - regs->pc = regs->lar - 4; -} - -/* - * misalignment handler tests - */ -#ifdef CONFIG_TEST_MISALIGNMENT_HANDLER -static u8 __initdata testbuf[512] __attribute__((aligned(16))) = { - [257] = 0x11, - [258] = 0x22, - [259] = 0x33, - [260] = 0x44, -}; - -#define ASSERTCMP(X, OP, Y) \ -do { \ - if (unlikely(!((X) OP (Y)))) { \ - printk(KERN_ERR "\n"); \ - printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \ - __LINE__); \ - printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \ - (unsigned long)(X), (unsigned long)(Y)); \ - BUG(); \ - } \ -} while(0) - -static int __init test_misalignment(void) -{ - register void *r asm("e0"); - register u32 y asm("e1"); - void *p = testbuf, *q; - u32 tmp, tmp2, x; - - printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p); - p++; - - printk(KERN_NOTICE "___ MOV (Am),Dn ___\n"); - q = p + 256; - asm volatile("mov (%0),%1" : "+a"(q), "=d"(x)); - ASSERTCMP(q, ==, p + 256); - ASSERTCMP(x, ==, 0x44332211); - - printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n"); - q = p; - asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x)); - ASSERTCMP(q, ==, p); - ASSERTCMP(x, ==, 0x44332211); - - printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n"); - tmp = 256; - q = p; - asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp)); - ASSERTCMP(q, ==, p); - ASSERTCMP(x, ==, 0x44332211); - ASSERTCMP(tmp, ==, 256); - - printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n"); - r = p; - asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y)); - ASSERTCMP(r, ==, p); - ASSERTCMP(y, ==, 0x44332211); - - printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n"); - r = p + 256; - asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y)); - ASSERTCMP(r, ==, p + 256 + 4); - ASSERTCMP(y, ==, 0x44332211); - - printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n"); - r = p + 256; - asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y)); - ASSERTCMP(r, ==, p + 256 + 8); - ASSERTCMP(y, ==, 0x44332211); - - printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n"); - asm volatile( - "add -16,sp \n" - "mov +0x11,%0 \n" - "movbu %0,(7,sp) \n" - "mov +0x22,%0 \n" - "movbu %0,(8,sp) \n" - "mov +0x33,%0 \n" - "movbu %0,(9,sp) \n" - "mov +0x44,%0 \n" - "movbu %0,(10,sp) \n" - "mov (7,sp),%1 \n" - "add +16,sp \n" - : "+a"(q), "=d"(x)); - ASSERTCMP(x, ==, 0x44332211); - - printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n"); - asm volatile( - "add -264,sp \n" - "mov +0x11,%0 \n" - "movbu %0,(259,sp) \n" - "mov +0x22,%0 \n" - "movbu %0,(260,sp) \n" - "mov +0x33,%0 \n" - "movbu %0,(261,sp) \n" - "mov +0x55,%0 \n" - "movbu %0,(262,sp) \n" - "mov (259,sp),%1 \n" - "add +264,sp \n" - : "+d"(tmp), "=d"(x)); - ASSERTCMP(x, ==, 0x55332211); - - printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n"); - asm volatile( - "add -264,sp \n" - "mov +0x11,%0 \n" - "movbu %0,(260,sp) \n" - "mov +0x22,%0 \n" - "movbu %0,(261,sp) \n" - "mov +0x33,%0 \n" - "movbu %0,(262,sp) \n" - "mov +0x55,%0 \n" - "movbu %0,(263,sp) \n" - "mov (260,sp),%1 \n" - "add +264,sp \n" - : "+d"(tmp), "=d"(x)); - ASSERTCMP(x, ==, 0x55332211); - - - printk(KERN_NOTICE "___ MOV_LNE ___\n"); - tmp = 1; - tmp2 = 2; - q = p + 256; - asm volatile( - "setlb \n" - "mov %2,%3 \n" - "mov %1,%2 \n" - "cmp +0,%1 \n" - "mov_lne (%0+,4),%1" - : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x) - : - : "cc"); - ASSERTCMP(q, ==, p + 256 + 12); - ASSERTCMP(x, ==, 0x44332211); - - printk(KERN_NOTICE "___ MOV in SETLB ___\n"); - tmp = 1; - tmp2 = 2; - q = p + 256; - asm volatile( - "setlb \n" - "mov %1,%3 \n" - "mov (%0+),%1 \n" - "cmp +0,%1 \n" - "lne " - : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x) - : - : "cc"); - - ASSERTCMP(q, ==, p + 256 + 8); - ASSERTCMP(x, ==, 0x44332211); - - printk(KERN_NOTICE "<==test_misalignment()\n"); - return 0; -} - -arch_initcall(test_misalignment); - -#endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */ diff --git a/arch/mn10300/mm/mmu-context.c b/arch/mn10300/mm/mmu-context.c deleted file mode 100644 index a4f7d3dcc6e6..000000000000 --- a/arch/mn10300/mm/mmu-context.c +++ /dev/null @@ -1,62 +0,0 @@ -/* MN10300 MMU context allocation and management - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include - -#ifdef CONFIG_MN10300_TLB_USE_PIDR -/* - * list of the MMU contexts last allocated on each CPU - */ -unsigned long mmu_context_cache[NR_CPUS] = { - [0 ... NR_CPUS - 1] = - MMU_CONTEXT_FIRST_VERSION * 2 - (1 - MMU_CONTEXT_TLBPID_LOCK_NR), -}; -#endif /* CONFIG_MN10300_TLB_USE_PIDR */ - -/* - * preemptively set a TLB entry - */ -void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) -{ - unsigned long pteu, ptel, cnx, flags; - pte_t pte = *ptep; - - addr &= PAGE_MASK; - ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2); - - /* make sure the context doesn't migrate and defend against - * interference from vmalloc'd regions */ - local_irq_save(flags); - - cnx = ~MMU_NO_CONTEXT; -#ifdef CONFIG_MN10300_TLB_USE_PIDR - cnx = mm_context(vma->vm_mm); -#endif - - if (cnx != MMU_NO_CONTEXT) { - pteu = addr; -#ifdef CONFIG_MN10300_TLB_USE_PIDR - pteu |= cnx & MMU_CONTEXT_TLBPID_MASK; -#endif - if (!(pte_val(pte) & _PAGE_NX)) { - IPTEU = pteu; - if (IPTEL & xPTEL_V) - IPTEL = ptel; - } - DPTEU = pteu; - if (DPTEL & xPTEL_V) - DPTEL = ptel; - } - - local_irq_restore(flags); -} diff --git a/arch/mn10300/mm/pgtable.c b/arch/mn10300/mm/pgtable.c deleted file mode 100644 index 9577cf768875..000000000000 --- a/arch/mn10300/mm/pgtable.c +++ /dev/null @@ -1,174 +0,0 @@ -/* MN10300 Page table management - * - * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Modified by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * Associate a large virtual page frame with a given physical page frame - * and protection flags for that frame. pfn is for the base of the page, - * vaddr is what the page gets mapped to - both must be properly aligned. - * The pmd must already be instantiated. Assumes PAE mode. - */ -void set_pmd_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags) -{ - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - - if (vaddr & (PMD_SIZE-1)) { /* vaddr is misaligned */ - printk(KERN_ERR "set_pmd_pfn: vaddr misaligned\n"); - return; /* BUG(); */ - } - if (pfn & (PTRS_PER_PTE-1)) { /* pfn is misaligned */ - printk(KERN_ERR "set_pmd_pfn: pfn misaligned\n"); - return; /* BUG(); */ - } - pgd = swapper_pg_dir + pgd_index(vaddr); - if (pgd_none(*pgd)) { - printk(KERN_ERR "set_pmd_pfn: pgd_none\n"); - return; /* BUG(); */ - } - pud = pud_offset(pgd, vaddr); - pmd = pmd_offset(pud, vaddr); - set_pmd(pmd, pfn_pmd(pfn, flags)); - /* - * It's enough to flush this one mapping. - * (PGE mappings get flushed as well) - */ - local_flush_tlb_one(vaddr); -} - -pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL); - if (pte) - clear_page(pte); - return pte; -} - -struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) -{ - struct page *pte; - -#ifdef CONFIG_HIGHPTE - pte = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM, 0); -#else - pte = alloc_pages(GFP_KERNEL, 0); -#endif - if (!pte) - return NULL; - clear_highpage(pte); - if (!pgtable_page_ctor(pte)) { - __free_page(pte); - return NULL; - } - return pte; -} - -/* - * List of all pgd's needed for non-PAE so it can invalidate entries - * in both cached and uncached pgd's; not needed for PAE since the - * kernel pmd is shared. If PAE were not to share the pmd a similar - * tactic would be needed. This is essentially codepath-based locking - * against pageattr.c; it is the unique case in which a valid change - * of kernel pagetables can't be lazily synchronized by vmalloc faults. - * vmalloc faults work because attached pagetables are never freed. - * If the locking proves to be non-performant, a ticketing scheme with - * checks at dup_mmap(), exec(), and other mmlist addition points - * could be used. The locking scheme was chosen on the basis of - * manfred's recommendations and having no core impact whatsoever. - * -- nyc - */ -DEFINE_SPINLOCK(pgd_lock); -struct page *pgd_list; - -static inline void pgd_list_add(pgd_t *pgd) -{ - struct page *page = virt_to_page(pgd); - page->index = (unsigned long) pgd_list; - if (pgd_list) - set_page_private(pgd_list, (unsigned long) &page->index); - pgd_list = page; - set_page_private(page, (unsigned long) &pgd_list); -} - -static inline void pgd_list_del(pgd_t *pgd) -{ - struct page *next, **pprev, *page = virt_to_page(pgd); - next = (struct page *) page->index; - pprev = (struct page **) page_private(page); - *pprev = next; - if (next) - set_page_private(next, (unsigned long) pprev); -} - -void pgd_ctor(void *pgd) -{ - unsigned long flags; - - if (PTRS_PER_PMD == 1) - spin_lock_irqsave(&pgd_lock, flags); - - memcpy((pgd_t *)pgd + USER_PTRS_PER_PGD, - swapper_pg_dir + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - - if (PTRS_PER_PMD > 1) - return; - - pgd_list_add(pgd); - spin_unlock_irqrestore(&pgd_lock, flags); - memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); -} - -/* never called when PTRS_PER_PMD > 1 */ -void pgd_dtor(void *pgd) -{ - unsigned long flags; /* can be called from interrupt context */ - - spin_lock_irqsave(&pgd_lock, flags); - pgd_list_del(pgd); - spin_unlock_irqrestore(&pgd_lock, flags); -} - -pgd_t *pgd_alloc(struct mm_struct *mm) -{ - return quicklist_alloc(0, GFP_KERNEL, pgd_ctor); -} - -void pgd_free(struct mm_struct *mm, pgd_t *pgd) -{ - quicklist_free(0, pgd_dtor, pgd); -} - -void __init pgtable_cache_init(void) -{ -} - -void check_pgt_cache(void) -{ - quicklist_trim(0, pgd_dtor, 25, 16); -} diff --git a/arch/mn10300/mm/tlb-mn10300.S b/arch/mn10300/mm/tlb-mn10300.S deleted file mode 100644 index b9940177d81b..000000000000 --- a/arch/mn10300/mm/tlb-mn10300.S +++ /dev/null @@ -1,220 +0,0 @@ -############################################################################### -# -# TLB loading functions -# -# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. -# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. -# Modified by David Howells (dhowells@redhat.com) -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public Licence -# as published by the Free Software Foundation; either version -# 2 of the Licence, or (at your option) any later version. -# -############################################################################### -#include -#include -#include -#include -#include -#include -#include - -############################################################################### -# -# Instruction TLB Miss handler entry point -# -############################################################################### - .type itlb_miss,@function -ENTRY(itlb_miss) -#ifdef CONFIG_GDBSTUB - movm [d2,d3,a2],(sp) -#else - or EPSW_nAR,epsw # switch D0-D3 & A0-A3 to the alternate - # register bank - nop - nop - nop -#endif - -#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR) - mov (MMUCTR),d2 - mov d2,(MMUCTR) -#endif - - and ~EPSW_NMID,epsw - mov (IPTEU),d3 - mov (PTBR),a2 - mov d3,d2 - and 0xffc00000,d2 - lsr 20,d2 - mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22] - btst _PAGE_VALID,a2 - beq itlb_miss_fault # jump if doesn't point anywhere - - and ~(PAGE_SIZE-1),a2 - mov d3,d2 - and 0x003ff000,d2 - lsr 10,d2 - add d2,a2 - mov (a2),d2 # get pte from PTD[addr 21..12] - btst _PAGE_VALID,d2 - beq itlb_miss_fault # jump if doesn't point to a page - # (might be a swap id) -#if ((_PAGE_ACCESSED & 0xffffff00) == 0) - bset _PAGE_ACCESSED,(0,a2) -#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0) - bset +(_PAGE_ACCESSED >> 8),(1,a2) -#else -#error "_PAGE_ACCESSED value is out of range" -#endif - and ~xPTEL2_UNUSED1,d2 -itlb_miss_set: - mov d2,(IPTEL2) # change the TLB -#ifdef CONFIG_GDBSTUB - movm (sp),[d2,d3,a2] -#endif - rti - -itlb_miss_fault: - mov _PAGE_VALID,d2 # force address error handler to be - # invoked - bra itlb_miss_set - - .size itlb_miss, . - itlb_miss - -############################################################################### -# -# Data TLB Miss handler entry point -# -############################################################################### - .type dtlb_miss,@function -ENTRY(dtlb_miss) -#ifdef CONFIG_GDBSTUB - movm [d2,d3,a2],(sp) -#else - or EPSW_nAR,epsw # switch D0-D3 & A0-A3 to the alternate - # register bank - nop - nop - nop -#endif - -#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR) - mov (MMUCTR),d2 - mov d2,(MMUCTR) -#endif - - and ~EPSW_NMID,epsw - mov (DPTEU),d3 - mov (PTBR),a2 - mov d3,d2 - and 0xffc00000,d2 - lsr 20,d2 - mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22] - btst _PAGE_VALID,a2 - beq dtlb_miss_fault # jump if doesn't point anywhere - - and ~(PAGE_SIZE-1),a2 - mov d3,d2 - and 0x003ff000,d2 - lsr 10,d2 - add d2,a2 - mov (a2),d2 # get pte from PTD[addr 21..12] - btst _PAGE_VALID,d2 - beq dtlb_miss_fault # jump if doesn't point to a page - # (might be a swap id) -#if ((_PAGE_ACCESSED & 0xffffff00) == 0) - bset _PAGE_ACCESSED,(0,a2) -#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0) - bset +(_PAGE_ACCESSED >> 8),(1,a2) -#else -#error "_PAGE_ACCESSED value is out of range" -#endif - and ~xPTEL2_UNUSED1,d2 -dtlb_miss_set: - mov d2,(DPTEL2) # change the TLB -#ifdef CONFIG_GDBSTUB - movm (sp),[d2,d3,a2] -#endif - rti - -dtlb_miss_fault: - mov _PAGE_VALID,d2 # force address error handler to be - # invoked - bra dtlb_miss_set - .size dtlb_miss, . - dtlb_miss - -############################################################################### -# -# Instruction TLB Address Error handler entry point -# -############################################################################### - .type itlb_aerror,@function -ENTRY(itlb_aerror) - add -4,sp - SAVE_ALL - -#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR) - mov (MMUCTR),d1 - mov d1,(MMUCTR) -#endif - - and ~EPSW_NMID,epsw - add -4,sp # need to pass three params - - # calculate the fault code - movhu (MMUFCR_IFC),d1 - or 0x00010000,d1 # it's an instruction fetch - - # determine the page address - mov (IPTEU),d0 - and PAGE_MASK,d0 - mov d0,(12,sp) - - clr d0 - mov d0,(IPTEL2) - - or EPSW_IE,epsw - mov fp,d0 - call do_page_fault[],0 # do_page_fault(regs,code,addr - - jmp ret_from_exception - .size itlb_aerror, . - itlb_aerror - -############################################################################### -# -# Data TLB Address Error handler entry point -# -############################################################################### - .type dtlb_aerror,@function -ENTRY(dtlb_aerror) - add -4,sp - SAVE_ALL - -#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR) - mov (MMUCTR),d1 - mov d1,(MMUCTR) -#endif - - add -4,sp # need to pass three params - and ~EPSW_NMID,epsw - - # calculate the fault code - movhu (MMUFCR_DFC),d1 - - # determine the page address - mov (DPTEU),a2 - mov a2,d0 - and PAGE_MASK,d0 - mov d0,(12,sp) - - clr d0 - mov d0,(DPTEL2) - - or EPSW_IE,epsw - mov fp,d0 - call do_page_fault[],0 # do_page_fault(regs,code,addr - - jmp ret_from_exception - .size dtlb_aerror, . - dtlb_aerror diff --git a/arch/mn10300/mm/tlb-smp.c b/arch/mn10300/mm/tlb-smp.c deleted file mode 100644 index 085f2bb691ac..000000000000 --- a/arch/mn10300/mm/tlb-smp.c +++ /dev/null @@ -1,213 +0,0 @@ -/* SMP TLB support routines. - * - * Copyright (C) 2006-2008 Panasonic Corporation - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * For flush TLB - */ -#define FLUSH_ALL 0xffffffff - -static cpumask_t flush_cpumask; -static struct mm_struct *flush_mm; -static unsigned long flush_va; -static DEFINE_SPINLOCK(tlbstate_lock); - -DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { - &init_mm, 0 -}; - -static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, - unsigned long va); -static void do_flush_tlb_all(void *info); - -/** - * smp_flush_tlb - Callback to invalidate the TLB. - * @unused: Callback context (ignored). - */ -void smp_flush_tlb(void *unused) -{ - unsigned long cpu_id; - - cpu_id = get_cpu(); - - if (!cpumask_test_cpu(cpu_id, &flush_cpumask)) - /* This was a BUG() but until someone can quote me the line - * from the intel manual that guarantees an IPI to multiple - * CPUs is retried _only_ on the erroring CPUs its staying as a - * return - * - * BUG(); - */ - goto out; - - if (flush_va == FLUSH_ALL) - local_flush_tlb(); - else - local_flush_tlb_page(flush_mm, flush_va); - - smp_mb__before_atomic(); - cpumask_clear_cpu(cpu_id, &flush_cpumask); - smp_mb__after_atomic(); -out: - put_cpu(); -} - -/** - * flush_tlb_others - Tell the specified CPUs to invalidate their TLBs - * @cpumask: The list of CPUs to target. - * @mm: The VM context to flush from (if va!=FLUSH_ALL). - * @va: Virtual address to flush or FLUSH_ALL to flush everything. - */ -static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, - unsigned long va) -{ - cpumask_t tmp; - - /* A couple of sanity checks (to be removed): - * - mask must not be empty - * - current CPU must not be in mask - * - we do not send IPIs to as-yet unbooted CPUs. - */ - BUG_ON(!mm); - BUG_ON(cpumask_empty(&cpumask)); - BUG_ON(cpumask_test_cpu(smp_processor_id(), &cpumask)); - - cpumask_and(&tmp, &cpumask, cpu_online_mask); - BUG_ON(!cpumask_equal(&cpumask, &tmp)); - - /* I'm not happy about this global shared spinlock in the MM hot path, - * but we'll see how contended it is. - * - * Temporarily this turns IRQs off, so that lockups are detected by the - * NMI watchdog. - */ - spin_lock(&tlbstate_lock); - - flush_mm = mm; - flush_va = va; -#if NR_CPUS <= BITS_PER_LONG - atomic_or(cpumask.bits[0], (atomic_t *)&flush_cpumask.bits[0]); -#else -#error Not supported. -#endif - - /* FIXME: if NR_CPUS>=3, change send_IPI_mask */ - smp_call_function(smp_flush_tlb, NULL, 1); - - while (!cpumask_empty(&flush_cpumask)) - /* Lockup detection does not belong here */ - smp_mb(); - - flush_mm = NULL; - flush_va = 0; - spin_unlock(&tlbstate_lock); -} - -/** - * flush_tlb_mm - Invalidate TLB of specified VM context - * @mm: The VM context to invalidate. - */ -void flush_tlb_mm(struct mm_struct *mm) -{ - cpumask_t cpu_mask; - - preempt_disable(); - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - - local_flush_tlb(); - if (!cpumask_empty(&cpu_mask)) - flush_tlb_others(cpu_mask, mm, FLUSH_ALL); - - preempt_enable(); -} - -/** - * flush_tlb_current_task - Invalidate TLB of current task - */ -void flush_tlb_current_task(void) -{ - struct mm_struct *mm = current->mm; - cpumask_t cpu_mask; - - preempt_disable(); - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - - local_flush_tlb(); - if (!cpumask_empty(&cpu_mask)) - flush_tlb_others(cpu_mask, mm, FLUSH_ALL); - - preempt_enable(); -} - -/** - * flush_tlb_page - Invalidate TLB of page - * @vma: The VM context to invalidate the page for. - * @va: The virtual address of the page to invalidate. - */ -void flush_tlb_page(struct vm_area_struct *vma, unsigned long va) -{ - struct mm_struct *mm = vma->vm_mm; - cpumask_t cpu_mask; - - preempt_disable(); - cpumask_copy(&cpu_mask, mm_cpumask(mm)); - cpumask_clear_cpu(smp_processor_id(), &cpu_mask); - - local_flush_tlb_page(mm, va); - if (!cpumask_empty(&cpu_mask)) - flush_tlb_others(cpu_mask, mm, va); - - preempt_enable(); -} - -/** - * do_flush_tlb_all - Callback to completely invalidate a TLB - * @unused: Callback context (ignored). - */ -static void do_flush_tlb_all(void *unused) -{ - local_flush_tlb_all(); -} - -/** - * flush_tlb_all - Completely invalidate TLBs on all CPUs - */ -void flush_tlb_all(void) -{ - on_each_cpu(do_flush_tlb_all, 0, 1); -} diff --git a/arch/mn10300/oprofile/Makefile b/arch/mn10300/oprofile/Makefile deleted file mode 100644 index 9fa95aaf496b..000000000000 --- a/arch/mn10300/oprofile/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the MN10300-specific profiling code -# -obj-$(CONFIG_OPROFILE) += oprofile.o - -DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \ - oprof.o cpu_buffer.o buffer_sync.o \ - event_buffer.o oprofile_files.o \ - oprofilefs.o oprofile_stats.o \ - timer_int.o ) - -oprofile-y := $(DRIVER_OBJS) op_model_null.o - diff --git a/arch/mn10300/oprofile/op_model_null.c b/arch/mn10300/oprofile/op_model_null.c deleted file mode 100644 index cd4ab374bc4f..000000000000 --- a/arch/mn10300/oprofile/op_model_null.c +++ /dev/null @@ -1,22 +0,0 @@ -/* Null profiling driver - * - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * Licence. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include - -int __init oprofile_arch_init(struct oprofile_operations *ops) -{ - return -ENODEV; -} - -void oprofile_arch_exit(void) -{ -} - diff --git a/arch/mn10300/proc-mn103e010/Makefile b/arch/mn10300/proc-mn103e010/Makefile deleted file mode 100644 index ac2c9784cd21..000000000000 --- a/arch/mn10300/proc-mn103e010/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the MN103E010 processor chip specific code -# -obj-y := proc-init.o - diff --git a/arch/mn10300/proc-mn103e010/include/proc/cache.h b/arch/mn10300/proc-mn103e010/include/proc/cache.h deleted file mode 100644 index 967d144f307e..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/cache.h +++ /dev/null @@ -1,43 +0,0 @@ -/* MN103E010 Cache specification - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CACHE_H -#define _ASM_PROC_CACHE_H - -/* L1 cache */ - -#define L1_CACHE_NWAYS 4 /* number of ways in caches */ -#define L1_CACHE_NENTRIES 256 /* number of entries in each way */ -#define L1_CACHE_BYTES 16 /* bytes per entry */ -#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */ -#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */ - -#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ -#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ -#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ -#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ -#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) - -/* - * specification of the interval between interrupt checking intervals whilst - * managing the cache with the interrupts disabled - */ -#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 - -/* - * The size of range at which it becomes more economical to just flush the - * whole cache rather than trying to flush the specified range. - */ -#define MN10300_DCACHE_FLUSH_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) -#define MN10300_DCACHE_FLUSH_INV_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) - -#endif /* _ASM_PROC_CACHE_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/clock.h b/arch/mn10300/proc-mn103e010/include/proc/clock.h deleted file mode 100644 index 704a819f1f4b..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/clock.h +++ /dev/null @@ -1,16 +0,0 @@ -/* MN103E010-specific clocks - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CLOCK_H -#define _ASM_PROC_CLOCK_H - -#include - -#endif /* _ASM_PROC_CLOCK_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h deleted file mode 100644 index d72d328d1f9c..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h +++ /dev/null @@ -1,102 +0,0 @@ -/* MN103E010 on-board DMA controller registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_DMACTL_REGS_H -#define _ASM_PROC_DMACTL_REGS_H - -#include - -#ifdef __KERNEL__ - -/* DMA registers */ -#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */ -#define DMxCTR_BG 0x0000001f /* transfer request source */ -#define DMxCTR_BG_SOFT 0x00000000 /* - software source */ -#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */ -#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */ -#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */ -#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */ -#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */ -#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */ -#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */ -#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */ -#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */ -#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */ -#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */ -#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */ -#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */ -#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */ -#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */ -#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */ -#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */ -#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */ -#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */ -#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */ -#define DMxCTR_SAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */ -#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */ -#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */ -#define DMxCTR_DAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */ -#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */ -#define DMxCTR_TM 0x00001800 /* DMA transfer mode */ -#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */ -#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */ -#define DMxCTR_UT 0x00006000 /* DMA transfer unit */ -#define DMxCTR_UT_1 0x00000000 /* - 1 byte */ -#define DMxCTR_UT_2 0x00002000 /* - 2 byte */ -#define DMxCTR_UT_4 0x00004000 /* - 4 byte */ -#define DMxCTR_UT_16 0x00006000 /* - 16 byte */ -#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */ -#define DMxCTR_RQM 0x00060000 /* external request input source mode */ -#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */ -#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */ -#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */ -#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */ -#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */ -#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */ - -#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */ - -#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */ - -#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */ -#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */ - -#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent - * size reg */ -#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */ - -#define DM0IRQ 16 /* DMA channel 0 complete IRQ */ -#define DM1IRQ 17 /* DMA channel 1 complete IRQ */ -#define DM2IRQ 18 /* DMA channel 2 complete IRQ */ -#define DM3IRQ 19 /* DMA channel 3 complete IRQ */ - -#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */ -#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */ -#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */ -#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */ - -#ifndef __ASSEMBLY__ - -struct mn10300_dmactl_regs { - u32 ctr; - const void *src; - void *dst; - u32 siz; - u32 cyc; -} __attribute__((aligned(0x100))); - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PROC_DMACTL_REGS_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h b/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h deleted file mode 100644 index 516afe824055..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_PROC_INTCTL_REGS_H -#define _ASM_PROC_INTCTL_REGS_H - -#ifndef _ASM_INTCTL_REGS_H -# error "please don't include this file directly" -#endif - -/* intr acceptance group reg */ -#define IAGR __SYSREG(0xd4000100, u16) - -/* group number register */ -#define IAGR_GN 0x00fc - -#define __GET_XIRQ_TRIGGER(X, Z) (((Z) >> ((X) * 2)) & 3) - -#define __SET_XIRQ_TRIGGER(X, Y, Z) \ -({ \ - typeof(Z) x = (Z); \ - x &= ~(3 << ((X) * 2)); \ - x |= ((Y) & 3) << ((X) * 2); \ - (Z) = x; \ -}) - -/* external pin intr spec reg */ -#define EXTMD __SYSREG(0xd4000200, u16) -#define GET_XIRQ_TRIGGER(X) __GET_XIRQ_TRIGGER(X, EXTMD) -#define SET_XIRQ_TRIGGER(X, Y) __SET_XIRQ_TRIGGER(X, Y, EXTMD) - -#endif /* _ASM_PROC_INTCTL_REGS_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/irq.h b/arch/mn10300/proc-mn103e010/include/proc/irq.h deleted file mode 100644 index aa6ee8f98b1b..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/irq.h +++ /dev/null @@ -1,34 +0,0 @@ -/* MN103E010 On-board interrupt controller numbers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_IRQ_H -#define _ASM_PROC_IRQ_H - -#ifdef __KERNEL__ - -#define GxICR_NUM_IRQS 42 - -#define GxICR_NUM_XIRQS 8 - -#define XIRQ0 34 -#define XIRQ1 35 -#define XIRQ2 36 -#define XIRQ3 37 -#define XIRQ4 38 -#define XIRQ5 39 -#define XIRQ6 40 -#define XIRQ7 41 - -#define XIRQ2IRQ(num) (XIRQ0 + num) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PROC_IRQ_H */ diff --git a/arch/mn10300/proc-mn103e010/include/proc/proc.h b/arch/mn10300/proc-mn103e010/include/proc/proc.h deleted file mode 100644 index 39c4f8e7d2d3..000000000000 --- a/arch/mn10300/proc-mn103e010/include/proc/proc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* MN103E010 Processor description - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_PROC_H -#define _ASM_PROC_PROC_H - -#define PROCESSOR_VENDOR_NAME "Panasonic" -#define PROCESSOR_MODEL_NAME "mn103e010" - -#endif /* _ASM_PROC_PROC_H */ diff --git a/arch/mn10300/proc-mn103e010/proc-init.c b/arch/mn10300/proc-mn103e010/proc-init.c deleted file mode 100644 index 102d86a6ae56..000000000000 --- a/arch/mn10300/proc-mn103e010/proc-init.c +++ /dev/null @@ -1,115 +0,0 @@ -/* MN103E010 Processor initialisation - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include - -/* - * initialise the on-silicon processor peripherals - */ -asmlinkage void __init processor_init(void) -{ - int loop; - - /* set up the exception table first */ - for (loop = 0x000; loop < 0x400; loop += 8) - __set_intr_stub(loop, __common_exception); - - __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); - __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); - __set_intr_stub(EXCEP_IAERROR, itlb_aerror); - __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); - __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); - __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); - __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); - __set_intr_stub(EXCEP_SYSCALL0, system_call); - - __set_intr_stub(EXCEP_NMI, nmi_handler); - __set_intr_stub(EXCEP_WDT, nmi_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); - - IVAR0 = EXCEP_IRQ_LEVEL0; - IVAR1 = EXCEP_IRQ_LEVEL1; - IVAR2 = EXCEP_IRQ_LEVEL2; - IVAR3 = EXCEP_IRQ_LEVEL3; - IVAR4 = EXCEP_IRQ_LEVEL4; - IVAR5 = EXCEP_IRQ_LEVEL5; - IVAR6 = EXCEP_IRQ_LEVEL6; - - mn10300_dcache_flush_inv(); - mn10300_icache_inv(); - - /* disable all interrupts and set to priority 6 (lowest) */ - for (loop = 0; loop < NR_IRQS; loop++) - GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; - - /* clear the timers */ - TM0MD = 0; - TM1MD = 0; - TM2MD = 0; - TM3MD = 0; - TM4MD = 0; - TM5MD = 0; - TM6MD = 0; - TM6MDA = 0; - TM6MDB = 0; - TM7MD = 0; - TM8MD = 0; - TM9MD = 0; - TM10MD = 0; - TM11MD = 0; - - calibrate_clock(); -} - -/* - * determine the memory size and base from the memory controller regs - */ -void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size) -{ - unsigned long base, size; - - *mem_base = 0; - *mem_size = 0; - - base = SDBASE(0); - if (base & SDBASE_CE) { - size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; - size = ~size + 1; - base &= SDBASE_CBA; - - printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base); - *mem_size += size; - *mem_base = base; - } - - base = SDBASE(1); - if (base & SDBASE_CE) { - size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; - size = ~size + 1; - base &= SDBASE_CBA; - - printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base); - *mem_size += size; - if (*mem_base == 0) - *mem_base = base; - } -} diff --git a/arch/mn10300/proc-mn2ws0050/Makefile b/arch/mn10300/proc-mn2ws0050/Makefile deleted file mode 100644 index d4ca13309a85..000000000000 --- a/arch/mn10300/proc-mn2ws0050/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := proc-init.o diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h deleted file mode 100644 index bcb5df2d892f..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Cache specification - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 13-Nov-2006 MEI Add L1_CACHE_SHIFT_MAX definition. - * 29-Jul-2008 MEI Add define for MN10300_HAS_AREAPURGE_REG. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CACHE_H -#define _ASM_PROC_CACHE_H - -/* - * L1 cache - */ -#define L1_CACHE_NWAYS 4 /* number of ways in caches */ -#define L1_CACHE_NENTRIES 128 /* number of entries in each way */ -#define L1_CACHE_BYTES 32 /* bytes per entry */ -#define L1_CACHE_SHIFT 5 /* shift for bytes per entry */ -#define L1_CACHE_WAYDISP 0x1000 /* distance from one way to the next */ - -#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ -#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ -#define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */ -#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ -#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) - -/* - * specification of the interval between interrupt checking intervals whilst - * managing the cache with the interrupts disabled - */ -#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 - -/* - * The size of range at which it becomes more economical to just flush the - * whole cache rather than trying to flush the specified range. - */ -#define MN10300_DCACHE_FLUSH_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) -#define MN10300_DCACHE_FLUSH_INV_BORDER \ - +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) - -#endif /* _ASM_PROC_CACHE_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/clock.h b/arch/mn10300/proc-mn2ws0050/include/proc/clock.h deleted file mode 100644 index fe4c0a4a53a2..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/clock.h +++ /dev/null @@ -1,20 +0,0 @@ -/* clock.h: proc-specific clocks - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 23-Feb-2007 MEI Delete define for watchdog timer. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_PROC_CLOCK_H -#define _ASM_PROC_CLOCK_H - -#include - -#endif /* _ASM_PROC_CLOCK_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h deleted file mode 100644 index 4c4319e241d1..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h +++ /dev/null @@ -1,103 +0,0 @@ -/* MN2WS0050 on-board DMA controller registers - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - */ - -#ifndef _ASM_PROC_DMACTL_REGS_H -#define _ASM_PROC_DMACTL_REGS_H - -#include - -#ifdef __KERNEL__ - -/* DMA registers */ -#define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */ -#define DMxCTR_BG 0x0000001f /* transfer request source */ -#define DMxCTR_BG_SOFT 0x00000000 /* - software source */ -#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */ -#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */ -#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */ -#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */ -#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */ -#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */ -#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */ -#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */ -#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */ -#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */ -#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */ -#define DMxCTR_BG_RYBY 0x0000000d /* - NAND Flash RY/BY request source */ -#define DMxCTR_BG_RMC 0x0000000e /* - remote controller output */ -#define DMxCTR_BG_XIRQ12 0x00000011 /* - XIRQ12 pin interrupt source */ -#define DMxCTR_BG_XIRQ13 0x00000012 /* - XIRQ13 pin interrupt source */ -#define DMxCTR_BG_TCK 0x00000014 /* - tick timer underflow */ -#define DMxCTR_BG_SC4TX 0x00000019 /* - serial port4 transmission */ -#define DMxCTR_BG_SC4RX 0x0000001a /* - serial port4 reception */ -#define DMxCTR_BG_SC5TX 0x0000001b /* - serial port5 transmission */ -#define DMxCTR_BG_SC5RX 0x0000001c /* - serial port5 reception */ -#define DMxCTR_BG_SC6TX 0x0000001d /* - serial port6 transmission */ -#define DMxCTR_BG_SC6RX 0x0000001e /* - serial port6 reception */ -#define DMxCTR_BG_TMSUFLOW 0x0000001f /* - timestamp timer underflow */ -#define DMxCTR_SAM 0x00000060 /* DMA transfer src addr mode */ -#define DMxCTR_SAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */ -#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */ -#define DMxCTR_DAM 0x00000300 /* DMA transfer dest addr mode */ -#define DMxCTR_DAM_INCR 0x00000000 /* - increment */ -#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */ -#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */ -#define DMxCTR_UT 0x00006000 /* DMA transfer unit */ -#define DMxCTR_UT_1 0x00000000 /* - 1 byte */ -#define DMxCTR_UT_2 0x00002000 /* - 2 byte */ -#define DMxCTR_UT_4 0x00004000 /* - 4 byte */ -#define DMxCTR_UT_16 0x00006000 /* - 16 byte */ -#define DMxCTR_RRE 0x00008000 /* DMA round robin enable */ -#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */ -#define DMxCTR_RQM 0x00060000 /* external request input source mode */ -#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */ -#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */ -#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */ -#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */ -#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */ -#define DMxCTR_PERR 0x40000000 /* DMA transfer parameter error flag */ -#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */ - -#define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */ - -#define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */ - -#define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */ -#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */ - -#define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */ -#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */ - -#define DM0IRQ 16 /* DMA channel 0 complete IRQ */ -#define DM1IRQ 17 /* DMA channel 1 complete IRQ */ -#define DM2IRQ 18 /* DMA channel 2 complete IRQ */ -#define DM3IRQ 19 /* DMA channel 3 complete IRQ */ - -#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */ -#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */ -#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */ -#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */ - -#ifndef __ASSEMBLY__ - -struct mn10300_dmactl_regs { - u32 ctr; - const void *src; - void *dst; - u32 siz; - u32 cyc; -} __attribute__((aligned(0x100))); - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_PROC_DMACTL_REGS_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h deleted file mode 100644 index 4d4084ea6694..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_PROC_INTCTL_REGS_H -#define _ASM_PROC_INTCTL_REGS_H - -#ifndef _ASM_INTCTL_REGS_H -# error "please don't include this file directly" -#endif - -/* intr acceptance group reg */ -#define IAGR __SYSREG(0xd4000100, u16) - -/* group number register */ -#define IAGR_GN 0x003fc - -#define __GET_XIRQ_TRIGGER(X, Z) (((Z) >> ((X) * 2)) & 3) - -#define __SET_XIRQ_TRIGGER(X, Y, Z) \ -({ \ - typeof(Z) x = (Z); \ - x &= ~(3 << ((X) * 2)); \ - x |= ((Y) & 3) << ((X) * 2); \ - (Z) = x; \ -}) - -/* external pin intr spec reg */ -#define EXTMD0 __SYSREG(0xd4000200, u32) -#define GET_XIRQ_TRIGGER(X) __GET_XIRQ_TRIGGER(X, EXTMD0) -#define SET_XIRQ_TRIGGER(X, Y) __SET_XIRQ_TRIGGER(X, Y, EXTMD0) - -#endif /* _ASM_PROC_INTCTL_REGS_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/irq.h b/arch/mn10300/proc-mn2ws0050/include/proc/irq.h deleted file mode 100644 index 37777a85ab6f..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/irq.h +++ /dev/null @@ -1,49 +0,0 @@ -/* MN2WS0050 on-board interrupt controller registers - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 13-Nov-2006 MEI Define extended IRQ number for SMP support. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _PROC_IRQ_H -#define _PROC_IRQ_H - -#ifdef __KERNEL__ - -#define GxICR_NUM_IRQS 163 -#ifdef CONFIG_SMP -#define GxICR_NUM_EXT_IRQS 197 -#endif /* CONFIG_SMP */ - -#define GxICR_NUM_XIRQS 16 - -#define XIRQ0 34 -#define XIRQ1 35 -#define XIRQ2 36 -#define XIRQ3 37 -#define XIRQ4 38 -#define XIRQ5 39 -#define XIRQ6 40 -#define XIRQ7 41 -#define XIRQ8 42 -#define XIRQ9 43 -#define XIRQ10 44 -#define XIRQ11 45 -#define XIRQ12 46 -#define XIRQ13 47 -#define XIRQ14 48 -#define XIRQ15 49 - -#define XIRQ2IRQ(num) (XIRQ0 + num) - -#endif /* __KERNEL__ */ - -#endif /* _PROC_IRQ_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h deleted file mode 100644 index 84448f3828b3..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h +++ /dev/null @@ -1,120 +0,0 @@ -/* NAND flash interface register definitions - * - * Copyright (C) 2008-2009 Panasonic Corporation - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PROC_NAND_REGS_H_ -#define _PROC_NAND_REGS_H_ - -/* command register */ -#define FCOMMAND_0 __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */ -#define FCOMMAND_1 __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */ -#define FCOMMAND_2 __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */ -#define FCOMMAND_3 __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */ - -/* for dma 16 byte trans, use FCOMMAND2 register */ -#define FCOMMAND2_0 __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */ -#define FCOMMAND2_1 __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */ -#define FCOMMAND2_2 __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */ -#define FCOMMAND2_3 __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */ - -#define FCOMMAND_FIEN 0x80 /* nand flash I/F enable */ -#define FCOMMAND_BW_8BIT 0x00 /* 8bit bus width */ -#define FCOMMAND_BW_16BIT 0x40 /* 16bit bus width */ -#define FCOMMAND_BLOCKSZ_SMALL 0x00 /* small block */ -#define FCOMMAND_BLOCKSZ_LARGE 0x20 /* large block */ -#define FCOMMAND_DMASTART 0x10 /* dma start */ -#define FCOMMAND_RYBY 0x08 /* ready/busy flag */ -#define FCOMMAND_RYBYINTMSK 0x04 /* mask ready/busy interrupt */ -#define FCOMMAND_XFWP 0x02 /* write protect enable */ -#define FCOMMAND_XFCE 0x01 /* flash device disable */ -#define FCOMMAND_SEQKILL 0x10 /* stop seq-read */ -#define FCOMMAND_ANUM 0x07 /* address cycle */ -#define FCOMMAND_ANUM_NONE 0x00 /* address cycle none */ -#define FCOMMAND_ANUM_1CYC 0x01 /* address cycle 1cycle */ -#define FCOMMAND_ANUM_2CYC 0x02 /* address cycle 2cycle */ -#define FCOMMAND_ANUM_3CYC 0x03 /* address cycle 3cycle */ -#define FCOMMAND_ANUM_4CYC 0x04 /* address cycle 4cycle */ -#define FCOMMAND_ANUM_5CYC 0x05 /* address cycle 5cycle */ -#define FCOMMAND_FCMD_READ0 0x00 /* read1 command */ -#define FCOMMAND_FCMD_SEQIN 0x80 /* page program 1st command */ -#define FCOMMAND_FCMD_PAGEPROG 0x10 /* page program 2nd command */ -#define FCOMMAND_FCMD_RESET 0xff /* reset command */ -#define FCOMMAND_FCMD_ERASE1 0x60 /* erase 1st command */ -#define FCOMMAND_FCMD_ERASE2 0xd0 /* erase 2nd command */ -#define FCOMMAND_FCMD_STATUS 0x70 /* read status command */ -#define FCOMMAND_FCMD_READID 0x90 /* read id command */ -#define FCOMMAND_FCMD_READOOB 0x50 /* read3 command */ -/* address register */ -#define FADD __SYSREG(0xd8f00004, u32) -/* address register 2 */ -#define FADD2 __SYSREG(0xd8f00008, u32) -/* error judgement register */ -#define FJUDGE __SYSREG(0xd8f0000c, u32) -#define FJUDGE_NOERR 0x0 /* no error */ -#define FJUDGE_1BITERR 0x1 /* 1bit error in data area */ -#define FJUDGE_PARITYERR 0x2 /* parity error */ -#define FJUDGE_UNCORRECTABLE 0x3 /* uncorrectable error */ -#define FJUDGE_ERRJDG_MSK 0x3 /* mask of judgement result */ -/* 1st ECC store register */ -#define FECC11 __SYSREG(0xd8f00010, u32) -/* 2nd ECC store register */ -#define FECC12 __SYSREG(0xd8f00014, u32) -/* 3rd ECC store register */ -#define FECC21 __SYSREG(0xd8f00018, u32) -/* 4th ECC store register */ -#define FECC22 __SYSREG(0xd8f0001c, u32) -/* 5th ECC store register */ -#define FECC31 __SYSREG(0xd8f00020, u32) -/* 6th ECC store register */ -#define FECC32 __SYSREG(0xd8f00024, u32) -/* 7th ECC store register */ -#define FECC41 __SYSREG(0xd8f00028, u32) -/* 8th ECC store register */ -#define FECC42 __SYSREG(0xd8f0002c, u32) -/* data register */ -#define FDATA __SYSREG(0xd8f00030, u32) -/* access pulse register */ -#define FPWS __SYSREG(0xd8f00100, u32) -#define FPWS_PWS1W_2CLK 0x00000000 /* write pulse width 1clock */ -#define FPWS_PWS1W_3CLK 0x01000000 /* write pulse width 2clock */ -#define FPWS_PWS1W_4CLK 0x02000000 /* write pulse width 4clock */ -#define FPWS_PWS1W_5CLK 0x03000000 /* write pulse width 5clock */ -#define FPWS_PWS1W_6CLK 0x04000000 /* write pulse width 6clock */ -#define FPWS_PWS1W_7CLK 0x05000000 /* write pulse width 7clock */ -#define FPWS_PWS1W_8CLK 0x06000000 /* write pulse width 8clock */ -#define FPWS_PWS1R_3CLK 0x00010000 /* read pulse width 3clock */ -#define FPWS_PWS1R_4CLK 0x00020000 /* read pulse width 4clock */ -#define FPWS_PWS1R_5CLK 0x00030000 /* read pulse width 5clock */ -#define FPWS_PWS1R_6CLK 0x00040000 /* read pulse width 6clock */ -#define FPWS_PWS1R_7CLK 0x00050000 /* read pulse width 7clock */ -#define FPWS_PWS1R_8CLK 0x00060000 /* read pulse width 8clock */ -#define FPWS_PWS2W_2CLK 0x00000100 /* write pulse interval 2clock */ -#define FPWS_PWS2W_3CLK 0x00000200 /* write pulse interval 3clock */ -#define FPWS_PWS2W_4CLK 0x00000300 /* write pulse interval 4clock */ -#define FPWS_PWS2W_5CLK 0x00000400 /* write pulse interval 5clock */ -#define FPWS_PWS2W_6CLK 0x00000500 /* write pulse interval 6clock */ -#define FPWS_PWS2R_2CLK 0x00000001 /* read pulse interval 2clock */ -#define FPWS_PWS2R_3CLK 0x00000002 /* read pulse interval 3clock */ -#define FPWS_PWS2R_4CLK 0x00000003 /* read pulse interval 4clock */ -#define FPWS_PWS2R_5CLK 0x00000004 /* read pulse interval 5clock */ -#define FPWS_PWS2R_6CLK 0x00000005 /* read pulse interval 6clock */ -/* command register 2 */ -#define FCOMMAND2 __SYSREG(0xd8f00110, u32) -/* transfer frequency register */ -#define FNUM __SYSREG(0xd8f00114, u32) -#define FSDATA_ADDR 0xd8f00400 -/* active data register */ -#define FSDATA __SYSREG(FSDATA_ADDR, u32) - -#endif /* _PROC_NAND_REGS_H_ */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/proc.h b/arch/mn10300/proc-mn2ws0050/include/proc/proc.h deleted file mode 100644 index 90d5cadd05bd..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/proc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* proc.h: MN2WS0050 processor description - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_PROC_H -#define _ASM_PROC_PROC_H - -#define PROCESSOR_VENDOR_NAME "Panasonic" -#define PROCESSOR_MODEL_NAME "mn2ws0050" - -#endif /* _ASM_PROC_PROC_H */ diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h deleted file mode 100644 index 22f277fbb4de..000000000000 --- a/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h +++ /dev/null @@ -1,51 +0,0 @@ -/* MN10300/AM33v2 Microcontroller SMP registers - * - * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd. - * All Rights Reserved. - * Created: - * 13-Nov-2006 MEI Add extended cache and atomic operation register - * for SMP support. - * 23-Feb-2007 MEI Add define for gdbstub SMP. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _ASM_PROC_SMP_REGS_H -#define _ASM_PROC_SMP_REGS_H - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -#include -#endif -#include - -/* - * Reference to the interrupt controllers of other CPUs - */ -#define CROSS_ICR_CPU_SHIFT 16 - -#define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ - ((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16) -#define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ - (((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8) - -/* CPU ID register */ -#define CPUID __SYSREGC(0xc0000054, u32) -#define CPUID_MASK 0x00000007 /* CPU ID mask */ - -/* extended cache control register */ -#define ECHCTR __SYSREG(0xc0000c20, u32) -#define ECHCTR_IBCM 0x00000001 /* instruction cache broad cast mask */ -#define ECHCTR_DBCM 0x00000002 /* data cache broad cast mask */ -#define ECHCTR_ISPM 0x00000004 /* instruction cache snoop mask */ -#define ECHCTR_DSPM 0x00000008 /* data cache snoop mask */ - -#define NMIAGR __SYSREG(0xd400013c, u16) -#define NMIAGR_GN 0x03fc - -#endif /* __KERNEL__ */ -#endif /* _ASM_PROC_SMP_REGS_H */ diff --git a/arch/mn10300/proc-mn2ws0050/proc-init.c b/arch/mn10300/proc-mn2ws0050/proc-init.c deleted file mode 100644 index 25b1b453c515..000000000000 --- a/arch/mn10300/proc-mn2ws0050/proc-init.c +++ /dev/null @@ -1,134 +0,0 @@ -/* MN2WS0050 processor initialisation - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MEMCONF __SYSREGC(0xdf800400, u32) - -/* - * initialise the on-silicon processor peripherals - */ -asmlinkage void __init processor_init(void) -{ - int loop; - - /* set up the exception table first */ - for (loop = 0x000; loop < 0x400; loop += 8) - __set_intr_stub(loop, __common_exception); - - __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); - __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); - __set_intr_stub(EXCEP_IAERROR, itlb_aerror); - __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); - __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); - __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); - __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); - __set_intr_stub(EXCEP_SYSCALL0, system_call); - - __set_intr_stub(EXCEP_NMI, nmi_handler); - __set_intr_stub(EXCEP_WDT, nmi_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); - __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); - - IVAR0 = EXCEP_IRQ_LEVEL0; - IVAR1 = EXCEP_IRQ_LEVEL1; - IVAR2 = EXCEP_IRQ_LEVEL2; - IVAR3 = EXCEP_IRQ_LEVEL3; - IVAR4 = EXCEP_IRQ_LEVEL4; - IVAR5 = EXCEP_IRQ_LEVEL5; - IVAR6 = EXCEP_IRQ_LEVEL6; - -#ifndef CONFIG_MN10300_HAS_CACHE_SNOOP - mn10300_dcache_flush_inv(); - mn10300_icache_inv(); -#endif - - /* disable all interrupts and set to priority 6 (lowest) */ -#ifdef CONFIG_SMP - for (loop = 0; loop < GxICR_NUM_IRQS; loop++) - GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; -#else /* !CONFIG_SMP */ - for (loop = 0; loop < NR_IRQS; loop++) - GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; -#endif /* !CONFIG_SMP */ - - /* clear the timers */ - TM0MD = 0; - TM1MD = 0; - TM2MD = 0; - TM3MD = 0; - TM4MD = 0; - TM5MD = 0; - TM6MD = 0; - TM6MDA = 0; - TM6MDB = 0; - TM7MD = 0; - TM8MD = 0; - TM9MD = 0; - TM10MD = 0; - TM11MD = 0; - TM12MD = 0; - TM13MD = 0; - TM14MD = 0; - TM15MD = 0; - - calibrate_clock(); -} - -/* - * determine the memory size and base from the memory controller regs - */ -void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size) -{ - unsigned long memconf = MEMCONF; - unsigned long size = 0; /* order: MByte */ - - *mem_base = 0x90000000; /* fixed address */ - - switch (memconf & 0x00000003) { - case 0x01: - size = 256 / 8; /* 256 Mbit per chip */ - break; - case 0x02: - size = 512 / 8; /* 512 Mbit per chip */ - break; - case 0x03: - size = 1024 / 8; /* 1 Gbit per chip */ - break; - default: - panic("Invalid SDRAM size"); - break; - } - - printk(KERN_INFO "DDR2-SDRAM: %luMB x 2 @%08lx\n", size, *mem_base); - - *mem_size = (size * 2) << 20; -} diff --git a/arch/mn10300/unit-asb2303/Makefile b/arch/mn10300/unit-asb2303/Makefile deleted file mode 100644 index 38a5bb43b0bb..000000000000 --- a/arch/mn10300/unit-asb2303/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -############################################################################### -# -# Makefile for the ASB2303 board -# -############################################################################### -obj-y := unit-init.o smc91111.o flash.o leds.o diff --git a/arch/mn10300/unit-asb2303/flash.c b/arch/mn10300/unit-asb2303/flash.c deleted file mode 100644 index b03d8738d67c..000000000000 --- a/arch/mn10300/unit-asb2303/flash.c +++ /dev/null @@ -1,99 +0,0 @@ -/* Handle mapping of the flash on the ASB2303 board - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include - -#define ASB2303_PROM_ADDR 0xA0000000 /* Boot PROM */ -#define ASB2303_PROM_SIZE (2 * 1024 * 1024) -#define ASB2303_FLASH_ADDR 0xA4000000 /* System Flash */ -#define ASB2303_FLASH_SIZE (32 * 1024 * 1024) -#define ASB2303_CONFIG_ADDR 0xA6000000 /* System Config EEPROM */ -#define ASB2303_CONFIG_SIZE (8 * 1024) - -/* - * default MTD partition table for both main flash devices, expected to be - * overridden by RedBoot - */ -static struct mtd_partition asb2303_partitions[] = { - { - .name = "Bootloader", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM /* force read-only */ - }, { - .name = "Kernel", - .size = 0x00400000, - .offset = 0x00040000, - }, { - .name = "Filesystem", - .size = MTDPART_SIZ_FULL, - .offset = 0x00440000 - } -}; - -/* - * the ASB2303 Boot PROM definition - */ -static struct physmap_flash_data asb2303_bootprom_data = { - .width = 2, - .nr_parts = 1, - .parts = asb2303_partitions, -}; - -static struct resource asb2303_bootprom_resource = { - .start = ASB2303_PROM_ADDR, - .end = ASB2303_PROM_ADDR + ASB2303_PROM_SIZE, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device asb2303_bootprom = { - .name = "physmap-flash", - .id = 0, - .dev.platform_data = &asb2303_bootprom_data, - .num_resources = 1, - .resource = &asb2303_bootprom_resource, -}; - -/* - * the ASB2303 System Flash definition - */ -static struct physmap_flash_data asb2303_sysflash_data = { - .width = 4, - .nr_parts = 1, - .parts = asb2303_partitions, -}; - -static struct resource asb2303_sysflash_resource = { - .start = ASB2303_FLASH_ADDR, - .end = ASB2303_FLASH_ADDR + ASB2303_FLASH_SIZE, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device asb2303_sysflash = { - .name = "physmap-flash", - .id = 1, - .dev.platform_data = &asb2303_sysflash_data, - .num_resources = 1, - .resource = &asb2303_sysflash_resource, -}; - -/* - * register the ASB2303 flashes - */ -static int __init asb2303_mtd_init(void) -{ - platform_device_register(&asb2303_bootprom); - platform_device_register(&asb2303_sysflash); - return 0; -} -device_initcall(asb2303_mtd_init); diff --git a/arch/mn10300/unit-asb2303/include/unit/clock.h b/arch/mn10300/unit-asb2303/include/unit/clock.h deleted file mode 100644 index 0316907a012e..000000000000 --- a/arch/mn10300/unit-asb2303/include/unit/clock.h +++ /dev/null @@ -1,24 +0,0 @@ -/* ASB2303-specific clocks - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_CLOCK_H -#define _ASM_UNIT_CLOCK_H - -#ifndef __ASSEMBLY__ - -#define MN10300_IOCLK 33333333UL -/* #define MN10300_IOBCLK 66666666UL */ - -#endif /* !__ASSEMBLY__ */ - -#define MN10300_WDCLK MN10300_IOCLK - -#endif /* _ASM_UNIT_CLOCK_H */ diff --git a/arch/mn10300/unit-asb2303/include/unit/leds.h b/arch/mn10300/unit-asb2303/include/unit/leds.h deleted file mode 100644 index 3a7543ea7b5c..000000000000 --- a/arch/mn10300/unit-asb2303/include/unit/leds.h +++ /dev/null @@ -1,43 +0,0 @@ -/* ASB2303-specific LEDs - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_LEDS_H -#define _ASM_UNIT_LEDS_H - -#include -#include -#include - -#define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32) -#define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32) - -/* - * use the 7-segment LEDs to indicate states - */ - -/* flip the 7-segment LEDs between "G" and "-" */ -#define mn10300_set_gdbleds(ONOFF) \ -do { \ - ASB2303_7SEGLEDS = (ONOFF) ? 0x85 : 0x7f; \ -} while (0) - -/* indicate double-fault by displaying "d" on the LEDs */ -#define mn10300_set_dbfleds \ - mov 0x43,d0 ; \ - movbu d0,(ASB2303_7SEGLEDS) - -#ifndef __ASSEMBLY__ -extern void peripheral_leds_display_exception(enum exception_code code); -extern void peripheral_leds_led_chase(void); -extern void debug_to_serial(const char *p, int n); -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_UNIT_LEDS_H */ diff --git a/arch/mn10300/unit-asb2303/include/unit/serial.h b/arch/mn10300/unit-asb2303/include/unit/serial.h deleted file mode 100644 index 991e356bac5f..000000000000 --- a/arch/mn10300/unit-asb2303/include/unit/serial.h +++ /dev/null @@ -1,141 +0,0 @@ -/* ASB2303-specific 8250 serial ports - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_SERIAL_H -#define _ASM_UNIT_SERIAL_H - -#include -#include -#include - -#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000 -#define SERIAL_PORT1_BASE_ADDRESS 0xA6FC0000 - -#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */ - -/* - * The ASB2303 has an 18.432 MHz clock the UART - */ -#define BASE_BAUD (18432000 / 16) - -/* - * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports - */ -#ifndef CONFIG_GDBSTUB_ON_TTYSx - -#define SERIAL_PORT_DFNS \ - { \ - .baud_base = BASE_BAUD, \ - .irq = SERIAL_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM, \ - }, \ - { \ - .baud_base = BASE_BAUD, \ - .irq = SERIAL_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) SERIAL_PORT1_BASE_ADDRESS, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM, \ - }, - -#ifndef __ASSEMBLY__ - -static inline void __debug_to_serial(const char *p, int n) -{ -} - -#endif /* !__ASSEMBLY__ */ - -#else /* CONFIG_GDBSTUB_ON_TTYSx */ - -#define SERIAL_PORT_DFNS /* both stolen by gdb-stub because they share an IRQ */ - -#if defined(CONFIG_GDBSTUB_ON_TTYS0) -#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8) -#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) -#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8) -#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8) -#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8) -#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8) -#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8) -#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8) -#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) -#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) -#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) -#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8) -#define GDBPORT_SERIAL_IRQ SERIAL_IRQ - -#elif defined(CONFIG_GDBSTUB_ON_TTYS1) -#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_RX * 4, u8) -#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_TX * 4, u8) -#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLL * 4, u8) -#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLM * 4, u8) -#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IER * 4, u8) -#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IIR * 4, u8) -#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_FCR * 4, u8) -#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LCR * 4, u8) -#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MCR * 4, u8) -#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LSR * 4, u8) -#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MSR * 4, u8) -#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_SCR * 4, u8) -#define GDBPORT_SERIAL_IRQ SERIAL_IRQ -#endif - -#ifndef __ASSEMBLY__ - -#define LSR_WAIT_FOR(STATE) \ -do { \ - while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE)) {} \ -} while (0) -#define FLOWCTL_WAIT_FOR(LINE) \ -do { \ - while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) {} \ -} while (0) -#define FLOWCTL_CLEAR(LINE) \ -do { \ - GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; \ -} while (0) -#define FLOWCTL_SET(LINE) \ -do { \ - GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; \ -} while (0) -#define FLOWCTL_QUERY(LINE) ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; }) - -static inline void __debug_to_serial(const char *p, int n) -{ - char ch; - - FLOWCTL_SET(DTR); - - for (; n > 0; n--) { - LSR_WAIT_FOR(THRE); - FLOWCTL_WAIT_FOR(CTS); - - ch = *p++; - if (ch == 0x0a) { - GDBPORT_SERIAL_TX = 0x0d; - LSR_WAIT_FOR(THRE); - FLOWCTL_WAIT_FOR(CTS); - } - GDBPORT_SERIAL_TX = ch; - } - - FLOWCTL_CLEAR(DTR); -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* CONFIG_GDBSTUB_ON_TTYSx */ - -#endif /* _ASM_UNIT_SERIAL_H */ diff --git a/arch/mn10300/unit-asb2303/include/unit/smc91111.h b/arch/mn10300/unit-asb2303/include/unit/smc91111.h deleted file mode 100644 index dd4e2946438e..000000000000 --- a/arch/mn10300/unit-asb2303/include/unit/smc91111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Support for the SMC91C111 NIC on an ASB2303 - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_UNIT_SMC91111_H -#define _ASM_UNIT_SMC91111_H - -#include - -#define SMC91111_BASE 0xAA000300UL -#define SMC91111_BASE_END 0xAA000400UL -#define SMC91111_IRQ XIRQ3 - -#define SMC_CAN_USE_8BIT 0 -#define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 0 -#define SMC_NOWAIT 1 -#define SMC_IRQ_FLAGS (0) - -#if SMC_CAN_USE_8BIT -#define SMC_inb(a, r) inb((unsigned long) ((a) + (r))) -#define SMC_outb(v, a, r) outb(v, (unsigned long) ((a) + (r))) -#endif - -#if SMC_CAN_USE_16BIT -#define SMC_inw(a, r) inw((unsigned long) ((a) + (r))) -#define SMC_outw(lp, v, a, r) outw(v, (unsigned long) ((a) + (r))) -#define SMC_insw(a, r, p, l) insw((unsigned long) ((a) + (r)), (p), (l)) -#define SMC_outsw(a, r, p, l) outsw((unsigned long) ((a) + (r)), (p), (l)) -#endif - -#if SMC_CAN_USE_32BIT -#define SMC_inl(a, r) inl((unsigned long) ((a) + (r))) -#define SMC_outl(v, a, r) outl(v, (unsigned long) ((a) + (r))) -#define SMC_insl(a, r, p, l) insl((unsigned long) ((a) + (r)), (p), (l)) -#define SMC_outsl(a, r, p, l) outsl((unsigned long) ((a) + (r)), (p), (l)) -#endif - -#define RPC_LSA_DEFAULT RPC_LED_100_10 -#define RPC_LSB_DEFAULT RPC_LED_TX_RX - -#define set_irq_type(irq, type) - -#endif /* _ASM_UNIT_SMC91111_H */ diff --git a/arch/mn10300/unit-asb2303/include/unit/timex.h b/arch/mn10300/unit-asb2303/include/unit/timex.h deleted file mode 100644 index c37f9832cf17..000000000000 --- a/arch/mn10300/unit-asb2303/include/unit/timex.h +++ /dev/null @@ -1,146 +0,0 @@ -/* ASB2303-specific timer specifications - * - * Copyright (C) 2007, 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_UNIT_TIMEX_H -#define _ASM_UNIT_TIMEX_H - -#include -#include -#include - -/* - * jiffies counter specifications - */ - -#define TMJCBR_MAX 0xffff -#define TMJCIRQ TM1IRQ -#define TMJCICR TM1ICR - -#ifndef __ASSEMBLY__ - -#define MN10300_SRC_IOCLK MN10300_IOCLK - -#ifndef HZ -# error HZ undeclared. -#endif /* !HZ */ -/* use as little prescaling as possible to avoid losing accuracy */ -#if (MN10300_SRC_IOCLK + HZ / 2) / HZ - 1 <= TMJCBR_MAX -# define IOCLK_PRESCALE 1 -# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK -# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK -#elif (MN10300_SRC_IOCLK / 8 + HZ / 2) / HZ - 1 <= TMJCBR_MAX -# define IOCLK_PRESCALE 8 -# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_8 -# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_8 -#elif (MN10300_SRC_IOCLK / 32 + HZ / 2) / HZ - 1 <= TMJCBR_MAX -# define IOCLK_PRESCALE 32 -# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_32 -# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_32 -#else -# error You lose. -#endif - -#define MN10300_JCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) -#define MN10300_TSCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) - -#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ) -#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ) - -static inline void stop_jiffies_counter(void) -{ - u16 tmp; - TM01MD = JC_TIMER_CLKSRC | TM1MD_SRC_TM0CASCADE << 8; - tmp = TM01MD; -} - -static inline void reload_jiffies_counter(u32 cnt) -{ - u32 tmp; - - TM01BR = cnt; - tmp = TM01BR; - - TM01MD = JC_TIMER_CLKSRC | \ - TM1MD_SRC_TM0CASCADE << 8 | \ - TM0MD_INIT_COUNTER | \ - TM1MD_INIT_COUNTER << 8; - - - TM01MD = JC_TIMER_CLKSRC | \ - TM1MD_SRC_TM0CASCADE << 8 | \ - TM0MD_COUNT_ENABLE | \ - TM1MD_COUNT_ENABLE << 8; - - tmp = TM01MD; -} - -#endif /* !__ASSEMBLY__ */ - - -/* - * timestamp counter specifications - */ - -#define TMTSCBR_MAX 0xffffffff -#define TMTSCBC TM45BC - -#ifndef __ASSEMBLY__ - -static inline void startup_timestamp_counter(void) -{ - u32 t32; - - /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time - * - count down from 4Gig-1 to 0 and wrap at IOCLK rate - */ - TM45BR = TMTSCBR_MAX; - t32 = TM45BR; - - TM4MD = TSC_TIMER_CLKSRC; - TM4MD |= TM4MD_INIT_COUNTER; - TM4MD &= ~TM4MD_INIT_COUNTER; - TM4ICR = 0; - t32 = TM4ICR; - - TM5MD = TM5MD_SRC_TM4CASCADE; - TM5MD |= TM5MD_INIT_COUNTER; - TM5MD &= ~TM5MD_INIT_COUNTER; - TM5ICR = 0; - t32 = TM5ICR; - - TM5MD |= TM5MD_COUNT_ENABLE; - TM4MD |= TM4MD_COUNT_ENABLE; - t32 = TM5MD; - t32 = TM4MD; -} - -static inline void shutdown_timestamp_counter(void) -{ - u8 t8; - TM4MD = 0; - TM5MD = 0; - t8 = TM4MD; - t8 = TM5MD; -} - -/* - * we use a cascaded pair of 16-bit down-counting timers to count I/O - * clock cycles for the purposes of time keeping - */ -typedef unsigned long cycles_t; - -static inline cycles_t read_timestamp_counter(void) -{ - return (cycles_t)~TMTSCBC; -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_UNIT_TIMEX_H */ diff --git a/arch/mn10300/unit-asb2303/leds.c b/arch/mn10300/unit-asb2303/leds.c deleted file mode 100644 index c03839357a14..000000000000 --- a/arch/mn10300/unit-asb2303/leds.c +++ /dev/null @@ -1,52 +0,0 @@ -/* ASB2303 peripheral 7-segment LEDs x1 support - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include - -#include -#include -#include -#include -#include - -#if 0 -static const u8 asb2303_led_hex_tbl[16] = { - 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0, - 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c -}; -#endif - -static const u8 asb2303_led_chase_tbl[6] = { - ~0x02, /* top - segA */ - ~0x04, /* right top - segB */ - ~0x08, /* right bottom - segC */ - ~0x10, /* bottom - segD */ - ~0x20, /* left bottom - segE */ - ~0x40, /* left top - segF */ -}; - -static unsigned asb2303_led_chase; - -void peripheral_leds_display_exception(enum exception_code code) -{ - ASB2303_GPIO0DEF = 0x5555; /* configure as an output port */ - ASB2303_7SEGLEDS = 0x6d; /* triple horizontal bar */ -} - -void peripheral_leds_led_chase(void) -{ - ASB2303_GPIO0DEF = 0x5555; /* configure as an output port */ - ASB2303_7SEGLEDS = asb2303_led_chase_tbl[asb2303_led_chase]; - asb2303_led_chase++; - if (asb2303_led_chase >= 6) - asb2303_led_chase = 0; -} diff --git a/arch/mn10300/unit-asb2303/smc91111.c b/arch/mn10300/unit-asb2303/smc91111.c deleted file mode 100644 index 53677694b165..000000000000 --- a/arch/mn10300/unit-asb2303/smc91111.c +++ /dev/null @@ -1,53 +0,0 @@ -/* ASB2303 initialisation - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -static struct resource smc91c111_resources[] = { - [0] = { - .start = SMC91111_BASE, - .end = SMC91111_BASE_END, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SMC91111_IRQ, - .end = SMC91111_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91c111_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91c111_resources), - .resource = smc91c111_resources, -}; - -/* - * add platform devices - */ -static int __init unit_device_init(void) -{ - platform_device_register(&smc91c111_device); - return 0; -} - -device_initcall(unit_device_init); diff --git a/arch/mn10300/unit-asb2303/unit-init.c b/arch/mn10300/unit-asb2303/unit-init.c deleted file mode 100644 index 834a76aa551a..000000000000 --- a/arch/mn10300/unit-asb2303/unit-init.c +++ /dev/null @@ -1,68 +0,0 @@ -/* ASB2303 initialisation - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * initialise some of the unit hardware before gdbstub is set up - */ -asmlinkage void __init unit_init(void) -{ - /* set up the external interrupts */ - SET_XIRQ_TRIGGER(0, XIRQ_TRIGGER_HILEVEL); - SET_XIRQ_TRIGGER(2, XIRQ_TRIGGER_LOWLEVEL); - SET_XIRQ_TRIGGER(3, XIRQ_TRIGGER_HILEVEL); - SET_XIRQ_TRIGGER(4, XIRQ_TRIGGER_LOWLEVEL); - SET_XIRQ_TRIGGER(5, XIRQ_TRIGGER_LOWLEVEL); - -#ifdef CONFIG_EXT_SERIAL_IRQ_LEVEL - set_intr_level(XIRQ0, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL)); -#endif - -#ifdef CONFIG_ETHERNET_IRQ_LEVEL - set_intr_level(XIRQ3, NUM2GxICR_LEVEL(CONFIG_ETHERNET_IRQ_LEVEL)); -#endif -} - -/* - * initialise the rest of the unit hardware after gdbstub is ready - */ -void __init unit_setup(void) -{ -} - -/* - * initialise the external interrupts used by a unit of this type - */ -void __init unit_init_IRQ(void) -{ - unsigned int extnum; - - for (extnum = 0; extnum < NR_XIRQS; extnum++) { - switch (GET_XIRQ_TRIGGER(extnum)) { - case XIRQ_TRIGGER_HILEVEL: - case XIRQ_TRIGGER_LOWLEVEL: - mn10300_set_lateack_irq_type(XIRQ2IRQ(extnum)); - break; - default: - break; - } - } -} diff --git a/arch/mn10300/unit-asb2305/Makefile b/arch/mn10300/unit-asb2305/Makefile deleted file mode 100644 index cbc5abaa939a..000000000000 --- a/arch/mn10300/unit-asb2305/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -############################################################################### -# -# Makefile for the ASB2305 board -# -############################################################################### -obj-y := unit-init.o leds.o - -obj-$(CONFIG_PCI) += pci.o pci-asb2305.o pci-irq.o diff --git a/arch/mn10300/unit-asb2305/include/unit/clock.h b/arch/mn10300/unit-asb2305/include/unit/clock.h deleted file mode 100644 index 29e3425431cf..000000000000 --- a/arch/mn10300/unit-asb2305/include/unit/clock.h +++ /dev/null @@ -1,24 +0,0 @@ -/* ASB2305-specific clocks - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_CLOCK_H -#define _ASM_UNIT_CLOCK_H - -#ifndef __ASSEMBLY__ - -#define MN10300_IOCLK 33333333UL -/* #define MN10300_IOBCLK 66666666UL */ - -#endif /* !__ASSEMBLY__ */ - -#define MN10300_WDCLK MN10300_IOCLK - -#endif /* _ASM_UNIT_CLOCK_H */ diff --git a/arch/mn10300/unit-asb2305/include/unit/leds.h b/arch/mn10300/unit-asb2305/include/unit/leds.h deleted file mode 100644 index bc471f617fd1..000000000000 --- a/arch/mn10300/unit-asb2305/include/unit/leds.h +++ /dev/null @@ -1,51 +0,0 @@ -/* ASB2305-specific LEDs - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_LEDS_H -#define _ASM_UNIT_LEDS_H - -#include -#include -#include - -#define ASB2305_7SEGLEDS __SYSREG(0xA6F90000, u32) - -/* perform a hard reset by driving PIO06 low */ -#define mn10300_unit_hard_reset() \ -do { \ - P0OUT &= 0xbf; \ - P0MD = (P0MD & P0MD_6) | P0MD_6_OUT; \ -} while (0) - -/* - * use the 7-segment LEDs to indicate states - */ -/* indicate double-fault by displaying "db-f" on the LEDs */ -#define mn10300_set_dbfleds \ - mov 0x43077f1d,d0 ; \ - mov d0,(ASB2305_7SEGLEDS) - -/* flip the 7-segment LEDs between "Gdb-" and "----" */ -#define mn10300_set_gdbleds(ONOFF) \ -do { \ - ASB2305_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f; \ -} while (0) - -#ifndef __ASSEMBLY__ -extern void peripheral_leds_display_exception(enum exception_code); -extern void peripheral_leds_led_chase(void); -extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int); -extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int); -extern void peripheral_leds7x4_display_minssecs(unsigned int, unsigned int); -extern void peripheral_leds7x4_display_rtc(void); -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_UNIT_LEDS_H */ diff --git a/arch/mn10300/unit-asb2305/include/unit/serial.h b/arch/mn10300/unit-asb2305/include/unit/serial.h deleted file mode 100644 index 88c08219315f..000000000000 --- a/arch/mn10300/unit-asb2305/include/unit/serial.h +++ /dev/null @@ -1,125 +0,0 @@ -/* ASB2305-specific 8250 serial ports - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_UNIT_SERIAL_H -#define _ASM_UNIT_SERIAL_H - -#include -#include -#include - -#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000 -#define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8) - -#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */ - -/* - * The ASB2305 has an 18.432 MHz clock the UART - */ -#define BASE_BAUD (18432000 / 16) - -/* - * dispose of the /dev/ttyS0 serial port - */ -#ifndef CONFIG_GDBSTUB_ON_TTYSx - -#define SERIAL_PORT_DFNS \ - { \ - .baud_base = BASE_BAUD, \ - .irq = SERIAL_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM, \ - }, - -#ifndef __ASSEMBLY__ - -static inline void __debug_to_serial(const char *p, int n) -{ -} - -#endif /* !__ASSEMBLY__ */ - -#else /* CONFIG_GDBSTUB_ON_TTYSx */ - -#define SERIAL_PORT_DFNS /* stolen by gdb-stub */ - -#if defined(CONFIG_GDBSTUB_ON_TTYS0) -#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8) -#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) -#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8) -#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8) -#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8) -#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8) -#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8) -#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8) -#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) -#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) -#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) -#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8) -#define GDBPORT_SERIAL_IRQ SERIAL_IRQ - -#elif defined(CONFIG_GDBSTUB_ON_TTYS1) -#error The ASB2305 doesnt have a /dev/ttyS1 -#endif - -#ifndef __ASSEMBLY__ - -#define TTYS0_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) -#define TTYS0_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) -#define TTYS0_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) -#define TTYS0_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) - -#define LSR_WAIT_FOR(STATE) \ -do { \ - while (!(TTYS0_LSR & UART_LSR_##STATE)) {} \ -} while (0) -#define FLOWCTL_WAIT_FOR(LINE) \ -do { \ - while (!(TTYS0_MSR & UART_MSR_##LINE)) {} \ -} while (0) -#define FLOWCTL_CLEAR(LINE) \ -do { \ - TTYS0_MCR &= ~UART_MCR_##LINE; \ -} while (0) -#define FLOWCTL_SET(LINE) \ -do { \ - TTYS0_MCR |= UART_MCR_##LINE; \ -} while (0) -#define FLOWCTL_QUERY(LINE) ({ TTYS0_MSR & UART_MSR_##LINE; }) - -static inline void __debug_to_serial(const char *p, int n) -{ - char ch; - - FLOWCTL_SET(DTR); - - for (; n > 0; n--) { - LSR_WAIT_FOR(THRE); - FLOWCTL_WAIT_FOR(CTS); - - ch = *p++; - if (ch == 0x0a) { - TTYS0_TX = 0x0d; - LSR_WAIT_FOR(THRE); - FLOWCTL_WAIT_FOR(CTS); - } - TTYS0_TX = ch; - } - - FLOWCTL_CLEAR(DTR); -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* CONFIG_GDBSTUB_ON_TTYSx */ - -#endif /* _ASM_UNIT_SERIAL_H */ diff --git a/arch/mn10300/unit-asb2305/include/unit/timex.h b/arch/mn10300/unit-asb2305/include/unit/timex.h deleted file mode 100644 index 4cefc224f448..000000000000 --- a/arch/mn10300/unit-asb2305/include/unit/timex.h +++ /dev/null @@ -1,146 +0,0 @@ -/* ASB2305-specific timer specifications - * - * Copyright (C) 2007, 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _ASM_UNIT_TIMEX_H -#define _ASM_UNIT_TIMEX_H - -#include -#include -#include - -/* - * jiffies counter specifications - */ - -#define TMJCBR_MAX 0xffff -#define TMJCIRQ TM1IRQ -#define TMJCICR TM1ICR - -#ifndef __ASSEMBLY__ - -#define MN10300_SRC_IOCLK MN10300_IOCLK - -#ifndef HZ -# error HZ undeclared. -#endif /* !HZ */ -/* use as little prescaling as possible to avoid losing accuracy */ -#if (MN10300_SRC_IOCLK + HZ / 2) / HZ - 1 <= TMJCBR_MAX -# define IOCLK_PRESCALE 1 -# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK -# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK -#elif (MN10300_SRC_IOCLK / 8 + HZ / 2) / HZ - 1 <= TMJCBR_MAX -# define IOCLK_PRESCALE 8 -# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_8 -# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_8 -#elif (MN10300_SRC_IOCLK / 32 + HZ / 2) / HZ - 1 <= TMJCBR_MAX -# define IOCLK_PRESCALE 32 -# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_32 -# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_32 -#else -# error You lose. -#endif - -#define MN10300_JCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) -#define MN10300_TSCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) - -#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ) -#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ) - -static inline void stop_jiffies_counter(void) -{ - u16 tmp; - TM01MD = JC_TIMER_CLKSRC | TM1MD_SRC_TM0CASCADE << 8; - tmp = TM01MD; -} - -static inline void reload_jiffies_counter(u32 cnt) -{ - u32 tmp; - - TM01BR = cnt; - tmp = TM01BR; - - TM01MD = JC_TIMER_CLKSRC | \ - TM1MD_SRC_TM0CASCADE << 8 | \ - TM0MD_INIT_COUNTER | \ - TM1MD_INIT_COUNTER << 8; - - - TM01MD = JC_TIMER_CLKSRC | \ - TM1MD_SRC_TM0CASCADE << 8 | \ - TM0MD_COUNT_ENABLE | \ - TM1MD_COUNT_ENABLE << 8; - - tmp = TM01MD; -} - -#endif /* !__ASSEMBLY__ */ - - -/* - * timestamp counter specifications - */ - -#define TMTSCBR_MAX 0xffffffff -#define TMTSCBC TM45BC - -#ifndef __ASSEMBLY__ - -static inline void startup_timestamp_counter(void) -{ - u32 t32; - - /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time - * - count down from 4Gig-1 to 0 and wrap at IOCLK rate - */ - TM45BR = TMTSCBR_MAX; - t32 = TM45BR; - - TM4MD = TSC_TIMER_CLKSRC; - TM4MD |= TM4MD_INIT_COUNTER; - TM4MD &= ~TM4MD_INIT_COUNTER; - TM4ICR = 0; - t32 = TM4ICR; - - TM5MD = TM5MD_SRC_TM4CASCADE; - TM5MD |= TM5MD_INIT_COUNTER; - TM5MD &= ~TM5MD_INIT_COUNTER; - TM5ICR = 0; - t32 = TM5ICR; - - TM5MD |= TM5MD_COUNT_ENABLE; - TM4MD |= TM4MD_COUNT_ENABLE; - t32 = TM5MD; - t32 = TM4MD; -} - -static inline void shutdown_timestamp_counter(void) -{ - u8 t8; - TM4MD = 0; - TM5MD = 0; - t8 = TM4MD; - t8 = TM5MD; -} - -/* - * we use a cascaded pair of 16-bit down-counting timers to count I/O - * clock cycles for the purposes of time keeping - */ -typedef unsigned long cycles_t; - -static inline cycles_t read_timestamp_counter(void) -{ - return (cycles_t)~TMTSCBC; -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_UNIT_TIMEX_H */ diff --git a/arch/mn10300/unit-asb2305/leds.c b/arch/mn10300/unit-asb2305/leds.c deleted file mode 100644 index 6f8de9954026..000000000000 --- a/arch/mn10300/unit-asb2305/leds.c +++ /dev/null @@ -1,124 +0,0 @@ -/* ASB2305 Peripheral 7-segment LEDs x4 support - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -static const u8 asb2305_led_hex_tbl[16] = { - 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0, - 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c -}; - -static const u32 asb2305_led_chase_tbl[6] = { - ~0x02020202, /* top - segA */ - ~0x04040404, /* right top - segB */ - ~0x08080808, /* right bottom - segC */ - ~0x10101010, /* bottom - segD */ - ~0x20202020, /* left bottom - segE */ - ~0x40404040, /* left top - segF */ -}; - -static unsigned asb2305_led_chase; - -void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points) -{ - u32 leds; - - leds = asb2305_led_hex_tbl[(val/1000) % 10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[(val/100) % 10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[(val/10) % 10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[val % 10]; - leds |= points^0x01010101; - - ASB2305_7SEGLEDS = leds; -} - -void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points) -{ - u32 leds; - - leds = asb2305_led_hex_tbl[(val/1000) % 10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[(val/100) % 10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[(val/10) % 10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[val % 10]; - leds |= points^0x01010101; - - ASB2305_7SEGLEDS = leds; -} - -void peripheral_leds_display_exception(enum exception_code code) -{ - u32 leds; - - leds = asb2305_led_hex_tbl[(code/0x100) % 0x10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[(code/0x10) % 0x10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[code % 0x10]; - leds |= 0x6d010101; - - ASB2305_7SEGLEDS = leds; -} - -void peripheral_leds7x4_display_minssecs(unsigned int time, unsigned int points) -{ - u32 leds; - - leds = asb2305_led_hex_tbl[(time/600) % 6]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[(time/60) % 10]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[(time/10) % 6]; - leds <<= 8; - leds |= asb2305_led_hex_tbl[time % 10]; - leds |= points^0x01010101; - - ASB2305_7SEGLEDS = leds; -} - -void peripheral_leds7x4_display_rtc(void) -{ - unsigned int clock; - u8 mins, secs; - - mins = RTMCR; - secs = RTSCR; - - clock = ((mins & 0xf0) >> 4); - clock *= 10; - clock += (mins & 0x0f); - clock *= 6; - - clock += ((secs & 0xf0) >> 4); - clock *= 10; - clock += (secs & 0x0f); - - peripheral_leds7x4_display_minssecs(clock, 0); -} - -void peripheral_leds_led_chase(void) -{ - ASB2305_7SEGLEDS = asb2305_led_chase_tbl[asb2305_led_chase]; - asb2305_led_chase++; - if (asb2305_led_chase >= 6) - asb2305_led_chase = 0; -} diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.c b/arch/mn10300/unit-asb2305/pci-asb2305.c deleted file mode 100644 index e0f4617c0c7a..000000000000 --- a/arch/mn10300/unit-asb2305/pci-asb2305.c +++ /dev/null @@ -1,212 +0,0 @@ -/* ASB2305 PCI resource stuff - * - * Copyright (C) 2001 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - Derived from arch/i386/pci-i386.c - * - Copyright 1997--2000 Martin Mares - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include "pci-asb2305.h" - -/* - * We need to avoid collisions with `mirrored' VGA ports - * and other strange ISA hardware, so we always want the - * addresses to be allocated in the 0x000-0x0ff region - * modulo 0x400. - * - * Why? Because some silly external IO cards only decode - * the low 10 bits of the IO address. The 0x00-0xff region - * is reserved for motherboard devices that decode all 16 - * bits, so it's ok to allocate at, say, 0x2800-0x28ff, - * but we want to try to avoid allocating at 0x2900-0x2bff - * which might have be mirrored at 0x0100-0x03ff.. - */ -resource_size_t pcibios_align_resource(void *data, const struct resource *res, - resource_size_t size, resource_size_t align) -{ - resource_size_t start = res->start; - -#if 0 - struct pci_dev *dev = data; - - printk(KERN_DEBUG - "### PCIBIOS_ALIGN_RESOURCE(%s,,{%08lx-%08lx,%08lx},%lx)\n", - pci_name(dev), - res->start, - res->end, - res->flags, - size - ); -#endif - - if ((res->flags & IORESOURCE_IO) && (start & 0x300)) - start = (start + 0x3ff) & ~0x3ff; - - return start; -} - - -/* - * Handle resources of PCI devices. If the world were perfect, we could - * just allocate all the resource regions and do nothing more. It isn't. - * On the other hand, we cannot just re-allocate all devices, as it would - * require us to know lots of host bridge internals. So we attempt to - * keep as much of the original configuration as possible, but tweak it - * when it's found to be wrong. - * - * Known BIOS problems we have to work around: - * - I/O or memory regions not configured - * - regions configured, but not enabled in the command register - * - bogus I/O addresses above 64K used - * - expansion ROMs left enabled (this may sound harmless, but given - * the fact the PCI specs explicitly allow address decoders to be - * shared between expansion ROMs and other resource regions, it's - * at least dangerous) - * - * Our solution: - * (1) Allocate resources for all buses behind PCI-to-PCI bridges. - * This gives us fixed barriers on where we can allocate. - * (2) Allocate resources for all enabled devices. If there is - * a collision, just mark the resource as unallocated. Also - * disable expansion ROMs during this step. - * (3) Try to allocate resources for disabled devices. If the - * resources were assigned correctly, everything goes well, - * if they weren't, they won't disturb allocation of other - * resources. - * (4) Assign new addresses to resources which were either - * not configured at all or misconfigured. If explicitly - * requested by the user, configure expansion ROM address - * as well. - */ -static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) -{ - struct pci_bus *bus; - struct pci_dev *dev; - int idx; - struct resource *r; - - /* Depth-First Search on bus tree */ - list_for_each_entry(bus, bus_list, node) { - dev = bus->self; - if (dev) { - for (idx = PCI_BRIDGE_RESOURCES; - idx < PCI_NUM_RESOURCES; - idx++) { - r = &dev->resource[idx]; - if (!r->flags) - continue; - if (!r->start || - pci_claim_bridge_resource(dev, idx) < 0) { - printk(KERN_ERR "PCI:" - " Cannot allocate resource" - " region %d of bridge %s\n", - idx, pci_name(dev)); - /* Something is wrong with the region. - * Invalidate the resource to prevent - * child resource allocations in this - * range. */ - r->start = r->end = 0; - r->flags = 0; - } - } - } - pcibios_allocate_bus_resources(&bus->children); - } -} - -static void __init pcibios_allocate_resources(int pass) -{ - struct pci_dev *dev = NULL; - int idx, disabled; - u16 command; - struct resource *r; - - for_each_pci_dev(dev) { - pci_read_config_word(dev, PCI_COMMAND, &command); - for (idx = 0; idx < 6; idx++) { - r = &dev->resource[idx]; - if (r->parent) /* Already allocated */ - continue; - if (!r->start) /* Address not assigned */ - continue; - if (r->flags & IORESOURCE_IO) - disabled = !(command & PCI_COMMAND_IO); - else - disabled = !(command & PCI_COMMAND_MEMORY); - if (pass == disabled) { - DBG("PCI[%s]: Resource %08lx-%08lx" - " (f=%lx, d=%d, p=%d)\n", - pci_name(dev), r->start, r->end, r->flags, - disabled, pass); - if (pci_claim_resource(dev, idx) < 0) { - printk(KERN_ERR "PCI:" - " Cannot allocate resource" - " region %d of device %s\n", - idx, pci_name(dev)); - /* We'll assign a new address later */ - r->end -= r->start; - r->start = 0; - } - } - } - if (!pass) { - r = &dev->resource[PCI_ROM_RESOURCE]; - if (r->flags & IORESOURCE_ROM_ENABLE) { - /* Turn the ROM off, leave the resource region, - * but keep it unregistered. */ - u32 reg; - DBG("PCI: Switching off ROM of %s\n", - pci_name(dev)); - r->flags &= ~IORESOURCE_ROM_ENABLE; - pci_read_config_dword( - dev, dev->rom_base_reg, ®); - pci_write_config_dword( - dev, dev->rom_base_reg, - reg & ~PCI_ROM_ADDRESS_ENABLE); - } - } - } -} - -static int __init pcibios_assign_resources(void) -{ - struct pci_dev *dev = NULL; - struct resource *r; - - /* Try to use BIOS settings for ROMs, otherwise let - pci_assign_unassigned_resources() allocate the new - addresses. */ - for_each_pci_dev(dev) { - r = &dev->resource[PCI_ROM_RESOURCE]; - if (!r->flags || !r->start) - continue; - if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) { - r->end -= r->start; - r->start = 0; - } - } - - pci_assign_unassigned_resources(); - - return 0; -} - -fs_initcall(pcibios_assign_resources); - -void __init pcibios_resource_survey(void) -{ - DBG("PCI: Allocating resources\n"); - pcibios_allocate_bus_resources(&pci_root_buses); - pcibios_allocate_resources(0); - pcibios_allocate_resources(1); -} diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.h b/arch/mn10300/unit-asb2305/pci-asb2305.h deleted file mode 100644 index 0667f613b023..000000000000 --- a/arch/mn10300/unit-asb2305/pci-asb2305.h +++ /dev/null @@ -1,65 +0,0 @@ -/* ASB2305 Arch-specific PCI declarations - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * Derived from: arch/i386/kernel/pci-i386.h: (c) 1999 Martin Mares - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _PCI_ASB2305_H -#define _PCI_ASB2305_H - -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -extern unsigned int pci_probe; - -/* pci-asb2305.c */ - -extern void pcibios_resource_survey(void); - -/* pci.c */ - -extern struct pci_ops *pci_root_ops; - -/* pci-irq.c */ - -struct irq_info { - u8 bus, devfn; /* Bus, device and function */ - struct { - u8 link; /* IRQ line ID, chipset dependent, - * 0=not routed */ - u16 bitmap; /* Available IRQs */ - } __attribute__((packed)) irq[4]; - u8 slot; /* Slot number, 0=onboard */ - u8 rfu; -} __attribute__((packed)); - -struct irq_routing_table { - u32 signature; /* PIRQ_SIGNATURE should be here */ - u16 version; /* PIRQ_VERSION */ - u16 size; /* Table size in bytes */ - u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ - u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ - u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */ - u32 miniport_data; /* Crap */ - u8 rfu[11]; - u8 checksum; /* Modulo 256 checksum must give zero */ - struct irq_info slots[0]; -} __attribute__((packed)); - -extern unsigned int pcibios_irq_mask; - -extern void pcibios_irq_init(void); -extern void pcibios_fixup_irqs(void); -extern void pcibios_enable_irq(struct pci_dev *dev); - -#endif /* PCI_ASB2305_H */ diff --git a/arch/mn10300/unit-asb2305/pci-irq.c b/arch/mn10300/unit-asb2305/pci-irq.c deleted file mode 100644 index fcb28ceb824d..000000000000 --- a/arch/mn10300/unit-asb2305/pci-irq.c +++ /dev/null @@ -1,46 +0,0 @@ -/* PCI IRQ routing on the MN103E010 based ASB2305 - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - * - * This is simple: All PCI interrupts route through the CPU's XIRQ1 pin [IRQ 35] - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include "pci-asb2305.h" - -void __init pcibios_irq_init(void) -{ -} - -void __init pcibios_fixup_irqs(void) -{ - struct pci_dev *dev = NULL; - u8 line, pin; - - for_each_pci_dev(dev) { - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - if (pin) { - dev->irq = XIRQ1; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, - dev->irq); - } - pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line); - } -} - -void pcibios_enable_irq(struct pci_dev *dev) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); -} diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c deleted file mode 100644 index 3dfe2d31c67b..000000000000 --- a/arch/mn10300/unit-asb2305/pci.c +++ /dev/null @@ -1,505 +0,0 @@ -/* ASB2305 PCI support - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * Derived from arch/i386/kernel/pci-pc.c - * (c) 1999--2000 Martin Mares - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "pci-asb2305.h" - -unsigned int pci_probe = 1; - -struct pci_ops *pci_root_ops; - -/* - * The accessible PCI window does not cover the entire CPU address space, but - * there are devices we want to access outside of that window, so we need to - * insert specific PCI bus resources instead of using the platform-level bus - * resources directly for the PCI root bus. - * - * These are configured and inserted by pcibios_init(). - */ -static struct resource pci_ioport_resource = { - .name = "PCI IO", - .start = 0xbe000000, - .end = 0xbe03ffff, - .flags = IORESOURCE_IO, -}; - -static struct resource pci_iomem_resource = { - .name = "PCI mem", - .start = 0xb8000000, - .end = 0xbbffffff, - .flags = IORESOURCE_MEM, -}; - -/* - * Functions for accessing PCI configuration space - */ - -#define CONFIG_CMD(bus, devfn, where) \ - (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) - -#define MEM_PAGING_REG (*(volatile __u32 *) 0xBFFFFFF4) -#define CONFIG_ADDRESS (*(volatile __u32 *) 0xBFFFFFF8) -#define CONFIG_DATAL(X) (*(volatile __u32 *) 0xBFFFFFFC) -#define CONFIG_DATAW(X) (*(volatile __u16 *) (0xBFFFFFFC + ((X) & 2))) -#define CONFIG_DATAB(X) (*(volatile __u8 *) (0xBFFFFFFC + ((X) & 3))) - -#define BRIDGEREGB(X) (*(volatile __u8 *) (0xBE040000 + (X))) -#define BRIDGEREGW(X) (*(volatile __u16 *) (0xBE040000 + (X))) -#define BRIDGEREGL(X) (*(volatile __u32 *) (0xBE040000 + (X))) - -static inline int __query(const struct pci_bus *bus, unsigned int devfn) -{ -#if 0 - return bus->number == 0 && (devfn == PCI_DEVFN(0, 0)); - return bus->number == 1; - return bus->number == 0 && - (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0)); -#endif - return 1; -} - -/* - * - */ -static int pci_ampci_read_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u32 *_value) -{ - u32 rawval, value; - - if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { - value = BRIDGEREGB(where); - __pcbdebug("=> %02hx", &BRIDGEREGL(where), value); - } else { - CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where); - rawval = CONFIG_ADDRESS; - value = CONFIG_DATAB(where); - if (__query(bus, devfn)) - __pcidebug("=> %02hx", bus, devfn, where, value); - } - - *_value = value; - return PCIBIOS_SUCCESSFUL; -} - -static int pci_ampci_read_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u32 *_value) -{ - u32 rawval, value; - - if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { - value = BRIDGEREGW(where); - __pcbdebug("=> %04hx", &BRIDGEREGL(where), value); - } else { - CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where); - rawval = CONFIG_ADDRESS; - value = CONFIG_DATAW(where); - if (__query(bus, devfn)) - __pcidebug("=> %04hx", bus, devfn, where, value); - } - - *_value = value; - return PCIBIOS_SUCCESSFUL; -} - -static int pci_ampci_read_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 *_value) -{ - u32 rawval, value; - - if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { - value = BRIDGEREGL(where); - __pcbdebug("=> %08x", &BRIDGEREGL(where), value); - } else { - CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where); - rawval = CONFIG_ADDRESS; - value = CONFIG_DATAL(where); - if (__query(bus, devfn)) - __pcidebug("=> %08x", bus, devfn, where, value); - } - - *_value = value; - return PCIBIOS_SUCCESSFUL; -} - -static int pci_ampci_write_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 value) -{ - u32 rawval; - - if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { - __pcbdebug("<= %02x", &BRIDGEREGB(where), value); - BRIDGEREGB(where) = value; - } else { - if (bus->number == 0 && - (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0)) - ) - __pcidebug("<= %02x", bus, devfn, where, value); - CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where); - rawval = CONFIG_ADDRESS; - CONFIG_DATAB(where) = value; - } - return PCIBIOS_SUCCESSFUL; -} - -static int pci_ampci_write_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 value) -{ - u32 rawval; - - if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { - __pcbdebug("<= %04hx", &BRIDGEREGW(where), value); - BRIDGEREGW(where) = value; - } else { - if (__query(bus, devfn)) - __pcidebug("<= %04hx", bus, devfn, where, value); - CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where); - rawval = CONFIG_ADDRESS; - CONFIG_DATAW(where) = value; - } - return PCIBIOS_SUCCESSFUL; -} - -static int pci_ampci_write_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 value) -{ - u32 rawval; - - if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) { - __pcbdebug("<= %08x", &BRIDGEREGL(where), value); - BRIDGEREGL(where) = value; - } else { - if (__query(bus, devfn)) - __pcidebug("<= %08x", bus, devfn, where, value); - CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where); - rawval = CONFIG_ADDRESS; - CONFIG_DATAL(where) = value; - } - return PCIBIOS_SUCCESSFUL; -} - -static int pci_ampci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - switch (size) { - case 1: - return pci_ampci_read_config_byte(bus, devfn, where, val); - case 2: - return pci_ampci_read_config_word(bus, devfn, where, val); - case 4: - return pci_ampci_read_config_dword(bus, devfn, where, val); - default: - BUG(); - return -EOPNOTSUPP; - } -} - -static int pci_ampci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - switch (size) { - case 1: - return pci_ampci_write_config_byte(bus, devfn, where, val); - case 2: - return pci_ampci_write_config_word(bus, devfn, where, val); - case 4: - return pci_ampci_write_config_dword(bus, devfn, where, val); - default: - BUG(); - return -EOPNOTSUPP; - } -} - -static struct pci_ops pci_direct_ampci = { - .read = pci_ampci_read_config, - .write = pci_ampci_write_config, -}; - -/* - * Before we decide to use direct hardware access mechanisms, we try to do some - * trivial checks to ensure it at least _seems_ to be working -- we just test - * whether bus 00 contains a host bridge (this is similar to checking - * techniques used in XFree86, but ours should be more reliable since we - * attempt to make use of direct access hints provided by the PCI BIOS). - * - * This should be close to trivial, but it isn't, because there are buggy - * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. - */ -static int __init pci_sanity_check(struct pci_ops *o) -{ - struct pci_bus bus; /* Fake bus and device */ - u32 x; - - bus.number = 0; - - if ((!o->read(&bus, 0, PCI_CLASS_DEVICE, 2, &x) && - (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) || - (!o->read(&bus, 0, PCI_VENDOR_ID, 2, &x) && - (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ))) - return 1; - - printk(KERN_ERR "PCI: Sanity check failed\n"); - return 0; -} - -static int __init pci_check_direct(void) -{ - unsigned long flags; - - local_irq_save(flags); - - /* - * Check if access works. - */ - if (pci_sanity_check(&pci_direct_ampci)) { - local_irq_restore(flags); - printk(KERN_INFO "PCI: Using configuration ampci\n"); - request_mem_region(0xBE040000, 256, "AMPCI bridge"); - request_mem_region(0xBFFFFFF4, 12, "PCI ampci"); - request_mem_region(0xBC000000, 32 * 1024 * 1024, "PCI SRAM"); - return 0; - } - - local_irq_restore(flags); - return -ENODEV; -} - -static void pcibios_fixup_device_resources(struct pci_dev *dev) -{ - int idx; - - if (!dev->bus) - return; - - for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) { - struct resource *r = &dev->resource[idx]; - - if (!r->flags || r->parent || !r->start) - continue; - - pci_claim_resource(dev, idx); - } -} - -static void pcibios_fixup_bridge_resources(struct pci_dev *dev) -{ - int idx; - - if (!dev->bus) - return; - - for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) { - struct resource *r = &dev->resource[idx]; - - if (!r->flags || r->parent || !r->start) - continue; - - pci_claim_bridge_resource(dev, idx); - } -} - -/* - * Called after each bus is probed, but before its children - * are examined. - */ -void pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_dev *dev; - - if (bus->self) { - pci_read_bridge_bases(bus); - pcibios_fixup_bridge_resources(bus->self); - } - - list_for_each_entry(dev, &bus->devices, bus_list) - pcibios_fixup_device_resources(dev); -} - -/* - * Initialization. Try all known PCI access methods. Note that we support - * using both PCI BIOS and direct access: in such cases, we use I/O ports - * to access config space, but we still keep BIOS order of cards to be - * compatible with 2.0.X. This should go away some day. - */ -static int __init pcibios_init(void) -{ - resource_size_t io_offset, mem_offset; - LIST_HEAD(resources); - struct pci_bus *bus; - - ioport_resource.start = 0xA0000000; - ioport_resource.end = 0xDFFFFFFF; - iomem_resource.start = 0xA0000000; - iomem_resource.end = 0xDFFFFFFF; - - if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0) - panic("Unable to insert PCI IOMEM resource\n"); - if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0) - panic("Unable to insert PCI IOPORT resource\n"); - - if (!pci_probe) - return 0; - - if (pci_check_direct() < 0) { - printk(KERN_WARNING "PCI: No PCI bus detected\n"); - return 0; - } - - printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", - MEM_PAGING_REG); - - io_offset = pci_ioport_resource.start - - (pci_ioport_resource.start & 0x00ffffff); - mem_offset = pci_iomem_resource.start - - ((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG); - - pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset); - pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset); - bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources); - if (!bus) - return 0; - - pcibios_irq_init(); - pcibios_fixup_irqs(); - pcibios_resource_survey(); - pci_bus_add_devices(bus); - return 0; -} - -arch_initcall(pcibios_init); - -char *__init pcibios_setup(char *str) -{ - if (!strcmp(str, "off")) { - pci_probe = 0; - return NULL; - } - - return str; -} - -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - int err; - - err = pci_enable_resources(dev, mask); - if (err == 0) - pcibios_enable_irq(dev); - return err; -} - -/* - * disable the ethernet chipset - */ -static void __init unit_disable_pcnet(struct pci_bus *bus, struct pci_ops *o) -{ - u32 x; - - bus->number = 0; - - o->read (bus, PCI_DEVFN(2, 0), PCI_VENDOR_ID, 4, &x); - o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x); - x |= PCI_COMMAND_MASTER | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_SERR | PCI_COMMAND_PARITY; - o->write(bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, x); - o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x); - o->write(bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, 0x00030001); - o->read (bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, &x); - -#define RDP (*(volatile u32 *) 0xBE030010) -#define RAP (*(volatile u32 *) 0xBE030014) -#define __set_RAP(X) do { RAP = (X); x = RAP; } while (0) -#define __set_RDP(X) do { RDP = (X); x = RDP; } while (0) -#define __get_RDP() ({ RDP & 0xffff; }) - - __set_RAP(0); - __set_RDP(0x0004); /* CSR0 = STOP */ - - __set_RAP(88); /* check CSR88 indicates an Am79C973 */ - BUG_ON(__get_RDP() != 0x5003); - - for (x = 0; x < 100; x++) - asm volatile("nop"); - - __set_RDP(0x0004); /* CSR0 = STOP */ -} - -/* - * initialise the unit hardware - */ -asmlinkage void __init unit_pci_init(void) -{ - struct pci_bus bus; /* Fake bus and device */ - struct pci_ops *o = &pci_direct_ampci; - u32 x; - - set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_PCI_IRQ_LEVEL)); - - memset(&bus, 0, sizeof(bus)); - - MEM_PAGING_REG = 0xE8000000; - - /* we need to set up the bridge _now_ or we won't be able to access the - * PCI config registers - */ - BRIDGEREGW(PCI_COMMAND) |= - PCI_COMMAND_SERR | PCI_COMMAND_PARITY | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER; - BRIDGEREGW(PCI_STATUS) = 0xF800; - BRIDGEREGB(PCI_LATENCY_TIMER) = 0x10; - BRIDGEREGL(PCI_BASE_ADDRESS_0) = 0x80000000; - BRIDGEREGB(PCI_INTERRUPT_LINE) = 1; - BRIDGEREGL(0x48) = 0x98000000; /* AMPCI base addr */ - BRIDGEREGB(0x41) = 0x00; /* secondary bus - * number */ - BRIDGEREGB(0x42) = 0x01; /* subordinate bus - * number */ - BRIDGEREGB(0x44) = 0x01; - BRIDGEREGL(0x50) = 0x00000001; - BRIDGEREGL(0x58) = 0x00001002; - BRIDGEREGL(0x5C) = 0x00000011; - - /* we also need to set up the PCI-PCI bridge */ - bus.number = 0; - - /* IO: 0x00000000-0x00020000 */ - o->read (&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, &x); - x |= PCI_COMMAND_MASTER | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_SERR | PCI_COMMAND_PARITY; - o->write(&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, x); - - o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x); - o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x); - o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x); - o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x); - - o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, 0x01); - o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x); - o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, 0x00020000); - o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x); - o->write(&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, 0xEBB0EA00); - o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x); - o->write(&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, 0xE9F0E800); - o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x); - - unit_disable_pcnet(&bus, o); -} diff --git a/arch/mn10300/unit-asb2305/unit-init.c b/arch/mn10300/unit-asb2305/unit-init.c deleted file mode 100644 index bc4adfaf815c..000000000000 --- a/arch/mn10300/unit-asb2305/unit-init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* ASB2305 Initialisation - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * initialise some of the unit hardware before gdbstub is set up - */ -asmlinkage void __init unit_init(void) -{ -#ifndef CONFIG_GDBSTUB_ON_TTYSx - /* set the 16550 interrupt line to level 3 if not being used for GDB */ -#ifdef CONFIG_EXT_SERIAL_IRQ_LEVEL - set_intr_level(XIRQ0, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL)); -#endif -#endif /* CONFIG_GDBSTUB_ON_TTYSx */ -} - -/* - * initialise the rest of the unit hardware after gdbstub is ready - */ -void __init unit_setup(void) -{ -#ifdef CONFIG_PCI - unit_pci_init(); -#endif -} - -/* - * initialise the external interrupts used by a unit of this type - */ -void __init unit_init_IRQ(void) -{ - unsigned int extnum; - - for (extnum = 0; extnum < NR_XIRQS; extnum++) { - switch (GET_XIRQ_TRIGGER(extnum)) { - case XIRQ_TRIGGER_HILEVEL: - case XIRQ_TRIGGER_LOWLEVEL: - mn10300_set_lateack_irq_type(XIRQ2IRQ(extnum)); - break; - default: - break; - } - } -} diff --git a/arch/mn10300/unit-asb2364/Makefile b/arch/mn10300/unit-asb2364/Makefile deleted file mode 100644 index b3263ecfc4ff..000000000000 --- a/arch/mn10300/unit-asb2364/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Makefile for the linux kernel. -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# -# Note 2! The CFLAGS definitions are now in the main makefile... - -obj-y := unit-init.o leds.o irq-fpga.o - -obj-$(CONFIG_SMSC911X) += smsc911x.o diff --git a/arch/mn10300/unit-asb2364/include/unit/clock.h b/arch/mn10300/unit-asb2364/include/unit/clock.h deleted file mode 100644 index d34ac9a7508b..000000000000 --- a/arch/mn10300/unit-asb2364/include/unit/clock.h +++ /dev/null @@ -1,29 +0,0 @@ -/* clock.h: unit-specific clocks - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * Modified by Matsushita Electric Industrial Co., Ltd. - * Modifications: - * 23-Feb-2007 MEI Add define for watchdog timer. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_CLOCK_H -#define _ASM_UNIT_CLOCK_H - -#ifndef __ASSEMBLY__ - -#define MN10300_IOCLK 100000000UL /* for DDR800 */ -/*#define MN10300_IOCLK 83333333UL */ /* for DDR667 */ -#define MN10300_IOBCLK MN10300_IOCLK /* IOBCLK is equal to IOCLK */ - -#endif /* !__ASSEMBLY__ */ - -#define MN10300_WDCLK 27000000UL - -#endif /* _ASM_UNIT_CLOCK_H */ diff --git a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h deleted file mode 100644 index 2901ed344b3d..000000000000 --- a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* ASB2364 FPGA registers - */ - -#ifndef _ASM_UNIT_FPGA_REGS_H -#define _ASM_UNIT_FPGA_REGS_H - -#include - -#ifdef __KERNEL__ - -#define ASB2364_FPGA_REG_RESET_LAN __SYSREG(0xa9001300, u16) -#define ASB2364_FPGA_REG_RESET_UART __SYSREG(0xa9001304, u16) -#define ASB2364_FPGA_REG_RESET_I2C __SYSREG(0xa9001308, u16) -#define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16) -#define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16) - -#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16) -#define ASB2364_FPGA_REG_IRQ_LAN ASB2364_FPGA_REG_IRQ(0) -#define ASB2364_FPGA_REG_IRQ_UART ASB2364_FPGA_REG_IRQ(1) -#define ASB2364_FPGA_REG_IRQ_I2C ASB2364_FPGA_REG_IRQ(2) -#define ASB2364_FPGA_REG_IRQ_USB ASB2364_FPGA_REG_IRQ(3) -#define ASB2364_FPGA_REG_IRQ_FPGA ASB2364_FPGA_REG_IRQ(5) - -#define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16) -#define ASB2364_FPGA_REG_MASK_LAN ASB2364_FPGA_REG_MASK(0) -#define ASB2364_FPGA_REG_MASK_UART ASB2364_FPGA_REG_MASK(1) -#define ASB2364_FPGA_REG_MASK_I2C ASB2364_FPGA_REG_MASK(2) -#define ASB2364_FPGA_REG_MASK_USB ASB2364_FPGA_REG_MASK(3) -#define ASB2364_FPGA_REG_MASK_FPGA ASB2364_FPGA_REG_MASK(5) - -#define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16) -#define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16) -#define ASB2364_FPGA_REG_CPLD6_SET1 __SYSREG(0xa9002600, u16) -#define ASB2364_FPGA_REG_CPLD6_SET2 __SYSREG(0xa9002604, u16) -#define ASB2364_FPGA_REG_CPLD7_SET1 __SYSREG(0xa9002700, u16) -#define ASB2364_FPGA_REG_CPLD7_SET2 __SYSREG(0xa9002704, u16) -#define ASB2364_FPGA_REG_CPLD8_SET1 __SYSREG(0xa9002800, u16) -#define ASB2364_FPGA_REG_CPLD8_SET2 __SYSREG(0xa9002804, u16) -#define ASB2364_FPGA_REG_CPLD9_SET1 __SYSREG(0xa9002900, u16) -#define ASB2364_FPGA_REG_CPLD9_SET2 __SYSREG(0xa9002904, u16) -#define ASB2364_FPGA_REG_CPLD10_SET1 __SYSREG(0xa9002a00, u16) -#define ASB2364_FPGA_REG_CPLD10_SET2 __SYSREG(0xa9002a04, u16) - -#define SyncExBus() \ - do { \ - unsigned short w; \ - w = *(volatile short *)0xa9000000; \ - } while (0) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_UNIT_FPGA_REGS_H */ diff --git a/arch/mn10300/unit-asb2364/include/unit/irq.h b/arch/mn10300/unit-asb2364/include/unit/irq.h deleted file mode 100644 index 786148e46565..000000000000 --- a/arch/mn10300/unit-asb2364/include/unit/irq.h +++ /dev/null @@ -1,35 +0,0 @@ -/* ASB2364 FPGA irq numbers - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#ifndef _UNIT_IRQ_H -#define _UNIT_IRQ_H - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_SMP -#define NR_CPU_IRQS GxICR_NUM_EXT_IRQS -#else -#define NR_CPU_IRQS GxICR_NUM_IRQS -#endif - -enum { - FPGA_LAN_IRQ = NR_CPU_IRQS, - FPGA_UART_IRQ, - FPGA_I2C_IRQ, - FPGA_USB_IRQ, - FPGA_RESERVED_IRQ, - FPGA_FPGA_IRQ, - NR_IRQS -}; - -extern void __init irq_fpga_init(void); - -#endif /* !__ASSEMBLY__ */ -#endif /* _UNIT_IRQ_H */ diff --git a/arch/mn10300/unit-asb2364/include/unit/leds.h b/arch/mn10300/unit-asb2364/include/unit/leds.h deleted file mode 100644 index 03a3933ad323..000000000000 --- a/arch/mn10300/unit-asb2364/include/unit/leds.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Unit-specific leds - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_LEDS_H -#define _ASM_UNIT_LEDS_H - -#include -#include -#include - -#define MN10300_USE_7SEGLEDS 0 - -#define ASB2364_7SEGLEDS __SYSREG(0xA9001630, u32) - -/* - * use the 7-segment LEDs to indicate states - */ - -#if MN10300_USE_7SEGLEDS -/* flip the 7-segment LEDs between "Gdb-" and "----" */ -#define mn10300_set_gdbleds(ONOFF) \ - do { \ - ASB2364_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f; \ - } while (0) -#else -#define mn10300_set_gdbleds(ONOFF) do {} while (0) -#endif - -#if MN10300_USE_7SEGLEDS -/* indicate double-fault by displaying "db-f" on the LEDs */ -#define mn10300_set_dbfleds \ - mov 0x43077f1d,d0 ; \ - mov d0,(ASB2364_7SEGLEDS) -#else -#define mn10300_set_dbfleds -#endif - -#ifndef __ASSEMBLY__ -extern void peripheral_leds_display_exception(enum exception_code); -extern void peripheral_leds_led_chase(void); -extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int); -extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int); -extern void debug_to_serial(const char *, int); -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_UNIT_LEDS_H */ diff --git a/arch/mn10300/unit-asb2364/include/unit/serial.h b/arch/mn10300/unit-asb2364/include/unit/serial.h deleted file mode 100644 index 92f224a97efc..000000000000 --- a/arch/mn10300/unit-asb2364/include/unit/serial.h +++ /dev/null @@ -1,151 +0,0 @@ -/* Unit-specific 8250 serial ports - * - * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _ASM_UNIT_SERIAL_H -#define _ASM_UNIT_SERIAL_H - -#include -#include -#include -#include - -#define SERIAL_PORT0_BASE_ADDRESS 0xA8200000 - -#define SERIAL_IRQ XIRQ1 /* single serial (TL16C550C) (Lo) */ - -/* - * The ASB2364 has an 12.288 MHz clock - * for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD (12288000 / 16) - -/* - * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports - */ -#ifndef CONFIG_GDBSTUB_ON_TTYSx - -#define SERIAL_PORT_DFNS \ - { \ - .baud_base = BASE_BAUD, \ - .irq = SERIAL_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \ - .iomem_reg_shift = 1, \ - .io_type = SERIAL_IO_MEM, \ - }, - -#ifndef __ASSEMBLY__ - -static inline void __debug_to_serial(const char *p, int n) -{ -} - -#endif /* !__ASSEMBLY__ */ - -#else /* CONFIG_GDBSTUB_ON_TTYSx */ - -#define SERIAL_PORT_DFNS /* stolen by gdb-stub */ - -#if defined(CONFIG_GDBSTUB_ON_TTYS0) -#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 2, u8) -#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 2, u8) -#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 2, u8) -#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 2, u8) -#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8) -#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 2, u8) -#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8) -#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8) -#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 2, u8) -#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 2, u8) -#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 2, u8) -#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 2, u8) -#define GDBPORT_SERIAL_IRQ SERIAL_IRQ - -#elif defined(CONFIG_GDBSTUB_ON_TTYS1) -#error The ASB2364 does not have a /dev/ttyS1 -#endif - -#ifndef __ASSEMBLY__ - -static inline void __debug_to_serial(const char *p, int n) -{ - char ch; - -#define LSR_WAIT_FOR(STATE) \ - do {} while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE)) -#define FLOWCTL_QUERY(LINE) \ - ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; }) -#define FLOWCTL_WAIT_FOR(LINE) \ - do {} while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) -#define FLOWCTL_CLEAR(LINE) \ - do { GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; } while (0) -#define FLOWCTL_SET(LINE) \ - do { GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; } while (0) - - FLOWCTL_SET(DTR); - - for (; n > 0; n--) { - LSR_WAIT_FOR(THRE); - FLOWCTL_WAIT_FOR(CTS); - - ch = *p++; - if (ch == 0x0a) { - GDBPORT_SERIAL_TX = 0x0d; - LSR_WAIT_FOR(THRE); - FLOWCTL_WAIT_FOR(CTS); - } - GDBPORT_SERIAL_TX = ch; - } - - FLOWCTL_CLEAR(DTR); -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* CONFIG_GDBSTUB_ON_TTYSx */ - -#define SERIAL_INITIALIZE \ -do { \ - /* release reset */ \ - ASB2364_FPGA_REG_RESET_UART = 0x0001; \ - SyncExBus(); \ -} while (0) - -#define SERIAL_CHECK_INTERRUPT \ -do { \ - if ((ASB2364_FPGA_REG_IRQ_UART & 0x0001) == 0x0001) { \ - return IRQ_NONE; \ - } \ -} while (0) - -#define SERIAL_CLEAR_INTERRUPT \ -do { \ - ASB2364_FPGA_REG_IRQ_UART = 0x0001; \ - SyncExBus(); \ -} while (0) - -#define SERIAL_SET_INT_MASK \ -do { \ - ASB2364_FPGA_REG_MASK_UART = 0x0001; \ - SyncExBus(); \ -} while (0) - -#define SERIAL_CLEAR_INT_MASK \ -do { \ - ASB2364_FPGA_REG_MASK_UART = 0x0000; \ - SyncExBus(); \ -} while (0) - -#endif /* _ASM_UNIT_SERIAL_H */ diff --git a/arch/mn10300/unit-asb2364/include/unit/smsc911x.h b/arch/mn10300/unit-asb2364/include/unit/smsc911x.h deleted file mode 100644 index 4c1ede535fa9..000000000000 --- a/arch/mn10300/unit-asb2364/include/unit/smsc911x.h +++ /dev/null @@ -1,171 +0,0 @@ -/* Support for the SMSC911x NIC - * - * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_UNIT_SMSC911X_H -#define _ASM_UNIT_SMSC911X_H - -#include -#include -#include - -#define MN10300_USE_EXT_EEPROM - - -#define SMSC911X_BASE 0xA8000000UL -#define SMSC911X_BASE_END 0xA8000100UL -#define SMSC911X_IRQ FPGA_LAN_IRQ - -/* - * Allow the FPGA to be initialised by the SMSC911x driver - */ -#undef SMSC_INITIALIZE -#define SMSC_INITIALIZE() \ -do { \ - /* release reset */ \ - ASB2364_FPGA_REG_RESET_LAN = 0x0001; \ - SyncExBus(); \ -} while (0) - -#ifdef MN10300_USE_EXT_EEPROM -#include -#include - -#define EEPROM_ADDRESS 0xA0 -#define MAC_OFFSET 0x0008 -#define USE_IIC_CH 0 /* 0 or 1 */ -#define IIC_OFFSET (0x80000 * USE_IIC_CH) -#define IIC_DTRM __SYSREG(0xd8400000 + IIC_OFFSET, u32) -#define IIC_DREC __SYSREG(0xd8400004 + IIC_OFFSET, u32) -#define IIC_MYADD __SYSREG(0xd8400008 + IIC_OFFSET, u32) -#define IIC_CLK __SYSREG(0xd840000c + IIC_OFFSET, u32) -#define IIC_BRST __SYSREG(0xd8400010 + IIC_OFFSET, u32) -#define IIC_HOLD __SYSREG(0xd8400014 + IIC_OFFSET, u32) -#define IIC_BSTS __SYSREG(0xd8400018 + IIC_OFFSET, u32) -#define IIC_ICR __SYSREG(0xd4000080 + 4 * USE_IIC_CH, u16) - -#define IIC_CLK_PLS ((unsigned short)(MN10300_IOCLK / 100000 - 1)) -#define IIC_CLK_LOW ((unsigned short)(IIC_CLK_PLS / 2)) - -#define SYS_IIC_DTRM_Bit_STA ((unsigned short)0x0400) -#define SYS_IIC_DTRM_Bit_STO ((unsigned short)0x0200) -#define SYS_IIC_DTRM_Bit_ACK ((unsigned short)0x0100) -#define SYS_IIC_DTRM_Bit_DATA ((unsigned short)0x00FF) - -static inline void POLL_INT_REQ(volatile u16 *icr) -{ - unsigned long flags; - u16 tmp; - - while (!(*icr & GxICR_REQUEST)) - ; - flags = arch_local_cli_save(); - tmp = *icr; - *icr = (tmp & GxICR_LEVEL) | GxICR_DETECT; - tmp = *icr; - arch_local_irq_restore(flags); -} - -/* - * Implement the SMSC911x hook for MAC address retrieval - */ -#undef smsc_get_mac -static inline int smsc_get_mac(struct net_device *dev) -{ - unsigned char *mac_buf = dev->dev_addr; - int i; - unsigned short value; - unsigned int data; - int mac_length = 6; - int check; - u16 orig_gicr, tmp; - unsigned long flags; - - /* save original GnICR and clear GnICR.IE */ - flags = arch_local_cli_save(); - orig_gicr = IIC_ICR; - IIC_ICR = orig_gicr & GxICR_LEVEL; - tmp = IIC_ICR; - arch_local_irq_restore(flags); - - IIC_MYADD = 0x00000008; - IIC_CLK = (IIC_CLK_LOW << 16) + (IIC_CLK_PLS); - /* bus hung recovery */ - - while (1) { - check = 0; - for (i = 0; i < 3; i++) { - if ((IIC_BSTS & 0x00000003) == 0x00000003) - check++; - udelay(3); - } - - if (check == 3) { - IIC_BRST = 0x00000003; - break; - } else { - for (i = 0; i < 3; i++) { - IIC_BRST = 0x00000002; - udelay(8); - IIC_BRST = 0x00000003; - udelay(8); - } - } - } - - IIC_BRST = 0x00000002; - IIC_BRST = 0x00000003; - - value = SYS_IIC_DTRM_Bit_STA | SYS_IIC_DTRM_Bit_ACK; - value |= (((unsigned short)EEPROM_ADDRESS & SYS_IIC_DTRM_Bit_DATA) | - (unsigned short)0x0000); - IIC_DTRM = value; - POLL_INT_REQ(&IIC_ICR); - - /** send offset of MAC address in EEPROM **/ - IIC_DTRM = (unsigned char)((MAC_OFFSET & 0xFF00) >> 8); - POLL_INT_REQ(&IIC_ICR); - - IIC_DTRM = (unsigned char)(MAC_OFFSET & 0x00FF); - POLL_INT_REQ(&IIC_ICR); - - udelay(1000); - - value = SYS_IIC_DTRM_Bit_STA; - value |= (((unsigned short)EEPROM_ADDRESS & SYS_IIC_DTRM_Bit_DATA) | - (unsigned short)0x0001); - IIC_DTRM = value; - POLL_INT_REQ(&IIC_ICR); - - IIC_DTRM = 0x00000000; - while (mac_length > 0) { - POLL_INT_REQ(&IIC_ICR); - - data = IIC_DREC; - mac_length--; - if (mac_length == 0) - value = 0x00000300; /* stop IIC bus */ - else if (mac_length == 1) - value = 0x00000100; /* no ack */ - else - value = 0x00000000; /* ack */ - IIC_DTRM = value; - *mac_buf++ = (unsigned char)(data & 0xff); - } - - /* restore GnICR.LV and GnICR.IE */ - flags = arch_local_cli_save(); - IIC_ICR = (orig_gicr & (GxICR_LEVEL | GxICR_ENABLE)); - tmp = IIC_ICR; - arch_local_irq_restore(flags); - - return 0; -} -#endif /* MN10300_USE_EXT_EEPROM */ -#endif /* _ASM_UNIT_SMSC911X_H */ diff --git a/arch/mn10300/unit-asb2364/include/unit/timex.h b/arch/mn10300/unit-asb2364/include/unit/timex.h deleted file mode 100644 index 42f32db75087..000000000000 --- a/arch/mn10300/unit-asb2364/include/unit/timex.h +++ /dev/null @@ -1,155 +0,0 @@ -/* timex.h: MN2WS0038 architecture timer specifications - * - * Copyright (C) 2002, 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef _ASM_UNIT_TIMEX_H -#define _ASM_UNIT_TIMEX_H - -#include -#include -#include - -/* - * jiffies counter specifications - */ - -#define TMJCBR_MAX 0xffffff /* 24bit */ -#define TMJCIRQ TMTIRQ - -#ifndef __ASSEMBLY__ - -#define MN10300_SRC_IOBCLK MN10300_IOBCLK - -#ifndef HZ -# error HZ undeclared. -#endif /* !HZ */ - -#define MN10300_JCCLK (MN10300_SRC_IOBCLK) -#define MN10300_TSCCLK (MN10300_SRC_IOBCLK) - -#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ) -#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ) - -/* Check bit width of MTM interval value that sets base register */ -#if (MN10300_JC_PER_HZ - 1) > TMJCBR_MAX -# error MTM tick timer interval value is overflow. -#endif - -static inline void stop_jiffies_counter(void) -{ - u16 tmp; - TMTMD = 0; - tmp = TMTMD; -} - -static inline void reload_jiffies_counter(u32 cnt) -{ - u32 tmp; - - TMTBR = cnt; - tmp = TMTBR; - - TMTMD = TMTMD_TMTLDE; - TMTMD = TMTMD_TMTCNE; - tmp = TMTMD; -} - -#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS) && \ - !defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) -/* - * If we aren't using broadcasting, each core needs its own event timer. - * Since CPU0 uses the tick timer which is 24-bits, we use timer 4 & 5 - * cascaded to 32-bits for CPU1 (but only really use 24-bits to match - * CPU0). - */ - -#define TMJC1IRQ TM5IRQ - -static inline void stop_jiffies_counter1(void) -{ - u8 tmp; - TM4MD = 0; - TM5MD = 0; - tmp = TM4MD; - tmp = TM5MD; -} - -static inline void reload_jiffies_counter1(u32 cnt) -{ - u32 tmp; - - TM45BR = cnt; - tmp = TM45BR; - - TM4MD = TM4MD_INIT_COUNTER; - tmp = TM4MD; - - TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_INIT_COUNTER; - TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_COUNT_ENABLE; - tmp = TM5MD; - - TM4MD = TM4MD_COUNT_ENABLE; - tmp = TM4MD; -} -#endif /* CONFIG_SMP&GENERIC_CLOCKEVENTS&!GENERIC_CLOCKEVENTS_BROADCAST */ - -#endif /* !__ASSEMBLY__ */ - - -/* - * timestamp counter specifications - */ -#define TMTSCBR_MAX 0xffffffff - -#ifndef __ASSEMBLY__ - -/* Use 32-bit timestamp counter */ -#define TMTSCMD TMSMD -#define TMTSCBR TMSBR -#define TMTSCBC TMSBC -#define TMTSCICR TMSICR - -static inline void startup_timestamp_counter(void) -{ - u32 sync; - - /* set up TMS(Timestamp) 32bit timer register to count real time - * - count down from 4Gig-1 to 0 and wrap at IOBCLK rate - */ - - TMTSCBR = TMTSCBR_MAX; - sync = TMTSCBR; - - TMTSCICR = 0; - sync = TMTSCICR; - - TMTSCMD = TMTMD_TMTLDE; - TMTSCMD = TMTMD_TMTCNE; - sync = TMTSCMD; -} - -static inline void shutdown_timestamp_counter(void) -{ - TMTSCMD = 0; -} - -/* - * we use a cascaded pair of 16-bit down-counting timers to count I/O - * clock cycles for the purposes of time keeping - */ -typedef unsigned long cycles_t; - -static inline cycles_t read_timestamp_counter(void) -{ - return (cycles_t)~TMTSCBC; -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_UNIT_TIMEX_H */ diff --git a/arch/mn10300/unit-asb2364/irq-fpga.c b/arch/mn10300/unit-asb2364/irq-fpga.c deleted file mode 100644 index 073e2ccc4a44..000000000000 --- a/arch/mn10300/unit-asb2364/irq-fpga.c +++ /dev/null @@ -1,108 +0,0 @@ -/* ASB2364 FPGA interrupt multiplexing - * - * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#include -#include -#include -#include - -/* - * FPGA PIC operations - */ -static void asb2364_fpga_mask(struct irq_data *d) -{ - ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001; - SyncExBus(); -} - -static void asb2364_fpga_ack(struct irq_data *d) -{ - ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001; - SyncExBus(); -} - -static void asb2364_fpga_mask_ack(struct irq_data *d) -{ - ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001; - SyncExBus(); -} - -static void asb2364_fpga_unmask(struct irq_data *d) -{ - ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0000; - SyncExBus(); -} - -static struct irq_chip asb2364_fpga_pic = { - .name = "fpga", - .irq_ack = asb2364_fpga_ack, - .irq_mask = asb2364_fpga_mask, - .irq_mask_ack = asb2364_fpga_mask_ack, - .irq_unmask = asb2364_fpga_unmask, -}; - -/* - * FPGA PIC interrupt handler - */ -static irqreturn_t fpga_interrupt(int irq, void *_mask) -{ - if ((ASB2364_FPGA_REG_IRQ_LAN & 0x0001) != 0x0001) - generic_handle_irq(FPGA_LAN_IRQ); - if ((ASB2364_FPGA_REG_IRQ_UART & 0x0001) != 0x0001) - generic_handle_irq(FPGA_UART_IRQ); - if ((ASB2364_FPGA_REG_IRQ_I2C & 0x0001) != 0x0001) - generic_handle_irq(FPGA_I2C_IRQ); - if ((ASB2364_FPGA_REG_IRQ_USB & 0x0001) != 0x0001) - generic_handle_irq(FPGA_USB_IRQ); - if ((ASB2364_FPGA_REG_IRQ_FPGA & 0x0001) != 0x0001) - generic_handle_irq(FPGA_FPGA_IRQ); - - return IRQ_HANDLED; -} - -/* - * Define an interrupt action for each FPGA PIC output - */ -static struct irqaction fpga_irq[] = { - [0] = { - .handler = fpga_interrupt, - .flags = IRQF_SHARED, - .name = "fpga", - }, -}; - -/* - * Initialise the FPGA's PIC - */ -void __init irq_fpga_init(void) -{ - int irq; - - ASB2364_FPGA_REG_MASK_LAN = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_MASK_UART = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_MASK_I2C = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_MASK_USB = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_MASK_FPGA = 0x0001; - SyncExBus(); - - for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++) - irq_set_chip_and_handler(irq, &asb2364_fpga_pic, - handle_level_irq); - - /* the FPGA drives the XIRQ1 input on the CPU PIC */ - setup_irq(XIRQ1, &fpga_irq[0]); -} diff --git a/arch/mn10300/unit-asb2364/leds.c b/arch/mn10300/unit-asb2364/leds.c deleted file mode 100644 index 1ff830c372b3..000000000000 --- a/arch/mn10300/unit-asb2364/leds.c +++ /dev/null @@ -1,98 +0,0 @@ -/* leds.c: ASB2364 peripheral 7seg LEDs x4 support - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#if MN10300_USE_7SEGLEDS -static const u8 asb2364_led_hex_tbl[16] = { - 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0, - 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c -}; - -static const u32 asb2364_led_chase_tbl[6] = { - ~0x02020202, /* top - segA */ - ~0x04040404, /* right top - segB */ - ~0x08080808, /* right bottom - segC */ - ~0x10101010, /* bottom - segD */ - ~0x20202020, /* left bottom - segE */ - ~0x40404040, /* left top - segF */ -}; - -static unsigned asb2364_led_chase; - -void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points) -{ - u32 leds; - - leds = asb2364_led_hex_tbl[(val/1000) % 10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[(val/100) % 10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[(val/10) % 10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[val % 10]; - leds |= points^0x01010101; - - ASB2364_7SEGLEDS = leds; -} - -void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points) -{ - u32 leds; - - leds = asb2364_led_hex_tbl[(val/1000) % 10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[(val/100) % 10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[(val/10) % 10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[val % 10]; - leds |= points^0x01010101; - - ASB2364_7SEGLEDS = leds; -} - -/* display triple horizontal bar and exception code */ -void peripheral_leds_display_exception(enum exception_code code) -{ - u32 leds; - - leds = asb2364_led_hex_tbl[(code/0x100) % 0x10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[(code/0x10) % 0x10]; - leds <<= 8; - leds |= asb2364_led_hex_tbl[code % 0x10]; - leds |= 0x6d010101; - - ASB2364_7SEGLEDS = leds; -} - -void peripheral_leds_led_chase(void) -{ - ASB2364_7SEGLEDS = asb2364_led_chase_tbl[asb2364_led_chase]; - asb2364_led_chase++; - if (asb2364_led_chase >= 6) - asb2364_led_chase = 0; -} -#else /* MN10300_USE_7SEGLEDS */ -void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points) { } -void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points) { } -void peripheral_leds_display_exception(enum exception_code code) { } -void peripheral_leds_led_chase(void) { } -#endif /* MN10300_USE_7SEGLEDS */ diff --git a/arch/mn10300/unit-asb2364/smsc911x.c b/arch/mn10300/unit-asb2364/smsc911x.c deleted file mode 100644 index 544a73e94c81..000000000000 --- a/arch/mn10300/unit-asb2364/smsc911x.c +++ /dev/null @@ -1,58 +0,0 @@ -/* Specification for the SMSC911x NIC - * - * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd. - * All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_32BIT, -}; - -static struct resource smsc911x_resources[] = { - [0] = { - .start = SMSC911X_BASE, - .end = SMSC911X_BASE_END, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SMSC911X_IRQ, - .end = SMSC911X_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - } -}; - -/* - * add platform devices - */ -static int __init unit_device_init(void) -{ - platform_device_register(&smsc911x_device); - return 0; -} - -device_initcall(unit_device_init); diff --git a/arch/mn10300/unit-asb2364/unit-init.c b/arch/mn10300/unit-asb2364/unit-init.c deleted file mode 100644 index 6359b41ce7e9..000000000000 --- a/arch/mn10300/unit-asb2364/unit-init.c +++ /dev/null @@ -1,132 +0,0 @@ -/* ASB2364 initialisation - * - * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TTYS0_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8) -#define LAN_IRQ_CFG __SYSREG(SMSC911X_BASE + 0x54, u32) -#define LAN_INT_EN __SYSREG(SMSC911X_BASE + 0x5c, u32) - -/* - * initialise some of the unit hardware before gdbstub is set up - */ -asmlinkage void __init unit_init(void) -{ - /* Make sure we aren't going to get unexpected interrupts */ - TTYS0_SERIAL_IER = 0; - SC0RXICR = 0; - SC0TXICR = 0; - SC1RXICR = 0; - SC1TXICR = 0; - SC2RXICR = 0; - SC2TXICR = 0; - - /* Attempt to reset the FPGA attached peripherals */ - ASB2364_FPGA_REG_RESET_LAN = 0x0000; - SyncExBus(); - ASB2364_FPGA_REG_RESET_UART = 0x0000; - SyncExBus(); - ASB2364_FPGA_REG_RESET_I2C = 0x0000; - SyncExBus(); - ASB2364_FPGA_REG_RESET_USB = 0x0000; - SyncExBus(); - ASB2364_FPGA_REG_RESET_AV = 0x0000; - SyncExBus(); - - /* set up the external interrupts */ - - /* XIRQ[0]: NAND RXBY */ - /* SET_XIRQ_TRIGGER(0, XIRQ_TRIGGER_LOWLEVEL); */ - - /* XIRQ[1]: LAN, UART, I2C, USB, PCI, FPGA */ - SET_XIRQ_TRIGGER(1, XIRQ_TRIGGER_LOWLEVEL); - - /* XIRQ[2]: Extend Slot 1-9 */ - /* SET_XIRQ_TRIGGER(2, XIRQ_TRIGGER_LOWLEVEL); */ - -#if defined(CONFIG_EXT_SERIAL_IRQ_LEVEL) && \ - defined(CONFIG_ETHERNET_IRQ_LEVEL) && \ - (CONFIG_EXT_SERIAL_IRQ_LEVEL != CONFIG_ETHERNET_IRQ_LEVEL) -# error CONFIG_EXT_SERIAL_IRQ_LEVEL != CONFIG_ETHERNET_IRQ_LEVEL -#endif - -#if defined(CONFIG_EXT_SERIAL_IRQ_LEVEL) - set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL)); -#elif defined(CONFIG_ETHERNET_IRQ_LEVEL) - set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_ETHERNET_IRQ_LEVEL)); -#endif -} - -/* - * initialise the rest of the unit hardware after gdbstub is ready - */ -asmlinkage void __init unit_setup(void) -{ - /* Release the reset on the SMSC911X so that it is ready by the time we - * need it */ - ASB2364_FPGA_REG_RESET_LAN = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_RESET_UART = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_RESET_I2C = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_RESET_USB = 0x0001; - SyncExBus(); - ASB2364_FPGA_REG_RESET_AV = 0x0001; - SyncExBus(); - - /* Make sure the ethernet chipset isn't going to give us an interrupt - * storm from stuff it was doing pre-reset */ - LAN_IRQ_CFG = 0; - LAN_INT_EN = 0; -} - -/* - * initialise the external interrupts used by a unit of this type - */ -void __init unit_init_IRQ(void) -{ - unsigned int extnum; - - for (extnum = 0 ; extnum < NR_XIRQS ; extnum++) { - switch (GET_XIRQ_TRIGGER(extnum)) { - /* LEVEL triggered interrupts should be made - * post-ACK'able as they hold their lines until - * serviced - */ - case XIRQ_TRIGGER_HILEVEL: - case XIRQ_TRIGGER_LOWLEVEL: - mn10300_set_lateack_irq_type(XIRQ2IRQ(extnum)); - break; - default: - break; - } - } - -#define IRQCTL __SYSREG(0xd5000090, u32) - IRQCTL |= 0x02; - - irq_fpga_init(); -} diff --git a/crypto/sha3_generic.c b/crypto/sha3_generic.c index ded148783303..264ec12c0b9c 100644 --- a/crypto/sha3_generic.c +++ b/crypto/sha3_generic.c @@ -21,7 +21,7 @@ #include /* - * On some 32-bit architectures (mn10300 and h8300), GCC ends up using + * On some 32-bit architectures (h8300), GCC ends up using * over 1 KB of stack if we inline the round calculation into the loop * in keccakf(). On the other hand, on 64-bit architectures with plenty * of [64-bit wide] general purpose registers, not inlining it severely diff --git a/drivers/input/joystick/analog.c b/drivers/input/joystick/analog.c index c868a878c84f..be1b4921f22a 100644 --- a/drivers/input/joystick/analog.c +++ b/drivers/input/joystick/analog.c @@ -163,7 +163,7 @@ static unsigned int get_time_pit(void) #define GET_TIME(x) do { x = (unsigned int)rdtsc(); } while (0) #define DELTA(x,y) ((y)-(x)) #define TIME_NAME "TSC" -#elif defined(__alpha__) || defined(CONFIG_MN10300) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) || defined(CONFIG_TILE) +#elif defined(__alpha__) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) || defined(CONFIG_TILE) #define GET_TIME(x) do { x = get_cycles(); } while (0) #define DELTA(x,y) ((y)-(x)) #define TIME_NAME "get_cycles" diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig index 4c2f612e4414..948603e9b905 100644 --- a/drivers/net/ethernet/smsc/Kconfig +++ b/drivers/net/ethernet/smsc/Kconfig @@ -6,7 +6,7 @@ config NET_VENDOR_SMSC bool "SMC (SMSC)/Western Digital devices" default y depends on ARM || ARM64 || ATARI_ETHERNAT || BLACKFIN || COLDFIRE || \ - ISA || M32R || MAC || MIPS || MN10300 || NIOS2 || PCI || \ + ISA || M32R || MAC || MIPS || NIOS2 || PCI || \ PCMCIA || SUPERH || XTENSA || H8300 ---help--- If you have a network (Ethernet) card belonging to this class, say Y. @@ -38,7 +38,7 @@ config SMC91X select MII depends on !OF || GPIOLIB depends on ARM || ARM64 || ATARI_ETHERNAT || BLACKFIN || COLDFIRE || \ - M32R || MIPS || MN10300 || NIOS2 || SUPERH || XTENSA || H8300 + M32R || MIPS || NIOS2 || SUPERH || XTENSA || H8300 ---help--- This is a driver for SMC's 91x series of Ethernet chipsets, including the SMC91C94 and the SMC91C111. Say Y if you want it @@ -77,7 +77,7 @@ config SMC911X tristate "SMSC LAN911[5678] support" select CRC32 select MII - depends on (ARM || SUPERH || MN10300) + depends on (ARM || SUPERH) ---help--- This is a driver for SMSC's LAN911x series of Ethernet chipsets including the new LAN9115, LAN9116, LAN9117, and LAN9118. diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h index 08b17adf0a65..8445622dc4cf 100644 --- a/drivers/net/ethernet/smsc/smc91x.h +++ b/drivers/net/ethernet/smsc/smc91x.h @@ -162,14 +162,6 @@ static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg, #define RPC_LSA_DEFAULT RPC_LED_TX_RX #define RPC_LSB_DEFAULT RPC_LED_100_10 -#elif defined(CONFIG_MN10300) - -/* - * MN10300/AM33 configuration - */ - -#include - #elif defined(CONFIG_ATARI) #define SMC_CAN_USE_8BIT 1 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 8ab5f0a5d323..be5a3dc99c11 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -868,7 +868,7 @@ comment "Platform RTC drivers" config RTC_DRV_CMOS tristate "PC-style 'CMOS'" - depends on X86 || ARM || M32R || PPC || MIPS || SPARC64 || MN10300 + depends on X86 || ARM || M32R || PPC || MIPS || SPARC64 default y if X86 select RTC_MC146818_LIB help diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index 9dca53df3584..f7c0f72abb56 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -711,7 +711,7 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) address_space = 64; #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ || defined(__sparc__) || defined(__mips__) \ - || defined(__powerpc__) || defined(CONFIG_MN10300) + || defined(__powerpc__) address_space = 128; #else #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. diff --git a/drivers/staging/speakup/Kconfig b/drivers/staging/speakup/Kconfig index 7e8037e230b8..efd6f4560d3e 100644 --- a/drivers/staging/speakup/Kconfig +++ b/drivers/staging/speakup/Kconfig @@ -1,7 +1,7 @@ menu "Speakup console speech" config SPEAKUP - depends on VT && !MN10300 + depends on VT tristate "Speakup core" ---help--- This is the Speakup screen reader. Think of it as a diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index 7f1f1fbcef9e..005ed87c8216 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig @@ -7,7 +7,7 @@ menu "Console display driver support" config VGA_CONSOLE bool "VGA text console" if EXPERT || !X86 depends on !4xx && !PPC_8xx && !SPARC && !M68K && !PARISC && !FRV && \ - !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !CRIS && \ + !SUPERH && !BLACKFIN && !AVR32 && !CRIS && \ (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) && \ !ARM64 && !ARC && !MICROBLAZE && !OPENRISC default y diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h index 3f38eb03649c..abe6dd9ca2a8 100644 --- a/include/asm-generic/atomic.h +++ b/include/asm-generic/atomic.h @@ -2,8 +2,6 @@ * Generic C implementation of atomic counter operations. Usable on * UP systems only. Do not include in machine independent code. * - * Originally implemented for MN10300. - * * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) * diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h index fe297b599b0a..29458bbb2fa0 100644 --- a/include/asm-generic/barrier.h +++ b/include/asm-generic/barrier.h @@ -1,5 +1,5 @@ /* - * Generic barrier definitions, originally based on MN10300 definitions. + * Generic barrier definitions. * * It should be possible to use these on really simple architectures, * but it serves more as a starting point for new ports. diff --git a/include/asm-generic/exec.h b/include/asm-generic/exec.h index 567766b0074a..32c0a216f576 100644 --- a/include/asm-generic/exec.h +++ b/include/asm-generic/exec.h @@ -1,4 +1,4 @@ -/* Generic process execution definitions, based on MN10300 definitions. +/* Generic process execution definitions. * * It should be possible to use these on really simple architectures, * but it serves more as a starting point for new ports. diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b4531e3b2120..fe184b9bb6ea 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -1,4 +1,4 @@ -/* Generic I/O port emulation, based on MN10300 code +/* Generic I/O port emulation. * * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) diff --git a/include/asm-generic/pci_iomap.h b/include/asm-generic/pci_iomap.h index 854f96ad5ccb..d4f16dcc2ed7 100644 --- a/include/asm-generic/pci_iomap.h +++ b/include/asm-generic/pci_iomap.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* Generic I/O port emulation, based on MN10300 code +/* Generic I/O port emulation. * * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) diff --git a/include/asm-generic/switch_to.h b/include/asm-generic/switch_to.h index 052c4ac04fd5..986acc9d34bb 100644 --- a/include/asm-generic/switch_to.h +++ b/include/asm-generic/switch_to.h @@ -1,4 +1,4 @@ -/* Generic task switch macro wrapper, based on MN10300 definitions. +/* Generic task switch macro wrapper. * * It should be possible to use these on really simple architectures, * but it serves more as a starting point for new ports. diff --git a/include/linux/ide.h b/include/linux/ide.h index 771989d25ef8..20d42c0d9fb6 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -25,7 +25,7 @@ #include #include -#if defined(CONFIG_CRIS) || defined(CONFIG_FRV) || defined(CONFIG_MN10300) +#if defined(CONFIG_CRIS) || defined(CONFIG_FRV) # define SUPPORT_VLB_SYNC 0 #else # define SUPPORT_VLB_SYNC 1 diff --git a/init/Kconfig b/init/Kconfig index e37f4b2a6445..a14bcc9724a2 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -1108,7 +1108,7 @@ config MULTIUSER config SGETMASK_SYSCALL bool "sgetmask/ssetmask syscalls support" if EXPERT - def_bool PARISC || MN10300 || BLACKFIN || M68K || PPC || MIPS || X86 || SPARC || CRIS || MICROBLAZE || SUPERH + def_bool PARISC || BLACKFIN || M68K || PPC || MIPS || X86 || SPARC || CRIS || MICROBLAZE || SUPERH ---help--- sys_sgetmask and sys_ssetmask are obsolete system calls no longer supported in libc but still enabled by default in some diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index d5964b051017..41ac9d294245 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -356,7 +356,7 @@ config FRAME_POINTER bool "Compile the kernel with frame pointers" depends on DEBUG_KERNEL && \ (CRIS || M68K || FRV || UML || \ - SUPERH || BLACKFIN || MN10300) || \ + SUPERH || BLACKFIN) || \ ARCH_WANT_FRAME_POINTERS default y if (DEBUG_INFO && UML) || ARCH_WANT_FRAME_POINTERS help diff --git a/lib/test_user_copy.c b/lib/test_user_copy.c index 4621db801b23..a6556f3364d1 100644 --- a/lib/test_user_copy.c +++ b/lib/test_user_copy.c @@ -35,7 +35,6 @@ !defined(CONFIG_M32R) && \ !defined(CONFIG_M68K) && \ !defined(CONFIG_MICROBLAZE) && \ - !defined(CONFIG_MN10300) && \ !defined(CONFIG_NIOS2) && \ !defined(CONFIG_PPC32) && \ !defined(CONFIG_SUPERH)) diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index 9917f928d0fd..4ff08a0ef5d3 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -840,8 +840,7 @@ static const char *const section_white_list[] = ".debug*", ".cranges", /* sh64 */ ".zdebug*", /* Compressed debug sections. */ - ".GCC-command-line", /* mn10300 */ - ".GCC.command.line", /* record-gcc-switches, non mn10300 */ + ".GCC.command.line", /* record-gcc-switches */ ".mdebug*", /* alpha, score, mips etc. */ ".pdr", /* alpha, score, mips etc. */ ".stab*", @@ -1104,8 +1103,8 @@ static const struct sectioncheck *section_mismatch( /* * The target section could be the SHT_NUL section when we're * handling relocations to un-resolved symbols, trying to match it - * doesn't make much sense and causes build failures on parisc and - * mn10300 architectures. + * doesn't make much sense and causes build failures on parisc + * architectures. */ if (*tosec == '\0') return NULL; diff --git a/tools/arch/mn10300/include/uapi/asm/bitsperlong.h b/tools/arch/mn10300/include/uapi/asm/bitsperlong.h deleted file mode 100644 index 6dc0bb0c13b2..000000000000 --- a/tools/arch/mn10300/include/uapi/asm/bitsperlong.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/tools/arch/mn10300/include/uapi/asm/mman.h b/tools/arch/mn10300/include/uapi/asm/mman.h deleted file mode 100644 index b9360639974f..000000000000 --- a/tools/arch/mn10300/include/uapi/asm/mman.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef TOOLS_ARCH_MN10300_UAPI_ASM_MMAN_FIX_H -#define TOOLS_ARCH_MN10300_UAPI_ASM_MMAN_FIX_H -#include -/* MAP_32BIT is undefined on mn10300, fix it for perf */ -#define MAP_32BIT 0 -#endif diff --git a/tools/include/asm-generic/barrier.h b/tools/include/asm-generic/barrier.h index 47b933903eaf..52278d880a61 100644 --- a/tools/include/asm-generic/barrier.h +++ b/tools/include/asm-generic/barrier.h @@ -1,7 +1,7 @@ /* * Copied from the kernel sources to tools/perf/: * - * Generic barrier definitions, originally based on MN10300 definitions. + * Generic barrier definitions. * * It should be possible to use these on really simple architectures, * but it serves more as a starting point for new ports. -- cgit v1.2.3 From 78b98e3c5a66d569a53b8f57b6a698f912794a43 Mon Sep 17 00:00:00 2001 From: Miroslav Lichvar Date: Fri, 9 Mar 2018 10:42:48 -0800 Subject: timekeeping/ntp: Determine the multiplier directly from NTP tick length When the length of the NTP tick changes significantly, e.g. when an NTP/PTP application is correcting the initial offset of the clock, a large value may accumulate in the NTP error before the multiplier converges to the correct value. It may then take a very long time (hours or even days) before the error is corrected. This causes the clock to have an unstable frequency offset, which has a negative impact on the stability of synchronization with precise time sources (e.g. NTP/PTP using hardware timestamping or the PTP KVM clock). Use division to determine the correct multiplier directly from the NTP tick length and replace the iterative approach. This removes the last major source of the NTP error. The only remaining source is now limited resolution of the multiplier, which is corrected by adding 1 to the multiplier when the system clock is behind the NTP time. Signed-off-by: Miroslav Lichvar Signed-off-by: John Stultz Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Prarit Bhargava Cc: Richard Cochran Cc: Stephen Boyd Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1520620971-9567-3-git-send-email-john.stultz@linaro.org Signed-off-by: Ingo Molnar --- include/linux/timekeeper_internal.h | 2 + kernel/time/timekeeping.c | 138 ++++++++++++------------------------ 2 files changed, 49 insertions(+), 91 deletions(-) (limited to 'include/linux') diff --git a/include/linux/timekeeper_internal.h b/include/linux/timekeeper_internal.h index d315c3d6725c..7acb953298a7 100644 --- a/include/linux/timekeeper_internal.h +++ b/include/linux/timekeeper_internal.h @@ -117,6 +117,8 @@ struct timekeeper { s64 ntp_error; u32 ntp_error_shift; u32 ntp_err_mult; + /* Flag used to avoid updating NTP twice with same second */ + u32 skip_second_overflow; #ifdef CONFIG_DEBUG_TIMEKEEPING long last_warning; /* diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index c1a0ac17336e..e11760121cb2 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -332,6 +332,7 @@ static void tk_setup_internals(struct timekeeper *tk, struct clocksource *clock) tk->tkr_mono.mult = clock->mult; tk->tkr_raw.mult = clock->mult; tk->ntp_err_mult = 0; + tk->skip_second_overflow = 0; } /* Timekeeper helper functions. */ @@ -1799,20 +1800,19 @@ device_initcall(timekeeping_init_ops); */ static __always_inline void timekeeping_apply_adjustment(struct timekeeper *tk, s64 offset, - bool negative, - int adj_scale) + s32 mult_adj) { s64 interval = tk->cycle_interval; - s32 mult_adj = 1; - if (negative) { - mult_adj = -mult_adj; + if (mult_adj == 0) { + return; + } else if (mult_adj == -1) { interval = -interval; - offset = -offset; + offset = -offset; + } else if (mult_adj != 1) { + interval *= mult_adj; + offset *= mult_adj; } - mult_adj <<= adj_scale; - interval <<= adj_scale; - offset <<= adj_scale; /* * So the following can be confusing. @@ -1873,85 +1873,35 @@ static __always_inline void timekeeping_apply_adjustment(struct timekeeper *tk, } /* - * Calculate the multiplier adjustment needed to match the frequency - * specified by NTP + * Adjust the timekeeper's multiplier to the correct frequency + * and also to reduce the accumulated error value. */ -static __always_inline void timekeeping_freqadjust(struct timekeeper *tk, - s64 offset) +static void timekeeping_adjust(struct timekeeper *tk, s64 offset) { - s64 interval = tk->cycle_interval; - s64 xinterval = tk->xtime_interval; - u32 base = tk->tkr_mono.clock->mult; - u32 max = tk->tkr_mono.clock->maxadj; - u32 cur_adj = tk->tkr_mono.mult; - s64 tick_error; - bool negative; - u32 adj_scale; - - /* Remove any current error adj from freq calculation */ - if (tk->ntp_err_mult) - xinterval -= tk->cycle_interval; - - tk->ntp_tick = ntp_tick_length(); - - /* Calculate current error per tick */ - tick_error = ntp_tick_length() >> tk->ntp_error_shift; - tick_error -= (xinterval + tk->xtime_remainder); - - /* Don't worry about correcting it if its small */ - if (likely((tick_error >= 0) && (tick_error <= interval))) - return; - - /* preserve the direction of correction */ - negative = (tick_error < 0); + u32 mult; - /* If any adjustment would pass the max, just return */ - if (negative && (cur_adj - 1) <= (base - max)) - return; - if (!negative && (cur_adj + 1) >= (base + max)) - return; /* - * Sort out the magnitude of the correction, but - * avoid making so large a correction that we go - * over the max adjustment. + * Determine the multiplier from the current NTP tick length. + * Avoid expensive division when the tick length doesn't change. */ - adj_scale = 0; - tick_error = abs(tick_error); - while (tick_error > interval) { - u32 adj = 1 << (adj_scale + 1); - - /* Check if adjustment gets us within 1 unit from the max */ - if (negative && (cur_adj - adj) <= (base - max)) - break; - if (!negative && (cur_adj + adj) >= (base + max)) - break; - - adj_scale++; - tick_error >>= 1; + if (likely(tk->ntp_tick == ntp_tick_length())) { + mult = tk->tkr_mono.mult - tk->ntp_err_mult; + } else { + tk->ntp_tick = ntp_tick_length(); + mult = div64_u64((tk->ntp_tick >> tk->ntp_error_shift) - + tk->xtime_remainder, tk->cycle_interval); } - /* scale the corrections */ - timekeeping_apply_adjustment(tk, offset, negative, adj_scale); -} + /* + * If the clock is behind the NTP time, increase the multiplier by 1 + * to catch up with it. If it's ahead and there was a remainder in the + * tick division, the clock will slow down. Otherwise it will stay + * ahead until the tick length changes to a non-divisible value. + */ + tk->ntp_err_mult = tk->ntp_error > 0 ? 1 : 0; + mult += tk->ntp_err_mult; -/* - * Adjust the timekeeper's multiplier to the correct frequency - * and also to reduce the accumulated error value. - */ -static void timekeeping_adjust(struct timekeeper *tk, s64 offset) -{ - /* Correct for the current frequency error */ - timekeeping_freqadjust(tk, offset); - - /* Next make a small adjustment to fix any cumulative error */ - if (!tk->ntp_err_mult && (tk->ntp_error > 0)) { - tk->ntp_err_mult = 1; - timekeeping_apply_adjustment(tk, offset, 0, 0); - } else if (tk->ntp_err_mult && (tk->ntp_error <= 0)) { - /* Undo any existing error adjustment */ - timekeeping_apply_adjustment(tk, offset, 1, 0); - tk->ntp_err_mult = 0; - } + timekeeping_apply_adjustment(tk, offset, mult - tk->tkr_mono.mult); if (unlikely(tk->tkr_mono.clock->maxadj && (abs(tk->tkr_mono.mult - tk->tkr_mono.clock->mult) @@ -1968,18 +1918,15 @@ static void timekeeping_adjust(struct timekeeper *tk, s64 offset) * in the code above, its possible the required corrective factor to * xtime_nsec could cause it to underflow. * - * Now, since we already accumulated the second, cannot simply roll - * the accumulated second back, since the NTP subsystem has been - * notified via second_overflow. So instead we push xtime_nsec forward - * by the amount we underflowed, and add that amount into the error. - * - * We'll correct this error next time through this function, when - * xtime_nsec is not as small. + * Now, since we have already accumulated the second and the NTP + * subsystem has been notified via second_overflow(), we need to skip + * the next update. */ if (unlikely((s64)tk->tkr_mono.xtime_nsec < 0)) { - s64 neg = -(s64)tk->tkr_mono.xtime_nsec; - tk->tkr_mono.xtime_nsec = 0; - tk->ntp_error += neg << tk->ntp_error_shift; + tk->tkr_mono.xtime_nsec += (u64)NSEC_PER_SEC << + tk->tkr_mono.shift; + tk->xtime_sec--; + tk->skip_second_overflow = 1; } } @@ -2002,6 +1949,15 @@ static inline unsigned int accumulate_nsecs_to_secs(struct timekeeper *tk) tk->tkr_mono.xtime_nsec -= nsecps; tk->xtime_sec++; + /* + * Skip NTP update if this second was accumulated before, + * i.e. xtime_nsec underflowed in timekeeping_adjust() + */ + if (unlikely(tk->skip_second_overflow)) { + tk->skip_second_overflow = 0; + continue; + } + /* Figure out if its a leap sec and apply if needed */ leap = second_overflow(tk->xtime_sec); if (unlikely(leap)) { @@ -2118,7 +2074,7 @@ void update_wall_time(void) shift--; } - /* correct the clock when NTP error is too big */ + /* Adjust the multiplier to correct NTP error */ timekeeping_adjust(tk, offset); /* -- cgit v1.2.3 From 00b4145298aeb05a2d110117ed18148cb21ebd14 Mon Sep 17 00:00:00 2001 From: Tom Zanussi Date: Mon, 15 Jan 2018 20:51:39 -0600 Subject: ring-buffer: Add interface for setting absolute time stamps Define a new function, tracing_set_time_stamp_abs(), which can be used to enable or disable the use of absolute timestamps rather than time deltas for a trace array. Only the interface is added here; a subsequent patch will add the underlying implementation. Link: http://lkml.kernel.org/r/ce96119de44c7fe0ee44786d15254e9b493040d3.1516069914.git.tom.zanussi@linux.intel.com Signed-off-by: Tom Zanussi Signed-off-by: Baohong Liu Signed-off-by: Steven Rostedt (VMware) --- include/linux/ring_buffer.h | 2 ++ kernel/trace/ring_buffer.c | 11 +++++++++++ kernel/trace/trace.c | 33 ++++++++++++++++++++++++++++++++- kernel/trace/trace.h | 3 +++ 4 files changed, 48 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h index 7d9eb39fa76a..025159e17e1b 100644 --- a/include/linux/ring_buffer.h +++ b/include/linux/ring_buffer.h @@ -178,6 +178,8 @@ void ring_buffer_normalize_time_stamp(struct ring_buffer *buffer, int cpu, u64 *ts); void ring_buffer_set_clock(struct ring_buffer *buffer, u64 (*clock)(void)); +void ring_buffer_set_time_stamp_abs(struct ring_buffer *buffer, bool abs); +bool ring_buffer_time_stamp_abs(struct ring_buffer *buffer); size_t ring_buffer_page_len(void *page); diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index dcf1c4dd3efe..2a03e069bbc6 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -488,6 +488,7 @@ struct ring_buffer { u64 (*clock)(void); struct rb_irq_work irq_work; + bool time_stamp_abs; }; struct ring_buffer_iter { @@ -1382,6 +1383,16 @@ void ring_buffer_set_clock(struct ring_buffer *buffer, buffer->clock = clock; } +void ring_buffer_set_time_stamp_abs(struct ring_buffer *buffer, bool abs) +{ + buffer->time_stamp_abs = abs; +} + +bool ring_buffer_time_stamp_abs(struct ring_buffer *buffer) +{ + return buffer->time_stamp_abs; +} + static void rb_reset_cpu(struct ring_buffer_per_cpu *cpu_buffer); static inline unsigned long rb_page_entries(struct buffer_page *bpage) diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 20a2300ae4e8..cba003f0362e 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -2269,7 +2269,7 @@ trace_event_buffer_lock_reserve(struct ring_buffer **current_rb, *current_rb = trace_file->tr->trace_buffer.buffer; - if ((trace_file->flags & + if (!ring_buffer_time_stamp_abs(*current_rb) && (trace_file->flags & (EVENT_FILE_FL_SOFT_DISABLED | EVENT_FILE_FL_FILTERED)) && (entry = this_cpu_read(trace_buffered_event))) { /* Try to use the per cpu buffer first */ @@ -6282,6 +6282,37 @@ static int tracing_clock_open(struct inode *inode, struct file *file) return ret; } +int tracing_set_time_stamp_abs(struct trace_array *tr, bool abs) +{ + int ret = 0; + + mutex_lock(&trace_types_lock); + + if (abs && tr->time_stamp_abs_ref++) + goto out; + + if (!abs) { + if (WARN_ON_ONCE(!tr->time_stamp_abs_ref)) { + ret = -EINVAL; + goto out; + } + + if (--tr->time_stamp_abs_ref) + goto out; + } + + ring_buffer_set_time_stamp_abs(tr->trace_buffer.buffer, abs); + +#ifdef CONFIG_TRACER_MAX_TRACE + if (tr->max_buffer.buffer) + ring_buffer_set_time_stamp_abs(tr->max_buffer.buffer, abs); +#endif + out: + mutex_unlock(&trace_types_lock); + + return ret; +} + struct ftrace_buffer_info { struct trace_iterator iter; void *spare; diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h index 2a6d0325a761..477341710ebf 100644 --- a/kernel/trace/trace.h +++ b/kernel/trace/trace.h @@ -273,6 +273,7 @@ struct trace_array { /* function tracing enabled */ int function_enabled; #endif + int time_stamp_abs_ref; }; enum { @@ -286,6 +287,8 @@ extern struct mutex trace_types_lock; extern int trace_array_get(struct trace_array *tr); extern void trace_array_put(struct trace_array *tr); +extern int tracing_set_time_stamp_abs(struct trace_array *tr, bool abs); + /* * The global tracer (top) should be the first trace array added, * but we check the flag anyway. -- cgit v1.2.3 From dc4e2801d400b0346fb281ce9cf010d611e2243c Mon Sep 17 00:00:00 2001 From: Tom Zanussi Date: Mon, 15 Jan 2018 20:51:40 -0600 Subject: ring-buffer: Redefine the unimplemented RINGBUF_TYPE_TIME_STAMP RINGBUF_TYPE_TIME_STAMP is defined but not used, and from what I can gather was reserved for something like an absolute timestamp feature for the ring buffer, if not a complete replacement of the current time_delta scheme. This code redefines RINGBUF_TYPE_TIME_STAMP to implement absolute time stamps. Another way to look at it is that it essentially forces extended time_deltas for all events. The motivation for doing this is to enable time_deltas that aren't dependent on previous events in the ring buffer, making it feasible to use the ring_buffer_event timetamps in a more random-access way, for purposes other than serial event printing. To set/reset this mode, use tracing_set_timestamp_abs() from the previous interface patch. Link: http://lkml.kernel.org/r/477b362dba1ce7fab9889a1a8e885a62c472f041.1516069914.git.tom.zanussi@linux.intel.com Signed-off-by: Tom Zanussi Signed-off-by: Steven Rostedt (VMware) --- include/linux/ring_buffer.h | 12 ++--- kernel/trace/ring_buffer.c | 104 ++++++++++++++++++++++++++++++++------------ 2 files changed, 83 insertions(+), 33 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h index 025159e17e1b..7cb84774c20d 100644 --- a/include/linux/ring_buffer.h +++ b/include/linux/ring_buffer.h @@ -34,10 +34,12 @@ struct ring_buffer_event { * array[0] = time delta (28 .. 59) * size = 8 bytes * - * @RINGBUF_TYPE_TIME_STAMP: Sync time stamp with external clock - * array[0] = tv_nsec - * array[1..2] = tv_sec - * size = 16 bytes + * @RINGBUF_TYPE_TIME_STAMP: Absolute timestamp + * Same format as TIME_EXTEND except that the + * value is an absolute timestamp, not a delta + * event.time_delta contains bottom 27 bits + * array[0] = top (28 .. 59) bits + * size = 8 bytes * * <= @RINGBUF_TYPE_DATA_TYPE_LEN_MAX: * Data record @@ -54,12 +56,12 @@ enum ring_buffer_type { RINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28, RINGBUF_TYPE_PADDING, RINGBUF_TYPE_TIME_EXTEND, - /* FIXME: RINGBUF_TYPE_TIME_STAMP not implemented */ RINGBUF_TYPE_TIME_STAMP, }; unsigned ring_buffer_event_length(struct ring_buffer_event *event); void *ring_buffer_event_data(struct ring_buffer_event *event); +u64 ring_buffer_event_time_stamp(struct ring_buffer_event *event); /* * ring_buffer_discard_commit will remove an event that has not diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 2a03e069bbc6..33073cdebb26 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -41,6 +41,8 @@ int ring_buffer_print_entry_header(struct trace_seq *s) RINGBUF_TYPE_PADDING); trace_seq_printf(s, "\ttime_extend : type == %d\n", RINGBUF_TYPE_TIME_EXTEND); + trace_seq_printf(s, "\ttime_stamp : type == %d\n", + RINGBUF_TYPE_TIME_STAMP); trace_seq_printf(s, "\tdata max type_len == %d\n", RINGBUF_TYPE_DATA_TYPE_LEN_MAX); @@ -140,12 +142,15 @@ int ring_buffer_print_entry_header(struct trace_seq *s) enum { RB_LEN_TIME_EXTEND = 8, - RB_LEN_TIME_STAMP = 16, + RB_LEN_TIME_STAMP = 8, }; #define skip_time_extend(event) \ ((struct ring_buffer_event *)((char *)event + RB_LEN_TIME_EXTEND)) +#define extended_time(event) \ + (event->type_len >= RINGBUF_TYPE_TIME_EXTEND) + static inline int rb_null_event(struct ring_buffer_event *event) { return event->type_len == RINGBUF_TYPE_PADDING && !event->time_delta; @@ -209,7 +214,7 @@ rb_event_ts_length(struct ring_buffer_event *event) { unsigned len = 0; - if (event->type_len == RINGBUF_TYPE_TIME_EXTEND) { + if (extended_time(event)) { /* time extends include the data event after it */ len = RB_LEN_TIME_EXTEND; event = skip_time_extend(event); @@ -231,7 +236,7 @@ unsigned ring_buffer_event_length(struct ring_buffer_event *event) { unsigned length; - if (event->type_len == RINGBUF_TYPE_TIME_EXTEND) + if (extended_time(event)) event = skip_time_extend(event); length = rb_event_length(event); @@ -248,7 +253,7 @@ EXPORT_SYMBOL_GPL(ring_buffer_event_length); static __always_inline void * rb_event_data(struct ring_buffer_event *event) { - if (event->type_len == RINGBUF_TYPE_TIME_EXTEND) + if (extended_time(event)) event = skip_time_extend(event); BUG_ON(event->type_len > RINGBUF_TYPE_DATA_TYPE_LEN_MAX); /* If length is in len field, then array[0] has the data */ @@ -275,6 +280,27 @@ EXPORT_SYMBOL_GPL(ring_buffer_event_data); #define TS_MASK ((1ULL << TS_SHIFT) - 1) #define TS_DELTA_TEST (~TS_MASK) +/** + * ring_buffer_event_time_stamp - return the event's extended timestamp + * @event: the event to get the timestamp of + * + * Returns the extended timestamp associated with a data event. + * An extended time_stamp is a 64-bit timestamp represented + * internally in a special way that makes the best use of space + * contained within a ring buffer event. This function decodes + * it and maps it to a straight u64 value. + */ +u64 ring_buffer_event_time_stamp(struct ring_buffer_event *event) +{ + u64 ts; + + ts = event->array[0]; + ts <<= TS_SHIFT; + ts += event->time_delta; + + return ts; +} + /* Flag when events were overwritten */ #define RB_MISSED_EVENTS (1 << 31) /* Missed count stored at end */ @@ -2217,12 +2243,15 @@ rb_move_tail(struct ring_buffer_per_cpu *cpu_buffer, /* Slow path, do not inline */ static noinline struct ring_buffer_event * -rb_add_time_stamp(struct ring_buffer_event *event, u64 delta) +rb_add_time_stamp(struct ring_buffer_event *event, u64 delta, bool abs) { - event->type_len = RINGBUF_TYPE_TIME_EXTEND; + if (abs) + event->type_len = RINGBUF_TYPE_TIME_STAMP; + else + event->type_len = RINGBUF_TYPE_TIME_EXTEND; - /* Not the first event on the page? */ - if (rb_event_index(event)) { + /* Not the first event on the page, or not delta? */ + if (abs || rb_event_index(event)) { event->time_delta = delta & TS_MASK; event->array[0] = delta >> TS_SHIFT; } else { @@ -2265,7 +2294,9 @@ rb_update_event(struct ring_buffer_per_cpu *cpu_buffer, * add it to the start of the resevered space. */ if (unlikely(info->add_timestamp)) { - event = rb_add_time_stamp(event, delta); + bool abs = ring_buffer_time_stamp_abs(cpu_buffer->buffer); + + event = rb_add_time_stamp(event, info->delta, abs); length -= RB_LEN_TIME_EXTEND; delta = 0; } @@ -2453,7 +2484,7 @@ static __always_inline void rb_end_commit(struct ring_buffer_per_cpu *cpu_buffer static inline void rb_event_discard(struct ring_buffer_event *event) { - if (event->type_len == RINGBUF_TYPE_TIME_EXTEND) + if (extended_time(event)) event = skip_time_extend(event); /* array[0] holds the actual length for the discarded event */ @@ -2497,10 +2528,11 @@ rb_update_write_stamp(struct ring_buffer_per_cpu *cpu_buffer, cpu_buffer->write_stamp = cpu_buffer->commit_page->page->time_stamp; else if (event->type_len == RINGBUF_TYPE_TIME_EXTEND) { - delta = event->array[0]; - delta <<= TS_SHIFT; - delta += event->time_delta; + delta = ring_buffer_event_time_stamp(event); cpu_buffer->write_stamp += delta; + } else if (event->type_len == RINGBUF_TYPE_TIME_STAMP) { + delta = ring_buffer_event_time_stamp(event); + cpu_buffer->write_stamp = delta; } else cpu_buffer->write_stamp += event->time_delta; } @@ -2680,7 +2712,7 @@ __rb_reserve_next(struct ring_buffer_per_cpu *cpu_buffer, * If this is the first commit on the page, then it has the same * timestamp as the page itself. */ - if (!tail) + if (!tail && !ring_buffer_time_stamp_abs(cpu_buffer->buffer)) info->delta = 0; /* See if we shot pass the end of this buffer page */ @@ -2757,8 +2789,11 @@ rb_reserve_next_event(struct ring_buffer *buffer, /* make sure this diff is calculated here */ barrier(); - /* Did the write stamp get updated already? */ - if (likely(info.ts >= cpu_buffer->write_stamp)) { + if (ring_buffer_time_stamp_abs(buffer)) { + info.delta = info.ts; + rb_handle_timestamp(cpu_buffer, &info); + } else /* Did the write stamp get updated already? */ + if (likely(info.ts >= cpu_buffer->write_stamp)) { info.delta = diff; if (unlikely(test_time_stamp(info.delta))) rb_handle_timestamp(cpu_buffer, &info); @@ -3440,14 +3475,13 @@ rb_update_read_stamp(struct ring_buffer_per_cpu *cpu_buffer, return; case RINGBUF_TYPE_TIME_EXTEND: - delta = event->array[0]; - delta <<= TS_SHIFT; - delta += event->time_delta; + delta = ring_buffer_event_time_stamp(event); cpu_buffer->read_stamp += delta; return; case RINGBUF_TYPE_TIME_STAMP: - /* FIXME: not implemented */ + delta = ring_buffer_event_time_stamp(event); + cpu_buffer->read_stamp = delta; return; case RINGBUF_TYPE_DATA: @@ -3471,14 +3505,13 @@ rb_update_iter_read_stamp(struct ring_buffer_iter *iter, return; case RINGBUF_TYPE_TIME_EXTEND: - delta = event->array[0]; - delta <<= TS_SHIFT; - delta += event->time_delta; + delta = ring_buffer_event_time_stamp(event); iter->read_stamp += delta; return; case RINGBUF_TYPE_TIME_STAMP: - /* FIXME: not implemented */ + delta = ring_buffer_event_time_stamp(event); + iter->read_stamp = delta; return; case RINGBUF_TYPE_DATA: @@ -3702,6 +3735,8 @@ rb_buffer_peek(struct ring_buffer_per_cpu *cpu_buffer, u64 *ts, struct buffer_page *reader; int nr_loops = 0; + if (ts) + *ts = 0; again: /* * We repeat when a time extend is encountered. @@ -3738,12 +3773,17 @@ rb_buffer_peek(struct ring_buffer_per_cpu *cpu_buffer, u64 *ts, goto again; case RINGBUF_TYPE_TIME_STAMP: - /* FIXME: not implemented */ + if (ts) { + *ts = ring_buffer_event_time_stamp(event); + ring_buffer_normalize_time_stamp(cpu_buffer->buffer, + cpu_buffer->cpu, ts); + } + /* Internal data, OK to advance */ rb_advance_reader(cpu_buffer); goto again; case RINGBUF_TYPE_DATA: - if (ts) { + if (ts && !(*ts)) { *ts = cpu_buffer->read_stamp + event->time_delta; ring_buffer_normalize_time_stamp(cpu_buffer->buffer, cpu_buffer->cpu, ts); @@ -3768,6 +3808,9 @@ rb_iter_peek(struct ring_buffer_iter *iter, u64 *ts) struct ring_buffer_event *event; int nr_loops = 0; + if (ts) + *ts = 0; + cpu_buffer = iter->cpu_buffer; buffer = cpu_buffer->buffer; @@ -3820,12 +3863,17 @@ rb_iter_peek(struct ring_buffer_iter *iter, u64 *ts) goto again; case RINGBUF_TYPE_TIME_STAMP: - /* FIXME: not implemented */ + if (ts) { + *ts = ring_buffer_event_time_stamp(event); + ring_buffer_normalize_time_stamp(cpu_buffer->buffer, + cpu_buffer->cpu, ts); + } + /* Internal data, OK to advance */ rb_advance_iter(iter); goto again; case RINGBUF_TYPE_DATA: - if (ts) { + if (ts && !(*ts)) { *ts = iter->read_stamp + event->time_delta; ring_buffer_normalize_time_stamp(buffer, cpu_buffer->cpu, ts); -- cgit v1.2.3 From 1ac4f51c0eb518e04ff3455f0c7d17ad9187eb27 Mon Sep 17 00:00:00 2001 From: Tom Zanussi Date: Mon, 15 Jan 2018 20:51:42 -0600 Subject: tracing: Give event triggers access to ring_buffer_event The ring_buffer event can provide a timestamp that may be useful to various triggers - pass it into the handlers for that purpose. Link: http://lkml.kernel.org/r/6de592683b59fa70ffa5d43d0109896623fc1367.1516069914.git.tom.zanussi@linux.intel.com Signed-off-by: Tom Zanussi Signed-off-by: Steven Rostedt (VMware) --- include/linux/trace_events.h | 14 ++++++----- kernel/trace/trace.h | 9 +++---- kernel/trace/trace_events_hist.c | 11 +++++---- kernel/trace/trace_events_trigger.c | 47 +++++++++++++++++++++++-------------- 4 files changed, 49 insertions(+), 32 deletions(-) (limited to 'include/linux') diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h index 8a1442c4e513..0cf48c61cc6d 100644 --- a/include/linux/trace_events.h +++ b/include/linux/trace_events.h @@ -430,11 +430,13 @@ enum event_trigger_type { extern int filter_match_preds(struct event_filter *filter, void *rec); -extern enum event_trigger_type event_triggers_call(struct trace_event_file *file, - void *rec); -extern void event_triggers_post_call(struct trace_event_file *file, - enum event_trigger_type tt, - void *rec); +extern enum event_trigger_type +event_triggers_call(struct trace_event_file *file, void *rec, + struct ring_buffer_event *event); +extern void +event_triggers_post_call(struct trace_event_file *file, + enum event_trigger_type tt, + void *rec, struct ring_buffer_event *event); bool trace_event_ignore_this_pid(struct trace_event_file *trace_file); @@ -454,7 +456,7 @@ trace_trigger_soft_disabled(struct trace_event_file *file) if (!(eflags & EVENT_FILE_FL_TRIGGER_COND)) { if (eflags & EVENT_FILE_FL_TRIGGER_MODE) - event_triggers_call(file, NULL); + event_triggers_call(file, NULL, NULL); if (eflags & EVENT_FILE_FL_SOFT_DISABLED) return true; if (eflags & EVENT_FILE_FL_PID_FILTER) diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h index 477341710ebf..99060f7eebbd 100644 --- a/kernel/trace/trace.h +++ b/kernel/trace/trace.h @@ -1294,7 +1294,7 @@ __event_trigger_test_discard(struct trace_event_file *file, unsigned long eflags = file->flags; if (eflags & EVENT_FILE_FL_TRIGGER_COND) - *tt = event_triggers_call(file, entry); + *tt = event_triggers_call(file, entry, event); if (test_bit(EVENT_FILE_FL_SOFT_DISABLED_BIT, &file->flags) || (unlikely(file->flags & EVENT_FILE_FL_FILTERED) && @@ -1331,7 +1331,7 @@ event_trigger_unlock_commit(struct trace_event_file *file, trace_buffer_unlock_commit(file->tr, buffer, event, irq_flags, pc); if (tt) - event_triggers_post_call(file, tt, entry); + event_triggers_post_call(file, tt, entry, event); } /** @@ -1364,7 +1364,7 @@ event_trigger_unlock_commit_regs(struct trace_event_file *file, irq_flags, pc, regs); if (tt) - event_triggers_post_call(file, tt, entry); + event_triggers_post_call(file, tt, entry, event); } #define FILTER_PRED_INVALID ((unsigned short)-1) @@ -1589,7 +1589,8 @@ extern int register_trigger_hist_enable_disable_cmds(void); */ struct event_trigger_ops { void (*func)(struct event_trigger_data *data, - void *rec); + void *rec, + struct ring_buffer_event *rbe); int (*init)(struct event_trigger_ops *ops, struct event_trigger_data *data); void (*free)(struct event_trigger_ops *ops, diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c index 712260e72be5..63a19123cf47 100644 --- a/kernel/trace/trace_events_hist.c +++ b/kernel/trace/trace_events_hist.c @@ -909,7 +909,8 @@ static inline void add_to_key(char *compound_key, void *key, memcpy(compound_key + key_field->offset, key, size); } -static void event_hist_trigger(struct event_trigger_data *data, void *rec) +static void event_hist_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { struct hist_trigger_data *hist_data = data->private_data; bool use_compound_key = (hist_data->n_keys > 1); @@ -1658,7 +1659,8 @@ __init int register_trigger_hist_cmd(void) } static void -hist_enable_trigger(struct event_trigger_data *data, void *rec) +hist_enable_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { struct enable_trigger_data *enable_data = data->private_data; struct event_trigger_data *test; @@ -1674,7 +1676,8 @@ hist_enable_trigger(struct event_trigger_data *data, void *rec) } static void -hist_enable_count_trigger(struct event_trigger_data *data, void *rec) +hist_enable_count_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { if (!data->count) return; @@ -1682,7 +1685,7 @@ hist_enable_count_trigger(struct event_trigger_data *data, void *rec) if (data->count != -1) (data->count)--; - hist_enable_trigger(data, rec); + hist_enable_trigger(data, rec, event); } static struct event_trigger_ops hist_enable_trigger_ops = { diff --git a/kernel/trace/trace_events_trigger.c b/kernel/trace/trace_events_trigger.c index 87411482a46f..632471692462 100644 --- a/kernel/trace/trace_events_trigger.c +++ b/kernel/trace/trace_events_trigger.c @@ -63,7 +63,8 @@ void trigger_data_free(struct event_trigger_data *data) * any trigger that should be deferred, ETT_NONE if nothing to defer. */ enum event_trigger_type -event_triggers_call(struct trace_event_file *file, void *rec) +event_triggers_call(struct trace_event_file *file, void *rec, + struct ring_buffer_event *event) { struct event_trigger_data *data; enum event_trigger_type tt = ETT_NONE; @@ -76,7 +77,7 @@ event_triggers_call(struct trace_event_file *file, void *rec) if (data->paused) continue; if (!rec) { - data->ops->func(data, rec); + data->ops->func(data, rec, event); continue; } filter = rcu_dereference_sched(data->filter); @@ -86,7 +87,7 @@ event_triggers_call(struct trace_event_file *file, void *rec) tt |= data->cmd_ops->trigger_type; continue; } - data->ops->func(data, rec); + data->ops->func(data, rec, event); } return tt; } @@ -108,7 +109,7 @@ EXPORT_SYMBOL_GPL(event_triggers_call); void event_triggers_post_call(struct trace_event_file *file, enum event_trigger_type tt, - void *rec) + void *rec, struct ring_buffer_event *event) { struct event_trigger_data *data; @@ -116,7 +117,7 @@ event_triggers_post_call(struct trace_event_file *file, if (data->paused) continue; if (data->cmd_ops->trigger_type & tt) - data->ops->func(data, rec); + data->ops->func(data, rec, event); } } EXPORT_SYMBOL_GPL(event_triggers_post_call); @@ -909,7 +910,8 @@ void set_named_trigger_data(struct event_trigger_data *data, } static void -traceon_trigger(struct event_trigger_data *data, void *rec) +traceon_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { if (tracing_is_on()) return; @@ -918,7 +920,8 @@ traceon_trigger(struct event_trigger_data *data, void *rec) } static void -traceon_count_trigger(struct event_trigger_data *data, void *rec) +traceon_count_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { if (tracing_is_on()) return; @@ -933,7 +936,8 @@ traceon_count_trigger(struct event_trigger_data *data, void *rec) } static void -traceoff_trigger(struct event_trigger_data *data, void *rec) +traceoff_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { if (!tracing_is_on()) return; @@ -942,7 +946,8 @@ traceoff_trigger(struct event_trigger_data *data, void *rec) } static void -traceoff_count_trigger(struct event_trigger_data *data, void *rec) +traceoff_count_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { if (!tracing_is_on()) return; @@ -1039,13 +1044,15 @@ static struct event_command trigger_traceoff_cmd = { #ifdef CONFIG_TRACER_SNAPSHOT static void -snapshot_trigger(struct event_trigger_data *data, void *rec) +snapshot_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { tracing_snapshot(); } static void -snapshot_count_trigger(struct event_trigger_data *data, void *rec) +snapshot_count_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { if (!data->count) return; @@ -1053,7 +1060,7 @@ snapshot_count_trigger(struct event_trigger_data *data, void *rec) if (data->count != -1) (data->count)--; - snapshot_trigger(data, rec); + snapshot_trigger(data, rec, event); } static int @@ -1141,13 +1148,15 @@ static __init int register_trigger_snapshot_cmd(void) { return 0; } #endif static void -stacktrace_trigger(struct event_trigger_data *data, void *rec) +stacktrace_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { trace_dump_stack(STACK_SKIP); } static void -stacktrace_count_trigger(struct event_trigger_data *data, void *rec) +stacktrace_count_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { if (!data->count) return; @@ -1155,7 +1164,7 @@ stacktrace_count_trigger(struct event_trigger_data *data, void *rec) if (data->count != -1) (data->count)--; - stacktrace_trigger(data, rec); + stacktrace_trigger(data, rec, event); } static int @@ -1217,7 +1226,8 @@ static __init void unregister_trigger_traceon_traceoff_cmds(void) } static void -event_enable_trigger(struct event_trigger_data *data, void *rec) +event_enable_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { struct enable_trigger_data *enable_data = data->private_data; @@ -1228,7 +1238,8 @@ event_enable_trigger(struct event_trigger_data *data, void *rec) } static void -event_enable_count_trigger(struct event_trigger_data *data, void *rec) +event_enable_count_trigger(struct event_trigger_data *data, void *rec, + struct ring_buffer_event *event) { struct enable_trigger_data *enable_data = data->private_data; @@ -1242,7 +1253,7 @@ event_enable_count_trigger(struct event_trigger_data *data, void *rec) if (data->count != -1) (data->count)--; - event_enable_trigger(data, rec); + event_enable_trigger(data, rec, event); } int event_enable_trigger_print(struct seq_file *m, -- cgit v1.2.3 From 8e012066fe0de5ff5be606836f9075511bce5604 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Wed, 7 Feb 2018 17:26:32 -0500 Subject: ring-buffer: Add nesting for adding events within events The ring-buffer code has recusion protection in case tracing ends up tracing itself, the ring-buffer will detect that it was called at the same context (normal, softirq, interrupt or NMI), and not continue to record the event. With the histogram synthetic events, they are called while tracing another event at the same context. The recusion protection triggers because it detects tracing at the same context and stops it. Add ring_buffer_nest_start() and ring_buffer_nest_end() that will notify the ring buffer that a trace is about to happen within another trace and that it is intended, and not to trigger the recursion blocking. Signed-off-by: Steven Rostedt (VMware) --- include/linux/ring_buffer.h | 3 +++ kernel/trace/ring_buffer.c | 57 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 57 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ring_buffer.h b/include/linux/ring_buffer.h index 7cb84774c20d..a0233edc0718 100644 --- a/include/linux/ring_buffer.h +++ b/include/linux/ring_buffer.h @@ -117,6 +117,9 @@ int ring_buffer_unlock_commit(struct ring_buffer *buffer, int ring_buffer_write(struct ring_buffer *buffer, unsigned long length, void *data); +void ring_buffer_nest_start(struct ring_buffer *buffer); +void ring_buffer_nest_end(struct ring_buffer *buffer); + struct ring_buffer_event * ring_buffer_peek(struct ring_buffer *buffer, int cpu, u64 *ts, unsigned long *lost_events); diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 33073cdebb26..a2fd3893cc02 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -477,6 +477,7 @@ struct ring_buffer_per_cpu { struct buffer_page *reader_page; unsigned long lost_events; unsigned long last_overrun; + unsigned long nest; local_t entries_bytes; local_t entries; local_t overrun; @@ -2624,10 +2625,10 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer) bit = pc & NMI_MASK ? RB_CTX_NMI : pc & HARDIRQ_MASK ? RB_CTX_IRQ : RB_CTX_SOFTIRQ; - if (unlikely(val & (1 << bit))) + if (unlikely(val & (1 << (bit + cpu_buffer->nest)))) return 1; - val |= (1 << bit); + val |= (1 << (bit + cpu_buffer->nest)); cpu_buffer->current_context = val; return 0; @@ -2636,7 +2637,57 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer) static __always_inline void trace_recursive_unlock(struct ring_buffer_per_cpu *cpu_buffer) { - cpu_buffer->current_context &= cpu_buffer->current_context - 1; + cpu_buffer->current_context &= + cpu_buffer->current_context - (1 << cpu_buffer->nest); +} + +/* The recursive locking above uses 4 bits */ +#define NESTED_BITS 4 + +/** + * ring_buffer_nest_start - Allow to trace while nested + * @buffer: The ring buffer to modify + * + * The ring buffer has a safty mechanism to prevent recursion. + * But there may be a case where a trace needs to be done while + * tracing something else. In this case, calling this function + * will allow this function to nest within a currently active + * ring_buffer_lock_reserve(). + * + * Call this function before calling another ring_buffer_lock_reserve() and + * call ring_buffer_nest_end() after the nested ring_buffer_unlock_commit(). + */ +void ring_buffer_nest_start(struct ring_buffer *buffer) +{ + struct ring_buffer_per_cpu *cpu_buffer; + int cpu; + + /* Enabled by ring_buffer_nest_end() */ + preempt_disable_notrace(); + cpu = raw_smp_processor_id(); + cpu_buffer = buffer->buffers[cpu]; + /* This is the shift value for the above recusive locking */ + cpu_buffer->nest += NESTED_BITS; +} + +/** + * ring_buffer_nest_end - Allow to trace while nested + * @buffer: The ring buffer to modify + * + * Must be called after ring_buffer_nest_start() and after the + * ring_buffer_unlock_commit(). + */ +void ring_buffer_nest_end(struct ring_buffer *buffer) +{ + struct ring_buffer_per_cpu *cpu_buffer; + int cpu; + + /* disabled by ring_buffer_nest_start() */ + cpu = raw_smp_processor_id(); + cpu_buffer = buffer->buffers[cpu]; + /* This is the shift value for the above recusive locking */ + cpu_buffer->nest -= NESTED_BITS; + preempt_enable_notrace(); } /** -- cgit v1.2.3 From d1ed7c558612630ce4c48e440a6fdd8d4785f6a3 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 24 Feb 2018 23:45:56 +0100 Subject: leds: Extends disk trigger for reads and writes This adds two new disk triggers for triggering on reads and writes respectively, named "disk-read" and "disk-write". The use case comes from working on the D-Link DNS-313 NAS box. This features an RGB LED for disk activity. with these two triggers I can couple the green LED to read activity and the red LED to write activity, which gives the appropriate user feedback about what is happening on the disk. When tested it gave exactly the feedback desired. The in-kernel interface is simply changed to pass a bool indicating if the activity is write activity and update each trigger (and the composite "disk-activity" trigger) depending on what is passed in. Signed-off-by: Linus Walleij Reviewed-by: Bartlomiej Zolnierkiewicz Acked-by: Pavel Machek Acked-by: Tejun Heo Acked-by: David S. Miller Signed-off-by: Jacek Anaszewski --- drivers/ata/libata-core.c | 2 +- drivers/ide/ide-disk.c | 2 +- drivers/leds/trigger/ledtrig-disk.c | 12 +++++++++++- include/linux/leds.h | 4 ++-- 4 files changed, 15 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 3c09122bf038..fa75de6abbf1 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -5219,7 +5219,7 @@ void ata_qc_complete(struct ata_queued_cmd *qc) struct ata_port *ap = qc->ap; /* Trigger the LED (if available) */ - ledtrig_disk_activity(); + ledtrig_disk_activity(!!(qc->tf.flags & ATA_TFLAG_WRITE)); /* XXX: New EH and old EH use different mechanisms to * synchronize EH with regular execution path. diff --git a/drivers/ide/ide-disk.c b/drivers/ide/ide-disk.c index 188d1b03715d..67bc72d78fbf 100644 --- a/drivers/ide/ide-disk.c +++ b/drivers/ide/ide-disk.c @@ -187,7 +187,7 @@ static ide_startstop_t ide_do_rw_disk(ide_drive_t *drive, struct request *rq, BUG_ON(drive->dev_flags & IDE_DFLAG_BLOCKED); BUG_ON(blk_rq_is_passthrough(rq)); - ledtrig_disk_activity(); + ledtrig_disk_activity(rq_data_dir(rq) == WRITE); pr_debug("%s: %sing: block=%llu, sectors=%u\n", drive->name, rq_data_dir(rq) == READ ? "read" : "writ", diff --git a/drivers/leds/trigger/ledtrig-disk.c b/drivers/leds/trigger/ledtrig-disk.c index cd525b4125eb..9816b0d60270 100644 --- a/drivers/leds/trigger/ledtrig-disk.c +++ b/drivers/leds/trigger/ledtrig-disk.c @@ -18,9 +18,11 @@ #define BLINK_DELAY 30 DEFINE_LED_TRIGGER(ledtrig_disk); +DEFINE_LED_TRIGGER(ledtrig_disk_read); +DEFINE_LED_TRIGGER(ledtrig_disk_write); DEFINE_LED_TRIGGER(ledtrig_ide); -void ledtrig_disk_activity(void) +void ledtrig_disk_activity(bool write) { unsigned long blink_delay = BLINK_DELAY; @@ -28,12 +30,20 @@ void ledtrig_disk_activity(void) &blink_delay, &blink_delay, 0); led_trigger_blink_oneshot(ledtrig_ide, &blink_delay, &blink_delay, 0); + if (write) + led_trigger_blink_oneshot(ledtrig_disk_write, + &blink_delay, &blink_delay, 0); + else + led_trigger_blink_oneshot(ledtrig_disk_read, + &blink_delay, &blink_delay, 0); } EXPORT_SYMBOL(ledtrig_disk_activity); static int __init ledtrig_disk_init(void) { led_trigger_register_simple("disk-activity", &ledtrig_disk); + led_trigger_register_simple("disk-read", &ledtrig_disk_read); + led_trigger_register_simple("disk-write", &ledtrig_disk_write); led_trigger_register_simple("ide-disk", &ledtrig_ide); return 0; diff --git a/include/linux/leds.h b/include/linux/leds.h index 5579c64c8fd6..b7e82550e655 100644 --- a/include/linux/leds.h +++ b/include/linux/leds.h @@ -346,9 +346,9 @@ static inline void *led_get_trigger_data(struct led_classdev *led_cdev) /* Trigger specific functions */ #ifdef CONFIG_LEDS_TRIGGER_DISK -extern void ledtrig_disk_activity(void); +extern void ledtrig_disk_activity(bool write); #else -static inline void ledtrig_disk_activity(void) {} +static inline void ledtrig_disk_activity(bool write) {} #endif #ifdef CONFIG_LEDS_TRIGGER_MTD -- cgit v1.2.3 From b1d0a5d0cba4597c0394997b2d5fced3e3841b4e Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Sat, 10 Mar 2018 01:15:45 +0100 Subject: netfilter: x_tables: add and use xt_check_proc_name recent and hashlimit both create /proc files, but only check that name is 0 terminated. This can trigger WARN() from procfs when name is "" or "/". Add helper for this and then use it for both. Cc: Eric Dumazet Reported-by: Eric Dumazet Reported-by: Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- include/linux/netfilter/x_tables.h | 2 ++ net/netfilter/x_tables.c | 30 ++++++++++++++++++++++++++++++ net/netfilter/xt_hashlimit.c | 16 ++++++++++------ net/netfilter/xt_recent.c | 6 +++--- 4 files changed, 45 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h index 1313b35c3ab7..14529511c4b8 100644 --- a/include/linux/netfilter/x_tables.h +++ b/include/linux/netfilter/x_tables.h @@ -285,6 +285,8 @@ unsigned int *xt_alloc_entry_offsets(unsigned int size); bool xt_find_jump_offset(const unsigned int *offsets, unsigned int target, unsigned int size); +int xt_check_proc_name(const char *name, unsigned int size); + int xt_check_match(struct xt_mtchk_param *, unsigned int size, u_int8_t proto, bool inv_proto); int xt_check_target(struct xt_tgchk_param *, unsigned int size, u_int8_t proto, diff --git a/net/netfilter/x_tables.c b/net/netfilter/x_tables.c index fa1655aff8d3..4aa01c90e9d1 100644 --- a/net/netfilter/x_tables.c +++ b/net/netfilter/x_tables.c @@ -423,6 +423,36 @@ textify_hooks(char *buf, size_t size, unsigned int mask, uint8_t nfproto) return buf; } +/** + * xt_check_proc_name - check that name is suitable for /proc file creation + * + * @name: file name candidate + * @size: length of buffer + * + * some x_tables modules wish to create a file in /proc. + * This function makes sure that the name is suitable for this + * purpose, it checks that name is NUL terminated and isn't a 'special' + * name, like "..". + * + * returns negative number on error or 0 if name is useable. + */ +int xt_check_proc_name(const char *name, unsigned int size) +{ + if (name[0] == '\0') + return -EINVAL; + + if (strnlen(name, size) == size) + return -ENAMETOOLONG; + + if (strcmp(name, ".") == 0 || + strcmp(name, "..") == 0 || + strchr(name, '/')) + return -EINVAL; + + return 0; +} +EXPORT_SYMBOL(xt_check_proc_name); + int xt_check_match(struct xt_mtchk_param *par, unsigned int size, u_int8_t proto, bool inv_proto) { diff --git a/net/netfilter/xt_hashlimit.c b/net/netfilter/xt_hashlimit.c index 66f5aca62a08..3360f13dc208 100644 --- a/net/netfilter/xt_hashlimit.c +++ b/net/netfilter/xt_hashlimit.c @@ -917,8 +917,9 @@ static int hashlimit_mt_check_v1(const struct xt_mtchk_param *par) struct hashlimit_cfg3 cfg = {}; int ret; - if (info->name[sizeof(info->name) - 1] != '\0') - return -EINVAL; + ret = xt_check_proc_name(info->name, sizeof(info->name)); + if (ret) + return ret; ret = cfg_copy(&cfg, (void *)&info->cfg, 1); @@ -935,8 +936,9 @@ static int hashlimit_mt_check_v2(const struct xt_mtchk_param *par) struct hashlimit_cfg3 cfg = {}; int ret; - if (info->name[sizeof(info->name) - 1] != '\0') - return -EINVAL; + ret = xt_check_proc_name(info->name, sizeof(info->name)); + if (ret) + return ret; ret = cfg_copy(&cfg, (void *)&info->cfg, 2); @@ -950,9 +952,11 @@ static int hashlimit_mt_check_v2(const struct xt_mtchk_param *par) static int hashlimit_mt_check(const struct xt_mtchk_param *par) { struct xt_hashlimit_mtinfo3 *info = par->matchinfo; + int ret; - if (info->name[sizeof(info->name) - 1] != '\0') - return -EINVAL; + ret = xt_check_proc_name(info->name, sizeof(info->name)); + if (ret) + return ret; return hashlimit_mt_check_common(par, &info->hinfo, &info->cfg, info->name, 3); diff --git a/net/netfilter/xt_recent.c b/net/netfilter/xt_recent.c index 6d232d18faff..81ee1d6543b2 100644 --- a/net/netfilter/xt_recent.c +++ b/net/netfilter/xt_recent.c @@ -361,9 +361,9 @@ static int recent_mt_check(const struct xt_mtchk_param *par, info->hit_count, XT_RECENT_MAX_NSTAMPS - 1); return -EINVAL; } - if (info->name[0] == '\0' || - strnlen(info->name, XT_RECENT_NAME_LEN) == XT_RECENT_NAME_LEN) - return -EINVAL; + ret = xt_check_proc_name(info->name, sizeof(info->name)); + if (ret) + return ret; if (ip_pkt_list_tot && info->hit_count < ip_pkt_list_tot) nstamp_mask = roundup_pow_of_two(ip_pkt_list_tot) - 1; -- cgit v1.2.3 From c59c9c85e36aa09cfd901cc15a0d8d3772c18195 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 7 Feb 2018 18:22:49 +0800 Subject: soc: mediatek: avoid hardcoded value with bus_prot_mask use a meaningful definition for bus_prot_mask instead of just hardcoded for it. Signed-off-by: Sean Wang Reviewed-by: Ulf Hansson Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-scpsys.c | 5 +++-- include/linux/soc/mediatek/infracfg.h | 4 ++++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 435ce5ec648a..5346f33dd70b 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -518,7 +518,8 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = SPM_CONN_PWR_CON, - .bus_prot_mask = 0x0104, + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | + MT2701_TOP_AXI_PROT_EN_CONN_S, .clk_id = {CLK_NONE}, .active_wakeup = true, }, @@ -528,7 +529,7 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .clk_id = {CLK_MM}, - .bus_prot_mask = 0x0002, + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0, .active_wakeup = true, }, [MT2701_POWER_DOMAIN_MFG] = { diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index b0a507d356ef..fd25f0148566 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -21,6 +21,10 @@ #define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) + #define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) #define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) #define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ -- cgit v1.2.3 From 7e904a91bf6049071ef9d605a52f863ae774081d Mon Sep 17 00:00:00 2001 From: Sai Praneeth Date: Mon, 12 Mar 2018 08:44:56 +0000 Subject: efi: Use efi_mm in x86 as well as ARM Presently, only ARM uses mm_struct to manage EFI page tables and EFI runtime region mappings. As this is the preferred approach, let's make this data structure common across architectures. Specially, for x86, using this data structure improves code maintainability and readability. Tested-by: Bhupesh Sharma [ardb: don't #include the world to get a declaration of struct mm_struct] Signed-off-by: Sai Praneeth Prakhya Signed-off-by: Ard Biesheuvel Reviewed-by: Matt Fleming Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Lee, Chun-Yi Cc: Linus Torvalds Cc: Michael S. Tsirkin Cc: Peter Zijlstra Cc: Ravi Shankar Cc: Ricardo Neri Cc: Thomas Gleixner Cc: Tony Luck Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20180312084500.10764-2-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar --- arch/x86/include/asm/efi.h | 1 + arch/x86/platform/efi/efi_64.c | 3 +++ drivers/firmware/efi/arm-runtime.c | 9 --------- drivers/firmware/efi/efi.c | 9 +++++++++ include/linux/efi.h | 2 ++ 5 files changed, 15 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index a399c1ebf6f0..c62443fa7d0a 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * We map the EFI regions needed for runtime services non-contiguously, diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c index 780460aa5ea5..29425b6c98a7 100644 --- a/arch/x86/platform/efi/efi_64.c +++ b/arch/x86/platform/efi/efi_64.c @@ -233,6 +233,9 @@ int __init efi_alloc_page_tables(void) return -ENOMEM; } + mm_init_cpumask(&efi_mm); + init_new_context(NULL, &efi_mm); + return 0; } diff --git a/drivers/firmware/efi/arm-runtime.c b/drivers/firmware/efi/arm-runtime.c index 13561aeb7396..5889cbea60b8 100644 --- a/drivers/firmware/efi/arm-runtime.c +++ b/drivers/firmware/efi/arm-runtime.c @@ -31,15 +31,6 @@ extern u64 efi_system_table; -static struct mm_struct efi_mm = { - .mm_rb = RB_ROOT, - .mm_users = ATOMIC_INIT(2), - .mm_count = ATOMIC_INIT(1), - .mmap_sem = __RWSEM_INITIALIZER(efi_mm.mmap_sem), - .page_table_lock = __SPIN_LOCK_UNLOCKED(efi_mm.page_table_lock), - .mmlist = LIST_HEAD_INIT(efi_mm.mmlist), -}; - #ifdef CONFIG_ARM64_PTDUMP_DEBUGFS #include diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c index 92b9e79e5da9..232f4915223b 100644 --- a/drivers/firmware/efi/efi.c +++ b/drivers/firmware/efi/efi.c @@ -75,6 +75,15 @@ static unsigned long *efi_tables[] = { &efi.mem_attr_table, }; +struct mm_struct efi_mm = { + .mm_rb = RB_ROOT, + .mm_users = ATOMIC_INIT(2), + .mm_count = ATOMIC_INIT(1), + .mmap_sem = __RWSEM_INITIALIZER(efi_mm.mmap_sem), + .page_table_lock = __SPIN_LOCK_UNLOCKED(efi_mm.page_table_lock), + .mmlist = LIST_HEAD_INIT(efi_mm.mmlist), +}; + static bool disable_runtime; static int __init setup_noefi(char *arg) { diff --git a/include/linux/efi.h b/include/linux/efi.h index f5083aa72eae..f1b7d68ac460 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -966,6 +966,8 @@ extern struct efi { unsigned long flags; } efi; +extern struct mm_struct efi_mm; + static inline int efi_guidcmp (efi_guid_t left, efi_guid_t right) { -- cgit v1.2.3 From 9e49e2447c6385e45c6fddd70d6c0e917e21b669 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Tue, 27 Feb 2018 17:05:10 +0100 Subject: sched/core: Remove TASK_ALL It's unused: $ git grep "\" | wc -l 1 ... and it is also dangerous, kill the bugger. Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Sebastian Andrzej Siewior Acked-by: Thomas Gleixner Cc: Linus Torvalds Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/20180227160510.10829-1-bigeasy@linutronix.de Signed-off-by: Ingo Molnar --- include/linux/sched.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/sched.h b/include/linux/sched.h index b161ef8a902e..21b1168da951 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -93,7 +93,6 @@ struct task_group; /* Convenience macros for the sake of wake_up(): */ #define TASK_NORMAL (TASK_INTERRUPTIBLE | TASK_UNINTERRUPTIBLE) -#define TASK_ALL (TASK_NORMAL | __TASK_STOPPED | __TASK_TRACED) /* get_task_state(): */ #define TASK_REPORT (TASK_RUNNING | TASK_INTERRUPTIBLE | \ -- cgit v1.2.3 From 8e1a2031e4b556b01ca53cd1fb2d83d811a6605b Mon Sep 17 00:00:00 2001 From: Alexey Budankov Date: Fri, 8 Sep 2017 11:47:03 +0300 Subject: perf/cor: Use RB trees for pinned/flexible groups Change event groups into RB trees sorted by CPU and then by a 64bit index, so that multiplexing hrtimer interrupt handler would be able skipping to the current CPU's list and ignore groups allocated for the other CPUs. New API for manipulating event groups in the trees is implemented as well as adoption on the API in the current implementation. pinned_group_sched_in() and flexible_group_sched_in() API are introduced to consolidate code enabling the whole group from pinned and flexible groups appropriately. Signed-off-by: Alexey Budankov Signed-off-by: Peter Zijlstra (Intel) Acked-by: Mark Rutland Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: David Carrillo-Cisneros Cc: Dmitri Prokhorov Cc: Jiri Olsa Cc: Kan Liang Cc: Linus Torvalds Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Valery Cherepennikov Cc: Vince Weaver Cc: linux-kernel@vger.kernel.org Link: http://lkml.kernel.org/r/372f9c8b-0cfe-4240-e44d-83d863d40813@linux.intel.com Signed-off-by: Ingo Molnar --- include/linux/perf_event.h | 16 ++- kernel/events/core.c | 307 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 267 insertions(+), 56 deletions(-) (limited to 'include/linux') diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 7546822a1d74..6e3f854a34d8 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -558,7 +558,11 @@ struct perf_event { */ struct list_head group_entry; struct list_head sibling_list; - + /* + * Node on the pinned or flexible tree located at the event context; + */ + struct rb_node group_node; + u64 group_index; /* * We need storage to track the entries in perf_pmu_migrate_context; we * cannot use the event_entry because of RCU and we want to keep the @@ -690,6 +694,12 @@ struct perf_event { #endif /* CONFIG_PERF_EVENTS */ }; + +struct perf_event_groups { + struct rb_root tree; + u64 index; +}; + /** * struct perf_event_context - event context structure * @@ -710,8 +720,8 @@ struct perf_event_context { struct mutex mutex; struct list_head active_ctx_list; - struct list_head pinned_groups; - struct list_head flexible_groups; + struct perf_event_groups pinned_groups; + struct perf_event_groups flexible_groups; struct list_head event_list; int nr_events; int nr_active; diff --git a/kernel/events/core.c b/kernel/events/core.c index 8b6a2774e084..c9fee3640f40 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1460,8 +1460,21 @@ static enum event_type_t get_event_type(struct perf_event *event) return event_type; } -static struct list_head * -ctx_group_list(struct perf_event *event, struct perf_event_context *ctx) +/* + * Helper function to initialize group leader event; + */ +void init_event_group(struct perf_event *event) +{ + RB_CLEAR_NODE(&event->group_node); + event->group_index = 0; +} + +/* + * Extract pinned or flexible groups from the context + * based on event attrs bits; + */ +static struct perf_event_groups * +get_event_groups(struct perf_event *event, struct perf_event_context *ctx) { if (event->attr.pinned) return &ctx->pinned_groups; @@ -1469,6 +1482,169 @@ ctx_group_list(struct perf_event *event, struct perf_event_context *ctx) return &ctx->flexible_groups; } +/* + * Helper function to initializes perf event groups object; + */ +void perf_event_groups_init(struct perf_event_groups *groups) +{ + groups->tree = RB_ROOT; + groups->index = 0; +} + +/* + * Compare function for event groups; + * Implements complex key that first sorts by CPU and then by + * virtual index which provides ordering when rotating + * groups for the same CPU; + */ +int perf_event_groups_less(struct perf_event *left, struct perf_event *right) +{ + if (left->cpu < right->cpu) { + return 1; + } else if (left->cpu > right->cpu) { + return 0; + } else { + if (left->group_index < right->group_index) { + return 1; + } else if(left->group_index > right->group_index) { + return 0; + } else { + return 0; + } + } +} + +/* + * Insert a group into a tree using event->cpu as a key. If event->cpu node + * is already attached to the tree then the event is added to the attached + * group's group_list list. + */ +static void +perf_event_groups_insert(struct perf_event_groups *groups, + struct perf_event *event) +{ + struct perf_event *node_event; + struct rb_node *parent; + struct rb_node **node; + + event->group_index = ++groups->index; + + node = &groups->tree.rb_node; + parent = *node; + + while (*node) { + parent = *node; + node_event = container_of(*node, + struct perf_event, group_node); + + if (perf_event_groups_less(event, node_event)) + node = &parent->rb_left; + else + node = &parent->rb_right; + } + + rb_link_node(&event->group_node, parent, node); + rb_insert_color(&event->group_node, &groups->tree); +} + +/* + * Helper function to insert event into the pinned or + * flexible groups; + */ +static void +add_event_to_groups(struct perf_event *event, struct perf_event_context *ctx) +{ + struct perf_event_groups *groups; + + groups = get_event_groups(event, ctx); + perf_event_groups_insert(groups, event); +} + +/* + * Delete a group from a tree. If the group is directly attached to the tree + * it also detaches all groups on the group's group_list list. + */ +static void +perf_event_groups_delete(struct perf_event_groups *groups, + struct perf_event *event) +{ + if (!RB_EMPTY_NODE(&event->group_node) && + !RB_EMPTY_ROOT(&groups->tree)) + rb_erase(&event->group_node, &groups->tree); + + init_event_group(event); +} + +/* + * Helper function to delete event from its groups; + */ +static void +del_event_from_groups(struct perf_event *event, struct perf_event_context *ctx) +{ + struct perf_event_groups *groups; + + groups = get_event_groups(event, ctx); + perf_event_groups_delete(groups, event); +} + +/* + * Get a group by a cpu key from groups tree with the least group_index; + */ +static struct perf_event * +perf_event_groups_first(struct perf_event_groups *groups, int cpu) +{ + struct perf_event *node_event = NULL, *match = NULL; + struct rb_node *node = groups->tree.rb_node; + + while (node) { + node_event = container_of(node, + struct perf_event, group_node); + + if (cpu < node_event->cpu) { + node = node->rb_left; + } else if (cpu > node_event->cpu) { + node = node->rb_right; + } else { + match = node_event; + node = node->rb_left; + } + } + + return match; +} + +/* + * Find group list by a cpu key and rotate it. + */ +static void +perf_event_groups_rotate(struct perf_event_groups *groups, int cpu) +{ + struct perf_event *event = + perf_event_groups_first(groups, cpu); + + if (event) { + perf_event_groups_delete(groups, event); + perf_event_groups_insert(groups, event); + } +} + +/* + * Iterate event groups thru the whole tree. + */ +#define perf_event_groups_for_each(event, groups, node) \ + for (event = rb_entry_safe(rb_first(&((groups)->tree)), \ + typeof(*event), node); event; \ + event = rb_entry_safe(rb_next(&event->node), \ + typeof(*event), node)) +/* + * Iterate event groups with cpu == key. + */ +#define perf_event_groups_for_each_cpu(event, key, groups, node) \ + for (event = perf_event_groups_first(groups, key); \ + event && event->cpu == key; \ + event = rb_entry_safe(rb_next(&event->node), \ + typeof(*event), node)) + /* * Add a event from the lists for its context. * Must be called with ctx->mutex and ctx->lock held. @@ -1489,12 +1665,8 @@ list_add_event(struct perf_event *event, struct perf_event_context *ctx) * perf_group_detach can, at all times, locate all siblings. */ if (event->group_leader == event) { - struct list_head *list; - event->group_caps = event->event_caps; - - list = ctx_group_list(event, ctx); - list_add_tail(&event->group_entry, list); + add_event_to_groups(event, ctx); } list_update_cgroup_event(event, ctx, true); @@ -1688,7 +1860,7 @@ list_del_event(struct perf_event *event, struct perf_event_context *ctx) list_del_rcu(&event->event_entry); if (event->group_leader == event) - list_del_init(&event->group_entry); + del_event_from_groups(event, ctx); /* * If event was in error state, then keep it @@ -1706,7 +1878,6 @@ list_del_event(struct perf_event *event, struct perf_event_context *ctx) static void perf_group_detach(struct perf_event *event) { struct perf_event *sibling, *tmp; - struct list_head *list = NULL; lockdep_assert_held(&event->ctx->lock); @@ -1727,22 +1898,23 @@ static void perf_group_detach(struct perf_event *event) goto out; } - if (!list_empty(&event->group_entry)) - list = &event->group_entry; - /* * If this was a group event with sibling events then * upgrade the siblings to singleton events by adding them * to whatever list we are on. */ list_for_each_entry_safe(sibling, tmp, &event->sibling_list, group_entry) { - if (list) - list_move_tail(&sibling->group_entry, list); + sibling->group_leader = sibling; /* Inherit group flags from the previous leader */ sibling->group_caps = event->group_caps; + if (!RB_EMPTY_NODE(&event->group_node)) { + list_del_init(&sibling->group_entry); + add_event_to_groups(sibling, event->ctx); + } + WARN_ON_ONCE(sibling->ctx != event->ctx); } @@ -2186,6 +2358,22 @@ static int group_can_go_on(struct perf_event *event, return can_add_hw; } +static int +flexible_group_sched_in(struct perf_event *event, + struct perf_event_context *ctx, + struct perf_cpu_context *cpuctx, + int *can_add_hw) +{ + if (event->state <= PERF_EVENT_STATE_OFF || !event_filter_match(event)) + return 0; + + if (group_can_go_on(event, cpuctx, *can_add_hw)) + if (group_sched_in(event, cpuctx, ctx)) + *can_add_hw = 0; + + return 1; +} + static void add_event_to_ctx(struct perf_event *event, struct perf_event_context *ctx) { @@ -2652,6 +2840,7 @@ static void ctx_sched_out(struct perf_event_context *ctx, struct perf_cpu_context *cpuctx, enum event_type_t event_type) { + int sw = -1, cpu = smp_processor_id(); int is_active = ctx->is_active; struct perf_event *event; @@ -2700,12 +2889,20 @@ static void ctx_sched_out(struct perf_event_context *ctx, perf_pmu_disable(ctx->pmu); if (is_active & EVENT_PINNED) { - list_for_each_entry(event, &ctx->pinned_groups, group_entry) + perf_event_groups_for_each_cpu(event, cpu, + &ctx->pinned_groups, group_node) + group_sched_out(event, cpuctx, ctx); + perf_event_groups_for_each_cpu(event, sw, + &ctx->pinned_groups, group_node) group_sched_out(event, cpuctx, ctx); } if (is_active & EVENT_FLEXIBLE) { - list_for_each_entry(event, &ctx->flexible_groups, group_entry) + perf_event_groups_for_each_cpu(event, cpu, + &ctx->flexible_groups, group_node) + group_sched_out(event, cpuctx, ctx); + perf_event_groups_for_each_cpu(event, sw, + &ctx->flexible_groups, group_node) group_sched_out(event, cpuctx, ctx); } perf_pmu_enable(ctx->pmu); @@ -2996,23 +3193,28 @@ static void ctx_pinned_sched_in(struct perf_event_context *ctx, struct perf_cpu_context *cpuctx) { + int sw = -1, cpu = smp_processor_id(); struct perf_event *event; + int can_add_hw; + + perf_event_groups_for_each_cpu(event, sw, + &ctx->pinned_groups, group_node) { + can_add_hw = 1; + if (flexible_group_sched_in(event, ctx, cpuctx, &can_add_hw)) { + if (event->state == PERF_EVENT_STATE_INACTIVE) + perf_event_set_state(event, + PERF_EVENT_STATE_ERROR); + } + } - list_for_each_entry(event, &ctx->pinned_groups, group_entry) { - if (event->state <= PERF_EVENT_STATE_OFF) - continue; - if (!event_filter_match(event)) - continue; - - if (group_can_go_on(event, cpuctx, 1)) - group_sched_in(event, cpuctx, ctx); - - /* - * If this pinned group hasn't been scheduled, - * put it in error state. - */ - if (event->state == PERF_EVENT_STATE_INACTIVE) - perf_event_set_state(event, PERF_EVENT_STATE_ERROR); + perf_event_groups_for_each_cpu(event, cpu, + &ctx->pinned_groups, group_node) { + can_add_hw = 1; + if (flexible_group_sched_in(event, ctx, cpuctx, &can_add_hw)) { + if (event->state == PERF_EVENT_STATE_INACTIVE) + perf_event_set_state(event, + PERF_EVENT_STATE_ERROR); + } } } @@ -3020,25 +3222,19 @@ static void ctx_flexible_sched_in(struct perf_event_context *ctx, struct perf_cpu_context *cpuctx) { + int sw = -1, cpu = smp_processor_id(); struct perf_event *event; int can_add_hw = 1; - list_for_each_entry(event, &ctx->flexible_groups, group_entry) { - /* Ignore events in OFF or ERROR state */ - if (event->state <= PERF_EVENT_STATE_OFF) - continue; - /* - * Listen to the 'cpu' scheduling filter constraint - * of events: - */ - if (!event_filter_match(event)) - continue; + perf_event_groups_for_each_cpu(event, sw, + &ctx->flexible_groups, group_node) + flexible_group_sched_in(event, ctx, cpuctx, &can_add_hw); + + can_add_hw = 1; + perf_event_groups_for_each_cpu(event, cpu, + &ctx->flexible_groups, group_node) + flexible_group_sched_in(event, ctx, cpuctx, &can_add_hw); - if (group_can_go_on(event, cpuctx, can_add_hw)) { - if (group_sched_in(event, cpuctx, ctx)) - can_add_hw = 0; - } - } } static void @@ -3119,7 +3315,7 @@ static void perf_event_context_sched_in(struct perf_event_context *ctx, * However, if task's ctx is not carrying any pinned * events, no need to flip the cpuctx's events around. */ - if (!list_empty(&ctx->pinned_groups)) + if (!RB_EMPTY_ROOT(&ctx->pinned_groups.tree)) cpu_ctx_sched_out(cpuctx, EVENT_FLEXIBLE); perf_event_sched_in(cpuctx, ctx, task); perf_pmu_enable(ctx->pmu); @@ -3356,8 +3552,12 @@ static void rotate_ctx(struct perf_event_context *ctx) * Rotate the first entry last of non-pinned groups. Rotation might be * disabled by the inheritance code. */ - if (!ctx->rotate_disable) - list_rotate_left(&ctx->flexible_groups); + if (!ctx->rotate_disable) { + int sw = -1, cpu = smp_processor_id(); + + perf_event_groups_rotate(&ctx->flexible_groups, sw); + perf_event_groups_rotate(&ctx->flexible_groups, cpu); + } } static int perf_rotate_context(struct perf_cpu_context *cpuctx) @@ -3715,8 +3915,8 @@ static void __perf_event_init_context(struct perf_event_context *ctx) raw_spin_lock_init(&ctx->lock); mutex_init(&ctx->mutex); INIT_LIST_HEAD(&ctx->active_ctx_list); - INIT_LIST_HEAD(&ctx->pinned_groups); - INIT_LIST_HEAD(&ctx->flexible_groups); + perf_event_groups_init(&ctx->pinned_groups); + perf_event_groups_init(&ctx->flexible_groups); INIT_LIST_HEAD(&ctx->event_list); atomic_set(&ctx->refcount, 1); } @@ -9561,6 +9761,7 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, INIT_LIST_HEAD(&event->group_entry); INIT_LIST_HEAD(&event->event_entry); INIT_LIST_HEAD(&event->sibling_list); + init_event_group(event); INIT_LIST_HEAD(&event->rb_entry); INIT_LIST_HEAD(&event->active_entry); INIT_LIST_HEAD(&event->addr_filters.list); @@ -11085,7 +11286,7 @@ static int perf_event_init_context(struct task_struct *child, int ctxn) * We dont have to disable NMIs - we are only looking at * the list, not manipulating it: */ - list_for_each_entry(event, &parent_ctx->pinned_groups, group_entry) { + perf_event_groups_for_each(event, &parent_ctx->pinned_groups, group_node) { ret = inherit_task_group(event, parent, parent_ctx, child, ctxn, &inherited_all); if (ret) @@ -11101,7 +11302,7 @@ static int perf_event_init_context(struct task_struct *child, int ctxn) parent_ctx->rotate_disable = 1; raw_spin_unlock_irqrestore(&parent_ctx->lock, flags); - list_for_each_entry(event, &parent_ctx->flexible_groups, group_entry) { + perf_event_groups_for_each(event, &parent_ctx->flexible_groups, group_node) { ret = inherit_task_group(event, parent, parent_ctx, child, ctxn, &inherited_all); if (ret) -- cgit v1.2.3 From 8343aae66167df6708128a778e750d48dbe31302 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Mon, 13 Nov 2017 14:28:33 +0100 Subject: perf/core: Remove perf_event::group_entry Now that all the grouping is done with RB trees, we no longer need group_entry and can replace the whole thing with sibling_list. Signed-off-by: Peter Zijlstra (Intel) Acked-by: Mark Rutland Cc: Alexander Shishkin Cc: Alexey Budankov Cc: Arnaldo Carvalho de Melo Cc: David Carrillo-Cisneros Cc: Dmitri Prokhorov Cc: Jiri Olsa Cc: Kan Liang Cc: Linus Torvalds Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Valery Cherepennikov Cc: Vince Weaver Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/alpha/kernel/perf_event.c | 2 +- arch/arm/mach-imx/mmdc.c | 2 +- arch/arm/mm/cache-l2x0-pmu.c | 2 +- arch/mips/kernel/perf_event_mipsxx.c | 2 +- arch/powerpc/perf/core-book3s.c | 2 +- arch/powerpc/perf/core-fsl-emb.c | 2 +- arch/sparc/kernel/perf_event.c | 2 +- arch/x86/events/core.c | 2 +- arch/x86/events/intel/uncore.c | 2 +- drivers/bus/arm-cci.c | 2 +- drivers/bus/arm-ccn.c | 2 +- drivers/perf/arm_dsu_pmu.c | 2 +- drivers/perf/arm_pmu.c | 2 +- drivers/perf/hisilicon/hisi_uncore_pmu.c | 3 +-- drivers/perf/qcom_l2_pmu.c | 4 ++-- drivers/perf/qcom_l3_pmu.c | 2 +- drivers/perf/xgene_pmu.c | 2 +- include/linux/perf_event.h | 5 ----- kernel/events/core.c | 37 ++++++++++++++++---------------- 19 files changed, 36 insertions(+), 43 deletions(-) (limited to 'include/linux') diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index a1f6bc7f1e4c..435864c24479 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -351,7 +351,7 @@ static int collect_events(struct perf_event *group, int max_count, evtype[n] = group->hw.event_base; current_idx[n++] = PMC_NO_INDEX; } - list_for_each_entry(pe, &group->sibling_list, group_entry) { + list_for_each_entry(pe, &group->sibling_list, sibling_list) { if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) return -1; diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 5fb1d2254b5e..27a9ca20933e 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -269,7 +269,7 @@ static bool mmdc_pmu_group_is_valid(struct perf_event *event) return false; } - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) return false; } diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c index 0a1e2280141f..3a89ea4c2b57 100644 --- a/arch/arm/mm/cache-l2x0-pmu.c +++ b/arch/arm/mm/cache-l2x0-pmu.c @@ -293,7 +293,7 @@ static bool l2x0_pmu_group_is_valid(struct perf_event *event) else if (!is_software_event(leader)) return false; - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { if (sibling->pmu == pmu) num_hw++; else if (!is_software_event(sibling)) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 6668f67a61c3..46097ff3208b 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -711,7 +711,7 @@ static int validate_group(struct perf_event *event) if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) return -EINVAL; - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) return -EINVAL; } diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index f89bbd54ecec..7c1f66050433 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -1426,7 +1426,7 @@ static int collect_events(struct perf_event *group, int max_count, flags[n] = group->hw.event_base; events[n++] = group->hw.config; } - list_for_each_entry(event, &group->sibling_list, group_entry) { + list_for_each_entry(event, &group->sibling_list, sibling_list) { if (event->pmu->task_ctx_nr == perf_hw_context && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c index 5d747b4cb8ee..94c2e63662c6 100644 --- a/arch/powerpc/perf/core-fsl-emb.c +++ b/arch/powerpc/perf/core-fsl-emb.c @@ -277,7 +277,7 @@ static int collect_events(struct perf_event *group, int max_count, ctrs[n] = group; n++; } - list_for_each_entry(event, &group->sibling_list, group_entry) { + list_for_each_entry(event, &group->sibling_list, sibling_list) { if (!is_software_event(event) && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 5c1f54758312..a0a86d369119 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1342,7 +1342,7 @@ static int collect_events(struct perf_event *group, int max_count, events[n] = group->hw.event_base; current_idx[n++] = PIC_NO_INDEX; } - list_for_each_entry(event, &group->sibling_list, group_entry) { + list_for_each_entry(event, &group->sibling_list, sibling_list) { if (!is_software_event(event) && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 9c86e10f1196..77a4125b6b1f 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -990,7 +990,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, if (!dogrp) return n; - list_for_each_entry(event, &leader->sibling_list, group_entry) { + list_for_each_entry(event, &leader->sibling_list, sibling_list) { if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF) continue; diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 7874c980d569..9e374cd22ad2 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -354,7 +354,7 @@ uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, if (!dogrp) return n; - list_for_each_entry(event, &leader->sibling_list, group_entry) { + list_for_each_entry(event, &leader->sibling_list, sibling_list) { if (!is_box_event(box, event) || event->state <= PERF_EVENT_STATE_OFF) continue; diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 5426c04fe24b..c98435bdb64f 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1311,7 +1311,7 @@ validate_group(struct perf_event *event) if (!validate_event(event->pmu, &fake_pmu, leader)) return -EINVAL; - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { if (!validate_event(event->pmu, &fake_pmu, sibling)) return -EINVAL; } diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index b52332e52ca5..1c310a4be000 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -847,7 +847,7 @@ static int arm_ccn_pmu_event_init(struct perf_event *event) return -EINVAL; list_for_each_entry(sibling, &event->group_leader->sibling_list, - group_entry) + sibling_list) if (sibling->pmu != event->pmu && !is_software_event(sibling)) return -EINVAL; diff --git a/drivers/perf/arm_dsu_pmu.c b/drivers/perf/arm_dsu_pmu.c index 38f2cc2a6c74..660680d78147 100644 --- a/drivers/perf/arm_dsu_pmu.c +++ b/drivers/perf/arm_dsu_pmu.c @@ -536,7 +536,7 @@ static bool dsu_pmu_validate_group(struct perf_event *event) memset(fake_hw.used_mask, 0, sizeof(fake_hw.used_mask)); if (!dsu_pmu_validate_event(event->pmu, &fake_hw, leader)) return false; - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { if (!dsu_pmu_validate_event(event->pmu, &fake_hw, sibling)) return false; } diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 0c2ed11c0603..628d7a7b9526 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -311,7 +311,7 @@ validate_group(struct perf_event *event) if (!validate_event(event->pmu, &fake_pmu, leader)) return -EINVAL; - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { if (!validate_event(event->pmu, &fake_pmu, sibling)) return -EINVAL; } diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c index 7ed24b954422..e3356087fd76 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -82,8 +82,7 @@ static bool hisi_validate_event_group(struct perf_event *event) counters++; } - list_for_each_entry(sibling, &event->group_leader->sibling_list, - group_entry) { + list_for_each_entry(sibling, &event->group_leader->sibling_list, sibling_list) { if (is_software_event(sibling)) continue; if (sibling->pmu != event->pmu) diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c index 4fdc8486a8e4..5e535a718965 100644 --- a/drivers/perf/qcom_l2_pmu.c +++ b/drivers/perf/qcom_l2_pmu.c @@ -535,7 +535,7 @@ static int l2_cache_event_init(struct perf_event *event) } list_for_each_entry(sibling, &event->group_leader->sibling_list, - group_entry) + sibling_list) if (sibling->pmu != event->pmu && !is_software_event(sibling)) { dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, @@ -572,7 +572,7 @@ static int l2_cache_event_init(struct perf_event *event) } list_for_each_entry(sibling, &event->group_leader->sibling_list, - group_entry) { + sibling_list) { if ((sibling != event) && !is_software_event(sibling) && (L2_EVT_GROUP(sibling->attr.config) == diff --git a/drivers/perf/qcom_l3_pmu.c b/drivers/perf/qcom_l3_pmu.c index 7f6b62b29e9d..5dedf4b1a552 100644 --- a/drivers/perf/qcom_l3_pmu.c +++ b/drivers/perf/qcom_l3_pmu.c @@ -468,7 +468,7 @@ static bool qcom_l3_cache__validate_event_group(struct perf_event *event) counters = event_num_counters(event); counters += event_num_counters(leader); - list_for_each_entry(sibling, &leader->sibling_list, group_entry) { + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { if (is_software_event(sibling)) continue; if (sibling->pmu != event->pmu) diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c index eb23311bc70c..f1f4a56cab5e 100644 --- a/drivers/perf/xgene_pmu.c +++ b/drivers/perf/xgene_pmu.c @@ -950,7 +950,7 @@ static int xgene_perf_event_init(struct perf_event *event) return -EINVAL; list_for_each_entry(sibling, &event->group_leader->sibling_list, - group_entry) + sibling_list) if (sibling->pmu != event->pmu && !is_software_event(sibling)) return -EINVAL; diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 6e3f854a34d8..84044ec21b31 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -549,14 +549,9 @@ struct perf_event { struct list_head event_entry; /* - * XXX: group_entry and sibling_list should be mutually exclusive; - * either you're a sibling on a group, or you're the group leader. - * Rework the code to always use the same list element. - * * Locked for modification by both ctx->mutex and ctx->lock; holding * either sufficies for read. */ - struct list_head group_entry; struct list_head sibling_list; /* * Node on the pinned or flexible tree located at the event context; diff --git a/kernel/events/core.c b/kernel/events/core.c index 2d8c0208ca4a..9a07bbe66451 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -643,7 +643,7 @@ static void perf_event_update_sibling_time(struct perf_event *leader) { struct perf_event *sibling; - list_for_each_entry(sibling, &leader->sibling_list, group_entry) + list_for_each_entry(sibling, &leader->sibling_list, sibling_list) perf_event_update_time(sibling); } @@ -1835,12 +1835,12 @@ static void perf_group_attach(struct perf_event *event) group_leader->group_caps &= event->event_caps; - list_add_tail(&event->group_entry, &group_leader->sibling_list); + list_add_tail(&event->sibling_list, &group_leader->sibling_list); group_leader->nr_siblings++; perf_event__header_size(group_leader); - list_for_each_entry(pos, &group_leader->sibling_list, group_entry) + list_for_each_entry(pos, &group_leader->sibling_list, sibling_list) perf_event__header_size(pos); } @@ -1904,7 +1904,7 @@ static void perf_group_detach(struct perf_event *event) * If this is a sibling, remove it from its group. */ if (event->group_leader != event) { - list_del_init(&event->group_entry); + list_del_init(&event->sibling_list); event->group_leader->nr_siblings--; goto out; } @@ -1914,7 +1914,7 @@ static void perf_group_detach(struct perf_event *event) * upgrade the siblings to singleton events by adding them * to whatever list we are on. */ - list_for_each_entry_safe(sibling, tmp, &event->sibling_list, group_entry) { + list_for_each_entry_safe(sibling, tmp, &event->sibling_list, sibling_list) { sibling->group_leader = sibling; @@ -1922,7 +1922,7 @@ static void perf_group_detach(struct perf_event *event) sibling->group_caps = event->group_caps; if (!RB_EMPTY_NODE(&event->group_node)) { - list_del_init(&sibling->group_entry); + list_del_init(&sibling->sibling_list); add_event_to_groups(sibling, event->ctx); } @@ -1932,7 +1932,7 @@ static void perf_group_detach(struct perf_event *event) out: perf_event__header_size(event->group_leader); - list_for_each_entry(tmp, &event->group_leader->sibling_list, group_entry) + list_for_each_entry(tmp, &event->group_leader->sibling_list, sibling_list) perf_event__header_size(tmp); } @@ -1960,7 +1960,7 @@ static inline int pmu_filter_match(struct perf_event *event) if (!__pmu_filter_match(event)) return 0; - list_for_each_entry(child, &event->sibling_list, group_entry) { + list_for_each_entry(child, &event->sibling_list, sibling_list) { if (!__pmu_filter_match(child)) return 0; } @@ -2028,7 +2028,7 @@ group_sched_out(struct perf_event *group_event, /* * Schedule out siblings (if any): */ - list_for_each_entry(event, &group_event->sibling_list, group_entry) + list_for_each_entry(event, &group_event->sibling_list, sibling_list) event_sched_out(event, cpuctx, ctx); perf_pmu_enable(ctx->pmu); @@ -2307,7 +2307,7 @@ group_sched_in(struct perf_event *group_event, /* * Schedule in siblings as one group (if any): */ - list_for_each_entry(event, &group_event->sibling_list, group_entry) { + list_for_each_entry(event, &group_event->sibling_list, sibling_list) { if (event_sched_in(event, cpuctx, ctx)) { partial_group = event; goto group_error; @@ -2323,7 +2323,7 @@ group_error: * partial group before returning: * The events up to the failed event are scheduled out normally. */ - list_for_each_entry(event, &group_event->sibling_list, group_entry) { + list_for_each_entry(event, &group_event->sibling_list, sibling_list) { if (event == partial_group) break; @@ -3796,7 +3796,7 @@ static void __perf_event_read(void *info) pmu->read(event); - list_for_each_entry(sub, &event->sibling_list, group_entry) { + list_for_each_entry(sub, &event->sibling_list, sibling_list) { if (sub->state == PERF_EVENT_STATE_ACTIVE) { /* * Use sibling's PMU rather than @event's since @@ -4642,7 +4642,7 @@ static int __perf_read_group_add(struct perf_event *leader, if (read_format & PERF_FORMAT_ID) values[n++] = primary_event_id(leader); - list_for_each_entry(sub, &leader->sibling_list, group_entry) { + list_for_each_entry(sub, &leader->sibling_list, sibling_list) { values[n++] += perf_event_count(sub); if (read_format & PERF_FORMAT_ID) values[n++] = primary_event_id(sub); @@ -4836,7 +4836,7 @@ static void perf_event_for_each(struct perf_event *event, event = event->group_leader; perf_event_for_each_child(event, func); - list_for_each_entry(sibling, &event->sibling_list, group_entry) + list_for_each_entry(sibling, &event->sibling_list, sibling_list) perf_event_for_each_child(sibling, func); } @@ -5995,7 +5995,7 @@ static void perf_output_read_group(struct perf_output_handle *handle, __output_copy(handle, values, n * sizeof(u64)); - list_for_each_entry(sub, &leader->sibling_list, group_entry) { + list_for_each_entry(sub, &leader->sibling_list, sibling_list) { n = 0; if ((sub != event) && @@ -9813,7 +9813,6 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, mutex_init(&event->child_mutex); INIT_LIST_HEAD(&event->child_list); - INIT_LIST_HEAD(&event->group_entry); INIT_LIST_HEAD(&event->event_entry); INIT_LIST_HEAD(&event->sibling_list); init_event_group(event); @@ -10581,7 +10580,7 @@ SYSCALL_DEFINE5(perf_event_open, put_ctx(gctx); list_for_each_entry(sibling, &group_leader->sibling_list, - group_entry) { + sibling_list) { perf_remove_from_context(sibling, 0); put_ctx(gctx); } @@ -10603,7 +10602,7 @@ SYSCALL_DEFINE5(perf_event_open, * reachable through the group lists. */ list_for_each_entry(sibling, &group_leader->sibling_list, - group_entry) { + sibling_list) { perf_event__state_init(sibling); perf_install_in_context(ctx, sibling, sibling->cpu); get_ctx(ctx); @@ -11242,7 +11241,7 @@ static int inherit_group(struct perf_event *parent_event, * case inherit_event() will create individual events, similar to what * perf_group_detach() would do anyway. */ - list_for_each_entry(sub, &parent_event->sibling_list, group_entry) { + list_for_each_entry(sub, &parent_event->sibling_list, sibling_list) { child_ctr = inherit_event(sub, parent, parent_ctx, child, leader, child_ctx); if (IS_ERR(child_ctr)) -- cgit v1.2.3 From 6668128a9e25f7a11d25359e46df2541e6b43fc9 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Mon, 13 Nov 2017 14:28:38 +0100 Subject: perf/core: Optimize ctx_sched_out() When an event group contains more events than can be scheduled on the hardware, iterating the full event group for ctx_sched_out is a waste of time. Keep track of the events that got programmed on the hardware, such that we can iterate this smaller list in order to schedule them out. Signed-off-by: Peter Zijlstra (Intel) Acked-by: Mark Rutland Cc: Alexander Shishkin Cc: Alexey Budankov Cc: Arnaldo Carvalho de Melo Cc: David Carrillo-Cisneros Cc: Dmitri Prokhorov Cc: Jiri Olsa Cc: Kan Liang Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Valery Cherepennikov Cc: Vince Weaver Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/perf_event.h | 5 +++++ kernel/events/core.c | 53 +++++++++++++++++++++++++--------------------- 2 files changed, 34 insertions(+), 24 deletions(-) (limited to 'include/linux') diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 84044ec21b31..2bb200e1bbea 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -553,6 +553,7 @@ struct perf_event { * either sufficies for read. */ struct list_head sibling_list; + struct list_head active_list; /* * Node on the pinned or flexible tree located at the event context; */ @@ -718,6 +719,10 @@ struct perf_event_context { struct perf_event_groups pinned_groups; struct perf_event_groups flexible_groups; struct list_head event_list; + + struct list_head pinned_active; + struct list_head flexible_active; + int nr_events; int nr_active; int is_active; diff --git a/kernel/events/core.c b/kernel/events/core.c index 9a07bbe66451..4d601c06074f 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1647,14 +1647,6 @@ perf_event_groups_rotate(struct perf_event_groups *groups, int cpu) typeof(*event), node); event; \ event = rb_entry_safe(rb_next(&event->node), \ typeof(*event), node)) -/* - * Iterate event groups with cpu == key. - */ -#define perf_event_groups_for_each_cpu(event, key, groups, node) \ - for (event = perf_event_groups_first(groups, key); \ - event && event->cpu == key; \ - event = rb_entry_safe(rb_next(&event->node), \ - typeof(*event), node)) /* * Add a event from the lists for its context. @@ -1889,8 +1881,9 @@ list_del_event(struct perf_event *event, struct perf_event_context *ctx) static void perf_group_detach(struct perf_event *event) { struct perf_event *sibling, *tmp; + struct perf_event_context *ctx = event->ctx; - lockdep_assert_held(&event->ctx->lock); + lockdep_assert_held(&ctx->lock); /* * We can have double detach due to exit/hot-unplug + close. @@ -1924,6 +1917,13 @@ static void perf_group_detach(struct perf_event *event) if (!RB_EMPTY_NODE(&event->group_node)) { list_del_init(&sibling->sibling_list); add_event_to_groups(sibling, event->ctx); + + if (sibling->state == PERF_EVENT_STATE_ACTIVE) { + struct list_head *list = sibling->attr.pinned ? + &ctx->pinned_active : &ctx->flexible_active; + + list_add_tail(&sibling->active_list, list); + } } WARN_ON_ONCE(sibling->ctx != event->ctx); @@ -1988,6 +1988,13 @@ event_sched_out(struct perf_event *event, if (event->state != PERF_EVENT_STATE_ACTIVE) return; + /* + * Asymmetry; we only schedule events _IN_ through ctx_sched_in(), but + * we can schedule events _OUT_ individually through things like + * __perf_remove_from_context(). + */ + list_del_init(&event->active_list); + perf_pmu_disable(event->pmu); event->pmu->del(event, 0); @@ -2835,9 +2842,8 @@ static void ctx_sched_out(struct perf_event_context *ctx, struct perf_cpu_context *cpuctx, enum event_type_t event_type) { - int sw = -1, cpu = smp_processor_id(); + struct perf_event *event, *tmp; int is_active = ctx->is_active; - struct perf_event *event; lockdep_assert_held(&ctx->lock); @@ -2884,20 +2890,12 @@ static void ctx_sched_out(struct perf_event_context *ctx, perf_pmu_disable(ctx->pmu); if (is_active & EVENT_PINNED) { - perf_event_groups_for_each_cpu(event, cpu, - &ctx->pinned_groups, group_node) - group_sched_out(event, cpuctx, ctx); - perf_event_groups_for_each_cpu(event, sw, - &ctx->pinned_groups, group_node) + list_for_each_entry_safe(event, tmp, &ctx->pinned_active, active_list) group_sched_out(event, cpuctx, ctx); } if (is_active & EVENT_FLEXIBLE) { - perf_event_groups_for_each_cpu(event, cpu, - &ctx->flexible_groups, group_node) - group_sched_out(event, cpuctx, ctx); - perf_event_groups_for_each_cpu(event, sw, - &ctx->flexible_groups, group_node) + list_for_each_entry_safe(event, tmp, &ctx->flexible_active, active_list) group_sched_out(event, cpuctx, ctx); } perf_pmu_enable(ctx->pmu); @@ -3231,8 +3229,10 @@ static int pinned_sched_in(struct perf_event *event, void *data) if (!event_filter_match(event)) return 0; - if (group_can_go_on(event, sid->cpuctx, sid->can_add_hw)) - group_sched_in(event, sid->cpuctx, sid->ctx); + if (group_can_go_on(event, sid->cpuctx, sid->can_add_hw)) { + if (!group_sched_in(event, sid->cpuctx, sid->ctx)) + list_add_tail(&event->active_list, &sid->ctx->pinned_active); + } /* * If this pinned group hasn't been scheduled, @@ -3255,7 +3255,9 @@ static int flexible_sched_in(struct perf_event *event, void *data) return 0; if (group_can_go_on(event, sid->cpuctx, sid->can_add_hw)) { - if (group_sched_in(event, sid->cpuctx, sid->ctx)) + if (!group_sched_in(event, sid->cpuctx, sid->ctx)) + list_add_tail(&event->active_list, &sid->ctx->flexible_active); + else sid->can_add_hw = 0; } @@ -3973,6 +3975,8 @@ static void __perf_event_init_context(struct perf_event_context *ctx) perf_event_groups_init(&ctx->pinned_groups); perf_event_groups_init(&ctx->flexible_groups); INIT_LIST_HEAD(&ctx->event_list); + INIT_LIST_HEAD(&ctx->pinned_active); + INIT_LIST_HEAD(&ctx->flexible_active); atomic_set(&ctx->refcount, 1); } @@ -9815,6 +9819,7 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, INIT_LIST_HEAD(&event->event_entry); INIT_LIST_HEAD(&event->sibling_list); + INIT_LIST_HEAD(&event->active_list); init_event_group(event); INIT_LIST_HEAD(&event->rb_entry); INIT_LIST_HEAD(&event->active_entry); -- cgit v1.2.3 From a2c054a896b8ac794ddcfc7c92e2dc7ec4ed4ed5 Mon Sep 17 00:00:00 2001 From: Brad Mouring Date: Thu, 8 Mar 2018 16:23:03 -0600 Subject: net: phy: Tell caller result of phy_change() In 664fcf123a30e (net: phy: Threaded interrupts allow some simplification) the phy_interrupt system was changed to use a traditional threaded interrupt scheme instead of a workqueue approach. With this change, the phy status check moved into phy_change, which did not report back to the caller whether or not the interrupt was handled. This means that, in the case of a shared phy interrupt, only the first phydev's interrupt registers are checked (since phy_interrupt() would always return IRQ_HANDLED). This leads to interrupt storms when it is a secondary device that's actually the interrupt source. Signed-off-by: Brad Mouring Signed-off-by: David S. Miller --- drivers/net/phy/phy.c | 145 +++++++++++++++++++++++++------------------------- include/linux/phy.h | 1 - 2 files changed, 72 insertions(+), 74 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index a6f924fee584..9aabfa1a455a 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -617,6 +617,77 @@ static void phy_error(struct phy_device *phydev) phy_trigger_machine(phydev, false); } +/** + * phy_disable_interrupts - Disable the PHY interrupts from the PHY side + * @phydev: target phy_device struct + */ +static int phy_disable_interrupts(struct phy_device *phydev) +{ + int err; + + /* Disable PHY interrupts */ + err = phy_config_interrupt(phydev, PHY_INTERRUPT_DISABLED); + if (err) + goto phy_err; + + /* Clear the interrupt */ + err = phy_clear_interrupt(phydev); + if (err) + goto phy_err; + + return 0; + +phy_err: + phy_error(phydev); + + return err; +} + +/** + * phy_change - Called by the phy_interrupt to handle PHY changes + * @phydev: phy_device struct that interrupted + */ +static irqreturn_t phy_change(struct phy_device *phydev) +{ + if (phy_interrupt_is_valid(phydev)) { + if (phydev->drv->did_interrupt && + !phydev->drv->did_interrupt(phydev)) + return IRQ_NONE; + + if (phydev->state == PHY_HALTED) + if (phy_disable_interrupts(phydev)) + goto phy_err; + } + + mutex_lock(&phydev->lock); + if ((PHY_RUNNING == phydev->state) || (PHY_NOLINK == phydev->state)) + phydev->state = PHY_CHANGELINK; + mutex_unlock(&phydev->lock); + + /* reschedule state queue work to run as soon as possible */ + phy_trigger_machine(phydev, true); + + if (phy_interrupt_is_valid(phydev) && phy_clear_interrupt(phydev)) + goto phy_err; + return IRQ_HANDLED; + +phy_err: + phy_error(phydev); + return IRQ_NONE; +} + +/** + * phy_change_work - Scheduled by the phy_mac_interrupt to handle PHY changes + * @work: work_struct that describes the work to be done + */ +void phy_change_work(struct work_struct *work) +{ + struct phy_device *phydev = + container_of(work, struct phy_device, phy_queue); + + phy_change(phydev); +} + /** * phy_interrupt - PHY interrupt handler * @irq: interrupt line @@ -632,9 +703,7 @@ static irqreturn_t phy_interrupt(int irq, void *phy_dat) if (PHY_HALTED == phydev->state) return IRQ_NONE; /* It can't be ours. */ - phy_change(phydev); - - return IRQ_HANDLED; + return phy_change(phydev); } /** @@ -651,32 +720,6 @@ static int phy_enable_interrupts(struct phy_device *phydev) return phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED); } -/** - * phy_disable_interrupts - Disable the PHY interrupts from the PHY side - * @phydev: target phy_device struct - */ -static int phy_disable_interrupts(struct phy_device *phydev) -{ - int err; - - /* Disable PHY interrupts */ - err = phy_config_interrupt(phydev, PHY_INTERRUPT_DISABLED); - if (err) - goto phy_err; - - /* Clear the interrupt */ - err = phy_clear_interrupt(phydev); - if (err) - goto phy_err; - - return 0; - -phy_err: - phy_error(phydev); - - return err; -} - /** * phy_start_interrupts - request and enable interrupts for a PHY device * @phydev: target phy_device struct @@ -719,50 +762,6 @@ int phy_stop_interrupts(struct phy_device *phydev) } EXPORT_SYMBOL(phy_stop_interrupts); -/** - * phy_change - Called by the phy_interrupt to handle PHY changes - * @phydev: phy_device struct that interrupted - */ -void phy_change(struct phy_device *phydev) -{ - if (phy_interrupt_is_valid(phydev)) { - if (phydev->drv->did_interrupt && - !phydev->drv->did_interrupt(phydev)) - return; - - if (phydev->state == PHY_HALTED) - if (phy_disable_interrupts(phydev)) - goto phy_err; - } - - mutex_lock(&phydev->lock); - if ((PHY_RUNNING == phydev->state) || (PHY_NOLINK == phydev->state)) - phydev->state = PHY_CHANGELINK; - mutex_unlock(&phydev->lock); - - /* reschedule state queue work to run as soon as possible */ - phy_trigger_machine(phydev, true); - - if (phy_interrupt_is_valid(phydev) && phy_clear_interrupt(phydev)) - goto phy_err; - return; - -phy_err: - phy_error(phydev); -} - -/** - * phy_change_work - Scheduled by the phy_mac_interrupt to handle PHY changes - * @work: work_struct that describes the work to be done - */ -void phy_change_work(struct work_struct *work) -{ - struct phy_device *phydev = - container_of(work, struct phy_device, phy_queue); - - phy_change(phydev); -} - /** * phy_stop - Bring down the PHY link, and stop checking the status * @phydev: target phy_device struct diff --git a/include/linux/phy.h b/include/linux/phy.h index d7069539f351..b260fb336b25 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1012,7 +1012,6 @@ int phy_driver_register(struct phy_driver *new_driver, struct module *owner); int phy_drivers_register(struct phy_driver *new_driver, int n, struct module *owner); void phy_state_machine(struct work_struct *work); -void phy_change(struct phy_device *phydev); void phy_change_work(struct work_struct *work); void phy_mac_interrupt(struct phy_device *phydev); void phy_start_machine(struct phy_device *phydev); -- cgit v1.2.3 From bf2ae2e4bf9360e07c0cdfa166bcdc0afd92f4ce Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sat, 10 Mar 2018 18:57:50 +0800 Subject: sock_diag: request _diag module only when the family or proto has been registered Now when using 'ss' in iproute, kernel would try to load all _diag modules, which also causes corresponding family and proto modules to be loaded as well due to module dependencies. Like after running 'ss', sctp, dccp, af_packet (if it works as a module) would be loaded. For example: $ lsmod|grep sctp $ ss $ lsmod|grep sctp sctp_diag 16384 0 sctp 323584 5 sctp_diag inet_diag 24576 4 raw_diag,tcp_diag,sctp_diag,udp_diag libcrc32c 16384 3 nf_conntrack,nf_nat,sctp As these family and proto modules are loaded unintentionally, it could cause some problems, like: - Some debug tools use 'ss' to collect the socket info, which loads all those diag and family and protocol modules. It's noisy for identifying issues. - Users usually expect to drop sctp init packet silently when they have no sense of sctp protocol instead of sending abort back. - It wastes resources (especially with multiple netns), and SCTP module can't be unloaded once it's loaded. ... In short, it's really inappropriate to have these family and proto modules loaded unexpectedly when just doing debugging with inet_diag. This patch is to introduce sock_load_diag_module() where it loads the _diag module only when it's corresponding family or proto has been already registered. Note that we can't just load _diag module without the family or proto loaded, as some symbols used in _diag module are from the family or proto module. v1->v2: - move inet proto check to inet_diag to avoid a compiling err. v2->v3: - define sock_load_diag_module in sock.c and export one symbol only. - improve the changelog. Reported-by: Sabrina Dubroca Acked-by: Marcelo Ricardo Leitner Acked-by: Phil Sutter Acked-by: Sabrina Dubroca Signed-off-by: Xin Long Signed-off-by: David S. Miller --- include/linux/net.h | 1 + include/net/sock.h | 1 + net/core/sock.c | 21 +++++++++++++++++++++ net/core/sock_diag.c | 12 ++++-------- net/ipv4/inet_diag.c | 3 +-- net/socket.c | 5 +++++ 6 files changed, 33 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/include/linux/net.h b/include/linux/net.h index 91216b16feb7..2a0391eea05c 100644 --- a/include/linux/net.h +++ b/include/linux/net.h @@ -222,6 +222,7 @@ enum { int sock_wake_async(struct socket_wq *sk_wq, int how, int band); int sock_register(const struct net_proto_family *fam); void sock_unregister(int family); +bool sock_is_registered(int family); int __sock_create(struct net *net, int family, int type, int proto, struct socket **res, int kern); int sock_create(int family, int type, int proto, struct socket **res); diff --git a/include/net/sock.h b/include/net/sock.h index 169c92afcafa..ae23f3b389ca 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1137,6 +1137,7 @@ struct proto { int proto_register(struct proto *prot, int alloc_slab); void proto_unregister(struct proto *prot); +int sock_load_diag_module(int family, int protocol); #ifdef SOCK_REFCNT_DEBUG static inline void sk_refcnt_debug_inc(struct sock *sk) diff --git a/net/core/sock.c b/net/core/sock.c index c501499a04fe..85b0b64e7f9d 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -3261,6 +3261,27 @@ void proto_unregister(struct proto *prot) } EXPORT_SYMBOL(proto_unregister); +int sock_load_diag_module(int family, int protocol) +{ + if (!protocol) { + if (!sock_is_registered(family)) + return -ENOENT; + + return request_module("net-pf-%d-proto-%d-type-%d", PF_NETLINK, + NETLINK_SOCK_DIAG, family); + } + +#ifdef CONFIG_INET + if (family == AF_INET && + !rcu_access_pointer(inet_protos[protocol])) + return -ENOENT; +#endif + + return request_module("net-pf-%d-proto-%d-type-%d-%d", PF_NETLINK, + NETLINK_SOCK_DIAG, family, protocol); +} +EXPORT_SYMBOL(sock_load_diag_module); + #ifdef CONFIG_PROC_FS static void *proto_seq_start(struct seq_file *seq, loff_t *pos) __acquires(proto_list_mutex) diff --git a/net/core/sock_diag.c b/net/core/sock_diag.c index 146b50e30659..c37b5be7c5e4 100644 --- a/net/core/sock_diag.c +++ b/net/core/sock_diag.c @@ -220,8 +220,7 @@ static int __sock_diag_cmd(struct sk_buff *skb, struct nlmsghdr *nlh) return -EINVAL; if (sock_diag_handlers[req->sdiag_family] == NULL) - request_module("net-pf-%d-proto-%d-type-%d", PF_NETLINK, - NETLINK_SOCK_DIAG, req->sdiag_family); + sock_load_diag_module(req->sdiag_family, 0); mutex_lock(&sock_diag_table_mutex); hndl = sock_diag_handlers[req->sdiag_family]; @@ -247,8 +246,7 @@ static int sock_diag_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh, case TCPDIAG_GETSOCK: case DCCPDIAG_GETSOCK: if (inet_rcv_compat == NULL) - request_module("net-pf-%d-proto-%d-type-%d", PF_NETLINK, - NETLINK_SOCK_DIAG, AF_INET); + sock_load_diag_module(AF_INET, 0); mutex_lock(&sock_diag_table_mutex); if (inet_rcv_compat != NULL) @@ -281,14 +279,12 @@ static int sock_diag_bind(struct net *net, int group) case SKNLGRP_INET_TCP_DESTROY: case SKNLGRP_INET_UDP_DESTROY: if (!sock_diag_handlers[AF_INET]) - request_module("net-pf-%d-proto-%d-type-%d", PF_NETLINK, - NETLINK_SOCK_DIAG, AF_INET); + sock_load_diag_module(AF_INET, 0); break; case SKNLGRP_INET6_TCP_DESTROY: case SKNLGRP_INET6_UDP_DESTROY: if (!sock_diag_handlers[AF_INET6]) - request_module("net-pf-%d-proto-%d-type-%d", PF_NETLINK, - NETLINK_SOCK_DIAG, AF_INET6); + sock_load_diag_module(AF_INET6, 0); break; } return 0; diff --git a/net/ipv4/inet_diag.c b/net/ipv4/inet_diag.c index a383f299ce24..4e5bc4b2f14e 100644 --- a/net/ipv4/inet_diag.c +++ b/net/ipv4/inet_diag.c @@ -53,8 +53,7 @@ static DEFINE_MUTEX(inet_diag_table_mutex); static const struct inet_diag_handler *inet_diag_lock_handler(int proto) { if (!inet_diag_table[proto]) - request_module("net-pf-%d-proto-%d-type-%d-%d", PF_NETLINK, - NETLINK_SOCK_DIAG, AF_INET, proto); + sock_load_diag_module(AF_INET, proto); mutex_lock(&inet_diag_table_mutex); if (!inet_diag_table[proto]) diff --git a/net/socket.c b/net/socket.c index a93c99b518ca..08847c3b8c39 100644 --- a/net/socket.c +++ b/net/socket.c @@ -2587,6 +2587,11 @@ void sock_unregister(int family) } EXPORT_SYMBOL(sock_unregister); +bool sock_is_registered(int family) +{ + return family < NPROTO && rcu_access_pointer(net_families[family]); +} + static int __init sock_init(void) { int err; -- cgit v1.2.3 From c8f4c36f81623002165dce874fa60bb0c154b10e Mon Sep 17 00:00:00 2001 From: Nikolay Borisov Date: Fri, 23 Feb 2018 13:45:28 +0200 Subject: direct-io: Remove unused DIO_ASYNC_EXTEND flag This flag was added by 6039257378e4 ("direct-io: add flag to allow aio writes beyond i_size") to support XFS. However, with the rework of XFS' DIO's path to use iomap in acdda3aae146 ("xfs: use iomap_dio_rw") it became redundant. So let's remove it. Reviewed-by: Christoph Hellwig Signed-off-by: Nikolay Borisov Signed-off-by: Jens Axboe --- fs/direct-io.c | 3 +-- include/linux/fs.h | 3 --- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'include/linux') diff --git a/fs/direct-io.c b/fs/direct-io.c index 1357ef563893..88f0c7fba1ce 100644 --- a/fs/direct-io.c +++ b/fs/direct-io.c @@ -1252,8 +1252,7 @@ do_blockdev_direct_IO(struct kiocb *iocb, struct inode *inode, */ if (is_sync_kiocb(iocb)) dio->is_async = false; - else if (!(dio->flags & DIO_ASYNC_EXTEND) && - iov_iter_rw(iter) == WRITE && end > i_size_read(inode)) + else if (iov_iter_rw(iter) == WRITE && end > i_size_read(inode)) dio->is_async = false; else dio->is_async = true; diff --git a/include/linux/fs.h b/include/linux/fs.h index 2a815560fda0..260c233e7375 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2977,9 +2977,6 @@ enum { /* filesystem does not support filling holes */ DIO_SKIP_HOLES = 0x02, - /* filesystem can handle aio writes beyond i_size */ - DIO_ASYNC_EXTEND = 0x04, - /* inode/fs/bdev does not need truncate protection */ DIO_SKIP_DIO_COUNT = 0x08, }; -- cgit v1.2.3 From ce3077ee80d6ac1087c06441f4c63ce5f13ef12c Mon Sep 17 00:00:00 2001 From: Nikolay Borisov Date: Fri, 23 Feb 2018 13:45:29 +0200 Subject: direct-io: Remove unused DIO_SKIP_DIO_COUNT logic This flag was added by fe0f07d08ee3 ("direct-io: only inc/deci inode->i_dio_count for file systems") as means to optimise the atomic modificaiton of the variable for blockdevices. However with the advent of 542ff7bf18c6 ("block: new direct I/O implementation") it became unused. So let's remove it. Reviewed-by: Christoph Hellwig Signed-off-by: Nikolay Borisov Signed-off-by: Jens Axboe --- fs/direct-io.c | 6 ++---- include/linux/fs.h | 3 --- 2 files changed, 2 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/fs/direct-io.c b/fs/direct-io.c index 88f0c7fba1ce..ba12ee659673 100644 --- a/fs/direct-io.c +++ b/fs/direct-io.c @@ -315,8 +315,7 @@ static ssize_t dio_complete(struct dio *dio, ssize_t ret, unsigned int flags) dio_warn_stale_pagecache(dio->iocb->ki_filp); } - if (!(dio->flags & DIO_SKIP_DIO_COUNT)) - inode_dio_end(dio->inode); + inode_dio_end(dio->inode); if (flags & DIO_COMPLETE_ASYNC) { /* @@ -1296,8 +1295,7 @@ do_blockdev_direct_IO(struct kiocb *iocb, struct inode *inode, /* * Will be decremented at I/O completion time. */ - if (!(dio->flags & DIO_SKIP_DIO_COUNT)) - inode_dio_begin(inode); + inode_dio_begin(inode); retval = 0; sdio.blkbits = blkbits; diff --git a/include/linux/fs.h b/include/linux/fs.h index 260c233e7375..9bee267209e5 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2976,9 +2976,6 @@ enum { /* filesystem does not support filling holes */ DIO_SKIP_HOLES = 0x02, - - /* inode/fs/bdev does not need truncate protection */ - DIO_SKIP_DIO_COUNT = 0x08, }; void dio_end_io(struct bio *bio); -- cgit v1.2.3 From e6d3cc7b1fac3d7f1313faf8ac9b23830113e3ec Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Feb 2018 14:43:33 +0100 Subject: clk: divider: export clk_div_mask() helper Export clk_div_mask() in clk-provider header so every clock providers derived from the generic clock divider may share the definition instead of redefining it. Signed-off-by: Jerome Brunet Signed-off-by: Michael Turquette Signed-off-by: Stephen Boyd --- drivers/clk/clk-divider.c | 24 +++++++++++------------- include/linux/clk-provider.h | 1 + 2 files changed, 12 insertions(+), 13 deletions(-) (limited to 'include/linux') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index b49942b9fe50..3c98d2650fa3 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -28,12 +28,10 @@ * parent - fixed parent. No clk_set_parent support */ -#define div_mask(width) ((1 << (width)) - 1) - static unsigned int _get_table_maxdiv(const struct clk_div_table *table, u8 width) { - unsigned int maxdiv = 0, mask = div_mask(width); + unsigned int maxdiv = 0, mask = clk_div_mask(width); const struct clk_div_table *clkt; for (clkt = table; clkt->div; clkt++) @@ -57,12 +55,12 @@ static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width, unsigned long flags) { if (flags & CLK_DIVIDER_ONE_BASED) - return div_mask(width); + return clk_div_mask(width); if (flags & CLK_DIVIDER_POWER_OF_TWO) - return 1 << div_mask(width); + return 1 << clk_div_mask(width); if (table) return _get_table_maxdiv(table, width); - return div_mask(width) + 1; + return clk_div_mask(width) + 1; } static unsigned int _get_table_div(const struct clk_div_table *table, @@ -84,7 +82,7 @@ static unsigned int _get_div(const struct clk_div_table *table, if (flags & CLK_DIVIDER_POWER_OF_TWO) return 1 << val; if (flags & CLK_DIVIDER_MAX_AT_ZERO) - return val ? val : div_mask(width) + 1; + return val ? val : clk_div_mask(width) + 1; if (table) return _get_table_div(table, val); return val + 1; @@ -109,7 +107,7 @@ static unsigned int _get_val(const struct clk_div_table *table, if (flags & CLK_DIVIDER_POWER_OF_TWO) return __ffs(div); if (flags & CLK_DIVIDER_MAX_AT_ZERO) - return (div == div_mask(width) + 1) ? 0 : div; + return (div == clk_div_mask(width) + 1) ? 0 : div; if (table) return _get_table_val(table, div); return div - 1; @@ -141,7 +139,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, unsigned int val; val = clk_readl(divider->reg) >> divider->shift; - val &= div_mask(divider->width); + val &= clk_div_mask(divider->width); return divider_recalc_rate(hw, parent_rate, val, divider->table, divider->flags, divider->width); @@ -353,7 +351,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { bestdiv = clk_readl(divider->reg) >> divider->shift; - bestdiv &= div_mask(divider->width); + bestdiv &= clk_div_mask(divider->width); bestdiv = _get_div(divider->table, bestdiv, divider->flags, divider->width); return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); @@ -376,7 +374,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, value = _get_val(table, div, flags, width); - return min_t(unsigned int, value, div_mask(width)); + return min_t(unsigned int, value, clk_div_mask(width)); } EXPORT_SYMBOL_GPL(divider_get_val); @@ -399,10 +397,10 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, __acquire(divider->lock); if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { - val = div_mask(divider->width) << (divider->shift + 16); + val = clk_div_mask(divider->width) << (divider->shift + 16); } else { val = clk_readl(divider->reg); - val &= ~(div_mask(divider->width) << divider->shift); + val &= ~(clk_div_mask(divider->width) << divider->shift); } val |= (u32)value << divider->shift; clk_writel(val, divider->reg); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index f711be6e8c44..d8ba26d03332 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -399,6 +399,7 @@ struct clk_divider { spinlock_t *lock; }; +#define clk_div_mask(width) ((1 << (width)) - 1) #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) #define CLK_DIVIDER_ONE_BASED BIT(0) -- cgit v1.2.3 From 77deb66d262f8512130ff75ec5ea8e31070b41ed Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Feb 2018 14:43:34 +0100 Subject: clk: mux: add helper function for index/value translation Add helper functions for the translation between parent index and register value in the generic multiplexer function. The purpose of this change is avoid duplicating the code in other clock providers, using the same generic logic. Signed-off-by: Jerome Brunet Signed-off-by: Michael Turquette Signed-off-by: Stephen Boyd --- drivers/clk/clk-mux.c | 75 +++++++++++++++++++++++++------------------- include/linux/clk-provider.h | 4 +++ 2 files changed, 47 insertions(+), 32 deletions(-) (limited to 'include/linux') diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 39cabe157163..ac4a042f8658 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -26,35 +26,24 @@ * parent - parent is adjustable through clk_set_parent */ -static u8 clk_mux_get_parent(struct clk_hw *hw) +int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, + unsigned int val) { - struct clk_mux *mux = to_clk_mux(hw); int num_parents = clk_hw_get_num_parents(hw); - u32 val; - /* - * FIXME need a mux-specific flag to determine if val is bitwise or numeric - * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 - * to 0x7 (index starts at one) - * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so - * val = 0x4 really means "bit 2, index starts at bit 0" - */ - val = clk_readl(mux->reg) >> mux->shift; - val &= mux->mask; - - if (mux->table) { + if (table) { int i; for (i = 0; i < num_parents; i++) - if (mux->table[i] == val) + if (table[i] == val) return i; return -EINVAL; } - if (val && (mux->flags & CLK_MUX_INDEX_BIT)) + if (val && (flags & CLK_MUX_INDEX_BIT)) val = ffs(val) - 1; - if (val && (mux->flags & CLK_MUX_INDEX_ONE)) + if (val && (flags & CLK_MUX_INDEX_ONE)) val--; if (val >= num_parents) @@ -62,36 +51,58 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) return val; } +EXPORT_SYMBOL_GPL(clk_mux_val_to_index); -static int clk_mux_set_parent(struct clk_hw *hw, u8 index) +unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index) { - struct clk_mux *mux = to_clk_mux(hw); - u32 val; - unsigned long flags = 0; + unsigned int val = index; - if (mux->table) { - index = mux->table[index]; + if (table) { + val = table[index]; } else { - if (mux->flags & CLK_MUX_INDEX_BIT) - index = 1 << index; + if (flags & CLK_MUX_INDEX_BIT) + val = 1 << index; - if (mux->flags & CLK_MUX_INDEX_ONE) - index++; + if (flags & CLK_MUX_INDEX_ONE) + val++; } + return val; +} +EXPORT_SYMBOL_GPL(clk_mux_index_to_val); + +static u8 clk_mux_get_parent(struct clk_hw *hw) +{ + struct clk_mux *mux = to_clk_mux(hw); + u32 val; + + val = clk_readl(mux->reg) >> mux->shift; + val &= mux->mask; + + return clk_mux_val_to_index(hw, mux->table, mux->flags, val); +} + +static int clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_mux *mux = to_clk_mux(hw); + u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); + unsigned long flags = 0; + u32 reg; + if (mux->lock) spin_lock_irqsave(mux->lock, flags); else __acquire(mux->lock); if (mux->flags & CLK_MUX_HIWORD_MASK) { - val = mux->mask << (mux->shift + 16); + reg = mux->mask << (mux->shift + 16); } else { - val = clk_readl(mux->reg); - val &= ~(mux->mask << mux->shift); + reg = clk_readl(mux->reg); + reg &= ~(mux->mask << mux->shift); } - val |= index << mux->shift; - clk_writel(val, mux->reg); + val = val << mux->shift; + reg |= val; + clk_writel(reg, mux->reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index d8ba26d03332..fe720d679c31 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -511,6 +511,10 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); +int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, + unsigned int val); +unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); + void clk_unregister_mux(struct clk *clk); void clk_hw_unregister_mux(struct clk_hw *hw); -- cgit v1.2.3 From fe3f338f0cb2ed4d4f06da054c21ae2f8a36ef2d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Feb 2018 14:43:38 +0100 Subject: clk: fix mux clock documentation The mux documentation mentions the non-existing parameter width instead of mask, so just sed this. The table field is missing in the documentation of clk_mux. Add a small blurb explaining what it is Fixes: 9d9f78ed9af0 ("clk: basic clock hardware types") Signed-off-by: Jerome Brunet Signed-off-by: Michael Turquette Signed-off-by: Stephen Boyd --- include/linux/clk-provider.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index fe720d679c31..cb18526d69cb 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -450,8 +450,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw); * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer + * @table: array of register values corresponding to the parent index * @shift: shift to multiplexer bit field - * @width: width of mutliplexer bit field + * @mask: mask of mutliplexer bit field * @flags: hardware-specific flags * @lock: register lock * -- cgit v1.2.3 From b15ee490e16324c35b51f04bad54ae45a2cefd29 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Feb 2018 14:43:39 +0100 Subject: clk: divider: read-only divider can propagate rate change When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the register shall be left un-touched, but it does not mean the clock should stop rate propagation if CLK_SET_RATE_PARENT is set This is properly handled in qcom clk-regmap-divider but it was not in the generic divider To fix this situation, introduce a new helper function divider_ro_round_rate, on the same model as divider_round_rate. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Signed-off-by: Jerome Brunet Tested-By: David Lechner Signed-off-by: Michael Turquette Signed-off-by: Stephen Boyd --- drivers/clk/clk-divider.c | 36 ++++++++++++++++++++++++++++++------ include/linux/clk-provider.h | 15 +++++++++++++++ 2 files changed, 45 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 3c98d2650fa3..b6234a5da12d 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -342,19 +342,43 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, } EXPORT_SYMBOL_GPL(divider_round_rate_parent); +long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, + unsigned long rate, unsigned long *prate, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val) +{ + int div; + + div = _get_div(table, val, flags, width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!parent) + return -EINVAL; + + *prate = clk_hw_round_rate(parent, rate * div); + } + + return DIV_ROUND_UP_ULL((u64)*prate, div); +} +EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent); + + static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_divider *divider = to_clk_divider(hw); - int bestdiv; /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { - bestdiv = clk_readl(divider->reg) >> divider->shift; - bestdiv &= clk_div_mask(divider->width); - bestdiv = _get_div(divider->table, bestdiv, divider->flags, - divider->width); - return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); + u32 val; + + val = clk_readl(divider->reg) >> divider->shift; + val &= clk_div_mask(divider->width); + + return divider_ro_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags, + val); } return divider_round_rate(hw, rate, prate, divider->table, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index cb18526d69cb..210a890008f9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -420,6 +420,10 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags); +long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, + unsigned long rate, unsigned long *prate, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags); @@ -780,6 +784,17 @@ static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, rate, prate, table, width, flags); } +static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate, + const struct clk_div_table *table, + u8 width, unsigned long flags, + unsigned int val) +{ + return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), + rate, prate, table, width, flags, + val); +} + /* * FIXME clock api without lock protection */ -- cgit v1.2.3 From bdbc90fa55af632f8a883a3d93c54a08708ed80a Mon Sep 17 00:00:00 2001 From: Yunlong Song Date: Wed, 28 Feb 2018 20:31:52 +0800 Subject: f2fs: don't put dentry page in pagecache into highmem Previous dentry page uses highmem, which will cause panic in platforms using highmem (such as arm), since the address space of dentry pages from highmem directly goes into the decryption path via the function fscrypt_fname_disk_to_usr. But sg_init_one assumes the address is not from highmem, and then cause panic since it doesn't call kmap_high but kunmap_high is triggered at the end. To fix this problem in a simple way, this patch avoids to put dentry page in pagecache into highmem. Signed-off-by: Yunlong Song Reviewed-by: Chao Yu [Jaegeuk Kim: fix coding style] Signed-off-by: Jaegeuk Kim --- fs/f2fs/dir.c | 23 +++++------------------ fs/f2fs/f2fs.h | 6 ------ fs/f2fs/inline.c | 3 +-- fs/f2fs/inode.c | 2 +- fs/f2fs/namei.c | 32 ++++++++------------------------ fs/f2fs/recovery.c | 11 +++++------ include/linux/f2fs_fs.h | 1 - 7 files changed, 20 insertions(+), 58 deletions(-) (limited to 'include/linux') diff --git a/fs/f2fs/dir.c b/fs/f2fs/dir.c index f00b5ed8c011..797eb05cb538 100644 --- a/fs/f2fs/dir.c +++ b/fs/f2fs/dir.c @@ -94,14 +94,12 @@ static struct f2fs_dir_entry *find_in_block(struct page *dentry_page, struct f2fs_dir_entry *de; struct f2fs_dentry_ptr d; - dentry_blk = (struct f2fs_dentry_block *)kmap(dentry_page); + dentry_blk = (struct f2fs_dentry_block *)page_address(dentry_page); make_dentry_ptr_block(NULL, &d, dentry_blk); de = find_target_dentry(fname, namehash, max_slots, &d); if (de) *res_page = dentry_page; - else - kunmap(dentry_page); return de; } @@ -287,7 +285,6 @@ ino_t f2fs_inode_by_name(struct inode *dir, const struct qstr *qstr, de = f2fs_find_entry(dir, qstr, page); if (de) { res = le32_to_cpu(de->ino); - f2fs_dentry_kunmap(dir, *page); f2fs_put_page(*page, 0); } @@ -302,7 +299,6 @@ void f2fs_set_link(struct inode *dir, struct f2fs_dir_entry *de, f2fs_wait_on_page_writeback(page, type, true); de->ino = cpu_to_le32(inode->i_ino); set_de_type(de, inode->i_mode); - f2fs_dentry_kunmap(dir, page); set_page_dirty(page); dir->i_mtime = dir->i_ctime = current_time(dir); @@ -350,13 +346,11 @@ static int make_empty_dir(struct inode *inode, if (IS_ERR(dentry_page)) return PTR_ERR(dentry_page); - dentry_blk = kmap_atomic(dentry_page); + dentry_blk = page_address(dentry_page); make_dentry_ptr_block(NULL, &d, dentry_blk); do_make_empty_dir(inode, parent, &d); - kunmap_atomic(dentry_blk); - set_page_dirty(dentry_page); f2fs_put_page(dentry_page, 1); return 0; @@ -547,13 +541,12 @@ start: if (IS_ERR(dentry_page)) return PTR_ERR(dentry_page); - dentry_blk = kmap(dentry_page); + dentry_blk = page_address(dentry_page); bit_pos = room_for_filename(&dentry_blk->dentry_bitmap, slots, NR_DENTRY_IN_BLOCK); if (bit_pos < NR_DENTRY_IN_BLOCK) goto add_dentry; - kunmap(dentry_page); f2fs_put_page(dentry_page, 1); } @@ -588,7 +581,6 @@ fail: if (inode) up_write(&F2FS_I(inode)->i_sem); - kunmap(dentry_page); f2fs_put_page(dentry_page, 1); return err; @@ -642,7 +634,6 @@ int __f2fs_add_link(struct inode *dir, const struct qstr *name, F2FS_I(dir)->task = NULL; } if (de) { - f2fs_dentry_kunmap(dir, page); f2fs_put_page(page, 0); err = -EEXIST; } else if (IS_ERR(page)) { @@ -730,7 +721,6 @@ void f2fs_delete_entry(struct f2fs_dir_entry *dentry, struct page *page, bit_pos = find_next_bit_le(&dentry_blk->dentry_bitmap, NR_DENTRY_IN_BLOCK, 0); - kunmap(page); /* kunmap - pair of f2fs_find_entry */ set_page_dirty(page); dir->i_ctime = dir->i_mtime = current_time(dir); @@ -775,7 +765,7 @@ bool f2fs_empty_dir(struct inode *dir) return false; } - dentry_blk = kmap_atomic(dentry_page); + dentry_blk = page_address(dentry_page); if (bidx == 0) bit_pos = 2; else @@ -783,7 +773,6 @@ bool f2fs_empty_dir(struct inode *dir) bit_pos = find_next_bit_le(&dentry_blk->dentry_bitmap, NR_DENTRY_IN_BLOCK, bit_pos); - kunmap_atomic(dentry_blk); f2fs_put_page(dentry_page, 1); @@ -901,19 +890,17 @@ static int f2fs_readdir(struct file *file, struct dir_context *ctx) } } - dentry_blk = kmap(dentry_page); + dentry_blk = page_address(dentry_page); make_dentry_ptr_block(inode, &d, dentry_blk); err = f2fs_fill_dentries(ctx, &d, n * NR_DENTRY_IN_BLOCK, &fstr); if (err) { - kunmap(dentry_page); f2fs_put_page(dentry_page, 1); break; } - kunmap(dentry_page); f2fs_put_page(dentry_page, 1); } out_free: diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 6300ac5bcbe4..8b652e000326 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -2399,12 +2399,6 @@ static inline int f2fs_has_inline_dentry(struct inode *inode) return is_inode_flag_set(inode, FI_INLINE_DENTRY); } -static inline void f2fs_dentry_kunmap(struct inode *dir, struct page *page) -{ - if (!f2fs_has_inline_dentry(dir)) - kunmap(page); -} - static inline int is_file(struct inode *inode, int type) { return F2FS_I(inode)->i_advise & type; diff --git a/fs/f2fs/inline.c b/fs/f2fs/inline.c index 90e38d8ea688..3b77d6421218 100644 --- a/fs/f2fs/inline.c +++ b/fs/f2fs/inline.c @@ -369,7 +369,7 @@ static int f2fs_move_inline_dirents(struct inode *dir, struct page *ipage, f2fs_wait_on_page_writeback(page, DATA, true); zero_user_segment(page, MAX_INLINE_DATA(dir), PAGE_SIZE); - dentry_blk = kmap_atomic(page); + dentry_blk = page_address(page); make_dentry_ptr_inline(dir, &src, inline_dentry); make_dentry_ptr_block(dir, &dst, dentry_blk); @@ -386,7 +386,6 @@ static int f2fs_move_inline_dirents(struct inode *dir, struct page *ipage, memcpy(dst.dentry, src.dentry, SIZE_OF_DIR_ENTRY * src.max); memcpy(dst.filename, src.filename, src.max * F2FS_SLOT_LEN); - kunmap_atomic(dentry_blk); if (!PageUptodate(page)) SetPageUptodate(page); set_page_dirty(page); diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index 205add3d0f3a..4efc815129b1 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -328,7 +328,7 @@ make_now: inode->i_op = &f2fs_dir_inode_operations; inode->i_fop = &f2fs_dir_operations; inode->i_mapping->a_ops = &f2fs_dblock_aops; - mapping_set_gfp_mask(inode->i_mapping, GFP_F2FS_HIGH_ZERO); + inode_nohighmem(inode); } else if (S_ISLNK(inode->i_mode)) { if (f2fs_encrypted_inode(inode)) inode->i_op = &f2fs_encrypted_symlink_inode_operations; diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index b68e7b03959f..2ebf3d045dd2 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -317,7 +317,6 @@ static int __recover_dot_dentries(struct inode *dir, nid_t pino) de = f2fs_find_entry(dir, &dot, &page); if (de) { - f2fs_dentry_kunmap(dir, page); f2fs_put_page(page, 0); } else if (IS_ERR(page)) { err = PTR_ERR(page); @@ -329,14 +328,12 @@ static int __recover_dot_dentries(struct inode *dir, nid_t pino) } de = f2fs_find_entry(dir, &dotdot, &page); - if (de) { - f2fs_dentry_kunmap(dir, page); + if (de) f2fs_put_page(page, 0); - } else if (IS_ERR(page)) { + else if (IS_ERR(page)) err = PTR_ERR(page); - } else { + else err = __f2fs_add_link(dir, &dotdot, NULL, pino, S_IFDIR); - } out: if (!err) clear_inode_flag(dir, FI_INLINE_DOTS); @@ -377,7 +374,6 @@ static struct dentry *f2fs_lookup(struct inode *dir, struct dentry *dentry, } ino = le32_to_cpu(de->ino); - f2fs_dentry_kunmap(dir, page); f2fs_put_page(page, 0); inode = f2fs_iget(dir->i_sb, ino); @@ -452,7 +448,6 @@ static int f2fs_unlink(struct inode *dir, struct dentry *dentry) err = acquire_orphan_inode(sbi); if (err) { f2fs_unlock_op(sbi); - f2fs_dentry_kunmap(dir, page); f2fs_put_page(page, 0); goto fail; } @@ -579,7 +574,7 @@ static int f2fs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) inode->i_op = &f2fs_dir_inode_operations; inode->i_fop = &f2fs_dir_operations; inode->i_mapping->a_ops = &f2fs_dblock_aops; - mapping_set_gfp_mask(inode->i_mapping, GFP_F2FS_HIGH_ZERO); + inode_nohighmem(inode); set_inode_flag(inode, FI_INC_LINK); f2fs_lock_op(sbi); @@ -893,13 +888,11 @@ static int f2fs_rename(struct inode *old_dir, struct dentry *old_dentry, } if (old_dir_entry) { - if (old_dir != new_dir && !whiteout) { + if (old_dir != new_dir && !whiteout) f2fs_set_link(old_inode, old_dir_entry, old_dir_page, new_dir); - } else { - f2fs_dentry_kunmap(old_inode, old_dir_page); + else f2fs_put_page(old_dir_page, 0); - } f2fs_i_links_write(old_dir, false); } add_ino_entry(sbi, new_dir->i_ino, TRANS_DIR_INO); @@ -912,20 +905,15 @@ static int f2fs_rename(struct inode *old_dir, struct dentry *old_dentry, put_out_dir: f2fs_unlock_op(sbi); - if (new_page) { - f2fs_dentry_kunmap(new_dir, new_page); + if (new_page) f2fs_put_page(new_page, 0); - } out_whiteout: if (whiteout) iput(whiteout); out_dir: - if (old_dir_entry) { - f2fs_dentry_kunmap(old_inode, old_dir_page); + if (old_dir_entry) f2fs_put_page(old_dir_page, 0); - } out_old: - f2fs_dentry_kunmap(old_dir, old_page); f2fs_put_page(old_page, 0); out: return err; @@ -1067,19 +1055,15 @@ static int f2fs_cross_rename(struct inode *old_dir, struct dentry *old_dentry, return 0; out_new_dir: if (new_dir_entry) { - f2fs_dentry_kunmap(new_inode, new_dir_page); f2fs_put_page(new_dir_page, 0); } out_old_dir: if (old_dir_entry) { - f2fs_dentry_kunmap(old_inode, old_dir_page); f2fs_put_page(old_dir_page, 0); } out_new: - f2fs_dentry_kunmap(new_dir, new_page); f2fs_put_page(new_page, 0); out_old: - f2fs_dentry_kunmap(old_dir, old_page); f2fs_put_page(old_page, 0); out: return err; diff --git a/fs/f2fs/recovery.c b/fs/f2fs/recovery.c index 337f3363f48f..c5e5c45130b5 100644 --- a/fs/f2fs/recovery.c +++ b/fs/f2fs/recovery.c @@ -144,7 +144,7 @@ static int recover_dentry(struct inode *inode, struct page *ipage, retry: de = __f2fs_find_entry(dir, &fname, &page); if (de && inode->i_ino == le32_to_cpu(de->ino)) - goto out_unmap_put; + goto out_put; if (de) { einode = f2fs_iget_retry(inode->i_sb, le32_to_cpu(de->ino)); @@ -153,19 +153,19 @@ retry: err = PTR_ERR(einode); if (err == -ENOENT) err = -EEXIST; - goto out_unmap_put; + goto out_put; } err = dquot_initialize(einode); if (err) { iput(einode); - goto out_unmap_put; + goto out_put; } err = acquire_orphan_inode(F2FS_I_SB(inode)); if (err) { iput(einode); - goto out_unmap_put; + goto out_put; } f2fs_delete_entry(de, page, dir, einode); iput(einode); @@ -180,8 +180,7 @@ retry: goto retry; goto out; -out_unmap_put: - f2fs_dentry_kunmap(dir, page); +out_put: f2fs_put_page(page, 0); out: if (file_enc_name(inode)) diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index 58aecb60ea51..393b880afc9a 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -46,7 +46,6 @@ /* This flag is used by node and meta inodes, and by recovery */ #define GFP_F2FS_ZERO (GFP_NOFS | __GFP_ZERO) -#define GFP_F2FS_HIGH_ZERO (GFP_NOFS | __GFP_ZERO | __GFP_HIGHMEM) /* * For further optimization on multi-head logs, on-disk layout supports maximum -- cgit v1.2.3 From 199bc3fef29cacf672e7e5cd49d296c1fdc1a891 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Thu, 25 Jan 2018 19:40:08 +0800 Subject: f2fs: support large nat bitmap Previously, we will store all nat version bitmap in checkpoint pack block, so our total node entry number has a limitation which caused total node number can not exceed (3900 * 8) block * 455 node/block = 14196000. So that once user wants to create more nodes in large size image, it becomes a bottleneck, that's unreasonable. This patch detects the new layout of nat/sit version bitmap in image in order to enable supporting large nat bitmap. Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim --- fs/f2fs/f2fs.h | 6 ++++++ include/linux/f2fs_fs.h | 1 + 2 files changed, 7 insertions(+) (limited to 'include/linux') diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 8b652e000326..3f4dafecd910 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -1762,6 +1762,12 @@ static inline void *__bitmap_ptr(struct f2fs_sb_info *sbi, int flag) struct f2fs_checkpoint *ckpt = F2FS_CKPT(sbi); int offset; + if (is_set_ckpt_flags(sbi, CP_LARGE_NAT_BITMAP_FLAG)) { + offset = (flag == SIT_BITMAP) ? + le32_to_cpu(ckpt->nat_ver_bitmap_bytesize) : 0; + return &ckpt->sit_nat_version_bitmap + offset; + } + if (__cp_payload(sbi) > 0) { if (flag == NAT_BITMAP) return &ckpt->sit_nat_version_bitmap; diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index 393b880afc9a..96c9bdbace50 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -116,6 +116,7 @@ struct f2fs_super_block { /* * For checkpoint */ +#define CP_LARGE_NAT_BITMAP_FLAG 0x00000400 #define CP_NOCRC_RECOVERY_FLAG 0x00000200 #define CP_TRIMMED_FLAG 0x00000100 #define CP_NAT_BITS_FLAG 0x00000080 -- cgit v1.2.3 From 846ae671ad368e344a2b141c0f19e1014b27a0dd Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Mon, 26 Feb 2018 22:04:13 +0800 Subject: f2fs: expose extension_list sysfs entry This patch adds a sysfs entry 'extension_list' to support query/add/del item in extension list. Query: cat /sys/fs/f2fs//extension_list Add: echo 'extension' > /sys/fs/f2fs//extension_list Del: echo '!extension' > /sys/fs/f2fs//extension_list Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim --- Documentation/ABI/testing/sysfs-fs-f2fs | 9 +++++++ fs/f2fs/f2fs.h | 4 +++- fs/f2fs/file.c | 4 ++-- fs/f2fs/namei.c | 42 ++++++++++++++++++++++++++++++--- fs/f2fs/super.c | 2 +- fs/f2fs/sysfs.c | 40 +++++++++++++++++++++++++++++++ include/linux/f2fs_fs.h | 3 ++- 7 files changed, 96 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/Documentation/ABI/testing/sysfs-fs-f2fs b/Documentation/ABI/testing/sysfs-fs-f2fs index d870b5514d15..7fa84e349ad9 100644 --- a/Documentation/ABI/testing/sysfs-fs-f2fs +++ b/Documentation/ABI/testing/sysfs-fs-f2fs @@ -192,3 +192,12 @@ Date: November 2017 Contact: "Sheng Yong" Description: Controls readahead inode block in readdir. + +What: /sys/fs/f2fs//extension_list +Date: Feburary 2018 +Contact: "Chao Yu" +Description: + Used to control configure extension list: + - Query: cat /sys/fs/f2fs//extension_list + - Add: echo 'extension' > /sys/fs/f2fs//extension_list + - Del: echo '!extension' > /sys/fs/f2fs//extension_list diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 6d0e7b185b39..3bb4e943454a 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -1047,7 +1047,7 @@ struct f2fs_sb_info { struct super_block *sb; /* pointer to VFS super block */ struct proc_dir_entry *s_proc; /* proc entry */ struct f2fs_super_block *raw_super; /* raw super block pointer */ - struct mutex sb_lock; /* lock for raw super block */ + struct rw_semaphore sb_lock; /* lock for raw super block */ int valid_super_block; /* valid super block no */ unsigned long s_flag; /* flags for sbi */ @@ -2605,6 +2605,8 @@ void handle_failed_inode(struct inode *inode); /* * namei.c */ +int update_extension_list(struct f2fs_sb_info *sbi, const char *name, + bool set); struct dentry *f2fs_get_parent(struct dentry *child); /* diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index db9dc9efafae..c0a80987e88e 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -1970,7 +1970,7 @@ static int f2fs_ioc_get_encryption_pwsalt(struct file *filp, unsigned long arg) if (err) return err; - mutex_lock(&sbi->sb_lock); + down_write(&sbi->sb_lock); if (uuid_is_nonzero(sbi->raw_super->encrypt_pw_salt)) goto got_it; @@ -1989,7 +1989,7 @@ got_it: 16)) err = -EFAULT; out_err: - mutex_unlock(&sbi->sb_lock); + up_write(&sbi->sb_lock); mnt_drop_write_file(filp); return err; } diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index 2ebf3d045dd2..2bd6e9f5746a 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -171,16 +171,52 @@ static int is_multimedia_file(const unsigned char *s, const char *sub) static inline void set_cold_files(struct f2fs_sb_info *sbi, struct inode *inode, const unsigned char *name) { - int i; - __u8 (*extlist)[8] = sbi->raw_super->extension_list; + __u8 (*extlist)[F2FS_EXTENSION_LEN] = sbi->raw_super->extension_list; + int i, count; + + down_read(&sbi->sb_lock); + + count = le32_to_cpu(sbi->raw_super->extension_count); - int count = le32_to_cpu(sbi->raw_super->extension_count); for (i = 0; i < count; i++) { if (is_multimedia_file(name, extlist[i])) { file_set_cold(inode); break; } } + + up_read(&sbi->sb_lock); +} + +int update_extension_list(struct f2fs_sb_info *sbi, const char *name, bool set) +{ + __u8 (*extlist)[F2FS_EXTENSION_LEN] = sbi->raw_super->extension_list; + int count = le32_to_cpu(sbi->raw_super->extension_count); + int i; + + for (i = 0; i < count; i++) { + if (strcmp(name, extlist[i])) + continue; + + if (set) + return -EINVAL; + + memcpy(extlist[i], extlist[i + 1], + F2FS_EXTENSION_LEN * (count - i - 1)); + memset(extlist[count - 1], 0, F2FS_EXTENSION_LEN); + sbi->raw_super->extension_count = cpu_to_le32(count - 1); + return 0; + } + + if (!set) + return -EINVAL; + + if (count == F2FS_MAX_EXTENSION) + return -EINVAL; + + strncpy(extlist[count], name, strlen(name)); + sbi->raw_super->extension_count = cpu_to_le32(count + 1); + return 0; } static int f2fs_create(struct inode *dir, struct dentry *dentry, umode_t mode, diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index d2833a232528..06da158d4263 100644 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -2222,7 +2222,7 @@ static void init_sb_info(struct f2fs_sb_info *sbi) sbi->dirty_device = 0; spin_lock_init(&sbi->dev_lock); - mutex_init(&sbi->sb_lock); + init_rwsem(&sbi->sb_lock); } static int init_percpu_info(struct f2fs_sb_info *sbi) diff --git a/fs/f2fs/sysfs.c b/fs/f2fs/sysfs.c index 374ee5c82f94..d27b28e602a6 100644 --- a/fs/f2fs/sysfs.c +++ b/fs/f2fs/sysfs.c @@ -136,6 +136,18 @@ static ssize_t f2fs_sbi_show(struct f2fs_attr *a, if (!ptr) return -EINVAL; + if (!strcmp(a->attr.name, "extension_list")) { + __u8 (*extlist)[F2FS_EXTENSION_LEN] = + sbi->raw_super->extension_list; + int count = le32_to_cpu(sbi->raw_super->extension_count); + int len = 0, i; + + for (i = 0; i < count; i++) + len += snprintf(buf + len, PAGE_SIZE - len, "%s\n", + extlist[i]); + return len; + } + ui = (unsigned int *)(ptr + a->offset); return snprintf(buf, PAGE_SIZE, "%u\n", *ui); @@ -154,6 +166,32 @@ static ssize_t f2fs_sbi_store(struct f2fs_attr *a, if (!ptr) return -EINVAL; + if (!strcmp(a->attr.name, "extension_list")) { + const char *name = strim((char *)buf); + bool set = true; + + if (name[0] == '!') { + name++; + set = false; + } + + if (strlen(name) >= F2FS_EXTENSION_LEN) + return -EINVAL; + + down_write(&sbi->sb_lock); + + ret = update_extension_list(sbi, name, set); + if (ret) + goto out; + + ret = f2fs_commit_super(sbi, false); + if (ret) + update_extension_list(sbi, name, !set); +out: + up_write(&sbi->sb_lock); + return ret ? ret : count; + } + ui = (unsigned int *)(ptr + a->offset); ret = kstrtoul(skip_spaces(buf), 0, &t); @@ -307,6 +345,7 @@ F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, idle_interval, interval_time[REQ_TIME]); F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, iostat_enable, iostat_enable); F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, readdir_ra, readdir_ra); F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, gc_pin_file_thresh, gc_pin_file_threshold); +F2FS_RW_ATTR(F2FS_SBI, f2fs_super_block, extension_list, extension_list); #ifdef CONFIG_F2FS_FAULT_INJECTION F2FS_RW_ATTR(FAULT_INFO_RATE, f2fs_fault_info, inject_rate, inject_rate); F2FS_RW_ATTR(FAULT_INFO_TYPE, f2fs_fault_info, inject_type, inject_type); @@ -357,6 +396,7 @@ static struct attribute *f2fs_attrs[] = { ATTR_LIST(iostat_enable), ATTR_LIST(readdir_ra), ATTR_LIST(gc_pin_file_thresh), + ATTR_LIST(extension_list), #ifdef CONFIG_F2FS_FAULT_INJECTION ATTR_LIST(inject_rate), ATTR_LIST(inject_type), diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index 96c9bdbace50..d8c241451712 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -21,6 +21,7 @@ #define F2FS_BLKSIZE 4096 /* support only 4KB block */ #define F2FS_BLKSIZE_BITS 12 /* bits for F2FS_BLKSIZE */ #define F2FS_MAX_EXTENSION 64 /* # of extension entries */ +#define F2FS_EXTENSION_LEN 8 /* max size of extension */ #define F2FS_BLK_ALIGN(x) (((x) + F2FS_BLKSIZE - 1) >> F2FS_BLKSIZE_BITS) #define NULL_ADDR ((block_t)0) /* used as block_t addresses */ @@ -101,7 +102,7 @@ struct f2fs_super_block { __u8 uuid[16]; /* 128-bit uuid for volume */ __le16 volume_name[MAX_VOLUME_NAME]; /* volume name */ __le32 extension_count; /* # of extensions below */ - __u8 extension_list[F2FS_MAX_EXTENSION][8]; /* extension array */ + __u8 extension_list[F2FS_MAX_EXTENSION][F2FS_EXTENSION_LEN];/* extension array */ __le32 cp_payload; __u8 version[VERSION_LEN]; /* the kernel version */ __u8 init_version[VERSION_LEN]; /* the initial kernel version */ -- cgit v1.2.3 From b6a06cbbb5f7fd03589cff9178314af04c568826 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Wed, 28 Feb 2018 17:07:27 +0800 Subject: f2fs: support hot file extension This patch supports to recognize hot file extension in f2fs, so that we can allocate proper hot segment location for its data, which can lead to better hot/cold seperation in filesystem. In addition, we changes a bit on query/add/del operation method for extension_list sysfs entry as below: - Query: cat /sys/fs/f2fs//extension_list - Add: echo 'extension' > /sys/fs/f2fs//extension_list - Del: echo '!extension' > /sys/fs/f2fs//extension_list - Add: echo '[h/c]extension' > /sys/fs/f2fs//extension_list - Del: echo '[h/c]!extension' > /sys/fs/f2fs//extension_list - [h] means add/del hot file extension - [c] means add/del cold file extension Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim --- Documentation/ABI/testing/sysfs-fs-f2fs | 6 ++- fs/f2fs/f2fs.h | 6 ++- fs/f2fs/namei.c | 79 ++++++++++++++++++++++++--------- fs/f2fs/segment.c | 3 +- fs/f2fs/sysfs.c | 30 ++++++++++--- include/linux/f2fs_fs.h | 3 +- 6 files changed, 96 insertions(+), 31 deletions(-) (limited to 'include/linux') diff --git a/Documentation/ABI/testing/sysfs-fs-f2fs b/Documentation/ABI/testing/sysfs-fs-f2fs index 7fa84e349ad9..540553c933b6 100644 --- a/Documentation/ABI/testing/sysfs-fs-f2fs +++ b/Documentation/ABI/testing/sysfs-fs-f2fs @@ -199,5 +199,7 @@ Contact: "Chao Yu" Description: Used to control configure extension list: - Query: cat /sys/fs/f2fs//extension_list - - Add: echo 'extension' > /sys/fs/f2fs//extension_list - - Del: echo '!extension' > /sys/fs/f2fs//extension_list + - Add: echo '[h/c]extension' > /sys/fs/f2fs//extension_list + - Del: echo '[h/c]!extension' > /sys/fs/f2fs//extension_list + - [h] means add/del hot file extension + - [c] means add/del cold file extension diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 833c9bc06d03..f6dc70666ebb 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -576,6 +576,7 @@ enum { #define FADVISE_ENCRYPT_BIT 0x04 #define FADVISE_ENC_NAME_BIT 0x08 #define FADVISE_KEEP_SIZE_BIT 0x10 +#define FADVISE_HOT_BIT 0x20 #define file_is_cold(inode) is_file(inode, FADVISE_COLD_BIT) #define file_wrong_pino(inode) is_file(inode, FADVISE_LOST_PINO_BIT) @@ -590,6 +591,9 @@ enum { #define file_set_enc_name(inode) set_file(inode, FADVISE_ENC_NAME_BIT) #define file_keep_isize(inode) is_file(inode, FADVISE_KEEP_SIZE_BIT) #define file_set_keep_isize(inode) set_file(inode, FADVISE_KEEP_SIZE_BIT) +#define file_is_hot(inode) is_file(inode, FADVISE_HOT_BIT) +#define file_set_hot(inode) set_file(inode, FADVISE_HOT_BIT) +#define file_clear_hot(inode) clear_file(inode, FADVISE_HOT_BIT) #define DEF_DIR_LEVEL 0 @@ -2614,7 +2618,7 @@ void handle_failed_inode(struct inode *inode); * namei.c */ int update_extension_list(struct f2fs_sb_info *sbi, const char *name, - bool set); + bool hot, bool set); struct dentry *f2fs_get_parent(struct dentry *child); /* diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index 2bd6e9f5746a..78ea0156f027 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -142,7 +142,7 @@ fail_drop: return ERR_PTR(err); } -static int is_multimedia_file(const unsigned char *s, const char *sub) +static int is_extension_exist(const unsigned char *s, const char *sub) { size_t slen = strlen(s); size_t sublen = strlen(sub); @@ -168,33 +168,59 @@ static int is_multimedia_file(const unsigned char *s, const char *sub) /* * Set multimedia files as cold files for hot/cold data separation */ -static inline void set_cold_files(struct f2fs_sb_info *sbi, struct inode *inode, +static inline void set_file_temperature(struct f2fs_sb_info *sbi, struct inode *inode, const unsigned char *name) { __u8 (*extlist)[F2FS_EXTENSION_LEN] = sbi->raw_super->extension_list; - int i, count; + int i, cold_count, hot_count; down_read(&sbi->sb_lock); - count = le32_to_cpu(sbi->raw_super->extension_count); + cold_count = le32_to_cpu(sbi->raw_super->extension_count); + hot_count = sbi->raw_super->hot_ext_count; - for (i = 0; i < count; i++) { - if (is_multimedia_file(name, extlist[i])) { + for (i = 0; i < cold_count + hot_count; i++) { + if (!is_extension_exist(name, extlist[i])) + continue; + if (i < cold_count) file_set_cold(inode); - break; - } + else + file_set_hot(inode); + break; } up_read(&sbi->sb_lock); } -int update_extension_list(struct f2fs_sb_info *sbi, const char *name, bool set) +int update_extension_list(struct f2fs_sb_info *sbi, const char *name, + bool hot, bool set) { __u8 (*extlist)[F2FS_EXTENSION_LEN] = sbi->raw_super->extension_list; - int count = le32_to_cpu(sbi->raw_super->extension_count); + int cold_count = le32_to_cpu(sbi->raw_super->extension_count); + int hot_count = sbi->raw_super->hot_ext_count; + int total_count = cold_count + hot_count; + int start, count; int i; - for (i = 0; i < count; i++) { + if (set) { + if (total_count == F2FS_MAX_EXTENSION) + return -EINVAL; + } else { + if (!hot && !cold_count) + return -EINVAL; + if (hot && !hot_count) + return -EINVAL; + } + + if (hot) { + start = cold_count; + count = total_count; + } else { + start = 0; + count = cold_count; + } + + for (i = start; i < count; i++) { if (strcmp(name, extlist[i])) continue; @@ -202,20 +228,33 @@ int update_extension_list(struct f2fs_sb_info *sbi, const char *name, bool set) return -EINVAL; memcpy(extlist[i], extlist[i + 1], - F2FS_EXTENSION_LEN * (count - i - 1)); - memset(extlist[count - 1], 0, F2FS_EXTENSION_LEN); - sbi->raw_super->extension_count = cpu_to_le32(count - 1); + F2FS_EXTENSION_LEN * (total_count - i - 1)); + memset(extlist[total_count - 1], 0, F2FS_EXTENSION_LEN); + if (hot) + sbi->raw_super->hot_ext_count = hot_count - 1; + else + sbi->raw_super->extension_count = + cpu_to_le32(cold_count - 1); return 0; } if (!set) return -EINVAL; - if (count == F2FS_MAX_EXTENSION) - return -EINVAL; - - strncpy(extlist[count], name, strlen(name)); - sbi->raw_super->extension_count = cpu_to_le32(count + 1); + if (hot) { + strncpy(extlist[count], name, strlen(name)); + sbi->raw_super->hot_ext_count = hot_count + 1; + } else { + char buf[F2FS_MAX_EXTENSION][F2FS_EXTENSION_LEN]; + + memcpy(buf, &extlist[cold_count], + F2FS_EXTENSION_LEN * hot_count); + memset(extlist[cold_count], 0, F2FS_EXTENSION_LEN); + strncpy(extlist[cold_count], name, strlen(name)); + memcpy(&extlist[cold_count + 1], buf, + F2FS_EXTENSION_LEN * hot_count); + sbi->raw_super->extension_count = cpu_to_le32(cold_count + 1); + } return 0; } @@ -239,7 +278,7 @@ static int f2fs_create(struct inode *dir, struct dentry *dentry, umode_t mode, return PTR_ERR(inode); if (!test_opt(sbi, DISABLE_EXT_IDENTIFY)) - set_cold_files(sbi, inode, dentry->d_name.name); + set_file_temperature(sbi, inode, dentry->d_name.name); inode->i_op = &f2fs_file_inode_operations; inode->i_fop = &f2fs_file_operations; diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index 1e3dd3de4ecc..f61c77bd673c 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -2587,7 +2587,8 @@ static int __get_segment_type_6(struct f2fs_io_info *fio) if (is_cold_data(fio->page) || file_is_cold(inode)) return CURSEG_COLD_DATA; - if (is_inode_flag_set(inode, FI_HOT_DATA)) + if (file_is_hot(inode) || + is_inode_flag_set(inode, FI_HOT_DATA)) return CURSEG_HOT_DATA; return rw_hint_to_seg_type(inode->i_write_hint); } else { diff --git a/fs/f2fs/sysfs.c b/fs/f2fs/sysfs.c index d27b28e602a6..23a2d8d66c43 100644 --- a/fs/f2fs/sysfs.c +++ b/fs/f2fs/sysfs.c @@ -139,10 +139,19 @@ static ssize_t f2fs_sbi_show(struct f2fs_attr *a, if (!strcmp(a->attr.name, "extension_list")) { __u8 (*extlist)[F2FS_EXTENSION_LEN] = sbi->raw_super->extension_list; - int count = le32_to_cpu(sbi->raw_super->extension_count); + int cold_count = le32_to_cpu(sbi->raw_super->extension_count); + int hot_count = sbi->raw_super->hot_ext_count; int len = 0, i; - for (i = 0; i < count; i++) + len += snprintf(buf + len, PAGE_SIZE - len, + "cold file extenstion:\n"); + for (i = 0; i < cold_count; i++) + len += snprintf(buf + len, PAGE_SIZE - len, "%s\n", + extlist[i]); + + len += snprintf(buf + len, PAGE_SIZE - len, + "hot file extenstion:\n"); + for (i = cold_count; i < cold_count + hot_count; i++) len += snprintf(buf + len, PAGE_SIZE - len, "%s\n", extlist[i]); return len; @@ -168,9 +177,18 @@ static ssize_t f2fs_sbi_store(struct f2fs_attr *a, if (!strcmp(a->attr.name, "extension_list")) { const char *name = strim((char *)buf); - bool set = true; + bool set = true, hot; + + if (!strncmp(name, "[h]", 3)) + hot = true; + else if (!strncmp(name, "[c]", 3)) + hot = false; + else + return -EINVAL; + + name += 3; - if (name[0] == '!') { + if (*name == '!') { name++; set = false; } @@ -180,13 +198,13 @@ static ssize_t f2fs_sbi_store(struct f2fs_attr *a, down_write(&sbi->sb_lock); - ret = update_extension_list(sbi, name, set); + ret = update_extension_list(sbi, name, hot, set); if (ret) goto out; ret = f2fs_commit_super(sbi, false); if (ret) - update_extension_list(sbi, name, !set); + update_extension_list(sbi, name, hot, !set); out: up_write(&sbi->sb_lock); return ret ? ret : count; diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index d8c241451712..b06ab1f04ff6 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -111,7 +111,8 @@ struct f2fs_super_block { __u8 encrypt_pw_salt[16]; /* Salt used for string2key algorithm */ struct f2fs_device devs[MAX_DEVICES]; /* device list */ __le32 qf_ino[F2FS_MAX_QUOTAS]; /* quota inode numbers */ - __u8 reserved[315]; /* valid reserved region */ + __u8 hot_ext_count; /* # of hot file extension */ + __u8 reserved[314]; /* valid reserved region */ } __packed; /* -- cgit v1.2.3 From 72199320d49dbafa1a99f94f1cd60dc90035c154 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 1 Mar 2018 17:33:32 +0100 Subject: timekeeping: Add the new CLOCK_MONOTONIC_ACTIVE clock The planned change to unify the behaviour of the MONOTONIC and BOOTTIME clocks vs. suspend removes the ability to retrieve the active non-suspended time of a system. Provide a new CLOCK_MONOTONIC_ACTIVE clock which returns the active non-suspended time of the system via clock_gettime(). This preserves the old behaviour of CLOCK_MONOTONIC before the BOOTTIME/MONOTONIC unification. This new clock also allows applications to detect programmatically that the MONOTONIC and BOOTTIME clocks are identical. Signed-off-by: Thomas Gleixner Cc: Dmitry Torokhov Cc: John Stultz Cc: Jonathan Corbet Cc: Kevin Easton Cc: Linus Torvalds Cc: Mark Salyzyn Cc: Michael Kerrisk Cc: Peter Zijlstra Cc: Petr Mladek Cc: Prarit Bhargava Cc: Sergey Senozhatsky Cc: Steven Rostedt Link: http://lkml.kernel.org/r/20180301165149.965235774@linutronix.de Signed-off-by: Ingo Molnar --- include/linux/timekeeper_internal.h | 2 ++ include/linux/timekeeping.h | 1 + include/uapi/linux/time.h | 1 + kernel/time/posix-stubs.c | 2 ++ kernel/time/posix-timers.c | 13 +++++++++++++ kernel/time/timekeeping.c | 36 ++++++++++++++++++++++++++++++++++++ 6 files changed, 55 insertions(+) (limited to 'include/linux') diff --git a/include/linux/timekeeper_internal.h b/include/linux/timekeeper_internal.h index 7acb953298a7..4b3dca173e89 100644 --- a/include/linux/timekeeper_internal.h +++ b/include/linux/timekeeper_internal.h @@ -52,6 +52,7 @@ struct tk_read_base { * @offs_real: Offset clock monotonic -> clock realtime * @offs_boot: Offset clock monotonic -> clock boottime * @offs_tai: Offset clock monotonic -> clock tai + * @time_suspended: Accumulated suspend time * @tai_offset: The current UTC to TAI offset in seconds * @clock_was_set_seq: The sequence number of clock was set events * @cs_was_changed_seq: The sequence number of clocksource change events @@ -94,6 +95,7 @@ struct timekeeper { ktime_t offs_real; ktime_t offs_boot; ktime_t offs_tai; + ktime_t time_suspended; s32 tai_offset; unsigned int clock_was_set_seq; u8 cs_was_changed_seq; diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index b17bcce58bc4..440b1935d3a5 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -32,6 +32,7 @@ extern void getrawmonotonic64(struct timespec64 *ts); extern void ktime_get_ts64(struct timespec64 *ts); extern time64_t ktime_get_seconds(void); extern time64_t ktime_get_real_seconds(void); +extern void ktime_get_active_ts64(struct timespec64 *ts); extern int __getnstimeofday64(struct timespec64 *tv); extern void getnstimeofday64(struct timespec64 *tv); diff --git a/include/uapi/linux/time.h b/include/uapi/linux/time.h index 53f8dd84beb5..61a187df8da2 100644 --- a/include/uapi/linux/time.h +++ b/include/uapi/linux/time.h @@ -61,6 +61,7 @@ struct itimerval { */ #define CLOCK_SGI_CYCLE 10 #define CLOCK_TAI 11 +#define CLOCK_MONOTONIC_ACTIVE 12 #define MAX_CLOCKS 16 #define CLOCKS_MASK (CLOCK_REALTIME | CLOCK_MONOTONIC) diff --git a/kernel/time/posix-stubs.c b/kernel/time/posix-stubs.c index b258bee13b02..6259dbc0191a 100644 --- a/kernel/time/posix-stubs.c +++ b/kernel/time/posix-stubs.c @@ -73,6 +73,8 @@ int do_clock_gettime(clockid_t which_clock, struct timespec64 *tp) case CLOCK_BOOTTIME: get_monotonic_boottime64(tp); break; + case CLOCK_MONOTONIC_ACTIVE: + ktime_get_active_ts64(tp); default: return -EINVAL; } diff --git a/kernel/time/posix-timers.c b/kernel/time/posix-timers.c index 75043046914e..556fe02a47a4 100644 --- a/kernel/time/posix-timers.c +++ b/kernel/time/posix-timers.c @@ -263,6 +263,13 @@ static int posix_get_tai(clockid_t which_clock, struct timespec64 *tp) return 0; } +static int posix_get_monotonic_active(clockid_t which_clock, + struct timespec64 *tp) +{ + ktime_get_active_ts64(tp); + return 0; +} + static int posix_get_hrtimer_res(clockid_t which_clock, struct timespec64 *tp) { tp->tv_sec = 0; @@ -1330,6 +1337,11 @@ static const struct k_clock clock_boottime = { .timer_arm = common_hrtimer_arm, }; +static const struct k_clock clock_monotonic_active = { + .clock_getres = posix_get_hrtimer_res, + .clock_get = posix_get_monotonic_active, +}; + static const struct k_clock * const posix_clocks[] = { [CLOCK_REALTIME] = &clock_realtime, [CLOCK_MONOTONIC] = &clock_monotonic, @@ -1342,6 +1354,7 @@ static const struct k_clock * const posix_clocks[] = { [CLOCK_REALTIME_ALARM] = &alarm_clock, [CLOCK_BOOTTIME_ALARM] = &alarm_clock, [CLOCK_TAI] = &clock_tai, + [CLOCK_MONOTONIC_ACTIVE] = &clock_monotonic_active, }; static const struct k_clock *clockid_to_kclock(const clockid_t id) diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index e11760121cb2..a2b7f583e64e 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -139,6 +139,9 @@ static void tk_set_wall_to_mono(struct timekeeper *tk, struct timespec64 wtm) static inline void tk_update_sleep_time(struct timekeeper *tk, ktime_t delta) { tk->offs_boot = ktime_add(tk->offs_boot, delta); + + /* Accumulate time spent in suspend */ + tk->time_suspended += delta; } /* @@ -886,6 +889,39 @@ void ktime_get_ts64(struct timespec64 *ts) } EXPORT_SYMBOL_GPL(ktime_get_ts64); +/** + * ktime_get_active_ts64 - Get the active non-suspended monotonic clock + * @ts: pointer to timespec variable + * + * The function calculates the monotonic clock from the realtime clock and + * the wall_to_monotonic offset, subtracts the accumulated suspend time and + * stores the result in normalized timespec64 format in the variable + * pointed to by @ts. + */ +void ktime_get_active_ts64(struct timespec64 *ts) +{ + struct timekeeper *tk = &tk_core.timekeeper; + struct timespec64 tomono, tsusp; + u64 nsec, nssusp; + unsigned int seq; + + WARN_ON(timekeeping_suspended); + + do { + seq = read_seqcount_begin(&tk_core.seq); + ts->tv_sec = tk->xtime_sec; + nsec = timekeeping_get_ns(&tk->tkr_mono); + tomono = tk->wall_to_monotonic; + nssusp = tk->time_suspended; + } while (read_seqcount_retry(&tk_core.seq, seq)); + + ts->tv_sec += tomono.tv_sec; + ts->tv_nsec = 0; + timespec64_add_ns(ts, nsec + tomono.tv_nsec); + tsusp = ns_to_timespec64(nssusp); + *ts = timespec64_sub(*ts, tsusp); +} + /** * ktime_get_seconds - Get the seconds portion of CLOCK_MONOTONIC * -- cgit v1.2.3 From d6c7270e913db75ca5fdc79915ba780e97ae2857 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 1 Mar 2018 17:33:35 +0100 Subject: timekeeping: Remove boot time specific code Now that the MONOTONIC and BOOTTIME clocks are the same, remove all the special handling from timekeeping. Keep wrappers for the existing users of the *boot* timekeeper interfaces. Signed-off-by: Thomas Gleixner Cc: Dmitry Torokhov Cc: John Stultz Cc: Jonathan Corbet Cc: Kevin Easton Cc: Linus Torvalds Cc: Mark Salyzyn Cc: Michael Kerrisk Cc: Peter Zijlstra Cc: Petr Mladek Cc: Prarit Bhargava Cc: Sergey Senozhatsky Cc: Steven Rostedt Link: http://lkml.kernel.org/r/20180301165150.236279497@linutronix.de Signed-off-by: Ingo Molnar --- include/linux/timekeeping.h | 42 +++++++++++++++++------------------------- kernel/time/timekeeping.c | 31 ------------------------------- 2 files changed, 17 insertions(+), 56 deletions(-) (limited to 'include/linux') diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index 440b1935d3a5..abb396731332 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -38,15 +38,19 @@ extern int __getnstimeofday64(struct timespec64 *tv); extern void getnstimeofday64(struct timespec64 *tv); extern void getboottime64(struct timespec64 *ts); -#define ktime_get_real_ts64(ts) getnstimeofday64(ts) +#define ktime_get_real_ts64(ts) getnstimeofday64(ts) + +/* Clock BOOTTIME compatibility wrappers */ +static inline void get_monotonic_boottime64(struct timespec64 *ts) +{ + ktime_get_ts64(ts); +} /* * ktime_t based interfaces */ - enum tk_offsets { TK_OFFS_REAL, - TK_OFFS_BOOT, TK_OFFS_TAI, TK_OFFS_MAX, }; @@ -57,6 +61,10 @@ extern ktime_t ktime_mono_to_any(ktime_t tmono, enum tk_offsets offs); extern ktime_t ktime_get_raw(void); extern u32 ktime_get_resolution_ns(void); +/* Clock BOOTTIME compatibility wrappers */ +static inline ktime_t ktime_get_boottime(void) { return ktime_get(); } +static inline u64 ktime_get_boot_ns(void) { return ktime_get(); } + /** * ktime_get_real - get the real (wall-) time in ktime_t format */ @@ -65,17 +73,6 @@ static inline ktime_t ktime_get_real(void) return ktime_get_with_offset(TK_OFFS_REAL); } -/** - * ktime_get_boottime - Returns monotonic time since boot in ktime_t format - * - * This is similar to CLOCK_MONTONIC/ktime_get, but also includes the - * time spent in suspend. - */ -static inline ktime_t ktime_get_boottime(void) -{ - return ktime_get_with_offset(TK_OFFS_BOOT); -} - /** * ktime_get_clocktai - Returns the TAI time of day in ktime_t format */ @@ -102,11 +99,6 @@ static inline u64 ktime_get_real_ns(void) return ktime_to_ns(ktime_get_real()); } -static inline u64 ktime_get_boot_ns(void) -{ - return ktime_to_ns(ktime_get_boottime()); -} - static inline u64 ktime_get_tai_ns(void) { return ktime_to_ns(ktime_get_clocktai()); @@ -119,17 +111,17 @@ static inline u64 ktime_get_raw_ns(void) extern u64 ktime_get_mono_fast_ns(void); extern u64 ktime_get_raw_fast_ns(void); -extern u64 ktime_get_boot_fast_ns(void); extern u64 ktime_get_real_fast_ns(void); -/* - * timespec64 interfaces utilizing the ktime based ones - */ -static inline void get_monotonic_boottime64(struct timespec64 *ts) +/* Clock BOOTTIME compatibility wrappers */ +static inline u64 ktime_get_boot_fast_ns(void) { - *ts = ktime_to_timespec64(ktime_get_boottime()); + return ktime_get_mono_fast_ns(); } +/* + * timespec64 interfaces utilizing the ktime based ones + */ static inline void timekeeping_clocktai64(struct timespec64 *ts) { *ts = ktime_to_timespec64(ktime_get_clocktai()); diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index b509fe7acd64..8355c8803282 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -473,36 +473,6 @@ u64 ktime_get_raw_fast_ns(void) } EXPORT_SYMBOL_GPL(ktime_get_raw_fast_ns); -/** - * ktime_get_boot_fast_ns - NMI safe and fast access to boot clock. - * - * To keep it NMI safe since we're accessing from tracing, we're not using a - * separate timekeeper with updates to monotonic clock and boot offset - * protected with seqlocks. This has the following minor side effects: - * - * (1) Its possible that a timestamp be taken after the boot offset is updated - * but before the timekeeper is updated. If this happens, the new boot offset - * is added to the old timekeeping making the clock appear to update slightly - * earlier: - * CPU 0 CPU 1 - * timekeeping_inject_sleeptime64() - * __timekeeping_inject_sleeptime(tk, delta); - * timestamp(); - * timekeeping_update(tk, TK_CLEAR_NTP...); - * - * (2) On 32-bit systems, the 64-bit boot offset (tk->offs_boot) may be - * partially updated. Since the tk->offs_boot update is a rare event, this - * should be a rare occurrence which postprocessing should be able to handle. - */ -u64 notrace ktime_get_boot_fast_ns(void) -{ - struct timekeeper *tk = &tk_core.timekeeper; - - return (ktime_get_mono_fast_ns() + ktime_to_ns(tk->offs_boot)); -} -EXPORT_SYMBOL_GPL(ktime_get_boot_fast_ns); - - /* * See comment for __ktime_get_fast_ns() vs. timestamp ordering */ @@ -794,7 +764,6 @@ EXPORT_SYMBOL_GPL(ktime_get_resolution_ns); static ktime_t *offsets[TK_OFFS_MAX] = { [TK_OFFS_REAL] = &tk_core.timekeeper.offs_real, - [TK_OFFS_BOOT] = &tk_core.timekeeper.offs_boot, [TK_OFFS_TAI] = &tk_core.timekeeper.offs_tai, }; -- cgit v1.2.3 From 127bfa5f4342e63d83a0b07ece376c2e8878e4a5 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 1 Mar 2018 17:33:37 +0100 Subject: hrtimer: Unify MONOTONIC and BOOTTIME clock behavior Now that th MONOTONIC and BOOTTIME clocks are indentical remove all the special casing. The user space visible interfaces still support both clocks, but their behavior is identical. Signed-off-by: Thomas Gleixner Cc: Dmitry Torokhov Cc: John Stultz Cc: Jonathan Corbet Cc: Kevin Easton Cc: Linus Torvalds Cc: Mark Salyzyn Cc: Michael Kerrisk Cc: Peter Zijlstra Cc: Petr Mladek Cc: Prarit Bhargava Cc: Sergey Senozhatsky Cc: Steven Rostedt Link: http://lkml.kernel.org/r/20180301165150.410218515@linutronix.de Signed-off-by: Ingo Molnar --- include/linux/hrtimer.h | 2 -- kernel/time/hrtimer.c | 16 ++-------------- kernel/time/timekeeping.c | 4 +--- kernel/time/timekeeping.h | 1 - 4 files changed, 3 insertions(+), 20 deletions(-) (limited to 'include/linux') diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h index c7902ca7c9f4..78f456fcd242 100644 --- a/include/linux/hrtimer.h +++ b/include/linux/hrtimer.h @@ -161,11 +161,9 @@ struct hrtimer_clock_base { enum hrtimer_base_type { HRTIMER_BASE_MONOTONIC, HRTIMER_BASE_REALTIME, - HRTIMER_BASE_BOOTTIME, HRTIMER_BASE_TAI, HRTIMER_BASE_MONOTONIC_SOFT, HRTIMER_BASE_REALTIME_SOFT, - HRTIMER_BASE_BOOTTIME_SOFT, HRTIMER_BASE_TAI_SOFT, HRTIMER_MAX_CLOCK_BASES, }; diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c index 23788100e214..9b082ce86325 100644 --- a/kernel/time/hrtimer.c +++ b/kernel/time/hrtimer.c @@ -90,11 +90,6 @@ DEFINE_PER_CPU(struct hrtimer_cpu_base, hrtimer_bases) = .clockid = CLOCK_REALTIME, .get_time = &ktime_get_real, }, - { - .index = HRTIMER_BASE_BOOTTIME, - .clockid = CLOCK_BOOTTIME, - .get_time = &ktime_get_boottime, - }, { .index = HRTIMER_BASE_TAI, .clockid = CLOCK_TAI, @@ -110,11 +105,6 @@ DEFINE_PER_CPU(struct hrtimer_cpu_base, hrtimer_bases) = .clockid = CLOCK_REALTIME, .get_time = &ktime_get_real, }, - { - .index = HRTIMER_BASE_BOOTTIME_SOFT, - .clockid = CLOCK_BOOTTIME, - .get_time = &ktime_get_boottime, - }, { .index = HRTIMER_BASE_TAI_SOFT, .clockid = CLOCK_TAI, @@ -129,7 +119,7 @@ static const int hrtimer_clock_to_base_table[MAX_CLOCKS] = { [CLOCK_REALTIME] = HRTIMER_BASE_REALTIME, [CLOCK_MONOTONIC] = HRTIMER_BASE_MONOTONIC, - [CLOCK_BOOTTIME] = HRTIMER_BASE_BOOTTIME, + [CLOCK_BOOTTIME] = HRTIMER_BASE_MONOTONIC, [CLOCK_TAI] = HRTIMER_BASE_TAI, }; @@ -565,14 +555,12 @@ __hrtimer_get_next_event(struct hrtimer_cpu_base *cpu_base, unsigned int active_ static inline ktime_t hrtimer_update_base(struct hrtimer_cpu_base *base) { ktime_t *offs_real = &base->clock_base[HRTIMER_BASE_REALTIME].offset; - ktime_t *offs_boot = &base->clock_base[HRTIMER_BASE_BOOTTIME].offset; ktime_t *offs_tai = &base->clock_base[HRTIMER_BASE_TAI].offset; ktime_t now = ktime_get_update_offsets_now(&base->clock_was_set_seq, - offs_real, offs_boot, offs_tai); + offs_real, offs_tai); base->clock_base[HRTIMER_BASE_REALTIME_SOFT].offset = *offs_real; - base->clock_base[HRTIMER_BASE_BOOTTIME_SOFT].offset = *offs_boot; base->clock_base[HRTIMER_BASE_TAI_SOFT].offset = *offs_tai; return now; diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index 8355c8803282..ca90219a1e73 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -2195,7 +2195,6 @@ void do_timer(unsigned long ticks) * ktime_get_update_offsets_now - hrtimer helper * @cwsseq: pointer to check and store the clock was set sequence number * @offs_real: pointer to storage for monotonic -> realtime offset - * @offs_boot: pointer to storage for monotonic -> boottime offset * @offs_tai: pointer to storage for monotonic -> clock tai offset * * Returns current monotonic time and updates the offsets if the @@ -2205,7 +2204,7 @@ void do_timer(unsigned long ticks) * Called from hrtimer_interrupt() or retrigger_next_event() */ ktime_t ktime_get_update_offsets_now(unsigned int *cwsseq, ktime_t *offs_real, - ktime_t *offs_boot, ktime_t *offs_tai) + ktime_t *offs_tai) { struct timekeeper *tk = &tk_core.timekeeper; unsigned int seq; @@ -2222,7 +2221,6 @@ ktime_t ktime_get_update_offsets_now(unsigned int *cwsseq, ktime_t *offs_real, if (*cwsseq != tk->clock_was_set_seq) { *cwsseq = tk->clock_was_set_seq; *offs_real = tk->offs_real; - *offs_boot = tk->offs_boot; *offs_tai = tk->offs_tai; } diff --git a/kernel/time/timekeeping.h b/kernel/time/timekeeping.h index 7a9b4eb7a1d5..79b67f5e0343 100644 --- a/kernel/time/timekeeping.h +++ b/kernel/time/timekeeping.h @@ -6,7 +6,6 @@ */ extern ktime_t ktime_get_update_offsets_now(unsigned int *cwsseq, ktime_t *offs_real, - ktime_t *offs_boot, ktime_t *offs_tai); extern int timekeeping_valid_for_hres(void); -- cgit v1.2.3 From 92af4dcb4e1c5f58dc337bc97bdffd4e853dbc93 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 1 Mar 2018 17:33:38 +0100 Subject: tracing: Unify the "boot" and "mono" tracing clocks Unify the "boot" and "mono" tracing clocks and document the new behaviour. Signed-off-by: Thomas Gleixner Cc: Dmitry Torokhov Cc: John Stultz Cc: Jonathan Corbet Cc: Kevin Easton Cc: Linus Torvalds Cc: Mark Salyzyn Cc: Michael Kerrisk Cc: Peter Zijlstra Cc: Petr Mladek Cc: Prarit Bhargava Cc: Sergey Senozhatsky Cc: Steven Rostedt Link: http://lkml.kernel.org/r/20180301165150.489635255@linutronix.de Signed-off-by: Ingo Molnar --- Documentation/trace/ftrace.txt | 14 +++----------- include/linux/timekeeping.h | 6 ------ kernel/trace/trace.c | 2 +- 3 files changed, 4 insertions(+), 18 deletions(-) (limited to 'include/linux') diff --git a/Documentation/trace/ftrace.txt b/Documentation/trace/ftrace.txt index d4601df6e72e..bf89f98bfdb9 100644 --- a/Documentation/trace/ftrace.txt +++ b/Documentation/trace/ftrace.txt @@ -449,17 +449,9 @@ of ftrace. Here is a list of some of the key files: which is montonic but is not subject to any rate adjustments and ticks at the same rate as the hardware clocksource. - boot: This is the boot clock (CLOCK_BOOTTIME) and is based on the - fast monotonic clock, but also accounts for time spent in - suspend. Since the clock access is designed for use in - tracing in the suspend path, some side effects are possible - if clock is accessed after the suspend time is accounted before - the fast mono clock is updated. In this case, the clock update - appears to happen slightly sooner than it normally would have. - Also on 32-bit systems, it's possible that the 64-bit boot offset - sees a partial update. These effects are rare and post - processing should be able to handle them. See comments in the - ktime_get_boot_fast_ns() function for more information. + boot: Same as mono. Used to be a separate clock which accounted + for the time spent in suspend while CLOCK_MONOTONIC did + not. To set a clock, simply echo the clock name into this file. diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index abb396731332..82c219dfd3bb 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -113,12 +113,6 @@ extern u64 ktime_get_mono_fast_ns(void); extern u64 ktime_get_raw_fast_ns(void); extern u64 ktime_get_real_fast_ns(void); -/* Clock BOOTTIME compatibility wrappers */ -static inline u64 ktime_get_boot_fast_ns(void) -{ - return ktime_get_mono_fast_ns(); -} - /* * timespec64 interfaces utilizing the ktime based ones */ diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 20a2300ae4e8..300f4ea39646 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -1164,7 +1164,7 @@ static struct { { trace_clock, "perf", 1 }, { ktime_get_mono_fast_ns, "mono", 1 }, { ktime_get_raw_fast_ns, "mono_raw", 1 }, - { ktime_get_boot_fast_ns, "boot", 1 }, + { ktime_get_mono_fast_ns, "boot", 1 }, ARCH_TRACE_CLOCKS }; -- cgit v1.2.3 From 32ff77e8cc9e66cc4fb38098f64fd54cc8f54573 Mon Sep 17 00:00:00 2001 From: Milind Chabbi Date: Mon, 12 Mar 2018 14:45:47 +0100 Subject: perf/core: Implement fast breakpoint modification via _IOC_MODIFY_ATTRIBUTES Problem and motivation: Once a breakpoint perf event (PERF_TYPE_BREAKPOINT) is created, there is no flexibility to change the breakpoint type (bp_type), breakpoint address (bp_addr), or breakpoint length (bp_len). The only option is to close the perf event and configure a new breakpoint event. This inflexibility has a significant performance overhead. For example, sampling-based, lightweight performance profilers (and also concurrency bug detection tools), monitor different addresses for a short duration using PERF_TYPE_BREAKPOINT and change the address (bp_addr) to another address or change the kind of breakpoint (bp_type) from "write" to a "read" or vice-versa or change the length (bp_len) of the address being monitored. The cost of these modifications is prohibitive since it involves unmapping the circular buffer associated with the perf event, closing the perf event, opening another perf event and mmaping another circular buffer. Solution: The new ioctl flag for perf events, PERF_EVENT_IOC_MODIFY_ATTRIBUTES, introduced in this patch takes a pointer to a struct perf_event_attr as an argument to update an old breakpoint event with new address, type, and size. This facility allows retaining a previous mmaped perf events ring buffer and avoids having to close and reopen another perf event. This patch supports only changing PERF_TYPE_BREAKPOINT event type; future implementations can extend this feature. The patch replicates some of its functionality of modify_user_hw_breakpoint() in kernel/events/hw_breakpoint.c. modify_user_hw_breakpoint cannot be called directly since perf_event_ctx_lock() is already held in _perf_ioctl(). Evidence: Experiments show that the baseline (not able to modify an already created breakpoint) costs an order of magnitude (~10x) more than the suggested optimization (having the ability to dynamically modifying a configured breakpoint via ioctl). When the breakpoints typically do not trap, the speedup due to the suggested optimization is ~10x; even when the breakpoints always trap, the speedup is ~4x due to the suggested optimization. Testing: tests posted at https://github.com/linux-contrib/perf_event_modify_bp demonstrate the performance significance of this patch. Tests also check the functional correctness of the patch. Signed-off-by: Milind Chabbi [ Using modify_user_hw_breakpoint_check function. ] [ Reformated PERF_EVENT_IOC_*, so the values are all in one column. ] Signed-off-by: Jiri Olsa Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: David Ahern Cc: Frederic Weisbecker Cc: Hari Bathini Cc: Jin Yao Cc: Jiri Olsa Cc: Kan Liang Cc: Linus Torvalds Cc: Michael Ellerman Cc: Namhyung Kim Cc: Oleg Nesterov Cc: Peter Zijlstra Cc: Sukadev Bhattiprolu Cc: Thomas Gleixner Cc: Will Deacon Link: http://lkml.kernel.org/r/20180312134548.31532-8-jolsa@kernel.org Signed-off-by: Ingo Molnar --- include/linux/hw_breakpoint.h | 7 +++++ include/uapi/linux/perf_event.h | 23 +++++++++-------- kernel/events/core.c | 48 +++++++++++++++++++++++++++++++++++ kernel/events/hw_breakpoint.c | 2 +- tools/include/uapi/linux/perf_event.h | 23 +++++++++-------- 5 files changed, 80 insertions(+), 23 deletions(-) (limited to 'include/linux') diff --git a/include/linux/hw_breakpoint.h b/include/linux/hw_breakpoint.h index cf045885a499..6058c3844a76 100644 --- a/include/linux/hw_breakpoint.h +++ b/include/linux/hw_breakpoint.h @@ -53,6 +53,9 @@ register_user_hw_breakpoint(struct perf_event_attr *attr, /* FIXME: only change from the attr, and don't unregister */ extern int modify_user_hw_breakpoint(struct perf_event *bp, struct perf_event_attr *attr); +extern int +modify_user_hw_breakpoint_check(struct perf_event *bp, struct perf_event_attr *attr, + bool check); /* * Kernel breakpoints are not associated with any particular thread. @@ -97,6 +100,10 @@ register_user_hw_breakpoint(struct perf_event_attr *attr, static inline int modify_user_hw_breakpoint(struct perf_event *bp, struct perf_event_attr *attr) { return -ENOSYS; } +static inline int +modify_user_hw_breakpoint_check(struct perf_event *bp, struct perf_event_attr *attr, + bool check) { return -ENOSYS; } + static inline struct perf_event * register_wide_hw_breakpoint_cpu(struct perf_event_attr *attr, perf_overflow_handler_t triggered, diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 6f873503552d..912b85b52344 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -448,17 +448,18 @@ struct perf_event_query_bpf { /* * Ioctls that can be done on a perf event fd: */ -#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) -#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) -#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) -#define PERF_EVENT_IOC_RESET _IO ('$', 3) -#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) -#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) -#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) -#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) -#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) -#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) -#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) +#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) +#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) +#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) +#define PERF_EVENT_IOC_RESET _IO ('$', 3) +#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) +#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) +#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) +#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) +#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) +#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) +#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) +#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) enum perf_event_ioc_flags { PERF_IOC_FLAG_GROUP = 1U << 0, diff --git a/kernel/events/core.c b/kernel/events/core.c index ee145bdee6ed..3b4c7792a6ac 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -2846,6 +2846,41 @@ int perf_event_refresh(struct perf_event *event, int refresh) } EXPORT_SYMBOL_GPL(perf_event_refresh); +static int perf_event_modify_breakpoint(struct perf_event *bp, + struct perf_event_attr *attr) +{ + int err; + + _perf_event_disable(bp); + + err = modify_user_hw_breakpoint_check(bp, attr, true); + if (err) { + if (!bp->attr.disabled) + _perf_event_enable(bp); + + return err; + } + + if (!attr->disabled) + _perf_event_enable(bp); + return 0; +} + +static int perf_event_modify_attr(struct perf_event *event, + struct perf_event_attr *attr) +{ + if (event->attr.type != attr->type) + return -EINVAL; + + switch (event->attr.type) { + case PERF_TYPE_BREAKPOINT: + return perf_event_modify_breakpoint(event, attr); + default: + /* Place holder for future additions. */ + return -EOPNOTSUPP; + } +} + static void ctx_sched_out(struct perf_event_context *ctx, struct perf_cpu_context *cpuctx, enum event_type_t event_type) @@ -4952,6 +4987,8 @@ static int perf_event_set_output(struct perf_event *event, struct perf_event *output_event); static int perf_event_set_filter(struct perf_event *event, void __user *arg); static int perf_event_set_bpf_prog(struct perf_event *event, u32 prog_fd); +static int perf_copy_attr(struct perf_event_attr __user *uattr, + struct perf_event_attr *attr); static long _perf_ioctl(struct perf_event *event, unsigned int cmd, unsigned long arg) { @@ -5024,6 +5061,17 @@ static long _perf_ioctl(struct perf_event *event, unsigned int cmd, unsigned lon case PERF_EVENT_IOC_QUERY_BPF: return perf_event_query_prog_array(event, (void __user *)arg); + + case PERF_EVENT_IOC_MODIFY_ATTRIBUTES: { + struct perf_event_attr new_attr; + int err = perf_copy_attr((struct perf_event_attr __user *)arg, + &new_attr); + + if (err) + return err; + + return perf_event_modify_attr(event, &new_attr); + } default: return -ENOTTY; } diff --git a/kernel/events/hw_breakpoint.c b/kernel/events/hw_breakpoint.c index 0c82663395f7..6253d5519cd8 100644 --- a/kernel/events/hw_breakpoint.c +++ b/kernel/events/hw_breakpoint.c @@ -456,7 +456,7 @@ register_user_hw_breakpoint(struct perf_event_attr *attr, } EXPORT_SYMBOL_GPL(register_user_hw_breakpoint); -static int +int modify_user_hw_breakpoint_check(struct perf_event *bp, struct perf_event_attr *attr, bool check) { diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index 6f873503552d..912b85b52344 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -448,17 +448,18 @@ struct perf_event_query_bpf { /* * Ioctls that can be done on a perf event fd: */ -#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) -#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) -#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) -#define PERF_EVENT_IOC_RESET _IO ('$', 3) -#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) -#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) -#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) -#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) -#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) -#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) -#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) +#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) +#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) +#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) +#define PERF_EVENT_IOC_RESET _IO ('$', 3) +#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) +#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) +#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) +#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) +#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) +#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) +#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) +#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) enum perf_event_ioc_flags { PERF_IOC_FLAG_GROUP = 1U << 0, -- cgit v1.2.3 From 31156ec378c2ed10330c8c06bbf36fb7d7a55506 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 13 Mar 2018 17:28:39 +0100 Subject: bsg-lib: introduce a timeout field in struct bsg_job The zfcp driver wants to know the timeout for a bsg job, so add a field to struct bsg_job for it in preparation of not exposing the request to the bsg-lib users. Signed-off-by: Christoph Hellwig Reviewed-by: Benjamin Block Reviewed-by: Hannes Reinecke Reviewed-by: Johannes Thumshirn Signed-off-by: Jens Axboe --- block/bsg-lib.c | 1 + drivers/s390/scsi/zfcp_fc.c | 4 ++-- include/linux/bsg-lib.h | 2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/block/bsg-lib.c b/block/bsg-lib.c index b4fe1a48f111..fb509779a090 100644 --- a/block/bsg-lib.c +++ b/block/bsg-lib.c @@ -132,6 +132,7 @@ static int bsg_prepare_job(struct device *dev, struct request *req) struct bsg_job *job = blk_mq_rq_to_pdu(req); int ret; + job->timeout = req->timeout; job->request = rq->cmd; job->request_len = rq->cmd_len; diff --git a/drivers/s390/scsi/zfcp_fc.c b/drivers/s390/scsi/zfcp_fc.c index ca218c82321f..6162cf57a20a 100644 --- a/drivers/s390/scsi/zfcp_fc.c +++ b/drivers/s390/scsi/zfcp_fc.c @@ -961,7 +961,7 @@ static int zfcp_fc_exec_els_job(struct bsg_job *job, d_id = ntoh24(bsg_request->rqst_data.h_els.port_id); els->handler = zfcp_fc_ct_els_job_handler; - return zfcp_fsf_send_els(adapter, d_id, els, job->req->timeout / HZ); + return zfcp_fsf_send_els(adapter, d_id, els, job->timeout / HZ); } static int zfcp_fc_exec_ct_job(struct bsg_job *job, @@ -980,7 +980,7 @@ static int zfcp_fc_exec_ct_job(struct bsg_job *job, return ret; ct->handler = zfcp_fc_ct_job_handler; - ret = zfcp_fsf_send_ct(wka_port, ct, NULL, job->req->timeout / HZ); + ret = zfcp_fsf_send_ct(wka_port, ct, NULL, job->timeout / HZ); if (ret) zfcp_fc_wka_port_put(wka_port); diff --git a/include/linux/bsg-lib.h b/include/linux/bsg-lib.h index b1be0233ce35..402223c95ce1 100644 --- a/include/linux/bsg-lib.h +++ b/include/linux/bsg-lib.h @@ -44,6 +44,8 @@ struct bsg_job { struct kref kref; + unsigned int timeout; + /* Transport/driver specific request/reply structs */ void *request; void *reply; -- cgit v1.2.3 From ef6fa64f9b8e1611854077ea9213f2eef2428cd2 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 13 Mar 2018 17:28:40 +0100 Subject: bsg-lib: remove bsg_job.req Users of the bsg-lib interface should only use the bsg_job data structure and not know about implementation details of it. Signed-off-by: Christoph Hellwig Reviewed-by: Benjamin Block Reviewed-by: Hannes Reinecke Reviewed-by: Johannes Thumshirn Signed-off-by: Jens Axboe --- block/bsg-lib.c | 14 ++++++-------- include/linux/bsg-lib.h | 1 - 2 files changed, 6 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/block/bsg-lib.c b/block/bsg-lib.c index fb509779a090..f2c2d54a61b4 100644 --- a/block/bsg-lib.c +++ b/block/bsg-lib.c @@ -35,7 +35,7 @@ static void bsg_teardown_job(struct kref *kref) { struct bsg_job *job = container_of(kref, struct bsg_job, kref); - struct request *rq = job->req; + struct request *rq = blk_mq_rq_from_pdu(job); put_device(job->dev); /* release reference for the request */ @@ -68,19 +68,18 @@ EXPORT_SYMBOL_GPL(bsg_job_get); void bsg_job_done(struct bsg_job *job, int result, unsigned int reply_payload_rcv_len) { - struct request *req = job->req; + struct request *req = blk_mq_rq_from_pdu(job); struct request *rsp = req->next_rq; - struct scsi_request *rq = scsi_req(req); int err; - err = scsi_req(job->req)->result = result; + err = job->sreq.result = result; if (err < 0) /* we're only returning the result field in the reply */ - rq->sense_len = sizeof(u32); + job->sreq.sense_len = sizeof(u32); else - rq->sense_len = job->reply_len; + job->sreq.sense_len = job->reply_len; /* we assume all request payload was transferred, residual == 0 */ - rq->resid_len = 0; + job->sreq.resid_len = 0; if (rsp) { WARN_ON(reply_payload_rcv_len > scsi_req(rsp)->resid_len); @@ -232,7 +231,6 @@ static void bsg_initialize_rq(struct request *req) sreq->sense = sense; sreq->sense_len = SCSI_SENSE_BUFFERSIZE; - job->req = req; job->reply = sense; job->reply_len = sreq->sense_len; job->dd_data = job + 1; diff --git a/include/linux/bsg-lib.h b/include/linux/bsg-lib.h index 402223c95ce1..08762d297cbd 100644 --- a/include/linux/bsg-lib.h +++ b/include/linux/bsg-lib.h @@ -40,7 +40,6 @@ struct bsg_buffer { struct bsg_job { struct scsi_request sreq; struct device *dev; - struct request *req; struct kref kref; -- cgit v1.2.3 From 17cb960f29c29ee07bf6848ada3265f4be55972e Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 13 Mar 2018 17:28:41 +0100 Subject: bsg: split handling of SCSI CDBs vs transport requeues The current BSG design tries to shoe-horn the transport-specific passthrough commands into the overall framework for SCSI passthrough requests. This has a couple problems: - each passthrough queue has to set the QUEUE_FLAG_SCSI_PASSTHROUGH flag despite not dealing with SCSI commands at all. Because of that these queues could also incorrectly accept SCSI commands from in-kernel users or through the legacy SCSI_IOCTL_SEND_COMMAND ioctl. - the real SCSI bsg queues also incorrectly accept bsg requests of the BSG_SUB_PROTOCOL_SCSI_TRANSPORT type - the bsg transport code is almost unredable because it tries to reuse different SCSI concepts for its own purpose. This patch instead adds a new bsg_ops structure to handle the two cases differently, and thus solves all of the above problems. Another side effect is that the bsg-lib queues also don't need to embedd a struct scsi_request anymore. Signed-off-by: Christoph Hellwig Reviewed-by: Hannes Reinecke Reviewed-by: Johannes Thumshirn Signed-off-by: Jens Axboe --- block/bsg-lib.c | 158 +++++++++++++++-------- block/bsg.c | 262 +++++++++++++++++--------------------- drivers/scsi/scsi_lib.c | 4 +- drivers/scsi/scsi_sysfs.c | 3 +- drivers/scsi/scsi_transport_sas.c | 1 - include/linux/bsg-lib.h | 4 +- include/linux/bsg.h | 35 +++-- 7 files changed, 250 insertions(+), 217 deletions(-) (limited to 'include/linux') diff --git a/block/bsg-lib.c b/block/bsg-lib.c index f2c2d54a61b4..fc2e5ff2c4b9 100644 --- a/block/bsg-lib.c +++ b/block/bsg-lib.c @@ -27,6 +27,94 @@ #include #include #include +#include + +#define uptr64(val) ((void __user *)(uintptr_t)(val)) + +static int bsg_transport_check_proto(struct sg_io_v4 *hdr) +{ + if (hdr->protocol != BSG_PROTOCOL_SCSI || + hdr->subprotocol != BSG_SUB_PROTOCOL_SCSI_TRANSPORT) + return -EINVAL; + if (!capable(CAP_SYS_RAWIO)) + return -EPERM; + return 0; +} + +static int bsg_transport_fill_hdr(struct request *rq, struct sg_io_v4 *hdr, + fmode_t mode) +{ + struct bsg_job *job = blk_mq_rq_to_pdu(rq); + + job->request_len = hdr->request_len; + job->request = memdup_user(uptr64(hdr->request), hdr->request_len); + if (IS_ERR(job->request)) + return PTR_ERR(job->request); + return 0; +} + +static int bsg_transport_complete_rq(struct request *rq, struct sg_io_v4 *hdr) +{ + struct bsg_job *job = blk_mq_rq_to_pdu(rq); + int ret = 0; + + /* + * The assignments below don't make much sense, but are kept for + * bug by bug backwards compatibility: + */ + hdr->device_status = job->result & 0xff; + hdr->transport_status = host_byte(job->result); + hdr->driver_status = driver_byte(job->result); + hdr->info = 0; + if (hdr->device_status || hdr->transport_status || hdr->driver_status) + hdr->info |= SG_INFO_CHECK; + hdr->response_len = 0; + + if (job->result < 0) { + /* we're only returning the result field in the reply */ + job->reply_len = sizeof(u32); + ret = job->result; + } + + if (job->reply_len && hdr->response) { + int len = min(hdr->max_response_len, job->reply_len); + + if (copy_to_user(uptr64(hdr->response), job->reply, len)) + ret = -EFAULT; + else + hdr->response_len = len; + } + + /* we assume all request payload was transferred, residual == 0 */ + hdr->dout_resid = 0; + + if (rq->next_rq) { + unsigned int rsp_len = job->reply_payload.payload_len; + + if (WARN_ON(job->reply_payload_rcv_len > rsp_len)) + hdr->din_resid = 0; + else + hdr->din_resid = rsp_len - job->reply_payload_rcv_len; + } else { + hdr->din_resid = 0; + } + + return ret; +} + +static void bsg_transport_free_rq(struct request *rq) +{ + struct bsg_job *job = blk_mq_rq_to_pdu(rq); + + kfree(job->request); +} + +static const struct bsg_ops bsg_transport_ops = { + .check_proto = bsg_transport_check_proto, + .fill_hdr = bsg_transport_fill_hdr, + .complete_rq = bsg_transport_complete_rq, + .free_rq = bsg_transport_free_rq, +}; /** * bsg_teardown_job - routine to teardown a bsg job @@ -68,27 +156,9 @@ EXPORT_SYMBOL_GPL(bsg_job_get); void bsg_job_done(struct bsg_job *job, int result, unsigned int reply_payload_rcv_len) { - struct request *req = blk_mq_rq_from_pdu(job); - struct request *rsp = req->next_rq; - int err; - - err = job->sreq.result = result; - if (err < 0) - /* we're only returning the result field in the reply */ - job->sreq.sense_len = sizeof(u32); - else - job->sreq.sense_len = job->reply_len; - /* we assume all request payload was transferred, residual == 0 */ - job->sreq.resid_len = 0; - - if (rsp) { - WARN_ON(reply_payload_rcv_len > scsi_req(rsp)->resid_len); - - /* set reply (bidi) residual */ - scsi_req(rsp)->resid_len -= - min(reply_payload_rcv_len, scsi_req(rsp)->resid_len); - } - blk_complete_request(req); + job->result = result; + job->reply_payload_rcv_len = reply_payload_rcv_len; + blk_complete_request(blk_mq_rq_from_pdu(job)); } EXPORT_SYMBOL_GPL(bsg_job_done); @@ -113,7 +183,6 @@ static int bsg_map_buffer(struct bsg_buffer *buf, struct request *req) if (!buf->sg_list) return -ENOMEM; sg_init_table(buf->sg_list, req->nr_phys_segments); - scsi_req(req)->resid_len = blk_rq_bytes(req); buf->sg_cnt = blk_rq_map_sg(req->q, req, buf->sg_list); buf->payload_len = blk_rq_bytes(req); return 0; @@ -124,16 +193,13 @@ static int bsg_map_buffer(struct bsg_buffer *buf, struct request *req) * @dev: device that is being sent the bsg request * @req: BSG request that needs a job structure */ -static int bsg_prepare_job(struct device *dev, struct request *req) +static bool bsg_prepare_job(struct device *dev, struct request *req) { struct request *rsp = req->next_rq; - struct scsi_request *rq = scsi_req(req); struct bsg_job *job = blk_mq_rq_to_pdu(req); int ret; job->timeout = req->timeout; - job->request = rq->cmd; - job->request_len = rq->cmd_len; if (req->bio) { ret = bsg_map_buffer(&job->request_payload, req); @@ -149,12 +215,13 @@ static int bsg_prepare_job(struct device *dev, struct request *req) /* take a reference for the request */ get_device(job->dev); kref_init(&job->kref); - return 0; + return true; failjob_rls_rqst_payload: kfree(job->request_payload.sg_list); failjob_rls_job: - return -ENOMEM; + job->result = -ENOMEM; + return false; } /** @@ -183,9 +250,7 @@ static void bsg_request_fn(struct request_queue *q) break; spin_unlock_irq(q->queue_lock); - ret = bsg_prepare_job(dev, req); - if (ret) { - scsi_req(req)->result = ret; + if (!bsg_prepare_job(dev, req)) { blk_end_request_all(req, BLK_STS_OK); spin_lock_irq(q->queue_lock); continue; @@ -202,46 +267,34 @@ static void bsg_request_fn(struct request_queue *q) spin_lock_irq(q->queue_lock); } +/* called right after the request is allocated for the request_queue */ static int bsg_init_rq(struct request_queue *q, struct request *req, gfp_t gfp) { struct bsg_job *job = blk_mq_rq_to_pdu(req); - struct scsi_request *sreq = &job->sreq; - - /* called right after the request is allocated for the request_queue */ - sreq->sense = kzalloc(SCSI_SENSE_BUFFERSIZE, gfp); - if (!sreq->sense) + job->reply = kzalloc(SCSI_SENSE_BUFFERSIZE, gfp); + if (!job->reply) return -ENOMEM; - return 0; } +/* called right before the request is given to the request_queue user */ static void bsg_initialize_rq(struct request *req) { struct bsg_job *job = blk_mq_rq_to_pdu(req); - struct scsi_request *sreq = &job->sreq; - void *sense = sreq->sense; - - /* called right before the request is given to the request_queue user */ + void *reply = job->reply; memset(job, 0, sizeof(*job)); - - scsi_req_init(sreq); - - sreq->sense = sense; - sreq->sense_len = SCSI_SENSE_BUFFERSIZE; - - job->reply = sense; - job->reply_len = sreq->sense_len; + job->reply = reply; + job->reply_len = SCSI_SENSE_BUFFERSIZE; job->dd_data = job + 1; } static void bsg_exit_rq(struct request_queue *q, struct request *req) { struct bsg_job *job = blk_mq_rq_to_pdu(req); - struct scsi_request *sreq = &job->sreq; - kfree(sreq->sense); + kfree(job->reply); } /** @@ -275,11 +328,10 @@ struct request_queue *bsg_setup_queue(struct device *dev, const char *name, q->queuedata = dev; q->bsg_job_fn = job_fn; blk_queue_flag_set(QUEUE_FLAG_BIDI, q); - blk_queue_flag_set(QUEUE_FLAG_SCSI_PASSTHROUGH, q); blk_queue_softirq_done(q, bsg_softirq_done); blk_queue_rq_timeout(q, BLK_DEFAULT_SG_TIMEOUT); - ret = bsg_register_queue(q, dev, name, release); + ret = bsg_register_queue(q, dev, name, &bsg_transport_ops, release); if (ret) { printk(KERN_ERR "%s: bsg interface failed to " "initialize - register queue\n", dev->kobj.name); diff --git a/block/bsg.c b/block/bsg.c index 06dc96e1f670..defa06c11858 100644 --- a/block/bsg.c +++ b/block/bsg.c @@ -130,114 +130,120 @@ static inline struct hlist_head *bsg_dev_idx_hash(int index) return &bsg_device_list[index & (BSG_LIST_ARRAY_SIZE - 1)]; } -static int blk_fill_sgv4_hdr_rq(struct request_queue *q, struct request *rq, - struct sg_io_v4 *hdr, struct bsg_device *bd, - fmode_t mode) +#define uptr64(val) ((void __user *)(uintptr_t)(val)) + +static int bsg_scsi_check_proto(struct sg_io_v4 *hdr) +{ + if (hdr->protocol != BSG_PROTOCOL_SCSI || + hdr->subprotocol != BSG_SUB_PROTOCOL_SCSI_CMD) + return -EINVAL; + return 0; +} + +static int bsg_scsi_fill_hdr(struct request *rq, struct sg_io_v4 *hdr, + fmode_t mode) { - struct scsi_request *req = scsi_req(rq); + struct scsi_request *sreq = scsi_req(rq); - if (hdr->request_len > BLK_MAX_CDB) { - req->cmd = kzalloc(hdr->request_len, GFP_KERNEL); - if (!req->cmd) + sreq->cmd_len = hdr->request_len; + if (sreq->cmd_len > BLK_MAX_CDB) { + sreq->cmd = kzalloc(sreq->cmd_len, GFP_KERNEL); + if (!sreq->cmd) return -ENOMEM; } - if (copy_from_user(req->cmd, (void __user *)(unsigned long)hdr->request, - hdr->request_len)) + if (copy_from_user(sreq->cmd, uptr64(hdr->request), sreq->cmd_len)) return -EFAULT; - - if (hdr->subprotocol == BSG_SUB_PROTOCOL_SCSI_CMD) { - if (blk_verify_command(req->cmd, mode)) - return -EPERM; - } else if (!capable(CAP_SYS_RAWIO)) + if (blk_verify_command(sreq->cmd, mode)) return -EPERM; - - /* - * fill in request structure - */ - req->cmd_len = hdr->request_len; - - rq->timeout = msecs_to_jiffies(hdr->timeout); - if (!rq->timeout) - rq->timeout = q->sg_timeout; - if (!rq->timeout) - rq->timeout = BLK_DEFAULT_SG_TIMEOUT; - if (rq->timeout < BLK_MIN_SG_TIMEOUT) - rq->timeout = BLK_MIN_SG_TIMEOUT; - return 0; } -/* - * Check if sg_io_v4 from user is allowed and valid - */ -static int -bsg_validate_sgv4_hdr(struct sg_io_v4 *hdr, int *op) +static int bsg_scsi_complete_rq(struct request *rq, struct sg_io_v4 *hdr) { + struct scsi_request *sreq = scsi_req(rq); int ret = 0; - if (hdr->guard != 'Q') - return -EINVAL; + /* + * fill in all the output members + */ + hdr->device_status = sreq->result & 0xff; + hdr->transport_status = host_byte(sreq->result); + hdr->driver_status = driver_byte(sreq->result); + hdr->info = 0; + if (hdr->device_status || hdr->transport_status || hdr->driver_status) + hdr->info |= SG_INFO_CHECK; + hdr->response_len = 0; - switch (hdr->protocol) { - case BSG_PROTOCOL_SCSI: - switch (hdr->subprotocol) { - case BSG_SUB_PROTOCOL_SCSI_CMD: - case BSG_SUB_PROTOCOL_SCSI_TRANSPORT: - break; - default: - ret = -EINVAL; - } - break; - default: - ret = -EINVAL; + if (sreq->sense_len && hdr->response) { + int len = min_t(unsigned int, hdr->max_response_len, + sreq->sense_len); + + if (copy_to_user(uptr64(hdr->response), sreq->sense, len)) + ret = -EFAULT; + else + hdr->response_len = len; + } + + if (rq->next_rq) { + hdr->dout_resid = sreq->resid_len; + hdr->din_resid = scsi_req(rq->next_rq)->resid_len; + } else if (rq_data_dir(rq) == READ) { + hdr->din_resid = sreq->resid_len; + } else { + hdr->dout_resid = sreq->resid_len; } - *op = hdr->dout_xfer_len ? REQ_OP_SCSI_OUT : REQ_OP_SCSI_IN; return ret; } -/* - * map sg_io_v4 to a request. - */ +static void bsg_scsi_free_rq(struct request *rq) +{ + scsi_req_free_cmd(scsi_req(rq)); +} + +static const struct bsg_ops bsg_scsi_ops = { + .check_proto = bsg_scsi_check_proto, + .fill_hdr = bsg_scsi_fill_hdr, + .complete_rq = bsg_scsi_complete_rq, + .free_rq = bsg_scsi_free_rq, +}; + static struct request * -bsg_map_hdr(struct bsg_device *bd, struct sg_io_v4 *hdr, fmode_t mode) +bsg_map_hdr(struct request_queue *q, struct sg_io_v4 *hdr, fmode_t mode) { - struct request_queue *q = bd->queue; struct request *rq, *next_rq = NULL; int ret; - unsigned int op, dxfer_len; - void __user *dxferp = NULL; - struct bsg_class_device *bcd = &q->bsg_dev; - /* if the LLD has been removed then the bsg_unregister_queue will - * eventually be called and the class_dev was freed, so we can no - * longer use this request_queue. Return no such address. - */ - if (!bcd->class_dev) + if (!q->bsg_dev.class_dev) return ERR_PTR(-ENXIO); - bsg_dbg(bd, "map hdr %llx/%u %llx/%u\n", - (unsigned long long) hdr->dout_xferp, - hdr->dout_xfer_len, (unsigned long long) hdr->din_xferp, - hdr->din_xfer_len); + if (hdr->guard != 'Q') + return ERR_PTR(-EINVAL); - ret = bsg_validate_sgv4_hdr(hdr, &op); + ret = q->bsg_dev.ops->check_proto(hdr); if (ret) return ERR_PTR(ret); - /* - * map scatter-gather elements separately and string them to request - */ - rq = blk_get_request(q, op, GFP_KERNEL); + rq = blk_get_request(q, hdr->dout_xfer_len ? + REQ_OP_SCSI_OUT : REQ_OP_SCSI_IN, + GFP_KERNEL); if (IS_ERR(rq)) return rq; - ret = blk_fill_sgv4_hdr_rq(q, rq, hdr, bd, mode); + ret = q->bsg_dev.ops->fill_hdr(rq, hdr, mode); if (ret) goto out; - if (op == REQ_OP_SCSI_OUT && hdr->din_xfer_len) { + rq->timeout = msecs_to_jiffies(hdr->timeout); + if (!rq->timeout) + rq->timeout = q->sg_timeout; + if (!rq->timeout) + rq->timeout = BLK_DEFAULT_SG_TIMEOUT; + if (rq->timeout < BLK_MIN_SG_TIMEOUT) + rq->timeout = BLK_MIN_SG_TIMEOUT; + + if (hdr->dout_xfer_len && hdr->din_xfer_len) { if (!test_bit(QUEUE_FLAG_BIDI, &q->queue_flags)) { ret = -EOPNOTSUPP; goto out; @@ -246,42 +252,39 @@ bsg_map_hdr(struct bsg_device *bd, struct sg_io_v4 *hdr, fmode_t mode) next_rq = blk_get_request(q, REQ_OP_SCSI_IN, GFP_KERNEL); if (IS_ERR(next_rq)) { ret = PTR_ERR(next_rq); - next_rq = NULL; goto out; } - rq->next_rq = next_rq; - dxferp = (void __user *)(unsigned long)hdr->din_xferp; - ret = blk_rq_map_user(q, next_rq, NULL, dxferp, + rq->next_rq = next_rq; + ret = blk_rq_map_user(q, next_rq, NULL, uptr64(hdr->din_xferp), hdr->din_xfer_len, GFP_KERNEL); if (ret) - goto out; + goto out_free_nextrq; } if (hdr->dout_xfer_len) { - dxfer_len = hdr->dout_xfer_len; - dxferp = (void __user *)(unsigned long)hdr->dout_xferp; + ret = blk_rq_map_user(q, rq, NULL, uptr64(hdr->dout_xferp), + hdr->dout_xfer_len, GFP_KERNEL); } else if (hdr->din_xfer_len) { - dxfer_len = hdr->din_xfer_len; - dxferp = (void __user *)(unsigned long)hdr->din_xferp; - } else - dxfer_len = 0; - - if (dxfer_len) { - ret = blk_rq_map_user(q, rq, NULL, dxferp, dxfer_len, - GFP_KERNEL); - if (ret) - goto out; + ret = blk_rq_map_user(q, rq, NULL, uptr64(hdr->din_xferp), + hdr->din_xfer_len, GFP_KERNEL); + } else { + ret = blk_rq_map_user(q, rq, NULL, NULL, 0, GFP_KERNEL); } + if (ret) + goto out_unmap_nextrq; return rq; + +out_unmap_nextrq: + if (rq->next_rq) + blk_rq_unmap_user(rq->next_rq->bio); +out_free_nextrq: + if (rq->next_rq) + blk_put_request(rq->next_rq); out: - scsi_req_free_cmd(scsi_req(rq)); + q->bsg_dev.ops->free_rq(rq); blk_put_request(rq); - if (next_rq) { - blk_rq_unmap_user(next_rq->bio); - blk_put_request(next_rq); - } return ERR_PTR(ret); } @@ -383,56 +386,18 @@ static struct bsg_command *bsg_get_done_cmd(struct bsg_device *bd) static int blk_complete_sgv4_hdr_rq(struct request *rq, struct sg_io_v4 *hdr, struct bio *bio, struct bio *bidi_bio) { - struct scsi_request *req = scsi_req(rq); - int ret = 0; - - pr_debug("rq %p bio %p 0x%x\n", rq, bio, req->result); - /* - * fill in all the output members - */ - hdr->device_status = req->result & 0xff; - hdr->transport_status = host_byte(req->result); - hdr->driver_status = driver_byte(req->result); - hdr->info = 0; - if (hdr->device_status || hdr->transport_status || hdr->driver_status) - hdr->info |= SG_INFO_CHECK; - hdr->response_len = 0; - - if (req->sense_len && hdr->response) { - int len = min_t(unsigned int, hdr->max_response_len, - req->sense_len); + int ret; - ret = copy_to_user((void __user *)(unsigned long)hdr->response, - req->sense, len); - if (!ret) - hdr->response_len = len; - else - ret = -EFAULT; - } + ret = rq->q->bsg_dev.ops->complete_rq(rq, hdr); if (rq->next_rq) { - hdr->dout_resid = req->resid_len; - hdr->din_resid = scsi_req(rq->next_rq)->resid_len; blk_rq_unmap_user(bidi_bio); blk_put_request(rq->next_rq); - } else if (rq_data_dir(rq) == READ) - hdr->din_resid = req->resid_len; - else - hdr->dout_resid = req->resid_len; - - /* - * If the request generated a negative error number, return it - * (providing we aren't already returning an error); if it's - * just a protocol response (i.e. non negative), that gets - * processed above. - */ - if (!ret && req->result < 0) - ret = req->result; + } blk_rq_unmap_user(bio); - scsi_req_free_cmd(req); + rq->q->bsg_dev.ops->free_rq(rq); blk_put_request(rq); - return ret; } @@ -614,7 +579,7 @@ static int __bsg_write(struct bsg_device *bd, const char __user *buf, /* * get a request, fill in the blanks, and add to request queue */ - rq = bsg_map_hdr(bd, &bc->hdr, mode); + rq = bsg_map_hdr(bd->queue, &bc->hdr, mode); if (IS_ERR(rq)) { ret = PTR_ERR(rq); rq = NULL; @@ -742,11 +707,6 @@ static struct bsg_device *bsg_add_device(struct inode *inode, struct bsg_device *bd; unsigned char buf[32]; - if (!blk_queue_scsi_passthrough(rq)) { - WARN_ONCE(true, "Attempt to register a non-SCSI queue\n"); - return ERR_PTR(-EINVAL); - } - if (!blk_get_queue(rq)) return ERR_PTR(-ENXIO); @@ -907,7 +867,7 @@ static long bsg_ioctl(struct file *file, unsigned int cmd, unsigned long arg) if (copy_from_user(&hdr, uarg, sizeof(hdr))) return -EFAULT; - rq = bsg_map_hdr(bd, &hdr, file->f_mode); + rq = bsg_map_hdr(bd->queue, &hdr, file->f_mode); if (IS_ERR(rq)) return PTR_ERR(rq); @@ -959,7 +919,8 @@ void bsg_unregister_queue(struct request_queue *q) EXPORT_SYMBOL_GPL(bsg_unregister_queue); int bsg_register_queue(struct request_queue *q, struct device *parent, - const char *name, void (*release)(struct device *)) + const char *name, const struct bsg_ops *ops, + void (*release)(struct device *)) { struct bsg_class_device *bcd; dev_t dev; @@ -996,6 +957,7 @@ int bsg_register_queue(struct request_queue *q, struct device *parent, bcd->queue = q; bcd->parent = get_device(parent); bcd->release = release; + bcd->ops = ops; kref_init(&bcd->ref); dev = MKDEV(bsg_major, bcd->minor); class_dev = device_create(bsg_class, parent, dev, NULL, "%s", devname); @@ -1023,7 +985,17 @@ unlock: mutex_unlock(&bsg_mutex); return ret; } -EXPORT_SYMBOL_GPL(bsg_register_queue); + +int bsg_scsi_register_queue(struct request_queue *q, struct device *parent) +{ + if (!blk_queue_scsi_passthrough(q)) { + WARN_ONCE(true, "Attempt to register a non-SCSI queue\n"); + return -EINVAL; + } + + return bsg_register_queue(q, parent, NULL, &bsg_scsi_ops, NULL); +} +EXPORT_SYMBOL_GPL(bsg_scsi_register_queue); static struct cdev bsg_cdev; diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index 538152f3528e..37c1d63e847e 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -2140,8 +2140,6 @@ void __scsi_init_queue(struct Scsi_Host *shost, struct request_queue *q) { struct device *dev = shost->dma_dev; - blk_queue_flag_set(QUEUE_FLAG_SCSI_PASSTHROUGH, q); - /* * this limit is imposed by hardware restrictions */ @@ -2239,6 +2237,7 @@ struct request_queue *scsi_old_alloc_queue(struct scsi_device *sdev) } __scsi_init_queue(shost, q); + blk_queue_flag_set(QUEUE_FLAG_SCSI_PASSTHROUGH, q); blk_queue_prep_rq(q, scsi_prep_fn); blk_queue_unprep_rq(q, scsi_unprep_fn); blk_queue_softirq_done(q, scsi_softirq_done); @@ -2270,6 +2269,7 @@ struct request_queue *scsi_mq_alloc_queue(struct scsi_device *sdev) sdev->request_queue->queuedata = sdev; __scsi_init_queue(sdev->host, sdev->request_queue); + blk_queue_flag_set(QUEUE_FLAG_SCSI_PASSTHROUGH, sdev->request_queue); return sdev->request_queue; } diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c index 91b90f672d23..7142c8be1099 100644 --- a/drivers/scsi/scsi_sysfs.c +++ b/drivers/scsi/scsi_sysfs.c @@ -1292,8 +1292,7 @@ int scsi_sysfs_add_sdev(struct scsi_device *sdev) transport_add_device(&sdev->sdev_gendev); sdev->is_visible = 1; - error = bsg_register_queue(rq, &sdev->sdev_gendev, NULL, NULL); - + error = bsg_scsi_register_queue(rq, &sdev->sdev_gendev); if (error) /* we're treating error on bsg register as non-fatal, * so pretend nothing went wrong */ diff --git a/drivers/scsi/scsi_transport_sas.c b/drivers/scsi/scsi_transport_sas.c index 7c0987616684..08acbabfae07 100644 --- a/drivers/scsi/scsi_transport_sas.c +++ b/drivers/scsi/scsi_transport_sas.c @@ -228,7 +228,6 @@ static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy) */ blk_queue_bounce_limit(q, BLK_BOUNCE_HIGH); blk_queue_flag_set(QUEUE_FLAG_BIDI, q); - blk_queue_flag_set(QUEUE_FLAG_SCSI_PASSTHROUGH, q); return 0; } diff --git a/include/linux/bsg-lib.h b/include/linux/bsg-lib.h index 08762d297cbd..28a7ccc55c89 100644 --- a/include/linux/bsg-lib.h +++ b/include/linux/bsg-lib.h @@ -38,7 +38,6 @@ struct bsg_buffer { }; struct bsg_job { - struct scsi_request sreq; struct device *dev; struct kref kref; @@ -64,6 +63,9 @@ struct bsg_job { struct bsg_buffer request_payload; struct bsg_buffer reply_payload; + int result; + unsigned int reply_payload_rcv_len; + void *dd_data; /* Used for driver-specific storage */ }; diff --git a/include/linux/bsg.h b/include/linux/bsg.h index 2a202e41a3af..0c7dd9ceb139 100644 --- a/include/linux/bsg.h +++ b/include/linux/bsg.h @@ -1,34 +1,43 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef BSG_H -#define BSG_H +#ifndef _LINUX_BSG_H +#define _LINUX_BSG_H #include +struct request; + +#ifdef CONFIG_BLK_DEV_BSG +struct bsg_ops { + int (*check_proto)(struct sg_io_v4 *hdr); + int (*fill_hdr)(struct request *rq, struct sg_io_v4 *hdr, + fmode_t mode); + int (*complete_rq)(struct request *rq, struct sg_io_v4 *hdr); + void (*free_rq)(struct request *rq); +}; -#if defined(CONFIG_BLK_DEV_BSG) struct bsg_class_device { struct device *class_dev; struct device *parent; int minor; struct request_queue *queue; struct kref ref; + const struct bsg_ops *ops; void (*release)(struct device *); }; -extern int bsg_register_queue(struct request_queue *q, - struct device *parent, const char *name, - void (*release)(struct device *)); -extern void bsg_unregister_queue(struct request_queue *); +int bsg_register_queue(struct request_queue *q, struct device *parent, + const char *name, const struct bsg_ops *ops, + void (*release)(struct device *)); +int bsg_scsi_register_queue(struct request_queue *q, struct device *parent); +void bsg_unregister_queue(struct request_queue *q); #else -static inline int bsg_register_queue(struct request_queue *q, - struct device *parent, const char *name, - void (*release)(struct device *)) +static inline int bsg_scsi_register_queue(struct request_queue *q, + struct device *parent) { return 0; } static inline void bsg_unregister_queue(struct request_queue *q) { } -#endif - -#endif +#endif /* CONFIG_BLK_DEV_BSG */ +#endif /* _LINUX_BSG_H */ -- cgit v1.2.3 From be9fc0971a5c27b791608cf9705a04fe96dbd395 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 13 Mar 2018 12:44:53 +0100 Subject: net: fix sysctl_fb_tunnels_only_for_init_net link error The new variable is only available when CONFIG_SYSCTL is enabled, otherwise we get a link error: net/ipv4/ip_tunnel.o: In function `ip_tunnel_init_net': ip_tunnel.c:(.text+0x278b): undefined reference to `sysctl_fb_tunnels_only_for_init_net' net/ipv6/sit.o: In function `sit_init_net': sit.c:(.init.text+0x4c): undefined reference to `sysctl_fb_tunnels_only_for_init_net' net/ipv6/ip6_tunnel.o: In function `ip6_tnl_init_net': ip6_tunnel.c:(.init.text+0x39): undefined reference to `sysctl_fb_tunnels_only_for_init_net' This adds an extra condition, keeping the traditional behavior when CONFIG_SYSCTL is disabled. Fixes: 79134e6ce2c9 ("net: do not create fallback tunnels for non-default namespaces") Signed-off-by: Arnd Bergmann Signed-off-by: David S. Miller --- include/linux/netdevice.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 5fbb9f1da7fd..913b1cc882cf 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -589,7 +589,9 @@ extern int sysctl_fb_tunnels_only_for_init_net; static inline bool net_has_fallback_tunnels(const struct net *net) { - return net == &init_net || !sysctl_fb_tunnels_only_for_init_net; + return net == &init_net || + !IS_ENABLED(CONFIG_SYSCTL) || + !sysctl_fb_tunnels_only_for_init_net; } static inline int netdev_queue_numa_node_read(const struct netdev_queue *q) -- cgit v1.2.3 From 2623c7a5f2799569d8bb05eb211da524a8144cb3 Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Fri, 9 Mar 2018 08:34:41 +0000 Subject: libata: add refcounting to ata_host After commit 9a6d6a2ddabb ("ata: make ata port as parent device of scsi host") manual driver unbind/remove causes use-after-free. Unbind unconditionally invokes devres_release_all() which calls ata_host_release() and frees ata_host/ata_port memory while it is still being referenced as a parent of SCSI host. When SCSI host is finally released scsi_host_dev_release() calls put_device(parent) and accesses freed ata_port memory. Add reference counting to make sure that ata_host lives long enough. Bug report: https://lkml.org/lkml/2017/11/1/945 Fixes: 9a6d6a2ddabb ("ata: make ata port as parent device of scsi host") Cc: Tejun Heo Cc: Lin Ming Cc: linux-ide@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Taras Kondratiuk Signed-off-by: Tejun Heo --- drivers/ata/libata-core.c | 44 ++++++++++++++++++++++++++++++++++-------- drivers/ata/libata-transport.c | 4 ++++ drivers/ata/libata.h | 2 ++ include/linux/libata.h | 1 + 4 files changed, 43 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 61b09968d032..b8b85bf97288 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -6005,7 +6005,7 @@ struct ata_port *ata_port_alloc(struct ata_host *host) return ap; } -static void ata_host_release(struct device *gendev, void *res) +static void ata_devres_release(struct device *gendev, void *res) { struct ata_host *host = dev_get_drvdata(gendev); int i; @@ -6019,13 +6019,36 @@ static void ata_host_release(struct device *gendev, void *res) if (ap->scsi_host) scsi_host_put(ap->scsi_host); + } + + dev_set_drvdata(gendev, NULL); + ata_host_put(host); +} + +static void ata_host_release(struct kref *kref) +{ + struct ata_host *host = container_of(kref, struct ata_host, kref); + int i; + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap = host->ports[i]; + kfree(ap->pmp_link); kfree(ap->slave_link); kfree(ap); host->ports[i] = NULL; } + kfree(host); +} - dev_set_drvdata(gendev, NULL); +void ata_host_get(struct ata_host *host) +{ + kref_get(&host->kref); +} + +void ata_host_put(struct ata_host *host) +{ + kref_put(&host->kref, ata_host_release); } /** @@ -6053,26 +6076,31 @@ struct ata_host *ata_host_alloc(struct device *dev, int max_ports) struct ata_host *host; size_t sz; int i; + void *dr; DPRINTK("ENTER\n"); - if (!devres_open_group(dev, NULL, GFP_KERNEL)) - return NULL; - /* alloc a container for our list of ATA ports (buses) */ sz = sizeof(struct ata_host) + (max_ports + 1) * sizeof(void *); - /* alloc a container for our list of ATA ports (buses) */ - host = devres_alloc(ata_host_release, sz, GFP_KERNEL); + host = kzalloc(sz, GFP_KERNEL); if (!host) + return NULL; + + if (!devres_open_group(dev, NULL, GFP_KERNEL)) + return NULL; + + dr = devres_alloc(ata_devres_release, 0, GFP_KERNEL); + if (!dr) goto err_out; - devres_add(dev, host); + devres_add(dev, dr); dev_set_drvdata(dev, host); spin_lock_init(&host->lock); mutex_init(&host->eh_mutex); host->dev = dev; host->n_ports = max_ports; + kref_init(&host->kref); /* allocate ports bound to this host */ for (i = 0; i < max_ports; i++) { diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c index 19e6e539a061..a0b0b4d986f2 100644 --- a/drivers/ata/libata-transport.c +++ b/drivers/ata/libata-transport.c @@ -224,6 +224,8 @@ static DECLARE_TRANSPORT_CLASS(ata_port_class, static void ata_tport_release(struct device *dev) { + struct ata_port *ap = tdev_to_port(dev); + ata_host_put(ap->host); } /** @@ -284,6 +286,7 @@ int ata_tport_add(struct device *parent, dev->type = &ata_port_type; dev->parent = parent; + ata_host_get(ap->host); dev->release = ata_tport_release; dev_set_name(dev, "ata%d", ap->print_id); transport_setup_device(dev); @@ -314,6 +317,7 @@ int ata_tport_add(struct device *parent, tport_err: transport_destroy_device(dev); put_device(dev); + ata_host_put(ap->host); return error; } diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h index f953cb4bb1ba..9e21c49cf6be 100644 --- a/drivers/ata/libata.h +++ b/drivers/ata/libata.h @@ -100,6 +100,8 @@ extern int ata_port_probe(struct ata_port *ap); extern void __ata_port_probe(struct ata_port *ap); extern unsigned int ata_read_log_page(struct ata_device *dev, u8 log, u8 page, void *buf, unsigned int sectors); +extern void ata_host_get(struct ata_host *host); +extern void ata_host_put(struct ata_host *host); #define to_ata_port(d) container_of(d, struct ata_port, tdev) diff --git a/include/linux/libata.h b/include/linux/libata.h index ed9826b21c5e..1795fecdea17 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -617,6 +617,7 @@ struct ata_host { void *private_data; struct ata_port_operations *ops; unsigned long flags; + struct kref kref; struct mutex eh_mutex; struct task_struct *eh_owner; -- cgit v1.2.3 From c2b37f76485f073f020e60b5954b6dc4e55f693c Mon Sep 17 00:00:00 2001 From: Boris Pismenny Date: Thu, 8 Mar 2018 15:51:41 +0200 Subject: IB/mlx5: Fix integer overflows in mlx5_ib_create_srq This patch validates user provided input to prevent integer overflow due to integer manipulation in the mlx5_ib_create_srq function. Cc: syzkaller Fixes: e126ba97dba9 ("mlx5: Add driver for Mellanox Connect-IB adapters") Signed-off-by: Boris Pismenny Signed-off-by: Leon Romanovsky Signed-off-by: Doug Ledford --- drivers/infiniband/hw/mlx5/srq.c | 15 +++++++++------ include/linux/mlx5/driver.h | 4 ++-- 2 files changed, 11 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx5/srq.c b/drivers/infiniband/hw/mlx5/srq.c index 6d5fadad9090..3c7522d025f2 100644 --- a/drivers/infiniband/hw/mlx5/srq.c +++ b/drivers/infiniband/hw/mlx5/srq.c @@ -241,8 +241,8 @@ struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, { struct mlx5_ib_dev *dev = to_mdev(pd->device); struct mlx5_ib_srq *srq; - int desc_size; - int buf_size; + size_t desc_size; + size_t buf_size; int err; struct mlx5_srq_attr in = {0}; __u32 max_srq_wqes = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); @@ -266,15 +266,18 @@ struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, desc_size = sizeof(struct mlx5_wqe_srq_next_seg) + srq->msrq.max_gs * sizeof(struct mlx5_wqe_data_seg); + if (desc_size == 0 || srq->msrq.max_gs > desc_size) + return ERR_PTR(-EINVAL); desc_size = roundup_pow_of_two(desc_size); - desc_size = max_t(int, 32, desc_size); + desc_size = max_t(size_t, 32, desc_size); + if (desc_size < sizeof(struct mlx5_wqe_srq_next_seg)) + return ERR_PTR(-EINVAL); srq->msrq.max_avail_gather = (desc_size - sizeof(struct mlx5_wqe_srq_next_seg)) / sizeof(struct mlx5_wqe_data_seg); srq->msrq.wqe_shift = ilog2(desc_size); buf_size = srq->msrq.max * desc_size; - mlx5_ib_dbg(dev, "desc_size 0x%x, req wr 0x%x, srq size 0x%x, max_gs 0x%x, max_avail_gather 0x%x\n", - desc_size, init_attr->attr.max_wr, srq->msrq.max, srq->msrq.max_gs, - srq->msrq.max_avail_gather); + if (buf_size < desc_size) + return ERR_PTR(-EINVAL); in.type = init_attr->srq_type; if (pd->uobject) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 6ed79a8a8318..9d3a03364e6e 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -453,8 +453,8 @@ struct mlx5_core_srq { struct mlx5_core_rsc_common common; /* must be first */ u32 srqn; int max; - int max_gs; - int max_avail_gather; + size_t max_gs; + size_t max_avail_gather; int wqe_shift; void (*event) (struct mlx5_core_srq *, enum mlx5_event); -- cgit v1.2.3 From 6417250d3f894e66a68ba1cd93676143f2376a6f Mon Sep 17 00:00:00 2001 From: Stephen Hemminger Date: Tue, 6 Mar 2018 19:34:42 -0800 Subject: workqueue: remove unused cancel_work() Found this by accident. There are no usages of bare cancel_work() in current kernel source. Signed-off-by: Stephen Hemminger Signed-off-by: Tejun Heo --- include/linux/workqueue.h | 1 - kernel/workqueue.c | 8 -------- 2 files changed, 9 deletions(-) (limited to 'include/linux') diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h index bc0cda180c8b..0c3301421c57 100644 --- a/include/linux/workqueue.h +++ b/include/linux/workqueue.h @@ -456,7 +456,6 @@ extern int schedule_on_each_cpu(work_func_t func); int execute_in_process_context(work_func_t fn, struct execute_work *); extern bool flush_work(struct work_struct *work); -extern bool cancel_work(struct work_struct *work); extern bool cancel_work_sync(struct work_struct *work); extern bool flush_delayed_work(struct delayed_work *dwork); diff --git a/kernel/workqueue.c b/kernel/workqueue.c index ccd1080dd6e7..6ec6ba65127b 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -3018,14 +3018,6 @@ static bool __cancel_work(struct work_struct *work, bool is_dwork) return ret; } -/* - * See cancel_delayed_work() - */ -bool cancel_work(struct work_struct *work) -{ - return __cancel_work(work, false); -} - /** * cancel_delayed_work - cancel a delayed work * @dwork: delayed_work to cancel -- cgit v1.2.3 From 2a4d2c4240c00e7db8fb64e377bd2180cc30b146 Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Sat, 3 Mar 2018 10:53:24 +0100 Subject: PCI: Make pci_wakeup_bus() & pci_bus_set_current_state() public There are PCI devices which are power-manageable by a nonstandard means, such as a custom ACPI method. One example are discrete GPUs in hybrid graphics laptops, another are Thunderbolt controllers in Macs. Such devices can't be put into D3cold with pci_set_power_state() because pci_platform_power_transition() fails with -ENODEV. Instead they're put into D3hot by pci_set_power_state() and subsequently into D3cold by invoking the nonstandard means. However as a consequence the cached current_state is incorrectly left at D3hot. What we need to do is walk the hierarchy below such a PCI device on powerdown and update the current_state to D3cold. On powerup the PCI device itself and the hierarchy below it is in D0uninitialized, so we need to walk the hierarchy again and wake all devices, causing them to be put into D0active and then letting them autosuspend as they see fit. To this end make pci_wakeup_bus() & pci_bus_set_current_state() public so PCI drivers don't have to reinvent the wheel. Cc: Rafael J. Wysocki Acked-by: Bjorn Helgaas Signed-off-by: Lukas Wunner Link: https://patchwork.freedesktop.org/patch/msgid/2962443259e7faec577274b4ef8c54aad66f9a94.1520068884.git.lukas@wunner.de --- drivers/pci/pci.c | 8 ++++---- include/linux/pci.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f6a4dd10d9b0..bd6f156dc3cf 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -800,7 +800,7 @@ static int pci_wakeup(struct pci_dev *pci_dev, void *ign) * pci_wakeup_bus - Walk given bus and wake up devices on it * @bus: Top bus of the subtree to walk. */ -static void pci_wakeup_bus(struct pci_bus *bus) +void pci_wakeup_bus(struct pci_bus *bus) { if (bus) pci_walk_bus(bus, pci_wakeup, NULL); @@ -850,11 +850,11 @@ static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) } /** - * __pci_bus_set_current_state - Walk given bus and set current state of devices + * pci_bus_set_current_state - Walk given bus and set current state of devices * @bus: Top bus of the subtree to walk. * @state: state to be set */ -static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) +void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) { if (bus) pci_walk_bus(bus, __pci_dev_set_current_state, &state); @@ -876,7 +876,7 @@ int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) ret = pci_platform_power_transition(dev, state); /* Power off the bridge may power off the whole hierarchy */ if (!ret && state == PCI_D3cold) - __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); + pci_bus_set_current_state(dev->subordinate, PCI_D3cold); return ret; } EXPORT_SYMBOL_GPL(__pci_complete_power_transition); diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1beda008..ae42289662df 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1147,6 +1147,8 @@ void pci_pme_wakeup_bus(struct pci_bus *bus); void pci_d3cold_enable(struct pci_dev *dev); void pci_d3cold_disable(struct pci_dev *dev); bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); +void pci_wakeup_bus(struct pci_bus *bus); +void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); /* PCI Virtual Channel */ int pci_save_vc_state(struct pci_dev *dev); -- cgit v1.2.3 From 07f4f97d7b4bf325d9f558c5b58230387e4e57e0 Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Sat, 3 Mar 2018 10:53:24 +0100 Subject: vga_switcheroo: Use device link for HDA controller Back in 2013, runtime PM for GPUs with integrated HDA controller was introduced with commits 0d69704ae348 ("gpu/vga_switcheroo: add driver control power feature. (v3)") and 246efa4a072f ("snd/hda: add runtime suspend/resume on optimus support (v4)"). Briefly, the idea was that the HDA controller is forced on and off in unison with the GPU. The original code is mostly still in place even though it was never a 100% perfect solution: E.g. on access to the HDA controller, the GPU is powered up via vga_switcheroo_runtime_resume_hdmi_audio() but there are no provisions to keep it resumed until access to the HDA controller has ceased: The GPU autosuspends after 5 seconds, rendering the HDA controller inaccessible. Additionally, a kludge is required when hda_intel.c probes: It has to check whether the GPU is powered down (check_hdmi_disabled()) and defer probing if so. However in the meantime (in v4.10) the driver core has gained a feature called device links which promises to solve such issues in a clean way: It allows us to declare a dependency from the HDA controller (consumer) to the GPU (supplier). The PM core then automagically ensures that the GPU is runtime resumed as long as the HDA controller's ->probe hook is executed and whenever the HDA controller is accessed. By default, the HDA controller has a dependency on its parent, a PCIe Root Port. Adding a device link creates another dependency on its sibling: PCIe Root Port ^ ^ | | | | HDA ===> GPU The device link is not only used for runtime PM, it also guarantees that on system sleep, the HDA controller suspends before the GPU and resumes after the GPU, and on system shutdown the HDA controller's ->shutdown hook is executed before the one of the GPU. It is a complete solution. Using this functionality is as simple as calling device_link_add(), which results in a dmesg entry like this: pci 0000:01:00.1: Linked as a consumer to 0000:01:00.0 The code for the GPU-governed audio power management can thus be removed (except where it's still needed for legacy manual power control). The device link is added in a PCI quirk rather than in hda_intel.c. It is therefore legal for the GPU to runtime suspend to D3cold even if the HDA controller is not bound to a driver or if CONFIG_SND_HDA_INTEL is not enabled, for accesses to the HDA controller will cause the GPU to wake up regardless if they're occurring outside of hda_intel.c (think config space readout via sysfs). Contrary to the previous implementation, the HDA controller's power state is now self-governed, rather than GPU-governed, whereas the GPU's power state is no longer fully self-governed. (The HDA controller needs to runtime suspend before the GPU can.) It is thus crucial that runtime PM is always activated on the HDA controller even if CONFIG_SND_HDA_POWER_SAVE_DEFAULT is set to 0 (which is the default), lest the GPU stays awake. This is achieved by setting the auto_runtime_pm flag on every codec and the AZX_DCAPS_PM_RUNTIME flag on the HDA controller. A side effect is that power consumption might be reduced if the GPU is in use but the HDA controller is not, because the HDA controller is now allowed to go to D3hot. Before, it was forced to stay in D0 as long as the GPU was in use. (There is no reduction in power consumption on my Nvidia GK107, but there might be on other chips.) The code paths for legacy manual power control are adjusted such that runtime PM is disabled during power off, thereby preventing the PM core from resuming the HDA controller. Note that the device link is not only added on vga_switcheroo capable systems, but for *any* GPU with integrated HDA controller. The idea is that the HDA controller streams audio via connectors located on the GPU, so the GPU needs to be on for the HDA controller to do anything useful. This commit implicitly fixes an unbalanced runtime PM ref upon unbind of hda_intel.c: On ->probe, a runtime PM ref was previously released under the condition "azx_has_pm_runtime(chip) || hda->use_vga_switcheroo", but on ->remove a runtime PM ref was only acquired under the first of those conditions. Thus, binding and unbinding the driver twice on a vga_switcheroo capable system caused the runtime PM refcount to drop below zero. The issue is resolved because the AZX_DCAPS_PM_RUNTIME flag is now always set if use_vga_switcheroo is true. For more information on device links please refer to: https://www.kernel.org/doc/html/latest/driver-api/device_link.html Documentation/driver-api/device_link.rst Cc: Dave Airlie Cc: Ben Skeggs Cc: Alex Deucher Cc: Rafael J. Wysocki Acked-by: Bjorn Helgaas Reviewed-by: Takashi Iwai Reviewed-by: Peter Wu Tested-by: Kai Heng Feng # AMD PowerXpress Tested-by: Mike Lothian # AMD PowerXpress Tested-by: Denis Lisov # Nvidia Optimus Tested-by: Peter Wu # Nvidia Optimus Tested-by: Lukas Wunner # MacBook Pro Signed-off-by: Lukas Wunner Link: https://patchwork.freedesktop.org/patch/msgid/51bd38360ff502a8c42b1ebf4405ee1d3f27118d.1520068884.git.lukas@wunner.de --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 - drivers/gpu/drm/nouveau/nouveau_drm.c | 2 - drivers/gpu/drm/radeon/radeon_drv.c | 2 - drivers/gpu/vga/vga_switcheroo.c | 115 +++----------------------------- drivers/pci/quirks.c | 39 +++++++++++ include/linux/pci_ids.h | 1 + include/linux/vga_switcheroo.h | 6 -- include/sound/hdaudio.h | 3 - sound/pci/hda/hda_intel.c | 36 +++++++--- sound/pci/hda/hda_intel.h | 3 - 10 files changed, 73 insertions(+), 136 deletions(-) (limited to 'include/linux') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 50afcf65181a..ba4335fd4f65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -720,7 +720,6 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; drm_kms_helper_poll_disable(drm_dev); - vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); ret = amdgpu_device_suspend(drm_dev, false, false); pci_save_state(pdev); @@ -757,7 +756,6 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) ret = amdgpu_device_resume(drm_dev, false, false); drm_kms_helper_poll_enable(drm_dev); - vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 3e293029e3a6..6959951d45d6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -856,7 +856,6 @@ nouveau_pmops_runtime_suspend(struct device *dev) } drm_kms_helper_poll_disable(drm_dev); - vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); nouveau_switcheroo_optimus_dsm(); ret = nouveau_do_suspend(drm_dev, true); pci_save_state(pdev); @@ -891,7 +890,6 @@ nouveau_pmops_runtime_resume(struct device *dev) /* do magic */ nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); - vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; /* Monitors may have been connected / disconnected during suspend */ diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 31dd04f6baa1..b28288a781ef 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -415,7 +415,6 @@ static int radeon_pmops_runtime_suspend(struct device *dev) drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; drm_kms_helper_poll_disable(drm_dev); - vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); ret = radeon_suspend_kms(drm_dev, false, false, false); pci_save_state(pdev); @@ -452,7 +451,6 @@ static int radeon_pmops_runtime_resume(struct device *dev) ret = radeon_resume_kms(drm_dev, false, false); drm_kms_helper_poll_enable(drm_dev); - vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; return 0; } diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c index 2488af797020..4ee0ed642386 100644 --- a/drivers/gpu/vga/vga_switcheroo.c +++ b/drivers/gpu/vga/vga_switcheroo.c @@ -105,8 +105,7 @@ * @list: client list * * Registered client. A client can be either a GPU or an audio device on a GPU. - * For audio clients, the @fb_info, @active and @driver_power_control members - * are bogus. + * For audio clients, the @fb_info and @active members are bogus. */ struct vga_switcheroo_client { struct pci_dev *pdev; @@ -332,8 +331,8 @@ EXPORT_SYMBOL(vga_switcheroo_register_client); * @ops: client callbacks * @id: client identifier * - * Register audio client (audio device on a GPU). The power state of the - * client is assumed to be ON. Beforehand, vga_switcheroo_client_probe_defer() + * Register audio client (audio device on a GPU). The client is assumed + * to use runtime PM. Beforehand, vga_switcheroo_client_probe_defer() * shall be called to ensure that all prerequisites are met. * * Return: 0 on success, -ENOMEM on memory allocation error. @@ -342,7 +341,7 @@ int vga_switcheroo_register_audio_client(struct pci_dev *pdev, const struct vga_switcheroo_client_ops *ops, enum vga_switcheroo_client_id id) { - return register_client(pdev, ops, id | ID_BIT_AUDIO, false, false); + return register_client(pdev, ops, id | ID_BIT_AUDIO, false, true); } EXPORT_SYMBOL(vga_switcheroo_register_audio_client); @@ -655,10 +654,8 @@ static void set_audio_state(enum vga_switcheroo_client_id id, struct vga_switcheroo_client *client; client = find_client_from_id(&vgasr_priv.clients, id | ID_BIT_AUDIO); - if (client) { + if (client) client->ops->set_gpu_state(client->pdev, state); - client->pwr_state = state; - } } /* stage one happens before delay */ @@ -953,10 +950,6 @@ EXPORT_SYMBOL(vga_switcheroo_process_delayed_switch); * Specifying nouveau.runpm=0, radeon.runpm=0 or amdgpu.runpm=0 on the kernel * command line disables it. * - * When the driver decides to power up or down, it notifies vga_switcheroo - * thereof so that it can power the audio device on the GPU up or down. - * This is achieved by vga_switcheroo_set_dynamic_switch(). - * * After the GPU has been suspended, the handler needs to be called to cut * power to the GPU. Likewise it needs to reinstate power before the GPU * can resume. This is achieved by vga_switcheroo_init_domain_pm_ops(), @@ -964,8 +957,9 @@ EXPORT_SYMBOL(vga_switcheroo_process_delayed_switch); * calls to the handler. * * When the audio device resumes, the GPU needs to be woken. This is achieved - * by vga_switcheroo_init_domain_pm_optimus_hdmi_audio(), which augments the - * audio device's resume function. + * by a PCI quirk which calls device_link_add() to declare a dependency on the + * GPU. That way, the GPU is kept awake whenever and as long as the audio + * device is in use. * * On muxed machines, if the mux is initially switched to the discrete GPU, * the user ends up with a black screen when the GPU powers down after boot. @@ -991,33 +985,6 @@ static void vga_switcheroo_power_switch(struct pci_dev *pdev, vgasr_priv.handler->power_state(client->id, state); } -/** - * vga_switcheroo_set_dynamic_switch() - helper for driver power control - * @pdev: client pci device - * @dynamic: new power state - * - * Helper for GPUs whose power state is controlled by the driver's runtime pm. - * When the driver decides to power up or down, it notifies vga_switcheroo - * thereof using this helper so that it can power the audio device on the GPU - * up or down. - */ -void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, - enum vga_switcheroo_state dynamic) -{ - struct vga_switcheroo_client *client; - - mutex_lock(&vgasr_mutex); - client = find_client_from_pci(&vgasr_priv.clients, pdev); - if (!client || !client->driver_power_control) { - mutex_unlock(&vgasr_mutex); - return; - } - - set_audio_state(client->id, dynamic); - mutex_unlock(&vgasr_mutex); -} -EXPORT_SYMBOL(vga_switcheroo_set_dynamic_switch); - /* switcheroo power domain */ static int vga_switcheroo_runtime_suspend(struct device *dev) { @@ -1089,69 +1056,3 @@ void vga_switcheroo_fini_domain_pm_ops(struct device *dev) dev_pm_domain_set(dev, NULL); } EXPORT_SYMBOL(vga_switcheroo_fini_domain_pm_ops); - -static int vga_switcheroo_runtime_resume_hdmi_audio(struct device *dev) -{ - struct pci_dev *pdev = to_pci_dev(dev); - struct vga_switcheroo_client *client; - struct device *video_dev = NULL; - int ret; - - /* we need to check if we have to switch back on the video - * device so the audio device can come back - */ - mutex_lock(&vgasr_mutex); - list_for_each_entry(client, &vgasr_priv.clients, list) { - if (PCI_SLOT(client->pdev->devfn) == PCI_SLOT(pdev->devfn) && - client_is_vga(client)) { - video_dev = &client->pdev->dev; - break; - } - } - mutex_unlock(&vgasr_mutex); - - if (video_dev) { - ret = pm_runtime_get_sync(video_dev); - if (ret && ret != 1) - return ret; - } - ret = dev->bus->pm->runtime_resume(dev); - - /* put the reference for the gpu */ - if (video_dev) { - pm_runtime_mark_last_busy(video_dev); - pm_runtime_put_autosuspend(video_dev); - } - return ret; -} - -/** - * vga_switcheroo_init_domain_pm_optimus_hdmi_audio() - helper for driver - * power control - * @dev: audio client device - * @domain: power domain - * - * Helper for GPUs whose power state is controlled by the driver's runtime pm. - * When the audio device resumes, the GPU needs to be woken. This helper - * augments the audio device's resume function to do that. - * - * Return: 0 on success, -EINVAL if no power management operations are - * defined for this device. - */ -int -vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev, - struct dev_pm_domain *domain) -{ - /* copy over all the bus versions */ - if (dev->bus && dev->bus->pm) { - domain->ops = *dev->bus->pm; - domain->ops.runtime_resume = - vga_switcheroo_runtime_resume_hdmi_audio; - - dev_pm_domain_set(dev, domain); - return 0; - } - dev_pm_domain_set(dev, NULL); - return -EINVAL; -} -EXPORT_SYMBOL(vga_switcheroo_init_domain_pm_optimus_hdmi_audio); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index fc734014206f..ec582d37c189 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -26,6 +26,7 @@ #include #include #include +#include #include /* isa_dma_bridge_buggy */ #include "pci.h" @@ -4832,3 +4833,41 @@ static void quirk_fsl_no_msi(struct pci_dev *pdev) pdev->no_msi = 1; } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); + +/* + * GPUs with integrated HDA controller for streaming audio to attached displays + * need a device link from the HDA controller (consumer) to the GPU (supplier) + * so that the GPU is powered up whenever the HDA controller is accessed. + * The GPU and HDA controller are functions 0 and 1 of the same PCI device. + * The device link stays in place until shutdown (or removal of the PCI device + * if it's hotplugged). Runtime PM is allowed by default on the HDA controller + * to prevent it from permanently keeping the GPU awake. + */ +static void quirk_gpu_hda(struct pci_dev *hda) +{ + struct pci_dev *gpu; + + if (PCI_FUNC(hda->devfn) != 1) + return; + + gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus), + hda->bus->number, + PCI_DEVFN(PCI_SLOT(hda->devfn), 0)); + if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) { + pci_dev_put(gpu); + return; + } + + if (!device_link_add(&hda->dev, &gpu->dev, + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) + pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu)); + + pm_runtime_allow(&hda->dev); + pci_dev_put(gpu); +} +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, + PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, + PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a6b30667a331..a637a7d8ce5b 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -45,6 +45,7 @@ #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 #define PCI_BASE_CLASS_MEMORY 0x05 diff --git a/include/linux/vga_switcheroo.h b/include/linux/vga_switcheroo.h index 960bedbdec87..77f0f0af3a71 100644 --- a/include/linux/vga_switcheroo.h +++ b/include/linux/vga_switcheroo.h @@ -168,11 +168,8 @@ int vga_switcheroo_process_delayed_switch(void); bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev); enum vga_switcheroo_state vga_switcheroo_get_client_state(struct pci_dev *dev); -void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, enum vga_switcheroo_state dynamic); - int vga_switcheroo_init_domain_pm_ops(struct device *dev, struct dev_pm_domain *domain); void vga_switcheroo_fini_domain_pm_ops(struct device *dev); -int vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev, struct dev_pm_domain *domain); #else static inline void vga_switcheroo_unregister_client(struct pci_dev *dev) {} @@ -192,11 +189,8 @@ static inline int vga_switcheroo_process_delayed_switch(void) { return 0; } static inline bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev) { return false; } static inline enum vga_switcheroo_state vga_switcheroo_get_client_state(struct pci_dev *dev) { return VGA_SWITCHEROO_ON; } -static inline void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, enum vga_switcheroo_state dynamic) {} - static inline int vga_switcheroo_init_domain_pm_ops(struct device *dev, struct dev_pm_domain *domain) { return -EINVAL; } static inline void vga_switcheroo_fini_domain_pm_ops(struct device *dev) {} -static inline int vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev, struct dev_pm_domain *domain) { return -EINVAL; } #endif #endif /* _LINUX_VGA_SWITCHEROO_H_ */ diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index 68169e3749de..5b2ed12f58ce 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -227,9 +227,6 @@ struct hdac_io_ops { #define HDA_UNSOL_QUEUE_SIZE 64 #define HDA_MAX_CODECS 8 /* limit by controller side */ -/* HD Audio class code */ -#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 - /* * CORB/RIRB * diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index c71dcacea807..ec4e6b829ee2 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1227,6 +1227,7 @@ static void azx_vs_set_state(struct pci_dev *pci, struct snd_card *card = pci_get_drvdata(pci); struct azx *chip = card->private_data; struct hda_intel *hda = container_of(chip, struct hda_intel, chip); + struct hda_codec *codec; bool disabled; wait_for_completion(&hda->probe_wait); @@ -1251,8 +1252,12 @@ static void azx_vs_set_state(struct pci_dev *pci, dev_info(chip->card->dev, "%s via vga_switcheroo\n", disabled ? "Disabling" : "Enabling"); if (disabled) { - pm_runtime_put_sync_suspend(card->dev); - azx_suspend(card->dev); + list_for_each_codec(codec, &chip->bus) { + pm_runtime_suspend(hda_codec_dev(codec)); + pm_runtime_disable(hda_codec_dev(codec)); + } + pm_runtime_suspend(card->dev); + pm_runtime_disable(card->dev); /* when we get suspended by vga_switcheroo we end up in D3cold, * however we have no ACPI handle, so pci/acpi can't put us there, * put ourselves there */ @@ -1263,9 +1268,12 @@ static void azx_vs_set_state(struct pci_dev *pci, "Cannot lock devices!\n"); } else { snd_hda_unlock_devices(&chip->bus); - pm_runtime_get_noresume(card->dev); chip->disabled = false; - azx_resume(card->dev); + pm_runtime_enable(card->dev); + list_for_each_codec(codec, &chip->bus) { + pm_runtime_enable(hda_codec_dev(codec)); + pm_runtime_resume(hda_codec_dev(codec)); + } } } } @@ -1295,6 +1303,7 @@ static void init_vga_switcheroo(struct azx *chip) dev_info(chip->card->dev, "Handle vga_switcheroo audio client\n"); hda->use_vga_switcheroo = 1; + chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; pci_dev_put(p); } } @@ -1320,9 +1329,6 @@ static int register_vga_switcheroo(struct azx *chip) return err; hda->vga_switcheroo_registered = 1; - /* register as an optimus hdmi audio power domain */ - vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, - &hda->hdmi_pm_domain); return 0; } #else @@ -1351,10 +1357,8 @@ static int azx_free(struct azx *chip) if (use_vga_switcheroo(hda)) { if (chip->disabled && hda->probe_continued) snd_hda_unlock_devices(&chip->bus); - if (hda->vga_switcheroo_registered) { + if (hda->vga_switcheroo_registered) vga_switcheroo_unregister_client(chip->pci); - vga_switcheroo_fini_domain_pm_ops(chip->card->dev); - } } if (bus->chip_init) { @@ -2197,6 +2201,7 @@ static int azx_probe_continue(struct azx *chip) struct hda_intel *hda = container_of(chip, struct hda_intel, chip); struct hdac_bus *bus = azx_bus(chip); struct pci_dev *pci = chip->pci; + struct hda_codec *codec; int dev = chip->dev_index; int err; @@ -2278,8 +2283,17 @@ static int azx_probe_continue(struct azx *chip) chip->running = 1; azx_add_card_list(chip); + + /* + * The discrete GPU cannot power down unless the HDA controller runtime + * suspends, so activate runtime PM on codecs even if power_save == 0. + */ + if (use_vga_switcheroo(hda)) + list_for_each_codec(codec, &chip->bus) + codec->auto_runtime_pm = 1; + snd_hda_set_power_save(&chip->bus, power_save * 1000); - if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) + if (azx_has_pm_runtime(chip)) pm_runtime_put_autosuspend(&pci->dev); out_free: diff --git a/sound/pci/hda/hda_intel.h b/sound/pci/hda/hda_intel.h index ff0c4d617bc1..e3a3d318d2e5 100644 --- a/sound/pci/hda/hda_intel.h +++ b/sound/pci/hda/hda_intel.h @@ -40,9 +40,6 @@ struct hda_intel { unsigned int vga_switcheroo_registered:1; unsigned int init_failed:1; /* delayed init failed */ - /* secondary power domain for hdmi audio under vga device */ - struct dev_pm_domain hdmi_pm_domain; - bool need_i915_power:1; /* the hda controller needs i915 power */ }; -- cgit v1.2.3 From dba0bc7b76dcf80f82f5a7542605d4abc52808f2 Mon Sep 17 00:00:00 2001 From: Derek Basehore Date: Wed, 28 Feb 2018 21:48:18 -0800 Subject: irqchip/gic-v3-its: Add ability to save/restore ITS state Some platforms power off GIC logic in suspend, so we need to save/restore state. The distributor and redistributor registers need to be handled in firmware code due to access permissions on those registers, but the ITS registers can be restored in the kernel. We limit this to systems where the ITS collections are implemented in HW (as opposed to being backed by memory tables), as they are the only ones that cannot be dealt with by the firmware. Signed-off-by: Derek Basehore [maz: fixed changelog, dropped DT property, limited to HCC being >0] Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 107 +++++++++++++++++++++++++++++++++++++ include/linux/irqchip/arm-gic-v3.h | 3 +- 2 files changed, 109 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 1d3056f53747..06682c33acba 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -46,6 +47,7 @@ #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) +#define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3) #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) @@ -101,6 +103,8 @@ struct its_node { struct its_collection *collections; struct fwnode_handle *fwnode_handle; u64 (*get_msi_base)(struct its_device *its_dev); + u64 cbaser_save; + u32 ctlr_save; struct list_head its_device_list; u64 flags; unsigned long list_nr; @@ -3042,6 +3046,104 @@ static void its_enable_quirks(struct its_node *its) gic_enable_quirks(iidr, its_quirks, its); } +static int its_save_disable(void) +{ + struct its_node *its; + int err = 0; + + spin_lock(&its_lock); + list_for_each_entry(its, &its_nodes, entry) { + void __iomem *base; + + if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) + continue; + + base = its->base; + its->ctlr_save = readl_relaxed(base + GITS_CTLR); + err = its_force_quiescent(base); + if (err) { + pr_err("ITS@%pa: failed to quiesce: %d\n", + &its->phys_base, err); + writel_relaxed(its->ctlr_save, base + GITS_CTLR); + goto err; + } + + its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); + } + +err: + if (err) { + list_for_each_entry_continue_reverse(its, &its_nodes, entry) { + void __iomem *base; + + if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) + continue; + + base = its->base; + writel_relaxed(its->ctlr_save, base + GITS_CTLR); + } + } + spin_unlock(&its_lock); + + return err; +} + +static void its_restore_enable(void) +{ + struct its_node *its; + int ret; + + spin_lock(&its_lock); + list_for_each_entry(its, &its_nodes, entry) { + void __iomem *base; + int i; + + if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE)) + continue; + + base = its->base; + + /* + * Make sure that the ITS is disabled. If it fails to quiesce, + * don't restore it since writing to CBASER or BASER + * registers is undefined according to the GIC v3 ITS + * Specification. + */ + ret = its_force_quiescent(base); + if (ret) { + pr_err("ITS@%pa: failed to quiesce on resume: %d\n", + &its->phys_base, ret); + continue; + } + + gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); + + /* + * Writing CBASER resets CREADR to 0, so make CWRITER and + * cmd_write line up with it. + */ + its->cmd_write = its->cmd_base; + gits_write_cwriter(0, base + GITS_CWRITER); + + /* Restore GITS_BASER from the value cache. */ + for (i = 0; i < GITS_BASER_NR_REGS; i++) { + struct its_baser *baser = &its->tables[i]; + + if (!(baser->val & GITS_BASER_VALID)) + continue; + + its_write_baser(its, baser, baser->val); + } + writel_relaxed(its->ctlr_save, base + GITS_CTLR); + } + spin_unlock(&its_lock); +} + +static struct syscore_ops its_syscore_ops = { + .suspend = its_save_disable, + .resume = its_restore_enable, +}; + static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) { struct irq_domain *inner_domain; @@ -3261,6 +3363,9 @@ static int __init its_probe_one(struct resource *res, ctlr |= GITS_CTLR_ImDe; writel_relaxed(ctlr, its->base + GITS_CTLR); + if (GITS_TYPER_HCC(typer)) + its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE; + err = its_init_domain(handle, its); if (err) goto out_free_tables; @@ -3517,5 +3622,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, } } + register_syscore_ops(&its_syscore_ops); + return 0; } diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c00c4c33e432..9aacea2aa938 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -312,7 +312,8 @@ #define GITS_TYPER_DEVBITS_SHIFT 13 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) #define GITS_TYPER_PTA (1UL << 19) -#define GITS_TYPER_HWCOLLCNT_SHIFT 24 +#define GITS_TYPER_HCC_SHIFT 24 +#define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) #define GITS_TYPER_VMOVP (1ULL << 37) #define GITS_IIDR_REV_SHIFT 12 -- cgit v1.2.3 From 001f86137d3fca3c9002beaa7609c666715ebc70 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Mon, 12 Mar 2018 11:24:27 -0700 Subject: EDAC: Add new memory type for non-volatile DIMMs There are now non-volatile versions of DIMMs. Add a new entry to "enum mem_type" and a new string in edac_mem_types[]. Signed-off-by: Tony Luck Cc: "Rafael J. Wysocki" Cc: Aristeu Rozanski Cc: Dan Williams Cc: Jean Delvare Cc: Len Brown Cc: Mauro Carvalho Chehab Cc: Qiuxu Zhuo Cc: linux-acpi@vger.kernel.org Cc: linux-edac Cc: linux-nvdimm@lists.01.org Link: http://lkml.kernel.org/r/20180312182430.10335-3-tony.luck@intel.com Signed-off-by: Borislav Petkov --- drivers/edac/edac_mc.c | 3 ++- include/linux/edac.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 1f61b736e075..3bb82e511eca 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -214,7 +214,8 @@ const char * const edac_mem_types[] = { [MEM_RDDR3] = "Registered-DDR3", [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM", [MEM_DDR4] = "Unbuffered-DDR4", - [MEM_RDDR4] = "Registered-DDR4" + [MEM_RDDR4] = "Registered-DDR4", + [MEM_NVDIMM] = "Non-volatile-RAM", }; EXPORT_SYMBOL_GPL(edac_mem_types); diff --git a/include/linux/edac.h b/include/linux/edac.h index cd75c173fd00..bffb97828ed6 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -186,6 +186,7 @@ static inline char *mc_event_error_type(const unsigned int err_type) * @MEM_RDDR4: Registered DDR4 RAM * This is a variant of the DDR4 memories. * @MEM_LRDDR4: Load-Reduced DDR4 memory. + * @MEM_NVDIMM: Non-volatile RAM */ enum mem_type { MEM_EMPTY = 0, @@ -209,6 +210,7 @@ enum mem_type { MEM_DDR4, MEM_RDDR4, MEM_LRDDR4, + MEM_NVDIMM, }; #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) @@ -231,6 +233,7 @@ enum mem_type { #define MEM_FLAG_DDR4 BIT(MEM_DDR4) #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4) #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4) +#define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM) /** * enum edac-type - Error Detection and Correction capabilities and mode -- cgit v1.2.3 From 6deae96b42eb1fa84938088087de0bd748f53093 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Mon, 12 Mar 2018 11:24:29 -0700 Subject: firmware, DMI: Add function to look up a handle and return DIMM size When we first scan the SMBIOS table, save the size of the DIMM. Provide a function for other code (EDAC driver) to look up the size of a DIMM from its SMBIOS handle. Reviewed-by: Jean Delvare Signed-off-by: Tony Luck Cc: Aristeu Rozanski Cc: Dan Williams Cc: Len Brown Cc: Mauro Carvalho Chehab Cc: Qiuxu Zhuo Cc: "Rafael J. Wysocki" Cc: linux-acpi@vger.kernel.org Cc: linux-nvdimm@lists.01.org Link: http://lkml.kernel.org/r/20180312182430.10335-5-tony.luck@intel.com Signed-off-by: Borislav Petkov --- drivers/firmware/dmi_scan.c | 31 +++++++++++++++++++++++++++++++ include/linux/dmi.h | 2 ++ 2 files changed, 33 insertions(+) (limited to 'include/linux') diff --git a/drivers/firmware/dmi_scan.c b/drivers/firmware/dmi_scan.c index e763e1484331..35c6c74c9304 100644 --- a/drivers/firmware/dmi_scan.c +++ b/drivers/firmware/dmi_scan.c @@ -32,6 +32,7 @@ static char dmi_ids_string[128] __initdata; static struct dmi_memdev_info { const char *device; const char *bank; + u64 size; /* bytes */ u16 handle; } *dmi_memdev; static int dmi_memdev_nr; @@ -386,6 +387,8 @@ static void __init save_mem_devices(const struct dmi_header *dm, void *v) { const char *d = (const char *)dm; static int nr; + u64 bytes; + u16 size; if (dm->type != DMI_ENTRY_MEM_DEVICE || dm->length < 0x12) return; @@ -396,6 +399,20 @@ static void __init save_mem_devices(const struct dmi_header *dm, void *v) dmi_memdev[nr].handle = get_unaligned(&dm->handle); dmi_memdev[nr].device = dmi_string(dm, d[0x10]); dmi_memdev[nr].bank = dmi_string(dm, d[0x11]); + + size = get_unaligned((u16 *)&d[0xC]); + if (size == 0) + bytes = 0; + else if (size == 0xffff) + bytes = ~0ull; + else if (size & 0x8000) + bytes = (u64)(size & 0x7fff) << 10; + else if (size != 0x7fff) + bytes = (u64)size << 20; + else + bytes = (u64)get_unaligned((u32 *)&d[0x1C]) << 20; + + dmi_memdev[nr].size = bytes; nr++; } @@ -1065,3 +1082,17 @@ void dmi_memdev_name(u16 handle, const char **bank, const char **device) } } EXPORT_SYMBOL_GPL(dmi_memdev_name); + +u64 dmi_memdev_size(u16 handle) +{ + int n; + + if (dmi_memdev) { + for (n = 0; n < dmi_memdev_nr; n++) { + if (handle == dmi_memdev[n].handle) + return dmi_memdev[n].size; + } + } + return ~0ull; +} +EXPORT_SYMBOL_GPL(dmi_memdev_size); diff --git a/include/linux/dmi.h b/include/linux/dmi.h index 46e151172d95..7f5929123b69 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -113,6 +113,7 @@ extern int dmi_walk(void (*decode)(const struct dmi_header *, void *), void *private_data); extern bool dmi_match(enum dmi_field f, const char *str); extern void dmi_memdev_name(u16 handle, const char **bank, const char **device); +extern u64 dmi_memdev_size(u16 handle); #else @@ -142,6 +143,7 @@ static inline bool dmi_match(enum dmi_field f, const char *str) { return false; } static inline void dmi_memdev_name(u16 handle, const char **bank, const char **device) { } +static inline u64 dmi_memdev_size(u16 handle) { return ~0ul; } static inline const struct dmi_system_id * dmi_first_match(const struct dmi_system_id *list) { return NULL; } -- cgit v1.2.3 From 9c692d5ae7ea84d221d7504b7ebef07ea8f3ff27 Mon Sep 17 00:00:00 2001 From: Bogdan Purcareata Date: Fri, 2 Mar 2018 04:23:58 -0600 Subject: staging: fsl-mc: Move DPBP out of staging Move the source files out of staging into their final locations: - dpbp.c goes to drivers/bus/fsl-mc/, next to the core infrastructure - dpbp-cmd.h gets merged into drivers/bus/fsl-mc/fsl-mc-private.h, next to the other internally used APIs - dpbp.h gets merged into include/linux/fsl/mc.h, exposing the public API Update references in the dpaa2-eth staging driver. DPBP stands for Data Path Buffer Pool - you can read more about the object in Documentation/networking/dpaa2/overview.rst Signed-off-by: Bogdan Purcareata Reviewed-by: Laurentiu Tudor Signed-off-by: Greg Kroah-Hartman --- drivers/bus/fsl-mc/Makefile | 1 + drivers/bus/fsl-mc/dpbp.c | 186 +++++++++++++++++++++++++ drivers/bus/fsl-mc/fsl-mc-private.h | 39 ++++++ drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h | 2 +- drivers/staging/fsl-mc/bus/Makefile | 3 +- drivers/staging/fsl-mc/bus/dpbp-cmd.h | 44 ------ drivers/staging/fsl-mc/bus/dpbp.c | 186 ------------------------- drivers/staging/fsl-mc/include/dpbp.h | 53 ------- include/linux/fsl/mc.h | 42 ++++++ 9 files changed, 270 insertions(+), 286 deletions(-) create mode 100644 drivers/bus/fsl-mc/dpbp.c delete mode 100644 drivers/staging/fsl-mc/bus/dpbp-cmd.h delete mode 100644 drivers/staging/fsl-mc/bus/dpbp.c delete mode 100644 drivers/staging/fsl-mc/include/dpbp.h (limited to 'include/linux') diff --git a/drivers/bus/fsl-mc/Makefile b/drivers/bus/fsl-mc/Makefile index 6a97f2c3a065..da26e529baf1 100644 --- a/drivers/bus/fsl-mc/Makefile +++ b/drivers/bus/fsl-mc/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o mc-bus-driver-objs := fsl-mc-bus.o \ mc-sys.o \ mc-io.o \ + dpbp.o \ dprc.o \ dprc-driver.o \ fsl-mc-allocator.o \ diff --git a/drivers/bus/fsl-mc/dpbp.c b/drivers/bus/fsl-mc/dpbp.c new file mode 100644 index 000000000000..0aeacc5bf461 --- /dev/null +++ b/drivers/bus/fsl-mc/dpbp.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2013-2016 Freescale Semiconductor Inc. + * + */ +#include +#include +#include + +#include "fsl-mc-private.h" + +/** + * dpbp_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpbp_id: DPBP unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpbp_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int dpbp_id, + u16 *token) +{ + struct mc_command cmd = { 0 }; + struct dpbp_cmd_open *cmd_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN, + cmd_flags, 0); + cmd_params = (struct dpbp_cmd_open *)cmd.params; + cmd_params->dpbp_id = cpu_to_le32(dpbp_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return err; +} +EXPORT_SYMBOL_GPL(dpbp_open); + +/** + * dpbp_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpbp_close); + +/** + * dpbp_enable() - Enable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpbp_enable); + +/** + * dpbp_disable() - Disable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_disable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpbp_disable); + +/** + * dpbp_reset() - Reset the DPBP, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_reset(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpbp_reset); + +/** + * dpbp_get_attributes - Retrieve DPBP attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_attributes(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dpbp_attr *attr) +{ + struct mc_command cmd = { 0 }; + struct dpbp_rsp_get_attributes *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR, + cmd_flags, token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params; + attr->bpid = le16_to_cpu(rsp_params->bpid); + attr->id = le32_to_cpu(rsp_params->id); + + return 0; +} +EXPORT_SYMBOL_GPL(dpbp_get_attributes); diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h index bed990c517f3..4ef8d7e078fb 100644 --- a/drivers/bus/fsl-mc/fsl-mc-private.h +++ b/drivers/bus/fsl-mc/fsl-mc-private.h @@ -379,6 +379,45 @@ int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id); +/* + * Data Path Buffer Pool (DPBP) API + */ + +/* DPBP Version */ +#define DPBP_VER_MAJOR 3 +#define DPBP_VER_MINOR 2 + +/* Command versioning */ +#define DPBP_CMD_BASE_VERSION 1 +#define DPBP_CMD_ID_OFFSET 4 + +#define DPBP_CMD(id) (((id) << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION) + +/* Command IDs */ +#define DPBP_CMDID_CLOSE DPBP_CMD(0x800) +#define DPBP_CMDID_OPEN DPBP_CMD(0x804) + +#define DPBP_CMDID_ENABLE DPBP_CMD(0x002) +#define DPBP_CMDID_DISABLE DPBP_CMD(0x003) +#define DPBP_CMDID_GET_ATTR DPBP_CMD(0x004) +#define DPBP_CMDID_RESET DPBP_CMD(0x005) + +struct dpbp_cmd_open { + __le32 dpbp_id; +}; + +#define DPBP_ENABLE 0x1 + +struct dpbp_rsp_get_attributes { + /* response word 0 */ + __le16 pad; + __le16 bpid; + __le32 id; + /* response word 1 */ + __le16 version_major; + __le16 version_minor; +}; + /** * Maximum number of total IRQs that can be pre-allocated for an MC bus' * IRQ pool diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h index e577410fdf4f..ce864eede95c 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h @@ -35,10 +35,10 @@ #include #include +#include #include "../../fsl-mc/include/dpaa2-io.h" #include "../../fsl-mc/include/dpaa2-fd.h" -#include "../../fsl-mc/include/dpbp.h" #include "../../fsl-mc/include/dpcon.h" #include "dpni.h" #include "dpni-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/Makefile b/drivers/staging/fsl-mc/bus/Makefile index b67889ecbe5c..ea6479f65410 100644 --- a/drivers/staging/fsl-mc/bus/Makefile +++ b/drivers/staging/fsl-mc/bus/Makefile @@ -4,8 +4,7 @@ # # Copyright (C) 2014 Freescale Semiconductor, Inc. # -obj-$(CONFIG_FSL_MC_BUS) += dpbp.o \ - dpcon.o +obj-$(CONFIG_FSL_MC_BUS) += dpcon.o # MC DPIO driver obj-$(CONFIG_FSL_MC_DPIO) += dpio/ diff --git a/drivers/staging/fsl-mc/bus/dpbp-cmd.h b/drivers/staging/fsl-mc/bus/dpbp-cmd.h deleted file mode 100644 index 334002144e20..000000000000 --- a/drivers/staging/fsl-mc/bus/dpbp-cmd.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#ifndef _FSL_DPBP_CMD_H -#define _FSL_DPBP_CMD_H - -/* DPBP Version */ -#define DPBP_VER_MAJOR 3 -#define DPBP_VER_MINOR 2 - -/* Command versioning */ -#define DPBP_CMD_BASE_VERSION 1 -#define DPBP_CMD_ID_OFFSET 4 - -#define DPBP_CMD(id) (((id) << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION) - -/* Command IDs */ -#define DPBP_CMDID_CLOSE DPBP_CMD(0x800) -#define DPBP_CMDID_OPEN DPBP_CMD(0x804) - -#define DPBP_CMDID_ENABLE DPBP_CMD(0x002) -#define DPBP_CMDID_DISABLE DPBP_CMD(0x003) -#define DPBP_CMDID_GET_ATTR DPBP_CMD(0x004) -#define DPBP_CMDID_RESET DPBP_CMD(0x005) - -struct dpbp_cmd_open { - __le32 dpbp_id; -}; - -#define DPBP_ENABLE 0x1 - -struct dpbp_rsp_get_attributes { - /* response word 0 */ - __le16 pad; - __le16 bpid; - __le32 id; - /* response word 1 */ - __le16 version_major; - __le16 version_minor; -}; - -#endif /* _FSL_DPBP_CMD_H */ diff --git a/drivers/staging/fsl-mc/bus/dpbp.c b/drivers/staging/fsl-mc/bus/dpbp.c deleted file mode 100644 index 85735bb15930..000000000000 --- a/drivers/staging/fsl-mc/bus/dpbp.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#include -#include -#include "../include/dpbp.h" - -#include "dpbp-cmd.h" - -/** - * dpbp_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpbp_id: DPBP unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpbp_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int dpbp_id, - u16 *token) -{ - struct mc_command cmd = { 0 }; - struct dpbp_cmd_open *cmd_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN, - cmd_flags, 0); - cmd_params = (struct dpbp_cmd_open *)cmd.params; - cmd_params->dpbp_id = cpu_to_le32(dpbp_id); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - *token = mc_cmd_hdr_read_token(&cmd); - - return err; -} -EXPORT_SYMBOL_GPL(dpbp_open); - -/** - * dpbp_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpbp_close); - -/** - * dpbp_enable() - Enable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_enable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpbp_enable); - -/** - * dpbp_disable() - Disable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_disable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE, - cmd_flags, token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpbp_disable); - -/** - * dpbp_reset() - Reset the DPBP, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_reset(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET, - cmd_flags, token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpbp_reset); - -/** - * dpbp_get_attributes - Retrieve DPBP attributes. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_get_attributes(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dpbp_attr *attr) -{ - struct mc_command cmd = { 0 }; - struct dpbp_rsp_get_attributes *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR, - cmd_flags, token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params; - attr->bpid = le16_to_cpu(rsp_params->bpid); - attr->id = le32_to_cpu(rsp_params->id); - - return 0; -} -EXPORT_SYMBOL_GPL(dpbp_get_attributes); diff --git a/drivers/staging/fsl-mc/include/dpbp.h b/drivers/staging/fsl-mc/include/dpbp.h deleted file mode 100644 index 7b9f7ad5e925..000000000000 --- a/drivers/staging/fsl-mc/include/dpbp.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#ifndef __FSL_DPBP_H -#define __FSL_DPBP_H - -/* - * Data Path Buffer Pool API - * Contains initialization APIs and runtime control APIs for DPBP - */ - -struct fsl_mc_io; - -int dpbp_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int dpbp_id, - u16 *token); - -int dpbp_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -int dpbp_enable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -int dpbp_disable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -int dpbp_reset(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/** - * struct dpbp_attr - Structure representing DPBP attributes - * @id: DPBP object ID - * @bpid: Hardware buffer pool ID; should be used as an argument in - * acquire/release operations on buffers - */ -struct dpbp_attr { - int id; - u16 bpid; -}; - -int dpbp_get_attributes(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dpbp_attr *attr); - -#endif /* __FSL_DPBP_H */ diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h index 765ba41f5987..66118e1fb5b9 100644 --- a/include/linux/fsl/mc.h +++ b/include/linux/fsl/mc.h @@ -451,4 +451,46 @@ static inline bool is_fsl_mc_bus_dprtc(const struct fsl_mc_device *mc_dev) return mc_dev->dev.type == &fsl_mc_bus_dprtc_type; } +/* + * Data Path Buffer Pool (DPBP) API + * Contains initialization APIs and runtime control APIs for DPBP + */ + +int dpbp_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int dpbp_id, + u16 *token); + +int dpbp_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +int dpbp_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +int dpbp_disable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +int dpbp_reset(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +/** + * struct dpbp_attr - Structure representing DPBP attributes + * @id: DPBP object ID + * @bpid: Hardware buffer pool ID; should be used as an argument in + * acquire/release operations on buffers + */ +struct dpbp_attr { + int id; + u16 bpid; +}; + +int dpbp_get_attributes(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dpbp_attr *attr); + #endif /* _FSL_MC_H_ */ -- cgit v1.2.3 From 70ae9cf015a165c33b63c9c7718f5a3c70e51f96 Mon Sep 17 00:00:00 2001 From: Bogdan Purcareata Date: Fri, 2 Mar 2018 04:23:59 -0600 Subject: staging: fsl-mc: Move DPCON out of staging Move the source files out of staging into their final locations: - dpcon.c goes to drivers/bus/fsl-mc/, next to the core infrastructure - dpcon-cmd.h gets merged into drivers/bus/fsl-mc/fsl-mc-private.h, next to the other internally used APIs - dpcon.h gets merged into include/linux/fsl/mc.h, exposing the public API Update references in the dpaa2-eth staging driver. DPCON stands for Data Path Concentrator - an interface between DPIO (Data Path IO) and its users (e.g. dpaa2-eth). You can read more about DPIO in Documentation/networking/dpaa2/overview.rst Signed-off-by: Bogdan Purcareata Reviewed-by: Laurentiu Tudor Signed-off-by: Greg Kroah-Hartman --- drivers/bus/fsl-mc/Makefile | 1 + drivers/bus/fsl-mc/dpcon.c | 222 +++++++++++++++++++++++++ drivers/bus/fsl-mc/fsl-mc-private.h | 48 ++++++ drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h | 1 - drivers/staging/fsl-mc/bus/Makefile | 1 - drivers/staging/fsl-mc/bus/dpcon-cmd.h | 53 ------ drivers/staging/fsl-mc/bus/dpcon.c | 222 ------------------------- drivers/staging/fsl-mc/include/dpcon.h | 79 --------- include/linux/fsl/mc.h | 66 ++++++++ 9 files changed, 337 insertions(+), 356 deletions(-) create mode 100644 drivers/bus/fsl-mc/dpcon.c delete mode 100644 drivers/staging/fsl-mc/bus/dpcon-cmd.h delete mode 100644 drivers/staging/fsl-mc/bus/dpcon.c delete mode 100644 drivers/staging/fsl-mc/include/dpcon.h (limited to 'include/linux') diff --git a/drivers/bus/fsl-mc/Makefile b/drivers/bus/fsl-mc/Makefile index da26e529baf1..3c518c7e8374 100644 --- a/drivers/bus/fsl-mc/Makefile +++ b/drivers/bus/fsl-mc/Makefile @@ -10,6 +10,7 @@ mc-bus-driver-objs := fsl-mc-bus.o \ mc-sys.o \ mc-io.o \ dpbp.o \ + dpcon.o \ dprc.o \ dprc-driver.o \ fsl-mc-allocator.o \ diff --git a/drivers/bus/fsl-mc/dpcon.c b/drivers/bus/fsl-mc/dpcon.c new file mode 100644 index 000000000000..a1ba819449d5 --- /dev/null +++ b/drivers/bus/fsl-mc/dpcon.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2013-2016 Freescale Semiconductor Inc. + * + */ +#include +#include +#include + +#include "fsl-mc-private.h" + +/** + * dpcon_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpcon_id: DPCON unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpcon_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpcon_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int dpcon_id, + u16 *token) +{ + struct mc_command cmd = { 0 }; + struct dpcon_cmd_open *dpcon_cmd; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN, + cmd_flags, + 0); + dpcon_cmd = (struct dpcon_cmd_open *)cmd.params; + dpcon_cmd->dpcon_id = cpu_to_le32(dpcon_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + *token = mc_cmd_hdr_read_token(&cmd); + + return 0; +} +EXPORT_SYMBOL_GPL(dpcon_open); + +/** + * dpcon_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCON object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpcon_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpcon_close); + +/** + * dpcon_enable() - Enable the DPCON + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCON object + * + * Return: '0' on Success; Error code otherwise + */ +int dpcon_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpcon_enable); + +/** + * dpcon_disable() - Disable the DPCON + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCON object + * + * Return: '0' on Success; Error code otherwise + */ +int dpcon_disable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE, + cmd_flags, + token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpcon_disable); + +/** + * dpcon_reset() - Reset the DPCON, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCON object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpcon_reset(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET, + cmd_flags, token); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpcon_reset); + +/** + * dpcon_get_attributes() - Retrieve DPCON attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCON object + * @attr: Object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpcon_get_attributes(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dpcon_attr *attr) +{ + struct mc_command cmd = { 0 }; + struct dpcon_rsp_get_attr *dpcon_rsp; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR, + cmd_flags, + token); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + dpcon_rsp = (struct dpcon_rsp_get_attr *)cmd.params; + attr->id = le32_to_cpu(dpcon_rsp->id); + attr->qbman_ch_id = le16_to_cpu(dpcon_rsp->qbman_ch_id); + attr->num_priorities = dpcon_rsp->num_priorities; + + return 0; +} +EXPORT_SYMBOL_GPL(dpcon_get_attributes); + +/** + * dpcon_set_notification() - Set DPCON notification destination + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCON object + * @cfg: Notification parameters + * + * Return: '0' on Success; Error code otherwise + */ +int dpcon_set_notification(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dpcon_notification_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + struct dpcon_cmd_set_notification *dpcon_cmd; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION, + cmd_flags, + token); + dpcon_cmd = (struct dpcon_cmd_set_notification *)cmd.params; + dpcon_cmd->dpio_id = cpu_to_le32(cfg->dpio_id); + dpcon_cmd->priority = cfg->priority; + dpcon_cmd->user_ctx = cpu_to_le64(cfg->user_ctx); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} +EXPORT_SYMBOL_GPL(dpcon_set_notification); diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h index 4ef8d7e078fb..52c069d28547 100644 --- a/drivers/bus/fsl-mc/fsl-mc-private.h +++ b/drivers/bus/fsl-mc/fsl-mc-private.h @@ -418,6 +418,54 @@ struct dpbp_rsp_get_attributes { __le16 version_minor; }; +/* + * Data Path Concentrator (DPCON) API + */ + +/* DPCON Version */ +#define DPCON_VER_MAJOR 3 +#define DPCON_VER_MINOR 2 + +/* Command versioning */ +#define DPCON_CMD_BASE_VERSION 1 +#define DPCON_CMD_ID_OFFSET 4 + +#define DPCON_CMD(id) (((id) << DPCON_CMD_ID_OFFSET) | DPCON_CMD_BASE_VERSION) + +/* Command IDs */ +#define DPCON_CMDID_CLOSE DPCON_CMD(0x800) +#define DPCON_CMDID_OPEN DPCON_CMD(0x808) + +#define DPCON_CMDID_ENABLE DPCON_CMD(0x002) +#define DPCON_CMDID_DISABLE DPCON_CMD(0x003) +#define DPCON_CMDID_GET_ATTR DPCON_CMD(0x004) +#define DPCON_CMDID_RESET DPCON_CMD(0x005) + +#define DPCON_CMDID_SET_NOTIFICATION DPCON_CMD(0x100) + +struct dpcon_cmd_open { + __le32 dpcon_id; +}; + +#define DPCON_ENABLE 1 + +struct dpcon_rsp_get_attr { + /* response word 0 */ + __le32 id; + __le16 qbman_ch_id; + u8 num_priorities; + u8 pad; +}; + +struct dpcon_cmd_set_notification { + /* cmd word 0 */ + __le32 dpio_id; + u8 priority; + u8 pad[3]; + /* cmd word 1 */ + __le64 user_ctx; +}; + /** * Maximum number of total IRQs that can be pre-allocated for an MC bus' * IRQ pool diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h index ce864eede95c..b8990cf62915 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h @@ -39,7 +39,6 @@ #include "../../fsl-mc/include/dpaa2-io.h" #include "../../fsl-mc/include/dpaa2-fd.h" -#include "../../fsl-mc/include/dpcon.h" #include "dpni.h" #include "dpni-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/Makefile b/drivers/staging/fsl-mc/bus/Makefile index ea6479f65410..21d8ebc8ce21 100644 --- a/drivers/staging/fsl-mc/bus/Makefile +++ b/drivers/staging/fsl-mc/bus/Makefile @@ -4,7 +4,6 @@ # # Copyright (C) 2014 Freescale Semiconductor, Inc. # -obj-$(CONFIG_FSL_MC_BUS) += dpcon.o # MC DPIO driver obj-$(CONFIG_FSL_MC_DPIO) += dpio/ diff --git a/drivers/staging/fsl-mc/bus/dpcon-cmd.h b/drivers/staging/fsl-mc/bus/dpcon-cmd.h deleted file mode 100644 index 27fa09877970..000000000000 --- a/drivers/staging/fsl-mc/bus/dpcon-cmd.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#ifndef _FSL_DPCON_CMD_H -#define _FSL_DPCON_CMD_H - -/* DPCON Version */ -#define DPCON_VER_MAJOR 3 -#define DPCON_VER_MINOR 2 - -/* Command versioning */ -#define DPCON_CMD_BASE_VERSION 1 -#define DPCON_CMD_ID_OFFSET 4 - -#define DPCON_CMD(id) (((id) << DPCON_CMD_ID_OFFSET) | DPCON_CMD_BASE_VERSION) - -/* Command IDs */ -#define DPCON_CMDID_CLOSE DPCON_CMD(0x800) -#define DPCON_CMDID_OPEN DPCON_CMD(0x808) - -#define DPCON_CMDID_ENABLE DPCON_CMD(0x002) -#define DPCON_CMDID_DISABLE DPCON_CMD(0x003) -#define DPCON_CMDID_GET_ATTR DPCON_CMD(0x004) -#define DPCON_CMDID_RESET DPCON_CMD(0x005) - -#define DPCON_CMDID_SET_NOTIFICATION DPCON_CMD(0x100) - -struct dpcon_cmd_open { - __le32 dpcon_id; -}; - -#define DPCON_ENABLE 1 - -struct dpcon_rsp_get_attr { - /* response word 0 */ - __le32 id; - __le16 qbman_ch_id; - u8 num_priorities; - u8 pad; -}; - -struct dpcon_cmd_set_notification { - /* cmd word 0 */ - __le32 dpio_id; - u8 priority; - u8 pad[3]; - /* cmd word 1 */ - __le64 user_ctx; -}; - -#endif /* _FSL_DPCON_CMD_H */ diff --git a/drivers/staging/fsl-mc/bus/dpcon.c b/drivers/staging/fsl-mc/bus/dpcon.c deleted file mode 100644 index 021b4252eba0..000000000000 --- a/drivers/staging/fsl-mc/bus/dpcon.c +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#include -#include -#include "../include/dpcon.h" - -#include "dpcon-cmd.h" - -/** - * dpcon_open() - Open a control session for the specified object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpcon_id: DPCON unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpcon_create() function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpcon_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int dpcon_id, - u16 *token) -{ - struct mc_command cmd = { 0 }; - struct dpcon_cmd_open *dpcon_cmd; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN, - cmd_flags, - 0); - dpcon_cmd = (struct dpcon_cmd_open *)cmd.params; - dpcon_cmd->dpcon_id = cpu_to_le32(dpcon_id); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - *token = mc_cmd_hdr_read_token(&cmd); - - return 0; -} -EXPORT_SYMBOL_GPL(dpcon_open); - -/** - * dpcon_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPCON object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpcon_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE, - cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpcon_close); - -/** - * dpcon_enable() - Enable the DPCON - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPCON object - * - * Return: '0' on Success; Error code otherwise - */ -int dpcon_enable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE, - cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpcon_enable); - -/** - * dpcon_disable() - Disable the DPCON - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPCON object - * - * Return: '0' on Success; Error code otherwise - */ -int dpcon_disable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE, - cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpcon_disable); - -/** - * dpcon_reset() - Reset the DPCON, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPCON object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpcon_reset(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET, - cmd_flags, token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpcon_reset); - -/** - * dpcon_get_attributes() - Retrieve DPCON attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPCON object - * @attr: Object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpcon_get_attributes(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dpcon_attr *attr) -{ - struct mc_command cmd = { 0 }; - struct dpcon_rsp_get_attr *dpcon_rsp; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - dpcon_rsp = (struct dpcon_rsp_get_attr *)cmd.params; - attr->id = le32_to_cpu(dpcon_rsp->id); - attr->qbman_ch_id = le16_to_cpu(dpcon_rsp->qbman_ch_id); - attr->num_priorities = dpcon_rsp->num_priorities; - - return 0; -} -EXPORT_SYMBOL_GPL(dpcon_get_attributes); - -/** - * dpcon_set_notification() - Set DPCON notification destination - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPCON object - * @cfg: Notification parameters - * - * Return: '0' on Success; Error code otherwise - */ -int dpcon_set_notification(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dpcon_notification_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - struct dpcon_cmd_set_notification *dpcon_cmd; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION, - cmd_flags, - token); - dpcon_cmd = (struct dpcon_cmd_set_notification *)cmd.params; - dpcon_cmd->dpio_id = cpu_to_le32(cfg->dpio_id); - dpcon_cmd->priority = cfg->priority; - dpcon_cmd->user_ctx = cpu_to_le64(cfg->user_ctx); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} -EXPORT_SYMBOL_GPL(dpcon_set_notification); diff --git a/drivers/staging/fsl-mc/include/dpcon.h b/drivers/staging/fsl-mc/include/dpcon.h deleted file mode 100644 index 062e90ad929b..000000000000 --- a/drivers/staging/fsl-mc/include/dpcon.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - */ -#ifndef __FSL_DPCON_H -#define __FSL_DPCON_H - -/* Data Path Concentrator API - * Contains initialization APIs and runtime control APIs for DPCON - */ - -struct fsl_mc_io; - -/** General DPCON macros */ - -/** - * Use it to disable notifications; see dpcon_set_notification() - */ -#define DPCON_INVALID_DPIO_ID (int)(-1) - -int dpcon_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - int dpcon_id, - u16 *token); - -int dpcon_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -int dpcon_enable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -int dpcon_disable(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -int dpcon_reset(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/** - * struct dpcon_attr - Structure representing DPCON attributes - * @id: DPCON object ID - * @qbman_ch_id: Channel ID to be used by dequeue operation - * @num_priorities: Number of priorities for the DPCON channel (1-8) - */ -struct dpcon_attr { - int id; - u16 qbman_ch_id; - u8 num_priorities; -}; - -int dpcon_get_attributes(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dpcon_attr *attr); - -/** - * struct dpcon_notification_cfg - Structure representing notification params - * @dpio_id: DPIO object ID; must be configured with a notification channel; - * to disable notifications set it to 'DPCON_INVALID_DPIO_ID'; - * @priority: Priority selection within the DPIO channel; valid values - * are 0-7, depending on the number of priorities in that channel - * @user_ctx: User context value provided with each CDAN message - */ -struct dpcon_notification_cfg { - int dpio_id; - u8 priority; - u64 user_ctx; -}; - -int dpcon_set_notification(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - struct dpcon_notification_cfg *cfg); - -#endif /* __FSL_DPCON_H */ diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h index 66118e1fb5b9..cfb1fbf3a882 100644 --- a/include/linux/fsl/mc.h +++ b/include/linux/fsl/mc.h @@ -493,4 +493,70 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io, u16 token, struct dpbp_attr *attr); +/* Data Path Concentrator (DPCON) API + * Contains initialization APIs and runtime control APIs for DPCON + */ + +/** + * Use it to disable notifications; see dpcon_set_notification() + */ +#define DPCON_INVALID_DPIO_ID (int)(-1) + +int dpcon_open(struct fsl_mc_io *mc_io, + u32 cmd_flags, + int dpcon_id, + u16 *token); + +int dpcon_close(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +int dpcon_enable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +int dpcon_disable(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +int dpcon_reset(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token); + +/** + * struct dpcon_attr - Structure representing DPCON attributes + * @id: DPCON object ID + * @qbman_ch_id: Channel ID to be used by dequeue operation + * @num_priorities: Number of priorities for the DPCON channel (1-8) + */ +struct dpcon_attr { + int id; + u16 qbman_ch_id; + u8 num_priorities; +}; + +int dpcon_get_attributes(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dpcon_attr *attr); + +/** + * struct dpcon_notification_cfg - Structure representing notification params + * @dpio_id: DPIO object ID; must be configured with a notification channel; + * to disable notifications set it to 'DPCON_INVALID_DPIO_ID'; + * @priority: Priority selection within the DPIO channel; valid values + * are 0-7, depending on the number of priorities in that channel + * @user_ctx: User context value provided with each CDAN message + */ +struct dpcon_notification_cfg { + int dpio_id; + u8 priority; + u64 user_ctx; +}; + +int dpcon_set_notification(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 token, + struct dpcon_notification_cfg *cfg); + #endif /* _FSL_MC_H_ */ -- cgit v1.2.3 From 4dcb31d4649df36297296b819437709f5407059c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 14 Mar 2018 09:04:16 -0700 Subject: net: use skb_to_full_sk() in skb_update_prio() Andrei Vagin reported a KASAN: slab-out-of-bounds error in skb_update_prio() Since SYNACK might be attached to a request socket, we need to get back to the listener socket. Since this listener is manipulated without locks, add const qualifiers to sock_cgroup_prioidx() so that the const can also be used in skb_update_prio() Also add the const qualifier to sock_cgroup_classid() for consistency. Fixes: ca6fb0651883 ("tcp: attach SYNACK messages to request sockets instead of listener") Signed-off-by: Eric Dumazet Reported-by: Andrei Vagin Signed-off-by: David S. Miller --- include/linux/cgroup-defs.h | 4 ++-- net/core/dev.c | 22 +++++++++++++++------- 2 files changed, 17 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/include/linux/cgroup-defs.h b/include/linux/cgroup-defs.h index 9f242b876fde..f8e76d01a5ad 100644 --- a/include/linux/cgroup-defs.h +++ b/include/linux/cgroup-defs.h @@ -755,13 +755,13 @@ struct sock_cgroup_data { * updaters and return part of the previous pointer as the prioidx or * classid. Such races are short-lived and the result isn't critical. */ -static inline u16 sock_cgroup_prioidx(struct sock_cgroup_data *skcd) +static inline u16 sock_cgroup_prioidx(const struct sock_cgroup_data *skcd) { /* fallback to 1 which is always the ID of the root cgroup */ return (skcd->is_data & 1) ? skcd->prioidx : 1; } -static inline u32 sock_cgroup_classid(struct sock_cgroup_data *skcd) +static inline u32 sock_cgroup_classid(const struct sock_cgroup_data *skcd) { /* fallback to 0 which is the unconfigured default classid */ return (skcd->is_data & 1) ? skcd->classid : 0; diff --git a/net/core/dev.c b/net/core/dev.c index 2cedf520cb28..12be20535714 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -3278,15 +3278,23 @@ static inline int __dev_xmit_skb(struct sk_buff *skb, struct Qdisc *q, #if IS_ENABLED(CONFIG_CGROUP_NET_PRIO) static void skb_update_prio(struct sk_buff *skb) { - struct netprio_map *map = rcu_dereference_bh(skb->dev->priomap); + const struct netprio_map *map; + const struct sock *sk; + unsigned int prioidx; - if (!skb->priority && skb->sk && map) { - unsigned int prioidx = - sock_cgroup_prioidx(&skb->sk->sk_cgrp_data); + if (skb->priority) + return; + map = rcu_dereference_bh(skb->dev->priomap); + if (!map) + return; + sk = skb_to_full_sk(skb); + if (!sk) + return; - if (prioidx < map->priomap_len) - skb->priority = map->priomap[prioidx]; - } + prioidx = sock_cgroup_prioidx(&sk->sk_cgrp_data); + + if (prioidx < map->priomap_len) + skb->priority = map->priomap[prioidx]; } #else #define skb_update_prio(skb) -- cgit v1.2.3 From 83fc580dcc2f0f36114477c4ac7adbe5c32329a3 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Thu, 8 Mar 2018 16:03:27 -0800 Subject: Input: gpio-keys - add support for wakeup event action Add support for specifying event actions to trigger wakeup when using the gpio-keys input device as a wakeup source. This would allow the device to configure when to wakeup the system. For example a gpio-keys input device for pen insert, may only want to wakeup the system when ejecting the pen. Suggested-by: Brian Norris Signed-off-by: Jeffy Chen Reviewed-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/gpio-keys.txt | 8 ++ drivers/input/keyboard/gpio_keys.c | 145 +++++++++++++++++++-- include/dt-bindings/input/gpio-keys.h | 13 ++ include/linux/gpio_keys.h | 2 + 4 files changed, 154 insertions(+), 14 deletions(-) create mode 100644 include/dt-bindings/input/gpio-keys.h (limited to 'include/linux') diff --git a/Documentation/devicetree/bindings/input/gpio-keys.txt b/Documentation/devicetree/bindings/input/gpio-keys.txt index a94940481e55..996ce84352cb 100644 --- a/Documentation/devicetree/bindings/input/gpio-keys.txt +++ b/Documentation/devicetree/bindings/input/gpio-keys.txt @@ -26,6 +26,14 @@ Optional subnode-properties: If not specified defaults to 5. - wakeup-source: Boolean, button can wake-up the system. (Legacy property supported: "gpio-key,wakeup") + - wakeup-event-action: Specifies whether the key should wake the + system when asserted, when deasserted, or both. This property is + only valid for keys that wake up the system (e.g., when the + "wakeup-source" property is also provided). + Supported values are defined in linux-event-codes.h: + EV_ACT_ASSERTED - asserted + EV_ACT_DEASSERTED - deasserted + EV_ACT_ANY - both asserted and deasserted - linux,can-disable: Boolean, indicates that button is connected to dedicated (not shared) interrupt which can be disabled to suppress events from the button. diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c index 87e613dc33b8..052e37675086 100644 --- a/drivers/input/keyboard/gpio_keys.c +++ b/drivers/input/keyboard/gpio_keys.c @@ -30,6 +30,7 @@ #include #include #include +#include struct gpio_button_data { const struct gpio_keys_button *button; @@ -45,6 +46,7 @@ struct gpio_button_data { unsigned int software_debounce; /* in msecs, for GPIO-driven buttons */ unsigned int irq; + unsigned int wakeup_trigger_type; spinlock_t lock; bool disabled; bool key_pressed; @@ -540,6 +542,8 @@ static int gpio_keys_setup_key(struct platform_device *pdev, } if (bdata->gpiod) { + bool active_low = gpiod_is_active_low(bdata->gpiod); + if (button->debounce_interval) { error = gpiod_set_debounce(bdata->gpiod, button->debounce_interval * 1000); @@ -568,6 +572,24 @@ static int gpio_keys_setup_key(struct platform_device *pdev, isr = gpio_keys_gpio_isr; irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; + switch (button->wakeup_event_action) { + case EV_ACT_ASSERTED: + bdata->wakeup_trigger_type = active_low ? + IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; + break; + case EV_ACT_DEASSERTED: + bdata->wakeup_trigger_type = active_low ? + IRQ_TYPE_EDGE_RISING : IRQ_TYPE_EDGE_FALLING; + break; + case EV_ACT_ANY: + /* fall through */ + default: + /* + * For other cases, we are OK letting suspend/resume + * not reconfigure the trigger type. + */ + break; + } } else { if (!button->irq) { dev_err(dev, "Found button without gpio or irq\n"); @@ -586,6 +608,11 @@ static int gpio_keys_setup_key(struct platform_device *pdev, isr = gpio_keys_irq_isr; irqflags = 0; + + /* + * For IRQ buttons, there is no interrupt for release. + * So we don't need to reconfigure the trigger type for wakeup. + */ } bdata->code = &ddata->keymap[idx]; @@ -718,6 +745,9 @@ gpio_keys_get_devtree_pdata(struct device *dev) /* legacy name */ fwnode_property_read_bool(child, "gpio-key,wakeup"); + fwnode_property_read_u32(child, "wakeup-event-action", + &button->wakeup_event_action); + button->can_disable = fwnode_property_read_bool(child, "linux,can-disable"); @@ -845,19 +875,112 @@ static int gpio_keys_probe(struct platform_device *pdev) return 0; } +static int __maybe_unused +gpio_keys_button_enable_wakeup(struct gpio_button_data *bdata) +{ + int error; + + error = enable_irq_wake(bdata->irq); + if (error) { + dev_err(bdata->input->dev.parent, + "failed to configure IRQ %d as wakeup source: %d\n", + bdata->irq, error); + return error; + } + + if (bdata->wakeup_trigger_type) { + error = irq_set_irq_type(bdata->irq, + bdata->wakeup_trigger_type); + if (error) { + dev_err(bdata->input->dev.parent, + "failed to set wakeup trigger %08x for IRQ %d: %d\n", + bdata->wakeup_trigger_type, bdata->irq, error); + disable_irq_wake(bdata->irq); + return error; + } + } + + return 0; +} + +static void __maybe_unused +gpio_keys_button_disable_wakeup(struct gpio_button_data *bdata) +{ + int error; + + /* + * The trigger type is always both edges for gpio-based keys and we do + * not support changing wakeup trigger for interrupt-based keys. + */ + if (bdata->wakeup_trigger_type) { + error = irq_set_irq_type(bdata->irq, IRQ_TYPE_EDGE_BOTH); + if (error) + dev_warn(bdata->input->dev.parent, + "failed to restore interrupt trigger for IRQ %d: %d\n", + bdata->irq, error); + } + + error = disable_irq_wake(bdata->irq); + if (error) + dev_warn(bdata->input->dev.parent, + "failed to disable IRQ %d as wake source: %d\n", + bdata->irq, error); +} + +static int __maybe_unused +gpio_keys_enable_wakeup(struct gpio_keys_drvdata *ddata) +{ + struct gpio_button_data *bdata; + int error; + int i; + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + bdata = &ddata->data[i]; + if (bdata->button->wakeup) { + error = gpio_keys_button_enable_wakeup(bdata); + if (error) + goto err_out; + } + bdata->suspended = true; + } + + return 0; + +err_out: + while (i--) { + bdata = &ddata->data[i]; + if (bdata->button->wakeup) + gpio_keys_button_disable_wakeup(bdata); + bdata->suspended = false; + } + + return error; +} + +static void __maybe_unused +gpio_keys_disable_wakeup(struct gpio_keys_drvdata *ddata) +{ + struct gpio_button_data *bdata; + int i; + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + bdata = &ddata->data[i]; + bdata->suspended = false; + if (irqd_is_wakeup_set(irq_get_irq_data(bdata->irq))) + gpio_keys_button_disable_wakeup(bdata); + } +} + static int __maybe_unused gpio_keys_suspend(struct device *dev) { struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev); struct input_dev *input = ddata->input; - int i; + int error; if (device_may_wakeup(dev)) { - for (i = 0; i < ddata->pdata->nbuttons; i++) { - struct gpio_button_data *bdata = &ddata->data[i]; - if (bdata->button->wakeup) - enable_irq_wake(bdata->irq); - bdata->suspended = true; - } + error = gpio_keys_enable_wakeup(ddata); + if (error) + return error; } else { mutex_lock(&input->mutex); if (input->users) @@ -873,15 +996,9 @@ static int __maybe_unused gpio_keys_resume(struct device *dev) struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev); struct input_dev *input = ddata->input; int error = 0; - int i; if (device_may_wakeup(dev)) { - for (i = 0; i < ddata->pdata->nbuttons; i++) { - struct gpio_button_data *bdata = &ddata->data[i]; - if (bdata->button->wakeup) - disable_irq_wake(bdata->irq); - bdata->suspended = false; - } + gpio_keys_disable_wakeup(ddata); } else { mutex_lock(&input->mutex); if (input->users) diff --git a/include/dt-bindings/input/gpio-keys.h b/include/dt-bindings/input/gpio-keys.h new file mode 100644 index 000000000000..8962df79e753 --- /dev/null +++ b/include/dt-bindings/input/gpio-keys.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for gpio keys bindings. + */ + +#ifndef _DT_BINDINGS_GPIO_KEYS_H +#define _DT_BINDINGS_GPIO_KEYS_H + +#define EV_ACT_ANY 0x00 /* asserted or deasserted */ +#define EV_ACT_ASSERTED 0x01 /* asserted */ +#define EV_ACT_DEASSERTED 0x02 /* deasserted */ + +#endif /* _DT_BINDINGS_GPIO_KEYS_H */ diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h index d06bf77400f1..7160df54a6fe 100644 --- a/include/linux/gpio_keys.h +++ b/include/linux/gpio_keys.h @@ -13,6 +13,7 @@ struct device; * @desc: label that will be attached to button's gpio * @type: input event type (%EV_KEY, %EV_SW, %EV_ABS) * @wakeup: configure the button as a wake-up source + * @wakeup_event_action: event action to trigger wakeup * @debounce_interval: debounce ticks interval in msecs * @can_disable: %true indicates that userspace is allowed to * disable button via sysfs @@ -26,6 +27,7 @@ struct gpio_keys_button { const char *desc; unsigned int type; int wakeup; + int wakeup_event_action; int debounce_interval; bool can_disable; int value; -- cgit v1.2.3 From c4ccc893ce2ab819171f797e8b2c702cc87cb84a Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Mon, 12 Mar 2018 10:41:18 +0100 Subject: PCI: Add Altera vendor ID Add the Altera PCI Vendor id to pci_ids.h and remove the private definitions from xillybus_pcie.c and altera-cvp.c. Signed-off-by: Johannes Thumshirn Cc: Bjorn Helgaas Cc: Eli Billauer Cc: Anatolij Gustschin Acked-by: Eli Billauer Acked-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko Signed-off-by: Greg Kroah-Hartman --- drivers/char/xillybus/xillybus_pcie.c | 1 - drivers/fpga/altera-cvp.c | 2 -- include/linux/pci_ids.h | 2 ++ 3 files changed, 2 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/char/xillybus/xillybus_pcie.c b/drivers/char/xillybus/xillybus_pcie.c index dff2d1538164..05e5324f60bd 100644 --- a/drivers/char/xillybus/xillybus_pcie.c +++ b/drivers/char/xillybus/xillybus_pcie.c @@ -24,7 +24,6 @@ MODULE_LICENSE("GPL v2"); #define PCI_DEVICE_ID_XILLYBUS 0xebeb -#define PCI_VENDOR_ID_ALTERA 0x1172 #define PCI_VENDOR_ID_ACTEL 0x11aa #define PCI_VENDOR_ID_LATTICE 0x1204 diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 00e73d28077c..77b04e4b3254 100644 --- a/drivers/fpga/altera-cvp.c +++ b/drivers/fpga/altera-cvp.c @@ -384,8 +384,6 @@ static int altera_cvp_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id); static void altera_cvp_remove(struct pci_dev *pdev); -#define PCI_VENDOR_ID_ALTERA 0x1172 - static struct pci_device_id altera_cvp_id_tbl[] = { { PCI_VDEVICE(ALTERA, PCI_ANY_ID) }, { } diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a6b30667a331..6a96a70fb462 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -1561,6 +1561,8 @@ #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408 +#define PCI_VENDOR_ID_ALTERA 0x1172 + #define PCI_VENDOR_ID_SBE 0x1176 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302 -- cgit v1.2.3 From 0b2ed745e76debad33410870c4850ef2ca42f5e3 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 9 Mar 2018 14:46:55 +0000 Subject: nvmem: Document struct nvmem_config Add a simple description of struct nvmem_config and its fields. Cc: Srinivas Kandagatla Cc: Heiko Stuebner Cc: Masahiro Yamada Cc: Carlo Caione Cc: Kevin Hilman Cc: Matthias Brugger Cc: cphealy@gmail.com Cc: linux-kernel@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- include/linux/nvmem-provider.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index 497706f5adca..a39f76ff2ccd 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -22,6 +22,28 @@ typedef int (*nvmem_reg_read_t)(void *priv, unsigned int offset, typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, void *val, size_t bytes); +/** + * struct nvmem_config - NVMEM device configuration + * + * @dev: Parent device. + * @name: Optional name. + * @id: Optional device ID used in full name. Ignored if name is NULL. + * @owner: Pointer to exporter module. Used for refcounting. + * @cells: Optional array of pre-defined NVMEM cells. + * @ncells: Number of elements in cells. + * @read_only: Device is read-only. + * @root_only: Device is accessibly to root only. + * @reg_read: Callback to read data. + * @reg_write: Callback to write data. + * @size: Device size. + * @word_size: Minimum read/write access granularity. + * @stride: Minimum read/write access stride. + * @priv: User context passed to read/write callbacks. + * + * Note: A default "nvmem" name will be assigned to the device if + * no name is specified in its configuration. In such case "" is + * generated with ida_simple_get() and provided id field is ignored. + */ struct nvmem_config { struct device *dev; const char *name; -- cgit v1.2.3 From fd0f4906a3cdf2fedc980764a073f2313bdf1f47 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 9 Mar 2018 14:46:56 +0000 Subject: nvmem: core: Allow specifying device name verbatim Add code to allow avoid having nvmem core append a numeric suffix to the end of the name by passing config->id of -1. Cc: Srinivas Kandagatla Cc: Heiko Stuebner Cc: Masahiro Yamada Cc: Carlo Caione Cc: Kevin Hilman Cc: Matthias Brugger Cc: cphealy@gmail.com Cc: linux-kernel@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- drivers/nvmem/core.c | 11 ++++++++--- include/linux/nvmem-provider.h | 3 +++ 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 35a3dbeea324..99e04cfcc723 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -473,9 +473,14 @@ struct nvmem_device *nvmem_register(const struct nvmem_config *config) nvmem->reg_read = config->reg_read; nvmem->reg_write = config->reg_write; nvmem->dev.of_node = config->dev->of_node; - dev_set_name(&nvmem->dev, "%s%d", - config->name ? : "nvmem", - config->name ? config->id : nvmem->id); + + if (config->id == -1 && config->name) { + dev_set_name(&nvmem->dev, "%s", config->name); + } else { + dev_set_name(&nvmem->dev, "%s%d", + config->name ? : "nvmem", + config->name ? config->id : nvmem->id); + } nvmem->read_only = device_property_present(config->dev, "read-only") | config->read_only; diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index a39f76ff2ccd..b00567a07496 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -43,6 +43,9 @@ typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, * Note: A default "nvmem" name will be assigned to the device if * no name is specified in its configuration. In such case "" is * generated with ida_simple_get() and provided id field is ignored. + * + * Note: Specifying name and setting id to -1 implies a unique device + * whose name is provided as-is (kept unaltered). */ struct nvmem_config { struct device *dev; -- cgit v1.2.3 From f1f50eca5f90527d2cca3479cda08883958777f6 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 9 Mar 2018 14:46:57 +0000 Subject: nvmem: Introduce devm_nvmem_(un)register() Introduce devm_nvmem_register()/devm_nvmem_unregister() to make .remove() unnecessary in trivial drivers. Cc: Srinivas Kandagatla Cc: Heiko Stuebner Cc: Masahiro Yamada Cc: Carlo Caione Cc: Kevin Hilman Cc: Matthias Brugger Cc: cphealy@gmail.com Cc: linux-kernel@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- drivers/nvmem/core.c | 59 ++++++++++++++++++++++++++++++++++++++++++ include/linux/nvmem-provider.h | 17 ++++++++++++ 2 files changed, 76 insertions(+) (limited to 'include/linux') diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 99e04cfcc723..b05aa8e81303 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -549,6 +549,65 @@ int nvmem_unregister(struct nvmem_device *nvmem) } EXPORT_SYMBOL_GPL(nvmem_unregister); +static void devm_nvmem_release(struct device *dev, void *res) +{ + WARN_ON(nvmem_unregister(*(struct nvmem_device **)res)); +} + +/** + * devm_nvmem_register() - Register a managed nvmem device for given + * nvmem_config. + * Also creates an binary entry in /sys/bus/nvmem/devices/dev-name/nvmem + * + * @config: nvmem device configuration with which nvmem device is created. + * + * Return: Will be an ERR_PTR() on error or a valid pointer to nvmem_device + * on success. + */ +struct nvmem_device *devm_nvmem_register(struct device *dev, + const struct nvmem_config *config) +{ + struct nvmem_device **ptr, *nvmem; + + ptr = devres_alloc(devm_nvmem_release, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + nvmem = nvmem_register(config); + + if (!IS_ERR(nvmem)) { + *ptr = nvmem; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return nvmem; +} +EXPORT_SYMBOL_GPL(devm_nvmem_register); + +static int devm_nvmem_match(struct device *dev, void *res, void *data) +{ + struct nvmem_device **r = res; + + return *r == data; +} + +/** + * devm_nvmem_unregister() - Unregister previously registered managed nvmem + * device. + * + * @nvmem: Pointer to previously registered nvmem device. + * + * Return: Will be an negative on error or a zero on success. + */ +int devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem) +{ + return devres_release(dev, devm_nvmem_release, devm_nvmem_match, nvmem); +} +EXPORT_SYMBOL(devm_nvmem_unregister); + + static struct nvmem_device *__nvmem_device_get(struct device_node *np, struct nvmem_cell **cellp, const char *cell_id) diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index b00567a07496..f89598bc4e1c 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -72,6 +72,11 @@ struct nvmem_config { struct nvmem_device *nvmem_register(const struct nvmem_config *cfg); int nvmem_unregister(struct nvmem_device *nvmem); +struct nvmem_device *devm_nvmem_register(struct device *dev, + const struct nvmem_config *cfg); + +int devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem); + #else static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c) @@ -84,5 +89,17 @@ static inline int nvmem_unregister(struct nvmem_device *nvmem) return -ENOSYS; } +static inline struct nvmem_device * +devm_nvmem_register(struct device *dev, const struct nvmem_config *c) +{ + return nvmem_register(c); +} + +static inline int +devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem) +{ + return nvmem_unregister(nvmem); +} + #endif /* CONFIG_NVMEM */ #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ -- cgit v1.2.3 From 16ca6a607d84bef0129698d8d808f501afd08d43 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 6 Mar 2018 21:48:01 +0000 Subject: KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid The vgic code is trying to be clever when injecting GICv2 SGIs, and will happily populate LRs with the same interrupt number if they come from multiple vcpus (after all, they are distinct interrupt sources). Unfortunately, this is against the letter of the architecture, and the GICv2 architecture spec says "Each valid interrupt stored in the List registers must have a unique VirtualID for that virtual CPU interface.". GICv3 has similar (although slightly ambiguous) restrictions. This results in guests locking up when using GICv2-on-GICv3, for example. The obvious fix is to stop trying so hard, and inject a single vcpu per SGI per guest entry. After all, pending SGIs with multiple source vcpus are pretty rare, and are mostly seen in scenario where the physical CPUs are severely overcomitted. But as we now only inject a single instance of a multi-source SGI per vcpu entry, we may delay those interrupts for longer than strictly necessary, and run the risk of injecting lower priority interrupts in the meantime. In order to address this, we adopt a three stage strategy: - If we encounter a multi-source SGI in the AP list while computing its depth, we force the list to be sorted - When populating the LRs, we prevent the injection of any interrupt of lower priority than that of the first multi-source SGI we've injected. - Finally, the injection of a multi-source SGI triggers the request of a maintenance interrupt when there will be no pending interrupt in the LRs (HCR_NPIE). At the point where the last pending interrupt in the LRs switches from Pending to Active, the maintenance interrupt will be delivered, allowing us to add the remaining SGIs using the same process. Cc: stable@vger.kernel.org Fixes: 0919e84c0fc1 ("KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework") Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/linux/irqchip/arm-gic-v3.h | 1 + include/linux/irqchip/arm-gic.h | 1 + virt/kvm/arm/vgic/vgic-v2.c | 9 +++++- virt/kvm/arm/vgic/vgic-v3.c | 9 +++++- virt/kvm/arm/vgic/vgic.c | 61 +++++++++++++++++++++++++++++--------- virt/kvm/arm/vgic/vgic.h | 2 ++ 6 files changed, 67 insertions(+), 16 deletions(-) (limited to 'include/linux') diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c00c4c33e432..b26eccc78fb1 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -503,6 +503,7 @@ #define ICH_HCR_EN (1 << 0) #define ICH_HCR_UIE (1 << 1) +#define ICH_HCR_NPIE (1 << 3) #define ICH_HCR_TC (1 << 10) #define ICH_HCR_TALL0 (1 << 11) #define ICH_HCR_TALL1 (1 << 12) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index d3453ee072fc..68d8b1f73682 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -84,6 +84,7 @@ #define GICH_HCR_EN (1 << 0) #define GICH_HCR_UIE (1 << 1) +#define GICH_HCR_NPIE (1 << 3) #define GICH_LR_VIRTUALID (0x3ff << 0) #define GICH_LR_PHYSID_CPUID_SHIFT (10) diff --git a/virt/kvm/arm/vgic/vgic-v2.c b/virt/kvm/arm/vgic/vgic-v2.c index e9d840a75e7b..29556f71b691 100644 --- a/virt/kvm/arm/vgic/vgic-v2.c +++ b/virt/kvm/arm/vgic/vgic-v2.c @@ -37,6 +37,13 @@ void vgic_v2_init_lrs(void) vgic_v2_write_lr(i, 0); } +void vgic_v2_set_npie(struct kvm_vcpu *vcpu) +{ + struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; + + cpuif->vgic_hcr |= GICH_HCR_NPIE; +} + void vgic_v2_set_underflow(struct kvm_vcpu *vcpu) { struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; @@ -64,7 +71,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu) int lr; unsigned long flags; - cpuif->vgic_hcr &= ~GICH_HCR_UIE; + cpuif->vgic_hcr &= ~(GICH_HCR_UIE | GICH_HCR_NPIE); for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { u32 val = cpuif->vgic_lr[lr]; diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c index 6b329414e57a..0ff2006f3781 100644 --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -26,6 +26,13 @@ static bool group1_trap; static bool common_trap; static bool gicv4_enable; +void vgic_v3_set_npie(struct kvm_vcpu *vcpu) +{ + struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; + + cpuif->vgic_hcr |= ICH_HCR_NPIE; +} + void vgic_v3_set_underflow(struct kvm_vcpu *vcpu) { struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; @@ -47,7 +54,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) int lr; unsigned long flags; - cpuif->vgic_hcr &= ~ICH_HCR_UIE; + cpuif->vgic_hcr &= ~(ICH_HCR_UIE | ICH_HCR_NPIE); for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { u64 val = cpuif->vgic_lr[lr]; diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c index 0001858a2c23..8201899126f6 100644 --- a/virt/kvm/arm/vgic/vgic.c +++ b/virt/kvm/arm/vgic/vgic.c @@ -710,22 +710,37 @@ static inline void vgic_set_underflow(struct kvm_vcpu *vcpu) vgic_v3_set_underflow(vcpu); } +static inline void vgic_set_npie(struct kvm_vcpu *vcpu) +{ + if (kvm_vgic_global_state.type == VGIC_V2) + vgic_v2_set_npie(vcpu); + else + vgic_v3_set_npie(vcpu); +} + /* Requires the ap_list_lock to be held. */ -static int compute_ap_list_depth(struct kvm_vcpu *vcpu) +static int compute_ap_list_depth(struct kvm_vcpu *vcpu, + bool *multi_sgi) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; struct vgic_irq *irq; int count = 0; + *multi_sgi = false; + DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock)); list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) { spin_lock(&irq->irq_lock); /* GICv2 SGIs can count for more than one... */ - if (vgic_irq_is_sgi(irq->intid) && irq->source) - count += hweight8(irq->source); - else + if (vgic_irq_is_sgi(irq->intid) && irq->source) { + int w = hweight8(irq->source); + + count += w; + *multi_sgi |= (w > 1); + } else { count++; + } spin_unlock(&irq->irq_lock); } return count; @@ -736,28 +751,43 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; struct vgic_irq *irq; - int count = 0; + int count; + bool npie = false; + bool multi_sgi; + u8 prio = 0xff; DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock)); - if (compute_ap_list_depth(vcpu) > kvm_vgic_global_state.nr_lr) + count = compute_ap_list_depth(vcpu, &multi_sgi); + if (count > kvm_vgic_global_state.nr_lr || multi_sgi) vgic_sort_ap_list(vcpu); + count = 0; + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) { spin_lock(&irq->irq_lock); - if (unlikely(vgic_target_oracle(irq) != vcpu)) - goto next; - /* - * If we get an SGI with multiple sources, try to get - * them in all at once. + * If we have multi-SGIs in the pipeline, we need to + * guarantee that they are all seen before any IRQ of + * lower priority. In that case, we need to filter out + * these interrupts by exiting early. This is easy as + * the AP list has been sorted already. */ - do { + if (multi_sgi && irq->priority > prio) { + spin_unlock(&irq->irq_lock); + break; + } + + if (likely(vgic_target_oracle(irq) == vcpu)) { vgic_populate_lr(vcpu, irq, count++); - } while (irq->source && count < kvm_vgic_global_state.nr_lr); -next: + if (irq->source) { + npie = true; + prio = irq->priority; + } + } + spin_unlock(&irq->irq_lock); if (count == kvm_vgic_global_state.nr_lr) { @@ -768,6 +798,9 @@ next: } } + if (npie) + vgic_set_npie(vcpu); + vcpu->arch.vgic_cpu.used_lrs = count; /* Nuke remaining LRs */ diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h index 5b11859a1a1e..f5b8519e5546 100644 --- a/virt/kvm/arm/vgic/vgic.h +++ b/virt/kvm/arm/vgic/vgic.h @@ -160,6 +160,7 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu); void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr); void vgic_v2_set_underflow(struct kvm_vcpu *vcpu); +void vgic_v2_set_npie(struct kvm_vcpu *vcpu); int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, int offset, u32 *val); @@ -189,6 +190,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu); void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr); void vgic_v3_set_underflow(struct kvm_vcpu *vcpu); +void vgic_v3_set_npie(struct kvm_vcpu *vcpu); void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); void vgic_v3_enable(struct kvm_vcpu *vcpu); -- cgit v1.2.3 From 72f7cc09b143cf972c8c7571fc95d1017ba76c3d Mon Sep 17 00:00:00 2001 From: Mark Bloch Date: Tue, 13 Mar 2018 15:18:46 +0200 Subject: IB/mlx5: Expose more priorities for bypass namespace BYPASS namespace is used by the RDMA side to insert flow rules into the vport RX flow tables. Currently only 8 priorities are exposed, increase this to 16 to allow more flexibility. This change will also cause the BYPASS namespace to use 32 levels (as apposed to 16 today) of flow tables, 16 levels for regular rules and 16 for don't trap rules. Reviewed-by: Maor Gottlieb Signed-off-by: Mark Bloch Signed-off-by: Leon Romanovsky Signed-off-by: Doug Ledford --- include/linux/mlx5/device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index e5258ee4e38b..413df3c11a46 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1204,8 +1204,8 @@ static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; } -#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 -#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 +#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 +#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ -- cgit v1.2.3 From caacdbf4aa567ab5e8de1a4070195c5d3e8f1340 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 7 Mar 2018 15:57:27 -0800 Subject: genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER The arm multi irq handler registration mechanism has been copied into a handful of architectures, including arm64 and openrisc. RISC-V needs the same mechanism. Instead of adding yet another copy for RISC-V copy the arm implementation into the core code depending on a new Kconfig symbol: CONFIG_GENERIC_MULTI_IRQ_HANDLER. Subsequent patches will convert the various architectures. Signed-off-by: Palmer Dabbelt Signed-off-by: Thomas Gleixner Cc: jonas@southpole.se Cc: catalin.marinas@arm.com Cc: Will Deacon Cc: linux@armlinux.org.uk Cc: stefan.kristiansson@saunalahti.fi Cc: openrisc@lists.librecores.org Cc: shorne@gmail.com Cc: linux-riscv@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lkml.kernel.org/r/20180307235731.22627-2-palmer@sifive.com --- include/linux/irq.h | 18 ++++++++++++++++++ kernel/irq/Kconfig | 5 +++++ kernel/irq/handle.c | 15 +++++++++++++++ 3 files changed, 38 insertions(+) (limited to 'include/linux') diff --git a/include/linux/irq.h b/include/linux/irq.h index 979eed1b2654..65916a305f3d 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1165,4 +1165,22 @@ int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); int ipi_send_single(unsigned int virq, unsigned int cpu); int ipi_send_mask(unsigned int virq, const struct cpumask *dest); +#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER +/* + * Registers a generic IRQ handling function as the top-level IRQ handler in + * the system, which is generally the first C code called from an assembly + * architecture-specific interrupt handler. + * + * Returns 0 on success, or -EBUSY if an IRQ handler has already been + * registered. + */ +int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); + +/* + * Allows interrupt handlers to find the irqchip that's been registered as the + * top-level IRQ handler. + */ +extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; +#endif + #endif /* _LINUX_IRQ_H */ diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig index 6fc87ccda1d7..5f3e2baefca9 100644 --- a/kernel/irq/Kconfig +++ b/kernel/irq/Kconfig @@ -132,3 +132,8 @@ config GENERIC_IRQ_DEBUGFS If you don't know what to do here, say N. endmenu + +config GENERIC_IRQ_MULTI_HANDLER + bool + help + Allow to specify the low level IRQ handler at run time. diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c index 79f987b942b8..3570c715c3e7 100644 --- a/kernel/irq/handle.c +++ b/kernel/irq/handle.c @@ -20,6 +20,10 @@ #include "internals.h" +#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER +void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; +#endif + /** * handle_bad_irq - handle spurious and unhandled irqs * @desc: description of the interrupt @@ -207,3 +211,14 @@ irqreturn_t handle_irq_event(struct irq_desc *desc) irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); return ret; } + +#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER +int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) +{ + if (handle_arch_irq) + return -EBUSY; + + handle_arch_irq = handle_irq; + return 0; +} +#endif -- cgit v1.2.3 From e36df28f532f882965404d58e240f2e058b61f45 Mon Sep 17 00:00:00 2001 From: Dave Young Date: Tue, 13 Feb 2018 15:28:34 +0800 Subject: printk: move dump stack related code to lib/dump_stack.c dump_stack related stuff should belong to lib/dump_stack.c thus move them there. Also conditionally compile lib/dump_stack.c since dump_stack code does not make sense if printk is disabled. Link: http://lkml.kernel.org/r/20180213072834.GA24784@dhcp-128-65.nay.redhat.com To: Steven Rostedt Cc: linux-kernel@vger.kernel.org Cc: akpm@linux-foundation.org Cc: Andi Kleen Signed-off-by: Dave Young Suggested-by: Steven Rostedt Suggested-by: Sergey Senozhatsky Reviewed-by: Sergey Senozhatsky Signed-off-by: Petr Mladek --- include/linux/printk.h | 7 ++++-- kernel/printk/printk.c | 60 -------------------------------------------------- lib/Makefile | 3 ++- lib/dump_stack.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 67 insertions(+), 63 deletions(-) (limited to 'include/linux') diff --git a/include/linux/printk.h b/include/linux/printk.h index e9b603ee9953..6d7e800affd8 100644 --- a/include/linux/printk.h +++ b/include/linux/printk.h @@ -201,6 +201,7 @@ void __init setup_log_buf(int early); __printf(1, 2) void dump_stack_set_arch_desc(const char *fmt, ...); void dump_stack_print_info(const char *log_lvl); void show_regs_print_info(const char *log_lvl); +extern asmlinkage void dump_stack(void) __cold; extern void printk_safe_init(void); extern void printk_safe_flush(void); extern void printk_safe_flush_on_panic(void); @@ -264,6 +265,10 @@ static inline void show_regs_print_info(const char *log_lvl) { } +static inline asmlinkage void dump_stack(void) +{ +} + static inline void printk_safe_init(void) { } @@ -279,8 +284,6 @@ static inline void printk_safe_flush_on_panic(void) extern int kptr_restrict; -extern asmlinkage void dump_stack(void) __cold; - #ifndef pr_fmt #define pr_fmt(fmt) fmt #endif diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index fa3de5f10e0e..dc663f288463 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -42,13 +42,11 @@ #include #include #include -#include #include #include #include #include #include -#include #include #include @@ -3257,62 +3255,4 @@ void kmsg_dump_rewind(struct kmsg_dumper *dumper) } EXPORT_SYMBOL_GPL(kmsg_dump_rewind); -static char dump_stack_arch_desc_str[128]; - -/** - * dump_stack_set_arch_desc - set arch-specific str to show with task dumps - * @fmt: printf-style format string - * @...: arguments for the format string - * - * The configured string will be printed right after utsname during task - * dumps. Usually used to add arch-specific system identifiers. If an - * arch wants to make use of such an ID string, it should initialize this - * as soon as possible during boot. - */ -void __init dump_stack_set_arch_desc(const char *fmt, ...) -{ - va_list args; - - va_start(args, fmt); - vsnprintf(dump_stack_arch_desc_str, sizeof(dump_stack_arch_desc_str), - fmt, args); - va_end(args); -} - -/** - * dump_stack_print_info - print generic debug info for dump_stack() - * @log_lvl: log level - * - * Arch-specific dump_stack() implementations can use this function to - * print out the same debug information as the generic dump_stack(). - */ -void dump_stack_print_info(const char *log_lvl) -{ - printk("%sCPU: %d PID: %d Comm: %.20s %s%s %s %.*s\n", - log_lvl, raw_smp_processor_id(), current->pid, current->comm, - kexec_crash_loaded() ? "Kdump: loaded " : "", - print_tainted(), - init_utsname()->release, - (int)strcspn(init_utsname()->version, " "), - init_utsname()->version); - - if (dump_stack_arch_desc_str[0] != '\0') - printk("%sHardware name: %s\n", - log_lvl, dump_stack_arch_desc_str); - - print_worker_info(log_lvl, current); -} - -/** - * show_regs_print_info - print generic debug info for show_regs() - * @log_lvl: log level - * - * show_regs() implementations can use this function to print out generic - * debug information. - */ -void show_regs_print_info(const char *log_lvl) -{ - dump_stack_print_info(log_lvl); -} - #endif diff --git a/lib/Makefile b/lib/Makefile index 7adb066692b3..6ae3bd481379 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -18,7 +18,7 @@ KCOV_INSTRUMENT_debugobjects.o := n KCOV_INSTRUMENT_dynamic_debug.o := n lib-y := ctype.o string.o vsprintf.o cmdline.o \ - rbtree.o radix-tree.o dump_stack.o timerqueue.o\ + rbtree.o radix-tree.o timerqueue.o\ idr.o int_sqrt.o extable.o \ sha1.o chacha20.o irq_regs.o argv_split.o \ flex_proportions.o ratelimit.o show_mem.o \ @@ -26,6 +26,7 @@ lib-y := ctype.o string.o vsprintf.o cmdline.o \ earlycpio.o seq_buf.o siphash.o \ nmi_backtrace.o nodemask.o win_minmax.o +lib-$(CONFIG_PRINTK) += dump_stack.o lib-$(CONFIG_MMU) += ioremap.o lib-$(CONFIG_SMP) += cpumask.o lib-$(CONFIG_DMA_DIRECT_OPS) += dma-direct.o diff --git a/lib/dump_stack.c b/lib/dump_stack.c index c5edbedd364d..5cff72f18c4a 100644 --- a/lib/dump_stack.c +++ b/lib/dump_stack.c @@ -10,6 +10,66 @@ #include #include #include +#include +#include + +static char dump_stack_arch_desc_str[128]; + +/** + * dump_stack_set_arch_desc - set arch-specific str to show with task dumps + * @fmt: printf-style format string + * @...: arguments for the format string + * + * The configured string will be printed right after utsname during task + * dumps. Usually used to add arch-specific system identifiers. If an + * arch wants to make use of such an ID string, it should initialize this + * as soon as possible during boot. + */ +void __init dump_stack_set_arch_desc(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + vsnprintf(dump_stack_arch_desc_str, sizeof(dump_stack_arch_desc_str), + fmt, args); + va_end(args); +} + +/** + * dump_stack_print_info - print generic debug info for dump_stack() + * @log_lvl: log level + * + * Arch-specific dump_stack() implementations can use this function to + * print out the same debug information as the generic dump_stack(). + */ +void dump_stack_print_info(const char *log_lvl) +{ + printk("%sCPU: %d PID: %d Comm: %.20s %s%s %s %.*s\n", + log_lvl, raw_smp_processor_id(), current->pid, current->comm, + kexec_crash_loaded() ? "Kdump: loaded " : "", + print_tainted(), + init_utsname()->release, + (int)strcspn(init_utsname()->version, " "), + init_utsname()->version); + + if (dump_stack_arch_desc_str[0] != '\0') + printk("%sHardware name: %s\n", + log_lvl, dump_stack_arch_desc_str); + + print_worker_info(log_lvl, current); +} + +/** + * show_regs_print_info - print generic debug info for show_regs() + * @log_lvl: log level + * + * show_regs() implementations can use this function to print out generic + * debug information. + */ +void show_regs_print_info(const char *log_lvl) +{ + dump_stack_print_info(log_lvl); +} static void __dump_stack(void) { -- cgit v1.2.3 From 71cfdd0bad3ad91680e6b82cac634154cf56376e Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Wed, 14 Mar 2018 19:25:06 +0100 Subject: libnvdimm: provide module_nd_driver wrapper Provide a module_nd_driver() wrapper over simple nd_driver_register() nd_driver_unregister() combinations in module_init() and module_exit() respectively. Note an explicit nd_driver_unregister() had to be implemented as nd bus drivers did call device_unregister() direcly in the module_exit() function. Signed-off-by: Johannes Thumshirn Signed-off-by: Dan Williams --- include/linux/nd.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nd.h b/include/linux/nd.h index 5dc6b695437d..43c181a6add5 100644 --- a/include/linux/nd.h +++ b/include/linux/nd.h @@ -180,6 +180,12 @@ struct nd_region; void nvdimm_region_notify(struct nd_region *nd_region, enum nvdimm_event event); int __must_check __nd_driver_register(struct nd_device_driver *nd_drv, struct module *module, const char *mod_name); +static inline void nd_driver_unregister(struct nd_device_driver *drv) +{ + driver_unregister(&drv->drv); +} #define nd_driver_register(driver) \ __nd_driver_register(driver, THIS_MODULE, KBUILD_MODNAME) +#define module_nd_driver(driver) \ + module_driver(driver, nd_driver_register, nd_driver_unregister) #endif /* __LINUX_ND_H__ */ -- cgit v1.2.3 From dcba51bbb9e0cc7f80d36eb20a033a4dff2ce9cc Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 12 Feb 2018 22:03:08 +0100 Subject: mtd: Get rid of unused fields in struct erase_info Some fields are not used by MTD drivers, users or core code. Moreover, those fields are not documented, so get rid of them to avoid any confusion. Signed-off-by: Boris Brezillon Reviewed-by: Richard Weinberger --- include/linux/mtd/mtd.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 205ededccc60..2a407dc9beaa 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -48,14 +48,9 @@ struct erase_info { uint64_t addr; uint64_t len; uint64_t fail_addr; - u_long time; - u_long retries; - unsigned dev; - unsigned cell; void (*callback) (struct erase_info *self); u_long priv; u_char state; - struct erase_info *next; }; struct mtd_erase_region_info { -- cgit v1.2.3 From 219c7b06f3da9ac2b51ed671881b20f1b127daef Mon Sep 17 00:00:00 2001 From: Mathieu Malaterre Date: Sat, 10 Mar 2018 19:06:45 +0100 Subject: powerpc: Mark the variable earlycon_acpi_spcr_enable maybe_unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-use the object-like macro EARLYCON_USED_OR_UNUSED to mark `earlycon_acpi_spcr_enable` as maybe_unused. Fix the following warning (treated as error in W=1) CC arch/powerpc/kernel/setup-common.o In file included from ./include/linux/serial_8250.h:14:0, from arch/powerpc/kernel/setup-common.c:33: ./include/linux/serial_core.h:382:19: error: ‘earlycon_acpi_spcr_enable’ defined but not used [-Werror=unused-const-variable=] static const bool earlycon_acpi_spcr_enable; ^~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Signed-off-by: Mathieu Malaterre Signed-off-by: Greg Kroah-Hartman --- include/linux/serial_core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index b32df49a3bd5..1d356105f25a 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -379,7 +379,7 @@ extern int of_setup_earlycon(const struct earlycon_id *match, extern bool earlycon_acpi_spcr_enable __initdata; int setup_earlycon(char *buf); #else -static const bool earlycon_acpi_spcr_enable; +static const bool earlycon_acpi_spcr_enable EARLYCON_USED_OR_UNUSED; static inline int setup_earlycon(char *buf) { return 0; } #endif -- cgit v1.2.3 From 884cfd9023ce6afe8bcf181ec988d8516eb32bf0 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 12 Feb 2018 22:03:09 +0100 Subject: mtd: Stop assuming mtd_erase() is asynchronous None of the mtd->_erase() implementations work in an asynchronous manner, so let's simplify MTD users that call mtd_erase(). All they need to do is check the value returned by mtd_erase() and assume that != 0 means failure. Signed-off-by: Boris Brezillon Reviewed-by: Richard Weinberger --- drivers/mtd/devices/bcm47xxsflash.c | 3 -- drivers/mtd/ftl.c | 51 ++++---------------- drivers/mtd/inftlmount.c | 5 +- drivers/mtd/mtdblock.c | 20 -------- drivers/mtd/mtdchar.c | 33 +------------ drivers/mtd/mtdconcat.c | 48 ++----------------- drivers/mtd/mtdcore.c | 8 ++-- drivers/mtd/mtdoops.c | 19 -------- drivers/mtd/mtdpart.c | 2 - drivers/mtd/mtdswap.c | 32 ------------- drivers/mtd/nftlmount.c | 4 +- drivers/mtd/rfd_ftl.c | 92 +++++++++++-------------------------- drivers/mtd/sm_ftl.c | 18 -------- drivers/mtd/sm_ftl.h | 4 -- drivers/mtd/tests/mtd_test.c | 4 -- drivers/mtd/tests/speedtest.c | 6 --- drivers/mtd/ubi/io.c | 35 -------------- fs/jffs2/erase.c | 36 ++------------- include/linux/mtd/mtd.h | 2 - 19 files changed, 52 insertions(+), 370 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c index e2bd81817df4..6b84947cfbea 100644 --- a/drivers/mtd/devices/bcm47xxsflash.c +++ b/drivers/mtd/devices/bcm47xxsflash.c @@ -95,9 +95,6 @@ static int bcm47xxsflash_erase(struct mtd_info *mtd, struct erase_info *erase) else erase->state = MTD_ERASE_DONE; - if (erase->callback) - erase->callback(erase); - return err; } diff --git a/drivers/mtd/ftl.c b/drivers/mtd/ftl.c index 664d206a4cbe..fcf9907e7987 100644 --- a/drivers/mtd/ftl.c +++ b/drivers/mtd/ftl.c @@ -140,12 +140,6 @@ typedef struct partition_t { #define XFER_PREPARED 0x03 #define XFER_FAILED 0x04 -/*====================================================================*/ - - -static void ftl_erase_callback(struct erase_info *done); - - /*====================================================================== Scan_header() checks to see if a memory region contains an FTL @@ -349,17 +343,19 @@ static int erase_xfer(partition_t *part, return -ENOMEM; erase->mtd = part->mbd.mtd; - erase->callback = ftl_erase_callback; erase->addr = xfer->Offset; erase->len = 1 << part->header.EraseUnitSize; - erase->priv = (u_long)part; ret = mtd_erase(part->mbd.mtd, erase); + if (!ret) { + xfer->state = XFER_ERASED; + xfer->EraseCount++; + } else { + xfer->state = XFER_FAILED; + pr_notice("ftl_cs: erase failed: err = %d\n", ret); + } - if (!ret) - xfer->EraseCount++; - else - kfree(erase); + kfree(erase); return ret; } /* erase_xfer */ @@ -371,37 +367,6 @@ static int erase_xfer(partition_t *part, ======================================================================*/ -static void ftl_erase_callback(struct erase_info *erase) -{ - partition_t *part; - struct xfer_info_t *xfer; - int i; - - /* Look up the transfer unit */ - part = (partition_t *)(erase->priv); - - for (i = 0; i < part->header.NumTransferUnits; i++) - if (part->XferInfo[i].Offset == erase->addr) break; - - if (i == part->header.NumTransferUnits) { - printk(KERN_NOTICE "ftl_cs: internal error: " - "erase lookup failed!\n"); - return; - } - - xfer = &part->XferInfo[i]; - if (erase->state == MTD_ERASE_DONE) - xfer->state = XFER_ERASED; - else { - xfer->state = XFER_FAILED; - printk(KERN_NOTICE "ftl_cs: erase failed: state = %d\n", - erase->state); - } - - kfree(erase); - -} /* ftl_erase_callback */ - static int prepare_xfer(partition_t *part, int i) { erase_unit_header_t header; diff --git a/drivers/mtd/inftlmount.c b/drivers/mtd/inftlmount.c index 8d6bb189ea8e..0f47be4834d8 100644 --- a/drivers/mtd/inftlmount.c +++ b/drivers/mtd/inftlmount.c @@ -393,9 +393,10 @@ int INFTL_formatblock(struct INFTLrecord *inftl, int block) mark only the failed block in the bbt. */ for (physblock = 0; physblock < inftl->EraseSize; physblock += instr->len, instr->addr += instr->len) { - mtd_erase(inftl->mbd.mtd, instr); + int ret; - if (instr->state == MTD_ERASE_FAILED) { + ret = mtd_erase(inftl->mbd.mtd, instr); + if (ret) { printk(KERN_WARNING "INFTL: error while formatting block %d\n", block); goto fail; diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c index bb4c14f83c75..7b2b7f651181 100644 --- a/drivers/mtd/mtdblock.c +++ b/drivers/mtd/mtdblock.c @@ -55,48 +55,28 @@ struct mtdblk_dev { * being written to until a different sector is required. */ -static void erase_callback(struct erase_info *done) -{ - wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv; - wake_up(wait_q); -} - static int erase_write (struct mtd_info *mtd, unsigned long pos, int len, const char *buf) { struct erase_info erase; - DECLARE_WAITQUEUE(wait, current); - wait_queue_head_t wait_q; size_t retlen; int ret; /* * First, let's erase the flash block. */ - - init_waitqueue_head(&wait_q); erase.mtd = mtd; - erase.callback = erase_callback; erase.addr = pos; erase.len = len; - erase.priv = (u_long)&wait_q; - - set_current_state(TASK_INTERRUPTIBLE); - add_wait_queue(&wait_q, &wait); ret = mtd_erase(mtd, &erase); if (ret) { - set_current_state(TASK_RUNNING); - remove_wait_queue(&wait_q, &wait); printk (KERN_WARNING "mtdblock: erase of region [0x%lx, 0x%x] " "on \"%s\" failed\n", pos, len, mtd->name); return ret; } - schedule(); /* Wait for erase to finish. */ - remove_wait_queue(&wait_q, &wait); - /* * Next, write the data to flash. */ diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c index de8c902059b8..2beb22dd6bbb 100644 --- a/drivers/mtd/mtdchar.c +++ b/drivers/mtd/mtdchar.c @@ -324,10 +324,6 @@ static ssize_t mtdchar_write(struct file *file, const char __user *buf, size_t c IOCTL calls for getting device parameters. ======================================================================*/ -static void mtdchar_erase_callback (struct erase_info *instr) -{ - wake_up((wait_queue_head_t *)instr->priv); -} static int otp_select_filemode(struct mtd_file_info *mfi, int mode) { @@ -709,11 +705,6 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg) if (!erase) ret = -ENOMEM; else { - wait_queue_head_t waitq; - DECLARE_WAITQUEUE(wait, current); - - init_waitqueue_head(&waitq); - if (cmd == MEMERASE64) { struct erase_info_user64 einfo64; @@ -736,30 +727,8 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg) erase->len = einfo32.length; } erase->mtd = mtd; - erase->callback = mtdchar_erase_callback; - erase->priv = (unsigned long)&waitq; - - /* - FIXME: Allow INTERRUPTIBLE. Which means - not having the wait_queue head on the stack. - - If the wq_head is on the stack, and we - leave because we got interrupted, then the - wq_head is no longer there when the - callback routine tries to wake us up. - */ + ret = mtd_erase(mtd, erase); - if (!ret) { - set_current_state(TASK_UNINTERRUPTIBLE); - add_wait_queue(&waitq, &wait); - if (erase->state != MTD_ERASE_DONE && - erase->state != MTD_ERASE_FAILED) - schedule(); - remove_wait_queue(&waitq, &wait); - set_current_state(TASK_RUNNING); - - ret = (erase->state == MTD_ERASE_FAILED)?-EIO:0; - } kfree(erase); } break; diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c index 60bf53df5454..caa09bf6e572 100644 --- a/drivers/mtd/mtdconcat.c +++ b/drivers/mtd/mtdconcat.c @@ -333,45 +333,6 @@ concat_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) return -EINVAL; } -static void concat_erase_callback(struct erase_info *instr) -{ - wake_up((wait_queue_head_t *) instr->priv); -} - -static int concat_dev_erase(struct mtd_info *mtd, struct erase_info *erase) -{ - int err; - wait_queue_head_t waitq; - DECLARE_WAITQUEUE(wait, current); - - /* - * This code was stol^H^H^H^Hinspired by mtdchar.c - */ - init_waitqueue_head(&waitq); - - erase->mtd = mtd; - erase->callback = concat_erase_callback; - erase->priv = (unsigned long) &waitq; - - /* - * FIXME: Allow INTERRUPTIBLE. Which means - * not having the wait_queue head on the stack. - */ - err = mtd_erase(mtd, erase); - if (!err) { - set_current_state(TASK_UNINTERRUPTIBLE); - add_wait_queue(&waitq, &wait); - if (erase->state != MTD_ERASE_DONE - && erase->state != MTD_ERASE_FAILED) - schedule(); - remove_wait_queue(&waitq, &wait); - set_current_state(TASK_RUNNING); - - err = (erase->state == MTD_ERASE_FAILED) ? -EIO : 0; - } - return err; -} - static int concat_erase(struct mtd_info *mtd, struct erase_info *instr) { struct mtd_concat *concat = CONCAT(mtd); @@ -466,7 +427,8 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr) erase->len = length; length -= erase->len; - if ((err = concat_dev_erase(subdev, erase))) { + erase->mtd = subdev; + if ((err = mtd_erase(subdev, erase))) { /* sanity check: should never happen since * block alignment has been checked above */ BUG_ON(err == -EINVAL); @@ -487,12 +449,8 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr) } instr->state = erase->state; kfree(erase); - if (err) - return err; - if (instr->callback) - instr->callback(instr); - return 0; + return err; } static int concat_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index c87859ff338b..f92ad02959eb 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -945,11 +945,9 @@ void __put_mtd_device(struct mtd_info *mtd) EXPORT_SYMBOL_GPL(__put_mtd_device); /* - * Erase is an asynchronous operation. Device drivers are supposed - * to call instr->callback() whenever the operation completes, even - * if it completes with a failure. - * Callers are supposed to pass a callback function and wait for it - * to be called before writing to the block. + * Erase is an synchronous operation. Device drivers are epected to return a + * negative error code if the operation failed and update instr->fail_addr + * to point the portion that was not properly erased. */ int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) { diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c index 97bb8f6304d4..028ded59297b 100644 --- a/drivers/mtd/mtdoops.c +++ b/drivers/mtd/mtdoops.c @@ -84,12 +84,6 @@ static int page_is_used(struct mtdoops_context *cxt, int page) return test_bit(page, cxt->oops_page_used); } -static void mtdoops_erase_callback(struct erase_info *done) -{ - wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv; - wake_up(wait_q); -} - static int mtdoops_erase_block(struct mtdoops_context *cxt, int offset) { struct mtd_info *mtd = cxt->mtd; @@ -97,34 +91,21 @@ static int mtdoops_erase_block(struct mtdoops_context *cxt, int offset) u32 start_page = start_page_offset / record_size; u32 erase_pages = mtd->erasesize / record_size; struct erase_info erase; - DECLARE_WAITQUEUE(wait, current); - wait_queue_head_t wait_q; int ret; int page; - init_waitqueue_head(&wait_q); erase.mtd = mtd; - erase.callback = mtdoops_erase_callback; erase.addr = offset; erase.len = mtd->erasesize; - erase.priv = (u_long)&wait_q; - - set_current_state(TASK_INTERRUPTIBLE); - add_wait_queue(&wait_q, &wait); ret = mtd_erase(mtd, &erase); if (ret) { - set_current_state(TASK_RUNNING); - remove_wait_queue(&wait_q, &wait); printk(KERN_WARNING "mtdoops: erase of region [0x%llx, 0x%llx] on \"%s\" failed\n", (unsigned long long)erase.addr, (unsigned long long)erase.len, mtddev); return ret; } - schedule(); /* Wait for erase to finish. */ - remove_wait_queue(&wait_q, &wait); - /* Mark pages as unused */ for (page = start_page; page < start_page + erase_pages; page++) mark_page_unused(cxt, page); diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 76cd21d1171b..ae1206633d9d 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -222,8 +222,6 @@ void mtd_erase_callback(struct erase_info *instr) instr->fail_addr -= part->offset; instr->addr -= part->offset; } - if (instr->callback) - instr->callback(instr); } EXPORT_SYMBOL_GPL(mtd_erase_callback); diff --git a/drivers/mtd/mtdswap.c b/drivers/mtd/mtdswap.c index 7eb0e1f4f980..d390324d102e 100644 --- a/drivers/mtd/mtdswap.c +++ b/drivers/mtd/mtdswap.c @@ -536,18 +536,10 @@ static void mtdswap_store_eb(struct mtdswap_dev *d, struct swap_eb *eb) mtdswap_rb_add(d, eb, MTDSWAP_HIFRAG); } - -static void mtdswap_erase_callback(struct erase_info *done) -{ - wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv; - wake_up(wait_q); -} - static int mtdswap_erase_block(struct mtdswap_dev *d, struct swap_eb *eb) { struct mtd_info *mtd = d->mtd; struct erase_info erase; - wait_queue_head_t wq; unsigned int retries = 0; int ret; @@ -556,14 +548,11 @@ static int mtdswap_erase_block(struct mtdswap_dev *d, struct swap_eb *eb) d->max_erase_count = eb->erase_count; retry: - init_waitqueue_head(&wq); memset(&erase, 0, sizeof(struct erase_info)); erase.mtd = mtd; - erase.callback = mtdswap_erase_callback; erase.addr = mtdswap_eb_offset(d, eb); erase.len = mtd->erasesize; - erase.priv = (u_long)&wq; ret = mtd_erase(mtd, &erase); if (ret) { @@ -582,27 +571,6 @@ retry: return -EIO; } - ret = wait_event_interruptible(wq, erase.state == MTD_ERASE_DONE || - erase.state == MTD_ERASE_FAILED); - if (ret) { - dev_err(d->dev, "Interrupted erase block %#llx erasure on %s\n", - erase.addr, mtd->name); - return -EINTR; - } - - if (erase.state == MTD_ERASE_FAILED) { - if (retries++ < MTDSWAP_ERASE_RETRIES) { - dev_warn(d->dev, - "erase of erase block %#llx on %s failed", - erase.addr, mtd->name); - yield(); - goto retry; - } - - mtdswap_handle_badblock(d, eb); - return -EIO; - } - return 0; } diff --git a/drivers/mtd/nftlmount.c b/drivers/mtd/nftlmount.c index 184c8fbfe465..07e122449759 100644 --- a/drivers/mtd/nftlmount.c +++ b/drivers/mtd/nftlmount.c @@ -331,9 +331,7 @@ int NFTL_formatblock(struct NFTLrecord *nftl, int block) instr->mtd = nftl->mbd.mtd; instr->addr = block * nftl->EraseSize; instr->len = nftl->EraseSize; - mtd_erase(mtd, instr); - - if (instr->state == MTD_ERASE_FAILED) { + if (mtd_erase(mtd, instr)) { printk("Error while formatting block %d\n", block); goto fail; } diff --git a/drivers/mtd/rfd_ftl.c b/drivers/mtd/rfd_ftl.c index d1cbf26db2c0..4e0b55cd08e2 100644 --- a/drivers/mtd/rfd_ftl.c +++ b/drivers/mtd/rfd_ftl.c @@ -266,91 +266,55 @@ static int rfd_ftl_readsect(struct mtd_blktrans_dev *dev, u_long sector, char *b return 0; } -static void erase_callback(struct erase_info *erase) -{ - struct partition *part; - u16 magic; - int i, rc; - size_t retlen; - - part = (struct partition*)erase->priv; - - i = (u32)erase->addr / part->block_size; - if (i >= part->total_blocks || part->blocks[i].offset != erase->addr || - erase->addr > UINT_MAX) { - printk(KERN_ERR PREFIX "erase callback for unknown offset %llx " - "on '%s'\n", (unsigned long long)erase->addr, part->mbd.mtd->name); - return; - } - - if (erase->state != MTD_ERASE_DONE) { - printk(KERN_WARNING PREFIX "erase failed at 0x%llx on '%s', " - "state %d\n", (unsigned long long)erase->addr, - part->mbd.mtd->name, erase->state); - - part->blocks[i].state = BLOCK_FAILED; - part->blocks[i].free_sectors = 0; - part->blocks[i].used_sectors = 0; - - kfree(erase); - - return; - } - - magic = cpu_to_le16(RFD_MAGIC); - - part->blocks[i].state = BLOCK_ERASED; - part->blocks[i].free_sectors = part->data_sectors_per_block; - part->blocks[i].used_sectors = 0; - part->blocks[i].erases++; - - rc = mtd_write(part->mbd.mtd, part->blocks[i].offset, sizeof(magic), - &retlen, (u_char *)&magic); - - if (!rc && retlen != sizeof(magic)) - rc = -EIO; - - if (rc) { - printk(KERN_ERR PREFIX "'%s': unable to write RFD " - "header at 0x%lx\n", - part->mbd.mtd->name, - part->blocks[i].offset); - part->blocks[i].state = BLOCK_FAILED; - } - else - part->blocks[i].state = BLOCK_OK; - - kfree(erase); -} - static int erase_block(struct partition *part, int block) { struct erase_info *erase; - int rc = -ENOMEM; + int rc; erase = kmalloc(sizeof(struct erase_info), GFP_KERNEL); if (!erase) - goto err; + return -ENOMEM; erase->mtd = part->mbd.mtd; - erase->callback = erase_callback; erase->addr = part->blocks[block].offset; erase->len = part->block_size; - erase->priv = (u_long)part; part->blocks[block].state = BLOCK_ERASING; part->blocks[block].free_sectors = 0; rc = mtd_erase(part->mbd.mtd, erase); - if (rc) { printk(KERN_ERR PREFIX "erase of region %llx,%llx on '%s' " "failed\n", (unsigned long long)erase->addr, (unsigned long long)erase->len, part->mbd.mtd->name); - kfree(erase); + part->blocks[block].state = BLOCK_FAILED; + part->blocks[block].free_sectors = 0; + part->blocks[block].used_sectors = 0; + } else { + u16 magic = cpu_to_le16(RFD_MAGIC); + size_t retlen; + + part->blocks[block].state = BLOCK_ERASED; + part->blocks[block].free_sectors = part->data_sectors_per_block; + part->blocks[block].used_sectors = 0; + part->blocks[block].erases++; + + rc = mtd_write(part->mbd.mtd, part->blocks[block].offset, + sizeof(magic), &retlen, (u_char *)&magic); + if (!rc && retlen != sizeof(magic)) + rc = -EIO; + + if (rc) { + pr_err(PREFIX "'%s': unable to write RFD header at 0x%lx\n", + part->mbd.mtd->name, part->blocks[block].offset); + part->blocks[block].state = BLOCK_FAILED; + } else { + part->blocks[block].state = BLOCK_OK; + } } -err: + kfree(erase); + return rc; } diff --git a/drivers/mtd/sm_ftl.c b/drivers/mtd/sm_ftl.c index 4237c7cebf02..c11156f9d96f 100644 --- a/drivers/mtd/sm_ftl.c +++ b/drivers/mtd/sm_ftl.c @@ -461,10 +461,8 @@ static int sm_erase_block(struct sm_ftl *ftl, int zone_num, uint16_t block, struct erase_info erase; erase.mtd = mtd; - erase.callback = sm_erase_callback; erase.addr = sm_mkoffset(ftl, zone_num, block, 0); erase.len = ftl->block_size; - erase.priv = (u_long)ftl; if (ftl->unstable) return -EIO; @@ -482,15 +480,6 @@ static int sm_erase_block(struct sm_ftl *ftl, int zone_num, uint16_t block, goto error; } - if (erase.state == MTD_ERASE_PENDING) - wait_for_completion(&ftl->erase_completion); - - if (erase.state != MTD_ERASE_DONE) { - sm_printk("erase of block %d in zone %d failed after wait", - block, zone_num); - goto error; - } - if (put_free) kfifo_in(&zone->free_sectors, (const unsigned char *)&block, sizeof(block)); @@ -501,12 +490,6 @@ error: return -EIO; } -static void sm_erase_callback(struct erase_info *self) -{ - struct sm_ftl *ftl = (struct sm_ftl *)self->priv; - complete(&ftl->erase_completion); -} - /* Thoroughly test that block is valid. */ static int sm_check_block(struct sm_ftl *ftl, int zone, int block) { @@ -1141,7 +1124,6 @@ static void sm_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd) mutex_init(&ftl->mutex); timer_setup(&ftl->timer, sm_cache_flush_timer, 0); INIT_WORK(&ftl->flush_work, sm_cache_flush_work); - init_completion(&ftl->erase_completion); /* Read media information */ if (sm_get_media_info(ftl, mtd)) { diff --git a/drivers/mtd/sm_ftl.h b/drivers/mtd/sm_ftl.h index 43bb7300785b..0a46d75cdc6a 100644 --- a/drivers/mtd/sm_ftl.h +++ b/drivers/mtd/sm_ftl.h @@ -53,9 +53,6 @@ struct sm_ftl { struct work_struct flush_work; struct timer_list timer; - /* Async erase stuff */ - struct completion erase_completion; - /* Geometry stuff */ int heads; int sectors; @@ -86,7 +83,6 @@ struct chs_entry { printk(KERN_DEBUG "sm_ftl" ": " format "\n", ## __VA_ARGS__) -static void sm_erase_callback(struct erase_info *self); static int sm_erase_block(struct sm_ftl *ftl, int zone_num, uint16_t block, int put_free); static void sm_mark_block_bad(struct sm_ftl *ftl, int zone_num, int block); diff --git a/drivers/mtd/tests/mtd_test.c b/drivers/mtd/tests/mtd_test.c index 3d0b8b5c1a53..0ac625e8f798 100644 --- a/drivers/mtd/tests/mtd_test.c +++ b/drivers/mtd/tests/mtd_test.c @@ -24,10 +24,6 @@ int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum) return err; } - if (ei.state == MTD_ERASE_FAILED) { - pr_info("some erase error occurred at EB %d\n", ebnum); - return -EIO; - } return 0; } diff --git a/drivers/mtd/tests/speedtest.c b/drivers/mtd/tests/speedtest.c index 0b89418a0888..f8e5dc11f943 100644 --- a/drivers/mtd/tests/speedtest.c +++ b/drivers/mtd/tests/speedtest.c @@ -70,12 +70,6 @@ static int multiblock_erase(int ebnum, int blocks) return err; } - if (ei.state == MTD_ERASE_FAILED) { - pr_err("some erase error occurred at EB %d," - "blocks %d\n", ebnum, blocks); - return -EIO; - } - return 0; } diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 8290432017ce..8843d26837b2 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -308,18 +308,6 @@ int ubi_io_write(struct ubi_device *ubi, const void *buf, int pnum, int offset, return err; } -/** - * erase_callback - MTD erasure call-back. - * @ei: MTD erase information object. - * - * Note, even though MTD erase interface is asynchronous, all the current - * implementations are synchronous anyway. - */ -static void erase_callback(struct erase_info *ei) -{ - wake_up_interruptible((wait_queue_head_t *)ei->priv); -} - /** * do_sync_erase - synchronously erase a physical eraseblock. * @ubi: UBI device description object @@ -333,7 +321,6 @@ static int do_sync_erase(struct ubi_device *ubi, int pnum) { int err, retries = 0; struct erase_info ei; - wait_queue_head_t wq; dbg_io("erase PEB %d", pnum); ubi_assert(pnum >= 0 && pnum < ubi->peb_count); @@ -344,14 +331,11 @@ static int do_sync_erase(struct ubi_device *ubi, int pnum) } retry: - init_waitqueue_head(&wq); memset(&ei, 0, sizeof(struct erase_info)); ei.mtd = ubi->mtd; ei.addr = (loff_t)pnum * ubi->peb_size; ei.len = ubi->peb_size; - ei.callback = erase_callback; - ei.priv = (unsigned long)&wq; err = mtd_erase(ubi->mtd, &ei); if (err) { @@ -366,25 +350,6 @@ retry: return err; } - err = wait_event_interruptible(wq, ei.state == MTD_ERASE_DONE || - ei.state == MTD_ERASE_FAILED); - if (err) { - ubi_err(ubi, "interrupted PEB %d erasure", pnum); - return -EINTR; - } - - if (ei.state == MTD_ERASE_FAILED) { - if (retries++ < UBI_IO_RETRIES) { - ubi_warn(ubi, "error while erasing PEB %d, retry", - pnum); - yield(); - goto retry; - } - ubi_err(ubi, "cannot erase PEB %d", pnum); - dump_stack(); - return -EIO; - } - err = ubi_self_check_all_ff(ubi, pnum, 0, ubi->peb_size); if (err) return err; diff --git a/fs/jffs2/erase.c b/fs/jffs2/erase.c index 4a6cf289be24..09bb6c00b869 100644 --- a/fs/jffs2/erase.c +++ b/fs/jffs2/erase.c @@ -21,14 +21,6 @@ #include #include "nodelist.h" -struct erase_priv_struct { - struct jffs2_eraseblock *jeb; - struct jffs2_sb_info *c; -}; - -#ifndef __ECOS -static void jffs2_erase_callback(struct erase_info *); -#endif static void jffs2_erase_failed(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t bad_offset); static void jffs2_erase_succeeded(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb); static void jffs2_mark_erased_block(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb); @@ -51,7 +43,7 @@ static void jffs2_erase_block(struct jffs2_sb_info *c, jffs2_dbg(1, "%s(): erase block %#08x (range %#08x-%#08x)\n", __func__, jeb->offset, jeb->offset, jeb->offset + c->sector_size); - instr = kmalloc(sizeof(struct erase_info) + sizeof(struct erase_priv_struct), GFP_KERNEL); + instr = kmalloc(sizeof(struct erase_info), GFP_KERNEL); if (!instr) { pr_warn("kmalloc for struct erase_info in jffs2_erase_block failed. Refiling block for later\n"); mutex_lock(&c->erase_free_sem); @@ -70,15 +62,13 @@ static void jffs2_erase_block(struct jffs2_sb_info *c, instr->mtd = c->mtd; instr->addr = jeb->offset; instr->len = c->sector_size; - instr->callback = jffs2_erase_callback; - instr->priv = (unsigned long)(&instr[1]); - - ((struct erase_priv_struct *)instr->priv)->jeb = jeb; - ((struct erase_priv_struct *)instr->priv)->c = c; ret = mtd_erase(c->mtd, instr); - if (!ret) + if (!ret) { + jffs2_erase_succeeded(c, jeb); + kfree(instr); return; + } bad_offset = instr->fail_addr; kfree(instr); @@ -214,22 +204,6 @@ static void jffs2_erase_failed(struct jffs2_sb_info *c, struct jffs2_eraseblock wake_up(&c->erase_wait); } -#ifndef __ECOS -static void jffs2_erase_callback(struct erase_info *instr) -{ - struct erase_priv_struct *priv = (void *)instr->priv; - - if(instr->state != MTD_ERASE_DONE) { - pr_warn("Erase at 0x%08llx finished, but state != MTD_ERASE_DONE. State is 0x%x instead.\n", - (unsigned long long)instr->addr, instr->state); - jffs2_erase_failed(priv->c, priv->jeb, instr->fail_addr); - } else { - jffs2_erase_succeeded(priv->c, priv->jeb); - } - kfree(instr); -} -#endif /* !__ECOS */ - /* Hmmm. Maybe we should accept the extra space it takes and make this a standard doubly-linked list? */ static inline void jffs2_remove_node_refs_from_ino_list(struct jffs2_sb_info *c, diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 2a407dc9beaa..5018437d7999 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -48,8 +48,6 @@ struct erase_info { uint64_t addr; uint64_t len; uint64_t fail_addr; - void (*callback) (struct erase_info *self); - u_long priv; u_char state; }; -- cgit v1.2.3 From 8ddfb47294c0f45a476a92ecf1e56cb5990c5468 Mon Sep 17 00:00:00 2001 From: Arend van Spriel Date: Fri, 9 Feb 2018 10:13:57 +0100 Subject: drivers: base: add description for .coredump() callback Commit 3c47d19ff4dc ("drivers: base: add coredump driver ops") added a new callback in struct device_driver, but not a kerneldoc description so here it is. Fixes: 3c47d19ff4dc ("drivers: base: add coredump driver ops") Signed-off-by: Arend van Spriel Signed-off-by: Greg Kroah-Hartman --- include/linux/device.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/device.h b/include/linux/device.h index b093405ed525..0b32a42db4ae 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -256,6 +256,7 @@ enum probe_type { * automatically. * @pm: Power management operations of the device which matched * this driver. + * @coredump: Called through sysfs to initiate a device coredump. * @p: Driver core's private data, no one other than the driver * core can touch this. * -- cgit v1.2.3 From 8f347c4232d5fc097599b711a3385722a6834005 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 12 Feb 2018 22:03:10 +0100 Subject: mtd: Unconditionally update ->fail_addr and ->addr in part_erase() ->fail_addr and ->addr can be updated no matter the result of parent->_erase(), we just need to remove the code doing the same thing in mtd_erase_callback() to avoid adjusting those fields twice. Note that this can be done because all MTD users have been converted to not pass an erase_info->callback() and are thus only taking the ->addr_fail and ->addr fields into account after part_erase() has returned. While we're at it, get rid of the erase_info->mtd field which was only needed to let mtd_erase_callback() get the partition device back. Signed-off-by: Boris Brezillon Reviewed-by: Richard Weinberger --- drivers/mtd/ftl.c | 1 - drivers/mtd/inftlmount.c | 3 --- drivers/mtd/mtdblock.c | 1 - drivers/mtd/mtdchar.c | 1 - drivers/mtd/mtdconcat.c | 1 - drivers/mtd/mtdoops.c | 1 - drivers/mtd/mtdpart.c | 16 ++++------------ drivers/mtd/mtdswap.c | 2 -- drivers/mtd/nand/nand_base.c | 1 - drivers/mtd/nand/nand_bbt.c | 1 - drivers/mtd/nftlmount.c | 1 - drivers/mtd/rfd_ftl.c | 1 - drivers/mtd/sm_ftl.c | 1 - drivers/mtd/tests/mtd_test.c | 1 - drivers/mtd/tests/speedtest.c | 1 - drivers/mtd/ubi/io.c | 1 - fs/jffs2/erase.c | 1 - include/linux/mtd/mtd.h | 3 ++- 18 files changed, 6 insertions(+), 32 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/ftl.c b/drivers/mtd/ftl.c index fcf9907e7987..0a6adfaec7b5 100644 --- a/drivers/mtd/ftl.c +++ b/drivers/mtd/ftl.c @@ -342,7 +342,6 @@ static int erase_xfer(partition_t *part, if (!erase) return -ENOMEM; - erase->mtd = part->mbd.mtd; erase->addr = xfer->Offset; erase->len = 1 << part->header.EraseUnitSize; diff --git a/drivers/mtd/inftlmount.c b/drivers/mtd/inftlmount.c index 0f47be4834d8..aab4f68bd36f 100644 --- a/drivers/mtd/inftlmount.c +++ b/drivers/mtd/inftlmount.c @@ -208,8 +208,6 @@ static int find_boot_record(struct INFTLrecord *inftl) if (ip->Reserved0 != ip->firstUnit) { struct erase_info *instr = &inftl->instr; - instr->mtd = inftl->mbd.mtd; - /* * Most likely this is using the * undocumented qiuck mount feature. @@ -385,7 +383,6 @@ int INFTL_formatblock(struct INFTLrecord *inftl, int block) _first_? */ /* Use async erase interface, test return code */ - instr->mtd = inftl->mbd.mtd; instr->addr = block * inftl->EraseSize; instr->len = inftl->mbd.mtd->erasesize; /* Erase one physical eraseblock at a time, even though the NAND api diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c index 7b2b7f651181..a5b1933c0490 100644 --- a/drivers/mtd/mtdblock.c +++ b/drivers/mtd/mtdblock.c @@ -65,7 +65,6 @@ static int erase_write (struct mtd_info *mtd, unsigned long pos, /* * First, let's erase the flash block. */ - erase.mtd = mtd; erase.addr = pos; erase.len = len; diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c index 2beb22dd6bbb..c06b33f80e75 100644 --- a/drivers/mtd/mtdchar.c +++ b/drivers/mtd/mtdchar.c @@ -726,7 +726,6 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg) erase->addr = einfo32.start; erase->len = einfo32.length; } - erase->mtd = mtd; ret = mtd_erase(mtd, erase); kfree(erase); diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c index caa09bf6e572..93c47e56d9d8 100644 --- a/drivers/mtd/mtdconcat.c +++ b/drivers/mtd/mtdconcat.c @@ -427,7 +427,6 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr) erase->len = length; length -= erase->len; - erase->mtd = subdev; if ((err = mtd_erase(subdev, erase))) { /* sanity check: should never happen since * block alignment has been checked above */ diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c index 028ded59297b..9f25111fd559 100644 --- a/drivers/mtd/mtdoops.c +++ b/drivers/mtd/mtdoops.c @@ -94,7 +94,6 @@ static int mtdoops_erase_block(struct mtdoops_context *cxt, int offset) int ret; int page; - erase.mtd = mtd; erase.addr = offset; erase.len = mtd->erasesize; diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index ae1206633d9d..1c07a6f0dfe5 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -205,23 +205,15 @@ static int part_erase(struct mtd_info *mtd, struct erase_info *instr) instr->addr += part->offset; ret = part->parent->_erase(part->parent, instr); - if (ret) { - if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) - instr->fail_addr -= part->offset; - instr->addr -= part->offset; - } + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; + return ret; } void mtd_erase_callback(struct erase_info *instr) { - if (instr->mtd->_erase == part_erase) { - struct mtd_part *part = mtd_to_part(instr->mtd); - - if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) - instr->fail_addr -= part->offset; - instr->addr -= part->offset; - } } EXPORT_SYMBOL_GPL(mtd_erase_callback); diff --git a/drivers/mtd/mtdswap.c b/drivers/mtd/mtdswap.c index d390324d102e..7161f8a17f62 100644 --- a/drivers/mtd/mtdswap.c +++ b/drivers/mtd/mtdswap.c @@ -549,8 +549,6 @@ static int mtdswap_erase_block(struct mtdswap_dev *d, struct swap_eb *eb) retry: memset(&erase, 0, sizeof(struct erase_info)); - - erase.mtd = mtd; erase.addr = mtdswap_eb_offset(d, eb); erase.len = mtd->erasesize; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index e70ca16a5118..16c8bc06975d 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -527,7 +527,6 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) /* Attempt erase before marking OOB */ memset(&einfo, 0, sizeof(einfo)); - einfo.mtd = mtd; einfo.addr = ofs; einfo.len = 1ULL << chip->phys_erase_shift; nand_erase_nand(mtd, &einfo, 0); diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 36092850be2c..d9f4ceff2568 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -852,7 +852,6 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, } memset(&einfo, 0, sizeof(einfo)); - einfo.mtd = mtd; einfo.addr = to; einfo.len = 1 << this->bbt_erase_shift; res = nand_erase_nand(mtd, &einfo, 1); diff --git a/drivers/mtd/nftlmount.c b/drivers/mtd/nftlmount.c index 07e122449759..d8f6dba01c87 100644 --- a/drivers/mtd/nftlmount.c +++ b/drivers/mtd/nftlmount.c @@ -328,7 +328,6 @@ int NFTL_formatblock(struct NFTLrecord *nftl, int block) memset(instr, 0, sizeof(struct erase_info)); /* XXX: use async erase interface, XXX: test return code */ - instr->mtd = nftl->mbd.mtd; instr->addr = block * nftl->EraseSize; instr->len = nftl->EraseSize; if (mtd_erase(mtd, instr)) { diff --git a/drivers/mtd/rfd_ftl.c b/drivers/mtd/rfd_ftl.c index 4e0b55cd08e2..df27f24ce0fa 100644 --- a/drivers/mtd/rfd_ftl.c +++ b/drivers/mtd/rfd_ftl.c @@ -275,7 +275,6 @@ static int erase_block(struct partition *part, int block) if (!erase) return -ENOMEM; - erase->mtd = part->mbd.mtd; erase->addr = part->blocks[block].offset; erase->len = part->block_size; diff --git a/drivers/mtd/sm_ftl.c b/drivers/mtd/sm_ftl.c index c11156f9d96f..72740ede9f05 100644 --- a/drivers/mtd/sm_ftl.c +++ b/drivers/mtd/sm_ftl.c @@ -460,7 +460,6 @@ static int sm_erase_block(struct sm_ftl *ftl, int zone_num, uint16_t block, struct mtd_info *mtd = ftl->trans->mtd; struct erase_info erase; - erase.mtd = mtd; erase.addr = sm_mkoffset(ftl, zone_num, block, 0); erase.len = ftl->block_size; diff --git a/drivers/mtd/tests/mtd_test.c b/drivers/mtd/tests/mtd_test.c index 0ac625e8f798..c84250beffdc 100644 --- a/drivers/mtd/tests/mtd_test.c +++ b/drivers/mtd/tests/mtd_test.c @@ -14,7 +14,6 @@ int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum) loff_t addr = (loff_t)ebnum * mtd->erasesize; memset(&ei, 0, sizeof(struct erase_info)); - ei.mtd = mtd; ei.addr = addr; ei.len = mtd->erasesize; diff --git a/drivers/mtd/tests/speedtest.c b/drivers/mtd/tests/speedtest.c index f8e5dc11f943..20edb3b49c77 100644 --- a/drivers/mtd/tests/speedtest.c +++ b/drivers/mtd/tests/speedtest.c @@ -59,7 +59,6 @@ static int multiblock_erase(int ebnum, int blocks) loff_t addr = (loff_t)ebnum * mtd->erasesize; memset(&ei, 0, sizeof(struct erase_info)); - ei.mtd = mtd; ei.addr = addr; ei.len = mtd->erasesize * blocks; diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 8843d26837b2..0e3a76a9e2f8 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -333,7 +333,6 @@ static int do_sync_erase(struct ubi_device *ubi, int pnum) retry: memset(&ei, 0, sizeof(struct erase_info)); - ei.mtd = ubi->mtd; ei.addr = (loff_t)pnum * ubi->peb_size; ei.len = ubi->peb_size; diff --git a/fs/jffs2/erase.c b/fs/jffs2/erase.c index 09bb6c00b869..83b8f06b4a64 100644 --- a/fs/jffs2/erase.c +++ b/fs/jffs2/erase.c @@ -59,7 +59,6 @@ static void jffs2_erase_block(struct jffs2_sb_info *c, memset(instr, 0, sizeof(*instr)); - instr->mtd = c->mtd; instr->addr = jeb->offset; instr->len = c->sector_size; diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 5018437d7999..4cbb7f555244 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -38,13 +38,14 @@ #define MTD_FAIL_ADDR_UNKNOWN -1LL +struct mtd_info; + /* * If the erase fails, fail_addr might indicate exactly which block failed. If * fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level * or was not specific to any particular block. */ struct erase_info { - struct mtd_info *mtd; uint64_t addr; uint64_t len; uint64_t fail_addr; -- cgit v1.2.3 From 48962f5c6fffcb676dd6ebd70f7869cfc6cc8356 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Tue, 13 Mar 2018 16:26:46 -0600 Subject: RDMA/mlx4: Move flag constants to uapi header MLX4_USER_DEV_CAP_LARGE_CQE (via mlx4_ib_alloc_ucontext_resp.dev_caps) and MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET (via mlx4_uverbs_ex_query_device_resp.comp_mask) are copied directly to userspace and form part of the uAPI. Move them to the uapi header where they belong. Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/mlx4/main.c | 2 +- drivers/infiniband/hw/mlx4/mlx4_ib.h | 4 ---- drivers/net/ethernet/mellanox/mlx4/fw.c | 1 + drivers/net/ethernet/mellanox/mlx4/main.c | 1 + include/linux/mlx4/device.h | 4 ---- include/uapi/rdma/mlx4-abi.h | 8 ++++++++ 6 files changed, 11 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c index c9eaaa216891..f57229b85536 100644 --- a/drivers/infiniband/hw/mlx4/main.c +++ b/drivers/infiniband/hw/mlx4/main.c @@ -575,7 +575,7 @@ static int mlx4_ib_query_device(struct ib_device *ibdev, if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { resp.response_length += sizeof(resp.hca_core_clock_offset); if (!err && !mlx4_is_slave(dev->dev)) { - resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP; + resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; } } diff --git a/drivers/infiniband/hw/mlx4/mlx4_ib.h b/drivers/infiniband/hw/mlx4/mlx4_ib.h index d0640bd79679..87c47b1dd870 100644 --- a/drivers/infiniband/hw/mlx4/mlx4_ib.h +++ b/drivers/infiniband/hw/mlx4/mlx4_ib.h @@ -641,10 +641,6 @@ struct mlx4_uverbs_ex_query_device { __u32 reserved; }; -enum query_device_resp_mask { - QUERY_DEVICE_RESP_MASK_TIMESTAMP = 1UL << 0, -}; - static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev) { return container_of(ibdev, struct mlx4_ib_dev, ib_dev); diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c index 634f603f941c..de6b3d416148 100644 --- a/drivers/net/ethernet/mellanox/mlx4/fw.c +++ b/drivers/net/ethernet/mellanox/mlx4/fw.c @@ -37,6 +37,7 @@ #include #include #include +#include #include "fw.h" #include "icm.h" diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c index 4d84cab77105..958619ff24ae 100644 --- a/drivers/net/ethernet/mellanox/mlx4/main.c +++ b/drivers/net/ethernet/mellanox/mlx4/main.c @@ -46,6 +46,7 @@ #include #include +#include #include #include diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index a9b5fed8f7c6..81d0799b6091 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -256,10 +256,6 @@ enum { MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 }; -enum { - MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 -}; - enum { MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, diff --git a/include/uapi/rdma/mlx4-abi.h b/include/uapi/rdma/mlx4-abi.h index d84616adff32..be58594cec87 100644 --- a/include/uapi/rdma/mlx4-abi.h +++ b/include/uapi/rdma/mlx4-abi.h @@ -59,6 +59,10 @@ struct mlx4_ib_alloc_ucontext_resp_v3 { __u16 bf_regs_per_page; }; +enum { + MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0, +}; + struct mlx4_ib_alloc_ucontext_resp { __u32 dev_caps; __u32 qp_tab_size; @@ -162,6 +166,10 @@ struct mlx4_ib_rss_caps { __u8 reserved[7]; }; +enum query_device_resp_mask { + MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, +}; + struct mlx4_uverbs_ex_query_device_resp { __u32 comp_mask; __u32 response_length; -- cgit v1.2.3 From 95dd77580ccd66a0da96e6d4696945b8cea39431 Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Wed, 14 Mar 2018 18:20:29 -0500 Subject: fs: Teach path_connected to handle nfs filesystems with multiple roots. On nfsv2 and nfsv3 the nfs server can export subsets of the same filesystem and report the same filesystem identifier, so that the nfs client can know they are the same filesystem. The subsets can be from disjoint directory trees. The nfsv2 and nfsv3 filesystems provides no way to find the common root of all directory trees exported form the server with the same filesystem identifier. The practical result is that in struct super s_root for nfs s_root is not necessarily the root of the filesystem. The nfs mount code sets s_root to the root of the first subset of the nfs filesystem that the kernel mounts. This effects the dcache invalidation code in generic_shutdown_super currently called shrunk_dcache_for_umount and that code for years has gone through an additional list of dentries that might be dentry trees that need to be freed to accomodate nfs. When I wrote path_connected I did not realize nfs was so special, and it's hueristic for avoiding calling is_subdir can fail. The practical case where this fails is when there is a move of a directory from the subtree exposed by one nfs mount to the subtree exposed by another nfs mount. This move can happen either locally or remotely. With the remote case requiring that the move directory be cached before the move and that after the move someone walks the path to where the move directory now exists and in so doing causes the already cached directory to be moved in the dcache through the magic of d_splice_alias. If someone whose working directory is in the move directory or a subdirectory and now starts calling .. from the initial mount of nfs (where s_root == mnt_root), then path_connected as a heuristic will not bother with the is_subdir check. As s_root really is not the root of the nfs filesystem this heuristic is wrong, and the path may actually not be connected and path_connected can fail. The is_subdir function might be cheap enough that we can call it unconditionally. Verifying that will take some benchmarking and the result may not be the same on all kernels this fix needs to be backported to. So I am avoiding that for now. Filesystems with snapshots such as nilfs and btrfs do something similar. But as the directory tree of the snapshots are disjoint from one another and from the main directory tree rename won't move things between them and this problem will not occur. Cc: stable@vger.kernel.org Reported-by: Al Viro Fixes: 397d425dc26d ("vfs: Test for and handle paths that are unreachable from their mnt_root") Signed-off-by: "Eric W. Biederman" Signed-off-by: Al Viro --- fs/namei.c | 5 +++-- fs/nfs/super.c | 2 ++ include/linux/fs.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/fs/namei.c b/fs/namei.c index 921ae32dbc80..cafa365eeb70 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -559,9 +559,10 @@ static int __nd_alloc_stack(struct nameidata *nd) static bool path_connected(const struct path *path) { struct vfsmount *mnt = path->mnt; + struct super_block *sb = mnt->mnt_sb; - /* Only bind mounts can have disconnected paths */ - if (mnt->mnt_root == mnt->mnt_sb->s_root) + /* Bind mounts and multi-root filesystems can have disconnected paths */ + if (!(sb->s_iflags & SB_I_MULTIROOT) && (mnt->mnt_root == sb->s_root)) return true; return is_subdir(path->dentry, mnt->mnt_root); diff --git a/fs/nfs/super.c b/fs/nfs/super.c index 29bacdc56f6a..5e470e233c83 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -2631,6 +2631,8 @@ struct dentry *nfs_fs_mount_common(struct nfs_server *server, /* initial superblock/root creation */ mount_info->fill_super(s, mount_info); nfs_get_cache_cookie(s, mount_info->parsed, mount_info->cloned); + if (!(server->flags & NFS_MOUNT_UNSHARED)) + s->s_iflags |= SB_I_MULTIROOT; } mntroot = nfs_get_root(s, mount_info->mntfh, dev_name); diff --git a/include/linux/fs.h b/include/linux/fs.h index 2a815560fda0..0430e03febaa 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1317,6 +1317,7 @@ extern int send_sigurg(struct fown_struct *fown); #define SB_I_CGROUPWB 0x00000001 /* cgroup-aware writeback enabled */ #define SB_I_NOEXEC 0x00000002 /* Ignore executables on this fs */ #define SB_I_NODEV 0x00000004 /* Ignore devices on this fs */ +#define SB_I_MULTIROOT 0x00000008 /* Multiple roots to the dentry tree */ /* sb->s_iflags to limit user namespace mounts */ #define SB_I_USERNS_VISIBLE 0x00000010 /* fstype already mounted */ -- cgit v1.2.3 From 4ba66a9760722ccbb691b8f7116cad2f791cca7b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 7 Mar 2018 22:23:24 +0100 Subject: arch: remove blackfin port The Analog Devices Blackfin port was added in 2007 and was rather active for a while, but all work on it has come to a standstill over time, as Analog have changed their product line-up. Aaron Wu confirmed that the architecture port is no longer relevant, and multiple people suggested removing blackfin independently because of some of its oddities like a non-working SMP port, and the amount of duplication between the chip variants, which cause extra work when doing cross-architecture changes. Link: https://docs.blackfin.uclinux.org/ Acked-by: Aaron Wu Acked-by: Bryan Wu Cc: Steven Miao Cc: Mike Frysinger Signed-off-by: Arnd Bergmann --- Documentation/00-INDEX | 2 - Documentation/admin-guide/kernel-parameters.rst | 1 - Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/blackfin/00-INDEX | 6 - Documentation/blackfin/bfin-gpio-notes.txt | 71 - Documentation/blackfin/bfin-spi-notes.txt | 16 - MAINTAINERS | 45 - arch/blackfin/Clear_BSD.txt | 33 - arch/blackfin/Kconfig | 1463 -------- arch/blackfin/Kconfig.debug | 258 -- arch/blackfin/Makefile | 168 - arch/blackfin/boot/.gitignore | 3 - arch/blackfin/boot/Makefile | 71 - arch/blackfin/boot/install.sh | 57 - arch/blackfin/configs/BF518F-EZBRD_defconfig | 121 - arch/blackfin/configs/BF526-EZBRD_defconfig | 158 - arch/blackfin/configs/BF527-AD7160-EVAL_defconfig | 104 - arch/blackfin/configs/BF527-EZKIT-V2_defconfig | 188 - arch/blackfin/configs/BF527-EZKIT_defconfig | 181 - arch/blackfin/configs/BF527-TLL6527M_defconfig | 178 - arch/blackfin/configs/BF533-EZKIT_defconfig | 114 - arch/blackfin/configs/BF533-STAMP_defconfig | 124 - arch/blackfin/configs/BF537-STAMP_defconfig | 136 - arch/blackfin/configs/BF538-EZKIT_defconfig | 133 - arch/blackfin/configs/BF548-EZKIT_defconfig | 207 -- arch/blackfin/configs/BF561-ACVILON_defconfig | 149 - arch/blackfin/configs/BF561-EZKIT-SMP_defconfig | 112 - arch/blackfin/configs/BF561-EZKIT_defconfig | 114 - arch/blackfin/configs/BF609-EZKIT_defconfig | 154 - arch/blackfin/configs/BlackStamp_defconfig | 108 - arch/blackfin/configs/CM-BF527_defconfig | 129 - arch/blackfin/configs/CM-BF533_defconfig | 76 - arch/blackfin/configs/CM-BF537E_defconfig | 107 - arch/blackfin/configs/CM-BF537U_defconfig | 96 - arch/blackfin/configs/CM-BF548_defconfig | 170 - arch/blackfin/configs/CM-BF561_defconfig | 104 - arch/blackfin/configs/DNP5370_defconfig | 118 - arch/blackfin/configs/H8606_defconfig | 87 - arch/blackfin/configs/IP0X_defconfig | 91 - arch/blackfin/configs/PNAV-10_defconfig | 111 - arch/blackfin/configs/SRV1_defconfig | 88 - arch/blackfin/configs/TCM-BF518_defconfig | 131 - arch/blackfin/configs/TCM-BF537_defconfig | 95 - arch/blackfin/include/asm/Kbuild | 28 - arch/blackfin/include/asm/asm-offsets.h | 1 - arch/blackfin/include/asm/atomic.h | 47 - arch/blackfin/include/asm/barrier.h | 86 - arch/blackfin/include/asm/bfin-global.h | 95 - arch/blackfin/include/asm/bfin-lq035q1.h | 40 - arch/blackfin/include/asm/bfin5xx_spi.h | 86 - arch/blackfin/include/asm/bfin_can.h | 728 ---- arch/blackfin/include/asm/bfin_dma.h | 165 - arch/blackfin/include/asm/bfin_pfmon.h | 44 - arch/blackfin/include/asm/bfin_ppi.h | 181 - arch/blackfin/include/asm/bfin_sdh.h | 161 - arch/blackfin/include/asm/bfin_serial.h | 429 --- arch/blackfin/include/asm/bfin_simple_timer.h | 27 - arch/blackfin/include/asm/bfin_sport.h | 71 - arch/blackfin/include/asm/bfin_sport3.h | 107 - arch/blackfin/include/asm/bfin_twi.h | 214 -- arch/blackfin/include/asm/bfin_watchdog.h | 30 - arch/blackfin/include/asm/bfrom.h | 90 - arch/blackfin/include/asm/bitops.h | 140 - arch/blackfin/include/asm/blackfin.h | 88 - arch/blackfin/include/asm/bug.h | 73 - arch/blackfin/include/asm/cache.h | 70 - arch/blackfin/include/asm/cacheflush.h | 118 - arch/blackfin/include/asm/cdef_LPBlackfin.h | 309 -- arch/blackfin/include/asm/checksum.h | 44 - arch/blackfin/include/asm/clocks.h | 74 - arch/blackfin/include/asm/cmpxchg.h | 132 - arch/blackfin/include/asm/context.S | 407 --- arch/blackfin/include/asm/cplb.h | 153 - arch/blackfin/include/asm/cplbinit.h | 66 - arch/blackfin/include/asm/cpu.h | 24 - arch/blackfin/include/asm/def_LPBlackfin.h | 697 ---- arch/blackfin/include/asm/delay.h | 51 - arch/blackfin/include/asm/dma-mapping.h | 46 - arch/blackfin/include/asm/dma.h | 349 -- arch/blackfin/include/asm/dpmc.h | 794 ----- arch/blackfin/include/asm/early_printk.h | 36 - arch/blackfin/include/asm/elf.h | 135 - arch/blackfin/include/asm/entry.h | 178 - arch/blackfin/include/asm/exec.h | 1 - arch/blackfin/include/asm/fixed_code.h | 30 - arch/blackfin/include/asm/flat.h | 62 - arch/blackfin/include/asm/ftrace.h | 73 - arch/blackfin/include/asm/gpio.h | 234 -- arch/blackfin/include/asm/gptimers.h | 337 -- arch/blackfin/include/asm/hardirq.h | 17 - arch/blackfin/include/asm/io.h | 49 - arch/blackfin/include/asm/ipipe.h | 209 -- arch/blackfin/include/asm/ipipe_base.h | 75 - arch/blackfin/include/asm/irq.h | 41 - arch/blackfin/include/asm/irq_handler.h | 66 - arch/blackfin/include/asm/irqflags.h | 289 -- arch/blackfin/include/asm/kgdb.h | 169 - arch/blackfin/include/asm/l1layout.h | 37 - arch/blackfin/include/asm/linkage.h | 13 - arch/blackfin/include/asm/mem_init.h | 500 --- arch/blackfin/include/asm/mem_map.h | 84 - arch/blackfin/include/asm/mmu.h | 36 - arch/blackfin/include/asm/mmu_context.h | 218 -- arch/blackfin/include/asm/module.h | 22 - arch/blackfin/include/asm/nand.h | 40 - arch/blackfin/include/asm/nmi.h | 14 - arch/blackfin/include/asm/page.h | 22 - arch/blackfin/include/asm/page_offset.h | 11 - arch/blackfin/include/asm/pci.h | 13 - arch/blackfin/include/asm/pda.h | 73 - arch/blackfin/include/asm/perf_event.h | 1 - arch/blackfin/include/asm/pgtable.h | 104 - arch/blackfin/include/asm/pm.h | 31 - arch/blackfin/include/asm/portmux.h | 1204 ------- arch/blackfin/include/asm/processor.h | 145 - arch/blackfin/include/asm/pseudo_instructions.h | 18 - arch/blackfin/include/asm/ptrace.h | 42 - arch/blackfin/include/asm/reboot.h | 20 - arch/blackfin/include/asm/rwlock.h | 7 - arch/blackfin/include/asm/scb.h | 21 - arch/blackfin/include/asm/sections.h | 67 - arch/blackfin/include/asm/segment.h | 13 - arch/blackfin/include/asm/smp.h | 54 - arch/blackfin/include/asm/spinlock.h | 81 - arch/blackfin/include/asm/spinlock_types.h | 28 - arch/blackfin/include/asm/string.h | 38 - arch/blackfin/include/asm/switch_to.h | 39 - arch/blackfin/include/asm/syscall.h | 96 - arch/blackfin/include/asm/thread_info.h | 98 - arch/blackfin/include/asm/time.h | 46 - arch/blackfin/include/asm/timex.h | 23 - arch/blackfin/include/asm/tlb.h | 22 - arch/blackfin/include/asm/tlbflush.h | 2 - arch/blackfin/include/asm/trace.h | 106 - arch/blackfin/include/asm/traps.h | 131 - arch/blackfin/include/asm/uaccess.h | 234 -- arch/blackfin/include/asm/unistd.h | 22 - arch/blackfin/include/asm/vga.h | 1 - arch/blackfin/include/mach-common/irq.h | 58 - arch/blackfin/include/mach-common/pll.h | 86 - arch/blackfin/include/mach-common/ports-a.h | 26 - arch/blackfin/include/mach-common/ports-b.h | 26 - arch/blackfin/include/mach-common/ports-c.h | 26 - arch/blackfin/include/mach-common/ports-d.h | 26 - arch/blackfin/include/mach-common/ports-e.h | 26 - arch/blackfin/include/mach-common/ports-f.h | 26 - arch/blackfin/include/mach-common/ports-g.h | 26 - arch/blackfin/include/mach-common/ports-h.h | 26 - arch/blackfin/include/mach-common/ports-i.h | 26 - arch/blackfin/include/mach-common/ports-j.h | 26 - arch/blackfin/include/uapi/asm/Kbuild | 25 - arch/blackfin/include/uapi/asm/bfin_sport.h | 137 - arch/blackfin/include/uapi/asm/byteorder.h | 7 - arch/blackfin/include/uapi/asm/cachectl.h | 21 - arch/blackfin/include/uapi/asm/fcntl.h | 18 - arch/blackfin/include/uapi/asm/fixed_code.h | 39 - arch/blackfin/include/uapi/asm/ioctls.h | 8 - arch/blackfin/include/uapi/asm/poll.h | 17 - arch/blackfin/include/uapi/asm/posix_types.h | 31 - arch/blackfin/include/uapi/asm/ptrace.h | 171 - arch/blackfin/include/uapi/asm/sigcontext.h | 62 - arch/blackfin/include/uapi/asm/siginfo.h | 16 - arch/blackfin/include/uapi/asm/signal.h | 8 - arch/blackfin/include/uapi/asm/stat.h | 70 - arch/blackfin/include/uapi/asm/swab.h | 51 - arch/blackfin/include/uapi/asm/unistd.h | 448 --- arch/blackfin/kernel/.gitignore | 1 - arch/blackfin/kernel/Makefile | 44 - arch/blackfin/kernel/asm-offsets.c | 164 - arch/blackfin/kernel/bfin_dma.c | 612 ---- arch/blackfin/kernel/bfin_gpio.c | 1208 ------- arch/blackfin/kernel/bfin_ksyms.c | 126 - arch/blackfin/kernel/cplb-mpu/Makefile | 10 - arch/blackfin/kernel/cplb-mpu/cplbinit.c | 102 - arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 379 --- arch/blackfin/kernel/cplb-nompu/Makefile | 11 - arch/blackfin/kernel/cplb-nompu/cplbinit.c | 212 -- arch/blackfin/kernel/cplb-nompu/cplbmgr.c | 227 -- arch/blackfin/kernel/cplbinfo.c | 180 - arch/blackfin/kernel/debug-mmrs.c | 1891 ---------- arch/blackfin/kernel/dma-mapping.c | 172 - arch/blackfin/kernel/dumpstack.c | 177 - arch/blackfin/kernel/early_printk.c | 271 -- arch/blackfin/kernel/entry.S | 59 - arch/blackfin/kernel/exception.c | 45 - arch/blackfin/kernel/fixed_code.S | 155 - arch/blackfin/kernel/flat.c | 84 - arch/blackfin/kernel/ftrace-entry.S | 207 -- arch/blackfin/kernel/ftrace.c | 125 - arch/blackfin/kernel/gptimers.c | 383 --- arch/blackfin/kernel/ipipe.c | 397 --- arch/blackfin/kernel/irqchip.c | 132 - arch/blackfin/kernel/kgdb.c | 473 --- arch/blackfin/kernel/kgdb_test.c | 114 - arch/blackfin/kernel/module.c | 292 -- arch/blackfin/kernel/nmi.c | 287 -- arch/blackfin/kernel/perf_event.c | 482 --- arch/blackfin/kernel/process.c | 438 --- arch/blackfin/kernel/pseudodbg.c | 191 -- arch/blackfin/kernel/ptrace.c | 413 --- arch/blackfin/kernel/reboot.c | 115 - arch/blackfin/kernel/setup.c | 1468 -------- arch/blackfin/kernel/shadow_console.c | 111 - arch/blackfin/kernel/signal.c | 287 -- arch/blackfin/kernel/stacktrace.c | 54 - arch/blackfin/kernel/sys_bfin.c | 88 - arch/blackfin/kernel/time-ts.c | 400 --- arch/blackfin/kernel/time.c | 160 - arch/blackfin/kernel/trace.c | 988 ------ arch/blackfin/kernel/traps.c | 585 ---- arch/blackfin/kernel/vmlinux.lds.S | 271 -- arch/blackfin/lib/Makefile | 12 - arch/blackfin/lib/ashldi3.c | 35 - arch/blackfin/lib/ashrdi3.c | 36 - arch/blackfin/lib/divsi3.S | 199 -- arch/blackfin/lib/gcclib.h | 24 - arch/blackfin/lib/ins.S | 118 - arch/blackfin/lib/lshrdi3.c | 35 - arch/blackfin/lib/memchr.S | 47 - arch/blackfin/lib/memcmp.S | 92 - arch/blackfin/lib/memcpy.S | 124 - arch/blackfin/lib/memmove.S | 93 - arch/blackfin/lib/memset.S | 87 - arch/blackfin/lib/modsi3.S | 57 - arch/blackfin/lib/muldi3.S | 74 - arch/blackfin/lib/outs.S | 68 - arch/blackfin/lib/smulsi3_highpart.S | 38 - arch/blackfin/lib/strcmp.S | 43 - arch/blackfin/lib/strcpy.S | 35 - arch/blackfin/lib/strncmp.S | 52 - arch/blackfin/lib/strncpy.S | 85 - arch/blackfin/lib/udivsi3.S | 277 -- arch/blackfin/lib/umodsi3.S | 49 - arch/blackfin/lib/umulsi3_highpart.S | 31 - arch/blackfin/mach-bf518/Kconfig | 320 -- arch/blackfin/mach-bf518/Makefile | 5 - arch/blackfin/mach-bf518/boards/Kconfig | 18 - arch/blackfin/mach-bf518/boards/Makefile | 6 - arch/blackfin/mach-bf518/boards/ezbrd.c | 794 ----- arch/blackfin/mach-bf518/boards/tcm-bf518.c | 739 ---- arch/blackfin/mach-bf518/dma.c | 98 - arch/blackfin/mach-bf518/include/mach/anomaly.h | 170 - arch/blackfin/mach-bf518/include/mach/bf518.h | 214 -- .../blackfin/mach-bf518/include/mach/bfin_serial.h | 14 - arch/blackfin/mach-bf518/include/mach/blackfin.h | 43 - arch/blackfin/mach-bf518/include/mach/cdefBF512.h | 1043 ------ arch/blackfin/mach-bf518/include/mach/cdefBF514.h | 80 - arch/blackfin/mach-bf518/include/mach/cdefBF516.h | 178 - arch/blackfin/mach-bf518/include/mach/cdefBF518.h | 56 - arch/blackfin/mach-bf518/include/mach/defBF512.h | 1304 ------- arch/blackfin/mach-bf518/include/mach/defBF514.h | 48 - arch/blackfin/mach-bf518/include/mach/defBF516.h | 392 --- arch/blackfin/mach-bf518/include/mach/defBF518.h | 67 - arch/blackfin/mach-bf518/include/mach/dma.h | 33 - arch/blackfin/mach-bf518/include/mach/gpio.h | 62 - arch/blackfin/mach-bf518/include/mach/irq.h | 205 -- arch/blackfin/mach-bf518/include/mach/mem_map.h | 70 - arch/blackfin/mach-bf518/include/mach/pll.h | 1 - arch/blackfin/mach-bf518/include/mach/portmux.h | 223 -- arch/blackfin/mach-bf518/ints-priority.c | 78 - arch/blackfin/mach-bf527/Kconfig | 325 -- arch/blackfin/mach-bf527/Makefile | 5 - arch/blackfin/mach-bf527/boards/Kconfig | 38 - arch/blackfin/mach-bf527/boards/Makefile | 11 - arch/blackfin/mach-bf527/boards/ad7160eval.c | 868 ----- arch/blackfin/mach-bf527/boards/cm_bf527.c | 992 ------ arch/blackfin/mach-bf527/boards/ezbrd.c | 891 ----- arch/blackfin/mach-bf527/boards/ezkit.c | 1335 -------- arch/blackfin/mach-bf527/boards/tll6527m.c | 946 ----- arch/blackfin/mach-bf527/dma.c | 98 - arch/blackfin/mach-bf527/include/mach/anomaly.h | 290 -- arch/blackfin/mach-bf527/include/mach/bf527.h | 237 -- .../blackfin/mach-bf527/include/mach/bfin_serial.h | 14 - arch/blackfin/mach-bf527/include/mach/blackfin.h | 37 - arch/blackfin/mach-bf527/include/mach/cdefBF522.h | 1095 ------ arch/blackfin/mach-bf527/include/mach/cdefBF525.h | 421 --- arch/blackfin/mach-bf527/include/mach/cdefBF527.h | 178 - arch/blackfin/mach-bf527/include/mach/defBF522.h | 1309 ------- arch/blackfin/mach-bf527/include/mach/defBF525.h | 678 ---- arch/blackfin/mach-bf527/include/mach/defBF527.h | 391 --- arch/blackfin/mach-bf527/include/mach/dma.h | 38 - arch/blackfin/mach-bf527/include/mach/gpio.h | 69 - arch/blackfin/mach-bf527/include/mach/irq.h | 204 -- arch/blackfin/mach-bf527/include/mach/mem_map.h | 70 - arch/blackfin/mach-bf527/include/mach/pll.h | 1 - arch/blackfin/mach-bf527/include/mach/portmux.h | 220 -- arch/blackfin/mach-bf527/ints-priority.c | 79 - arch/blackfin/mach-bf533/Kconfig | 96 - arch/blackfin/mach-bf533/Makefile | 5 - arch/blackfin/mach-bf533/boards/H8606.c | 452 --- arch/blackfin/mach-bf533/boards/Kconfig | 42 - arch/blackfin/mach-bf533/boards/Makefile | 11 - arch/blackfin/mach-bf533/boards/blackstamp.c | 523 --- arch/blackfin/mach-bf533/boards/cm_bf533.c | 582 ---- arch/blackfin/mach-bf533/boards/ezkit.c | 551 --- arch/blackfin/mach-bf533/boards/ip0x.c | 319 -- arch/blackfin/mach-bf533/boards/stamp.c | 919 ----- arch/blackfin/mach-bf533/dma.c | 78 - arch/blackfin/mach-bf533/include/mach/anomaly.h | 383 --- arch/blackfin/mach-bf533/include/mach/bf533.h | 138 - .../blackfin/mach-bf533/include/mach/bfin_serial.h | 14 - arch/blackfin/mach-bf533/include/mach/blackfin.h | 23 - arch/blackfin/mach-bf533/include/mach/cdefBF532.h | 682 ---- arch/blackfin/mach-bf533/include/mach/defBF532.h | 831 ----- arch/blackfin/mach-bf533/include/mach/dma.h | 26 - arch/blackfin/mach-bf533/include/mach/gpio.h | 33 - arch/blackfin/mach-bf533/include/mach/irq.h | 92 - arch/blackfin/mach-bf533/include/mach/mem_map.h | 139 - arch/blackfin/mach-bf533/include/mach/pll.h | 1 - arch/blackfin/mach-bf533/include/mach/portmux.h | 71 - arch/blackfin/mach-bf533/ints-priority.c | 44 - arch/blackfin/mach-bf537/Kconfig | 118 - arch/blackfin/mach-bf537/Makefile | 5 - arch/blackfin/mach-bf537/boards/Kconfig | 49 - arch/blackfin/mach-bf537/boards/Makefile | 12 - arch/blackfin/mach-bf537/boards/cm_bf537e.c | 945 ----- arch/blackfin/mach-bf537/boards/cm_bf537u.c | 802 ----- arch/blackfin/mach-bf537/boards/dnp5370.c | 413 --- arch/blackfin/mach-bf537/boards/minotaur.c | 585 ---- arch/blackfin/mach-bf537/boards/pnav10.c | 538 --- arch/blackfin/mach-bf537/boards/stamp.c | 3019 ---------------- arch/blackfin/mach-bf537/boards/tcm_bf537.c | 792 ----- arch/blackfin/mach-bf537/dma.c | 98 - arch/blackfin/mach-bf537/include/mach/anomaly.h | 241 -- arch/blackfin/mach-bf537/include/mach/bf537.h | 108 - .../blackfin/mach-bf537/include/mach/bfin_serial.h | 14 - arch/blackfin/mach-bf537/include/mach/blackfin.h | 33 - arch/blackfin/mach-bf537/include/mach/cdefBF534.h | 1736 ---------- arch/blackfin/mach-bf537/include/mach/cdefBF537.h | 178 - arch/blackfin/mach-bf537/include/mach/defBF534.h | 1470 -------- arch/blackfin/mach-bf537/include/mach/defBF537.h | 377 -- arch/blackfin/mach-bf537/include/mach/dma.h | 31 - arch/blackfin/mach-bf537/include/mach/gpio.h | 69 - arch/blackfin/mach-bf537/include/mach/irq.h | 184 - arch/blackfin/mach-bf537/include/mach/mem_map.h | 147 - arch/blackfin/mach-bf537/include/mach/pll.h | 1 - arch/blackfin/mach-bf537/include/mach/portmux.h | 152 - arch/blackfin/mach-bf537/ints-priority.c | 214 -- arch/blackfin/mach-bf538/Kconfig | 166 - arch/blackfin/mach-bf538/Makefile | 6 - arch/blackfin/mach-bf538/boards/Kconfig | 13 - arch/blackfin/mach-bf538/boards/Makefile | 5 - arch/blackfin/mach-bf538/boards/ezkit.c | 987 ------ arch/blackfin/mach-bf538/dma.c | 141 - arch/blackfin/mach-bf538/ext-gpio.c | 158 - arch/blackfin/mach-bf538/include/mach/anomaly.h | 215 -- arch/blackfin/mach-bf538/include/mach/bf538.h | 103 - .../blackfin/mach-bf538/include/mach/bfin_serial.h | 14 - arch/blackfin/mach-bf538/include/mach/blackfin.h | 33 - arch/blackfin/mach-bf538/include/mach/cdefBF538.h | 1960 ----------- arch/blackfin/mach-bf538/include/mach/cdefBF539.h | 240 -- arch/blackfin/mach-bf538/include/mach/defBF538.h | 1749 ---------- arch/blackfin/mach-bf538/include/mach/defBF539.h | 152 - arch/blackfin/mach-bf538/include/mach/dma.h | 41 - arch/blackfin/mach-bf538/include/mach/gpio.h | 81 - arch/blackfin/mach-bf538/include/mach/irq.h | 148 - arch/blackfin/mach-bf538/include/mach/mem_map.h | 74 - arch/blackfin/mach-bf538/include/mach/pll.h | 1 - arch/blackfin/mach-bf538/include/mach/portmux.h | 114 - arch/blackfin/mach-bf538/ints-priority.c | 73 - arch/blackfin/mach-bf548/Kconfig | 383 --- arch/blackfin/mach-bf548/Makefile | 5 - arch/blackfin/mach-bf548/boards/Kconfig | 19 - arch/blackfin/mach-bf548/boards/Makefile | 6 - arch/blackfin/mach-bf548/boards/cm_bf548.c | 1268 ------- arch/blackfin/mach-bf548/boards/ezkit.c | 2199 ------------ arch/blackfin/mach-bf548/dma.c | 139 - arch/blackfin/mach-bf548/include/mach/anomaly.h | 301 -- arch/blackfin/mach-bf548/include/mach/bf548.h | 105 - .../blackfin/mach-bf548/include/mach/bf54x-lq043.h | 36 - arch/blackfin/mach-bf548/include/mach/bf54x_keys.h | 23 - .../blackfin/mach-bf548/include/mach/bfin_serial.h | 16 - arch/blackfin/mach-bf548/include/mach/blackfin.h | 49 - arch/blackfin/mach-bf548/include/mach/cdefBF542.h | 554 --- arch/blackfin/mach-bf548/include/mach/cdefBF544.h | 913 ----- arch/blackfin/mach-bf548/include/mach/cdefBF547.h | 796 ----- arch/blackfin/mach-bf548/include/mach/cdefBF548.h | 761 ----- arch/blackfin/mach-bf548/include/mach/cdefBF549.h | 302 -- .../mach-bf548/include/mach/cdefBF54x_base.h | 2633 -------------- arch/blackfin/mach-bf548/include/mach/defBF542.h | 763 ----- arch/blackfin/mach-bf548/include/mach/defBF544.h | 630 ---- arch/blackfin/mach-bf548/include/mach/defBF547.h | 1034 ------ arch/blackfin/mach-bf548/include/mach/defBF548.h | 399 --- arch/blackfin/mach-bf548/include/mach/defBF549.h | 186 - .../mach-bf548/include/mach/defBF54x_base.h | 2294 ------------- arch/blackfin/mach-bf548/include/mach/dma.h | 72 - arch/blackfin/mach-bf548/include/mach/gpio.h | 210 -- arch/blackfin/mach-bf548/include/mach/irq.h | 454 --- arch/blackfin/mach-bf548/include/mach/mem_map.h | 84 - arch/blackfin/mach-bf548/include/mach/pll.h | 1 - arch/blackfin/mach-bf548/include/mach/portmux.h | 318 -- arch/blackfin/mach-bf548/ints-priority.c | 116 - arch/blackfin/mach-bf561/Kconfig | 213 -- arch/blackfin/mach-bf561/Makefile | 9 - arch/blackfin/mach-bf561/atomic.S | 945 ----- arch/blackfin/mach-bf561/boards/Kconfig | 30 - arch/blackfin/mach-bf561/boards/Makefile | 8 - arch/blackfin/mach-bf561/boards/acvilon.c | 543 --- arch/blackfin/mach-bf561/boards/cm_bf561.c | 556 --- arch/blackfin/mach-bf561/boards/ezkit.c | 688 ---- arch/blackfin/mach-bf561/boards/tepla.c | 162 - arch/blackfin/mach-bf561/coreb.c | 64 - arch/blackfin/mach-bf561/dma.c | 114 - arch/blackfin/mach-bf561/hotplug.c | 40 - arch/blackfin/mach-bf561/include/mach/anomaly.h | 353 -- arch/blackfin/mach-bf561/include/mach/bf561.h | 200 -- .../blackfin/mach-bf561/include/mach/bfin_serial.h | 14 - arch/blackfin/mach-bf561/include/mach/blackfin.h | 41 - arch/blackfin/mach-bf561/include/mach/cdefBF561.h | 1460 -------- arch/blackfin/mach-bf561/include/mach/defBF561.h | 1402 -------- arch/blackfin/mach-bf561/include/mach/dma.h | 39 - arch/blackfin/mach-bf561/include/mach/gpio.h | 67 - arch/blackfin/mach-bf561/include/mach/irq.h | 236 -- arch/blackfin/mach-bf561/include/mach/mem_map.h | 219 -- arch/blackfin/mach-bf561/include/mach/pll.h | 56 - arch/blackfin/mach-bf561/include/mach/portmux.h | 97 - arch/blackfin/mach-bf561/include/mach/smp.h | 32 - arch/blackfin/mach-bf561/ints-priority.c | 87 - arch/blackfin/mach-bf561/secondary.S | 192 -- arch/blackfin/mach-bf561/smp.c | 172 - arch/blackfin/mach-bf609/Kconfig | 1684 --------- arch/blackfin/mach-bf609/Makefile | 7 - arch/blackfin/mach-bf609/boards/Kconfig | 13 - arch/blackfin/mach-bf609/boards/Makefile | 5 - arch/blackfin/mach-bf609/boards/ezkit.c | 2191 ------------ arch/blackfin/mach-bf609/clock.c | 409 --- arch/blackfin/mach-bf609/dma.c | 202 -- arch/blackfin/mach-bf609/dpm.S | 158 - arch/blackfin/mach-bf609/include/mach/anomaly.h | 137 - arch/blackfin/mach-bf609/include/mach/bf609.h | 93 - .../blackfin/mach-bf609/include/mach/bfin_serial.h | 17 - arch/blackfin/mach-bf609/include/mach/blackfin.h | 25 - arch/blackfin/mach-bf609/include/mach/cdefBF609.h | 15 - .../mach-bf609/include/mach/cdefBF60x_base.h | 3254 ------------------ arch/blackfin/mach-bf609/include/mach/defBF609.h | 286 -- .../mach-bf609/include/mach/defBF60x_base.h | 3596 -------------------- arch/blackfin/mach-bf609/include/mach/dma.h | 116 - arch/blackfin/mach-bf609/include/mach/gpio.h | 165 - arch/blackfin/mach-bf609/include/mach/irq.h | 319 -- arch/blackfin/mach-bf609/include/mach/mem_map.h | 86 - arch/blackfin/mach-bf609/include/mach/pll.h | 1 - arch/blackfin/mach-bf609/include/mach/pm.h | 25 - arch/blackfin/mach-bf609/include/mach/portmux.h | 349 -- arch/blackfin/mach-bf609/ints-priority.c | 156 - arch/blackfin/mach-bf609/pm.c | 361 -- arch/blackfin/mach-bf609/scb.c | 363 -- arch/blackfin/mach-common/Makefile | 17 - arch/blackfin/mach-common/arch_checks.c | 66 - arch/blackfin/mach-common/cache-c.c | 85 - arch/blackfin/mach-common/cache.S | 124 - arch/blackfin/mach-common/clock.h | 28 - arch/blackfin/mach-common/clocks-init.c | 121 - arch/blackfin/mach-common/dpmc.c | 164 - arch/blackfin/mach-common/dpmc_modes.S | 320 -- arch/blackfin/mach-common/entry.S | 1711 ---------- arch/blackfin/mach-common/head.S | 229 -- arch/blackfin/mach-common/interrupt.S | 326 -- arch/blackfin/mach-common/ints-priority.c | 1366 -------- arch/blackfin/mach-common/pm.c | 301 -- arch/blackfin/mach-common/scb-init.c | 52 - arch/blackfin/mach-common/smp.c | 432 --- arch/blackfin/mm/Makefile | 5 - arch/blackfin/mm/blackfin_sram.h | 14 - arch/blackfin/mm/init.c | 122 - arch/blackfin/mm/isram-driver.c | 411 --- arch/blackfin/mm/maccess.c | 97 - arch/blackfin/mm/sram-alloc.c | 899 ----- arch/blackfin/oprofile/Makefile | 14 - arch/blackfin/oprofile/bfin_oprofile.c | 18 - include/linux/cpuhotplug.h | 1 - samples/Kconfig | 6 - samples/Makefile | 2 +- samples/blackfin/Makefile | 1 - samples/blackfin/gptimers-example.c | 91 - scripts/checkpatch.pl | 26 - 475 files changed, 2 insertions(+), 123907 deletions(-) delete mode 100644 Documentation/blackfin/00-INDEX delete mode 100644 Documentation/blackfin/bfin-gpio-notes.txt delete mode 100644 Documentation/blackfin/bfin-spi-notes.txt delete mode 100644 arch/blackfin/Clear_BSD.txt delete mode 100644 arch/blackfin/Kconfig delete mode 100644 arch/blackfin/Kconfig.debug delete mode 100644 arch/blackfin/Makefile delete mode 100644 arch/blackfin/boot/.gitignore delete mode 100644 arch/blackfin/boot/Makefile delete mode 100644 arch/blackfin/boot/install.sh delete mode 100644 arch/blackfin/configs/BF518F-EZBRD_defconfig delete mode 100644 arch/blackfin/configs/BF526-EZBRD_defconfig delete mode 100644 arch/blackfin/configs/BF527-AD7160-EVAL_defconfig delete mode 100644 arch/blackfin/configs/BF527-EZKIT-V2_defconfig delete mode 100644 arch/blackfin/configs/BF527-EZKIT_defconfig delete mode 100644 arch/blackfin/configs/BF527-TLL6527M_defconfig delete mode 100644 arch/blackfin/configs/BF533-EZKIT_defconfig delete mode 100644 arch/blackfin/configs/BF533-STAMP_defconfig delete mode 100644 arch/blackfin/configs/BF537-STAMP_defconfig delete mode 100644 arch/blackfin/configs/BF538-EZKIT_defconfig delete mode 100644 arch/blackfin/configs/BF548-EZKIT_defconfig delete mode 100644 arch/blackfin/configs/BF561-ACVILON_defconfig delete mode 100644 arch/blackfin/configs/BF561-EZKIT-SMP_defconfig delete mode 100644 arch/blackfin/configs/BF561-EZKIT_defconfig delete mode 100644 arch/blackfin/configs/BF609-EZKIT_defconfig delete mode 100644 arch/blackfin/configs/BlackStamp_defconfig delete mode 100644 arch/blackfin/configs/CM-BF527_defconfig delete mode 100644 arch/blackfin/configs/CM-BF533_defconfig delete mode 100644 arch/blackfin/configs/CM-BF537E_defconfig delete mode 100644 arch/blackfin/configs/CM-BF537U_defconfig delete mode 100644 arch/blackfin/configs/CM-BF548_defconfig delete mode 100644 arch/blackfin/configs/CM-BF561_defconfig delete mode 100644 arch/blackfin/configs/DNP5370_defconfig delete mode 100644 arch/blackfin/configs/H8606_defconfig delete mode 100644 arch/blackfin/configs/IP0X_defconfig delete mode 100644 arch/blackfin/configs/PNAV-10_defconfig delete mode 100644 arch/blackfin/configs/SRV1_defconfig delete mode 100644 arch/blackfin/configs/TCM-BF518_defconfig delete mode 100644 arch/blackfin/configs/TCM-BF537_defconfig delete mode 100644 arch/blackfin/include/asm/Kbuild delete mode 100644 arch/blackfin/include/asm/asm-offsets.h delete mode 100644 arch/blackfin/include/asm/atomic.h delete mode 100644 arch/blackfin/include/asm/barrier.h delete mode 100644 arch/blackfin/include/asm/bfin-global.h delete mode 100644 arch/blackfin/include/asm/bfin-lq035q1.h delete mode 100644 arch/blackfin/include/asm/bfin5xx_spi.h delete mode 100644 arch/blackfin/include/asm/bfin_can.h delete mode 100644 arch/blackfin/include/asm/bfin_dma.h delete mode 100644 arch/blackfin/include/asm/bfin_pfmon.h delete mode 100644 arch/blackfin/include/asm/bfin_ppi.h delete mode 100644 arch/blackfin/include/asm/bfin_sdh.h delete mode 100644 arch/blackfin/include/asm/bfin_serial.h delete mode 100644 arch/blackfin/include/asm/bfin_simple_timer.h delete mode 100644 arch/blackfin/include/asm/bfin_sport.h delete mode 100644 arch/blackfin/include/asm/bfin_sport3.h delete mode 100644 arch/blackfin/include/asm/bfin_twi.h delete mode 100644 arch/blackfin/include/asm/bfin_watchdog.h delete mode 100644 arch/blackfin/include/asm/bfrom.h delete mode 100644 arch/blackfin/include/asm/bitops.h delete mode 100644 arch/blackfin/include/asm/blackfin.h delete mode 100644 arch/blackfin/include/asm/bug.h delete mode 100644 arch/blackfin/include/asm/cache.h delete mode 100644 arch/blackfin/include/asm/cacheflush.h delete mode 100644 arch/blackfin/include/asm/cdef_LPBlackfin.h delete mode 100644 arch/blackfin/include/asm/checksum.h delete mode 100644 arch/blackfin/include/asm/clocks.h delete mode 100644 arch/blackfin/include/asm/cmpxchg.h delete mode 100644 arch/blackfin/include/asm/context.S delete mode 100644 arch/blackfin/include/asm/cplb.h delete mode 100644 arch/blackfin/include/asm/cplbinit.h delete mode 100644 arch/blackfin/include/asm/cpu.h delete mode 100644 arch/blackfin/include/asm/def_LPBlackfin.h delete mode 100644 arch/blackfin/include/asm/delay.h delete mode 100644 arch/blackfin/include/asm/dma-mapping.h delete mode 100644 arch/blackfin/include/asm/dma.h delete mode 100644 arch/blackfin/include/asm/dpmc.h delete mode 100644 arch/blackfin/include/asm/early_printk.h delete mode 100644 arch/blackfin/include/asm/elf.h delete mode 100644 arch/blackfin/include/asm/entry.h delete mode 100644 arch/blackfin/include/asm/exec.h delete mode 100644 arch/blackfin/include/asm/fixed_code.h delete mode 100644 arch/blackfin/include/asm/flat.h delete mode 100644 arch/blackfin/include/asm/ftrace.h delete mode 100644 arch/blackfin/include/asm/gpio.h delete mode 100644 arch/blackfin/include/asm/gptimers.h delete mode 100644 arch/blackfin/include/asm/hardirq.h delete mode 100644 arch/blackfin/include/asm/io.h delete mode 100644 arch/blackfin/include/asm/ipipe.h delete mode 100644 arch/blackfin/include/asm/ipipe_base.h delete mode 100644 arch/blackfin/include/asm/irq.h delete mode 100644 arch/blackfin/include/asm/irq_handler.h delete mode 100644 arch/blackfin/include/asm/irqflags.h delete mode 100644 arch/blackfin/include/asm/kgdb.h delete mode 100644 arch/blackfin/include/asm/l1layout.h delete mode 100644 arch/blackfin/include/asm/linkage.h delete mode 100644 arch/blackfin/include/asm/mem_init.h delete mode 100644 arch/blackfin/include/asm/mem_map.h delete mode 100644 arch/blackfin/include/asm/mmu.h delete mode 100644 arch/blackfin/include/asm/mmu_context.h delete mode 100644 arch/blackfin/include/asm/module.h delete mode 100644 arch/blackfin/include/asm/nand.h delete mode 100644 arch/blackfin/include/asm/nmi.h delete mode 100644 arch/blackfin/include/asm/page.h delete mode 100644 arch/blackfin/include/asm/page_offset.h delete mode 100644 arch/blackfin/include/asm/pci.h delete mode 100644 arch/blackfin/include/asm/pda.h delete mode 100644 arch/blackfin/include/asm/perf_event.h delete mode 100644 arch/blackfin/include/asm/pgtable.h delete mode 100644 arch/blackfin/include/asm/pm.h delete mode 100644 arch/blackfin/include/asm/portmux.h delete mode 100644 arch/blackfin/include/asm/processor.h delete mode 100644 arch/blackfin/include/asm/pseudo_instructions.h delete mode 100644 arch/blackfin/include/asm/ptrace.h delete mode 100644 arch/blackfin/include/asm/reboot.h delete mode 100644 arch/blackfin/include/asm/rwlock.h delete mode 100644 arch/blackfin/include/asm/scb.h delete mode 100644 arch/blackfin/include/asm/sections.h delete mode 100644 arch/blackfin/include/asm/segment.h delete mode 100644 arch/blackfin/include/asm/smp.h delete mode 100644 arch/blackfin/include/asm/spinlock.h delete mode 100644 arch/blackfin/include/asm/spinlock_types.h delete mode 100644 arch/blackfin/include/asm/string.h delete mode 100644 arch/blackfin/include/asm/switch_to.h delete mode 100644 arch/blackfin/include/asm/syscall.h delete mode 100644 arch/blackfin/include/asm/thread_info.h delete mode 100644 arch/blackfin/include/asm/time.h delete mode 100644 arch/blackfin/include/asm/timex.h delete mode 100644 arch/blackfin/include/asm/tlb.h delete mode 100644 arch/blackfin/include/asm/tlbflush.h delete mode 100644 arch/blackfin/include/asm/trace.h delete mode 100644 arch/blackfin/include/asm/traps.h delete mode 100644 arch/blackfin/include/asm/uaccess.h delete mode 100644 arch/blackfin/include/asm/unistd.h delete mode 100644 arch/blackfin/include/asm/vga.h delete mode 100644 arch/blackfin/include/mach-common/irq.h delete mode 100644 arch/blackfin/include/mach-common/pll.h delete mode 100644 arch/blackfin/include/mach-common/ports-a.h delete mode 100644 arch/blackfin/include/mach-common/ports-b.h delete mode 100644 arch/blackfin/include/mach-common/ports-c.h delete mode 100644 arch/blackfin/include/mach-common/ports-d.h delete mode 100644 arch/blackfin/include/mach-common/ports-e.h delete mode 100644 arch/blackfin/include/mach-common/ports-f.h delete mode 100644 arch/blackfin/include/mach-common/ports-g.h delete mode 100644 arch/blackfin/include/mach-common/ports-h.h delete mode 100644 arch/blackfin/include/mach-common/ports-i.h delete mode 100644 arch/blackfin/include/mach-common/ports-j.h delete mode 100644 arch/blackfin/include/uapi/asm/Kbuild delete mode 100644 arch/blackfin/include/uapi/asm/bfin_sport.h delete mode 100644 arch/blackfin/include/uapi/asm/byteorder.h delete mode 100644 arch/blackfin/include/uapi/asm/cachectl.h delete mode 100644 arch/blackfin/include/uapi/asm/fcntl.h delete mode 100644 arch/blackfin/include/uapi/asm/fixed_code.h delete mode 100644 arch/blackfin/include/uapi/asm/ioctls.h delete mode 100644 arch/blackfin/include/uapi/asm/poll.h delete mode 100644 arch/blackfin/include/uapi/asm/posix_types.h delete mode 100644 arch/blackfin/include/uapi/asm/ptrace.h delete mode 100644 arch/blackfin/include/uapi/asm/sigcontext.h delete mode 100644 arch/blackfin/include/uapi/asm/siginfo.h delete mode 100644 arch/blackfin/include/uapi/asm/signal.h delete mode 100644 arch/blackfin/include/uapi/asm/stat.h delete mode 100644 arch/blackfin/include/uapi/asm/swab.h delete mode 100644 arch/blackfin/include/uapi/asm/unistd.h delete mode 100644 arch/blackfin/kernel/.gitignore delete mode 100644 arch/blackfin/kernel/Makefile delete mode 100644 arch/blackfin/kernel/asm-offsets.c delete mode 100644 arch/blackfin/kernel/bfin_dma.c delete mode 100644 arch/blackfin/kernel/bfin_gpio.c delete mode 100644 arch/blackfin/kernel/bfin_ksyms.c delete mode 100644 arch/blackfin/kernel/cplb-mpu/Makefile delete mode 100644 arch/blackfin/kernel/cplb-mpu/cplbinit.c delete mode 100644 arch/blackfin/kernel/cplb-mpu/cplbmgr.c delete mode 100644 arch/blackfin/kernel/cplb-nompu/Makefile delete mode 100644 arch/blackfin/kernel/cplb-nompu/cplbinit.c delete mode 100644 arch/blackfin/kernel/cplb-nompu/cplbmgr.c delete mode 100644 arch/blackfin/kernel/cplbinfo.c delete mode 100644 arch/blackfin/kernel/debug-mmrs.c delete mode 100644 arch/blackfin/kernel/dma-mapping.c delete mode 100644 arch/blackfin/kernel/dumpstack.c delete mode 100644 arch/blackfin/kernel/early_printk.c delete mode 100644 arch/blackfin/kernel/entry.S delete mode 100644 arch/blackfin/kernel/exception.c delete mode 100644 arch/blackfin/kernel/fixed_code.S delete mode 100644 arch/blackfin/kernel/flat.c delete mode 100644 arch/blackfin/kernel/ftrace-entry.S delete mode 100644 arch/blackfin/kernel/ftrace.c delete mode 100644 arch/blackfin/kernel/gptimers.c delete mode 100644 arch/blackfin/kernel/ipipe.c delete mode 100644 arch/blackfin/kernel/irqchip.c delete mode 100644 arch/blackfin/kernel/kgdb.c delete mode 100644 arch/blackfin/kernel/kgdb_test.c delete mode 100644 arch/blackfin/kernel/module.c delete mode 100644 arch/blackfin/kernel/nmi.c delete mode 100644 arch/blackfin/kernel/perf_event.c delete mode 100644 arch/blackfin/kernel/process.c delete mode 100644 arch/blackfin/kernel/pseudodbg.c delete mode 100644 arch/blackfin/kernel/ptrace.c delete mode 100644 arch/blackfin/kernel/reboot.c delete mode 100644 arch/blackfin/kernel/setup.c delete mode 100644 arch/blackfin/kernel/shadow_console.c delete mode 100644 arch/blackfin/kernel/signal.c delete mode 100644 arch/blackfin/kernel/stacktrace.c delete mode 100644 arch/blackfin/kernel/sys_bfin.c delete mode 100644 arch/blackfin/kernel/time-ts.c delete mode 100644 arch/blackfin/kernel/time.c delete mode 100644 arch/blackfin/kernel/trace.c delete mode 100644 arch/blackfin/kernel/traps.c delete mode 100644 arch/blackfin/kernel/vmlinux.lds.S delete mode 100644 arch/blackfin/lib/Makefile delete mode 100644 arch/blackfin/lib/ashldi3.c delete mode 100644 arch/blackfin/lib/ashrdi3.c delete mode 100644 arch/blackfin/lib/divsi3.S delete mode 100644 arch/blackfin/lib/gcclib.h delete mode 100644 arch/blackfin/lib/ins.S delete mode 100644 arch/blackfin/lib/lshrdi3.c delete mode 100644 arch/blackfin/lib/memchr.S delete mode 100644 arch/blackfin/lib/memcmp.S delete mode 100644 arch/blackfin/lib/memcpy.S delete mode 100644 arch/blackfin/lib/memmove.S delete mode 100644 arch/blackfin/lib/memset.S delete mode 100644 arch/blackfin/lib/modsi3.S delete mode 100644 arch/blackfin/lib/muldi3.S delete mode 100644 arch/blackfin/lib/outs.S delete mode 100644 arch/blackfin/lib/smulsi3_highpart.S delete mode 100644 arch/blackfin/lib/strcmp.S delete mode 100644 arch/blackfin/lib/strcpy.S delete mode 100644 arch/blackfin/lib/strncmp.S delete mode 100644 arch/blackfin/lib/strncpy.S delete mode 100644 arch/blackfin/lib/udivsi3.S delete mode 100644 arch/blackfin/lib/umodsi3.S delete mode 100644 arch/blackfin/lib/umulsi3_highpart.S delete mode 100644 arch/blackfin/mach-bf518/Kconfig delete mode 100644 arch/blackfin/mach-bf518/Makefile delete mode 100644 arch/blackfin/mach-bf518/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf518/boards/Makefile delete mode 100644 arch/blackfin/mach-bf518/boards/ezbrd.c delete mode 100644 arch/blackfin/mach-bf518/boards/tcm-bf518.c delete mode 100644 arch/blackfin/mach-bf518/dma.c delete mode 100644 arch/blackfin/mach-bf518/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/bf518.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/cdefBF512.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/cdefBF514.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/cdefBF516.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/cdefBF518.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/defBF512.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/defBF514.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/defBF516.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/defBF518.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf518/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf518/ints-priority.c delete mode 100644 arch/blackfin/mach-bf527/Kconfig delete mode 100644 arch/blackfin/mach-bf527/Makefile delete mode 100644 arch/blackfin/mach-bf527/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf527/boards/Makefile delete mode 100644 arch/blackfin/mach-bf527/boards/ad7160eval.c delete mode 100644 arch/blackfin/mach-bf527/boards/cm_bf527.c delete mode 100644 arch/blackfin/mach-bf527/boards/ezbrd.c delete mode 100644 arch/blackfin/mach-bf527/boards/ezkit.c delete mode 100644 arch/blackfin/mach-bf527/boards/tll6527m.c delete mode 100644 arch/blackfin/mach-bf527/dma.c delete mode 100644 arch/blackfin/mach-bf527/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/bf527.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/cdefBF522.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/cdefBF525.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/cdefBF527.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/defBF522.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/defBF525.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/defBF527.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf527/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf527/ints-priority.c delete mode 100644 arch/blackfin/mach-bf533/Kconfig delete mode 100644 arch/blackfin/mach-bf533/Makefile delete mode 100644 arch/blackfin/mach-bf533/boards/H8606.c delete mode 100644 arch/blackfin/mach-bf533/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf533/boards/Makefile delete mode 100644 arch/blackfin/mach-bf533/boards/blackstamp.c delete mode 100644 arch/blackfin/mach-bf533/boards/cm_bf533.c delete mode 100644 arch/blackfin/mach-bf533/boards/ezkit.c delete mode 100644 arch/blackfin/mach-bf533/boards/ip0x.c delete mode 100644 arch/blackfin/mach-bf533/boards/stamp.c delete mode 100644 arch/blackfin/mach-bf533/dma.c delete mode 100644 arch/blackfin/mach-bf533/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/bf533.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/cdefBF532.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/defBF532.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf533/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf533/ints-priority.c delete mode 100644 arch/blackfin/mach-bf537/Kconfig delete mode 100644 arch/blackfin/mach-bf537/Makefile delete mode 100644 arch/blackfin/mach-bf537/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf537/boards/Makefile delete mode 100644 arch/blackfin/mach-bf537/boards/cm_bf537e.c delete mode 100644 arch/blackfin/mach-bf537/boards/cm_bf537u.c delete mode 100644 arch/blackfin/mach-bf537/boards/dnp5370.c delete mode 100644 arch/blackfin/mach-bf537/boards/minotaur.c delete mode 100644 arch/blackfin/mach-bf537/boards/pnav10.c delete mode 100644 arch/blackfin/mach-bf537/boards/stamp.c delete mode 100644 arch/blackfin/mach-bf537/boards/tcm_bf537.c delete mode 100644 arch/blackfin/mach-bf537/dma.c delete mode 100644 arch/blackfin/mach-bf537/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/bf537.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/cdefBF534.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/cdefBF537.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/defBF534.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/defBF537.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf537/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf537/ints-priority.c delete mode 100644 arch/blackfin/mach-bf538/Kconfig delete mode 100644 arch/blackfin/mach-bf538/Makefile delete mode 100644 arch/blackfin/mach-bf538/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf538/boards/Makefile delete mode 100644 arch/blackfin/mach-bf538/boards/ezkit.c delete mode 100644 arch/blackfin/mach-bf538/dma.c delete mode 100644 arch/blackfin/mach-bf538/ext-gpio.c delete mode 100644 arch/blackfin/mach-bf538/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/bf538.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/cdefBF538.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/cdefBF539.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/defBF538.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/defBF539.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf538/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf538/ints-priority.c delete mode 100644 arch/blackfin/mach-bf548/Kconfig delete mode 100644 arch/blackfin/mach-bf548/Makefile delete mode 100644 arch/blackfin/mach-bf548/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf548/boards/Makefile delete mode 100644 arch/blackfin/mach-bf548/boards/cm_bf548.c delete mode 100644 arch/blackfin/mach-bf548/boards/ezkit.c delete mode 100644 arch/blackfin/mach-bf548/dma.c delete mode 100644 arch/blackfin/mach-bf548/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/bf548.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/bf54x_keys.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF542.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF544.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF547.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF548.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF549.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/defBF542.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/defBF544.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/defBF547.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/defBF548.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/defBF549.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/defBF54x_base.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf548/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf548/ints-priority.c delete mode 100644 arch/blackfin/mach-bf561/Kconfig delete mode 100644 arch/blackfin/mach-bf561/Makefile delete mode 100644 arch/blackfin/mach-bf561/atomic.S delete mode 100644 arch/blackfin/mach-bf561/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf561/boards/Makefile delete mode 100644 arch/blackfin/mach-bf561/boards/acvilon.c delete mode 100644 arch/blackfin/mach-bf561/boards/cm_bf561.c delete mode 100644 arch/blackfin/mach-bf561/boards/ezkit.c delete mode 100644 arch/blackfin/mach-bf561/boards/tepla.c delete mode 100644 arch/blackfin/mach-bf561/coreb.c delete mode 100644 arch/blackfin/mach-bf561/dma.c delete mode 100644 arch/blackfin/mach-bf561/hotplug.c delete mode 100644 arch/blackfin/mach-bf561/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/bf561.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/cdefBF561.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/defBF561.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf561/include/mach/smp.h delete mode 100644 arch/blackfin/mach-bf561/ints-priority.c delete mode 100644 arch/blackfin/mach-bf561/secondary.S delete mode 100644 arch/blackfin/mach-bf561/smp.c delete mode 100644 arch/blackfin/mach-bf609/Kconfig delete mode 100644 arch/blackfin/mach-bf609/Makefile delete mode 100644 arch/blackfin/mach-bf609/boards/Kconfig delete mode 100644 arch/blackfin/mach-bf609/boards/Makefile delete mode 100644 arch/blackfin/mach-bf609/boards/ezkit.c delete mode 100644 arch/blackfin/mach-bf609/clock.c delete mode 100644 arch/blackfin/mach-bf609/dma.c delete mode 100644 arch/blackfin/mach-bf609/dpm.S delete mode 100644 arch/blackfin/mach-bf609/include/mach/anomaly.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/bf609.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/bfin_serial.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/blackfin.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/cdefBF609.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/defBF609.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/defBF60x_base.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/dma.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/gpio.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/irq.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/mem_map.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/pll.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/pm.h delete mode 100644 arch/blackfin/mach-bf609/include/mach/portmux.h delete mode 100644 arch/blackfin/mach-bf609/ints-priority.c delete mode 100644 arch/blackfin/mach-bf609/pm.c delete mode 100644 arch/blackfin/mach-bf609/scb.c delete mode 100644 arch/blackfin/mach-common/Makefile delete mode 100644 arch/blackfin/mach-common/arch_checks.c delete mode 100644 arch/blackfin/mach-common/cache-c.c delete mode 100644 arch/blackfin/mach-common/cache.S delete mode 100644 arch/blackfin/mach-common/clock.h delete mode 100644 arch/blackfin/mach-common/clocks-init.c delete mode 100644 arch/blackfin/mach-common/dpmc.c delete mode 100644 arch/blackfin/mach-common/dpmc_modes.S delete mode 100644 arch/blackfin/mach-common/entry.S delete mode 100644 arch/blackfin/mach-common/head.S delete mode 100644 arch/blackfin/mach-common/interrupt.S delete mode 100644 arch/blackfin/mach-common/ints-priority.c delete mode 100644 arch/blackfin/mach-common/pm.c delete mode 100644 arch/blackfin/mach-common/scb-init.c delete mode 100644 arch/blackfin/mach-common/smp.c delete mode 100644 arch/blackfin/mm/Makefile delete mode 100644 arch/blackfin/mm/blackfin_sram.h delete mode 100644 arch/blackfin/mm/init.c delete mode 100644 arch/blackfin/mm/isram-driver.c delete mode 100644 arch/blackfin/mm/maccess.c delete mode 100644 arch/blackfin/mm/sram-alloc.c delete mode 100644 arch/blackfin/oprofile/Makefile delete mode 100644 arch/blackfin/oprofile/bfin_oprofile.c delete mode 100644 samples/blackfin/Makefile delete mode 100644 samples/blackfin/gptimers-example.c (limited to 'include/linux') diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index b56b88e20196..ee2808415f64 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -66,8 +66,6 @@ backlight/ - directory with info on controlling backlights in flat panel displays bcache.txt - Block-layer cache on fast SSDs to improve slow (raid) I/O performance. -blackfin/ - - directory with documentation for the Blackfin arch. block/ - info on the Block I/O (BIO) layer. blockdev/ diff --git a/Documentation/admin-guide/kernel-parameters.rst b/Documentation/admin-guide/kernel-parameters.rst index 7242cbda15dd..b8d0bc07ed0a 100644 --- a/Documentation/admin-guide/kernel-parameters.rst +++ b/Documentation/admin-guide/kernel-parameters.rst @@ -89,7 +89,6 @@ parameter is applicable:: APM Advanced Power Management support is enabled. ARM ARM architecture is enabled. AX25 Appropriate AX.25 support is enabled. - BLACKFIN Blackfin architecture is enabled. CLK Common clock infrastructure is enabled. CMA Contiguous Memory Area support is enabled. DRM Direct Rendering Management support is enabled. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 30a8d0635898..c272ea194ff3 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1025,7 +1025,7 @@ address. The serial port must already be setup and configured. Options are not yet supported. - earlyprintk= [X86,SH,BLACKFIN,ARM,M68k,S390] + earlyprintk= [X86,SH,ARM,M68k,S390] earlyprintk=vga earlyprintk=efi earlyprintk=sclp diff --git a/Documentation/blackfin/00-INDEX b/Documentation/blackfin/00-INDEX deleted file mode 100644 index 265a1effebde..000000000000 --- a/Documentation/blackfin/00-INDEX +++ /dev/null @@ -1,6 +0,0 @@ -00-INDEX - - This file -bfin-gpio-notes.txt - - Notes in developing/using bfin-gpio driver. -bfin-spi-notes.txt - - Notes for using bfin spi bus driver. diff --git a/Documentation/blackfin/bfin-gpio-notes.txt b/Documentation/blackfin/bfin-gpio-notes.txt deleted file mode 100644 index d245f39c3d01..000000000000 --- a/Documentation/blackfin/bfin-gpio-notes.txt +++ /dev/null @@ -1,71 +0,0 @@ -/* - * File: Documentation/blackfin/bfin-gpio-notes.txt - * Based on: - * Author: - * - * Created: $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $ - * Description: This file contains the notes in developing/using bfin-gpio. - * - * - * Rev: - * - * Modified: - * Copyright 2004-2008 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - */ - - -1. Blackfin GPIO introduction - - There are many GPIO pins on Blackfin. Most of these pins are muxed to - multi-functions. They can be configured as peripheral, or just as GPIO, - configured to input with interrupt enabled, or output. - - For detailed information, please see "arch/blackfin/kernel/bfin_gpio.c", - or the relevant HRM. - - -2. Avoiding resource conflict - - Followed function groups are used to avoiding resource conflict, - - Use the pin as peripheral, - int peripheral_request(unsigned short per, const char *label); - int peripheral_request_list(const unsigned short per[], const char *label); - void peripheral_free(unsigned short per); - void peripheral_free_list(const unsigned short per[]); - - Use the pin as GPIO, - int bfin_gpio_request(unsigned gpio, const char *label); - void bfin_gpio_free(unsigned gpio); - - Use the pin as GPIO interrupt, - int bfin_gpio_irq_request(unsigned gpio, const char *label); - void bfin_gpio_irq_free(unsigned gpio); - - The request functions will record the function state for a certain pin, - the free functions will clear its function state. - Once a pin is requested, it can't be requested again before it is freed by - previous caller, otherwise kernel will dump stacks, and the request - function fail. - These functions are wrapped by other functions, most of the users need not - care. - - -3. But there are some exceptions - - Kernel permit the identical GPIO be requested both as GPIO and GPIO - interrupt. - Some drivers, like gpio-keys, need this behavior. Kernel only print out - warning messages like, - bfin-gpio: GPIO 24 is already reserved by gpio-keys: BTN0, and you are -configuring it as IRQ! - - Note: Consider the case that, if there are two drivers need the - identical GPIO, one of them use it as GPIO, the other use it as - GPIO interrupt. This will really cause resource conflict. So if - there is any abnormal driver behavior, please check the bfin-gpio - warning messages. - - - Kernel permit the identical GPIO be requested from the same driver twice. - - - diff --git a/Documentation/blackfin/bfin-spi-notes.txt b/Documentation/blackfin/bfin-spi-notes.txt deleted file mode 100644 index eae6eaf2a09d..000000000000 --- a/Documentation/blackfin/bfin-spi-notes.txt +++ /dev/null @@ -1,16 +0,0 @@ -SPI Chip Select behavior: - -With the Blackfin on-chip SPI peripheral, there is some logic tied to the CPHA -bit whether the Slave Select Line is controlled by hardware (CPHA=0) or -controlled by software (CPHA=1). However, the Linux SPI bus driver assumes that -the Slave Select is always under software control and being asserted during -the entire SPI transfer. - And not just bits_per_word duration. - -In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this -behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2 -timing, you can utilize the GPIO controlled SPI Slave Select option instead. -In this case, you should use GPIO based CS for all of your slaves and not just -the ones using mode 0 or 2 in order to guarantee correct CS toggling behavior. - -You can even use the same pin whose peripheral role is a SSEL, -but use it as a GPIO instead. diff --git a/MAINTAINERS b/MAINTAINERS index 2281937d9432..9e0c097824f5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2629,51 +2629,6 @@ F: Documentation/filesystems/bfs.txt F: fs/bfs/ F: include/uapi/linux/bfs_fs.h -BLACKFIN ARCHITECTURE -L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) -T: git git://git.code.sf.net/p/adi-linux/code -W: http://blackfin.uclinux.org -S: Orphan -F: arch/blackfin/ - -BLACKFIN EMAC DRIVER -L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) -W: http://blackfin.uclinux.org -S: Orphan -F: drivers/net/ethernet/adi/ - -BLACKFIN MEDIA DRIVER -L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) -W: http://blackfin.uclinux.org/ -S: Orphan -F: drivers/media/platform/blackfin/ -F: drivers/media/i2c/adv7183* -F: drivers/media/i2c/vs6624* - -BLACKFIN RTC DRIVER -L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) -W: http://blackfin.uclinux.org -S: Orphan -F: drivers/rtc/rtc-bfin.c - -BLACKFIN SDH DRIVER -L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) -W: http://blackfin.uclinux.org -S: Orphan -F: drivers/mmc/host/bfin_sdh.c - -BLACKFIN SERIAL DRIVER -L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) -W: http://blackfin.uclinux.org -S: Orphan -F: drivers/tty/serial/bfin_uart.c - -BLACKFIN WATCHDOG DRIVER -L: adi-buildroot-devel@lists.sourceforge.net (moderated for non-subscribers) -W: http://blackfin.uclinux.org -S: Orphan -F: drivers/watchdog/bfin_wdt.c - BLINKM RGB LED DRIVER M: Jan-Simon Moeller S: Maintained diff --git a/arch/blackfin/Clear_BSD.txt b/arch/blackfin/Clear_BSD.txt deleted file mode 100644 index bfa4b378a368..000000000000 --- a/arch/blackfin/Clear_BSD.txt +++ /dev/null @@ -1,33 +0,0 @@ -The Clear BSD license: - -Copyright (c) 2012, Analog Devices, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted (subject to the limitations in the -disclaimer below) provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the - distribution. - -* Neither the name of Analog Devices, Inc. nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - -NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig deleted file mode 100644 index d9c2866ba618..000000000000 --- a/arch/blackfin/Kconfig +++ /dev/null @@ -1,1463 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config MMU - def_bool n - -config FPU - def_bool n - -config RWSEM_GENERIC_SPINLOCK - def_bool y - -config RWSEM_XCHGADD_ALGORITHM - def_bool n - -config BLACKFIN - def_bool y - select HAVE_ARCH_KGDB - select HAVE_ARCH_TRACEHOOK - select HAVE_DYNAMIC_FTRACE - select HAVE_FTRACE_MCOUNT_RECORD - select HAVE_FUNCTION_GRAPH_TRACER - select HAVE_FUNCTION_TRACER - select HAVE_IDE - select HAVE_KERNEL_GZIP if RAMKERNEL - select HAVE_KERNEL_BZIP2 if RAMKERNEL - select HAVE_KERNEL_LZMA if RAMKERNEL - select HAVE_KERNEL_LZO if RAMKERNEL - select HAVE_OPROFILE - select HAVE_PERF_EVENTS - select ARCH_HAVE_CUSTOM_GPIO_H - select GPIOLIB - select HAVE_UID16 - select HAVE_UNDERSCORE_SYMBOL_PREFIX - select VIRT_TO_BUS - select ARCH_WANT_IPC_PARSE_VERSION - select GENERIC_ATOMIC64 - select GENERIC_IRQ_PROBE - select GENERIC_IRQ_SHOW - select HAVE_NMI_WATCHDOG if NMI_WATCHDOG - select GENERIC_SMP_IDLE_THREAD - select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS - select HAVE_MOD_ARCH_SPECIFIC - select MODULES_USE_ELF_RELA - select HAVE_DEBUG_STACKOVERFLOW - select HAVE_NMI - select ARCH_NO_COHERENT_DMA_MMAP - -config GENERIC_CSUM - def_bool y - -config GENERIC_BUG - def_bool y - depends on BUG - -config ZONE_DMA - def_bool y - -config FORCE_MAX_ZONEORDER - int - default "14" - -config GENERIC_CALIBRATE_DELAY - def_bool y - -config LOCKDEP_SUPPORT - def_bool y - -config STACKTRACE_SUPPORT - def_bool y - -config TRACE_IRQFLAGS_SUPPORT - def_bool y - -source "init/Kconfig" - -source "kernel/Kconfig.preempt" - -source "kernel/Kconfig.freezer" - -menu "Blackfin Processor Options" - -comment "Processor and Board Settings" - -choice - prompt "CPU" - default BF533 - -config BF512 - bool "BF512" - help - BF512 Processor Support. - -config BF514 - bool "BF514" - help - BF514 Processor Support. - -config BF516 - bool "BF516" - help - BF516 Processor Support. - -config BF518 - bool "BF518" - help - BF518 Processor Support. - -config BF522 - bool "BF522" - help - BF522 Processor Support. - -config BF523 - bool "BF523" - help - BF523 Processor Support. - -config BF524 - bool "BF524" - help - BF524 Processor Support. - -config BF525 - bool "BF525" - help - BF525 Processor Support. - -config BF526 - bool "BF526" - help - BF526 Processor Support. - -config BF527 - bool "BF527" - help - BF527 Processor Support. - -config BF531 - bool "BF531" - help - BF531 Processor Support. - -config BF532 - bool "BF532" - help - BF532 Processor Support. - -config BF533 - bool "BF533" - help - BF533 Processor Support. - -config BF534 - bool "BF534" - help - BF534 Processor Support. - -config BF536 - bool "BF536" - help - BF536 Processor Support. - -config BF537 - bool "BF537" - help - BF537 Processor Support. - -config BF538 - bool "BF538" - help - BF538 Processor Support. - -config BF539 - bool "BF539" - help - BF539 Processor Support. - -config BF542_std - bool "BF542" - help - BF542 Processor Support. - -config BF542M - bool "BF542m" - help - BF542 Processor Support. - -config BF544_std - bool "BF544" - help - BF544 Processor Support. - -config BF544M - bool "BF544m" - help - BF544 Processor Support. - -config BF547_std - bool "BF547" - help - BF547 Processor Support. - -config BF547M - bool "BF547m" - help - BF547 Processor Support. - -config BF548_std - bool "BF548" - help - BF548 Processor Support. - -config BF548M - bool "BF548m" - help - BF548 Processor Support. - -config BF549_std - bool "BF549" - help - BF549 Processor Support. - -config BF549M - bool "BF549m" - help - BF549 Processor Support. - -config BF561 - bool "BF561" - help - BF561 Processor Support. - -config BF609 - bool "BF609" - select CLKDEV_LOOKUP - help - BF609 Processor Support. - -endchoice - -config SMP - depends on BF561 - select TICKSOURCE_CORETMR - bool "Symmetric multi-processing support" - ---help--- - This enables support for systems with more than one CPU, - like the dual core BF561. If you have a system with only one - CPU, say N. If you have a system with more than one CPU, say Y. - - If you don't know what to do here, say N. - -config NR_CPUS - int - depends on SMP - default 2 if BF561 - -config HOTPLUG_CPU - bool "Support for hot-pluggable CPUs" - depends on SMP - default y - -config BF_REV_MIN - int - default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x - default 2 if (BF537 || BF536 || BF534) - default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) - default 4 if (BF538 || BF539) - -config BF_REV_MAX - int - default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x - default 3 if (BF537 || BF536 || BF534 || BF54xM) - default 5 if (BF561 || BF538 || BF539) - default 6 if (BF533 || BF532 || BF531) - -choice - prompt "Silicon Rev" - default BF_REV_0_0 if (BF51x || BF52x || BF60x) - default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) - default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) - -config BF_REV_0_0 - bool "0.0" - depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) - -config BF_REV_0_1 - bool "0.1" - depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) - -config BF_REV_0_2 - bool "0.2" - depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) - -config BF_REV_0_3 - bool "0.3" - depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) - -config BF_REV_0_4 - bool "0.4" - depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x) - -config BF_REV_0_5 - bool "0.5" - depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) - -config BF_REV_0_6 - bool "0.6" - depends on (BF533 || BF532 || BF531) - -config BF_REV_ANY - bool "any" - -config BF_REV_NONE - bool "none" - -endchoice - -config BF53x - bool - depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) - default y - -config GPIO_ADI - def_bool y - depends on !PINCTRL - depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561) - -config PINCTRL_BLACKFIN_ADI2 - def_bool y - depends on (BF54x || BF60x) - select PINCTRL - select PINCTRL_ADI2 - -config MEM_MT48LC64M4A2FB_7E - bool - depends on (BFIN533_STAMP) - default y - -config MEM_MT48LC16M16A2TG_75 - bool - depends on (BFIN533_EZKIT || BFIN561_EZKIT \ - || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ - || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ - || BFIN527_BLUETECHNIX_CM) - default y - -config MEM_MT48LC32M8A2_75 - bool - depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) - default y - -config MEM_MT48LC8M32B2B5_7 - bool - depends on (BFIN561_BLUETECHNIX_CM) - default y - -config MEM_MT48LC32M16A2TG_75 - bool - depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) - default y - -config MEM_MT48H32M16LFCJ_75 - bool - depends on (BFIN526_EZBRD) - default y - -config MEM_MT47H64M16 - bool - depends on (BFIN609_EZKIT) - default y - -source "arch/blackfin/mach-bf518/Kconfig" -source "arch/blackfin/mach-bf527/Kconfig" -source "arch/blackfin/mach-bf533/Kconfig" -source "arch/blackfin/mach-bf561/Kconfig" -source "arch/blackfin/mach-bf537/Kconfig" -source "arch/blackfin/mach-bf538/Kconfig" -source "arch/blackfin/mach-bf548/Kconfig" -source "arch/blackfin/mach-bf609/Kconfig" - -menu "Board customizations" - -config CMDLINE_BOOL - bool "Default bootloader kernel arguments" - -config CMDLINE - string "Initial kernel command string" - depends on CMDLINE_BOOL - default "console=ttyBF0,57600" - help - If you don't have a boot loader capable of passing a command line string - to the kernel, you may specify one here. As a minimum, you should specify - the memory size and the root device (e.g., mem=8M, root=/dev/nfs). - -config BOOT_LOAD - hex "Kernel load address for booting" - default "0x1000" - range 0x1000 0x20000000 - help - This option allows you to set the load address of the kernel. - This can be useful if you are on a board which has a small amount - of memory or you wish to reserve some memory at the beginning of - the address space. - - Note that you need to keep this value above 4k (0x1000) as this - memory region is used to capture NULL pointer references as well - as some core kernel functions. - -config PHY_RAM_BASE_ADDRESS - hex "Physical RAM Base" - default 0x0 - help - set BF609 FPGA physical SRAM base address - -config ROM_BASE - hex "Kernel ROM Base" - depends on ROMKERNEL - default "0x20040040" - range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) - range 0x20000000 0x30000000 if (BF54x || BF561) - range 0xB0000000 0xC0000000 if (BF60x) - help - Make sure your ROM base does not include any file-header - information that is prepended to the kernel. - - For example, the bootable U-Boot format (created with - mkimage) has a 64 byte header (0x40). So while the image - you write to flash might start at say 0x20080000, you have - to add 0x40 to get the kernel's ROM base as it will come - after the header. - -comment "Clock/PLL Setup" - -config CLKIN_HZ - int "Frequency of the crystal on the board in Hz" - default "10000000" if BFIN532_IP0X - default "11059200" if BFIN533_STAMP - default "24576000" if PNAV10 - default "25000000" # most people use this - default "27000000" if BFIN533_EZKIT - default "30000000" if BFIN561_EZKIT - default "24000000" if BFIN527_AD7160EVAL - help - The frequency of CLKIN crystal oscillator on the board in Hz. - Warning: This value should match the crystal on the board. Otherwise, - peripherals won't work properly. - -config BFIN_KERNEL_CLOCK - bool "Re-program Clocks while Kernel boots?" - default n - help - This option decides if kernel clocks are re-programed from the - bootloader settings. If the clocks are not set, the SDRAM settings - are also not changed, and the Bootloader does 100% of the hardware - configuration. - -config PLL_BYPASS - bool "Bypass PLL" - depends on BFIN_KERNEL_CLOCK && (!BF60x) - default n - -config CLKIN_HALF - bool "Half Clock In" - depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) - default n - help - If this is set the clock will be divided by 2, before it goes to the PLL. - -config VCO_MULT - int "VCO Multiplier" - depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) - range 1 64 - default "22" if BFIN533_EZKIT - default "45" if BFIN533_STAMP - default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) - default "22" if BFIN533_BLUETECHNIX_CM - default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) - default "20" if (BFIN561_EZKIT || BF609) - default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) - default "25" if BFIN527_AD7160EVAL - help - This controls the frequency of the on-chip PLL. This can be between 1 and 64. - PLL Frequency = (Crystal Frequency) * (this setting) - -choice - prompt "Core Clock Divider" - depends on BFIN_KERNEL_CLOCK - default CCLK_DIV_1 - help - This sets the frequency of the core. It can be 1, 2, 4 or 8 - Core Frequency = (PLL frequency) / (this setting) - -config CCLK_DIV_1 - bool "1" - -config CCLK_DIV_2 - bool "2" - -config CCLK_DIV_4 - bool "4" - -config CCLK_DIV_8 - bool "8" -endchoice - -config SCLK_DIV - int "System Clock Divider" - depends on BFIN_KERNEL_CLOCK - range 1 15 - default 4 - help - This sets the frequency of the system clock (including SDRAM or DDR) on - !BF60x else it set the clock for system buses and provides the - source from which SCLK0 and SCLK1 are derived. - This can be between 1 and 15 - System Clock = (PLL frequency) / (this setting) - -config SCLK0_DIV - int "System Clock0 Divider" - depends on BFIN_KERNEL_CLOCK && BF60x - range 1 15 - default 1 - help - This sets the frequency of the system clock0 for PVP and all other - peripherals not clocked by SCLK1. - This can be between 1 and 15 - System Clock0 = (System Clock) / (this setting) - -config SCLK1_DIV - int "System Clock1 Divider" - depends on BFIN_KERNEL_CLOCK && BF60x - range 1 15 - default 1 - help - This sets the frequency of the system clock1 (including SPORT, SPI and ACM). - This can be between 1 and 15 - System Clock1 = (System Clock) / (this setting) - -config DCLK_DIV - int "DDR Clock Divider" - depends on BFIN_KERNEL_CLOCK && BF60x - range 1 15 - default 2 - help - This sets the frequency of the DDR memory. - This can be between 1 and 15 - DDR Clock = (PLL frequency) / (this setting) - -choice - prompt "DDR SDRAM Chip Type" - depends on BFIN_KERNEL_CLOCK - depends on BF54x - default MEM_MT46V32M16_5B - -config MEM_MT46V32M16_6T - bool "MT46V32M16_6T" - -config MEM_MT46V32M16_5B - bool "MT46V32M16_5B" -endchoice - -choice - prompt "DDR/SDRAM Timing" - depends on BFIN_KERNEL_CLOCK && !BF60x - default BFIN_KERNEL_CLOCK_MEMINIT_CALC - help - This option allows you to specify Blackfin SDRAM/DDR Timing parameters - The calculated SDRAM timing parameters may not be 100% - accurate - This option is therefore marked experimental. - -config BFIN_KERNEL_CLOCK_MEMINIT_CALC - bool "Calculate Timings" - -config BFIN_KERNEL_CLOCK_MEMINIT_SPEC - bool "Provide accurate Timings based on target SCLK" - help - Please consult the Blackfin Hardware Reference Manuals as well - as the memory device datasheet. - http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram -endchoice - -menu "Memory Init Control" - depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC - -config MEM_DDRCTL0 - depends on BF54x - hex "DDRCTL0" - default 0x0 - -config MEM_DDRCTL1 - depends on BF54x - hex "DDRCTL1" - default 0x0 - -config MEM_DDRCTL2 - depends on BF54x - hex "DDRCTL2" - default 0x0 - -config MEM_EBIU_DDRQUE - depends on BF54x - hex "DDRQUE" - default 0x0 - -config MEM_SDRRC - depends on !BF54x - hex "SDRRC" - default 0x0 - -config MEM_SDGCTL - depends on !BF54x - hex "SDGCTL" - default 0x0 -endmenu - -# -# Max & Min Speeds for various Chips -# -config MAX_VCO_HZ - int - default 400000000 if BF512 - default 400000000 if BF514 - default 400000000 if BF516 - default 400000000 if BF518 - default 400000000 if BF522 - default 600000000 if BF523 - default 400000000 if BF524 - default 600000000 if BF525 - default 400000000 if BF526 - default 600000000 if BF527 - default 400000000 if BF531 - default 400000000 if BF532 - default 750000000 if BF533 - default 500000000 if BF534 - default 400000000 if BF536 - default 600000000 if BF537 - default 533333333 if BF538 - default 533333333 if BF539 - default 600000000 if BF542 - default 533333333 if BF544 - default 600000000 if BF547 - default 600000000 if BF548 - default 533333333 if BF549 - default 600000000 if BF561 - default 800000000 if BF609 - -config MIN_VCO_HZ - int - default 50000000 - -config MAX_SCLK_HZ - int - default 200000000 if BF609 - default 133333333 - -config MIN_SCLK_HZ - int - default 27000000 - -comment "Kernel Timer/Scheduler" - -source kernel/Kconfig.hz - -config SET_GENERIC_CLOCKEVENTS - bool "Generic clock events" - default y - select GENERIC_CLOCKEVENTS - -menu "Clock event device" - depends on GENERIC_CLOCKEVENTS -config TICKSOURCE_GPTMR0 - bool "GPTimer0" - depends on !SMP - select BFIN_GPTIMERS - -config TICKSOURCE_CORETMR - bool "Core timer" - default y -endmenu - -menu "Clock source" - depends on GENERIC_CLOCKEVENTS -config CYCLES_CLOCKSOURCE - bool "CYCLES" - default y - depends on !BFIN_SCRATCH_REG_CYCLES - depends on !SMP - help - If you say Y here, you will enable support for using the 'cycles' - registers as a clock source. Doing so means you will be unable to - safely write to the 'cycles' register during runtime. You will - still be able to read it (such as for performance monitoring), but - writing the registers will most likely crash the kernel. - -config GPTMR0_CLOCKSOURCE - bool "GPTimer0" - select BFIN_GPTIMERS - depends on !TICKSOURCE_GPTMR0 -endmenu - -comment "Misc" - -choice - prompt "Blackfin Exception Scratch Register" - default BFIN_SCRATCH_REG_RETN - help - Select the resource to reserve for the Exception handler: - - RETN: Non-Maskable Interrupt (NMI) - - RETE: Exception Return (JTAG/ICE) - - CYCLES: Performance counter - - If you are unsure, please select "RETN". - -config BFIN_SCRATCH_REG_RETN - bool "RETN" - help - Use the RETN register in the Blackfin exception handler - as a stack scratch register. This means you cannot - safely use NMI on the Blackfin while running Linux, but - you can debug the system with a JTAG ICE and use the - CYCLES performance registers. - - If you are unsure, please select "RETN". - -config BFIN_SCRATCH_REG_RETE - bool "RETE" - help - Use the RETE register in the Blackfin exception handler - as a stack scratch register. This means you cannot - safely use a JTAG ICE while debugging a Blackfin board, - but you can safely use the CYCLES performance registers - and the NMI. - - If you are unsure, please select "RETN". - -config BFIN_SCRATCH_REG_CYCLES - bool "CYCLES" - help - Use the CYCLES register in the Blackfin exception handler - as a stack scratch register. This means you cannot - safely use the CYCLES performance registers on a Blackfin - board at anytime, but you can debug the system with a JTAG - ICE and use the NMI. - - If you are unsure, please select "RETN". - -endchoice - -endmenu - - -menu "Blackfin Kernel Optimizations" - -comment "Memory Optimizations" - -config I_ENTRY_L1 - bool "Locate interrupt entry code in L1 Memory" - default y - depends on !SMP - help - If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked - into L1 instruction memory. (less latency) - -config EXCPT_IRQ_SYSC_L1 - bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" - default y - depends on !SMP - help - If enabled, the entire ASM lowlevel exception and interrupt entry code - (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. - (less latency) - -config DO_IRQ_L1 - bool "Locate frequently called do_irq dispatcher function in L1 Memory" - default y - depends on !SMP - help - If enabled, the frequently called do_irq dispatcher function is linked - into L1 instruction memory. (less latency) - -config CORE_TIMER_IRQ_L1 - bool "Locate frequently called timer_interrupt() function in L1 Memory" - default y - depends on !SMP - help - If enabled, the frequently called timer_interrupt() function is linked - into L1 instruction memory. (less latency) - -config IDLE_L1 - bool "Locate frequently idle function in L1 Memory" - default y - depends on !SMP - help - If enabled, the frequently called idle function is linked - into L1 instruction memory. (less latency) - -config SCHEDULE_L1 - bool "Locate kernel schedule function in L1 Memory" - default y - depends on !SMP - help - If enabled, the frequently called kernel schedule is linked - into L1 instruction memory. (less latency) - -config ARITHMETIC_OPS_L1 - bool "Locate kernel owned arithmetic functions in L1 Memory" - default y - depends on !SMP - help - If enabled, arithmetic functions are linked - into L1 instruction memory. (less latency) - -config ACCESS_OK_L1 - bool "Locate access_ok function in L1 Memory" - default y - depends on !SMP - help - If enabled, the access_ok function is linked - into L1 instruction memory. (less latency) - -config MEMSET_L1 - bool "Locate memset function in L1 Memory" - default y - depends on !SMP - help - If enabled, the memset function is linked - into L1 instruction memory. (less latency) - -config MEMCPY_L1 - bool "Locate memcpy function in L1 Memory" - default y - depends on !SMP - help - If enabled, the memcpy function is linked - into L1 instruction memory. (less latency) - -config STRCMP_L1 - bool "locate strcmp function in L1 Memory" - default y - depends on !SMP - help - If enabled, the strcmp function is linked - into L1 instruction memory (less latency). - -config STRNCMP_L1 - bool "locate strncmp function in L1 Memory" - default y - depends on !SMP - help - If enabled, the strncmp function is linked - into L1 instruction memory (less latency). - -config STRCPY_L1 - bool "locate strcpy function in L1 Memory" - default y - depends on !SMP - help - If enabled, the strcpy function is linked - into L1 instruction memory (less latency). - -config STRNCPY_L1 - bool "locate strncpy function in L1 Memory" - default y - depends on !SMP - help - If enabled, the strncpy function is linked - into L1 instruction memory (less latency). - -config SYS_BFIN_SPINLOCK_L1 - bool "Locate sys_bfin_spinlock function in L1 Memory" - default y - depends on !SMP - help - If enabled, sys_bfin_spinlock function is linked - into L1 instruction memory. (less latency) - -config CACHELINE_ALIGNED_L1 - bool "Locate cacheline_aligned data to L1 Data Memory" - default y if !BF54x - default n if BF54x - depends on !SMP && !BF531 && !CRC32 - help - If enabled, cacheline_aligned data is linked - into L1 data memory. (less latency) - -config SYSCALL_TAB_L1 - bool "Locate Syscall Table L1 Data Memory" - default n - depends on !SMP && !BF531 - help - If enabled, the Syscall LUT is linked - into L1 data memory. (less latency) - -config CPLB_SWITCH_TAB_L1 - bool "Locate CPLB Switch Tables L1 Data Memory" - default n - depends on !SMP && !BF531 - help - If enabled, the CPLB Switch Tables are linked - into L1 data memory. (less latency) - -config ICACHE_FLUSH_L1 - bool "Locate icache flush funcs in L1 Inst Memory" - default y - help - If enabled, the Blackfin icache flushing functions are linked - into L1 instruction memory. - - Note that this might be required to address anomalies, but - these functions are pretty small, so it shouldn't be too bad. - If you are using a processor affected by an anomaly, the build - system will double check for you and prevent it. - -config DCACHE_FLUSH_L1 - bool "Locate dcache flush funcs in L1 Inst Memory" - default y - depends on !SMP - help - If enabled, the Blackfin dcache flushing functions are linked - into L1 instruction memory. - -config APP_STACK_L1 - bool "Support locating application stack in L1 Scratch Memory" - default y - depends on !SMP - help - If enabled the application stack can be located in L1 - scratch memory (less latency). - - Currently only works with FLAT binaries. - -config EXCEPTION_L1_SCRATCH - bool "Locate exception stack in L1 Scratch Memory" - default n - depends on !SMP && !APP_STACK_L1 - help - Whenever an exception occurs, use the L1 Scratch memory for - stack storage. You cannot place the stacks of FLAT binaries - in L1 when using this option. - - If you don't use L1 Scratch, then you should say Y here. - -comment "Speed Optimizations" -config BFIN_INS_LOWOVERHEAD - bool "ins[bwl] low overhead, higher interrupt latency" - default y - depends on !SMP - help - Reads on the Blackfin are speculative. In Blackfin terms, this means - they can be interrupted at any time (even after they have been issued - on to the external bus), and re-issued after the interrupt occurs. - For memory - this is not a big deal, since memory does not change if - it sees a read. - - If a FIFO is sitting on the end of the read, it will see two reads, - when the core only sees one since the FIFO receives both the read - which is cancelled (and not delivered to the core) and the one which - is re-issued (which is delivered to the core). - - To solve this, interrupts are turned off before reads occur to - I/O space. This option controls which the overhead/latency of - controlling interrupts during this time - "n" turns interrupts off every read - (higher overhead, but lower interrupt latency) - "y" turns interrupts off every loop - (low overhead, but longer interrupt latency) - - default behavior is to leave this set to on (type "Y"). If you are experiencing - interrupt latency issues, it is safe and OK to turn this off. - -endmenu - -choice - prompt "Kernel executes from" - help - Choose the memory type that the kernel will be running in. - -config RAMKERNEL - bool "RAM" - help - The kernel will be resident in RAM when running. - -config ROMKERNEL - bool "ROM" - help - The kernel will be resident in FLASH/ROM when running. - -endchoice - -# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both -config XIP_KERNEL - bool - default y - depends on ROMKERNEL - -source "mm/Kconfig" - -config BFIN_GPTIMERS - tristate "Enable Blackfin General Purpose Timers API" - default n - help - Enable support for the General Purpose Timers API. If you - are unsure, say N. - - To compile this driver as a module, choose M here: the module - will be called gptimers. - -choice - prompt "Uncached DMA region" - default DMA_UNCACHED_1M -config DMA_UNCACHED_32M - bool "Enable 32M DMA region" -config DMA_UNCACHED_16M - bool "Enable 16M DMA region" -config DMA_UNCACHED_8M - bool "Enable 8M DMA region" -config DMA_UNCACHED_4M - bool "Enable 4M DMA region" -config DMA_UNCACHED_2M - bool "Enable 2M DMA region" -config DMA_UNCACHED_1M - bool "Enable 1M DMA region" -config DMA_UNCACHED_512K - bool "Enable 512K DMA region" -config DMA_UNCACHED_256K - bool "Enable 256K DMA region" -config DMA_UNCACHED_128K - bool "Enable 128K DMA region" -config DMA_UNCACHED_NONE - bool "Disable DMA region" -endchoice - - -comment "Cache Support" - -config BFIN_ICACHE - bool "Enable ICACHE" - default y -config BFIN_EXTMEM_ICACHEABLE - bool "Enable ICACHE for external memory" - depends on BFIN_ICACHE - default y -config BFIN_L2_ICACHEABLE - bool "Enable ICACHE for L2 SRAM" - depends on BFIN_ICACHE - depends on (BF54x || BF561 || BF60x) && !SMP - default n - -config BFIN_DCACHE - bool "Enable DCACHE" - default y -config BFIN_DCACHE_BANKA - bool "Enable only 16k BankA DCACHE - BankB is SRAM" - depends on BFIN_DCACHE && !BF531 - default n -config BFIN_EXTMEM_DCACHEABLE - bool "Enable DCACHE for external memory" - depends on BFIN_DCACHE - default y -choice - prompt "External memory DCACHE policy" - depends on BFIN_EXTMEM_DCACHEABLE - default BFIN_EXTMEM_WRITEBACK if !SMP - default BFIN_EXTMEM_WRITETHROUGH if SMP -config BFIN_EXTMEM_WRITEBACK - bool "Write back" - depends on !SMP - help - Write Back Policy: - Cached data will be written back to SDRAM only when needed. - This can give a nice increase in performance, but beware of - broken drivers that do not properly invalidate/flush their - cache. - - Write Through Policy: - Cached data will always be written back to SDRAM when the - cache is updated. This is a completely safe setting, but - performance is worse than Write Back. - - If you are unsure of the options and you want to be safe, - then go with Write Through. - -config BFIN_EXTMEM_WRITETHROUGH - bool "Write through" - help - Write Back Policy: - Cached data will be written back to SDRAM only when needed. - This can give a nice increase in performance, but beware of - broken drivers that do not properly invalidate/flush their - cache. - - Write Through Policy: - Cached data will always be written back to SDRAM when the - cache is updated. This is a completely safe setting, but - performance is worse than Write Back. - - If you are unsure of the options and you want to be safe, - then go with Write Through. - -endchoice - -config BFIN_L2_DCACHEABLE - bool "Enable DCACHE for L2 SRAM" - depends on BFIN_DCACHE - depends on (BF54x || BF561 || BF60x) && !SMP - default n -choice - prompt "L2 SRAM DCACHE policy" - depends on BFIN_L2_DCACHEABLE - default BFIN_L2_WRITEBACK -config BFIN_L2_WRITEBACK - bool "Write back" - -config BFIN_L2_WRITETHROUGH - bool "Write through" -endchoice - - -comment "Memory Protection Unit" -config MPU - bool "Enable the memory protection unit" - default n - help - Use the processor's MPU to protect applications from accessing - memory they do not own. This comes at a performance penalty - and is recommended only for debugging. - -comment "Asynchronous Memory Configuration" - -menu "EBIU_AMGCTL Global Control" - depends on !BF60x -config C_AMCKEN - bool "Enable CLKOUT" - default y - -config C_CDPRIO - bool "DMA has priority over core for ext. accesses" - default n - -config C_B0PEN - depends on BF561 - bool "Bank 0 16 bit packing enable" - default y - -config C_B1PEN - depends on BF561 - bool "Bank 1 16 bit packing enable" - default y - -config C_B2PEN - depends on BF561 - bool "Bank 2 16 bit packing enable" - default y - -config C_B3PEN - depends on BF561 - bool "Bank 3 16 bit packing enable" - default n - -choice - prompt "Enable Asynchronous Memory Banks" - default C_AMBEN_ALL - -config C_AMBEN - bool "Disable All Banks" - -config C_AMBEN_B0 - bool "Enable Bank 0" - -config C_AMBEN_B0_B1 - bool "Enable Bank 0 & 1" - -config C_AMBEN_B0_B1_B2 - bool "Enable Bank 0 & 1 & 2" - -config C_AMBEN_ALL - bool "Enable All Banks" -endchoice -endmenu - -menu "EBIU_AMBCTL Control" - depends on !BF60x -config BANK_0 - hex "Bank 0 (AMBCTL0.L)" - default 0x7BB0 - help - These are the low 16 bits of the EBIU_AMBCTL0 MMR which are - used to control the Asynchronous Memory Bank 0 settings. - -config BANK_1 - hex "Bank 1 (AMBCTL0.H)" - default 0x7BB0 - default 0x5558 if BF54x - help - These are the high 16 bits of the EBIU_AMBCTL0 MMR which are - used to control the Asynchronous Memory Bank 1 settings. - -config BANK_2 - hex "Bank 2 (AMBCTL1.L)" - default 0x7BB0 - help - These are the low 16 bits of the EBIU_AMBCTL1 MMR which are - used to control the Asynchronous Memory Bank 2 settings. - -config BANK_3 - hex "Bank 3 (AMBCTL1.H)" - default 0x99B3 - help - These are the high 16 bits of the EBIU_AMBCTL1 MMR which are - used to control the Asynchronous Memory Bank 3 settings. - -endmenu - -config EBIU_MBSCTLVAL - hex "EBIU Bank Select Control Register" - depends on BF54x - default 0 - -config EBIU_MODEVAL - hex "Flash Memory Mode Control Register" - depends on BF54x - default 1 - -config EBIU_FCTLVAL - hex "Flash Memory Bank Control Register" - depends on BF54x - default 6 -endmenu - -############################################################################# -menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" - -config PCI - bool "PCI support" - depends on BROKEN - help - Support for PCI bus. - -source "drivers/pci/Kconfig" - -source "drivers/pcmcia/Kconfig" - -endmenu - -menu "Executable file formats" - -source "fs/Kconfig.binfmt" - -endmenu - -menu "Power management options" - -source "kernel/power/Kconfig" - -config ARCH_SUSPEND_POSSIBLE - def_bool y - -choice - prompt "Standby Power Saving Mode" - depends on PM && !BF60x - default PM_BFIN_SLEEP_DEEPER -config PM_BFIN_SLEEP_DEEPER - bool "Sleep Deeper" - help - Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic - power dissipation by disabling the clock to the processor core (CCLK). - Furthermore, Standby sets the internal power supply voltage (VDDINT) - to 0.85 V to provide the greatest power savings, while preserving the - processor state. - The PLL and system clock (SCLK) continue to operate at a very low - frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, - the SDRAM is put into Self Refresh Mode. Typically an external event - such as GPIO interrupt or RTC activity wakes up the processor. - Various Peripherals such as UART, SPORT, PPI may not function as - normal during Sleep Deeper, due to the reduced SCLK frequency. - When in the sleep mode, system DMA access to L1 memory is not supported. - - If unsure, select "Sleep Deeper". - -config PM_BFIN_SLEEP - bool "Sleep" - help - Sleep Mode (High Power Savings) - The sleep mode reduces power - dissipation by disabling the clock to the processor core (CCLK). - The PLL and system clock (SCLK), however, continue to operate in - this mode. Typically an external event or RTC activity will wake - up the processor. When in the sleep mode, system DMA access to L1 - memory is not supported. - - If unsure, select "Sleep Deeper". -endchoice - -comment "Possible Suspend Mem / Hibernate Wake-Up Sources" - depends on PM - -config PM_BFIN_WAKE_PH6 - bool "Allow Wake-Up from on-chip PHY or PH6 GP" - depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) - default n - help - Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) - -config PM_BFIN_WAKE_GP - bool "Allow Wake-Up from GPIOs" - depends on PM && BF54x - default n - help - Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) - (all processors, except ADSP-BF549). This option sets - the general-purpose wake-up enable (GPWE) control bit to enable - wake-up upon detection of an active low signal on the /GPW (PH7) pin. - On ADSP-BF549 this option enables the same functionality on the - /MRXON pin also PH7. - -config PM_BFIN_WAKE_PA15 - bool "Allow Wake-Up from PA15" - depends on PM && BF60x - default n - help - Enable PA15 Wake-Up - -config PM_BFIN_WAKE_PA15_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_PA15 - default 0 - help - Wake-Up priority 0(low) 1(high) - -config PM_BFIN_WAKE_PB15 - bool "Allow Wake-Up from PB15" - depends on PM && BF60x - default n - help - Enable PB15 Wake-Up - -config PM_BFIN_WAKE_PB15_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_PB15 - default 0 - help - Wake-Up priority 0(low) 1(high) - -config PM_BFIN_WAKE_PC15 - bool "Allow Wake-Up from PC15" - depends on PM && BF60x - default n - help - Enable PC15 Wake-Up - -config PM_BFIN_WAKE_PC15_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_PC15 - default 0 - help - Wake-Up priority 0(low) 1(high) - -config PM_BFIN_WAKE_PD06 - bool "Allow Wake-Up from PD06(ETH0_PHYINT)" - depends on PM && BF60x - default n - help - Enable PD06(ETH0_PHYINT) Wake-up - -config PM_BFIN_WAKE_PD06_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_PD06 - default 0 - help - Wake-Up priority 0(low) 1(high) - -config PM_BFIN_WAKE_PE12 - bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" - depends on PM && BF60x - default n - help - Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up - -config PM_BFIN_WAKE_PE12_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_PE12 - default 0 - help - Wake-Up priority 0(low) 1(high) - -config PM_BFIN_WAKE_PG04 - bool "Allow Wake-Up from PG04(CAN0_RX)" - depends on PM && BF60x - default n - help - Enable PG04(CAN0_RX) Wake-up - -config PM_BFIN_WAKE_PG04_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_PG04 - default 0 - help - Wake-Up priority 0(low) 1(high) - -config PM_BFIN_WAKE_PG13 - bool "Allow Wake-Up from PG13" - depends on PM && BF60x - default n - help - Enable PG13 Wake-Up - -config PM_BFIN_WAKE_PG13_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_PG13 - default 0 - help - Wake-Up priority 0(low) 1(high) - -config PM_BFIN_WAKE_USB - bool "Allow Wake-Up from (USB)" - depends on PM && BF60x - default n - help - Enable (USB) Wake-up - -config PM_BFIN_WAKE_USB_POL - int "Wake-up priority" - depends on PM_BFIN_WAKE_USB - default 0 - help - Wake-Up priority 0(low) 1(high) - -endmenu - -menu "CPU Frequency scaling" - -source "drivers/cpufreq/Kconfig" - -config BFIN_CPU_FREQ - bool - depends on CPU_FREQ - default y - -config CPU_VOLTAGE - bool "CPU Voltage scaling" - depends on CPU_FREQ - default n - help - Say Y here if you want CPU voltage scaling according to the CPU frequency. - This option violates the PLL BYPASS recommendation in the Blackfin Processor - manuals. There is a theoretical risk that during VDDINT transitions - the PLL may unlock. - -endmenu - -source "net/Kconfig" - -source "drivers/Kconfig" - -source "drivers/firmware/Kconfig" - -source "fs/Kconfig" - -source "arch/blackfin/Kconfig.debug" - -source "security/Kconfig" - -source "crypto/Kconfig" - -source "lib/Kconfig" diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug deleted file mode 100644 index c8d957274cc2..000000000000 --- a/arch/blackfin/Kconfig.debug +++ /dev/null @@ -1,258 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menu "Kernel hacking" - -source "lib/Kconfig.debug" - -config DEBUG_VERBOSE - bool "Verbose fault messages" - default y - select PRINTK - help - When a program crashes due to an exception, or the kernel detects - an internal error, the kernel can print a not so brief message - explaining what the problem was. This debugging information is - useful to developers and kernel hackers when tracking down problems, - but mostly meaningless to other people. This is always helpful for - debugging but serves no purpose on a production system. - Most people should say N here. - -config DEBUG_MMRS - tristate "Generate Blackfin MMR tree" - depends on !PINCTRL - select DEBUG_FS - help - Create a tree of Blackfin MMRs via the debugfs tree. If - you enable this, you will find all MMRs laid out in the - /sys/kernel/debug/blackfin/ directory where you can read/write - MMRs directly from userspace. This is obviously just a debug - feature. - -config DEBUG_HWERR - bool "Hardware error interrupt debugging" - depends on DEBUG_KERNEL - help - When enabled, the hardware error interrupt is never disabled, and - will happen immediately when an error condition occurs. This comes - at a slight cost in code size, but is necessary if you are getting - hardware error interrupts and need to know where they are coming - from. - -config EXACT_HWERR - bool "Try to make Hardware errors exact" - depends on DEBUG_HWERR - help - By default, the Blackfin hardware errors are not exact - the error - be reported multiple cycles after the error happens. This delay - can cause the wrong application, or even the kernel to receive a - signal to be killed. If you are getting HW errors in your system, - try turning this on to ensure they are at least coming from the - proper thread. - - On production systems, it is safe (and a small optimization) to say N. - -config DEBUG_DOUBLEFAULT - bool "Debug Double Faults" - default n - help - If an exception is caused while executing code within the exception - handler, the NMI handler, the reset vector, or in emulator mode, - a double fault occurs. On the Blackfin, this is a unrecoverable - event. You have two options: - - RESET exactly when double fault occurs. The excepting - instruction address is stored in RETX, where the next kernel - boot will print it out. - - Print debug message. This is much more error prone, although - easier to handle. It is error prone since: - - The excepting instruction is not committed. - - All writebacks from the instruction are prevented. - - The generated exception is not taken. - - The EXCAUSE field is updated with an unrecoverable event - The only way to check this is to see if EXCAUSE contains the - unrecoverable event value at every exception return. By selecting - this option, you are skipping over the faulting instruction, and - hoping things stay together enough to print out a debug message. - - This does add a little kernel code, but is the only method to debug - double faults - if unsure say "Y" - -choice - prompt "Double Fault Failure Method" - default DEBUG_DOUBLEFAULT_PRINT - depends on DEBUG_DOUBLEFAULT - -config DEBUG_DOUBLEFAULT_PRINT - bool "Print" - -config DEBUG_DOUBLEFAULT_RESET - bool "Reset" - -endchoice - -config DEBUG_HUNT_FOR_ZERO - bool "Catch NULL pointer reads/writes" - default y - help - Say Y here to catch reads/writes to anywhere in the memory range - from 0x0000 - 0x0FFF (the first 4k) of memory. This is useful in - catching common programming errors such as NULL pointer dereferences. - - Misbehaving applications will be killed (generate a SEGV) while the - kernel will trigger a panic. - - Enabling this option will take up an extra entry in CPLB table. - Otherwise, there is no extra overhead. - -config DEBUG_BFIN_HWTRACE_ON - bool "Turn on Blackfin's Hardware Trace" - default y - help - All Blackfins include a Trace Unit which stores a history of the last - 16 changes in program flow taken by the program sequencer. The history - allows the user to recreate the program sequencer’s recent path. This - can be handy when an application dies - we print out the execution - path of how it got to the offending instruction. - - By turning this off, you may save a tiny amount of power. - -choice - prompt "Omit loop Tracing" - default DEBUG_BFIN_HWTRACE_COMPRESSION_OFF - depends on DEBUG_BFIN_HWTRACE_ON - help - The trace buffer can be configured to omit recording of changes in - program flow that match either the last entry or one of the last - two entries. Omitting one of these entries from the record prevents - the trace buffer from overflowing because of any sort of loop (for, do - while, etc) in the program. - - Because zero-overhead Hardware loops are not recorded in the trace buffer, - this feature can be used to prevent trace overflow from loops that - are nested four deep. - -config DEBUG_BFIN_HWTRACE_COMPRESSION_OFF - bool "Trace all Loops" - help - The trace buffer records all changes of flow - -config DEBUG_BFIN_HWTRACE_COMPRESSION_ONE - bool "Compress single-level loops" - help - The trace buffer does not record single loops - helpful if trace - is spinning on a while or do loop. - -config DEBUG_BFIN_HWTRACE_COMPRESSION_TWO - bool "Compress two-level loops" - help - The trace buffer does not record loops two levels deep. Helpful if - the trace is spinning in a nested loop - -endchoice - -config DEBUG_BFIN_HWTRACE_COMPRESSION - int - depends on DEBUG_BFIN_HWTRACE_ON - default 0 if DEBUG_BFIN_HWTRACE_COMPRESSION_OFF - default 1 if DEBUG_BFIN_HWTRACE_COMPRESSION_ONE - default 2 if DEBUG_BFIN_HWTRACE_COMPRESSION_TWO - - -config DEBUG_BFIN_HWTRACE_EXPAND - bool "Expand Trace Buffer greater than 16 entries" - depends on DEBUG_BFIN_HWTRACE_ON - default n - help - By selecting this option, every time the 16 hardware entries in - the Blackfin's HW Trace buffer are full, the kernel will move them - into a software buffer, for dumping when there is an issue. This - has a great impact on performance, (an interrupt every 16 change of - flows) and should normally be turned off, except in those nasty - debugging sessions - -config DEBUG_BFIN_HWTRACE_EXPAND_LEN - int "Size of Trace buffer (in power of 2k)" - range 0 4 - depends on DEBUG_BFIN_HWTRACE_EXPAND - default 1 - help - This sets the size of the software buffer that the trace information - is kept in. - 0 for (2^0) 1k, or 256 entries, - 1 for (2^1) 2k, or 512 entries, - 2 for (2^2) 4k, or 1024 entries, - 3 for (2^3) 8k, or 2048 entries, - 4 for (2^4) 16k, or 4096 entries - -config DEBUG_BFIN_NO_KERN_HWTRACE - bool "Turn off hwtrace in CPLB handlers" - depends on DEBUG_BFIN_HWTRACE_ON - default y - help - The CPLB error handler contains a lot of flow changes which can - quickly fill up the hardware trace buffer. When debugging crashes, - the hardware trace may indicate that the problem lies in kernel - space when in reality an application is buggy. - - Say Y here to disable hardware tracing in some known "jumpy" pieces - of code so that the trace buffer will extend further back. - -config EARLY_PRINTK - bool "Early printk" - default n - select SERIAL_CORE_CONSOLE - help - This option enables special console drivers which allow the kernel - to print messages very early in the bootup process. - - This is useful for kernel debugging when your machine crashes very - early before the console code is initialized. After enabling this - feature, you must add "earlyprintk=serial,uart0,57600" to the - command line (bootargs). It is safe to say Y here in all cases, as - all of this lives in the init section and is thrown away after the - kernel boots completely. - -config NMI_WATCHDOG - bool "Enable NMI watchdog to help debugging lockup on SMP" - default n - depends on SMP - help - If any CPU in the system does not execute the period local timer - interrupt for more than 5 seconds, then the NMI handler dumps debug - information. This information can be used to debug the lockup. - -config CPLB_INFO - bool "Display the CPLB information" - help - Display the CPLB information via /proc/cplbinfo. - -config ACCESS_CHECK - bool "Check the user pointer address" - default y - help - Usually the pointer transfer from user space is checked to see if its - address is in the kernel space. - - Say N here to disable that check to improve the performance. - -config BFIN_ISRAM_SELF_TEST - bool "isram boot self tests" - default n - help - Run some self tests of the isram driver code at boot. - -config BFIN_PSEUDODBG_INSNS - bool "Support pseudo debug instructions" - default n - help - This option allows the kernel to emulate some pseudo instructions which - allow simulator test cases to be run under Linux with no changes. - - Most people should say N here. - -config BFIN_PM_WAKEUP_TIME_BENCH - bool "Display the total time for kernel to resume from power saving mode" - default n - help - Display the total time when kernel resumes normal from standby or - suspend to mem mode. - -endmenu diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile deleted file mode 100644 index 1fce08632ad7..000000000000 --- a/arch/blackfin/Makefile +++ /dev/null @@ -1,168 +0,0 @@ -# -# arch/blackfin/Makefile -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# - -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := bfin-uclinux- -endif -LDFLAGS_vmlinux := -X -OBJCOPYFLAGS := -O binary -R .note -R .comment -S -GZFLAGS := -9 - -KBUILD_CFLAGS += $(call cc-option,-mno-fdpic) -ifeq ($(CONFIG_ROMKERNEL),y) -KBUILD_CFLAGS += -mlong-calls -endif -KBUILD_AFLAGS += $(call cc-option,-mno-fdpic) -KBUILD_CFLAGS_MODULE += -mlong-calls -LDFLAGS += -m elf32bfin - -KBUILD_DEFCONFIG := BF537-STAMP_defconfig - -# setup the machine name and the machine dependent settings -machine-$(CONFIG_BF512) := bf518 -machine-$(CONFIG_BF514) := bf518 -machine-$(CONFIG_BF516) := bf518 -machine-$(CONFIG_BF518) := bf518 -machine-$(CONFIG_BF522) := bf527 -machine-$(CONFIG_BF523) := bf527 -machine-$(CONFIG_BF524) := bf527 -machine-$(CONFIG_BF525) := bf527 -machine-$(CONFIG_BF526) := bf527 -machine-$(CONFIG_BF527) := bf527 -machine-$(CONFIG_BF531) := bf533 -machine-$(CONFIG_BF532) := bf533 -machine-$(CONFIG_BF533) := bf533 -machine-$(CONFIG_BF534) := bf537 -machine-$(CONFIG_BF536) := bf537 -machine-$(CONFIG_BF537) := bf537 -machine-$(CONFIG_BF538) := bf538 -machine-$(CONFIG_BF539) := bf538 -machine-$(CONFIG_BF542) := bf548 -machine-$(CONFIG_BF542M) := bf548 -machine-$(CONFIG_BF544) := bf548 -machine-$(CONFIG_BF544M) := bf548 -machine-$(CONFIG_BF547) := bf548 -machine-$(CONFIG_BF547M) := bf548 -machine-$(CONFIG_BF548) := bf548 -machine-$(CONFIG_BF548M) := bf548 -machine-$(CONFIG_BF549) := bf548 -machine-$(CONFIG_BF549M) := bf548 -machine-$(CONFIG_BF561) := bf561 -machine-$(CONFIG_BF609) := bf609 -MACHINE := $(machine-y) -export MACHINE - -cpu-$(CONFIG_BF512) := bf512 -cpu-$(CONFIG_BF514) := bf514 -cpu-$(CONFIG_BF516) := bf516 -cpu-$(CONFIG_BF518) := bf518 -cpu-$(CONFIG_BF522) := bf522 -cpu-$(CONFIG_BF523) := bf523 -cpu-$(CONFIG_BF524) := bf524 -cpu-$(CONFIG_BF525) := bf525 -cpu-$(CONFIG_BF526) := bf526 -cpu-$(CONFIG_BF527) := bf527 -cpu-$(CONFIG_BF531) := bf531 -cpu-$(CONFIG_BF532) := bf532 -cpu-$(CONFIG_BF533) := bf533 -cpu-$(CONFIG_BF534) := bf534 -cpu-$(CONFIG_BF536) := bf536 -cpu-$(CONFIG_BF537) := bf537 -cpu-$(CONFIG_BF538) := bf538 -cpu-$(CONFIG_BF539) := bf539 -cpu-$(CONFIG_BF542) := bf542 -cpu-$(CONFIG_BF542M) := bf542m -cpu-$(CONFIG_BF544) := bf544 -cpu-$(CONFIG_BF544M) := bf544m -cpu-$(CONFIG_BF547) := bf547 -cpu-$(CONFIG_BF547M) := bf547m -cpu-$(CONFIG_BF548) := bf548 -cpu-$(CONFIG_BF548M) := bf548m -cpu-$(CONFIG_BF549) := bf549 -cpu-$(CONFIG_BF549M) := bf549m -cpu-$(CONFIG_BF561) := bf561 -cpu-$(CONFIG_BF609) := bf609 - -rev-$(CONFIG_BF_REV_0_0) := 0.0 -rev-$(CONFIG_BF_REV_0_1) := 0.1 -rev-$(CONFIG_BF_REV_0_2) := 0.2 -rev-$(CONFIG_BF_REV_0_3) := 0.3 -rev-$(CONFIG_BF_REV_0_4) := 0.4 -rev-$(CONFIG_BF_REV_0_5) := 0.5 -rev-$(CONFIG_BF_REV_0_6) := 0.6 -rev-$(CONFIG_BF_REV_NONE) := none -rev-$(CONFIG_BF_REV_ANY) := any - -CPU_REV := $(cpu-y)-$(rev-y) -export CPU_REV - -KBUILD_CFLAGS += -mcpu=$(CPU_REV) -KBUILD_AFLAGS += -mcpu=$(CPU_REV) - -# - we utilize the silicon rev from the toolchain, so move it over to the checkflags -CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') -CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__ - -core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/ - -# If we have a machine-specific directory, then include it in the build. -ifneq ($(machine-y),) -core-y += arch/$(ARCH)/mach-$(MACHINE)/ -core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/ -endif - -ifeq ($(CONFIG_MPU),y) -core-y += arch/$(ARCH)/kernel/cplb-mpu/ -else -core-y += arch/$(ARCH)/kernel/cplb-nompu/ -endif - -drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/ - -libs-y += arch/$(ARCH)/lib/ - -machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y)) - -KBUILD_CFLAGS += -Iarch/$(ARCH)/include/ -KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include - -KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) - -CLEAN_FILES += \ - arch/$(ARCH)/kernel/asm-offsets.s \ - -archclean: - $(Q)$(MAKE) $(clean)=$(boot) - -INSTALL_PATH ?= /tftpboot -boot := arch/$(ARCH)/boot -BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip -PHONY += $(BOOT_TARGETS) install -KBUILD_IMAGE := $(boot)/uImage - -all: uImage - -$(BOOT_TARGETS): vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ - -install: - $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install - -define archhelp - echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)' - echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)' - echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)' - echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)' - echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)' - echo ' vmImage.lzo - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzo)' - echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)' - echo ' install - Install kernel using' - echo ' (your) ~/bin/$(INSTALLKERNEL) or' - echo ' (distribution) PATH: $(INSTALLKERNEL) or' - echo ' install to $$(INSTALL_PATH)' -endef diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore deleted file mode 100644 index 1287a5487e7d..000000000000 --- a/arch/blackfin/boot/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -vmImage* -vmlinux* -uImage* diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile deleted file mode 100644 index 3efaa094fb90..000000000000 --- a/arch/blackfin/boot/Makefile +++ /dev/null @@ -1,71 +0,0 @@ -# -# arch/blackfin/boot/Makefile -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# - -targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip -extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip - -ifeq ($(CONFIG_RAMKERNEL),y) -UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD) -else # CONFIG_ROMKERNEL must be set -UIMAGE_LOADADDR = $(CONFIG_ROM_BASE) -endif -UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') -UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)' -UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x - -$(obj)/vmlinux.bin: vmlinux FORCE - $(call if_changed,objcopy) - -$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE - $(call if_changed,gzip) - -$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE - $(call if_changed,bzip2) - -$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE - $(call if_changed,lzma) - -$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE - $(call if_changed,lzo) - -# The mkimage tool wants 64bytes prepended to the image -quiet_cmd_mk_bin_xip = BIN $@ - cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@ -$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE - $(call if_changed,mk_bin_xip) - -$(obj)/uImage.bin: $(obj)/vmlinux.bin - $(call if_changed,uimage,none) - -$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 - $(call if_changed,uimage,bzip2) - -$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz - $(call if_changed,uimage,gzip) - -$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma - $(call if_changed,uimage,lzma) - -$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo - $(call if_changed,uimage,lzo) - -$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip - $(call if_changed,uimage,none) - -suffix-y := bin -suffix-$(CONFIG_KERNEL_GZIP) := gz -suffix-$(CONFIG_KERNEL_BZIP2) := bz2 -suffix-$(CONFIG_KERNEL_LZMA) := lzma -suffix-$(CONFIG_KERNEL_LZO) := lzo -suffix-$(CONFIG_ROMKERNEL) := xip - -$(obj)/uImage: $(obj)/uImage.$(suffix-y) - @ln -sf $(notdir $<) $@ - -install: - sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)" diff --git a/arch/blackfin/boot/install.sh b/arch/blackfin/boot/install.sh deleted file mode 100644 index e2c6e40902b7..000000000000 --- a/arch/blackfin/boot/install.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/sh -# -# arch/blackfin/boot/install.sh -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 1995 by Linus Torvalds -# -# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin -# Adapted from code in arch/i386/boot/install.sh by Mike Frysinger -# -# "make install" script for Blackfin architecture -# -# Arguments: -# $1 - kernel version -# $2 - kernel image file -# $3 - kernel map file -# $4 - default install path (blank if root directory) -# - -verify () { - if [ ! -f "$1" ]; then - echo "" 1>&2 - echo " *** Missing file: $1" 1>&2 - echo ' *** You need to run "make" before "make install".' 1>&2 - echo "" 1>&2 - exit 1 - fi -} - -# Make sure the files actually exist -verify "$2" -verify "$3" - -# User may have a custom install script - -if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi -if which ${INSTALLKERNEL} >/dev/null 2>&1; then - exec ${INSTALLKERNEL} "$@" -fi - -# Default install - same as make zlilo - -back_it_up() { - local file=$1 - [ -f ${file} ] || return 0 - local stamp=$(stat -c %Y ${file} 2>/dev/null) - mv ${file} ${file}.${stamp:-old} -} - -back_it_up $4/uImage -back_it_up $4/System.map - -cat $2 > $4/uImage -cp $3 $4/System.map diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig deleted file mode 100644 index 99c00d835f47..000000000000 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ /dev/null @@ -1,121 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF518=y -CONFIG_IRQ_TIMER0=12 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_NET_BFIN=y -CONFIG_BFIN_MAC=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_SDH_BFIN=y -CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=m -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig deleted file mode 100644 index e66ba31ef84d..000000000000 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ /dev/null @@ -1,158 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF526=y -CONFIG_IRQ_TIMER0=12 -CONFIG_BFIN526_EZBRD=y -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=m -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_BFIN=y -CONFIG_BFIN_MAC=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GYRATION=y -CONFIG_HID_LOGITECH=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=y -CONFIG_USB_STORAGE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=m -# CONFIG_DNOTIFY is not set -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_VFAT_FS=m -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig deleted file mode 100644 index d95658fc3127..000000000000 --- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_PREEMPT=y -CONFIG_BF527=y -CONFIG_BF_REV_0_2=y -CONFIG_IRQ_TWI=7 -CONFIG_IRQ_PORTH_INTA=7 -CONFIG_IRQ_PORTH_INTB=7 -CONFIG_BFIN527_AD7160EVAL=y -CONFIG_BF527_SPORT0_PORTF=y -CONFIG_BF527_UART1_PORTG=y -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600" -CONFIG_CLKIN_HZ=24000000 -CONFIG_HZ_300=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_BFIN_GPTIMERS=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_1=0x5554 -CONFIG_BANK_3=0xFFC0 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_UNIX=y -# CONFIG_WIRELESS is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_AD7160=y -CONFIG_TOUCHSCREEN_AD7160_FW=y -# CONFIG_SERIO is not set -# CONFIG_BFIN_DMA_INTERFACE is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_BFIN_OTP is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_LOGO_BLACKFIN_VGA16 is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_G_SERIAL=y -CONFIG_MMC=y -CONFIG_MMC_SPI=y -CONFIG_EXT2_FS=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig deleted file mode 100644 index 0207c588c19f..000000000000 --- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig +++ /dev/null @@ -1,188 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF527=y -CONFIG_BF_REV_0_2=y -CONFIG_BFIN527_EZKIT_V2=y -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRTTY_SIR=m -CONFIG_BFIN_SIR=m -CONFIG_BFIN_SIR0=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=m -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_BFIN=y -CONFIG_BFIN_MAC=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ADP5520=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_AD7879=y -CONFIG_TOUCHSCREEN_AD7879_I2C=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_PMIC_ADP5520=y -CONFIG_FB=y -CONFIG_FB_BFIN_LQ035Q1=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_LOGO_BLACKFIN_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SOC=y -CONFIG_SND_BF5XX_I2S=y -CONFIG_SND_BF5XX_SOC_SSM2602=y -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GYRATION=y -CONFIG_HID_LOGITECH=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_BLACKFIN=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_ADP5520=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=m -# CONFIG_DNOTIFY is not set -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_VFAT_FS=m -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig deleted file mode 100644 index 99c131ba7d90..000000000000 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ /dev/null @@ -1,181 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF527=y -CONFIG_BF_REV_0_1=y -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRTTY_SIR=m -CONFIG_BFIN_SIR=m -CONFIG_BFIN_SIR0=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=m -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_BFIN=y -CONFIG_BFIN_MAC=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_FB=y -CONFIG_FB_BFIN_T350MCQB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_LTV350QV=m -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_LOGO_BLACKFIN_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SOC=y -CONFIG_SND_BF5XX_I2S=y -CONFIG_SND_BF5XX_SOC_SSM2602=y -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GYRATION=y -CONFIG_HID_LOGITECH=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_USB_MUSB_BLACKFIN=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=m -# CONFIG_DNOTIFY is not set -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_VFAT_FS=m -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF527-TLL6527M_defconfig b/arch/blackfin/configs/BF527-TLL6527M_defconfig deleted file mode 100644 index cdeb51856f26..000000000000 --- a/arch/blackfin/configs/BF527-TLL6527M_defconfig +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="DEV_0-1_pre2010" -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF527=y -CONFIG_BF_REV_0_2=y -CONFIG_BFIN527_TLL6527M=y -CONFIG_BF527_UART1_PORTG=y -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 -CONFIG_BOOT_LOAD=0x400000 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_DMA_UNCACHED_2M=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_0=0xFFC2 -CONFIG_BANK_1=0xFFC2 -CONFIG_BANK_2=0xFFC2 -CONFIG_BANK_3=0xFFC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRTTY_SIR=m -CONFIG_BFIN_SIR=m -CONFIG_BFIN_SIR0=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_GPIO_ADDR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_AD7879=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_AD714X=y -CONFIG_INPUT_ADXL34X=y -# CONFIG_SERIO is not set -CONFIG_BFIN_PPI=m -CONFIG_BFIN_SIMPLE_TIMER=m -CONFIG_BFIN_SPORT=m -# CONFIG_CONSOLE_TRANSLATIONS is not set -# CONFIG_DEVKMEM is not set -CONFIG_BFIN_JTAG_COMM=m -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_SMBUS=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_DEV=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -CONFIG_VIDEO_BLACKFIN_CAM=m -CONFIG_OV9655=y -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_6x11=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_LOGO_BLACKFIN_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_SOC=y -CONFIG_SND_BF5XX_I2S=y -CONFIG_SND_BF5XX_SOC_SSM2602=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=y -# CONFIG_DNOTIFY is not set -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC7=m diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig deleted file mode 100644 index ed7d2c096739..000000000000 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ /dev/null @@ -1,114 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BFIN533_EZKIT=y -CONFIG_TIMER0=11 -CONFIG_CLKIN_HZ=27000000 -CONFIG_HIGH_RES_TIMERS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xAAC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PLATRAM=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMC91X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -CONFIG_INPUT=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig deleted file mode 100644 index 0c241f4d28d7..000000000000 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ /dev/null @@ -1,124 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_TIMER0=11 -CONFIG_HIGH_RES_TIMERS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xAAC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -CONFIG_BFIN_SIR=m -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMC91X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_GPIO=m -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_FB=m -CONFIG_FIRMWARE_EDID=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_SOC=m -CONFIG_SND_BF5XX_I2S=m -CONFIG_SND_BF5XX_SOC_AD73311=m -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig deleted file mode 100644 index e5360b30e39a..000000000000 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ /dev/null @@ -1,136 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF537=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m -CONFIG_CAN_BFIN=m -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -CONFIG_BFIN_SIR=m -CONFIG_BFIN_SIR1=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_NET_BFIN=y -CONFIG_BFIN_MAC=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_BLACKFIN_TWI=m -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_FB=m -CONFIG_FIRMWARE_EDID=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_SOC=m -CONFIG_SND_BF5XX_I2S=m -CONFIG_SND_BF5XX_SOC_AD73311=m -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig deleted file mode 100644 index 60f6fb86125c..000000000000 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ /dev/null @@ -1,133 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF538=y -CONFIG_IRQ_TIMER0=12 -CONFIG_IRQ_TIMER1=12 -CONFIG_IRQ_TIMER2=12 -CONFIG_HIGH_RES_TIMERS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m -CONFIG_CAN_DEV=m -CONFIG_CAN_BFIN=m -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -CONFIG_BFIN_SIR=m -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_NAND=m -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_PHYLIB=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_AD7879=y -CONFIG_TOUCHSCREEN_AD7879_SPI=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_BFIN_JTAG_COMM=m -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -CONFIG_SERIAL_BFIN_UART1=y -CONFIG_SERIAL_BFIN_UART2=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -CONFIG_I2C_BLACKFIN_TWI=m -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_FB=m -CONFIG_FB_BFIN_LQ035Q1=m -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig deleted file mode 100644 index 38cb17d218d4..000000000000 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ /dev/null @@ -1,207 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF548_std=y -CONFIG_IRQ_TIMER0=11 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_CACHELINE_ALIGNED_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_DMA_UNCACHED_2M=y -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y -CONFIG_BANK_3=0x99B2 -CONFIG_EBIU_MBSCTLVAL=0x0 -CONFIG_EBIU_MODEVAL=0x1 -CONFIG_EBIU_FCTLVAL=0x6 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m -CONFIG_CAN_BFIN=m -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRTTY_SIR=m -CONFIG_BFIN_SIR=m -CONFIG_BFIN_SIR3=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_FW_LOADER=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_BF5XX=y -# CONFIG_MTD_NAND_BF5XX_HWECC is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_RAM=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_ATA=y -# CONFIG_SATA_PMP is not set -CONFIG_PATA_BF54X=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMSC911X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_BFIN=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_AD7877=m -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_BF54X_LQ043=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_6x11=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_LOGO_BLACKFIN_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_SOC=y -CONFIG_SND_BF5XX_AC97=y -CONFIG_SND_BF5XX_SOC_AD1980=y -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GYRATION=y -CONFIG_HID_LOGITECH=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_BLACKFIN=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=m -CONFIG_SDH_BFIN=y -CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NFSD=m -CONFIG_NFSD_V3=y -CONFIG_CIFS=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig deleted file mode 100644 index 78f6bc79f910..000000000000 --- a/arch/blackfin/configs/BF561-ACVILON_defconfig +++ /dev/null @@ -1,149 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF561=y -CONFIG_BF_REV_0_5=y -CONFIG_IRQ_TIMER0=10 -CONFIG_BFIN561_ACVILON=y -# CONFIG_BF561_COREB is not set -CONFIG_CLKIN_HZ=12000000 -CONFIG_HIGH_RES_TIMERS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_DMA_UNCACHED_4M=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_0=0x99b2 -CONFIG_BANK_1=0x3350 -CONFIG_BANK_3=0xAAC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_PLATRAM=y -CONFIG_MTD_PHRAM=y -CONFIG_MTD_BLOCK2MTD=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=2 -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_PIO=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_PCA_PLATFORM=y -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_SPI_SPIDEV=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PCF857X=y -CONFIG_SENSORS_LM75=y -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=y -CONFIG_SND_BF5XX_I2S=y -CONFIG_SND_BF5XX_SPORT_NUM=1 -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_MON=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_FTDI_SIO=y -CONFIG_USB_SERIAL_PL2303=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=866 -CONFIG_FAT_DEFAULT_IOCHARSET="cp1251" -CONFIG_NTFS_FS=y -CONFIG_CONFIGFS_FS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -# CONFIG_JFFS2_ZLIB is not set -CONFIG_JFFS2_LZO=y -# CONFIG_JFFS2_RTIME is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_CRAMFS=y -CONFIG_MINIX_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_DEFAULT="cp1251" -CONFIG_NLS_CODEPAGE_866=y -CONFIG_NLS_CODEPAGE_1251=y -CONFIG_NLS_KOI8_R=y -CONFIG_NLS_UTF8=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_CPLB_INFO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig deleted file mode 100644 index fac8bb578249..000000000000 --- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig +++ /dev/null @@ -1,112 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF561=y -CONFIG_SMP=y -CONFIG_IRQ_TIMER0=10 -CONFIG_CLKIN_HZ=30000000 -CONFIG_HIGH_RES_TIMERS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xAAC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMC91X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -CONFIG_INPUT=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig deleted file mode 100644 index 2a2e4d0cebc1..000000000000 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ /dev/null @@ -1,114 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF561=y -CONFIG_IRQ_TIMER0=10 -CONFIG_CLKIN_HZ=30000000 -CONFIG_HIGH_RES_TIMERS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y -CONFIG_BFIN_L2_DCACHEABLE=y -CONFIG_BFIN_L2_WRITETHROUGH=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xAAC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMC91X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set -CONFIG_INPUT=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_JTAG_COMM=m -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig deleted file mode 100644 index 3ce77f07208a..000000000000 --- a/arch/blackfin/configs/BF609-EZKIT_defconfig +++ /dev/null @@ -1,154 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF609=y -CONFIG_PINT1_ASSIGN=0x01010000 -CONFIG_PINT2_ASSIGN=0x07000101 -CONFIG_PINT3_ASSIGN=0x02020303 -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -# CONFIG_APP_STACK_L1 is not set -# CONFIG_BFIN_INS_LOWOVERHEAD is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_PM_BFIN_WAKE_PE12=y -CONFIG_PM_BFIN_WAKE_PE12_POL=1 -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_CAN=y -CONFIG_CAN_BFIN=y -CONFIG_IRDA=y -CONFIG_IRTTY_SIR=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_FW_LOADER=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=m -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_IEEE1588=y -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_BFIN_ROTARY=y -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_SIMPLE_TIMER=m -# CONFIG_BFIN_CRC is not set -CONFIG_BFIN_LINKPORT=y -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_ADI_V3=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_PINCTRL_MCP23S08=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=m -CONFIG_USB=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_BLACKFIN=m -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_ZERO=y -CONFIG_MMC=y -CONFIG_SDH_BFIN=y -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=m -CONFIG_UBIFS_FS=m -CONFIG_NFS_FS=m -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -CONFIG_FRAME_POINTER=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_BFIN_PSEUDODBG_INSNS=y -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=m -CONFIG_CRYPTO_ARC4=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_DEV_BFIN_CRC=m diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig deleted file mode 100644 index f4a9200e1ab1..000000000000 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF532=y -CONFIG_BF_REV_0_5=y -CONFIG_BLACKSTAMP=y -CONFIG_TIMER0=11 -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_ROMKERNEL=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xAAC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_BINFMT_SHARED_FLAT=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_MISC_DEVICES=y -CONFIG_EEPROM_AT25=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=m -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_GPIO=m -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_SPI_SPIDEV=m -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_SPI=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_SMB_FS=y -CONFIG_CIFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_UTF8=y -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig deleted file mode 100644 index 1902bb05d086..000000000000 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ /dev/null @@ -1,129 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF527=y -CONFIG_BF_REV_0_1=y -CONFIG_IRQ_TIMER0=12 -CONFIG_BFIN527_BLUETECHNIX_CM=y -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xFFC0 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_GPIO_ADDR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_BLACKFIN_TWI=m -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_USB=m -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=m -CONFIG_USB_MUSB_HDRC=m -CONFIG_USB_MUSB_PERIPHERAL=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_USB_STORAGE=m -CONFIG_USB_GADGET=m -CONFIG_USB_ETH=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_G_PRINTER=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_FS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig deleted file mode 100644 index 9a5716d57ebc..000000000000 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ /dev/null @@ -1,76 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_BFIN533_BLUETECHNIX_CM=y -CONFIG_TIMER0=11 -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xFFC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_BINFMT_SHARED_FLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_PHYSMAP=y -CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -# CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_SPI=m -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig deleted file mode 100644 index 684592884349..000000000000 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ /dev/null @@ -1,107 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_BF537=y -CONFIG_IRQ_TIMER0=12 -CONFIG_BFIN537_BLUETECHNIX_CM_E=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xFFC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_BINFMT_SHARED_FLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_GPIO_ADDR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_USB_GADGET=m -CONFIG_USB_ETH=m -CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_SPI=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig deleted file mode 100644 index d9915e984787..000000000000 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ /dev/null @@ -1,96 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_BF537=y -CONFIG_IRQ_TIMER0=12 -CONFIG_BFIN537_BLUETECHNIX_CM_U=y -CONFIG_CLKIN_HZ=30000000 -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_C_CDPRIO=y -CONFIG_BANK_2=0xFFC2 -CONFIG_BANK_3=0xFFC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_BINFMT_SHARED_FLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_GPIO_ADDR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=y -CONFIG_MMC=y -CONFIG_MMC_SPI=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRC_CCITT=m -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig deleted file mode 100644 index 92d8130cdb51..000000000000 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ /dev/null @@ -1,170 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_BF548_std=y -CONFIG_BF_REV_ANY=y -CONFIG_IRQ_TIMER0=11 -CONFIG_BFIN548_BLUETECHNIX_CM=y -# CONFIG_DEB_DMA_URGENT is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_CACHELINE_ALIGNED_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y -CONFIG_BANK_1=0x5554 -CONFIG_EBIU_MBSCTLVAL=0x0 -CONFIG_EBIU_MODEVAL=0x1 -CONFIG_EBIU_FCTLVAL=0x6 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_PIO=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=m -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_MON=m -CONFIG_USB_MUSB_HDRC=m -CONFIG_USB_MUSB_PERIPHERAL=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_STORAGE=m -CONFIG_USB_GADGET=m -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_G_PRINTER=m -CONFIG_MMC=m -CONFIG_SDH_BFIN=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=m -CONFIG_EXT2_FS=m -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_CIFS=m -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_FS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig deleted file mode 100644 index fa8d91132a57..000000000000 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_BF561=y -CONFIG_IRQ_TIMER0=10 -CONFIG_BFIN561_BLUETECHNIX_CM=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xFFC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_BINFMT_SHARED_FLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_PHYLIB=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_SMSC911X=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_USB_GADGET=m -CONFIG_USB_ETH=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_G_PRINTER=m -CONFIG_MMC=y -CONFIG_MMC_SPI=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRC_CCITT=m -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig deleted file mode 100644 index 88600593c731..000000000000 --- a/arch/blackfin/configs/DNP5370_defconfig +++ /dev/null @@ -1,118 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="DNP5370" -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLOB=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_BF537=y -CONFIG_BF_REV_0_3=y -CONFIG_DNP5370=y -CONFIG_IRQ_ERROR=7 -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_C_CDPRIO=y -CONFIG_C_AMBEN_B0_B1_B2=y -CONFIG_PM=y -# CONFIG_SUSPEND is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_RARP=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_LLC2=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=1 -CONFIG_MTD_BLOCK=y -CONFIG_NFTL=y -CONFIG_NFTL_RW=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_ROM=y -CONFIG_MTD_ABSENT=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_UCLINUX=y -CONFIG_MTD_PLATRAM=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_BLOCK2MTD=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_DAVICOM_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_BFIN_DMA_INTERFACE is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_BFIN_JTAG_COMM=y -CONFIG_BFIN_JTAG_COMM_CONSOLE=y -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -CONFIG_LEGACY_PTY_COUNT=64 -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_SPI_SPIDEV=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_LM75=y -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_SPI=y -CONFIG_DMADEVICES=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=850 -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_ROMFS_FS=y -CONFIG_ROMFS_BACKED_BY_BOTH=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_LOCK_ALLOC=y -CONFIG_DEBUG_KOBJECT=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_VM=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DEBUG_LIST=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_PAGE_POISONING=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_CPLB_INFO=y -CONFIG_CRC_CCITT=y diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig deleted file mode 100644 index 0ff97d8d047a..000000000000 --- a/arch/blackfin/configs/H8606_defconfig +++ /dev/null @@ -1,87 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_BF532=y -CONFIG_BF_REV_0_5=y -CONFIG_H8606_HVSISTEMAS=y -CONFIG_TIMER0=11 -# CONFIG_CACHELINE_ALIGNED_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_C_CDPRIO=y -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -# CONFIG_WIRELESS is not set -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_MISC_DEVICES=y -CONFIG_EEPROM_AT25=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_SPI_SPIDEV=y -CONFIG_WATCHDOG=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_INTF_DEV_UIE_EMUL=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS=m -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_CPLB_INFO=y diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig deleted file mode 100644 index 9e3ae4b36d20..000000000000 --- a/arch/blackfin/configs/IP0X_defconfig +++ /dev/null @@ -1,91 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_HOTPLUG is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_BF532=y -CONFIG_BF_REV_0_5=y -CONFIG_BFIN532_IP0X=y -CONFIG_TIMER0=11 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -# CONFIG_BFIN_ICACHE is not set -# CONFIG_BFIN_DCACHE is not set -CONFIG_C_CDPRIO=y -CONFIG_BANK_0=0xffc2 -CONFIG_BANK_1=0xffc2 -CONFIG_BANK_2=0xffc2 -CONFIG_BANK_3=0xffc2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_MANGLE=y -# CONFIG_WIRELESS is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_UCLINUX=y -CONFIG_MTD_PLATRAM=y -CONFIG_MTD_NAND=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_USB=y -CONFIG_USB_OTG_WHITELIST=y -CONFIG_USB_MON=y -CONFIG_USB_ISP1362_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_MMC=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_CPLB_INFO=y -CONFIG_CRC_CCITT=y diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig deleted file mode 100644 index c7926812971c..000000000000 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF537=y -CONFIG_IRQ_TIMER0=12 -CONFIG_PNAV10=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_C_CDPRIO=y -CONFIG_BANK_1=0x33B0 -CONFIG_BANK_2=0x33B0 -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_RAM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_UCLINUX=y -CONFIG_MTD_NAND=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_BFIN_MAC=y -# CONFIG_BFIN_MAC_USE_L1 is not set -CONFIG_BFIN_TX_DESC_NUM=100 -CONFIG_BFIN_RX_DESC_NUM=100 -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_AD7877=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_SOUND=y -CONFIG_SND=m -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -CONFIG_SOUND_PRIME=y -# CONFIG_HID is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_DEBUG_HUNT_FOR_ZERO is not set -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -# CONFIG_ACCESS_CHECK is not set -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig deleted file mode 100644 index 23fdc57d657a..000000000000 --- a/arch/blackfin/configs/SRV1_defconfig +++ /dev/null @@ -1,88 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_ALL=y -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF537=y -CONFIG_IRQ_TIMER0=12 -CONFIG_BOOT_LOAD=0x400000 -CONFIG_CLKIN_HZ=22118400 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_DMA_UNCACHED_2M=y -CONFIG_C_CDPRIO=y -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_IPV6 is not set -CONFIG_IRDA=m -CONFIG_IRLAN=m -CONFIG_IRCOMM=m -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRTTY_SIR=m -# CONFIG_WIRELESS is not set -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_UCLINUX=y -CONFIG_MTD_NAND=m -CONFIG_BLK_DEV_RAM=y -CONFIG_MISC_DEVICES=y -CONFIG_EEPROM_AT25=m -CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_HWMON=m -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_HID is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_CPLB_INFO=y diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig deleted file mode 100644 index e28959479fe0..000000000000 --- a/arch/blackfin/configs/TCM-BF518_defconfig +++ /dev/null @@ -1,131 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BF518=y -CONFIG_BF_REV_0_1=y -CONFIG_BFIN518F_TCM=y -CONFIG_IRQ_TIMER0=12 -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_SCHEDULE_L1 is not set -# CONFIG_MEMSET_L1 is not set -# CONFIG_MEMCPY_L1 is not set -# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=m -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0x99B2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_CFI_I2 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -# CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set -CONFIG_BFIN_JTAG_COMM=m -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_DEBUG=y -CONFIG_MMC_SPI=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BFIN=y -CONFIG_EXT2_FS=y -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=m -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_MMRS=y -CONFIG_DEBUG_HWERR=y -CONFIG_EXACT_HWERR=y -CONFIG_DEBUG_DOUBLEFAULT=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig deleted file mode 100644 index 39e85cce95d7..000000000000 --- a/arch/blackfin/configs/TCM-BF537_defconfig +++ /dev/null @@ -1,95 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_FUTEX is not set -# CONFIG_AIO is not set -CONFIG_SLAB=y -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_BF537=y -CONFIG_IRQ_TIMER0=12 -CONFIG_BFIN537_BLUETECHNIX_TCM=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -CONFIG_IP_CHECKSUM_L1=y -CONFIG_SYSCALL_TAB_L1=y -CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_C_CDPRIO=y -CONFIG_BANK_3=0xFFC2 -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -CONFIG_BINFMT_SHARED_FLAT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_GPIO_ADDR=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_BFIN_MAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -CONFIG_SERIAL_BFIN_UART0=y -CONFIG_SERIAL_BFIN_UART1=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_SPI=y -CONFIG_SPI_BFIN5XX=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_BFIN_WDT=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=y -CONFIG_MMC=y -CONFIG_MMC_SPI=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y -CONFIG_CPLB_INFO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild deleted file mode 100644 index fe736973630f..000000000000 --- a/arch/blackfin/include/asm/Kbuild +++ /dev/null @@ -1,28 +0,0 @@ -generic-y += bugs.h -generic-y += current.h -generic-y += device.h -generic-y += div64.h -generic-y += emergency-restart.h -generic-y += extable.h -generic-y += fb.h -generic-y += futex.h -generic-y += hw_irq.h -generic-y += irq_regs.h -generic-y += irq_work.h -generic-y += kdebug.h -generic-y += kmap_types.h -generic-y += kprobes.h -generic-y += local.h -generic-y += local64.h -generic-y += mcs_spinlock.h -generic-y += mm-arch-hooks.h -generic-y += percpu.h -generic-y += pgalloc.h -generic-y += preempt.h -generic-y += serial.h -generic-y += topology.h -generic-y += trace_clock.h -generic-y += unaligned.h -generic-y += user.h -generic-y += word-at-a-time.h -generic-y += xor.h diff --git a/arch/blackfin/include/asm/asm-offsets.h b/arch/blackfin/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/arch/blackfin/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h deleted file mode 100644 index 63c7deceeeb6..000000000000 --- a/arch/blackfin/include/asm/atomic.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2004-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ARCH_BLACKFIN_ATOMIC__ -#define __ARCH_BLACKFIN_ATOMIC__ - -#include - -#ifdef CONFIG_SMP - -#include -#include -#include - -asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); -asmlinkage int __raw_atomic_add_asm(volatile int *ptr, int value); -asmlinkage int __raw_atomic_xadd_asm(volatile int *ptr, int value); - -asmlinkage int __raw_atomic_and_asm(volatile int *ptr, int value); -asmlinkage int __raw_atomic_or_asm(volatile int *ptr, int value); -asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value); -asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value); - -#define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter) - -#define atomic_add_return(i, v) __raw_atomic_add_asm(&(v)->counter, i) -#define atomic_sub_return(i, v) __raw_atomic_add_asm(&(v)->counter, -(i)) - -#define atomic_fetch_add(i, v) __raw_atomic_xadd_asm(&(v)->counter, i) -#define atomic_fetch_sub(i, v) __raw_atomic_xadd_asm(&(v)->counter, -(i)) - -#define atomic_or(i, v) (void)__raw_atomic_or_asm(&(v)->counter, i) -#define atomic_and(i, v) (void)__raw_atomic_and_asm(&(v)->counter, i) -#define atomic_xor(i, v) (void)__raw_atomic_xor_asm(&(v)->counter, i) - -#define atomic_fetch_or(i, v) __raw_atomic_or_asm(&(v)->counter, i) -#define atomic_fetch_and(i, v) __raw_atomic_and_asm(&(v)->counter, i) -#define atomic_fetch_xor(i, v) __raw_atomic_xor_asm(&(v)->counter, i) - -#endif - -#include - -#endif diff --git a/arch/blackfin/include/asm/barrier.h b/arch/blackfin/include/asm/barrier.h deleted file mode 100644 index 7cca51cae5ff..000000000000 --- a/arch/blackfin/include/asm/barrier.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * Tony Kou (tonyko@lineo.ca) - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BLACKFIN_BARRIER_H -#define _BLACKFIN_BARRIER_H - -#include - -#define nop() __asm__ __volatile__ ("nop;\n\t" : : ) - -/* - * Force strict CPU ordering. - */ -#ifdef CONFIG_SMP - -#ifdef __ARCH_SYNC_CORE_DCACHE -/* Force Core data cache coherence */ -# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) -# define rmb() do { barrier(); smp_check_barrier(); } while (0) -# define wmb() do { barrier(); smp_mark_barrier(); } while (0) -/* - * read_barrier_depends - Flush all pending reads that subsequents reads - * depend on. - * - * No data-dependent reads from memory-like regions are ever reordered - * over this barrier. All reads preceding this primitive are guaranteed - * to access memory (but not necessarily other CPUs' caches) before any - * reads following this primitive that depend on the data return by - * any of the preceding reads. This primitive is much lighter weight than - * rmb() on most CPUs, and is never heavier weight than is - * rmb(). - * - * These ordering constraints are respected by both the local CPU - * and the compiler. - * - * Ordering is not guaranteed by anything other than these primitives, - * not even by data dependencies. See the documentation for - * memory_barrier() for examples and URLs to more information. - * - * For example, the following code would force ordering (the initial - * value of "a" is zero, "b" is one, and "p" is "&a"): - * - * - * CPU 0 CPU 1 - * - * b = 2; - * memory_barrier(); - * p = &b; q = p; - * read_barrier_depends(); - * d = *q; - * - * - * because the read of "*q" depends on the read of "p" and these - * two reads are separated by a read_barrier_depends(). However, - * the following code, with the same initial values for "a" and "b": - * - * - * CPU 0 CPU 1 - * - * a = 2; - * memory_barrier(); - * b = 3; y = b; - * read_barrier_depends(); - * x = a; - * - * - * does not enforce ordering, since there is no data dependency between - * the read of "a" and the read of "b". Therefore, on some CPUs, such - * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() - * in cases like this where there are no data dependencies. - */ -# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) -#endif - -#endif /* !CONFIG_SMP */ - -#define __smp_mb__before_atomic() barrier() -#define __smp_mb__after_atomic() barrier() - -#include - -#endif /* _BLACKFIN_BARRIER_H */ diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h deleted file mode 100644 index dc47d79287f9..000000000000 --- a/arch/blackfin/include/asm/bfin-global.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Global extern defines for blackfin - * - * Copyright 2006-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_GLOBAL_H_ -#define _BFIN_GLOBAL_H_ - -#ifndef __ASSEMBLY__ - -#include -#include - -#if defined(CONFIG_DMA_UNCACHED_32M) -# define DMA_UNCACHED_REGION (32 * 1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_16M) -# define DMA_UNCACHED_REGION (16 * 1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_8M) -# define DMA_UNCACHED_REGION (8 * 1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_4M) -# define DMA_UNCACHED_REGION (4 * 1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_2M) -# define DMA_UNCACHED_REGION (2 * 1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_1M) -# define DMA_UNCACHED_REGION (1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_512K) -# define DMA_UNCACHED_REGION (512 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_256K) -# define DMA_UNCACHED_REGION (256 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_128K) -# define DMA_UNCACHED_REGION (128 * 1024) -#else -# define DMA_UNCACHED_REGION (0) -#endif - -extern void bfin_setup_caches(unsigned int cpu); -extern void bfin_setup_cpudata(unsigned int cpu); - -extern unsigned long get_cclk(void); -extern unsigned long get_sclk(void); -#ifdef CONFIG_BF60x -extern unsigned long get_sclk0(void); -extern unsigned long get_sclk1(void); -extern unsigned long get_dclk(void); -#endif -extern unsigned long sclk_to_usecs(unsigned long sclk); -extern unsigned long usecs_to_sclk(unsigned long usecs); - -struct pt_regs; -#if defined(CONFIG_DEBUG_VERBOSE) -extern void dump_bfin_process(struct pt_regs *regs); -extern void dump_bfin_mem(struct pt_regs *regs); -extern void dump_bfin_trace_buffer(void); -#else -#define dump_bfin_process(regs) -#define dump_bfin_mem(regs) -#define dump_bfin_trace_buffer() -#endif - -extern void *l1_data_A_sram_alloc(size_t); -extern void *l1_data_B_sram_alloc(size_t); -extern void *l1_inst_sram_alloc(size_t); -extern void *l1_data_sram_alloc(size_t); -extern void *l1_data_sram_zalloc(size_t); -extern void *l2_sram_alloc(size_t); -extern void *l2_sram_zalloc(size_t); -extern int l1_data_A_sram_free(const void*); -extern int l1_data_B_sram_free(const void*); -extern int l1_inst_sram_free(const void*); -extern int l1_data_sram_free(const void*); -extern int l2_sram_free(const void *); -extern int sram_free(const void*); - -#define L1_INST_SRAM 0x00000001 -#define L1_DATA_A_SRAM 0x00000002 -#define L1_DATA_B_SRAM 0x00000004 -#define L1_DATA_SRAM 0x00000006 -#define L2_SRAM 0x00000008 -extern void *sram_alloc_with_lsl(size_t, unsigned long); -extern int sram_free_with_lsl(const void*); - -extern void *isram_memcpy(void *dest, const void *src, size_t n); - -extern const char bfin_board_name[]; - -extern unsigned long bfin_sic_iwr[]; -extern unsigned vr_wakeup; -extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ - -#endif - -#endif /* _BLACKFIN_H_ */ diff --git a/arch/blackfin/include/asm/bfin-lq035q1.h b/arch/blackfin/include/asm/bfin-lq035q1.h deleted file mode 100644 index 836895156b5b..000000000000 --- a/arch/blackfin/include/asm/bfin-lq035q1.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02 - * - * Copyright 2008-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef BFIN_LQ035Q1_H -#define BFIN_LQ035Q1_H - -/* - * LCD Modes - */ -#define LQ035_RL (0 << 8) /* Right -> Left Scan */ -#define LQ035_LR (1 << 8) /* Left -> Right Scan */ -#define LQ035_TB (1 << 9) /* Top -> Botton Scan */ -#define LQ035_BT (0 << 9) /* Botton -> Top Scan */ -#define LQ035_BGR (1 << 11) /* Use BGR format */ -#define LQ035_RGB (0 << 11) /* Use RGB format */ -#define LQ035_NORM (1 << 13) /* Reversal */ -#define LQ035_REV (0 << 13) /* Reversal */ - -/* - * PPI Modes - */ - -#define USE_RGB565_16_BIT_PPI 1 -#define USE_RGB565_8_BIT_PPI 2 -#define USE_RGB888_8_BIT_PPI 3 - -struct bfin_lq035q1fb_disp_info { - - unsigned mode; - unsigned ppi_mode; - /* GPIOs */ - int use_bl; - unsigned gpio_bl; -}; - -#endif /* BFIN_LQ035Q1_H */ diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h deleted file mode 100644 index fb95c853bb1e..000000000000 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Blackfin On-Chip SPI Driver - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _SPI_CHANNEL_H_ -#define _SPI_CHANNEL_H_ - -#define MIN_SPI_BAUD_VAL 2 - -#define BIT_CTL_ENABLE 0x4000 -#define BIT_CTL_OPENDRAIN 0x2000 -#define BIT_CTL_MASTER 0x1000 -#define BIT_CTL_CPOL 0x0800 -#define BIT_CTL_CPHA 0x0400 -#define BIT_CTL_LSBF 0x0200 -#define BIT_CTL_WORDSIZE 0x0100 -#define BIT_CTL_EMISO 0x0020 -#define BIT_CTL_PSSE 0x0010 -#define BIT_CTL_GM 0x0008 -#define BIT_CTL_SZ 0x0004 -#define BIT_CTL_RXMOD 0x0000 -#define BIT_CTL_TXMOD 0x0001 -#define BIT_CTL_TIMOD_DMA_TX 0x0003 -#define BIT_CTL_TIMOD_DMA_RX 0x0002 -#define BIT_CTL_SENDOPT 0x0004 -#define BIT_CTL_TIMOD 0x0003 - -#define BIT_STAT_SPIF 0x0001 -#define BIT_STAT_MODF 0x0002 -#define BIT_STAT_TXE 0x0004 -#define BIT_STAT_TXS 0x0008 -#define BIT_STAT_RBSY 0x0010 -#define BIT_STAT_RXS 0x0020 -#define BIT_STAT_TXCOL 0x0040 -#define BIT_STAT_CLR 0xFFFF - -#define BIT_STU_SENDOVER 0x0001 -#define BIT_STU_RECVFULL 0x0020 - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m - -/* - * bfin spi registers layout - */ -struct bfin_spi_regs { - __BFP(ctl); - __BFP(flg); - __BFP(stat); - __BFP(tdbr); - __BFP(rdbr); - __BFP(baud); - __BFP(shadow); -}; - -#undef __BFP - -#define MAX_CTRL_CS 8 /* cs in spi controller */ - -/* device.platform_data for SSP controller devices */ -struct bfin5xx_spi_master { - u16 num_chipselect; - u8 enable_dma; - u16 pin_req[7]; -}; - -/* spi_board_info.controller_data for SPI slave devices, - * copied to spi_device.platform_data ... mostly for dma tuning - */ -struct bfin5xx_spi_chip { - u16 ctl_reg; - u8 enable_dma; - u16 cs_chg_udelay; /* Some devices require 16-bit delays */ - /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ - u16 idle_tx_val; - u8 pio_interrupt; /* Enable spi data irq */ -}; - -#endif /* _SPI_CHANNEL_H_ */ diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h deleted file mode 100644 index b1492e0bcabb..000000000000 --- a/arch/blackfin/include/asm/bfin_can.h +++ /dev/null @@ -1,728 +0,0 @@ -/* - * bfin_can.h - interface to Blackfin CANs - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_CAN_H__ -#define __ASM_BFIN_CAN_H__ - -/* - * transmit and receive channels - */ -#define TRANSMIT_CHL 24 -#define RECEIVE_STD_CHL 0 -#define RECEIVE_EXT_CHL 4 -#define RECEIVE_RTR_CHL 8 -#define RECEIVE_EXT_RTR_CHL 12 -#define MAX_CHL_NUMBER 32 - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m - -/* - * bfin can registers layout - */ -struct bfin_can_mask_regs { - __BFP(aml); - __BFP(amh); -}; - -struct bfin_can_channel_regs { - /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */ - u16 data[8]; - __BFP(dlc); - __BFP(tsv); - __BFP(id0); - __BFP(id1); -}; - -struct bfin_can_regs { - /* - * global control and status registers - */ - __BFP(mc1); /* offset 0x00 */ - __BFP(md1); /* offset 0x04 */ - __BFP(trs1); /* offset 0x08 */ - __BFP(trr1); /* offset 0x0c */ - __BFP(ta1); /* offset 0x10 */ - __BFP(aa1); /* offset 0x14 */ - __BFP(rmp1); /* offset 0x18 */ - __BFP(rml1); /* offset 0x1c */ - __BFP(mbtif1); /* offset 0x20 */ - __BFP(mbrif1); /* offset 0x24 */ - __BFP(mbim1); /* offset 0x28 */ - __BFP(rfh1); /* offset 0x2c */ - __BFP(opss1); /* offset 0x30 */ - u32 __pad1[3]; - __BFP(mc2); /* offset 0x40 */ - __BFP(md2); /* offset 0x44 */ - __BFP(trs2); /* offset 0x48 */ - __BFP(trr2); /* offset 0x4c */ - __BFP(ta2); /* offset 0x50 */ - __BFP(aa2); /* offset 0x54 */ - __BFP(rmp2); /* offset 0x58 */ - __BFP(rml2); /* offset 0x5c */ - __BFP(mbtif2); /* offset 0x60 */ - __BFP(mbrif2); /* offset 0x64 */ - __BFP(mbim2); /* offset 0x68 */ - __BFP(rfh2); /* offset 0x6c */ - __BFP(opss2); /* offset 0x70 */ - u32 __pad2[3]; - __BFP(clock); /* offset 0x80 */ - __BFP(timing); /* offset 0x84 */ - __BFP(debug); /* offset 0x88 */ - __BFP(status); /* offset 0x8c */ - __BFP(cec); /* offset 0x90 */ - __BFP(gis); /* offset 0x94 */ - __BFP(gim); /* offset 0x98 */ - __BFP(gif); /* offset 0x9c */ - __BFP(control); /* offset 0xa0 */ - __BFP(intr); /* offset 0xa4 */ - __BFP(version); /* offset 0xa8 */ - __BFP(mbtd); /* offset 0xac */ - __BFP(ewr); /* offset 0xb0 */ - __BFP(esr); /* offset 0xb4 */ - u32 __pad3[2]; - __BFP(ucreg); /* offset 0xc0 */ - __BFP(uccnt); /* offset 0xc4 */ - __BFP(ucrc); /* offset 0xc8 */ - __BFP(uccnf); /* offset 0xcc */ - u32 __pad4[1]; - __BFP(version2); /* offset 0xd4 */ - u32 __pad5[10]; - - /* - * channel(mailbox) mask and message registers - */ - struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */ - struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */ -}; - -#undef __BFP - -/* CAN_CONTROL Masks */ -#define SRS 0x0001 /* Software Reset */ -#define DNM 0x0002 /* Device Net Mode */ -#define ABO 0x0004 /* Auto-Bus On Enable */ -#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ -#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ -#define SMR 0x0020 /* Sleep Mode Request */ -#define CSR 0x0040 /* CAN Suspend Mode Request */ -#define CCR 0x0080 /* CAN Configuration Mode Request */ - -/* CAN_STATUS Masks */ -#define WT 0x0001 /* TX Warning Flag */ -#define WR 0x0002 /* RX Warning Flag */ -#define EP 0x0004 /* Error Passive Mode */ -#define EBO 0x0008 /* Error Bus Off Mode */ -#define SMA 0x0020 /* Sleep Mode Acknowledge */ -#define CSA 0x0040 /* Suspend Mode Acknowledge */ -#define CCA 0x0080 /* Configuration Mode Acknowledge */ -#define MBPTR 0x1F00 /* Mailbox Pointer */ -#define TRM 0x4000 /* Transmit Mode */ -#define REC 0x8000 /* Receive Mode */ - -/* CAN_CLOCK Masks */ -#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ - -/* CAN_TIMING Masks */ -#define TSEG1 0x000F /* Time Segment 1 */ -#define TSEG2 0x0070 /* Time Segment 2 */ -#define SAM 0x0080 /* Sampling */ -#define SJW 0x0300 /* Synchronization Jump Width */ - -/* CAN_DEBUG Masks */ -#define DEC 0x0001 /* Disable CAN Error Counters */ -#define DRI 0x0002 /* Disable CAN RX Input */ -#define DTO 0x0004 /* Disable CAN TX Output */ -#define DIL 0x0008 /* Disable CAN Internal Loop */ -#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ -#define MRB 0x0020 /* Mode Read Back Enable */ -#define CDE 0x8000 /* CAN Debug Enable */ - -/* CAN_CEC Masks */ -#define RXECNT 0x00FF /* Receive Error Counter */ -#define TXECNT 0xFF00 /* Transmit Error Counter */ - -/* CAN_INTR Masks */ -#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ -#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ -#define GIRQ 0x0004 /* Global Interrupt */ -#define SMACK 0x0008 /* Sleep Mode Acknowledge */ -#define CANTX 0x0040 /* CAN TX Bus Value */ -#define CANRX 0x0080 /* CAN RX Bus Value */ - -/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ -#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define IDE 0x2000 /* Identifier Extension */ -#define RTR 0x4000 /* Remote Frame Transmission Request */ -#define AME 0x8000 /* Acceptance Mask Enable */ - -/* CAN_MBxx_TIMESTAMP Masks */ -#define TSV 0xFFFF /* Timestamp */ - -/* CAN_MBxx_LENGTH Masks */ -#define DLC 0x000F /* Data Length Code */ - -/* CAN_AMxxH and CAN_AMxxL Masks */ -#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ -#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ -#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ -#define BASEID 0x1FFC /* Base Identifier */ -#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ -#define FMD 0x4000 /* Full Mask Data Field Enable */ -#define FDF 0x8000 /* Filter On Data Field Enable */ - -/* CAN_MC1 Masks */ -#define MC0 0x0001 /* Enable Mailbox 0 */ -#define MC1 0x0002 /* Enable Mailbox 1 */ -#define MC2 0x0004 /* Enable Mailbox 2 */ -#define MC3 0x0008 /* Enable Mailbox 3 */ -#define MC4 0x0010 /* Enable Mailbox 4 */ -#define MC5 0x0020 /* Enable Mailbox 5 */ -#define MC6 0x0040 /* Enable Mailbox 6 */ -#define MC7 0x0080 /* Enable Mailbox 7 */ -#define MC8 0x0100 /* Enable Mailbox 8 */ -#define MC9 0x0200 /* Enable Mailbox 9 */ -#define MC10 0x0400 /* Enable Mailbox 10 */ -#define MC11 0x0800 /* Enable Mailbox 11 */ -#define MC12 0x1000 /* Enable Mailbox 12 */ -#define MC13 0x2000 /* Enable Mailbox 13 */ -#define MC14 0x4000 /* Enable Mailbox 14 */ -#define MC15 0x8000 /* Enable Mailbox 15 */ - -/* CAN_MC2 Masks */ -#define MC16 0x0001 /* Enable Mailbox 16 */ -#define MC17 0x0002 /* Enable Mailbox 17 */ -#define MC18 0x0004 /* Enable Mailbox 18 */ -#define MC19 0x0008 /* Enable Mailbox 19 */ -#define MC20 0x0010 /* Enable Mailbox 20 */ -#define MC21 0x0020 /* Enable Mailbox 21 */ -#define MC22 0x0040 /* Enable Mailbox 22 */ -#define MC23 0x0080 /* Enable Mailbox 23 */ -#define MC24 0x0100 /* Enable Mailbox 24 */ -#define MC25 0x0200 /* Enable Mailbox 25 */ -#define MC26 0x0400 /* Enable Mailbox 26 */ -#define MC27 0x0800 /* Enable Mailbox 27 */ -#define MC28 0x1000 /* Enable Mailbox 28 */ -#define MC29 0x2000 /* Enable Mailbox 29 */ -#define MC30 0x4000 /* Enable Mailbox 30 */ -#define MC31 0x8000 /* Enable Mailbox 31 */ - -/* CAN_MD1 Masks */ -#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ -#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ -#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ -#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ -#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ -#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ -#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ -#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ -#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ -#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ -#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ -#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ -#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ -#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ -#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ -#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ - -/* CAN_MD2 Masks */ -#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ -#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ -#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ -#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ -#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ -#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ -#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ -#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ -#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ -#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ -#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ -#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ -#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ -#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ -#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ -#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ - -/* CAN_RMP1 Masks */ -#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ -#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ -#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ -#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ -#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ -#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ -#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ -#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ -#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ -#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ -#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ -#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ -#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ -#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ -#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ -#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ - -/* CAN_RMP2 Masks */ -#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ -#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ -#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ -#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ -#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ -#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ -#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ -#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ -#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ -#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ -#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ -#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ -#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ -#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ -#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ -#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ - -/* CAN_RML1 Masks */ -#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ -#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ -#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ -#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ -#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ -#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ -#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ -#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ -#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ -#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ -#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ -#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ -#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ -#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ -#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ -#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ - -/* CAN_RML2 Masks */ -#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ -#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ -#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ -#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ -#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ -#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ -#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ -#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ -#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ -#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ -#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ -#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ -#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ -#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ -#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ -#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ - -/* CAN_OPSS1 Masks */ -#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ -#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ -#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ -#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ -#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ -#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ -#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ -#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ -#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ -#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ -#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ -#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ -#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ -#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ -#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ -#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ - -/* CAN_OPSS2 Masks */ -#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ -#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ -#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ -#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ -#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ -#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ -#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ -#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ -#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ -#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ -#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ -#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ -#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ -#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ -#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ -#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ - -/* CAN_TRR1 Masks */ -#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ -#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ -#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ -#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ -#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ -#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ -#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ -#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ -#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ -#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ -#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ -#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ -#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ -#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ -#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ -#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ - -/* CAN_TRR2 Masks */ -#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ -#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ -#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ -#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ -#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ -#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ -#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ -#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ -#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ -#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ -#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ -#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ -#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ -#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ -#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ -#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ - -/* CAN_TRS1 Masks */ -#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ -#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ -#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ -#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ -#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ -#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ -#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ -#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ -#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ -#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ -#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ -#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ -#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ -#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ -#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ -#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ - -/* CAN_TRS2 Masks */ -#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ -#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ -#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ -#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ -#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ -#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ -#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ -#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ -#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ -#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ -#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ -#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ -#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ -#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ -#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ -#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ - -/* CAN_AA1 Masks */ -#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ -#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ -#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ -#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ -#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ -#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ -#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ -#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ -#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ -#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ -#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ -#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ -#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ -#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ -#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ -#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ - -/* CAN_AA2 Masks */ -#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ -#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ -#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ -#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ -#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ -#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ -#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ -#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ -#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ -#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ -#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ -#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ -#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ -#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ -#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ -#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ - -/* CAN_TA1 Masks */ -#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ -#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ -#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ -#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ -#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ -#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ -#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ -#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ -#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ -#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ -#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ -#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ -#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ -#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ -#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ -#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ - -/* CAN_TA2 Masks */ -#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ -#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ -#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ -#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ -#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ -#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ -#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ -#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ -#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ -#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ -#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ -#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ -#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ -#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ -#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ -#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ - -/* CAN_MBTD Masks */ -#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ -#define TDA 0x0040 /* Temporary Disable Acknowledge */ -#define TDR 0x0080 /* Temporary Disable Request */ - -/* CAN_RFH1 Masks */ -#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ -#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ -#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ -#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ -#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ -#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ -#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ -#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ -#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ -#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ -#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ -#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ -#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ -#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ -#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ -#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ - -/* CAN_RFH2 Masks */ -#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ -#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ -#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ -#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ -#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ -#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ -#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ -#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ -#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ -#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ -#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ -#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ -#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ -#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ -#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ -#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ - -/* CAN_MBTIF1 Masks */ -#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ -#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ -#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ -#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ -#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ -#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ -#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ -#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ -#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ -#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ -#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ -#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ -#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ -#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ -#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ -#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ - -/* CAN_MBTIF2 Masks */ -#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ -#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ -#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ -#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ -#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ -#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ -#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ -#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ -#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ -#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ -#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ -#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ -#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ -#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ -#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ -#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ - -/* CAN_MBRIF1 Masks */ -#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ -#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ -#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ -#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ -#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ -#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ -#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ -#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ -#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ -#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ -#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ -#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ -#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ -#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ -#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ -#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ - -/* CAN_MBRIF2 Masks */ -#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ -#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ -#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ -#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ -#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ -#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ -#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ -#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ -#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ -#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ -#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ -#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ -#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ -#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ -#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ -#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ - -/* CAN_MBIM1 Masks */ -#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ -#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ -#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ -#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ -#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ -#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ -#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ -#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ -#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ -#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ -#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ -#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ -#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ -#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ -#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ -#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ - -/* CAN_MBIM2 Masks */ -#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ -#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ -#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ -#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ -#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ -#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ -#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ -#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ -#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ -#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ -#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ -#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ -#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ -#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ -#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ -#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ - -/* CAN_GIM Masks */ -#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ -#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ -#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ -#define BOIM 0x0008 /* Enable Bus Off Interrupt */ -#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ -#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ -#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ -#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ -#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ -#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ -#define ADIM 0x0400 /* Enable Access Denied Interrupt */ - -/* CAN_GIS Masks */ -#define EWTIS 0x0001 /* TX Error Count IRQ Status */ -#define EWRIS 0x0002 /* RX Error Count IRQ Status */ -#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ -#define BOIS 0x0008 /* Bus Off IRQ Status */ -#define WUIS 0x0010 /* Wake-Up IRQ Status */ -#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ -#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ -#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ -#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ -#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ -#define ADIS 0x0400 /* Access Denied IRQ Status */ - -/* CAN_GIF Masks */ -#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ -#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ -#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ -#define BOIF 0x0008 /* Bus Off IRQ Flag */ -#define WUIF 0x0010 /* Wake-Up IRQ Flag */ -#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ -#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ -#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ -#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ -#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ -#define ADIF 0x0400 /* Access Denied IRQ Flag */ - -/* CAN_UCCNF Masks */ -#define UCCNF 0x000F /* Universal Counter Mode */ -#define UC_STAMP 0x0001 /* Timestamp Mode */ -#define UC_WDOG 0x0002 /* Watchdog Mode */ -#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ -#define UC_ERROR 0x0006 /* CAN Error Frame Count */ -#define UC_OVER 0x0007 /* CAN Overload Frame Count */ -#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ -#define UC_AA 0x0009 /* TX Abort Count */ -#define UC_TA 0x000A /* TX Successful Count */ -#define UC_REJECT 0x000B /* RX Message Rejected Count */ -#define UC_RML 0x000C /* RX Message Lost Count */ -#define UC_RX 0x000D /* Total Successful RX Messages Count */ -#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ -#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ -#define UCRC 0x0020 /* Universal Counter Reload/Clear */ -#define UCCT 0x0040 /* Universal Counter CAN Trigger */ -#define UCE 0x0080 /* Universal Counter Enable */ - -/* CAN_ESR Masks */ -#define ACKE 0x0004 /* Acknowledge Error */ -#define SER 0x0008 /* Stuff Error */ -#define CRCE 0x0010 /* CRC Error */ -#define SA0 0x0020 /* Stuck At Dominant Error */ -#define BEF 0x0040 /* Bit Error Flag */ -#define FER 0x0080 /* Form Error Flag */ - -/* CAN_EWR Masks */ -#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ -#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ - -#endif diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h deleted file mode 100644 index 6319f4e49083..000000000000 --- a/arch/blackfin/include/asm/bfin_dma.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * bfin_dma.h - Blackfin DMA defines/structures/etc... - * - * Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_DMA_H__ -#define __ASM_BFIN_DMA_H__ - -#include - -/* DMA_CONFIG Masks */ -#define DMAEN 0x0001 /* DMA Channel Enable */ -#define WNR 0x0002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ -#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ - -#ifdef CONFIG_BF60x - -#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */ -#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */ -#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */ -#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */ -#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */ -#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */ -#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */ -#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */ -#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */ -#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */ -#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */ -#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */ -#define DI_EN DI_EN_X /* Data Interrupt Enable */ -#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */ -#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */ -#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */ -#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */ -#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */ -#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */ -#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */ -#define NDSIZE 0x00070000 /* Next Descriptor Size */ -#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */ -#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */ -#define DMAFLOW_LARGE DMAFLOW_LIST -#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */ -#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */ -#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */ -#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */ -#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */ -#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */ -#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */ - -#else - -#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */ -#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */ -#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ -#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ -#define RESTART 0x0020 /* DMA Buffer Clear */ -#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ -#define DI_EN 0x0080 /* Data Interrupt Enable */ -#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/ -#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define NDSIZE 0x0f00 /* Next Descriptor Size */ -#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ - -#endif -#define DMAFLOW 0x7000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ - -/* DMA_IRQ_STATUS Masks */ -#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#ifdef CONFIG_BF60x -#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */ -#else -#define DMA_PIRQ 0 -#endif - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m - -/* - * bfin dma registers layout - */ -struct bfin_dma_regs { - u32 next_desc_ptr; - u32 start_addr; -#ifdef CONFIG_BF60x - u32 cfg; - u32 x_count; - u32 x_modify; - u32 y_count; - u32 y_modify; - u32 pad1; - u32 pad2; - u32 curr_desc_ptr; - u32 prev_desc_ptr; - u32 curr_addr; - u32 irq_status; - u32 curr_x_count; - u32 curr_y_count; - u32 pad3; - u32 bw_limit_count; - u32 curr_bw_limit_count; - u32 bw_monitor_count; - u32 curr_bw_monitor_count; -#else - __BFP(config); - u32 __pad0; - __BFP(x_count); - __BFP(x_modify); - __BFP(y_count); - __BFP(y_modify); - u32 curr_desc_ptr; - u32 curr_addr; - __BFP(irq_status); - __BFP(peripheral_map); - __BFP(curr_x_count); - u32 __pad1; - __BFP(curr_y_count); - u32 __pad2; -#endif -}; - -#ifndef CONFIG_BF60x -/* - * bfin handshake mdma registers layout - */ -struct bfin_hmdma_regs { - __BFP(control); - __BFP(ecinit); - __BFP(bcinit); - __BFP(ecurgent); - __BFP(ecoverflow); - __BFP(ecount); - __BFP(bcount); -}; -#endif - -#undef __BFP - -#endif diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h deleted file mode 100644 index bf52e1f32257..000000000000 --- a/arch/blackfin/include/asm/bfin_pfmon.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Blackfin Performance Monitor definitions - * - * Copyright 2005-2011 Analog Devices Inc. - * - * Licensed under the Clear BSD license or GPL-2 (or later). - */ - -#ifndef __ASM_BFIN_PFMON_H__ -#define __ASM_BFIN_PFMON_H__ - -/* PFCTL Masks */ -#define PFMON_MASK 0xff -#define PFCEN_MASK 0x3 -#define PFCEN_DISABLE 0x0 -#define PFCEN_ENABLE_USER 0x1 -#define PFCEN_ENABLE_SUPV 0x2 -#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV) - -#define PFPWR_P 0 -#define PEMUSW0_P 2 -#define PFCEN0_P 3 -#define PFMON0_P 5 -#define PEMUSW1_P 13 -#define PFCEN1_P 14 -#define PFMON1_P 16 -#define PFCNT0_P 24 -#define PFCNT1_P 25 - -#define PFPWR (1 << PFPWR_P) -#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P)) -#define PEMUSW0 PEMUSW(0, 1) -#define PEMUSW1 PEMUSW(1, 1) -#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P)) -#define PFCEN0 PFCEN(0, PFCEN_MASK) -#define PFCEN1 PFCEN(1, PFCEN_MASK) -#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P)) -#define PFCNT0 PFCNT(0, 1) -#define PFCNT1 PFCNT(1, 1) -#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P)) -#define PFMON0 PFMON(0, PFMON_MASK) -#define PFMON1 PFMON(1, PFMON_MASK) - -#endif diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h deleted file mode 100644 index a4e872e16e75..000000000000 --- a/arch/blackfin/include/asm/bfin_ppi.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * bfin_ppi.h - interface to Blackfin PPIs - * - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_PPI_H__ -#define __ASM_BFIN_PPI_H__ - -#include -#include - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m - -/* - * bfin ppi registers layout - */ -struct bfin_ppi_regs { - __BFP(control); - __BFP(status); - __BFP(count); - __BFP(delay); - __BFP(frame); -}; - -/* - * bfin eppi registers layout - */ -struct bfin_eppi_regs { - __BFP(status); - __BFP(hcount); - __BFP(hdelay); - __BFP(vcount); - __BFP(vdelay); - __BFP(frame); - __BFP(line); - __BFP(clkdiv); - u32 control; - u32 fs1w_hbl; - u32 fs1p_avpl; - u32 fs2w_lvb; - u32 fs2p_lavf; - u32 clip; -}; - -/* - * bfin eppi3 registers layout - */ -struct bfin_eppi3_regs { - u32 stat; - u32 hcnt; - u32 hdly; - u32 vcnt; - u32 vdly; - u32 frame; - u32 line; - u32 clkdiv; - u32 ctl; - u32 fs1_wlhb; - u32 fs1_paspl; - u32 fs2_wlvb; - u32 fs2_palpf; - u32 imsk; - u32 oddclip; - u32 evenclip; - u32 fs1_dly; - u32 fs2_dly; - u32 ctl2; -}; - -#undef __BFP - -#ifdef EPPI0_CTL2 -#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */ -#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */ -#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */ -#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */ -#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */ -#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */ -#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */ -#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */ -#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */ -#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */ - -#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */ - -#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */ - -#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */ - -#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */ - -#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */ - -#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */ - -#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */ - -#define EPPI_CTL_EN 0x00000001 /* PPI Enable */ -#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */ -#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */ -#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */ -#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */ -#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */ -#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */ -#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */ -#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */ -#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */ -#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */ -#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */ -#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */ -#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */ -#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */ -#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */ -#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */ -#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */ -#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */ -#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */ -#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */ -#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */ -#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */ -#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */ -#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */ -#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */ -#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */ -#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */ -#define EPPI_CTL_DLEN 0x00070000 /* Data Length */ -#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */ -#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */ -#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */ -#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */ -#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */ -#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */ -#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */ -#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */ -#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */ -#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */ -#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */ -#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */ -#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */ -#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */ -#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */ -#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */ -#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */ -#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */ -#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */ -#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */ -#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */ - -#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */ -#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */ -#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */ -#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */ - -#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */ -#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */ - -#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */ -#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */ -#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */ -#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */ -#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */ -#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */ -#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */ -#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */ - -#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000 -#define EPPI_ODDCLIP_LOWODD 0x0000FFFF - -#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000 -#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF - -#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */ -#endif -#endif diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h deleted file mode 100644 index a99957ea9e9b..000000000000 --- a/arch/blackfin/include/asm/bfin_sdh.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Blackfin Secure Digital Host (SDH) definitions - * - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_SDH_H__ -#define __BFIN_SDH_H__ - -/* Platform resources */ -struct bfin_sd_host { - int dma_chan; - int irq_int0; - int irq_int1; - u16 pin_req[7]; -}; - -/* SDH_COMMAND bitmasks */ -#define CMD_IDX 0x3f /* Command Index */ -#define CMD_RSP (1 << 6) /* Response */ -#define CMD_L_RSP (1 << 7) /* Long Response */ -#define CMD_INT_E (1 << 8) /* Command Interrupt */ -#define CMD_PEND_E (1 << 9) /* Command Pending */ -#define CMD_E (1 << 10) /* Command Enable */ -#ifdef RSI_BLKSZ -#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */ -#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */ -#endif - -/* SDH_PWR_CTL bitmasks */ -#ifndef RSI_BLKSZ -#define PWR_ON 0x3 /* Power On */ -#define SD_CMD_OD (1 << 6) /* Open Drain Output */ -#define ROD_CTL (1 << 7) /* Rod Control */ -#endif - -/* SDH_CLK_CTL bitmasks */ -#define CLKDIV 0xff /* MC_CLK Divisor */ -#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ -#define PWR_SV_E (1 << 9) /* Power Save Enable */ -#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ -#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */ -#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */ -#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */ -#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */ - -/* SDH_RESP_CMD bitmasks */ -#define RESP_CMD 0x3f /* Response Command */ - -/* SDH_DATA_CTL bitmasks */ -#define DTX_E (1 << 0) /* Data Transfer Enable */ -#define DTX_DIR (1 << 1) /* Data Transfer Direction */ -#define DTX_MODE (1 << 2) /* Data Transfer Mode */ -#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */ -#ifndef RSI_BLKSZ -#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ -#else - -/* Bit masks for SDH_BLK_SIZE */ -#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */ -#endif - -/* SDH_STATUS bitmasks */ -#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */ -#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */ -#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */ -#define DAT_TIME_OUT (1 << 3) /* Data Time Out */ -#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */ -#define RX_OVERRUN (1 << 5) /* Receive Overrun */ -#define CMD_RESP_END (1 << 6) /* CMD Response End */ -#define CMD_SENT (1 << 7) /* CMD Sent */ -#define DAT_END (1 << 8) /* Data End */ -#define START_BIT_ERR (1 << 9) /* Start Bit Error */ -#define DAT_BLK_END (1 << 10) /* Data Block End */ -#define CMD_ACT (1 << 11) /* CMD Active */ -#define TX_ACT (1 << 12) /* Transmit Active */ -#define RX_ACT (1 << 13) /* Receive Active */ -#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */ -#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */ -#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */ -#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */ -#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */ -#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */ -#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */ -#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */ - -/* SDH_STATUS_CLR bitmasks */ -#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */ -#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */ -#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */ -#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */ -#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */ -#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */ -#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */ -#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */ -#define DAT_END_STAT (1 << 8) /* Data End Status */ -#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */ -#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */ - -/* SDH_MASK0 bitmasks */ -#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */ -#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */ -#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */ -#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */ -#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */ -#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */ -#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */ -#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */ -#define DAT_END_MASK (1 << 8) /* Data End Mask */ -#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */ -#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */ -#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */ -#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */ -#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */ -#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */ -#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */ -#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */ -#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */ -#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */ -#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */ -#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */ -#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */ - -/* SDH_FIFO_CNT bitmasks */ -#define FIFO_COUNT 0x7fff /* FIFO Count */ - -/* SDH_E_STATUS bitmasks */ -#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ -#define SD_CARD_DET (1 << 4) /* SD Card Detect */ -#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */ -#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */ -#define SD_CARD_READY (1 << 17) /* Card Ready */ - -/* SDH_E_MASK bitmasks */ -#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ -#define SCD_MSK (1 << 4) /* Mask Card Detect */ -#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */ - -/* SDH_CFG bitmasks */ -#define CLKS_EN (1 << 0) /* Clocks Enable */ -#define SD4E (1 << 2) /* SDIO 4-Bit Enable */ -#define MWE (1 << 3) /* Moving Window Enable */ -#define SD_RST (1 << 4) /* SDMMC Reset */ -#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ -#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ -#ifndef RSI_BLKSZ -#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ -#else -#define PWR_ON 0x600 /* Power On */ -#define SD_CMD_OD (1 << 11) /* Open Drain Output */ -#define BOOT_EN (1 << 12) /* Boot Enable */ -#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */ -#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */ -#endif - -/* SDH_RD_WAIT_EN bitmasks */ -#define RWR (1 << 0) /* Read Wait Request */ - -#endif diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h deleted file mode 100644 index b550ada7321b..000000000000 --- a/arch/blackfin/include/asm/bfin_serial.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_ASM_SERIAL_H__ -#define __BFIN_ASM_SERIAL_H__ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_BFIN_UART0_CTSRTS) || \ - defined(CONFIG_BFIN_UART1_CTSRTS) || \ - defined(CONFIG_BFIN_UART2_CTSRTS) || \ - defined(CONFIG_BFIN_UART3_CTSRTS) -# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE) -# define SERIAL_BFIN_HARD_CTSRTS -# else -# define SERIAL_BFIN_CTSRTS -# endif -#endif - -struct bfin_serial_port { - struct uart_port port; - unsigned int old_status; - int tx_irq; - int rx_irq; - int status_irq; -#ifndef BFIN_UART_BF54X_STYLE - unsigned int lsr; -#endif -#ifdef CONFIG_SERIAL_BFIN_DMA - int tx_done; - int tx_count; - struct circ_buf rx_dma_buf; - struct timer_list rx_dma_timer; - int rx_dma_nrows; - spinlock_t rx_lock; - unsigned int tx_dma_channel; - unsigned int rx_dma_channel; - struct work_struct tx_dma_workqueue; -#elif ANOMALY_05000363 - unsigned int anomaly_threshold; -#endif -#if defined(SERIAL_BFIN_CTSRTS) || \ - defined(SERIAL_BFIN_HARD_CTSRTS) - int cts_pin; - int rts_pin; -#endif -}; - -#ifdef BFIN_UART_BF60X_STYLE - -/* UART_CTL Masks */ -#define UCEN 0x1 /* Enable UARTx Clocks */ -#define LOOP_ENA 0x2 /* Loopback Mode Enable */ -#define UMOD_MDB 0x10 /* Enable MDB Mode */ -#define UMOD_IRDA 0x20 /* Enable IrDA Mode */ -#define UMOD_MASK 0x30 /* Uart Mode Mask */ -#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */ -#define WLS_MASK 0x300 /* Word length Select Mask */ -#define WLS_OFFSET 8 /* Word length Select Offset */ -#define STB 0x1000 /* Stop Bits */ -#define STBH 0x2000 /* Half Stop Bits */ -#define PEN 0x4000 /* Parity Enable */ -#define EPS 0x8000 /* Even Parity Select */ -#define STP 0x10000 /* Stick Parity */ -#define FPE 0x20000 /* Force Parity Error On Transmit */ -#define FFE 0x40000 /* Force Framing Error On Transmit */ -#define SB 0x80000 /* Set Break */ -#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) -#define FCPOL 0x400000 /* Flow Control Pin Polarity */ -#define RPOLC 0x800000 /* IrDA RX Polarity Change */ -#define TPOLC 0x1000000 /* IrDA TX Polarity Change */ -#define MRTS 0x2000000 /* Manual Request To Send */ -#define XOFF 0x4000000 /* Transmitter Off */ -#define ARTS 0x8000000 /* Automatic Request To Send */ -#define ACTS 0x10000000 /* Automatic Clear To Send */ -#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */ -#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */ - -/* UART_STAT Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x80 /* TSR and UART_THR Empty */ -#define TFI 0x100 /* Transmission Finished Indicator */ - -#define ASTKY 0x200 /* Address Sticky */ -#define ADDR 0x400 /* Address bit status */ -#define RO 0x800 /* Reception Ongoing */ -#define SCTS 0x1000 /* Sticky CTS */ -#define CTS 0x10000 /* Clear To Send */ -#define RFCS 0x20000 /* Receive FIFO Count Status */ - -/* UART_CLOCK Masks */ -#define EDBO 0x80000000 /* Enable Devide by One */ - -#else /* BFIN_UART_BF60X_STYLE */ - -/* UART_LCR Masks */ -#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ -#define WLS_MASK 0x03 /* Word length Select Mask */ -#define WLS_OFFSET 0 /* Word length Select Offset */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ -#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) - -/* UART_LSR Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ -#define TFI 0x80 /* Transmission Finished Indicator */ - -/* UART_MCR Masks */ -#define XOFF 0x01 /* Transmitter Off */ -#define MRTS 0x02 /* Manual Request To Send */ -#define RFIT 0x04 /* Receive FIFO IRQ Threshold */ -#define RFRT 0x08 /* Receive FIFO RTS Threshold */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define FCPOL 0x20 /* Flow Control Pin Polarity */ -#define ARTS 0x40 /* Automatic Request To Send */ -#define ACTS 0x80 /* Automatic Clear To Send */ - -/* UART_MSR Masks */ -#define SCTS 0x01 /* Sticky CTS */ -#define CTS 0x10 /* Clear To Send */ -#define RFCS 0x20 /* Receive FIFO Count Status */ - -/* UART_GCTL Masks */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define UMOD_IRDA 0x02 /* Enable IrDA Mode */ -#define UMOD_MASK 0x02 /* Uart Mode Mask */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - -#endif /* BFIN_UART_BF60X_STYLE */ - -/* UART_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ -#define EDSSI 0x08 /* Enable Modem Status Interrupt */ -#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ -#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ - -#if defined(BFIN_UART_BF60X_STYLE) -# define OFFSET_REDIV 0x00 /* Version ID Register */ -# define OFFSET_CTL 0x04 /* Control Register */ -# define OFFSET_STAT 0x08 /* Status Register */ -# define OFFSET_SCR 0x0C /* SCR Scratch Register */ -# define OFFSET_CLK 0x10 /* Clock Rate Register */ -# define OFFSET_IER 0x14 /* Interrupt Enable Register */ -# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */ -# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */ -# define OFFSET_RBR 0x20 /* Receive Buffer register */ -# define OFFSET_THR 0x24 /* Transmit Holding register */ -#elif defined(BFIN_UART_BF54X_STYLE) -# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -# define OFFSET_GCTL 0x08 /* Global Control Register */ -# define OFFSET_LCR 0x0C /* Line Control Register */ -# define OFFSET_MCR 0x10 /* Modem Control Register */ -# define OFFSET_LSR 0x14 /* Line Status Register */ -# define OFFSET_MSR 0x18 /* Modem Status Register */ -# define OFFSET_SCR 0x1C /* SCR Scratch Register */ -# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ -# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ -# define OFFSET_THR 0x28 /* Transmit Holding register */ -# define OFFSET_RBR 0x2C /* Receive Buffer register */ -#else /* BF533 style */ -# define OFFSET_THR 0x00 /* Transmit Holding register */ -# define OFFSET_RBR 0x00 /* Receive Buffer register */ -# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ -# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ -# define OFFSET_IER 0x04 /* Interrupt Enable Register */ -# define OFFSET_IIR 0x08 /* Interrupt Identification Register */ -# define OFFSET_LCR 0x0C /* Line Control Register */ -# define OFFSET_MCR 0x10 /* Modem Control Register */ -# define OFFSET_LSR 0x14 /* Line Status Register */ -# define OFFSET_MSR 0x18 /* Modem Status Register */ -# define OFFSET_SCR 0x1C /* SCR Scratch Register */ -# define OFFSET_GCTL 0x24 /* Global Control Register */ -/* code should not need IIR, so force build error if they use it */ -# undef OFFSET_IIR -#endif - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m -struct bfin_uart_regs { -#if defined(BFIN_UART_BF60X_STYLE) - u32 revid; - u32 ctl; - u32 stat; - u32 scr; - u32 clk; - u32 ier; - u32 ier_set; - u32 ier_clear; - u32 rbr; - u32 thr; - u32 taip; - u32 tsr; - u32 rsr; - u32 txdiv; - u32 rxdiv; -#elif defined(BFIN_UART_BF54X_STYLE) - __BFP(dll); - __BFP(dlh); - __BFP(gctl); - __BFP(lcr); - __BFP(mcr); - __BFP(lsr); - __BFP(msr); - __BFP(scr); - __BFP(ier_set); - __BFP(ier_clear); - __BFP(thr); - __BFP(rbr); -#else - union { - u16 dll; - u16 thr; - const u16 rbr; - }; - const u16 __pad0; - union { - u16 dlh; - u16 ier; - }; - const u16 __pad1; - const __BFP(iir); - __BFP(lcr); - __BFP(mcr); - __BFP(lsr); - __BFP(msr); - __BFP(scr); - const u32 __pad2; - __BFP(gctl); -#endif -}; -#undef __BFP - -#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase) - -/* -#ifndef port_membase -# define port_membase(p) 0 -#endif -*/ -#ifdef BFIN_UART_BF60X_STYLE - -#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR) -#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK) -#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL) -#define UART_GET_GCTL(p) UART_GET_CTL(p) -#define UART_GET_LCR(p) UART_GET_CTL(p) -#define UART_GET_MCR(p) UART_GET_CTL(p) -#if ANOMALY_16000030 -#define UART_GET_STAT(p) \ -({ \ - u32 __ret; \ - unsigned long flags; \ - flags = hard_local_irq_save(); \ - __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \ - hard_local_irq_restore(flags); \ - __ret; \ -}) -#else -#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT) -#endif -#define UART_GET_MSR(p) UART_GET_STAT(p) - -#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v) -#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v) -#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v) -#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v) -#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v) -#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v) -#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v) - -#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v) -#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER) -#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v) - -#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */ -#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */ - -#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1) -#define UART_GET_LSR(p) UART_GET_STAT(p) -#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v) - -/* This handles hard CTS/RTS */ -#define BFIN_UART_CTSRTS_HARD -#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS) -#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) -#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) -#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) -#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) -#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) - -#else /* BFIN_UART_BF60X_STYLE */ - -#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) -#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) -#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) -#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p)) -#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) -#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) -#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) -#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR) - -#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) -#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) -#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) -#define UART_PUT_CLK(p, v) do \ -{\ -UART_PUT_DLL(p, v & 0xFF); \ -UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0); - -#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) -#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) -#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) - -#ifdef BFIN_UART_BF54X_STYLE - -#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v) -#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET) -#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v) - -#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */ -#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */ - -#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1) -#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR) -#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v) - -/* This handles hard CTS/RTS */ -#define BFIN_UART_CTSRTS_HARD -#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS) -#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) -#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) -#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) -#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) -#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) - -#else /* BF533 style */ - -#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v)) -#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER) -#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v) -#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v)) - -#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) -#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) - -#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr) -#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v)) - -/* -#ifndef put_lsr_cache -# define put_lsr_cache(p, v) -#endif -#ifndef get_lsr_cache -# define get_lsr_cache(p) 0 -#endif -*/ - -/* The hardware clears the LSR bits upon read, so we need to cache - * some of the more fun bits in software so they don't get lost - * when checking the LSR in other code paths (TX). - */ -static inline void UART_CLEAR_LSR(void *p) -{ - put_lsr_cache(p, 0); - bfin_write16(port_membase(p) + OFFSET_LSR, -1); -} -static inline unsigned int UART_GET_LSR(void *p) -{ - unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR); - put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE))); - return lsr | get_lsr_cache(p); -} -static inline void UART_PUT_LSR(void *p, uint16_t val) -{ - put_lsr_cache(p, get_lsr_cache(p) & ~val); -} - -/* This handles soft CTS/RTS */ -#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin) -#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1) -#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0) -#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) - -#endif /* BFIN_UART_BF54X_STYLE */ - -#endif /* BFIN_UART_BF60X_STYLE */ - -#ifndef BFIN_UART_TX_FIFO_SIZE -# define BFIN_UART_TX_FIFO_SIZE 2 -#endif - -#endif /* __BFIN_ASM_SERIAL_H__ */ diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h deleted file mode 100644 index b2d5e733079e..000000000000 --- a/arch/blackfin/include/asm/bfin_simple_timer.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2006-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _bfin_simple_timer_h_ -#define _bfin_simple_timer_h_ - -#include - -#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't' - -#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2) -#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 3) -#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 4) -#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) -#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) -#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) -#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11) - -#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0 -#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1 -#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2 -#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3 - -#endif diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h deleted file mode 100644 index 50b9dfd4839f..000000000000 --- a/arch/blackfin/include/asm/bfin_sport.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * bfin_sport.h - interface to Blackfin SPORTs - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ -#ifndef __BFIN_SPORT_H__ -#define __BFIN_SPORT_H__ - - -#include -#include - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m -struct sport_register { - __BFP(tcr1); - __BFP(tcr2); - __BFP(tclkdiv); - __BFP(tfsdiv); - union { - u32 tx32; - u16 tx16; - }; - u32 __pad_tx; - union { - u32 rx32; /* use the anomaly wrapper below */ - u16 rx16; - }; - u32 __pad_rx; - __BFP(rcr1); - __BFP(rcr2); - __BFP(rclkdiv); - __BFP(rfsdiv); - __BFP(stat); - __BFP(chnl); - __BFP(mcmc1); - __BFP(mcmc2); - u32 mtcs0; - u32 mtcs1; - u32 mtcs2; - u32 mtcs3; - u32 mrcs0; - u32 mrcs1; - u32 mrcs2; - u32 mrcs3; -}; -#undef __BFP - -struct bfin_snd_platform_data { - const unsigned short *pin_req; -}; - -#define bfin_read_sport_rx32(base) \ -({ \ - struct sport_register *__mmrs = (void *)base; \ - u32 __ret; \ - unsigned long flags; \ - if (ANOMALY_05000473) \ - local_irq_save(flags); \ - __ret = __mmrs->rx32; \ - if (ANOMALY_05000473) \ - local_irq_restore(flags); \ - __ret; \ -}) - -#endif diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h deleted file mode 100644 index d82f5fa0ad9f..000000000000 --- a/arch/blackfin/include/asm/bfin_sport3.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * bfin_sport - Analog Devices BF6XX SPORT registers - * - * Copyright (c) 2012 Analog Devices Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _BFIN_SPORT3_H_ -#define _BFIN_SPORT3_H_ - -#include - -#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */ -#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */ -#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */ -#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */ -#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */ -#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */ -#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */ -#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */ -#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */ -#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */ -#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */ -#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */ -#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */ -#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */ -#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */ -#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */ -#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */ -#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */ -#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */ -#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */ -#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */ -#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */ -#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */ -#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */ -#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */ -#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */ -#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */ -#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */ -#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */ -#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */ -#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */ -#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */ -#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */ - -#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */ -#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */ - -#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */ -#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */ -#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */ -#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */ -#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */ - -#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */ -#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */ - -#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */ -#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */ -#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */ -#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */ -#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */ -#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */ - -#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */ - -#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */ -#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */ -#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */ - -struct sport_register { - u32 spctl; - u32 div; - u32 spmctl; - u32 spcs0; - u32 spcs1; - u32 spcs2; - u32 spcs3; - u32 spcnt; - u32 sperrctl; - u32 spmstat; - u32 spctl2; - u32 txa; - u32 rxa; - u32 txb; - u32 rxb; - u32 revid; -}; - -struct bfin_snd_platform_data { - const unsigned short *pin_req; -}; - -#endif diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h deleted file mode 100644 index 211e9c78f6fb..000000000000 --- a/arch/blackfin/include/asm/bfin_twi.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * bfin_twi.h - interface to Blackfin TWIs - * - * Copyright 2005-2014 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_TWI_H__ -#define __ASM_BFIN_TWI_H__ - -#include -#include -#include - -/* - * ADI twi registers layout - */ -struct bfin_twi_regs { - u16 clkdiv; - u16 dummy1; - u16 control; - u16 dummy2; - u16 slave_ctl; - u16 dummy3; - u16 slave_stat; - u16 dummy4; - u16 slave_addr; - u16 dummy5; - u16 master_ctl; - u16 dummy6; - u16 master_stat; - u16 dummy7; - u16 master_addr; - u16 dummy8; - u16 int_stat; - u16 dummy9; - u16 int_mask; - u16 dummy10; - u16 fifo_ctl; - u16 dummy11; - u16 fifo_stat; - u16 dummy12; - u32 __pad[20]; - u16 xmt_data8; - u16 dummy13; - u16 xmt_data16; - u16 dummy14; - u16 rcv_data8; - u16 dummy15; - u16 rcv_data16; - u16 dummy16; -}; - -struct bfin_twi_iface { - int irq; - spinlock_t lock; - char read_write; - u8 command; - u8 *transPtr; - int readNum; - int writeNum; - int cur_mode; - int manual_stop; - int result; - struct i2c_adapter adap; - struct completion complete; - struct i2c_msg *pmsg; - int msg_num; - int cur_msg; - u16 saved_clkdiv; - u16 saved_control; - struct bfin_twi_regs __iomem *regs_base; -}; - -/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/ -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Address Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - -#define DEFINE_TWI_REG(reg_name, reg) \ -static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ - { return bfin_read16(&iface->regs_base->reg); } \ -static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ - { bfin_write16(&iface->regs_base->reg, v); } - -DEFINE_TWI_REG(CLKDIV, clkdiv) -DEFINE_TWI_REG(SLAVE_CTL, slave_ctl) -DEFINE_TWI_REG(SLAVE_STAT, slave_stat) -DEFINE_TWI_REG(SLAVE_ADDR, slave_addr) -DEFINE_TWI_REG(MASTER_CTL, master_ctl) -DEFINE_TWI_REG(MASTER_STAT, master_stat) -DEFINE_TWI_REG(MASTER_ADDR, master_addr) -DEFINE_TWI_REG(INT_STAT, int_stat) -DEFINE_TWI_REG(INT_MASK, int_mask) -DEFINE_TWI_REG(FIFO_STAT, fifo_stat) -DEFINE_TWI_REG(XMT_DATA8, xmt_data8) -DEFINE_TWI_REG(XMT_DATA16, xmt_data16) -#if !ANOMALY_16000030 -DEFINE_TWI_REG(RCV_DATA8, rcv_data8) -DEFINE_TWI_REG(RCV_DATA16, rcv_data16) -#else -static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface) -{ - u16 ret; - unsigned long flags; - - flags = hard_local_irq_save(); - ret = bfin_read16(&iface->regs_base->rcv_data8); - hard_local_irq_restore(flags); - - return ret; -} - -static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface) -{ - u16 ret; - unsigned long flags; - - flags = hard_local_irq_save(); - ret = bfin_read16(&iface->regs_base->rcv_data16); - hard_local_irq_restore(flags); - - return ret; -} -#endif - -static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface) -{ - return bfin_read16(&iface->regs_base->fifo_ctl); -} - -static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v) -{ - bfin_write16(&iface->regs_base->fifo_ctl, v); - SSYNC(); -} - -static inline u16 read_CONTROL(struct bfin_twi_iface *iface) -{ - return bfin_read16(&iface->regs_base->control); -} - -static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v) -{ - SSYNC(); - bfin_write16(&iface->regs_base->control, v); -} -#endif diff --git a/arch/blackfin/include/asm/bfin_watchdog.h b/arch/blackfin/include/asm/bfin_watchdog.h deleted file mode 100644 index dce09829a095..000000000000 --- a/arch/blackfin/include/asm/bfin_watchdog.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * bfin_watchdog.h - Blackfin watchdog definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_WATCHDOG_H -#define _BFIN_WATCHDOG_H - -/* Bit in SWRST that indicates boot caused by watchdog */ -#define SWRST_RESET_WDOG 0x4000 - -/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */ -#define WDOG_EXPIRED 0x8000 - -/* Masks for WDEV field in WDOG_CTL register */ -#define ICTL_RESET 0x0 -#define ICTL_NMI 0x2 -#define ICTL_GPI 0x4 -#define ICTL_NONE 0x6 -#define ICTL_MASK 0x6 - -/* Masks for WDEN field in WDOG_CTL register */ -#define WDEN_MASK 0x0FF0 -#define WDEN_ENABLE 0x0000 -#define WDEN_DISABLE 0x0AD0 - -#endif diff --git a/arch/blackfin/include/asm/bfrom.h b/arch/blackfin/include/asm/bfrom.h deleted file mode 100644 index 9e4be5e5e767..000000000000 --- a/arch/blackfin/include/asm/bfrom.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Blackfin on-chip ROM API - * - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFROM_H__ -#define __BFROM_H__ - -#include - -/* Possible syscontrol action flags */ -#define SYSCTRL_READ 0x00000000 /* read registers */ -#define SYSCTRL_WRITE 0x00000001 /* write registers */ -#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ -#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */ -#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */ -#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ -#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ -#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ -#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ -#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ -#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ -#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ -#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ - -typedef struct ADI_SYSCTRL_VALUES { - uint16_t uwVrCtl; - uint16_t uwPllCtl; - uint16_t uwPllDiv; - uint16_t uwPllLockCnt; - uint16_t uwPllStat; -} ADI_SYSCTRL_VALUES; - -static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038; - -/* We need a dedicated function since we need to screw with the stack pointer - * when resetting. The on-chip ROM will save/restore registers on the stack - * when doing a system reset, so the stack cannot be outside of the chip. - */ -__attribute__((__noreturn__)) -static inline void bfrom_SoftReset(void *new_stack) -{ - while (1) - /* - * We don't declare the SP as clobbered on purpose, since - * it confuses the heck out of the compiler, and this function - * never returns - */ - __asm__ __volatile__( - "sp = %[stack];" - "jump (%[bfrom_syscontrol]);" - : : [bfrom_syscontrol] "p"(bfrom_SysControl), - "q0"(SYSCTRL_SOFTRESET), - "q1"(0), - "q2"(NULL), - [stack] "p"(new_stack) - ); -} - -/* OTP Functions */ -static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018; -static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A; -static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C; - -/* otp command: defines for "command" */ -#define OTP_INIT 0x00000001 -#define OTP_CLOSE 0x00000002 - -/* otp read/write: defines for "flags" */ -#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ -#define OTP_UPPER_HALF 0x00000001 -#define OTP_NO_ECC 0x00000010 /* do not use ECC */ -#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ -#define OTP_CHECK_FOR_PREV_WRITE 0x00000080 - -/* Return values for all functions */ -#define OTP_SUCCESS 0x00000000 -#define OTP_MASTER_ERROR 0x001 -#define OTP_WRITE_ERROR 0x003 -#define OTP_READ_ERROR 0x005 -#define OTP_ACC_VIO_ERROR 0x009 -#define OTP_DATA_MULT_ERROR 0x011 -#define OTP_ECC_MULT_ERROR 0x021 -#define OTP_PREV_WR_ERROR 0x041 -#define OTP_DATA_SB_WARN 0x100 -#define OTP_ECC_SB_WARN 0x200 - -#endif diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h deleted file mode 100644 index b298b654a26f..000000000000 --- a/arch/blackfin/include/asm/bitops.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_BITOPS_H -#define _BLACKFIN_BITOPS_H - -#include - -#include -#include -#include -#include -#include -#include - -#ifndef _LINUX_BITOPS_H -#error only can be included directly -#endif - -#include -#include -#include -#include - -#include - -#include - -#ifndef CONFIG_SMP -#include -/* - * clear_bit may not imply a memory barrier - */ -#include -#include -#else - -#include /* swab32 */ -#include - -asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr); - -asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr); - -asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr); - -asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr); - -asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr); - -asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr); - -asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr); - -static inline void set_bit(int nr, volatile unsigned long *addr) -{ - volatile unsigned long *a = addr + (nr >> 5); - __raw_bit_set_asm(a, nr & 0x1f); -} - -static inline void clear_bit(int nr, volatile unsigned long *addr) -{ - volatile unsigned long *a = addr + (nr >> 5); - __raw_bit_clear_asm(a, nr & 0x1f); -} - -static inline void change_bit(int nr, volatile unsigned long *addr) -{ - volatile unsigned long *a = addr + (nr >> 5); - __raw_bit_toggle_asm(a, nr & 0x1f); -} - -static inline int test_bit(int nr, const volatile unsigned long *addr) -{ - volatile const unsigned long *a = addr + (nr >> 5); - return __raw_bit_test_asm(a, nr & 0x1f) != 0; -} - -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) -{ - volatile unsigned long *a = addr + (nr >> 5); - return __raw_bit_test_set_asm(a, nr & 0x1f); -} - -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - volatile unsigned long *a = addr + (nr >> 5); - return __raw_bit_test_clear_asm(a, nr & 0x1f); -} - -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) -{ - volatile unsigned long *a = addr + (nr >> 5); - return __raw_bit_test_toggle_asm(a, nr & 0x1f); -} - -#define test_bit __skip_test_bit -#include -#undef test_bit - -#endif /* CONFIG_SMP */ - -/* Needs to be after test_bit and friends */ -#include - -/* - * hweightN: returns the hamming weight (i.e. the number - * of bits set) of a N-bit word - */ - -static inline unsigned int __arch_hweight32(unsigned int w) -{ - unsigned int res; - - __asm__ ("%0.l = ONES %1;" - "%0 = %0.l (Z);" - : "=d" (res) : "d" (w)); - return res; -} - -static inline unsigned int __arch_hweight64(__u64 w) -{ - return __arch_hweight32((unsigned int)(w >> 32)) + - __arch_hweight32((unsigned int)w); -} - -static inline unsigned int __arch_hweight16(unsigned int w) -{ - return __arch_hweight32(w & 0xffff); -} - -static inline unsigned int __arch_hweight8(unsigned int w) -{ - return __arch_hweight32(w & 0xff); -} - -#endif /* _BLACKFIN_BITOPS_H */ diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h deleted file mode 100644 index f111f366d758..000000000000 --- a/arch/blackfin/include/asm/blackfin.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Common header file for Blackfin family of processors. - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_H_ -#define _BLACKFIN_H_ - -#include - -#ifndef __ASSEMBLY__ - -/* SSYNC implementation for C file */ -static inline void SSYNC(void) -{ - int _tmp; - if (ANOMALY_05000312 || ANOMALY_05000244) - __asm__ __volatile__( - "cli %0;" - "nop;" - "nop;" - "nop;" - "ssync;" - "sti %0;" - : "=d" (_tmp) - ); - else - __asm__ __volatile__("ssync;"); -} - -/* CSYNC implementation for C file */ -static inline void CSYNC(void) -{ - int _tmp; - if (ANOMALY_05000312 || ANOMALY_05000244) - __asm__ __volatile__( - "cli %0;" - "nop;" - "nop;" - "nop;" - "csync;" - "sti %0;" - : "=d" (_tmp) - ); - else - __asm__ __volatile__("csync;"); -} - -#else /* __ASSEMBLY__ */ - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -/* SSYNC & CSYNC implementations for assembly files */ - -#define ssync(x) SSYNC(x) -#define csync(x) CSYNC(x) - -#if ANOMALY_05000312 || ANOMALY_05000244 -#define SSYNC(scratch) \ - cli scratch; \ - nop; nop; nop; \ - SSYNC; \ - sti scratch; - -#define CSYNC(scratch) \ - cli scratch; \ - nop; nop; nop; \ - CSYNC; \ - sti scratch; - -#else -#define SSYNC(scratch) SSYNC; -#define CSYNC(scratch) CSYNC; -#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */ - -#endif /* __ASSEMBLY__ */ - -#include -#include -#include - -#endif /* _BLACKFIN_H_ */ diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h deleted file mode 100644 index 76b2e82ee730..000000000000 --- a/arch/blackfin/include/asm/bug.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_BUG_H -#define _BLACKFIN_BUG_H - -#ifdef CONFIG_BUG - -/* - * This can be any undefined 16-bit opcode, meaning - * ((opcode & 0xc000) != 0xc000) - * Anything from 0x0001 to 0x000A (inclusive) will work - */ -#define BFIN_BUG_OPCODE 0x0001 - -#ifdef CONFIG_DEBUG_BUGVERBOSE - -#define _BUG_OR_WARN(flags) \ - asm volatile( \ - "1: .hword %0\n" \ - " .section __bug_table,\"aw\",@progbits\n" \ - "2: .long 1b\n" \ - " .long %1\n" \ - " .short %2\n" \ - " .short %3\n" \ - " .org 2b + %4\n" \ - " .previous" \ - : \ - : "i"(BFIN_BUG_OPCODE), "i"(__FILE__), \ - "i"(__LINE__), "i"(flags), \ - "i"(sizeof(struct bug_entry))) - -#else - -#define _BUG_OR_WARN(flags) \ - asm volatile( \ - "1: .hword %0\n" \ - " .section __bug_table,\"aw\",@progbits\n" \ - "2: .long 1b\n" \ - " .short %1\n" \ - " .org 2b + %2\n" \ - " .previous" \ - : \ - : "i"(BFIN_BUG_OPCODE), "i"(flags), \ - "i"(sizeof(struct bug_entry))) - -#endif /* CONFIG_DEBUG_BUGVERBOSE */ - -#define BUG() \ - do { \ - _BUG_OR_WARN(0); \ - unreachable(); \ - } while (0) - -#define WARN_ON(condition) \ - ({ \ - int __ret_warn_on = !!(condition); \ - if (unlikely(__ret_warn_on)) \ - _BUG_OR_WARN(BUGFLAG_WARNING); \ - unlikely(__ret_warn_on); \ - }) - -#define HAVE_ARCH_BUG -#define HAVE_ARCH_WARN_ON - -#endif - -#include - -#endif diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h deleted file mode 100644 index 568885a2c286..000000000000 --- a/arch/blackfin/include/asm/cache.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ARCH_BLACKFIN_CACHE_H -#define __ARCH_BLACKFIN_CACHE_H - -#include /* for asmlinkage */ - -/* - * Bytes per L1 cache line - * Blackfin loads 32 bytes for cache - */ -#define L1_CACHE_SHIFT 5 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES - -#ifdef CONFIG_SMP -#define __cacheline_aligned -#else -#define ____cacheline_aligned - -/* - * Put cacheline_aliged data to L1 data memory - */ -#ifdef CONFIG_CACHELINE_ALIGNED_L1 -#define __cacheline_aligned \ - __attribute__((__aligned__(L1_CACHE_BYTES), \ - __section__(".data_l1.cacheline_aligned"))) -#endif - -#endif - -/* - * largest L1 which this arch supports - */ -#define L1_CACHE_SHIFT_MAX 5 - -#if defined(CONFIG_SMP) && \ - !defined(CONFIG_BFIN_CACHE_COHERENT) -# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE) -# define __ARCH_SYNC_CORE_ICACHE -# endif -# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE) -# define __ARCH_SYNC_CORE_DCACHE -# endif -#ifndef __ASSEMBLY__ -asmlinkage void __raw_smp_mark_barrier_asm(void); -asmlinkage void __raw_smp_check_barrier_asm(void); - -static inline void smp_mark_barrier(void) -{ - __raw_smp_mark_barrier_asm(); -} -static inline void smp_check_barrier(void) -{ - __raw_smp_check_barrier_asm(); -} - -void resync_core_dcache(void); -void resync_core_icache(void); -#endif -#endif - - -#endif diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h deleted file mode 100644 index 9a5b2c572ebf..000000000000 --- a/arch/blackfin/include/asm/cacheflush.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Blackfin low-level cache routines - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_CACHEFLUSH_H -#define _BLACKFIN_CACHEFLUSH_H - -#include /* for SSYNC() */ -#include /* for _ramend */ -#ifdef CONFIG_SMP -#include -#endif - -extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); -extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); -extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); -extern void blackfin_dflush_page(void *page); -extern void blackfin_invalidate_entire_dcache(void); -extern void blackfin_invalidate_entire_icache(void); - -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -#ifdef CONFIG_SMP -#define flush_icache_range_others(start, end) \ - smp_icache_flush_range_others((start), (end)) -#else -#define flush_icache_range_others(start, end) do { } while (0) -#endif - -static inline void flush_icache_range(unsigned start, unsigned end) -{ -#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) - if (end <= physical_mem_end) - blackfin_dcache_flush_range(start, end); -#endif -#if defined(CONFIG_BFIN_L2_WRITEBACK) - if (start >= L2_START && end <= L2_START + L2_LENGTH) - blackfin_dcache_flush_range(start, end); -#endif - - /* Make sure all write buffers in the data side of the core - * are flushed before trying to invalidate the icache. This - * needs to be after the data flush and before the icache - * flush so that the SSYNC does the right thing in preventing - * the instruction prefetcher from hitting things in cached - * memory at the wrong time -- it runs much further ahead than - * the pipeline. - */ - SSYNC(); -#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) - if (end <= physical_mem_end) { - blackfin_icache_flush_range(start, end); - flush_icache_range_others(start, end); - } -#endif -#if defined(CONFIG_BFIN_L2_ICACHEABLE) - if (start >= L2_START && end <= L2_START + L2_LENGTH) { - blackfin_icache_flush_range(start, end); - flush_icache_range_others(start, end); - } -#endif -} - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ -do { memcpy(dst, src, len); \ - flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ -} while (0) - -#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) - -#if defined(CONFIG_BFIN_DCACHE) -# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) -#else -# define invalidate_dcache_range(start,end) do { } while (0) -#endif -#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) -# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 -# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) -#else -# define flush_dcache_range(start,end) do { } while (0) -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 -# define flush_dcache_page(page) do { } while (0) -#endif - -extern unsigned long reserved_mem_dcache_on; -extern unsigned long reserved_mem_icache_on; - -static inline int bfin_addr_dcacheable(unsigned long addr) -{ -#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE - if (addr < (_ramend - DMA_UNCACHED_REGION)) - return 1; -#endif - - if (reserved_mem_dcache_on && - addr >= _ramend && addr < physical_mem_end) - return 1; - -#ifdef CONFIG_BFIN_L2_DCACHEABLE - if (addr >= L2_START && addr < L2_START + L2_LENGTH) - return 1; -#endif - - return 0; -} - -#endif /* _BLACKFIN_ICACHEFLUSH_H */ diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h deleted file mode 100644 index 59af63c0c2be..000000000000 --- a/arch/blackfin/include/asm/cdef_LPBlackfin.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_LPBLACKFIN_H -#define _CDEF_LPBLACKFIN_H - -/*#if !defined(__ADSPLPBLACKFIN__) -#warning cdef_LPBlackfin.h should only be included for 532 compatible chips. -#endif -*/ -#include - -/*Cache & SRAM Memory*/ -#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) -#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) -#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val) -/* -#define MMR_TIMEOUT 0xFFE00010 -*/ -#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val) -#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val) -#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val) -#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val) -#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val) -#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val) -#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val) -#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val) -#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val) -#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val) -#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val) -#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val) -#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val) -#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val) -#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val) -#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val) -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val) -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val) -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val) -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val) -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val) -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val) -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val) -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val) -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val) -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val) -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val) -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val) -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val) -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val) -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val) -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val) -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val) -/* -#define DTEST_INDEX 0xFFE00304 -*/ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val) -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val) -/* -#define DTEST_DATA2 0xFFE00408 -#define DTEST_DATA3 0xFFE0040C -*/ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) -#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val) -#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val) -#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val) -#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val) -#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val) -#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val) -#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val) -#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val) -#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val) -#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val) -#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val) -#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val) -#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val) -#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val) -#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val) -#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val) -#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val) -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val) -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val) -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val) -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val) -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val) -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val) -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val) -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val) -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val) -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val) -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val) -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val) -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val) -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val) -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val) -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val) -#if 0 -#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */ -#endif -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val) - -#if !ANOMALY_05000481 -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#endif - -/* Event/Interrupt Registers*/ - -#define bfin_read_EVT0() bfin_read32(EVT0) -#define bfin_write_EVT0(val) bfin_write32(EVT0,val) -#define bfin_read_EVT1() bfin_read32(EVT1) -#define bfin_write_EVT1(val) bfin_write32(EVT1,val) -#define bfin_read_EVT2() bfin_read32(EVT2) -#define bfin_write_EVT2(val) bfin_write32(EVT2,val) -#define bfin_read_EVT3() bfin_read32(EVT3) -#define bfin_write_EVT3(val) bfin_write32(EVT3,val) -#define bfin_read_EVT4() bfin_read32(EVT4) -#define bfin_write_EVT4(val) bfin_write32(EVT4,val) -#define bfin_read_EVT5() bfin_read32(EVT5) -#define bfin_write_EVT5(val) bfin_write32(EVT5,val) -#define bfin_read_EVT6() bfin_read32(EVT6) -#define bfin_write_EVT6(val) bfin_write32(EVT6,val) -#define bfin_read_EVT7() bfin_read32(EVT7) -#define bfin_write_EVT7(val) bfin_write32(EVT7,val) -#define bfin_read_EVT8() bfin_read32(EVT8) -#define bfin_write_EVT8(val) bfin_write32(EVT8,val) -#define bfin_read_EVT9() bfin_read32(EVT9) -#define bfin_write_EVT9(val) bfin_write32(EVT9,val) -#define bfin_read_EVT10() bfin_read32(EVT10) -#define bfin_write_EVT10(val) bfin_write32(EVT10,val) -#define bfin_read_EVT11() bfin_read32(EVT11) -#define bfin_write_EVT11(val) bfin_write32(EVT11,val) -#define bfin_read_EVT12() bfin_read32(EVT12) -#define bfin_write_EVT12(val) bfin_write32(EVT12,val) -#define bfin_read_EVT13() bfin_read32(EVT13) -#define bfin_write_EVT13(val) bfin_write32(EVT13,val) -#define bfin_read_EVT14() bfin_read32(EVT14) -#define bfin_write_EVT14(val) bfin_write32(EVT14,val) -#define bfin_read_EVT15() bfin_read32(EVT15) -#define bfin_write_EVT15(val) bfin_write32(EVT15,val) -#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) -#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val) -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK,val) -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND,val) -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT,val) -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val) - -/*Core Timer Registers*/ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val) -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val) -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val) -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val) - -/*Debug/MP/Emulation Registers*/ -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID,val) -#define bfin_read_DBGCTL() bfin_read32(DBGCTL) -#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val) -#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT) -#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val) -#define bfin_read_EMUDAT() bfin_read32(EMUDAT) -#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val) - -/*Trace Buffer Registers*/ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val) -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val) -#define bfin_read_TBUF() bfin_read32(TBUF) -#define bfin_write_TBUF(val) bfin_write32(TBUF,val) - -/*Watch Point Control Registers*/ -#define bfin_read_WPIACTL() bfin_read32(WPIACTL) -#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val) -#define bfin_read_WPIA0() bfin_read32(WPIA0) -#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val) -#define bfin_read_WPIA1() bfin_read32(WPIA1) -#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val) -#define bfin_read_WPIA2() bfin_read32(WPIA2) -#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val) -#define bfin_read_WPIA3() bfin_read32(WPIA3) -#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val) -#define bfin_read_WPIA4() bfin_read32(WPIA4) -#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val) -#define bfin_read_WPIA5() bfin_read32(WPIA5) -#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val) -#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0) -#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val) -#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1) -#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val) -#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2) -#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val) -#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3) -#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val) -#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4) -#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val) -#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5) -#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val) -#define bfin_read_WPDACTL() bfin_read32(WPDACTL) -#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val) -#define bfin_read_WPDA0() bfin_read32(WPDA0) -#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val) -#define bfin_read_WPDA1() bfin_read32(WPDA1) -#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val) -#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0) -#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val) -#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1) -#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val) -#define bfin_read_WPSTAT() bfin_read32(WPSTAT) -#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val) - -/*Performance Monitor Registers*/ -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val) - -#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h deleted file mode 100644 index e7134bf94e3c..000000000000 --- a/arch/blackfin/include/asm/checksum.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * akbar.hussain@lineo.com - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_CHECKSUM_H -#define _BFIN_CHECKSUM_H - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ - -static inline __wsum -__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len, - __u8 proto, __wsum sum) -{ - unsigned int carry; - - __asm__ ("%0 = %0 + %2;\n\t" - "CC = AC0;\n\t" - "%1 = CC;\n\t" - "%0 = %0 + %1;\n\t" - "%0 = %0 + %3;\n\t" - "CC = AC0;\n\t" - "%1 = CC;\n\t" - "%0 = %0 + %1;\n\t" - "%0 = %0 + %4;\n\t" - "CC = AC0;\n\t" - "%1 = CC;\n\t" - "%0 = %0 + %1;\n\t" - : "=d" (sum), "=&d" (carry) - : "d" (daddr), "d" (saddr), "d" ((len + proto) << 8), "0"(sum) - : "CC"); - - return (sum); -} -#define csum_tcpudp_nofold __csum_tcpudp_nofold - -#include - -#endif diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h deleted file mode 100644 index 9b3c85b3c288..000000000000 --- a/arch/blackfin/include/asm/clocks.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Common Clock definitions for various kernel files - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_CLOCKS_H -#define _BFIN_CLOCKS_H - -#include - -#ifdef CONFIG_CCLK_DIV_1 -# define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -# define CONFIG_CCLK_DIV 1 -#endif - -#ifdef CONFIG_CCLK_DIV_2 -# define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -# define CONFIG_CCLK_DIV 2 -#endif - -#ifdef CONFIG_CCLK_DIV_4 -# define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -# define CONFIG_CCLK_DIV 4 -#endif - -#ifdef CONFIG_CCLK_DIV_8 -# define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -# define CONFIG_CCLK_DIV 8 -#endif - -#ifndef CONFIG_PLL_BYPASS -# ifndef CONFIG_CLKIN_HALF -# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -# else -# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) -# endif - -# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) -# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) - -#else -# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ) -# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ) -# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ) -# define CONFIG_VCO_MULT 0 -#endif - -#include - -struct clk_ops { - unsigned long (*get_rate)(struct clk *clk); - unsigned long (*round_rate)(struct clk *clk, unsigned long rate); - int (*set_rate)(struct clk *clk, unsigned long rate); - int (*enable)(struct clk *clk); - int (*disable)(struct clk *clk); -}; - -struct clk { - struct clk *parent; - const char *name; - unsigned long rate; - spinlock_t lock; - u32 flags; - const struct clk_ops *ops; - void __iomem *reg; - u32 mask; - u32 shift; -}; - -int clk_init(void); -#endif diff --git a/arch/blackfin/include/asm/cmpxchg.h b/arch/blackfin/include/asm/cmpxchg.h deleted file mode 100644 index 253928854299..000000000000 --- a/arch/blackfin/include/asm/cmpxchg.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2004-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ARCH_BLACKFIN_CMPXCHG__ -#define __ARCH_BLACKFIN_CMPXCHG__ - -#ifdef CONFIG_SMP - -#include - -asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value); -asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value); -asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value); -asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr, - unsigned long new, unsigned long old); -asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr, - unsigned long new, unsigned long old); -asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr, - unsigned long new, unsigned long old); - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) -{ - unsigned long tmp; - - switch (size) { - case 1: - tmp = __raw_xchg_1_asm(ptr, x); - break; - case 2: - tmp = __raw_xchg_2_asm(ptr, x); - break; - case 4: - tmp = __raw_xchg_4_asm(ptr, x); - break; - } - - return tmp; -} - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ -static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, - unsigned long new, int size) -{ - unsigned long tmp; - - switch (size) { - case 1: - tmp = __raw_cmpxchg_1_asm(ptr, new, old); - break; - case 2: - tmp = __raw_cmpxchg_2_asm(ptr, new, old); - break; - case 4: - tmp = __raw_cmpxchg_4_asm(ptr, new, old); - break; - } - - return tmp; -} -#define cmpxchg(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) - -#else /* !CONFIG_SMP */ - -#include -#include - -struct __xchg_dummy { - unsigned long a[100]; -}; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) -{ - unsigned long tmp = 0; - unsigned long flags; - - flags = hard_local_irq_save(); - - switch (size) { - case 1: - __asm__ __volatile__ - ("%0 = b%2 (z);\n\t" - "b%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("%0 = w%2 (z);\n\t" - "w%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("%0 = %2;\n\t" - "%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - hard_local_irq_restore(flags); - return tmp; -} - -#include - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#define cmpxchg(ptr, o, n) cmpxchg_local((ptr), (o), (n)) -#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n)) - -#endif /* !CONFIG_SMP */ - -#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) - -#endif /* __ARCH_BLACKFIN_CMPXCHG__ */ diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S deleted file mode 100644 index 507e7aa6a561..000000000000 --- a/arch/blackfin/include/asm/context.S +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -/* - * NOTE! The single-stepping code assumes that all interrupt handlers - * start by saving SYSCFG on the stack with their first instruction. - */ - -/* - * Code to save processor context. - * We even save the register which are preserved by a function call - * - r4, r5, r6, r7, p3, p4, p5 - */ -.macro save_context_with_interrupts - [--sp] = SYSCFG; - - [--sp] = P0; /*orig_p0*/ - [--sp] = R0; /*orig_r0*/ - - [--sp] = ( R7:0, P5:0 ); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = ASTAT; - - [--sp] = r0; /* Skip reserved */ - [--sp] = RETS; - r0 = RETI; - [--sp] = r0; - [--sp] = RETX; - [--sp] = RETN; - [--sp] = RETE; - [--sp] = SEQSTAT; - [--sp] = r0; /* Skip IPEND as well. */ - /* Switch to other method of keeping interrupts disabled. */ -#ifdef CONFIG_DEBUG_HWERR - r0 = 0x3f; - sti r0; -#else - cli r0; -#endif -#ifdef CONFIG_TRACE_IRQFLAGS - sp += -12; - call _trace_hardirqs_off; - sp += 12; -#endif - [--sp] = RETI; /*orig_pc*/ - /* Clear all L registers. */ - r0 = 0 (x); - l0 = r0; - l1 = r0; - l2 = r0; - l3 = r0; -.endm - -.macro save_context_syscall - [--sp] = SYSCFG; - - [--sp] = P0; /*orig_p0*/ - [--sp] = R0; /*orig_r0*/ - [--sp] = ( R7:0, P5:0 ); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = ASTAT; - - [--sp] = r0; /* Skip reserved */ - [--sp] = RETS; - r0 = RETI; - [--sp] = r0; - [--sp] = RETX; - [--sp] = RETN; - [--sp] = RETE; - [--sp] = SEQSTAT; - [--sp] = r0; /* Skip IPEND as well. */ - [--sp] = RETI; /*orig_pc*/ - /* Clear all L registers. */ - r0 = 0 (x); - l0 = r0; - l1 = r0; - l2 = r0; - l3 = r0; -.endm - -.macro save_context_no_interrupts - [--sp] = SYSCFG; - [--sp] = P0; /* orig_p0 */ - [--sp] = R0; /* orig_r0 */ - [--sp] = ( R7:0, P5:0 ); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = ASTAT; - -#ifdef CONFIG_KGDB - fp = 0(Z); - r1 = sp; - r1 += 60; - r1 += 60; - r1 += 60; - [--sp] = r1; -#else - [--sp] = r0; /* Skip reserved */ -#endif - [--sp] = RETS; - r0 = RETI; - [--sp] = r0; - [--sp] = RETX; - [--sp] = RETN; - [--sp] = RETE; - [--sp] = SEQSTAT; -#ifdef CONFIG_DEBUG_KERNEL - p1.l = lo(IPEND); - p1.h = hi(IPEND); - r1 = [p1]; - [--sp] = r1; -#else - [--sp] = r0; /* Skip IPEND as well. */ -#endif - [--sp] = r0; /*orig_pc*/ - /* Clear all L registers. */ - r0 = 0 (x); - l0 = r0; - l1 = r0; - l2 = r0; - l3 = r0; -.endm - -.macro restore_context_no_interrupts - sp += 4; /* Skip orig_pc */ - sp += 4; /* Skip IPEND */ - SEQSTAT = [sp++]; - RETE = [sp++]; - RETN = [sp++]; - RETX = [sp++]; - r0 = [sp++]; - RETI = r0; /* Restore RETI indirectly when in exception */ - RETS = [sp++]; - - sp += 4; /* Skip Reserved */ - - ASTAT = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - - sp += 4; - fp = [sp++]; - - ( R7 : 0, P5 : 0) = [ SP ++ ]; - sp += 8; /* Skip orig_r0/orig_p0 */ - SYSCFG = [sp++]; -.endm - -.macro restore_context_with_interrupts - sp += 4; /* Skip orig_pc */ - sp += 4; /* Skip IPEND */ - SEQSTAT = [sp++]; - RETE = [sp++]; - RETN = [sp++]; - RETX = [sp++]; - RETI = [sp++]; - -#ifdef CONFIG_TRACE_IRQFLAGS - sp += -12; - call _trace_hardirqs_on; - sp += 12; -#endif - - RETS = [sp++]; - -#ifdef CONFIG_SMP - GET_PDA(p0, r0); - r0 = [p0 + PDA_IRQFLAGS]; -#else - p0.h = _bfin_irq_flags; - p0.l = _bfin_irq_flags; - r0 = [p0]; -#endif - sti r0; - - sp += 4; /* Skip Reserved */ - - ASTAT = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - - sp += 4; - fp = [sp++]; - - ( R7 : 0, P5 : 0) = [ SP ++ ]; - sp += 8; /* Skip orig_r0/orig_p0 */ - csync; - SYSCFG = [sp++]; - csync; -.endm - -.macro save_context_cplb - [--sp] = (R7:0, P5:0); - [--sp] = fp; - - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = RETS; -.endm - -.macro restore_context_cplb - RETS = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - - fp = [sp++]; - - (R7:0, P5:0) = [SP++]; -.endm - -.macro pseudo_long_call func:req, scratch:req -#ifdef CONFIG_ROMKERNEL - \scratch\().l = \func; - \scratch\().h = \func; - call (\scratch); -#else - call \func; -#endif -.endm - -#if defined(CONFIG_BFIN_SCRATCH_REG_RETN) -# define EX_SCRATCH_REG RETN -#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE) -# define EX_SCRATCH_REG RETE -#else -# define EX_SCRATCH_REG CYCLES -#endif - diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h deleted file mode 100644 index 5c37f620c4b3..000000000000 --- a/arch/blackfin/include/asm/cplb.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CPLB_H -#define _CPLB_H - -#include - -#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) -#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) -#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) - -#if ANOMALY_05000158 -#define ANOMALY_05000158_WORKAROUND 0x200 -#else -#define ANOMALY_05000158_WORKAROUND 0x0 -#endif - -#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) - -#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) -#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) -#else -#define SDRAM_DGENERIC (CPLB_COMMON) -#endif - -#define SDRAM_DNON_CHBL (CPLB_COMMON) -#define SDRAM_EBIU (CPLB_COMMON) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) - -#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) - -#ifdef CONFIG_SMP -#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) -#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) -#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB) - -#else -#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) -# if defined(CONFIG_BFIN_L2_ICACHEABLE) -# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) -# else -# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) -# endif - -# if defined(CONFIG_BFIN_L2_WRITEBACK) -# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB) -# elif defined(CONFIG_BFIN_L2_WRITETHROUGH) -# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB) -# else -# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) -# endif -#endif /* CONFIG_SMP */ - -#define SIZE_1K 0x00000400 /* 1K */ -#define SIZE_4K 0x00001000 /* 4K */ -#define SIZE_1M 0x00100000 /* 1M */ -#define SIZE_4M 0x00400000 /* 4M */ -#define SIZE_16K 0x00004000 /* 16K */ -#define SIZE_64K 0x00010000 /* 64K */ -#define SIZE_16M 0x01000000 /* 16M */ -#define SIZE_64M 0x04000000 /* 64M */ - -#define MAX_CPLBS 16 - -#define CPLB_ENABLE_ICACHE_P 0 -#define CPLB_ENABLE_DCACHE_P 1 -#define CPLB_ENABLE_DCACHE2_P 2 -#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ -#define CPLB_ENABLE_ICPLBS_P 4 -#define CPLB_ENABLE_DCPLBS_P 5 - -#define CPLB_ENABLE_ICACHE (1< -#include -#include - -#ifdef CONFIG_CPLB_SWITCH_TAB_L1 -# define PDT_ATTR __attribute__((l1_data)) -#else -# define PDT_ATTR -#endif - -struct cplb_entry { - unsigned long data, addr; -}; - -struct cplb_boundary { - unsigned long eaddr; /* End of this region. */ - unsigned long data; /* CPLB data value. */ -}; - -extern struct cplb_boundary dcplb_bounds[]; -extern struct cplb_boundary icplb_bounds[]; -extern int dcplb_nr_bounds, icplb_nr_bounds; - -extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; -extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; -extern int first_switched_icplb; -extern int first_switched_dcplb; - -extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[]; -extern int nr_dcplb_prot[], nr_cplb_flush[]; - -#ifdef CONFIG_MPU - -extern int first_mask_dcplb; - -extern int page_mask_order; -extern int page_mask_nelts; - -extern unsigned long *current_rwx_mask[NR_CPUS]; - -extern void flush_switched_cplbs(unsigned int); -extern void set_mask_dcplbs(unsigned long *, unsigned int); - -extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); - -#endif /* CONFIG_MPU */ - -extern void bfin_icache_init(struct cplb_entry *icplb_tbl); -extern void bfin_dcache_init(struct cplb_entry *icplb_tbl); - -#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) -extern void generate_cplb_tables_all(void); -extern void generate_cplb_tables_cpu(unsigned int cpu); -#endif -#endif diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h deleted file mode 100644 index e349631c8299..000000000000 --- a/arch/blackfin/include/asm/cpu.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * Philippe Gerum - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_CPU_H -#define __ASM_BLACKFIN_CPU_H - -#include - -struct blackfin_cpudata { - struct cpu cpu; - unsigned int imemctl; - unsigned int dmemctl; -#ifdef CONFIG_SMP - struct task_struct *idle; -#endif -}; - -DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data); - -#endif diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h deleted file mode 100644 index c5c8d8a3a5fa..000000000000 --- a/arch/blackfin/include/asm/def_LPBlackfin.h +++ /dev/null @@ -1,697 +0,0 @@ -/* - * Blackfin core register bit & address definitions - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the Clear BSD license or GPL-2 (or later). - */ - -#ifndef _DEF_LPBLACKFIN_H -#define _DEF_LPBLACKFIN_H - -#include - -#define MK_BMSK_(x) (1<> __ffs(mask)) - -#ifndef __ASSEMBLY__ - -#include - -#if ANOMALY_05000198 -# define NOP_PAD_ANOMALY_05000198 "nop;" -#else -# define NOP_PAD_ANOMALY_05000198 -#endif - -#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \ - u32 __v; \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "%0 = " #asm_size "[%1]" #asm_ext ";" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) -#define _bfin_writeX(addr, val, size, asm_size) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - #asm_size "[%0] = %1;" \ - : \ - : "a" (addr), "d" ((u##size)(val)) \ - : "memory" \ - ) - -#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z)) -#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z)) -#define bfin_read32(addr) _bfin_readX(addr, 32, , ) -#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b) -#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) -#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) - -#define bfin_read(addr) \ -({ \ - sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ - sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ - sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ - ({ BUG(); 0; }); \ -}) -#define bfin_write(addr, val) \ -do { \ - switch (sizeof(*(addr))) { \ - case 1: bfin_write8(addr, val); break; \ - case 2: bfin_write16(addr, val); break; \ - case 4: bfin_write32(addr, val); break; \ - default: BUG(); \ - } \ -} while (0) - -#define bfin_write_or(addr, bits) \ -do { \ - typeof(addr) __addr = (addr); \ - bfin_write(__addr, bfin_read(__addr) | (bits)); \ -} while (0) - -#define bfin_write_and(addr, bits) \ -do { \ - typeof(addr) __addr = (addr); \ - bfin_write(__addr, bfin_read(__addr) & (bits)); \ -} while (0) - -#endif /* __ASSEMBLY__ */ - -/************************************************** - * System Register Bits - **************************************************/ - -/************************************************** - * ASTAT register - **************************************************/ - -/* definitions of ASTAT bit positions*/ - -/*Result of last ALU0 or shifter operation is zero*/ -#define ASTAT_AZ_P 0x00000000 -/*Result of last ALU0 or shifter operation is negative*/ -#define ASTAT_AN_P 0x00000001 -/*Condition Code, used for holding comparison results*/ -#define ASTAT_CC_P 0x00000005 -/*Quotient Bit*/ -#define ASTAT_AQ_P 0x00000006 -/*Rounding mode, set for biased, clear for unbiased*/ -#define ASTAT_RND_MOD_P 0x00000008 -/*Result of last ALU0 operation generated a carry*/ -#define ASTAT_AC0_P 0x0000000C -/*Result of last ALU0 operation generated a carry*/ -#define ASTAT_AC0_COPY_P 0x00000002 -/*Result of last ALU1 operation generated a carry*/ -#define ASTAT_AC1_P 0x0000000D -/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ -#define ASTAT_AV0_P 0x00000010 -/*Sticky version of ASTAT_AV0 */ -#define ASTAT_AV0S_P 0x00000011 -/*Result of last MAC1 operation overflowed, sticky for MAC*/ -#define ASTAT_AV1_P 0x00000012 -/*Sticky version of ASTAT_AV1 */ -#define ASTAT_AV1S_P 0x00000013 -/*Result of last ALU0 or MAC0 operation overflowed*/ -#define ASTAT_V_P 0x00000018 -/*Result of last ALU0 or MAC0 operation overflowed*/ -#define ASTAT_V_COPY_P 0x00000003 -/*Sticky version of ASTAT_V*/ -#define ASTAT_VS_P 0x00000019 - -/* Masks */ - -/*Result of last ALU0 or shifter operation is zero*/ -#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) -/*Result of last ALU0 or shifter operation is negative*/ -#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) -/*Result of last ALU0 operation generated a carry*/ -#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) -/*Result of last ALU0 operation generated a carry*/ -#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) -/*Result of last ALU0 operation generated a carry*/ -#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) -/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ -#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) -/*Result of last MAC1 operation overflowed, sticky for MAC*/ -#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) -/*Condition Code, used for holding comparison results*/ -#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) -/*Quotient Bit*/ -#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) -/*Rounding mode, set for biased, clear for unbiased*/ -#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) -/*Overflow Bit*/ -#define ASTAT_V MK_BMSK_(ASTAT_V_P) -/*Overflow Bit*/ -#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) - -/************************************************** - * SEQSTAT register - **************************************************/ - -/* Bit Positions */ -#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ -#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ -#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ -#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ -#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ -#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ -#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, - * set by IDLE instruction. - */ -#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last - * reset was a software reset - * (=1) - */ -#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ -#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ -#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ -#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ -#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ -/* Masks */ -/* Exception cause */ -#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \ - MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \ - MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \ - MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \ - MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \ - MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \ - 0) - -/* Indicates whether the last reset was a software reset (=1) */ -#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P)) - -/* Last hw error cause */ -#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \ - MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \ - 0) - -/* Translate bits to something useful */ - -/* Last hw error cause */ -#define SEQSTAT_HWERRCAUSE_SHIFT (14) -#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT) -#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT) -#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT) -#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT) - -/************************************************** - * SYSCFG register - **************************************************/ - -/* Bit Positions */ -#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when - * set it forces an exception - * for each instruction executed - */ -#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ -#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ - -/* Masks */ - -/* Supervisor single step, when set it forces an exception for each - *instruction executed - */ -#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P ) -/* Enable cycle counter (=1) */ -#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P ) -/* Self Nesting Interrupt Enable */ -#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) -/* Backward-compatibility for typos in prior releases */ -#define SYSCFG_SSSSTEP SYSCFG_SSSTEP -#define SYSCFG_CCCEN SYSCFG_CCEN - -/**************************************************** - * Core MMR Register Map - ****************************************************/ - -/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ - -#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside - * Buffer Status - */ -#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside - * Buffer Fault Address - */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside - * Buffer 0 - */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside - * Buffer 1 - */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside - * Buffer 2 - */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection - * Lookaside Buffer 3 - */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection - * Lookaside Buffer 4 - */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection - * Lookaside Buffer 5 - */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection - * Lookaside Buffer 6 - */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection - * Lookaside Buffer 7 - */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection - * Lookaside Buffer 8 - */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection - * Lookaside Buffer 9 - */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection - * Lookaside Buffer 10 - */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection - * Lookaside Buffer 11 - */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection - * Lookaside Buffer 12 - */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection - * Lookaside Buffer 13 - */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection - * Lookaside Buffer 14 - */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection - * Lookaside Buffer 15 - */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */ - -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ - -/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ - -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ -#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ -#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability - * Protection Lookaside Buffer 0 - */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability - * Protection Lookaside Buffer 1 - */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability - * Protection Lookaside Buffer 2 - */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability - * Protection Lookaside Buffer 3 - */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability - * Protection Lookaside Buffer 4 - */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability - * Protection Lookaside Buffer 5 - */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability - * Protection Lookaside Buffer 6 - */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability - * Protection Lookaside Buffer 7 - */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability - * Protection Lookaside Buffer 8 - */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability - * Protection Lookaside Buffer 9 - */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability - * Protection Lookaside Buffer 10 - */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability - * Protection Lookaside Buffer 11 - */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability - * Protection Lookaside Buffer 12 - */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability - * Protection Lookaside Buffer 13 - */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability - * Protection Lookaside Buffer 14 - */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability - * Protection Lookaside Buffer 15 - */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ - -/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ - -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ - -/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ - -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ - -/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ -#define DSPID 0xFFE05000 /* DSP Processor ID Register for - * MP implementations - */ - -#define DBGSTAT 0xFFE05008 /* Debug Status Register */ - -/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ - -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ - -/* Watchpoint Instruction Address Control Register */ -#define WPIACTL 0xFFE07000 -/* Watchpoint Instruction Address Register 0 */ -#define WPIA0 0xFFE07040 -/* Watchpoint Instruction Address Register 1 */ -#define WPIA1 0xFFE07044 -/* Watchpoint Instruction Address Register 2 */ -#define WPIA2 0xFFE07048 -/* Watchpoint Instruction Address Register 3 */ -#define WPIA3 0xFFE0704C -/* Watchpoint Instruction Address Register 4 */ -#define WPIA4 0xFFE07050 -/* Watchpoint Instruction Address Register 5 */ -#define WPIA5 0xFFE07054 -/* Watchpoint Instruction Address Count Register 0 */ -#define WPIACNT0 0xFFE07080 -/* Watchpoint Instruction Address Count Register 1 */ -#define WPIACNT1 0xFFE07084 -/* Watchpoint Instruction Address Count Register 2 */ -#define WPIACNT2 0xFFE07088 -/* Watchpoint Instruction Address Count Register 3 */ -#define WPIACNT3 0xFFE0708C -/* Watchpoint Instruction Address Count Register 4 */ -#define WPIACNT4 0xFFE07090 -/* Watchpoint Instruction Address Count Register 5 */ -#define WPIACNT5 0xFFE07094 -/* Watchpoint Data Address Control Register */ -#define WPDACTL 0xFFE07100 -/* Watchpoint Data Address Register 0 */ -#define WPDA0 0xFFE07140 -/* Watchpoint Data Address Register 1 */ -#define WPDA1 0xFFE07144 -/* Watchpoint Data Address Count Value Register 0 */ -#define WPDACNT0 0xFFE07180 -/* Watchpoint Data Address Count Value Register 1 */ -#define WPDACNT1 0xFFE07184 -/* Watchpoint Status Register */ -#define WPSTAT 0xFFE07200 - -/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ - -/* Performance Monitor Control Register */ -#define PFCTL 0xFFE08000 -/* Performance Monitor Counter Register 0 */ -#define PFCNTR0 0xFFE08100 -/* Performance Monitor Counter Register 1 */ -#define PFCNTR1 0xFFE08104 - -/**************************************************** - * Core MMR Register Bits - ****************************************************/ - -/************************************************** - * EVT registers (ILAT, IMASK, and IPEND). - **************************************************/ - -/* Bit Positions */ -#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ -#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ -#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ -#define EVT_EVX_P 0x00000003 /* Exception bit position */ -#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ -#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ -#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ -#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ -#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ -#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ -#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ -#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ -#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ -#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ -#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ -#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ - -/* Masks */ -#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ -#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ -#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ -#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ -#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ -#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ -#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ -#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ -#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ -#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ -#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ -#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ -#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ -#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ -#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ -#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ - -/************************************************** - * DMEM_CONTROL Register - **************************************************/ -/* Bit Positions */ -#define ENDM_P 0x00 /* (doesn't really exist) Enable - *Data Memory L1 - */ -#define DMCTL_ENDM_P ENDM_P /* "" (older define) */ - -#define ENDCPLB_P 0x01 /* Enable DCPLBS */ -#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */ -#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */ -#define DMCTL_DMC0_P DMC0_P /* "" (older define) */ -#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */ -#define DMCTL_DMC1_P DMC1_P /* "" (older define) */ -#define DCBS_P 0x04 /* L1 Data Cache Bank Select */ -#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ -#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ -#define RDCHK 0x9 /* Enable L1 Parity Check */ - -/* Masks */ -#define ENDM 0x00000001 /* (doesn't really exist) Enable - * Data Memory L1 - */ -#define ENDCPLB 0x00000002 /* Enable DCPLB */ -#define ASRAM_BSRAM 0x00000000 -#define ACACHE_BSRAM 0x00000008 -#define ACACHE_BCACHE 0x0000000C -#define DCBS 0x00000010 /* L1 Data Cache Bank Select */ -#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ -#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ - -/* IMEM_CONTROL Register */ -/* Bit Positions */ -#define ENIM_P 0x00 /* Enable L1 Code Memory */ -#define IMCTL_ENIM_P 0x00 /* "" (older define) */ -#define ENICPLB_P 0x01 /* Enable ICPLB */ -#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ -#define IMC_P 0x02 /* Enable */ -#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as - * cache (0=SRAM) - */ -#define ILOC0_P 0x03 /* Lock Way 0 */ -#define ILOC1_P 0x04 /* Lock Way 1 */ -#define ILOC2_P 0x05 /* Lock Way 2 */ -#define ILOC3_P 0x06 /* Lock Way 3 */ -#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement - * Priority - */ -/* Masks */ -#define ENIM 0x00000001 /* Enable L1 Code Memory */ -#define ENICPLB 0x00000002 /* Enable ICPLB */ -#define IMC 0x00000004 /* Configure L1 code memory as - * cache (0=SRAM) - */ -#define ILOC0 0x00000008 /* Lock Way 0 */ -#define ILOC1 0x00000010 /* Lock Way 1 */ -#define ILOC2 0x00000020 /* Lock Way 2 */ -#define ILOC3 0x00000040 /* Lock Way 3 */ -#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement - * Priority - */ - -/* TCNTL Masks */ -#define TMPWR 0x00000001 /* Timer Low Power Control, - * 0=low power mode, 1=active state - */ -#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ -#define TAUTORLD 0x00000004 /* Timer auto reload */ -#define TINT 0x00000008 /* Timer generated interrupt 0=no - * interrupt has been generated, - * 1=interrupt has been generated - * (sticky) - */ - -/* DCPLB_DATA and ICPLB_DATA Registers */ -/* Bit Positions */ -#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry - * locked - */ -#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access - * allowed (user mode) - */ -/* Masks */ -#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry - * locked - */ -#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access - * allowed (user mode) - */ - -#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ -#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ -#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ -#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#ifdef CONFIG_BF60x -#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ -#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ -#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ -#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ -#endif -#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not - * mapped to L1 - */ -#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high - * priority port - */ -#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable - * in L1 - */ -/* ICPLB_DATA only */ -#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, - * 1=priority for non-replacement - */ -/* DCPLB_DATA only */ -#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write - * access allowed (user mode) - */ -#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write - * access allowed (supervisor mode) - */ -#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ -#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on - * write-through writes, - * 1= allocate cache lines on - * write-through writes. - */ -#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ - -#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR - -/* TBUFCTL Masks */ -#define TBUFPWR 0x0001 -#define TBUFEN 0x0002 -#define TBUFOVF 0x0004 -#define TBUFCMPLP_SINGLE 0x0008 -#define TBUFCMPLP_DOUBLE 0x0010 -#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE) - -/* TBUFSTAT Masks */ -#define TBUFCNT 0x001F - -/* ITEST_COMMAND and DTEST_COMMAND Registers */ -/* Masks */ -#define TEST_READ 0x00000000 /* Read Access */ -#define TEST_WRITE 0x00000002 /* Write Access */ -#define TEST_TAG 0x00000000 /* Access TAG */ -#define TEST_DATA 0x00000004 /* Access DATA */ -#define TEST_DW0 0x00000000 /* Select Double Word 0 */ -#define TEST_DW1 0x00000008 /* Select Double Word 1 */ -#define TEST_DW2 0x00000010 /* Select Double Word 2 */ -#define TEST_DW3 0x00000018 /* Select Double Word 3 */ -#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ -#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ -#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ -#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ -#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ -#define TEST_WAY0 0x00000000 /* Access Way0 */ -#define TEST_WAY1 0x04000000 /* Access Way1 */ -/* ITEST_COMMAND only */ -#define TEST_WAY2 0x08000000 /* Access Way2 */ -#define TEST_WAY3 0x0C000000 /* Access Way3 */ -/* DTEST_COMMAND only */ -#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ -#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ - -#endif /* _DEF_LPBLACKFIN_H */ diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h deleted file mode 100644 index 171d8deb04a5..000000000000 --- a/arch/blackfin/include/asm/delay.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * delay.h - delay functions - * - * Copyright (c) 2004-2007 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_DELAY_H__ -#define __ASM_DELAY_H__ - -#include - -static inline void __delay(unsigned long loops) -{ -__asm__ __volatile__ ( - "LSETUP(1f, 1f) LC0 = %0;" - "1: NOP;" - : - : "a" (loops) - : "LT0", "LB0", "LC0" - ); -} - -#include /* needed for HZ */ - -/* - * close approximation borrowed from m68knommu to avoid 64-bit math - */ - -#define HZSCALE (268435456 / (1000000/HZ)) - -static inline unsigned long __to_delay(unsigned long scale) -{ - extern unsigned long loops_per_jiffy; - return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6; -} - -static inline void udelay(unsigned long usecs) -{ - __delay(__to_delay(usecs)); -} - -static inline void ndelay(unsigned long nsecs) -{ - __delay(__to_delay(1) * nsecs / 1000); -} - -#define ndelay ndelay - -#endif diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h deleted file mode 100644 index 04254ac36bed..000000000000 --- a/arch/blackfin/include/asm/dma-mapping.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_DMA_MAPPING_H -#define _BLACKFIN_DMA_MAPPING_H - -#include - -extern void -__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir); -static inline void -__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir) -{ - switch (dir) { - case DMA_NONE: - BUG(); - case DMA_TO_DEVICE: /* writeback only */ - flush_dcache_range(addr, addr + size); - break; - case DMA_FROM_DEVICE: /* invalidate only */ - case DMA_BIDIRECTIONAL: /* flush and invalidate */ - /* Blackfin has no dedicated invalidate (it includes a flush) */ - invalidate_dcache_range(addr, addr + size); - break; - } -} -static inline void -_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir) -{ - if (__builtin_constant_p(dir)) - __dma_sync_inline(addr, size, dir); - else - __dma_sync(addr, size, dir); -} - -extern const struct dma_map_ops bfin_dma_ops; - -static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) -{ - return &bfin_dma_ops; -} - -#endif /* _BLACKFIN_DMA_MAPPING_H */ diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h deleted file mode 100644 index 40e9c2bbc6e3..000000000000 --- a/arch/blackfin/include/asm/dma.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * dma.h - Blackfin DMA defines/structures/etc... - * - * Copyright 2004-2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_DMA_H_ -#define _BLACKFIN_DMA_H_ - -#include -#include -#include -#include -#include -#include -#include - -/*------------------------- - * config reg bits value - *-------------------------*/ -#define DATA_SIZE_8 0 -#define DATA_SIZE_16 1 -#define DATA_SIZE_32 2 -#ifdef CONFIG_BF60x -#define DATA_SIZE_64 3 -#endif - -#define DMA_FLOW_STOP 0 -#define DMA_FLOW_AUTO 1 -#ifdef CONFIG_BF60x -#define DMA_FLOW_LIST 4 -#define DMA_FLOW_ARRAY 5 -#define DMA_FLOW_LIST_DEMAND 6 -#define DMA_FLOW_ARRAY_DEMAND 7 -#else -#define DMA_FLOW_ARRAY 4 -#define DMA_FLOW_SMALL 6 -#define DMA_FLOW_LARGE 7 -#endif - -#define DIMENSION_LINEAR 0 -#define DIMENSION_2D 1 - -#define DIR_READ 0 -#define DIR_WRITE 1 - -#define INTR_DISABLE 0 -#ifdef CONFIG_BF60x -#define INTR_ON_PERI 1 -#endif -#define INTR_ON_BUF 2 -#define INTR_ON_ROW 3 - -#define DMA_NOSYNC_KEEP_DMA_BUF 0 -#define DMA_SYNC_RESTART 1 - -#ifdef DMA_MMR_SIZE_32 -#define DMA_MMR_SIZE_TYPE long -#define DMA_MMR_READ bfin_read32 -#define DMA_MMR_WRITE bfin_write32 -#else -#define DMA_MMR_SIZE_TYPE short -#define DMA_MMR_READ bfin_read16 -#define DMA_MMR_WRITE bfin_write16 -#endif - -struct dma_desc_array { - unsigned long start_addr; - unsigned DMA_MMR_SIZE_TYPE cfg; - unsigned DMA_MMR_SIZE_TYPE x_count; - DMA_MMR_SIZE_TYPE x_modify; -} __attribute__((packed)); - -struct dmasg { - void *next_desc_addr; - unsigned long start_addr; - unsigned DMA_MMR_SIZE_TYPE cfg; - unsigned DMA_MMR_SIZE_TYPE x_count; - DMA_MMR_SIZE_TYPE x_modify; - unsigned DMA_MMR_SIZE_TYPE y_count; - DMA_MMR_SIZE_TYPE y_modify; -} __attribute__((packed)); - -struct dma_register { - void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ - unsigned long start_addr; /* DMA Start address register */ -#ifdef CONFIG_BF60x - unsigned long cfg; /* DMA Configuration register */ - - unsigned long x_count; /* DMA x_count register */ - - long x_modify; /* DMA x_modify register */ - - unsigned long y_count; /* DMA y_count register */ - - long y_modify; /* DMA y_modify register */ - - unsigned long reserved; - unsigned long reserved2; - - void *curr_desc_ptr; /* DMA Current Descriptor Pointer - register */ - void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer - register */ - unsigned long curr_addr_ptr; /* DMA Current Address Pointer - register */ - unsigned long irq_status; /* DMA irq status register */ - - unsigned long curr_x_count; /* DMA Current x-count register */ - - unsigned long curr_y_count; /* DMA Current y-count register */ - - unsigned long reserved3; - - unsigned long bw_limit_count; /* DMA band width limit count register */ - unsigned long curr_bw_limit_count; /* DMA Current band width limit - count register */ - unsigned long bw_monitor_count; /* DMA band width limit count register */ - unsigned long curr_bw_monitor_count; /* DMA Current band width limit - count register */ -#else - unsigned short cfg; /* DMA Configuration register */ - unsigned short dummy1; /* DMA Configuration register */ - - unsigned long reserved; - - unsigned short x_count; /* DMA x_count register */ - unsigned short dummy2; - - short x_modify; /* DMA x_modify register */ - unsigned short dummy3; - - unsigned short y_count; /* DMA y_count register */ - unsigned short dummy4; - - short y_modify; /* DMA y_modify register */ - unsigned short dummy5; - - void *curr_desc_ptr; /* DMA Current Descriptor Pointer - register */ - unsigned long curr_addr_ptr; /* DMA Current Address Pointer - register */ - unsigned short irq_status; /* DMA irq status register */ - unsigned short dummy6; - - unsigned short peripheral_map; /* DMA peripheral map register */ - unsigned short dummy7; - - unsigned short curr_x_count; /* DMA Current x-count register */ - unsigned short dummy8; - - unsigned long reserved2; - - unsigned short curr_y_count; /* DMA Current y-count register */ - unsigned short dummy9; - - unsigned long reserved3; -#endif - -}; - -struct dma_channel { - const char *device_id; - atomic_t chan_status; - volatile struct dma_register *regs; - struct dmasg *sg; /* large mode descriptor */ - unsigned int irq; - void *data; -#ifdef CONFIG_PM - unsigned short saved_peripheral_map; -#endif -}; - -#ifdef CONFIG_PM -int blackfin_dma_suspend(void); -void blackfin_dma_resume(void); -#endif - -/******************************************************************************* -* DMA API's -*******************************************************************************/ -extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; -extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS]; -extern int channel2irq(unsigned int channel); - -static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) -{ - dma_ch[channel].regs->start_addr = addr; -} -static inline void set_dma_next_desc_addr(unsigned int channel, void *addr) -{ - dma_ch[channel].regs->next_desc_ptr = addr; -} -static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr) -{ - dma_ch[channel].regs->curr_desc_ptr = addr; -} -static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count) -{ - dma_ch[channel].regs->x_count = x_count; -} -static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count) -{ - dma_ch[channel].regs->y_count = y_count; -} -static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify) -{ - dma_ch[channel].regs->x_modify = x_modify; -} -static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify) -{ - dma_ch[channel].regs->y_modify = y_modify; -} -static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config) -{ - dma_ch[channel].regs->cfg = config; -} -static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr) -{ - dma_ch[channel].regs->curr_addr_ptr = addr; -} - -#ifdef CONFIG_BF60x -static inline unsigned long -set_bfin_dma_config2(char direction, char flow_mode, char intr_mode, - char dma_mode, char mem_width, char syncmode, char peri_width) -{ - unsigned long config = 0; - - switch (intr_mode) { - case INTR_ON_BUF: - if (dma_mode == DIMENSION_2D) - config = DI_EN_Y; - else - config = DI_EN_X; - break; - case INTR_ON_ROW: - config = DI_EN_X; - break; - case INTR_ON_PERI: - config = DI_EN_P; - break; - }; - - return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) | - (flow_mode << 12) | (syncmode << 2) | (peri_width << 4); -} -#endif - -static inline unsigned DMA_MMR_SIZE_TYPE -set_bfin_dma_config(char direction, char flow_mode, - char intr_mode, char dma_mode, char mem_width, char syncmode) -{ -#ifdef CONFIG_BF60x - return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode, - mem_width, syncmode, mem_width); -#else - return (direction << 1) | (mem_width << 2) | (dma_mode << 4) | - (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); -#endif -} - -static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel) -{ - return dma_ch[channel].regs->irq_status; -} -static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel) -{ - return dma_ch[channel].regs->curr_x_count; -} -static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel) -{ - return dma_ch[channel].regs->curr_y_count; -} -static inline void *get_dma_next_desc_ptr(unsigned int channel) -{ - return dma_ch[channel].regs->next_desc_ptr; -} -static inline void *get_dma_curr_desc_ptr(unsigned int channel) -{ - return dma_ch[channel].regs->curr_desc_ptr; -} -static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel) -{ - return dma_ch[channel].regs->cfg; -} -static inline unsigned long get_dma_curr_addr(unsigned int channel) -{ - return dma_ch[channel].regs->curr_addr_ptr; -} - -static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize) -{ - /* Make sure the internal data buffers in the core are drained - * so that the DMA descriptors are completely written when the - * DMA engine goes to fetch them below. - */ - SSYNC(); - - dma_ch[channel].regs->next_desc_ptr = sg; - dma_ch[channel].regs->cfg = - (dma_ch[channel].regs->cfg & ~NDSIZE) | - ((ndsize << NDSIZE_OFFSET) & NDSIZE); -} - -static inline int dma_channel_active(unsigned int channel) -{ - return atomic_read(&dma_ch[channel].chan_status); -} - -static inline void disable_dma(unsigned int channel) -{ - dma_ch[channel].regs->cfg &= ~DMAEN; - SSYNC(); -} -static inline void enable_dma(unsigned int channel) -{ - dma_ch[channel].regs->curr_x_count = 0; - dma_ch[channel].regs->curr_y_count = 0; - dma_ch[channel].regs->cfg |= DMAEN; -} -int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); - -static inline void dma_disable_irq(unsigned int channel) -{ - disable_irq(dma_ch[channel].irq); -} -static inline void dma_disable_irq_nosync(unsigned int channel) -{ - disable_irq_nosync(dma_ch[channel].irq); -} -static inline void dma_enable_irq(unsigned int channel) -{ - enable_irq(dma_ch[channel].irq); -} -static inline void clear_dma_irqstat(unsigned int channel) -{ - dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ; -} - -void *dma_memcpy(void *dest, const void *src, size_t count); -void *dma_memcpy_nocache(void *dest, const void *src, size_t count); -void *safe_dma_memcpy(void *dest, const void *src, size_t count); -void blackfin_dma_early_init(void); -void early_dma_memcpy(void *dest, const void *src, size_t count); -void early_dma_memcpy_done(void); - -#endif diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h deleted file mode 100644 index 2673b11376f4..000000000000 --- a/arch/blackfin/include/asm/dpmc.h +++ /dev/null @@ -1,794 +0,0 @@ -/* - * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver - * - * Copyright (C) 2004-2009 Analog Device Inc. - * - * Licensed under the GPL-2 - */ - -#ifndef _BLACKFIN_DPMC_H_ -#define _BLACKFIN_DPMC_H_ - -#ifdef __ASSEMBLY__ -#define PM_REG0 R7 -#define PM_REG1 R6 -#define PM_REG2 R5 -#define PM_REG3 R4 -#define PM_REG4 R3 -#define PM_REG5 R2 -#define PM_REG6 R1 -#define PM_REG7 R0 -#define PM_REG8 P5 -#define PM_REG9 P4 -#define PM_REG10 P3 -#define PM_REG11 P2 -#define PM_REG12 P1 -#define PM_REG13 P0 - -#define PM_REGSET0 R7:7 -#define PM_REGSET1 R7:6 -#define PM_REGSET2 R7:5 -#define PM_REGSET3 R7:4 -#define PM_REGSET4 R7:3 -#define PM_REGSET5 R7:2 -#define PM_REGSET6 R7:1 -#define PM_REGSET7 R7:0 -#define PM_REGSET8 R7:0, P5:5 -#define PM_REGSET9 R7:0, P5:4 -#define PM_REGSET10 R7:0, P5:3 -#define PM_REGSET11 R7:0, P5:2 -#define PM_REGSET12 R7:0, P5:1 -#define PM_REGSET13 R7:0, P5:0 - -#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))]; -#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n; -#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n); -#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++]; -#define PM_PUSH(n, x) PM_REG##n = [FP++]; -#define PM_POP(n, x) [FP--] = PM_REG##n; -#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE) -#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE) -#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE) -#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE) -#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE) -#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE) - - .macro bfin_init_pm_bench_cycles -#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH - R4 = 0; - CYCLES = R4; - CYCLES2 = R4; - R4 = SYSCFG; - BITSET(R4, 1); - SYSCFG = R4; -#endif - .endm - - .macro bfin_cpu_reg_save - /* - * Save the core regs early so we can blow them away when - * saving/restoring MMR states - */ - [--sp] = (R7:0, P5:0); - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - /* We can't push RETI directly as that'll change IPEND[4] */ - r7 = RETI; - [--sp] = RETS; - [--sp] = ASTAT; -#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH - [--sp] = CYCLES; - [--sp] = CYCLES2; -#endif - [--sp] = SYSCFG; - [--sp] = RETX; - [--sp] = SEQSTAT; - [--sp] = r7; - - /* Save first func arg in M3 */ - M3 = R0; - .endm - - .macro bfin_cpu_reg_restore - /* Restore Core Registers */ - RETI = [sp++]; - SEQSTAT = [sp++]; - RETX = [sp++]; - SYSCFG = [sp++]; -#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH - CYCLES2 = [sp++]; - CYCLES = [sp++]; -#endif - ASTAT = [sp++]; - RETS = [sp++]; - - LB1 = [sp++]; - LB0 = [sp++]; - LT1 = [sp++]; - LT0 = [sp++]; - LC1 = [sp++]; - LC0 = [sp++]; - - a1.w = [sp++]; - a1.x = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - b3 = [sp++]; - b2 = [sp++]; - b1 = [sp++]; - b0 = [sp++]; - - l3 = [sp++]; - l2 = [sp++]; - l1 = [sp++]; - l0 = [sp++]; - - m3 = [sp++]; - m2 = [sp++]; - m1 = [sp++]; - m0 = [sp++]; - - i3 = [sp++]; - i2 = [sp++]; - i1 = [sp++]; - i0 = [sp++]; - - usp = [sp++]; - fp = [sp++]; - (R7:0, P5:0) = [sp++]; - - .endm - - .macro bfin_sys_mmr_save - /* Save system MMRs */ - FP.H = hi(SYSMMR_BASE); - FP.L = lo(SYSMMR_BASE); -#ifdef SIC_IMASK0 - PM_SYS_PUSH(0, SIC_IMASK0) - PM_SYS_PUSH(1, SIC_IMASK1) -# ifdef SIC_IMASK2 - PM_SYS_PUSH(2, SIC_IMASK2) -# endif -#else -# ifdef SIC_IMASK - PM_SYS_PUSH(0, SIC_IMASK) -# endif -#endif - -#ifdef SIC_IAR0 - PM_SYS_PUSH(3, SIC_IAR0) - PM_SYS_PUSH(4, SIC_IAR1) - PM_SYS_PUSH(5, SIC_IAR2) -#endif -#ifdef SIC_IAR3 - PM_SYS_PUSH(6, SIC_IAR3) -#endif -#ifdef SIC_IAR4 - PM_SYS_PUSH(7, SIC_IAR4) - PM_SYS_PUSH(8, SIC_IAR5) - PM_SYS_PUSH(9, SIC_IAR6) -#endif -#ifdef SIC_IAR7 - PM_SYS_PUSH(10, SIC_IAR7) -#endif -#ifdef SIC_IAR8 - PM_SYS_PUSH(11, SIC_IAR8) - PM_SYS_PUSH(12, SIC_IAR9) - PM_SYS_PUSH(13, SIC_IAR10) -#endif - PM_PUSH_SYNC(13) -#ifdef SIC_IAR11 - PM_SYS_PUSH(0, SIC_IAR11) -#endif - -#ifdef SIC_IWR - PM_SYS_PUSH(1, SIC_IWR) -#endif -#ifdef SIC_IWR0 - PM_SYS_PUSH(1, SIC_IWR0) -#endif -#ifdef SIC_IWR1 - PM_SYS_PUSH(2, SIC_IWR1) -#endif -#ifdef SIC_IWR2 - PM_SYS_PUSH(3, SIC_IWR2) -#endif - -#ifdef PINT0_ASSIGN - PM_SYS_PUSH(4, PINT0_MASK_SET) - PM_SYS_PUSH(5, PINT1_MASK_SET) - PM_SYS_PUSH(6, PINT2_MASK_SET) - PM_SYS_PUSH(7, PINT3_MASK_SET) - PM_SYS_PUSH(8, PINT0_ASSIGN) - PM_SYS_PUSH(9, PINT1_ASSIGN) - PM_SYS_PUSH(10, PINT2_ASSIGN) - PM_SYS_PUSH(11, PINT3_ASSIGN) - PM_SYS_PUSH(12, PINT0_INVERT_SET) - PM_SYS_PUSH(13, PINT1_INVERT_SET) - PM_PUSH_SYNC(13) - PM_SYS_PUSH(0, PINT2_INVERT_SET) - PM_SYS_PUSH(1, PINT3_INVERT_SET) - PM_SYS_PUSH(2, PINT0_EDGE_SET) - PM_SYS_PUSH(3, PINT1_EDGE_SET) - PM_SYS_PUSH(4, PINT2_EDGE_SET) - PM_SYS_PUSH(5, PINT3_EDGE_SET) -#endif - -#ifdef SYSCR - PM_SYS_PUSH16(6, SYSCR) -#endif - -#ifdef EBIU_AMGCTL - PM_SYS_PUSH16(7, EBIU_AMGCTL) - PM_SYS_PUSH(8, EBIU_AMBCTL0) - PM_SYS_PUSH(9, EBIU_AMBCTL1) -#endif -#ifdef EBIU_FCTL - PM_SYS_PUSH(10, EBIU_MBSCTL) - PM_SYS_PUSH(11, EBIU_MODE) - PM_SYS_PUSH(12, EBIU_FCTL) - PM_PUSH_SYNC(12) -#else - PM_PUSH_SYNC(9) -#endif - .endm - - - .macro bfin_sys_mmr_restore -/* Restore System MMRs */ - FP.H = hi(SYSMMR_BASE); - FP.L = lo(SYSMMR_BASE); - -#ifdef EBIU_FCTL - PM_POP_SYNC(12) - PM_SYS_POP(12, EBIU_FCTL) - PM_SYS_POP(11, EBIU_MODE) - PM_SYS_POP(10, EBIU_MBSCTL) -#else - PM_POP_SYNC(9) -#endif - -#ifdef EBIU_AMGCTL - PM_SYS_POP(9, EBIU_AMBCTL1) - PM_SYS_POP(8, EBIU_AMBCTL0) - PM_SYS_POP16(7, EBIU_AMGCTL) -#endif - -#ifdef SYSCR - PM_SYS_POP16(6, SYSCR) -#endif - -#ifdef PINT0_ASSIGN - PM_SYS_POP(5, PINT3_EDGE_SET) - PM_SYS_POP(4, PINT2_EDGE_SET) - PM_SYS_POP(3, PINT1_EDGE_SET) - PM_SYS_POP(2, PINT0_EDGE_SET) - PM_SYS_POP(1, PINT3_INVERT_SET) - PM_SYS_POP(0, PINT2_INVERT_SET) - PM_POP_SYNC(13) - PM_SYS_POP(13, PINT1_INVERT_SET) - PM_SYS_POP(12, PINT0_INVERT_SET) - PM_SYS_POP(11, PINT3_ASSIGN) - PM_SYS_POP(10, PINT2_ASSIGN) - PM_SYS_POP(9, PINT1_ASSIGN) - PM_SYS_POP(8, PINT0_ASSIGN) - PM_SYS_POP(7, PINT3_MASK_SET) - PM_SYS_POP(6, PINT2_MASK_SET) - PM_SYS_POP(5, PINT1_MASK_SET) - PM_SYS_POP(4, PINT0_MASK_SET) -#endif - -#ifdef SIC_IWR2 - PM_SYS_POP(3, SIC_IWR2) -#endif -#ifdef SIC_IWR1 - PM_SYS_POP(2, SIC_IWR1) -#endif -#ifdef SIC_IWR0 - PM_SYS_POP(1, SIC_IWR0) -#endif -#ifdef SIC_IWR - PM_SYS_POP(1, SIC_IWR) -#endif - -#ifdef SIC_IAR11 - PM_SYS_POP(0, SIC_IAR11) -#endif - PM_POP_SYNC(13) -#ifdef SIC_IAR8 - PM_SYS_POP(13, SIC_IAR10) - PM_SYS_POP(12, SIC_IAR9) - PM_SYS_POP(11, SIC_IAR8) -#endif -#ifdef SIC_IAR7 - PM_SYS_POP(10, SIC_IAR7) -#endif -#ifdef SIC_IAR6 - PM_SYS_POP(9, SIC_IAR6) - PM_SYS_POP(8, SIC_IAR5) - PM_SYS_POP(7, SIC_IAR4) -#endif -#ifdef SIC_IAR3 - PM_SYS_POP(6, SIC_IAR3) -#endif -#ifdef SIC_IAR0 - PM_SYS_POP(5, SIC_IAR2) - PM_SYS_POP(4, SIC_IAR1) - PM_SYS_POP(3, SIC_IAR0) -#endif -#ifdef SIC_IMASK0 -# ifdef SIC_IMASK2 - PM_SYS_POP(2, SIC_IMASK2) -# endif - PM_SYS_POP(1, SIC_IMASK1) - PM_SYS_POP(0, SIC_IMASK0) -#else -# ifdef SIC_IMASK - PM_SYS_POP(0, SIC_IMASK) -# endif -#endif - .endm - - .macro bfin_core_mmr_save - /* Save Core MMRs */ - I0.H = hi(COREMMR_BASE); - I0.L = lo(COREMMR_BASE); - I1 = I0; - I2 = I0; - I3 = I0; - B0 = I0; - B1 = I0; - B2 = I0; - B3 = I0; - I1.L = lo(DCPLB_ADDR0); - I2.L = lo(DCPLB_DATA0); - I3.L = lo(ICPLB_ADDR0); - B0.L = lo(ICPLB_DATA0); - B1.L = lo(EVT2); - B2.L = lo(IMASK); - B3.L = lo(TCNTL); - - /* Event Vectors */ - FP = B1; - PM_PUSH(0, EVT2) - PM_PUSH(1, EVT3) - FP += 4; /* EVT4 */ - PM_PUSH(2, EVT5) - PM_PUSH(3, EVT6) - PM_PUSH(4, EVT7) - PM_PUSH(5, EVT8) - PM_PUSH_SYNC(5) - - PM_PUSH(0, EVT9) - PM_PUSH(1, EVT10) - PM_PUSH(2, EVT11) - PM_PUSH(3, EVT12) - PM_PUSH(4, EVT13) - PM_PUSH(5, EVT14) - PM_PUSH(6, EVT15) - - /* CEC */ - FP = B2; - PM_PUSH(7, IMASK) - FP += 4; /* IPEND */ - PM_PUSH(8, ILAT) - PM_PUSH(9, IPRIO) - - /* Core Timer */ - FP = B3; - PM_PUSH(10, TCNTL) - PM_PUSH(11, TPERIOD) - PM_PUSH(12, TSCALE) - PM_PUSH(13, TCOUNT) - PM_PUSH_SYNC(13) - - /* Misc non-contiguous registers */ - FP = I0; - PM_CORE_PUSH(0, DMEM_CONTROL); - PM_CORE_PUSH(1, IMEM_CONTROL); - PM_CORE_PUSH(2, TBUFCTL); - PM_PUSH_SYNC(2) - - /* DCPLB Addr */ - FP = I1; - PM_PUSH(0, DCPLB_ADDR0) - PM_PUSH(1, DCPLB_ADDR1) - PM_PUSH(2, DCPLB_ADDR2) - PM_PUSH(3, DCPLB_ADDR3) - PM_PUSH(4, DCPLB_ADDR4) - PM_PUSH(5, DCPLB_ADDR5) - PM_PUSH(6, DCPLB_ADDR6) - PM_PUSH(7, DCPLB_ADDR7) - PM_PUSH(8, DCPLB_ADDR8) - PM_PUSH(9, DCPLB_ADDR9) - PM_PUSH(10, DCPLB_ADDR10) - PM_PUSH(11, DCPLB_ADDR11) - PM_PUSH(12, DCPLB_ADDR12) - PM_PUSH(13, DCPLB_ADDR13) - PM_PUSH_SYNC(13) - PM_PUSH(0, DCPLB_ADDR14) - PM_PUSH(1, DCPLB_ADDR15) - - /* DCPLB Data */ - FP = I2; - PM_PUSH(2, DCPLB_DATA0) - PM_PUSH(3, DCPLB_DATA1) - PM_PUSH(4, DCPLB_DATA2) - PM_PUSH(5, DCPLB_DATA3) - PM_PUSH(6, DCPLB_DATA4) - PM_PUSH(7, DCPLB_DATA5) - PM_PUSH(8, DCPLB_DATA6) - PM_PUSH(9, DCPLB_DATA7) - PM_PUSH(10, DCPLB_DATA8) - PM_PUSH(11, DCPLB_DATA9) - PM_PUSH(12, DCPLB_DATA10) - PM_PUSH(13, DCPLB_DATA11) - PM_PUSH_SYNC(13) - PM_PUSH(0, DCPLB_DATA12) - PM_PUSH(1, DCPLB_DATA13) - PM_PUSH(2, DCPLB_DATA14) - PM_PUSH(3, DCPLB_DATA15) - - /* ICPLB Addr */ - FP = I3; - PM_PUSH(4, ICPLB_ADDR0) - PM_PUSH(5, ICPLB_ADDR1) - PM_PUSH(6, ICPLB_ADDR2) - PM_PUSH(7, ICPLB_ADDR3) - PM_PUSH(8, ICPLB_ADDR4) - PM_PUSH(9, ICPLB_ADDR5) - PM_PUSH(10, ICPLB_ADDR6) - PM_PUSH(11, ICPLB_ADDR7) - PM_PUSH(12, ICPLB_ADDR8) - PM_PUSH(13, ICPLB_ADDR9) - PM_PUSH_SYNC(13) - PM_PUSH(0, ICPLB_ADDR10) - PM_PUSH(1, ICPLB_ADDR11) - PM_PUSH(2, ICPLB_ADDR12) - PM_PUSH(3, ICPLB_ADDR13) - PM_PUSH(4, ICPLB_ADDR14) - PM_PUSH(5, ICPLB_ADDR15) - - /* ICPLB Data */ - FP = B0; - PM_PUSH(6, ICPLB_DATA0) - PM_PUSH(7, ICPLB_DATA1) - PM_PUSH(8, ICPLB_DATA2) - PM_PUSH(9, ICPLB_DATA3) - PM_PUSH(10, ICPLB_DATA4) - PM_PUSH(11, ICPLB_DATA5) - PM_PUSH(12, ICPLB_DATA6) - PM_PUSH(13, ICPLB_DATA7) - PM_PUSH_SYNC(13) - PM_PUSH(0, ICPLB_DATA8) - PM_PUSH(1, ICPLB_DATA9) - PM_PUSH(2, ICPLB_DATA10) - PM_PUSH(3, ICPLB_DATA11) - PM_PUSH(4, ICPLB_DATA12) - PM_PUSH(5, ICPLB_DATA13) - PM_PUSH(6, ICPLB_DATA14) - PM_PUSH(7, ICPLB_DATA15) - PM_PUSH_SYNC(7) - .endm - - .macro bfin_core_mmr_restore - /* Restore Core MMRs */ - I0.H = hi(COREMMR_BASE); - I0.L = lo(COREMMR_BASE); - I1 = I0; - I2 = I0; - I3 = I0; - B0 = I0; - B1 = I0; - B2 = I0; - B3 = I0; - I1.L = lo(DCPLB_ADDR15); - I2.L = lo(DCPLB_DATA15); - I3.L = lo(ICPLB_ADDR15); - B0.L = lo(ICPLB_DATA15); - B1.L = lo(EVT15); - B2.L = lo(IPRIO); - B3.L = lo(TCOUNT); - - /* ICPLB Data */ - FP = B0; - PM_POP_SYNC(7) - PM_POP(7, ICPLB_DATA15) - PM_POP(6, ICPLB_DATA14) - PM_POP(5, ICPLB_DATA13) - PM_POP(4, ICPLB_DATA12) - PM_POP(3, ICPLB_DATA11) - PM_POP(2, ICPLB_DATA10) - PM_POP(1, ICPLB_DATA9) - PM_POP(0, ICPLB_DATA8) - PM_POP_SYNC(13) - PM_POP(13, ICPLB_DATA7) - PM_POP(12, ICPLB_DATA6) - PM_POP(11, ICPLB_DATA5) - PM_POP(10, ICPLB_DATA4) - PM_POP(9, ICPLB_DATA3) - PM_POP(8, ICPLB_DATA2) - PM_POP(7, ICPLB_DATA1) - PM_POP(6, ICPLB_DATA0) - - /* ICPLB Addr */ - FP = I3; - PM_POP(5, ICPLB_ADDR15) - PM_POP(4, ICPLB_ADDR14) - PM_POP(3, ICPLB_ADDR13) - PM_POP(2, ICPLB_ADDR12) - PM_POP(1, ICPLB_ADDR11) - PM_POP(0, ICPLB_ADDR10) - PM_POP_SYNC(13) - PM_POP(13, ICPLB_ADDR9) - PM_POP(12, ICPLB_ADDR8) - PM_POP(11, ICPLB_ADDR7) - PM_POP(10, ICPLB_ADDR6) - PM_POP(9, ICPLB_ADDR5) - PM_POP(8, ICPLB_ADDR4) - PM_POP(7, ICPLB_ADDR3) - PM_POP(6, ICPLB_ADDR2) - PM_POP(5, ICPLB_ADDR1) - PM_POP(4, ICPLB_ADDR0) - - /* DCPLB Data */ - FP = I2; - PM_POP(3, DCPLB_DATA15) - PM_POP(2, DCPLB_DATA14) - PM_POP(1, DCPLB_DATA13) - PM_POP(0, DCPLB_DATA12) - PM_POP_SYNC(13) - PM_POP(13, DCPLB_DATA11) - PM_POP(12, DCPLB_DATA10) - PM_POP(11, DCPLB_DATA9) - PM_POP(10, DCPLB_DATA8) - PM_POP(9, DCPLB_DATA7) - PM_POP(8, DCPLB_DATA6) - PM_POP(7, DCPLB_DATA5) - PM_POP(6, DCPLB_DATA4) - PM_POP(5, DCPLB_DATA3) - PM_POP(4, DCPLB_DATA2) - PM_POP(3, DCPLB_DATA1) - PM_POP(2, DCPLB_DATA0) - - /* DCPLB Addr */ - FP = I1; - PM_POP(1, DCPLB_ADDR15) - PM_POP(0, DCPLB_ADDR14) - PM_POP_SYNC(13) - PM_POP(13, DCPLB_ADDR13) - PM_POP(12, DCPLB_ADDR12) - PM_POP(11, DCPLB_ADDR11) - PM_POP(10, DCPLB_ADDR10) - PM_POP(9, DCPLB_ADDR9) - PM_POP(8, DCPLB_ADDR8) - PM_POP(7, DCPLB_ADDR7) - PM_POP(6, DCPLB_ADDR6) - PM_POP(5, DCPLB_ADDR5) - PM_POP(4, DCPLB_ADDR4) - PM_POP(3, DCPLB_ADDR3) - PM_POP(2, DCPLB_ADDR2) - PM_POP(1, DCPLB_ADDR1) - PM_POP(0, DCPLB_ADDR0) - - - /* Misc non-contiguous registers */ - - /* icache & dcache will enable later - drop IMEM_CONTROL, DMEM_CONTROL pop - */ - FP = I0; - PM_POP_SYNC(2) - PM_CORE_POP(2, TBUFCTL) - PM_CORE_POP(1, IMEM_CONTROL) - PM_CORE_POP(0, DMEM_CONTROL) - - /* Core Timer */ - FP = B3; - R0 = 0x1; - [FP - 0xC] = R0; - - PM_POP_SYNC(13) - FP = B3; - PM_POP(13, TCOUNT) - PM_POP(12, TSCALE) - PM_POP(11, TPERIOD) - PM_POP(10, TCNTL) - - /* CEC */ - FP = B2; - PM_POP(9, IPRIO) - PM_POP(8, ILAT) - FP += -4; /* IPEND */ - PM_POP(7, IMASK) - - /* Event Vectors */ - FP = B1; - PM_POP(6, EVT15) - PM_POP(5, EVT14) - PM_POP(4, EVT13) - PM_POP(3, EVT12) - PM_POP(2, EVT11) - PM_POP(1, EVT10) - PM_POP(0, EVT9) - PM_POP_SYNC(5) - PM_POP(5, EVT8) - PM_POP(4, EVT7) - PM_POP(3, EVT6) - PM_POP(2, EVT5) - FP += -4; /* EVT4 */ - PM_POP(1, EVT3) - PM_POP(0, EVT2) - .endm -#endif - -#include - -/* PLL_CTL Masks */ -#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ -#define PLL_OFF 0x0002 /* PLL Not Powered */ -#define STOPCK 0x0008 /* Core Clock Off */ -#define PDWN 0x0020 /* Enter Deep Sleep Mode */ -#ifdef __ADSPBF539__ -# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */ -# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */ -#else -# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ -# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ -#endif -#define BYPASS 0x0100 /* Bypass the PLL */ -#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ -#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ -#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ - -/* PLL_DIV Masks */ -#define SSEL 0x000F /* System Select */ -#define CSEL 0x0030 /* Core Select */ -#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ -#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ -#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ -#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ - -#define CCLK_DIV1 CSEL_DIV1 -#define CCLK_DIV2 CSEL_DIV2 -#define CCLK_DIV4 CSEL_DIV4 -#define CCLK_DIV8 CSEL_DIV8 - -#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ - -#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */ -#define CANWS 0x0800 /* CAN Wake-Up Status */ -#define USBWS 0x2000 /* USB Wake-Up Status */ -#define KPADWS 0x4000 /* Keypad Wake-Up Status */ -#define ROTWS 0x8000 /* Rotary Wake-Up Status */ -#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ - -/* VR_CTL Masks */ -#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ -#else -#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ -#endif -#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ - -#define GAIN 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5 */ -#define GAIN_10 0x0004 /* GAIN = 1 */ -#define GAIN_20 0x0008 /* GAIN = 2 */ -#define GAIN_50 0x000C /* GAIN = 5 */ - -#define VLEV 0x00F0 /* Internal Voltage Level */ -#ifdef __ADSPBF52x__ -#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#else -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ -#endif - -#ifdef CONFIG_BF60x -#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */ -#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */ -#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */ -#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */ -#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */ -#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */ -#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */ -#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */ -#else -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ -#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ -#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */ -#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ -#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ -#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ -#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ -#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ - -#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ -#else -#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ -#endif -#endif - -#ifndef __ASSEMBLY__ - -void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); -void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); -void do_hibernate(int wakeup); -void set_dram_srfs(void); -void unset_dram_srfs(void); - -#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) - -#ifdef CONFIG_CPU_FREQ -#define CPUFREQ_CPU 0 -#endif -struct bfin_dpmc_platform_data { - const unsigned int *tuple_tab; - unsigned short tabsize; - unsigned short vr_settling_time; /* in us */ -}; - -#endif - -#endif /*_BLACKFIN_DPMC_H_*/ diff --git a/arch/blackfin/include/asm/early_printk.h b/arch/blackfin/include/asm/early_printk.h deleted file mode 100644 index 68a910db8864..000000000000 --- a/arch/blackfin/include/asm/early_printk.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * function prototpyes for early printk - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_EARLY_PRINTK_H__ -#define __ASM_EARLY_PRINTK_H__ - -#ifdef CONFIG_EARLY_PRINTK -/* For those that don't include it already */ -#include - -extern int setup_early_printk(char *); -extern void enable_shadow_console(void); -extern int shadow_console_enabled(void); -extern void mark_shadow_error(void); -extern void early_shadow_reg(unsigned long reg, unsigned int n); -extern void early_shadow_write(struct console *con, const char *s, - unsigned int n) __attribute__((nonnull(2))); -#define early_shadow_puts(str) early_shadow_write(NULL, str, strlen(str)) -#define early_shadow_stamp() \ - do { \ - early_shadow_puts(__FILE__ " : " __stringify(__LINE__) " ["); \ - early_shadow_puts(__func__); \ - early_shadow_puts("]\n"); \ - } while (0) -#else -#define setup_early_printk(fmt) do { } while (0) -#define enable_shadow_console(fmt) do { } while (0) -#define early_shadow_stamp() do { } while (0) -#endif /* CONFIG_EARLY_PRINTK */ - -#endif /* __ASM_EARLY_PRINTK_H__ */ diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h deleted file mode 100644 index d15cb9b5d52c..000000000000 --- a/arch/blackfin/include/asm/elf.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASMBFIN_ELF_H -#define __ASMBFIN_ELF_H - -/* - * ELF register definitions.. - */ - -#include -#include - -/* Processor specific flags for the ELF header e_flags field. */ -#define EF_BFIN_PIC 0x00000001 /* -fpic */ -#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */ -#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */ -#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */ -#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */ -#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */ - -#if 1 /* core dumps not supported, but linux/elfcore.h needs these */ -typedef unsigned long elf_greg_t; - -#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct { } elf_fpregset_t; -#endif - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN) - -#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */) -#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC) - -/* EM_BLACKFIN defined in linux/elf.h */ - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_BLACKFIN - -#define ELF_PLAT_INIT(_r) _r->p1 = 0 - -#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \ -do { \ - _regs->r7 = 0; \ - _regs->p0 = _exec_map_addr; \ - _regs->p1 = _interp_map_addr; \ - _regs->p2 = _dynamic_addr; \ -} while(0) - -#if 0 -#define CORE_DUMP_USE_REGSET -#endif -#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC -#define ELF_EXEC_PAGESIZE 4096 - -#define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */ -#define R_BFIN_PCREL5M2 1 /* LSETUP part a */ -#define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */ -#define R_BFIN_PCREL10 3 /* type 3, if cc jump */ -#define R_BFIN_PCREL12_JUMP 4 /* type 4, jump */ -#define R_BFIN_RIMM16 5 /* type 0x5, rN = */ -#define R_BFIN_LUIMM16 6 /* # 0x6, preg.l= Load imm 16 to lower half */ -#define R_BFIN_HUIMM16 7 /* # 0x7, preg.h= Load imm 16 to upper half */ -#define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s */ -#define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x */ -#define R_BFIN_PCREL24 10 /* # 0xa call , not expandable */ -#define R_BFIN_UNUSEDB 11 /* # 0xb not generated */ -#define R_BFIN_UNUSEDC 12 /* # 0xc not used */ -#define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l */ -#define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x if is above 24 bit limit call through P1 */ -#define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */ -#define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */ -#define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */ -#define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */ -#define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */ -#define R_BFIN_UNUSED14 20 /* 0x14, undefined */ -#define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */ - -/* arithmetic relocations */ -#define R_BFIN_PUSH 0xE0 -#define R_BFIN_CONST 0xE1 -#define R_BFIN_ADD 0xE2 -#define R_BFIN_SUB 0xE3 -#define R_BFIN_MULT 0xE4 -#define R_BFIN_DIV 0xE5 -#define R_BFIN_MOD 0xE6 -#define R_BFIN_LSHIFT 0xE7 -#define R_BFIN_RSHIFT 0xE8 -#define R_BFIN_AND 0xE9 -#define R_BFIN_OR 0xEA -#define R_BFIN_XOR 0xEB -#define R_BFIN_LAND 0xEC -#define R_BFIN_LOR 0xED -#define R_BFIN_LEN 0xEE -#define R_BFIN_NEG 0xEF -#define R_BFIN_COMP 0xF0 -#define R_BFIN_PAGE 0xF1 -#define R_BFIN_HWPAGE 0xF2 -#define R_BFIN_ADDR 0xF3 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE 0xD0000000UL - -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - memcpy((char *) &pr_reg, (char *)regs, \ - sizeof(struct pt_regs)); -#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */ - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -#define ELF_PLATFORM (NULL) - -#endif diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h deleted file mode 100644 index 4104d5783e2c..000000000000 --- a/arch/blackfin/include/asm/entry.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_ENTRY_H -#define __BFIN_ENTRY_H - -#include -#include - -#ifdef __ASSEMBLY__ - -#define LFLUSH_I_AND_D 0x00000808 -#define LSIGTRAP 5 - -/* - * NOTE! The single-stepping code assumes that all interrupt handlers - * start by saving SYSCFG on the stack with their first instruction. - */ - -/* This one is used for exceptions, emulation, and NMI. It doesn't push - RETI and doesn't do cli. */ -#define SAVE_ALL_SYS save_context_no_interrupts -/* This is used for all normal interrupts. It saves a minimum of registers - to the stack, loads the IRQ number, and jumps to common code. */ -#ifdef CONFIG_IPIPE -# define LOAD_IPIPE_IPEND \ - P0.l = lo(IPEND); \ - P0.h = hi(IPEND); \ - R1 = [P0]; -#else -# define LOAD_IPIPE_IPEND -#endif - -/* - * Workaround for anomalies 05000283 and 05000315 - */ -#if ANOMALY_05000283 || ANOMALY_05000315 -# define ANOMALY_283_315_WORKAROUND(preg, dreg) \ - cc = dreg == dreg; \ - preg.h = HI(CHIPID); \ - preg.l = LO(CHIPID); \ - if cc jump 1f; \ - dreg.l = W[preg]; \ -1: -#else -# define ANOMALY_283_315_WORKAROUND(preg, dreg) -#endif /* ANOMALY_05000283 || ANOMALY_05000315 */ - -#ifndef CONFIG_EXACT_HWERR -/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on, - * otherwise it is a waste of cycles. - */ -# ifndef CONFIG_DEBUG_KERNEL -#define INTERRUPT_ENTRY(N) \ - [--sp] = SYSCFG; \ - [--sp] = P0; /*orig_p0*/ \ - [--sp] = R0; /*orig_r0*/ \ - [--sp] = (R7:0,P5:0); \ - R0 = (N); \ - LOAD_IPIPE_IPEND \ - jump __common_int_entry; -# else /* CONFIG_DEBUG_KERNEL */ -#define INTERRUPT_ENTRY(N) \ - [--sp] = SYSCFG; \ - [--sp] = P0; /*orig_p0*/ \ - [--sp] = R0; /*orig_r0*/ \ - [--sp] = (R7:0,P5:0); \ - p0.l = lo(IPEND); \ - p0.h = hi(IPEND); \ - r1 = [p0]; \ - R0 = (N); \ - LOAD_IPIPE_IPEND \ - jump __common_int_entry; -# endif /* CONFIG_DEBUG_KERNEL */ - -/* For timer interrupts, we need to save IPEND, since the user_mode - *macro accesses it to determine where to account time. - */ -#define TIMER_INTERRUPT_ENTRY(N) \ - [--sp] = SYSCFG; \ - [--sp] = P0; /*orig_p0*/ \ - [--sp] = R0; /*orig_r0*/ \ - [--sp] = (R7:0,P5:0); \ - p0.l = lo(IPEND); \ - p0.h = hi(IPEND); \ - r1 = [p0]; \ - R0 = (N); \ - jump __common_int_entry; -#else /* CONFIG_EXACT_HWERR is defined */ - -/* if we want hardware error to be exact, we need to do a SSYNC (which forces - * read/writes to complete to the memory controllers), and check to see that - * caused a pending HW error condition. If so, we assume it was caused by user - * space, by setting the same interrupt that we are in (so it goes off again) - * and context restore, and a RTI (without servicing anything). This should - * cause the pending HWERR to fire, and when that is done, this interrupt will - * be re-serviced properly. - * As you can see by the code - we actually need to do two SSYNCS - one to - * make sure the read/writes complete, and another to make sure the hardware - * error is recognized by the core. - * - * The extra nop before the SSYNC is to make sure we work around 05000244, - * since the 283/315 workaround includes a branch to the end - */ -#define INTERRUPT_ENTRY(N) \ - [--sp] = SYSCFG; \ - [--sp] = P0; /*orig_p0*/ \ - [--sp] = R0; /*orig_r0*/ \ - [--sp] = (R7:0,P5:0); \ - R1 = ASTAT; \ - ANOMALY_283_315_WORKAROUND(p0, r0) \ - P0.L = LO(ILAT); \ - P0.H = HI(ILAT); \ - NOP; \ - SSYNC; \ - SSYNC; \ - R0 = [P0]; \ - CC = BITTST(R0, EVT_IVHW_P); \ - IF CC JUMP 1f; \ - ASTAT = R1; \ - p0.l = lo(IPEND); \ - p0.h = hi(IPEND); \ - r1 = [p0]; \ - R0 = (N); \ - LOAD_IPIPE_IPEND \ - jump __common_int_entry; \ -1: ASTAT = R1; \ - RAISE N; \ - (R7:0, P5:0) = [SP++]; \ - SP += 0x8; \ - SYSCFG = [SP++]; \ - CSYNC; \ - RTI; - -#define TIMER_INTERRUPT_ENTRY(N) \ - [--sp] = SYSCFG; \ - [--sp] = P0; /*orig_p0*/ \ - [--sp] = R0; /*orig_r0*/ \ - [--sp] = (R7:0,P5:0); \ - R1 = ASTAT; \ - ANOMALY_283_315_WORKAROUND(p0, r0) \ - P0.L = LO(ILAT); \ - P0.H = HI(ILAT); \ - NOP; \ - SSYNC; \ - SSYNC; \ - R0 = [P0]; \ - CC = BITTST(R0, EVT_IVHW_P); \ - IF CC JUMP 1f; \ - ASTAT = R1; \ - p0.l = lo(IPEND); \ - p0.h = hi(IPEND); \ - r1 = [p0]; \ - R0 = (N); \ - jump __common_int_entry; \ -1: ASTAT = R1; \ - RAISE N; \ - (R7:0, P5:0) = [SP++]; \ - SP += 0x8; \ - SYSCFG = [SP++]; \ - CSYNC; \ - RTI; -#endif /* CONFIG_EXACT_HWERR */ - -/* This one pushes RETI without using CLI. Interrupts are enabled. */ -#define SAVE_CONTEXT_SYSCALL save_context_syscall -#define SAVE_CONTEXT save_context_with_interrupts -#define SAVE_CONTEXT_CPLB save_context_cplb - -#define RESTORE_ALL_SYS restore_context_no_interrupts -#define RESTORE_CONTEXT restore_context_with_interrupts -#define RESTORE_CONTEXT_CPLB restore_context_cplb - -#endif /* __ASSEMBLY__ */ -#endif /* __BFIN_ENTRY_H */ diff --git a/arch/blackfin/include/asm/exec.h b/arch/blackfin/include/asm/exec.h deleted file mode 100644 index 54c2e1db274a..000000000000 --- a/arch/blackfin/include/asm/exec.h +++ /dev/null @@ -1 +0,0 @@ -/* define arch_align_stack() here */ diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h deleted file mode 100644 index bc330f06207b..000000000000 --- a/arch/blackfin/include/asm/fixed_code.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file defines the fixed addresses where userspace programs - * can find atomic code sequences. - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ -#ifndef __BFIN_ASM_FIXED_CODE_H__ -#define __BFIN_ASM_FIXED_CODE_H__ - -#include - -#ifndef __ASSEMBLY__ -#include -#include -extern asmlinkage void finish_atomic_sections(struct pt_regs *regs); -extern char fixed_code_start; -extern char fixed_code_end; -extern int atomic_xchg32(void); -extern int atomic_cas32(void); -extern int atomic_add32(void); -extern int atomic_sub32(void); -extern int atomic_ior32(void); -extern int atomic_and32(void); -extern int atomic_xor32(void); -extern void safe_user_instruction(void); -extern void sigreturn_stub(void); -#endif -#endif diff --git a/arch/blackfin/include/asm/flat.h b/arch/blackfin/include/asm/flat.h deleted file mode 100644 index f1d6ba7afbf2..000000000000 --- a/arch/blackfin/include/asm/flat.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * uClinux flat-format executables - * - * Copyright 2003-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 - */ - -#ifndef __BLACKFIN_FLAT_H__ -#define __BLACKFIN_FLAT_H__ - -#include - -#define flat_argvp_envp_on_stack() 0 -#define flat_old_ram_flag(flags) (flags) - -extern unsigned long bfin_get_addr_from_rp (u32 *ptr, u32 relval, - u32 flags, u32 *persistent); - -extern void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval); - -/* The amount by which a relocation can exceed the program image limits - without being regarded as an error. */ - -#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) - -static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags, - u32 *addr, u32 *persistent) -{ - *addr = bfin_get_addr_from_rp(rp, relval, flags, persistent); - return 0; -} - -static inline int flat_put_addr_at_rp(u32 __user *rp, u32 val, u32 relval) -{ - bfin_put_addr_at_rp(rp, val, relval); - return 0; -} - -/* Convert a relocation entry into an address. */ -static inline unsigned long -flat_get_relocate_addr (unsigned long relval) -{ - return relval & 0x03ffffff; /* Mask out top 6 bits */ -} - -static inline int flat_set_persistent(u32 relval, u32 *persistent) -{ - int type = (relval >> 26) & 7; - if (type == 3) { - *persistent = relval << 16; - return 1; - } - return 0; -} - -static inline int flat_addr_absolute(unsigned long relval) -{ - return (relval & (1 << 29)) != 0; -} - -#endif /* __BLACKFIN_FLAT_H__ */ diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h deleted file mode 100644 index 2f1c3c2657ad..000000000000 --- a/arch/blackfin/include/asm/ftrace.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Blackfin ftrace code - * - * Copyright 2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_FTRACE_H__ -#define __ASM_BFIN_FTRACE_H__ - -#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */ - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_DYNAMIC_FTRACE - -extern void _mcount(void); -#define MCOUNT_ADDR ((unsigned long)_mcount) - -static inline unsigned long ftrace_call_adjust(unsigned long addr) -{ - return addr; -} - -struct dyn_arch_ftrace { - /* No extra data needed for Blackfin */ -}; - -#endif - -#ifdef CONFIG_FRAME_POINTER -#include - -extern inline void *return_address(unsigned int level) -{ - unsigned long *endstack, *fp, *ret_addr; - unsigned int current_level = 0; - - if (level == 0) - return __builtin_return_address(0); - - fp = (unsigned long *)__builtin_frame_address(0); - endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level); - - while (((unsigned long)fp & 0x3) == 0 && fp && - (fp + 1) < endstack && current_level < level) { - fp = (unsigned long *)*fp; - current_level++; - } - - if (((unsigned long)fp & 0x3) == 0 && fp && - (fp + 1) < endstack) - ret_addr = (unsigned long *)*(fp + 1); - else - ret_addr = NULL; - - return ret_addr; -} - -#else - -extern inline void *return_address(unsigned int level) -{ - return NULL; -} - -#endif /* CONFIG_FRAME_POINTER */ - -#define ftrace_return_address(n) return_address(n) - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h deleted file mode 100644 index a2579321c7f1..000000000000 --- a/arch/blackfin/include/asm/gpio.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright 2006-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ARCH_BLACKFIN_GPIO_H__ -#define __ARCH_BLACKFIN_GPIO_H__ - -#define gpio_bank(x) ((x) >> 4) -#define gpio_bit(x) (1<<((x) & 0xF)) -#define gpio_sub_n(x) ((x) & 0xF) - -#define GPIO_BANKSIZE 16 -#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) - -#include - -#define PERIPHERAL_USAGE 1 -#define GPIO_USAGE 0 - -#ifndef BFIN_GPIO_PINT -# define BFIN_GPIO_PINT 0 -#endif - -#ifndef __ASSEMBLY__ - -#ifndef CONFIG_PINCTRL - -#include -#include -#include -#include - -/*********************************************************** -* -* FUNCTIONS: Blackfin General Purpose Ports Access Functions -* -* INPUTS/OUTPUTS: -* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS -* -* -* DESCRIPTION: These functions abstract direct register access -* to Blackfin processor General Purpose -* Ports Regsiters -* -* CAUTION: These functions do not belong to the GPIO Driver API -************************************************************* -* MODIFICATION HISTORY : -**************************************************************/ - -void set_gpio_dir(unsigned, unsigned short); -void set_gpio_inen(unsigned, unsigned short); -void set_gpio_polar(unsigned, unsigned short); -void set_gpio_edge(unsigned, unsigned short); -void set_gpio_both(unsigned, unsigned short); -void set_gpio_data(unsigned, unsigned short); -void set_gpio_maska(unsigned, unsigned short); -void set_gpio_maskb(unsigned, unsigned short); -void set_gpio_toggle(unsigned); -void set_gpiop_dir(unsigned, unsigned short); -void set_gpiop_inen(unsigned, unsigned short); -void set_gpiop_polar(unsigned, unsigned short); -void set_gpiop_edge(unsigned, unsigned short); -void set_gpiop_both(unsigned, unsigned short); -void set_gpiop_data(unsigned, unsigned short); -void set_gpiop_maska(unsigned, unsigned short); -void set_gpiop_maskb(unsigned, unsigned short); -unsigned short get_gpio_dir(unsigned); -unsigned short get_gpio_inen(unsigned); -unsigned short get_gpio_polar(unsigned); -unsigned short get_gpio_edge(unsigned); -unsigned short get_gpio_both(unsigned); -unsigned short get_gpio_maska(unsigned); -unsigned short get_gpio_maskb(unsigned); -unsigned short get_gpio_data(unsigned); -unsigned short get_gpiop_dir(unsigned); -unsigned short get_gpiop_inen(unsigned); -unsigned short get_gpiop_polar(unsigned); -unsigned short get_gpiop_edge(unsigned); -unsigned short get_gpiop_both(unsigned); -unsigned short get_gpiop_maska(unsigned); -unsigned short get_gpiop_maskb(unsigned); -unsigned short get_gpiop_data(unsigned); - -struct gpio_port_t { - unsigned short data; - unsigned short dummy1; - unsigned short data_clear; - unsigned short dummy2; - unsigned short data_set; - unsigned short dummy3; - unsigned short toggle; - unsigned short dummy4; - unsigned short maska; - unsigned short dummy5; - unsigned short maska_clear; - unsigned short dummy6; - unsigned short maska_set; - unsigned short dummy7; - unsigned short maska_toggle; - unsigned short dummy8; - unsigned short maskb; - unsigned short dummy9; - unsigned short maskb_clear; - unsigned short dummy10; - unsigned short maskb_set; - unsigned short dummy11; - unsigned short maskb_toggle; - unsigned short dummy12; - unsigned short dir; - unsigned short dummy13; - unsigned short polar; - unsigned short dummy14; - unsigned short edge; - unsigned short dummy15; - unsigned short both; - unsigned short dummy16; - unsigned short inen; -}; - -#ifdef BFIN_SPECIAL_GPIO_BANKS -void bfin_special_gpio_free(unsigned gpio); -int bfin_special_gpio_request(unsigned gpio, const char *label); -# ifdef CONFIG_PM -void bfin_special_gpio_pm_hibernate_restore(void); -void bfin_special_gpio_pm_hibernate_suspend(void); -# endif -#endif - -#ifdef CONFIG_PM -void bfin_gpio_pm_hibernate_restore(void); -void bfin_gpio_pm_hibernate_suspend(void); -int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); -int bfin_gpio_pm_standby_ctrl(unsigned ctrl); - -static inline int bfin_pm_standby_setup(void) -{ - return bfin_gpio_pm_standby_ctrl(1); -} - -static inline void bfin_pm_standby_restore(void) -{ - bfin_gpio_pm_standby_ctrl(0); -} - - -struct gpio_port_s { - unsigned short data; - unsigned short maska; - unsigned short maskb; - unsigned short dir; - unsigned short polar; - unsigned short edge; - unsigned short both; - unsigned short inen; - - unsigned short fer; - unsigned short reserved; - unsigned short mux; -}; -#endif /*CONFIG_PM*/ - -/*********************************************************** -* -* FUNCTIONS: Blackfin GPIO Driver -* -* INPUTS/OUTPUTS: -* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS -* -* -* DESCRIPTION: Blackfin GPIO Driver API -* -* CAUTION: -************************************************************* -* MODIFICATION HISTORY : -**************************************************************/ -int bfin_gpio_irq_request(unsigned gpio, const char *label); -void bfin_gpio_irq_free(unsigned gpio); -void bfin_gpio_irq_prepare(unsigned gpio); - -static inline int irq_to_gpio(unsigned irq) -{ - return irq - GPIO_IRQ_BASE; -} - -#else /* CONFIG_PINCTRL */ - -/* - * CONFIG_PM is not working with pin control and should probably - * avoid being selected when pin control is active, but so far, - * these stubs are here to make allyesconfig and allmodconfig - * compile properly. These functions are normally backed by the - * CONFIG_ADI_GPIO custom GPIO implementation. - */ - -static inline int bfin_pm_standby_setup(void) -{ - return 0; -} - -static inline void bfin_pm_standby_restore(void) -{ -} - -#endif /* CONFIG_PINCTRL */ - -#include -#include - -#include /* cansleep wrappers */ - -static inline int gpio_get_value(unsigned int gpio) -{ - return __gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned int gpio, int value) -{ - __gpio_set_value(gpio, value); -} - -static inline int gpio_cansleep(unsigned int gpio) -{ - return __gpio_cansleep(gpio); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return __gpio_to_irq(gpio); -} -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_BLACKFIN_GPIO_H__ */ diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h deleted file mode 100644 index 381e3d621a4c..000000000000 --- a/arch/blackfin/include/asm/gptimers.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * Copyright (C) 2005 John DeHority - * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) - * - * Licensed under the GPL-2. - */ - -#ifndef _BLACKFIN_TIMERS_H_ -#define _BLACKFIN_TIMERS_H_ - -#include -#include - -/* - * BF51x/BF52x/BF537: 8 timers: - */ -#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY) -# define MAX_BLACKFIN_GPTIMERS 8 -# define TIMER0_GROUP_REG TIMER_ENABLE -#endif -/* - * BF54x: 11 timers (BF542: 8 timers): - */ -#if defined(CONFIG_BF54x) -# ifdef CONFIG_BF542 -# define MAX_BLACKFIN_GPTIMERS 8 -# else -# define MAX_BLACKFIN_GPTIMERS 11 -# define TIMER8_GROUP_REG TIMER_ENABLE1 -# define TIMER_GROUP2 1 -# endif -# define TIMER0_GROUP_REG TIMER_ENABLE0 -#endif -/* - * BF561: 12 timers: - */ -#if defined(CONFIG_BF561) -# define MAX_BLACKFIN_GPTIMERS 12 -# define TIMER0_GROUP_REG TMRS8_ENABLE -# define TIMER8_GROUP_REG TMRS4_ENABLE -# define TIMER_GROUP2 1 -#endif -/* - * BF609: 8 timers: - */ -#if defined(CONFIG_BF60x) -# define MAX_BLACKFIN_GPTIMERS 8 -# define TIMER0_GROUP_REG TIMER_RUN -#endif -/* - * All others: 3 timers: - */ -#define TIMER_GROUP1 0 -#if !defined(MAX_BLACKFIN_GPTIMERS) -# define MAX_BLACKFIN_GPTIMERS 3 -# define TIMER0_GROUP_REG TIMER_ENABLE -#endif - -#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1) -#define BFIN_TIMER_OCTET(x) ((x) >> 3) - -/* used in masks for timer_enable() and timer_disable() */ -#define TIMER0bit 0x0001 /* 0001b */ -#define TIMER1bit 0x0002 /* 0010b */ -#define TIMER2bit 0x0004 /* 0100b */ -#define TIMER3bit 0x0008 -#define TIMER4bit 0x0010 -#define TIMER5bit 0x0020 -#define TIMER6bit 0x0040 -#define TIMER7bit 0x0080 -#define TIMER8bit 0x0100 -#define TIMER9bit 0x0200 -#define TIMER10bit 0x0400 -#define TIMER11bit 0x0800 - -#define TIMER0_id 0 -#define TIMER1_id 1 -#define TIMER2_id 2 -#define TIMER3_id 3 -#define TIMER4_id 4 -#define TIMER5_id 5 -#define TIMER6_id 6 -#define TIMER7_id 7 -#define TIMER8_id 8 -#define TIMER9_id 9 -#define TIMER10_id 10 -#define TIMER11_id 11 - -/* associated timers for ppi framesync: */ - -#if defined(CONFIG_BF561) -# define FS0_1_TIMER_ID TIMER8_id -# define FS0_2_TIMER_ID TIMER9_id -# define FS1_1_TIMER_ID TIMER10_id -# define FS1_2_TIMER_ID TIMER11_id -# define FS0_1_TIMER_BIT TIMER8bit -# define FS0_2_TIMER_BIT TIMER9bit -# define FS1_1_TIMER_BIT TIMER10bit -# define FS1_2_TIMER_BIT TIMER11bit -# undef FS1_TIMER_ID -# undef FS2_TIMER_ID -# undef FS1_TIMER_BIT -# undef FS2_TIMER_BIT -#else -# define FS1_TIMER_ID TIMER0_id -# define FS2_TIMER_ID TIMER1_id -# define FS1_TIMER_BIT TIMER0bit -# define FS2_TIMER_BIT TIMER1bit -#endif - -#ifdef CONFIG_BF60x -/* - * Timer Configuration Register Bits - */ -#define TIMER_EMU_RUN 0x8000 -#define TIMER_BPER_EN 0x4000 -#define TIMER_BWID_EN 0x2000 -#define TIMER_BDLY_EN 0x1000 -#define TIMER_OUT_DIS 0x0800 -#define TIMER_TIN_SEL 0x0400 -#define TIMER_CLK_SEL 0x0300 -#define TIMER_CLK_SCLK 0x0000 -#define TIMER_CLK_ALT_CLK0 0x0100 -#define TIMER_CLK_ALT_CLK1 0x0300 -#define TIMER_PULSE_HI 0x0080 -#define TIMER_SLAVE_TRIG 0x0040 -#define TIMER_IRQ_MODE 0x0030 -#define TIMER_IRQ_ACT_EDGE 0x0000 -#define TIMER_IRQ_DLY 0x0010 -#define TIMER_IRQ_WID_DLY 0x0020 -#define TIMER_IRQ_PER 0x0030 -#define TIMER_MODE 0x000f -#define TIMER_MODE_WDOG_P 0x0008 -#define TIMER_MODE_WDOG_W 0x0009 -#define TIMER_MODE_PWM_CONT 0x000c -#define TIMER_MODE_PWM 0x000d -#define TIMER_MODE_WDTH 0x000a -#define TIMER_MODE_WDTH_D 0x000b -#define TIMER_MODE_EXT_CLK 0x000e -#define TIMER_MODE_PININT 0x000f - -/* - * Timer Status Register Bits - */ -#define TIMER_STATUS_TIMIL0 0x0001 -#define TIMER_STATUS_TIMIL1 0x0002 -#define TIMER_STATUS_TIMIL2 0x0004 -#define TIMER_STATUS_TIMIL3 0x0008 -#define TIMER_STATUS_TIMIL4 0x0010 -#define TIMER_STATUS_TIMIL5 0x0020 -#define TIMER_STATUS_TIMIL6 0x0040 -#define TIMER_STATUS_TIMIL7 0x0080 - -#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */ -#define TIMER_STATUS_TOVF1 0x0002 -#define TIMER_STATUS_TOVF2 0x0004 -#define TIMER_STATUS_TOVF3 0x0008 -#define TIMER_STATUS_TOVF4 0x0010 -#define TIMER_STATUS_TOVF5 0x0020 -#define TIMER_STATUS_TOVF6 0x0040 -#define TIMER_STATUS_TOVF7 0x0080 - -/* - * Timer Slave Enable Status : write 1 to clear - */ -#define TIMER_STATUS_TRUN0 0x0001 -#define TIMER_STATUS_TRUN1 0x0002 -#define TIMER_STATUS_TRUN2 0x0004 -#define TIMER_STATUS_TRUN3 0x0008 -#define TIMER_STATUS_TRUN4 0x0010 -#define TIMER_STATUS_TRUN5 0x0020 -#define TIMER_STATUS_TRUN6 0x0040 -#define TIMER_STATUS_TRUN7 0x0080 - -#else - -/* - * Timer Configuration Register Bits - */ -#define TIMER_ERR 0xC000 -#define TIMER_ERR_OVFL 0x4000 -#define TIMER_ERR_PROG_PER 0x8000 -#define TIMER_ERR_PROG_PW 0xC000 -#define TIMER_EMU_RUN 0x0200 -#define TIMER_TOGGLE_HI 0x0100 -#define TIMER_CLK_SEL 0x0080 -#define TIMER_OUT_DIS 0x0040 -#define TIMER_TIN_SEL 0x0020 -#define TIMER_IRQ_ENA 0x0010 -#define TIMER_PERIOD_CNT 0x0008 -#define TIMER_PULSE_HI 0x0004 -#define TIMER_MODE 0x0003 -#define TIMER_MODE_PWM 0x0001 -#define TIMER_MODE_WDTH 0x0002 -#define TIMER_MODE_EXT_CLK 0x0003 - -/* - * Timer Status Register Bits - */ -#define TIMER_STATUS_TIMIL0 0x0001 -#define TIMER_STATUS_TIMIL1 0x0002 -#define TIMER_STATUS_TIMIL2 0x0004 -#define TIMER_STATUS_TIMIL3 0x00000008 -#define TIMER_STATUS_TIMIL4 0x00010000 -#define TIMER_STATUS_TIMIL5 0x00020000 -#define TIMER_STATUS_TIMIL6 0x00040000 -#define TIMER_STATUS_TIMIL7 0x00080000 -#define TIMER_STATUS_TIMIL8 0x0001 -#define TIMER_STATUS_TIMIL9 0x0002 -#define TIMER_STATUS_TIMIL10 0x0004 -#define TIMER_STATUS_TIMIL11 0x0008 - -#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ -#define TIMER_STATUS_TOVF1 0x0020 -#define TIMER_STATUS_TOVF2 0x0040 -#define TIMER_STATUS_TOVF3 0x00000080 -#define TIMER_STATUS_TOVF4 0x00100000 -#define TIMER_STATUS_TOVF5 0x00200000 -#define TIMER_STATUS_TOVF6 0x00400000 -#define TIMER_STATUS_TOVF7 0x00800000 -#define TIMER_STATUS_TOVF8 0x0010 -#define TIMER_STATUS_TOVF9 0x0020 -#define TIMER_STATUS_TOVF10 0x0040 -#define TIMER_STATUS_TOVF11 0x0080 - -/* - * Timer Slave Enable Status : write 1 to clear - */ -#define TIMER_STATUS_TRUN0 0x1000 -#define TIMER_STATUS_TRUN1 0x2000 -#define TIMER_STATUS_TRUN2 0x4000 -#define TIMER_STATUS_TRUN3 0x00008000 -#define TIMER_STATUS_TRUN4 0x10000000 -#define TIMER_STATUS_TRUN5 0x20000000 -#define TIMER_STATUS_TRUN6 0x40000000 -#define TIMER_STATUS_TRUN7 0x80000000 -#define TIMER_STATUS_TRUN 0xF000F000 -#define TIMER_STATUS_TRUN8 0x1000 -#define TIMER_STATUS_TRUN9 0x2000 -#define TIMER_STATUS_TRUN10 0x4000 -#define TIMER_STATUS_TRUN11 0x8000 - -#endif - -/* The actual gptimer API */ - -void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); -uint32_t get_gptimer_pwidth(unsigned int timer_id); -void set_gptimer_period(unsigned int timer_id, uint32_t period); -uint32_t get_gptimer_period(unsigned int timer_id); -#ifdef CONFIG_BF60x -void set_gptimer_delay(unsigned int timer_id, uint32_t delay); -uint32_t get_gptimer_delay(unsigned int timer_id); -#endif -uint32_t get_gptimer_count(unsigned int timer_id); -int get_gptimer_intr(unsigned int timer_id); -void clear_gptimer_intr(unsigned int timer_id); -int get_gptimer_over(unsigned int timer_id); -void clear_gptimer_over(unsigned int timer_id); -void set_gptimer_config(unsigned int timer_id, uint16_t config); -uint16_t get_gptimer_config(unsigned int timer_id); -int get_gptimer_run(unsigned int timer_id); -void set_gptimer_pulse_hi(unsigned int timer_id); -void clear_gptimer_pulse_hi(unsigned int timer_id); -void enable_gptimers(uint16_t mask); -void disable_gptimers(uint16_t mask); -void disable_gptimers_sync(uint16_t mask); -uint16_t get_enabled_gptimers(void); -uint32_t get_gptimer_status(unsigned int group); -void set_gptimer_status(unsigned int group, uint32_t value); - -static inline void enable_gptimer(unsigned int timer_id) -{ - enable_gptimers(1 << timer_id); -} - -static inline void disable_gptimer(unsigned int timer_id) -{ - disable_gptimers(1 << timer_id); -} - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -#define __BFP(m) u16 m; u16 __pad_##m - -/* - * bfin timer registers layout - */ -struct bfin_gptimer_regs { - __BFP(config); - u32 counter; - u32 period; - u32 width; -#ifdef CONFIG_BF60x - u32 delay; -#endif -}; - -/* - * bfin group timer registers layout - */ -#ifndef CONFIG_BF60x -struct bfin_gptimer_group_regs { - __BFP(enable); - __BFP(disable); - u32 status; -}; -#else -struct bfin_gptimer_group_regs { - __BFP(run); - __BFP(enable); - __BFP(disable); - __BFP(stop_cfg); - __BFP(stop_cfg_set); - __BFP(stop_cfg_clr); - __BFP(data_imsk); - __BFP(stat_imsk); - __BFP(tr_msk); - __BFP(tr_ie); - __BFP(data_ilat); - __BFP(stat_ilat); - __BFP(err_status); - __BFP(bcast_per); - __BFP(bcast_wid); - __BFP(bcast_dly); - -}; -#endif - -#undef __BFP - -#endif diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h deleted file mode 100644 index 58b54a6d5a16..000000000000 --- a/arch/blackfin/include/asm/hardirq.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_HARDIRQ_H -#define __BFIN_HARDIRQ_H - -#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 - -extern void ack_bad_irq(unsigned int irq); -#define ack_bad_irq ack_bad_irq - -#include - -#endif diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h deleted file mode 100644 index 6abebe82d4e9..000000000000 --- a/arch/blackfin/include/asm/io.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_IO_H -#define _BFIN_IO_H - -#include -#include -#include -#include - -#define __raw_readb bfin_read8 -#define __raw_readw bfin_read16 -#define __raw_readl bfin_read32 -#define __raw_writeb(val, addr) bfin_write8(addr, val) -#define __raw_writew(val, addr) bfin_write16(addr, val) -#define __raw_writel(val, addr) bfin_write32(addr, val) - -extern void outsb(unsigned long port, const void *addr, unsigned long count); -extern void outsw(unsigned long port, const void *addr, unsigned long count); -extern void outsw_8(unsigned long port, const void *addr, unsigned long count); -extern void outsl(unsigned long port, const void *addr, unsigned long count); -#define outsb outsb -#define outsw outsw -#define outsl outsl - -extern void insb(unsigned long port, void *addr, unsigned long count); -extern void insw(unsigned long port, void *addr, unsigned long count); -extern void insw_8(unsigned long port, void *addr, unsigned long count); -extern void insl(unsigned long port, void *addr, unsigned long count); -extern void insl_16(unsigned long port, void *addr, unsigned long count); -#define insb insb -#define insw insw -#define insl insl - -/** - * I/O write barrier - * - * Ensure ordering of I/O space writes. This will make sure that writes - * following the barrier will arrive after all previous writes. - */ -#define mmiowb() do { SSYNC(); wmb(); } while (0) - -#include - -#endif diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h deleted file mode 100644 index fe1160fbff91..000000000000 --- a/arch/blackfin/include/asm/ipipe.h +++ /dev/null @@ -1,209 +0,0 @@ -/* -*- linux-c -*- - * include/asm-blackfin/ipipe.h - * - * Copyright (C) 2002-2007 Philippe Gerum. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, - * USA; either version 2 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __ASM_BLACKFIN_IPIPE_H -#define __ASM_BLACKFIN_IPIPE_H - -#ifdef CONFIG_IPIPE - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IPIPE_ARCH_STRING "1.16-01" -#define IPIPE_MAJOR_NUMBER 1 -#define IPIPE_MINOR_NUMBER 16 -#define IPIPE_PATCH_NUMBER 1 - -#ifdef CONFIG_SMP -#error "I-pipe/blackfin: SMP not implemented" -#else /* !CONFIG_SMP */ -#define ipipe_processor_id() 0 -#endif /* CONFIG_SMP */ - -#define prepare_arch_switch(next) \ -do { \ - ipipe_schedule_notify(current, next); \ - hard_local_irq_disable(); \ -} while (0) - -#define task_hijacked(p) \ - ({ \ - int __x__ = __ipipe_root_domain_p; \ - if (__x__) \ - hard_local_irq_enable(); \ - !__x__; \ - }) - -struct ipipe_domain; - -struct ipipe_sysinfo { - int sys_nr_cpus; /* Number of CPUs on board */ - int sys_hrtimer_irq; /* hrtimer device IRQ */ - u64 sys_hrtimer_freq; /* hrtimer device frequency */ - u64 sys_hrclock_freq; /* hrclock device frequency */ - u64 sys_cpu_freq; /* CPU frequency (Hz) */ -}; - -#define ipipe_read_tsc(t) \ - ({ \ - unsigned long __cy2; \ - __asm__ __volatile__ ("1: %0 = CYCLES2\n" \ - "%1 = CYCLES\n" \ - "%2 = CYCLES2\n" \ - "CC = %2 == %0\n" \ - "if ! CC jump 1b\n" \ - : "=d,a" (((unsigned long *)&t)[1]), \ - "=d,a" (((unsigned long *)&t)[0]), \ - "=d,a" (__cy2) \ - : /*no input*/ : "CC"); \ - t; \ - }) - -#define ipipe_cpu_freq() __ipipe_core_clock -#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale) -#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1) - -/* Private interface -- Internal use only */ - -#define __ipipe_check_platform() do { } while (0) - -#define __ipipe_init_platform() do { } while (0) - -extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; - -extern unsigned long __ipipe_irq_lvmask; - -extern struct ipipe_domain ipipe_root; - -/* enable/disable_irqdesc _must_ be used in pairs. */ - -void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, - unsigned irq); - -void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, - unsigned irq); - -#define __ipipe_enable_irq(irq) \ - do { \ - struct irq_desc *desc = irq_to_desc(irq); \ - struct irq_chip *chip = get_irq_desc_chip(desc); \ - chip->irq_unmask(&desc->irq_data); \ - } while (0) - -#define __ipipe_disable_irq(irq) \ - do { \ - struct irq_desc *desc = irq_to_desc(irq); \ - struct irq_chip *chip = get_irq_desc_chip(desc); \ - chip->irq_mask(&desc->irq_data); \ - } while (0) - -static inline int __ipipe_check_tickdev(const char *devname) -{ - return 1; -} - -void __ipipe_enable_pipeline(void); - -#define __ipipe_hook_critical_ipi(ipd) do { } while (0) - -void ___ipipe_sync_pipeline(void); - -void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); - -int __ipipe_get_irq_priority(unsigned int irq); - -void __ipipe_serial_debug(const char *fmt, ...); - -asmlinkage void __ipipe_call_irqtail(unsigned long addr); - -DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); - -extern unsigned long __ipipe_core_clock; - -extern unsigned long __ipipe_freq_scale; - -extern unsigned long __ipipe_irq_tail_hook; - -static inline unsigned long __ipipe_ffnz(unsigned long ul) -{ - return ffs(ul) - 1; -} - -#define __ipipe_do_root_xirq(ipd, irq) \ - ((ipd)->irqs[irq].handler(irq, raw_cpu_ptr(&__ipipe_tick_regs))) - -#define __ipipe_run_irqtail(irq) /* Must be a macro */ \ - do { \ - unsigned long __pending; \ - CSYNC(); \ - __pending = bfin_read_IPEND(); \ - if (__pending & 0x8000) { \ - __pending &= ~0x8010; \ - if (__pending && (__pending & (__pending - 1)) == 0) \ - __ipipe_call_irqtail(__ipipe_irq_tail_hook); \ - } \ - } while (0) - -#define __ipipe_syscall_watched_p(p, sc) \ - (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls) - -#ifdef CONFIG_BF561 -#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) -#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) -#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) -#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() -#elif defined(CONFIG_BF54x) -#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) -#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) -#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) -#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) -#endif - -#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) - -#else /* !CONFIG_IPIPE */ - -#define task_hijacked(p) 0 -#define ipipe_trap_notify(t, r) 0 -#define __ipipe_root_tick_p(regs) 1 - -#endif /* !CONFIG_IPIPE */ - -#ifdef CONFIG_TICKSOURCE_CORETMR -#define IRQ_SYSTMR IRQ_CORETMR -#define IRQ_PRIOTMR IRQ_CORETMR -#else -#define IRQ_SYSTMR IRQ_TIMER0 -#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 -#endif - -#define ipipe_update_tick_evtdev(evtdev) do { } while (0) - -#endif /* !__ASM_BLACKFIN_IPIPE_H */ diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h deleted file mode 100644 index 84a4ffd36747..000000000000 --- a/arch/blackfin/include/asm/ipipe_base.h +++ /dev/null @@ -1,75 +0,0 @@ -/* -*- linux-c -*- - * include/asm-blackfin/ipipe_base.h - * - * Copyright (C) 2007 Philippe Gerum. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, - * USA; either version 2 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __ASM_BLACKFIN_IPIPE_BASE_H -#define __ASM_BLACKFIN_IPIPE_BASE_H - -#ifdef CONFIG_IPIPE - -#include -#include - -#define IPIPE_NR_XIRQS NR_IRQS - -/* Blackfin-specific, per-cpu pipeline status */ -#define IPIPE_SYNCDEFER_FLAG 15 -#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK) - - /* Blackfin traps -- i.e. exception vector numbers */ -#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ -/* Pseudo-vectors used for kernel events */ -#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS -#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT) -#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1) -#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2) -#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3) -#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4) -#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5) -#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6) -#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7) -#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN -#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1) - -#define IPIPE_TIMER_IRQ IRQ_CORETMR - -#define __IPIPE_FEATURE_SYSINFO_V2 1 - -#ifndef __ASSEMBLY__ - -extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ - -void __ipipe_stall_root(void); - -unsigned long __ipipe_test_and_stall_root(void); - -unsigned long __ipipe_test_root(void); - -void __ipipe_lock_root(void); - -void __ipipe_unlock_root(void); - -#endif /* !__ASSEMBLY__ */ - -#define __IPIPE_FEATURE_SYSINFO_V2 1 - -#endif /* CONFIG_IPIPE */ - -#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */ diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h deleted file mode 100644 index 89de539ed010..000000000000 --- a/arch/blackfin/include/asm/irq.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2003 HuTao - * 2002 Arcturus Networks Inc. (www.arcturusnetworks.com - * Ted Ma - * - * Licensed under the GPL-2 - */ - -#ifndef _BFIN_IRQ_H_ -#define _BFIN_IRQ_H_ - -#include - -/* IRQs that may be used by external irq_chip controllers */ -#define NR_SPARE_IRQS 32 - -#include - -/* SYS_IRQS and NR_IRQS are defined in */ -#include - -#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) -# define NOP_PAD_ANOMALY_05000244 "nop; nop;" -#else -# define NOP_PAD_ANOMALY_05000244 -#endif - -#define idle_with_irq_disabled() \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000244 \ - ".align 8;" \ - "sti %0;" \ - "idle;" \ - : \ - : "d" (bfin_irq_flags) \ - ) - -#include - -#endif /* _BFIN_IRQ_H_ */ diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h deleted file mode 100644 index d2f90c72378e..000000000000 --- a/arch/blackfin/include/asm/irq_handler.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _IRQ_HANDLER_H -#define _IRQ_HANDLER_H - -#include -#include -#include - -/* init functions only */ -extern int init_arch_irq(void); -extern void init_exception_vectors(void); -extern void program_IAR(void); -#ifdef init_mach_irq -extern void init_mach_irq(void); -#else -# define init_mach_irq() -#endif - -/* BASE LEVEL interrupt handler routines */ -asmlinkage void evt_exception(void); -asmlinkage void trap(void); -asmlinkage void evt_ivhw(void); -asmlinkage void evt_timer(void); -asmlinkage void evt_nmi(void); -asmlinkage void evt_evt7(void); -asmlinkage void evt_evt8(void); -asmlinkage void evt_evt9(void); -asmlinkage void evt_evt10(void); -asmlinkage void evt_evt11(void); -asmlinkage void evt_evt12(void); -asmlinkage void evt_evt13(void); -asmlinkage void evt_evt14(void); -asmlinkage void evt_soft_int1(void); -asmlinkage void evt_system_call(void); -asmlinkage void init_exception_buff(void); -asmlinkage void trap_c(struct pt_regs *fp); -asmlinkage void ex_replaceable(void); -asmlinkage void early_trap(void); - -extern void *ex_table[]; -extern void return_from_exception(void); - -extern int bfin_request_exception(unsigned int exception, void (*handler)(void)); -extern int bfin_free_exception(unsigned int exception, void (*handler)(void)); - -extern asmlinkage void lower_to_irq14(void); -extern asmlinkage void bfin_return_from_exception(void); -extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); -extern int bfin_internal_set_wake(unsigned int irq, unsigned int state); - -struct irq_data; -extern void bfin_handle_irq(unsigned irq); -extern void bfin_ack_noop(struct irq_data *); -extern void bfin_internal_mask_irq(unsigned int irq); -extern void bfin_internal_unmask_irq(unsigned int irq); - -struct irq_desc; -extern void bfin_demux_mac_status_irq(struct irq_desc *); -extern void bfin_demux_gpio_irq(struct irq_desc *); - -#endif diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h deleted file mode 100644 index 07aff230a812..000000000000 --- a/arch/blackfin/include/asm/irqflags.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * interface to Blackfin CEC - * - * Copyright 2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_IRQFLAGS_H__ -#define __ASM_BFIN_IRQFLAGS_H__ - -#include - -#ifdef CONFIG_SMP -# include -# include -# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask -#else -extern unsigned long bfin_irq_flags; -#endif - -static inline notrace void bfin_sti(unsigned long flags) -{ - asm volatile("sti %0;" : : "d" (flags)); -} - -static inline notrace unsigned long bfin_cli(void) -{ - unsigned long flags; - asm volatile("cli %0;" : "=d" (flags)); - return flags; -} - -#ifdef CONFIG_DEBUG_HWERR -# define bfin_no_irqs 0x3f -#else -# define bfin_no_irqs 0x1f -#endif - -/*****************************************************************************/ -/* - * Hard, untraced CPU interrupt flag manipulation and access. - */ -static inline notrace void __hard_local_irq_disable(void) -{ - bfin_cli(); -} - -static inline notrace void __hard_local_irq_enable(void) -{ - bfin_sti(bfin_irq_flags); -} - -static inline notrace unsigned long hard_local_save_flags(void) -{ - return bfin_read_IMASK(); -} - -static inline notrace unsigned long __hard_local_irq_save(void) -{ - unsigned long flags; - flags = bfin_cli(); -#ifdef CONFIG_DEBUG_HWERR - bfin_sti(0x3f); -#endif - return flags; -} - -static inline notrace int hard_irqs_disabled_flags(unsigned long flags) -{ -#ifdef CONFIG_BF60x - return (flags & IMASK_IVG11) == 0; -#else - return (flags & ~0x3f) == 0; -#endif -} - -static inline notrace int hard_irqs_disabled(void) -{ - unsigned long flags = hard_local_save_flags(); - return hard_irqs_disabled_flags(flags); -} - -static inline notrace void __hard_local_irq_restore(unsigned long flags) -{ - if (!hard_irqs_disabled_flags(flags)) - __hard_local_irq_enable(); -} - -/*****************************************************************************/ -/* - * Interrupt pipe handling. - */ -#ifdef CONFIG_IPIPE - -#include -#include -/* - * Way too many inter-deps between low-level headers in this port, so - * we redeclare the required bits we cannot pick from - * to prevent circular dependencies. - */ -void __ipipe_stall_root(void); -void __ipipe_unstall_root(void); -unsigned long __ipipe_test_root(void); -unsigned long __ipipe_test_and_stall_root(void); -void __ipipe_restore_root(unsigned long flags); - -#ifdef CONFIG_IPIPE_DEBUG_CONTEXT -struct ipipe_domain; -extern struct ipipe_domain ipipe_root; -void ipipe_check_context(struct ipipe_domain *ipd); -#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root) -#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */ -#define __check_irqop_context(ipd) do { } while (0) -#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */ - -/* - * Interrupt pipe interface to linux/irqflags.h. - */ -static inline notrace void arch_local_irq_disable(void) -{ - __check_irqop_context(); - __ipipe_stall_root(); - barrier(); -} - -static inline notrace void arch_local_irq_enable(void) -{ - barrier(); - __check_irqop_context(); - __ipipe_unstall_root(); -} - -static inline notrace unsigned long arch_local_save_flags(void) -{ - return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; -} - -static inline notrace int arch_irqs_disabled_flags(unsigned long flags) -{ - return flags == bfin_no_irqs; -} - -static inline notrace unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - - __check_irqop_context(); - flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; - barrier(); - - return flags; -} - -static inline notrace void arch_local_irq_restore(unsigned long flags) -{ - __check_irqop_context(); - __ipipe_restore_root(flags == bfin_no_irqs); -} - -static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real) -{ - /* - * Merge virtual and real interrupt mask bits into a single - * 32bit word. - */ - return (real & ~(1 << 31)) | ((virt != 0) << 31); -} - -static inline notrace int arch_demangle_irq_bits(unsigned long *x) -{ - int virt = (*x & (1 << 31)) != 0; - *x &= ~(1L << 31); - return virt; -} - -/* - * Interface to various arch routines that may be traced. - */ -#ifdef CONFIG_IPIPE_TRACE_IRQSOFF -static inline notrace void hard_local_irq_disable(void) -{ - if (!hard_irqs_disabled()) { - __hard_local_irq_disable(); - ipipe_trace_begin(0x80000000); - } -} - -static inline notrace void hard_local_irq_enable(void) -{ - if (hard_irqs_disabled()) { - ipipe_trace_end(0x80000000); - __hard_local_irq_enable(); - } -} - -static inline notrace unsigned long hard_local_irq_save(void) -{ - unsigned long flags = hard_local_save_flags(); - if (!hard_irqs_disabled_flags(flags)) { - __hard_local_irq_disable(); - ipipe_trace_begin(0x80000001); - } - return flags; -} - -static inline notrace void hard_local_irq_restore(unsigned long flags) -{ - if (!hard_irqs_disabled_flags(flags)) { - ipipe_trace_end(0x80000001); - __hard_local_irq_enable(); - } -} - -#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */ -# define hard_local_irq_disable() __hard_local_irq_disable() -# define hard_local_irq_enable() __hard_local_irq_enable() -# define hard_local_irq_save() __hard_local_irq_save() -# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) -#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ - -#define hard_local_irq_save_cond() hard_local_irq_save() -#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags) - -#else /* !CONFIG_IPIPE */ - -/* - * Direct interface to linux/irqflags.h. - */ -#define arch_local_save_flags() hard_local_save_flags() -#define arch_local_irq_save() __hard_local_irq_save() -#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags) -#define arch_local_irq_enable() __hard_local_irq_enable() -#define arch_local_irq_disable() __hard_local_irq_disable() -#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags) -#define arch_irqs_disabled() hard_irqs_disabled() - -/* - * Interface to various arch routines that may be traced. - */ -#define hard_local_irq_save() __hard_local_irq_save() -#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) -#define hard_local_irq_enable() __hard_local_irq_enable() -#define hard_local_irq_disable() __hard_local_irq_disable() -#define hard_local_irq_save_cond() hard_local_save_flags() -#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0) - -#endif /* !CONFIG_IPIPE */ - -#ifdef CONFIG_SMP -#define hard_local_irq_save_smp() hard_local_irq_save() -#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags) -#else -#define hard_local_irq_save_smp() hard_local_save_flags() -#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0) -#endif - -/* - * Remap the arch-neutral IRQ state manipulation macros to the - * blackfin-specific hard_local_irq_* API. - */ -#define local_irq_save_hw(flags) \ - do { \ - (flags) = hard_local_irq_save(); \ - } while (0) -#define local_irq_restore_hw(flags) \ - do { \ - hard_local_irq_restore(flags); \ - } while (0) -#define local_irq_disable_hw() \ - do { \ - hard_local_irq_disable(); \ - } while (0) -#define local_irq_enable_hw() \ - do { \ - hard_local_irq_enable(); \ - } while (0) -#define local_irq_save_hw_notrace(flags) \ - do { \ - (flags) = __hard_local_irq_save(); \ - } while (0) -#define local_irq_restore_hw_notrace(flags) \ - do { \ - __hard_local_irq_restore(flags); \ - } while (0) - -#define irqs_disabled_hw() hard_irqs_disabled() - -#endif diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h deleted file mode 100644 index 2703ddeeb5db..000000000000 --- a/arch/blackfin/include/asm/kgdb.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Blackfin KGDB header - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_KGDB_H__ -#define __ASM_BLACKFIN_KGDB_H__ - -#include - -/* - * BUFMAX defines the maximum number of characters in inbound/outbound buffers. - * At least NUMREGBYTES*2 are needed for register packets. - * Longer buffer is needed to list all threads. - */ -#define BUFMAX 2048 - -/* - * Note that this register image is different from - * the register image that Linux produces at interrupt time. - * - * Linux's register image is defined by struct pt_regs in ptrace.h. - */ -enum regnames { - /* Core Registers */ - BFIN_R0 = 0, - BFIN_R1, - BFIN_R2, - BFIN_R3, - BFIN_R4, - BFIN_R5, - BFIN_R6, - BFIN_R7, - BFIN_P0, - BFIN_P1, - BFIN_P2, - BFIN_P3, - BFIN_P4, - BFIN_P5, - BFIN_SP, - BFIN_FP, - BFIN_I0, - BFIN_I1, - BFIN_I2, - BFIN_I3, - BFIN_M0, - BFIN_M1, - BFIN_M2, - BFIN_M3, - BFIN_B0, - BFIN_B1, - BFIN_B2, - BFIN_B3, - BFIN_L0, - BFIN_L1, - BFIN_L2, - BFIN_L3, - BFIN_A0_DOT_X, - BFIN_A0_DOT_W, - BFIN_A1_DOT_X, - BFIN_A1_DOT_W, - BFIN_ASTAT, - BFIN_RETS, - BFIN_LC0, - BFIN_LT0, - BFIN_LB0, - BFIN_LC1, - BFIN_LT1, - BFIN_LB1, - BFIN_CYCLES, - BFIN_CYCLES2, - BFIN_USP, - BFIN_SEQSTAT, - BFIN_SYSCFG, - BFIN_RETI, - BFIN_RETX, - BFIN_RETN, - BFIN_RETE, - - /* Pseudo Registers */ - BFIN_PC, - BFIN_CC, - BFIN_EXTRA1, /* Address of .text section. */ - BFIN_EXTRA2, /* Address of .data section. */ - BFIN_EXTRA3, /* Address of .bss section. */ - BFIN_FDPIC_EXEC, - BFIN_FDPIC_INTERP, - - /* MMRs */ - BFIN_IPEND, - - /* LAST ENTRY SHOULD NOT BE CHANGED. */ - BFIN_NUM_REGS /* The number of all registers. */ -}; - -/* Number of bytes of registers. */ -#define NUMREGBYTES BFIN_NUM_REGS*4 - -static inline void arch_kgdb_breakpoint(void) -{ - asm("EXCPT 2;"); -} -#define BREAK_INSTR_SIZE 2 -#ifdef CONFIG_SMP -# define CACHE_FLUSH_IS_SAFE 0 -#else -# define CACHE_FLUSH_IS_SAFE 1 -#endif -#define GDB_ADJUSTS_BREAK_OFFSET -#define GDB_SKIP_HW_WATCH_TEST -#define HW_INST_WATCHPOINT_NUM 6 -#define HW_WATCHPOINT_NUM 8 -#define TYPE_INST_WATCHPOINT 0 -#define TYPE_DATA_WATCHPOINT 1 - -/* Instruction watchpoint address control register bits mask */ -#define WPPWR 0x1 -#define WPIREN01 0x2 -#define WPIRINV01 0x4 -#define WPIAEN0 0x8 -#define WPIAEN1 0x10 -#define WPICNTEN0 0x20 -#define WPICNTEN1 0x40 -#define EMUSW0 0x80 -#define EMUSW1 0x100 -#define WPIREN23 0x200 -#define WPIRINV23 0x400 -#define WPIAEN2 0x800 -#define WPIAEN3 0x1000 -#define WPICNTEN2 0x2000 -#define WPICNTEN3 0x4000 -#define EMUSW2 0x8000 -#define EMUSW3 0x10000 -#define WPIREN45 0x20000 -#define WPIRINV45 0x40000 -#define WPIAEN4 0x80000 -#define WPIAEN5 0x100000 -#define WPICNTEN4 0x200000 -#define WPICNTEN5 0x400000 -#define EMUSW4 0x800000 -#define EMUSW5 0x1000000 -#define WPAND 0x2000000 - -/* Data watchpoint address control register bits mask */ -#define WPDREN01 0x1 -#define WPDRINV01 0x2 -#define WPDAEN0 0x4 -#define WPDAEN1 0x8 -#define WPDCNTEN0 0x10 -#define WPDCNTEN1 0x20 - -#define WPDSRC0 0xc0 -#define WPDACC0_OFFSET 8 -#define WPDSRC1 0xc00 -#define WPDACC1_OFFSET 12 - -/* Watchpoint status register bits mask */ -#define STATIA0 0x1 -#define STATIA1 0x2 -#define STATIA2 0x4 -#define STATIA3 0x8 -#define STATIA4 0x10 -#define STATIA5 0x20 -#define STATDA0 0x40 -#define STATDA1 0x80 - -#endif diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h deleted file mode 100644 index c87e68647a2b..000000000000 --- a/arch/blackfin/include/asm/l1layout.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Defines a layout of L1 scratchpad memory that userspace can rely on. - * - * Copyright 2006-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _L1LAYOUT_H_ -#define _L1LAYOUT_H_ - -#include - -#ifndef CONFIG_SMP -#ifndef __ASSEMBLY__ - -/* Data that is "mapped" into the process VM at the start of the L1 scratch - memory, so that each process can access it at a fixed address. Used for - stack checking. */ -struct l1_scratch_task_info -{ - /* Points to the start of the stack. */ - void *stack_start; - /* Not updated by the kernel; a user process can modify this to - keep track of the lowest address of the stack pointer during its - runtime. */ - void *lowest_sp; -}; - -/* A pointer to the structure in memory. */ -#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\ - get_l1_scratch_start()) - -#endif -#endif - -#endif diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h deleted file mode 100644 index f7d6d47a048d..000000000000 --- a/arch/blackfin/include/asm/linkage.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -#define __ALIGN .align 4 -#define __ALIGN_STR ".align 4" - -#endif diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h deleted file mode 100644 index c865b33eeb68..000000000000 --- a/arch/blackfin/include/asm/mem_init.h +++ /dev/null @@ -1,500 +0,0 @@ -/* - * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MEM_INIT_H__ -#define __MEM_INIT_H__ - -#if defined(EBIU_SDGCTL) -#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ - defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ - defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ - defined(CONFIG_MEM_MT48LC32M8A2_75) || \ - defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ - defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ - defined(CONFIG_MEM_MT48LC32M8A2_75) -#if (CONFIG_SCLK_HZ > 119402985) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_7 -#define SDRAM_tRAS_num 7 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_6 -#define SDRAM_tRAS_num 6 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_5 -#define SDRAM_tRAS_num 5 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 4 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_3 -#define SDRAM_tRAS_num 3 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 4 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_3 -#define SDRAM_tRAS_num 3 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_2 -#define SDRAM_tRAS_num 2 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ <= 29850746) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_1 -#define SDRAM_tRAS_num 1 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#endif - -/* - * The BF526-EZ-Board changed SDRAM chips between revisions, - * so we use below timings to accommodate both. - */ -#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) -#if (CONFIG_SCLK_HZ > 119402985) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_8 -#define SDRAM_tRAS_num 8 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_7 -#define SDRAM_tRAS_num 7 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_6 -#define SDRAM_tRAS_num 6 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_5 -#define SDRAM_tRAS_num 5 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 4 -#define SDRAM_tRCD TRCD_2 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_4 -#define SDRAM_tRAS_num 4 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) -#define SDRAM_tRP TRP_2 -#define SDRAM_tRP_num 2 -#define SDRAM_tRAS TRAS_3 -#define SDRAM_tRAS_num 3 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_3 -#define SDRAM_tRAS_num 3 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#if (CONFIG_SCLK_HZ <= 29850746) -#define SDRAM_tRP TRP_1 -#define SDRAM_tRP_num 1 -#define SDRAM_tRAS TRAS_2 -#define SDRAM_tRAS_num 2 -#define SDRAM_tRCD TRCD_1 -#define SDRAM_tWR TWR_2 -#endif -#endif - -#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ - defined(CONFIG_MEM_MT48LC8M32B2B5_7) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \ - defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ - defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ - defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ - defined(CONFIG_MEM_MT48LC32M8A2_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) - /*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_2 -#endif - - -#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC -/* Equation from section 17 (p17-46) of BF533 HRM */ -#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) - -/* Enable SCLK Out */ -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) -#else -#define mem_SDRRC CONFIG_MEM_SDRRC -#define mem_SDGCTL CONFIG_MEM_SDGCTL -#endif -#endif - - -#if defined(EBIU_DDRCTL0) -#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) -#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) -#define DDR_CLK_HZ(x) (1000*1000*1000/x) - -#if defined(CONFIG_MEM_MT46V32M16_6T) -#define DDR_SIZE DEVSZ_512 -#define DDR_WIDTH DEVWD_16 -#define DDR_MAX_tCK 13 - -#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) -#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) -#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) -#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) -#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) - -#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) -#define DDR_tWTR DDR_TWTR(1) -#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) -#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) -#endif - -#if defined(CONFIG_MEM_MT46V32M16_5B) -#define DDR_SIZE DEVSZ_512 -#define DDR_WIDTH DEVWD_16 -#define DDR_MAX_tCK 13 - -#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) -#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) -#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) -#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) -#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) - -#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) -#define DDR_tWTR DDR_TWTR(2) -#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) -#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) -#endif - -#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) -# error "CONFIG_SCLK_HZ is too small (133333333 Hz)." -#endif - -#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC -#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) -#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ - | DDR_tMRD | DDR_tWR | DDR_tRCD) -#define mem_DDRCTL2 DDR_CL -#else -#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0 -#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1 -#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2 -#endif -#endif - -#if defined CONFIG_CLKIN_HALF -#define CLKIN_HALF 1 -#else -#define CLKIN_HALF 0 -#endif - -#if defined CONFIG_PLL_BYPASS -#define PLL_BYPASS 1 -#else -#define PLL_BYPASS 0 -#endif - -#ifdef CONFIG_BF60x - -/* DMC status bits */ -#define IDLE 0x1 -#define MEMINITDONE 0x4 -#define SRACK 0x8 -#define PDACK 0x10 -#define DPDACK 0x20 -#define DLLCALDONE 0x2000 -#define PENDREF 0xF0000 -#define PHYRDPHASE 0xF00000 -#define PHYRDPHASE_OFFSET 20 - -/* DMC control bits */ -#define LPDDR 0x2 -#define INIT 0x4 -#define SRREQ 0x8 -#define PDREQ 0x10 -#define DPDREQ 0x20 -#define PREC 0x40 -#define ADDRMODE 0x100 -#define RDTOWR 0xE00 -#define PPREF 0x1000 -#define DLLCAL 0x2000 - -/* DMC DLL control bits */ -#define DLLCALRDCNT 0xFF -#define DATACYC 0xF00 -#define DATACYC_OFFSET 8 - -/* CGU Divisor bits */ -#define CSEL_OFFSET 0 -#define S0SEL_OFFSET 5 -#define SYSSEL_OFFSET 8 -#define S1SEL_OFFSET 13 -#define DSEL_OFFSET 16 -#define OSEL_OFFSET 22 -#define ALGN 0x20000000 -#define UPDT 0x40000000 -#define LOCK 0x80000000 - -/* CGU Status bits */ -#define PLLEN 0x1 -#define PLLBP 0x2 -#define PLOCK 0x4 -#define CLKSALGN 0x8 - -/* CGU Control bits */ -#define MSEL_MASK 0x7F00 -#define DF_MASK 0x1 - -struct ddr_config { - u32 ddr_clk; - u32 dmc_ddrctl; - u32 dmc_effctl; - u32 dmc_ddrcfg; - u32 dmc_ddrtr0; - u32 dmc_ddrtr1; - u32 dmc_ddrtr2; - u32 dmc_ddrmr; - u32 dmc_ddrmr1; -}; - -#if defined(CONFIG_MEM_MT47H64M16) -static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { - [0] = { - .ddr_clk = 125, - .dmc_ddrctl = 0x00000904, - .dmc_effctl = 0x004400C0, - .dmc_ddrcfg = 0x00000422, - .dmc_ddrtr0 = 0x20705212, - .dmc_ddrtr1 = 0x201003CF, - .dmc_ddrtr2 = 0x00320107, - .dmc_ddrmr = 0x00000422, - .dmc_ddrmr1 = 0x4, - }, - [1] = { - .ddr_clk = 133, - .dmc_ddrctl = 0x00000904, - .dmc_effctl = 0x004400C0, - .dmc_ddrcfg = 0x00000422, - .dmc_ddrtr0 = 0x20806313, - .dmc_ddrtr1 = 0x2013040D, - .dmc_ddrtr2 = 0x00320108, - .dmc_ddrmr = 0x00000632, - .dmc_ddrmr1 = 0x4, - }, - [2] = { - .ddr_clk = 150, - .dmc_ddrctl = 0x00000904, - .dmc_effctl = 0x004400C0, - .dmc_ddrcfg = 0x00000422, - .dmc_ddrtr0 = 0x20A07323, - .dmc_ddrtr1 = 0x20160492, - .dmc_ddrtr2 = 0x00320209, - .dmc_ddrmr = 0x00000632, - .dmc_ddrmr1 = 0x4, - }, - [3] = { - .ddr_clk = 166, - .dmc_ddrctl = 0x00000904, - .dmc_effctl = 0x004400C0, - .dmc_ddrcfg = 0x00000422, - .dmc_ddrtr0 = 0x20A07323, - .dmc_ddrtr1 = 0x2016050E, - .dmc_ddrtr2 = 0x00320209, - .dmc_ddrmr = 0x00000632, - .dmc_ddrmr1 = 0x4, - }, - [4] = { - .ddr_clk = 200, - .dmc_ddrctl = 0x00000904, - .dmc_effctl = 0x004400C0, - .dmc_ddrcfg = 0x00000422, - .dmc_ddrtr0 = 0x20a07323, - .dmc_ddrtr1 = 0x2016050f, - .dmc_ddrtr2 = 0x00320509, - .dmc_ddrmr = 0x00000632, - .dmc_ddrmr1 = 0x4, - }, - [5] = { - .ddr_clk = 225, - .dmc_ddrctl = 0x00000904, - .dmc_effctl = 0x004400C0, - .dmc_ddrcfg = 0x00000422, - .dmc_ddrtr0 = 0x20E0A424, - .dmc_ddrtr1 = 0x302006DB, - .dmc_ddrtr2 = 0x0032020D, - .dmc_ddrmr = 0x00000842, - .dmc_ddrmr1 = 0x4, - }, - [6] = { - .ddr_clk = 250, - .dmc_ddrctl = 0x00000904, - .dmc_effctl = 0x004400C0, - .dmc_ddrcfg = 0x00000422, - .dmc_ddrtr0 = 0x20E0A424, - .dmc_ddrtr1 = 0x3020079E, - .dmc_ddrtr2 = 0x0032050D, - .dmc_ddrmr = 0x00000842, - .dmc_ddrmr1 = 0x4, - }, -}; -#endif - -static inline void dmc_enter_self_refresh(void) -{ - if (bfin_read_DMC0_STAT() & MEMINITDONE) { - bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); - while (!(bfin_read_DMC0_STAT() & SRACK)) - continue; - } -} - -static inline void dmc_exit_self_refresh(void) -{ - if (bfin_read_DMC0_STAT() & MEMINITDONE) { - bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); - while (bfin_read_DMC0_STAT() & SRACK) - continue; - } -} - -static inline void init_cgu(u32 cgu_div, u32 cgu_ctl) -{ - dmc_enter_self_refresh(); - - /* Don't set the same value of MSEL and DF to CGU_CTL */ - if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) - != cgu_ctl) { - bfin_write32(CGU0_DIV, cgu_div); - bfin_write32(CGU0_CTL, cgu_ctl); - while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) || - !(bfin_read32(CGU0_STAT) & PLOCK)) - continue; - } - - bfin_write32(CGU0_DIV, cgu_div | UPDT); - while (bfin_read32(CGU0_STAT) & CLKSALGN) - continue; - - dmc_exit_self_refresh(); -} - -static inline void init_dmc(u32 dmc_clk) -{ - int i, dlldatacycle, dll_ctl; - - for (i = 0; i < 7; i++) { - if (ddr_config_table[i].ddr_clk == dmc_clk) { - bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); - bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); - bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); - bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); - bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); - bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); - bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl); - bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); - break; - } - } - - while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) - continue; - - dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET; - dll_ctl = bfin_read_DMC0_DLLCTL(); - dll_ctl &= ~DATACYC; - bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); - - while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) - continue; -} -#endif - -#endif /*__MEM_INIT_H__*/ - diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h deleted file mode 100644 index 5e21627c9ba2..000000000000 --- a/arch/blackfin/include/asm/mem_map.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Common Blackfin memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MEM_MAP_H__ -#define __BFIN_MEM_MAP_H__ - -#include - -/* Every Blackfin so far has MMRs like this */ -#ifndef COREMMR_BASE -# define COREMMR_BASE 0xFFE00000 -#endif -#ifndef SYSMMR_BASE -# define SYSMMR_BASE 0xFFC00000 -#endif - -/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ -#ifndef L1_SCRATCH_START -# define L1_SCRATCH_START 0xFFB00000 -# define L1_SCRATCH_LENGTH 0x1000 -#endif - -/* Most parts lack on-chip L2 SRAM */ -#ifndef L2_START -# define L2_START 0 -# define L2_LENGTH 0 -#endif - -/* Most parts lack on-chip L1 ROM */ -#ifndef L1_ROM_START -# define L1_ROM_START 0 -# define L1_ROM_LENGTH 0 -#endif - -/* Allow wonky SMP ports to override this */ -#ifndef GET_PDA_SAFE -# define GET_PDA_SAFE(preg) \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; -# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) - -# ifndef __ASSEMBLY__ - -static inline unsigned long get_l1_scratch_start_cpu(int cpu) -{ - return L1_SCRATCH_START; -} -static inline unsigned long get_l1_code_start_cpu(int cpu) -{ - return L1_CODE_START; -} -static inline unsigned long get_l1_data_a_start_cpu(int cpu) -{ - return L1_DATA_A_START; -} -static inline unsigned long get_l1_data_b_start_cpu(int cpu) -{ - return L1_DATA_B_START; -} -static inline unsigned long get_l1_scratch_start(void) -{ - return get_l1_scratch_start_cpu(0); -} -static inline unsigned long get_l1_code_start(void) -{ - return get_l1_code_start_cpu(0); -} -static inline unsigned long get_l1_data_a_start(void) -{ - return get_l1_data_a_start_cpu(0); -} -static inline unsigned long get_l1_data_b_start(void) -{ - return get_l1_data_b_start_cpu(0); -} - -# endif /* __ASSEMBLY__ */ -#endif /* !GET_PDA_SAFE */ - -#endif diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h deleted file mode 100644 index 26f6b70b11e2..000000000000 --- a/arch/blackfin/include/asm/mmu.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2002 David McCullough - * - * Licensed under the GPL-2. - */ - -#ifndef __MMU_H -#define __MMU_H - -struct sram_list_struct { - struct sram_list_struct *next; - void *addr; - size_t length; -}; - -typedef struct { - unsigned long end_brk; - unsigned long stack_start; - - /* Points to the location in SDRAM where the L1 stack is normally - saved, or NULL if the stack is always in SDRAM. */ - void *l1_stack_save; - - struct sram_list_struct *sram_list; - -#ifdef CONFIG_BINFMT_ELF_FDPIC - unsigned long exec_fdpic_loadmap; - unsigned long interp_fdpic_loadmap; -#endif -#ifdef CONFIG_MPU - unsigned long *page_rwx_mask; -#endif -} mm_context_t; - -#endif diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h deleted file mode 100644 index 0ce6de873b27..000000000000 --- a/arch/blackfin/include/asm/mmu_context.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BLACKFIN_MMU_CONTEXT_H__ -#define __BLACKFIN_MMU_CONTEXT_H__ - -#include -#include -#include - -#include -#include -#include -#include -#include - -/* Note: L1 stacks are CPU-private things, so we bluntly disable this - feature in SMP mode, and use the per-CPU scratch SRAM bank only to - store the PDA instead. */ - -extern void *current_l1_stack_save; -extern int nr_l1stack_tasks; -extern void *l1_stack_base; -extern unsigned long l1_stack_len; - -extern int l1sram_free(const void*); -extern void *l1sram_alloc_max(void*); - -static inline void free_l1stack(void) -{ - nr_l1stack_tasks--; - if (nr_l1stack_tasks == 0) { - l1sram_free(l1_stack_base); - l1_stack_base = NULL; - l1_stack_len = 0; - } -} - -static inline unsigned long -alloc_l1stack(unsigned long length, unsigned long *stack_base) -{ - if (nr_l1stack_tasks == 0) { - l1_stack_base = l1sram_alloc_max(&l1_stack_len); - if (!l1_stack_base) - return 0; - } - - if (l1_stack_len < length) { - if (nr_l1stack_tasks == 0) - l1sram_free(l1_stack_base); - return 0; - } - *stack_base = (unsigned long)l1_stack_base; - nr_l1stack_tasks++; - return l1_stack_len; -} - -static inline int -activate_l1stack(struct mm_struct *mm, unsigned long sp_base) -{ - if (current_l1_stack_save) - memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len); - mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base; - memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); - return 1; -} - -#define deactivate_mm(tsk,mm) do { } while (0) - -#define activate_mm(prev, next) switch_mm(prev, next, NULL) - -static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, - struct task_struct *tsk) -{ -#ifdef CONFIG_MPU - unsigned int cpu = smp_processor_id(); -#endif - if (prev_mm == next_mm) - return; -#ifdef CONFIG_MPU - if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) { - flush_switched_cplbs(cpu); - set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu); - } -#endif - -#ifdef CONFIG_APP_STACK_L1 - /* L1 stack switching. */ - if (!next_mm->context.l1_stack_save) - return; - if (next_mm->context.l1_stack_save == current_l1_stack_save) - return; - if (current_l1_stack_save) { - memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len); - } - current_l1_stack_save = next_mm->context.l1_stack_save; - memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); -#endif -} - -#ifdef CONFIG_IPIPE -#define lock_mm_switch(flags) flags = hard_local_irq_save_cond() -#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags) -#else -#define lock_mm_switch(flags) do { (void)(flags); } while (0) -#define unlock_mm_switch(flags) do { (void)(flags); } while (0) -#endif /* CONFIG_IPIPE */ - -#ifdef CONFIG_MPU -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - unsigned long flags; - lock_mm_switch(flags); - __switch_mm(prev, next, tsk); - unlock_mm_switch(flags); -} - -static inline void protect_page(struct mm_struct *mm, unsigned long addr, - unsigned long flags) -{ - unsigned long *mask = mm->context.page_rwx_mask; - unsigned long page; - unsigned long idx; - unsigned long bit; - - if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)) - page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12; - else - page = addr >> 12; - idx = page >> 5; - bit = 1 << (page & 31); - - if (flags & VM_READ) - mask[idx] |= bit; - else - mask[idx] &= ~bit; - mask += page_mask_nelts; - if (flags & VM_WRITE) - mask[idx] |= bit; - else - mask[idx] &= ~bit; - mask += page_mask_nelts; - if (flags & VM_EXEC) - mask[idx] |= bit; - else - mask[idx] &= ~bit; -} - -static inline void update_protections(struct mm_struct *mm) -{ - unsigned int cpu = smp_processor_id(); - if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) { - flush_switched_cplbs(cpu); - set_mask_dcplbs(mm->context.page_rwx_mask, cpu); - } -} -#else /* !CONFIG_MPU */ -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - __switch_mm(prev, next, tsk); -} -#endif - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -/* Called when creating a new context during fork() or execve(). */ -static inline int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ -#ifdef CONFIG_MPU - unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order); - mm->context.page_rwx_mask = (unsigned long *)p; - memset(mm->context.page_rwx_mask, 0, - page_mask_nelts * 3 * sizeof(long)); -#endif - return 0; -} - -static inline void destroy_context(struct mm_struct *mm) -{ - struct sram_list_struct *tmp; -#ifdef CONFIG_MPU - unsigned int cpu = smp_processor_id(); -#endif - -#ifdef CONFIG_APP_STACK_L1 - if (current_l1_stack_save == mm->context.l1_stack_save) - current_l1_stack_save = 0; - if (mm->context.l1_stack_save) - free_l1stack(); -#endif - - while ((tmp = mm->context.sram_list)) { - mm->context.sram_list = tmp->next; - sram_free(tmp->addr); - kfree(tmp); - } -#ifdef CONFIG_MPU - if (current_rwx_mask[cpu] == mm->context.page_rwx_mask) - current_rwx_mask[cpu] = NULL; - free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order); -#endif -} - -#define ipipe_mm_switch_protect(flags) \ - flags = hard_local_irq_save_cond() - -#define ipipe_mm_switch_unprotect(flags) \ - hard_local_irq_restore_cond(flags) - -#endif diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h deleted file mode 100644 index 231a149b3f77..000000000000 --- a/arch/blackfin/include/asm/module.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _ASM_BFIN_MODULE_H -#define _ASM_BFIN_MODULE_H - -#include - -struct mod_arch_specific { - Elf_Shdr *text_l1; - Elf_Shdr *data_a_l1; - Elf_Shdr *bss_a_l1; - Elf_Shdr *data_b_l1; - Elf_Shdr *bss_b_l1; - Elf_Shdr *text_l2; - Elf_Shdr *data_l2; - Elf_Shdr *bss_l2; -}; -#endif /* _ASM_BFIN_MODULE_H */ diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h deleted file mode 100644 index 256c50d8d465..000000000000 --- a/arch/blackfin/include/asm/nand.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * BF5XX - NAND flash controller platform_device info - * - * Copyright 2007-2008 Analog Devices, Inc. - * - * Licensed under the GPL-2 - */ - -/* struct bf5xx_nand_platform - * - * define a interface between platform board specific code and - * bf54x NFC driver. - * - * nr_partitions = number of partitions pointed to be partitoons (or zero) - * partitions = mtd partition list - */ - -#define NFC_PG_SIZE_OFFSET 9 - -#define NFC_NWIDTH_8 0 -#define NFC_NWIDTH_16 1 -#define NFC_NWIDTH_OFFSET 8 - -#define NFC_RDDLY_OFFSET 4 -#define NFC_WRDLY_OFFSET 0 - -#define NFC_STAT_NBUSY 1 - -struct bf5xx_nand_platform { - /* NAND chip information */ - unsigned short data_width; - - /* RD/WR strobe delay timing information, all times in SCLK cycles */ - unsigned short rd_dly; - unsigned short wr_dly; - - /* NAND MTD partition information */ - int nr_partitions; - struct mtd_partition *partitions; -}; diff --git a/arch/blackfin/include/asm/nmi.h b/arch/blackfin/include/asm/nmi.h deleted file mode 100644 index 107d23705f46..000000000000 --- a/arch/blackfin/include/asm/nmi.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2010 Analog Devices Inc. - * - * Licensed under the GPL-2 - */ - -#ifndef _BFIN_NMI_H_ -#define _BFIN_NMI_H_ - -#include - -extern void arch_touch_nmi_watchdog(void); - -#endif diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h deleted file mode 100644 index b93474d5be75..000000000000 --- a/arch/blackfin/include/asm/page.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_PAGE_H -#define _BLACKFIN_PAGE_H - -#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT) -#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT) - -#define VM_DATA_DEFAULT_FLAGS \ - (VM_READ | VM_WRITE | \ - ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#include -#include -#include - -#endif diff --git a/arch/blackfin/include/asm/page_offset.h b/arch/blackfin/include/asm/page_offset.h deleted file mode 100644 index d06a89b89d20..000000000000 --- a/arch/blackfin/include/asm/page_offset.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This handles the memory map - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifdef CONFIG_BLACKFIN -#define PAGE_OFFSET_RAW 0x00000000 -#endif diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h deleted file mode 100644 index e6458ddbaf7e..000000000000 --- a/arch/blackfin/include/asm/pci.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Changed from asm-m68k version, Lineo Inc. May 2001 */ - -#ifndef _ASM_BFIN_PCI_H -#define _ASM_BFIN_PCI_H - -#include -#include - -#define PCIBIOS_MIN_IO 0x00001000 -#define PCIBIOS_MIN_MEM 0x10000000 - -#endif /* _ASM_BFIN_PCI_H */ diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h deleted file mode 100644 index 68d6f6618f2a..000000000000 --- a/arch/blackfin/include/asm/pda.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * Philippe Gerum - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _ASM_BLACKFIN_PDA_H -#define _ASM_BLACKFIN_PDA_H - -#include - -#ifndef __ASSEMBLY__ - -struct blackfin_pda { /* Per-processor Data Area */ -#ifdef CONFIG_SMP - struct blackfin_pda *next; -#endif - - unsigned long syscfg; -#ifdef CONFIG_SMP - unsigned long imask; /* Current IMASK value */ -#endif - - unsigned long *ipdt; /* Start of switchable I-CPLB table */ - unsigned long *ipdt_swapcount; /* Number of swaps in ipdt */ - unsigned long *dpdt; /* Start of switchable D-CPLB table */ - unsigned long *dpdt_swapcount; /* Number of swaps in dpdt */ - - /* - * Single instructions can have multiple faults, which - * need to be handled by traps.c, in irq5. We store - * the exception cause to ensure we don't miss a - * double fault condition - */ - unsigned long ex_iptr; - unsigned long ex_optr; - unsigned long ex_buf[4]; - unsigned long ex_imask; /* Saved imask from exception */ - unsigned long ex_ipend; /* Saved IPEND from exception */ - unsigned long *ex_stack; /* Exception stack space */ - -#ifdef ANOMALY_05000261 - unsigned long last_cplb_fault_retx; -#endif - unsigned long dcplb_fault_addr; - unsigned long icplb_fault_addr; - unsigned long retx; - unsigned long seqstat; - unsigned int __nmi_count; /* number of times NMI asserted on this CPU */ -#ifdef CONFIG_DEBUG_DOUBLEFAULT - unsigned long dcplb_doublefault_addr; - unsigned long icplb_doublefault_addr; - unsigned long retx_doublefault; - unsigned long seqstat_doublefault; -#endif -}; - -struct blackfin_initial_pda { - void *retx; -#ifdef CONFIG_DEBUG_DOUBLEFAULT - void *dcplb_doublefault_addr; - void *icplb_doublefault_addr; - void *retx_doublefault; - unsigned seqstat_doublefault; -#endif -}; - -extern struct blackfin_pda cpu_pda[]; - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_BLACKFIN_PDA_H */ diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h deleted file mode 100644 index 3d2b1716322f..000000000000 --- a/arch/blackfin/include/asm/perf_event.h +++ /dev/null @@ -1 +0,0 @@ -#define MAX_HWEVENTS 2 diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h deleted file mode 100644 index c1ee3d6533fb..000000000000 --- a/arch/blackfin/include/asm/pgtable.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_PGTABLE_H -#define _BLACKFIN_PGTABLE_H - -#include - -#include -#include - -typedef pte_t *pte_addr_t; -/* -* Trivial page table functions. -*/ -#define pgd_present(pgd) (1) -#define pgd_none(pgd) (0) -#define pgd_bad(pgd) (0) -#define pgd_clear(pgdp) -#define kern_addr_valid(addr) (1) - -#define pmd_offset(a, b) ((void *)0) -#define pmd_none(x) (!pmd_val(x)) -#define pmd_present(x) (pmd_val(x)) -#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) -#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK) - -#define kern_addr_valid(addr) (1) - -#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */ -#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */ -#define pgprot_noncached(prot) (prot) - -extern void paging_init(void); - -#define __swp_type(x) (0) -#define __swp_offset(x) (0) -#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -#define set_pte(pteptr, pteval) (*(pteptr) = pteval) -#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) - -/* - * Page assess control based on Blackfin CPLB management - */ -#define _PAGE_RD (CPLB_USER_RD) -#define _PAGE_WR (CPLB_USER_WR) -#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR) -#define _PAGE_ACCESSED CPLB_ALL_ACCESS -#define _PAGE_DIRTY (CPLB_DIRTY) - -#define PTE_BIT_FUNC(fn, op) \ - static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; } - -PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD); -PTE_BIT_FUNC(mkread, |= _PAGE_RD); -PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR); -PTE_BIT_FUNC(mkwrite, |= _PAGE_WR); -PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER); -PTE_BIT_FUNC(mkexec, |= _PAGE_USER); -PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY); -PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY); -PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED); -PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED); - -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) -extern char empty_zero_page[]; - -#define swapper_pg_dir ((pgd_t *) 0) -/* - * No page table caches to initialise. - */ -#define pgtable_cache_init() do { } while (0) - -/* - * All 32bit addresses are effectively valid for vmalloc... - * Sort of meaningless for non-VM targets. - */ -#define VMALLOC_START 0 -#define VMALLOC_END 0xffffffff - -/* provide a special get_unmapped_area for framebuffer mmaps of nommu */ -extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, - unsigned long, unsigned long, - unsigned long); -#define HAVE_ARCH_FB_UNMAPPED_AREA - -#define pgprot_writecombine pgprot_noncached - -#include - -#endif /* _BLACKFIN_PGTABLE_H */ diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h deleted file mode 100644 index f72239bf3638..000000000000 --- a/arch/blackfin/include/asm/pm.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Blackfin bf609 power management - * - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 - */ - -#ifndef __PM_H__ -#define __PM_H__ - -#include - -struct bfin_cpu_pm_fns { - void (*save)(unsigned long *); - void (*restore)(unsigned long *); - int (*valid)(suspend_state_t state); - void (*enter)(suspend_state_t state); - int (*prepare)(void); - void (*finish)(void); -}; - -extern struct bfin_cpu_pm_fns *bfin_cpu_pm; - -# ifdef CONFIG_BFIN_COREB -void bfin_coreb_start(void); -void bfin_coreb_stop(void); -void bfin_coreb_reset(void); -# endif - -#endif diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h deleted file mode 100644 index c8f0939419be..000000000000 --- a/arch/blackfin/include/asm/portmux.h +++ /dev/null @@ -1,1204 +0,0 @@ -/* - * Common header file for Blackfin family of processors - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _PORTMUX_H_ -#define _PORTMUX_H_ - -#define P_IDENT(x) ((x) & 0x1FF) -#define P_FUNCT(x) (((x) & 0x3) << 9) -#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3) -#define P_DEFINED 0x8000 -#define P_UNDEF 0x4000 -#define P_MAYSHARE 0x2000 -#define P_DONTCARE 0x1000 - -#ifdef CONFIG_PINCTRL -int bfin_internal_set_wake(unsigned int irq, unsigned int state); - -#define gpio_pint_regs bfin_pint_regs -#define adi_internal_set_wake bfin_internal_set_wake - -#define peripheral_request(per, label) (0) -#define peripheral_free(per) -#define peripheral_request_list(per, label) (0) -#define peripheral_free_list(per) -#else -int peripheral_request(unsigned short per, const char *label); -void peripheral_free(unsigned short per); -int peripheral_request_list(const unsigned short per[], const char *label); -void peripheral_free_list(const unsigned short per[]); -#endif - -#include -#include -#include -#include - -#ifndef P_SPORT2_TFS -#define P_SPORT2_TFS P_UNDEF -#endif - -#ifndef P_SPORT2_DTSEC -#define P_SPORT2_DTSEC P_UNDEF -#endif - -#ifndef P_SPORT2_DTPRI -#define P_SPORT2_DTPRI P_UNDEF -#endif - -#ifndef P_SPORT2_TSCLK -#define P_SPORT2_TSCLK P_UNDEF -#endif - -#ifndef P_SPORT2_RFS -#define P_SPORT2_RFS P_UNDEF -#endif - -#ifndef P_SPORT2_DRSEC -#define P_SPORT2_DRSEC P_UNDEF -#endif - -#ifndef P_SPORT2_DRPRI -#define P_SPORT2_DRPRI P_UNDEF -#endif - -#ifndef P_SPORT2_RSCLK -#define P_SPORT2_RSCLK P_UNDEF -#endif - -#ifndef P_SPORT3_TFS -#define P_SPORT3_TFS P_UNDEF -#endif - -#ifndef P_SPORT3_DTSEC -#define P_SPORT3_DTSEC P_UNDEF -#endif - -#ifndef P_SPORT3_DTPRI -#define P_SPORT3_DTPRI P_UNDEF -#endif - -#ifndef P_SPORT3_TSCLK -#define P_SPORT3_TSCLK P_UNDEF -#endif - -#ifndef P_SPORT3_RFS -#define P_SPORT3_RFS P_UNDEF -#endif - -#ifndef P_SPORT3_DRSEC -#define P_SPORT3_DRSEC P_UNDEF -#endif - -#ifndef P_SPORT3_DRPRI -#define P_SPORT3_DRPRI P_UNDEF -#endif - -#ifndef P_SPORT3_RSCLK -#define P_SPORT3_RSCLK P_UNDEF -#endif - -#ifndef P_TMR4 -#define P_TMR4 P_UNDEF -#endif - -#ifndef P_TMR5 -#define P_TMR5 P_UNDEF -#endif - -#ifndef P_TMR6 -#define P_TMR6 P_UNDEF -#endif - -#ifndef P_TMR7 -#define P_TMR7 P_UNDEF -#endif - -#ifndef P_TWI1_SCL -#define P_TWI1_SCL P_UNDEF -#endif - -#ifndef P_TWI1_SDA -#define P_TWI1_SDA P_UNDEF -#endif - -#ifndef P_UART3_RTS -#define P_UART3_RTS P_UNDEF -#endif - -#ifndef P_UART3_CTS -#define P_UART3_CTS P_UNDEF -#endif - -#ifndef P_UART2_TX -#define P_UART2_TX P_UNDEF -#endif - -#ifndef P_UART2_RX -#define P_UART2_RX P_UNDEF -#endif - -#ifndef P_UART3_TX -#define P_UART3_TX P_UNDEF -#endif - -#ifndef P_UART3_RX -#define P_UART3_RX P_UNDEF -#endif - -#ifndef P_SPI2_SS -#define P_SPI2_SS P_UNDEF -#endif - -#ifndef P_SPI2_SSEL1 -#define P_SPI2_SSEL1 P_UNDEF -#endif - -#ifndef P_SPI2_SSEL2 -#define P_SPI2_SSEL2 P_UNDEF -#endif - -#ifndef P_SPI2_SSEL3 -#define P_SPI2_SSEL3 P_UNDEF -#endif - -#ifndef P_SPI2_SSEL4 -#define P_SPI2_SSEL4 P_UNDEF -#endif - -#ifndef P_SPI2_SSEL5 -#define P_SPI2_SSEL5 P_UNDEF -#endif - -#ifndef P_SPI2_SSEL6 -#define P_SPI2_SSEL6 P_UNDEF -#endif - -#ifndef P_SPI2_SSEL7 -#define P_SPI2_SSEL7 P_UNDEF -#endif - -#ifndef P_SPI2_SCK -#define P_SPI2_SCK P_UNDEF -#endif - -#ifndef P_SPI2_MOSI -#define P_SPI2_MOSI P_UNDEF -#endif - -#ifndef P_SPI2_MISO -#define P_SPI2_MISO P_UNDEF -#endif - -#ifndef P_TMR0 -#define P_TMR0 P_UNDEF -#endif - -#ifndef P_TMR1 -#define P_TMR1 P_UNDEF -#endif - -#ifndef P_TMR2 -#define P_TMR2 P_UNDEF -#endif - -#ifndef P_TMR3 -#define P_TMR3 P_UNDEF -#endif - -#ifndef P_SPORT0_TFS -#define P_SPORT0_TFS P_UNDEF -#endif - -#ifndef P_SPORT0_DTSEC -#define P_SPORT0_DTSEC P_UNDEF -#endif - -#ifndef P_SPORT0_DTPRI -#define P_SPORT0_DTPRI P_UNDEF -#endif - -#ifndef P_SPORT0_TSCLK -#define P_SPORT0_TSCLK P_UNDEF -#endif - -#ifndef P_SPORT0_RFS -#define P_SPORT0_RFS P_UNDEF -#endif - -#ifndef P_SPORT0_DRSEC -#define P_SPORT0_DRSEC P_UNDEF -#endif - -#ifndef P_SPORT0_DRPRI -#define P_SPORT0_DRPRI P_UNDEF -#endif - -#ifndef P_SPORT0_RSCLK -#define P_SPORT0_RSCLK P_UNDEF -#endif - -#ifndef P_SD_D0 -#define P_SD_D0 P_UNDEF -#endif - -#ifndef P_SD_D1 -#define P_SD_D1 P_UNDEF -#endif - -#ifndef P_SD_D2 -#define P_SD_D2 P_UNDEF -#endif - -#ifndef P_SD_D3 -#define P_SD_D3 P_UNDEF -#endif - -#ifndef P_SD_CLK -#define P_SD_CLK P_UNDEF -#endif - -#ifndef P_SD_CMD -#define P_SD_CMD P_UNDEF -#endif - -#ifndef P_MMCLK -#define P_MMCLK P_UNDEF -#endif - -#ifndef P_MBCLK -#define P_MBCLK P_UNDEF -#endif - -#ifndef P_PPI1_D0 -#define P_PPI1_D0 P_UNDEF -#endif - -#ifndef P_PPI1_D1 -#define P_PPI1_D1 P_UNDEF -#endif - -#ifndef P_PPI1_D2 -#define P_PPI1_D2 P_UNDEF -#endif - -#ifndef P_PPI1_D3 -#define P_PPI1_D3 P_UNDEF -#endif - -#ifndef P_PPI1_D4 -#define P_PPI1_D4 P_UNDEF -#endif - -#ifndef P_PPI1_D5 -#define P_PPI1_D5 P_UNDEF -#endif - -#ifndef P_PPI1_D6 -#define P_PPI1_D6 P_UNDEF -#endif - -#ifndef P_PPI1_D7 -#define P_PPI1_D7 P_UNDEF -#endif - -#ifndef P_PPI1_D8 -#define P_PPI1_D8 P_UNDEF -#endif - -#ifndef P_PPI1_D9 -#define P_PPI1_D9 P_UNDEF -#endif - -#ifndef P_PPI1_D10 -#define P_PPI1_D10 P_UNDEF -#endif - -#ifndef P_PPI1_D11 -#define P_PPI1_D11 P_UNDEF -#endif - -#ifndef P_PPI1_D12 -#define P_PPI1_D12 P_UNDEF -#endif - -#ifndef P_PPI1_D13 -#define P_PPI1_D13 P_UNDEF -#endif - -#ifndef P_PPI1_D14 -#define P_PPI1_D14 P_UNDEF -#endif - -#ifndef P_PPI1_D15 -#define P_PPI1_D15 P_UNDEF -#endif - -#ifndef P_HOST_D8 -#define P_HOST_D8 P_UNDEF -#endif - -#ifndef P_HOST_D9 -#define P_HOST_D9 P_UNDEF -#endif - -#ifndef P_HOST_D10 -#define P_HOST_D10 P_UNDEF -#endif - -#ifndef P_HOST_D11 -#define P_HOST_D11 P_UNDEF -#endif - -#ifndef P_HOST_D12 -#define P_HOST_D12 P_UNDEF -#endif - -#ifndef P_HOST_D13 -#define P_HOST_D13 P_UNDEF -#endif - -#ifndef P_HOST_D14 -#define P_HOST_D14 P_UNDEF -#endif - -#ifndef P_HOST_D15 -#define P_HOST_D15 P_UNDEF -#endif - -#ifndef P_HOST_D0 -#define P_HOST_D0 P_UNDEF -#endif - -#ifndef P_HOST_D1 -#define P_HOST_D1 P_UNDEF -#endif - -#ifndef P_HOST_D2 -#define P_HOST_D2 P_UNDEF -#endif - -#ifndef P_HOST_D3 -#define P_HOST_D3 P_UNDEF -#endif - -#ifndef P_HOST_D4 -#define P_HOST_D4 P_UNDEF -#endif - -#ifndef P_HOST_D5 -#define P_HOST_D5 P_UNDEF -#endif - -#ifndef P_HOST_D6 -#define P_HOST_D6 P_UNDEF -#endif - -#ifndef P_HOST_D7 -#define P_HOST_D7 P_UNDEF -#endif - -#ifndef P_SPORT1_TFS -#define P_SPORT1_TFS P_UNDEF -#endif - -#ifndef P_SPORT1_DTSEC -#define P_SPORT1_DTSEC P_UNDEF -#endif - -#ifndef P_SPORT1_DTPRI -#define P_SPORT1_DTPRI P_UNDEF -#endif - -#ifndef P_SPORT1_TSCLK -#define P_SPORT1_TSCLK P_UNDEF -#endif - -#ifndef P_SPORT1_RFS -#define P_SPORT1_RFS P_UNDEF -#endif - -#ifndef P_SPORT1_DRSEC -#define P_SPORT1_DRSEC P_UNDEF -#endif - -#ifndef P_SPORT1_DRPRI -#define P_SPORT1_DRPRI P_UNDEF -#endif - -#ifndef P_SPORT1_RSCLK -#define P_SPORT1_RSCLK P_UNDEF -#endif - -#ifndef P_PPI2_D0 -#define P_PPI2_D0 P_UNDEF -#endif - -#ifndef P_PPI2_D1 -#define P_PPI2_D1 P_UNDEF -#endif - -#ifndef P_PPI2_D2 -#define P_PPI2_D2 P_UNDEF -#endif - -#ifndef P_PPI2_D3 -#define P_PPI2_D3 P_UNDEF -#endif - -#ifndef P_PPI2_D4 -#define P_PPI2_D4 P_UNDEF -#endif - -#ifndef P_PPI2_D5 -#define P_PPI2_D5 P_UNDEF -#endif - -#ifndef P_PPI2_D6 -#define P_PPI2_D6 P_UNDEF -#endif - -#ifndef P_PPI2_D7 -#define P_PPI2_D7 P_UNDEF -#endif - -#ifndef P_PPI0_D18 -#define P_PPI0_D18 P_UNDEF -#endif - -#ifndef P_PPI0_D19 -#define P_PPI0_D19 P_UNDEF -#endif - -#ifndef P_PPI0_D20 -#define P_PPI0_D20 P_UNDEF -#endif - -#ifndef P_PPI0_D21 -#define P_PPI0_D21 P_UNDEF -#endif - -#ifndef P_PPI0_D22 -#define P_PPI0_D22 P_UNDEF -#endif - -#ifndef P_PPI0_D23 -#define P_PPI0_D23 P_UNDEF -#endif - -#ifndef P_KEY_ROW0 -#define P_KEY_ROW0 P_UNDEF -#endif - -#ifndef P_KEY_ROW1 -#define P_KEY_ROW1 P_UNDEF -#endif - -#ifndef P_KEY_ROW2 -#define P_KEY_ROW2 P_UNDEF -#endif - -#ifndef P_KEY_ROW3 -#define P_KEY_ROW3 P_UNDEF -#endif - -#ifndef P_KEY_COL0 -#define P_KEY_COL0 P_UNDEF -#endif - -#ifndef P_KEY_COL1 -#define P_KEY_COL1 P_UNDEF -#endif - -#ifndef P_KEY_COL2 -#define P_KEY_COL2 P_UNDEF -#endif - -#ifndef P_KEY_COL3 -#define P_KEY_COL3 P_UNDEF -#endif - -#ifndef P_SPI0_SCK -#define P_SPI0_SCK P_UNDEF -#endif - -#ifndef P_SPI0_MISO -#define P_SPI0_MISO P_UNDEF -#endif - -#ifndef P_SPI0_MOSI -#define P_SPI0_MOSI P_UNDEF -#endif - -#ifndef P_SPI0_SS -#define P_SPI0_SS P_UNDEF -#endif - -#ifndef P_SPI0_SSEL1 -#define P_SPI0_SSEL1 P_UNDEF -#endif - -#ifndef P_SPI0_SSEL2 -#define P_SPI0_SSEL2 P_UNDEF -#endif - -#ifndef P_SPI0_SSEL3 -#define P_SPI0_SSEL3 P_UNDEF -#endif - -#ifndef P_SPI0_SSEL4 -#define P_SPI0_SSEL4 P_UNDEF -#endif - -#ifndef P_SPI0_SSEL5 -#define P_SPI0_SSEL5 P_UNDEF -#endif - -#ifndef P_SPI0_SSEL6 -#define P_SPI0_SSEL6 P_UNDEF -#endif - -#ifndef P_SPI0_SSEL7 -#define P_SPI0_SSEL7 P_UNDEF -#endif - -#ifndef P_UART0_TX -#define P_UART0_TX P_UNDEF -#endif - -#ifndef P_UART0_RX -#define P_UART0_RX P_UNDEF -#endif - -#ifndef P_UART1_RTS -#define P_UART1_RTS P_UNDEF -#endif - -#ifndef P_UART1_CTS -#define P_UART1_CTS P_UNDEF -#endif - -#ifndef P_PPI1_CLK -#define P_PPI1_CLK P_UNDEF -#endif - -#ifndef P_PPI1_FS1 -#define P_PPI1_FS1 P_UNDEF -#endif - -#ifndef P_PPI1_FS2 -#define P_PPI1_FS2 P_UNDEF -#endif - -#ifndef P_TWI0_SCL -#define P_TWI0_SCL P_UNDEF -#endif - -#ifndef P_TWI0_SDA -#define P_TWI0_SDA P_UNDEF -#endif - -#ifndef P_KEY_COL7 -#define P_KEY_COL7 P_UNDEF -#endif - -#ifndef P_KEY_ROW6 -#define P_KEY_ROW6 P_UNDEF -#endif - -#ifndef P_KEY_COL6 -#define P_KEY_COL6 P_UNDEF -#endif - -#ifndef P_KEY_ROW5 -#define P_KEY_ROW5 P_UNDEF -#endif - -#ifndef P_KEY_COL5 -#define P_KEY_COL5 P_UNDEF -#endif - -#ifndef P_KEY_ROW4 -#define P_KEY_ROW4 P_UNDEF -#endif - -#ifndef P_KEY_COL4 -#define P_KEY_COL4 P_UNDEF -#endif - -#ifndef P_KEY_ROW7 -#define P_KEY_ROW7 P_UNDEF -#endif - -#ifndef P_PPI0_D0 -#define P_PPI0_D0 P_UNDEF -#endif - -#ifndef P_PPI0_D1 -#define P_PPI0_D1 P_UNDEF -#endif - -#ifndef P_PPI0_D2 -#define P_PPI0_D2 P_UNDEF -#endif - -#ifndef P_PPI0_D3 -#define P_PPI0_D3 P_UNDEF -#endif - -#ifndef P_PPI0_D4 -#define P_PPI0_D4 P_UNDEF -#endif - -#ifndef P_PPI0_D5 -#define P_PPI0_D5 P_UNDEF -#endif - -#ifndef P_PPI0_D6 -#define P_PPI0_D6 P_UNDEF -#endif - -#ifndef P_PPI0_D7 -#define P_PPI0_D7 P_UNDEF -#endif - -#ifndef P_PPI0_D8 -#define P_PPI0_D8 P_UNDEF -#endif - -#ifndef P_PPI0_D9 -#define P_PPI0_D9 P_UNDEF -#endif - -#ifndef P_PPI0_D10 -#define P_PPI0_D10 P_UNDEF -#endif - -#ifndef P_PPI0_D11 -#define P_PPI0_D11 P_UNDEF -#endif - -#ifndef P_PPI0_D12 -#define P_PPI0_D12 P_UNDEF -#endif - -#ifndef P_PPI0_D13 -#define P_PPI0_D13 P_UNDEF -#endif - -#ifndef P_PPI0_D14 -#define P_PPI0_D14 P_UNDEF -#endif - -#ifndef P_PPI0_D15 -#define P_PPI0_D15 P_UNDEF -#endif - -#ifndef P_ATAPI_D0A -#define P_ATAPI_D0A P_UNDEF -#endif - -#ifndef P_ATAPI_D1A -#define P_ATAPI_D1A P_UNDEF -#endif - -#ifndef P_ATAPI_D2A -#define P_ATAPI_D2A P_UNDEF -#endif - -#ifndef P_ATAPI_D3A -#define P_ATAPI_D3A P_UNDEF -#endif - -#ifndef P_ATAPI_D4A -#define P_ATAPI_D4A P_UNDEF -#endif - -#ifndef P_ATAPI_D5A -#define P_ATAPI_D5A P_UNDEF -#endif - -#ifndef P_ATAPI_D6A -#define P_ATAPI_D6A P_UNDEF -#endif - -#ifndef P_ATAPI_D7A -#define P_ATAPI_D7A P_UNDEF -#endif - -#ifndef P_ATAPI_D8A -#define P_ATAPI_D8A P_UNDEF -#endif - -#ifndef P_ATAPI_D9A -#define P_ATAPI_D9A P_UNDEF -#endif - -#ifndef P_ATAPI_D10A -#define P_ATAPI_D10A P_UNDEF -#endif - -#ifndef P_ATAPI_D11A -#define P_ATAPI_D11A P_UNDEF -#endif - -#ifndef P_ATAPI_D12A -#define P_ATAPI_D12A P_UNDEF -#endif - -#ifndef P_ATAPI_D13A -#define P_ATAPI_D13A P_UNDEF -#endif - -#ifndef P_ATAPI_D14A -#define P_ATAPI_D14A P_UNDEF -#endif - -#ifndef P_ATAPI_D15A -#define P_ATAPI_D15A P_UNDEF -#endif - -#ifndef P_PPI0_CLK -#define P_PPI0_CLK P_UNDEF -#endif - -#ifndef P_PPI0_FS1 -#define P_PPI0_FS1 P_UNDEF -#endif - -#ifndef P_PPI0_FS2 -#define P_PPI0_FS2 P_UNDEF -#endif - -#ifndef P_PPI0_D16 -#define P_PPI0_D16 P_UNDEF -#endif - -#ifndef P_PPI0_D17 -#define P_PPI0_D17 P_UNDEF -#endif - -#ifndef P_SPI1_SSEL1 -#define P_SPI1_SSEL1 P_UNDEF -#endif - -#ifndef P_SPI1_SSEL2 -#define P_SPI1_SSEL2 P_UNDEF -#endif - -#ifndef P_SPI1_SSEL3 -#define P_SPI1_SSEL3 P_UNDEF -#endif - - -#ifndef P_SPI1_SSEL4 -#define P_SPI1_SSEL4 P_UNDEF -#endif - -#ifndef P_SPI1_SSEL5 -#define P_SPI1_SSEL5 P_UNDEF -#endif - -#ifndef P_SPI1_SSEL6 -#define P_SPI1_SSEL6 P_UNDEF -#endif - -#ifndef P_SPI1_SSEL7 -#define P_SPI1_SSEL7 P_UNDEF -#endif - -#ifndef P_SPI1_SCK -#define P_SPI1_SCK P_UNDEF -#endif - -#ifndef P_SPI1_MISO -#define P_SPI1_MISO P_UNDEF -#endif - -#ifndef P_SPI1_MOSI -#define P_SPI1_MOSI P_UNDEF -#endif - -#ifndef P_SPI1_SS -#define P_SPI1_SS P_UNDEF -#endif - -#ifndef P_CAN0_TX -#define P_CAN0_TX P_UNDEF -#endif - -#ifndef P_CAN0_RX -#define P_CAN0_RX P_UNDEF -#endif - -#ifndef P_CAN1_TX -#define P_CAN1_TX P_UNDEF -#endif - -#ifndef P_CAN1_RX -#define P_CAN1_RX P_UNDEF -#endif - -#ifndef P_ATAPI_A0A -#define P_ATAPI_A0A P_UNDEF -#endif - -#ifndef P_ATAPI_A1A -#define P_ATAPI_A1A P_UNDEF -#endif - -#ifndef P_ATAPI_A2A -#define P_ATAPI_A2A P_UNDEF -#endif - -#ifndef P_HOST_CE -#define P_HOST_CE P_UNDEF -#endif - -#ifndef P_HOST_RD -#define P_HOST_RD P_UNDEF -#endif - -#ifndef P_HOST_WR -#define P_HOST_WR P_UNDEF -#endif - -#ifndef P_MTXONB -#define P_MTXONB P_UNDEF -#endif - -#ifndef P_PPI2_FS2 -#define P_PPI2_FS2 P_UNDEF -#endif - -#ifndef P_PPI2_FS1 -#define P_PPI2_FS1 P_UNDEF -#endif - -#ifndef P_PPI2_CLK -#define P_PPI2_CLK P_UNDEF -#endif - -#ifndef P_CNT_CZM -#define P_CNT_CZM P_UNDEF -#endif - -#ifndef P_UART1_TX -#define P_UART1_TX P_UNDEF -#endif - -#ifndef P_UART1_RX -#define P_UART1_RX P_UNDEF -#endif - -#ifndef P_ATAPI_RESET -#define P_ATAPI_RESET P_UNDEF -#endif - -#ifndef P_HOST_ADDR -#define P_HOST_ADDR P_UNDEF -#endif - -#ifndef P_HOST_ACK -#define P_HOST_ACK P_UNDEF -#endif - -#ifndef P_MTX -#define P_MTX P_UNDEF -#endif - -#ifndef P_MRX -#define P_MRX P_UNDEF -#endif - -#ifndef P_MRXONB -#define P_MRXONB P_UNDEF -#endif - -#ifndef P_A4 -#define P_A4 P_UNDEF -#endif - -#ifndef P_A5 -#define P_A5 P_UNDEF -#endif - -#ifndef P_A6 -#define P_A6 P_UNDEF -#endif - -#ifndef P_A7 -#define P_A7 P_UNDEF -#endif - -#ifndef P_A8 -#define P_A8 P_UNDEF -#endif - -#ifndef P_A9 -#define P_A9 P_UNDEF -#endif - -#ifndef P_PPI1_FS3 -#define P_PPI1_FS3 P_UNDEF -#endif - -#ifndef P_PPI2_FS3 -#define P_PPI2_FS3 P_UNDEF -#endif - -#ifndef P_TMR8 -#define P_TMR8 P_UNDEF -#endif - -#ifndef P_TMR9 -#define P_TMR9 P_UNDEF -#endif - -#ifndef P_TMR10 -#define P_TMR10 P_UNDEF -#endif -#ifndef P_TMR11 -#define P_TMR11 P_UNDEF -#endif - -#ifndef P_DMAR0 -#define P_DMAR0 P_UNDEF -#endif - -#ifndef P_DMAR1 -#define P_DMAR1 P_UNDEF -#endif - -#ifndef P_PPI0_FS3 -#define P_PPI0_FS3 P_UNDEF -#endif - -#ifndef P_CNT_CDG -#define P_CNT_CDG P_UNDEF -#endif - -#ifndef P_CNT_CUD -#define P_CNT_CUD P_UNDEF -#endif - -#ifndef P_A10 -#define P_A10 P_UNDEF -#endif - -#ifndef P_A11 -#define P_A11 P_UNDEF -#endif - -#ifndef P_A12 -#define P_A12 P_UNDEF -#endif - -#ifndef P_A13 -#define P_A13 P_UNDEF -#endif - -#ifndef P_A14 -#define P_A14 P_UNDEF -#endif - -#ifndef P_A15 -#define P_A15 P_UNDEF -#endif - -#ifndef P_A16 -#define P_A16 P_UNDEF -#endif - -#ifndef P_A17 -#define P_A17 P_UNDEF -#endif - -#ifndef P_A18 -#define P_A18 P_UNDEF -#endif - -#ifndef P_A19 -#define P_A19 P_UNDEF -#endif - -#ifndef P_A20 -#define P_A20 P_UNDEF -#endif - -#ifndef P_A21 -#define P_A21 P_UNDEF -#endif - -#ifndef P_A22 -#define P_A22 P_UNDEF -#endif - -#ifndef P_A23 -#define P_A23 P_UNDEF -#endif - -#ifndef P_A24 -#define P_A24 P_UNDEF -#endif - -#ifndef P_A25 -#define P_A25 P_UNDEF -#endif - -#ifndef P_NOR_CLK -#define P_NOR_CLK P_UNDEF -#endif - -#ifndef P_TMRCLK -#define P_TMRCLK P_UNDEF -#endif - -#ifndef P_AMC_ARDY_NOR_WAIT -#define P_AMC_ARDY_NOR_WAIT P_UNDEF -#endif - -#ifndef P_NAND_CE -#define P_NAND_CE P_UNDEF -#endif - -#ifndef P_NAND_RB -#define P_NAND_RB P_UNDEF -#endif - -#ifndef P_ATAPI_DIOR -#define P_ATAPI_DIOR P_UNDEF -#endif - -#ifndef P_ATAPI_DIOW -#define P_ATAPI_DIOW P_UNDEF -#endif - -#ifndef P_ATAPI_CS0 -#define P_ATAPI_CS0 P_UNDEF -#endif - -#ifndef P_ATAPI_CS1 -#define P_ATAPI_CS1 P_UNDEF -#endif - -#ifndef P_ATAPI_DMACK -#define P_ATAPI_DMACK P_UNDEF -#endif - -#ifndef P_ATAPI_DMARQ -#define P_ATAPI_DMARQ P_UNDEF -#endif - -#ifndef P_ATAPI_INTRQ -#define P_ATAPI_INTRQ P_UNDEF -#endif - -#ifndef P_ATAPI_IORDY -#define P_ATAPI_IORDY P_UNDEF -#endif - -#ifndef P_AMC_BR -#define P_AMC_BR P_UNDEF -#endif - -#ifndef P_AMC_BG -#define P_AMC_BG P_UNDEF -#endif - -#ifndef P_AMC_BGH -#define P_AMC_BGH P_UNDEF -#endif - -/* EMAC */ - -#ifndef P_MII0_ETxD0 -#define P_MII0_ETxD0 P_UNDEF -#endif - -#ifndef P_MII0_ETxD1 -#define P_MII0_ETxD1 P_UNDEF -#endif - -#ifndef P_MII0_ETxD2 -#define P_MII0_ETxD2 P_UNDEF -#endif - -#ifndef P_MII0_ETxD3 -#define P_MII0_ETxD3 P_UNDEF -#endif - -#ifndef P_MII0_ETxEN -#define P_MII0_ETxEN P_UNDEF -#endif - -#ifndef P_MII0_TxCLK -#define P_MII0_TxCLK P_UNDEF -#endif - -#ifndef P_MII0_PHYINT -#define P_MII0_PHYINT P_UNDEF -#endif - -#ifndef P_MII0_COL -#define P_MII0_COL P_UNDEF -#endif - -#ifndef P_MII0_ERxD0 -#define P_MII0_ERxD0 P_UNDEF -#endif - -#ifndef P_MII0_ERxD1 -#define P_MII0_ERxD1 P_UNDEF -#endif - -#ifndef P_MII0_ERxD2 -#define P_MII0_ERxD2 P_UNDEF -#endif - -#ifndef P_MII0_ERxD3 -#define P_MII0_ERxD3 P_UNDEF -#endif - -#ifndef P_MII0_ERxDV -#define P_MII0_ERxDV P_UNDEF -#endif - -#ifndef P_MII0_ERxCLK -#define P_MII0_ERxCLK P_UNDEF -#endif - -#ifndef P_MII0_ERxER -#define P_MII0_ERxER P_UNDEF -#endif - -#ifndef P_MII0_CRS -#define P_MII0_CRS P_UNDEF -#endif - -#ifndef P_RMII0_REF_CLK -#define P_RMII0_REF_CLK P_UNDEF -#endif - -#ifndef P_RMII0_MDINT -#define P_RMII0_MDINT P_UNDEF -#endif - -#ifndef P_RMII0_CRS_DV -#define P_RMII0_CRS_DV P_UNDEF -#endif - -#ifndef P_MDC -#define P_MDC P_UNDEF -#endif - -#ifndef P_MDIO -#define P_MDIO P_UNDEF -#endif - -#endif /* _PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h deleted file mode 100644 index dbdbb8a558df..000000000000 --- a/arch/blackfin/include/asm/processor.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_PROCESSOR_H -#define __ASM_BFIN_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#include -#include - -static inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp)); - return usp; -} - -static inline void wrusp(unsigned long usp) -{ - __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); -} - -static inline unsigned long __get_SP(void) -{ - unsigned long sp; - - __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp)); - return sp; -} - -/* - * User space process size: 1st byte beyond user address space. - * Fairly meaningless on nommu. Parts of user programs can be scattered - * in a lot of places, so just disable this by setting it to 0xFFFFFFFF. - */ -#define TASK_SIZE 0xFFFFFFFF - -#ifdef __KERNEL__ -#define STACK_TOP TASK_SIZE -#endif - -#define TASK_UNMAPPED_BASE 0 - -struct thread_struct { - unsigned long ksp; /* kernel stack pointer */ - unsigned long usp; /* user stack pointer */ - unsigned short seqstat; /* saved status register */ - unsigned long esp0; /* points to SR of stack frame pt_regs */ - unsigned long pc; /* instruction pointer */ - void * debuggerinfo; -}; - -#define INIT_THREAD { \ - sizeof(init_stack) + (unsigned long) init_stack, 0, \ - PS_S, 0, 0 \ -} - -extern void start_thread(struct pt_regs *regs, unsigned long new_ip, - unsigned long new_sp); - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -static inline void release_thread(struct task_struct *dead_task) -{ -} - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) \ - ({ \ - unsigned long eip = 0; \ - if ((tsk)->thread.esp0 > PAGE_SIZE && \ - MAP_NR((tsk)->thread.esp0) < max_mapnr) \ - eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ - eip; }) -#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) - -#define cpu_relax() smp_mb() - -/* Get the Silicon Revision of the chip */ -static inline uint32_t __pure bfin_revid(void) -{ - /* Always use CHIPID, to work around ANOMALY_05000234 */ - uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28; - -#ifdef _BOOTROM_GET_DXE_ADDRESS_TWI - /* - * ANOMALY_05000364 - * Incorrect Revision Number in DSPID Register - */ - if (ANOMALY_05000364 && - bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796) - revid = 1; -#endif - - return revid; -} - -static inline uint16_t __pure bfin_cpuid(void) -{ - return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12; -} - -static inline uint32_t __pure bfin_dspid(void) -{ - return bfin_read_DSPID(); -} - -#define blackfin_core_id() (bfin_dspid() & 0xff) - -static inline uint32_t __pure bfin_compiled_revid(void) -{ -#if defined(CONFIG_BF_REV_0_0) - return 0; -#elif defined(CONFIG_BF_REV_0_1) - return 1; -#elif defined(CONFIG_BF_REV_0_2) - return 2; -#elif defined(CONFIG_BF_REV_0_3) - return 3; -#elif defined(CONFIG_BF_REV_0_4) - return 4; -#elif defined(CONFIG_BF_REV_0_5) - return 5; -#elif defined(CONFIG_BF_REV_0_6) - return 6; -#elif defined(CONFIG_BF_REV_ANY) - return 0xffff; -#else - return -1; -#endif -} - -#endif diff --git a/arch/blackfin/include/asm/pseudo_instructions.h b/arch/blackfin/include/asm/pseudo_instructions.h deleted file mode 100644 index b00adfa08169..000000000000 --- a/arch/blackfin/include/asm/pseudo_instructions.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * header file for pseudo instructions - * - * Copyright 2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_PSEUDO_ -#define _BLACKFIN_PSEUDO_ - -#include -#include - -extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode); -extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode); - -#endif diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h deleted file mode 100644 index c00491594b46..000000000000 --- a/arch/blackfin/include/asm/ptrace.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ -#ifndef _BFIN_PTRACE_H -#define _BFIN_PTRACE_H - -#include - -#ifndef __ASSEMBLY__ - -/* user_mode returns true if only one bit is set in IPEND, other than the - master interrupt enable. */ -#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) - -#define arch_has_single_step() (1) -/* common code demands this function */ -#define ptrace_disable(child) user_disable_single_step(child) -#define current_user_stack_pointer() rdusp() - -extern int is_user_addr_valid(struct task_struct *child, - unsigned long start, unsigned long len); - -/* - * Get the address of the live pt_regs for the specified task. - * These are saved onto the top kernel stack when the process - * is not running. - * - * Note: if a user thread is execve'd from kernel space, the - * kernel stack will not be empty on entry to the kernel, so - * ptracing these tasks will fail. - */ -#define task_pt_regs(task) \ - (struct pt_regs *) \ - ((unsigned long)task_stack_page(task) + \ - (THREAD_SIZE - sizeof(struct pt_regs))) - -#include - -#endif /* __ASSEMBLY__ */ -#endif /* _BFIN_PTRACE_H */ diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h deleted file mode 100644 index ae1e36329bec..000000000000 --- a/arch/blackfin/include/asm/reboot.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * reboot.h - shutdown/reboot header - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_REBOOT_H__ -#define __ASM_REBOOT_H__ - -/* optional board specific hooks */ -extern void native_machine_restart(char *cmd); -extern void native_machine_halt(void); -extern void native_machine_power_off(void); - -/* common reboot workarounds */ -extern void bfin_reset_boot_spi_cs(unsigned short pin); - -#endif diff --git a/arch/blackfin/include/asm/rwlock.h b/arch/blackfin/include/asm/rwlock.h deleted file mode 100644 index 98ebc07cb283..000000000000 --- a/arch/blackfin/include/asm/rwlock.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_BLACKFIN_RWLOCK_H -#define _ASM_BLACKFIN_RWLOCK_H - -#define RW_LOCK_BIAS 0x01000000 - -#endif diff --git a/arch/blackfin/include/asm/scb.h b/arch/blackfin/include/asm/scb.h deleted file mode 100644 index a294cc0d1a4a..000000000000 --- a/arch/blackfin/include/asm/scb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority - * - * Copyright 2012 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#define SCB_SLOT_OFFSET 24 -#define SCB_MI_MAX_SLOT 32 - -struct scb_mi_prio { - unsigned long scb_mi_arbr; - unsigned long scb_mi_arbw; - unsigned char scb_mi_slots; - unsigned char scb_mi_prio[SCB_MI_MAX_SLOT]; -}; - -extern struct scb_mi_prio scb_data[]; - -extern void init_scb(void); diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h deleted file mode 100644 index fbd408475725..000000000000 --- a/arch/blackfin/include/asm/sections.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_SECTIONS_H -#define _BLACKFIN_SECTIONS_H - -/* only used when MTD_UCLINUX */ -extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; - -extern unsigned long _ramstart, _ramend, _rambase; -extern unsigned long memory_start, memory_end, physical_mem_end; - -/* - * The weak markings on the lengths might seem weird, but this is required - * in order to make gcc accept the fact that these may actually have a value - * of 0 (since they aren't actually addresses, but sizes of sections). - */ -extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[]; -extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[], - _data_l1_lma[], __weak _data_l1_len[]; -#ifdef CONFIG_ROMKERNEL -extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[]; -#endif -extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], - _data_b_l1_lma[], __weak _data_b_l1_len[]; -extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], - _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[]; - -#include - -/* Blackfin systems have discontinuous memory map and no virtualized memory */ -static inline int arch_is_kernel_text(unsigned long addr) -{ - return - (L1_CODE_LENGTH && - addr >= (unsigned long)_stext_l1 && - addr < (unsigned long)_etext_l1) - || - (L2_LENGTH && - addr >= (unsigned long)_stext_l2 && - addr < (unsigned long)_etext_l2); -} -#define arch_is_kernel_text(addr) arch_is_kernel_text(addr) - -static inline int arch_is_kernel_data(unsigned long addr) -{ - return - (L1_DATA_A_LENGTH && - addr >= (unsigned long)_sdata_l1 && - addr < (unsigned long)_ebss_l1) - || - (L1_DATA_B_LENGTH && - addr >= (unsigned long)_sdata_b_l1 && - addr < (unsigned long)_ebss_b_l1) - || - (L2_LENGTH && - addr >= (unsigned long)_sdata_l2 && - addr < (unsigned long)_ebss_l2); -} -#define arch_is_kernel_data(addr) arch_is_kernel_data(addr) - -#include - -#endif diff --git a/arch/blackfin/include/asm/segment.h b/arch/blackfin/include/asm/segment.h deleted file mode 100644 index f8e1984ffc7e..000000000000 --- a/arch/blackfin/include/asm/segment.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_SEGMENT_H -#define _BFIN_SEGMENT_H - -#define KERNEL_DS (0x5) -#define USER_DS (0x1) - -#endif /* _BFIN_SEGMENT_H */ diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h deleted file mode 100644 index 9631598dcc5d..000000000000 --- a/arch/blackfin/include/asm/smp.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * Philippe Gerum - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_SMP_H -#define __ASM_BLACKFIN_SMP_H - -#include -#include -#include -#include -#include -#include - -#define raw_smp_processor_id() blackfin_core_id() - -extern void bfin_relocate_coreb_l1_mem(void); -extern void arch_send_call_function_single_ipi(int cpu); -extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); - -#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1) -asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr); -extern unsigned long blackfin_iflush_l1_entry[NR_CPUS]; -#endif - -struct corelock_slot { - int lock; -}; -extern struct corelock_slot corelock; - -#ifdef __ARCH_SYNC_CORE_ICACHE -extern unsigned long icache_invld_count[NR_CPUS]; -#endif -#ifdef __ARCH_SYNC_CORE_DCACHE -extern unsigned long dcache_invld_count[NR_CPUS]; -#endif - -void smp_icache_flush_range_others(unsigned long start, - unsigned long end); -#ifdef CONFIG_HOTPLUG_CPU -void coreb_die(void); -void cpu_die(void); -void platform_cpu_die(void); -int __cpu_disable(void); -int __cpu_die(unsigned int cpu); -#endif - -void smp_timer_broadcast(const struct cpumask *mask); - - -#endif /* !__ASM_BLACKFIN_SMP_H */ diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h deleted file mode 100644 index 839d1441af3a..000000000000 --- a/arch/blackfin/include/asm/spinlock.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_SPINLOCK_H -#define __BFIN_SPINLOCK_H - -#ifndef CONFIG_SMP -# include -#else - -#include -#include -#include - -asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr); -asmlinkage void __raw_spin_lock_asm(volatile int *ptr); -asmlinkage int __raw_spin_trylock_asm(volatile int *ptr); -asmlinkage void __raw_spin_unlock_asm(volatile int *ptr); -asmlinkage void __raw_read_lock_asm(volatile int *ptr); -asmlinkage int __raw_read_trylock_asm(volatile int *ptr); -asmlinkage void __raw_read_unlock_asm(volatile int *ptr); -asmlinkage void __raw_write_lock_asm(volatile int *ptr); -asmlinkage int __raw_write_trylock_asm(volatile int *ptr); -asmlinkage void __raw_write_unlock_asm(volatile int *ptr); - -static inline int arch_spin_is_locked(arch_spinlock_t *lock) -{ - return __raw_spin_is_locked_asm(&lock->lock); -} - -static inline void arch_spin_lock(arch_spinlock_t *lock) -{ - __raw_spin_lock_asm(&lock->lock); -} - -static inline int arch_spin_trylock(arch_spinlock_t *lock) -{ - return __raw_spin_trylock_asm(&lock->lock); -} - -static inline void arch_spin_unlock(arch_spinlock_t *lock) -{ - __raw_spin_unlock_asm(&lock->lock); -} - -static inline void arch_read_lock(arch_rwlock_t *rw) -{ - __raw_read_lock_asm(&rw->lock); -} - -static inline int arch_read_trylock(arch_rwlock_t *rw) -{ - return __raw_read_trylock_asm(&rw->lock); -} - -static inline void arch_read_unlock(arch_rwlock_t *rw) -{ - __raw_read_unlock_asm(&rw->lock); -} - -static inline void arch_write_lock(arch_rwlock_t *rw) -{ - __raw_write_lock_asm(&rw->lock); -} - -static inline int arch_write_trylock(arch_rwlock_t *rw) -{ - return __raw_write_trylock_asm(&rw->lock); -} - -static inline void arch_write_unlock(arch_rwlock_t *rw) -{ - __raw_write_unlock_asm(&rw->lock); -} - -#endif - -#endif /* !__BFIN_SPINLOCK_H */ diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h deleted file mode 100644 index 1a33608c958b..000000000000 --- a/arch/blackfin/include/asm/spinlock_types.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_SPINLOCK_TYPES_H -#define __ASM_SPINLOCK_TYPES_H - -#ifndef __LINUX_SPINLOCK_TYPES_H -# error "please don't include this file directly" -#endif - -#include - -typedef struct { - volatile unsigned int lock; -} arch_spinlock_t; - -#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } - -typedef struct { - volatile unsigned int lock; -} arch_rwlock_t; - -#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } - -#endif diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h deleted file mode 100644 index 423c099aa988..000000000000 --- a/arch/blackfin/include/asm/string.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_STRING_H_ -#define _BLACKFIN_STRING_H_ - -#include - -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#define __HAVE_ARCH_STRCPY -extern char *strcpy(char *dest, const char *src); - -#define __HAVE_ARCH_STRNCPY -extern char *strncpy(char *dest, const char *src, size_t n); - -#define __HAVE_ARCH_STRCMP -extern int strcmp(const char *cs, const char *ct); - -#define __HAVE_ARCH_STRNCMP -extern int strncmp(const char *cs, const char *ct, size_t count); - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *s, int c, size_t count); -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *d, const void *s, size_t count); -#define __HAVE_ARCH_MEMCMP -extern int memcmp(const void *, const void *, __kernel_size_t); -#define __HAVE_ARCH_MEMCHR -extern void *memchr(const void *s, int c, size_t n); -#define __HAVE_ARCH_MEMMOVE -extern void *memmove(void *dest, const void *src, size_t count); - -#endif /*__KERNEL__*/ -#endif /* _BLACKFIN_STRING_H_ */ diff --git a/arch/blackfin/include/asm/switch_to.h b/arch/blackfin/include/asm/switch_to.h deleted file mode 100644 index aaf671be9242..000000000000 --- a/arch/blackfin/include/asm/switch_to.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * Tony Kou (tonyko@lineo.ca) - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BLACKFIN_SWITCH_TO_H -#define _BLACKFIN_SWITCH_TO_H - -#define prepare_to_switch() do { } while(0) - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. - */ - -#include -#include - -asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next); - -#ifndef CONFIG_SMP -#define switch_to(prev,next,last) \ -do { \ - memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \ - sizeof *L1_SCRATCH_TASK_INFO); \ - memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \ - sizeof *L1_SCRATCH_TASK_INFO); \ - (last) = resume (prev, next); \ -} while (0) -#else -#define switch_to(prev, next, last) \ -do { \ - (last) = resume(prev, next); \ -} while (0) -#endif - -#endif /* _BLACKFIN_SWITCH_TO_H */ diff --git a/arch/blackfin/include/asm/syscall.h b/arch/blackfin/include/asm/syscall.h deleted file mode 100644 index 4921a4815cce..000000000000 --- a/arch/blackfin/include/asm/syscall.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Magic syscall break down functions - * - * Copyright 2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_SYSCALL_H__ -#define __ASM_BLACKFIN_SYSCALL_H__ - -/* - * Blackfin syscalls are simple: - * enter: - * p0: syscall number - * r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5 - * exit: - * r0: return/error value - */ - -#include -#include -#include - -static inline long -syscall_get_nr(struct task_struct *task, struct pt_regs *regs) -{ - return regs->p0; -} - -static inline void -syscall_rollback(struct task_struct *task, struct pt_regs *regs) -{ - regs->p0 = regs->orig_p0; -} - -static inline long -syscall_get_error(struct task_struct *task, struct pt_regs *regs) -{ - return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0; -} - -static inline long -syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) -{ - return regs->r0; -} - -static inline void -syscall_set_return_value(struct task_struct *task, struct pt_regs *regs, - int error, long val) -{ - regs->r0 = error ? -error : val; -} - -/** - * syscall_get_arguments() - * @task: unused - * @regs: the register layout to extract syscall arguments from - * @i: first syscall argument to extract - * @n: number of syscall arguments to extract - * @args: array to return the syscall arguments in - * - * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument - */ -static inline void -syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, - unsigned int i, unsigned int n, unsigned long *args) -{ - /* - * Assume the ptrace layout doesn't change -- r5 is first in memory, - * then r4, ..., then r0. So we simply reverse the ptrace register - * array in memory to store into the args array. - */ - long *aregs = ®s->r0 - i; - - BUG_ON(i > 5 || i + n > 6); - - while (n--) - *args++ = *aregs--; -} - -/* See syscall_get_arguments() comments */ -static inline void -syscall_set_arguments(struct task_struct *task, struct pt_regs *regs, - unsigned int i, unsigned int n, const unsigned long *args) -{ - long *aregs = ®s->r0 - i; - - BUG_ON(i > 5 || i + n > 6); - - while (n--) - *aregs-- = *args++; -} - -#endif diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h deleted file mode 100644 index a5aeab4e5f2d..000000000000 --- a/arch/blackfin/include/asm/thread_info.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#include -#include -#include -#include - -#ifdef __KERNEL__ - -/* Thread Align Mask to reach to the top of the stack - * for any process - */ -#define ALIGN_PAGE_MASK 0xffffe000 - -/* - * Size of kernel stack for each process. This must be a power of 2... - */ -#define THREAD_SIZE_ORDER 1 -#define THREAD_SIZE 8192 /* 2 pages */ -#define STACK_WARN (THREAD_SIZE/8) - -#ifndef __ASSEMBLY__ - -typedef unsigned long mm_segment_t; - -/* - * low level task data. - * If you change this, change the TI_* offsets below to match. - */ - -struct thread_info { - struct task_struct *task; /* main task structure */ - unsigned long flags; /* low level flags */ - int cpu; /* cpu we're on */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - mm_segment_t addr_limit; /* address limit */ -#ifndef CONFIG_SMP - struct l1_scratch_task_info l1_task_info; -#endif -}; - -/* - * macros/functions for gaining access to the thread information structure - */ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = INIT_PREEMPT_COUNT, \ -} - -/* Given a task stack pointer, you can find its corresponding - * thread_info structure just by masking it to the THREAD_SIZE - * boundary (currently 8K as you can see above). - */ -__attribute_const__ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - __asm__("%0 = sp;" : "=da"(ti)); - return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1)); -} - -#endif /* __ASSEMBLY__ */ - -/* - * thread information flag bit numbers - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_MEMDIE 4 /* is terminating due to OOM killer */ -#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ -#define TIF_IRQ_SYNC 7 /* sync pipeline stage */ -#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */ -#define TIF_SINGLESTEP 9 - -/* as above, but as bit values */ -#define _TIF_SYSCALL_TRACE (1<mm) - -#include - -#endif /* _BLACKFIN_TLB_H */ diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h deleted file mode 100644 index 7c368682c0a3..000000000000 --- a/arch/blackfin/include/asm/tlbflush.h +++ /dev/null @@ -1,2 +0,0 @@ -#include -#define flush_tlb_kernel_range(s, e) do { } while (0) diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h deleted file mode 100644 index 33589a29b8d8..000000000000 --- a/arch/blackfin/include/asm/trace.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * header file for hardware trace functions - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_TRACE_ -#define _BLACKFIN_TRACE_ - -/* Normally, we use ON, but you can't turn on software expansion until - * interrupts subsystem is ready - */ - -#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03) -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND -#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2)) -#else -#define BFIN_TRACE_ON (BFIN_TRACE_INIT) -#endif - -#ifndef __ASSEMBLY__ -extern unsigned long trace_buff_offset; -extern unsigned long software_trace_buff[]; -#if defined(CONFIG_DEBUG_VERBOSE) -extern void decode_address(char *buf, unsigned long address); -extern bool get_instruction(unsigned int *val, unsigned short *address); -#else -static inline void decode_address(char *buf, unsigned long address) { } -static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; } -#endif - -/* Trace Macros for C files */ - -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - -#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT) - -#define trace_buffer_save(x) \ - do { \ - (x) = bfin_read_TBUFCTL(); \ - bfin_write_TBUFCTL((x) & ~TBUFEN); \ - } while (0) - -#define trace_buffer_restore(x) \ - do { \ - bfin_write_TBUFCTL((x)); \ - } while (0) -#else /* DEBUG_BFIN_HWTRACE_ON */ - -#define trace_buffer_save(x) -#define trace_buffer_restore(x) -#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ - -#else -/* Trace Macros for Assembly files */ - -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - -#define trace_buffer_stop(preg, dreg) \ - preg.L = LO(TBUFCTL); \ - preg.H = HI(TBUFCTL); \ - dreg = 0x1; \ - [preg] = dreg; - -#define trace_buffer_init(preg, dreg) \ - preg.L = LO(TBUFCTL); \ - preg.H = HI(TBUFCTL); \ - dreg = BFIN_TRACE_INIT; \ - [preg] = dreg; - -#define trace_buffer_save(preg, dreg) \ - preg.L = LO(TBUFCTL); \ - preg.H = HI(TBUFCTL); \ - dreg = [preg]; \ - [--sp] = dreg; \ - dreg = 0x1; \ - [preg] = dreg; - -#define trace_buffer_restore(preg, dreg) \ - preg.L = LO(TBUFCTL); \ - preg.H = HI(TBUFCTL); \ - dreg = [sp++]; \ - [preg] = dreg; - -#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ - -#define trace_buffer_stop(preg, dreg) -#define trace_buffer_init(preg, dreg) -#define trace_buffer_save(preg, dreg) -#define trace_buffer_restore(preg, dreg) - -#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ - -#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE -# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg) -# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg) -#else -# define DEBUG_HWTRACE_SAVE(preg, dreg) -# define DEBUG_HWTRACE_RESTORE(preg, dreg) -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* _BLACKFIN_TRACE_ */ diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h deleted file mode 100644 index cec771b8100c..000000000000 --- a/arch/blackfin/include/asm/traps.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2001 Lineo, Inc - * Tony Kou - * 1993 Hamish Macdonald - * - * Licensed under the GPL-2 - */ - -#ifndef _BFIN_TRAPS_H -#define _BFIN_TRAPS_H - -#define VEC_SYS (0) -#define VEC_EXCPT01 (1) -#define VEC_EXCPT02 (2) -#define VEC_EXCPT03 (3) -#define VEC_EXCPT04 (4) -#define VEC_EXCPT05 (5) -#define VEC_EXCPT06 (6) -#define VEC_EXCPT07 (7) -#define VEC_EXCPT08 (8) -#define VEC_EXCPT09 (9) -#define VEC_EXCPT10 (10) -#define VEC_EXCPT11 (11) -#define VEC_EXCPT12 (12) -#define VEC_EXCPT13 (13) -#define VEC_EXCPT14 (14) -#define VEC_EXCPT15 (15) -#define VEC_STEP (16) -#define VEC_OVFLOW (17) -#define VEC_UNDEF_I (33) -#define VEC_ILGAL_I (34) -#define VEC_CPLB_VL (35) -#define VEC_MISALI_D (36) -#define VEC_UNCOV (37) -#define VEC_CPLB_M (38) -#define VEC_CPLB_MHIT (39) -#define VEC_WATCH (40) -#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ -#define VEC_MISALI_I (42) -#define VEC_CPLB_I_VL (43) -#define VEC_CPLB_I_M (44) -#define VEC_CPLB_I_MHIT (45) -#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ -/* The hardware reserves (63) for future use - we use it to tell our - * normal exception handling code we have a hardware error - */ -#define VEC_HWERR (63) - -#ifndef __ASSEMBLY__ - -#define HWC_x2(level) \ - "System MMR Error\n" \ - level " - An error occurred due to an invalid access to an System MMR location\n" \ - level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \ - level " or a 16-bit register is accessed with a 32-bit instruction.\n" -#define HWC_x3(level) \ - "External Memory Addressing Error\n" -#define EXC_0x04(level) \ - "Unimplmented exception occurred\n" \ - level " - Maybe you forgot to install a custom exception handler?\n" -#define HWC_x12(level) \ - "Performance Monitor Overflow\n" -#define HWC_x18(level) \ - "RAISE 5 instruction\n" \ - level " Software issued a RAISE 5 instruction to invoke the Hardware\n" -#define HWC_default(level) \ - "Reserved\n" -#define EXC_0x03(level) \ - "Application stack overflow\n" \ - level " - Please increase the stack size of the application using elf2flt -s option,\n" \ - level " and/or reduce the stack use of the application.\n" -#define EXC_0x10(level) \ - "Single step\n" \ - level " - When the processor is in single step mode, every instruction\n" \ - level " generates an exception. Primarily used for debugging.\n" -#define EXC_0x11(level) \ - "Exception caused by a trace buffer full condition\n" \ - level " - The processor takes this exception when the trace\n" \ - level " buffer overflows (only when enabled by the Trace Unit Control register).\n" -#define EXC_0x21(level) \ - "Undefined instruction\n" \ - level " - May be used to emulate instructions that are not defined for\n" \ - level " a particular processor implementation.\n" -#define EXC_0x22(level) \ - "Illegal instruction combination\n" \ - level " - See section for multi-issue rules in the Blackfin\n" \ - level " Processor Instruction Set Reference.\n" -#define EXC_0x23(level) \ - "Data access CPLB protection violation\n" \ - level " - Attempted read or write to Supervisor resource,\n" \ - level " or illegal data memory access. \n" -#define EXC_0x24(level) \ - "Data access misaligned address violation\n" \ - level " - Attempted misaligned data memory or data cache access.\n" -#define EXC_0x25(level) \ - "Unrecoverable event\n" \ - level " - For example, an exception generated while processing a previous exception.\n" -#define EXC_0x26(level) \ - "Data access CPLB miss\n" \ - level " - Used by the MMU to signal a CPLB miss on a data access.\n" -#define EXC_0x27(level) \ - "Data access multiple CPLB hits\n" \ - level " - More than one CPLB entry matches data fetch address.\n" -#define EXC_0x28(level) \ - "Program Sequencer Exception caused by an emulation watchpoint match\n" \ - level " - There is a watchpoint match, and one of the EMUSW\n" \ - level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" -#define EXC_0x2A(level) \ - "Instruction fetch misaligned address violation\n" \ - level " - Attempted misaligned instruction cache fetch.\n" -#define EXC_0x2B(level) \ - "CPLB protection violation\n" \ - level " - Illegal instruction fetch access (memory protection violation).\n" -#define EXC_0x2C(level) \ - "Instruction fetch CPLB miss\n" \ - level " - CPLB miss on an instruction fetch.\n" -#define EXC_0x2D(level) \ - "Instruction fetch multiple CPLB hits\n" \ - level " - More than one CPLB entry matches instruction fetch address.\n" -#define EXC_0x2E(level) \ - "Illegal use of supervisor resource\n" \ - level " - Attempted to use a Supervisor register or instruction from User mode.\n" \ - level " Supervisor resources are registers and instructions that are reserved\n" \ - level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ - level " only instructions.\n" - -extern void double_fault_c(struct pt_regs *fp); - -#endif /* __ASSEMBLY__ */ -#endif /* _BFIN_TRAPS_H */ diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h deleted file mode 100644 index 45da4bcb050e..000000000000 --- a/arch/blackfin/include/asm/uaccess.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - * Based on: include/asm-m68knommu/uaccess.h - */ - -#ifndef __BLACKFIN_UACCESS_H -#define __BLACKFIN_UACCESS_H - -/* - * User space memory access functions - */ -#include -#include - -#include -#include - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) - -static inline void set_fs(mm_segment_t fs) -{ - current_thread_info()->addr_limit = fs; -} - -#define segment_eq(a, b) ((a) == (b)) - -#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size)) - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - */ - -#ifndef CONFIG_ACCESS_CHECK -static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; } -#else -extern int _access_ok(unsigned long addr, unsigned long size); -#endif - -#include - -/* - * These are the main single-value transfer routines. They automatically - * use the right size if we just have the right pointer type. - */ - -#define put_user(x, p) \ - ({ \ - int _err = 0; \ - typeof(*(p)) _x = (x); \ - typeof(*(p)) __user *_p = (p); \ - if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\ - _err = -EFAULT; \ - } \ - else { \ - switch (sizeof (*(_p))) { \ - case 1: \ - __put_user_asm(_x, _p, B); \ - break; \ - case 2: \ - __put_user_asm(_x, _p, W); \ - break; \ - case 4: \ - __put_user_asm(_x, _p, ); \ - break; \ - case 8: { \ - long _xl, _xh; \ - _xl = ((__force long *)&_x)[0]; \ - _xh = ((__force long *)&_x)[1]; \ - __put_user_asm(_xl, ((__force long __user *)_p)+0, );\ - __put_user_asm(_xh, ((__force long __user *)_p)+1, );\ - } break; \ - default: \ - _err = __put_user_bad(); \ - break; \ - } \ - } \ - _err; \ - }) - -#define __put_user(x, p) put_user(x, p) -static inline int bad_user_access_length(void) -{ - panic("bad_user_access_length"); - return -1; -} - -#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\ - __FILE__, __LINE__, __func__),\ - bad_user_access_length(), (-EFAULT)) - -/* - * Tell gcc we read from memory instead of writing: this is because - * we do not write to any memory gcc knows about, so there are no - * aliasing issues. - */ - -#define __ptr(x) ((unsigned long __force *)(x)) - -#define __put_user_asm(x, p, bhw) \ - __asm__ (#bhw"[%1] = %0;\n\t" \ - : /* no outputs */ \ - :"d" (x), "a" (__ptr(p)) : "memory") - -#define get_user(x, ptr) \ -({ \ - int _err = 0; \ - unsigned long _val = 0; \ - const typeof(*(ptr)) __user *_p = (ptr); \ - const size_t ptr_size = sizeof(*(_p)); \ - if (likely(access_ok(VERIFY_READ, _p, ptr_size))) { \ - BUILD_BUG_ON(ptr_size >= 8); \ - switch (ptr_size) { \ - case 1: \ - __get_user_asm(_val, _p, B, (Z)); \ - break; \ - case 2: \ - __get_user_asm(_val, _p, W, (Z)); \ - break; \ - case 4: \ - __get_user_asm(_val, _p, , ); \ - break; \ - } \ - } else \ - _err = -EFAULT; \ - x = (__force typeof(*(ptr)))_val; \ - _err; \ -}) - -#define __get_user(x, p) get_user(x, p) - -#define __get_user_bad() (bad_user_access_length(), (-EFAULT)) - -#define __get_user_asm(x, ptr, bhw, option) \ -({ \ - __asm__ __volatile__ ( \ - "%0 =" #bhw "[%1]" #option ";" \ - : "=d" (x) \ - : "a" (__ptr(ptr))); \ -}) - -static inline unsigned long __must_check -raw_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - memcpy(to, (const void __force *)from, n); - return 0; -} - -static inline unsigned long __must_check -raw_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - memcpy((void __force *)to, from, n); - SSYNC(); - return 0; -} - -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER -/* - * Copy a null terminated string from userspace. - */ - -static inline long __must_check -strncpy_from_user(char *dst, const char __user *src, long count) -{ - char *tmp; - if (!access_ok(VERIFY_READ, src, 1)) - return -EFAULT; - strncpy(dst, (const char __force *)src, count); - for (tmp = dst; *tmp && count > 0; tmp++, count--) ; - return (tmp - dst); -} - -/* - * Get the size of a string in user space. - * src: The string to measure - * n: The maximum valid length - * - * Get the size of a NUL-terminated string in user space. - * - * Returns the size of the string INCLUDING the terminating NUL. - * On exception, returns 0. - * If the string is too long, returns a value greater than n. - */ -static inline long __must_check strnlen_user(const char __user *src, long n) -{ - if (!access_ok(VERIFY_READ, src, 1)) - return 0; - return strnlen((const char __force *)src, n) + 1; -} - -/* - * Zero Userspace - */ - -static inline unsigned long __must_check -__clear_user(void __user *to, unsigned long n) -{ - if (!access_ok(VERIFY_WRITE, to, n)) - return n; - memset((void __force *)to, 0, n); - return 0; -} - -#define clear_user(to, n) __clear_user(to, n) - -/* How to interpret these return values: - * CORE: can be accessed by core load or dma memcpy - * CORE_ONLY: can only be accessed by core load - * DMA: can only be accessed by dma memcpy - * IDMA: can only be accessed by interprocessor dma memcpy (BF561) - * ITEST: can be accessed by isram memcpy or dma memcpy - */ -enum { - BFIN_MEM_ACCESS_CORE = 0, - BFIN_MEM_ACCESS_CORE_ONLY, - BFIN_MEM_ACCESS_DMA, - BFIN_MEM_ACCESS_IDMA, - BFIN_MEM_ACCESS_ITEST, -}; -/** - * bfin_mem_access_type() - what kind of memory access is required - * @addr: the address to check - * @size: number of bytes needed - * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above) - */ -int bfin_mem_access_type(unsigned long addr, unsigned long size); - -#endif /* _BLACKFIN_UACCESS_H */ diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h deleted file mode 100644 index c8c8ff9eff61..000000000000 --- a/arch/blackfin/include/asm/unistd.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ -#ifndef __ASM_BFIN_UNISTD_H -#define __ASM_BFIN_UNISTD_H - -#include - -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_TIME -#define __ARCH_WANT_SYS_FADVISE64 -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_VFORK - -#endif /* __ASM_BFIN_UNISTD_H */ diff --git a/arch/blackfin/include/asm/vga.h b/arch/blackfin/include/asm/vga.h deleted file mode 100644 index 89d82fd8fcf1..000000000000 --- a/arch/blackfin/include/asm/vga.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h deleted file mode 100644 index af9fc8171ebc..000000000000 --- a/arch/blackfin/include/mach-common/irq.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Common Blackfin IRQ definitions (i.e. the CEC) - * - * Copyright 2005-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_COMMON_IRQ_H_ -#define _MACH_COMMON_IRQ_H_ - -/* - * Core events interrupt source definitions - * - * Event Source Event Name - * Emulation EMU 0 (highest priority) - * Reset RST 1 - * NMI NMI 2 - * Exception EVX 3 - * Reserved -- 4 - * Hardware Error IVHW 5 - * Core Timer IVTMR 6 - * Peripherals IVG7 7 - * Peripherals IVG8 8 - * Peripherals IVG9 9 - * Peripherals IVG10 10 - * Peripherals IVG11 11 - * Peripherals IVG12 12 - * Peripherals IVG13 13 - * Softirq IVG14 14 - * System Call IVG15 15 (lowest priority) - */ - -/* The ABSTRACT IRQ definitions */ -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt */ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ - -#define IVG7 7 -#define IVG8 8 -#define IVG9 9 -#define IVG10 10 -#define IVG11 11 -#define IVG12 12 -#define IVG13 13 -#define IVG14 14 -#define IVG15 15 - -#define BFIN_IRQ(x) ((x) + IVG7) -#define BFIN_SYSIRQ(x) ((x) - IVG7) - -#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) - -#endif diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h deleted file mode 100644 index 382178b361af..000000000000 --- a/arch/blackfin/include/mach-common/pll.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_COMMON_PLL_H -#define _MACH_COMMON_PLL_H - -#ifndef __ASSEMBLY__ - -#include -#include - -#ifndef bfin_iwr_restore -static inline void -bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2) -{ -#ifdef SIC_IWR - bfin_write_SIC_IWR(iwr0); -#else - bfin_write_SIC_IWR0(iwr0); -# ifdef SIC_IWR1 - bfin_write_SIC_IWR1(iwr1); -# endif -# ifdef SIC_IWR2 - bfin_write_SIC_IWR2(iwr2); -# endif -#endif -} -#endif - -#ifndef bfin_iwr_save -static inline void -bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2, - unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) -{ -#ifdef SIC_IWR - *iwr0 = bfin_read_SIC_IWR(); -#else - *iwr0 = bfin_read_SIC_IWR0(); -# ifdef SIC_IWR1 - *iwr1 = bfin_read_SIC_IWR1(); -# endif -# ifdef SIC_IWR2 - *iwr2 = bfin_read_SIC_IWR2(); -# endif -#endif - bfin_iwr_restore(niwr0, niwr1, niwr2); -} -#endif - -static inline void _bfin_write_pll_relock(u32 addr, unsigned int val) -{ - unsigned long flags, iwr0, iwr1, iwr2; - - if (val == bfin_read_PLL_CTL()) - return; - - flags = hard_local_irq_save(); - /* Enable the PLL Wakeup bit in SIC IWR */ - bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2); - - bfin_write16(addr, val); - SSYNC(); - asm("IDLE;"); - - bfin_iwr_restore(iwr0, iwr1, iwr2); - hard_local_irq_restore(flags); -} - -/* Writing to PLL_CTL initiates a PLL relock sequence */ -static inline void bfin_write_PLL_CTL(unsigned int val) -{ - _bfin_write_pll_relock(PLL_CTL, val); -} - -/* Writing to VR_CTL initiates a PLL relock sequence */ -static inline void bfin_write_VR_CTL(unsigned int val) -{ - _bfin_write_pll_relock(VR_CTL, val); -} - -#endif - -#endif diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h deleted file mode 100644 index 71bcd74f83fd..000000000000 --- a/arch/blackfin/include/mach-common/ports-a.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port A Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_A__ -#define __BFIN_PERIPHERAL_PORT_A__ - -#define PA0 (1 << 0) -#define PA1 (1 << 1) -#define PA2 (1 << 2) -#define PA3 (1 << 3) -#define PA4 (1 << 4) -#define PA5 (1 << 5) -#define PA6 (1 << 6) -#define PA7 (1 << 7) -#define PA8 (1 << 8) -#define PA9 (1 << 9) -#define PA10 (1 << 10) -#define PA11 (1 << 11) -#define PA12 (1 << 12) -#define PA13 (1 << 13) -#define PA14 (1 << 14) -#define PA15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h deleted file mode 100644 index 8013cc8e839b..000000000000 --- a/arch/blackfin/include/mach-common/ports-b.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port B Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_B__ -#define __BFIN_PERIPHERAL_PORT_B__ - -#define PB0 (1 << 0) -#define PB1 (1 << 1) -#define PB2 (1 << 2) -#define PB3 (1 << 3) -#define PB4 (1 << 4) -#define PB5 (1 << 5) -#define PB6 (1 << 6) -#define PB7 (1 << 7) -#define PB8 (1 << 8) -#define PB9 (1 << 9) -#define PB10 (1 << 10) -#define PB11 (1 << 11) -#define PB12 (1 << 12) -#define PB13 (1 << 13) -#define PB14 (1 << 14) -#define PB15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h deleted file mode 100644 index 94e71010ffe9..000000000000 --- a/arch/blackfin/include/mach-common/ports-c.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port C Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_C__ -#define __BFIN_PERIPHERAL_PORT_C__ - -#define PC0 (1 << 0) -#define PC1 (1 << 1) -#define PC2 (1 << 2) -#define PC3 (1 << 3) -#define PC4 (1 << 4) -#define PC5 (1 << 5) -#define PC6 (1 << 6) -#define PC7 (1 << 7) -#define PC8 (1 << 8) -#define PC9 (1 << 9) -#define PC10 (1 << 10) -#define PC11 (1 << 11) -#define PC12 (1 << 12) -#define PC13 (1 << 13) -#define PC14 (1 << 14) -#define PC15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h deleted file mode 100644 index ba84a9fb3450..000000000000 --- a/arch/blackfin/include/mach-common/ports-d.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port D Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_D__ -#define __BFIN_PERIPHERAL_PORT_D__ - -#define PD0 (1 << 0) -#define PD1 (1 << 1) -#define PD2 (1 << 2) -#define PD3 (1 << 3) -#define PD4 (1 << 4) -#define PD5 (1 << 5) -#define PD6 (1 << 6) -#define PD7 (1 << 7) -#define PD8 (1 << 8) -#define PD9 (1 << 9) -#define PD10 (1 << 10) -#define PD11 (1 << 11) -#define PD12 (1 << 12) -#define PD13 (1 << 13) -#define PD14 (1 << 14) -#define PD15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h deleted file mode 100644 index 2264fb58bc2b..000000000000 --- a/arch/blackfin/include/mach-common/ports-e.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port E Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_E__ -#define __BFIN_PERIPHERAL_PORT_E__ - -#define PE0 (1 << 0) -#define PE1 (1 << 1) -#define PE2 (1 << 2) -#define PE3 (1 << 3) -#define PE4 (1 << 4) -#define PE5 (1 << 5) -#define PE6 (1 << 6) -#define PE7 (1 << 7) -#define PE8 (1 << 8) -#define PE9 (1 << 9) -#define PE10 (1 << 10) -#define PE11 (1 << 11) -#define PE12 (1 << 12) -#define PE13 (1 << 13) -#define PE14 (1 << 14) -#define PE15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h deleted file mode 100644 index 2b8ca3ae2a8e..000000000000 --- a/arch/blackfin/include/mach-common/ports-f.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port F Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_F__ -#define __BFIN_PERIPHERAL_PORT_F__ - -#define PF0 (1 << 0) -#define PF1 (1 << 1) -#define PF2 (1 << 2) -#define PF3 (1 << 3) -#define PF4 (1 << 4) -#define PF5 (1 << 5) -#define PF6 (1 << 6) -#define PF7 (1 << 7) -#define PF8 (1 << 8) -#define PF9 (1 << 9) -#define PF10 (1 << 10) -#define PF11 (1 << 11) -#define PF12 (1 << 12) -#define PF13 (1 << 13) -#define PF14 (1 << 14) -#define PF15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h deleted file mode 100644 index 11ad917fcf91..000000000000 --- a/arch/blackfin/include/mach-common/ports-g.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port G Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_G__ -#define __BFIN_PERIPHERAL_PORT_G__ - -#define PG0 (1 << 0) -#define PG1 (1 << 1) -#define PG2 (1 << 2) -#define PG3 (1 << 3) -#define PG4 (1 << 4) -#define PG5 (1 << 5) -#define PG6 (1 << 6) -#define PG7 (1 << 7) -#define PG8 (1 << 8) -#define PG9 (1 << 9) -#define PG10 (1 << 10) -#define PG11 (1 << 11) -#define PG12 (1 << 12) -#define PG13 (1 << 13) -#define PG14 (1 << 14) -#define PG15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h deleted file mode 100644 index 511d088b8094..000000000000 --- a/arch/blackfin/include/mach-common/ports-h.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port H Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_H__ -#define __BFIN_PERIPHERAL_PORT_H__ - -#define PH0 (1 << 0) -#define PH1 (1 << 1) -#define PH2 (1 << 2) -#define PH3 (1 << 3) -#define PH4 (1 << 4) -#define PH5 (1 << 5) -#define PH6 (1 << 6) -#define PH7 (1 << 7) -#define PH8 (1 << 8) -#define PH9 (1 << 9) -#define PH10 (1 << 10) -#define PH11 (1 << 11) -#define PH12 (1 << 12) -#define PH13 (1 << 13) -#define PH14 (1 << 14) -#define PH15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h deleted file mode 100644 index 21bbab166ae8..000000000000 --- a/arch/blackfin/include/mach-common/ports-i.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port I Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_I__ -#define __BFIN_PERIPHERAL_PORT_I__ - -#define PI0 (1 << 0) -#define PI1 (1 << 1) -#define PI2 (1 << 2) -#define PI3 (1 << 3) -#define PI4 (1 << 4) -#define PI5 (1 << 5) -#define PI6 (1 << 6) -#define PI7 (1 << 7) -#define PI8 (1 << 8) -#define PI9 (1 << 9) -#define PI10 (1 << 10) -#define PI11 (1 << 11) -#define PI12 (1 << 12) -#define PI13 (1 << 13) -#define PI14 (1 << 14) -#define PI15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h deleted file mode 100644 index 96a252b0b0bd..000000000000 --- a/arch/blackfin/include/mach-common/ports-j.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Port J Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_J__ -#define __BFIN_PERIPHERAL_PORT_J__ - -#define PJ0 (1 << 0) -#define PJ1 (1 << 1) -#define PJ2 (1 << 2) -#define PJ3 (1 << 3) -#define PJ4 (1 << 4) -#define PJ5 (1 << 5) -#define PJ6 (1 << 6) -#define PJ7 (1 << 7) -#define PJ8 (1 << 8) -#define PJ9 (1 << 9) -#define PJ10 (1 << 10) -#define PJ11 (1 << 11) -#define PJ12 (1 << 12) -#define PJ13 (1 << 13) -#define PJ14 (1 << 14) -#define PJ15 (1 << 15) - -#endif diff --git a/arch/blackfin/include/uapi/asm/Kbuild b/arch/blackfin/include/uapi/asm/Kbuild deleted file mode 100644 index 2240b38c2915..000000000000 --- a/arch/blackfin/include/uapi/asm/Kbuild +++ /dev/null @@ -1,25 +0,0 @@ -# UAPI Header export list -include include/uapi/asm-generic/Kbuild.asm - -generic-y += auxvec.h -generic-y += bitsperlong.h -generic-y += bpf_perf_event.h -generic-y += errno.h -generic-y += ioctl.h -generic-y += ipcbuf.h -generic-y += kvm_para.h -generic-y += mman.h -generic-y += msgbuf.h -generic-y += param.h -generic-y += resource.h -generic-y += sembuf.h -generic-y += setup.h -generic-y += shmbuf.h -generic-y += shmparam.h -generic-y += socket.h -generic-y += sockios.h -generic-y += statfs.h -generic-y += termbits.h -generic-y += termios.h -generic-y += types.h -generic-y += ucontext.h diff --git a/arch/blackfin/include/uapi/asm/bfin_sport.h b/arch/blackfin/include/uapi/asm/bfin_sport.h deleted file mode 100644 index 86c36a208dc5..000000000000 --- a/arch/blackfin/include/uapi/asm/bfin_sport.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * bfin_sport.h - interface to Blackfin SPORTs - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI__BFIN_SPORT_H__ -#define _UAPI__BFIN_SPORT_H__ - -/* Sport mode: it can be set to TDM, i2s or others */ -#define NORM_MODE 0x0 -#define TDM_MODE 0x1 -#define I2S_MODE 0x2 -#define NDSO_MODE 0x3 - -/* Data format, normal, a-law or u-law */ -#define NORM_FORMAT 0x0 -#define ALAW_FORMAT 0x2 -#define ULAW_FORMAT 0x3 - -/* Function driver which use sport must initialize the structure */ -struct sport_config { - /* TDM (multichannels), I2S or other mode */ - unsigned int mode:3; - unsigned int polled; /* use poll instead of irq when set */ - - /* if TDM mode is selected, channels must be set */ - int channels; /* Must be in 8 units */ - unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */ - - /* I2S mode */ - unsigned int right_first:1; /* Right stereo channel first */ - - /* In mormal mode, the following item need to be set */ - unsigned int lsb_first:1; /* order of transmit or receive data */ - unsigned int fsync:1; /* Frame sync required */ - unsigned int data_indep:1; /* data independent frame sync generated */ - unsigned int act_low:1; /* Active low TFS */ - unsigned int late_fsync:1; /* Late frame sync */ - unsigned int tckfe:1; - unsigned int sec_en:1; /* Secondary side enabled */ - - /* Choose clock source */ - unsigned int int_clk:1; /* Internal or external clock */ - - /* If external clock is used, the following fields are ignored */ - int serial_clk; - int fsync_clk; - - unsigned int data_format:2; /* Normal, u-law or a-law */ - - int word_len; /* How length of the word in bits, 3-32 bits */ - int dma_enabled; -}; - -/* Userspace interface */ -#define SPORT_IOC_MAGIC 'P' -#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) -#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long) -#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long) - - -/* SPORT_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define DTYPE_NORM 0x0000 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORT_TCR2 Masks */ -#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */ -#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x) -#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x) -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* TX Right-First Data Order */ - -/* SPORT_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -/* DTYPE_* defined above */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORT_RCR2 Masks */ -/* SLEN defined above */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORT_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORT_MCMC1 Masks */ -#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */ -#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x) -#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x) -#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */ -#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x) -#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x) - -/* SPORT_MCMC2 Masks */ -#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0xF000 /* Multichannel Frame Delay */ -#define DP_MFD(x) BFIN_DEPOSIT(MFD, x) -#define EX_MFD(x) BFIN_EXTRACT(MFD, x) - -#endif /* _UAPI__BFIN_SPORT_H__ */ diff --git a/arch/blackfin/include/uapi/asm/byteorder.h b/arch/blackfin/include/uapi/asm/byteorder.h deleted file mode 100644 index bcab6670c7fe..000000000000 --- a/arch/blackfin/include/uapi/asm/byteorder.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI__BFIN_ASM_BYTEORDER_H -#define _UAPI__BFIN_ASM_BYTEORDER_H - -#include - -#endif /* _UAPI__BFIN_ASM_BYTEORDER_H */ diff --git a/arch/blackfin/include/uapi/asm/cachectl.h b/arch/blackfin/include/uapi/asm/cachectl.h deleted file mode 100644 index b5c86fbbca94..000000000000 --- a/arch/blackfin/include/uapi/asm/cachectl.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * based on the mips/cachectl.h - * - * Copyright 2010 Analog Devices Inc. - * Copyright (C) 1994, 1995, 1996 by Ralf Baechle - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI_ASM_CACHECTL -#define _UAPI_ASM_CACHECTL - -/* - * Options for cacheflush system call - */ -#define ICACHE (1<<0) /* flush instruction cache */ -#define DCACHE (1<<1) /* writeback and flush data cache */ -#define BCACHE (ICACHE|DCACHE) /* flush both caches */ - -#endif /* _UAPI_ASM_CACHECTL */ diff --git a/arch/blackfin/include/uapi/asm/fcntl.h b/arch/blackfin/include/uapi/asm/fcntl.h deleted file mode 100644 index 0b02954f06c3..000000000000 --- a/arch/blackfin/include/uapi/asm/fcntl.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI_BFIN_FCNTL_H -#define _UAPI_BFIN_FCNTL_H - -#define O_DIRECTORY 040000 /* must be a directory */ -#define O_NOFOLLOW 0100000 /* don't follow links */ -#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */ -#define O_LARGEFILE 0400000 - -#include - -#endif /* _UAPI_BFIN_FCNTL_H */ diff --git a/arch/blackfin/include/uapi/asm/fixed_code.h b/arch/blackfin/include/uapi/asm/fixed_code.h deleted file mode 100644 index 707b9214bb26..000000000000 --- a/arch/blackfin/include/uapi/asm/fixed_code.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * This file defines the fixed addresses where userspace programs - * can find atomic code sequences. - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI__BFIN_ASM_FIXED_CODE_H__ -#define _UAPI__BFIN_ASM_FIXED_CODE_H__ - - -#ifndef CONFIG_PHY_RAM_BASE_ADDRESS -#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0 -#endif - -#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) - -#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) - -#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) - -#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) -#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420) -#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430) -#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440) -#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450) -#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460) -#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470) - -#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) - -#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) - -#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490) - -#endif /* _UAPI__BFIN_ASM_FIXED_CODE_H__ */ diff --git a/arch/blackfin/include/uapi/asm/ioctls.h b/arch/blackfin/include/uapi/asm/ioctls.h deleted file mode 100644 index 422fee3e4776..000000000000 --- a/arch/blackfin/include/uapi/asm/ioctls.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI__ARCH_BFIN_IOCTLS_H__ -#define _UAPI__ARCH_BFIN_IOCTLS_H__ - -#define FIOQSIZE 0x545E -#include - -#endif /* _UAPI__ARCH_BFIN_IOCTLS_H__ */ diff --git a/arch/blackfin/include/uapi/asm/poll.h b/arch/blackfin/include/uapi/asm/poll.h deleted file mode 100644 index cd2f1a78aba5..000000000000 --- a/arch/blackfin/include/uapi/asm/poll.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - */ - -#ifndef _UAPI__BFIN_POLL_H -#define _UAPI__BFIN_POLL_H - -#define POLLWRNORM POLLOUT -#define POLLWRBAND 256 - -#include - -#endif /* _UAPI__BFIN_POLL_H */ diff --git a/arch/blackfin/include/uapi/asm/posix_types.h b/arch/blackfin/include/uapi/asm/posix_types.h deleted file mode 100644 index 8947c75cf638..000000000000 --- a/arch/blackfin/include/uapi/asm/posix_types.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI__ARCH_BFIN_POSIX_TYPES_H -#define _UAPI__ARCH_BFIN_POSIX_TYPES_H - -typedef unsigned short __kernel_mode_t; -#define __kernel_mode_t __kernel_mode_t - -typedef unsigned int __kernel_ipc_pid_t; -#define __kernel_ipc_pid_t __kernel_ipc_pid_t - -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -#define __kernel_size_t __kernel_size_t - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -#define __kernel_old_uid_t __kernel_old_uid_t - -typedef unsigned short __kernel_old_dev_t; -#define __kernel_old_dev_t __kernel_old_dev_t - -#include - -#endif /* _UAPI__ARCH_BFIN_POSIX_TYPES_H */ diff --git a/arch/blackfin/include/uapi/asm/ptrace.h b/arch/blackfin/include/uapi/asm/ptrace.h deleted file mode 100644 index e4423d5560da..000000000000 --- a/arch/blackfin/include/uapi/asm/ptrace.h +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI_BFIN_PTRACE_H -#define _UAPI_BFIN_PTRACE_H - -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 7 are data registers R0-R7 - * 8 - 15 are address registers P0-P7 - * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 - * 32 - 33 A registers A0 & A1 - * 34 - status register - * ----------------------------- - * - * We follows above, except: - * 32-33 --- Low 32-bit of A0&1 - * 34-35 --- High 8-bit of A0&1 - */ - -#ifndef __ASSEMBLY__ - -struct task_struct; - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long orig_pc; - long ipend; - long seqstat; - long rete; - long retn; - long retx; - long pc; /* PC == RETI */ - long rets; - long reserved; /* Used as scratch during system calls */ - long astat; - long lb1; - long lb0; - long lt1; - long lt0; - long lc1; - long lc0; - long a1w; - long a1x; - long a0w; - long a0x; - long b3; - long b2; - long b1; - long b0; - long l3; - long l2; - long l1; - long l0; - long m3; - long m2; - long m1; - long m0; - long i3; - long i2; - long i1; - long i0; - long usp; - long fp; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - long r4; - long r3; - long r2; - long r1; - long r0; - long orig_r0; - long orig_p0; - long syscfg; -}; - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 /* ptrace signal */ - -#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ -#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ -#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ - -#define PS_S (0x0002) - - -#endif /* __ASSEMBLY__ */ - -/* - * Offsets used by 'ptrace' system call interface. - */ - -#define PT_R0 204 -#define PT_R1 200 -#define PT_R2 196 -#define PT_R3 192 -#define PT_R4 188 -#define PT_R5 184 -#define PT_R6 180 -#define PT_R7 176 -#define PT_P0 172 -#define PT_P1 168 -#define PT_P2 164 -#define PT_P3 160 -#define PT_P4 156 -#define PT_P5 152 -#define PT_FP 148 -#define PT_USP 144 -#define PT_I0 140 -#define PT_I1 136 -#define PT_I2 132 -#define PT_I3 128 -#define PT_M0 124 -#define PT_M1 120 -#define PT_M2 116 -#define PT_M3 112 -#define PT_L0 108 -#define PT_L1 104 -#define PT_L2 100 -#define PT_L3 96 -#define PT_B0 92 -#define PT_B1 88 -#define PT_B2 84 -#define PT_B3 80 -#define PT_A0X 76 -#define PT_A0W 72 -#define PT_A1X 68 -#define PT_A1W 64 -#define PT_LC0 60 -#define PT_LC1 56 -#define PT_LT0 52 -#define PT_LT1 48 -#define PT_LB0 44 -#define PT_LB1 40 -#define PT_ASTAT 36 -#define PT_RESERVED 32 -#define PT_RETS 28 -#define PT_PC 24 -#define PT_RETX 20 -#define PT_RETN 16 -#define PT_RETE 12 -#define PT_SEQSTAT 8 -#define PT_IPEND 4 - -#define PT_ORIG_R0 208 -#define PT_ORIG_P0 212 -#define PT_SYSCFG 216 -#define PT_TEXT_ADDR 220 -#define PT_TEXT_END_ADDR 224 -#define PT_DATA_ADDR 228 -#define PT_FDPIC_EXEC 232 -#define PT_FDPIC_INTERP 236 - -#define PT_LAST_PSEUDO PT_FDPIC_INTERP - -#endif /* _UAPI_BFIN_PTRACE_H */ diff --git a/arch/blackfin/include/uapi/asm/sigcontext.h b/arch/blackfin/include/uapi/asm/sigcontext.h deleted file mode 100644 index 66b4d32af89c..000000000000 --- a/arch/blackfin/include/uapi/asm/sigcontext.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI_ASM_BLACKFIN_SIGCONTEXT_H -#define _UAPI_ASM_BLACKFIN_SIGCONTEXT_H - -/* Add new entries at the end of the structure only. */ -struct sigcontext { - unsigned long sc_r0; - unsigned long sc_r1; - unsigned long sc_r2; - unsigned long sc_r3; - unsigned long sc_r4; - unsigned long sc_r5; - unsigned long sc_r6; - unsigned long sc_r7; - unsigned long sc_p0; - unsigned long sc_p1; - unsigned long sc_p2; - unsigned long sc_p3; - unsigned long sc_p4; - unsigned long sc_p5; - unsigned long sc_usp; - unsigned long sc_a0w; - unsigned long sc_a1w; - unsigned long sc_a0x; - unsigned long sc_a1x; - unsigned long sc_astat; - unsigned long sc_rets; - unsigned long sc_pc; - unsigned long sc_retx; - unsigned long sc_fp; - unsigned long sc_i0; - unsigned long sc_i1; - unsigned long sc_i2; - unsigned long sc_i3; - unsigned long sc_m0; - unsigned long sc_m1; - unsigned long sc_m2; - unsigned long sc_m3; - unsigned long sc_l0; - unsigned long sc_l1; - unsigned long sc_l2; - unsigned long sc_l3; - unsigned long sc_b0; - unsigned long sc_b1; - unsigned long sc_b2; - unsigned long sc_b3; - unsigned long sc_lc0; - unsigned long sc_lc1; - unsigned long sc_lt0; - unsigned long sc_lt1; - unsigned long sc_lb0; - unsigned long sc_lb1; - unsigned long sc_seqstat; -}; - -#endif /* _UAPI_ASM_BLACKFIN_SIGCONTEXT_H */ diff --git a/arch/blackfin/include/uapi/asm/siginfo.h b/arch/blackfin/include/uapi/asm/siginfo.h deleted file mode 100644 index 2dd8c9c39248..000000000000 --- a/arch/blackfin/include/uapi/asm/siginfo.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI_BFIN_SIGINFO_H -#define _UAPI_BFIN_SIGINFO_H - -#include -#include - -#define si_uid16 _sifields._kill._uid - -#endif /* _UAPI_BFIN_SIGINFO_H */ diff --git a/arch/blackfin/include/uapi/asm/signal.h b/arch/blackfin/include/uapi/asm/signal.h deleted file mode 100644 index f8e3b99ba0a2..000000000000 --- a/arch/blackfin/include/uapi/asm/signal.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_BLACKFIN_SIGNAL_H -#define _UAPI_BLACKFIN_SIGNAL_H - -#define SA_RESTORER 0x04000000 -#include - -#endif /* _UAPI_BLACKFIN_SIGNAL_H */ diff --git a/arch/blackfin/include/uapi/asm/stat.h b/arch/blackfin/include/uapi/asm/stat.h deleted file mode 100644 index 458959d1a5ec..000000000000 --- a/arch/blackfin/include/uapi/asm/stat.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * Copyright 2004-2006 Analog Devices Inc. - * - * Licensed under the GPL-2. - */ - -#ifndef _UAPI_BFIN_STAT_H -#define _UAPI_BFIN_STAT_H - -struct stat { - unsigned short st_dev; - unsigned short __pad1; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned short __pad2; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long __unused1; - unsigned long st_mtime; - unsigned long __unused2; - unsigned long st_ctime; - unsigned long __unused3; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad1[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad2[4]; - - long long st_size; - unsigned long st_blksize; - - long long st_blocks; /* Number 512-byte blocks allocated. */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; - - unsigned long long st_ino; -}; - -#endif /* _UAPI_BFIN_STAT_H */ diff --git a/arch/blackfin/include/uapi/asm/swab.h b/arch/blackfin/include/uapi/asm/swab.h deleted file mode 100644 index d3437933b95f..000000000000 --- a/arch/blackfin/include/uapi/asm/swab.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI_BLACKFIN_SWAB_H -#define _UAPI_BLACKFIN_SWAB_H - -#include -#include - -#ifdef __GNUC__ - -static __inline__ __attribute_const__ __u32 __arch_swahb32(__u32 xx) -{ - __u32 tmp; - __asm__("%1 = %0 >> 8 (V);\n\t" - "%0 = %0 << 8 (V);\n\t" - "%0 = %0 | %1;\n\t" - : "+d"(xx), "=&d"(tmp)); - return xx; -} -#define __arch_swahb32 __arch_swahb32 - -static __inline__ __attribute_const__ __u32 __arch_swahw32(__u32 xx) -{ - __u32 rv; - __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx)); - return rv; -} -#define __arch_swahw32 __arch_swahw32 - -static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 xx) -{ - return __arch_swahb32(__arch_swahw32(xx)); -} -#define __arch_swab32 __arch_swab32 - -static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx) -{ - __u32 xw = xx; - __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw)); - return (__u16)xw; -} -#define __arch_swab16 __arch_swab16 - -#endif /* __GNUC__ */ - -#endif /* _UAPI_BLACKFIN_SWAB_H */ diff --git a/arch/blackfin/include/uapi/asm/unistd.h b/arch/blackfin/include/uapi/asm/unistd.h deleted file mode 100644 index 2d392c09323c..000000000000 --- a/arch/blackfin/include/uapi/asm/unistd.h +++ /dev/null @@ -1,448 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _UAPI__ASM_BFIN_UNISTD_H -#define _UAPI__ASM_BFIN_UNISTD_H -/* - * This file contains the system call numbers. - */ -#define __NR_restart_syscall 0 -#define __NR_exit 1 - /* 2 __NR_fork not supported on nommu */ -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 - /* 7 __NR_waitpid obsolete */ -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_chown 16 - /* 17 __NR_break obsolete */ - /* 18 __NR_oldstat obsolete */ -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 - /* 22 __NR_umount obsolete */ -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 - /* 28 __NR_oldfstat obsolete */ -#define __NR_pause 29 - /* 30 __NR_utime obsolete */ - /* 31 __NR_stty obsolete */ - /* 32 __NR_gtty obsolete */ -#define __NR_access 33 -#define __NR_nice 34 - /* 35 __NR_ftime obsolete */ -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 - /* 44 __NR_prof obsolete */ -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 - /* 48 __NR_signal obsolete */ -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 - /* 53 __NR_lock obsolete */ -#define __NR_ioctl 54 -#define __NR_fcntl 55 - /* 56 __NR_mpx obsolete */ -#define __NR_setpgid 57 - /* 58 __NR_ulimit obsolete */ - /* 59 __NR_oldolduname obsolete */ -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 - /* 67 __NR_sigaction obsolete */ -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 - /* 72 __NR_sigsuspend obsolete */ - /* 73 __NR_sigpending obsolete */ -#define __NR_sethostname 74 -#define __NR_setrlimit 75 - /* 76 __NR_old_getrlimit obsolete */ -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 - /* 82 __NR_select obsolete */ -#define __NR_symlink 83 - /* 84 __NR_oldlstat obsolete */ -#define __NR_readlink 85 - /* 86 __NR_uselib obsolete */ - /* 87 __NR_swapon obsolete */ -#define __NR_reboot 88 - /* 89 __NR_readdir obsolete */ - /* 90 __NR_mmap obsolete */ -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 - /* 98 __NR_profil obsolete */ -#define __NR_statfs 99 -#define __NR_fstatfs 100 - /* 101 __NR_ioperm */ - /* 102 __NR_socketcall obsolete */ -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 - /* 109 __NR_olduname obsolete */ - /* 110 __NR_iopl obsolete */ -#define __NR_vhangup 111 - /* 112 __NR_idle obsolete */ - /* 113 __NR_vm86old */ -#define __NR_wait4 114 - /* 115 __NR_swapoff obsolete */ -#define __NR_sysinfo 116 - /* 117 __NR_ipc oboslete */ -#define __NR_fsync 118 - /* 119 __NR_sigreturn obsolete */ -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 - /* 123 __NR_modify_ldt obsolete */ -#define __NR_adjtimex 124 -#define __NR_mprotect 125 - /* 126 __NR_sigprocmask obsolete */ - /* 127 __NR_create_module obsolete */ -#define __NR_init_module 128 -#define __NR_delete_module 129 - /* 130 __NR_get_kernel_syms obsolete */ -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 - /* 135 was sysfs */ -#define __NR_personality 136 - /* 137 __NR_afs_syscall */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 - /* 142 __NR__newselect obsolete */ -#define __NR_flock 143 - /* 144 __NR_msync obsolete */ -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 - /* 150 __NR_mlock */ - /* 151 __NR_munlock */ - /* 152 __NR_mlockall */ - /* 153 __NR_munlockall */ -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 - /* 166 __NR_vm86 */ - /* 167 __NR_query_module */ - /* 168 __NR_poll */ -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread 180 -#define __NR_pwrite 181 -#define __NR_lchown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 - /* 188 __NR_getpmsg */ - /* 189 __NR_putpmsg */ -#define __NR_vfork 190 -#define __NR_getrlimit 191 -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_chown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_lchown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 - /* 218 __NR_mincore */ - /* 219 __NR_madvise */ -#define __NR_getdents64 220 -#define __NR_fcntl64 221 - /* 222 reserved for TUX */ - /* 223 reserved for TUX */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 - /* 243 __NR_set_thread_area */ - /* 244 __NR_get_thread_area */ -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 - /* 250 __NR_alloc_hugepages */ - /* 251 __NR_free_hugepages */ -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_bfin_spinlock 254 - -#define __NR_epoll_create 255 -#define __NR_epoll_ctl 256 -#define __NR_epoll_wait 257 - /* 258 __NR_remap_file_pages */ -#define __NR_set_tid_address 259 -#define __NR_timer_create 260 -#define __NR_timer_settime 261 -#define __NR_timer_gettime 262 -#define __NR_timer_getoverrun 263 -#define __NR_timer_delete 264 -#define __NR_clock_settime 265 -#define __NR_clock_gettime 266 -#define __NR_clock_getres 267 -#define __NR_clock_nanosleep 268 -#define __NR_statfs64 269 -#define __NR_fstatfs64 270 -#define __NR_tgkill 271 -#define __NR_utimes 272 -#define __NR_fadvise64_64 273 - /* 274 __NR_vserver */ - /* 275 __NR_mbind */ - /* 276 __NR_get_mempolicy */ - /* 277 __NR_set_mempolicy */ -#define __NR_mq_open 278 -#define __NR_mq_unlink 279 -#define __NR_mq_timedsend 280 -#define __NR_mq_timedreceive 281 -#define __NR_mq_notify 282 -#define __NR_mq_getsetattr 283 -#define __NR_kexec_load 284 -#define __NR_waitid 285 -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 - /* 294 __NR_migrate_pages */ -#define __NR_openat 295 -#define __NR_mkdirat 296 -#define __NR_mknodat 297 -#define __NR_fchownat 298 -#define __NR_futimesat 299 -#define __NR_fstatat64 300 -#define __NR_unlinkat 301 -#define __NR_renameat 302 -#define __NR_linkat 303 -#define __NR_symlinkat 304 -#define __NR_readlinkat 305 -#define __NR_fchmodat 306 -#define __NR_faccessat 307 -#define __NR_pselect6 308 -#define __NR_ppoll 309 -#define __NR_unshare 310 - -/* Blackfin private syscalls */ -#define __NR_sram_alloc 311 -#define __NR_sram_free 312 -#define __NR_dma_memcpy 313 - -/* socket syscalls */ -#define __NR_accept 314 -#define __NR_bind 315 -#define __NR_connect 316 -#define __NR_getpeername 317 -#define __NR_getsockname 318 -#define __NR_getsockopt 319 -#define __NR_listen 320 -#define __NR_recv 321 -#define __NR_recvfrom 322 -#define __NR_recvmsg 323 -#define __NR_send 324 -#define __NR_sendmsg 325 -#define __NR_sendto 326 -#define __NR_setsockopt 327 -#define __NR_shutdown 328 -#define __NR_socket 329 -#define __NR_socketpair 330 - -/* sysv ipc syscalls */ -#define __NR_semctl 331 -#define __NR_semget 332 -#define __NR_semop 333 -#define __NR_msgctl 334 -#define __NR_msgget 335 -#define __NR_msgrcv 336 -#define __NR_msgsnd 337 -#define __NR_shmat 338 -#define __NR_shmctl 339 -#define __NR_shmdt 340 -#define __NR_shmget 341 - -#define __NR_splice 342 -#define __NR_sync_file_range 343 -#define __NR_tee 344 -#define __NR_vmsplice 345 - -#define __NR_epoll_pwait 346 -#define __NR_utimensat 347 -#define __NR_signalfd 348 -#define __NR_timerfd_create 349 -#define __NR_eventfd 350 -#define __NR_pread64 351 -#define __NR_pwrite64 352 -#define __NR_fadvise64 353 -#define __NR_set_robust_list 354 -#define __NR_get_robust_list 355 -#define __NR_fallocate 356 -#define __NR_semtimedop 357 -#define __NR_timerfd_settime 358 -#define __NR_timerfd_gettime 359 -#define __NR_signalfd4 360 -#define __NR_eventfd2 361 -#define __NR_epoll_create1 362 -#define __NR_dup3 363 -#define __NR_pipe2 364 -#define __NR_inotify_init1 365 -#define __NR_preadv 366 -#define __NR_pwritev 367 -#define __NR_rt_tgsigqueueinfo 368 -#define __NR_perf_event_open 369 -#define __NR_recvmmsg 370 -#define __NR_fanotify_init 371 -#define __NR_fanotify_mark 372 -#define __NR_prlimit64 373 -#define __NR_cacheflush 374 -#define __NR_name_to_handle_at 375 -#define __NR_open_by_handle_at 376 -#define __NR_clock_adjtime 377 -#define __NR_syncfs 378 -#define __NR_setns 379 -#define __NR_sendmmsg 380 -#define __NR_process_vm_readv 381 -#define __NR_process_vm_writev 382 -#define __NR_kcmp 383 -#define __NR_finit_module 384 -#define __NR_sched_setattr 385 -#define __NR_sched_getattr 386 -#define __NR_renameat2 387 -#define __NR_seccomp 388 -#define __NR_getrandom 389 -#define __NR_memfd_create 390 -#define __NR_bpf 391 -#define __NR_execveat 392 - -#define __NR_syscall 393 /* For internal using, not implemented */ -#define NR_syscalls __NR_syscall - -/* Old optional stuff no one actually uses */ -#define __IGNORE_sysfs -#define __IGNORE_uselib - -/* Implement the newer interfaces */ -#define __IGNORE_mmap -#define __IGNORE_poll -#define __IGNORE_select -#define __IGNORE_utime - -/* Not relevant on no-mmu */ -#define __IGNORE_swapon -#define __IGNORE_swapoff -#define __IGNORE_msync -#define __IGNORE_mlock -#define __IGNORE_munlock -#define __IGNORE_mlockall -#define __IGNORE_munlockall -#define __IGNORE_mincore -#define __IGNORE_madvise -#define __IGNORE_remap_file_pages -#define __IGNORE_mbind -#define __IGNORE_get_mempolicy -#define __IGNORE_set_mempolicy -#define __IGNORE_migrate_pages -#define __IGNORE_move_pages -#define __IGNORE_getcpu - - -#endif /* _UAPI__ASM_BFIN_UNISTD_H */ diff --git a/arch/blackfin/kernel/.gitignore b/arch/blackfin/kernel/.gitignore deleted file mode 100644 index c5f676c3c224..000000000000 --- a/arch/blackfin/kernel/.gitignore +++ /dev/null @@ -1 +0,0 @@ -vmlinux.lds diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile deleted file mode 100644 index 1580791f0e3a..000000000000 --- a/arch/blackfin/kernel/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/kernel/Makefile -# - -extra-y := vmlinux.lds - -obj-y := \ - entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ - sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ - fixed_code.o reboot.o bfin_dma.o \ - exception.o dumpstack.o - -ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) - obj-y += time-ts.o -else - obj-y += time.o -endif - -obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o -obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o -obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o -obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o -CFLAGS_REMOVE_ftrace.o = -pg - -obj-$(CONFIG_IPIPE) += ipipe.o -obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o -obj-$(CONFIG_CPLB_INFO) += cplbinfo.o -obj-$(CONFIG_MODULES) += module.o -obj-$(CONFIG_KGDB) += kgdb.o -obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o -obj-$(CONFIG_NMI_WATCHDOG) += nmi.o -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o -obj-$(CONFIG_STACKTRACE) += stacktrace.o -obj-$(CONFIG_DEBUG_VERBOSE) += trace.o -obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o -obj-$(CONFIG_PERF_EVENTS) += perf_event.o - -# the kgdb test puts code into L2 and without linker -# relaxation, we need to force long calls to/from it -CFLAGS_kgdb_test.o := -mlong-calls - -obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c deleted file mode 100644 index 486560aea050..000000000000 --- a/arch/blackfin/kernel/asm-offsets.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * generate definitions needed by assembly language modules - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int main(void) -{ - /* offsets into the task struct */ - DEFINE(TASK_STATE, offsetof(struct task_struct, state)); - DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags)); - DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace)); - DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked)); - DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); - DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack)); - DEFINE(TASK_MM, offsetof(struct task_struct, mm)); - DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); - DEFINE(TASK_SIGPENDING, offsetof(struct task_struct, pending)); - - /* offsets into the irq_cpustat_t struct */ - DEFINE(CPUSTAT_SOFTIRQ_PENDING, - offsetof(irq_cpustat_t, __softirq_pending)); - - /* offsets into the thread struct */ - DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp)); - DEFINE(THREAD_USP, offsetof(struct thread_struct, usp)); - DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat)); - DEFINE(PT_SR, offsetof(struct thread_struct, seqstat)); - DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0)); - DEFINE(THREAD_PC, offsetof(struct thread_struct, pc)); - DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE); - - /* offsets in thread_info struct */ - OFFSET(TI_TASK, thread_info, task); - OFFSET(TI_FLAGS, thread_info, flags); - OFFSET(TI_CPU, thread_info, cpu); - OFFSET(TI_PREEMPT, thread_info, preempt_count); - - /* offsets into the pt_regs */ - DEFINE(PT_ORIG_R0, offsetof(struct pt_regs, orig_r0)); - DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0)); - DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc)); - DEFINE(PT_R0, offsetof(struct pt_regs, r0)); - DEFINE(PT_R1, offsetof(struct pt_regs, r1)); - DEFINE(PT_R2, offsetof(struct pt_regs, r2)); - DEFINE(PT_R3, offsetof(struct pt_regs, r3)); - DEFINE(PT_R4, offsetof(struct pt_regs, r4)); - DEFINE(PT_R5, offsetof(struct pt_regs, r5)); - DEFINE(PT_R6, offsetof(struct pt_regs, r6)); - DEFINE(PT_R7, offsetof(struct pt_regs, r7)); - - DEFINE(PT_P0, offsetof(struct pt_regs, p0)); - DEFINE(PT_P1, offsetof(struct pt_regs, p1)); - DEFINE(PT_P2, offsetof(struct pt_regs, p2)); - DEFINE(PT_P3, offsetof(struct pt_regs, p3)); - DEFINE(PT_P4, offsetof(struct pt_regs, p4)); - DEFINE(PT_P5, offsetof(struct pt_regs, p5)); - - DEFINE(PT_FP, offsetof(struct pt_regs, fp)); - DEFINE(PT_USP, offsetof(struct pt_regs, usp)); - DEFINE(PT_I0, offsetof(struct pt_regs, i0)); - DEFINE(PT_I1, offsetof(struct pt_regs, i1)); - DEFINE(PT_I2, offsetof(struct pt_regs, i2)); - DEFINE(PT_I3, offsetof(struct pt_regs, i3)); - DEFINE(PT_M0, offsetof(struct pt_regs, m0)); - DEFINE(PT_M1, offsetof(struct pt_regs, m1)); - DEFINE(PT_M2, offsetof(struct pt_regs, m2)); - DEFINE(PT_M3, offsetof(struct pt_regs, m3)); - DEFINE(PT_L0, offsetof(struct pt_regs, l0)); - DEFINE(PT_L1, offsetof(struct pt_regs, l1)); - DEFINE(PT_L2, offsetof(struct pt_regs, l2)); - DEFINE(PT_L3, offsetof(struct pt_regs, l3)); - DEFINE(PT_B0, offsetof(struct pt_regs, b0)); - DEFINE(PT_B1, offsetof(struct pt_regs, b1)); - DEFINE(PT_B2, offsetof(struct pt_regs, b2)); - DEFINE(PT_B3, offsetof(struct pt_regs, b3)); - DEFINE(PT_A0X, offsetof(struct pt_regs, a0x)); - DEFINE(PT_A0W, offsetof(struct pt_regs, a0w)); - DEFINE(PT_A1X, offsetof(struct pt_regs, a1x)); - DEFINE(PT_A1W, offsetof(struct pt_regs, a1w)); - DEFINE(PT_LC0, offsetof(struct pt_regs, lc0)); - DEFINE(PT_LC1, offsetof(struct pt_regs, lc1)); - DEFINE(PT_LT0, offsetof(struct pt_regs, lt0)); - DEFINE(PT_LT1, offsetof(struct pt_regs, lt1)); - DEFINE(PT_LB0, offsetof(struct pt_regs, lb0)); - DEFINE(PT_LB1, offsetof(struct pt_regs, lb1)); - DEFINE(PT_ASTAT, offsetof(struct pt_regs, astat)); - DEFINE(PT_RESERVED, offsetof(struct pt_regs, reserved)); - DEFINE(PT_RETS, offsetof(struct pt_regs, rets)); - DEFINE(PT_PC, offsetof(struct pt_regs, pc)); - DEFINE(PT_RETX, offsetof(struct pt_regs, retx)); - DEFINE(PT_RETN, offsetof(struct pt_regs, retn)); - DEFINE(PT_RETE, offsetof(struct pt_regs, rete)); - DEFINE(PT_SEQSTAT, offsetof(struct pt_regs, seqstat)); - DEFINE(PT_SYSCFG, offsetof(struct pt_regs, syscfg)); - DEFINE(PT_IPEND, offsetof(struct pt_regs, ipend)); - DEFINE(SIZEOF_PTREGS, sizeof(struct pt_regs)); - DEFINE(PT_TEXT_ADDR, sizeof(struct pt_regs)); /* Needed by gdb */ - DEFINE(PT_TEXT_END_ADDR, 4 + sizeof(struct pt_regs));/* Needed by gdb */ - DEFINE(PT_DATA_ADDR, 8 + sizeof(struct pt_regs)); /* Needed by gdb */ - DEFINE(PT_FDPIC_EXEC, 12 + sizeof(struct pt_regs)); /* Needed by gdb */ - DEFINE(PT_FDPIC_INTERP, 16 + sizeof(struct pt_regs));/* Needed by gdb */ - - /* signal defines */ - DEFINE(SIGSEGV, SIGSEGV); - DEFINE(SIGTRAP, SIGTRAP); - - /* PDA management (in L1 scratchpad) */ - DEFINE(PDA_SYSCFG, offsetof(struct blackfin_pda, syscfg)); -#ifdef CONFIG_SMP - DEFINE(PDA_IRQFLAGS, offsetof(struct blackfin_pda, imask)); -#endif - DEFINE(PDA_IPDT, offsetof(struct blackfin_pda, ipdt)); - DEFINE(PDA_IPDT_SWAPCOUNT, offsetof(struct blackfin_pda, ipdt_swapcount)); - DEFINE(PDA_DPDT, offsetof(struct blackfin_pda, dpdt)); - DEFINE(PDA_DPDT_SWAPCOUNT, offsetof(struct blackfin_pda, dpdt_swapcount)); - DEFINE(PDA_EXIPTR, offsetof(struct blackfin_pda, ex_iptr)); - DEFINE(PDA_EXOPTR, offsetof(struct blackfin_pda, ex_optr)); - DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf)); - DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask)); - DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack)); - DEFINE(PDA_EXIPEND, offsetof(struct blackfin_pda, ex_ipend)); -#ifdef ANOMALY_05000261 - DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx)); -#endif - DEFINE(PDA_DCPLB, offsetof(struct blackfin_pda, dcplb_fault_addr)); - DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr)); - DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx)); - DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat)); -#ifdef CONFIG_DEBUG_DOUBLEFAULT - DEFINE(PDA_DF_DCPLB, offsetof(struct blackfin_pda, dcplb_doublefault_addr)); - DEFINE(PDA_DF_ICPLB, offsetof(struct blackfin_pda, icplb_doublefault_addr)); - DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault)); - DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault)); -#endif - - /* PDA initial management */ - DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx)); -#ifdef CONFIG_DEBUG_DOUBLEFAULT - DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr)); - DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr)); - DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault)); - DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault)); -#endif - -#ifdef CONFIG_SMP - /* Inter-core lock (in L2 SRAM) */ - DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot)); -#endif - - return 0; -} diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c deleted file mode 100644 index 9d3eb0cf8ccc..000000000000 --- a/arch/blackfin/kernel/bfin_dma.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * bfin_dma.c - Blackfin DMA implementation - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * To make sure we work around 05000119 - we always check DMA_DONE bit, - * never the DMA_RUN bit - */ - -struct dma_channel dma_ch[MAX_DMA_CHANNELS]; -EXPORT_SYMBOL(dma_ch); - -static int __init blackfin_dma_init(void) -{ - int i; - - printk(KERN_INFO "Blackfin DMA Controller\n"); - - -#if ANOMALY_05000480 - bfin_write_DMAC_TC_PER(0x0111); -#endif - - for (i = 0; i < MAX_DMA_CHANNELS; i++) { - atomic_set(&dma_ch[i].chan_status, 0); - dma_ch[i].regs = dma_io_base_addr[i]; - } -#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x) - /* Mark MEMDMA Channel 3 as requested since we're using it internally */ - request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy"); - request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy"); -#else - /* Mark MEMDMA Channel 0 as requested since we're using it internally */ - request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); - request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy"); -#endif - -#if defined(CONFIG_DEB_DMA_URGENT) - bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() - | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT); -#endif - - return 0; -} -arch_initcall(blackfin_dma_init); - -#ifdef CONFIG_PROC_FS -static int proc_dma_show(struct seq_file *m, void *v) -{ - int i; - - for (i = 0; i < MAX_DMA_CHANNELS; ++i) - if (dma_channel_active(i)) - seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); - - return 0; -} - -static int proc_dma_open(struct inode *inode, struct file *file) -{ - return single_open(file, proc_dma_show, NULL); -} - -static const struct file_operations proc_dma_operations = { - .open = proc_dma_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init proc_dma_init(void) -{ - proc_create("dma", 0, NULL, &proc_dma_operations); - return 0; -} -late_initcall(proc_dma_init); -#endif - -static void set_dma_peripheral_map(unsigned int channel, const char *device_id) -{ -#ifdef CONFIG_BF54x - unsigned int per_map; - - switch (channel) { - case CH_UART2_RX: per_map = 0xC << 12; break; - case CH_UART2_TX: per_map = 0xD << 12; break; - case CH_UART3_RX: per_map = 0xE << 12; break; - case CH_UART3_TX: per_map = 0xF << 12; break; - default: return; - } - - if (strncmp(device_id, "BFIN_UART", 9) == 0) - dma_ch[channel].regs->peripheral_map = per_map; -#endif -} - -/** - * request_dma - request a DMA channel - * - * Request the specific DMA channel from the system if it's available. - */ -int request_dma(unsigned int channel, const char *device_id) -{ - pr_debug("request_dma() : BEGIN\n"); - - if (device_id == NULL) - printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel); - -#if defined(CONFIG_BF561) && ANOMALY_05000182 - if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) { - if (get_cclk() > 500000000) { - printk(KERN_WARNING - "Request IMDMA failed due to ANOMALY 05000182\n"); - return -EFAULT; - } - } -#endif - - if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) { - pr_debug("DMA CHANNEL IN USE\n"); - return -EBUSY; - } - - set_dma_peripheral_map(channel, device_id); - dma_ch[channel].device_id = device_id; - dma_ch[channel].irq = 0; - - /* This is to be enabled by putting a restriction - - * you have to request DMA, before doing any operations on - * descriptor/channel - */ - pr_debug("request_dma() : END\n"); - return 0; -} -EXPORT_SYMBOL(request_dma); - -int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) -{ - int ret; - unsigned int irq; - - BUG_ON(channel >= MAX_DMA_CHANNELS || !callback || - !atomic_read(&dma_ch[channel].chan_status)); - - irq = channel2irq(channel); - ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data); - if (ret) - return ret; - - dma_ch[channel].irq = irq; - dma_ch[channel].data = data; - - return 0; -} -EXPORT_SYMBOL(set_dma_callback); - -/** - * clear_dma_buffer - clear DMA fifos for specified channel - * - * Set the Buffer Clear bit in the Configuration register of specific DMA - * channel. This will stop the descriptor based DMA operation. - */ -static void clear_dma_buffer(unsigned int channel) -{ - dma_ch[channel].regs->cfg |= RESTART; - SSYNC(); - dma_ch[channel].regs->cfg &= ~RESTART; -} - -void free_dma(unsigned int channel) -{ - pr_debug("freedma() : BEGIN\n"); - BUG_ON(channel >= MAX_DMA_CHANNELS || - !atomic_read(&dma_ch[channel].chan_status)); - - /* Halt the DMA */ - disable_dma(channel); - clear_dma_buffer(channel); - - if (dma_ch[channel].irq) - free_irq(dma_ch[channel].irq, dma_ch[channel].data); - - /* Clear the DMA Variable in the Channel */ - atomic_set(&dma_ch[channel].chan_status, 0); - - pr_debug("freedma() : END\n"); -} -EXPORT_SYMBOL(free_dma); - -#ifdef CONFIG_PM -# ifndef MAX_DMA_SUSPEND_CHANNELS -# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS -# endif -# ifndef CONFIG_BF60x -int blackfin_dma_suspend(void) -{ - int i; - - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - if (dma_ch[i].regs->cfg & DMAEN) { - printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); - return -EBUSY; - } - if (i < MAX_DMA_SUSPEND_CHANNELS) - dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; - } - -#if ANOMALY_05000480 - bfin_write_DMAC_TC_PER(0x0); -#endif - return 0; -} - -void blackfin_dma_resume(void) -{ - int i; - - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - dma_ch[i].regs->cfg = 0; - if (i < MAX_DMA_SUSPEND_CHANNELS) - dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; - } -#if ANOMALY_05000480 - bfin_write_DMAC_TC_PER(0x0111); -#endif -} -# else -int blackfin_dma_suspend(void) -{ - return 0; -} - -void blackfin_dma_resume(void) -{ -} -#endif -#endif - -/** - * blackfin_dma_early_init - minimal DMA init - * - * Setup a few DMA registers so we can safely do DMA transfers early on in - * the kernel booting process. Really this just means using dma_memcpy(). - */ -void __init blackfin_dma_early_init(void) -{ - early_shadow_stamp(); - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_S1_CONFIG(0); -} - -void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) -{ - unsigned long dst = (unsigned long)pdst; - unsigned long src = (unsigned long)psrc; - struct dma_register *dst_ch, *src_ch; - - early_shadow_stamp(); - - /* We assume that everything is 4 byte aligned, so include - * a basic sanity check - */ - BUG_ON(dst % 4); - BUG_ON(src % 4); - BUG_ON(size % 4); - - src_ch = 0; - /* Find an avalible memDMA channel */ - while (1) { - if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) { - dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; - src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; - } else { - dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; - src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; - } - - if (!DMA_MMR_READ(&src_ch->cfg)) - break; - else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) { - DMA_MMR_WRITE(&src_ch->cfg, 0); - break; - } - } - - /* Force a sync in case a previous config reset on this channel - * occurred. This is needed so subsequent writes to DMA registers - * are not spuriously lost/corrupted. - */ - __builtin_bfin_ssync(); - - /* Destination */ - bfin_write32(&dst_ch->start_addr, dst); - DMA_MMR_WRITE(&dst_ch->x_count, size >> 2); - DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2); - DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR); - - /* Source */ - bfin_write32(&src_ch->start_addr, src); - DMA_MMR_WRITE(&src_ch->x_count, size >> 2); - DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2); - DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR); - - /* Enable */ - DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32); - DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32); - - /* Since we are atomic now, don't use the workaround ssync */ - __builtin_bfin_ssync(); - -#ifdef CONFIG_BF60x - /* Work around a possible MDMA anomaly. Running 2 MDMA channels to - * transfer DDR data to L1 SRAM may corrupt data. - * Should be reverted after this issue is root caused. - */ - while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE)) - continue; -#endif -} - -void __init early_dma_memcpy_done(void) -{ - early_shadow_stamp(); - - while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || - (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) - continue; - - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR); - /* - * Now that DMA is done, we would normally flush cache, but - * i/d cache isn't running this early, so we don't bother, - * and just clear out the DMA channel for next time - */ - bfin_write_MDMA_S0_CONFIG(0); - bfin_write_MDMA_S1_CONFIG(0); - bfin_write_MDMA_D0_CONFIG(0); - bfin_write_MDMA_D1_CONFIG(0); - - __builtin_bfin_ssync(); -} - -#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x) -#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG -#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG -#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR -#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS -#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT -#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY -#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT -#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY -#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG -#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR -#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS -#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS -#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT -#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY -#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT -#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY -#else -#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG -#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG -#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR -#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS -#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT -#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY -#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT -#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY -#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG -#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR -#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS -#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS -#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT -#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY -#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT -#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY -#endif - -/** - * __dma_memcpy - program the MDMA registers - * - * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs - * while programming registers so that everything is fully configured. Wait - * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE - * check will make sure we don't clobber any existing transfer. - */ -static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf) -{ - static DEFINE_SPINLOCK(mdma_lock); - unsigned long flags; - - spin_lock_irqsave(&mdma_lock, flags); - - /* Force a sync in case a previous config reset on this channel - * occurred. This is needed so subsequent writes to DMA registers - * are not spuriously lost/corrupted. Do it under irq lock and - * without the anomaly version (because we are atomic already). - */ - __builtin_bfin_ssync(); - - if (bfin_read_MDMA_S_CONFIG()) - while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE)) - continue; - - if (conf & DMA2D) { - /* For larger bit sizes, we've already divided down cnt so it - * is no longer a multiple of 64k. So we have to break down - * the limit here so it is a multiple of the incoming size. - * There is no limitation here in terms of total size other - * than the hardware though as the bits lost in the shift are - * made up by MODIFY (== we can hit the whole address space). - * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4 - */ - u32 shift = abs(dmod) >> 1; - size_t ycnt = cnt >> (16 - shift); - cnt = 1 << (16 - shift); - bfin_write_MDMA_D_Y_COUNT(ycnt); - bfin_write_MDMA_S_Y_COUNT(ycnt); - bfin_write_MDMA_D_Y_MODIFY(dmod); - bfin_write_MDMA_S_Y_MODIFY(smod); - } - - bfin_write_MDMA_D_START_ADDR(daddr); - bfin_write_MDMA_D_X_COUNT(cnt); - bfin_write_MDMA_D_X_MODIFY(dmod); - bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR); - - bfin_write_MDMA_S_START_ADDR(saddr); - bfin_write_MDMA_S_X_COUNT(cnt); - bfin_write_MDMA_S_X_MODIFY(smod); - bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR); - - bfin_write_MDMA_S_CONFIG(DMAEN | conf); - if (conf & DMA2D) - bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf); - else - bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf); - - spin_unlock_irqrestore(&mdma_lock, flags); - - SSYNC(); - - while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE)) - if (bfin_read_MDMA_S_CONFIG()) - continue; - else - return; - - bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR); - - bfin_write_MDMA_S_CONFIG(0); - bfin_write_MDMA_D_CONFIG(0); -} - -/** - * _dma_memcpy - translate C memcpy settings into MDMA settings - * - * Handle all the high level steps before we touch the MDMA registers. So - * handle direction, tweaking of sizes, and formatting of addresses. - */ -static void *_dma_memcpy(void *pdst, const void *psrc, size_t size) -{ - u32 conf, shift; - s16 mod; - unsigned long dst = (unsigned long)pdst; - unsigned long src = (unsigned long)psrc; - - if (size == 0) - return NULL; - - if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) { - conf = WDSIZE_32; - shift = 2; - } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) { - conf = WDSIZE_16; - shift = 1; - } else { - conf = WDSIZE_8; - shift = 0; - } - - /* If the two memory regions have a chance of overlapping, make - * sure the memcpy still works as expected. Do this by having the - * copy run backwards instead. - */ - mod = 1 << shift; - if (src < dst) { - mod *= -1; - dst += size + mod; - src += size + mod; - } - size >>= shift; - -#ifndef DMA_MMR_SIZE_32 - if (size > 0x10000) - conf |= DMA2D; -#endif - - __dma_memcpy(dst, mod, src, mod, size, conf); - - return pdst; -} - -/** - * dma_memcpy - DMA memcpy under mutex lock - * - * Do not check arguments before starting the DMA memcpy. Break the transfer - * up into two pieces. The first transfer is in multiples of 64k and the - * second transfer is the piece smaller than 64k. - */ -void *dma_memcpy(void *pdst, const void *psrc, size_t size) -{ - unsigned long dst = (unsigned long)pdst; - unsigned long src = (unsigned long)psrc; - - if (bfin_addr_dcacheable(src)) - blackfin_dcache_flush_range(src, src + size); - - if (bfin_addr_dcacheable(dst)) - blackfin_dcache_invalidate_range(dst, dst + size); - - return dma_memcpy_nocache(pdst, psrc, size); -} -EXPORT_SYMBOL(dma_memcpy); - -/** - * dma_memcpy_nocache - DMA memcpy under mutex lock - * - No cache flush/invalidate - * - * Do not check arguments before starting the DMA memcpy. Break the transfer - * up into two pieces. The first transfer is in multiples of 64k and the - * second transfer is the piece smaller than 64k. - */ -void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size) -{ -#ifdef DMA_MMR_SIZE_32 - _dma_memcpy(pdst, psrc, size); -#else - size_t bulk, rest; - - bulk = size & ~0xffff; - rest = size - bulk; - if (bulk) - _dma_memcpy(pdst, psrc, bulk); - _dma_memcpy(pdst + bulk, psrc + bulk, rest); -#endif - return pdst; -} -EXPORT_SYMBOL(dma_memcpy_nocache); - -/** - * safe_dma_memcpy - DMA memcpy w/argument checking - * - * Verify arguments are safe before heading to dma_memcpy(). - */ -void *safe_dma_memcpy(void *dst, const void *src, size_t size) -{ - if (!access_ok(VERIFY_WRITE, dst, size)) - return NULL; - if (!access_ok(VERIFY_READ, src, size)) - return NULL; - return dma_memcpy(dst, src, size); -} -EXPORT_SYMBOL(safe_dma_memcpy); - -static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len, - u16 size, u16 dma_size) -{ - blackfin_dcache_flush_range(buf, buf + len * size); - __dma_memcpy(addr, 0, buf, size, len, dma_size); -} - -static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len, - u16 size, u16 dma_size) -{ - blackfin_dcache_invalidate_range(buf, buf + len * size); - __dma_memcpy(buf, size, addr, 0, len, dma_size); -} - -#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \ -void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \ -{ \ - _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \ -} \ -EXPORT_SYMBOL(dma_##io##s##bwl) -MAKE_DMA_IO(out, b, 1, 8, const); -MAKE_DMA_IO(in, b, 1, 8, ); -MAKE_DMA_IO(out, w, 2, 16, const); -MAKE_DMA_IO(in, w, 2, 16, ); -MAKE_DMA_IO(out, l, 4, 32, const); -MAKE_DMA_IO(in, l, 4, 32, ); diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c deleted file mode 100644 index 63da80bbadf6..000000000000 --- a/arch/blackfin/kernel/bfin_gpio.c +++ /dev/null @@ -1,1208 +0,0 @@ -/* - * GPIO Abstraction Layer - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -/* FIXME: consumer API required for gpio_set_value() etc, get rid of this */ -#include -#include -#include -#include -#include - -#if ANOMALY_05000311 || ANOMALY_05000323 -enum { - AWA_data = SYSCR, - AWA_data_clear = SYSCR, - AWA_data_set = SYSCR, - AWA_toggle = SYSCR, - AWA_maska = BFIN_UART_SCR, - AWA_maska_clear = BFIN_UART_SCR, - AWA_maska_set = BFIN_UART_SCR, - AWA_maska_toggle = BFIN_UART_SCR, - AWA_maskb = BFIN_UART_GCTL, - AWA_maskb_clear = BFIN_UART_GCTL, - AWA_maskb_set = BFIN_UART_GCTL, - AWA_maskb_toggle = BFIN_UART_GCTL, - AWA_dir = SPORT1_STAT, - AWA_polar = SPORT1_STAT, - AWA_edge = SPORT1_STAT, - AWA_both = SPORT1_STAT, -#if ANOMALY_05000311 - AWA_inen = TIMER_ENABLE, -#elif ANOMALY_05000323 - AWA_inen = DMA1_1_CONFIG, -#endif -}; - /* Anomaly Workaround */ -#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name) -#else -#define AWA_DUMMY_READ(...) do { } while (0) -#endif - -static struct gpio_port_t * const gpio_array[] = { -#if defined(BF533_FAMILY) || defined(BF538_FAMILY) - (struct gpio_port_t *) FIO_FLAG_D, -#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) - (struct gpio_port_t *) PORTFIO, - (struct gpio_port_t *) PORTGIO, - (struct gpio_port_t *) PORTHIO, -#elif defined(BF561_FAMILY) - (struct gpio_port_t *) FIO0_FLAG_D, - (struct gpio_port_t *) FIO1_FLAG_D, - (struct gpio_port_t *) FIO2_FLAG_D, -#else -# error no gpio arrays defined -#endif -}; - -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) -static unsigned short * const port_fer[] = { - (unsigned short *) PORTF_FER, - (unsigned short *) PORTG_FER, - (unsigned short *) PORTH_FER, -}; - -# if !defined(BF537_FAMILY) -static unsigned short * const port_mux[] = { - (unsigned short *) PORTF_MUX, - (unsigned short *) PORTG_MUX, - (unsigned short *) PORTH_MUX, -}; - -static const -u8 pmux_offset[][16] = { -# if defined(CONFIG_BF52x) - { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */ - { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */ - { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */ -# elif defined(CONFIG_BF51x) - { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */ - { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */ - { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */ -# endif -}; -# endif - -#elif defined(BF538_FAMILY) -static unsigned short * const port_fer[] = { - (unsigned short *) PORTCIO_FER, - (unsigned short *) PORTDIO_FER, - (unsigned short *) PORTEIO_FER, -}; -#endif - -#define RESOURCE_LABEL_SIZE 16 - -static struct str_ident { - char name[RESOURCE_LABEL_SIZE]; -} str_ident[MAX_RESOURCES]; - -#if defined(CONFIG_PM) -static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM]; -# ifdef BF538_FAMILY -static unsigned short port_fer_saved[3]; -# endif -#endif - -static void gpio_error(unsigned gpio) -{ - printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio); -} - -static void set_label(unsigned short ident, const char *label) -{ - if (label) { - strncpy(str_ident[ident].name, label, - RESOURCE_LABEL_SIZE); - str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; - } -} - -static char *get_label(unsigned short ident) -{ - return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN"); -} - -static int cmp_label(unsigned short ident, const char *label) -{ - if (label == NULL) { - dump_stack(); - printk(KERN_ERR "Please provide none-null label\n"); - } - - if (label) - return strcmp(str_ident[ident].name, label); - else - return -EINVAL; -} - -#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)] -#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i)) -#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i)) -#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i)) -#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c] - -DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM); -DECLARE_RESERVED_MAP(peri, DIV_ROUND_UP(MAX_RESOURCES, GPIO_BANKSIZE)); -DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM); - -inline int check_gpio(unsigned gpio) -{ - if (gpio >= MAX_BLACKFIN_GPIOS) - return -EINVAL; - return 0; -} - -static void port_setup(unsigned gpio, unsigned short usage) -{ -#if defined(BF538_FAMILY) - /* - * BF538/9 Port C,D and E are special. - * Inverted PORT_FER polarity on CDE and no PORF_FER on F - * Regular PORT F GPIOs are handled here, CDE are exclusively - * managed by GPIOLIB - */ - - if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES) - return; - - gpio -= MAX_BLACKFIN_GPIOS; - - if (usage == GPIO_USAGE) - *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); - else - *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); - SSYNC(); - return; -#endif - - if (check_gpio(gpio)) - return; - -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) - if (usage == GPIO_USAGE) - *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); - else - *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); - SSYNC(); -#endif -} - -#ifdef BF537_FAMILY -static const s8 port_mux[] = { - [GPIO_PF0] = 3, - [GPIO_PF1] = 3, - [GPIO_PF2] = 4, - [GPIO_PF3] = 4, - [GPIO_PF4] = 5, - [GPIO_PF5] = 6, - [GPIO_PF6] = 7, - [GPIO_PF7] = 8, - [GPIO_PF8 ... GPIO_PF15] = -1, - [GPIO_PG0 ... GPIO_PG7] = -1, - [GPIO_PG8] = 9, - [GPIO_PG9] = 9, - [GPIO_PG10] = 10, - [GPIO_PG11] = 10, - [GPIO_PG12] = 10, - [GPIO_PG13] = 11, - [GPIO_PG14] = 11, - [GPIO_PG15] = 11, - [GPIO_PH0 ... GPIO_PH15] = -1, - [PORT_PJ0 ... PORT_PJ3] = -1, - [PORT_PJ4] = 1, - [PORT_PJ5] = 1, - [PORT_PJ6 ... PORT_PJ9] = -1, - [PORT_PJ10] = 0, - [PORT_PJ11] = 0, -}; - -static int portmux_group_check(unsigned short per) -{ - u16 ident = P_IDENT(per); - u16 function = P_FUNCT2MUX(per); - s8 offset = port_mux[ident]; - u16 m, pmux, pfunc, mask; - - if (offset < 0) - return 0; - - pmux = bfin_read_PORT_MUX(); - for (m = 0; m < ARRAY_SIZE(port_mux); ++m) { - if (m == ident) - continue; - if (port_mux[m] != offset) - continue; - if (!is_reserved(peri, m, 1)) - continue; - - if (offset == 1) - mask = 3; - else - mask = 1; - - pfunc = (pmux >> offset) & mask; - if (pfunc != (function & mask)) { - pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n", - ident, function, m, pfunc); - return -EINVAL; - } - } - - return 0; -} - -static void portmux_setup(unsigned short per) -{ - u16 ident = P_IDENT(per); - u16 function = P_FUNCT2MUX(per); - s8 offset = port_mux[ident]; - u16 pmux, mask; - - if (offset == -1) - return; - - pmux = bfin_read_PORT_MUX(); - if (offset == 1) - mask = 3; - else - mask = 1; - - pmux &= ~(mask << offset); - pmux |= ((function & mask) << offset); - - bfin_write_PORT_MUX(pmux); -} -#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) -static int portmux_group_check(unsigned short per) -{ - u16 ident = P_IDENT(per); - u16 function = P_FUNCT2MUX(per); - u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; - u16 pin, gpiopin, pfunc; - - for (pin = 0; pin < GPIO_BANKSIZE; ++pin) { - if (offset != pmux_offset[gpio_bank(ident)][pin]) - continue; - - gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin; - if (gpiopin == ident) - continue; - if (!is_reserved(peri, gpiopin, 1)) - continue; - - pfunc = *port_mux[gpio_bank(ident)]; - pfunc = (pfunc >> offset) & 3; - if (pfunc != function) { - pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n", - ident, function, gpiopin, pfunc); - return -EINVAL; - } - } - - return 0; -} - -inline void portmux_setup(unsigned short per) -{ - u16 ident = P_IDENT(per); - u16 function = P_FUNCT2MUX(per); - u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; - u16 pmux; - - pmux = *port_mux[gpio_bank(ident)]; - if (((pmux >> offset) & 3) == function) - return; - pmux &= ~(3 << offset); - pmux |= (function & 3) << offset; - *port_mux[gpio_bank(ident)] = pmux; - SSYNC(); -} -#else -# define portmux_setup(...) do { } while (0) -static int portmux_group_check(unsigned short per) -{ - return 0; -} -#endif - -/*********************************************************** -* -* FUNCTIONS: Blackfin General Purpose Ports Access Functions -* -* INPUTS/OUTPUTS: -* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS -* -* -* DESCRIPTION: These functions abstract direct register access -* to Blackfin processor General Purpose -* Ports Regsiters -* -* CAUTION: These functions do not belong to the GPIO Driver API -************************************************************* -* MODIFICATION HISTORY : -**************************************************************/ - -/* Set a specific bit */ - -#define SET_GPIO(name) \ -void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ -{ \ - unsigned long flags; \ - flags = hard_local_irq_save(); \ - if (arg) \ - gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ - else \ - gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ - AWA_DUMMY_READ(name); \ - hard_local_irq_restore(flags); \ -} \ -EXPORT_SYMBOL(set_gpio_ ## name); - -SET_GPIO(dir) /* set_gpio_dir() */ -SET_GPIO(inen) /* set_gpio_inen() */ -SET_GPIO(polar) /* set_gpio_polar() */ -SET_GPIO(edge) /* set_gpio_edge() */ -SET_GPIO(both) /* set_gpio_both() */ - - -#define SET_GPIO_SC(name) \ -void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ -{ \ - unsigned long flags; \ - if (ANOMALY_05000311 || ANOMALY_05000323) \ - flags = hard_local_irq_save(); \ - if (arg) \ - gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ - else \ - gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ - if (ANOMALY_05000311 || ANOMALY_05000323) { \ - AWA_DUMMY_READ(name); \ - hard_local_irq_restore(flags); \ - } \ -} \ -EXPORT_SYMBOL(set_gpio_ ## name); - -SET_GPIO_SC(maska) -SET_GPIO_SC(maskb) -SET_GPIO_SC(data) - -void set_gpio_toggle(unsigned gpio) -{ - unsigned long flags; - if (ANOMALY_05000311 || ANOMALY_05000323) - flags = hard_local_irq_save(); - gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio); - if (ANOMALY_05000311 || ANOMALY_05000323) { - AWA_DUMMY_READ(toggle); - hard_local_irq_restore(flags); - } -} -EXPORT_SYMBOL(set_gpio_toggle); - - -/*Set current PORT date (16-bit word)*/ - -#define SET_GPIO_P(name) \ -void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ -{ \ - unsigned long flags; \ - if (ANOMALY_05000311 || ANOMALY_05000323) \ - flags = hard_local_irq_save(); \ - gpio_array[gpio_bank(gpio)]->name = arg; \ - if (ANOMALY_05000311 || ANOMALY_05000323) { \ - AWA_DUMMY_READ(name); \ - hard_local_irq_restore(flags); \ - } \ -} \ -EXPORT_SYMBOL(set_gpiop_ ## name); - -SET_GPIO_P(data) -SET_GPIO_P(dir) -SET_GPIO_P(inen) -SET_GPIO_P(polar) -SET_GPIO_P(edge) -SET_GPIO_P(both) -SET_GPIO_P(maska) -SET_GPIO_P(maskb) - -/* Get a specific bit */ -#define GET_GPIO(name) \ -unsigned short get_gpio_ ## name(unsigned gpio) \ -{ \ - unsigned long flags; \ - unsigned short ret; \ - if (ANOMALY_05000311 || ANOMALY_05000323) \ - flags = hard_local_irq_save(); \ - ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ - if (ANOMALY_05000311 || ANOMALY_05000323) { \ - AWA_DUMMY_READ(name); \ - hard_local_irq_restore(flags); \ - } \ - return ret; \ -} \ -EXPORT_SYMBOL(get_gpio_ ## name); - -GET_GPIO(data) -GET_GPIO(dir) -GET_GPIO(inen) -GET_GPIO(polar) -GET_GPIO(edge) -GET_GPIO(both) -GET_GPIO(maska) -GET_GPIO(maskb) - -/*Get current PORT date (16-bit word)*/ - -#define GET_GPIO_P(name) \ -unsigned short get_gpiop_ ## name(unsigned gpio) \ -{ \ - unsigned long flags; \ - unsigned short ret; \ - if (ANOMALY_05000311 || ANOMALY_05000323) \ - flags = hard_local_irq_save(); \ - ret = (gpio_array[gpio_bank(gpio)]->name); \ - if (ANOMALY_05000311 || ANOMALY_05000323) { \ - AWA_DUMMY_READ(name); \ - hard_local_irq_restore(flags); \ - } \ - return ret; \ -} \ -EXPORT_SYMBOL(get_gpiop_ ## name); - -GET_GPIO_P(data) -GET_GPIO_P(dir) -GET_GPIO_P(inen) -GET_GPIO_P(polar) -GET_GPIO_P(edge) -GET_GPIO_P(both) -GET_GPIO_P(maska) -GET_GPIO_P(maskb) - - -#ifdef CONFIG_PM -DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM); - -static const unsigned int sic_iwr_irqs[] = { -#if defined(BF533_FAMILY) - IRQ_PROG_INTB -#elif defined(BF537_FAMILY) - IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX -#elif defined(BF538_FAMILY) - IRQ_PORTF_INTB -#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) - IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB -#elif defined(BF561_FAMILY) - IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB -#else -# error no SIC_IWR defined -#endif -}; - -/*********************************************************** -* -* FUNCTIONS: Blackfin PM Setup API -* -* INPUTS/OUTPUTS: -* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS -* type - -* PM_WAKE_RISING -* PM_WAKE_FALLING -* PM_WAKE_HIGH -* PM_WAKE_LOW -* PM_WAKE_BOTH_EDGES -* -* DESCRIPTION: Blackfin PM Driver API -* -* CAUTION: -************************************************************* -* MODIFICATION HISTORY : -**************************************************************/ -int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl) -{ - unsigned long flags; - - if (check_gpio(gpio) < 0) - return -EINVAL; - - flags = hard_local_irq_save(); - if (ctrl) - reserve(wakeup, gpio); - else - unreserve(wakeup, gpio); - - set_gpio_maskb(gpio, ctrl); - hard_local_irq_restore(flags); - - return 0; -} - -int bfin_gpio_pm_standby_ctrl(unsigned ctrl) -{ - u16 bank, mask, i; - - for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { - mask = map_entry(wakeup, i); - bank = gpio_bank(i); - - if (mask) - bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl); - } - return 0; -} - -void bfin_gpio_pm_hibernate_suspend(void) -{ - int i, bank; - -#ifdef BF538_FAMILY - for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i) - port_fer_saved[i] = *port_fer[i]; -#endif - - for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { - bank = gpio_bank(i); - -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) - gpio_bank_saved[bank].fer = *port_fer[bank]; -#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) - gpio_bank_saved[bank].mux = *port_mux[bank]; -#else - if (bank == 0) - gpio_bank_saved[bank].mux = bfin_read_PORT_MUX(); -#endif -#endif - gpio_bank_saved[bank].data = gpio_array[bank]->data; - gpio_bank_saved[bank].inen = gpio_array[bank]->inen; - gpio_bank_saved[bank].polar = gpio_array[bank]->polar; - gpio_bank_saved[bank].dir = gpio_array[bank]->dir; - gpio_bank_saved[bank].edge = gpio_array[bank]->edge; - gpio_bank_saved[bank].both = gpio_array[bank]->both; - gpio_bank_saved[bank].maska = gpio_array[bank]->maska; - } - -#ifdef BFIN_SPECIAL_GPIO_BANKS - bfin_special_gpio_pm_hibernate_suspend(); -#endif - - AWA_DUMMY_READ(maska); -} - -void bfin_gpio_pm_hibernate_restore(void) -{ - int i, bank; - -#ifdef BF538_FAMILY - for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i) - *port_fer[i] = port_fer_saved[i]; -#endif - - for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { - bank = gpio_bank(i); - -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) -#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) - *port_mux[bank] = gpio_bank_saved[bank].mux; -#else - if (bank == 0) - bfin_write_PORT_MUX(gpio_bank_saved[bank].mux); -#endif - *port_fer[bank] = gpio_bank_saved[bank].fer; -#endif - gpio_array[bank]->inen = gpio_bank_saved[bank].inen; - gpio_array[bank]->data_set = gpio_bank_saved[bank].data - & gpio_bank_saved[bank].dir; - gpio_array[bank]->dir = gpio_bank_saved[bank].dir; - gpio_array[bank]->polar = gpio_bank_saved[bank].polar; - gpio_array[bank]->edge = gpio_bank_saved[bank].edge; - gpio_array[bank]->both = gpio_bank_saved[bank].both; - gpio_array[bank]->maska = gpio_bank_saved[bank].maska; - } - -#ifdef BFIN_SPECIAL_GPIO_BANKS - bfin_special_gpio_pm_hibernate_restore(); -#endif - - AWA_DUMMY_READ(maska); -} - - -#endif - -/*********************************************************** -* -* FUNCTIONS: Blackfin Peripheral Resource Allocation -* and PortMux Setup -* -* INPUTS/OUTPUTS: -* per Peripheral Identifier -* label String -* -* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API -* -* CAUTION: -************************************************************* -* MODIFICATION HISTORY : -**************************************************************/ - -int peripheral_request(unsigned short per, const char *label) -{ - unsigned long flags; - unsigned short ident = P_IDENT(per); - - /* - * Don't cares are pins with only one dedicated function - */ - - if (per & P_DONTCARE) - return 0; - - if (!(per & P_DEFINED)) - return -ENODEV; - - BUG_ON(ident >= MAX_RESOURCES); - - flags = hard_local_irq_save(); - - /* If a pin can be muxed as either GPIO or peripheral, make - * sure it is not already a GPIO pin when we request it. - */ - if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) { - if (system_state == SYSTEM_BOOTING) - dump_stack(); - printk(KERN_ERR - "%s: Peripheral %d is already reserved as GPIO by %s !\n", - __func__, ident, get_label(ident)); - hard_local_irq_restore(flags); - return -EBUSY; - } - - if (unlikely(is_reserved(peri, ident, 1))) { - - /* - * Pin functions like AMC address strobes my - * be requested and used by several drivers - */ - - if (!(per & P_MAYSHARE)) { - /* - * Allow that the identical pin function can - * be requested from the same driver twice - */ - - if (cmp_label(ident, label) == 0) - goto anyway; - - if (system_state == SYSTEM_BOOTING) - dump_stack(); - printk(KERN_ERR - "%s: Peripheral %d function %d is already reserved by %s !\n", - __func__, ident, P_FUNCT2MUX(per), get_label(ident)); - hard_local_irq_restore(flags); - return -EBUSY; - } - } - - if (unlikely(portmux_group_check(per))) { - hard_local_irq_restore(flags); - return -EBUSY; - } - anyway: - reserve(peri, ident); - - portmux_setup(per); - port_setup(ident, PERIPHERAL_USAGE); - - hard_local_irq_restore(flags); - set_label(ident, label); - - return 0; -} -EXPORT_SYMBOL(peripheral_request); - -int peripheral_request_list(const unsigned short per[], const char *label) -{ - u16 cnt; - int ret; - - for (cnt = 0; per[cnt] != 0; cnt++) { - - ret = peripheral_request(per[cnt], label); - - if (ret < 0) { - for ( ; cnt > 0; cnt--) - peripheral_free(per[cnt - 1]); - - return ret; - } - } - - return 0; -} -EXPORT_SYMBOL(peripheral_request_list); - -void peripheral_free(unsigned short per) -{ - unsigned long flags; - unsigned short ident = P_IDENT(per); - - if (per & P_DONTCARE) - return; - - if (!(per & P_DEFINED)) - return; - - flags = hard_local_irq_save(); - - if (unlikely(!is_reserved(peri, ident, 0))) { - hard_local_irq_restore(flags); - return; - } - - if (!(per & P_MAYSHARE)) - port_setup(ident, GPIO_USAGE); - - unreserve(peri, ident); - - set_label(ident, "free"); - - hard_local_irq_restore(flags); -} -EXPORT_SYMBOL(peripheral_free); - -void peripheral_free_list(const unsigned short per[]) -{ - u16 cnt; - for (cnt = 0; per[cnt] != 0; cnt++) - peripheral_free(per[cnt]); -} -EXPORT_SYMBOL(peripheral_free_list); - -/*********************************************************** -* -* FUNCTIONS: Blackfin GPIO Driver -* -* INPUTS/OUTPUTS: -* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS -* label String -* -* DESCRIPTION: Blackfin GPIO Driver API -* -* CAUTION: -************************************************************* -* MODIFICATION HISTORY : -**************************************************************/ - -int bfin_gpio_request(unsigned gpio, const char *label) -{ - unsigned long flags; - - if (check_gpio(gpio) < 0) - return -EINVAL; - - flags = hard_local_irq_save(); - - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) { - hard_local_irq_restore(flags); - return 0; - } - - if (unlikely(is_reserved(gpio, gpio, 1))) { - if (system_state == SYSTEM_BOOTING) - dump_stack(); - printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", - gpio, get_label(gpio)); - hard_local_irq_restore(flags); - return -EBUSY; - } - if (unlikely(is_reserved(peri, gpio, 1))) { - if (system_state == SYSTEM_BOOTING) - dump_stack(); - printk(KERN_ERR - "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", - gpio, get_label(gpio)); - hard_local_irq_restore(flags); - return -EBUSY; - } - if (unlikely(is_reserved(gpio_irq, gpio, 1))) { - printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" - " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); - } else { /* Reset POLAR setting when acquiring a gpio for the first time */ - set_gpio_polar(gpio, 0); - } - - reserve(gpio, gpio); - set_label(gpio, label); - - hard_local_irq_restore(flags); - - port_setup(gpio, GPIO_USAGE); - - return 0; -} -EXPORT_SYMBOL(bfin_gpio_request); - -void bfin_gpio_free(unsigned gpio) -{ - unsigned long flags; - - if (check_gpio(gpio) < 0) - return; - - might_sleep(); - - flags = hard_local_irq_save(); - - if (unlikely(!is_reserved(gpio, gpio, 0))) { - if (system_state == SYSTEM_BOOTING) - dump_stack(); - gpio_error(gpio); - hard_local_irq_restore(flags); - return; - } - - unreserve(gpio, gpio); - - set_label(gpio, "free"); - - hard_local_irq_restore(flags); -} -EXPORT_SYMBOL(bfin_gpio_free); - -#ifdef BFIN_SPECIAL_GPIO_BANKS -DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES)); - -int bfin_special_gpio_request(unsigned gpio, const char *label) -{ - unsigned long flags; - - flags = hard_local_irq_save(); - - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) { - hard_local_irq_restore(flags); - return 0; - } - - if (unlikely(is_reserved(special_gpio, gpio, 1))) { - hard_local_irq_restore(flags); - printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", - gpio, get_label(gpio)); - - return -EBUSY; - } - if (unlikely(is_reserved(peri, gpio, 1))) { - hard_local_irq_restore(flags); - printk(KERN_ERR - "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", - gpio, get_label(gpio)); - - return -EBUSY; - } - - reserve(special_gpio, gpio); - reserve(peri, gpio); - - set_label(gpio, label); - hard_local_irq_restore(flags); - port_setup(gpio, GPIO_USAGE); - - return 0; -} -EXPORT_SYMBOL(bfin_special_gpio_request); - -void bfin_special_gpio_free(unsigned gpio) -{ - unsigned long flags; - - might_sleep(); - - flags = hard_local_irq_save(); - - if (unlikely(!is_reserved(special_gpio, gpio, 0))) { - gpio_error(gpio); - hard_local_irq_restore(flags); - return; - } - - unreserve(special_gpio, gpio); - unreserve(peri, gpio); - set_label(gpio, "free"); - hard_local_irq_restore(flags); -} -EXPORT_SYMBOL(bfin_special_gpio_free); -#endif - - -int bfin_gpio_irq_request(unsigned gpio, const char *label) -{ - unsigned long flags; - - if (check_gpio(gpio) < 0) - return -EINVAL; - - flags = hard_local_irq_save(); - - if (unlikely(is_reserved(peri, gpio, 1))) { - if (system_state == SYSTEM_BOOTING) - dump_stack(); - printk(KERN_ERR - "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", - gpio, get_label(gpio)); - hard_local_irq_restore(flags); - return -EBUSY; - } - if (unlikely(is_reserved(gpio, gpio, 1))) - printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! " - "(Documentation/blackfin/bfin-gpio-notes.txt)\n", - gpio, get_label(gpio)); - - reserve(gpio_irq, gpio); - set_label(gpio, label); - - hard_local_irq_restore(flags); - - port_setup(gpio, GPIO_USAGE); - - return 0; -} - -void bfin_gpio_irq_free(unsigned gpio) -{ - unsigned long flags; - - if (check_gpio(gpio) < 0) - return; - - flags = hard_local_irq_save(); - - if (unlikely(!is_reserved(gpio_irq, gpio, 0))) { - if (system_state == SYSTEM_BOOTING) - dump_stack(); - gpio_error(gpio); - hard_local_irq_restore(flags); - return; - } - - unreserve(gpio_irq, gpio); - - set_label(gpio, "free"); - - hard_local_irq_restore(flags); -} - -static inline void __bfin_gpio_direction_input(unsigned gpio) -{ - gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); - gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); -} - -int bfin_gpio_direction_input(unsigned gpio) -{ - unsigned long flags; - - if (unlikely(!is_reserved(gpio, gpio, 0))) { - gpio_error(gpio); - return -EINVAL; - } - - flags = hard_local_irq_save(); - __bfin_gpio_direction_input(gpio); - AWA_DUMMY_READ(inen); - hard_local_irq_restore(flags); - - return 0; -} -EXPORT_SYMBOL(bfin_gpio_direction_input); - -void bfin_gpio_irq_prepare(unsigned gpio) -{ - port_setup(gpio, GPIO_USAGE); -} - -void bfin_gpio_set_value(unsigned gpio, int arg) -{ - if (arg) - gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); - else - gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio); -} -EXPORT_SYMBOL(bfin_gpio_set_value); - -int bfin_gpio_direction_output(unsigned gpio, int value) -{ - unsigned long flags; - - if (unlikely(!is_reserved(gpio, gpio, 0))) { - gpio_error(gpio); - return -EINVAL; - } - - flags = hard_local_irq_save(); - - gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); - gpio_set_value(gpio, value); - gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); - - AWA_DUMMY_READ(dir); - hard_local_irq_restore(flags); - - return 0; -} -EXPORT_SYMBOL(bfin_gpio_direction_output); - -int bfin_gpio_get_value(unsigned gpio) -{ - unsigned long flags; - - if (unlikely(get_gpio_edge(gpio))) { - int ret; - flags = hard_local_irq_save(); - set_gpio_edge(gpio, 0); - ret = get_gpio_data(gpio); - set_gpio_edge(gpio, 1); - hard_local_irq_restore(flags); - return ret; - } else - return get_gpio_data(gpio); -} -EXPORT_SYMBOL(bfin_gpio_get_value); - -/* If we are booting from SPI and our board lacks a strong enough pull up, - * the core can reset and execute the bootrom faster than the resistor can - * pull the signal logically high. To work around this (common) error in - * board design, we explicitly set the pin back to GPIO mode, force /CS - * high, and wait for the electrons to do their thing. - * - * This function only makes sense to be called from reset code, but it - * lives here as we need to force all the GPIO states w/out going through - * BUG() checks and such. - */ -void bfin_reset_boot_spi_cs(unsigned short pin) -{ - unsigned short gpio = P_IDENT(pin); - port_setup(gpio, GPIO_USAGE); - gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); - AWA_DUMMY_READ(data_set); - udelay(1); -} - -#if defined(CONFIG_PROC_FS) -static int gpio_proc_show(struct seq_file *m, void *v) -{ - int c, irq, gpio; - - for (c = 0; c < MAX_RESOURCES; c++) { - irq = is_reserved(gpio_irq, c, 1); - gpio = is_reserved(gpio, c, 1); - if (!check_gpio(c) && (gpio || irq)) - seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c, - get_label(c), (gpio && irq) ? " *" : "", - get_gpio_dir(c) ? "OUTPUT" : "INPUT"); - else if (is_reserved(peri, c, 1)) - seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c)); - else - continue; - } - - return 0; -} - -static int gpio_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, gpio_proc_show, NULL); -} - -static const struct file_operations gpio_proc_ops = { - .open = gpio_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static __init int gpio_register_proc(void) -{ - struct proc_dir_entry *proc_gpio; - - proc_gpio = proc_create("gpio", 0, NULL, &gpio_proc_ops); - return proc_gpio == NULL; -} -__initcall(gpio_register_proc); -#endif - -#ifdef CONFIG_GPIOLIB -static int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_gpio_direction_input(gpio); -} - -static int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level) -{ - return bfin_gpio_direction_output(gpio, level); -} - -static int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio) -{ - return !!bfin_gpio_get_value(gpio); -} - -static void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value) -{ - return bfin_gpio_set_value(gpio, value); -} - -static int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_gpio_request(gpio, chip->label); -} - -static void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_gpio_free(gpio); -} - -static int bfin_gpiolib_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) -{ - return gpio + GPIO_IRQ_BASE; -} - -static struct gpio_chip bfin_chip = { - .label = "BFIN-GPIO", - .direction_input = bfin_gpiolib_direction_input, - .get = bfin_gpiolib_get_value, - .direction_output = bfin_gpiolib_direction_output, - .set = bfin_gpiolib_set_value, - .request = bfin_gpiolib_gpio_request, - .free = bfin_gpiolib_gpio_free, - .to_irq = bfin_gpiolib_gpio_to_irq, - .base = 0, - .ngpio = MAX_BLACKFIN_GPIOS, -}; - -static int __init bfin_gpiolib_setup(void) -{ - return gpiochip_add_data(&bfin_chip, NULL); -} -arch_initcall(bfin_gpiolib_setup); -#endif diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c deleted file mode 100644 index 68096e8f787f..000000000000 --- a/arch/blackfin/kernel/bfin_ksyms.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * arch/blackfin/kernel/bfin_ksyms.c - exports for random symbols - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include -#include - -/* Allow people to have their own Blackfin exception handler in a module */ -EXPORT_SYMBOL(bfin_return_from_exception); - -/* All the Blackfin cache functions: mach-common/cache.S */ -EXPORT_SYMBOL(blackfin_dcache_invalidate_range); -EXPORT_SYMBOL(blackfin_icache_flush_range); -EXPORT_SYMBOL(blackfin_dcache_flush_range); -EXPORT_SYMBOL(blackfin_dflush_page); - -/* The following are special because they're not called - * explicitly (the C compiler generates them). Fortunately, - * their interface isn't gonna change any time soon now, so - * it's OK to leave it out of version control. - */ -EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(memset); -EXPORT_SYMBOL(memcmp); -EXPORT_SYMBOL(memmove); -EXPORT_SYMBOL(memchr); - -/* - * Because string functions are both inline and exported functions and - * folder arch/blackfin/lib is configured as a library path in Makefile, - * symbols exported in folder lib is not linked into built-in.o but - * inlined only. In order to export string symbols to kernel module - * properly, they should be exported here. - */ -EXPORT_SYMBOL(strcpy); -EXPORT_SYMBOL(strncpy); -EXPORT_SYMBOL(strcmp); -EXPORT_SYMBOL(strncmp); - -/* - * libgcc functions - functions that are used internally by the - * compiler... (prototypes are not correct though, but that - * doesn't really matter since they're not versioned). - */ -extern void __ashldi3(void); -extern void __ashrdi3(void); -extern void __smulsi3_highpart(void); -extern void __umulsi3_highpart(void); -extern void __divsi3(void); -extern void __lshrdi3(void); -extern void __modsi3(void); -extern void __muldi3(void); -extern void __udivsi3(void); -extern void __umodsi3(void); -EXPORT_SYMBOL(__ashldi3); -EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__umulsi3_highpart); -EXPORT_SYMBOL(__smulsi3_highpart); -EXPORT_SYMBOL(__divsi3); -EXPORT_SYMBOL(__lshrdi3); -EXPORT_SYMBOL(__modsi3); -EXPORT_SYMBOL(__muldi3); -EXPORT_SYMBOL(__udivsi3); -EXPORT_SYMBOL(__umodsi3); - -/* Input/output symbols: lib/{in,out}s.S */ -EXPORT_SYMBOL(outsb); -EXPORT_SYMBOL(insb); -EXPORT_SYMBOL(outsw); -EXPORT_SYMBOL(outsw_8); -EXPORT_SYMBOL(insw); -EXPORT_SYMBOL(insw_8); -EXPORT_SYMBOL(outsl); -EXPORT_SYMBOL(insl); -EXPORT_SYMBOL(insl_16); - -#ifdef CONFIG_SMP -EXPORT_SYMBOL(__raw_atomic_add_asm); -EXPORT_SYMBOL(__raw_atomic_xadd_asm); -EXPORT_SYMBOL(__raw_atomic_and_asm); -EXPORT_SYMBOL(__raw_atomic_or_asm); -EXPORT_SYMBOL(__raw_atomic_xor_asm); -EXPORT_SYMBOL(__raw_atomic_test_asm); - -EXPORT_SYMBOL(__raw_xchg_1_asm); -EXPORT_SYMBOL(__raw_xchg_2_asm); -EXPORT_SYMBOL(__raw_xchg_4_asm); -EXPORT_SYMBOL(__raw_cmpxchg_1_asm); -EXPORT_SYMBOL(__raw_cmpxchg_2_asm); -EXPORT_SYMBOL(__raw_cmpxchg_4_asm); -EXPORT_SYMBOL(__raw_spin_is_locked_asm); -EXPORT_SYMBOL(__raw_spin_lock_asm); -EXPORT_SYMBOL(__raw_spin_trylock_asm); -EXPORT_SYMBOL(__raw_spin_unlock_asm); -EXPORT_SYMBOL(__raw_read_lock_asm); -EXPORT_SYMBOL(__raw_read_trylock_asm); -EXPORT_SYMBOL(__raw_read_unlock_asm); -EXPORT_SYMBOL(__raw_write_lock_asm); -EXPORT_SYMBOL(__raw_write_trylock_asm); -EXPORT_SYMBOL(__raw_write_unlock_asm); -EXPORT_SYMBOL(__raw_bit_set_asm); -EXPORT_SYMBOL(__raw_bit_clear_asm); -EXPORT_SYMBOL(__raw_bit_toggle_asm); -EXPORT_SYMBOL(__raw_bit_test_asm); -EXPORT_SYMBOL(__raw_bit_test_set_asm); -EXPORT_SYMBOL(__raw_bit_test_clear_asm); -EXPORT_SYMBOL(__raw_bit_test_toggle_asm); -EXPORT_SYMBOL(__raw_uncached_fetch_asm); -#ifdef __ARCH_SYNC_CORE_DCACHE -EXPORT_SYMBOL(__raw_smp_mark_barrier_asm); -EXPORT_SYMBOL(__raw_smp_check_barrier_asm); -#endif -#endif - -#ifdef CONFIG_FUNCTION_TRACER -extern void _mcount(void); -EXPORT_SYMBOL(_mcount); -#endif diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile deleted file mode 100644 index 394d0b1b28fe..000000000000 --- a/arch/blackfin/kernel/cplb-mpu/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# arch/blackfin/kernel/cplb-nompu/Makefile -# - -obj-y := cplbinit.o cplbmgr.o - -CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ - -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ - -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \ - -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3 diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c deleted file mode 100644 index c15fd05f0b09..000000000000 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Blackfin CPLB initialization - * - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include -#include -#include - -struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; -struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; - -int first_switched_icplb, first_switched_dcplb; -int first_mask_dcplb; - -void __init generate_cplb_tables_cpu(unsigned int cpu) -{ - int i_d, i_i; - unsigned long addr; - unsigned long d_data, i_data; - unsigned long d_cache = 0, i_cache = 0; - - printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); - -#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE - i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; -#endif - -#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE - d_cache = CPLB_L1_CHBL; -#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH - d_cache |= CPLB_L1_AOW | CPLB_WT; -#endif -#endif - - i_d = i_i = 0; - - /* Set up the zero page. */ - dcplb_tbl[cpu][i_d].addr = 0; - dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; - - icplb_tbl[cpu][i_i].addr = 0; - icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB; - - /* Cover kernel memory with 4M pages. */ - addr = 0; - d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY; - i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB; - - for (; addr < memory_start; addr += 4 * 1024 * 1024) { - dcplb_tbl[cpu][i_d].addr = addr; - dcplb_tbl[cpu][i_d++].data = d_data; - icplb_tbl[cpu][i_i].addr = addr; - icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0); - } - -#ifdef CONFIG_ROMKERNEL - /* Cover kernel XIP flash area */ - addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1); - dcplb_tbl[cpu][i_d].addr = addr; - dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD; - icplb_tbl[cpu][i_i].addr = addr; - icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD; -#endif - - /* Cover L1 memory. One 4M area for code and data each is enough. */ -#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0 - dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu); - dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; -#endif -#if L1_CODE_LENGTH > 0 - icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu); - icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; -#endif - - /* Cover L2 memory */ -#if L2_LENGTH > 0 - dcplb_tbl[cpu][i_d].addr = L2_START; - dcplb_tbl[cpu][i_d++].data = L2_DMEMORY; - icplb_tbl[cpu][i_i].addr = L2_START; - icplb_tbl[cpu][i_i++].data = L2_IMEMORY; -#endif - - first_mask_dcplb = i_d; - first_switched_dcplb = i_d + (1 << page_mask_order); - first_switched_icplb = i_i; - - while (i_d < MAX_CPLBS) - dcplb_tbl[cpu][i_d++].data = 0; - while (i_i < MAX_CPLBS) - icplb_tbl[cpu][i_i++].data = 0; -} - -void __init generate_cplb_tables_all(void) -{ -} diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c deleted file mode 100644 index b56bd8514b7c..000000000000 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Blackfin CPLB exception handling for when MPU in on - * - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include -#include -#include -#include - -/* - * WARNING - * - * This file is compiled with certain -ffixed-reg options. We have to - * make sure not to call any functions here that could clobber these - * registers. - */ - -int page_mask_nelts; -int page_mask_order; -unsigned long *current_rwx_mask[NR_CPUS]; - -int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS]; -int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS]; -int nr_cplb_flush[NR_CPUS]; - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -#define MGR_ATTR __attribute__((l1_text)) -#else -#define MGR_ATTR -#endif - -/* - * Given the contents of the status register, return the index of the - * CPLB that caused the fault. - */ -static inline int faulting_cplb_index(int status) -{ - int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF); - return 30 - signbits; -} - -/* - * Given the contents of the status register and the DCPLB_DATA contents, - * return true if a write access should be permitted. - */ -static inline int write_permitted(int status, unsigned long data) -{ - if (status & FAULT_USERSUPV) - return !!(data & CPLB_SUPV_WR); - else - return !!(data & CPLB_USER_WR); -} - -/* Counters to implement round-robin replacement. */ -static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS]; - -/* - * Find an ICPLB entry to be evicted and return its index. - */ -MGR_ATTR static int evict_one_icplb(unsigned int cpu) -{ - int i; - for (i = first_switched_icplb; i < MAX_CPLBS; i++) - if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0) - return i; - i = first_switched_icplb + icplb_rr_index[cpu]; - if (i >= MAX_CPLBS) { - i -= MAX_CPLBS - first_switched_icplb; - icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb; - } - icplb_rr_index[cpu]++; - return i; -} - -MGR_ATTR static int evict_one_dcplb(unsigned int cpu) -{ - int i; - for (i = first_switched_dcplb; i < MAX_CPLBS; i++) - if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0) - return i; - i = first_switched_dcplb + dcplb_rr_index[cpu]; - if (i >= MAX_CPLBS) { - i -= MAX_CPLBS - first_switched_dcplb; - dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb; - } - dcplb_rr_index[cpu]++; - return i; -} - -MGR_ATTR static noinline int dcplb_miss(unsigned int cpu) -{ - unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); - int status = bfin_read_DCPLB_STATUS(); - unsigned long *mask; - int idx; - unsigned long d_data; - - nr_dcplb_miss[cpu]++; - - d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE - if (bfin_addr_dcacheable(addr)) { - d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; -# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH - d_data |= CPLB_L1_AOW | CPLB_WT; -# endif - } -#endif - - if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { - addr = L2_START; - d_data = L2_DMEMORY; - } else if (addr >= physical_mem_end) { - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { -#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM) - mask = current_rwx_mask[cpu]; - if (mask) { - int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT; - int idx = page >> 5; - int bit = 1 << (page & 31); - - if (mask[idx] & bit) - d_data |= CPLB_USER_RD; - } -#endif - } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH - && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { - addr &= ~(1 * 1024 * 1024 - 1); - d_data &= ~PAGE_SIZE_4KB; - d_data |= PAGE_SIZE_1MB; - } else - return CPLB_PROT_VIOL; - } else if (addr >= _ramend) { - d_data |= CPLB_USER_RD | CPLB_USER_WR; - if (reserved_mem_dcache_on) - d_data |= CPLB_L1_CHBL; - } else { - mask = current_rwx_mask[cpu]; - if (mask) { - int page = addr >> PAGE_SHIFT; - int idx = page >> 5; - int bit = 1 << (page & 31); - - if (mask[idx] & bit) - d_data |= CPLB_USER_RD; - - mask += page_mask_nelts; - if (mask[idx] & bit) - d_data |= CPLB_USER_WR; - } - } - idx = evict_one_dcplb(cpu); - - addr &= PAGE_MASK; - dcplb_tbl[cpu][idx].addr = addr; - dcplb_tbl[cpu][idx].data = d_data; - - _disable_dcplb(); - bfin_write32(DCPLB_DATA0 + idx * 4, d_data); - bfin_write32(DCPLB_ADDR0 + idx * 4, addr); - _enable_dcplb(); - - return 0; -} - -MGR_ATTR static noinline int icplb_miss(unsigned int cpu) -{ - unsigned long addr = bfin_read_ICPLB_FAULT_ADDR(); - int status = bfin_read_ICPLB_STATUS(); - int idx; - unsigned long i_data; - - nr_icplb_miss[cpu]++; - - /* If inside the uncached DMA region, fault. */ - if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend) - return CPLB_PROT_VIOL; - - if (status & FAULT_USERSUPV) - nr_icplb_supv_miss[cpu]++; - - /* - * First, try to find a CPLB that matches this address. If we - * find one, then the fact that we're in the miss handler means - * that the instruction crosses a page boundary. - */ - for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) { - if (icplb_tbl[cpu][idx].data & CPLB_VALID) { - unsigned long this_addr = icplb_tbl[cpu][idx].addr; - if (this_addr <= addr && this_addr + PAGE_SIZE > addr) { - addr += PAGE_SIZE; - break; - } - } - } - - i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; - -#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE - /* - * Normal RAM, and possibly the reserved memory area, are - * cacheable. - */ - if (addr < _ramend || - (addr < physical_mem_end && reserved_mem_icache_on)) - i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; -#endif - - if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { - addr = L2_START; - i_data = L2_IMEMORY; - } else if (addr >= physical_mem_end) { - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - if (!(status & FAULT_USERSUPV)) { - unsigned long *mask = current_rwx_mask[cpu]; - - if (mask) { - int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT; - int idx = page >> 5; - int bit = 1 << (page & 31); - - mask += 2 * page_mask_nelts; - if (mask[idx] & bit) - i_data |= CPLB_USER_RD; - } - } - } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH - && (status & FAULT_USERSUPV)) { - addr &= ~(1 * 1024 * 1024 - 1); - i_data &= ~PAGE_SIZE_4KB; - i_data |= PAGE_SIZE_1MB; - } else - return CPLB_PROT_VIOL; - } else if (addr >= _ramend) { - i_data |= CPLB_USER_RD; - if (reserved_mem_icache_on) - i_data |= CPLB_L1_CHBL; - } else { - /* - * Two cases to distinguish - a supervisor access must - * necessarily be for a module page; we grant it - * unconditionally (could do better here in the future). - * Otherwise, check the x bitmap of the current process. - */ - if (!(status & FAULT_USERSUPV)) { - unsigned long *mask = current_rwx_mask[cpu]; - - if (mask) { - int page = addr >> PAGE_SHIFT; - int idx = page >> 5; - int bit = 1 << (page & 31); - - mask += 2 * page_mask_nelts; - if (mask[idx] & bit) - i_data |= CPLB_USER_RD; - } - } - } - idx = evict_one_icplb(cpu); - addr &= PAGE_MASK; - icplb_tbl[cpu][idx].addr = addr; - icplb_tbl[cpu][idx].data = i_data; - - _disable_icplb(); - bfin_write32(ICPLB_DATA0 + idx * 4, i_data); - bfin_write32(ICPLB_ADDR0 + idx * 4, addr); - _enable_icplb(); - - return 0; -} - -MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu) -{ - int status = bfin_read_DCPLB_STATUS(); - - nr_dcplb_prot[cpu]++; - - if (status & FAULT_RW) { - int idx = faulting_cplb_index(status); - unsigned long data = dcplb_tbl[cpu][idx].data; - if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) && - write_permitted(status, data)) { - data |= CPLB_DIRTY; - dcplb_tbl[cpu][idx].data = data; - bfin_write32(DCPLB_DATA0 + idx * 4, data); - return 0; - } - } - return CPLB_PROT_VIOL; -} - -MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs) -{ - int cause = seqstat & 0x3f; - unsigned int cpu = raw_smp_processor_id(); - switch (cause) { - case 0x23: - return dcplb_protection_fault(cpu); - case 0x2C: - return icplb_miss(cpu); - case 0x26: - return dcplb_miss(cpu); - default: - return 1; - } -} - -void flush_switched_cplbs(unsigned int cpu) -{ - int i; - unsigned long flags; - - nr_cplb_flush[cpu]++; - - flags = hard_local_irq_save(); - _disable_icplb(); - for (i = first_switched_icplb; i < MAX_CPLBS; i++) { - icplb_tbl[cpu][i].data = 0; - bfin_write32(ICPLB_DATA0 + i * 4, 0); - } - _enable_icplb(); - - _disable_dcplb(); - for (i = first_switched_dcplb; i < MAX_CPLBS; i++) { - dcplb_tbl[cpu][i].data = 0; - bfin_write32(DCPLB_DATA0 + i * 4, 0); - } - _enable_dcplb(); - hard_local_irq_restore(flags); - -} - -void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) -{ - int i; - unsigned long addr = (unsigned long)masks; - unsigned long d_data; - unsigned long flags; - - if (!masks) { - current_rwx_mask[cpu] = masks; - return; - } - - flags = hard_local_irq_save(); - current_rwx_mask[cpu] = masks; - - if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { - addr = L2_START; - d_data = L2_DMEMORY; - } else { - d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; -#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE - d_data |= CPLB_L1_CHBL; -# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH - d_data |= CPLB_L1_AOW | CPLB_WT; -# endif -#endif - } - - _disable_dcplb(); - for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { - dcplb_tbl[cpu][i].addr = addr; - dcplb_tbl[cpu][i].data = d_data; - bfin_write32(DCPLB_DATA0 + i * 4, d_data); - bfin_write32(DCPLB_ADDR0 + i * 4, addr); - addr += PAGE_SIZE; - } - _enable_dcplb(); - hard_local_irq_restore(flags); -} diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile deleted file mode 100644 index 81baa27bc389..000000000000 --- a/arch/blackfin/kernel/cplb-nompu/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/kernel/cplb-nompu/Makefile -# - -obj-y := cplbinit.o cplbmgr.o - -CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ - -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ - -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \ - -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3 diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c deleted file mode 100644 index b49a53b583d5..000000000000 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Blackfin CPLB initialization - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include -#include -#include -#include - -struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; -struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; - -int first_switched_icplb PDT_ATTR; -int first_switched_dcplb PDT_ATTR; - -struct cplb_boundary dcplb_bounds[9] PDT_ATTR; -struct cplb_boundary icplb_bounds[9] PDT_ATTR; - -int icplb_nr_bounds PDT_ATTR; -int dcplb_nr_bounds PDT_ATTR; - -void __init generate_cplb_tables_cpu(unsigned int cpu) -{ - int i_d, i_i; - unsigned long addr; - unsigned long cplb_pageflags, cplb_pagesize; - - struct cplb_entry *d_tbl = dcplb_tbl[cpu]; - struct cplb_entry *i_tbl = icplb_tbl[cpu]; - - printk(KERN_INFO "NOMPU: setting up cplb tables\n"); - - i_d = i_i = 0; - -#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO - /* Set up the zero page. */ - d_tbl[i_d].addr = 0; - d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; - i_tbl[i_i].addr = 0; - i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB; -#endif - - /* Cover kernel memory with 4M pages. */ - addr = 0; - -#ifdef PAGE_SIZE_16MB - cplb_pageflags = PAGE_SIZE_16MB; - cplb_pagesize = SIZE_16M; -#else - cplb_pageflags = PAGE_SIZE_4MB; - cplb_pagesize = SIZE_4M; -#endif - - - for (; addr < memory_start; addr += cplb_pagesize) { - d_tbl[i_d].addr = addr; - d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags; - i_tbl[i_i].addr = addr; - i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags; - } - -#ifdef CONFIG_ROMKERNEL - /* Cover kernel XIP flash area */ -#ifdef CONFIG_BF60x - addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1); - d_tbl[i_d].addr = addr; - d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB; - i_tbl[i_i].addr = addr; - i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB; -#else - addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1); - d_tbl[i_d].addr = addr; - d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; - i_tbl[i_i].addr = addr; - i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; -#endif -#endif - - /* Cover L1 memory. One 4M area for code and data each is enough. */ - if (cpu == 0) { - if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { - d_tbl[i_d].addr = L1_DATA_A_START; - d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; - } - i_tbl[i_i].addr = L1_CODE_START; - i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; - } -#ifdef CONFIG_SMP - else { - if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { - d_tbl[i_d].addr = COREB_L1_DATA_A_START; - d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; - } - i_tbl[i_i].addr = COREB_L1_CODE_START; - i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; - } -#endif - first_switched_dcplb = i_d; - first_switched_icplb = i_i; - - BUG_ON(first_switched_dcplb > MAX_CPLBS); - BUG_ON(first_switched_icplb > MAX_CPLBS); - - while (i_d < MAX_CPLBS) - d_tbl[i_d++].data = 0; - while (i_i < MAX_CPLBS) - i_tbl[i_i++].data = 0; -} - -void __init generate_cplb_tables_all(void) -{ - unsigned long uncached_end; - int i_d, i_i; - - i_d = 0; - /* Normal RAM, including MTD FS. */ -#ifdef CONFIG_MTD_UCLINUX - uncached_end = memory_mtd_start + mtd_size; -#else - uncached_end = memory_end; -#endif - /* - * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached - * so that we don't have to use 4kB pages and cause CPLB thrashing - */ - if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION || - ((_ramend - uncached_end) >= 1 * 1024 * 1024)) - dcplb_bounds[i_d].eaddr = uncached_end; - else - dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1); - dcplb_bounds[i_d++].data = SDRAM_DGENERIC; - /* DMA uncached region. */ - if (DMA_UNCACHED_REGION) { - dcplb_bounds[i_d].eaddr = _ramend; - dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL; - } - if (_ramend != physical_mem_end) { - /* Reserved memory. */ - dcplb_bounds[i_d].eaddr = physical_mem_end; - dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ? - SDRAM_DGENERIC : SDRAM_DNON_CHBL); - } - /* Addressing hole up to the async bank. */ - dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE; - dcplb_bounds[i_d++].data = 0; - /* ASYNC banks. */ - dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; - dcplb_bounds[i_d++].data = SDRAM_EBIU; - /* Addressing hole up to BootROM. */ - dcplb_bounds[i_d].eaddr = BOOT_ROM_START; - dcplb_bounds[i_d++].data = 0; - /* BootROM -- largest one should be less than 1 meg. */ - dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH; - dcplb_bounds[i_d++].data = SDRAM_DGENERIC; - if (L2_LENGTH) { - /* Addressing hole up to L2 SRAM. */ - dcplb_bounds[i_d].eaddr = L2_START; - dcplb_bounds[i_d++].data = 0; - /* L2 SRAM. */ - dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH; - dcplb_bounds[i_d++].data = L2_DMEMORY; - } - dcplb_nr_bounds = i_d; - BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds)); - - i_i = 0; - /* Normal RAM, including MTD FS. */ - icplb_bounds[i_i].eaddr = uncached_end; - icplb_bounds[i_i++].data = SDRAM_IGENERIC; - if (_ramend != physical_mem_end) { - /* DMA uncached region. */ - if (DMA_UNCACHED_REGION) { - /* Normally this hole is caught by the async below. */ - icplb_bounds[i_i].eaddr = _ramend; - icplb_bounds[i_i++].data = 0; - } - /* Reserved memory. */ - icplb_bounds[i_i].eaddr = physical_mem_end; - icplb_bounds[i_i++].data = (reserved_mem_icache_on ? - SDRAM_IGENERIC : SDRAM_INON_CHBL); - } - /* Addressing hole up to the async bank. */ - icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE; - icplb_bounds[i_i++].data = 0; - /* ASYNC banks. */ - icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; - icplb_bounds[i_i++].data = SDRAM_EBIU; - /* Addressing hole up to BootROM. */ - icplb_bounds[i_i].eaddr = BOOT_ROM_START; - icplb_bounds[i_i++].data = 0; - /* BootROM -- largest one should be less than 1 meg. */ - icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH; - icplb_bounds[i_i++].data = SDRAM_IGENERIC; - - if (L2_LENGTH) { - /* Addressing hole up to L2 SRAM. */ - icplb_bounds[i_i].eaddr = L2_START; - icplb_bounds[i_i++].data = 0; - /* L2 SRAM. */ - icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH; - icplb_bounds[i_i++].data = L2_IMEMORY; - } - icplb_nr_bounds = i_i; - BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds)); -} diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c deleted file mode 100644 index 79cc0f6dcdd5..000000000000 --- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c - * Author: Michael McTernan - * - * Description: CPLB miss handler. - * - * Modified: - * Copyright 2008 Airvana Inc. - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include - -/* - * WARNING - * - * This file is compiled with certain -ffixed-reg options. We have to - * make sure not to call any functions here that could clobber these - * registers. - */ - -int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS]; -int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS]; -int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS]; - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -#define MGR_ATTR __attribute__((l1_text)) -#else -#define MGR_ATTR -#endif - -static inline void write_dcplb_data(int cpu, int idx, unsigned long data, - unsigned long addr) -{ - _disable_dcplb(); - bfin_write32(DCPLB_DATA0 + idx * 4, data); - bfin_write32(DCPLB_ADDR0 + idx * 4, addr); - _enable_dcplb(); - -#ifdef CONFIG_CPLB_INFO - dcplb_tbl[cpu][idx].addr = addr; - dcplb_tbl[cpu][idx].data = data; -#endif -} - -static inline void write_icplb_data(int cpu, int idx, unsigned long data, - unsigned long addr) -{ - _disable_icplb(); - bfin_write32(ICPLB_DATA0 + idx * 4, data); - bfin_write32(ICPLB_ADDR0 + idx * 4, addr); - _enable_icplb(); - -#ifdef CONFIG_CPLB_INFO - icplb_tbl[cpu][idx].addr = addr; - icplb_tbl[cpu][idx].data = data; -#endif -} - -/* Counters to implement round-robin replacement. */ -static int icplb_rr_index[NR_CPUS] PDT_ATTR; -static int dcplb_rr_index[NR_CPUS] PDT_ATTR; - -/* - * Find an ICPLB entry to be evicted and return its index. - */ -static int evict_one_icplb(int cpu) -{ - int i = first_switched_icplb + icplb_rr_index[cpu]; - if (i >= MAX_CPLBS) { - i -= MAX_CPLBS - first_switched_icplb; - icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb; - } - icplb_rr_index[cpu]++; - return i; -} - -static int evict_one_dcplb(int cpu) -{ - int i = first_switched_dcplb + dcplb_rr_index[cpu]; - if (i >= MAX_CPLBS) { - i -= MAX_CPLBS - first_switched_dcplb; - dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb; - } - dcplb_rr_index[cpu]++; - return i; -} - -MGR_ATTR static int icplb_miss(int cpu) -{ - unsigned long addr = bfin_read_ICPLB_FAULT_ADDR(); - int status = bfin_read_ICPLB_STATUS(); - int idx; - unsigned long i_data, base, addr1, eaddr; - - nr_icplb_miss[cpu]++; - if (unlikely(status & FAULT_USERSUPV)) - nr_icplb_supv_miss[cpu]++; - - base = 0; - idx = 0; - do { - eaddr = icplb_bounds[idx].eaddr; - if (addr < eaddr) - break; - base = eaddr; - } while (++idx < icplb_nr_bounds); - - if (unlikely(idx == icplb_nr_bounds)) - return CPLB_NO_ADDR_MATCH; - - i_data = icplb_bounds[idx].data; - if (unlikely(i_data == 0)) - return CPLB_NO_ADDR_MATCH; - - addr1 = addr & ~(SIZE_4M - 1); - addr &= ~(SIZE_1M - 1); - i_data |= PAGE_SIZE_1MB; - if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) { - /* - * This works because - * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB. - */ - i_data |= PAGE_SIZE_4MB; - addr = addr1; - } - - /* Pick entry to evict */ - idx = evict_one_icplb(cpu); - - write_icplb_data(cpu, idx, i_data, addr); - - return CPLB_RELOADED; -} - -MGR_ATTR static int dcplb_miss(int cpu) -{ - unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); - int status = bfin_read_DCPLB_STATUS(); - int idx; - unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags; - - nr_dcplb_miss[cpu]++; - if (unlikely(status & FAULT_USERSUPV)) - nr_dcplb_supv_miss[cpu]++; - - base = 0; - idx = 0; - do { - eaddr = dcplb_bounds[idx].eaddr; - if (addr < eaddr) - break; - base = eaddr; - } while (++idx < dcplb_nr_bounds); - - if (unlikely(idx == dcplb_nr_bounds)) - return CPLB_NO_ADDR_MATCH; - - d_data = dcplb_bounds[idx].data; - if (unlikely(d_data == 0)) - return CPLB_NO_ADDR_MATCH; - - addr &= ~(SIZE_1M - 1); - d_data |= PAGE_SIZE_1MB; - - /* BF60x support large than 4M CPLB page size */ -#ifdef PAGE_SIZE_16MB - cplb_pageflags = PAGE_SIZE_16MB; - cplb_pagesize = SIZE_16M; -#else - cplb_pageflags = PAGE_SIZE_4MB; - cplb_pagesize = SIZE_4M; -#endif - -find_pagesize: - addr1 = addr & ~(cplb_pagesize - 1); - if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) { - /* - * This works because - * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB. - */ - d_data |= cplb_pageflags; - addr = addr1; - goto found_pagesize; - } else { - if (cplb_pagesize > SIZE_4M) { - cplb_pageflags = PAGE_SIZE_4MB; - cplb_pagesize = SIZE_4M; - goto find_pagesize; - } - } - -found_pagesize: -#ifdef CONFIG_BF60x - if ((addr >= ASYNC_BANK0_BASE) - && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)) - d_data |= PAGE_SIZE_64MB; -#endif - - /* Pick entry to evict */ - idx = evict_one_dcplb(cpu); - - write_dcplb_data(cpu, idx, d_data, addr); - - return CPLB_RELOADED; -} - -MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs) -{ - int cause = seqstat & 0x3f; - unsigned int cpu = raw_smp_processor_id(); - switch (cause) { - case VEC_CPLB_I_M: - return icplb_miss(cpu); - case VEC_CPLB_M: - return dcplb_miss(cpu); - default: - return CPLB_UNKNOWN_ERR; - } -} diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c deleted file mode 100644 index 5b80d59e66e5..000000000000 --- a/arch/blackfin/kernel/cplbinfo.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * arch/blackfin/kernel/cplbinfo.c - display CPLB status - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -static char const page_strtbl[][4] = { - "1K", "4K", "1M", "4M", -#ifdef CONFIG_BF60x - "16K", "64K", "16M", "64M", -#endif -}; -#define page(flags) (((flags) & 0x70000) >> 16) -#define strpage(flags) page_strtbl[page(flags)] - -struct cplbinfo_data { - loff_t pos; - char cplb_type; - u32 mem_control; - struct cplb_entry *tbl; - int switched; -}; - -static void cplbinfo_print_header(struct seq_file *m) -{ - seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n"); -} - -static int cplbinfo_nomore(struct cplbinfo_data *cdata) -{ - return cdata->pos >= MAX_CPLBS; -} - -static int cplbinfo_show(struct seq_file *m, void *p) -{ - struct cplbinfo_data *cdata; - unsigned long data, addr; - loff_t pos; - - cdata = p; - pos = cdata->pos; - addr = cdata->tbl[pos].addr; - data = cdata->tbl[pos].data; - - seq_printf(m, - "%d\t0x%08lx\t%05lx\t%s\t%c\t%c\t%c\t%c\n", - (int)pos, addr, data, strpage(data), - (data & CPLB_USER_RD) ? 'Y' : 'N', - (data & CPLB_USER_WR) ? 'Y' : 'N', - (data & CPLB_SUPV_WR) ? 'Y' : 'N', - pos < cdata->switched ? 'N' : 'Y'); - - return 0; -} - -static void cplbinfo_seq_init(struct cplbinfo_data *cdata, unsigned int cpu) -{ - if (cdata->cplb_type == 'I') { - cdata->mem_control = bfin_read_IMEM_CONTROL(); - cdata->tbl = icplb_tbl[cpu]; - cdata->switched = first_switched_icplb; - } else { - cdata->mem_control = bfin_read_DMEM_CONTROL(); - cdata->tbl = dcplb_tbl[cpu]; - cdata->switched = first_switched_dcplb; - } -} - -static void *cplbinfo_start(struct seq_file *m, loff_t *pos) -{ - struct cplbinfo_data *cdata = m->private; - - if (!*pos) { - seq_printf(m, "%cCPLBs are %sabled: 0x%x\n", cdata->cplb_type, - (cdata->mem_control & ENDCPLB ? "en" : "dis"), - cdata->mem_control); - cplbinfo_print_header(m); - } else if (cplbinfo_nomore(cdata)) - return NULL; - - get_cpu(); - return cdata; -} - -static void *cplbinfo_next(struct seq_file *m, void *p, loff_t *pos) -{ - struct cplbinfo_data *cdata = p; - cdata->pos = ++(*pos); - if (cplbinfo_nomore(cdata)) - return NULL; - else - return cdata; -} - -static void cplbinfo_stop(struct seq_file *m, void *p) -{ - put_cpu(); -} - -static const struct seq_operations cplbinfo_sops = { - .start = cplbinfo_start, - .next = cplbinfo_next, - .stop = cplbinfo_stop, - .show = cplbinfo_show, -}; - -#define CPLBINFO_DCPLB_FLAG 0x80000000 - -static int cplbinfo_open(struct inode *inode, struct file *file) -{ - char cplb_type; - unsigned int cpu = (unsigned long)PDE_DATA(file_inode(file)); - int ret; - struct seq_file *m; - struct cplbinfo_data *cdata; - - cplb_type = cpu & CPLBINFO_DCPLB_FLAG ? 'D' : 'I'; - cpu &= ~CPLBINFO_DCPLB_FLAG; - - if (!cpu_online(cpu)) - return -ENODEV; - - ret = seq_open_private(file, &cplbinfo_sops, sizeof(*cdata)); - if (ret) - return ret; - m = file->private_data; - cdata = m->private; - - cdata->pos = 0; - cdata->cplb_type = cplb_type; - cplbinfo_seq_init(cdata, cpu); - - return 0; -} - -static const struct file_operations cplbinfo_fops = { - .open = cplbinfo_open, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release_private, -}; - -static int __init cplbinfo_init(void) -{ - struct proc_dir_entry *cplb_dir, *cpu_dir; - char buf[10]; - unsigned int cpu; - - cplb_dir = proc_mkdir("cplbinfo", NULL); - if (!cplb_dir) - return -ENOMEM; - - for_each_possible_cpu(cpu) { - sprintf(buf, "cpu%i", cpu); - cpu_dir = proc_mkdir(buf, cplb_dir); - if (!cpu_dir) - return -ENOMEM; - - proc_create_data("icplb", S_IRUGO, cpu_dir, &cplbinfo_fops, - (void *)cpu); - proc_create_data("dcplb", S_IRUGO, cpu_dir, &cplbinfo_fops, - (void *)(cpu | CPLBINFO_DCPLB_FLAG)); - } - - return 0; -} -late_initcall(cplbinfo_init); diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c deleted file mode 100644 index 194773ce109e..000000000000 --- a/arch/blackfin/kernel/debug-mmrs.c +++ /dev/null @@ -1,1891 +0,0 @@ -/* - * debugfs interface to core/system MMRs - * - * Copyright 2007-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Common code defines PORT_MUX on us, so redirect the MMR back locally */ -#ifdef BFIN_PORT_MUX -#undef PORT_MUX -#define PORT_MUX BFIN_PORT_MUX -#endif - -#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr)) -#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR) -#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR) -#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR) - -#define D_RO(name, bits) d_RO(#name, bits, name) -#define D_WO(name, bits) d_WO(#name, bits, name) -#define D32(name) d(#name, 32, name) -#define D16(name) d(#name, 16, name) - -#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr) -#define __REGS(peri, sname, rname) \ - do { \ - struct bfin_##peri##_regs r; \ - void *addr = (void *)(base + REGS_OFF(peri, rname)); \ - strcpy(_buf, sname); \ - if (sizeof(r.rname) == 2) \ - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \ - else \ - debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \ - } while (0) -#define REGS_STR_PFX(buf, pfx, num) \ - ({ \ - buf + (num >= 0 ? \ - sprintf(buf, #pfx "%i_", num) : \ - sprintf(buf, #pfx "_")); \ - }) -#define REGS_STR_PFX_C(buf, pfx, num) \ - ({ \ - buf + (num >= 0 ? \ - sprintf(buf, #pfx "%c_", 'A' + num) : \ - sprintf(buf, #pfx "_")); \ - }) - -/* - * Core registers (not memory mapped) - */ -extern u32 last_seqstat; - -static int debug_cclk_get(void *data, u64 *val) -{ - *val = get_cclk(); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n"); - -static int debug_sclk_get(void *data, u64 *val) -{ - *val = get_sclk(); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n"); - -#define DEFINE_SYSREG(sr, pre, post) \ -static int sysreg_##sr##_get(void *data, u64 *val) \ -{ \ - unsigned long tmp; \ - pre; \ - __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \ - *val = tmp; \ - return 0; \ -} \ -static int sysreg_##sr##_set(void *data, u64 val) \ -{ \ - unsigned long tmp = val; \ - __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \ - post; \ - return 0; \ -} \ -DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n") - -DEFINE_SYSREG(cycles, , ); -DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), ); -DEFINE_SYSREG(emudat, , ); -DEFINE_SYSREG(seqstat, , ); -DEFINE_SYSREG(syscfg, , CSYNC()); -#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr) - -#ifndef CONFIG_BF60x -/* - * CAN - */ -#define CAN_OFF(mmr) REGS_OFF(can, mmr) -#define __CAN(uname, lname) __REGS(can, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num) -{ - static struct dentry *am, *mb; - int i, j; - char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num); - - if (!am) { - am = debugfs_create_dir("am", parent); - mb = debugfs_create_dir("mb", parent); - } - - __CAN(MC1, mc1); - __CAN(MD1, md1); - __CAN(TRS1, trs1); - __CAN(TRR1, trr1); - __CAN(TA1, ta1); - __CAN(AA1, aa1); - __CAN(RMP1, rmp1); - __CAN(RML1, rml1); - __CAN(MBTIF1, mbtif1); - __CAN(MBRIF1, mbrif1); - __CAN(MBIM1, mbim1); - __CAN(RFH1, rfh1); - __CAN(OPSS1, opss1); - - __CAN(MC2, mc2); - __CAN(MD2, md2); - __CAN(TRS2, trs2); - __CAN(TRR2, trr2); - __CAN(TA2, ta2); - __CAN(AA2, aa2); - __CAN(RMP2, rmp2); - __CAN(RML2, rml2); - __CAN(MBTIF2, mbtif2); - __CAN(MBRIF2, mbrif2); - __CAN(MBIM2, mbim2); - __CAN(RFH2, rfh2); - __CAN(OPSS2, opss2); - - __CAN(CLOCK, clock); - __CAN(TIMING, timing); - __CAN(DEBUG, debug); - __CAN(STATUS, status); - __CAN(CEC, cec); - __CAN(GIS, gis); - __CAN(GIM, gim); - __CAN(GIF, gif); - __CAN(CONTROL, control); - __CAN(INTR, intr); - __CAN(VERSION, version); - __CAN(MBTD, mbtd); - __CAN(EWR, ewr); - __CAN(ESR, esr); - /*__CAN(UCREG, ucreg); no longer exists */ - __CAN(UCCNT, uccnt); - __CAN(UCRC, ucrc); - __CAN(UCCNF, uccnf); - __CAN(VERSION2, version2); - - for (i = 0; i < 32; ++i) { - sprintf(_buf, "AM%02iL", i); - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am, - (u16 *)(base + CAN_OFF(msk[i].aml))); - sprintf(_buf, "AM%02iH", i); - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am, - (u16 *)(base + CAN_OFF(msk[i].amh))); - - for (j = 0; j < 3; ++j) { - sprintf(_buf, "MB%02i_DATA%i", i, j); - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, - (u16 *)(base + CAN_OFF(chl[i].data[j*2]))); - } - sprintf(_buf, "MB%02i_LENGTH", i); - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, - (u16 *)(base + CAN_OFF(chl[i].dlc))); - sprintf(_buf, "MB%02i_TIMESTAMP", i); - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, - (u16 *)(base + CAN_OFF(chl[i].tsv))); - sprintf(_buf, "MB%02i_ID0", i); - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, - (u16 *)(base + CAN_OFF(chl[i].id0))); - sprintf(_buf, "MB%02i_ID1", i); - debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb, - (u16 *)(base + CAN_OFF(chl[i].id1))); - } -} -#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num) - -/* - * DMA - */ -#define __DMA(uname, lname) __REGS(dma, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx) -{ - char buf[32], *_buf; - - if (mdma) - _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num); - else - _buf = buf + sprintf(buf, "%s%i_", pfx, num); - - __DMA(NEXT_DESC_PTR, next_desc_ptr); - __DMA(START_ADDR, start_addr); - __DMA(CONFIG, config); - __DMA(X_COUNT, x_count); - __DMA(X_MODIFY, x_modify); - __DMA(Y_COUNT, y_count); - __DMA(Y_MODIFY, y_modify); - __DMA(CURR_DESC_PTR, curr_desc_ptr); - __DMA(CURR_ADDR, curr_addr); - __DMA(IRQ_STATUS, irq_status); -#ifndef CONFIG_BF60x - if (strcmp(pfx, "IMDMA") != 0) - __DMA(PERIPHERAL_MAP, peripheral_map); -#endif - __DMA(CURR_X_COUNT, curr_x_count); - __DMA(CURR_Y_COUNT, curr_y_count); -} -#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA") -#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "") -#define _MDMA(num, x) \ - do { \ - _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \ - _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \ - } while (0) -#define MDMA(num) _MDMA(num, M) -#define IMDMA(num) _MDMA(num, IM) - -/* - * EPPI - */ -#define __EPPI(uname, lname) __REGS(eppi, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num); - __EPPI(STATUS, status); - __EPPI(HCOUNT, hcount); - __EPPI(HDELAY, hdelay); - __EPPI(VCOUNT, vcount); - __EPPI(VDELAY, vdelay); - __EPPI(FRAME, frame); - __EPPI(LINE, line); - __EPPI(CLKDIV, clkdiv); - __EPPI(CONTROL, control); - __EPPI(FS1W_HBL, fs1w_hbl); - __EPPI(FS1P_AVPL, fs1p_avpl); - __EPPI(FS2W_LVB, fs2w_lvb); - __EPPI(FS2P_LAVF, fs2p_lavf); - __EPPI(CLIP, clip); -} -#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num) - -/* - * General Purpose Timers - */ -#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num); - __GPTIMER(CONFIG, config); - __GPTIMER(COUNTER, counter); - __GPTIMER(PERIOD, period); - __GPTIMER(WIDTH, width); -} -#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num) - -#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr) -#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf; - - if (num == -1) { - _buf = buf + sprintf(buf, "TIMER_"); - __GPTIMER_GROUP(ENABLE, enable); - __GPTIMER_GROUP(DISABLE, disable); - __GPTIMER_GROUP(STATUS, status); - } else { - /* These MMRs are a bit odd as the group # is a suffix */ - _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num); - d(buf, 16, base + GPTIMER_GROUP_OFF(enable)); - - _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num); - d(buf, 16, base + GPTIMER_GROUP_OFF(disable)); - - _buf = buf + sprintf(buf, "TIMER_STATUS%i", num); - d(buf, 32, base + GPTIMER_GROUP_OFF(status)); - } -} -#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num) - -/* - * Handshake MDMA - */ -#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num); - __HMDMA(CONTROL, control); - __HMDMA(ECINIT, ecinit); - __HMDMA(BCINIT, bcinit); - __HMDMA(ECURGENT, ecurgent); - __HMDMA(ECOVERFLOW, ecoverflow); - __HMDMA(ECOUNT, ecount); - __HMDMA(BCOUNT, bcount); -} -#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num) - -/* - * Peripheral Interrupts (PINT/GPIO) - */ -#ifdef PINT0_MASK_SET -#define __PINT(uname, lname) __REGS(pint, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num); - __PINT(MASK_SET, mask_set); - __PINT(MASK_CLEAR, mask_clear); - __PINT(REQUEST, request); - __PINT(ASSIGN, assign); - __PINT(EDGE_SET, edge_set); - __PINT(EDGE_CLEAR, edge_clear); - __PINT(INVERT_SET, invert_set); - __PINT(INVERT_CLEAR, invert_clear); - __PINT(PINSTATE, pinstate); - __PINT(LATCH, latch); -} -#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num) -#endif - -/* - * Port/GPIO - */ -#define bfin_gpio_regs gpio_port_t -#define __PORT(uname, lname) __REGS(gpio, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf; -#ifdef __ADSPBF54x__ - _buf = REGS_STR_PFX_C(buf, PORT, num); - __PORT(FER, port_fer); - __PORT(SET, data_set); - __PORT(CLEAR, data_clear); - __PORT(DIR_SET, dir_set); - __PORT(DIR_CLEAR, dir_clear); - __PORT(INEN, inen); - __PORT(MUX, port_mux); -#else - _buf = buf + sprintf(buf, "PORT%cIO_", num); - __PORT(CLEAR, data_clear); - __PORT(SET, data_set); - __PORT(TOGGLE, toggle); - __PORT(MASKA, maska); - __PORT(MASKA_CLEAR, maska_clear); - __PORT(MASKA_SET, maska_set); - __PORT(MASKA_TOGGLE, maska_toggle); - __PORT(MASKB, maskb); - __PORT(MASKB_CLEAR, maskb_clear); - __PORT(MASKB_SET, maskb_set); - __PORT(MASKB_TOGGLE, maskb_toggle); - __PORT(DIR, dir); - __PORT(POLAR, polar); - __PORT(EDGE, edge); - __PORT(BOTH, both); - __PORT(INEN, inen); -#endif - _buf[-1] = '\0'; - d(buf, 16, base + REGS_OFF(gpio, data)); -} -#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num) - -/* - * PPI - */ -#define __PPI(uname, lname) __REGS(ppi, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num); - __PPI(CONTROL, control); - __PPI(STATUS, status); - __PPI(COUNT, count); - __PPI(DELAY, delay); - __PPI(FRAME, frame); -} -#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num) - -/* - * SPI - */ -#define __SPI(uname, lname) __REGS(spi, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num); - __SPI(CTL, ctl); - __SPI(FLG, flg); - __SPI(STAT, stat); - __SPI(TDBR, tdbr); - __SPI(RDBR, rdbr); - __SPI(BAUD, baud); - __SPI(SHADOW, shadow); -} -#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num) - -/* - * SPORT - */ -static inline int sport_width(void *mmr) -{ - unsigned long lmmr = (unsigned long)mmr; - if ((lmmr & 0xff) == 0x10) - /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */ - lmmr -= 0xc; - else - /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */ - lmmr += 0xc; - /* extract SLEN field from control register 2 and add 1 */ - return (bfin_read16(lmmr) & 0x1f) + 1; -} -static int sport_set(void *mmr, u64 val) -{ - unsigned long flags; - local_irq_save(flags); - if (sport_width(mmr) <= 16) - bfin_write16(mmr, val); - else - bfin_write32(mmr, val); - local_irq_restore(flags); - return 0; -} -static int sport_get(void *mmr, u64 *val) -{ - unsigned long flags; - local_irq_save(flags); - if (sport_width(mmr) <= 16) - *val = bfin_read16(mmr); - else - *val = bfin_read32(mmr); - local_irq_restore(flags); - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n"); -/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/ -DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n"); -#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1) -#define _D_SPORT(name, perms, fops) \ - do { \ - strcpy(_buf, #name); \ - debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \ - } while (0) -#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport) -#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro) -#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo) -#define __SPORT(name, bits) \ - do { \ - strcpy(_buf, #name); \ - debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \ - } while (0) -static void __init __maybe_unused -bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num); - __SPORT(CHNL, 16); - __SPORT(MCMC1, 16); - __SPORT(MCMC2, 16); - __SPORT(MRCS0, 32); - __SPORT(MRCS1, 32); - __SPORT(MRCS2, 32); - __SPORT(MRCS3, 32); - __SPORT(MTCS0, 32); - __SPORT(MTCS1, 32); - __SPORT(MTCS2, 32); - __SPORT(MTCS3, 32); - __SPORT(RCLKDIV, 16); - __SPORT(RCR1, 16); - __SPORT(RCR2, 16); - __SPORT(RFSDIV, 16); - __SPORT_RW(RX); - __SPORT(STAT, 16); - __SPORT(TCLKDIV, 16); - __SPORT(TCR1, 16); - __SPORT(TCR2, 16); - __SPORT(TFSDIV, 16); - __SPORT_WO(TX); -} -#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num) - -/* - * TWI - */ -#define __TWI(uname, lname) __REGS(twi, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num); - __TWI(CLKDIV, clkdiv); - __TWI(CONTROL, control); - __TWI(SLAVE_CTL, slave_ctl); - __TWI(SLAVE_STAT, slave_stat); - __TWI(SLAVE_ADDR, slave_addr); - __TWI(MASTER_CTL, master_ctl); - __TWI(MASTER_STAT, master_stat); - __TWI(MASTER_ADDR, master_addr); - __TWI(INT_STAT, int_stat); - __TWI(INT_MASK, int_mask); - __TWI(FIFO_CTL, fifo_ctl); - __TWI(FIFO_STAT, fifo_stat); - __TWI(XMT_DATA8, xmt_data8); - __TWI(XMT_DATA16, xmt_data16); - __TWI(RCV_DATA8, rcv_data8); - __TWI(RCV_DATA16, rcv_data16); -} -#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num) - -/* - * UART - */ -#define __UART(uname, lname) __REGS(uart, #uname, lname) -static void __init __maybe_unused -bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num) -{ - char buf[32], *_buf = REGS_STR_PFX(buf, UART, num); -#ifdef BFIN_UART_BF54X_STYLE - __UART(DLL, dll); - __UART(DLH, dlh); - __UART(GCTL, gctl); - __UART(LCR, lcr); - __UART(MCR, mcr); - __UART(LSR, lsr); - __UART(MSR, msr); - __UART(SCR, scr); - __UART(IER_SET, ier_set); - __UART(IER_CLEAR, ier_clear); - __UART(THR, thr); - __UART(RBR, rbr); -#else - __UART(DLL, dll); - __UART(THR, thr); - __UART(RBR, rbr); - __UART(DLH, dlh); - __UART(IER, ier); - __UART(IIR, iir); - __UART(LCR, lcr); - __UART(MCR, mcr); - __UART(LSR, lsr); - __UART(MSR, msr); - __UART(SCR, scr); - __UART(GCTL, gctl); -#endif -} -#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num) -#endif /* CONFIG_BF60x */ -/* - * The actual debugfs generation - */ -static struct dentry *debug_mmrs_dentry; - -static int __init bfin_debug_mmrs_init(void) -{ - struct dentry *top, *parent; - - pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n"); - - top = debugfs_create_dir("blackfin", NULL); - if (top == NULL) - return -1; - - parent = debugfs_create_dir("core_regs", top); - debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk); - debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk); - debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat); - D_SYSREG(cycles); - D_SYSREG(cycles2); - D_SYSREG(emudat); - D_SYSREG(seqstat); - D_SYSREG(syscfg); - - /* Core MMRs */ - parent = debugfs_create_dir("ctimer", top); - D32(TCNTL); - D32(TCOUNT); - D32(TPERIOD); - D32(TSCALE); - - parent = debugfs_create_dir("cec", top); - D32(EVT0); - D32(EVT1); - D32(EVT2); - D32(EVT3); - D32(EVT4); - D32(EVT5); - D32(EVT6); - D32(EVT7); - D32(EVT8); - D32(EVT9); - D32(EVT10); - D32(EVT11); - D32(EVT12); - D32(EVT13); - D32(EVT14); - D32(EVT15); - D32(EVT_OVERRIDE); - D32(IMASK); - D32(IPEND); - D32(ILAT); - D32(IPRIO); - - parent = debugfs_create_dir("debug", top); - D32(DBGSTAT); - D32(DSPID); - - parent = debugfs_create_dir("mmu", top); - D32(SRAM_BASE_ADDRESS); - D32(DCPLB_ADDR0); - D32(DCPLB_ADDR10); - D32(DCPLB_ADDR11); - D32(DCPLB_ADDR12); - D32(DCPLB_ADDR13); - D32(DCPLB_ADDR14); - D32(DCPLB_ADDR15); - D32(DCPLB_ADDR1); - D32(DCPLB_ADDR2); - D32(DCPLB_ADDR3); - D32(DCPLB_ADDR4); - D32(DCPLB_ADDR5); - D32(DCPLB_ADDR6); - D32(DCPLB_ADDR7); - D32(DCPLB_ADDR8); - D32(DCPLB_ADDR9); - D32(DCPLB_DATA0); - D32(DCPLB_DATA10); - D32(DCPLB_DATA11); - D32(DCPLB_DATA12); - D32(DCPLB_DATA13); - D32(DCPLB_DATA14); - D32(DCPLB_DATA15); - D32(DCPLB_DATA1); - D32(DCPLB_DATA2); - D32(DCPLB_DATA3); - D32(DCPLB_DATA4); - D32(DCPLB_DATA5); - D32(DCPLB_DATA6); - D32(DCPLB_DATA7); - D32(DCPLB_DATA8); - D32(DCPLB_DATA9); - D32(DCPLB_FAULT_ADDR); - D32(DCPLB_STATUS); - D32(DMEM_CONTROL); - D32(DTEST_COMMAND); - D32(DTEST_DATA0); - D32(DTEST_DATA1); - - D32(ICPLB_ADDR0); - D32(ICPLB_ADDR1); - D32(ICPLB_ADDR2); - D32(ICPLB_ADDR3); - D32(ICPLB_ADDR4); - D32(ICPLB_ADDR5); - D32(ICPLB_ADDR6); - D32(ICPLB_ADDR7); - D32(ICPLB_ADDR8); - D32(ICPLB_ADDR9); - D32(ICPLB_ADDR10); - D32(ICPLB_ADDR11); - D32(ICPLB_ADDR12); - D32(ICPLB_ADDR13); - D32(ICPLB_ADDR14); - D32(ICPLB_ADDR15); - D32(ICPLB_DATA0); - D32(ICPLB_DATA1); - D32(ICPLB_DATA2); - D32(ICPLB_DATA3); - D32(ICPLB_DATA4); - D32(ICPLB_DATA5); - D32(ICPLB_DATA6); - D32(ICPLB_DATA7); - D32(ICPLB_DATA8); - D32(ICPLB_DATA9); - D32(ICPLB_DATA10); - D32(ICPLB_DATA11); - D32(ICPLB_DATA12); - D32(ICPLB_DATA13); - D32(ICPLB_DATA14); - D32(ICPLB_DATA15); - D32(ICPLB_FAULT_ADDR); - D32(ICPLB_STATUS); - D32(IMEM_CONTROL); - if (!ANOMALY_05000481) { - D32(ITEST_COMMAND); - D32(ITEST_DATA0); - D32(ITEST_DATA1); - } - - parent = debugfs_create_dir("perf", top); - D32(PFCNTR0); - D32(PFCNTR1); - D32(PFCTL); - - parent = debugfs_create_dir("trace", top); - D32(TBUF); - D32(TBUFCTL); - D32(TBUFSTAT); - - parent = debugfs_create_dir("watchpoint", top); - D32(WPIACTL); - D32(WPIA0); - D32(WPIA1); - D32(WPIA2); - D32(WPIA3); - D32(WPIA4); - D32(WPIA5); - D32(WPIACNT0); - D32(WPIACNT1); - D32(WPIACNT2); - D32(WPIACNT3); - D32(WPIACNT4); - D32(WPIACNT5); - D32(WPDACTL); - D32(WPDA0); - D32(WPDA1); - D32(WPDACNT0); - D32(WPDACNT1); - D32(WPSTAT); -#ifndef CONFIG_BF60x - /* System MMRs */ -#ifdef ATAPI_CONTROL - parent = debugfs_create_dir("atapi", top); - D16(ATAPI_CONTROL); - D16(ATAPI_DEV_ADDR); - D16(ATAPI_DEV_RXBUF); - D16(ATAPI_DEV_TXBUF); - D16(ATAPI_DMA_TFRCNT); - D16(ATAPI_INT_MASK); - D16(ATAPI_INT_STATUS); - D16(ATAPI_LINE_STATUS); - D16(ATAPI_MULTI_TIM_0); - D16(ATAPI_MULTI_TIM_1); - D16(ATAPI_MULTI_TIM_2); - D16(ATAPI_PIO_TFRCNT); - D16(ATAPI_PIO_TIM_0); - D16(ATAPI_PIO_TIM_1); - D16(ATAPI_REG_TIM_0); - D16(ATAPI_SM_STATE); - D16(ATAPI_STATUS); - D16(ATAPI_TERMINATE); - D16(ATAPI_UDMAOUT_TFRCNT); - D16(ATAPI_ULTRA_TIM_0); - D16(ATAPI_ULTRA_TIM_1); - D16(ATAPI_ULTRA_TIM_2); - D16(ATAPI_ULTRA_TIM_3); - D16(ATAPI_UMAIN_TFRCNT); - D16(ATAPI_XFER_LEN); -#endif - -#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1) - parent = debugfs_create_dir("can", top); -# ifdef CAN_MC1 - bfin_debug_mmrs_can(parent, CAN_MC1, -1); -# endif -# ifdef CAN0_MC1 - CAN(0); -# endif -# ifdef CAN1_MC1 - CAN(1); -# endif -#endif - -#ifdef CNT_COMMAND - parent = debugfs_create_dir("counter", top); - D16(CNT_COMMAND); - D16(CNT_CONFIG); - D32(CNT_COUNTER); - D16(CNT_DEBOUNCE); - D16(CNT_IMASK); - D32(CNT_MAX); - D32(CNT_MIN); - D16(CNT_STATUS); -#endif - - parent = debugfs_create_dir("dmac", top); -#ifdef DMAC_TC_CNT - D16(DMAC_TC_CNT); - D16(DMAC_TC_PER); -#endif -#ifdef DMAC0_TC_CNT - D16(DMAC0_TC_CNT); - D16(DMAC0_TC_PER); -#endif -#ifdef DMAC1_TC_CNT - D16(DMAC1_TC_CNT); - D16(DMAC1_TC_PER); -#endif -#ifdef DMAC1_PERIMUX - D16(DMAC1_PERIMUX); -#endif - -#ifdef __ADSPBF561__ - /* XXX: should rewrite the MMR map */ -# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR -# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR -# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR -# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR -# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR -# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR -# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR -# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR -# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR -# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR -# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR -# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR -# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR -# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR -# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR -# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR -# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR -# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR -# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR -# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR -# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR -# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR -# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR -# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR -#endif - parent = debugfs_create_dir("dma", top); - DMA(0); - DMA(1); - DMA(1); - DMA(2); - DMA(3); - DMA(4); - DMA(5); - DMA(6); - DMA(7); -#ifdef DMA8_NEXT_DESC_PTR - DMA(8); - DMA(9); - DMA(10); - DMA(11); -#endif -#ifdef DMA12_NEXT_DESC_PTR - DMA(12); - DMA(13); - DMA(14); - DMA(15); - DMA(16); - DMA(17); - DMA(18); - DMA(19); -#endif -#ifdef DMA20_NEXT_DESC_PTR - DMA(20); - DMA(21); - DMA(22); - DMA(23); -#endif - - parent = debugfs_create_dir("ebiu_amc", top); - D32(EBIU_AMBCTL0); - D32(EBIU_AMBCTL1); - D16(EBIU_AMGCTL); -#ifdef EBIU_MBSCTL - D16(EBIU_MBSCTL); - D32(EBIU_ARBSTAT); - D32(EBIU_MODE); - D16(EBIU_FCTL); -#endif - -#ifdef EBIU_SDGCTL - parent = debugfs_create_dir("ebiu_sdram", top); -# ifdef __ADSPBF561__ - D32(EBIU_SDBCTL); -# else - D16(EBIU_SDBCTL); -# endif - D32(EBIU_SDGCTL); - D16(EBIU_SDRRC); - D16(EBIU_SDSTAT); -#endif - -#ifdef EBIU_DDRACCT - parent = debugfs_create_dir("ebiu_ddr", top); - D32(EBIU_DDRACCT); - D32(EBIU_DDRARCT); - D32(EBIU_DDRBRC0); - D32(EBIU_DDRBRC1); - D32(EBIU_DDRBRC2); - D32(EBIU_DDRBRC3); - D32(EBIU_DDRBRC4); - D32(EBIU_DDRBRC5); - D32(EBIU_DDRBRC6); - D32(EBIU_DDRBRC7); - D32(EBIU_DDRBWC0); - D32(EBIU_DDRBWC1); - D32(EBIU_DDRBWC2); - D32(EBIU_DDRBWC3); - D32(EBIU_DDRBWC4); - D32(EBIU_DDRBWC5); - D32(EBIU_DDRBWC6); - D32(EBIU_DDRBWC7); - D32(EBIU_DDRCTL0); - D32(EBIU_DDRCTL1); - D32(EBIU_DDRCTL2); - D32(EBIU_DDRCTL3); - D32(EBIU_DDRGC0); - D32(EBIU_DDRGC1); - D32(EBIU_DDRGC2); - D32(EBIU_DDRGC3); - D32(EBIU_DDRMCCL); - D32(EBIU_DDRMCEN); - D32(EBIU_DDRQUE); - D32(EBIU_DDRTACT); - D32(EBIU_ERRADD); - D16(EBIU_ERRMST); - D16(EBIU_RSTCTL); -#endif - -#ifdef EMAC_ADDRHI - parent = debugfs_create_dir("emac", top); - D32(EMAC_ADDRHI); - D32(EMAC_ADDRLO); - D32(EMAC_FLC); - D32(EMAC_HASHHI); - D32(EMAC_HASHLO); - D32(EMAC_MMC_CTL); - D32(EMAC_MMC_RIRQE); - D32(EMAC_MMC_RIRQS); - D32(EMAC_MMC_TIRQE); - D32(EMAC_MMC_TIRQS); - D32(EMAC_OPMODE); - D32(EMAC_RXC_ALIGN); - D32(EMAC_RXC_ALLFRM); - D32(EMAC_RXC_ALLOCT); - D32(EMAC_RXC_BROAD); - D32(EMAC_RXC_DMAOVF); - D32(EMAC_RXC_EQ64); - D32(EMAC_RXC_FCS); - D32(EMAC_RXC_GE1024); - D32(EMAC_RXC_LNERRI); - D32(EMAC_RXC_LNERRO); - D32(EMAC_RXC_LONG); - D32(EMAC_RXC_LT1024); - D32(EMAC_RXC_LT128); - D32(EMAC_RXC_LT256); - D32(EMAC_RXC_LT512); - D32(EMAC_RXC_MACCTL); - D32(EMAC_RXC_MULTI); - D32(EMAC_RXC_OCTET); - D32(EMAC_RXC_OK); - D32(EMAC_RXC_OPCODE); - D32(EMAC_RXC_PAUSE); - D32(EMAC_RXC_SHORT); - D32(EMAC_RXC_TYPED); - D32(EMAC_RXC_UNICST); - D32(EMAC_RX_IRQE); - D32(EMAC_RX_STAT); - D32(EMAC_RX_STKY); - D32(EMAC_STAADD); - D32(EMAC_STADAT); - D32(EMAC_SYSCTL); - D32(EMAC_SYSTAT); - D32(EMAC_TXC_1COL); - D32(EMAC_TXC_ABORT); - D32(EMAC_TXC_ALLFRM); - D32(EMAC_TXC_ALLOCT); - D32(EMAC_TXC_BROAD); - D32(EMAC_TXC_CRSERR); - D32(EMAC_TXC_DEFER); - D32(EMAC_TXC_DMAUND); - D32(EMAC_TXC_EQ64); - D32(EMAC_TXC_GE1024); - D32(EMAC_TXC_GT1COL); - D32(EMAC_TXC_LATECL); - D32(EMAC_TXC_LT1024); - D32(EMAC_TXC_LT128); - D32(EMAC_TXC_LT256); - D32(EMAC_TXC_LT512); - D32(EMAC_TXC_MACCTL); - D32(EMAC_TXC_MULTI); - D32(EMAC_TXC_OCTET); - D32(EMAC_TXC_OK); - D32(EMAC_TXC_UNICST); - D32(EMAC_TXC_XS_COL); - D32(EMAC_TXC_XS_DFR); - D32(EMAC_TX_IRQE); - D32(EMAC_TX_STAT); - D32(EMAC_TX_STKY); - D32(EMAC_VLAN1); - D32(EMAC_VLAN2); - D32(EMAC_WKUP_CTL); - D32(EMAC_WKUP_FFCMD); - D32(EMAC_WKUP_FFCRC0); - D32(EMAC_WKUP_FFCRC1); - D32(EMAC_WKUP_FFMSK0); - D32(EMAC_WKUP_FFMSK1); - D32(EMAC_WKUP_FFMSK2); - D32(EMAC_WKUP_FFMSK3); - D32(EMAC_WKUP_FFOFF); -# ifdef EMAC_PTP_ACCR - D32(EMAC_PTP_ACCR); - D32(EMAC_PTP_ADDEND); - D32(EMAC_PTP_ALARMHI); - D32(EMAC_PTP_ALARMLO); - D16(EMAC_PTP_CTL); - D32(EMAC_PTP_FOFF); - D32(EMAC_PTP_FV1); - D32(EMAC_PTP_FV2); - D32(EMAC_PTP_FV3); - D16(EMAC_PTP_ID_OFF); - D32(EMAC_PTP_ID_SNAP); - D16(EMAC_PTP_IE); - D16(EMAC_PTP_ISTAT); - D32(EMAC_PTP_OFFSET); - D32(EMAC_PTP_PPS_PERIOD); - D32(EMAC_PTP_PPS_STARTHI); - D32(EMAC_PTP_PPS_STARTLO); - D32(EMAC_PTP_RXSNAPHI); - D32(EMAC_PTP_RXSNAPLO); - D32(EMAC_PTP_TIMEHI); - D32(EMAC_PTP_TIMELO); - D32(EMAC_PTP_TXSNAPHI); - D32(EMAC_PTP_TXSNAPLO); -# endif -#endif - -#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS) - parent = debugfs_create_dir("eppi", top); -# ifdef EPPI0_STATUS - EPPI(0); -# endif -# ifdef EPPI1_STATUS - EPPI(1); -# endif -# ifdef EPPI2_STATUS - EPPI(2); -# endif -#endif - - parent = debugfs_create_dir("gptimer", top); -#ifdef TIMER_ENABLE - GPTIMER_GROUP(TIMER_ENABLE, -1); -#endif -#ifdef TIMER_ENABLE0 - GPTIMER_GROUP(TIMER_ENABLE0, 0); -#endif -#ifdef TIMER_ENABLE1 - GPTIMER_GROUP(TIMER_ENABLE1, 1); -#endif - /* XXX: Should convert BF561 MMR names */ -#ifdef TMRS4_DISABLE - GPTIMER_GROUP(TMRS4_ENABLE, 0); - GPTIMER_GROUP(TMRS8_ENABLE, 1); -#endif - GPTIMER(0); - GPTIMER(1); - GPTIMER(2); -#ifdef TIMER3_CONFIG - GPTIMER(3); - GPTIMER(4); - GPTIMER(5); - GPTIMER(6); - GPTIMER(7); -#endif -#ifdef TIMER8_CONFIG - GPTIMER(8); - GPTIMER(9); - GPTIMER(10); -#endif -#ifdef TIMER11_CONFIG - GPTIMER(11); -#endif - -#ifdef HMDMA0_CONTROL - parent = debugfs_create_dir("hmdma", top); - HMDMA(0); - HMDMA(1); -#endif - -#ifdef HOST_CONTROL - parent = debugfs_create_dir("hostdp", top); - D16(HOST_CONTROL); - D16(HOST_STATUS); - D16(HOST_TIMEOUT); -#endif - -#ifdef IMDMA_S0_CONFIG - parent = debugfs_create_dir("imdma", top); - IMDMA(0); - IMDMA(1); -#endif - -#ifdef KPAD_CTL - parent = debugfs_create_dir("keypad", top); - D16(KPAD_CTL); - D16(KPAD_PRESCALE); - D16(KPAD_MSEL); - D16(KPAD_ROWCOL); - D16(KPAD_STAT); - D16(KPAD_SOFTEVAL); -#endif - - parent = debugfs_create_dir("mdma", top); - MDMA(0); - MDMA(1); -#ifdef MDMA_D2_CONFIG - MDMA(2); - MDMA(3); -#endif - -#ifdef MXVR_CONFIG - parent = debugfs_create_dir("mxvr", top); - D16(MXVR_CONFIG); -# ifdef MXVR_PLL_CTL_0 - D32(MXVR_PLL_CTL_0); -# endif - D32(MXVR_STATE_0); - D32(MXVR_STATE_1); - D32(MXVR_INT_STAT_0); - D32(MXVR_INT_STAT_1); - D32(MXVR_INT_EN_0); - D32(MXVR_INT_EN_1); - D16(MXVR_POSITION); - D16(MXVR_MAX_POSITION); - D16(MXVR_DELAY); - D16(MXVR_MAX_DELAY); - D32(MXVR_LADDR); - D16(MXVR_GADDR); - D32(MXVR_AADDR); - D32(MXVR_ALLOC_0); - D32(MXVR_ALLOC_1); - D32(MXVR_ALLOC_2); - D32(MXVR_ALLOC_3); - D32(MXVR_ALLOC_4); - D32(MXVR_ALLOC_5); - D32(MXVR_ALLOC_6); - D32(MXVR_ALLOC_7); - D32(MXVR_ALLOC_8); - D32(MXVR_ALLOC_9); - D32(MXVR_ALLOC_10); - D32(MXVR_ALLOC_11); - D32(MXVR_ALLOC_12); - D32(MXVR_ALLOC_13); - D32(MXVR_ALLOC_14); - D32(MXVR_SYNC_LCHAN_0); - D32(MXVR_SYNC_LCHAN_1); - D32(MXVR_SYNC_LCHAN_2); - D32(MXVR_SYNC_LCHAN_3); - D32(MXVR_SYNC_LCHAN_4); - D32(MXVR_SYNC_LCHAN_5); - D32(MXVR_SYNC_LCHAN_6); - D32(MXVR_SYNC_LCHAN_7); - D32(MXVR_DMA0_CONFIG); - D32(MXVR_DMA0_START_ADDR); - D16(MXVR_DMA0_COUNT); - D32(MXVR_DMA0_CURR_ADDR); - D16(MXVR_DMA0_CURR_COUNT); - D32(MXVR_DMA1_CONFIG); - D32(MXVR_DMA1_START_ADDR); - D16(MXVR_DMA1_COUNT); - D32(MXVR_DMA1_CURR_ADDR); - D16(MXVR_DMA1_CURR_COUNT); - D32(MXVR_DMA2_CONFIG); - D32(MXVR_DMA2_START_ADDR); - D16(MXVR_DMA2_COUNT); - D32(MXVR_DMA2_CURR_ADDR); - D16(MXVR_DMA2_CURR_COUNT); - D32(MXVR_DMA3_CONFIG); - D32(MXVR_DMA3_START_ADDR); - D16(MXVR_DMA3_COUNT); - D32(MXVR_DMA3_CURR_ADDR); - D16(MXVR_DMA3_CURR_COUNT); - D32(MXVR_DMA4_CONFIG); - D32(MXVR_DMA4_START_ADDR); - D16(MXVR_DMA4_COUNT); - D32(MXVR_DMA4_CURR_ADDR); - D16(MXVR_DMA4_CURR_COUNT); - D32(MXVR_DMA5_CONFIG); - D32(MXVR_DMA5_START_ADDR); - D16(MXVR_DMA5_COUNT); - D32(MXVR_DMA5_CURR_ADDR); - D16(MXVR_DMA5_CURR_COUNT); - D32(MXVR_DMA6_CONFIG); - D32(MXVR_DMA6_START_ADDR); - D16(MXVR_DMA6_COUNT); - D32(MXVR_DMA6_CURR_ADDR); - D16(MXVR_DMA6_CURR_COUNT); - D32(MXVR_DMA7_CONFIG); - D32(MXVR_DMA7_START_ADDR); - D16(MXVR_DMA7_COUNT); - D32(MXVR_DMA7_CURR_ADDR); - D16(MXVR_DMA7_CURR_COUNT); - D16(MXVR_AP_CTL); - D32(MXVR_APRB_START_ADDR); - D32(MXVR_APRB_CURR_ADDR); - D32(MXVR_APTB_START_ADDR); - D32(MXVR_APTB_CURR_ADDR); - D32(MXVR_CM_CTL); - D32(MXVR_CMRB_START_ADDR); - D32(MXVR_CMRB_CURR_ADDR); - D32(MXVR_CMTB_START_ADDR); - D32(MXVR_CMTB_CURR_ADDR); - D32(MXVR_RRDB_START_ADDR); - D32(MXVR_RRDB_CURR_ADDR); - D32(MXVR_PAT_DATA_0); - D32(MXVR_PAT_EN_0); - D32(MXVR_PAT_DATA_1); - D32(MXVR_PAT_EN_1); - D16(MXVR_FRAME_CNT_0); - D16(MXVR_FRAME_CNT_1); - D32(MXVR_ROUTING_0); - D32(MXVR_ROUTING_1); - D32(MXVR_ROUTING_2); - D32(MXVR_ROUTING_3); - D32(MXVR_ROUTING_4); - D32(MXVR_ROUTING_5); - D32(MXVR_ROUTING_6); - D32(MXVR_ROUTING_7); - D32(MXVR_ROUTING_8); - D32(MXVR_ROUTING_9); - D32(MXVR_ROUTING_10); - D32(MXVR_ROUTING_11); - D32(MXVR_ROUTING_12); - D32(MXVR_ROUTING_13); - D32(MXVR_ROUTING_14); -# ifdef MXVR_PLL_CTL_1 - D32(MXVR_PLL_CTL_1); -# endif - D16(MXVR_BLOCK_CNT); -# ifdef MXVR_CLK_CTL - D32(MXVR_CLK_CTL); -# endif -# ifdef MXVR_CDRPLL_CTL - D32(MXVR_CDRPLL_CTL); -# endif -# ifdef MXVR_FMPLL_CTL - D32(MXVR_FMPLL_CTL); -# endif -# ifdef MXVR_PIN_CTL - D16(MXVR_PIN_CTL); -# endif -# ifdef MXVR_SCLK_CNT - D16(MXVR_SCLK_CNT); -# endif -#endif - -#ifdef NFC_ADDR - parent = debugfs_create_dir("nfc", top); - D_WO(NFC_ADDR, 16); - D_WO(NFC_CMD, 16); - D_RO(NFC_COUNT, 16); - D16(NFC_CTL); - D_WO(NFC_DATA_RD, 16); - D_WO(NFC_DATA_WR, 16); - D_RO(NFC_ECC0, 16); - D_RO(NFC_ECC1, 16); - D_RO(NFC_ECC2, 16); - D_RO(NFC_ECC3, 16); - D16(NFC_IRQMASK); - D16(NFC_IRQSTAT); - D_WO(NFC_PGCTL, 16); - D_RO(NFC_READ, 16); - D16(NFC_RST); - D_RO(NFC_STAT, 16); -#endif - -#ifdef OTP_CONTROL - parent = debugfs_create_dir("otp", top); - D16(OTP_CONTROL); - D16(OTP_BEN); - D16(OTP_STATUS); - D32(OTP_TIMING); - D32(OTP_DATA0); - D32(OTP_DATA1); - D32(OTP_DATA2); - D32(OTP_DATA3); -#endif - -#ifdef PINT0_MASK_SET - parent = debugfs_create_dir("pint", top); - PINT(0); - PINT(1); - PINT(2); - PINT(3); -#endif - -#ifdef PIXC_CTL - parent = debugfs_create_dir("pixc", top); - D16(PIXC_CTL); - D16(PIXC_PPL); - D16(PIXC_LPF); - D16(PIXC_AHSTART); - D16(PIXC_AHEND); - D16(PIXC_AVSTART); - D16(PIXC_AVEND); - D16(PIXC_ATRANSP); - D16(PIXC_BHSTART); - D16(PIXC_BHEND); - D16(PIXC_BVSTART); - D16(PIXC_BVEND); - D16(PIXC_BTRANSP); - D16(PIXC_INTRSTAT); - D32(PIXC_RYCON); - D32(PIXC_GUCON); - D32(PIXC_BVCON); - D32(PIXC_CCBIAS); - D32(PIXC_TC); -#endif - - parent = debugfs_create_dir("pll", top); - D16(PLL_CTL); - D16(PLL_DIV); - D16(PLL_LOCKCNT); - D16(PLL_STAT); - D16(VR_CTL); - D32(CHIPID); /* it's part of this hardware block */ - -#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL) - parent = debugfs_create_dir("ppi", top); -# ifdef PPI_CONTROL - bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1); -# endif -# ifdef PPI0_CONTROL - PPI(0); -# endif -# ifdef PPI1_CONTROL - PPI(1); -# endif -#endif - -#ifdef PWM_CTRL - parent = debugfs_create_dir("pwm", top); - D16(PWM_CTRL); - D16(PWM_STAT); - D16(PWM_TM); - D16(PWM_DT); - D16(PWM_GATE); - D16(PWM_CHA); - D16(PWM_CHB); - D16(PWM_CHC); - D16(PWM_SEG); - D16(PWM_SYNCWT); - D16(PWM_CHAL); - D16(PWM_CHBL); - D16(PWM_CHCL); - D16(PWM_LSI); - D16(PWM_STAT2); -#endif - -#ifdef RSI_CONFIG - parent = debugfs_create_dir("rsi", top); - D32(RSI_ARGUMENT); - D16(RSI_CEATA_CONTROL); - D16(RSI_CLK_CONTROL); - D16(RSI_COMMAND); - D16(RSI_CONFIG); - D16(RSI_DATA_CNT); - D16(RSI_DATA_CONTROL); - D16(RSI_DATA_LGTH); - D32(RSI_DATA_TIMER); - D16(RSI_EMASK); - D16(RSI_ESTAT); - D32(RSI_FIFO); - D16(RSI_FIFO_CNT); - D32(RSI_MASK0); - D32(RSI_MASK1); - D16(RSI_PID0); - D16(RSI_PID1); - D16(RSI_PID2); - D16(RSI_PID3); - D16(RSI_PID4); - D16(RSI_PID5); - D16(RSI_PID6); - D16(RSI_PID7); - D16(RSI_PWR_CONTROL); - D16(RSI_RD_WAIT_EN); - D32(RSI_RESPONSE0); - D32(RSI_RESPONSE1); - D32(RSI_RESPONSE2); - D32(RSI_RESPONSE3); - D16(RSI_RESP_CMD); - D32(RSI_STATUS); - D_WO(RSI_STATUSCL, 16); -#endif - -#ifdef RTC_ALARM - parent = debugfs_create_dir("rtc", top); - D32(RTC_ALARM); - D16(RTC_ICTL); - D16(RTC_ISTAT); - D16(RTC_PREN); - D32(RTC_STAT); - D16(RTC_SWCNT); -#endif - -#ifdef SDH_CFG - parent = debugfs_create_dir("sdh", top); - D32(SDH_ARGUMENT); - D16(SDH_CFG); - D16(SDH_CLK_CTL); - D16(SDH_COMMAND); - D_RO(SDH_DATA_CNT, 16); - D16(SDH_DATA_CTL); - D16(SDH_DATA_LGTH); - D32(SDH_DATA_TIMER); - D16(SDH_E_MASK); - D16(SDH_E_STATUS); - D32(SDH_FIFO); - D_RO(SDH_FIFO_CNT, 16); - D32(SDH_MASK0); - D32(SDH_MASK1); - D_RO(SDH_PID0, 16); - D_RO(SDH_PID1, 16); - D_RO(SDH_PID2, 16); - D_RO(SDH_PID3, 16); - D_RO(SDH_PID4, 16); - D_RO(SDH_PID5, 16); - D_RO(SDH_PID6, 16); - D_RO(SDH_PID7, 16); - D16(SDH_PWR_CTL); - D16(SDH_RD_WAIT_EN); - D_RO(SDH_RESPONSE0, 32); - D_RO(SDH_RESPONSE1, 32); - D_RO(SDH_RESPONSE2, 32); - D_RO(SDH_RESPONSE3, 32); - D_RO(SDH_RESP_CMD, 16); - D_RO(SDH_STATUS, 32); - D_WO(SDH_STATUS_CLR, 16); -#endif - -#ifdef SECURE_CONTROL - parent = debugfs_create_dir("security", top); - D16(SECURE_CONTROL); - D16(SECURE_STATUS); - D32(SECURE_SYSSWT); -#endif - - parent = debugfs_create_dir("sic", top); - D16(SWRST); - D16(SYSCR); - D16(SIC_RVECT); - D32(SIC_IAR0); - D32(SIC_IAR1); - D32(SIC_IAR2); -#ifdef SIC_IAR3 - D32(SIC_IAR3); -#endif -#ifdef SIC_IAR4 - D32(SIC_IAR4); - D32(SIC_IAR5); - D32(SIC_IAR6); -#endif -#ifdef SIC_IAR7 - D32(SIC_IAR7); -#endif -#ifdef SIC_IAR8 - D32(SIC_IAR8); - D32(SIC_IAR9); - D32(SIC_IAR10); - D32(SIC_IAR11); -#endif -#ifdef SIC_IMASK - D32(SIC_IMASK); - D32(SIC_ISR); - D32(SIC_IWR); -#endif -#ifdef SIC_IMASK0 - D32(SIC_IMASK0); - D32(SIC_IMASK1); - D32(SIC_ISR0); - D32(SIC_ISR1); - D32(SIC_IWR0); - D32(SIC_IWR1); -#endif -#ifdef SIC_IMASK2 - D32(SIC_IMASK2); - D32(SIC_ISR2); - D32(SIC_IWR2); -#endif -#ifdef SICB_RVECT - D16(SICB_SWRST); - D16(SICB_SYSCR); - D16(SICB_RVECT); - D32(SICB_IAR0); - D32(SICB_IAR1); - D32(SICB_IAR2); - D32(SICB_IAR3); - D32(SICB_IAR4); - D32(SICB_IAR5); - D32(SICB_IAR6); - D32(SICB_IAR7); - D32(SICB_IMASK0); - D32(SICB_IMASK1); - D32(SICB_ISR0); - D32(SICB_ISR1); - D32(SICB_IWR0); - D32(SICB_IWR1); -#endif - - parent = debugfs_create_dir("spi", top); -#ifdef SPI0_REGBASE - SPI(0); -#endif -#ifdef SPI1_REGBASE - SPI(1); -#endif -#ifdef SPI2_REGBASE - SPI(2); -#endif - - parent = debugfs_create_dir("sport", top); -#ifdef SPORT0_STAT - SPORT(0); -#endif -#ifdef SPORT1_STAT - SPORT(1); -#endif -#ifdef SPORT2_STAT - SPORT(2); -#endif -#ifdef SPORT3_STAT - SPORT(3); -#endif - -#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV) - parent = debugfs_create_dir("twi", top); -# ifdef TWI_CLKDIV - bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1); -# endif -# ifdef TWI0_CLKDIV - TWI(0); -# endif -# ifdef TWI1_CLKDIV - TWI(1); -# endif -#endif - - parent = debugfs_create_dir("uart", top); -#ifdef BFIN_UART_DLL - bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1); -#endif -#ifdef UART0_DLL - UART(0); -#endif -#ifdef UART1_DLL - UART(1); -#endif -#ifdef UART2_DLL - UART(2); -#endif -#ifdef UART3_DLL - UART(3); -#endif - -#ifdef USB_FADDR - parent = debugfs_create_dir("usb", top); - D16(USB_FADDR); - D16(USB_POWER); - D16(USB_INTRTX); - D16(USB_INTRRX); - D16(USB_INTRTXE); - D16(USB_INTRRXE); - D16(USB_INTRUSB); - D16(USB_INTRUSBE); - D16(USB_FRAME); - D16(USB_INDEX); - D16(USB_TESTMODE); - D16(USB_GLOBINTR); - D16(USB_GLOBAL_CTL); - D16(USB_TX_MAX_PACKET); - D16(USB_CSR0); - D16(USB_TXCSR); - D16(USB_RX_MAX_PACKET); - D16(USB_RXCSR); - D16(USB_COUNT0); - D16(USB_RXCOUNT); - D16(USB_TXTYPE); - D16(USB_NAKLIMIT0); - D16(USB_TXINTERVAL); - D16(USB_RXTYPE); - D16(USB_RXINTERVAL); - D16(USB_TXCOUNT); - D16(USB_EP0_FIFO); - D16(USB_EP1_FIFO); - D16(USB_EP2_FIFO); - D16(USB_EP3_FIFO); - D16(USB_EP4_FIFO); - D16(USB_EP5_FIFO); - D16(USB_EP6_FIFO); - D16(USB_EP7_FIFO); - D16(USB_OTG_DEV_CTL); - D16(USB_OTG_VBUS_IRQ); - D16(USB_OTG_VBUS_MASK); - D16(USB_LINKINFO); - D16(USB_VPLEN); - D16(USB_HS_EOF1); - D16(USB_FS_EOF1); - D16(USB_LS_EOF1); - D16(USB_APHY_CNTRL); - D16(USB_APHY_CALIB); - D16(USB_APHY_CNTRL2); - D16(USB_PLLOSC_CTRL); - D16(USB_SRP_CLKDIV); - D16(USB_EP_NI0_TXMAXP); - D16(USB_EP_NI0_TXCSR); - D16(USB_EP_NI0_RXMAXP); - D16(USB_EP_NI0_RXCSR); - D16(USB_EP_NI0_RXCOUNT); - D16(USB_EP_NI0_TXTYPE); - D16(USB_EP_NI0_TXINTERVAL); - D16(USB_EP_NI0_RXTYPE); - D16(USB_EP_NI0_RXINTERVAL); - D16(USB_EP_NI0_TXCOUNT); - D16(USB_EP_NI1_TXMAXP); - D16(USB_EP_NI1_TXCSR); - D16(USB_EP_NI1_RXMAXP); - D16(USB_EP_NI1_RXCSR); - D16(USB_EP_NI1_RXCOUNT); - D16(USB_EP_NI1_TXTYPE); - D16(USB_EP_NI1_TXINTERVAL); - D16(USB_EP_NI1_RXTYPE); - D16(USB_EP_NI1_RXINTERVAL); - D16(USB_EP_NI1_TXCOUNT); - D16(USB_EP_NI2_TXMAXP); - D16(USB_EP_NI2_TXCSR); - D16(USB_EP_NI2_RXMAXP); - D16(USB_EP_NI2_RXCSR); - D16(USB_EP_NI2_RXCOUNT); - D16(USB_EP_NI2_TXTYPE); - D16(USB_EP_NI2_TXINTERVAL); - D16(USB_EP_NI2_RXTYPE); - D16(USB_EP_NI2_RXINTERVAL); - D16(USB_EP_NI2_TXCOUNT); - D16(USB_EP_NI3_TXMAXP); - D16(USB_EP_NI3_TXCSR); - D16(USB_EP_NI3_RXMAXP); - D16(USB_EP_NI3_RXCSR); - D16(USB_EP_NI3_RXCOUNT); - D16(USB_EP_NI3_TXTYPE); - D16(USB_EP_NI3_TXINTERVAL); - D16(USB_EP_NI3_RXTYPE); - D16(USB_EP_NI3_RXINTERVAL); - D16(USB_EP_NI3_TXCOUNT); - D16(USB_EP_NI4_TXMAXP); - D16(USB_EP_NI4_TXCSR); - D16(USB_EP_NI4_RXMAXP); - D16(USB_EP_NI4_RXCSR); - D16(USB_EP_NI4_RXCOUNT); - D16(USB_EP_NI4_TXTYPE); - D16(USB_EP_NI4_TXINTERVAL); - D16(USB_EP_NI4_RXTYPE); - D16(USB_EP_NI4_RXINTERVAL); - D16(USB_EP_NI4_TXCOUNT); - D16(USB_EP_NI5_TXMAXP); - D16(USB_EP_NI5_TXCSR); - D16(USB_EP_NI5_RXMAXP); - D16(USB_EP_NI5_RXCSR); - D16(USB_EP_NI5_RXCOUNT); - D16(USB_EP_NI5_TXTYPE); - D16(USB_EP_NI5_TXINTERVAL); - D16(USB_EP_NI5_RXTYPE); - D16(USB_EP_NI5_RXINTERVAL); - D16(USB_EP_NI5_TXCOUNT); - D16(USB_EP_NI6_TXMAXP); - D16(USB_EP_NI6_TXCSR); - D16(USB_EP_NI6_RXMAXP); - D16(USB_EP_NI6_RXCSR); - D16(USB_EP_NI6_RXCOUNT); - D16(USB_EP_NI6_TXTYPE); - D16(USB_EP_NI6_TXINTERVAL); - D16(USB_EP_NI6_RXTYPE); - D16(USB_EP_NI6_RXINTERVAL); - D16(USB_EP_NI6_TXCOUNT); - D16(USB_EP_NI7_TXMAXP); - D16(USB_EP_NI7_TXCSR); - D16(USB_EP_NI7_RXMAXP); - D16(USB_EP_NI7_RXCSR); - D16(USB_EP_NI7_RXCOUNT); - D16(USB_EP_NI7_TXTYPE); - D16(USB_EP_NI7_TXINTERVAL); - D16(USB_EP_NI7_RXTYPE); - D16(USB_EP_NI7_RXINTERVAL); - D16(USB_EP_NI7_TXCOUNT); - D16(USB_DMA_INTERRUPT); - D16(USB_DMA0CONTROL); - D16(USB_DMA0ADDRLOW); - D16(USB_DMA0ADDRHIGH); - D16(USB_DMA0COUNTLOW); - D16(USB_DMA0COUNTHIGH); - D16(USB_DMA1CONTROL); - D16(USB_DMA1ADDRLOW); - D16(USB_DMA1ADDRHIGH); - D16(USB_DMA1COUNTLOW); - D16(USB_DMA1COUNTHIGH); - D16(USB_DMA2CONTROL); - D16(USB_DMA2ADDRLOW); - D16(USB_DMA2ADDRHIGH); - D16(USB_DMA2COUNTLOW); - D16(USB_DMA2COUNTHIGH); - D16(USB_DMA3CONTROL); - D16(USB_DMA3ADDRLOW); - D16(USB_DMA3ADDRHIGH); - D16(USB_DMA3COUNTLOW); - D16(USB_DMA3COUNTHIGH); - D16(USB_DMA4CONTROL); - D16(USB_DMA4ADDRLOW); - D16(USB_DMA4ADDRHIGH); - D16(USB_DMA4COUNTLOW); - D16(USB_DMA4COUNTHIGH); - D16(USB_DMA5CONTROL); - D16(USB_DMA5ADDRLOW); - D16(USB_DMA5ADDRHIGH); - D16(USB_DMA5COUNTLOW); - D16(USB_DMA5COUNTHIGH); - D16(USB_DMA6CONTROL); - D16(USB_DMA6ADDRLOW); - D16(USB_DMA6ADDRHIGH); - D16(USB_DMA6COUNTLOW); - D16(USB_DMA6COUNTHIGH); - D16(USB_DMA7CONTROL); - D16(USB_DMA7ADDRLOW); - D16(USB_DMA7ADDRHIGH); - D16(USB_DMA7COUNTLOW); - D16(USB_DMA7COUNTHIGH); -#endif - -#ifdef WDOG_CNT - parent = debugfs_create_dir("watchdog", top); - D32(WDOG_CNT); - D16(WDOG_CTL); - D32(WDOG_STAT); -#endif -#ifdef WDOGA_CNT - parent = debugfs_create_dir("watchdog", top); - D32(WDOGA_CNT); - D16(WDOGA_CTL); - D32(WDOGA_STAT); - D32(WDOGB_CNT); - D16(WDOGB_CTL); - D32(WDOGB_STAT); -#endif - - /* BF533 glue */ -#ifdef FIO_FLAG_D -#define PORTFIO FIO_FLAG_D -#endif - /* BF561 glue */ -#ifdef FIO0_FLAG_D -#define PORTFIO FIO0_FLAG_D -#endif -#ifdef FIO1_FLAG_D -#define PORTGIO FIO1_FLAG_D -#endif -#ifdef FIO2_FLAG_D -#define PORTHIO FIO2_FLAG_D -#endif - parent = debugfs_create_dir("port", top); -#ifdef PORTFIO - PORT(PORTFIO, 'F'); -#endif -#ifdef PORTGIO - PORT(PORTGIO, 'G'); -#endif -#ifdef PORTHIO - PORT(PORTHIO, 'H'); -#endif - -#ifdef __ADSPBF51x__ - D16(PORTF_FER); - D16(PORTF_DRIVE); - D16(PORTF_HYSTERESIS); - D16(PORTF_MUX); - - D16(PORTG_FER); - D16(PORTG_DRIVE); - D16(PORTG_HYSTERESIS); - D16(PORTG_MUX); - - D16(PORTH_FER); - D16(PORTH_DRIVE); - D16(PORTH_HYSTERESIS); - D16(PORTH_MUX); - - D16(MISCPORT_DRIVE); - D16(MISCPORT_HYSTERESIS); -#endif /* BF51x */ - -#ifdef __ADSPBF52x__ - D16(PORTF_FER); - D16(PORTF_DRIVE); - D16(PORTF_HYSTERESIS); - D16(PORTF_MUX); - D16(PORTF_SLEW); - - D16(PORTG_FER); - D16(PORTG_DRIVE); - D16(PORTG_HYSTERESIS); - D16(PORTG_MUX); - D16(PORTG_SLEW); - - D16(PORTH_FER); - D16(PORTH_DRIVE); - D16(PORTH_HYSTERESIS); - D16(PORTH_MUX); - D16(PORTH_SLEW); - - D16(MISCPORT_DRIVE); - D16(MISCPORT_HYSTERESIS); - D16(MISCPORT_SLEW); -#endif /* BF52x */ - -#ifdef BF537_FAMILY - D16(PORTF_FER); - D16(PORTG_FER); - D16(PORTH_FER); - D16(PORT_MUX); -#endif /* BF534 BF536 BF537 */ - -#ifdef BF538_FAMILY - D16(PORTCIO_FER); - D16(PORTCIO); - D16(PORTCIO_CLEAR); - D16(PORTCIO_SET); - D16(PORTCIO_TOGGLE); - D16(PORTCIO_DIR); - D16(PORTCIO_INEN); - - D16(PORTDIO); - D16(PORTDIO_CLEAR); - D16(PORTDIO_DIR); - D16(PORTDIO_FER); - D16(PORTDIO_INEN); - D16(PORTDIO_SET); - D16(PORTDIO_TOGGLE); - - D16(PORTEIO); - D16(PORTEIO_CLEAR); - D16(PORTEIO_DIR); - D16(PORTEIO_FER); - D16(PORTEIO_INEN); - D16(PORTEIO_SET); - D16(PORTEIO_TOGGLE); -#endif /* BF538 BF539 */ - -#ifdef __ADSPBF54x__ - { - int num; - unsigned long base; - - base = PORTA_FER; - for (num = 0; num < 10; ++num) { - PORT(base, num); - base += sizeof(struct bfin_gpio_regs); - } - - } -#endif /* BF54x */ -#endif /* CONFIG_BF60x */ - debug_mmrs_dentry = top; - - return 0; -} -module_init(bfin_debug_mmrs_init); - -static void __exit bfin_debug_mmrs_exit(void) -{ - debugfs_remove_recursive(debug_mmrs_dentry); -} -module_exit(bfin_debug_mmrs_exit); - -MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c deleted file mode 100644 index 477bb29a7987..000000000000 --- a/arch/blackfin/kernel/dma-mapping.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Dynamic DMA mapping support - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static spinlock_t dma_page_lock; -static unsigned long *dma_page; -static unsigned int dma_pages; -static unsigned long dma_base; -static unsigned long dma_size; -static unsigned int dma_initialized; - -static void dma_alloc_init(unsigned long start, unsigned long end) -{ - spin_lock_init(&dma_page_lock); - dma_initialized = 0; - - dma_page = (unsigned long *)__get_free_page(GFP_KERNEL); - memset(dma_page, 0, PAGE_SIZE); - dma_base = PAGE_ALIGN(start); - dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start); - dma_pages = dma_size >> PAGE_SHIFT; - memset((void *)dma_base, 0, DMA_UNCACHED_REGION); - dma_initialized = 1; - - printk(KERN_INFO "%s: dma_page @ 0x%p - %d pages at 0x%08lx\n", __func__, - dma_page, dma_pages, dma_base); -} - -static inline unsigned int get_pages(size_t size) -{ - return ((size - 1) >> PAGE_SHIFT) + 1; -} - -static unsigned long __alloc_dma_pages(unsigned int pages) -{ - unsigned long ret = 0, flags; - unsigned long start; - - if (dma_initialized == 0) - dma_alloc_init(_ramend - DMA_UNCACHED_REGION, _ramend); - - spin_lock_irqsave(&dma_page_lock, flags); - - start = bitmap_find_next_zero_area(dma_page, dma_pages, 0, pages, 0); - if (start < dma_pages) { - ret = dma_base + (start << PAGE_SHIFT); - bitmap_set(dma_page, start, pages); - } - spin_unlock_irqrestore(&dma_page_lock, flags); - return ret; -} - -static void __free_dma_pages(unsigned long addr, unsigned int pages) -{ - unsigned long page = (addr - dma_base) >> PAGE_SHIFT; - unsigned long flags; - - if ((page + pages) > dma_pages) { - printk(KERN_ERR "%s: freeing outside range.\n", __func__); - BUG(); - } - - spin_lock_irqsave(&dma_page_lock, flags); - bitmap_clear(dma_page, page, pages); - spin_unlock_irqrestore(&dma_page_lock, flags); -} - -static void *bfin_dma_alloc(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) -{ - void *ret; - - ret = (void *)__alloc_dma_pages(get_pages(size)); - - if (ret) { - memset(ret, 0, size); - *dma_handle = virt_to_phys(ret); - } - - return ret; -} - -static void bfin_dma_free(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle, unsigned long attrs) -{ - __free_dma_pages((unsigned long)vaddr, get_pages(size)); -} - -/* - * Streaming DMA mappings - */ -void __dma_sync(dma_addr_t addr, size_t size, - enum dma_data_direction dir) -{ - __dma_sync_inline(addr, size, dir); -} -EXPORT_SYMBOL(__dma_sync); - -static int bfin_dma_map_sg(struct device *dev, struct scatterlist *sg_list, - int nents, enum dma_data_direction direction, - unsigned long attrs) -{ - struct scatterlist *sg; - int i; - - for_each_sg(sg_list, sg, nents, i) { - sg->dma_address = (dma_addr_t) sg_virt(sg); - - if (attrs & DMA_ATTR_SKIP_CPU_SYNC) - continue; - - __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); - } - - return nents; -} - -static void bfin_dma_sync_sg_for_device(struct device *dev, - struct scatterlist *sg_list, int nelems, - enum dma_data_direction direction) -{ - struct scatterlist *sg; - int i; - - for_each_sg(sg_list, sg, nelems, i) { - sg->dma_address = (dma_addr_t) sg_virt(sg); - __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); - } -} - -static dma_addr_t bfin_dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction dir, - unsigned long attrs) -{ - dma_addr_t handle = (dma_addr_t)(page_address(page) + offset); - - if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) - _dma_sync(handle, size, dir); - - return handle; -} - -static inline void bfin_dma_sync_single_for_device(struct device *dev, - dma_addr_t handle, size_t size, enum dma_data_direction dir) -{ - _dma_sync(handle, size, dir); -} - -const struct dma_map_ops bfin_dma_ops = { - .alloc = bfin_dma_alloc, - .free = bfin_dma_free, - - .map_page = bfin_dma_map_page, - .map_sg = bfin_dma_map_sg, - - .sync_single_for_device = bfin_dma_sync_single_for_device, - .sync_sg_for_device = bfin_dma_sync_sg_for_device, -}; -EXPORT_SYMBOL(bfin_dma_ops); diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c deleted file mode 100644 index 3c992c1f8ef2..000000000000 --- a/arch/blackfin/kernel/dumpstack.c +++ /dev/null @@ -1,177 +0,0 @@ -/* Provide basic stack dumping functions - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include - -#include - -/* - * Checks to see if the address pointed to is either a - * 16-bit CALL instruction, or a 32-bit CALL instruction - */ -static bool is_bfin_call(unsigned short *addr) -{ - unsigned int opcode; - - if (!get_instruction(&opcode, addr)) - return false; - - if ((opcode >= 0x0060 && opcode <= 0x0067) || - (opcode >= 0x0070 && opcode <= 0x0077) || - (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF)) - return true; - - return false; - -} - -void show_stack(struct task_struct *task, unsigned long *stack) -{ -#ifdef CONFIG_PRINTK - unsigned int *addr, *endstack, *fp = 0, *frame; - unsigned short *ins_addr; - char buf[150]; - unsigned int i, j, ret_addr, frame_no = 0; - - /* - * If we have been passed a specific stack, use that one otherwise - * if we have been passed a task structure, use that, otherwise - * use the stack of where the variable "stack" exists - */ - - if (stack == NULL) { - if (task) { - /* We know this is a kernel stack, so this is the start/end */ - stack = (unsigned long *)task->thread.ksp; - endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE); - } else { - /* print out the existing stack info */ - stack = (unsigned long *)&stack; - endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack); - } - } else - endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack); - - printk(KERN_NOTICE "Stack info:\n"); - decode_address(buf, (unsigned int)stack); - printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf); - - if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) { - printk(KERN_NOTICE "Invalid stack pointer\n"); - return; - } - - /* First thing is to look for a frame pointer */ - for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) { - if (*addr & 0x1) - continue; - ins_addr = (unsigned short *)*addr; - ins_addr--; - if (is_bfin_call(ins_addr)) - fp = addr - 1; - - if (fp) { - /* Let's check to see if it is a frame pointer */ - while (fp >= (addr - 1) && fp < endstack - && fp && ((unsigned int) fp & 0x3) == 0) - fp = (unsigned int *)*fp; - if (fp == 0 || fp == endstack) { - fp = addr - 1; - break; - } - fp = 0; - } - } - if (fp) { - frame = fp; - printk(KERN_NOTICE " FP: (0x%p)\n", fp); - } else - frame = 0; - - /* - * Now that we think we know where things are, we - * walk the stack again, this time printing things out - * incase there is no frame pointer, we still look for - * valid return addresses - */ - - /* First time print out data, next time, print out symbols */ - for (j = 0; j <= 1; j++) { - if (j) - printk(KERN_NOTICE "Return addresses in stack:\n"); - else - printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack); - - fp = frame; - frame_no = 0; - - for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0; - addr < endstack; addr++, i++) { - - ret_addr = 0; - if (!j && i % 8 == 0) - printk(KERN_NOTICE "%p:", addr); - - /* if it is an odd address, or zero, just skip it */ - if (*addr & 0x1 || !*addr) - goto print; - - ins_addr = (unsigned short *)*addr; - - /* Go back one instruction, and see if it is a CALL */ - ins_addr--; - ret_addr = is_bfin_call(ins_addr); - print: - if (!j && stack == (unsigned long *)addr) - printk("[%08x]", *addr); - else if (ret_addr) - if (j) { - decode_address(buf, (unsigned int)*addr); - if (frame == addr) { - printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf); - continue; - } - printk(KERN_NOTICE " address : %s\n", buf); - } else - printk("<%08x>", *addr); - else if (fp == addr) { - if (j) - frame = addr+1; - else - printk("(%08x)", *addr); - - fp = (unsigned int *)*addr; - frame_no++; - - } else if (!j) - printk(" %08x ", *addr); - } - if (!j) - printk("\n"); - } -#endif -} -EXPORT_SYMBOL(show_stack); - -void dump_stack(void) -{ - unsigned long stack; -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - int tflags; -#endif - trace_buffer_save(tflags); - dump_bfin_trace_buffer(); - dump_stack_print_info(KERN_DEFAULT); - show_stack(current, &stack); - trace_buffer_restore(tflags); -} -EXPORT_SYMBOL(dump_stack); diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c deleted file mode 100644 index 4b89af9243d3..000000000000 --- a/arch/blackfin/kernel/early_printk.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * allow a console to be used for early printk - * derived from arch/x86/kernel/early_printk.c - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_BFIN -extern struct console *bfin_earlyserial_init(unsigned int port, - unsigned int cflag); -#endif -#ifdef CONFIG_BFIN_JTAG_COMM -extern struct console *bfin_jc_early_init(void); -#endif - -/* Default console */ -#define DEFAULT_PORT 0 -#define DEFAULT_CFLAG CS8|B57600 - -/* Default console for early crashes */ -#define DEFAULT_EARLY_PORT "serial,uart0,57600" - -#ifdef CONFIG_SERIAL_CORE -/* What should get here is "0,57600" */ -static struct console * __init earlyserial_init(char *buf) -{ - int baud, bit; - char parity; - unsigned int serial_port = DEFAULT_PORT; - unsigned int cflag = DEFAULT_CFLAG; - - serial_port = simple_strtoul(buf, &buf, 10); - buf++; - - cflag = 0; - baud = simple_strtoul(buf, &buf, 10); - switch (baud) { - case 1200: - cflag |= B1200; - break; - case 2400: - cflag |= B2400; - break; - case 4800: - cflag |= B4800; - break; - case 9600: - cflag |= B9600; - break; - case 19200: - cflag |= B19200; - break; - case 38400: - cflag |= B38400; - break; - case 115200: - cflag |= B115200; - break; - default: - cflag |= B57600; - } - - parity = buf[0]; - buf++; - switch (parity) { - case 'e': - cflag |= PARENB; - break; - case 'o': - cflag |= PARODD; - break; - } - - bit = simple_strtoul(buf, &buf, 10); - switch (bit) { - case 5: - cflag |= CS5; - break; - case 6: - cflag |= CS6; - break; - case 7: - cflag |= CS7; - break; - default: - cflag |= CS8; - } - -#ifdef CONFIG_SERIAL_BFIN - return bfin_earlyserial_init(serial_port, cflag); -#else - return NULL; -#endif - -} -#endif - -int __init setup_early_printk(char *buf) -{ - - /* Crashing in here would be really bad, so check both the var - and the pointer before we start using it - */ - if (!buf) - return 0; - - if (!*buf) - return 0; - - if (early_console != NULL) - return 0; - -#ifdef CONFIG_SERIAL_BFIN - /* Check for Blackfin Serial */ - if (!strncmp(buf, "serial,uart", 11)) { - buf += 11; - early_console = earlyserial_init(buf); - } -#endif - -#ifdef CONFIG_BFIN_JTAG_COMM - /* Check for Blackfin JTAG */ - if (!strncmp(buf, "jtag", 4)) { - buf += 4; - early_console = bfin_jc_early_init(); - } -#endif - -#ifdef CONFIG_FB - /* TODO: add framebuffer console support */ -#endif - - if (likely(early_console)) { - early_console->flags |= CON_BOOT; - - register_console(early_console); - printk(KERN_INFO "early printk enabled on %s%d\n", - early_console->name, - early_console->index); - } - - return 0; -} - -/* - * Set up a temporary Event Vector Table, so if something bad happens before - * the kernel is fully started, it doesn't vector off into somewhere we don't - * know - */ - -asmlinkage void __init init_early_exception_vectors(void) -{ - u32 evt; - SSYNC(); - - /* - * This starts up the shadow buffer, incase anything crashes before - * setup arch - */ - mark_shadow_error(); - early_shadow_puts(linux_banner); - early_shadow_stamp(); - - if (CPUID != bfin_cpuid()) { - early_shadow_puts("Running on wrong machine type, expected"); - early_shadow_reg(CPUID, 16); - early_shadow_puts(", but running on"); - early_shadow_reg(bfin_cpuid(), 16); - early_shadow_puts("\n"); - } - - /* cannot program in software: - * evt0 - emulation (jtag) - * evt1 - reset - */ - for (evt = EVT2; evt <= EVT15; evt += 4) - bfin_write32(evt, early_trap); - CSYNC(); - - /* Set all the return from interrupt, exception, NMI to a known place - * so if we do a RETI, RETX or RETN by mistake - we go somewhere known - * Note - don't change RETS - we are in a subroutine, or - * RETE - since it might screw up if emulator is attached - */ - asm("\tRETI = %0; RETX = %0; RETN = %0;\n" - : : "p"(early_trap)); - -} - -__attribute__((__noreturn__)) -asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr) -{ - /* This can happen before the uart is initialized, so initialize - * the UART now (but only if we are running on the processor we think - * we are compiled for - otherwise we write to MMRs that don't exist, - * and cause other problems. Nothing comes out the UART, but it does - * end up in the __buf_log. - */ - if (likely(early_console == NULL) && CPUID == bfin_cpuid()) - setup_early_printk(DEFAULT_EARLY_PORT); - - if (!shadow_console_enabled()) { - /* crap - we crashed before setup_arch() */ - early_shadow_puts("panic before setup_arch\n"); - early_shadow_puts("IPEND:"); - early_shadow_reg(fp->ipend, 16); - if (fp->seqstat & SEQSTAT_EXCAUSE) { - early_shadow_puts("\nEXCAUSE:"); - early_shadow_reg(fp->seqstat & SEQSTAT_EXCAUSE, 8); - } - if (fp->seqstat & SEQSTAT_HWERRCAUSE) { - early_shadow_puts("\nHWERRCAUSE:"); - early_shadow_reg( - (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14, 8); - } - early_shadow_puts("\nErr @"); - if (fp->ipend & EVT_EVX) - early_shadow_reg(fp->retx, 32); - else - early_shadow_reg(fp->pc, 32); -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - early_shadow_puts("\nTrace:"); - if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) { - while (bfin_read_TBUFSTAT() & TBUFCNT) { - early_shadow_puts("\nT :"); - early_shadow_reg(bfin_read_TBUF(), 32); - early_shadow_puts("\n S :"); - early_shadow_reg(bfin_read_TBUF(), 32); - } - } -#endif - early_shadow_puts("\nUse bfin-elf-addr2line to determine " - "function names\n"); - /* - * We should panic(), but we can't - since panic calls printk, - * and printk uses memcpy. - * we want to reboot, but if the machine type is different, - * can't due to machine specific reboot sequences - */ - if (CPUID == bfin_cpuid()) { - early_shadow_puts("Trying to restart\n"); - machine_restart(""); - } - - early_shadow_puts("Halting, since it is not safe to restart\n"); - while (1) - asm volatile ("EMUEXCPT; IDLE;\n"); - - } else { - printk(KERN_EMERG "Early panic\n"); - show_regs(fp); - dump_bfin_trace_buffer(); - } - - panic("Died early"); -} - -early_param("earlyprintk", setup_early_printk); diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S deleted file mode 100644 index 4071265fc4fe..000000000000 --- a/arch/blackfin/kernel/entry.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include - -#include - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -.section .l1.text -#else -.text -#endif - -ENTRY(_ret_from_fork) -#ifdef CONFIG_IPIPE - /* - * Hw IRQs are off on entry, and we don't want the scheduling tail - * code to starve high priority domains from interrupts while it - * runs. Therefore we first stall the root stage to have the - * virtual interrupt state reflect IMASK. - */ - p0.l = ___ipipe_root_status; - p0.h = ___ipipe_root_status; - r4 = [p0]; - bitset(r4, 0); - [p0] = r4; - /* - * Then we may enable hw IRQs, allowing preemption from high - * priority domains. schedule_tail() will do local_irq_enable() - * since Blackfin does not define __ARCH_WANT_UNLOCKED_CTXSW, so - * there is no need to unstall the root domain by ourselves - * afterwards. - */ - p0.l = _bfin_irq_flags; - p0.h = _bfin_irq_flags; - r4 = [p0]; - sti r4; -#endif /* CONFIG_IPIPE */ - SP += -12; - pseudo_long_call _schedule_tail, p5; - SP += 12; - p1 = [sp++]; - r0 = [sp++]; - cc = p1 == 0; - if cc jump .Lfork; - sp += -12; - call (p1); - sp += 12; -.Lfork: - RESTORE_CONTEXT - rti; -ENDPROC(_ret_from_fork) diff --git a/arch/blackfin/kernel/exception.c b/arch/blackfin/kernel/exception.c deleted file mode 100644 index 9208b5fd5186..000000000000 --- a/arch/blackfin/kernel/exception.c +++ /dev/null @@ -1,45 +0,0 @@ -/* Basic functions for adding/removing custom exception handlers - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include - -int bfin_request_exception(unsigned int exception, void (*handler)(void)) -{ - void (*curr_handler)(void); - - if (exception > 0x3F) - return -EINVAL; - - curr_handler = ex_table[exception]; - - if (curr_handler != ex_replaceable) - return -EBUSY; - - ex_table[exception] = handler; - - return 0; -} -EXPORT_SYMBOL(bfin_request_exception); - -int bfin_free_exception(unsigned int exception, void (*handler)(void)) -{ - void (*curr_handler)(void); - - if (exception > 0x3F) - return -EINVAL; - - curr_handler = ex_table[exception]; - - if (curr_handler != handler) - return -EBUSY; - - ex_table[exception] = ex_replaceable; - - return 0; -} -EXPORT_SYMBOL(bfin_free_exception); diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S deleted file mode 100644 index 0565917f23ba..000000000000 --- a/arch/blackfin/kernel/fixed_code.S +++ /dev/null @@ -1,155 +0,0 @@ -/* - * This file contains sequences of code that will be copied to a - * fixed location, defined in . The interrupt - * handlers ensure that these sequences appear to be atomic when - * executed from userspace. - * These are aligned to 16 bytes, so that we have some space to replace - * these sequences with something else (e.g. kernel traps if we ever do - * BF561 SMP). - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -__INIT - -ENTRY(_fixed_code_start) - -.align 16 -ENTRY(_sigreturn_stub) - P0 = __NR_rt_sigreturn; - EXCPT 0; - /* Speculative execution paranoia. */ -0: JUMP.S 0b; -ENDPROC (_sigreturn_stub) - -.align 16 - /* - * Atomic swap, 8 bit. - * Inputs: P0: memory address to use - * R1: value to store - * Output: R0: old contents of the memory address, zero extended. - */ -ENTRY(_atomic_xchg32) - R0 = [P0]; - [P0] = R1; - rts; -ENDPROC (_atomic_xchg32) - -.align 16 - /* - * Compare and swap, 32 bit. - * Inputs: P0: memory address to use - * R1: compare value - * R2: new value to store - * The new value is stored if the contents of the memory - * address is equal to the compare value. - * Output: R0: old contents of the memory address. - */ -ENTRY(_atomic_cas32) - R0 = [P0]; - CC = R0 == R1; - IF !CC JUMP 1f; - [P0] = R2; -1: - rts; -ENDPROC (_atomic_cas32) - -.align 16 - /* - * Atomic add, 32 bit. - * Inputs: P0: memory address to use - * R0: value to add - * Outputs: R0: new contents of the memory address. - * R1: previous contents of the memory address. - */ -ENTRY(_atomic_add32) - R1 = [P0]; - R0 = R1 + R0; - [P0] = R0; - rts; -ENDPROC (_atomic_add32) - -.align 16 - /* - * Atomic sub, 32 bit. - * Inputs: P0: memory address to use - * R0: value to subtract - * Outputs: R0: new contents of the memory address. - * R1: previous contents of the memory address. - */ -ENTRY(_atomic_sub32) - R1 = [P0]; - R0 = R1 - R0; - [P0] = R0; - rts; -ENDPROC (_atomic_sub32) - -.align 16 - /* - * Atomic ior, 32 bit. - * Inputs: P0: memory address to use - * R0: value to ior - * Outputs: R0: new contents of the memory address. - * R1: previous contents of the memory address. - */ -ENTRY(_atomic_ior32) - R1 = [P0]; - R0 = R1 | R0; - [P0] = R0; - rts; -ENDPROC (_atomic_ior32) - -.align 16 - /* - * Atomic and, 32 bit. - * Inputs: P0: memory address to use - * R0: value to and - * Outputs: R0: new contents of the memory address. - * R1: previous contents of the memory address. - */ -ENTRY(_atomic_and32) - R1 = [P0]; - R0 = R1 & R0; - [P0] = R0; - rts; -ENDPROC (_atomic_and32) - -.align 16 - /* - * Atomic xor, 32 bit. - * Inputs: P0: memory address to use - * R0: value to xor - * Outputs: R0: new contents of the memory address. - * R1: previous contents of the memory address. - */ -ENTRY(_atomic_xor32) - R1 = [P0]; - R0 = R1 ^ R0; - [P0] = R0; - rts; -ENDPROC (_atomic_xor32) - -.align 16 - /* - * safe_user_instruction - * Four NOPS are enough to allow the pipeline to speculativily load - * execute anything it wants. After that, things have gone bad, and - * we are stuck - so panic. Since we might be in user space, we can't - * call panic, so just cause a unhandled exception, this should cause - * a dump of the trace buffer so we can tell were we are, and a reboot - */ -ENTRY(_safe_user_instruction) - NOP; NOP; NOP; NOP; - EXCPT 0x4; -ENDPROC(_safe_user_instruction) - -ENTRY(_fixed_code_end) - -__FINIT diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c deleted file mode 100644 index 8ebc54daaa8e..000000000000 --- a/arch/blackfin/kernel/flat.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2007 Analog Devices Inc. - * - * Licensed under the GPL-2. - */ - -#include -#include -#include -#include - -#define FLAT_BFIN_RELOC_TYPE_16_BIT 0 -#define FLAT_BFIN_RELOC_TYPE_16H_BIT 1 -#define FLAT_BFIN_RELOC_TYPE_32_BIT 2 - -unsigned long bfin_get_addr_from_rp(u32 *ptr, - u32 relval, - u32 flags, - u32 *persistent) -{ - unsigned short *usptr = (unsigned short *)ptr; - int type = (relval >> 26) & 7; - u32 val; - - switch (type) { - case FLAT_BFIN_RELOC_TYPE_16_BIT: - case FLAT_BFIN_RELOC_TYPE_16H_BIT: - usptr = (unsigned short *)ptr; - pr_debug("*usptr = %x", get_unaligned(usptr)); - val = get_unaligned(usptr); - val += *persistent; - break; - - case FLAT_BFIN_RELOC_TYPE_32_BIT: - pr_debug("*ptr = %x", get_unaligned(ptr)); - val = get_unaligned(ptr); - break; - - default: - pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type); - return 0; - } - - /* - * Stack-relative relocs contain the offset into the stack, we - * have to add the stack's start address here and return 1 from - * flat_addr_absolute to prevent the normal address calculations - */ - if (relval & (1 << 29)) - return val + current->mm->context.end_brk; - - if ((flags & FLAT_FLAG_GOTPIC) == 0) - val = htonl(val); - return val; -} -EXPORT_SYMBOL(bfin_get_addr_from_rp); - -/* - * Insert the address ADDR into the symbol reference at RP; - * RELVAL is the raw relocation-table entry from which RP is derived - */ -void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval) -{ - unsigned short *usptr = (unsigned short *)ptr; - int type = (relval >> 26) & 7; - - switch (type) { - case FLAT_BFIN_RELOC_TYPE_16_BIT: - put_unaligned(addr, usptr); - pr_debug("new value %x at %p", get_unaligned(usptr), usptr); - break; - - case FLAT_BFIN_RELOC_TYPE_16H_BIT: - put_unaligned(addr >> 16, usptr); - pr_debug("new value %x", get_unaligned(usptr)); - break; - - case FLAT_BFIN_RELOC_TYPE_32_BIT: - put_unaligned(addr, ptr); - pr_debug("new ptr =%x", get_unaligned(ptr)); - break; - } -} -EXPORT_SYMBOL(bfin_put_addr_at_rp); diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S deleted file mode 100644 index 3b8bdcbb7da3..000000000000 --- a/arch/blackfin/kernel/ftrace-entry.S +++ /dev/null @@ -1,207 +0,0 @@ -/* - * mcount and friends -- ftrace stuff - * - * Copyright (C) 2009-2010 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include -#include - -.text - -#ifdef CONFIG_DYNAMIC_FTRACE - -/* Simple stub so we can boot the kernel until runtime patching has - * disabled all calls to this. Then it'll be unused. - */ -ENTRY(__mcount) -# if ANOMALY_05000371 - nop; nop; nop; nop; -# endif - rts; -ENDPROC(__mcount) - -/* GCC will have called us before setting up the function prologue, so we - * can clobber the normal scratch registers, but we need to make sure to - * save/restore the registers used for argument passing (R0-R2) in case - * the profiled function is using them. With data registers, R3 is the - * only one we can blow away. With pointer registers, we have P0-P2. - * - * Upon entry, the RETS will point to the top of the current profiled - * function. And since GCC pushed the previous RETS for us, the previous - * function will be waiting there. mmmm pie. - */ -ENTRY(_ftrace_caller) - /* save first/second/third function arg and the return register */ - [--sp] = r2; - [--sp] = r0; - [--sp] = r1; - [--sp] = rets; - - /* function_trace_call(unsigned long ip, unsigned long parent_ip): - * ip: this point was called by ... - * parent_ip: ... this function - * the ip itself will need adjusting for the mcount call - */ - r0 = rets; - r1 = [sp + 16]; /* skip the 4 local regs on stack */ - r0 += -MCOUNT_INSN_SIZE; - -.globl _ftrace_call -_ftrace_call: - call _ftrace_stub - -# ifdef CONFIG_FUNCTION_GRAPH_TRACER -.globl _ftrace_graph_call -_ftrace_graph_call: - nop; /* jump _ftrace_graph_caller; */ -# endif - - /* restore state and get out of dodge */ -.Lfinish_trace: - rets = [sp++]; - r1 = [sp++]; - r0 = [sp++]; - r2 = [sp++]; - -.globl _ftrace_stub -_ftrace_stub: - rts; -ENDPROC(_ftrace_caller) - -#else - -/* See documentation for _ftrace_caller */ -ENTRY(__mcount) - /* save third function arg early so we can do testing below */ - [--sp] = r2; - - /* load the function pointer to the tracer */ - p0.l = _ftrace_trace_function; - p0.h = _ftrace_trace_function; - r3 = [p0]; - - /* optional micro optimization: don't call the stub tracer */ - r2.l = _ftrace_stub; - r2.h = _ftrace_stub; - cc = r2 == r3; - if ! cc jump .Ldo_trace; - -# ifdef CONFIG_FUNCTION_GRAPH_TRACER - /* if the ftrace_graph_return function pointer is not set to - * the ftrace_stub entry, call prepare_ftrace_return(). - */ - p0.l = _ftrace_graph_return; - p0.h = _ftrace_graph_return; - r3 = [p0]; - cc = r2 == r3; - if ! cc jump _ftrace_graph_caller; - - /* similarly, if the ftrace_graph_entry function pointer is not - * set to the ftrace_graph_entry_stub entry, ... - */ - p0.l = _ftrace_graph_entry; - p0.h = _ftrace_graph_entry; - r2.l = _ftrace_graph_entry_stub; - r2.h = _ftrace_graph_entry_stub; - r3 = [p0]; - cc = r2 == r3; - if ! cc jump _ftrace_graph_caller; -# endif - - r2 = [sp++]; - rts; - -.Ldo_trace: - - /* save first/second function arg and the return register */ - [--sp] = r0; - [--sp] = r1; - [--sp] = rets; - - /* setup the tracer function */ - p0 = r3; - - /* function_trace_call(unsigned long ip, unsigned long parent_ip): - * ip: this point was called by ... - * parent_ip: ... this function - * the ip itself will need adjusting for the mcount call - */ - r0 = rets; - r1 = [sp + 16]; /* skip the 4 local regs on stack */ - r0 += -MCOUNT_INSN_SIZE; - - /* call the tracer */ - call (p0); - - /* restore state and get out of dodge */ -.Lfinish_trace: - rets = [sp++]; - r1 = [sp++]; - r0 = [sp++]; - r2 = [sp++]; - -.globl _ftrace_stub -_ftrace_stub: - rts; -ENDPROC(__mcount) - -#endif - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER -/* The prepare_ftrace_return() function is similar to the trace function - * except it takes a pointer to the location of the frompc. This is so - * the prepare_ftrace_return() can hijack it temporarily for probing - * purposes. - */ -ENTRY(_ftrace_graph_caller) -# ifndef CONFIG_DYNAMIC_FTRACE - /* save first/second function arg and the return register */ - [--sp] = r0; - [--sp] = r1; - [--sp] = rets; - - /* prepare_ftrace_return(parent, self_addr, frame_pointer) */ - r0 = sp; /* unsigned long *parent */ - r1 = rets; /* unsigned long self_addr */ -# else - r0 = sp; /* unsigned long *parent */ - r1 = [sp]; /* unsigned long self_addr */ -# endif -# ifdef HAVE_FUNCTION_GRAPH_FP_TEST - r2 = fp; /* unsigned long frame_pointer */ -# endif - r0 += 16; /* skip the 4 local regs on stack */ - r1 += -MCOUNT_INSN_SIZE; - call _prepare_ftrace_return; - - jump .Lfinish_trace; -ENDPROC(_ftrace_graph_caller) - -/* Undo the rewrite caused by ftrace_graph_caller(). The common function - * ftrace_return_to_handler() will return the original rets so we can - * restore it and be on our way. - */ -ENTRY(_return_to_handler) - /* make sure original return values are saved */ - [--sp] = p0; - [--sp] = r0; - [--sp] = r1; - - /* get original return address */ -# ifdef HAVE_FUNCTION_GRAPH_FP_TEST - r0 = fp; /* Blackfin is sane, so omit this */ -# endif - call _ftrace_return_to_handler; - rets = r0; - - /* anomaly 05000371 - make sure we have at least three instructions - * between rets setting and the return - */ - r1 = [sp++]; - r0 = [sp++]; - p0 = [sp++]; - rts; -ENDPROC(_return_to_handler) -#endif diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c deleted file mode 100644 index 8dad7589b843..000000000000 --- a/arch/blackfin/kernel/ftrace.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * ftrace graph code - * - * Copyright (C) 2009-2010 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_DYNAMIC_FTRACE - -static const unsigned char mnop[] = { - 0x03, 0xc0, 0x00, 0x18, /* MNOP; */ - 0x03, 0xc0, 0x00, 0x18, /* MNOP; */ -}; - -static void bfin_make_pcrel24(unsigned char *insn, unsigned long src, - unsigned long dst) -{ - uint32_t pcrel = (dst - src) >> 1; - insn[0] = pcrel >> 16; - insn[1] = 0xe3; - insn[2] = pcrel; - insn[3] = pcrel >> 8; -} -#define bfin_make_pcrel24(insn, src, dst) bfin_make_pcrel24(insn, src, (unsigned long)(dst)) - -static int ftrace_modify_code(unsigned long ip, const unsigned char *code, - unsigned long len) -{ - int ret = probe_kernel_write((void *)ip, (void *)code, len); - flush_icache_range(ip, ip + len); - return ret; -} - -int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, - unsigned long addr) -{ - /* Turn the mcount call site into two MNOPs as those are 32bit insns */ - return ftrace_modify_code(rec->ip, mnop, sizeof(mnop)); -} - -int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) -{ - /* Restore the mcount call site */ - unsigned char call[8]; - call[0] = 0x67; /* [--SP] = RETS; */ - call[1] = 0x01; - bfin_make_pcrel24(&call[2], rec->ip + 2, addr); - call[6] = 0x27; /* RETS = [SP++]; */ - call[7] = 0x01; - return ftrace_modify_code(rec->ip, call, sizeof(call)); -} - -int ftrace_update_ftrace_func(ftrace_func_t func) -{ - unsigned char call[4]; - unsigned long ip = (unsigned long)&ftrace_call; - bfin_make_pcrel24(call, ip, func); - return ftrace_modify_code(ip, call, sizeof(call)); -} - -int __init ftrace_dyn_arch_init(void) -{ - return 0; -} - -#endif - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER - -# ifdef CONFIG_DYNAMIC_FTRACE - -extern void ftrace_graph_call(void); - -int ftrace_enable_ftrace_graph_caller(void) -{ - unsigned long ip = (unsigned long)&ftrace_graph_call; - uint16_t jump_pcrel12 = ((unsigned long)&ftrace_graph_caller - ip) >> 1; - jump_pcrel12 |= 0x2000; - return ftrace_modify_code(ip, (void *)&jump_pcrel12, sizeof(jump_pcrel12)); -} - -int ftrace_disable_ftrace_graph_caller(void) -{ - return ftrace_modify_code((unsigned long)&ftrace_graph_call, empty_zero_page, 2); -} - -# endif - -/* - * Hook the return address and push it in the stack of return addrs - * in current thread info. - */ -void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, - unsigned long frame_pointer) -{ - struct ftrace_graph_ent trace; - unsigned long return_hooker = (unsigned long)&return_to_handler; - - if (unlikely(atomic_read(¤t->tracing_graph_pause))) - return; - - if (ftrace_push_return_trace(*parent, self_addr, &trace.depth, - frame_pointer, NULL) == -EBUSY) - return; - - trace.func = self_addr; - - /* Only trace if the calling function expects to */ - if (!ftrace_graph_entry(&trace)) { - current->curr_ret_stack--; - return; - } - - /* all is well in the world ! hijack RETS ... */ - *parent = return_hooker; -} - -#endif diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c deleted file mode 100644 index d776773d3869..000000000000 --- a/arch/blackfin/kernel/gptimers.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * gptimers.c - Blackfin General Purpose Timer core API - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * Copyright (C) 2005 John DeHority - * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) - * - * Licensed under the GPLv2. - */ - -#include -#include -#include - -#include -#include - -#ifdef DEBUG -# define tassert(expr) -#else -# define tassert(expr) \ - if (!(expr)) \ - printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__); -#endif - -#ifndef CONFIG_BF60x -# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1) -#else -# define BFIN_TIMER_NUM_GROUP 1 -#endif - -static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] = -{ - (void *)TIMER0_CONFIG, - (void *)TIMER1_CONFIG, - (void *)TIMER2_CONFIG, -#if (MAX_BLACKFIN_GPTIMERS > 3) - (void *)TIMER3_CONFIG, - (void *)TIMER4_CONFIG, - (void *)TIMER5_CONFIG, - (void *)TIMER6_CONFIG, - (void *)TIMER7_CONFIG, -# if (MAX_BLACKFIN_GPTIMERS > 8) - (void *)TIMER8_CONFIG, - (void *)TIMER9_CONFIG, - (void *)TIMER10_CONFIG, -# if (MAX_BLACKFIN_GPTIMERS > 11) - (void *)TIMER11_CONFIG, -# endif -# endif -#endif -}; - -static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] = -{ - (void *)TIMER0_GROUP_REG, -#if (MAX_BLACKFIN_GPTIMERS > 8) - (void *)TIMER8_GROUP_REG, -#endif -}; - -static uint32_t const trun_mask[MAX_BLACKFIN_GPTIMERS] = -{ - TIMER_STATUS_TRUN0, - TIMER_STATUS_TRUN1, - TIMER_STATUS_TRUN2, -#if (MAX_BLACKFIN_GPTIMERS > 3) - TIMER_STATUS_TRUN3, - TIMER_STATUS_TRUN4, - TIMER_STATUS_TRUN5, - TIMER_STATUS_TRUN6, - TIMER_STATUS_TRUN7, -# if (MAX_BLACKFIN_GPTIMERS > 8) - TIMER_STATUS_TRUN8, - TIMER_STATUS_TRUN9, - TIMER_STATUS_TRUN10, -# if (MAX_BLACKFIN_GPTIMERS > 11) - TIMER_STATUS_TRUN11, -# endif -# endif -#endif -}; - -static uint32_t const tovf_mask[MAX_BLACKFIN_GPTIMERS] = -{ - TIMER_STATUS_TOVF0, - TIMER_STATUS_TOVF1, - TIMER_STATUS_TOVF2, -#if (MAX_BLACKFIN_GPTIMERS > 3) - TIMER_STATUS_TOVF3, - TIMER_STATUS_TOVF4, - TIMER_STATUS_TOVF5, - TIMER_STATUS_TOVF6, - TIMER_STATUS_TOVF7, -# if (MAX_BLACKFIN_GPTIMERS > 8) - TIMER_STATUS_TOVF8, - TIMER_STATUS_TOVF9, - TIMER_STATUS_TOVF10, -# if (MAX_BLACKFIN_GPTIMERS > 11) - TIMER_STATUS_TOVF11, -# endif -# endif -#endif -}; - -static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] = -{ - TIMER_STATUS_TIMIL0, - TIMER_STATUS_TIMIL1, - TIMER_STATUS_TIMIL2, -#if (MAX_BLACKFIN_GPTIMERS > 3) - TIMER_STATUS_TIMIL3, - TIMER_STATUS_TIMIL4, - TIMER_STATUS_TIMIL5, - TIMER_STATUS_TIMIL6, - TIMER_STATUS_TIMIL7, -# if (MAX_BLACKFIN_GPTIMERS > 8) - TIMER_STATUS_TIMIL8, - TIMER_STATUS_TIMIL9, - TIMER_STATUS_TIMIL10, -# if (MAX_BLACKFIN_GPTIMERS > 11) - TIMER_STATUS_TIMIL11, -# endif -# endif -#endif -}; - -void set_gptimer_pwidth(unsigned int timer_id, uint32_t value) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&timer_regs[timer_id]->width, value); - SSYNC(); -} -EXPORT_SYMBOL(set_gptimer_pwidth); - -uint32_t get_gptimer_pwidth(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return bfin_read(&timer_regs[timer_id]->width); -} -EXPORT_SYMBOL(get_gptimer_pwidth); - -void set_gptimer_period(unsigned int timer_id, uint32_t period) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&timer_regs[timer_id]->period, period); - SSYNC(); -} -EXPORT_SYMBOL(set_gptimer_period); - -uint32_t get_gptimer_period(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return bfin_read(&timer_regs[timer_id]->period); -} -EXPORT_SYMBOL(get_gptimer_period); - -uint32_t get_gptimer_count(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return bfin_read(&timer_regs[timer_id]->counter); -} -EXPORT_SYMBOL(get_gptimer_count); - -#ifdef CONFIG_BF60x -void set_gptimer_delay(unsigned int timer_id, uint32_t delay) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&timer_regs[timer_id]->delay, delay); - SSYNC(); -} -EXPORT_SYMBOL(set_gptimer_delay); - -uint32_t get_gptimer_delay(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return bfin_read(&timer_regs[timer_id]->delay); -} -EXPORT_SYMBOL(get_gptimer_delay); -#endif - -#ifdef CONFIG_BF60x -int get_gptimer_intr(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]); -} -EXPORT_SYMBOL(get_gptimer_intr); - -void clear_gptimer_intr(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]); -} -EXPORT_SYMBOL(clear_gptimer_intr); - -int get_gptimer_over(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]); -} -EXPORT_SYMBOL(get_gptimer_over); - -void clear_gptimer_over(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]); -} -EXPORT_SYMBOL(clear_gptimer_over); - -int get_gptimer_run(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]); -} -EXPORT_SYMBOL(get_gptimer_run); - -uint32_t get_gptimer_status(unsigned int group) -{ - tassert(group < BFIN_TIMER_NUM_GROUP); - return bfin_read(&group_regs[group]->data_ilat); -} -EXPORT_SYMBOL(get_gptimer_status); - -void set_gptimer_status(unsigned int group, uint32_t value) -{ - tassert(group < BFIN_TIMER_NUM_GROUP); - bfin_write(&group_regs[group]->data_ilat, value); - SSYNC(); -} -EXPORT_SYMBOL(set_gptimer_status); -#else -uint32_t get_gptimer_status(unsigned int group) -{ - tassert(group < BFIN_TIMER_NUM_GROUP); - return bfin_read(&group_regs[group]->status); -} -EXPORT_SYMBOL(get_gptimer_status); - -void set_gptimer_status(unsigned int group, uint32_t value) -{ - tassert(group < BFIN_TIMER_NUM_GROUP); - bfin_write(&group_regs[group]->status, value); - SSYNC(); -} -EXPORT_SYMBOL(set_gptimer_status); - -static uint32_t read_gptimer_status(unsigned int timer_id) -{ - return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status); -} - -int get_gptimer_intr(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]); -} -EXPORT_SYMBOL(get_gptimer_intr); - -void clear_gptimer_intr(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]); -} -EXPORT_SYMBOL(clear_gptimer_intr); - -int get_gptimer_over(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]); -} -EXPORT_SYMBOL(get_gptimer_over); - -void clear_gptimer_over(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]); -} -EXPORT_SYMBOL(clear_gptimer_over); - -int get_gptimer_run(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]); -} -EXPORT_SYMBOL(get_gptimer_run); -#endif - -void set_gptimer_config(unsigned int timer_id, uint16_t config) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write(&timer_regs[timer_id]->config, config); - SSYNC(); -} -EXPORT_SYMBOL(set_gptimer_config); - -uint16_t get_gptimer_config(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return bfin_read(&timer_regs[timer_id]->config); -} -EXPORT_SYMBOL(get_gptimer_config); - -void enable_gptimers(uint16_t mask) -{ - int i; -#ifdef CONFIG_BF60x - uint16_t imask; - imask = bfin_read16(TIMER_DATA_IMSK); - imask &= ~mask; - bfin_write16(TIMER_DATA_IMSK, imask); -#endif - tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); - for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { - bfin_write(&group_regs[i]->enable, mask & 0xFF); - mask >>= 8; - } - SSYNC(); -} -EXPORT_SYMBOL(enable_gptimers); - -static void _disable_gptimers(uint16_t mask) -{ - int i; - uint16_t m = mask; - tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); - for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { - bfin_write(&group_regs[i]->disable, m & 0xFF); - m >>= 8; - } -} - -void disable_gptimers(uint16_t mask) -{ -#ifndef CONFIG_BF60x - int i; - _disable_gptimers(mask); - for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) - if (mask & (1 << i)) - bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]); - SSYNC(); -#else - _disable_gptimers(mask); -#endif -} -EXPORT_SYMBOL(disable_gptimers); - -void disable_gptimers_sync(uint16_t mask) -{ - _disable_gptimers(mask); - SSYNC(); -} -EXPORT_SYMBOL(disable_gptimers_sync); - -void set_gptimer_pulse_hi(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI); - SSYNC(); -} -EXPORT_SYMBOL(set_gptimer_pulse_hi); - -void clear_gptimer_pulse_hi(unsigned int timer_id) -{ - tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI); - SSYNC(); -} -EXPORT_SYMBOL(clear_gptimer_pulse_hi); - -uint16_t get_enabled_gptimers(void) -{ - int i; - uint16_t result = 0; - for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) - result |= (bfin_read(&group_regs[i]->enable) << (i << 3)); - return result; -} -EXPORT_SYMBOL(get_enabled_gptimers); - -MODULE_AUTHOR("Axel Weiss (awe@aglaia-gmbh.de)"); -MODULE_DESCRIPTION("Blackfin General Purpose Timers API"); -MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c deleted file mode 100644 index f657b38163e3..000000000000 --- a/arch/blackfin/kernel/ipipe.c +++ /dev/null @@ -1,397 +0,0 @@ -/* -*- linux-c -*- - * linux/arch/blackfin/kernel/ipipe.c - * - * Copyright (C) 2005-2007 Philippe Gerum. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, - * USA; either version 2 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * Architecture-dependent I-pipe support for the Blackfin. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); - -asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); - -static void __ipipe_no_irqtail(void); - -unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail; -EXPORT_SYMBOL(__ipipe_irq_tail_hook); - -unsigned long __ipipe_core_clock; -EXPORT_SYMBOL(__ipipe_core_clock); - -unsigned long __ipipe_freq_scale; -EXPORT_SYMBOL(__ipipe_freq_scale); - -atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; - -unsigned long __ipipe_irq_lvmask = bfin_no_irqs; -EXPORT_SYMBOL(__ipipe_irq_lvmask); - -static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc) -{ - desc->ipipe_ack(irq, desc); -} - -/* - * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw - * interrupts are off, and secondary CPUs are still lost in space. - */ -void __ipipe_enable_pipeline(void) -{ - unsigned irq; - - __ipipe_core_clock = get_cclk(); /* Fetch this once. */ - __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock; - - for (irq = 0; irq < NR_IRQS; ++irq) - ipipe_virtualize_irq(ipipe_root_domain, - irq, - (ipipe_irq_handler_t)&asm_do_IRQ, - NULL, - &__ipipe_ack_irq, - IPIPE_HANDLE_MASK | IPIPE_PASS_MASK); -} - -/* - * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic - * interrupt protection log is maintained here for each domain. Hw - * interrupts are masked on entry. - */ -void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) -{ - struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); - struct ipipe_domain *this_domain, *next_domain; - struct list_head *head, *pos; - struct ipipe_irqdesc *idesc; - int m_ack, s = -1; - - /* - * Software-triggered IRQs do not need any ack. The contents - * of the register frame should only be used when processing - * the timer interrupt, but not for handling any other - * interrupt. - */ - m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); - this_domain = __ipipe_current_domain; - idesc = &this_domain->irqs[irq]; - - if (unlikely(test_bit(IPIPE_STICKY_FLAG, &idesc->control))) - head = &this_domain->p_link; - else { - head = __ipipe_pipeline.next; - next_domain = list_entry(head, struct ipipe_domain, p_link); - idesc = &next_domain->irqs[irq]; - if (likely(test_bit(IPIPE_WIRED_FLAG, &idesc->control))) { - if (!m_ack && idesc->acknowledge != NULL) - idesc->acknowledge(irq, irq_to_desc(irq)); - if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) - s = __test_and_set_bit(IPIPE_STALL_FLAG, - &p->status); - __ipipe_dispatch_wired(next_domain, irq); - goto out; - } - } - - /* Ack the interrupt. */ - - pos = head; - while (pos != &__ipipe_pipeline) { - next_domain = list_entry(pos, struct ipipe_domain, p_link); - idesc = &next_domain->irqs[irq]; - if (test_bit(IPIPE_HANDLE_FLAG, &idesc->control)) { - __ipipe_set_irq_pending(next_domain, irq); - if (!m_ack && idesc->acknowledge != NULL) { - idesc->acknowledge(irq, irq_to_desc(irq)); - m_ack = 1; - } - } - if (!test_bit(IPIPE_PASS_FLAG, &idesc->control)) - break; - pos = next_domain->p_link.next; - } - - /* - * Now walk the pipeline, yielding control to the highest - * priority domain that has pending interrupt(s) or - * immediately to the current domain if the interrupt has been - * marked as 'sticky'. This search does not go beyond the - * current domain in the pipeline. We also enforce the - * additional root stage lock (blackfin-specific). - */ - if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) - s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status); - - /* - * If the interrupt preempted the head domain, then do not - * even try to walk the pipeline, unless an interrupt is - * pending for it. - */ - if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) && - !__ipipe_ipending_p(ipipe_head_cpudom_ptr())) - goto out; - - __ipipe_walk_pipeline(head); -out: - if (!s) - __clear_bit(IPIPE_STALL_FLAG, &p->status); -} - -void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) -{ - struct irq_desc *desc = irq_to_desc(irq); - int prio = __ipipe_get_irq_priority(irq); - - desc->depth = 0; - if (ipd != &ipipe_root && - atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1) - __set_bit(prio, &__ipipe_irq_lvmask); -} -EXPORT_SYMBOL(__ipipe_enable_irqdesc); - -void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) -{ - int prio = __ipipe_get_irq_priority(irq); - - if (ipd != &ipipe_root && - atomic_dec_and_test(&__ipipe_irq_lvdepth[prio])) - __clear_bit(prio, &__ipipe_irq_lvmask); -} -EXPORT_SYMBOL(__ipipe_disable_irqdesc); - -asmlinkage int __ipipe_syscall_root(struct pt_regs *regs) -{ - struct ipipe_percpu_domain_data *p; - void (*hook)(void); - int ret; - - WARN_ON_ONCE(irqs_disabled_hw()); - - /* - * We need to run the IRQ tail hook each time we intercept a - * syscall, because we know that important operations might be - * pending there (e.g. Xenomai deferred rescheduling). - */ - hook = (__typeof__(hook))__ipipe_irq_tail_hook; - hook(); - - /* - * This routine either returns: - * 0 -- if the syscall is to be passed to Linux; - * >0 -- if the syscall should not be passed to Linux, and no - * tail work should be performed; - * <0 -- if the syscall should not be passed to Linux but the - * tail work has to be performed (for handling signals etc). - */ - - if (!__ipipe_syscall_watched_p(current, regs->orig_p0) || - !__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL)) - return 0; - - ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs); - - hard_local_irq_disable(); - - /* - * This is the end of the syscall path, so we may - * safely assume a valid Linux task stack here. - */ - if (current->ipipe_flags & PF_EVTRET) { - current->ipipe_flags &= ~PF_EVTRET; - __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs); - } - - if (!__ipipe_root_domain_p) - ret = -1; - else { - p = ipipe_root_cpudom_ptr(); - if (__ipipe_ipending_p(p)) - __ipipe_sync_pipeline(); - } - - hard_local_irq_enable(); - - return -ret; -} - -static void __ipipe_no_irqtail(void) -{ -} - -int ipipe_get_sysinfo(struct ipipe_sysinfo *info) -{ - info->sys_nr_cpus = num_online_cpus(); - info->sys_cpu_freq = ipipe_cpu_freq(); - info->sys_hrtimer_irq = IPIPE_TIMER_IRQ; - info->sys_hrtimer_freq = __ipipe_core_clock; - info->sys_hrclock_freq = __ipipe_core_clock; - - return 0; -} - -/* - * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline - * just like if it has been actually received from a hw source. Also - * works for virtual interrupts. - */ -int ipipe_trigger_irq(unsigned irq) -{ - unsigned long flags; - -#ifdef CONFIG_IPIPE_DEBUG - if (irq >= IPIPE_NR_IRQS || - (ipipe_virtual_irq_p(irq) - && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) - return -EINVAL; -#endif - - flags = hard_local_irq_save(); - __ipipe_handle_irq(irq, NULL); - hard_local_irq_restore(flags); - - return 1; -} - -asmlinkage void __ipipe_sync_root(void) -{ - void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; - struct ipipe_percpu_domain_data *p; - unsigned long flags; - - BUG_ON(irqs_disabled()); - - flags = hard_local_irq_save(); - - if (irq_tail_hook) - irq_tail_hook(); - - clear_thread_flag(TIF_IRQ_SYNC); - - p = ipipe_root_cpudom_ptr(); - if (__ipipe_ipending_p(p)) - __ipipe_sync_pipeline(); - - hard_local_irq_restore(flags); -} - -void ___ipipe_sync_pipeline(void) -{ - if (__ipipe_root_domain_p && - test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) - return; - - __ipipe_sync_stage(); -} - -void __ipipe_disable_root_irqs_hw(void) -{ - /* - * This code is called by the ins{bwl} routines (see - * arch/blackfin/lib/ins.S), which are heavily used by the - * network stack. It masks all interrupts but those handled by - * non-root domains, so that we keep decent network transfer - * rates for Linux without inducing pathological jitter for - * the real-time domain. - */ - bfin_sti(__ipipe_irq_lvmask); - __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); -} - -void __ipipe_enable_root_irqs_hw(void) -{ - __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); - bfin_sti(bfin_irq_flags); -} - -/* - * We could use standard atomic bitops in the following root status - * manipulation routines, but let's prepare for SMP support in the - * same move, preventing CPU migration as required. - */ -void __ipipe_stall_root(void) -{ - unsigned long *p, flags; - - flags = hard_local_irq_save(); - p = &__ipipe_root_status; - __set_bit(IPIPE_STALL_FLAG, p); - hard_local_irq_restore(flags); -} -EXPORT_SYMBOL(__ipipe_stall_root); - -unsigned long __ipipe_test_and_stall_root(void) -{ - unsigned long *p, flags; - int x; - - flags = hard_local_irq_save(); - p = &__ipipe_root_status; - x = __test_and_set_bit(IPIPE_STALL_FLAG, p); - hard_local_irq_restore(flags); - - return x; -} -EXPORT_SYMBOL(__ipipe_test_and_stall_root); - -unsigned long __ipipe_test_root(void) -{ - const unsigned long *p; - unsigned long flags; - int x; - - flags = hard_local_irq_save_smp(); - p = &__ipipe_root_status; - x = test_bit(IPIPE_STALL_FLAG, p); - hard_local_irq_restore_smp(flags); - - return x; -} -EXPORT_SYMBOL(__ipipe_test_root); - -void __ipipe_lock_root(void) -{ - unsigned long *p, flags; - - flags = hard_local_irq_save(); - p = &__ipipe_root_status; - __set_bit(IPIPE_SYNCDEFER_FLAG, p); - hard_local_irq_restore(flags); -} -EXPORT_SYMBOL(__ipipe_lock_root); - -void __ipipe_unlock_root(void) -{ - unsigned long *p, flags; - - flags = hard_local_irq_save(); - p = &__ipipe_root_status; - __clear_bit(IPIPE_SYNCDEFER_FLAG, p); - hard_local_irq_restore(flags); -} -EXPORT_SYMBOL(__ipipe_unlock_root); diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c deleted file mode 100644 index 052cde5ed2e4..000000000000 --- a/arch/blackfin/kernel/irqchip.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static atomic_t irq_err_count; -void ack_bad_irq(unsigned int irq) -{ - atomic_inc(&irq_err_count); - printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); -} - -static struct irq_desc bad_irq_desc = { - .handle_irq = handle_bad_irq, - .lock = __RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock), -}; - -#ifdef CONFIG_CPUMASK_OFFSTACK -/* We are not allocating a variable-sized bad_irq_desc.affinity */ -#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK." -#endif - -#ifdef CONFIG_PROC_FS -int arch_show_interrupts(struct seq_file *p, int prec) -{ - int j; - - seq_printf(p, "%*s: ", prec, "NMI"); - for_each_online_cpu(j) - seq_printf(p, "%10u ", cpu_pda[j].__nmi_count); - seq_printf(p, " CORE Non Maskable Interrupt\n"); - seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); - return 0; -} -#endif - -#ifdef CONFIG_DEBUG_STACKOVERFLOW -static void check_stack_overflow(int irq) -{ - /* Debugging check for stack overflow: is there less than STACK_WARN free? */ - long sp = __get_SP() & (THREAD_SIZE - 1); - - if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { - dump_stack(); - pr_emerg("irq%i: possible stack overflow only %ld bytes free\n", - irq, sp - sizeof(struct thread_info)); - } -} -#else -static inline void check_stack_overflow(int irq) { } -#endif - -#ifndef CONFIG_IPIPE -static void maybe_lower_to_irq14(void) -{ - unsigned short pending, other_ints; - - /* - * If we're the only interrupt running (ignoring IRQ15 which - * is for syscalls), lower our priority to IRQ14 so that - * softirqs run at that level. If there's another, - * lower-level interrupt, irq_exit will defer softirqs to - * that. If the interrupt pipeline is enabled, we are already - * running at IRQ14 priority, so we don't need this code. - */ - CSYNC(); - pending = bfin_read_IPEND() & ~0x8000; - other_ints = pending & (pending - 1); - if (other_ints == 0) - lower_to_irq14(); -} -#else -static inline void maybe_lower_to_irq14(void) { } -#endif - -/* - * do_IRQ handles all hardware IRQs. Decoded IRQs should not - * come via this function. Instead, they should provide their - * own 'handler' - */ -#ifdef CONFIG_DO_IRQ_L1 -__attribute__((l1_text)) -#endif -asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) -{ - struct pt_regs *old_regs = set_irq_regs(regs); - - irq_enter(); - - check_stack_overflow(irq); - - /* - * Some hardware gives randomly wrong interrupts. Rather - * than crashing, do something sensible. - */ - if (irq >= NR_IRQS) - handle_bad_irq(&bad_irq_desc); - else - generic_handle_irq(irq); - - maybe_lower_to_irq14(); - - irq_exit(); - - set_irq_regs(old_regs); -} - -void __init init_IRQ(void) -{ - init_arch_irq(); - -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - /* Now that evt_ivhw is set up, turn this on */ - trace_buff_offset = 0; - bfin_write_TBUFCTL(BFIN_TRACE_ON); - printk(KERN_INFO "Hardware Trace expanded to %ik\n", - 1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN); -#endif -} diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c deleted file mode 100644 index cf773f0f1f30..000000000000 --- a/arch/blackfin/kernel/kgdb.c +++ /dev/null @@ -1,473 +0,0 @@ -/* - * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include /* for linux pt_regs struct */ -#include -#include -#include - -void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - gdb_regs[BFIN_R0] = regs->r0; - gdb_regs[BFIN_R1] = regs->r1; - gdb_regs[BFIN_R2] = regs->r2; - gdb_regs[BFIN_R3] = regs->r3; - gdb_regs[BFIN_R4] = regs->r4; - gdb_regs[BFIN_R5] = regs->r5; - gdb_regs[BFIN_R6] = regs->r6; - gdb_regs[BFIN_R7] = regs->r7; - gdb_regs[BFIN_P0] = regs->p0; - gdb_regs[BFIN_P1] = regs->p1; - gdb_regs[BFIN_P2] = regs->p2; - gdb_regs[BFIN_P3] = regs->p3; - gdb_regs[BFIN_P4] = regs->p4; - gdb_regs[BFIN_P5] = regs->p5; - gdb_regs[BFIN_SP] = regs->reserved; - gdb_regs[BFIN_FP] = regs->fp; - gdb_regs[BFIN_I0] = regs->i0; - gdb_regs[BFIN_I1] = regs->i1; - gdb_regs[BFIN_I2] = regs->i2; - gdb_regs[BFIN_I3] = regs->i3; - gdb_regs[BFIN_M0] = regs->m0; - gdb_regs[BFIN_M1] = regs->m1; - gdb_regs[BFIN_M2] = regs->m2; - gdb_regs[BFIN_M3] = regs->m3; - gdb_regs[BFIN_B0] = regs->b0; - gdb_regs[BFIN_B1] = regs->b1; - gdb_regs[BFIN_B2] = regs->b2; - gdb_regs[BFIN_B3] = regs->b3; - gdb_regs[BFIN_L0] = regs->l0; - gdb_regs[BFIN_L1] = regs->l1; - gdb_regs[BFIN_L2] = regs->l2; - gdb_regs[BFIN_L3] = regs->l3; - gdb_regs[BFIN_A0_DOT_X] = regs->a0x; - gdb_regs[BFIN_A0_DOT_W] = regs->a0w; - gdb_regs[BFIN_A1_DOT_X] = regs->a1x; - gdb_regs[BFIN_A1_DOT_W] = regs->a1w; - gdb_regs[BFIN_ASTAT] = regs->astat; - gdb_regs[BFIN_RETS] = regs->rets; - gdb_regs[BFIN_LC0] = regs->lc0; - gdb_regs[BFIN_LT0] = regs->lt0; - gdb_regs[BFIN_LB0] = regs->lb0; - gdb_regs[BFIN_LC1] = regs->lc1; - gdb_regs[BFIN_LT1] = regs->lt1; - gdb_regs[BFIN_LB1] = regs->lb1; - gdb_regs[BFIN_CYCLES] = 0; - gdb_regs[BFIN_CYCLES2] = 0; - gdb_regs[BFIN_USP] = regs->usp; - gdb_regs[BFIN_SEQSTAT] = regs->seqstat; - gdb_regs[BFIN_SYSCFG] = regs->syscfg; - gdb_regs[BFIN_RETI] = regs->pc; - gdb_regs[BFIN_RETX] = regs->retx; - gdb_regs[BFIN_RETN] = regs->retn; - gdb_regs[BFIN_RETE] = regs->rete; - gdb_regs[BFIN_PC] = regs->pc; - gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1; - gdb_regs[BFIN_EXTRA1] = 0; - gdb_regs[BFIN_EXTRA2] = 0; - gdb_regs[BFIN_EXTRA3] = 0; - gdb_regs[BFIN_IPEND] = regs->ipend; -} - -/* - * Extracts ebp, esp and eip values understandable by gdb from the values - * saved by switch_to. - * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp - * prior to entering switch_to is 8 greater than the value that is saved. - * If switch_to changes, change following code appropriately. - */ -void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) -{ - gdb_regs[BFIN_SP] = p->thread.ksp; - gdb_regs[BFIN_PC] = p->thread.pc; - gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat; -} - -void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) -{ - regs->r0 = gdb_regs[BFIN_R0]; - regs->r1 = gdb_regs[BFIN_R1]; - regs->r2 = gdb_regs[BFIN_R2]; - regs->r3 = gdb_regs[BFIN_R3]; - regs->r4 = gdb_regs[BFIN_R4]; - regs->r5 = gdb_regs[BFIN_R5]; - regs->r6 = gdb_regs[BFIN_R6]; - regs->r7 = gdb_regs[BFIN_R7]; - regs->p0 = gdb_regs[BFIN_P0]; - regs->p1 = gdb_regs[BFIN_P1]; - regs->p2 = gdb_regs[BFIN_P2]; - regs->p3 = gdb_regs[BFIN_P3]; - regs->p4 = gdb_regs[BFIN_P4]; - regs->p5 = gdb_regs[BFIN_P5]; - regs->fp = gdb_regs[BFIN_FP]; - regs->i0 = gdb_regs[BFIN_I0]; - regs->i1 = gdb_regs[BFIN_I1]; - regs->i2 = gdb_regs[BFIN_I2]; - regs->i3 = gdb_regs[BFIN_I3]; - regs->m0 = gdb_regs[BFIN_M0]; - regs->m1 = gdb_regs[BFIN_M1]; - regs->m2 = gdb_regs[BFIN_M2]; - regs->m3 = gdb_regs[BFIN_M3]; - regs->b0 = gdb_regs[BFIN_B0]; - regs->b1 = gdb_regs[BFIN_B1]; - regs->b2 = gdb_regs[BFIN_B2]; - regs->b3 = gdb_regs[BFIN_B3]; - regs->l0 = gdb_regs[BFIN_L0]; - regs->l1 = gdb_regs[BFIN_L1]; - regs->l2 = gdb_regs[BFIN_L2]; - regs->l3 = gdb_regs[BFIN_L3]; - regs->a0x = gdb_regs[BFIN_A0_DOT_X]; - regs->a0w = gdb_regs[BFIN_A0_DOT_W]; - regs->a1x = gdb_regs[BFIN_A1_DOT_X]; - regs->a1w = gdb_regs[BFIN_A1_DOT_W]; - regs->rets = gdb_regs[BFIN_RETS]; - regs->lc0 = gdb_regs[BFIN_LC0]; - regs->lt0 = gdb_regs[BFIN_LT0]; - regs->lb0 = gdb_regs[BFIN_LB0]; - regs->lc1 = gdb_regs[BFIN_LC1]; - regs->lt1 = gdb_regs[BFIN_LT1]; - regs->lb1 = gdb_regs[BFIN_LB1]; - regs->usp = gdb_regs[BFIN_USP]; - regs->syscfg = gdb_regs[BFIN_SYSCFG]; - regs->retx = gdb_regs[BFIN_RETX]; - regs->retn = gdb_regs[BFIN_RETN]; - regs->rete = gdb_regs[BFIN_RETE]; - regs->pc = gdb_regs[BFIN_PC]; - -#if 0 /* can't change these */ - regs->astat = gdb_regs[BFIN_ASTAT]; - regs->seqstat = gdb_regs[BFIN_SEQSTAT]; - regs->ipend = gdb_regs[BFIN_IPEND]; -#endif -} - -static struct hw_breakpoint { - unsigned int occupied:1; - unsigned int skip:1; - unsigned int enabled:1; - unsigned int type:1; - unsigned int dataacc:2; - unsigned short count; - unsigned int addr; -} breakinfo[HW_WATCHPOINT_NUM]; - -static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type) -{ - int breakno; - int bfin_type; - int dataacc = 0; - - switch (type) { - case BP_HARDWARE_BREAKPOINT: - bfin_type = TYPE_INST_WATCHPOINT; - break; - case BP_WRITE_WATCHPOINT: - dataacc = 1; - bfin_type = TYPE_DATA_WATCHPOINT; - break; - case BP_READ_WATCHPOINT: - dataacc = 2; - bfin_type = TYPE_DATA_WATCHPOINT; - break; - case BP_ACCESS_WATCHPOINT: - dataacc = 3; - bfin_type = TYPE_DATA_WATCHPOINT; - break; - default: - return -ENOSPC; - } - - /* Because hardware data watchpoint impelemented in current - * Blackfin can not trigger an exception event as the hardware - * instrction watchpoint does, we ignaore all data watch point here. - * They can be turned on easily after future blackfin design - * supports this feature. - */ - for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++) - if (bfin_type == breakinfo[breakno].type - && !breakinfo[breakno].occupied) { - breakinfo[breakno].occupied = 1; - breakinfo[breakno].skip = 0; - breakinfo[breakno].enabled = 1; - breakinfo[breakno].addr = addr; - breakinfo[breakno].dataacc = dataacc; - breakinfo[breakno].count = 0; - return 0; - } - - return -ENOSPC; -} - -static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type) -{ - int breakno; - int bfin_type; - - switch (type) { - case BP_HARDWARE_BREAKPOINT: - bfin_type = TYPE_INST_WATCHPOINT; - break; - case BP_WRITE_WATCHPOINT: - case BP_READ_WATCHPOINT: - case BP_ACCESS_WATCHPOINT: - bfin_type = TYPE_DATA_WATCHPOINT; - break; - default: - return 0; - } - for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++) - if (bfin_type == breakinfo[breakno].type - && breakinfo[breakno].occupied - && breakinfo[breakno].addr == addr) { - breakinfo[breakno].occupied = 0; - breakinfo[breakno].enabled = 0; - } - - return 0; -} - -static void bfin_remove_all_hw_break(void) -{ - int breakno; - - memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM); - - for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++) - breakinfo[breakno].type = TYPE_INST_WATCHPOINT; - for (; breakno < HW_WATCHPOINT_NUM; breakno++) - breakinfo[breakno].type = TYPE_DATA_WATCHPOINT; -} - -static void bfin_correct_hw_break(void) -{ - int breakno; - unsigned int wpiactl = 0; - unsigned int wpdactl = 0; - int enable_wp = 0; - - for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++) - if (breakinfo[breakno].enabled) { - enable_wp = 1; - - switch (breakno) { - case 0: - wpiactl |= WPIAEN0|WPICNTEN0; - bfin_write_WPIA0(breakinfo[breakno].addr); - bfin_write_WPIACNT0(breakinfo[breakno].count - + breakinfo->skip); - break; - case 1: - wpiactl |= WPIAEN1|WPICNTEN1; - bfin_write_WPIA1(breakinfo[breakno].addr); - bfin_write_WPIACNT1(breakinfo[breakno].count - + breakinfo->skip); - break; - case 2: - wpiactl |= WPIAEN2|WPICNTEN2; - bfin_write_WPIA2(breakinfo[breakno].addr); - bfin_write_WPIACNT2(breakinfo[breakno].count - + breakinfo->skip); - break; - case 3: - wpiactl |= WPIAEN3|WPICNTEN3; - bfin_write_WPIA3(breakinfo[breakno].addr); - bfin_write_WPIACNT3(breakinfo[breakno].count - + breakinfo->skip); - break; - case 4: - wpiactl |= WPIAEN4|WPICNTEN4; - bfin_write_WPIA4(breakinfo[breakno].addr); - bfin_write_WPIACNT4(breakinfo[breakno].count - + breakinfo->skip); - break; - case 5: - wpiactl |= WPIAEN5|WPICNTEN5; - bfin_write_WPIA5(breakinfo[breakno].addr); - bfin_write_WPIACNT5(breakinfo[breakno].count - + breakinfo->skip); - break; - case 6: - wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0; - wpdactl |= breakinfo[breakno].dataacc - << WPDACC0_OFFSET; - bfin_write_WPDA0(breakinfo[breakno].addr); - bfin_write_WPDACNT0(breakinfo[breakno].count - + breakinfo->skip); - break; - case 7: - wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1; - wpdactl |= breakinfo[breakno].dataacc - << WPDACC1_OFFSET; - bfin_write_WPDA1(breakinfo[breakno].addr); - bfin_write_WPDACNT1(breakinfo[breakno].count - + breakinfo->skip); - break; - } - } - - /* Should enable WPPWR bit first before set any other - * WPIACTL and WPDACTL bits */ - if (enable_wp) { - bfin_write_WPIACTL(WPPWR); - CSYNC(); - bfin_write_WPIACTL(wpiactl|WPPWR); - bfin_write_WPDACTL(wpdactl); - CSYNC(); - } -} - -static void bfin_disable_hw_debug(struct pt_regs *regs) -{ - /* Disable hardware debugging while we are in kgdb */ - bfin_write_WPIACTL(0); - bfin_write_WPDACTL(0); - CSYNC(); -} - -#ifdef CONFIG_SMP -void kgdb_passive_cpu_callback(void *info) -{ - kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs()); -} - -void kgdb_roundup_cpus(unsigned long flags) -{ - unsigned int cpu; - - for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids; - cpu = cpumask_next(cpu, cpu_online_mask)) - smp_call_function_single(cpu, kgdb_passive_cpu_callback, - NULL, 0); -} - -void kgdb_roundup_cpu(int cpu, unsigned long flags) -{ - smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0); -} -#endif - -#ifdef CONFIG_IPIPE -static unsigned long kgdb_arch_imask; -#endif - -int kgdb_arch_handle_exception(int vector, int signo, - int err_code, char *remcom_in_buffer, - char *remcom_out_buffer, - struct pt_regs *regs) -{ - long addr; - char *ptr; - int newPC; - int i; - - switch (remcom_in_buffer[0]) { - case 'c': - case 's': - if (kgdb_contthread && kgdb_contthread != current) { - strcpy(remcom_out_buffer, "E00"); - break; - } - - kgdb_contthread = NULL; - - /* try to read optional parameter, pc unchanged if no parm */ - ptr = &remcom_in_buffer[1]; - if (kgdb_hex2long(&ptr, &addr)) { - regs->retx = addr; - } - newPC = regs->retx; - - /* clear the trace bit */ - regs->syscfg &= 0xfffffffe; - - /* set the trace bit if we're stepping */ - if (remcom_in_buffer[0] == 's') { - regs->syscfg |= 0x1; - kgdb_single_step = regs->ipend; - kgdb_single_step >>= 6; - for (i = 10; i > 0; i--, kgdb_single_step >>= 1) - if (kgdb_single_step & 1) - break; - /* i indicate event priority of current stopped instruction - * user space instruction is 0, IVG15 is 1, IVTMR is 10. - * kgdb_single_step > 0 means in single step mode - */ - kgdb_single_step = i + 1; - - preempt_disable(); -#ifdef CONFIG_IPIPE - kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask; - cpu_pda[raw_smp_processor_id()].ex_imask = 0; -#endif - } - - bfin_correct_hw_break(); - - return 0; - } /* switch */ - return -1; /* this means that we do not want to exit from the handler */ -} - -struct kgdb_arch arch_kgdb_ops = { - .gdb_bpt_instr = {0xa1}, - .flags = KGDB_HW_BREAKPOINT, - .set_hw_breakpoint = bfin_set_hw_break, - .remove_hw_breakpoint = bfin_remove_hw_break, - .disable_hw_break = bfin_disable_hw_debug, - .remove_all_hw_break = bfin_remove_all_hw_break, - .correct_hw_break = bfin_correct_hw_break, -}; - -#define IN_MEM(addr, size, l1_addr, l1_size) \ -({ \ - unsigned long __addr = (unsigned long)(addr); \ - (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ -}) -#define ASYNC_BANK_SIZE \ - (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ - ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) - -int kgdb_validate_break_address(unsigned long addr) -{ - int cpu = raw_smp_processor_id(); - - if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end) - return 0; - if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) - return 0; - if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) - return 0; -#ifdef CONFIG_SMP - else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH)) - return 0; -#endif - if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH)) - return 0; - - return -EFAULT; -} - -void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip) -{ - regs->retx = ip; -} - -int kgdb_arch_init(void) -{ - kgdb_single_step = 0; -#ifdef CONFIG_IPIPE - kgdb_arch_imask = 0; -#endif - - bfin_remove_all_hw_break(); - return 0; -} - -void kgdb_arch_exit(void) -{ -} diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c deleted file mode 100644 index b8b785dc4e3b..000000000000 --- a/arch/blackfin/kernel/kgdb_test.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * arch/blackfin/kernel/kgdb_test.c - Blackfin kgdb tests - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -#include -#include - -#include - -/* Symbols are here for kgdb test to poke directly */ -static char cmdline[256]; -static size_t len; - -#ifndef CONFIG_SMP -static int num1 __attribute__((l1_data)); - -void kgdb_l1_test(void) __attribute__((l1_text)); - -void kgdb_l1_test(void) -{ - pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); - pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test); - num1 = num1 + 10; - pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); -} -#endif - -#if L2_LENGTH - -static int num2 __attribute__((l2)); -void kgdb_l2_test(void) __attribute__((l2)); - -void kgdb_l2_test(void) -{ - pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); - pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test); - num2 = num2 + 20; - pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); -} - -#endif - -noinline int kgdb_test(char *name, int len, int count, int z) -{ - pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z); - count = z; - return count; -} - -static ssize_t -kgdb_test_proc_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) -{ - kgdb_test("hello world!", 12, 0x55, 0x10); -#ifndef CONFIG_SMP - kgdb_l1_test(); -#endif -#if L2_LENGTH - kgdb_l2_test(); -#endif - - return 0; -} - -static ssize_t -kgdb_test_proc_write(struct file *file, const char __user *buffer, - size_t count, loff_t *pos) -{ - len = min_t(size_t, 255, count); - memcpy(cmdline, buffer, count); - cmdline[len] = 0; - - return len; -} - -static const struct file_operations kgdb_test_proc_fops = { - .owner = THIS_MODULE, - .read = kgdb_test_proc_read, - .write = kgdb_test_proc_write, - .llseek = noop_llseek, -}; - -static int __init kgdbtest_init(void) -{ - struct proc_dir_entry *entry; - -#if L2_LENGTH - num2 = 0; -#endif - - entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops); - if (entry == NULL) - return -ENOMEM; - - return 0; -} - -static void __exit kgdbtest_exit(void) -{ - remove_proc_entry("kgdbtest", NULL); -} - -module_init(kgdbtest_init); -module_exit(kgdbtest_exit); -MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c deleted file mode 100644 index 15af5768c403..000000000000 --- a/arch/blackfin/kernel/module.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define mod_err(mod, fmt, ...) \ - pr_err("module %s: " fmt, (mod)->name, ##__VA_ARGS__) -#define mod_debug(mod, fmt, ...) \ - pr_debug("module %s: " fmt, (mod)->name, ##__VA_ARGS__) - -/* Transfer the section to the L1 memory */ -int -module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, - char *secstrings, struct module *mod) -{ - /* - * XXX: sechdrs are vmalloced in kernel/module.c - * and would be vfreed just after module is loaded, - * so we hack to keep the only information we needed - * in mod->arch to correctly free L1 I/D sram later. - * NOTE: this breaks the semantic of mod->arch structure. - */ - Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; - void *dest; - - for (s = sechdrs; s < sechdrs_end; ++s) { - const char *shname = secstrings + s->sh_name; - - if (s->sh_size == 0) - continue; - - if (!strcmp(".l1.text", shname) || - (!strcmp(".text", shname) && - (hdr->e_flags & EF_BFIN_CODE_IN_L1))) { - - dest = l1_inst_sram_alloc(s->sh_size); - mod->arch.text_l1 = dest; - if (dest == NULL) { - mod_err(mod, "L1 inst memory allocation failed\n"); - return -1; - } - dma_memcpy(dest, (void *)s->sh_addr, s->sh_size); - - } else if (!strcmp(".l1.data", shname) || - (!strcmp(".data", shname) && - (hdr->e_flags & EF_BFIN_DATA_IN_L1))) { - - dest = l1_data_sram_alloc(s->sh_size); - mod->arch.data_a_l1 = dest; - if (dest == NULL) { - mod_err(mod, "L1 data memory allocation failed\n"); - return -1; - } - memcpy(dest, (void *)s->sh_addr, s->sh_size); - - } else if (!strcmp(".l1.bss", shname) || - (!strcmp(".bss", shname) && - (hdr->e_flags & EF_BFIN_DATA_IN_L1))) { - - dest = l1_data_sram_zalloc(s->sh_size); - mod->arch.bss_a_l1 = dest; - if (dest == NULL) { - mod_err(mod, "L1 data memory allocation failed\n"); - return -1; - } - - } else if (!strcmp(".l1.data.B", shname)) { - - dest = l1_data_B_sram_alloc(s->sh_size); - mod->arch.data_b_l1 = dest; - if (dest == NULL) { - mod_err(mod, "L1 data memory allocation failed\n"); - return -1; - } - memcpy(dest, (void *)s->sh_addr, s->sh_size); - - } else if (!strcmp(".l1.bss.B", shname)) { - - dest = l1_data_B_sram_alloc(s->sh_size); - mod->arch.bss_b_l1 = dest; - if (dest == NULL) { - mod_err(mod, "L1 data memory allocation failed\n"); - return -1; - } - memset(dest, 0, s->sh_size); - - } else if (!strcmp(".l2.text", shname) || - (!strcmp(".text", shname) && - (hdr->e_flags & EF_BFIN_CODE_IN_L2))) { - - dest = l2_sram_alloc(s->sh_size); - mod->arch.text_l2 = dest; - if (dest == NULL) { - mod_err(mod, "L2 SRAM allocation failed\n"); - return -1; - } - memcpy(dest, (void *)s->sh_addr, s->sh_size); - - } else if (!strcmp(".l2.data", shname) || - (!strcmp(".data", shname) && - (hdr->e_flags & EF_BFIN_DATA_IN_L2))) { - - dest = l2_sram_alloc(s->sh_size); - mod->arch.data_l2 = dest; - if (dest == NULL) { - mod_err(mod, "L2 SRAM allocation failed\n"); - return -1; - } - memcpy(dest, (void *)s->sh_addr, s->sh_size); - - } else if (!strcmp(".l2.bss", shname) || - (!strcmp(".bss", shname) && - (hdr->e_flags & EF_BFIN_DATA_IN_L2))) { - - dest = l2_sram_zalloc(s->sh_size); - mod->arch.bss_l2 = dest; - if (dest == NULL) { - mod_err(mod, "L2 SRAM allocation failed\n"); - return -1; - } - - } else - continue; - - s->sh_flags &= ~SHF_ALLOC; - s->sh_addr = (unsigned long)dest; - } - - return 0; -} - -/*************************************************************************/ -/* FUNCTION : apply_relocate_add */ -/* ABSTRACT : Blackfin specific relocation handling for the loadable */ -/* modules. Modules are expected to be .o files. */ -/* Arithmetic relocations are handled. */ -/* We do not expect LSETUP to be split and hence is not */ -/* handled. */ -/* R_BFIN_BYTE and R_BFIN_BYTE2 are also not handled as the */ -/* gas does not generate it. */ -/*************************************************************************/ -int -apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, - unsigned int symindex, unsigned int relsec, - struct module *mod) -{ - unsigned int i; - Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - unsigned long location, value, size; - - mod_debug(mod, "applying relocate section %u to %u\n", - relsec, sechdrs[relsec].sh_info); - - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = sechdrs[sechdrs[relsec].sh_info].sh_addr + - rel[i].r_offset; - - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *) sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - value = sym->st_value; - value += rel[i].r_addend; - -#ifdef CONFIG_SMP - if (location >= COREB_L1_DATA_A_START) { - mod_err(mod, "cannot relocate in L1: %u (SMP kernel)\n", - ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } -#endif - - mod_debug(mod, "location is %lx, value is %lx type is %d\n", - location, value, ELF32_R_TYPE(rel[i].r_info)); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - - case R_BFIN_HUIMM16: - value >>= 16; - case R_BFIN_LUIMM16: - case R_BFIN_RIMM16: - size = 2; - break; - case R_BFIN_BYTE4_DATA: - size = 4; - break; - - case R_BFIN_PCREL24: - case R_BFIN_PCREL24_JUMP_L: - case R_BFIN_PCREL12_JUMP: - case R_BFIN_PCREL12_JUMP_S: - case R_BFIN_PCREL10: - mod_err(mod, "unsupported relocation: %u (no -mlong-calls?)\n", - ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - - default: - mod_err(mod, "unknown relocation: %u\n", - ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - - switch (bfin_mem_access_type(location, size)) { - case BFIN_MEM_ACCESS_CORE: - case BFIN_MEM_ACCESS_CORE_ONLY: - memcpy((void *)location, &value, size); - break; - case BFIN_MEM_ACCESS_DMA: - dma_memcpy((void *)location, &value, size); - break; - case BFIN_MEM_ACCESS_ITEST: - isram_memcpy((void *)location, &value, size); - break; - default: - mod_err(mod, "invalid relocation for %#lx\n", location); - return -ENOEXEC; - } - } - - return 0; -} - -int -module_finalize(const Elf_Ehdr * hdr, - const Elf_Shdr * sechdrs, struct module *mod) -{ - unsigned int i, strindex = 0, symindex = 0; - char *secstrings; - long err = 0; - - secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; - - for (i = 1; i < hdr->e_shnum; i++) { - /* Internal symbols and strings. */ - if (sechdrs[i].sh_type == SHT_SYMTAB) { - symindex = i; - strindex = sechdrs[i].sh_link; - } - } - - for (i = 1; i < hdr->e_shnum; i++) { - const char *strtab = (char *)sechdrs[strindex].sh_addr; - unsigned int info = sechdrs[i].sh_info; - const char *shname = secstrings + sechdrs[i].sh_name; - - /* Not a valid relocation section? */ - if (info >= hdr->e_shnum) - continue; - - /* Only support RELA relocation types */ - if (sechdrs[i].sh_type != SHT_RELA) - continue; - - if (!strcmp(".rela.l2.text", shname) || - !strcmp(".rela.l1.text", shname) || - (!strcmp(".rela.text", shname) && - (hdr->e_flags & (EF_BFIN_CODE_IN_L1 | EF_BFIN_CODE_IN_L2)))) { - - err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab, - symindex, i, mod); - if (err < 0) - return -ENOEXEC; - } - } - - return 0; -} - -void module_arch_cleanup(struct module *mod) -{ - l1_inst_sram_free(mod->arch.text_l1); - l1_data_A_sram_free(mod->arch.data_a_l1); - l1_data_A_sram_free(mod->arch.bss_a_l1); - l1_data_B_sram_free(mod->arch.data_b_l1); - l1_data_B_sram_free(mod->arch.bss_b_l1); - l2_sram_free(mod->arch.text_l2); - l2_sram_free(mod->arch.data_l2); - l2_sram_free(mod->arch.bss_l2); -} diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c deleted file mode 100644 index 8a211d95821f..000000000000 --- a/arch/blackfin/kernel/nmi.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Blackfin nmi_watchdog Driver - * - * Originally based on bfin_wdt.c - * Copyright 2010-2010 Analog Devices Inc. - * Graff Yang - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRV_NAME "nmi-wdt" - -#define NMI_WDT_TIMEOUT 5 /* 5 seconds */ -#define NMI_CHECK_TIMEOUT (4 * HZ) /* 4 seconds in jiffies */ -static int nmi_wdt_cpu = 1; - -static unsigned int timeout = NMI_WDT_TIMEOUT; -static int nmi_active; - -static unsigned short wdoga_ctl; -static unsigned int wdoga_cnt; -static struct corelock_slot saved_corelock; -static atomic_t nmi_touched[NR_CPUS]; -static struct timer_list ntimer; - -enum { - COREA_ENTER_NMI = 0, - COREA_EXIT_NMI, - COREB_EXIT_NMI, - - NMI_EVENT_NR, -}; -static unsigned long nmi_event __attribute__ ((__section__(".l2.bss"))); - -/* we are in nmi, non-atomic bit ops is safe */ -static inline void set_nmi_event(int event) -{ - __set_bit(event, &nmi_event); -} - -static inline void wait_nmi_event(int event) -{ - while (!test_bit(event, &nmi_event)) - barrier(); - __clear_bit(event, &nmi_event); -} - -static inline void send_corea_nmi(void) -{ - wdoga_ctl = bfin_read_WDOGA_CTL(); - wdoga_cnt = bfin_read_WDOGA_CNT(); - - bfin_write_WDOGA_CTL(WDEN_DISABLE); - bfin_write_WDOGA_CNT(0); - bfin_write_WDOGA_CTL(WDEN_ENABLE | ICTL_NMI); -} - -static inline void restore_corea_nmi(void) -{ - bfin_write_WDOGA_CTL(WDEN_DISABLE); - bfin_write_WDOGA_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE); - - bfin_write_WDOGA_CNT(wdoga_cnt); - bfin_write_WDOGA_CTL(wdoga_ctl); -} - -static inline void save_corelock(void) -{ - saved_corelock = corelock; - corelock.lock = 0; -} - -static inline void restore_corelock(void) -{ - corelock = saved_corelock; -} - - -static inline void nmi_wdt_keepalive(void) -{ - bfin_write_WDOGB_STAT(0); -} - -static inline void nmi_wdt_stop(void) -{ - bfin_write_WDOGB_CTL(WDEN_DISABLE); -} - -/* before calling this function, you must stop the WDT */ -static inline void nmi_wdt_clear(void) -{ - /* clear TRO bit, disable event generation */ - bfin_write_WDOGB_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE); -} - -static inline void nmi_wdt_start(void) -{ - bfin_write_WDOGB_CTL(WDEN_ENABLE | ICTL_NMI); -} - -static inline int nmi_wdt_running(void) -{ - return ((bfin_read_WDOGB_CTL() & WDEN_MASK) != WDEN_DISABLE); -} - -static inline int nmi_wdt_set_timeout(unsigned long t) -{ - u32 cnt, max_t, sclk; - int run; - - sclk = get_sclk(); - max_t = -1 / sclk; - cnt = t * sclk; - if (t > max_t) { - pr_warning("NMI: timeout value is too large\n"); - return -EINVAL; - } - - run = nmi_wdt_running(); - nmi_wdt_stop(); - bfin_write_WDOGB_CNT(cnt); - if (run) - nmi_wdt_start(); - - timeout = t; - - return 0; -} - -int check_nmi_wdt_touched(void) -{ - unsigned int this_cpu = smp_processor_id(); - unsigned int cpu; - cpumask_t mask; - - cpumask_copy(&mask, cpu_online_mask); - if (!atomic_read(&nmi_touched[this_cpu])) - return 0; - - atomic_set(&nmi_touched[this_cpu], 0); - - cpumask_clear_cpu(this_cpu, &mask); - for_each_cpu(cpu, &mask) { - invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]), - (unsigned long)(&nmi_touched[cpu])); - if (!atomic_read(&nmi_touched[cpu])) - return 0; - atomic_set(&nmi_touched[cpu], 0); - } - - return 1; -} - -static void nmi_wdt_timer(struct timer_list *unused) -{ - if (check_nmi_wdt_touched()) - nmi_wdt_keepalive(); - - mod_timer(&ntimer, jiffies + NMI_CHECK_TIMEOUT); -} - -static int __init init_nmi_wdt(void) -{ - nmi_wdt_set_timeout(timeout); - nmi_wdt_start(); - nmi_active = true; - - timer_setup(&ntimer, nmi_wdt_timer, 0); - ntimer.expires = jiffies + NMI_CHECK_TIMEOUT; - add_timer(&ntimer); - - pr_info("nmi_wdt: initialized: timeout=%d sec\n", timeout); - return 0; -} -device_initcall(init_nmi_wdt); - -void arch_touch_nmi_watchdog(void) -{ - atomic_set(&nmi_touched[smp_processor_id()], 1); -} - -/* Suspend/resume support */ -#ifdef CONFIG_PM -static int nmi_wdt_suspend(void) -{ - nmi_wdt_stop(); - return 0; -} - -static void nmi_wdt_resume(void) -{ - if (nmi_active) - nmi_wdt_start(); -} - -static struct syscore_ops nmi_syscore_ops = { - .resume = nmi_wdt_resume, - .suspend = nmi_wdt_suspend, -}; - -static int __init init_nmi_wdt_syscore(void) -{ - if (nmi_active) - register_syscore_ops(&nmi_syscore_ops); - - return 0; -} -late_initcall(init_nmi_wdt_syscore); - -#endif /* CONFIG_PM */ - - -asmlinkage notrace void do_nmi(struct pt_regs *fp) -{ - unsigned int cpu = smp_processor_id(); - nmi_enter(); - - cpu_pda[cpu].__nmi_count += 1; - - if (cpu == nmi_wdt_cpu) { - /* CoreB goes here first */ - - /* reload the WDOG_STAT */ - nmi_wdt_keepalive(); - - /* clear nmi interrupt for CoreB */ - nmi_wdt_stop(); - nmi_wdt_clear(); - - /* trigger NMI interrupt of CoreA */ - send_corea_nmi(); - - /* waiting CoreB to enter NMI */ - wait_nmi_event(COREA_ENTER_NMI); - - /* recover WDOGA's settings */ - restore_corea_nmi(); - - save_corelock(); - - /* corelock is save/cleared, CoreA is dummping messages */ - - wait_nmi_event(COREA_EXIT_NMI); - } else { - /* OK, CoreA entered NMI */ - set_nmi_event(COREA_ENTER_NMI); - } - - pr_emerg("\nNMI Watchdog detected LOCKUP, dump for CPU %d\n", cpu); - dump_bfin_process(fp); - dump_bfin_mem(fp); - show_regs(fp); - dump_bfin_trace_buffer(); - show_stack(current, (unsigned long *)fp); - - if (cpu == nmi_wdt_cpu) { - pr_emerg("This fault is not recoverable, sorry!\n"); - - /* CoreA dump finished, restore the corelock */ - restore_corelock(); - - set_nmi_event(COREB_EXIT_NMI); - } else { - /* CoreB dump finished, notice the CoreA we are done */ - set_nmi_event(COREA_EXIT_NMI); - - /* synchronize with CoreA */ - wait_nmi_event(COREB_EXIT_NMI); - } - - nmi_exit(); -} diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c deleted file mode 100644 index 6a9524ad04a5..000000000000 --- a/arch/blackfin/kernel/perf_event.c +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Blackfin performance counters - * - * Copyright 2011 Analog Devices Inc. - * - * Ripped from SuperH version: - * - * Copyright (C) 2009 Paul Mundt - * - * Heavily based on the x86 and PowerPC implementations. - * - * x86: - * Copyright (C) 2008 Thomas Gleixner - * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar - * Copyright (C) 2009 Jaswinder Singh Rajput - * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter - * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra - * Copyright (C) 2009 Intel Corporation, - * - * ppc: - * Copyright 2008-2009 Paul Mackerras, IBM Corporation. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include - -/* - * We have two counters, and each counter can support an event type. - * The 'o' is PFCNTx=1 and 's' is PFCNTx=0 - * - * 0x04 o pc invariant branches - * 0x06 o mispredicted branches - * 0x09 o predicted branches taken - * 0x0B o EXCPT insn - * 0x0C o CSYNC/SSYNC insn - * 0x0D o Insns committed - * 0x0E o Interrupts taken - * 0x0F o Misaligned address exceptions - * 0x80 o Code memory fetches stalled due to DMA - * 0x83 o 64bit insn fetches delivered - * 0x9A o data cache fills (bank a) - * 0x9B o data cache fills (bank b) - * 0x9C o data cache lines evicted (bank a) - * 0x9D o data cache lines evicted (bank b) - * 0x9E o data cache high priority fills - * 0x9F o data cache low priority fills - * 0x00 s loop 0 iterations - * 0x01 s loop 1 iterations - * 0x0A s CSYNC/SSYNC stalls - * 0x10 s DAG read/after write hazards - * 0x13 s RAW data hazards - * 0x81 s code TAG stalls - * 0x82 s code fill stalls - * 0x90 s processor to memory stalls - * 0x91 s data memory stalls not hidden by 0x90 - * 0x92 s data store buffer full stalls - * 0x93 s data memory write buffer full stalls due to high->low priority - * 0x95 s data memory fill buffer stalls - * 0x96 s data TAG collision stalls - * 0x97 s data collision stalls - * 0x98 s data stalls - * 0x99 s data stalls sent to processor - */ - -static const int event_map[] = { - /* use CYCLES cpu register */ - [PERF_COUNT_HW_CPU_CYCLES] = -1, - [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D, - [PERF_COUNT_HW_CACHE_REFERENCES] = -1, - [PERF_COUNT_HW_CACHE_MISSES] = 0x83, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09, - [PERF_COUNT_HW_BRANCH_MISSES] = 0x06, - [PERF_COUNT_HW_BUS_CYCLES] = -1, -}; - -#define C(x) PERF_COUNT_HW_CACHE_##x - -static const int cache_events[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = -{ - [C(L1D)] = { /* Data bank A */ - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = 0, - [C(RESULT_MISS) ] = 0x9A, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = 0, - [C(RESULT_MISS) ] = 0, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = 0, - [C(RESULT_MISS) ] = 0, - }, - }, - - [C(L1I)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = 0, - [C(RESULT_MISS) ] = 0x83, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = 0, - [C(RESULT_MISS) ] = 0, - }, - }, - - [C(LL)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - }, - - [C(DTLB)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - }, - - [C(ITLB)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - }, - - [C(BPU)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS) ] = -1, - }, - }, -}; - -const char *perf_pmu_name(void) -{ - return "bfin"; -} -EXPORT_SYMBOL(perf_pmu_name); - -int perf_num_counters(void) -{ - return ARRAY_SIZE(event_map); -} -EXPORT_SYMBOL(perf_num_counters); - -static u64 bfin_pfmon_read(int idx) -{ - return bfin_read32(PFCNTR0 + (idx * 4)); -} - -static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx) -{ - bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK)); -} - -static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx) -{ - u32 val, mask; - - val = PFPWR; - if (idx) { - mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1); - /* The packed config is for event0, so shift it to event1 slots */ - val |= (hwc->config << (PFMON1_P - PFMON0_P)); - val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P); - bfin_write_PFCNTR1(0); - } else { - mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0); - val |= hwc->config; - bfin_write_PFCNTR0(0); - } - - bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val); -} - -static void bfin_pfmon_disable_all(void) -{ - bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR); -} - -static void bfin_pfmon_enable_all(void) -{ - bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR); -} - -struct cpu_hw_events { - struct perf_event *events[MAX_HWEVENTS]; - unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; -}; -DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); - -static int hw_perf_cache_event(int config, int *evp) -{ - unsigned long type, op, result; - int ev; - - /* unpack config */ - type = config & 0xff; - op = (config >> 8) & 0xff; - result = (config >> 16) & 0xff; - - if (type >= PERF_COUNT_HW_CACHE_MAX || - op >= PERF_COUNT_HW_CACHE_OP_MAX || - result >= PERF_COUNT_HW_CACHE_RESULT_MAX) - return -EINVAL; - - ev = cache_events[type][op][result]; - if (ev == 0) - return -EOPNOTSUPP; - if (ev == -1) - return -EINVAL; - *evp = ev; - return 0; -} - -static void bfin_perf_event_update(struct perf_event *event, - struct hw_perf_event *hwc, int idx) -{ - u64 prev_raw_count, new_raw_count; - s64 delta; - int shift = 0; - - /* - * Depending on the counter configuration, they may or may not - * be chained, in which case the previous counter value can be - * updated underneath us if the lower-half overflows. - * - * Our tactic to handle this is to first atomically read and - * exchange a new raw count - then add that new-prev delta - * count to the generic counter atomically. - * - * As there is no interrupt associated with the overflow events, - * this is the simplest approach for maintaining consistency. - */ -again: - prev_raw_count = local64_read(&hwc->prev_count); - new_raw_count = bfin_pfmon_read(idx); - - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count) - goto again; - - /* - * Now we have the new raw value and have updated the prev - * timestamp already. We can now calculate the elapsed delta - * (counter-)time and add that to the generic counter. - * - * Careful, not all hw sign-extends above the physical width - * of the count. - */ - delta = (new_raw_count << shift) - (prev_raw_count << shift); - delta >>= shift; - - local64_add(delta, &event->count); -} - -static void bfin_pmu_stop(struct perf_event *event, int flags) -{ - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - if (!(event->hw.state & PERF_HES_STOPPED)) { - bfin_pfmon_disable(hwc, idx); - cpuc->events[idx] = NULL; - event->hw.state |= PERF_HES_STOPPED; - } - - if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) { - bfin_perf_event_update(event, &event->hw, idx); - event->hw.state |= PERF_HES_UPTODATE; - } -} - -static void bfin_pmu_start(struct perf_event *event, int flags) -{ - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - if (WARN_ON_ONCE(idx == -1)) - return; - - if (flags & PERF_EF_RELOAD) - WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); - - cpuc->events[idx] = event; - event->hw.state = 0; - bfin_pfmon_enable(hwc, idx); -} - -static void bfin_pmu_del(struct perf_event *event, int flags) -{ - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - - bfin_pmu_stop(event, PERF_EF_UPDATE); - __clear_bit(event->hw.idx, cpuc->used_mask); - - perf_event_update_userpage(event); -} - -static int bfin_pmu_add(struct perf_event *event, int flags) -{ - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - int ret = -EAGAIN; - - perf_pmu_disable(event->pmu); - - if (__test_and_set_bit(idx, cpuc->used_mask)) { - idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS); - if (idx == MAX_HWEVENTS) - goto out; - - __set_bit(idx, cpuc->used_mask); - hwc->idx = idx; - } - - bfin_pfmon_disable(hwc, idx); - - event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; - if (flags & PERF_EF_START) - bfin_pmu_start(event, PERF_EF_RELOAD); - - perf_event_update_userpage(event); - ret = 0; -out: - perf_pmu_enable(event->pmu); - return ret; -} - -static void bfin_pmu_read(struct perf_event *event) -{ - bfin_perf_event_update(event, &event->hw, event->hw.idx); -} - -static int bfin_pmu_event_init(struct perf_event *event) -{ - struct perf_event_attr *attr = &event->attr; - struct hw_perf_event *hwc = &event->hw; - int config = -1; - int ret; - - if (attr->exclude_hv || attr->exclude_idle) - return -EPERM; - - ret = 0; - switch (attr->type) { - case PERF_TYPE_RAW: - config = PFMON(0, attr->config & PFMON_MASK) | - PFCNT(0, !(attr->config & 0x100)); - break; - case PERF_TYPE_HW_CACHE: - ret = hw_perf_cache_event(attr->config, &config); - break; - case PERF_TYPE_HARDWARE: - if (attr->config >= ARRAY_SIZE(event_map)) - return -EINVAL; - - config = event_map[attr->config]; - break; - } - - if (config == -1) - return -EINVAL; - - if (!attr->exclude_kernel) - config |= PFCEN(0, PFCEN_ENABLE_SUPV); - if (!attr->exclude_user) - config |= PFCEN(0, PFCEN_ENABLE_USER); - - hwc->config |= config; - - return ret; -} - -static void bfin_pmu_enable(struct pmu *pmu) -{ - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - struct perf_event *event; - struct hw_perf_event *hwc; - int i; - - for (i = 0; i < MAX_HWEVENTS; ++i) { - event = cpuc->events[i]; - if (!event) - continue; - hwc = &event->hw; - bfin_pfmon_enable(hwc, hwc->idx); - } - - bfin_pfmon_enable_all(); -} - -static void bfin_pmu_disable(struct pmu *pmu) -{ - bfin_pfmon_disable_all(); -} - -static struct pmu pmu = { - .pmu_enable = bfin_pmu_enable, - .pmu_disable = bfin_pmu_disable, - .event_init = bfin_pmu_event_init, - .add = bfin_pmu_add, - .del = bfin_pmu_del, - .start = bfin_pmu_start, - .stop = bfin_pmu_stop, - .read = bfin_pmu_read, -}; - -static int bfin_pmu_prepare_cpu(unsigned int cpu) -{ - struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); - - bfin_write_PFCTL(0); - memset(cpuhw, 0, sizeof(struct cpu_hw_events)); - return 0; -} - -static int __init bfin_pmu_init(void) -{ - int ret; - - /* - * All of the on-chip counters are "limited", in that they have - * no interrupts, and are therefore unable to do sampling without - * further work and timer assistance. - */ - pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; - - ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); - if (!ret) - cpuhp_setup_state(CPUHP_PERF_BFIN,"perf/bfin:starting", - bfin_pmu_prepare_cpu, NULL); - return ret; -} -early_initcall(bfin_pmu_init); diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c deleted file mode 100644 index 89814850b08b..000000000000 --- a/arch/blackfin/kernel/process.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - * Blackfin architecture-dependent process handling - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -asmlinkage void ret_from_fork(void); - -/* Points to the SDRAM backup memory for the stack that is currently in - * L1 scratchpad memory. - */ -void *current_l1_stack_save; - -/* The number of tasks currently using a L1 stack area. The SRAM is - * allocated/deallocated whenever this changes from/to zero. - */ -int nr_l1stack_tasks; - -/* Start and length of the area in L1 scratchpad memory which we've allocated - * for process stacks. - */ -void *l1_stack_base; -unsigned long l1_stack_len; - -void (*pm_power_off)(void) = NULL; -EXPORT_SYMBOL(pm_power_off); - -/* - * The idle loop on BFIN - */ -#ifdef CONFIG_IDLE_L1 -void arch_cpu_idle(void)__attribute__((l1_text)); -#endif - -/* - * This is our default idle handler. We need to disable - * interrupts here to ensure we don't miss a wakeup call. - */ -void arch_cpu_idle(void) -{ -#ifdef CONFIG_IPIPE - ipipe_suspend_domain(); -#endif - hard_local_irq_disable(); - if (!need_resched()) - idle_with_irq_disabled(); - - hard_local_irq_enable(); -} - -#ifdef CONFIG_HOTPLUG_CPU -void arch_cpu_idle_dead(void) -{ - cpu_die(); -} -#endif - -/* - * Do necessary setup to start up a newly executed thread. - * - * pass the data segment into user programs if it exists, - * it can't hurt anything as far as I can tell - */ -void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) -{ - regs->pc = new_ip; - if (current->mm) - regs->p5 = current->mm->start_data; -#ifndef CONFIG_SMP - task_thread_info(current)->l1_task_info.stack_start = - (void *)current->mm->context.stack_start; - task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp; - memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, - sizeof(*L1_SCRATCH_TASK_INFO)); -#endif - wrusp(new_sp); -} -EXPORT_SYMBOL_GPL(start_thread); - -void flush_thread(void) -{ -} - -asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp) -{ -#ifdef __ARCH_SYNC_CORE_DCACHE - if (current->nr_cpus_allowed == num_possible_cpus()) - set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id())); -#endif - if (newsp) - newsp -= 12; - return do_fork(clone_flags, newsp, 0, NULL, NULL); -} - -int -copy_thread(unsigned long clone_flags, - unsigned long usp, unsigned long topstk, - struct task_struct *p) -{ - struct pt_regs *childregs; - unsigned long *v; - - childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1; - v = ((unsigned long *)childregs) - 2; - if (unlikely(p->flags & PF_KTHREAD)) { - memset(childregs, 0, sizeof(struct pt_regs)); - v[0] = usp; - v[1] = topstk; - childregs->orig_p0 = -1; - childregs->ipend = 0x8000; - __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):); - p->thread.usp = 0; - } else { - *childregs = *current_pt_regs(); - childregs->r0 = 0; - p->thread.usp = usp ? : rdusp(); - v[0] = v[1] = 0; - } - - p->thread.ksp = (unsigned long)v; - p->thread.pc = (unsigned long)ret_from_fork; - - return 0; -} - -unsigned long get_wchan(struct task_struct *p) -{ - unsigned long fp, pc; - unsigned long stack_page; - int count = 0; - if (!p || p == current || p->state == TASK_RUNNING) - return 0; - - stack_page = (unsigned long)p; - fp = p->thread.usp; - do { - if (fp < stack_page + sizeof(struct thread_info) || - fp >= 8184 + stack_page) - return 0; - pc = ((unsigned long *)fp)[1]; - if (!in_sched_functions(pc)) - return pc; - fp = *(unsigned long *)fp; - } - while (count++ < 16); - return 0; -} - -void finish_atomic_sections (struct pt_regs *regs) -{ - int __user *up0 = (int __user *)regs->p0; - - switch (regs->pc) { - default: - /* not in middle of an atomic step, so resume like normal */ - return; - - case ATOMIC_XCHG32 + 2: - put_user(regs->r1, up0); - break; - - case ATOMIC_CAS32 + 2: - case ATOMIC_CAS32 + 4: - if (regs->r0 == regs->r1) - case ATOMIC_CAS32 + 6: - put_user(regs->r2, up0); - break; - - case ATOMIC_ADD32 + 2: - regs->r0 = regs->r1 + regs->r0; - /* fall through */ - case ATOMIC_ADD32 + 4: - put_user(regs->r0, up0); - break; - - case ATOMIC_SUB32 + 2: - regs->r0 = regs->r1 - regs->r0; - /* fall through */ - case ATOMIC_SUB32 + 4: - put_user(regs->r0, up0); - break; - - case ATOMIC_IOR32 + 2: - regs->r0 = regs->r1 | regs->r0; - /* fall through */ - case ATOMIC_IOR32 + 4: - put_user(regs->r0, up0); - break; - - case ATOMIC_AND32 + 2: - regs->r0 = regs->r1 & regs->r0; - /* fall through */ - case ATOMIC_AND32 + 4: - put_user(regs->r0, up0); - break; - - case ATOMIC_XOR32 + 2: - regs->r0 = regs->r1 ^ regs->r0; - /* fall through */ - case ATOMIC_XOR32 + 4: - put_user(regs->r0, up0); - break; - } - - /* - * We've finished the atomic section, and the only thing left for - * userspace is to do a RTS, so we might as well handle that too - * since we need to update the PC anyways. - */ - regs->pc = regs->rets; -} - -static inline -int in_mem(unsigned long addr, unsigned long size, - unsigned long start, unsigned long end) -{ - return addr >= start && addr + size <= end; -} -static inline -int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off, - unsigned long const_addr, unsigned long const_size) -{ - return const_size && - in_mem(addr, size, const_addr + off, const_addr + const_size); -} -static inline -int in_mem_const(unsigned long addr, unsigned long size, - unsigned long const_addr, unsigned long const_size) -{ - return in_mem_const_off(addr, size, 0, const_addr, const_size); -} -#ifdef CONFIG_BF60x -#define ASYNC_ENABLED(bnum, bctlnum) 1 -#else -#define ASYNC_ENABLED(bnum, bctlnum) \ -({ \ - (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \ - bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \ - 1; \ -}) -#endif -/* - * We can't read EBIU banks that aren't enabled or we end up hanging - * on the access to the async space. Make sure we validate accesses - * that cross async banks too. - * 0 - found, but unusable - * 1 - found & usable - * 2 - not found - */ -static -int in_async(unsigned long addr, unsigned long size) -{ - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) { - if (!ASYNC_ENABLED(0, 0)) - return 0; - if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) - return 1; - size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr; - addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE; - } - if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) { - if (!ASYNC_ENABLED(1, 0)) - return 0; - if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) - return 1; - size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr; - addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE; - } - if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) { - if (!ASYNC_ENABLED(2, 1)) - return 0; - if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) - return 1; - size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr; - addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE; - } - if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - if (ASYNC_ENABLED(3, 1)) - return 0; - if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) - return 1; - return 0; - } - - /* not within async bounds */ - return 2; -} - -int bfin_mem_access_type(unsigned long addr, unsigned long size) -{ - int cpu = raw_smp_processor_id(); - - /* Check that things do not wrap around */ - if (addr > ULONG_MAX - size) - return -EFAULT; - - if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end)) - return BFIN_MEM_ACCESS_CORE; - - if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) - return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; - if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) - return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; - if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) - return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; - if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) - return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; -#ifdef COREB_L1_CODE_START - if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH)) - return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; - if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) - return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; - if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH)) - return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; - if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) - return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; -#endif - if (in_mem_const(addr, size, L2_START, L2_LENGTH)) - return BFIN_MEM_ACCESS_CORE; - - if (addr >= SYSMMR_BASE) - return BFIN_MEM_ACCESS_CORE_ONLY; - - switch (in_async(addr, size)) { - case 0: return -EFAULT; - case 1: return BFIN_MEM_ACCESS_CORE; - case 2: /* fall through */; - } - - if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) - return BFIN_MEM_ACCESS_CORE; - if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) - return BFIN_MEM_ACCESS_DMA; - - return -EFAULT; -} - -#if defined(CONFIG_ACCESS_CHECK) -#ifdef CONFIG_ACCESS_OK_L1 -__attribute__((l1_text)) -#endif -/* Return 1 if access to memory range is OK, 0 otherwise */ -int _access_ok(unsigned long addr, unsigned long size) -{ - int aret; - - if (size == 0) - return 1; - /* Check that things do not wrap around */ - if (addr > ULONG_MAX - size) - return 0; - if (uaccess_kernel()) - return 1; -#ifdef CONFIG_MTD_UCLINUX - if (1) -#else - if (0) -#endif - { - if (in_mem(addr, size, memory_start, memory_end)) - return 1; - if (in_mem(addr, size, memory_mtd_end, physical_mem_end)) - return 1; -# ifndef CONFIG_ROMFS_ON_MTD - if (0) -# endif - /* For XIP, allow user space to use pointers within the ROMFS. */ - if (in_mem(addr, size, memory_mtd_start, memory_mtd_end)) - return 1; - } else { - if (in_mem(addr, size, memory_start, physical_mem_end)) - return 1; - } - - if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end)) - return 1; - - if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) - return 1; - if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH)) - return 1; - if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH)) - return 1; - if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) - return 1; -#ifdef COREB_L1_CODE_START - if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH)) - return 1; - if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) - return 1; - if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH)) - return 1; - if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) - return 1; -#endif - -#ifndef CONFIG_EXCEPTION_L1_SCRATCH - if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len)) - return 1; -#endif - - aret = in_async(addr, size); - if (aret < 2) - return aret; - - if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) - return 1; - - if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) - return 1; - if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) - return 1; - - return 0; -} -EXPORT_SYMBOL(_access_ok); -#endif /* CONFIG_ACCESS_CHECK */ diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c deleted file mode 100644 index db85bc94334e..000000000000 --- a/arch/blackfin/kernel/pseudodbg.c +++ /dev/null @@ -1,191 +0,0 @@ -/* The fake debug assert instructions - * - * Copyright 2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include - -const char * const greg_names[] = { - "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", - "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", - "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", - "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3", - "A0.X", "A0.W", "A1.X", "A1.W", "", "", "ASTAT", "RETS", - "", "", "", "", "", "", "", "", - "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2", - "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT", -}; - -static const char *get_allreg_name(int grp, int reg) -{ - return greg_names[(grp << 3) | reg]; -} - -/* - * Unfortunately, the pt_regs structure is not laid out the same way as the - * hardware register file, so we need to do some fix ups. - * - * CYCLES is not stored in the pt_regs structure - so, we just read it from - * the hardware. - * - * Don't support: - * - All reserved registers - * - All in group 7 are (supervisors only) - */ - -static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg) -{ - long *val = &fp->r0; - unsigned long tmp; - - /* Only do Dregs and Pregs for now */ - if (grp == 5 || - (grp == 4 && (reg == 4 || reg == 5)) || - (grp == 7)) - return false; - - if (grp == 0 || (grp == 1 && reg < 6)) - val -= (reg + 8 * grp); - else if (grp == 1 && reg == 6) - val = &fp->usp; - else if (grp == 1 && reg == 7) - val = &fp->fp; - else if (grp == 2) { - val = &fp->i0; - val -= reg; - } else if (grp == 3 && reg >= 4) { - val = &fp->l0; - val -= (reg - 4); - } else if (grp == 3 && reg < 4) { - val = &fp->b0; - val -= reg; - } else if (grp == 4 && reg < 4) { - val = &fp->a0x; - val -= reg; - } else if (grp == 4 && reg == 6) - val = &fp->astat; - else if (grp == 4 && reg == 7) - val = &fp->rets; - else if (grp == 6 && reg < 6) { - val = &fp->lc0; - val -= reg; - } else if (grp == 6 && reg == 6) { - __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp)); - val = &tmp; - } else if (grp == 6 && reg == 7) { - __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp)); - val = &tmp; - } - - *value = *val; - return true; - -} - -#define PseudoDbg_Assert_opcode 0xf0000000 -#define PseudoDbg_Assert_expected_bits 0 -#define PseudoDbg_Assert_expected_mask 0xffff -#define PseudoDbg_Assert_regtest_bits 16 -#define PseudoDbg_Assert_regtest_mask 0x7 -#define PseudoDbg_Assert_grp_bits 19 -#define PseudoDbg_Assert_grp_mask 0x7 -#define PseudoDbg_Assert_dbgop_bits 22 -#define PseudoDbg_Assert_dbgop_mask 0x3 -#define PseudoDbg_Assert_dontcare_bits 24 -#define PseudoDbg_Assert_dontcare_mask 0x7 -#define PseudoDbg_Assert_code_bits 27 -#define PseudoDbg_Assert_code_mask 0x1f - -/* - * DBGA - debug assert - */ -bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode) -{ - int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask); - int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask); - int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask); - int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask); - long value; - - if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode) - return false; - - if (!fix_up_reg(fp, &value, grp, regtest)) - return false; - - if (dbgop == 0 || dbgop == 2) { - /* DBGA ( regs_lo , uimm16 ) */ - /* DBGAL ( regs , uimm16 ) */ - if (expected != (value & 0xFFFF)) { - pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n", - get_allreg_name(grp, regtest), - expected, (unsigned int)(value & 0xFFFF)); - return false; - } - - } else if (dbgop == 1 || dbgop == 3) { - /* DBGA ( regs_hi , uimm16 ) */ - /* DBGAH ( regs , uimm16 ) */ - if (expected != ((value >> 16) & 0xFFFF)) { - pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n", - get_allreg_name(grp, regtest), - expected, (unsigned int)((value >> 16) & 0xFFFF)); - return false; - } - } - - fp->pc += 4; - return true; -} - -#define PseudoDbg_opcode 0xf8000000 -#define PseudoDbg_reg_bits 0 -#define PseudoDbg_reg_mask 0x7 -#define PseudoDbg_grp_bits 3 -#define PseudoDbg_grp_mask 0x7 -#define PseudoDbg_fn_bits 6 -#define PseudoDbg_fn_mask 0x3 -#define PseudoDbg_code_bits 8 -#define PseudoDbg_code_mask 0xff - -/* - * DBG - debug (dump a register value out) - */ -bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode) -{ - int grp, fn, reg; - long value, value1; - - if ((opcode & 0xFF000000) != PseudoDbg_opcode) - return false; - - opcode >>= 16; - grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask); - fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask); - reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); - - if (fn == 3 && (reg == 0 || reg == 1)) { - if (!fix_up_reg(fp, &value, 4, 2 * reg)) - return false; - if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1)) - return false; - - pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1); - fp->pc += 2; - return true; - - } else if (fn == 0) { - if (!fix_up_reg(fp, &value, grp, reg)) - return false; - - pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value); - fp->pc += 2; - return true; - } - - return false; -} diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c deleted file mode 100644 index a6827095b99a..000000000000 --- a/arch/blackfin/kernel/ptrace.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds - * these modifications are Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * does not yet catch signals sent when the child dies. - * in exit.c or in signal.c. - */ - -/* - * Get contents of register REGNO in task TASK. - */ -static inline long -get_reg(struct task_struct *task, unsigned long regno, - unsigned long __user *datap) -{ - long tmp; - struct pt_regs *regs = task_pt_regs(task); - - if (regno & 3 || regno > PT_LAST_PSEUDO) - return -EIO; - - switch (regno) { - case PT_TEXT_ADDR: - tmp = task->mm->start_code; - break; - case PT_TEXT_END_ADDR: - tmp = task->mm->end_code; - break; - case PT_DATA_ADDR: - tmp = task->mm->start_data; - break; - case PT_USP: - tmp = task->thread.usp; - break; - default: - if (regno < sizeof(*regs)) { - void *reg_ptr = regs; - tmp = *(long *)(reg_ptr + regno); - } else - return -EIO; - } - - return put_user(tmp, datap); -} - -/* - * Write contents of register REGNO in task TASK. - */ -static inline int -put_reg(struct task_struct *task, unsigned long regno, unsigned long data) -{ - struct pt_regs *regs = task_pt_regs(task); - - if (regno & 3 || regno > PT_LAST_PSEUDO) - return -EIO; - - switch (regno) { - case PT_PC: - /*********************************************************************/ - /* At this point the kernel is most likely in exception. */ - /* The RETX register will be used to populate the pc of the process. */ - /*********************************************************************/ - regs->retx = data; - regs->pc = data; - break; - case PT_RETX: - break; /* regs->retx = data; break; */ - case PT_USP: - regs->usp = data; - task->thread.usp = data; - break; - case PT_SYSCFG: /* don't let userspace screw with this */ - if ((data & ~1) != 0x6) - pr_warning("ptrace: ignore syscfg write of %#lx\n", data); - break; /* regs->syscfg = data; break; */ - default: - if (regno < sizeof(*regs)) { - void *reg_offset = regs; - *(long *)(reg_offset + regno) = data; - } - /* Ignore writes to pseudo registers */ - } - - return 0; -} - -/* - * check that an address falls within the bounds of the target process's memory mappings - */ -int -is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len) -{ - bool valid; - struct vm_area_struct *vma; - struct sram_list_struct *sraml; - - /* overflow */ - if (start + len < start) - return -EIO; - - down_read(&child->mm->mmap_sem); - vma = find_vma(child->mm, start); - valid = vma && start >= vma->vm_start && start + len <= vma->vm_end; - up_read(&child->mm->mmap_sem); - if (valid) - return 0; - - for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next) - if (start >= (unsigned long)sraml->addr - && start + len < (unsigned long)sraml->addr + sraml->length) - return 0; - - if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END) - return 0; - -#ifdef CONFIG_APP_STACK_L1 - if (child->mm->context.l1_stack_save) - if (start >= (unsigned long)l1_stack_base && - start + len < (unsigned long)l1_stack_base + l1_stack_len) - return 0; -#endif - - return -EIO; -} - -/* - * retrieve the contents of Blackfin userspace general registers - */ -static int genregs_get(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - void *kbuf, void __user *ubuf) -{ - struct pt_regs *regs = task_pt_regs(target); - int ret; - - /* This sucks ... */ - regs->usp = target->thread.usp; - - ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, - regs, 0, sizeof(*regs)); - if (ret < 0) - return ret; - - return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, - sizeof(*regs), -1); -} - -/* - * update the contents of the Blackfin userspace general registers - */ -static int genregs_set(struct task_struct *target, - const struct user_regset *regset, - unsigned int pos, unsigned int count, - const void *kbuf, const void __user *ubuf) -{ - struct pt_regs *regs = task_pt_regs(target); - int ret; - - /* Don't let people set SYSCFG (it's at the end of pt_regs) */ - ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - regs, 0, PT_SYSCFG); - if (ret < 0) - return ret; - - /* This sucks ... */ - target->thread.usp = regs->usp; - /* regs->retx = regs->pc; */ - - return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, - PT_SYSCFG, -1); -} - -/* - * Define the register sets available on the Blackfin under Linux - */ -enum bfin_regset { - REGSET_GENERAL, -}; - -static const struct user_regset bfin_regsets[] = { - [REGSET_GENERAL] = { - .core_note_type = NT_PRSTATUS, - .n = sizeof(struct pt_regs) / sizeof(long), - .size = sizeof(long), - .align = sizeof(long), - .get = genregs_get, - .set = genregs_set, - }, -}; - -static const struct user_regset_view user_bfin_native_view = { - .name = "Blackfin", - .e_machine = EM_BLACKFIN, - .regsets = bfin_regsets, - .n = ARRAY_SIZE(bfin_regsets), -}; - -const struct user_regset_view *task_user_regset_view(struct task_struct *task) -{ - return &user_bfin_native_view; -} - -void user_enable_single_step(struct task_struct *child) -{ - struct pt_regs *regs = task_pt_regs(child); - regs->syscfg |= SYSCFG_SSSTEP; - - set_tsk_thread_flag(child, TIF_SINGLESTEP); -} - -void user_disable_single_step(struct task_struct *child) -{ - struct pt_regs *regs = task_pt_regs(child); - regs->syscfg &= ~SYSCFG_SSSTEP; - - clear_tsk_thread_flag(child, TIF_SINGLESTEP); -} - -long arch_ptrace(struct task_struct *child, long request, - unsigned long addr, unsigned long data) -{ - int ret; - unsigned long __user *datap = (unsigned long __user *)data; - void *paddr = (void *)addr; - - switch (request) { - /* when I and D space are separate, these will need to be fixed. */ - case PTRACE_PEEKDATA: - pr_debug("ptrace: PEEKDATA\n"); - /* fall through */ - case PTRACE_PEEKTEXT: /* read word at location addr. */ - { - unsigned long tmp = 0; - int copied = 0, to_copy = sizeof(tmp); - - ret = -EIO; - pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %i\n", addr, to_copy); - if (is_user_addr_valid(child, addr, to_copy) < 0) - break; - pr_debug("ptrace: user address is valid\n"); - - switch (bfin_mem_access_type(addr, to_copy)) { - case BFIN_MEM_ACCESS_CORE: - case BFIN_MEM_ACCESS_CORE_ONLY: - copied = ptrace_access_vm(child, addr, &tmp, - to_copy, FOLL_FORCE); - if (copied) - break; - - /* hrm, why didn't that work ... maybe no mapping */ - if (addr >= FIXED_CODE_START && - addr + to_copy <= FIXED_CODE_END) { - copy_from_user_page(0, 0, 0, &tmp, paddr, to_copy); - copied = to_copy; - } else if (addr >= BOOT_ROM_START) { - memcpy(&tmp, paddr, to_copy); - copied = to_copy; - } - - break; - case BFIN_MEM_ACCESS_DMA: - if (safe_dma_memcpy(&tmp, paddr, to_copy)) - copied = to_copy; - break; - case BFIN_MEM_ACCESS_ITEST: - if (isram_memcpy(&tmp, paddr, to_copy)) - copied = to_copy; - break; - default: - copied = 0; - break; - } - - pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp); - if (copied == to_copy) - ret = put_user(tmp, datap); - break; - } - - /* when I and D space are separate, this will have to be fixed. */ - case PTRACE_POKEDATA: - pr_debug("ptrace: PTRACE_PEEKDATA\n"); - /* fall through */ - case PTRACE_POKETEXT: /* write the word at location addr. */ - { - int copied = 0, to_copy = sizeof(data); - - ret = -EIO; - pr_debug("ptrace: POKETEXT at addr 0x%08lx + %i bytes %lx\n", - addr, to_copy, data); - if (is_user_addr_valid(child, addr, to_copy) < 0) - break; - pr_debug("ptrace: user address is valid\n"); - - switch (bfin_mem_access_type(addr, to_copy)) { - case BFIN_MEM_ACCESS_CORE: - case BFIN_MEM_ACCESS_CORE_ONLY: - copied = ptrace_access_vm(child, addr, &data, - to_copy, - FOLL_FORCE | FOLL_WRITE); - break; - case BFIN_MEM_ACCESS_DMA: - if (safe_dma_memcpy(paddr, &data, to_copy)) - copied = to_copy; - break; - case BFIN_MEM_ACCESS_ITEST: - if (isram_memcpy(paddr, &data, to_copy)) - copied = to_copy; - break; - default: - copied = 0; - break; - } - - pr_debug("ptrace: copied size %d\n", copied); - if (copied == to_copy) - ret = 0; - break; - } - - case PTRACE_PEEKUSR: - switch (addr) { -#ifdef CONFIG_BINFMT_ELF_FDPIC /* backwards compat */ - case PT_FDPIC_EXEC: - request = PTRACE_GETFDPIC; - addr = PTRACE_GETFDPIC_EXEC; - goto case_default; - case PT_FDPIC_INTERP: - request = PTRACE_GETFDPIC; - addr = PTRACE_GETFDPIC_INTERP; - goto case_default; -#endif - default: - ret = get_reg(child, addr, datap); - } - pr_debug("ptrace: PEEKUSR reg %li with %#lx = %i\n", addr, data, ret); - break; - - case PTRACE_POKEUSR: - ret = put_reg(child, addr, data); - pr_debug("ptrace: POKEUSR reg %li with %li = %i\n", addr, data, ret); - break; - - case PTRACE_GETREGS: - pr_debug("ptrace: PTRACE_GETREGS\n"); - return copy_regset_to_user(child, &user_bfin_native_view, - REGSET_GENERAL, - 0, sizeof(struct pt_regs), - datap); - - case PTRACE_SETREGS: - pr_debug("ptrace: PTRACE_SETREGS\n"); - return copy_regset_from_user(child, &user_bfin_native_view, - REGSET_GENERAL, - 0, sizeof(struct pt_regs), - datap); - - case_default: - default: - ret = ptrace_request(child, request, addr, data); - break; - } - - return ret; -} - -asmlinkage int syscall_trace_enter(struct pt_regs *regs) -{ - int ret = 0; - - if (test_thread_flag(TIF_SYSCALL_TRACE)) - ret = tracehook_report_syscall_entry(regs); - - return ret; -} - -asmlinkage void syscall_trace_leave(struct pt_regs *regs) -{ - int step; - - step = test_thread_flag(TIF_SINGLESTEP); - if (step || test_thread_flag(TIF_SYSCALL_TRACE)) - tracehook_report_syscall_exit(regs, step); -} diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c deleted file mode 100644 index c4f50a328501..000000000000 --- a/arch/blackfin/kernel/reboot.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * arch/blackfin/kernel/reboot.c - handle shutdown/reboot - * - * Copyright 2004-2007 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -/* A system soft reset makes external memory unusable so force - * this function into L1. We use the compiler ssync here rather - * than SSYNC() because it's safe (no interrupts and such) and - * we save some L1. We do not need to force sanity in the SYSCR - * register as the BMODE selection bit is cleared by the soft - * reset while the Core B bit (on dual core parts) is cleared by - * the core reset. - */ -__attribute__ ((__l1_text__, __noreturn__)) -static void bfin_reset(void) -{ -#ifndef CONFIG_BF60x - if (!ANOMALY_05000353 && !ANOMALY_05000386) - bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20)); - - /* Wait for completion of "system" events such as cache line - * line fills so that we avoid infinite stalls later on as - * much as possible. This code is in L1, so it won't trigger - * any such event after this point in time. - */ - __builtin_bfin_ssync(); - - /* Initiate System software reset. */ - bfin_write_SWRST(0x7); - - /* Due to the way reset is handled in the hardware, we need - * to delay for 10 SCLKS. The only reliable way to do this is - * to calculate the CCLK/SCLK ratio and multiply 10. For now, - * we'll assume worse case which is a 1:15 ratio. - */ - asm( - "LSETUP (1f, 1f) LC0 = %0\n" - "1: nop;" - : - : "a" (15 * 10) - : "LC0", "LB0", "LT0" - ); - - /* Clear System software reset */ - bfin_write_SWRST(0); - - /* The BF526 ROM will crash during reset */ -#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) - /* Seems to be fixed with newer parts though ... */ - if (__SILICON_REVISION__ < 1 && bfin_revid() < 1) - bfin_read_SWRST(); -#endif - /* Wait for the SWRST write to complete. Cannot rely on SSYNC - * though as the System state is all reset now. - */ - asm( - "LSETUP (1f, 1f) LC1 = %0\n" - "1: nop;" - : - : "a" (15 * 1) - : "LC1", "LB1", "LT1" - ); - - while (1) - /* Issue core reset */ - asm("raise 1"); -#else - while (1) - bfin_write_RCU0_CTL(0x1); -#endif -} - -__attribute__((weak)) -void native_machine_restart(char *cmd) -{ -} - -void machine_restart(char *cmd) -{ - native_machine_restart(cmd); - if (smp_processor_id()) - smp_call_function((void *)bfin_reset, 0, 1); - else - bfin_reset(); -} - -__attribute__((weak)) -void native_machine_halt(void) -{ - idle_with_irq_disabled(); -} - -void machine_halt(void) -{ - native_machine_halt(); -} - -__attribute__((weak)) -void native_machine_power_off(void) -{ - idle_with_irq_disabled(); -} - -void machine_power_off(void) -{ - native_machine_power_off(); -} diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c deleted file mode 100644 index ad82468bd94d..000000000000 --- a/arch/blackfin/kernel/setup.c +++ /dev/null @@ -1,1468 +0,0 @@ -/* - * Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MTD_UCLINUX -#include -#include -#include -#include -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_BF60x -#include -#endif -#ifdef CONFIG_SCB_PRIORITY -#include -#endif - -u16 _bfin_swrst; -EXPORT_SYMBOL(_bfin_swrst); - -unsigned long memory_start, memory_end, physical_mem_end; -unsigned long _rambase, _ramstart, _ramend; -unsigned long reserved_mem_dcache_on; -unsigned long reserved_mem_icache_on; -EXPORT_SYMBOL(memory_start); -EXPORT_SYMBOL(memory_end); -EXPORT_SYMBOL(physical_mem_end); -EXPORT_SYMBOL(_ramend); -EXPORT_SYMBOL(reserved_mem_dcache_on); - -#ifdef CONFIG_MTD_UCLINUX -extern struct map_info uclinux_ram_map; -unsigned long memory_mtd_end, memory_mtd_start, mtd_size; -EXPORT_SYMBOL(memory_mtd_end); -EXPORT_SYMBOL(memory_mtd_start); -EXPORT_SYMBOL(mtd_size); -#endif - -char __initdata command_line[COMMAND_LINE_SIZE]; -struct blackfin_initial_pda __initdata initial_pda; - -/* boot memmap, for parsing "memmap=" */ -#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ -#define BFIN_MEMMAP_RAM 1 -#define BFIN_MEMMAP_RESERVED 2 -static struct bfin_memmap { - int nr_map; - struct bfin_memmap_entry { - unsigned long long addr; /* start of memory segment */ - unsigned long long size; - unsigned long type; - } map[BFIN_MEMMAP_MAX]; -} bfin_memmap __initdata; - -/* for memmap sanitization */ -struct change_member { - struct bfin_memmap_entry *pentry; /* pointer to original entry */ - unsigned long long addr; /* address for this change point */ -}; -static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata; -static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata; -static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; -static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; - -DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); - -static int early_init_clkin_hz(char *buf); - -#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) -void __init generate_cplb_tables(void) -{ - unsigned int cpu; - - generate_cplb_tables_all(); - /* Generate per-CPU I&D CPLB tables */ - for (cpu = 0; cpu < num_possible_cpus(); ++cpu) - generate_cplb_tables_cpu(cpu); -} -#endif - -void bfin_setup_caches(unsigned int cpu) -{ -#ifdef CONFIG_BFIN_ICACHE - bfin_icache_init(icplb_tbl[cpu]); -#endif - -#ifdef CONFIG_BFIN_DCACHE - bfin_dcache_init(dcplb_tbl[cpu]); -#endif - - bfin_setup_cpudata(cpu); - - /* - * In cache coherence emulation mode, we need to have the - * D-cache enabled before running any atomic operation which - * might involve cache invalidation (i.e. spinlock, rwlock). - * So printk's are deferred until then. - */ -#ifdef CONFIG_BFIN_ICACHE - printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); - printk(KERN_INFO " External memory:" -# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE - " cacheable" -# else - " uncacheable" -# endif - " in instruction cache\n"); - if (L2_LENGTH) - printk(KERN_INFO " L2 SRAM :" -# ifdef CONFIG_BFIN_L2_ICACHEABLE - " cacheable" -# else - " uncacheable" -# endif - " in instruction cache\n"); - -#else - printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); -#endif - -#ifdef CONFIG_BFIN_DCACHE - printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); - printk(KERN_INFO " External memory:" -# if defined CONFIG_BFIN_EXTMEM_WRITEBACK - " cacheable (write-back)" -# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH - " cacheable (write-through)" -# else - " uncacheable" -# endif - " in data cache\n"); - if (L2_LENGTH) - printk(KERN_INFO " L2 SRAM :" -# if defined CONFIG_BFIN_L2_WRITEBACK - " cacheable (write-back)" -# elif defined CONFIG_BFIN_L2_WRITETHROUGH - " cacheable (write-through)" -# else - " uncacheable" -# endif - " in data cache\n"); -#else - printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); -#endif -} - -void bfin_setup_cpudata(unsigned int cpu) -{ - struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); - - cpudata->imemctl = bfin_read_IMEM_CONTROL(); - cpudata->dmemctl = bfin_read_DMEM_CONTROL(); -} - -void __init bfin_cache_init(void) -{ -#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) - generate_cplb_tables(); -#endif - bfin_setup_caches(0); -} - -void __init bfin_relocate_l1_mem(void) -{ - unsigned long text_l1_len = (unsigned long)_text_l1_len; - unsigned long data_l1_len = (unsigned long)_data_l1_len; - unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; - unsigned long l2_len = (unsigned long)_l2_len; - - early_shadow_stamp(); - - /* - * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S - * we know that everything about l1 text/data is nice and aligned, - * so copy by 4 byte chunks, and don't worry about overlapping - * src/dest. - * - * We can't use the dma_memcpy functions, since they can call - * scheduler functions which might be in L1 :( and core writes - * into L1 instruction cause bad access errors, so we are stuck, - * we are required to use DMA, but can't use the common dma - * functions. We can't use memcpy either - since that might be - * going to be in the relocated L1 - */ - - blackfin_dma_early_init(); - - /* if necessary, copy L1 text to L1 instruction SRAM */ - if (L1_CODE_LENGTH && text_l1_len) - early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len); - - /* if necessary, copy L1 data to L1 data bank A SRAM */ - if (L1_DATA_A_LENGTH && data_l1_len) - early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len); - - /* if necessary, copy L1 data B to L1 data bank B SRAM */ - if (L1_DATA_B_LENGTH && data_b_l1_len) - early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len); - - early_dma_memcpy_done(); - -#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1) - blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1; -#endif - - /* if necessary, copy L2 text/data to L2 SRAM */ - if (L2_LENGTH && l2_len) - memcpy(_stext_l2, _l2_lma, l2_len); -} - -#ifdef CONFIG_SMP -void __init bfin_relocate_coreb_l1_mem(void) -{ - unsigned long text_l1_len = (unsigned long)_text_l1_len; - unsigned long data_l1_len = (unsigned long)_data_l1_len; - unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; - - blackfin_dma_early_init(); - - /* if necessary, copy L1 text to L1 instruction SRAM */ - if (L1_CODE_LENGTH && text_l1_len) - early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma, - text_l1_len); - - /* if necessary, copy L1 data to L1 data bank A SRAM */ - if (L1_DATA_A_LENGTH && data_l1_len) - early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma, - data_l1_len); - - /* if necessary, copy L1 data B to L1 data bank B SRAM */ - if (L1_DATA_B_LENGTH && data_b_l1_len) - early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma, - data_b_l1_len); - - early_dma_memcpy_done(); - -#ifdef CONFIG_ICACHE_FLUSH_L1 - blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 - - (unsigned long)_stext_l1 + COREB_L1_CODE_START; -#endif -} -#endif - -#ifdef CONFIG_ROMKERNEL -void __init bfin_relocate_xip_data(void) -{ - early_shadow_stamp(); - - memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info)); - memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len); -} -#endif - -/* add_memory_region to memmap */ -static void __init add_memory_region(unsigned long long start, - unsigned long long size, int type) -{ - int i; - - i = bfin_memmap.nr_map; - - if (i == BFIN_MEMMAP_MAX) { - printk(KERN_ERR "Ooops! Too many entries in the memory map!\n"); - return; - } - - bfin_memmap.map[i].addr = start; - bfin_memmap.map[i].size = size; - bfin_memmap.map[i].type = type; - bfin_memmap.nr_map++; -} - -/* - * Sanitize the boot memmap, removing overlaps. - */ -static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) -{ - struct change_member *change_tmp; - unsigned long current_type, last_type; - unsigned long long last_addr; - int chgidx, still_changing; - int overlap_entries; - int new_entry; - int old_nr, new_nr, chg_nr; - int i; - - /* - Visually we're performing the following (1,2,3,4 = memory types) - - Sample memory map (w/overlaps): - ____22__________________ - ______________________4_ - ____1111________________ - _44_____________________ - 11111111________________ - ____________________33__ - ___________44___________ - __________33333_________ - ______________22________ - ___________________2222_ - _________111111111______ - _____________________11_ - _________________4______ - - Sanitized equivalent (no overlap): - 1_______________________ - _44_____________________ - ___1____________________ - ____22__________________ - ______11________________ - _________1______________ - __________3_____________ - ___________44___________ - _____________33_________ - _______________2________ - ________________1_______ - _________________4______ - ___________________2____ - ____________________33__ - ______________________4_ - */ - /* if there's only one memory region, don't bother */ - if (*pnr_map < 2) - return -1; - - old_nr = *pnr_map; - - /* bail out if we find any unreasonable addresses in memmap */ - for (i = 0; i < old_nr; i++) - if (map[i].addr + map[i].size < map[i].addr) - return -1; - - /* create pointers for initial change-point information (for sorting) */ - for (i = 0; i < 2*old_nr; i++) - change_point[i] = &change_point_list[i]; - - /* record all known change-points (starting and ending addresses), - omitting those that are for empty memory regions */ - chgidx = 0; - for (i = 0; i < old_nr; i++) { - if (map[i].size != 0) { - change_point[chgidx]->addr = map[i].addr; - change_point[chgidx++]->pentry = &map[i]; - change_point[chgidx]->addr = map[i].addr + map[i].size; - change_point[chgidx++]->pentry = &map[i]; - } - } - chg_nr = chgidx; /* true number of change-points */ - - /* sort change-point list by memory addresses (low -> high) */ - still_changing = 1; - while (still_changing) { - still_changing = 0; - for (i = 1; i < chg_nr; i++) { - /* if > , swap */ - /* or, if current= & last=, swap */ - if ((change_point[i]->addr < change_point[i-1]->addr) || - ((change_point[i]->addr == change_point[i-1]->addr) && - (change_point[i]->addr == change_point[i]->pentry->addr) && - (change_point[i-1]->addr != change_point[i-1]->pentry->addr)) - ) { - change_tmp = change_point[i]; - change_point[i] = change_point[i-1]; - change_point[i-1] = change_tmp; - still_changing = 1; - } - } - } - - /* create a new memmap, removing overlaps */ - overlap_entries = 0; /* number of entries in the overlap table */ - new_entry = 0; /* index for creating new memmap entries */ - last_type = 0; /* start with undefined memory type */ - last_addr = 0; /* start with 0 as last starting address */ - /* loop through change-points, determining affect on the new memmap */ - for (chgidx = 0; chgidx < chg_nr; chgidx++) { - /* keep track of all overlapping memmap entries */ - if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) { - /* add map entry to overlap list (> 1 entry implies an overlap) */ - overlap_list[overlap_entries++] = change_point[chgidx]->pentry; - } else { - /* remove entry from list (order independent, so swap with last) */ - for (i = 0; i < overlap_entries; i++) { - if (overlap_list[i] == change_point[chgidx]->pentry) - overlap_list[i] = overlap_list[overlap_entries-1]; - } - overlap_entries--; - } - /* if there are overlapping entries, decide which "type" to use */ - /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */ - current_type = 0; - for (i = 0; i < overlap_entries; i++) - if (overlap_list[i]->type > current_type) - current_type = overlap_list[i]->type; - /* continue building up new memmap based on this information */ - if (current_type != last_type) { - if (last_type != 0) { - new_map[new_entry].size = - change_point[chgidx]->addr - last_addr; - /* move forward only if the new size was non-zero */ - if (new_map[new_entry].size != 0) - if (++new_entry >= BFIN_MEMMAP_MAX) - break; /* no more space left for new entries */ - } - if (current_type != 0) { - new_map[new_entry].addr = change_point[chgidx]->addr; - new_map[new_entry].type = current_type; - last_addr = change_point[chgidx]->addr; - } - last_type = current_type; - } - } - new_nr = new_entry; /* retain count for new entries */ - - /* copy new mapping into original location */ - memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); - *pnr_map = new_nr; - - return 0; -} - -static void __init print_memory_map(char *who) -{ - int i; - - for (i = 0; i < bfin_memmap.nr_map; i++) { - printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who, - bfin_memmap.map[i].addr, - bfin_memmap.map[i].addr + bfin_memmap.map[i].size); - switch (bfin_memmap.map[i].type) { - case BFIN_MEMMAP_RAM: - printk(KERN_CONT "(usable)\n"); - break; - case BFIN_MEMMAP_RESERVED: - printk(KERN_CONT "(reserved)\n"); - break; - default: - printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type); - break; - } - } -} - -static __init int parse_memmap(char *arg) -{ - unsigned long long start_at, mem_size; - - if (!arg) - return -EINVAL; - - mem_size = memparse(arg, &arg); - if (*arg == '@') { - start_at = memparse(arg+1, &arg); - add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM); - } else if (*arg == '$') { - start_at = memparse(arg+1, &arg); - add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED); - } - - return 0; -} - -/* - * Initial parsing of the command line. Currently, we support: - * - Controlling the linux memory size: mem=xxx[KMG] - * - Controlling the physical memory size: max_mem=xxx[KMG][$][#] - * $ -> reserved memory is dcacheable - * # -> reserved memory is icacheable - * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region - * @ from to +, type RAM - * $ from to +, type RESERVED - */ -static __init void parse_cmdline_early(char *cmdline_p) -{ - char c = ' ', *to = cmdline_p; - unsigned int memsize; - for (;;) { - if (c == ' ') { - if (!memcmp(to, "mem=", 4)) { - to += 4; - memsize = memparse(to, &to); - if (memsize) - _ramend = memsize; - - } else if (!memcmp(to, "max_mem=", 8)) { - to += 8; - memsize = memparse(to, &to); - if (memsize) { - physical_mem_end = memsize; - if (*to != ' ') { - if (*to == '$' - || *(to + 1) == '$') - reserved_mem_dcache_on = 1; - if (*to == '#' - || *(to + 1) == '#') - reserved_mem_icache_on = 1; - } - } - } else if (!memcmp(to, "clkin_hz=", 9)) { - to += 9; - early_init_clkin_hz(to); -#ifdef CONFIG_EARLY_PRINTK - } else if (!memcmp(to, "earlyprintk=", 12)) { - to += 12; - setup_early_printk(to); -#endif - } else if (!memcmp(to, "memmap=", 7)) { - to += 7; - parse_memmap(to); - } - } - c = *(to++); - if (!c) - break; - } -} - -/* - * Setup memory defaults from user config. - * The physical memory layout looks like: - * - * [_rambase, _ramstart]: kernel image - * [memory_start, memory_end]: dynamic memory managed by kernel - * [memory_end, _ramend]: reserved memory - * [memory_mtd_start(memory_end), - * memory_mtd_start + mtd_size]: rootfs (if any) - * [_ramend - DMA_UNCACHED_REGION, - * _ramend]: uncached DMA region - * [_ramend, physical_mem_end]: memory not managed by kernel - */ -static __init void memory_setup(void) -{ -#ifdef CONFIG_MTD_UCLINUX - unsigned long mtd_phys = 0; -#endif - unsigned long max_mem; - - _rambase = CONFIG_BOOT_LOAD; - _ramstart = (unsigned long)_end; - - if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) { - console_init(); - panic("DMA region exceeds memory limit: %lu.", - _ramend - _ramstart); - } - max_mem = memory_end = _ramend - DMA_UNCACHED_REGION; - -#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) - /* Due to a Hardware Anomaly we need to limit the size of usable - * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on - * 05000263 - Hardware loop corrupted when taking an ICPLB exception - */ -# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO)) - if (max_mem >= 56 * 1024 * 1024) - max_mem = 56 * 1024 * 1024; -# else - if (max_mem >= 60 * 1024 * 1024) - max_mem = 60 * 1024 * 1024; -# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */ -#endif /* ANOMALY_05000263 */ - - -#ifdef CONFIG_MPU - /* Round up to multiple of 4MB */ - memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; -#else - memory_start = PAGE_ALIGN(_ramstart); -#endif - -#if defined(CONFIG_MTD_UCLINUX) - /* generic memory mapped MTD driver */ - memory_mtd_end = memory_end; - - mtd_phys = _ramstart; - mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8))); - -# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS) - if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC) - mtd_size = - PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10); -# endif - -# if defined(CONFIG_CRAMFS) - if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC) - mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4))); -# endif - -# if defined(CONFIG_ROMFS_FS) - if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0 - && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) { - mtd_size = - PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); - - /* ROM_FS is XIP, so if we found it, we need to limit memory */ - if (memory_end > max_mem) { - pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", - (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); - memory_end = max_mem; - } - } -# endif /* CONFIG_ROMFS_FS */ - - /* Since the default MTD_UCLINUX has no magic number, we just blindly - * read 8 past the end of the kernel's image, and look at it. - * When no image is attached, mtd_size is set to a random number - * Do some basic sanity checks before operating on things - */ - if (mtd_size == 0 || memory_end <= mtd_size) { - pr_emerg("Could not find valid ram mtd attached.\n"); - } else { - memory_end -= mtd_size; - - /* Relocate MTD image to the top of memory after the uncached memory area */ - uclinux_ram_map.phys = memory_mtd_start = memory_end; - uclinux_ram_map.size = mtd_size; - pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n", - _end, mtd_size, (void *)memory_mtd_start); - dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); - } -#endif /* CONFIG_MTD_UCLINUX */ - - /* We need lo limit memory, since everything could have a text section - * of userspace in it, and expose anomaly 05000263. If the anomaly - * doesn't exist, or we don't need to - then dont. - */ - if (memory_end > max_mem) { - pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", - (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); - memory_end = max_mem; - } - -#ifdef CONFIG_MPU -#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM) - page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE - - ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32; -#else - page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32; -#endif - page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); -#endif - - init_mm.start_code = (unsigned long)_stext; - init_mm.end_code = (unsigned long)_etext; - init_mm.end_data = (unsigned long)_edata; - init_mm.brk = (unsigned long)0; - - printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); - printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20); - - printk(KERN_INFO "Memory map:\n" - " fixedcode = 0x%p-0x%p\n" - " text = 0x%p-0x%p\n" - " rodata = 0x%p-0x%p\n" - " bss = 0x%p-0x%p\n" - " data = 0x%p-0x%p\n" - " stack = 0x%p-0x%p\n" - " init = 0x%p-0x%p\n" - " available = 0x%p-0x%p\n" -#ifdef CONFIG_MTD_UCLINUX - " rootfs = 0x%p-0x%p\n" -#endif -#if DMA_UNCACHED_REGION > 0 - " DMA Zone = 0x%p-0x%p\n" -#endif - , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END, - _stext, _etext, - __start_rodata, __end_rodata, - __bss_start, __bss_stop, - _sdata, _edata, - (void *)&init_thread_union, - (void *)((int)(&init_thread_union) + THREAD_SIZE), - __init_begin, __init_end, - (void *)_ramstart, (void *)memory_end -#ifdef CONFIG_MTD_UCLINUX - , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size) -#endif -#if DMA_UNCACHED_REGION > 0 - , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend) -#endif - ); -} - -/* - * Find the lowest, highest page frame number we have available - */ -void __init find_min_max_pfn(void) -{ - int i; - - max_pfn = 0; - min_low_pfn = PFN_DOWN(memory_end); - - for (i = 0; i < bfin_memmap.nr_map; i++) { - unsigned long start, end; - /* RAM? */ - if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) - continue; - start = PFN_UP(bfin_memmap.map[i].addr); - end = PFN_DOWN(bfin_memmap.map[i].addr + - bfin_memmap.map[i].size); - if (start >= end) - continue; - if (end > max_pfn) - max_pfn = end; - if (start < min_low_pfn) - min_low_pfn = start; - } -} - -static __init void setup_bootmem_allocator(void) -{ - int bootmap_size; - int i; - unsigned long start_pfn, end_pfn; - unsigned long curr_pfn, last_pfn, size; - - /* mark memory between memory_start and memory_end usable */ - add_memory_region(memory_start, - memory_end - memory_start, BFIN_MEMMAP_RAM); - /* sanity check for overlap */ - sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map); - print_memory_map("boot memmap"); - - /* initialize globals in linux/bootmem.h */ - find_min_max_pfn(); - /* pfn of the last usable page frame */ - if (max_pfn > memory_end >> PAGE_SHIFT) - max_pfn = memory_end >> PAGE_SHIFT; - /* pfn of last page frame directly mapped by kernel */ - max_low_pfn = max_pfn; - /* pfn of the first usable page frame after kernel image*/ - if (min_low_pfn < memory_start >> PAGE_SHIFT) - min_low_pfn = memory_start >> PAGE_SHIFT; - start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT; - end_pfn = memory_end >> PAGE_SHIFT; - - /* - * give all the memory to the bootmap allocator, tell it to put the - * boot mem_map at the start of memory. - */ - bootmap_size = init_bootmem_node(NODE_DATA(0), - memory_start >> PAGE_SHIFT, /* map goes here */ - start_pfn, end_pfn); - - /* register the memmap regions with the bootmem allocator */ - for (i = 0; i < bfin_memmap.nr_map; i++) { - /* - * Reserve usable memory - */ - if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM) - continue; - /* - * We are rounding up the start address of usable memory: - */ - curr_pfn = PFN_UP(bfin_memmap.map[i].addr); - if (curr_pfn >= end_pfn) - continue; - /* - * ... and at the end of the usable range downwards: - */ - last_pfn = PFN_DOWN(bfin_memmap.map[i].addr + - bfin_memmap.map[i].size); - - if (last_pfn > end_pfn) - last_pfn = end_pfn; - - /* - * .. finally, did all the rounding and playing - * around just make the area go away? - */ - if (last_pfn <= curr_pfn) - continue; - - size = last_pfn - curr_pfn; - free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); - } - - /* reserve memory before memory_start, including bootmap */ - reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS, - memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS, - BOOTMEM_DEFAULT); -} - -#define EBSZ_TO_MEG(ebsz) \ -({ \ - int meg = 0; \ - switch (ebsz & 0xf) { \ - case 0x1: meg = 16; break; \ - case 0x3: meg = 32; break; \ - case 0x5: meg = 64; break; \ - case 0x7: meg = 128; break; \ - case 0x9: meg = 256; break; \ - case 0xb: meg = 512; break; \ - } \ - meg; \ -}) -static inline int __init get_mem_size(void) -{ -#if defined(EBIU_SDBCTL) -# if defined(BF561_FAMILY) - int ret = 0; - u32 sdbctl = bfin_read_EBIU_SDBCTL(); - ret += EBSZ_TO_MEG(sdbctl >> 0); - ret += EBSZ_TO_MEG(sdbctl >> 8); - ret += EBSZ_TO_MEG(sdbctl >> 16); - ret += EBSZ_TO_MEG(sdbctl >> 24); - return ret; -# else - return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL()); -# endif -#elif defined(EBIU_DDRCTL1) - u32 ddrctl = bfin_read_EBIU_DDRCTL1(); - int ret = 0; - switch (ddrctl & 0xc0000) { - case DEVSZ_64: - ret = 64 / 8; - break; - case DEVSZ_128: - ret = 128 / 8; - break; - case DEVSZ_256: - ret = 256 / 8; - break; - case DEVSZ_512: - ret = 512 / 8; - break; - } - switch (ddrctl & 0x30000) { - case DEVWD_4: - ret *= 2; - case DEVWD_8: - ret *= 2; - case DEVWD_16: - break; - } - if ((ddrctl & 0xc000) == 0x4000) - ret *= 2; - return ret; -#elif defined(CONFIG_BF60x) - u32 ddrctl = bfin_read_DMC0_CFG(); - int ret; - switch (ddrctl & 0xf00) { - case DEVSZ_64: - ret = 64 / 8; - break; - case DEVSZ_128: - ret = 128 / 8; - break; - case DEVSZ_256: - ret = 256 / 8; - break; - case DEVSZ_512: - ret = 512 / 8; - break; - case DEVSZ_1G: - ret = 1024 / 8; - break; - case DEVSZ_2G: - ret = 2048 / 8; - break; - } - return ret; -#endif - BUG(); -} - -__attribute__((weak)) -void __init native_machine_early_platform_add_devices(void) -{ -} - -#ifdef CONFIG_BF60x -static inline u_long bfin_get_clk(char *name) -{ - struct clk *clk; - u_long clk_rate; - - clk = clk_get(NULL, name); - if (IS_ERR(clk)) - return 0; - - clk_rate = clk_get_rate(clk); - clk_put(clk); - return clk_rate; -} -#endif - -void __init setup_arch(char **cmdline_p) -{ - u32 mmr; - unsigned long sclk, cclk; - - native_machine_early_platform_add_devices(); - - enable_shadow_console(); - - /* Check to make sure we are running on the right processor */ - mmr = bfin_cpuid(); - if (unlikely(CPUID != bfin_cpuid())) - printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", - CPU, bfin_cpuid(), bfin_revid()); - -#ifdef CONFIG_DUMMY_CONSOLE - conswitchp = &dummy_con; -#endif - -#if defined(CONFIG_CMDLINE_BOOL) - strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line)); - command_line[sizeof(command_line) - 1] = 0; -#endif - - /* Keep a copy of command line */ - *cmdline_p = &command_line[0]; - memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); - boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; - - memset(&bfin_memmap, 0, sizeof(bfin_memmap)); - -#ifdef CONFIG_BF60x - /* Should init clock device before parse command early */ - clk_init(); -#endif - /* If the user does not specify things on the command line, use - * what the bootloader set things up as - */ - physical_mem_end = 0; - parse_cmdline_early(&command_line[0]); - - if (_ramend == 0) - _ramend = get_mem_size() * 1024 * 1024; - - if (physical_mem_end == 0) - physical_mem_end = _ramend; - - memory_setup(); - -#ifndef CONFIG_BF60x - /* Initialize Async memory banks */ - bfin_write_EBIU_AMBCTL0(AMBCTL0VAL); - bfin_write_EBIU_AMBCTL1(AMBCTL1VAL); - bfin_write_EBIU_AMGCTL(AMGCTLVAL); -#ifdef CONFIG_EBIU_MBSCTLVAL - bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL); - bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); - bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); -#endif -#endif -#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL - bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15); - bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15); - bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15); - bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() & - ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO); -#endif - - cclk = get_cclk(); - sclk = get_sclk(); - - if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk) - panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK"); - -#ifdef BF561_FAMILY - if (ANOMALY_05000266) { - bfin_read_IMDMA_D0_IRQ_STATUS(); - bfin_read_IMDMA_D1_IRQ_STATUS(); - } -#endif - - mmr = bfin_read_TBUFCTL(); - printk(KERN_INFO "Hardware Trace %s and %sabled\n", - (mmr & 0x1) ? "active" : "off", - (mmr & 0x2) ? "en" : "dis"); -#ifndef CONFIG_BF60x - mmr = bfin_read_SYSCR(); - printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF); - - /* Newer parts mirror SWRST bits in SYSCR */ -#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \ - defined(CONFIG_BF538) || defined(CONFIG_BF539) - _bfin_swrst = bfin_read_SWRST(); -#else - /* Clear boot mode field */ - _bfin_swrst = mmr & ~0xf; -#endif - -#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT - bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT); -#endif -#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET - bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); -#endif - -#ifdef CONFIG_SMP - if (_bfin_swrst & SWRST_DBL_FAULT_A) { -#else - if (_bfin_swrst & RESET_DOUBLE) { -#endif - printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* We assume the crashing kernel, and the current symbol table match */ - printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n", - initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE, - initial_pda.retx_doublefault); - printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", - initial_pda.dcplb_doublefault_addr); - printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", - initial_pda.icplb_doublefault_addr); -#endif - printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", - initial_pda.retx); - } else if (_bfin_swrst & RESET_WDOG) - printk(KERN_INFO "Recovering from Watchdog event\n"); - else if (_bfin_swrst & RESET_SOFTWARE) - printk(KERN_NOTICE "Reset caused by Software reset\n"); -#endif - printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n"); - if (bfin_compiled_revid() == 0xffff) - printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); - else if (bfin_compiled_revid() == -1) - printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); - else - printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); - - if (likely(CPUID == bfin_cpuid())) { - if (bfin_revid() != bfin_compiled_revid()) { - if (bfin_compiled_revid() == -1) - printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", - bfin_revid()); - else if (bfin_compiled_revid() != 0xffff) { - printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", - bfin_compiled_revid(), bfin_revid()); - if (bfin_compiled_revid() > bfin_revid()) - panic("Error: you are missing anomaly workarounds for this rev"); - } - } - if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) - printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", - CPU, bfin_revid()); - } - - printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); - -#ifdef CONFIG_BF60x - printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n", - cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000); -#else - printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", - cclk / 1000000, sclk / 1000000); -#endif - - setup_bootmem_allocator(); - - paging_init(); - - /* Copy atomic sequences to their fixed location, and sanity check that - these locations are the ones that we advertise to userspace. */ - memcpy((void *)FIXED_CODE_START, &fixed_code_start, - FIXED_CODE_END - FIXED_CODE_START); - BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start - != SIGRETURN_STUB - FIXED_CODE_START); - BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start - != ATOMIC_XCHG32 - FIXED_CODE_START); - BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start - != ATOMIC_CAS32 - FIXED_CODE_START); - BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start - != ATOMIC_ADD32 - FIXED_CODE_START); - BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start - != ATOMIC_SUB32 - FIXED_CODE_START); - BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start - != ATOMIC_IOR32 - FIXED_CODE_START); - BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start - != ATOMIC_AND32 - FIXED_CODE_START); - BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start - != ATOMIC_XOR32 - FIXED_CODE_START); - BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start - != SAFE_USER_INSTRUCTION - FIXED_CODE_START); - -#ifdef CONFIG_SMP - platform_init_cpus(); -#endif - init_exception_vectors(); - bfin_cache_init(); /* Initialize caches for the boot CPU */ -#ifdef CONFIG_SCB_PRIORITY - init_scb(); -#endif -} - -static int __init topology_init(void) -{ - unsigned int cpu; - - for_each_possible_cpu(cpu) { - register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); - } - - return 0; -} - -subsys_initcall(topology_init); - -/* Get the input clock frequency */ -static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; -#ifndef CONFIG_BF60x -static u_long get_clkin_hz(void) -{ - return cached_clkin_hz; -} -#endif -static int __init early_init_clkin_hz(char *buf) -{ - cached_clkin_hz = simple_strtoul(buf, NULL, 0); -#ifdef BFIN_KERNEL_CLOCK - if (cached_clkin_hz != CONFIG_CLKIN_HZ) - panic("cannot change clkin_hz when reprogramming clocks"); -#endif - return 1; -} -early_param("clkin_hz=", early_init_clkin_hz); - -#ifndef CONFIG_BF60x -/* Get the voltage input multiplier */ -static u_long get_vco(void) -{ - static u_long cached_vco; - u_long msel, pll_ctl; - - /* The assumption here is that VCO never changes at runtime. - * If, someday, we support that, then we'll have to change this. - */ - if (cached_vco) - return cached_vco; - - pll_ctl = bfin_read_PLL_CTL(); - msel = (pll_ctl >> 9) & 0x3F; - if (0 == msel) - msel = 64; - - cached_vco = get_clkin_hz(); - cached_vco >>= (1 & pll_ctl); /* DF bit */ - cached_vco *= msel; - return cached_vco; -} -#endif - -/* Get the Core clock */ -u_long get_cclk(void) -{ -#ifdef CONFIG_BF60x - return bfin_get_clk("CCLK"); -#else - static u_long cached_cclk_pll_div, cached_cclk; - u_long csel, ssel; - - if (bfin_read_PLL_STAT() & 0x1) - return get_clkin_hz(); - - ssel = bfin_read_PLL_DIV(); - if (ssel == cached_cclk_pll_div) - return cached_cclk; - else - cached_cclk_pll_div = ssel; - - csel = ((ssel >> 4) & 0x03); - ssel &= 0xf; - if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */ - cached_cclk = get_vco() / ssel; - else - cached_cclk = get_vco() >> csel; - return cached_cclk; -#endif -} -EXPORT_SYMBOL(get_cclk); - -#ifdef CONFIG_BF60x -/* Get the bf60x clock of SCLK0 domain */ -u_long get_sclk0(void) -{ - return bfin_get_clk("SCLK0"); -} -EXPORT_SYMBOL(get_sclk0); - -/* Get the bf60x clock of SCLK1 domain */ -u_long get_sclk1(void) -{ - return bfin_get_clk("SCLK1"); -} -EXPORT_SYMBOL(get_sclk1); - -/* Get the bf60x DRAM clock */ -u_long get_dclk(void) -{ - return bfin_get_clk("DCLK"); -} -EXPORT_SYMBOL(get_dclk); -#endif - -/* Get the default system clock */ -u_long get_sclk(void) -{ -#ifdef CONFIG_BF60x - return get_sclk0(); -#else - static u_long cached_sclk; - u_long ssel; - - /* The assumption here is that SCLK never changes at runtime. - * If, someday, we support that, then we'll have to change this. - */ - if (cached_sclk) - return cached_sclk; - - if (bfin_read_PLL_STAT() & 0x1) - return get_clkin_hz(); - - ssel = bfin_read_PLL_DIV() & 0xf; - if (0 == ssel) { - printk(KERN_WARNING "Invalid System Clock\n"); - ssel = 1; - } - - cached_sclk = get_vco() / ssel; - return cached_sclk; -#endif -} -EXPORT_SYMBOL(get_sclk); - -unsigned long sclk_to_usecs(unsigned long sclk) -{ - u64 tmp = USEC_PER_SEC * (u64)sclk; - do_div(tmp, get_sclk()); - return tmp; -} -EXPORT_SYMBOL(sclk_to_usecs); - -unsigned long usecs_to_sclk(unsigned long usecs) -{ - u64 tmp = get_sclk() * (u64)usecs; - do_div(tmp, USEC_PER_SEC); - return tmp; -} -EXPORT_SYMBOL(usecs_to_sclk); - -/* - * Get CPU information for use by the procfs. - */ -static int show_cpuinfo(struct seq_file *m, void *v) -{ - char *cpu, *mmu, *fpu, *vendor, *cache; - uint32_t revid; - int cpu_num = *(unsigned int *)v; - u_long sclk, cclk; - u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; - struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num); - - cpu = CPU; - mmu = "none"; - fpu = "none"; - revid = bfin_revid(); - - sclk = get_sclk(); - cclk = get_cclk(); - - switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { - case 0xca: - vendor = "Analog Devices"; - break; - default: - vendor = "unknown"; - break; - } - - seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor); - - if (CPUID == bfin_cpuid()) - seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); - else - seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n", - CPUID, bfin_cpuid()); - - seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n" - "stepping\t: %d ", - cpu, cclk/1000000, sclk/1000000, -#ifdef CONFIG_MPU - "mpu on", -#else - "mpu off", -#endif - revid); - - if (bfin_revid() != bfin_compiled_revid()) { - if (bfin_compiled_revid() == -1) - seq_printf(m, "(Compiled for Rev none)"); - else if (bfin_compiled_revid() == 0xffff) - seq_printf(m, "(Compiled for Rev any)"); - else - seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid()); - } - - seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n", - cclk/1000000, cclk%1000000, - sclk/1000000, sclk%1000000); - seq_printf(m, "bogomips\t: %lu.%02lu\n" - "Calibration\t: %lu loops\n", - (loops_per_jiffy * HZ) / 500000, - ((loops_per_jiffy * HZ) / 5000) % 100, - (loops_per_jiffy * HZ)); - - /* Check Cache configutation */ - switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { - case ACACHE_BSRAM: - cache = "dbank-A/B\t: cache/sram"; - dcache_size = 16; - dsup_banks = 1; - break; - case ACACHE_BCACHE: - cache = "dbank-A/B\t: cache/cache"; - dcache_size = 32; - dsup_banks = 2; - break; - case ASRAM_BSRAM: - cache = "dbank-A/B\t: sram/sram"; - dcache_size = 0; - dsup_banks = 0; - break; - default: - cache = "unknown"; - dcache_size = 0; - dsup_banks = 0; - break; - } - - /* Is it turned on? */ - if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) - dcache_size = 0; - - if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB)) - icache_size = 0; - - seq_printf(m, "cache size\t: %d KB(L1 icache) " - "%d KB(L1 dcache) %d KB(L2 cache)\n", - icache_size, dcache_size, 0); - seq_printf(m, "%s\n", cache); - seq_printf(m, "external memory\t: " -#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) - "cacheable" -#else - "uncacheable" -#endif - " in instruction cache\n"); - seq_printf(m, "external memory\t: " -#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) - "cacheable (write-back)" -#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) - "cacheable (write-through)" -#else - "uncacheable" -#endif - " in data cache\n"); - - if (icache_size) - seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", - BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES); - else - seq_printf(m, "icache setup\t: off\n"); - - seq_printf(m, - "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", - dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, - BFIN_DLINES); -#ifdef __ARCH_SYNC_CORE_DCACHE - seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]); -#endif -#ifdef __ARCH_SYNC_CORE_ICACHE - seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]); -#endif - - seq_printf(m, "\n"); - - if (cpu_num != num_possible_cpus() - 1) - return 0; - - if (L2_LENGTH) { - seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); - seq_printf(m, "L2 SRAM\t\t: " -#if defined(CONFIG_BFIN_L2_ICACHEABLE) - "cacheable" -#else - "uncacheable" -#endif - " in instruction cache\n"); - seq_printf(m, "L2 SRAM\t\t: " -#if defined(CONFIG_BFIN_L2_WRITEBACK) - "cacheable (write-back)" -#elif defined(CONFIG_BFIN_L2_WRITETHROUGH) - "cacheable (write-through)" -#else - "uncacheable" -#endif - " in data cache\n"); - } - seq_printf(m, "board name\t: %s\n", bfin_board_name); - seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n", - physical_mem_end >> 10, 0ul, physical_mem_end); - seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n", - ((int)memory_end - (int)_rambase) >> 10, - _rambase, memory_end); - - return 0; -} - -static void *c_start(struct seq_file *m, loff_t *pos) -{ - if (*pos == 0) - *pos = cpumask_first(cpu_online_mask); - if (*pos >= num_online_cpus()) - return NULL; - - return pos; -} - -static void *c_next(struct seq_file *m, void *v, loff_t *pos) -{ - *pos = cpumask_next(*pos, cpu_online_mask); - - return c_start(m, pos); -} - -static void c_stop(struct seq_file *m, void *v) -{ -} - -const struct seq_operations cpuinfo_op = { - .start = c_start, - .next = c_next, - .stop = c_stop, - .show = show_cpuinfo, -}; - -void __init cmdline_init(const char *r0) -{ - early_shadow_stamp(); - if (r0) - strlcpy(command_line, r0, COMMAND_LINE_SIZE); -} diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c deleted file mode 100644 index aeb8343eeb03..000000000000 --- a/arch/blackfin/kernel/shadow_console.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * manage a small early shadow of the log buffer which we can pass between the - * bootloader so early crash messages are communicated properly and easily - * - * Copyright 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500) -#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000) -#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0) -#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF) - -static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START; - -__init void early_shadow_write(struct console *con, const char *s, - unsigned int n) -{ - unsigned int i; - /* - * save 2 bytes for the double null at the end - * once we fail on a long line, make sure we don't write a short line afterwards - */ - if ((shadow_console_buffer + n) <= (char *)(SHADOW_CONSOLE_END - 2)) { - /* can't use memcpy - it may not be relocated yet */ - for (i = 0; i <= n; i++) - shadow_console_buffer[i] = s[i]; - shadow_console_buffer += n; - shadow_console_buffer[0] = 0; - shadow_console_buffer[1] = 0; - } else - shadow_console_buffer = (char *)SHADOW_CONSOLE_END; -} - -static __initdata struct console early_shadow_console = { - .name = "early_shadow", - .write = early_shadow_write, - .flags = CON_BOOT | CON_PRINTBUFFER, - .index = -1, - .device = 0, -}; - -__init int shadow_console_enabled(void) -{ - return early_shadow_console.flags & CON_ENABLED; -} - -__init void mark_shadow_error(void) -{ - int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC; - loc[0] = SHADOW_CONSOLE_MAGIC; - loc[1] = SHADOW_CONSOLE_START; -} - -__init void enable_shadow_console(void) -{ - if (!shadow_console_enabled()) { - register_console(&early_shadow_console); - /* for now, assume things are going to fail */ - mark_shadow_error(); - } -} - -static __init int disable_shadow_console(void) -{ - /* - * by the time pure_initcall runs, the standard console is enabled, - * and the early_console is off, so unset the magic numbers - * unregistering the console is taken care of in common code (See - * ./kernel/printk:disable_boot_consoles() ) - */ - int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC; - - loc[0] = 0; - - return 0; -} -pure_initcall(disable_shadow_console); - -/* - * since we can't use printk, dump numbers (as hex), n = # bits - */ -__init void early_shadow_reg(unsigned long reg, unsigned int n) -{ - /* - * can't use any "normal" kernel features, since thay - * may not be relocated to their execute address yet - */ - int i; - char ascii[11] = " 0x"; - - n = n / 4; - reg = reg << ((8 - n) * 4); - n += 3; - - for (i = 3; i <= n ; i++) { - ascii[i] = hex_asc_lo(reg >> 28); - reg <<= 4; - } - early_shadow_write(NULL, ascii, n); - -} diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c deleted file mode 100644 index 5f5172779204..000000000000 --- a/arch/blackfin/kernel/signal.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* Location of the trace bit in SYSCFG. */ -#define TRACE_BITS 0x0001 - -struct fdpic_func_descriptor { - unsigned long text; - unsigned long GOT; -}; - -struct rt_sigframe { - int sig; - struct siginfo *pinfo; - void *puc; - /* This is no longer needed by the kernel, but unfortunately userspace - * code expects it to be there. */ - char retcode[8]; - struct siginfo info; - struct ucontext uc; -}; - -static inline int -rt_restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *pr0) -{ - unsigned long usp = 0; - int err = 0; - - /* Always make any pending restarted system calls return -EINTR */ - current->restart_block.fn = do_no_restart_syscall; - -#define RESTORE(x) err |= __get_user(regs->x, &sc->sc_##x) - - /* restore passed registers */ - RESTORE(r0); RESTORE(r1); RESTORE(r2); RESTORE(r3); - RESTORE(r4); RESTORE(r5); RESTORE(r6); RESTORE(r7); - RESTORE(p0); RESTORE(p1); RESTORE(p2); RESTORE(p3); - RESTORE(p4); RESTORE(p5); - err |= __get_user(usp, &sc->sc_usp); - wrusp(usp); - RESTORE(a0w); RESTORE(a1w); - RESTORE(a0x); RESTORE(a1x); - RESTORE(astat); - RESTORE(rets); - RESTORE(pc); - RESTORE(retx); - RESTORE(fp); - RESTORE(i0); RESTORE(i1); RESTORE(i2); RESTORE(i3); - RESTORE(m0); RESTORE(m1); RESTORE(m2); RESTORE(m3); - RESTORE(l0); RESTORE(l1); RESTORE(l2); RESTORE(l3); - RESTORE(b0); RESTORE(b1); RESTORE(b2); RESTORE(b3); - RESTORE(lc0); RESTORE(lc1); - RESTORE(lt0); RESTORE(lt1); - RESTORE(lb0); RESTORE(lb1); - RESTORE(seqstat); - - regs->orig_p0 = -1; /* disable syscall checks */ - - *pr0 = regs->r0; - return err; -} - -asmlinkage int sys_rt_sigreturn(void) -{ - struct pt_regs *regs = current_pt_regs(); - unsigned long usp = rdusp(); - struct rt_sigframe *frame = (struct rt_sigframe *)(usp); - sigset_t set; - int r0; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - set_current_blocked(&set); - - if (rt_restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) - goto badframe; - - if (restore_altstack(&frame->uc.uc_stack)) - goto badframe; - - return r0; - - badframe: - force_sig(SIGSEGV, current); - return 0; -} - -static inline int rt_setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs) -{ - int err = 0; - -#define SETUP(x) err |= __put_user(regs->x, &sc->sc_##x) - - SETUP(r0); SETUP(r1); SETUP(r2); SETUP(r3); - SETUP(r4); SETUP(r5); SETUP(r6); SETUP(r7); - SETUP(p0); SETUP(p1); SETUP(p2); SETUP(p3); - SETUP(p4); SETUP(p5); - err |= __put_user(rdusp(), &sc->sc_usp); - SETUP(a0w); SETUP(a1w); - SETUP(a0x); SETUP(a1x); - SETUP(astat); - SETUP(rets); - SETUP(pc); - SETUP(retx); - SETUP(fp); - SETUP(i0); SETUP(i1); SETUP(i2); SETUP(i3); - SETUP(m0); SETUP(m1); SETUP(m2); SETUP(m3); - SETUP(l0); SETUP(l1); SETUP(l2); SETUP(l3); - SETUP(b0); SETUP(b1); SETUP(b2); SETUP(b3); - SETUP(lc0); SETUP(lc1); - SETUP(lt0); SETUP(lt1); - SETUP(lb0); SETUP(lb1); - SETUP(seqstat); - - return err; -} - -static inline void *get_sigframe(struct ksignal *ksig, - size_t frame_size) -{ - unsigned long usp = sigsp(rdusp(), ksig); - - return (void *)((usp - frame_size) & -8UL); -} - -static int -setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) -{ - struct rt_sigframe *frame; - int err = 0; - - frame = get_sigframe(ksig, sizeof(*frame)); - - err |= __put_user(ksig->sig, &frame->sig); - - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, &ksig->info); - - /* Create the ucontext. */ - err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); - err |= __save_altstack(&frame->uc.uc_stack, rdusp()); - err |= rt_setup_sigcontext(&frame->uc.uc_mcontext, regs); - err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - - if (err) - return -EFAULT; - - /* Set up registers for signal handler */ - if (current->personality & FDPIC_FUNCPTRS) { - struct fdpic_func_descriptor __user *funcptr = - (struct fdpic_func_descriptor *) ksig->ka.sa.sa_handler; - u32 pc, p3; - err |= __get_user(pc, &funcptr->text); - err |= __get_user(p3, &funcptr->GOT); - if (err) - return -EFAULT; - regs->pc = pc; - regs->p3 = p3; - } else - regs->pc = (unsigned long)ksig->ka.sa.sa_handler; - wrusp((unsigned long)frame); - regs->rets = SIGRETURN_STUB; - - regs->r0 = frame->sig; - regs->r1 = (unsigned long)(&frame->info); - regs->r2 = (unsigned long)(&frame->uc); - - return 0; -} - -static inline void -handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) -{ - switch (regs->r0) { - case -ERESTARTNOHAND: - if (!has_handler) - goto do_restart; - regs->r0 = -EINTR; - break; - - case -ERESTARTSYS: - if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { - regs->r0 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - do_restart: - regs->p0 = regs->orig_p0; - regs->r0 = regs->orig_r0; - regs->pc -= 2; - break; - - case -ERESTART_RESTARTBLOCK: - regs->p0 = __NR_restart_syscall; - regs->pc -= 2; - break; - } -} - -/* - * OK, we're invoking a handler - */ -static void -handle_signal(struct ksignal *ksig, struct pt_regs *regs) -{ - int ret; - - /* are we from a system call? to see pt_regs->orig_p0 */ - if (regs->orig_p0 >= 0) - /* If so, check system call restarting.. */ - handle_restart(regs, &ksig->ka, 1); - - /* set up the stack frame */ - ret = setup_rt_frame(ksig, sigmask_to_save(), regs); - - signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP)); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - * - * Note that we go through the signals twice: once to check the signals - * that the kernel can handle, and then we build all the user-level signal - * handling stack-frames in one go after that. - */ -asmlinkage void do_signal(struct pt_regs *regs) -{ - struct ksignal ksig; - - current->thread.esp0 = (unsigned long)regs; - - if (get_signal(&ksig)) { - /* Whee! Actually deliver the signal. */ - handle_signal(&ksig, regs); - return; - } - - /* Did we come from a system call? */ - if (regs->orig_p0 >= 0) - /* Restart the system call - no handlers present */ - handle_restart(regs, NULL, 0); - - /* if there's no signal to deliver, we just put the saved sigmask - * back */ - restore_saved_sigmask(); -} - -/* - * notification of userspace execution resumption - */ -asmlinkage void do_notify_resume(struct pt_regs *regs) -{ - if (test_thread_flag(TIF_SIGPENDING)) - do_signal(regs); - - if (test_thread_flag(TIF_NOTIFY_RESUME)) { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(regs); - } -} - diff --git a/arch/blackfin/kernel/stacktrace.c b/arch/blackfin/kernel/stacktrace.c deleted file mode 100644 index 17198f3650b6..000000000000 --- a/arch/blackfin/kernel/stacktrace.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Blackfin stacktrace code (mostly copied from avr32) - * - * Copyright 2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include - -register unsigned long current_frame_pointer asm("FP"); - -struct stackframe { - unsigned long fp; - unsigned long rets; -}; - -/* - * Save stack-backtrace addresses into a stack_trace buffer. - */ -void save_stack_trace(struct stack_trace *trace) -{ - unsigned long low, high; - unsigned long fp; - struct stackframe *frame; - int skip = trace->skip; - - low = (unsigned long)task_stack_page(current); - high = low + THREAD_SIZE; - fp = current_frame_pointer; - - while (fp >= low && fp <= (high - sizeof(*frame))) { - frame = (struct stackframe *)fp; - - if (skip) { - skip--; - } else { - trace->entries[trace->nr_entries++] = frame->rets; - if (trace->nr_entries >= trace->max_entries) - break; - } - - /* - * The next frame must be at a higher address than the - * current frame. - */ - low = fp + sizeof(*frame); - fp = frame->fp; - } -} -EXPORT_SYMBOL_GPL(save_stack_trace); diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c deleted file mode 100644 index d998383cb956..000000000000 --- a/arch/blackfin/kernel/sys_bfin.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * contains various random system calls that have a non-standard - * calling sequence on the Linux/Blackfin platform. - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags) -{ - return sram_alloc_with_lsl(size, flags); -} - -asmlinkage int sys_sram_free(const void *addr) -{ - return sram_free_with_lsl(addr); -} - -asmlinkage void *sys_dma_memcpy(void *dest, const void *src, size_t len) -{ - return safe_dma_memcpy(dest, src, len); -} - -#if defined(CONFIG_FB) || defined(CONFIG_FB_MODULE) -#include -#include -unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, - unsigned long len, unsigned long pgoff, unsigned long flags) -{ - struct fb_info *info = filp->private_data; - return (unsigned long)info->screen_base; -} -EXPORT_SYMBOL(get_fb_unmapped_area); -#endif - -/* Needed for legacy userspace atomic emulation */ -static DEFINE_SPINLOCK(bfin_spinlock_lock); - -#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1 -__attribute__((l1_text)) -#endif -asmlinkage int sys_bfin_spinlock(int *p) -{ - int ret, tmp = 0; - - spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */ - ret = get_user(tmp, p); - if (likely(ret == 0)) { - if (unlikely(tmp)) - ret = 1; - else - put_user(1, p); - } - spin_unlock(&bfin_spinlock_lock); - - return ret; -} - -SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op) -{ - if (is_user_addr_valid(current, addr, len) != 0) - return -EINVAL; - - if (op & DCACHE) - blackfin_dcache_flush_range(addr, addr + len); - if (op & ICACHE) - blackfin_icache_flush_range(addr, addr + len); - - return 0; -} diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c deleted file mode 100644 index 01350557fbd7..000000000000 --- a/arch/blackfin/kernel/time-ts.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Based on arm clockevents implementation and old bfin time tick. - * - * Copyright 2008-2009 Analog Devics Inc. - * 2008 GeoTechnologies - * Vitja Makarov - * - * Licensed under the GPL-2 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - - -#if defined(CONFIG_CYCLES_CLOCKSOURCE) - -static notrace u64 bfin_read_cycles(struct clocksource *cs) -{ -#ifdef CONFIG_CPU_FREQ - return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); -#else - return get_cycles(); -#endif -} - -static struct clocksource bfin_cs_cycles = { - .name = "bfin_cs_cycles", - .rating = 400, - .read = bfin_read_cycles, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static inline unsigned long long bfin_cs_cycles_sched_clock(void) -{ - return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles), - bfin_cs_cycles.mult, bfin_cs_cycles.shift); -} - -static int __init bfin_cs_cycles_init(void) -{ - if (clocksource_register_hz(&bfin_cs_cycles, get_cclk())) - panic("failed to register clocksource"); - - return 0; -} -#else -# define bfin_cs_cycles_init() -#endif - -#ifdef CONFIG_GPTMR0_CLOCKSOURCE - -void __init setup_gptimer0(void) -{ - disable_gptimers(TIMER0bit); - -#ifdef CONFIG_BF60x - bfin_write16(TIMER_DATA_IMSK, 0); - set_gptimer_config(TIMER0_id, TIMER_OUT_DIS - | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER); -#else - set_gptimer_config(TIMER0_id, \ - TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM); -#endif - set_gptimer_period(TIMER0_id, -1); - set_gptimer_pwidth(TIMER0_id, -2); - SSYNC(); - enable_gptimers(TIMER0bit); -} - -static u64 bfin_read_gptimer0(struct clocksource *cs) -{ - return bfin_read_TIMER0_COUNTER(); -} - -static struct clocksource bfin_cs_gptimer0 = { - .name = "bfin_cs_gptimer0", - .rating = 350, - .read = bfin_read_gptimer0, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static inline unsigned long long bfin_cs_gptimer0_sched_clock(void) -{ - return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(), - bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift); -} - -static int __init bfin_cs_gptimer0_init(void) -{ - setup_gptimer0(); - - if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk())) - panic("failed to register clocksource"); - - return 0; -} -#else -# define bfin_cs_gptimer0_init() -#endif - -#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE) -/* prefer to use cycles since it has higher rating */ -notrace unsigned long long sched_clock(void) -{ -#if defined(CONFIG_CYCLES_CLOCKSOURCE) - return bfin_cs_cycles_sched_clock(); -#else - return bfin_cs_gptimer0_sched_clock(); -#endif -} -#endif - -#if defined(CONFIG_TICKSOURCE_GPTMR0) -static int bfin_gptmr0_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - disable_gptimers(TIMER0bit); - - /* it starts counting three SCLK cycles after the TIMENx bit is set */ - set_gptimer_pwidth(TIMER0_id, cycles - 3); - enable_gptimers(TIMER0bit); - return 0; -} - -static int bfin_gptmr0_set_periodic(struct clock_event_device *evt) -{ -#ifndef CONFIG_BF60x - set_gptimer_config(TIMER0_id, - TIMER_OUT_DIS | TIMER_IRQ_ENA | - TIMER_PERIOD_CNT | TIMER_MODE_PWM); -#else - set_gptimer_config(TIMER0_id, - TIMER_OUT_DIS | TIMER_MODE_PWM_CONT | - TIMER_PULSE_HI | TIMER_IRQ_PER); -#endif - - set_gptimer_period(TIMER0_id, get_sclk() / HZ); - set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1); - enable_gptimers(TIMER0bit); - return 0; -} - -static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt) -{ - disable_gptimers(TIMER0bit); -#ifndef CONFIG_BF60x - set_gptimer_config(TIMER0_id, - TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM); -#else - set_gptimer_config(TIMER0_id, - TIMER_OUT_DIS | TIMER_MODE_PWM | TIMER_PULSE_HI | - TIMER_IRQ_WID_DLY); -#endif - - set_gptimer_period(TIMER0_id, 0); - return 0; -} - -static int bfin_gptmr0_shutdown(struct clock_event_device *evt) -{ - disable_gptimers(TIMER0bit); - return 0; -} - -static void bfin_gptmr0_ack(void) -{ - clear_gptimer_intr(TIMER0_id); -} - -static void __init bfin_gptmr0_init(void) -{ - disable_gptimers(TIMER0bit); -} - -#ifdef CONFIG_CORE_TIMER_IRQ_L1 -__attribute__((l1_text)) -#endif -irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - smp_mb(); - /* - * We want to ACK before we handle so that we can handle smaller timer - * intervals. This way if the timer expires again while we're handling - * things, we're more likely to see that 2nd int rather than swallowing - * it by ACKing the int at the end of this handler. - */ - bfin_gptmr0_ack(); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction gptmr0_irq = { - .name = "Blackfin GPTimer0", - .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU, - .handler = bfin_gptmr0_interrupt, -}; - -static struct clock_event_device clockevent_gptmr0 = { - .name = "bfin_gptimer0", - .rating = 300, - .irq = IRQ_TIMER0, - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = bfin_gptmr0_set_next_event, - .set_state_shutdown = bfin_gptmr0_shutdown, - .set_state_periodic = bfin_gptmr0_set_periodic, - .set_state_oneshot = bfin_gptmr0_set_oneshot, -}; - -static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt) -{ - unsigned long clock_tick; - - clock_tick = get_sclk(); - evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(-1, evt); - evt->max_delta_ticks = (unsigned long)-1; - evt->min_delta_ns = clockevent_delta2ns(100, evt); - evt->min_delta_ticks = 100; - - evt->cpumask = cpumask_of(0); - - clockevents_register_device(evt); -} -#endif /* CONFIG_TICKSOURCE_GPTMR0 */ - -#if defined(CONFIG_TICKSOURCE_CORETMR) -/* per-cpu local core timer */ -DEFINE_PER_CPU(struct clock_event_device, coretmr_events); - -static int bfin_coretmr_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - bfin_write_TCNTL(TMPWR); - CSYNC(); - bfin_write_TCOUNT(cycles); - CSYNC(); - bfin_write_TCNTL(TMPWR | TMREN); - return 0; -} - -static int bfin_coretmr_set_periodic(struct clock_event_device *evt) -{ - unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); - - bfin_write_TCNTL(TMPWR); - CSYNC(); - bfin_write_TSCALE(TIME_SCALE - 1); - bfin_write_TPERIOD(tcount); - bfin_write_TCOUNT(tcount); - CSYNC(); - bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD); - return 0; -} - -static int bfin_coretmr_set_oneshot(struct clock_event_device *evt) -{ - bfin_write_TCNTL(TMPWR); - CSYNC(); - bfin_write_TSCALE(TIME_SCALE - 1); - bfin_write_TPERIOD(0); - bfin_write_TCOUNT(0); - return 0; -} - -static int bfin_coretmr_shutdown(struct clock_event_device *evt) -{ - bfin_write_TCNTL(0); - CSYNC(); - return 0; -} - -void bfin_coretmr_init(void) -{ - /* power up the timer, but don't enable it just yet */ - bfin_write_TCNTL(TMPWR); - CSYNC(); - - /* the TSCALE prescaler counter. */ - bfin_write_TSCALE(TIME_SCALE - 1); - bfin_write_TPERIOD(0); - bfin_write_TCOUNT(0); - - CSYNC(); -} - -#ifdef CONFIG_CORE_TIMER_IRQ_L1 -__attribute__((l1_text)) -#endif - -irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id) -{ - int cpu = smp_processor_id(); - struct clock_event_device *evt = &per_cpu(coretmr_events, cpu); - - smp_mb(); - evt->event_handler(evt); - - touch_nmi_watchdog(); - - return IRQ_HANDLED; -} - -static struct irqaction coretmr_irq = { - .name = "Blackfin CoreTimer", - .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU, - .handler = bfin_coretmr_interrupt, -}; - -void bfin_coretmr_clockevent_init(void) -{ - unsigned long clock_tick; - unsigned int cpu = smp_processor_id(); - struct clock_event_device *evt = &per_cpu(coretmr_events, cpu); - -#ifdef CONFIG_SMP - evt->broadcast = smp_timer_broadcast; -#endif - - evt->name = "bfin_core_timer"; - evt->rating = 350; - evt->irq = -1; - evt->shift = 32; - evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - evt->set_next_event = bfin_coretmr_set_next_event; - evt->set_state_shutdown = bfin_coretmr_shutdown; - evt->set_state_periodic = bfin_coretmr_set_periodic; - evt->set_state_oneshot = bfin_coretmr_set_oneshot; - - clock_tick = get_cclk() / TIME_SCALE; - evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(-1, evt); - evt->max_delta_ticks = (unsigned long)-1; - evt->min_delta_ns = clockevent_delta2ns(100, evt); - evt->min_delta_ticks = 100; - - evt->cpumask = cpumask_of(cpu); - - clockevents_register_device(evt); -} -#endif /* CONFIG_TICKSOURCE_CORETMR */ - - -void read_persistent_clock(struct timespec *ts) -{ - time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */ - ts->tv_sec = secs_since_1970; - ts->tv_nsec = 0; -} - -void __init time_init(void) -{ - -#ifdef CONFIG_RTC_DRV_BFIN - /* [#2663] hack to filter junk RTC values that would cause - * userspace to have to deal with time values greater than - * 2^31 seconds (which uClibc cannot cope with yet) - */ - if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) { - printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n"); - bfin_write_RTC_STAT(0); - } -#endif - - bfin_cs_cycles_init(); - bfin_cs_gptimer0_init(); - -#if defined(CONFIG_TICKSOURCE_CORETMR) - bfin_coretmr_init(); - setup_irq(IRQ_CORETMR, &coretmr_irq); - bfin_coretmr_clockevent_init(); -#endif - -#if defined(CONFIG_TICKSOURCE_GPTMR0) - bfin_gptmr0_init(); - setup_irq(IRQ_TIMER0, &gptmr0_irq); - gptmr0_irq.dev_id = &clockevent_gptmr0; - bfin_gptmr0_clockevent_init(&clockevent_gptmr0); -#endif - -#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0) -# error at least one clock event device is required -#endif -} diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c deleted file mode 100644 index 3126b920a4a5..000000000000 --- a/arch/blackfin/kernel/time.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * arch/blackfin/kernel/time.c - * - * This file contains the Blackfin-specific time handling details. - * Most of the stuff is located in the machine specific files. - * - * Copyright 2004-2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* This is an NTP setting */ -#define TICK_SIZE (tick_nsec / 1000) - -static struct irqaction bfin_timer_irq = { - .name = "Blackfin Timer Tick", -}; - -#if defined(CONFIG_IPIPE) -void __init setup_system_timer0(void) -{ - /* Power down the core timer, just to play safe. */ - bfin_write_TCNTL(0); - - disable_gptimers(TIMER0bit); - set_gptimer_status(0, TIMER_STATUS_TRUN0); - while (get_gptimer_status(0) & TIMER_STATUS_TRUN0) - udelay(10); - - set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */ - set_gptimer_period(TIMER0_id, get_sclk() / HZ); - set_gptimer_pwidth(TIMER0_id, 1); - SSYNC(); - enable_gptimers(TIMER0bit); -} -#else -void __init setup_core_timer(void) -{ - u32 tcount; - - /* power up the timer, but don't enable it just yet */ - bfin_write_TCNTL(TMPWR); - CSYNC(); - - /* the TSCALE prescaler counter */ - bfin_write_TSCALE(TIME_SCALE - 1); - - tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); - bfin_write_TPERIOD(tcount); - bfin_write_TCOUNT(tcount); - - /* now enable the timer */ - CSYNC(); - - bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR); -} -#endif - -static void __init -time_sched_init(irqreturn_t(*timer_routine) (int, void *)) -{ -#if defined(CONFIG_IPIPE) - setup_system_timer0(); - bfin_timer_irq.handler = timer_routine; - setup_irq(IRQ_TIMER0, &bfin_timer_irq); -#else - setup_core_timer(); - bfin_timer_irq.handler = timer_routine; - setup_irq(IRQ_CORETMR, &bfin_timer_irq); -#endif -} - -#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET -/* - * Should return useconds since last timer tick - */ -static u32 blackfin_gettimeoffset(void) -{ - unsigned long offset; - unsigned long clocks_per_jiffy; - -#if defined(CONFIG_IPIPE) - clocks_per_jiffy = bfin_read_TIMER0_PERIOD(); - offset = bfin_read_TIMER0_COUNTER() / \ - (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); - - if ((get_gptimer_status(0) & TIMER_STATUS_TIMIL0) && offset < (100000 / HZ / 2)) - offset += (USEC_PER_SEC / HZ); -#else - clocks_per_jiffy = bfin_read_TPERIOD(); - offset = (clocks_per_jiffy - bfin_read_TCOUNT()) / \ - (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); - - /* Check if we just wrapped the counters and maybe missed a tick */ - if ((bfin_read_ILAT() & (1 << IRQ_CORETMR)) - && (offset < (100000 / HZ / 2))) - offset += (USEC_PER_SEC / HZ); -#endif - return offset; -} -#endif - -/* - * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "xtime_update()" routine every clocktick - */ -#ifdef CONFIG_CORE_TIMER_IRQ_L1 -__attribute__((l1_text)) -#endif -irqreturn_t timer_interrupt(int irq, void *dummy) -{ - xtime_update(1); - -#ifdef CONFIG_IPIPE - update_root_process_times(get_irq_regs()); -#else - update_process_times(user_mode(get_irq_regs())); -#endif - profile_tick(CPU_PROFILING); - - return IRQ_HANDLED; -} - -void read_persistent_clock(struct timespec *ts) -{ - time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */ - ts->tv_sec = secs_since_1970; - ts->tv_nsec = 0; -} - -void __init time_init(void) -{ -#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET - arch_gettimeoffset = blackfin_gettimeoffset; -#endif - -#ifdef CONFIG_RTC_DRV_BFIN - /* [#2663] hack to filter junk RTC values that would cause - * userspace to have to deal with time values greater than - * 2^31 seconds (which uClibc cannot cope with yet) - */ - if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) { - printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n"); - bfin_write_RTC_STAT(0); - } -#endif - - time_sched_init(timer_interrupt); -} diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c deleted file mode 100644 index 151f22196ab6..000000000000 --- a/arch/blackfin/kernel/trace.c +++ /dev/null @@ -1,988 +0,0 @@ -/* provide some functions which dump the trace buffer, in a nice way for people - * to read it, and understand what is going on - * - * Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void decode_address(char *buf, unsigned long address) -{ - struct task_struct *p; - struct mm_struct *mm; - unsigned long offset; - struct rb_node *n; - -#ifdef CONFIG_KALLSYMS - unsigned long symsize; - const char *symname; - char *modname; - char *delim = ":"; - char namebuf[128]; -#endif - - buf += sprintf(buf, "<0x%08lx> ", address); - -#ifdef CONFIG_KALLSYMS - /* look up the address and see if we are in kernel space */ - symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf); - - if (symname) { - /* yeah! kernel space! */ - if (!modname) - modname = delim = ""; - sprintf(buf, "{ %s%s%s%s + 0x%lx }", - delim, modname, delim, symname, - (unsigned long)offset); - return; - } -#endif - - if (address >= FIXED_CODE_START && address < FIXED_CODE_END) { - /* Problem in fixed code section? */ - strcat(buf, "/* Maybe fixed code section */"); - return; - - } else if (address < CONFIG_BOOT_LOAD) { - /* Problem somewhere before the kernel start address */ - strcat(buf, "/* Maybe null pointer? */"); - return; - - } else if (address >= COREMMR_BASE) { - strcat(buf, "/* core mmrs */"); - return; - - } else if (address >= SYSMMR_BASE) { - strcat(buf, "/* system mmrs */"); - return; - - } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) { - strcat(buf, "/* on-chip L1 ROM */"); - return; - - } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) { - strcat(buf, "/* on-chip scratchpad */"); - return; - - } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) { - strcat(buf, "/* unconnected memory */"); - return; - - } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) { - strcat(buf, "/* reserved memory */"); - return; - - } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) { - strcat(buf, "/* on-chip Data Bank A */"); - return; - - } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) { - strcat(buf, "/* on-chip Data Bank B */"); - return; - } - - /* - * Don't walk any of the vmas if we are oopsing, it has been known - * to cause problems - corrupt vmas (kernel crashes) cause double faults - */ - if (oops_in_progress) { - strcat(buf, "/* kernel dynamic memory (maybe user-space) */"); - return; - } - - /* looks like we're off in user-land, so let's walk all the - * mappings of all our processes and see if we can't be a whee - * bit more specific - */ - read_lock(&tasklist_lock); - for_each_process(p) { - struct task_struct *t; - - t = find_lock_task_mm(p); - if (!t) - continue; - - mm = t->mm; - if (!down_read_trylock(&mm->mmap_sem)) - goto __continue; - - for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) { - struct vm_area_struct *vma; - - vma = rb_entry(n, struct vm_area_struct, vm_rb); - - if (address >= vma->vm_start && address < vma->vm_end) { - char _tmpbuf[256]; - char *name = t->comm; - struct file *file = vma->vm_file; - - if (file) { - char *d_name = file_path(file, _tmpbuf, - sizeof(_tmpbuf)); - if (!IS_ERR(d_name)) - name = d_name; - } - - /* FLAT does not have its text aligned to the start of - * the map while FDPIC ELF does ... - */ - - /* before we can check flat/fdpic, we need to - * make sure current is valid - */ - if ((unsigned long)current >= FIXED_CODE_START && - !((unsigned long)current & 0x3)) { - if (current->mm && - (address > current->mm->start_code) && - (address < current->mm->end_code)) - offset = address - current->mm->start_code; - else - offset = (address - vma->vm_start) + - (vma->vm_pgoff << PAGE_SHIFT); - - sprintf(buf, "[ %s + 0x%lx ]", name, offset); - } else - sprintf(buf, "[ %s vma:0x%lx-0x%lx]", - name, vma->vm_start, vma->vm_end); - - up_read(&mm->mmap_sem); - task_unlock(t); - - if (buf[0] == '\0') - sprintf(buf, "[ %s ] dynamic memory", name); - - goto done; - } - } - - up_read(&mm->mmap_sem); -__continue: - task_unlock(t); - } - - /* - * we were unable to find this address anywhere, - * or some MMs were skipped because they were in use. - */ - sprintf(buf, "/* kernel dynamic memory */"); - -done: - read_unlock(&tasklist_lock); -} - -#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1) - -/* - * Similar to get_user, do some address checking, then dereference - * Return true on success, false on bad address - */ -bool get_mem16(unsigned short *val, unsigned short *address) -{ - unsigned long addr = (unsigned long)address; - - /* Check for odd addresses */ - if (addr & 0x1) - return false; - - switch (bfin_mem_access_type(addr, 2)) { - case BFIN_MEM_ACCESS_CORE: - case BFIN_MEM_ACCESS_CORE_ONLY: - *val = *address; - return true; - case BFIN_MEM_ACCESS_DMA: - dma_memcpy(val, address, 2); - return true; - case BFIN_MEM_ACCESS_ITEST: - isram_memcpy(val, address, 2); - return true; - default: /* invalid access */ - return false; - } -} - -bool get_instruction(unsigned int *val, unsigned short *address) -{ - unsigned long addr = (unsigned long)address; - unsigned short opcode0, opcode1; - - /* Check for odd addresses */ - if (addr & 0x1) - return false; - - /* MMR region will never have instructions */ - if (addr >= SYSMMR_BASE) - return false; - - /* Scratchpad will never have instructions */ - if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH) - return false; - - /* Data banks will never have instructions */ - if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START) - return false; - - if (!get_mem16(&opcode0, address)) - return false; - - /* was this a 32-bit instruction? If so, get the next 16 bits */ - if ((opcode0 & 0xc000) == 0xc000) { - if (!get_mem16(&opcode1, address + 1)) - return false; - *val = (opcode0 << 16) + opcode1; - } else - *val = opcode0; - - return true; -} - -#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON) -/* - * decode the instruction if we are printing out the trace, as it - * makes things easier to follow, without running it through objdump - * Decode the change of flow, and the common load/store instructions - * which are the main cause for faults, and discontinuities in the trace - * buffer. - */ - -#define ProgCtrl_opcode 0x0000 -#define ProgCtrl_poprnd_bits 0 -#define ProgCtrl_poprnd_mask 0xf -#define ProgCtrl_prgfunc_bits 4 -#define ProgCtrl_prgfunc_mask 0xf -#define ProgCtrl_code_bits 8 -#define ProgCtrl_code_mask 0xff - -static void decode_ProgCtrl_0(unsigned int opcode) -{ - int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); - int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); - - if (prgfunc == 0 && poprnd == 0) - pr_cont("NOP"); - else if (prgfunc == 1 && poprnd == 0) - pr_cont("RTS"); - else if (prgfunc == 1 && poprnd == 1) - pr_cont("RTI"); - else if (prgfunc == 1 && poprnd == 2) - pr_cont("RTX"); - else if (prgfunc == 1 && poprnd == 3) - pr_cont("RTN"); - else if (prgfunc == 1 && poprnd == 4) - pr_cont("RTE"); - else if (prgfunc == 2 && poprnd == 0) - pr_cont("IDLE"); - else if (prgfunc == 2 && poprnd == 3) - pr_cont("CSYNC"); - else if (prgfunc == 2 && poprnd == 4) - pr_cont("SSYNC"); - else if (prgfunc == 2 && poprnd == 5) - pr_cont("EMUEXCPT"); - else if (prgfunc == 3) - pr_cont("CLI R%i", poprnd); - else if (prgfunc == 4) - pr_cont("STI R%i", poprnd); - else if (prgfunc == 5) - pr_cont("JUMP (P%i)", poprnd); - else if (prgfunc == 6) - pr_cont("CALL (P%i)", poprnd); - else if (prgfunc == 7) - pr_cont("CALL (PC + P%i)", poprnd); - else if (prgfunc == 8) - pr_cont("JUMP (PC + P%i", poprnd); - else if (prgfunc == 9) - pr_cont("RAISE %i", poprnd); - else if (prgfunc == 10) - pr_cont("EXCPT %i", poprnd); - else - pr_cont("0x%04x", opcode); - -} - -#define BRCC_opcode 0x1000 -#define BRCC_offset_bits 0 -#define BRCC_offset_mask 0x3ff -#define BRCC_B_bits 10 -#define BRCC_B_mask 0x1 -#define BRCC_T_bits 11 -#define BRCC_T_mask 0x1 -#define BRCC_code_bits 12 -#define BRCC_code_mask 0xf - -static void decode_BRCC_0(unsigned int opcode) -{ - int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask); - int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask); - - pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : ""); -} - -#define CALLa_opcode 0xe2000000 -#define CALLa_addr_bits 0 -#define CALLa_addr_mask 0xffffff -#define CALLa_S_bits 24 -#define CALLa_S_mask 0x1 -#define CALLa_code_bits 25 -#define CALLa_code_mask 0x7f - -static void decode_CALLa_0(unsigned int opcode) -{ - int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask); - - if (S) - pr_cont("CALL pcrel"); - else - pr_cont("JUMP.L"); -} - -#define LoopSetup_opcode 0xe0800000 -#define LoopSetup_eoffset_bits 0 -#define LoopSetup_eoffset_mask 0x3ff -#define LoopSetup_dontcare_bits 10 -#define LoopSetup_dontcare_mask 0x3 -#define LoopSetup_reg_bits 12 -#define LoopSetup_reg_mask 0xf -#define LoopSetup_soffset_bits 16 -#define LoopSetup_soffset_mask 0xf -#define LoopSetup_c_bits 20 -#define LoopSetup_c_mask 0x1 -#define LoopSetup_rop_bits 21 -#define LoopSetup_rop_mask 0x3 -#define LoopSetup_code_bits 23 -#define LoopSetup_code_mask 0x1ff - -static void decode_LoopSetup_0(unsigned int opcode) -{ - int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask); - int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask); - int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask); - - pr_cont("LSETUP <> LC%i", c); - if ((rop & 1) == 1) - pr_cont("= P%i", reg); - if ((rop & 2) == 2) - pr_cont(" >> 0x1"); -} - -#define DspLDST_opcode 0x9c00 -#define DspLDST_reg_bits 0 -#define DspLDST_reg_mask 0x7 -#define DspLDST_i_bits 3 -#define DspLDST_i_mask 0x3 -#define DspLDST_m_bits 5 -#define DspLDST_m_mask 0x3 -#define DspLDST_aop_bits 7 -#define DspLDST_aop_mask 0x3 -#define DspLDST_W_bits 9 -#define DspLDST_W_mask 0x1 -#define DspLDST_code_bits 10 -#define DspLDST_code_mask 0x3f - -static void decode_dspLDST_0(unsigned int opcode) -{ - int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask); - int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask); - int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask); - int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask); - int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask); - - if (W == 0) { - pr_cont("R%i", reg); - switch (m) { - case 0: - pr_cont(" = "); - break; - case 1: - pr_cont(".L = "); - break; - case 2: - pr_cont(".W = "); - break; - } - } - - pr_cont("[ I%i", i); - - switch (aop) { - case 0: - pr_cont("++ ]"); - break; - case 1: - pr_cont("-- ]"); - break; - } - - if (W == 1) { - pr_cont(" = R%i", reg); - switch (m) { - case 1: - pr_cont(".L = "); - break; - case 2: - pr_cont(".W = "); - break; - } - } -} - -#define LDST_opcode 0x9000 -#define LDST_reg_bits 0 -#define LDST_reg_mask 0x7 -#define LDST_ptr_bits 3 -#define LDST_ptr_mask 0x7 -#define LDST_Z_bits 6 -#define LDST_Z_mask 0x1 -#define LDST_aop_bits 7 -#define LDST_aop_mask 0x3 -#define LDST_W_bits 9 -#define LDST_W_mask 0x1 -#define LDST_sz_bits 10 -#define LDST_sz_mask 0x3 -#define LDST_code_bits 12 -#define LDST_code_mask 0xf - -static void decode_LDST_0(unsigned int opcode) -{ - int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask); - int W = ((opcode >> LDST_W_bits) & LDST_W_mask); - int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask); - int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask); - int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask); - int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask); - - if (W == 0) - pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg); - - switch (sz) { - case 1: - pr_cont("W"); - break; - case 2: - pr_cont("B"); - break; - } - - pr_cont("[P%i", ptr); - - switch (aop) { - case 0: - pr_cont("++"); - break; - case 1: - pr_cont("--"); - break; - } - pr_cont("]"); - - if (W == 1) - pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg); - - if (sz) { - if (Z) - pr_cont(" (X)"); - else - pr_cont(" (Z)"); - } -} - -#define LDSTii_opcode 0xa000 -#define LDSTii_reg_bit 0 -#define LDSTii_reg_mask 0x7 -#define LDSTii_ptr_bit 3 -#define LDSTii_ptr_mask 0x7 -#define LDSTii_offset_bit 6 -#define LDSTii_offset_mask 0xf -#define LDSTii_op_bit 10 -#define LDSTii_op_mask 0x3 -#define LDSTii_W_bit 12 -#define LDSTii_W_mask 0x1 -#define LDSTii_code_bit 13 -#define LDSTii_code_mask 0x7 - -static void decode_LDSTii_0(unsigned int opcode) -{ - int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask); - int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask); - int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask); - int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask); - int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask); - - if (W == 0) { - pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg, - op == 1 || op == 2 ? "" : "W", ptr, offset); - if (op == 2) - pr_cont("(Z)"); - if (op == 3) - pr_cont("(X)"); - } else { - pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr, - offset, op == 3 ? "P" : "R", reg); - } -} - -#define LDSTidxI_opcode 0xe4000000 -#define LDSTidxI_offset_bits 0 -#define LDSTidxI_offset_mask 0xffff -#define LDSTidxI_reg_bits 16 -#define LDSTidxI_reg_mask 0x7 -#define LDSTidxI_ptr_bits 19 -#define LDSTidxI_ptr_mask 0x7 -#define LDSTidxI_sz_bits 22 -#define LDSTidxI_sz_mask 0x3 -#define LDSTidxI_Z_bits 24 -#define LDSTidxI_Z_mask 0x1 -#define LDSTidxI_W_bits 25 -#define LDSTidxI_W_mask 0x1 -#define LDSTidxI_code_bits 26 -#define LDSTidxI_code_mask 0x3f - -static void decode_LDSTidxI_0(unsigned int opcode) -{ - int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask); - int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask); - int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask); - int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask); - int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask); - int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); - - if (W == 0) - pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg); - - if (sz == 1) - pr_cont("W"); - if (sz == 2) - pr_cont("B"); - - pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "", - (offset & 0x1f) << 2); - - if (W == 0 && sz != 0) { - if (Z) - pr_cont("(X)"); - else - pr_cont("(Z)"); - } - - if (W == 1) - pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg); - -} - -static void decode_opcode(unsigned int opcode) -{ -#ifdef CONFIG_BUG - if (opcode == BFIN_BUG_OPCODE) - pr_cont("BUG"); - else -#endif - if ((opcode & 0xffffff00) == ProgCtrl_opcode) - decode_ProgCtrl_0(opcode); - else if ((opcode & 0xfffff000) == BRCC_opcode) - decode_BRCC_0(opcode); - else if ((opcode & 0xfffff000) == 0x2000) - pr_cont("JUMP.S"); - else if ((opcode & 0xfe000000) == CALLa_opcode) - decode_CALLa_0(opcode); - else if ((opcode & 0xff8000C0) == LoopSetup_opcode) - decode_LoopSetup_0(opcode); - else if ((opcode & 0xfffffc00) == DspLDST_opcode) - decode_dspLDST_0(opcode); - else if ((opcode & 0xfffff000) == LDST_opcode) - decode_LDST_0(opcode); - else if ((opcode & 0xffffe000) == LDSTii_opcode) - decode_LDSTii_0(opcode); - else if ((opcode & 0xfc000000) == LDSTidxI_opcode) - decode_LDSTidxI_0(opcode); - else if (opcode & 0xffff0000) - pr_cont("0x%08x", opcode); - else - pr_cont("0x%04x", opcode); -} - -#define BIT_MULTI_INS 0x08000000 -static void decode_instruction(unsigned short *address) -{ - unsigned int opcode; - - if (!get_instruction(&opcode, address)) - return; - - decode_opcode(opcode); - - /* If things are a 32-bit instruction, it has the possibility of being - * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions) - * This test collidates with the unlink instruction, so disallow that - */ - if ((opcode & 0xc0000000) == 0xc0000000 && - (opcode & BIT_MULTI_INS) && - (opcode & 0xe8000000) != 0xe8000000) { - pr_cont(" || "); - if (!get_instruction(&opcode, address + 2)) - return; - decode_opcode(opcode); - pr_cont(" || "); - if (!get_instruction(&opcode, address + 3)) - return; - decode_opcode(opcode); - } -} -#endif - -void dump_bfin_trace_buffer(void) -{ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - int tflags, i = 0, fault = 0; - char buf[150]; - unsigned short *addr; - unsigned int cpu = raw_smp_processor_id(); -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - int j, index; -#endif - - trace_buffer_save(tflags); - - pr_notice("Hardware Trace:\n"); - -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n"); -#endif - - if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) { - for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) { - addr = (unsigned short *)bfin_read_TBUF(); - decode_address(buf, (unsigned long)addr); - pr_notice("%4i Target : %s\n", i, buf); - /* Normally, the faulting instruction doesn't go into - * the trace buffer, (since it doesn't commit), so - * we print out the fault address here - */ - if (!fault && addr == ((unsigned short *)evt_ivhw)) { - addr = (unsigned short *)bfin_read_TBUF(); - decode_address(buf, (unsigned long)addr); - pr_notice(" FAULT : %s ", buf); - decode_instruction(addr); - pr_cont("\n"); - fault = 1; - continue; - } - if (!fault && addr == (unsigned short *)trap && - (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) { - decode_address(buf, cpu_pda[cpu].icplb_fault_addr); - pr_notice(" FAULT : %s ", buf); - decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr); - pr_cont("\n"); - fault = 1; - } - addr = (unsigned short *)bfin_read_TBUF(); - decode_address(buf, (unsigned long)addr); - pr_notice(" Source : %s ", buf); - decode_instruction(addr); - pr_cont("\n"); - } - } - -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - if (trace_buff_offset) - index = trace_buff_offset / 4; - else - index = EXPAND_LEN; - - j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128; - while (j) { - decode_address(buf, software_trace_buff[index]); - pr_notice("%4i Target : %s\n", i, buf); - index -= 1; - if (index < 0) - index = EXPAND_LEN; - decode_address(buf, software_trace_buff[index]); - pr_notice(" Source : %s ", buf); - decode_instruction((unsigned short *)software_trace_buff[index]); - pr_cont("\n"); - index -= 1; - if (index < 0) - index = EXPAND_LEN; - j--; - i++; - } -#endif - - trace_buffer_restore(tflags); -#endif -} -EXPORT_SYMBOL(dump_bfin_trace_buffer); - -void dump_bfin_process(struct pt_regs *fp) -{ - /* We should be able to look at fp->ipend, but we don't push it on the - * stack all the time, so do this until we fix that */ - unsigned int context = bfin_read_IPEND(); - - if (oops_in_progress) - pr_emerg("Kernel OOPS in progress\n"); - - if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) - pr_notice("HW Error context\n"); - else if (context & 0x0020) - pr_notice("Deferred Exception context\n"); - else if (context & 0x3FC0) - pr_notice("Interrupt context\n"); - else if (context & 0x4000) - pr_notice("Deferred Interrupt context\n"); - else if (context & 0x8000) - pr_notice("Kernel process context\n"); - - /* Because we are crashing, and pointers could be bad, we check things - * pretty closely before we use them - */ - if ((unsigned long)current >= FIXED_CODE_START && - !((unsigned long)current & 0x3) && current->pid) { - pr_notice("CURRENT PROCESS:\n"); - if (current->comm >= (char *)FIXED_CODE_START) - pr_notice("COMM=%s PID=%d", - current->comm, current->pid); - else - pr_notice("COMM= invalid"); - - pr_cont(" CPU=%d\n", current_thread_info()->cpu); - if (!((unsigned long)current->mm & 0x3) && - (unsigned long)current->mm >= FIXED_CODE_START) { - pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n", - (void *)current->mm->start_code, - (void *)current->mm->end_code, - (void *)current->mm->start_data, - (void *)current->mm->end_data); - pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n", - (void *)current->mm->end_data, - (void *)current->mm->brk, - (void *)current->mm->start_stack); - } else - pr_notice("invalid mm\n"); - } else - pr_notice("No Valid process in current context\n"); -} - -void dump_bfin_mem(struct pt_regs *fp) -{ - unsigned short *addr, *erraddr, val = 0, err = 0; - char sti = 0, buf[6]; - - erraddr = (void *)fp->pc; - - pr_notice("return address: [0x%p]; contents of:", erraddr); - - for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10; - addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10; - addr++) { - if (!((unsigned long)addr & 0xF)) - pr_notice("0x%p: ", addr); - - if (!get_mem16(&val, addr)) { - val = 0; - sprintf(buf, "????"); - } else - sprintf(buf, "%04x", val); - - if (addr == erraddr) { - pr_cont("[%s]", buf); - err = val; - } else - pr_cont(" %s ", buf); - - /* Do any previous instructions turn on interrupts? */ - if (addr <= erraddr && /* in the past */ - ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */ - val == 0x017b)) /* [SP++] = RETI */ - sti = 1; - } - - pr_cont("\n"); - - /* Hardware error interrupts can be deferred */ - if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR && - oops_in_progress)){ - pr_notice("Looks like this was a deferred error - sorry\n"); -#ifndef CONFIG_DEBUG_HWERR - pr_notice("The remaining message may be meaningless\n"); - pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n"); -#else - /* If we are handling only one peripheral interrupt - * and current mm and pid are valid, and the last error - * was in that user space process's text area - * print it out - because that is where the problem exists - */ - if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) && - (current->pid && current->mm)) { - /* And the last RETI points to the current userspace context */ - if ((fp + 1)->pc >= current->mm->start_code && - (fp + 1)->pc <= current->mm->end_code) { - pr_notice("It might be better to look around here :\n"); - pr_notice("-------------------------------------------\n"); - show_regs(fp + 1); - pr_notice("-------------------------------------------\n"); - } - } -#endif - } -} - -void show_regs(struct pt_regs *fp) -{ - char buf[150]; - struct irqaction *action; - unsigned int i; - unsigned long flags = 0; - unsigned int cpu = raw_smp_processor_id(); - unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); - - pr_notice("\n"); - show_regs_print_info(KERN_NOTICE); - - if (CPUID != bfin_cpuid()) - pr_notice("Compiled for cpu family 0x%04x (Rev %d), " - "but running on:0x%04x (Rev %d)\n", - CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid()); - - pr_notice("ADSP-%s-0.%d", - CPU, bfin_compiled_revid()); - - if (bfin_compiled_revid() != bfin_revid()) - pr_cont("(Detected 0.%d)", bfin_revid()); - - pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n", - get_cclk()/1000000, get_sclk()/1000000, -#ifdef CONFIG_MPU - "mpu on" -#else - "mpu off" -#endif - ); - - pr_notice("%s", linux_banner); - - pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted()); - pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n", - (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg); - if (fp->ipend & EVT_IRPTEN) - pr_notice(" Global Interrupts Disabled (IPEND[4])\n"); - if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 | - EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR))) - pr_notice(" Peripheral interrupts masked off\n"); - if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14))) - pr_notice(" Kernel interrupts masked off\n"); - if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) { - pr_notice(" HWERRCAUSE: 0x%lx\n", - (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14); -#ifdef EBIU_ERRMST - /* If the error was from the EBIU, print it out */ - if (bfin_read_EBIU_ERRMST() & CORE_ERROR) { - pr_notice(" EBIU Error Reason : 0x%04x\n", - bfin_read_EBIU_ERRMST()); - pr_notice(" EBIU Error Address : 0x%08x\n", - bfin_read_EBIU_ERRADD()); - } -#endif - } - pr_notice(" EXCAUSE : 0x%lx\n", - fp->seqstat & SEQSTAT_EXCAUSE); - for (i = 2; i <= 15 ; i++) { - if (fp->ipend & (1 << i)) { - if (i != 4) { - decode_address(buf, bfin_read32(EVT0 + 4*i)); - pr_notice(" physical IVG%i asserted : %s\n", i, buf); - } else - pr_notice(" interrupts disabled\n"); - } - } - - /* if no interrupts are going off, don't print this out */ - if (fp->ipend & ~0x3F) { - for (i = 0; i < (NR_IRQS - 1); i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!in_atomic) - raw_spin_lock_irqsave(&desc->lock, flags); - - action = desc->action; - if (!action) - goto unlock; - - decode_address(buf, (unsigned int)action->handler); - pr_notice(" logical irq %3d mapped : %s", i, buf); - for (action = action->next; action; action = action->next) { - decode_address(buf, (unsigned int)action->handler); - pr_cont(", %s", buf); - } - pr_cont("\n"); -unlock: - if (!in_atomic) - raw_spin_unlock_irqrestore(&desc->lock, flags); - } - } - - decode_address(buf, fp->rete); - pr_notice(" RETE: %s\n", buf); - decode_address(buf, fp->retn); - pr_notice(" RETN: %s\n", buf); - decode_address(buf, fp->retx); - pr_notice(" RETX: %s\n", buf); - decode_address(buf, fp->rets); - pr_notice(" RETS: %s\n", buf); - decode_address(buf, fp->pc); - pr_notice(" PC : %s\n", buf); - - if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && - (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { - decode_address(buf, cpu_pda[cpu].dcplb_fault_addr); - pr_notice("DCPLB_FAULT_ADDR: %s\n", buf); - decode_address(buf, cpu_pda[cpu].icplb_fault_addr); - pr_notice("ICPLB_FAULT_ADDR: %s\n", buf); - } - - pr_notice("PROCESSOR STATE:\n"); - pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", - fp->r0, fp->r1, fp->r2, fp->r3); - pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n", - fp->r4, fp->r5, fp->r6, fp->r7); - pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", - fp->p0, fp->p1, fp->p2, fp->p3); - pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", - fp->p4, fp->p5, fp->fp, (long)fp); - pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n", - fp->lb0, fp->lt0, fp->lc0); - pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n", - fp->lb1, fp->lt1, fp->lc1); - pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n", - fp->b0, fp->l0, fp->m0, fp->i0); - pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n", - fp->b1, fp->l1, fp->m1, fp->i1); - pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n", - fp->b2, fp->l2, fp->m2, fp->i2); - pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", - fp->b3, fp->l3, fp->m3, fp->i3); - pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", - fp->a0w, fp->a0x, fp->a1w, fp->a1x); - - pr_notice("USP : %08lx ASTAT: %08lx\n", - rdusp(), fp->astat); - - pr_notice("\n"); -} diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c deleted file mode 100644 index a323a40a46e9..000000000000 --- a/arch/blackfin/kernel/traps.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Main exception handling logic. - * - * Copyright 2004-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_KGDB -# include - -# define CHK_DEBUGGER_TRAP() \ - do { \ - kgdb_handle_exception(trapnr, sig, info.si_code, fp); \ - } while (0) -# define CHK_DEBUGGER_TRAP_MAYBE() \ - do { \ - if (kgdb_connected) \ - CHK_DEBUGGER_TRAP(); \ - } while (0) -#else -# define CHK_DEBUGGER_TRAP() do { } while (0) -# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0) -#endif - - -#ifdef CONFIG_DEBUG_VERBOSE -#define verbose_printk(fmt, arg...) \ - printk(fmt, ##arg) -#else -#define verbose_printk(fmt, arg...) \ - ({ if (0) printk(fmt, ##arg); 0; }) -#endif - -#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE) -u32 last_seqstat; -#ifdef CONFIG_DEBUG_MMRS_MODULE -EXPORT_SYMBOL(last_seqstat); -#endif -#endif - -/* Initiate the event table handler */ -void __init trap_init(void) -{ - CSYNC(); - bfin_write_EVT3(trap); - CSYNC(); -} - -static int kernel_mode_regs(struct pt_regs *regs) -{ - return regs->ipend & 0xffc0; -} - -asmlinkage notrace void trap_c(struct pt_regs *fp) -{ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - int j; -#endif -#ifdef CONFIG_BFIN_PSEUDODBG_INSNS - int opcode; -#endif - unsigned int cpu = raw_smp_processor_id(); - const char *strerror = NULL; - int sig = 0; - siginfo_t info; - unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE; - - trace_buffer_save(j); -#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE) - last_seqstat = (u32)fp->seqstat; -#endif - - /* Important - be very careful dereferncing pointers - will lead to - * double faults if the stack has become corrupt - */ - - /* trap_c() will be called for exceptions. During exceptions - * processing, the pc value should be set with retx value. - * With this change we can cleanup some code in signal.c- TODO - */ - fp->orig_pc = fp->retx; - /* printk("exception: 0x%x, ipend=%x, reti=%x, retx=%x\n", - trapnr, fp->ipend, fp->pc, fp->retx); */ - - /* send the appropriate signal to the user program */ - switch (trapnr) { - - /* This table works in conjunction with the one in ./mach-common/entry.S - * Some exceptions are handled there (in assembly, in exception space) - * Some are handled here, (in C, in interrupt space) - * Some, like CPLB, are handled in both, where the normal path is - * handled in assembly/exception space, and the error path is handled - * here - */ - - /* 0x00 - Linux Syscall, getting here is an error */ - /* 0x01 - userspace gdb breakpoint, handled here */ - case VEC_EXCPT01: - info.si_code = TRAP_ILLTRAP; - sig = SIGTRAP; - CHK_DEBUGGER_TRAP_MAYBE(); - /* Check if this is a breakpoint in kernel space */ - if (kernel_mode_regs(fp)) - goto traps_done; - else - break; - /* 0x03 - User Defined, userspace stack overflow */ - case VEC_EXCPT03: - info.si_code = SEGV_STACKFLOW; - sig = SIGSEGV; - strerror = KERN_NOTICE EXC_0x03(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x02 - KGDB initial connection and break signal trap */ - case VEC_EXCPT02: -#ifdef CONFIG_KGDB - info.si_code = TRAP_ILLTRAP; - sig = SIGTRAP; - CHK_DEBUGGER_TRAP(); - goto traps_done; -#endif - /* 0x04 - User Defined */ - /* 0x05 - User Defined */ - /* 0x06 - User Defined */ - /* 0x07 - User Defined */ - /* 0x08 - User Defined */ - /* 0x09 - User Defined */ - /* 0x0A - User Defined */ - /* 0x0B - User Defined */ - /* 0x0C - User Defined */ - /* 0x0D - User Defined */ - /* 0x0E - User Defined */ - /* 0x0F - User Defined */ - /* If we got here, it is most likely that someone was trying to use a - * custom exception handler, and it is not actually installed properly - */ - case VEC_EXCPT04 ... VEC_EXCPT15: - info.si_code = ILL_ILLPARAOP; - sig = SIGILL; - strerror = KERN_NOTICE EXC_0x04(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x10 HW Single step, handled here */ - case VEC_STEP: - info.si_code = TRAP_STEP; - sig = SIGTRAP; - CHK_DEBUGGER_TRAP_MAYBE(); - /* Check if this is a single step in kernel space */ - if (kernel_mode_regs(fp)) - goto traps_done; - else - break; - /* 0x11 - Trace Buffer Full, handled here */ - case VEC_OVFLOW: - info.si_code = TRAP_TRACEFLOW; - sig = SIGTRAP; - strerror = KERN_NOTICE EXC_0x11(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x12 - Reserved, Caught by default */ - /* 0x13 - Reserved, Caught by default */ - /* 0x14 - Reserved, Caught by default */ - /* 0x15 - Reserved, Caught by default */ - /* 0x16 - Reserved, Caught by default */ - /* 0x17 - Reserved, Caught by default */ - /* 0x18 - Reserved, Caught by default */ - /* 0x19 - Reserved, Caught by default */ - /* 0x1A - Reserved, Caught by default */ - /* 0x1B - Reserved, Caught by default */ - /* 0x1C - Reserved, Caught by default */ - /* 0x1D - Reserved, Caught by default */ - /* 0x1E - Reserved, Caught by default */ - /* 0x1F - Reserved, Caught by default */ - /* 0x20 - Reserved, Caught by default */ - /* 0x21 - Undefined Instruction, handled here */ - case VEC_UNDEF_I: -#ifdef CONFIG_BUG - if (kernel_mode_regs(fp)) { - switch (report_bug(fp->pc, fp)) { - case BUG_TRAP_TYPE_NONE: - break; - case BUG_TRAP_TYPE_WARN: - dump_bfin_trace_buffer(); - fp->pc += 2; - goto traps_done; - case BUG_TRAP_TYPE_BUG: - /* call to panic() will dump trace, and it is - * off at this point, so it won't be clobbered - */ - panic("BUG()"); - } - } -#endif -#ifdef CONFIG_BFIN_PSEUDODBG_INSNS - /* - * Support for the fake instructions, if the instruction fails, - * then just execute a illegal opcode failure (like normal). - * Don't support these instructions inside the kernel - */ - if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) { - if (execute_pseudodbg_assert(fp, opcode)) - goto traps_done; - if (execute_pseudodbg(fp, opcode)) - goto traps_done; - } -#endif - info.si_code = ILL_ILLOPC; - sig = SIGILL; - strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x22 - Illegal Instruction Combination, handled here */ - case VEC_ILGAL_I: - info.si_code = ILL_ILLPARAOP; - sig = SIGILL; - strerror = KERN_NOTICE EXC_0x22(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x23 - Data CPLB protection violation, handled here */ - case VEC_CPLB_VL: - info.si_code = ILL_CPLB_VI; - sig = SIGSEGV; - strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x24 - Data access misaligned, handled here */ - case VEC_MISALI_D: - info.si_code = BUS_ADRALN; - sig = SIGBUS; - strerror = KERN_NOTICE EXC_0x24(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x25 - Unrecoverable Event, handled here */ - case VEC_UNCOV: - info.si_code = ILL_ILLEXCPT; - sig = SIGILL; - strerror = KERN_NOTICE EXC_0x25(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr, - error case is handled here */ - case VEC_CPLB_M: - info.si_code = BUS_ADRALN; - sig = SIGBUS; - strerror = KERN_NOTICE EXC_0x26(KERN_NOTICE); - break; - /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */ - case VEC_CPLB_MHIT: - info.si_code = ILL_CPLB_MULHIT; - sig = SIGSEGV; -#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO - if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START) - strerror = KERN_NOTICE "NULL pointer access\n"; - else -#endif - strerror = KERN_NOTICE EXC_0x27(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x28 - Emulation Watchpoint, handled here */ - case VEC_WATCH: - info.si_code = TRAP_WATCHPT; - sig = SIGTRAP; - pr_debug(EXC_0x28(KERN_DEBUG)); - CHK_DEBUGGER_TRAP_MAYBE(); - /* Check if this is a watchpoint in kernel space */ - if (kernel_mode_regs(fp)) - goto traps_done; - else - break; -#ifdef CONFIG_BF535 - /* 0x29 - Instruction fetch access error (535 only) */ - case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */ - info.si_code = BUS_OPFETCH; - sig = SIGBUS; - strerror = KERN_NOTICE "BF535: VEC_ISTRU_VL\n"; - CHK_DEBUGGER_TRAP_MAYBE(); - break; -#else - /* 0x29 - Reserved, Caught by default */ -#endif - /* 0x2A - Instruction fetch misaligned, handled here */ - case VEC_MISALI_I: - info.si_code = BUS_ADRALN; - sig = SIGBUS; - strerror = KERN_NOTICE EXC_0x2A(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x2B - Instruction CPLB protection violation, handled here */ - case VEC_CPLB_I_VL: - info.si_code = ILL_CPLB_VI; - sig = SIGBUS; - strerror = KERN_NOTICE EXC_0x2B(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */ - case VEC_CPLB_I_M: - info.si_code = ILL_CPLB_MISS; - sig = SIGBUS; - strerror = KERN_NOTICE EXC_0x2C(KERN_NOTICE); - break; - /* 0x2D - Instruction CPLB Multiple Hits, handled here */ - case VEC_CPLB_I_MHIT: - info.si_code = ILL_CPLB_MULHIT; - sig = SIGSEGV; -#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO - if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START) - strerror = KERN_NOTICE "Jump to NULL address\n"; - else -#endif - strerror = KERN_NOTICE EXC_0x2D(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x2E - Illegal use of Supervisor Resource, handled here */ - case VEC_ILL_RES: - info.si_code = ILL_PRVOPC; - sig = SIGILL; - strerror = KERN_NOTICE EXC_0x2E(KERN_NOTICE); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* 0x2F - Reserved, Caught by default */ - /* 0x30 - Reserved, Caught by default */ - /* 0x31 - Reserved, Caught by default */ - /* 0x32 - Reserved, Caught by default */ - /* 0x33 - Reserved, Caught by default */ - /* 0x34 - Reserved, Caught by default */ - /* 0x35 - Reserved, Caught by default */ - /* 0x36 - Reserved, Caught by default */ - /* 0x37 - Reserved, Caught by default */ - /* 0x38 - Reserved, Caught by default */ - /* 0x39 - Reserved, Caught by default */ - /* 0x3A - Reserved, Caught by default */ - /* 0x3B - Reserved, Caught by default */ - /* 0x3C - Reserved, Caught by default */ - /* 0x3D - Reserved, Caught by default */ - /* 0x3E - Reserved, Caught by default */ - /* 0x3F - Reserved, Caught by default */ - case VEC_HWERR: - info.si_code = BUS_ADRALN; - sig = SIGBUS; - switch (fp->seqstat & SEQSTAT_HWERRCAUSE) { - /* System MMR Error */ - case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): - info.si_code = BUS_ADRALN; - sig = SIGBUS; - strerror = KERN_NOTICE HWC_x2(KERN_NOTICE); - break; - /* External Memory Addressing Error */ - case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): - if (ANOMALY_05000310) { - static unsigned long anomaly_rets; - - if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) && - (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) { - /* - * A false hardware error will happen while fetching at - * the L1 instruction SRAM boundary. Ignore it. - */ - anomaly_rets = fp->rets; - goto traps_done; - } else if (fp->rets == anomaly_rets) { - /* - * While boundary code returns to a function, at the ret - * point, a new false hardware error might occur too based - * on tests. Ignore it too. - */ - goto traps_done; - } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) && - (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) { - /* - * If boundary code calls a function, at the entry point, - * a new false hardware error maybe happen based on tests. - * Ignore it too. - */ - goto traps_done; - } else - anomaly_rets = 0; - } - - info.si_code = BUS_ADRERR; - sig = SIGBUS; - strerror = KERN_NOTICE HWC_x3(KERN_NOTICE); - break; - /* Performance Monitor Overflow */ - case (SEQSTAT_HWERRCAUSE_PERF_FLOW): - strerror = KERN_NOTICE HWC_x12(KERN_NOTICE); - break; - /* RAISE 5 instruction */ - case (SEQSTAT_HWERRCAUSE_RAISE_5): - printk(KERN_NOTICE HWC_x18(KERN_NOTICE)); - break; - default: /* Reserved */ - printk(KERN_NOTICE HWC_default(KERN_NOTICE)); - break; - } - CHK_DEBUGGER_TRAP_MAYBE(); - break; - /* - * We should be handling all known exception types above, - * if we get here we hit a reserved one, so panic - */ - default: - info.si_code = ILL_ILLPARAOP; - sig = SIGILL; - verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n", - (fp->seqstat & SEQSTAT_EXCAUSE)); - CHK_DEBUGGER_TRAP_MAYBE(); - break; - } - - BUG_ON(sig == 0); - - /* If the fault was caused by a kernel thread, or interrupt handler - * we will kernel panic, so the system reboots. - */ - if (kernel_mode_regs(fp) || (current && !current->mm)) { - console_verbose(); - oops_in_progress = 1; - } - - if (sig != SIGTRAP) { - if (strerror) - verbose_printk(strerror); - - dump_bfin_process(fp); - dump_bfin_mem(fp); - show_regs(fp); - - /* Print out the trace buffer if it makes sense */ -#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE - if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M) - verbose_printk(KERN_NOTICE "No trace since you do not have " - "CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n\n"); - else -#endif - dump_bfin_trace_buffer(); - - if (oops_in_progress) { - /* Dump the current kernel stack */ - verbose_printk(KERN_NOTICE "Kernel Stack\n"); - show_stack(current, NULL); - print_modules(); -#ifndef CONFIG_ACCESS_CHECK - verbose_printk(KERN_EMERG "Please turn on " - "CONFIG_ACCESS_CHECK\n"); -#endif - panic("Kernel exception"); - } else { -#ifdef CONFIG_DEBUG_VERBOSE - unsigned long *stack; - /* Dump the user space stack */ - stack = (unsigned long *)rdusp(); - verbose_printk(KERN_NOTICE "Userspace Stack\n"); - show_stack(NULL, stack); -#endif - } - } - -#ifdef CONFIG_IPIPE - if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp)) -#endif - { - info.si_signo = sig; - info.si_errno = 0; - switch (trapnr) { - case VEC_CPLB_VL: - case VEC_MISALI_D: - case VEC_CPLB_M: - case VEC_CPLB_MHIT: - info.si_addr = (void __user *)cpu_pda[cpu].dcplb_fault_addr; - break; - default: - info.si_addr = (void __user *)fp->pc; - break; - } - force_sig_info(sig, &info, current); - } - - if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) || - (ANOMALY_05000281 && trapnr == VEC_HWERR) || - (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL))) - fp->pc = SAFE_USER_INSTRUCTION; - - traps_done: - trace_buffer_restore(j); -} - -asmlinkage void double_fault_c(struct pt_regs *fp) -{ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON - int j; - trace_buffer_save(j); -#endif - - console_verbose(); - oops_in_progress = 1; -#ifdef CONFIG_DEBUG_VERBOSE - printk(KERN_EMERG "Double Fault\n"); -#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT - if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) { - unsigned int cpu = raw_smp_processor_id(); - char buf[150]; - decode_address(buf, cpu_pda[cpu].retx_doublefault); - printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n", - (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf); - decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr); - printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf); - decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr); - printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf); - - decode_address(buf, fp->retx); - printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf); - } else -#endif - { - dump_bfin_process(fp); - dump_bfin_mem(fp); - show_regs(fp); - dump_bfin_trace_buffer(); - } -#endif - panic("Double Fault - unrecoverable event"); - -} - - -void panic_cplb_error(int cplb_panic, struct pt_regs *fp) -{ - switch (cplb_panic) { - case CPLB_NO_UNLOCKED: - printk(KERN_EMERG "All CPLBs are locked\n"); - break; - case CPLB_PROT_VIOL: - return; - case CPLB_NO_ADDR_MATCH: - return; - case CPLB_UNKNOWN_ERR: - printk(KERN_EMERG "Unknown CPLB Exception\n"); - break; - } - - oops_in_progress = 1; - - dump_bfin_process(fp); - dump_bfin_mem(fp); - show_regs(fp); - dump_stack(); - panic("Unrecoverable event"); -} - -#ifdef CONFIG_BUG -int is_valid_bugaddr(unsigned long addr) -{ - unsigned int opcode; - - if (!get_instruction(&opcode, (unsigned short *)addr)) - return 0; - - return opcode == BFIN_BUG_OPCODE; -} -#endif - -/* stub this out */ -#ifndef CONFIG_DEBUG_VERBOSE -void show_regs(struct pt_regs *fp) -{ - -} -#endif diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S deleted file mode 100644 index 334ef8139b35..000000000000 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include -#include -#include -#include - -OUTPUT_FORMAT("elf32-bfin") -ENTRY(__start) -_jiffies = _jiffies_64; - -SECTIONS -{ -#ifdef CONFIG_RAMKERNEL - . = CONFIG_BOOT_LOAD; -#else - . = CONFIG_ROM_BASE; -#endif - - /* Neither the text, ro_data or bss section need to be aligned - * So pack them back to back - */ - .text : - { - __text = .; - _text = .; - __stext = .; - TEXT_TEXT -#ifndef CONFIG_SCHEDULE_L1 - SCHED_TEXT -#endif - CPUIDLE_TEXT - LOCK_TEXT - IRQENTRY_TEXT - SOFTIRQENTRY_TEXT - KPROBES_TEXT -#ifdef CONFIG_ROMKERNEL - __sinittext = .; - INIT_TEXT - __einittext = .; - EXIT_TEXT -#endif - *(.text.*) - *(.fixup) - -#if !L1_CODE_LENGTH - *(.l1.text) -#endif - __etext = .; - } - - EXCEPTION_TABLE(4) - NOTES - - /* Just in case the first read only is a 32-bit access */ - RO_DATA(4) - __rodata_end = .; - -#ifdef CONFIG_ROMKERNEL - . = CONFIG_BOOT_LOAD; - .bss : AT(__rodata_end) -#else - .bss : -#endif - { - . = ALIGN(4); - ___bss_start = .; - *(.bss .bss.*) - *(COMMON) -#if !L1_DATA_A_LENGTH - *(.l1.bss) -#endif -#if !L1_DATA_B_LENGTH - *(.l1.bss.B) -#endif - . = ALIGN(4); - ___bss_stop = .; - } - -#if defined(CONFIG_ROMKERNEL) - .data : AT(LOADADDR(.bss) + SIZEOF(.bss)) -#else - .data : -#endif - { - __sdata = .; - /* This gets done first, so the glob doesn't suck it in */ - CACHELINE_ALIGNED_DATA(32) - -#if !L1_DATA_A_LENGTH - . = ALIGN(32); - *(.data_l1.cacheline_aligned) - *(.l1.data) -#endif -#if !L1_DATA_B_LENGTH - *(.l1.data.B) -#endif -#if !L2_LENGTH - . = ALIGN(32); - *(.data_l2.cacheline_aligned) - *(.l2.data) -#endif - - DATA_DATA - CONSTRUCTORS - - INIT_TASK_DATA(THREAD_SIZE) - - __edata = .; - } - __data_lma = LOADADDR(.data); - __data_len = SIZEOF(.data); - - BUG_TABLE - - /* The init section should be last, so when we free it, it goes into - * the general memory pool, and (hopefully) will decrease fragmentation - * a tiny bit. The init section has a _requirement_ that it be - * PAGE_SIZE aligned - */ - . = ALIGN(PAGE_SIZE); - ___init_begin = .; - -#ifdef CONFIG_RAMKERNEL - INIT_TEXT_SECTION(PAGE_SIZE) - - /* We have to discard exit text and such at runtime, not link time, to - * handle embedded cross-section references (alt instructions, bug - * table, eh_frame, etc...). We need all of our .text up front and - * .data after it for PCREL call issues. - */ - .exit.text : - { - EXIT_TEXT - } - - . = ALIGN(16); - INIT_DATA_SECTION(16) - PERCPU_SECTION(32) - - .exit.data : - { - EXIT_DATA - } - - .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data)) -#else - .init.data : AT(__data_lma + __data_len + 32) - { - __sinitdata = .; - INIT_DATA - INIT_SETUP(16) - INIT_CALLS - CON_INITCALL - SECURITY_INITCALL - INIT_RAM_FS - - . = ALIGN(PAGE_SIZE); - ___per_cpu_load = .; - PERCPU_INPUT(32) - - EXIT_DATA - __einitdata = .; - } - __init_data_lma = LOADADDR(.init.data); - __init_data_len = SIZEOF(.init.data); - __init_data_end = .; - - .text_l1 L1_CODE_START : AT(__init_data_lma + __init_data_len) -#endif - { - . = ALIGN(4); - __stext_l1 = .; - *(.l1.text.head) - *(.l1.text) -#ifdef CONFIG_SCHEDULE_L1 - SCHED_TEXT -#endif - . = ALIGN(4); - __etext_l1 = .; - } - __text_l1_lma = LOADADDR(.text_l1); - __text_l1_len = SIZEOF(.text_l1); - ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!") - - .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len) - { - . = ALIGN(4); - __sdata_l1 = .; - *(.l1.data) - __edata_l1 = .; - - . = ALIGN(32); - *(.data_l1.cacheline_aligned) - - . = ALIGN(4); - __sbss_l1 = .; - *(.l1.bss) - . = ALIGN(4); - __ebss_l1 = .; - } - __data_l1_lma = LOADADDR(.data_l1); - __data_l1_len = SIZEOF(.data_l1); - ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!") - - .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len) - { - . = ALIGN(4); - __sdata_b_l1 = .; - *(.l1.data.B) - __edata_b_l1 = .; - - . = ALIGN(4); - __sbss_b_l1 = .; - *(.l1.bss.B) - . = ALIGN(4); - __ebss_b_l1 = .; - } - __data_b_l1_lma = LOADADDR(.data_b_l1); - __data_b_l1_len = SIZEOF(.data_b_l1); - ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!") - - .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len) - { - . = ALIGN(4); - __stext_l2 = .; - *(.l2.text) - . = ALIGN(4); - __etext_l2 = .; - - . = ALIGN(4); - __sdata_l2 = .; - *(.l2.data) - __edata_l2 = .; - - . = ALIGN(32); - *(.data_l2.cacheline_aligned) - - . = ALIGN(4); - __sbss_l2 = .; - *(.l2.bss) - . = ALIGN(4); - __ebss_l2 = .; - } - __l2_lma = LOADADDR(.text_data_l2); - __l2_len = SIZEOF(.text_data_l2); - ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!") - - /* Force trailing alignment of our init section so that when we - * free our init memory, we don't leave behind a partial page. - */ -#ifdef CONFIG_RAMKERNEL - . = __l2_lma + __l2_len; -#else - . = __init_data_end; -#endif - . = ALIGN(PAGE_SIZE); - ___init_end = .; - - __end =.; - - STABS_DEBUG - - DWARF_DEBUG - - DISCARDS -} diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile deleted file mode 100644 index 74ddde0eb2e7..000000000000 --- a/arch/blackfin/lib/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/lib/Makefile -# - -lib-y := \ - ashldi3.o ashrdi3.o lshrdi3.o \ - muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \ - memcpy.o memset.o memcmp.o memchr.o memmove.o \ - strcmp.o strcpy.o strncmp.o strncpy.o \ - umulsi3_highpart.o smulsi3_highpart.o \ - ins.o outs.o diff --git a/arch/blackfin/lib/ashldi3.c b/arch/blackfin/lib/ashldi3.c deleted file mode 100644 index ab69d8768afc..000000000000 --- a/arch/blackfin/lib/ashldi3.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include "gcclib.h" - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -DItype __ashldi3(DItype u, word_type b)__attribute__((l1_text)); -#endif - -DItype __ashldi3(DItype u, word_type b) -{ - DIunion w; - word_type bm; - DIunion uu; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof(SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) { - w.s.low = 0; - w.s.high = (USItype) uu.s.low << -bm; - } else { - USItype carries = (USItype) uu.s.low >> bm; - w.s.low = (USItype) uu.s.low << b; - w.s.high = ((USItype) uu.s.high << b) | carries; - } - - return w.ll; -} diff --git a/arch/blackfin/lib/ashrdi3.c b/arch/blackfin/lib/ashrdi3.c deleted file mode 100644 index b5b351e82e10..000000000000 --- a/arch/blackfin/lib/ashrdi3.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include "gcclib.h" - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text)); -#endif - -DItype __ashrdi3(DItype u, word_type b) -{ - DIunion w; - word_type bm; - DIunion uu; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof(SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) { - /* w.s.high = 1..1 or 0..0 */ - w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1); - w.s.low = uu.s.high >> -bm; - } else { - USItype carries = (USItype) uu.s.high << bm; - w.s.high = uu.s.high >> b; - w.s.low = ((USItype) uu.s.low >> b) | carries; - } - - return w.ll; -} diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S deleted file mode 100644 index ef2cd99efb89..000000000000 --- a/arch/blackfin/lib/divsi3.S +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - * - * 16 / 32 bit signed division. - * Special cases : - * 1) If(numerator == 0) - * return 0 - * 2) If(denominator ==0) - * return positive max = 0x7fffffff - * 3) If(numerator == denominator) - * return 1 - * 4) If(denominator ==1) - * return numerator - * 5) If(denominator == -1) - * return -numerator - * - * Operand : R0 - Numerator (i) - * R1 - Denominator (i) - * R0 - Quotient (o) - * Registers Used : R2-R7,P0-P2 - * - */ - -.global ___divsi3; -.type ___divsi3, STT_FUNC; - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -.section .l1.text -#else -.text -#endif - -.align 2; -___divsi3 : - - - R3 = R0 ^ R1; - R0 = ABS R0; - - CC = V; - - r3 = rot r3 by -1; - r1 = abs r1; /* now both positive, r3.30 means "negate result", - ** r3.31 means overflow, add one to result - */ - cc = r0 < r1; - if cc jump .Lret_zero; - r2 = r1 >> 15; - cc = r2; - if cc jump .Lidents; - r2 = r1 << 16; - cc = r2 <= r0; - if cc jump .Lidents; - - DIVS(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - DIVQ(R0, R1); - - R0 = R0.L (Z); - r1 = r3 >> 31; /* add overflow issue back in */ - r0 = r0 + r1; - r1 = -r0; - cc = bittst(r3, 30); - if cc r0 = r1; - RTS; - -/* Can't use the primitives. Test common identities. -** If the identity is true, return the value in R2. -*/ - -.Lidents: - CC = R1 == 0; /* check for divide by zero */ - IF CC JUMP .Lident_return; - - CC = R0 == 0; /* check for division of zero */ - IF CC JUMP .Lzero_return; - - CC = R0 == R1; /* check for identical operands */ - IF CC JUMP .Lident_return; - - CC = R1 == 1; /* check for divide by 1 */ - IF CC JUMP .Lident_return; - - R2.L = ONES R1; - R2 = R2.L (Z); - CC = R2 == 1; - IF CC JUMP .Lpower_of_two; - - /* Identities haven't helped either. - ** Perform the full division process. - */ - - P1 = 31; /* Set loop counter */ - - [--SP] = (R7:5); /* Push registers R5-R7 */ - R2 = -R1; - [--SP] = R2; - R2 = R0 << 1; /* R2 lsw of dividend */ - R6 = R0 ^ R1; /* Get sign */ - R5 = R6 >> 31; /* Shift sign to LSB */ - - R0 = 0 ; /* Clear msw partial remainder */ - R2 = R2 | R5; /* Shift quotient bit */ - R6 = R0 ^ R1; /* Get new quotient bit */ - - LSETUP(.Llst,.Llend) LC0 = P1; /* Setup loop */ -.Llst: R7 = R2 >> 31; /* record copy of carry from R2 */ - R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */ - R0 = R0 << 1 || R5 = [SP]; - R0 = R0 | R7; /* and add carry */ - CC = R6 < 0; /* Check quotient(AQ) */ - /* we might be subtracting divisor (AQ==0) */ - IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/ - R0 = R0 + R5; /* do add or subtract, as indicated by AQ */ - R6 = R0 ^ R1; /* Generate next quotient bit */ - R5 = R6 >> 31; - /* Assume AQ==1, shift in zero */ - BITTGL(R5,0); /* tweak AQ to be what we want to shift in */ -.Llend: R2 = R2 + R5; /* and then set shifted-in value to - ** tweaked AQ. - */ - r1 = r3 >> 31; - r2 = r2 + r1; - cc = bittst(r3,30); - r0 = -r2; - if !cc r0 = r2; - SP += 4; - (R7:5)= [SP++]; /* Pop registers R6-R7 */ - RTS; - -.Lident_return: - CC = R1 == 0; /* check for divide by zero => 0x7fffffff */ - R2 = -1 (X); - R2 >>= 1; - IF CC JUMP .Ltrue_ident_return; - - CC = R0 == R1; /* check for identical operands => 1 */ - R2 = 1 (Z); - IF CC JUMP .Ltrue_ident_return; - - R2 = R0; /* assume divide by 1 => numerator */ - /*FALLTHRU*/ - -.Ltrue_ident_return: - R0 = R2; /* Return an identity value */ - R2 = -R2; - CC = bittst(R3,30); - IF CC R0 = R2; -.Lzero_return: - RTS; /* ...including zero */ - -.Lpower_of_two: - /* Y has a single bit set, which means it's a power of two. - ** That means we can perform the division just by shifting - ** X to the right the appropriate number of bits - */ - - /* signbits returns the number of sign bits, minus one. - ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need - ** to shift right n-signbits spaces. It also means 0x80000000 - ** is a special case, because that *also* gives a signbits of 0 - */ - - R2 = R0 >> 31; - CC = R1 < 0; - IF CC JUMP .Ltrue_ident_return; - - R1.l = SIGNBITS R1; - R1 = R1.L (Z); - R1 += -30; - R0 = LSHIFT R0 by R1.L; - r1 = r3 >> 31; - r0 = r0 + r1; - R2 = -R0; // negate result if necessary - CC = bittst(R3,30); - IF CC R0 = R2; - RTS; - -.Lret_zero: - R0 = 0; - RTS; - -.size ___divsi3, .-___divsi3 diff --git a/arch/blackfin/lib/gcclib.h b/arch/blackfin/lib/gcclib.h deleted file mode 100644 index 724f07f14f8d..000000000000 --- a/arch/blackfin/lib/gcclib.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#define BITS_PER_UNIT 8 -#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT) - -typedef unsigned int UQItype __attribute__ ((mode(QI))); -typedef int SItype __attribute__ ((mode(SI))); -typedef unsigned int USItype __attribute__ ((mode(SI))); -typedef int DItype __attribute__ ((mode(DI))); -typedef int word_type __attribute__ ((mode(__word__))); -typedef unsigned int UDItype __attribute__ ((mode(DI))); - -struct DIstruct { - SItype low, high; -}; - -typedef union { - struct DIstruct s; - DItype ll; -} DIunion; diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S deleted file mode 100644 index d59608deccc1..000000000000 --- a/arch/blackfin/lib/ins.S +++ /dev/null @@ -1,118 +0,0 @@ -/* - * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops - * - * Copyright 2004-2008 Analog Devices Inc. - * Copyright (C) 2005 Bas Vermeulen, BuyWays BV - * Licensed under the GPL-2 or later. - */ - -#include -#include - -.align 2 - -#ifdef CONFIG_IPIPE -# define DO_CLI \ - [--sp] = rets; \ - [--sp] = (P5:0); \ - sp += -12; \ - call ___ipipe_disable_root_irqs_hw; \ - sp += 12; \ - (P5:0) = [sp++]; -# define CLI_INNER_NOP -#else -# define DO_CLI cli R3; -# define CLI_INNER_NOP nop; nop; nop; -#endif - -#ifdef CONFIG_IPIPE -# define DO_STI \ - sp += -12; \ - call ___ipipe_enable_root_irqs_hw; \ - sp += 12; \ -2: rets = [sp++]; -#else -# define DO_STI 2: sti R3; -#endif - -#ifdef CONFIG_BFIN_INS_LOWOVERHEAD -# define CLI_OUTER DO_CLI; -# define STI_OUTER DO_STI; -# define CLI_INNER 1: -# if ANOMALY_05000416 -# define STI_INNER nop; 2: nop; -# else -# define STI_INNER 2: -# endif -#else -# define CLI_OUTER -# define STI_OUTER -# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP; -# define STI_INNER DO_STI; -#endif - -/* - * Reads on the Blackfin are speculative. In Blackfin terms, this means they - * can be interrupted at any time (even after they have been issued on to the - * external bus), and re-issued after the interrupt occurs. - * - * If a FIFO is sitting on the end of the read, it will see two reads, - * when the core only sees one. The FIFO receives the read which is cancelled, - * and not delivered to the core. - * - * To solve this, interrupts are turned off before reads occur to I/O space. - * There are 3 versions of all these functions - * - turns interrupts off every read (higher overhead, but lower latency) - * - turns interrupts off every loop (low overhead, but longer latency) - * - DMA version, which do not suffer from this issue. DMA versions have - * different name (prefixed by dma_ ), and are located in - * ../kernel/bfin_dma.c - * Using the dma related functions are recommended for transferring large - * buffers in/out of FIFOs. - */ - -#define COMMON_INS(func, ops) \ -ENTRY(_ins##func) \ - P0 = R0; /* P0 = port */ \ - CLI_OUTER; /* 3 instructions before first read access */ \ - P1 = R1; /* P1 = address */ \ - P2 = R2; /* P2 = count */ \ - SSYNC; \ - \ - LSETUP(1f, 2f) LC0 = P2; \ - CLI_INNER; \ - ops; \ - STI_INNER; \ - \ - STI_OUTER; \ - RTS; \ -ENDPROC(_ins##func) - -COMMON_INS(l, \ - R0 = [P0]; \ - [P1++] = R0; \ -) - -COMMON_INS(w, \ - R0 = W[P0]; \ - W[P1++] = R0; \ -) - -COMMON_INS(w_8, \ - R0 = W[P0]; \ - B[P1++] = R0; \ - R0 = R0 >> 8; \ - B[P1++] = R0; \ -) - -COMMON_INS(b, \ - R0 = B[P0]; \ - B[P1++] = R0; \ -) - -COMMON_INS(l_16, \ - R0 = [P0]; \ - W[P1++] = R0; \ - R0 = R0 >> 16; \ - W[P1++] = R0; \ -) diff --git a/arch/blackfin/lib/lshrdi3.c b/arch/blackfin/lib/lshrdi3.c deleted file mode 100644 index 53f1741047e5..000000000000 --- a/arch/blackfin/lib/lshrdi3.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include "gcclib.h" - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text)); -#endif - -DItype __lshrdi3(DItype u, word_type b) -{ - DIunion w; - word_type bm; - DIunion uu; - - if (b == 0) - return u; - - uu.ll = u; - - bm = (sizeof(SItype) * BITS_PER_UNIT) - b; - if (bm <= 0) { - w.s.high = 0; - w.s.low = (USItype) uu.s.high >> -bm; - } else { - USItype carries = (USItype) uu.s.high << bm; - w.s.high = (USItype) uu.s.high >> b; - w.s.low = ((USItype) uu.s.low >> b) | carries; - } - - return w.ll; -} diff --git a/arch/blackfin/lib/memchr.S b/arch/blackfin/lib/memchr.S deleted file mode 100644 index bcfc8a14c3f2..000000000000 --- a/arch/blackfin/lib/memchr.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -/* void *memchr(const void *s, int c, size_t n); - * R0 = address (s) - * R1 = sought byte (c) - * R2 = count (n) - * - * Returns pointer to located character. - */ - -.text - -.align 2 - -ENTRY(_memchr) - P0 = R0; /* P0 = address */ - P2 = R2; /* P2 = count */ - R1 = R1.B(Z); - CC = R2 == 0; - IF CC JUMP .Lfailed; - -.Lbytes: - LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2; - -.Lbyte_loop_s: - R3 = B[P0++](Z); - CC = R3 == R1; - IF CC JUMP .Lfound; -.Lbyte_loop_e: - NOP; - -.Lfailed: - R0=0; - RTS; - -.Lfound: - R0 = P0; - R0 += -1; - RTS; - -ENDPROC(_memchr) diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S deleted file mode 100644 index 2e1c9477f2f7..000000000000 --- a/arch/blackfin/lib/memcmp.S +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -/* int memcmp(const void *s1, const void *s2, size_t n); - * R0 = First Address (s1) - * R1 = Second Address (s2) - * R2 = count (n) - * - * Favours word aligned data. - */ - -.text - -.align 2 - -ENTRY(_memcmp) - I1 = P3; - P0 = R0; /* P0 = s1 address */ - P3 = R1; /* P3 = s2 Address */ - P2 = R2 ; /* P2 = count */ - CC = R2 <= 7(IU); - IF CC JUMP .Ltoo_small; - I0 = R1; /* s2 */ - R1 = R1 | R0; /* OR addresses together */ - R1 <<= 30; /* check bottom two bits */ - CC = AZ; /* AZ set if zero. */ - IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */ - - P1 = P2 >> 2; /* count = n/4 */ - R3 = 3; - R2 = R2 & R3; /* remainder */ - P2 = R2; /* set remainder */ - - LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1; -.Lquad_loop_s: -#if ANOMALY_05000202 - R0 = [P0++]; - R1 = [I0++]; -#else - MNOP || R0 = [P0++] || R1 = [I0++]; -#endif - CC = R0 == R1; - IF !CC JUMP .Lquad_different; -.Lquad_loop_e: - NOP; - - P3 = I0; /* s2 */ -.Ltoo_small: - CC = P2 == 0; /* Check zero count*/ - IF CC JUMP .Lfinished; /* very unlikely*/ - -.Lbytes: - LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2; -.Lbyte_loop_s: - R1 = B[P3++](Z); /* *s2 */ - R0 = B[P0++](Z); /* *s1 */ - CC = R0 == R1; - IF !CC JUMP .Ldifferent; -.Lbyte_loop_e: - NOP; - -.Ldifferent: - R0 = R0 - R1; - P3 = I1; - RTS; - -.Lquad_different: - /* We've read two quads which don't match. - * Can't just compare them, because we're - * a little-endian machine, so the MSBs of - * the regs occur at later addresses in the - * string. - * Arrange to re-read those two quads again, - * byte-by-byte. - */ - P0 += -4; /* back up to the start of the */ - P3 = I0; /* quads, and increase the*/ - P2 += 4; /* remainder count*/ - P3 += -4; - JUMP .Lbytes; - -.Lfinished: - R0 = 0; - P3 = I1; - RTS; - -ENDPROC(_memcmp) diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S deleted file mode 100644 index 53cb3698ab33..000000000000 --- a/arch/blackfin/lib/memcpy.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * internal version of memcpy(), issued by the compiler to copy blocks of - * data around. This is really memmove() - it has to be able to deal with - * possible overlaps, because that ambiguity is when the compiler gives up - * and calls a function. We have our own, internal version so that we get - * something we trust, even if the user has redefined the normal symbol. - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -/* void *memcpy(void *dest, const void *src, size_t n); - * R0 = To Address (dest) (leave unchanged to form result) - * R1 = From Address (src) - * R2 = count - * - * Note: Favours word alignment - */ - -#ifdef CONFIG_MEMCPY_L1 -.section .l1.text -#else -.text -#endif - -.align 2 - -ENTRY(_memcpy) - CC = R2 <= 0; /* length not positive? */ - IF CC JUMP .L_P1L2147483647; /* Nothing to do */ - - P0 = R0 ; /* dst*/ - P1 = R1 ; /* src*/ - P2 = R2 ; /* length */ - - /* check for overlapping data */ - CC = R1 < R0; /* src < dst */ - IF !CC JUMP .Lno_overlap; - R3 = R1 + R2; - CC = R0 < R3; /* and dst < src+len */ - IF CC JUMP .Lhas_overlap; - -.Lno_overlap: - /* Check for aligned data.*/ - - R3 = R1 | R0; - R1 = 0x3; - R3 = R3 & R1; - CC = R3; /* low bits set on either address? */ - IF CC JUMP .Lnot_aligned; - - /* Both addresses are word-aligned, so we can copy - at least part of the data using word copies.*/ - P2 = P2 >> 2; - CC = P2 <= 2; - IF !CC JUMP .Lmore_than_seven; - /* less than eight bytes... */ - P2 = R2; - LSETUP(.Lthree_start, .Lthree_end) LC0=P2; -.Lthree_start: - R3 = B[P1++] (X); -.Lthree_end: - B[P0++] = R3; - - RTS; - -.Lmore_than_seven: - /* There's at least eight bytes to copy. */ - P2 += -1; /* because we unroll one iteration */ - LSETUP(.Lword_loops, .Lword_loope) LC0=P2; - I1 = P1; - R3 = [I1++]; -#if ANOMALY_05000202 -.Lword_loops: - [P0++] = R3; -.Lword_loope: - R3 = [I1++]; -#else -.Lword_loops: -.Lword_loope: - MNOP || [P0++] = R3 || R3 = [I1++]; -#endif - [P0++] = R3; - /* Any remaining bytes to copy? */ - R3 = 0x3; - R3 = R2 & R3; - CC = R3 == 0; - P1 = I1; /* in case there's something left, */ - IF !CC JUMP .Lbytes_left; - RTS; -.Lbytes_left: P2 = R3; -.Lnot_aligned: - /* From here, we're copying byte-by-byte. */ - LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2; -.Lbyte_start: - R1 = B[P1++] (X); -.Lbyte_end: - B[P0++] = R1; - -.L_P1L2147483647: - RTS; - -.Lhas_overlap: - /* Need to reverse the copying, because the - * dst would clobber the src. - * Don't bother to work out alignment for - * the reverse case. - */ - P0 = P0 + P2; - P0 += -1; - P1 = P1 + P2; - P1 += -1; - LSETUP(.Lover_start, .Lover_end) LC0=P2; -.Lover_start: - R1 = B[P1--] (X); -.Lover_end: - B[P0--] = R1; - - RTS; - -ENDPROC(_memcpy) diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S deleted file mode 100644 index e0b78208f1d6..000000000000 --- a/arch/blackfin/lib/memmove.S +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -.align 2 - -/* - * C Library function MEMMOVE - * R0 = To Address (leave unchanged to form result) - * R1 = From Address - * R2 = count - * Data may overlap - */ - -ENTRY(_memmove) - I1 = P3; - P0 = R0; /* P0 = To address */ - P3 = R1; /* P3 = From Address */ - P2 = R2; /* P2 = count */ - CC = P2 == 0; /* Check zero count*/ - IF CC JUMP .Lfinished; /* very unlikely */ - - CC = R1 < R0 (IU); /* From < To */ - IF !CC JUMP .Lno_overlap; - R3 = R1 + R2; - CC = R0 <= R3 (IU); /* (From+len) >= To */ - IF CC JUMP .Loverlap; -.Lno_overlap: - R3 = 11; - CC = R2 <= R3; - IF CC JUMP .Lbytes; - R3 = R1 | R0; /* OR addresses together */ - R3 <<= 30; /* check bottom two bits */ - CC = AZ; /* AZ set if zero.*/ - IF !CC JUMP .Lbytes; /* Jump if addrs not aligned.*/ - - I0 = P3; - P1 = P2 >> 2; /* count = n/4 */ - P1 += -1; - R3 = 3; - R2 = R2 & R3; /* remainder */ - P2 = R2; /* set remainder */ - R1 = [I0++]; - - LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1; -#if ANOMALY_05000202 -.Lquad_loops: - [P0++] = R1; -.Lquad_loope: - R1 = [I0++]; -#else -.Lquad_loops: -.Lquad_loope: - MNOP || [P0++] = R1 || R1 = [I0++]; -#endif - [P0++] = R1; - - CC = P2 == 0; /* any remaining bytes? */ - P3 = I0; /* Amend P3 to updated ptr. */ - IF !CC JUMP .Lbytes; - P3 = I1; - RTS; - -.Lbytes: LSETUP (.Lbyte2_s, .Lbyte2_e) LC0=P2; -.Lbyte2_s: R1 = B[P3++](Z); -.Lbyte2_e: B[P0++] = R1; - -.Lfinished: P3 = I1; - RTS; - -.Loverlap: - P2 += -1; - P0 = P0 + P2; - P3 = P3 + P2; - R1 = B[P3--] (Z); - CC = P2 == 0; - IF CC JUMP .Lno_loop; -#if ANOMALY_05000245 - NOP; - NOP; -#endif - LSETUP (.Lol_s, .Lol_e) LC0 = P2; -.Lol_s: B[P0--] = R1; -.Lol_e: R1 = B[P3--] (Z); -.Lno_loop: B[P0] = R1; - P3 = I1; - RTS; - -ENDPROC(_memmove) diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S deleted file mode 100644 index cdcf9148ea20..000000000000 --- a/arch/blackfin/lib/memset.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -.align 2 - -#ifdef CONFIG_MEMSET_L1 -.section .l1.text -#else -.text -#endif - -/* - * C Library function MEMSET - * R0 = address (leave unchanged to form result) - * R1 = filler byte - * R2 = count - * Favours word aligned data. - * The strncpy assumes that I0 and I1 are not used in this function - */ - -ENTRY(_memset) - P0 = R0 ; /* P0 = address */ - P2 = R2 ; /* P2 = count */ - R3 = R0 + R2; /* end */ - CC = R2 <= 7(IU); - IF CC JUMP .Ltoo_small; - R1 = R1.B (Z); /* R1 = fill char */ - R2 = 3; - R2 = R0 & R2; /* addr bottom two bits */ - CC = R2 == 0; /* AZ set if zero. */ - IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */ - -.Laligned: - P1 = P2 >> 2; /* count = n/4 */ - R2 = R1 << 8; /* create quad filler */ - R2.L = R2.L + R1.L(NS); - R2.H = R2.L + R1.H(NS); - P2 = R3; - - LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1; -.Lquad_loop: - [P0++] = R2; - - CC = P0 == P2; - IF !CC JUMP .Lbytes_left; - RTS; - -.Lbytes_left: - R2 = R3; /* end point */ - R3 = P0; /* current position */ - R2 = R2 - R3; /* bytes left */ - P2 = R2; - -.Ltoo_small: - CC = P2 == 0; /* Check zero count */ - IF CC JUMP .Lfinished; /* Unusual */ - -.Lbytes: - LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2; -.Lbyte_loop: - B[P0++] = R1; - -.Lfinished: - RTS; - -.Lforce_align: - CC = BITTST (R0, 0); /* odd byte */ - R0 = 4; - R0 = R0 - R2; - P1 = R0; - R0 = P0; /* Recover return address */ - IF !CC JUMP .Lskip1; - B[P0++] = R1; -.Lskip1: - CC = R2 <= 2; /* 2 bytes */ - P2 -= P1; /* reduce count */ - IF !CC JUMP .Laligned; - B[P0++] = R1; - B[P0++] = R1; - JUMP .Laligned; - -ENDPROC(_memset) diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S deleted file mode 100644 index f7026ce1fa0e..000000000000 --- a/arch/blackfin/lib/modsi3.S +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This program computes 32 bit signed remainder. It calls div32 function - * for quotient estimation. - * Registers in: R0, R1 = Numerator/ Denominator - * Registers out: R0 = Remainder - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -.global ___modsi3; -.type ___modsi3, STT_FUNC; -.extern ___divsi3; -.type ___divsi3, STT_FUNC; - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -.section .l1.text -#else -.text -#endif - -___modsi3: - - CC=R0==0; - IF CC JUMP .LRETURN_R0; /* Return 0, if numerator == 0 */ - CC=R1==0; - IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 0 */ - CC=R0==R1; - IF CC JUMP .LRETURN_ZERO; /* Return 0, if numerator == denominator */ - CC = R1 == 1; - IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 1 */ - CC = R1 == -1; - IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == -1 */ - - /* Valid input. Use __divsi3() to compute the quotient, and then - * derive the remainder from that. */ - - [--SP] = (R7:6); /* Push R7 and R6 */ - [--SP] = RETS; /* and return address */ - R7 = R0; /* Copy of R0 */ - R6 = R1; /* Save for later */ - SP += -12; /* Should always provide this space */ - CALL ___divsi3; /* Compute signed quotient using ___divsi3()*/ - SP += 12; - R0 *= R6; /* Quotient * divisor */ - R0 = R7 - R0; /* Dividend - (quotient * divisor) */ - RETS = [SP++]; /* Get back return address */ - (R7:6) = [SP++]; /* Pop registers R7 and R4 */ - RTS; /* Store remainder */ - -.LRETURN_ZERO: - R0 = 0; -.LRETURN_R0: - RTS; - -.size ___modsi3, .-___modsi3 diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S deleted file mode 100644 index abf9b2a515b2..000000000000 --- a/arch/blackfin/lib/muldi3.S +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -.align 2 -.global ___muldi3; -.type ___muldi3, STT_FUNC; - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -.section .l1.text -#else -.text -#endif - -/* - R1:R0 * R3:R2 - = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l -[X] = (R1.h * R3.h) * 2^96 -[X] + (R1.h * R3.l + R1.l * R3.h) * 2^80 -[X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64 -[T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48 -[T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32 -[T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16 -[T4] + (R0.l * R2.l) - - We can discard the first three lines marked "X" since we produce - only a 64 bit result. So, we need ten 16-bit multiplies. - - Individual mul-acc results: -[E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h -[E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h -[E3] = R0.l * R2.h + R2.l * R0.h -[E4] = R0.l * R2.l - - We also need to add high parts from lower-level results to higher ones: - E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4 - - One interesting property is that all parts of the result that depend - on the sign of the multiplication are discarded. Those would be the - multiplications involving R1.h and R3.h, but only the top 16 bit of - the 32 bit result depend on the sign, and since R1.h and R3.h only - occur in E1, the top half of these results is cut off. - So, we can just use FU mode for all of the 16-bit multiplies, and - ignore questions of when to use mixed mode. */ - -___muldi3: - /* [SP] technically is part of the caller's frame, but we can - use it as scratch space. */ - A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */ - A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */ - A0 += A1; /* E1 */ - R4 = A0.w; - A0 = R0.l * R3.l (FU); /* E2 */ - A0 += R2.l * R1.l (FU); /* E2 */ - - A1 = R2.L * R0.L (FU); /* E4 */ - R3 = A1.w; - A1 = A1 >> 16; /* E3c */ - A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */ - A1 += R0.L * R2.H (FU); /* E3c */ - R0 = A1.w; - A1 = A1 >> 16; /* E2c */ - A0 += A1; /* E2c */ - R1 = A0.w; - - /* low(result) = low(E3c):low(E4) */ - R0 = PACK (R0.l, R3.l); - /* high(result) = E2c + (E1 << 16) */ - R1.h = R1.h + R4.l (NS) || R4 = [SP]; - RTS; - -.size ___muldi3, .-___muldi3 diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S deleted file mode 100644 index 06a5e674401f..000000000000 --- a/arch/blackfin/lib/outs.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Implementation of outs{bwl} for BlackFin processors using zero overhead loops. - * - * Copyright 2005-2009 Analog Devices Inc. - * 2005 BuyWays BV - * Bas Vermeulen - * - * Licensed under the GPL-2. - */ - -#include - -.align 2 - -ENTRY(_outsl) - CC = R2 == 0; - IF CC JUMP 1f; - P0 = R0; /* P0 = port */ - P1 = R1; /* P1 = address */ - P2 = R2; /* P2 = count */ - - LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2; -.Llong_loop_s: R0 = [P1++]; -.Llong_loop_e: [P0] = R0; -1: RTS; -ENDPROC(_outsl) - -ENTRY(_outsw) - CC = R2 == 0; - IF CC JUMP 1f; - P0 = R0; /* P0 = port */ - P1 = R1; /* P1 = address */ - P2 = R2; /* P2 = count */ - - LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2; -.Lword_loop_s: R0 = W[P1++]; -.Lword_loop_e: W[P0] = R0; -1: RTS; -ENDPROC(_outsw) - -ENTRY(_outsb) - CC = R2 == 0; - IF CC JUMP 1f; - P0 = R0; /* P0 = port */ - P1 = R1; /* P1 = address */ - P2 = R2; /* P2 = count */ - - LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2; -.Lbyte_loop_s: R0 = B[P1++]; -.Lbyte_loop_e: B[P0] = R0; -1: RTS; -ENDPROC(_outsb) - -ENTRY(_outsw_8) - CC = R2 == 0; - IF CC JUMP 1f; - P0 = R0; /* P0 = port */ - P1 = R1; /* P1 = address */ - P2 = R2; /* P2 = count */ - - LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; -.Lword8_loop_s: R1 = B[P1++]; - R0 = B[P1++]; - R0 = R0 << 8; - R0 = R0 + R1; -.Lword8_loop_e: W[P0] = R0; -1: RTS; -ENDPROC(_outsw_8) diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S deleted file mode 100644 index e50d6c4ac2a5..000000000000 --- a/arch/blackfin/lib/smulsi3_highpart.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2007 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -.align 2 -.global ___smulsi3_highpart; -.type ___smulsi3_highpart, STT_FUNC; - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -.section .l1.text -#else -.text -#endif - -___smulsi3_highpart: - R2 = R1.L * R0.L (FU); - R3 = R1.H * R0.L (IS,M); - R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M); - - R1.L = R2.H + R1.L; - cc = ac0; - R2 = cc; - - R1.L = R1.L + R3.L; - cc = ac0; - R1 >>>= 16; - R3 >>>= 16; - R1 = R1 + R3; - R1 = R1 + R2; - R2 = cc; - R1 = R1 + R2; - - R0 = R0 + R1; - RTS; - -.size ___smulsi3_highpart, .-___smulsi3_highpart diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S deleted file mode 100644 index 9c8b9863713e..000000000000 --- a/arch/blackfin/lib/strcmp.S +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -/* void *strcmp(char *s1, const char *s2); - * R0 = address (s1) - * R1 = address (s2) - * - * Returns an integer less than, equal to, or greater than zero if s1 - * (or the first n bytes thereof) is found, respectively, to be less - * than, to match, or be greater than s2. - */ - -#ifdef CONFIG_STRCMP_L1 -.section .l1.text -#else -.text -#endif - -.align 2 - -ENTRY(_strcmp) - P0 = R0 ; /* s1 */ - P1 = R1 ; /* s2 */ - -1: - R0 = B[P0++] (Z); /* get *s1 */ - R1 = B[P1++] (Z); /* get *s2 */ - CC = R0 == R1; /* compare a byte */ - if ! cc jump 2f; /* not equal, break out */ - CC = R0; /* at end of s1? */ - if cc jump 1b (bp); /* no, keep going */ - jump.s 3f; /* strings are equal */ -2: - R0 = R0 - R1; /* *s1 - *s2 */ -3: - RTS; - -ENDPROC(_strcmp) diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S deleted file mode 100644 index 9495aa77cc40..000000000000 --- a/arch/blackfin/lib/strcpy.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -/* void *strcpy(char *dest, const char *src); - * R0 = address (dest) - * R1 = address (src) - * - * Returns a pointer to the destination string dest - */ - -#ifdef CONFIG_STRCPY_L1 -.section .l1.text -#else -.text -#endif - -.align 2 - -ENTRY(_strcpy) - P0 = R0 ; /* dst*/ - P1 = R1 ; /* src*/ - -1: - R1 = B [P1++] (Z); - B [P0++] = R1; - CC = R1; - if cc jump 1b (bp); - RTS; - -ENDPROC(_strcpy) diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S deleted file mode 100644 index 3bfaedce893e..000000000000 --- a/arch/blackfin/lib/strncmp.S +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -/* void *strncpy(char *s1, const char *s2, size_t n); - * R0 = address (dest) - * R1 = address (src) - * R2 = size (n) - * Returns a pointer to the destination string dest - */ - -#ifdef CONFIG_STRNCMP_L1 -.section .l1.text -#else -.text -#endif - -.align 2 - -ENTRY(_strncmp) - CC = R2 == 0; - if CC JUMP 5f; - - P0 = R0 ; /* s1 */ - P1 = R1 ; /* s2 */ -1: - R0 = B[P0++] (Z); /* get *s1 */ - R1 = B[P1++] (Z); /* get *s2 */ - CC = R0 == R1; /* compare a byte */ - if ! cc jump 3f; /* not equal, break out */ - CC = R0; /* at end of s1? */ - if ! cc jump 4f; /* yes, all done */ - R2 += -1; /* no, adjust count */ - CC = R2 == 0; - if ! cc jump 1b (bp); /* more to do, keep going */ -2: - R0 = 0; /* strings are equal */ - jump.s 4f; -3: - R0 = R0 - R1; /* *s1 - *s2 */ -4: - RTS; - -5: - R0 = 0; - RTS; - -ENDPROC(_strncmp) diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S deleted file mode 100644 index 92fd1823bbee..000000000000 --- a/arch/blackfin/lib/strncpy.S +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include -#include - -/* void *strncpy(char *dest, const char *src, size_t n); - * R0 = address (dest) - * R1 = address (src) - * R2 = size - * Returns a pointer (R0) to the destination string dest - * we do this by not changing R0 - */ - -#ifdef CONFIG_STRNCPY_L1 -.section .l1.text -#else -.text -#endif - -.align 2 - -ENTRY(_strncpy) - CC = R2 == 0; - if CC JUMP 6f; - - P2 = R2 ; /* size */ - P0 = R0 ; /* dst*/ - P1 = R1 ; /* src*/ - - LSETUP (1f, 2f) LC0 = P2; -1: - R1 = B [P1++] (Z); - B [P0++] = R1; - CC = R1 == 0; -2: - if CC jump 3f; - - RTS; - - /* if src is shorter than n, we need to null pad bytes in dest - * but, we can get here when the last byte is zero, and we don't - * want to copy an extra byte at the end, so we need to check - */ -3: - R2 = LC0; - CC = R2 - if ! CC jump 6f; - - /* if the required null padded portion is small, do it here, rather than - * handling the overhead of memset (which is OK when things are big). - */ - R3 = 0x20; - CC = R2 < R3; - IF CC jump 4f; - - R2 += -1; - - /* Set things up for memset - * R0 = address - * R1 = filler byte (this case it's zero, set above) - * R2 = count (set above) - */ - - I1 = R0; - R0 = RETS; - I0 = R0; - R0 = P0; - pseudo_long_call _memset, p0; - R0 = I0; - RETS = R0; - R0 = I1; - RTS; - -4: - LSETUP(5f, 5f) LC0; -5: - B [P0++] = R1; -6: - RTS; - -ENDPROC(_strncpy) diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S deleted file mode 100644 index 90bfa809b392..000000000000 --- a/arch/blackfin/lib/udivsi3.S +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#include - -#define CARRY AC0 - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -.section .l1.text -#else -.text -#endif - - -ENTRY(___udivsi3) - - CC = R0 < R1 (IU); /* If X < Y, always return 0 */ - IF CC JUMP .Lreturn_ident; - - R2 = R1 << 16; - CC = R2 <= R0 (IU); - IF CC JUMP .Lidents; - - R2 = R0 >> 31; /* if X is a 31-bit number */ - R3 = R1 >> 15; /* and Y is a 15-bit number */ - R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/ - CC = R2; - IF CC JUMP .Ly_16bit; - -/* METHOD 1: FAST DIVQ - We know we have a 31-bit dividend, and 15-bit divisor so we can use the - simple divq approach (first setting AQ to 0 - implying unsigned division, - then 16 DIVQ's). -*/ - - AQ = CC; /* Clear AQ (CC==0) */ - -/* ISR States: When dividing two integers (32.0/16.0) using divide primitives, - we need to shift the dividend one bit to the left. - We have already checked that we have a 31-bit number so we are safe to do - that. -*/ - R0 <<= 1; - DIVQ(R0, R1); // 1 - DIVQ(R0, R1); // 2 - DIVQ(R0, R1); // 3 - DIVQ(R0, R1); // 4 - DIVQ(R0, R1); // 5 - DIVQ(R0, R1); // 6 - DIVQ(R0, R1); // 7 - DIVQ(R0, R1); // 8 - DIVQ(R0, R1); // 9 - DIVQ(R0, R1); // 10 - DIVQ(R0, R1); // 11 - DIVQ(R0, R1); // 12 - DIVQ(R0, R1); // 13 - DIVQ(R0, R1); // 14 - DIVQ(R0, R1); // 15 - DIVQ(R0, R1); // 16 - R0 = R0.L (Z); - RTS; - -.Ly_16bit: - /* We know that the upper 17 bits of Y might have bits set, - ** or that the sign bit of X might have a bit. If Y is a - ** 16-bit number, but not bigger, then we can use the builtins - ** with a post-divide correction. - ** R3 currently holds Y>>15, which means R3's LSB is the - ** bit we're interested in. - */ - - /* According to the ISR, to use the Divide primitives for - ** unsigned integer divide, the useable range is 31 bits - */ - CC = ! BITTST(R0, 31); - - /* IF condition is true we can scale our inputs and use the divide primitives, - ** with some post-adjustment - */ - R3 += -1; /* if so, Y is 0x00008nnn */ - CC &= AZ; - - /* If condition is true we can scale our inputs and use the divide primitives, - ** with some post-adjustment - */ - R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */ - R2 = R0 >> 16; - - R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */ - CC &= CARRY; - IF CC JUMP .Lshift_and_correct; - - /* Fall through to the identities */ - -/* METHOD 2: identities and manual calculation - We are not able to use the divide primites, but may still catch some special - cases. -*/ -.Lidents: - /* Test for common identities. Value to be returned is placed in R2. */ - CC = R0 == 0; /* 0/Y => 0 */ - IF CC JUMP .Lreturn_r0; - CC = R0 == R1; /* X==Y => 1 */ - IF CC JUMP .Lreturn_ident; - CC = R1 == 1; /* X/1 => X */ - IF CC JUMP .Lreturn_ident; - - R2.L = ONES R1; - R2 = R2.L (Z); - CC = R2 == 1; - IF CC JUMP .Lpower_of_two; - - [--SP] = (R7:5); /* Push registers R5-R7 */ - - /* Idents don't match. Go for the full operation. */ - - - R6 = 2; /* assume we'll shift two */ - R3 = 1; - - P2 = R1; - /* If either R0 or R1 have sign set, */ - /* divide them by two, and note it's */ - /* been done. */ - CC = R1 < 0; - R2 = R1 >> 1; - IF CC R1 = R2; /* Possibly-shifted R1 */ - IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */ - - P0 = 0; - R3 = -R1; - [--SP] = R3; - R2 = R0 >> 1; - R2 = R0 >> 1; - CC = R0 < 0; - IF CC P0 = R6; /* Number of values divided */ - IF !CC R2 = R0; /* Shifted R0 */ - - /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */ - - /* r2 holds Copy dividend */ - R3 = 0; /* Clear partial remainder */ - R7 = 0; /* Initialise quotient bit */ - - P1 = 32; /* Set loop counter */ - LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */ -.Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */ - R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */ - R3 = R3 << 1 || R5 = [SP]; - R3 = R3 | R6; /* Include any carry */ - CC = R7 < 0; /* Check quotient(AQ) */ - /* If AQ==0, we'll sub divisor */ - IF CC R5 = R1; /* and if AQ==1, we'll add it. */ - R3 = R3 + R5; /* Add/sub divisor to partial remainder */ - R7 = R3 ^ R1; /* Generate next quotient bit */ - - R5 = R7 >> 31; /* Get AQ */ - BITTGL(R5, 0); /* Invert it, to get what we'll shift */ -.Lulend: R2 = R2 + R5; /* and "shift" it in. */ - - CC = P0 == 0; /* Check how many inputs we shifted */ - IF CC JUMP .Lno_mult; /* if none... */ - R6 = R2 << 1; - CC = P0 == 1; - IF CC R2 = R6; /* if 1, Q = Q*2 */ - IF !CC R1 = P2; /* if 2, restore stored divisor */ - - R3 = R2; /* Copy of R2 */ - R3 *= R1; /* Q * divisor */ - R5 = R0 - R3; /* Z = (dividend - Q * divisor) */ - CC = R1 <= R5 (IU); /* Check if divisor <= Z? */ - R6 = CC; /* if yes, R6 = 1 */ - R2 = R2 + R6; /* if yes, add one to quotient(Q) */ -.Lno_mult: - SP += 4; - (R7:5) = [SP++]; /* Pop registers R5-R7 */ - R0 = R2; /* Store quotient */ - RTS; - -.Lreturn_ident: - CC = R0 < R1 (IU); /* If X < Y, always return 0 */ - R2 = 0; - IF CC JUMP .Ltrue_return_ident; - R2 = -1 (X); /* X/0 => 0xFFFFFFFF */ - CC = R1 == 0; - IF CC JUMP .Ltrue_return_ident; - R2 = -R2; /* R2 now 1 */ - CC = R0 == R1; /* X==Y => 1 */ - IF CC JUMP .Ltrue_return_ident; - R2 = R0; /* X/1 => X */ - /*FALLTHRU*/ - -.Ltrue_return_ident: - R0 = R2; -.Lreturn_r0: - RTS; - -.Lpower_of_two: - /* Y has a single bit set, which means it's a power of two. - ** That means we can perform the division just by shifting - ** X to the right the appropriate number of bits - */ - - /* signbits returns the number of sign bits, minus one. - ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need - ** to shift right n-signbits spaces. It also means 0x80000000 - ** is a special case, because that *also* gives a signbits of 0 - */ - - R2 = R0 >> 31; - CC = R1 < 0; - IF CC JUMP .Ltrue_return_ident; - - R1.l = SIGNBITS R1; - R1 = R1.L (Z); - R1 += -30; - R0 = LSHIFT R0 by R1.L; - RTS; - -/* METHOD 3: PRESCALE AND USE THE DIVIDE PRIMITIVES WITH SOME POST-CORRECTION - Two scaling operations are required to use the divide primitives with a - divisor > 0x7FFFF. - Firstly (as in method 1) we need to shift the dividend 1 to the left for - integer division. - Secondly we need to shift both the divisor and dividend 1 to the right so - both are in range for the primitives. - The left/right shift of the dividend does nothing so we can skip it. -*/ -.Lshift_and_correct: - R2 = R0; - // R3 is already R1 >> 1 - CC=!CC; - AQ = CC; /* Clear AQ, got here with CC = 0 */ - DIVQ(R2, R3); // 1 - DIVQ(R2, R3); // 2 - DIVQ(R2, R3); // 3 - DIVQ(R2, R3); // 4 - DIVQ(R2, R3); // 5 - DIVQ(R2, R3); // 6 - DIVQ(R2, R3); // 7 - DIVQ(R2, R3); // 8 - DIVQ(R2, R3); // 9 - DIVQ(R2, R3); // 10 - DIVQ(R2, R3); // 11 - DIVQ(R2, R3); // 12 - DIVQ(R2, R3); // 13 - DIVQ(R2, R3); // 14 - DIVQ(R2, R3); // 15 - DIVQ(R2, R3); // 16 - - /* According to the Instruction Set Reference: - To divide by a divisor > 0x7FFF, - 1. prescale and perform divide to obtain quotient (Q) (done above), - 2. multiply quotient by unscaled divisor (result M) - 3. subtract the product from the divident to get an error (E = X - M) - 4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q) - */ - R3 = R2.L (Z); /* Q = X' / Y' */ - R2 = R3; /* Preserve Q */ - R2 *= R1; /* M = Q * Y */ - R2 = R0 - R2; /* E = X - M */ - R0 = R3; /* Copy Q into result reg */ - -/* Correction: If result of the multiply is negative, we overflowed - and need to correct the result by subtracting 1 from the result.*/ - R3 = 0xFFFF (Z); - R2 = R2 >> 16; /* E >> 16 */ - CC = R2 == R3; - R3 = 1 ; - R1 = R0 - R3; - IF CC R0 = R1; - RTS; - -ENDPROC(___udivsi3) diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S deleted file mode 100644 index 3794c00d859d..000000000000 --- a/arch/blackfin/lib/umodsi3.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * libgcc1 routines for Blackfin 5xx - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifdef CONFIG_ARITHMETIC_OPS_L1 -.section .l1.text -#else -.text -#endif - -.extern ___udivsi3; -.type ___udivsi3, STT_FUNC; -.globl ___umodsi3 -.type ___umodsi3, STT_FUNC; -___umodsi3: - - CC=R0==0; - IF CC JUMP .LRETURN_R0; /* Return 0, if NR == 0 */ - CC= R1==0; - IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 0 */ - CC=R0==R1; - IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if NR == DR */ - CC = R1 == 1; - IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 1 */ - CC = R0>= 16; - /* Unsigned multiplication has the nice property that we can - ignore carry on this first addition. */ - R0 = R0 + R3; - R0 = R0 + R1; - cc = ac0; - R1 = cc; - R1 = PACK(R1.l,R0.h); - R0 = R1 + R2; - RTS; - -.size ___umulsi3_highpart, .-___umulsi3_highpart diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig deleted file mode 100644 index 4731f6b27e47..000000000000 --- a/arch/blackfin/mach-bf518/Kconfig +++ /dev/null @@ -1,320 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config BF51x - def_bool y - depends on (BF512 || BF514 || BF516 || BF518) - -if (BF51x) - -source "arch/blackfin/mach-bf518/boards/Kconfig" - -menu "BF518 Specific Configuration" - -comment "Alternative Multiplexing Scheme" - -choice - prompt "PWM Channel Pins" - default BF518_PWM_ALL_PORTF - help - Select pins used for the PWM channels: - PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL - - See the Hardware Reference Manual for more details. - -config BF518_PWM_ALL_PORTF - bool "PF1 - PF6" - help - PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL} - -config BF518_PWM_PORTF_PORTG - bool "PF11 - PF14 / PG1 - PG2" - help - PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL} - PG{1,2} <-> PWM_{CH,CL} - -endchoice - -choice - prompt "PWM Sync Pin" - default BF518_PWM_SYNC_PF7 - help - Select the pin used for PWM_SYNC. - - See the Hardware Reference Manual for more details. - -config BF518_PWM_SYNC_PF7 - bool "PF7" -config BF518_PWM_SYNC_PF15 - bool "PF15" -endchoice - -choice - prompt "PWM Trip B Pin" - default BF518_PWM_TRIPB_PG10 - help - Select the pin used for PWM_TRIPB. - - See the Hardware Reference Manual for more details. - -config BF518_PWM_TRIPB_PG10 - bool "PG10" -config BF518_PWM_TRIPB_PG14 - bool "PG14" -endchoice - -choice - prompt "PPI / Timer Pins" - default BF518_PPI_TMR_PG5 - help - Select pins used for PPI/Timer: - PPICLK PPIFS1 PPIFS2 - TMRCLK TMR0 TMR1 - - See the Hardware Reference Manual for more details. - -config BF518_PPI_TMR_PG5 - bool "PG5 - PG7" - help - PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2} - -config BF518_PPI_TMR_PG12 - bool "PG12 - PG14" - help - PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2} - -endchoice - -comment "Hysteresis/Schmitt Trigger Control" -config BFIN_HYSTERESIS_CONTROL - bool "Enable Hysteresis Control" - help - The ADSP-BF51x allows to control input hysteresis for Port F, - Port G and Port H and other processor signal inputs. - The Schmitt trigger enables can be set only for pin groups. - Saying Y will overwrite the default reset or boot loader - initialization. - -menu "PORT F" - depends on BFIN_HYSTERESIS_CONTROL -config GPIO_HYST_PORTF_0_7 - bool "Enable Hysteresis on PORTF {0...7}" -config GPIO_HYST_PORTF_8_9 - bool "Enable Hysteresis on PORTF {8, 9}" -config GPIO_HYST_PORTF_10 - bool "Enable Hysteresis on PORTF 10" -config GPIO_HYST_PORTF_11 - bool "Enable Hysteresis on PORTF 11" -config GPIO_HYST_PORTF_12_13 - bool "Enable Hysteresis on PORTF {12, 13}" -config GPIO_HYST_PORTF_14_15 - bool "Enable Hysteresis on PORTF {14, 15}" -endmenu - -menu "PORT G" - depends on BFIN_HYSTERESIS_CONTROL -config GPIO_HYST_PORTG_0 - bool "Enable Hysteresis on PORTG 0" -config GPIO_HYST_PORTG_1_4 - bool "Enable Hysteresis on PORTG {1...4}" -config GPIO_HYST_PORTG_5_6 - bool "Enable Hysteresis on PORTG {5, 6}" -config GPIO_HYST_PORTG_7_8 - bool "Enable Hysteresis on PORTG {7, 8}" -config GPIO_HYST_PORTG_9 - bool "Enable Hysteresis on PORTG 9" -config GPIO_HYST_PORTG_10 - bool "Enable Hysteresis on PORTG 10" -config GPIO_HYST_PORTG_11_13 - bool "Enable Hysteresis on PORTG {11...13}" -config GPIO_HYST_PORTG_14_15 - bool "Enable Hysteresis on PORTG {14, 15}" -endmenu - -menu "PORT H" - depends on BFIN_HYSTERESIS_CONTROL -config GPIO_HYST_PORTH_0_7 - bool "Enable Hysteresis on PORTH {0...7}" - -endmenu - -menu "None-GPIO" - depends on BFIN_HYSTERESIS_CONTROL -config NONEGPIO_HYST_NMI_RST_BMODE - bool "Enable Hysteresis on {NMI, RESET, BMODE}" -config NONEGPIO_HYST_JTAG - bool "Enable Hysteresis on JTAG" -endmenu - -comment "Interrupt Priority Assignment" -menu "Priority" - -config IRQ_PLL_WAKEUP - int "IRQ_PLL_WAKEUP" - default 7 -config IRQ_DMA0_ERROR - int "IRQ_DMA0_ERROR" - default 7 -config IRQ_DMAR0_BLK - int "IRQ_DMAR0_BLK" - default 7 -config IRQ_DMAR1_BLK - int "IRQ_DMAR1_BLK" - default 7 -config IRQ_DMAR0_OVR - int "IRQ_DMAR0_OVR" - default 7 -config IRQ_DMAR1_OVR - int "IRQ_DMAR1_OVR" - default 7 -config IRQ_PPI_ERROR - int "IRQ_PPI_ERROR" - default 7 -config IRQ_MAC_ERROR - int "IRQ_MAC_ERROR" - default 7 -config IRQ_SPORT0_ERROR - int "IRQ_SPORT0_ERROR" - default 7 -config IRQ_SPORT1_ERROR - int "IRQ_SPORT1_ERROR" - default 7 -config IRQ_PTP_ERROR - int "IRQ_PTP_ERROR" - default 7 -config IRQ_UART0_ERROR - int "IRQ_UART0_ERROR" - default 7 -config IRQ_UART1_ERROR - int "IRQ_UART1_ERROR" - default 7 -config IRQ_RTC - int "IRQ_RTC" - default 8 -config IRQ_PPI - int "IRQ_PPI" - default 8 -config IRQ_SPORT0_RX - int "IRQ_SPORT0_RX" - default 9 -config IRQ_SPORT0_TX - int "IRQ_SPORT0_TX" - default 9 -config IRQ_SPORT1_RX - int "IRQ_SPORT1_RX" - default 9 -config IRQ_SPORT1_TX - int "IRQ_SPORT1_TX" - default 9 -config IRQ_TWI - int "IRQ_TWI" - default 10 -config IRQ_SPI0 - int "IRQ_SPI" - default 10 -config IRQ_UART0_RX - int "IRQ_UART0_RX" - default 10 -config IRQ_UART0_TX - int "IRQ_UART0_TX" - default 10 -config IRQ_UART1_RX - int "IRQ_UART1_RX" - default 10 -config IRQ_UART1_TX - int "IRQ_UART1_TX" - default 10 -config IRQ_OPTSEC - int "IRQ_OPTSEC" - default 11 -config IRQ_CNT - int "IRQ_CNT" - default 11 -config IRQ_MAC_RX - int "IRQ_MAC_RX" - default 11 -config IRQ_PORTH_INTA - int "IRQ_PORTH_INTA" - default 11 -config IRQ_MAC_TX - int "IRQ_MAC_TX/NFC" - default 11 -config IRQ_PORTH_INTB - int "IRQ_PORTH_INTB" - default 11 -config IRQ_TIMER0 - int "IRQ_TIMER0" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config IRQ_TIMER1 - int "IRQ_TIMER1" - default 12 -config IRQ_TIMER2 - int "IRQ_TIMER2" - default 12 -config IRQ_TIMER3 - int "IRQ_TIMER3" - default 12 -config IRQ_TIMER4 - int "IRQ_TIMER4" - default 12 -config IRQ_TIMER5 - int "IRQ_TIMER5" - default 12 -config IRQ_TIMER6 - int "IRQ_TIMER6" - default 12 -config IRQ_TIMER7 - int "IRQ_TIMER7" - default 12 -config IRQ_PORTG_INTA - int "IRQ_PORTG_INTA" - default 12 -config IRQ_PORTG_INTB - int "IRQ_PORTG_INTB" - default 12 -config IRQ_MEM_DMA0 - int "IRQ_MEM_DMA0" - default 13 -config IRQ_MEM_DMA1 - int "IRQ_MEM_DMA1" - default 13 -config IRQ_WATCH - int "IRQ_WATCH" - default 13 -config IRQ_PORTF_INTA - int "IRQ_PORTF_INTA" - default 13 -config IRQ_PORTF_INTB - int "IRQ_PORTF_INTB" - default 13 -config IRQ_SPI0_ERROR - int "IRQ_SPI0_ERROR" - default 7 -config IRQ_SPI1_ERROR - int "IRQ_SPI1_ERROR" - default 7 -config IRQ_RSI_INT0 - int "IRQ_RSI_INT0" - default 7 -config IRQ_RSI_INT1 - int "IRQ_RSI_INT1" - default 7 -config IRQ_PWM_TRIP - int "IRQ_PWM_TRIP" - default 10 -config IRQ_PWM_SYNC - int "IRQ_PWM_SYNC" - default 10 -config IRQ_PTP_STAT - int "IRQ_PTP_STAT" - default 10 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf518/Makefile b/arch/blackfin/mach-bf518/Makefile deleted file mode 100644 index 168a193f9f9a..000000000000 --- a/arch/blackfin/mach-bf518/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf518/Makefile -# - -obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf518/boards/Kconfig b/arch/blackfin/mach-bf518/boards/Kconfig deleted file mode 100644 index f7b93b950ef4..000000000000 --- a/arch/blackfin/mach-bf518/boards/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN518F_EZBRD - help - Select your board! - -config BFIN518F_EZBRD - bool "BF518F-EZBRD" - help - BF518-EZBRD board support. - -config BFIN518F_TCM - bool "Bluetechnix TCM-BF518" - help - Bluetechnix TCM-BF518 board support. - -endchoice diff --git a/arch/blackfin/mach-bf518/boards/Makefile b/arch/blackfin/mach-bf518/boards/Makefile deleted file mode 100644 index a9ef25c6b302..000000000000 --- a/arch/blackfin/mach-bf518/boards/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# arch/blackfin/mach-bf518/boards/Makefile -# - -obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o -obj-$(CONFIG_BFIN518F_TCM) += tcm-bf518.o diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c deleted file mode 100644 index c51d1b810ac3..000000000000 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ /dev/null @@ -1,794 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF518F-EZBRD"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezbrd_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x1C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data ezbrd_flash_data = { - .width = 2, - .parts = ezbrd_partitions, - .nr_parts = ARRAY_SIZE(ezbrd_partitions), -}; - -static struct resource ezbrd_flash_resource = { - .start = 0x20000000, -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - .end = 0x202fffff, -#else - .end = 0x203fffff, -#endif - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezbrd_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezbrd_flash_data, - }, - .num_resources = 1, - .resource = &ezbrd_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = { - P_MII0_ETxD0, - P_MII0_ETxD1, - P_MII0_ETxEN, - P_MII0_ERxD0, - P_MII0_ERxD1, - P_MII0_TxCLK, - P_MII0_PHYINT, - P_MII0_CRS, - P_MII0_MDC, - P_MII0_MDIO, - 0 -}; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_MII, - .mac_peripherals = bfin_mac_peripherals, - .vlan1_mask = 1, - .vlan2_mask = 2, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; - -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PF8, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \ - && defined(CONFIG_SND_SOC_WM8731_SPI) - { - .modalias = "wm8731", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - { - .modalias = "bfin-lq035q1-spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -}; - -/* SPI controller data */ -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 6, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI0, - .end = CH_SPI0, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; - -/* SPI (1) */ -static struct bfin5xx_spi_master bfin_spi1_info = { - .num_chipselect = 6, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, -}; - -static struct resource bfin_spi1_resource[] = { - [0] = { - .start = SPI1_REGBASE, - .end = SPI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI1, - .end = CH_SPI1, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi1_device = { - .name = "bfin-spi", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi1_resource), - .resource = bfin_spi1_resource, - .dev = { - .platform_data = &bfin_spi1_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = IRQ_PF8, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) - { - I2C_BOARD_INFO("ssm2602", 0x1b), - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - -static struct bfin_sd_host bfin_sdh_data = { - .dma_chan = CH_RSI, - .irq_int0 = IRQ_RSI_INT0, - .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, -}; - -static struct platform_device bf51x_sdh_device = { - .name = "bfin-sdh", - .id = 0, - .dev = { - .platform_data = &bfin_sdh_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_100, 400000000), - VRPAIR(VLEV_105, 426000000), - VRPAIR(VLEV_110, 500000000), - VRPAIR(VLEV_115, 533000000), - VRPAIR(VLEV_120, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, - &bfin_spi1_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - &bf51x_sdh_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezbrd_flash_device, -#endif -}; - -static int __init ezbrd_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */ - peripheral_request(P_AMS2, "ParaFlash"); -#if !IS_ENABLED(CONFIG_SPI_BFIN5XX) - peripheral_request(P_AMS3, "ParaFlash"); -#endif - return 0; -} - -arch_initcall(ezbrd_init); - -static struct platform_device *ezbrd_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezbrd_early_devices, - ARRAY_SIZE(ezbrd_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -int bfin_get_ether_addr(char *addr) -{ - /* the MAC is stored in OTP memory page 0xDF */ - u32 ret; - u64 otp_mac; - u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; - - ret = otp_read(0xDF, 0x00, &otp_mac); - if (!(ret & 0x1)) { - char *otp_mac_p = (char *)&otp_mac; - for (ret = 0; ret < 6; ++ret) - addr[ret] = otp_mac_p[5 - ret]; - } - return 0; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c deleted file mode 100644 index 37d868085f6a..000000000000 --- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c +++ /dev/null @@ -1,739 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix TCM-BF518"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition tcm_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, - { - .name = "linux(nor)", - .size = 0x1C0000, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data tcm_flash_data = { - .width = 2, - .parts = tcm_partitions, - .nr_parts = ARRAY_SIZE(tcm_partitions), -}; - -static struct resource tcm_flash_resource = { - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device tcm_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &tcm_flash_data, - }, - .num_resources = 1, - .resource = &tcm_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_MII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_MII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* SPI0_SSEL2 */ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PF8, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \ - && defined(CONFIG_SND_SOC_WM8731_SPI) - { - .modalias = "wm8731", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - { - .modalias = "bfin-lq035q1-spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -}; - -/* SPI controller data */ -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 6, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI0, - .end = CH_SPI0, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; - -/* SPI (1) */ -static struct bfin5xx_spi_master bfin_spi1_info = { - .num_chipselect = 6, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, -}; - -static struct resource bfin_spi1_resource[] = { - [0] = { - .start = SPI1_REGBASE, - .end = SPI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI1, - .end = CH_SPI1, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi1_device = { - .name = "bfin-spi", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi1_resource), - .resource = bfin_spi1_resource, - .dev = { - .platform_data = &bfin_spi1_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = IRQ_PF8, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - -static struct bfin_sd_host bfin_sdh_data = { - .dma_chan = CH_RSI, - .irq_int0 = IRQ_RSI_INT0, - .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, -}; - -static struct platform_device bf51x_sdh_device = { - .name = "bfin-sdh", - .id = 0, - .dev = { - .platform_data = &bfin_sdh_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_100, 400000000), - VRPAIR(VLEV_105, 426000000), - VRPAIR(VLEV_110, 500000000), - VRPAIR(VLEV_115, 533000000), - VRPAIR(VLEV_120, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *tcm_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, - &bfin_spi1_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - &bf51x_sdh_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &tcm_flash_device, -#endif -}; - -static int __init tcm_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - platform_add_devices(tcm_devices, ARRAY_SIZE(tcm_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(tcm_init); - -static struct platform_device *tcm_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(tcm_early_devices, - ARRAY_SIZE(tcm_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -int bfin_get_ether_addr(char *addr) -{ - return 1; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c deleted file mode 100644 index bcd1fbc8c543..000000000000 --- a/arch/blackfin/mach-bf518/dma.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * the simple DMA Implementation for Blackfin - * - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) DMA8_NEXT_DESC_PTR, - (struct dma_register *) DMA9_NEXT_DESC_PTR, - (struct dma_register *) DMA10_NEXT_DESC_PTR, - (struct dma_register *) DMA11_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI: - ret_irq = IRQ_PPI; - break; - - case CH_EMAC_RX: - ret_irq = IRQ_MAC_RX; - break; - - case CH_EMAC_TX: - ret_irq = IRQ_MAC_TX; - break; - - case CH_UART1_RX: - ret_irq = IRQ_UART1_RX; - break; - - case CH_UART1_TX: - ret_irq = IRQ_UART1_TX; - break; - - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - - case CH_SPI0: - ret_irq = IRQ_SPI0; - break; - - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h deleted file mode 100644 index 46cb88231d66..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List - */ - -#if __SILICON_REVISION__ < 0 -# error will not work on BF518 silicon version -#endif - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (1) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ -#define ANOMALY_05000405 (1) -/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ -#define ANOMALY_05000408 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ -#define ANOMALY_05000421 (1) -/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ -#define ANOMALY_05000422 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) -/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ -#define ANOMALY_05000431 (1) -/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ -#define ANOMALY_05000434 (1) -/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ -#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) -/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ -#define ANOMALY_05000438 (__SILICON_REVISION__ < 1) -/* Preboot Cannot be Used to Alter the PLL_DIV Register */ -#define ANOMALY_05000439 (__SILICON_REVISION__ < 1) -/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ -#define ANOMALY_05000440 (__SILICON_REVISION__ < 1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* Incorrect L1 Instruction Bank B Memory Map Location */ -#define ANOMALY_05000444 (__SILICON_REVISION__ < 1) -/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) -/* PWM_TRIPB Signal Not Available on PG10 */ -#define ANOMALY_05000453 (__SILICON_REVISION__ < 1) -/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ -#define ANOMALY_05000455 (__SILICON_REVISION__ < 1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (__SILICON_REVISION__ < 2) -/* Incorrect Default MSEL Value in PLL_CTL */ -#define ANOMALY_05000472 (__SILICON_REVISION__ < 2) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* PLL Latches Incorrect Settings During Reset */ -#define ANOMALY_05000482 (__SILICON_REVISION__ < 2) -/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (__SILICON_REVISION__ < 2) -/* SPI Master Boot Can Fail Under Certain Conditions */ -#define ANOMALY_05000490 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ -#define ANOMALY_05000498 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000099 (0) -#define ANOMALY_05000120 (0) -#define ANOMALY_05000125 (0) -#define ANOMALY_05000149 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000179 (0) -#define ANOMALY_05000182 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000189 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000202 (0) -#define ANOMALY_05000215 (0) -#define ANOMALY_05000219 (0) -#define ANOMALY_05000220 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000231 (0) -#define ANOMALY_05000233 (0) -#define ANOMALY_05000234 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000248 (0) -#define ANOMALY_05000250 (0) -#define ANOMALY_05000257 (0) -#define ANOMALY_05000261 (0) -#define ANOMALY_05000263 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000278 (0) -#define ANOMALY_05000281 (0) -#define ANOMALY_05000283 (0) -#define ANOMALY_05000285 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000301 (0) -#define ANOMALY_05000305 (0) -#define ANOMALY_05000307 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000312 (0) -#define ANOMALY_05000315 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (0) -#define ANOMALY_05000357 (0) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000364 (0) -#define ANOMALY_05000371 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000383 (0) -#define ANOMALY_05000386 (0) -#define ANOMALY_05000389 (0) -#define ANOMALY_05000400 (0) -#define ANOMALY_05000402 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000456 (0) -#define ANOMALY_05000450 (0) -#define ANOMALY_05000465 (0) -#define ANOMALY_05000467 (0) -#define ANOMALY_05000474 (0) -#define ANOMALY_05000475 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h deleted file mode 100644 index 6906dee4f4cc..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/bf518.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF518_H__ -#define __MACH_BF518_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) - -/**************************** Hysteresis Settings ****************************/ - -#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL -#ifdef CONFIG_GPIO_HYST_PORTF_0_7 -#define HYST_PORTF_0_7 (1 << 0) -#else -#define HYST_PORTF_0_7 (0 << 0) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_8_9 -#define HYST_PORTF_8_9 (1 << 2) -#else -#define HYST_PORTF_8_9 (0 << 2) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_10 -#define HYST_PORTF_10 (1 << 4) -#else -#define HYST_PORTF_10 (0 << 4) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_11 -#define HYST_PORTF_11 (1 << 6) -#else -#define HYST_PORTF_11 (0 << 6) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_12_13 -#define HYST_PORTF_12_13 (1 << 8) -#else -#define HYST_PORTF_12_13 (0 << 8) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_14_15 -#define HYST_PORTF_14_15 (1 << 10) -#else -#define HYST_PORTF_14_15 (0 << 10) -#endif - -#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \ - HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15) - -#ifdef CONFIG_GPIO_HYST_PORTG_0 -#define HYST_PORTG_0 (1 << 0) -#else -#define HYST_PORTG_0 (0 << 0) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_1_4 -#define HYST_PORTG_1_4 (1 << 2) -#else -#define HYST_PORTG_1_4 (0 << 2) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_5_6 -#define HYST_PORTG_5_6 (1 << 4) -#else -#define HYST_PORTG_5_6 (0 << 4) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_7_8 -#define HYST_PORTG_7_8 (1 << 6) -#else -#define HYST_PORTG_7_8 (0 << 6) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_9 -#define HYST_PORTG_9 (1 << 8) -#else -#define HYST_PORTG_9 (0 << 8) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_10 -#define HYST_PORTG_10 (1 << 10) -#else -#define HYST_PORTG_10 (0 << 10) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_11_13 -#define HYST_PORTG_11_13 (1 << 12) -#else -#define HYST_PORTG_11_13 (0 << 12) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_14_15 -#define HYST_PORTG_14_15 (1 << 14) -#else -#define HYST_PORTG_14_15 (0 << 14) -#endif - -#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \ - HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \ - HYST_PORTG_11_13 | HYST_PORTG_14_15) - -#ifdef CONFIG_GPIO_HYST_PORTH_0_7 -#define HYST_PORTH_0_7 (1 << 0) -#else -#define HYST_PORTH_0_7 (0 << 0) -#endif - -#define HYST_PORTH_0_15 (HYST_PORTH_0_7) - -#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE -#define HYST_NMI_RST_BMODE (1 << 2) -#else -#define HYST_NMI_RST_BMODE (0 << 2) -#endif -#ifdef CONFIG_NONEGPIO_HYST_JTAG -#define HYST_JTAG (1 << 4) -#else -#define HYST_JTAG (0 << 4) -#endif - -#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG) -#define HYST_NONEGPIO_MASK (0x3C) -#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */ - -#ifdef CONFIG_BF518 -#define CPU "BF518" -#define CPUID 0x27e8 -#endif -#ifdef CONFIG_BF516 -#define CPU "BF516" -#define CPUID 0x27e8 -#endif -#ifdef CONFIG_BF514 -#define CPU "BF514" -#define CPUID 0x27e8 -#endif -#ifdef CONFIG_BF512 -#define CPU "BF512" -#define CPUID 0x27e8 -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF518_H__ */ diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h deleted file mode 100644 index 00c603fe8218..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 2 - -#endif diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h deleted file mode 100644 index a8828863226e..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#include "bf518.h" -#include "anomaly.h" - -#include -#ifdef CONFIG_BF512 -# include "defBF512.h" -#endif -#ifdef CONFIG_BF514 -# include "defBF514.h" -#endif -#ifdef CONFIG_BF516 -# include "defBF516.h" -#endif -#ifdef CONFIG_BF518 -# include "defBF518.h" -#endif - -#ifndef __ASSEMBLY__ -# include -# ifdef CONFIG_BF512 -# include "cdefBF512.h" -# endif -# ifdef CONFIG_BF514 -# include "cdefBF514.h" -# endif -# ifdef CONFIG_BF516 -# include "cdefBF516.h" -# endif -# ifdef CONFIG_BF518 -# include "cdefBF518.h" -# endif -#endif - -#endif diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h deleted file mode 100644 index 1c03ad4bcb72..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h +++ /dev/null @@ -1,1043 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _CDEF_BF512_H -#define _CDEF_BF512_H - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) - - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) - -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) - -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) - -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) - -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) -#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) - -/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ - -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) -#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) - - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) - -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) - -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) - -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) - -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) - -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) - -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) - -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) - -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) - - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) - - -/* DMA Traffic Control Registers */ -#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) -#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) -#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) -#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) - -/* DMA Controller */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) - -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) - -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) - -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) - -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) - -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) - -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) - -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) - -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) - -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) - -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) - -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) - -/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */ - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) -#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) - -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) - -/* ==== end from cdefBF534.h ==== */ - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ - -#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) -#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) -#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) - -#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) -#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) -#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) -#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) -#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) -#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) -#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) -#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) -#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) -#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) -#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) -#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) -#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) -#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) -#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) -#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) -#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) -#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) -#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) -#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) -#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) -#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS) -#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val) - -/* HOST Port Registers */ - -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) - -/* Counter Registers */ - -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) - -/* Security Registers */ - -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) - -#endif /* _CDEF_BF512_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h deleted file mode 100644 index 861221d1dcc9..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _CDEF_BF514_H -#define _CDEF_BF514_H - -/* BF514 is BF512 + RSI */ -#include "cdefBF512.h" - -/* Removable Storage Interface Registers */ - -#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) -#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) -#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) -#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) -#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) -#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) -#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) -#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) -#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) -#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) -#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) -#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) -#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) -#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) -#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) -#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) -#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) -#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) -#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) -#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) -#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) -#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) -#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) -#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) -#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) -#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) -#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) -#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) -#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) -#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) -#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) -#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) -#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) -#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) -#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) -#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) -#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) -#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) -#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) -#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) -#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) -#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) -#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) -#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) -#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) -#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) -#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) -#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) -#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) -#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) -#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) -#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) -#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) -#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) -#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) -#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) -#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) -#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) -#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) -#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) -#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) -#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) -#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) -#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) - -#endif /* _CDEF_BF514_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h deleted file mode 100644 index cc9bf0d378c3..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _CDEF_BF516_H -#define _CDEF_BF516_H - -/* BF516 is BF514 + EMAC */ -#include "cdefBF514.h" - -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ - -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) - -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) - -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) - -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) - -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) - -#endif /* _CDEF_BF516_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h deleted file mode 100644 index 96a82fd62ef1..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _CDEF_BF518_H -#define _CDEF_BF518_H - -/* BF518 is BF516 + IEEE-1588 */ -#include "cdefBF516.h" - -/* PTP TSYNC Registers */ - -#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) -#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) -#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE) -#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val) -#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT) -#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val) -#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF) -#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val) -#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1) -#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val) -#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2) -#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val) -#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3) -#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val) -#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND) -#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val) -#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR) -#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val) -#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET) -#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val) -#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO) -#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val) -#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI) -#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val) -#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO) -#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI) -#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO) -#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI) -#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO) -#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val) -#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI) -#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val) -#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF) -#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val) -#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP) -#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val) -#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI) -#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val) -#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) -#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) - -#endif /* _CDEF_BF518_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h deleted file mode 100644 index e6a017faad01..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/defBF512.h +++ /dev/null @@ -1,1304 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF512_H -#define _DEF_BF512_H - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */ -/* ************************************************************** */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 /* Device ID Register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ - -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ - -/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ -#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ -#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ -#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ -#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ -#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ -#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ -#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ - - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI0_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI0_STAT 0xFFC00508 /* SPI Status register */ -#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ -#define SPI1_REGBASE 0xFFC03400 -#define SPI1_CTL 0xFFC03400 /* SPI Control Register */ -#define SPI1_FLG 0xFFC03404 /* SPI Flag register */ -#define SPI1_STAT 0xFFC03408 /* SPI Status register */ -#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */ -#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */ - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ - -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ - -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ - -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ - -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ - -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Traffic Control Registers */ -#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ - -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ - -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ - -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define TWI0_REGBASE 0xFFC01400 -#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ - -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ - - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ -#define PORTF_MUX 0xFFC03210 /* Port F mux control */ -#define PORTG_MUX 0xFFC03214 /* Port G mux control */ -#define PORTH_MUX 0xFFC03218 /* Port H mux control */ -#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ -#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ -#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ -#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ -#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ -#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ -#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ -#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ -#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ -#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ -#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ -#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */ - - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ -/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ - -#if 0 -#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ - -#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ -#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ -#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ -#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ -#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ -#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ -#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ - -#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ -#define IRQ_TWI 0x00000200 /* TWI Interrupt */ -#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ -#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ -#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ -#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ -#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ -#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ - -#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ -#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ -#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ -#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ -#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ -#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ -#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ -#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ -#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ -#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ - -#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ -#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ -#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ -#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ -#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ -#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ -#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ -#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ -#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ -#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ -#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ -#endif - -/* SIC_IAR0 Macros */ -#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Macros */ -#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Macros */ -#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IAR3 Macros */ -#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ -#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ -#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ -#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ -#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ -#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ -#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ -#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ - - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ - -/* **************** GENERAL PURPOSE TIMER MASKS **********************/ -/* TIMER_ENABLE Masks */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ -#define TIMEN3 0x0008 /* Enable Timer 3 */ -#define TIMEN4 0x0010 /* Enable Timer 4 */ -#define TIMEN5 0x0020 /* Enable Timer 5 */ -#define TIMEN6 0x0040 /* Enable Timer 6 */ -#define TIMEN7 0x0080 /* Enable Timer 7 */ - -/* TIMER_DISABLE Masks */ -#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ -#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ -#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ -#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ -#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ -#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ -#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ -#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ - -/* TIMER_STATUS Masks */ -#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ -#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ -#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ -#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ -#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ -#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ -#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ -#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 - -/* TIMERx_CONFIG Masks */ -#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ -#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ -#define EXT_CLK 0x0003 /* External Clock Mode */ -#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ -#define PERIOD_CNT 0x0008 /* Period Count */ -#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ -#define TIN_SEL 0x0020 /* Timer Input Select */ -#define OUT_DIS 0x0040 /* Output Pad Disable */ -#define CLK_SEL 0x0080 /* Timer Clock Select */ -#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ -#define EMU_RUN 0x0200 /* Emulation Behavior Select */ -#define ERR_TYP 0xC000 /* Error Type */ - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ -#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ -#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ -#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ -#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ -#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ -#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ - -#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ -#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ -#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ -#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ -#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ -#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ -#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ -#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ -#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ -#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ -#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ -#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ -#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ - -#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ -#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ -#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ -#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ -#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ -#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ -#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ - - -/* ********************** SDRAM CONTROLLER MASKS **********************************************/ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SDRAM Signals */ -#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ -#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ -#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ -#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ -#define EBUFE 0x02000000 /* Enable External Buffering Timing */ -#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ -#define EMREN 0x10000000 /* Extended Mode Register Enable */ -#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ -#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x0001 /* Enable SDRAM External Bank */ -#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ -#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ -#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ -#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ -#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ -#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ -#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x0001 /* SDRAM Controller Idle */ -#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ -#define SDPUA 0x0004 /* SDRAM Power-Up Active */ -#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ -#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ -#define BGSTAT 0x0020 /* Bus Grant Status */ - - -/* ************************** DMA CONTROLLER MASKS ********************************/ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ -#define PMAP_PPI 0x0000 /* PPI Port DMA */ -#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ -#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ -#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ -#define PMAP_SPI 0x7000 /* SPI Port DMA */ -#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ -#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ -#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ -#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ - -/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - - -/* ******************* PIN CONTROL REGISTER MASKS ************************/ -/* PORT_MUX Masks */ -#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ -#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ -#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ - -#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ -#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ -#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ -#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ - -#define PFDE 0x0008 /* Port F DMA Request Enable */ -#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ -#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ - -#define PFTE 0x0010 /* Port F Timer Enable */ -#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ -#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ - -#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ -#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ -#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ - -#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ -#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ -#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ - -#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ -#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ -#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ - -#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ -#define PFFE_TIMER 0x0000 /* Enable TMR2 */ -#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ - -#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ -#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ -#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ - -#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ -#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ -#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ - -#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ -#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ -#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - -/* entry addresses of the user-callable Boot ROM functions */ - -#define _BOOTROM_RESET 0xEF000000 -#define _BOOTROM_FINAL_INIT 0xEF000002 -#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 -#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 -#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A -#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C -#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 -#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 -#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define PGDE_UART PFDE_UART -#define PGDE_DMA PFDE_DMA -#define CKELOW SCKELOW - -/* HOST Port Registers */ - -#define HOST_CONTROL 0xffc03400 /* HOST Control Register */ -#define HOST_STATUS 0xffc03404 /* HOST Status Register */ -#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ - -/* Counter Registers */ - -#define CNT_CONFIG 0xffc03500 /* Configuration Register */ -#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ -#define CNT_STATUS 0xffc03508 /* Status Register */ -#define CNT_COMMAND 0xffc0350c /* Command Register */ -#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ -#define CNT_COUNTER 0xffc03514 /* Counter Register */ -#define CNT_MAX 0xffc03518 /* Maximal Count Register */ -#define CNT_MIN 0xffc0351c /* Minimal Count Register */ - -/* OTP/FUSE Registers */ - -#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ -#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ - -/* Security Registers */ - -#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ -#define SECURE_CONTROL 0xffc03624 /* Secure Control */ -#define SECURE_STATUS 0xffc03628 /* Secure Status */ - -/* OTP Read/Write Data Buffer Registers */ - -#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ - -/* Motor Control PWM Registers */ - -#define PWM_CTRL 0xffc03700 /* PWM Control Register */ -#define PWM_STAT 0xffc03704 /* PWM Status Register */ -#define PWM_TM 0xffc03708 /* PWM Period Register */ -#define PWM_DT 0xffc0370c /* PWM Dead Time Register */ -#define PWM_GATE 0xffc03710 /* PWM Chopping Control */ -#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */ -#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */ -#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */ -#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */ -#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */ -#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ -#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ -#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ -#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */ -#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */ - - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for HOST_CONTROL */ - -#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ -#define HOST_CNTR_nHOST_EN 0x0 -#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ -#define HOST_CNTR_nHOST_END 0x0 -#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ -#define HOST_CNTR_nDATA_SIZE 0x0 -#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ -#define HOST_CNTR_nHOST_RST 0x0 -#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ -#define HOST_CNTR_nHRDY_OVR 0x0 -#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ -#define HOST_CNTR_nINT_MODE 0x0 -#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ -#define HOST_CNTR_ nBT_EN 0x0 -#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ -#define HOST_CNTR_nEHW 0x0 -#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ -#define HOST_CNTR_nEHR 0x0 -#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ -#define HOST_CNTR_nBDR 0x0 - -/* Bit masks for HOST_STATUS */ - -#define HOST_STAT_READY 0x1 /* DMA Ready */ -#define HOST_STAT_nREADY 0x0 -#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ -#define HOST_STAT_nFIFOFULL 0x0 -#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ -#define HOST_STAT_nFIFOEMPTY 0x0 -#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ -#define HOST_STAT_nCOMPLETE 0x0 -#define HOST_STAT_HSHK 0x10 /* Host Handshake */ -#define HOST_STAT_nHSHK 0x0 -#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ -#define HOST_STAT_nTIMEOUT 0x0 -#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ -#define HOST_STAT_nHIRQ 0x0 -#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define HOST_STAT_nALLOW_CNFG 0x0 -#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ -#define HOST_STAT_nDMA_DIR 0x0 -#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ -#define HOST_STAT_nBTE 0x0 -#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ -#define HOST_STAT_nHOSTRD_DONE 0x0 - -/* Bit masks for HOST_TIMEOUT */ - -#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ - -/* Bit masks for SECURE_SYSSWT */ - -#define EMUDABL 0x1 /* Emulation Disable. */ -#define nEMUDABL 0x0 -#define RSTDABL 0x2 /* Reset Disable */ -#define nRSTDABL 0x0 -#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ -#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ -#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ -#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define nDMA0OVR 0x0 -#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define nDMA1OVR 0x0 -#define EMUOVR 0x4000 /* Emulation Override */ -#define nEMUOVR 0x0 -#define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define nOTPSEN 0x0 -#define L2DABL 0x70000 /* L2 Memory Disable. */ - -/* Bit masks for SECURE_CONTROL */ - -#define SECURE0 0x1 /* SECURE 0 */ -#define nSECURE0 0x0 -#define SECURE1 0x2 /* SECURE 1 */ -#define nSECURE1 0x0 -#define SECURE2 0x4 /* SECURE 2 */ -#define nSECURE2 0x0 -#define SECURE3 0x8 /* SECURE 3 */ -#define nSECURE3 0x0 - -/* Bit masks for SECURE_STATUS */ - -#define SECMODE 0x3 /* Secured Mode Control State */ -#define NMI 0x4 /* Non Maskable Interrupt */ -#define nNMI 0x0 -#define AFVALID 0x8 /* Authentication Firmware Valid */ -#define nAFVALID 0x0 -#define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define nAFEXIT 0x0 -#define SECSTAT 0xe0 /* Secure Status */ - -#endif /* _DEF_BF512_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h deleted file mode 100644 index 97feaa629ed7..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/defBF514.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF514_H -#define _DEF_BF514_H - -/* BF514 is BF512 + RSI */ -#include "defBF512.h" - -/* Removable Storage Interface Registers */ - -#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ -#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ -#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ -#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ -#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ -#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ -#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ -#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ -#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ -#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ -#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ -#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ -#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ -#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ -#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ -#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ -#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ -#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ -#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ -#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ -#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ -#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ -#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ -#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ -#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ -#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ -#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ -#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ -#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */ -#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */ -#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */ -#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */ - -#endif /* _DEF_BF514_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h deleted file mode 100644 index 7c79cb6a03b1..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/defBF516.h +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF516_H -#define _DEF_BF516_H - -/* BF516 is BF514 + EMAC */ -#include "defBF514.h" - -/* The following are the #defines needed by ADSP-BF516 that are not in the common header */ -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ - -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ - -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ - -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ - -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ - -/* Listing for IEEE-Supported Count Registers */ - -#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ -#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ -#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ -#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ -#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ -#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ -#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ -#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ -#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ -#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ -#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ -#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ -#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ -#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ -#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ -#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ -#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ -#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ -#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ -#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ -#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ -#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ -#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ -#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ -#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ -#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ -#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ -#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ -#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ -#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ -#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ -#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ -#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ -#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ -#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ -#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ -#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ - -/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ - -/* EMAC_OPMODE Masks */ - -#define RE 0x00000001 /* Receiver Enable */ -#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ -#define HU 0x00000010 /* Hash Filter Unicast Address */ -#define HM 0x00000020 /* Hash Filter Multicast Address */ -#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ -#define PR 0x00000080 /* Promiscuous Mode Enable */ -#define IFE 0x00000100 /* Inverse Filtering Enable */ -#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ -#define PBF 0x00000400 /* Pass Bad Frames Enable */ -#define PSF 0x00000800 /* Pass Short Frames Enable */ -#define RAF 0x00001000 /* Receive-All Mode */ -#define TE 0x00010000 /* Transmitter Enable */ -#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ -#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ -#define DC 0x00080000 /* Deferral Check */ -#define BOLMT 0x00300000 /* Back-Off Limit */ -#define BOLMT_10 0x00000000 /* 10-bit range */ -#define BOLMT_8 0x00100000 /* 8-bit range */ -#define BOLMT_4 0x00200000 /* 4-bit range */ -#define BOLMT_1 0x00300000 /* 1-bit range */ -#define DRTY 0x00400000 /* Disable TX Retry On Collision */ -#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ -#define RMII 0x01000000 /* RMII/MII* Mode */ -#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ -#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ -#define LB 0x08000000 /* Internal Loopback Enable */ -#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ - -/* EMAC_STAADD Masks */ - -#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ -#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ -#define STADISPRE 0x00000004 /* Disable Preamble Generation */ -#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ -#define REGAD 0x000007C0 /* STA Register Address */ -#define PHYAD 0x0000F800 /* PHY Device Address */ - -#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ -#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ - -/* EMAC_STADAT Mask */ - -#define STADATA 0x0000FFFF /* Station Management Data */ - -/* EMAC_FLC Masks */ - -#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ -#define FLCE 0x00000002 /* Flow Control Enable */ -#define PCF 0x00000004 /* Pass Control Frames */ -#define BKPRSEN 0x00000008 /* Enable Backpressure */ -#define FLCPAUSE 0xFFFF0000 /* Pause Time */ - -#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ - -/* EMAC_WKUP_CTL Masks */ - -#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ -#define MPKE 0x00000002 /* Magic Packet Enable */ -#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ -#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ -#define MPKS 0x00000020 /* Magic Packet Received Status */ -#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ - -/* EMAC_WKUP_FFCMD Masks */ - -#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ -#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ -#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ -#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ -#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ -#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ -#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ -#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ - -/* EMAC_WKUP_FFOFF Masks */ - -#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ -#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ -#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ -#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ - -#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ -#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ -#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ -#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ -/* Set ALL Offsets */ -#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) - -/* EMAC_WKUP_FFCRC0 Masks */ - -#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ -#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ - -#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ -#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ - -/* EMAC_WKUP_FFCRC1 Masks */ - -#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ -#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ - -#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ -#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ - -/* EMAC_SYSCTL Masks */ - -#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ -#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ -#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ -#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ -#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ - -#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ - -/* EMAC_SYSTAT Masks */ - -#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ -#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ -#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ -#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ -#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ -#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ -#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ -#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ - -/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ - -#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ -#define RX_COMP 0x00001000 /* RX Frame Complete */ -#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ -#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ -#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ -#define RX_CRC 0x00010000 /* RX Frame CRC Error */ -#define RX_LEN 0x00020000 /* RX Frame Length Error */ -#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ -#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ -#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ -#define RX_PHY 0x00200000 /* RX Frame PHY Error */ -#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ -#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ -#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ -#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ -#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ -#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ -#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ -#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ -#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ -#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ - -/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ - -#define TX_COMP 0x00000001 /* TX Frame Complete */ -#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ -#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ -#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ -#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ -#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ -#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ -#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ -#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ -#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ -#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ -#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ -#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ -#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ -#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ - -/* EMAC_MMC_CTL Masks */ -#define RSTC 0x00000001 /* Reset All Counters */ -#define CROLL 0x00000002 /* Counter Roll-Over Enable */ -#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ -#define MMCE 0x00000008 /* Enable MMC Counter Operation */ - -/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ -#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ -#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ -#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ -#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ -#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ -#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ -#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ -#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ -#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ -#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ -#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ -#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ -#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ -#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ -#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ -#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ -#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ -#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ -#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ -#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ -#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ -#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ -#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ -#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ - -/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ - -#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ -#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ -#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ -#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ -#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ -#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ -#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ -#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ -#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ -#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ -#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ -#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ -#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ -#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ -#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ -#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ -#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ -#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ -#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ -#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ -#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ -#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ -#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ - -#endif /* _DEF_BF516_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h deleted file mode 100644 index 12042ff13601..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/defBF518.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF518_H -#define _DEF_BF518_H - -/* BF518 is BF516 + IEEE-1588 */ -#include "defBF516.h" - -/* PTP TSYNC Registers */ - -#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */ -#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */ -#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */ -#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */ -#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */ -#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */ -#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */ -#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */ -#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */ -#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */ -#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */ -#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */ -#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */ -#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */ -#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */ -#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */ -#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */ -#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */ -#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */ -#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */ -#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */ -#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ -#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ - -/* Bit masks for EMAC_PTP_CTL */ - -#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */ -#define TL 0x2 /* Timestamp lock control */ -#define ASEN 0x10 /* Auxiliary snapshot control */ -#define PPSEN 0x80 /* Pulse-per-second (PPS) control */ -#define CKOEN 0x2000 /* Clock output control */ - -/* Bit masks for EMAC_PTP_IE */ - -#define ALIE 0x1 /* Alarm interrupt enable */ -#define RXEIE 0x2 /* Receive event interrupt enable */ -#define RXGIE 0x4 /* Receive general interrupt enable */ -#define TXIE 0x8 /* Transmit interrupt enable */ -#define RXOVE 0x10 /* Receive overrun error interrupt enable */ -#define TXOVE 0x20 /* Transmit overrun error interrupt enable */ -#define ASIE 0x40 /* Auxiliary snapshot interrupt enable */ - -/* Bit masks for EMAC_PTP_ISTAT */ - -#define ALS 0x1 /* Alarm status */ -#define RXEL 0x2 /* Receive event interrupt status */ -#define RXGL 0x4 /* Receive general interrupt status */ -#define TXTL 0x8 /* Transmit snapshot status */ -#define RXOV 0x10 /* Receive snapshot overrun status */ -#define TXOV 0x20 /* Transmit snapshot overrun status */ -#define ASL 0x40 /* Auxiliary snapshot interrupt status */ - -#endif /* _DEF_BF518_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/dma.h b/arch/blackfin/mach-bf518/include/mach/dma.h deleted file mode 100644 index bbd33c1706e2..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/dma.h +++ /dev/null @@ -1,33 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define MAX_DMA_CHANNELS 16 - -#define CH_PPI 0 /* PPI receive/transmit */ -#define CH_EMAC_RX 1 /* Ethernet MAC receive */ -#define CH_EMAC_TX 2 /* Ethernet MAC transmit */ -#define CH_SPORT0_RX 3 /* SPORT0 receive */ -#define CH_SPORT0_TX 4 /* SPORT0 transmit */ -#define CH_RSI 4 /* RSI */ -#define CH_SPORT1_RX 5 /* SPORT1 receive */ -#define CH_SPI1 5 /* SPI1 transmit/receive */ -#define CH_SPORT1_TX 6 /* SPORT1 transmit */ -#define CH_SPI0 7 /* SPI0 transmit/receive */ -#define CH_UART0_RX 8 /* UART0 receive */ -#define CH_UART0_TX 9 /* UART0 transmit */ -#define CH_UART1_RX 10 /* UART1 receive */ -#define CH_UART1_TX 11 /* UART1 transmit */ - -#define CH_MEM_STREAM0_SRC 12 /* RX */ -#define CH_MEM_STREAM0_DEST 13 /* TX */ -#define CH_MEM_STREAM1_SRC 14 /* RX */ -#define CH_MEM_STREAM1_DEST 15 /* TX */ - -#endif diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h deleted file mode 100644 index b480705bfc2e..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/gpio.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 41 - -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 -#define GPIO_PG0 16 -#define GPIO_PG1 17 -#define GPIO_PG2 18 -#define GPIO_PG3 19 -#define GPIO_PG4 20 -#define GPIO_PG5 21 -#define GPIO_PG6 22 -#define GPIO_PG7 23 -#define GPIO_PG8 24 -#define GPIO_PG9 25 -#define GPIO_PG10 26 -#define GPIO_PG11 27 -#define GPIO_PG12 28 -#define GPIO_PG13 29 -#define GPIO_PG14 30 -#define GPIO_PG15 31 -#define GPIO_PH0 32 -#define GPIO_PH1 33 -#define GPIO_PH2 34 -#define GPIO_PH3 35 -#define GPIO_PH4 36 -#define GPIO_PH5 37 -#define GPIO_PH6 38 -#define GPIO_PH7 39 -#define GPIO_PH8 40 - -#define PORT_F GPIO_PF0 -#define PORT_G GPIO_PG0 -#define PORT_H GPIO_PH0 - -#include -#include -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h deleted file mode 100644 index edf8efd457dc..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/irq.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BF518_IRQ_H_ -#define _BF518_IRQ_H_ - -#include - -#define NR_PERI_INTS (2 * 32) - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ -#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ -#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */ -#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */ -#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */ -#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */ -#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */ -#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */ -#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */ -#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */ -#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ -#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ -#define IRQ_RTC BFIN_IRQ(14) /* RTC */ -#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */ -#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ -#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ -#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */ -#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */ -#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */ -#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ -#define IRQ_TWI BFIN_IRQ(20) /* TWI */ -#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */ -#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ -#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ -#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ -#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ -#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ -#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ -#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */ -#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ -#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */ -#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ -#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ -#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ -#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ -#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ -#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ -#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ -#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ -#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ -#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ -#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ -#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ -#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */ -#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */ -#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */ -#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */ -#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */ -#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */ -#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */ -#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */ -#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */ -#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */ -#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */ - -#define SYS_IRQS BFIN_IRQ(63) /* 70 */ - -#define IRQ_PF0 71 -#define IRQ_PF1 72 -#define IRQ_PF2 73 -#define IRQ_PF3 74 -#define IRQ_PF4 75 -#define IRQ_PF5 76 -#define IRQ_PF6 77 -#define IRQ_PF7 78 -#define IRQ_PF8 79 -#define IRQ_PF9 80 -#define IRQ_PF10 81 -#define IRQ_PF11 82 -#define IRQ_PF12 83 -#define IRQ_PF13 84 -#define IRQ_PF14 85 -#define IRQ_PF15 86 - -#define IRQ_PG0 87 -#define IRQ_PG1 88 -#define IRQ_PG2 89 -#define IRQ_PG3 90 -#define IRQ_PG4 91 -#define IRQ_PG5 92 -#define IRQ_PG6 93 -#define IRQ_PG7 94 -#define IRQ_PG8 95 -#define IRQ_PG9 96 -#define IRQ_PG10 97 -#define IRQ_PG11 98 -#define IRQ_PG12 99 -#define IRQ_PG13 100 -#define IRQ_PG14 101 -#define IRQ_PG15 102 - -#define IRQ_PH0 103 -#define IRQ_PH1 104 -#define IRQ_PH2 105 -#define IRQ_PH3 106 -#define IRQ_PH4 107 -#define IRQ_PH5 108 -#define IRQ_PH6 109 -#define IRQ_PH7 110 -#define IRQ_PH8 111 -#define IRQ_PH9 112 -#define IRQ_PH10 113 -#define IRQ_PH11 114 -#define IRQ_PH12 115 -#define IRQ_PH13 116 -#define IRQ_PH14 117 -#define IRQ_PH15 118 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ -#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ -#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ -#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ -#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ -#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ -#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ -#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ - -#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) - -/* IAR0 BIT FIELDS */ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA0_ERROR_POS 4 -#define IRQ_DMAR0_BLK_POS 8 -#define IRQ_DMAR1_BLK_POS 12 -#define IRQ_DMAR0_OVR_POS 16 -#define IRQ_DMAR1_OVR_POS 20 -#define IRQ_PPI_ERROR_POS 24 -#define IRQ_MAC_ERROR_POS 28 - -/* IAR1 BIT FIELDS */ -#define IRQ_SPORT0_ERROR_POS 0 -#define IRQ_SPORT1_ERROR_POS 4 -#define IRQ_PTP_ERROR_POS 8 -#define IRQ_UART0_ERROR_POS 16 -#define IRQ_UART1_ERROR_POS 20 -#define IRQ_RTC_POS 24 -#define IRQ_PPI_POS 28 - -/* IAR2 BIT FIELDS */ -#define IRQ_SPORT0_RX_POS 0 -#define IRQ_SPORT0_TX_POS 4 -#define IRQ_RSI_POS 4 -#define IRQ_SPORT1_RX_POS 8 -#define IRQ_SPI1_POS 8 -#define IRQ_SPORT1_TX_POS 12 -#define IRQ_TWI_POS 16 -#define IRQ_SPI0_POS 20 -#define IRQ_UART0_RX_POS 24 -#define IRQ_UART0_TX_POS 28 - -/* IAR3 BIT FIELDS */ -#define IRQ_UART1_RX_POS 0 -#define IRQ_UART1_TX_POS 4 -#define IRQ_OPTSEC_POS 8 -#define IRQ_CNT_POS 12 -#define IRQ_MAC_RX_POS 16 -#define IRQ_PORTH_INTA_POS 20 -#define IRQ_MAC_TX_POS 24 -#define IRQ_PORTH_INTB_POS 28 - -/* IAR4 BIT FIELDS */ -#define IRQ_TIMER0_POS 0 -#define IRQ_TIMER1_POS 4 -#define IRQ_TIMER2_POS 8 -#define IRQ_TIMER3_POS 12 -#define IRQ_TIMER4_POS 16 -#define IRQ_TIMER5_POS 20 -#define IRQ_TIMER6_POS 24 -#define IRQ_TIMER7_POS 28 - -/* IAR5 BIT FIELDS */ -#define IRQ_PORTG_INTA_POS 0 -#define IRQ_PORTG_INTB_POS 4 -#define IRQ_MEM_DMA0_POS 8 -#define IRQ_MEM_DMA1_POS 12 -#define IRQ_WATCH_POS 16 -#define IRQ_PORTF_INTA_POS 20 -#define IRQ_PORTF_INTB_POS 24 -#define IRQ_SPI0_ERROR_POS 28 - -/* IAR6 BIT FIELDS */ -#define IRQ_SPI1_ERROR_POS 0 -#define IRQ_RSI_INT0_POS 12 -#define IRQ_RSI_INT1_POS 16 -#define IRQ_PWM_TRIP_POS 20 -#define IRQ_PWM_SYNC_POS 24 -#define IRQ_PTP_STAT_POS 28 - -#endif diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h deleted file mode 100644 index 073b5d73d391..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/mem_map.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * BF51x memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x8000 - -/* Level 1 Memory */ - -/* Memory Map for ADSP-BF518/6/4/2 processors */ - -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16 * 1024) -#else -#define BFIN_ICACHESIZE (0) -#endif - -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#define L1_CODE_LENGTH 0x8000 - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16 * 1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32 * 1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE 0 -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE */ - -#endif diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h deleted file mode 100644 index 94cca674d835..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h deleted file mode 100644 index b3b806f468da..000000000000 --- a/arch/blackfin/mach-bf518/include/mach/portmux.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define MAX_RESOURCES MAX_BLACKFIN_GPIOS - -/* EMAC MII/RMII Port Mux */ -#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) -#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) -#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) -#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) -#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) -#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) -#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) - -#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) -#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) -#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) -#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) -#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) -#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) -#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) -#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) -#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) -#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) -#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) - -#define P_MII0 {\ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxD2, \ - P_MII0_ETxD3, \ - P_MII0_ETxEN, \ - P_MII0_TxCLK, \ - P_MII0_PHYINT, \ - P_MII0_COL, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxD2, \ - P_MII0_ERxD3, \ - P_MII0_ERxDV, \ - P_MII0_ERxCLK, \ - P_MII0_ERxER, \ - P_MII0_CRS, \ - P_MII0_MDC, \ - P_MII0_MDIO, 0} - -#define P_RMII0 {\ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxEN, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxER, \ - P_MII0_TxCLK, \ - P_MII0_PHYINT, \ - P_MII0_CRS, \ - P_MII0_MDC, \ - P_MII0_MDIO, 0} - -/* PPI Port Mux */ -#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) -#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) -#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) -#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) - -#ifndef CONFIG_BF518_PPI_TMR_PG12 -#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) -#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) -#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) -#else -#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) -#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) -#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) -#endif -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) - -/* SPI Port Mux */ -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) -#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) -#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) -#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) - -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) - -#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) -#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) -#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) -#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) - -#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2)) -#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) -#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2)) -#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2)) -#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) - -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 - -/* SPORT Port Mux */ -#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) -#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) -#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) -#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) -#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) -#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) -#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) - -#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) -#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) -#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) -#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) -#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) -#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) -#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) -#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) - -/* UART Port Mux */ -#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) -#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) - -#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) -#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) - -/* Timer */ -#ifndef CONFIG_BF518_PPI_TMR_PG12 -#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) -#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) -#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) -#else -#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) -#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) -#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) -#endif -#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) -#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) -#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2)) -#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) -#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) -#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2)) - -/* DMA */ -#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1)) -#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) - -/* TWI */ -#define P_TWI0_SCL (P_DONTCARE) -#define P_TWI0_SDA (P_DONTCARE) - -/* PWM */ -#ifndef CONFIG_BF518_PWM_PORTF_PORTG -#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) -#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) -#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) -#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) -#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) -#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) -#else -#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) -#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) -#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) -#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) -#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) -#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) -#endif - -#ifndef CONFIG_BF518_PWM_SYNC_PF15 -#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) -#else -#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) -#endif - -#ifndef CONFIG_BF518_PWM_TRIPB_PG14 -#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2)) -#else -#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) -#endif - -/* RSI */ -#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) -#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) -#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) -#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) -#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2)) -#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2)) -#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) -#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) -#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) -#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) - -/* PTP */ -#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) -#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) - -/* AMS */ -#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) -#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) - -#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1)) - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c deleted file mode 100644 index bb05bef34ec0..000000000000 --- a/arch/blackfin/mach-bf518/ints-priority.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | - ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) | - ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) | - ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) | - ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) | - ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) | - ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) | - ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS)); - - - bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | - ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) | - ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) | - ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) | - ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) | - ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) | - ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS)); - - bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | - ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | - ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | - ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | - ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) | - ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) | - ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | - ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); - - bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | - ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | - ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) | - ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) | - ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) | - ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) | - ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | - ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); - - bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | - ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | - ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | - ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | - ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | - ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | - ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | - ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS)); - - bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | - ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | - ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) | - ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) | - ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) | - ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) | - ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) | - ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS)); - - bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) | - ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) | - ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) | - ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) | - ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) | - ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS)); - - SSYNC(); -} diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig deleted file mode 100644 index 6df20f9c7bd4..000000000000 --- a/arch/blackfin/mach-bf527/Kconfig +++ /dev/null @@ -1,325 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config BF52x - def_bool y - depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) - -if (BF52x) - -source "arch/blackfin/mach-bf527/boards/Kconfig" - -menu "BF527 Specific Configuration" - -comment "Alternative Multiplexing Scheme" - -choice - prompt "SPORT0" - default BF527_SPORT0_PORTG - help - Select PORT used for SPORT0. See Hardware Reference Manual - -config BF527_SPORT0_PORTF - bool "PORT F" - help - PORT F - -config BF527_SPORT0_PORTG - bool "PORT G" - help - PORT G -endchoice - -choice - prompt "SPORT0 TSCLK Location" - depends on BF527_SPORT0_PORTG - default BF527_SPORT0_TSCLK_PG10 - help - Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual - -config BF527_SPORT0_TSCLK_PG10 - bool "PORT PG10" - help - PORT PG10 - -config BF527_SPORT0_TSCLK_PG14 - bool "PORT PG14" - help - PORT PG14 -endchoice - -choice - prompt "UART1" - default BF527_UART1_PORTF - help - Select PORT used for UART1. See Hardware Reference Manual - -config BF527_UART1_PORTF - bool "PORT F" - help - PORT F - -config BF527_UART1_PORTG - bool "PORT G" - help - PORT G -endchoice - -choice - prompt "NAND (NFC) Data" - default BF527_NAND_D_PORTH - help - Select PORT used for NAND Data Bus. See Hardware Reference Manual - -config BF527_NAND_D_PORTF - bool "PORT F" - help - PORT F - -config BF527_NAND_D_PORTH - bool "PORT H" - help - PORT H -endchoice - -comment "Hysteresis/Schmitt Trigger Control" -config BFIN_HYSTERESIS_CONTROL - bool "Enable Hysteresis Control" - help - The ADSP-BF52x allows to control input hysteresis for Port F, - Port G and Port H and other processor signal inputs. - The Schmitt trigger enables can be set only for pin groups. - Saying Y will overwrite the default reset or boot loader - initialization. - -menu "PORT F" - depends on BFIN_HYSTERESIS_CONTROL -config GPIO_HYST_PORTF_0_7 - bool "Enable Hysteresis on PORTF {0...7}" -config GPIO_HYST_PORTF_8_9 - bool "Enable Hysteresis on PORTF {8, 9}" -config GPIO_HYST_PORTF_10 - bool "Enable Hysteresis on PORTF 10" -config GPIO_HYST_PORTF_11 - bool "Enable Hysteresis on PORTF 11" -config GPIO_HYST_PORTF_12_13 - bool "Enable Hysteresis on PORTF {12, 13}" -config GPIO_HYST_PORTF_14_15 - bool "Enable Hysteresis on PORTF {14, 15}" -endmenu - -menu "PORT G" - depends on BFIN_HYSTERESIS_CONTROL -config GPIO_HYST_PORTG_0 - bool "Enable Hysteresis on PORTG 0" -config GPIO_HYST_PORTG_1_4 - bool "Enable Hysteresis on PORTG {1...4}" -config GPIO_HYST_PORTG_5_6 - bool "Enable Hysteresis on PORTG {5, 6}" -config GPIO_HYST_PORTG_7_8 - bool "Enable Hysteresis on PORTG {7, 8}" -config GPIO_HYST_PORTG_9 - bool "Enable Hysteresis on PORTG 9" -config GPIO_HYST_PORTG_10 - bool "Enable Hysteresis on PORTG 10" -config GPIO_HYST_PORTG_11_13 - bool "Enable Hysteresis on PORTG {11...13}" -config GPIO_HYST_PORTG_14_15 - bool "Enable Hysteresis on PORTG {14, 15}" -endmenu - -menu "PORT H" - depends on BFIN_HYSTERESIS_CONTROL -config GPIO_HYST_PORTH_0_7 - bool "Enable Hysteresis on PORTH {0...7}" -config GPIO_HYST_PORTH_8 - bool "Enable Hysteresis on PORTH 8" -config GPIO_HYST_PORTH_9_15 - bool "Enable Hysteresis on PORTH {9...15}" -endmenu - -menu "None-GPIO" - depends on BFIN_HYSTERESIS_CONTROL -config NONEGPIO_HYST_TMR0_FS1_PPICLK - bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}" -config NONEGPIO_HYST_NMI_RST_BMODE - bool "Enable Hysteresis on {NMI, RESET, BMODE}" -config NONEGPIO_HYST_JTAG - bool "Enable Hysteresis on JTAG" -endmenu - -comment "Interrupt Priority Assignment" -menu "Priority" - -config IRQ_PLL_WAKEUP - int "IRQ_PLL_WAKEUP" - default 7 -config IRQ_DMA0_ERROR - int "IRQ_DMA0_ERROR" - default 7 -config IRQ_DMAR0_BLK - int "IRQ_DMAR0_BLK" - default 7 -config IRQ_DMAR1_BLK - int "IRQ_DMAR1_BLK" - default 7 -config IRQ_DMAR0_OVR - int "IRQ_DMAR0_OVR" - default 7 -config IRQ_DMAR1_OVR - int "IRQ_DMAR1_OVR" - default 7 -config IRQ_PPI_ERROR - int "IRQ_PPI_ERROR" - default 7 -config IRQ_MAC_ERROR - int "IRQ_MAC_ERROR" - default 7 -config IRQ_SPORT0_ERROR - int "IRQ_SPORT0_ERROR" - default 7 -config IRQ_SPORT1_ERROR - int "IRQ_SPORT1_ERROR" - default 7 -config IRQ_UART0_ERROR - int "IRQ_UART0_ERROR" - default 7 -config IRQ_UART1_ERROR - int "IRQ_UART1_ERROR" - default 7 -config IRQ_RTC - int "IRQ_RTC" - default 8 -config IRQ_PPI - int "IRQ_PPI" - default 8 -config IRQ_SPORT0_RX - int "IRQ_SPORT0_RX" - default 9 -config IRQ_SPORT0_TX - int "IRQ_SPORT0_TX" - default 9 -config IRQ_SPORT1_RX - int "IRQ_SPORT1_RX" - default 9 -config IRQ_SPORT1_TX - int "IRQ_SPORT1_TX" - default 9 -config IRQ_TWI - int "IRQ_TWI" - default 10 -config IRQ_SPI - int "IRQ_SPI" - default 10 -config IRQ_UART0_RX - int "IRQ_UART0_RX" - default 10 -config IRQ_UART0_TX - int "IRQ_UART0_TX" - default 10 -config IRQ_UART1_RX - int "IRQ_UART1_RX" - default 10 -config IRQ_UART1_TX - int "IRQ_UART1_TX" - default 10 -config IRQ_OPTSEC - int "IRQ_OPTSEC" - default 11 -config IRQ_CNT - int "IRQ_CNT" - default 11 -config IRQ_MAC_RX - int "IRQ_MAC_RX" - default 11 -config IRQ_PORTH_INTA - int "IRQ_PORTH_INTA" - default 11 -config IRQ_MAC_TX - int "IRQ_MAC_TX/NFC" - default 11 -config IRQ_PORTH_INTB - int "IRQ_PORTH_INTB" - default 11 -config IRQ_TIMER0 - int "IRQ_TIMER0" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config IRQ_TIMER1 - int "IRQ_TIMER1" - default 12 -config IRQ_TIMER2 - int "IRQ_TIMER2" - default 12 -config IRQ_TIMER3 - int "IRQ_TIMER3" - default 12 -config IRQ_TIMER4 - int "IRQ_TIMER4" - default 12 -config IRQ_TIMER5 - int "IRQ_TIMER5" - default 12 -config IRQ_TIMER6 - int "IRQ_TIMER6" - default 12 -config IRQ_TIMER7 - int "IRQ_TIMER7" - default 12 -config IRQ_PORTG_INTA - int "IRQ_PORTG_INTA" - default 12 -config IRQ_PORTG_INTB - int "IRQ_PORTG_INTB" - default 12 -config IRQ_MEM_DMA0 - int "IRQ_MEM_DMA0" - default 13 -config IRQ_MEM_DMA1 - int "IRQ_MEM_DMA1" - default 13 -config IRQ_WATCH - int "IRQ_WATCH" - default 13 -config IRQ_PORTF_INTA - int "IRQ_PORTF_INTA" - default 13 -config IRQ_PORTF_INTB - int "IRQ_PORTF_INTB" - default 13 -config IRQ_SPI_ERROR - int "IRQ_SPI_ERROR" - default 7 -config IRQ_NFC_ERROR - int "IRQ_NFC_ERROR" - default 7 -config IRQ_HDMA_ERROR - int "IRQ_HDMA_ERROR" - default 7 -config IRQ_HDMA - int "IRQ_HDMA" - default 7 -config IRQ_USB_EINT - int "IRQ_USB_EINT" - default 10 -config IRQ_USB_INT0 - int "IRQ_USB_INT0" - default 10 -config IRQ_USB_INT1 - int "IRQ_USB_INT1" - default 10 -config IRQ_USB_INT2 - int "IRQ_USB_INT2" - default 10 -config IRQ_USB_DMA - int "IRQ_USB_DMA" - default 10 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile deleted file mode 100644 index 4a6cdafab8ce..000000000000 --- a/arch/blackfin/mach-bf527/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf527/Makefile -# - -obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig deleted file mode 100644 index a76f02fae11c..000000000000 --- a/arch/blackfin/mach-bf527/boards/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN527_EZKIT - help - Select your board! - -config BFIN527_EZKIT - bool "BF527-EZKIT" - help - BF527-EZKIT-LITE board support. - -config BFIN527_EZKIT_V2 - bool "BF527-EZKIT-V2" - help - BF527-EZKIT-LITE V2.1+ board support. - -config BFIN527_BLUETECHNIX_CM - bool "Bluetechnix CM-BF527" - help - CM-BF527 support for EVAL- and DEV-Board. - -config BFIN526_EZBRD - bool "BF526-EZBRD" - help - BF526-EZBRD/EZKIT Lite board support. - -config BFIN527_AD7160EVAL - bool "BF527-AD7160-EVAL" - help - BF527-AD7160-EVAL board support. - -config BFIN527_TLL6527M - bool "The Learning Labs TLL6527M" - help - TLL6527M V1.0 platform support - -endchoice diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile deleted file mode 100644 index 6ada1537e20a..000000000000 --- a/arch/blackfin/mach-bf527/boards/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/mach-bf527/boards/Makefile -# - -obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o -obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o -obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o -obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o -obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o -obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c deleted file mode 100644 index 68f2a8a806ea..000000000000 --- a/arch/blackfin/mach-bf527/boards/ad7160eval.c +++ /dev/null @@ -1,868 +0,0 @@ -/* - * Copyright 2004-20010 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF527-AD7160EVAL"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xffc03800, - .end = 0xffc03cff, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_INT0, - .end = IRQ_USB_INT0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 0, - .dyn_fifo = 0, - .soft_con = 1, - .dma = 1, - .num_eps = 8, - .dma_channels = 8, - .gpio_vrsel = GPIO_PG13, - /* Some custom boards need to be active low, just set it to "0" - * if it is the case. - */ - .gpio_vrsel_active = 1, - .clkin = 24, /* musb CLKIN in MHZ */ -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_OTG) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC_HCD) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z) -static struct resource bf52x_ra158z_resources[] = { - { - .start = IRQ_PPI_ERROR, - .end = IRQ_PPI_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf52x_ra158z_device = { - .name = "bfin-ra158z", - .id = -1, - .num_resources = ARRAY_SIZE(bf52x_ra158z_resources), - .resource = bf52x_ra158z_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ad7160eval_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x1C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data ad7160eval_flash_data = { - .width = 2, - .parts = ad7160eval_partitions, - .nr_parts = ARRAY_SIZE(ad7160eval_partitions), -}; - -static struct resource ad7160eval_flash_resource = { - .start = 0x20000000, - .end = 0x203fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ad7160eval_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ad7160eval_flash_data, - }, - .num_resources = 1, - .resource = &ad7160eval_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) -static struct mtd_partition partition_info[] = { - { - .name = "linux kernel(nand)", - .offset = 0, - .size = 4 * 1024 * 1024, - }, - { - .name = "file system(nand)", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct bf5xx_nand_platform bf5xx_nand_platform = { - .data_width = NFC_NWIDTH_8, - .partitions = partition_info, - .nr_partitions = ARRAY_SIZE(partition_info), - .rd_dly = 3, - .wr_dly = 3, -}; - -static struct resource bf5xx_nand_resources[] = { - { - .start = NFC_CTL, - .end = NFC_DATA_RD + 2, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_NFC, - .end = CH_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf5xx_nand_device = { - .name = "bf5xx-nand", - .id = 0, - .num_resources = ARRAY_SIZE(bf5xx_nand_resources), - .resource = bf5xx_nand_resources, - .dev = { - .platform_data = &bf5xx_nand_platform, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_RMII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_RMII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = GPIO_PH3 + MAX_CTRL_CS, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin */ - .start = GPIO_PF9, - .end = GPIO_PF9, - .flags = IORESOURCE_IO, - }, - { /* RTS pin */ - .start = GPIO_PF10, - .end = GPIO_PF10, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160) -#include -static const struct ad7160_platform_data bfin_ad7160_ts_info = { - .sensor_x_res = 854, - .sensor_y_res = 480, - .pressure = 100, - .filter_coef = 3, - .coord_pref = AD7160_ORIG_TOP_LEFT, - .first_touch_window = 5, - .move_window = 3, - .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID | - AD7160_EMIT_ABS_MT_PRESSURE | - AD7160_TRACKING_ID_ASCENDING, - .finger_act_ctrl = 0x64, - .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) | - AD7160_HAPTIC_SLOT_A_LVL_HIGH | - AD7160_HAPTIC_SLOT_B(60) | - AD7160_HAPTIC_SLOT_B_LVL_LOW, - - .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) | - AD7160_HAPTIC_SLOT_A_LVL_HIGH | - AD7160_HAPTIC_SLOT_B(80) | - AD7160_HAPTIC_SLOT_B_LVL_LOW | - AD7160_HAPTIC_SLOT_C(120) | - AD7160_HAPTIC_SLOT_C_LVL_HIGH | - AD7160_HAPTIC_SLOT_D(30) | - AD7160_HAPTIC_SLOT_D_LVL_LOW, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160) - { - I2C_BOARD_INFO("ad7160", 0x33), - .irq = IRQ_PH1, - .platform_data = (void *)&bfin_ad7160_ts_info, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) -#include - -static const u16 per_cnt[] = { - P_CNT_CUD, - P_CNT_CDG, - P_CNT_CZM, - 0 -}; - -static struct bfin_rotary_platform_data bfin_rotary_data = { - /*.rotary_up_key = KEY_UP,*/ - /*.rotary_down_key = KEY_DOWN,*/ - .rotary_rel_code = REL_WHEEL, - .rotary_button_key = KEY_ENTER, - .debounce = 10, /* 0..17 */ - .mode = ROT_QUAD_ENC | ROT_DEBE, - .pm_wakeup = 1, - .pin_list = per_cnt, -}; - -static struct resource bfin_rotary_resources[] = { - { - .start = CNT_CONFIG, - .end = CNT_CONFIG + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CNT, - .end = IRQ_CNT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_rotary_device = { - .name = "bfin-rotary", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_rotary_resources), - .resource = bfin_rotary_resources, - .dev = { - .platform_data = &bfin_rotary_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = { - VRPAIR(VLEV_100, 400000000), - VRPAIR(VLEV_105, 426000000), - VRPAIR(VLEV_110, 500000000), - VRPAIR(VLEV_115, 533000000), - VRPAIR(VLEV_120, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) - &bf5xx_nand_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z) - &bf52x_ra158z_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) - &bfin_rotary_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ad7160eval_flash_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif -}; - -static int __init ad7160eval_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(ad7160eval_init); - -static struct platform_device *ad7160eval_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ad7160eval_early_devices, - ARRAY_SIZE(ad7160eval_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -int bfin_get_ether_addr(char *addr) -{ - /* the MAC is stored in OTP memory page 0xDF */ - u32 ret; - u64 otp_mac; - u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; - - ret = otp_read(0xDF, 0x00, &otp_mac); - if (!(ret & 0x1)) { - char *otp_mac_p = (char *)&otp_mac; - for (ret = 0; ret < 6; ++ret) - addr[ret] = otp_mac_p[5 - ret]; - } - return 0; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c deleted file mode 100644 index b1004b35db36..000000000000 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ /dev/null @@ -1,992 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix CM-BF527"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x203C0000, - .end = 0x203C0000 + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xffc03800, - .end = 0xffc03cff, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_INT0, - .end = IRQ_USB_INT0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "mc" - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "dma" - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 0, - .dyn_fifo = 0, - .soft_con = 1, - .dma = 1, - .num_eps = 8, - .dma_channels = 8, - .gpio_vrsel = GPIO_PF11, - /* Some custom boards need to be active low, just set it to "0" - * if it is the case. - */ - .gpio_vrsel_active = 1, - .clkin = 24, /* musb CLKIN in MHZ */ -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_OTG) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC_HCD) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) -static struct mtd_partition partition_info[] = { - { - .name = "linux kernel(nand)", - .offset = 0, - .size = 4 * 1024 * 1024, - }, - { - .name = "file system(nand)", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct bf5xx_nand_platform bf5xx_nand_platform = { - .data_width = NFC_NWIDTH_8, - .partitions = partition_info, - .nr_partitions = ARRAY_SIZE(partition_info), - .rd_dly = 3, - .wr_dly = 3, -}; - -static struct resource bf5xx_nand_resources[] = { - { - .start = NFC_CTL, - .end = NFC_DATA_RD + 2, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_NFC, - .end = CH_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf5xx_nand_device = { - .name = "bf5xx-nand", - .id = 0, - .num_resources = ARRAY_SIZE(bf5xx_nand_resources), - .resource = bf5xx_nand_resources, - .dev = { - .platform_data = &bf5xx_nand_platform, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) -static struct resource bfin_pcmcia_cf_resources[] = { - { - .start = 0x20310000, /* IO PORT */ - .end = 0x20312000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20311000, /* Attribute Memory */ - .end = 0x20311FFF, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, { - .start = 6, /* Card Detect PF6 */ - .end = 6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pcmcia_cf_device = { - .name = "bfin_cf_pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), - .resource = bfin_pcmcia_cf_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_DM9000) -static struct resource dm9000_resources[] = { - [0] = { - .start = 0x203FB800, - .end = 0x203FB800 + 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x203FB804, - .end = 0x203FB804 + 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), - }, -}; - -static struct platform_device dm9000_device = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(dm9000_resources), - .resource = dm9000_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_RMII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_RMII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PF8, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \ - && defined(CONFIG_SND_SOC_WM8731_SPI) - { - .modalias = "wm8731", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) -static struct mtd_partition cm_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data cm_flash_data = { - .width = 2, - .parts = cm_partitions, - .nr_parts = ARRAY_SIZE(cm_partitions), -}; - -static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 }; - -static struct resource cm_flash_resource[] = { - { - .name = "cfi_probe", - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, - }, { - .start = (unsigned long)cm_flash_gpios, - .end = ARRAY_SIZE(cm_flash_gpios), - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device cm_flash_device = { - .name = "gpio-addr-flash", - .id = 0, - .dev = { - .platform_data = &cm_flash_data, - }, - .num_resources = ARRAY_SIZE(cm_flash_resource), - .resource = cm_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin */ - .start = GPIO_PF9, - .end = GPIO_PF9, - .flags = IORESOURCE_IO, - }, - { /* RTS pin */ - .start = GPIO_PF10, - .end = GPIO_PF10, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = IRQ_PF8, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_100, 400000000), - VRPAIR(VLEV_105, 426000000), - VRPAIR(VLEV_110, 500000000), - VRPAIR(VLEV_115, 533000000), - VRPAIR(VLEV_120, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cmbf527_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) - &bf5xx_nand_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) - &bfin_pcmcia_cf_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) - &bfin_isp1760_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_DM9000) - &dm9000_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) - &cm_flash_device, -#endif -}; - -static int __init cm_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(cm_init); - -static struct platform_device *cmbf527_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cmbf527_early_devices, - ARRAY_SIZE(cmbf527_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -int bfin_get_ether_addr(char *addr) -{ - return 1; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c deleted file mode 100644 index 80bcfd1d023e..000000000000 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ /dev/null @@ -1,891 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF526-EZBRD"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xffc03800, - .end = 0xffc03cff, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_INT0, - .end = IRQ_USB_INT0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "mc" - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "dma" - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 0, - .dyn_fifo = 0, - .soft_con = 1, - .dma = 1, - .num_eps = 8, - .dma_channels = 8, - .gpio_vrsel = GPIO_PG13, - /* Some custom boards need to be active low, just set it to "0" - * if it is the case. - */ - .gpio_vrsel_active = 1, - .clkin = 24, /* musb CLKIN in MHZ */ -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_OTG) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC_HCD) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezbrd_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x1C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data ezbrd_flash_data = { - .width = 2, - .parts = ezbrd_partitions, - .nr_parts = ARRAY_SIZE(ezbrd_partitions), -}; - -static struct resource ezbrd_flash_resource = { - .start = 0x20000000, - .end = 0x203fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezbrd_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezbrd_flash_data, - }, - .num_resources = 1, - .resource = &ezbrd_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) -static struct mtd_partition partition_info[] = { - { - .name = "bootloader(nand)", - .offset = 0, - .size = 0x40000, - }, { - .name = "linux kernel(nand)", - .offset = MTDPART_OFS_APPEND, - .size = 4 * 1024 * 1024, - }, - { - .name = "file system(nand)", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct bf5xx_nand_platform bf5xx_nand_platform = { - .data_width = NFC_NWIDTH_8, - .partitions = partition_info, - .nr_partitions = ARRAY_SIZE(partition_info), - .rd_dly = 3, - .wr_dly = 3, -}; - -static struct resource bf5xx_nand_resources[] = { - { - .start = NFC_CTL, - .end = NFC_DATA_RD + 2, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_NFC, - .end = CH_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf5xx_nand_device = { - .name = "bf5xx-nand", - .id = 0, - .num_resources = ARRAY_SIZE(bf5xx_nand_resources), - .resource = bf5xx_nand_resources, - .dev = { - .platform_data = &bf5xx_nand_platform, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_RMII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_RMII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "sst25wf040", -}; - -/* SPI flash chip (sst25wf040) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) -#include -static const struct ad7879_platform_data bfin_ad7879_ts_info = { - .model = 7879, /* Model = AD7879 */ - .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ - .pressure_max = 10000, - .pressure_min = 0, - .first_conversion_delay = 3, /* wait 512us before do a first conversion */ - .acquisition_time = 1, /* 4us acquisition time per sample */ - .median = 2, /* do 8 measurements */ - .averaging = 1, /* take the average of 4 middle samples */ - .pen_down_acc_interval = 255, /* 9.4 ms */ - .gpio_export = 1, /* Export GPIO to gpiolib */ - .gpio_base = -1, /* Dynamic allocation */ -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PF8, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI) - { - .modalias = "ad7879", - .platform_data = &bfin_ad7879_ts_info, - .irq = IRQ_PG0, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \ - && defined(CONFIG_SND_SOC_WM8731_SPI) - { - .modalias = "wm8731", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - { - .modalias = "bfin-lq035q1-spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin */ - .start = GPIO_PG0, - .end = GPIO_PG0, - .flags = IORESOURCE_IO, - }, - { /* RTS pin */ - .start = GPIO_PF10, - .end = GPIO_PF10, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = IRQ_PF8, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_100, 400000000), - VRPAIR(VLEV_105, 426000000), - VRPAIR(VLEV_110, 500000000), - VRPAIR(VLEV_115, 533000000), - VRPAIR(VLEV_120, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) -#include - -static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { - .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, - .ppi_mode = USE_RGB565_16_BIT_PPI, - .use_bl = 1, - .gpio_bl = GPIO_PG12, -}; - -static struct resource bfin_lq035q1_resources[] = { - { - .start = IRQ_PPI_ERROR, - .end = IRQ_PPI_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_lq035q1_device = { - .name = "bfin-lq035q1", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), - .resource = bfin_lq035q1_resources, - .dev = { - .platform_data = &bfin_lq035q1_data, - }, -}; -#endif - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) - &bf5xx_nand_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - &bfin_lq035q1_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezbrd_flash_device, -#endif -}; - -static int __init ezbrd_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(ezbrd_init); - -static struct platform_device *ezbrd_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezbrd_early_devices, - ARRAY_SIZE(ezbrd_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -int bfin_get_ether_addr(char *addr) -{ - /* the MAC is stored in OTP memory page 0xDF */ - u32 ret; - u64 otp_mac; - u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; - - ret = otp_read(0xDF, 0x00, &otp_mac); - if (!(ret & 0x1)) { - char *otp_mac_p = (char *)&otp_mac; - for (ret = 0; ret < 6; ++ret) - addr[ret] = otp_mac_p[5 - ret]; - } - return 0; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c deleted file mode 100644 index 571edfd2ecf3..000000000000 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ /dev/null @@ -1,1335 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -#ifdef CONFIG_BFIN527_EZKIT_V2 -const char bfin_board_name[] = "ADI BF527-EZKIT V2"; -#else -const char bfin_board_name[] = "ADI BF527-EZKIT"; -#endif - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x203C0000, - .end = 0x203C0000 + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xffc03800, - .end = 0xffc03cff, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_INT0, - .end = IRQ_USB_INT0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "mc" - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "dma" - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 0, - .dyn_fifo = 0, - .soft_con = 1, - .dma = 1, - .num_eps = 8, - .dma_channels = 8, - .gpio_vrsel = GPIO_PG13, - /* Some custom boards need to be active low, just set it to "0" - * if it is the case. - */ - .gpio_vrsel_active = 1, - .clkin = 24, /* musb CLKIN in MHZ */ -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB) - -static struct resource bf52x_t350mcqb_resources[] = { - { - .start = IRQ_PPI_ERROR, - .end = IRQ_PPI_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf52x_t350mcqb_device = { - .name = "bfin-t350mcqb", - .id = -1, - .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources), - .resource = bf52x_t350mcqb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) -#include - -static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { - .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, - .ppi_mode = USE_RGB565_8_BIT_PPI, -}; - -static struct resource bfin_lq035q1_resources[] = { - { - .start = IRQ_PPI_ERROR, - .end = IRQ_PPI_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_lq035q1_device = { - .name = "bfin-lq035q1", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), - .resource = bfin_lq035q1_resources, - .dev = { - .platform_data = &bfin_lq035q1_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezkit_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x1C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data ezkit_flash_data = { - .width = 2, - .parts = ezkit_partitions, - .nr_parts = ARRAY_SIZE(ezkit_partitions), -}; - -static struct resource ezkit_flash_resource = { - .start = 0x20000000, - .end = 0x203fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezkit_flash_data, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) -static struct mtd_partition partition_info[] = { - { - .name = "bootloader(nand)", - .offset = 0, - .size = 0x40000, - }, { - .name = "linux kernel(nand)", - .offset = MTDPART_OFS_APPEND, - .size = 4 * 1024 * 1024, - }, - { - .name = "file system(nand)", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct bf5xx_nand_platform bf5xx_nand_platform = { - .data_width = NFC_NWIDTH_8, - .partitions = partition_info, - .nr_partitions = ARRAY_SIZE(partition_info), - .rd_dly = 3, - .wr_dly = 3, -}; - -static struct resource bf5xx_nand_resources[] = { - { - .start = NFC_CTL, - .end = NFC_DATA_RD + 2, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_NFC, - .end = CH_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf5xx_nand_device = { - .name = "bf5xx-nand", - .id = 0, - .num_resources = ARRAY_SIZE(bf5xx_nand_resources), - .resource = bf5xx_nand_resources, - .dev = { - .platform_data = &bf5xx_nand_platform, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) -static struct resource bfin_pcmcia_cf_resources[] = { - { - .start = 0x20310000, /* IO PORT */ - .end = 0x20312000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20311000, /* Attribute Memory */ - .end = 0x20311FFF, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, { - .start = 6, /* Card Detect PF6 */ - .end = 6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pcmcia_cf_device = { - .name = "bfin_cf_pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), - .resource = bfin_pcmcia_cf_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_DM9000) -static struct resource dm9000_resources[] = { - [0] = { - .start = 0x203FB800, - .end = 0x203FB800 + 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x203FB800 + 4, - .end = 0x203FB800 + 5, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), - }, -}; - -static struct platform_device dm9000_device = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(dm9000_resources), - .resource = dm9000_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_RMII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_RMII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = 1, - .flags = IORESOURCE_BUS, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) -#include -static const struct ad7879_platform_data bfin_ad7879_ts_info = { - .model = 7879, /* Model = AD7879 */ - .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ - .pressure_max = 10000, - .pressure_min = 0, - .first_conversion_delay = 3, /* wait 512us before do a first conversion */ - .acquisition_time = 1, /* 4us acquisition time per sample */ - .median = 2, /* do 8 measurements */ - .averaging = 1, /* take the average of 4 middle samples */ - .pen_down_acc_interval = 255, /* 9.4 ms */ - .gpio_export = 0, /* Export GPIO to gpiolib */ -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - -static const u16 bfin_snd_pin[][7] = { - {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0}, - {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0}, -}; - -static struct bfin_snd_platform_data bfin_snd_data[] = { - { - .pin_req = &bfin_snd_pin[0][0], - }, - { - .pin_req = &bfin_snd_pin[1][0], - }, -}; - -#define BFIN_SND_RES(x) \ - [x] = { \ - { \ - .start = SPORT##x##_TCR1, \ - .end = SPORT##x##_TCR1, \ - .flags = IORESOURCE_MEM \ - }, \ - { \ - .start = CH_SPORT##x##_RX, \ - .end = CH_SPORT##x##_RX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = CH_SPORT##x##_TX, \ - .end = CH_SPORT##x##_TX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = IRQ_SPORT##x##_ERROR, \ - .end = IRQ_SPORT##x##_ERROR, \ - .flags = IORESOURCE_IRQ, \ - } \ - } - -static struct resource bfin_snd_resources[][4] = { - BFIN_SND_RES(0), - BFIN_SND_RES(1), -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s_pcm = { - .name = "bfin-i2s-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97_pcm = { - .name = "bfin-ac97-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) -static const char * const ad1836_link[] = { - "bfin-i2s.0", - "spi0.4", -}; -static struct platform_device bfin_ad1836_machine = { - .name = "bfin-snd-ad1836", - .id = -1, - .dev = { - .platform_data = (void *)ad1836_link, - }, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = "ad1836", - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 3, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_0, - }, -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PF8, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI) - { - .modalias = "ad7879", - .platform_data = &bfin_ad7879_ts_info, - .irq = IRQ_PF8, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 3, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - { - .modalias = "bfin-lq035q1-spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 7, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin */ - .start = GPIO_PF9, - .end = GPIO_PF9, - .flags = IORESOURCE_IO, - }, - { /* RTS pin */ - .start = GPIO_PF10, - .end = GPIO_PF10, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_PMIC_ADP5520) -#include - - /* - * ADP5520/5501 LEDs Data - */ - -static struct led_info adp5520_leds[] = { - { - .name = "adp5520-led1", - .default_trigger = "none", - .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms, - }, -}; - -static struct adp5520_leds_platform_data adp5520_leds_data = { - .num_leds = ARRAY_SIZE(adp5520_leds), - .leds = adp5520_leds, - .fade_in = ADP5520_FADE_T_600ms, - .fade_out = ADP5520_FADE_T_600ms, - .led_on_time = ADP5520_LED_ONT_600ms, -}; - - /* - * ADP5520 Keypad Data - */ - -static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = { - [ADP5520_KEY(3, 3)] = KEY_1, - [ADP5520_KEY(2, 3)] = KEY_2, - [ADP5520_KEY(1, 3)] = KEY_3, - [ADP5520_KEY(0, 3)] = KEY_UP, - [ADP5520_KEY(3, 2)] = KEY_4, - [ADP5520_KEY(2, 2)] = KEY_5, - [ADP5520_KEY(1, 2)] = KEY_6, - [ADP5520_KEY(0, 2)] = KEY_DOWN, - [ADP5520_KEY(3, 1)] = KEY_7, - [ADP5520_KEY(2, 1)] = KEY_8, - [ADP5520_KEY(1, 1)] = KEY_9, - [ADP5520_KEY(0, 1)] = KEY_DOT, - [ADP5520_KEY(3, 0)] = KEY_BACKSPACE, - [ADP5520_KEY(2, 0)] = KEY_0, - [ADP5520_KEY(1, 0)] = KEY_HELP, - [ADP5520_KEY(0, 0)] = KEY_ENTER, -}; - -static struct adp5520_keys_platform_data adp5520_keys_data = { - .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0, - .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0, - .keymap = adp5520_keymap, - .keymapsize = ARRAY_SIZE(adp5520_keymap), - .repeat = 0, -}; - - /* - * ADP5520/5501 Multifunction Device Init Data - */ - -static struct adp5520_platform_data adp5520_pdev_data = { - .leds = &adp5520_leds_data, - .keys = &adp5520_keys_data, -}; - -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = IRQ_PF8, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C) - { - I2C_BOARD_INFO("ad7879", 0x2C), - .irq = IRQ_PF8, - .platform_data = (void *)&bfin_ad7879_ts_info, - }, -#endif -#if IS_ENABLED(CONFIG_PMIC_ADP5520) - { - I2C_BOARD_INFO("pmic-adp5520", 0x32), - .irq = IRQ_PF9, - .platform_data = (void *)&adp5520_pdev_data, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) - { - I2C_BOARD_INFO("ssm2602", 0x1b), - }, -#endif -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("ad5252", 0x2f), - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373) - { - I2C_BOARD_INFO("adau1373", 0x1A), - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) -#include - -static const u16 per_cnt[] = { - P_CNT_CUD, - P_CNT_CDG, - P_CNT_CZM, - 0 -}; - -static struct bfin_rotary_platform_data bfin_rotary_data = { - /*.rotary_up_key = KEY_UP,*/ - /*.rotary_down_key = KEY_DOWN,*/ - .rotary_rel_code = REL_WHEEL, - .rotary_button_key = KEY_ENTER, - .debounce = 10, /* 0..17 */ - .mode = ROT_QUAD_ENC | ROT_DEBE, - .pm_wakeup = 1, - .pin_list = per_cnt, -}; - -static struct resource bfin_rotary_resources[] = { - { - .start = CNT_CONFIG, - .end = CNT_CONFIG + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CNT, - .end = IRQ_CNT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_rotary_device = { - .name = "bfin-rotary", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_rotary_resources), - .resource = bfin_rotary_resources, - .dev = { - .platform_data = &bfin_rotary_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_100, 400000000), - VRPAIR(VLEV_105, 426000000), - VRPAIR(VLEV_110, 500000000), - VRPAIR(VLEV_115, 533000000), - VRPAIR(VLEV_120, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) - &bf5xx_nand_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) - &bfin_pcmcia_cf_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) - &bfin_isp1760_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_DM9000) - &dm9000_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB) - &bf52x_t350mcqb_device, -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - &bfin_lq035q1_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) - &bfin_rotary_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezkit_flash_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - &bfin_ad1836_machine, -#endif -}; - -static int __init ezkit_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(ezkit_init); - -static struct platform_device *ezkit_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezkit_early_devices, - ARRAY_SIZE(ezkit_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -int bfin_get_ether_addr(char *addr) -{ - /* the MAC is stored in OTP memory page 0xDF */ - u32 ret; - u64 otp_mac; - u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; - - ret = otp_read(0xDF, 0x00, &otp_mac); - if (!(ret & 0x1)) { - char *otp_mac_p = (char *)&otp_mac; - for (ret = 0; ret < 6; ++ret) - addr[ret] = otp_mac_p[5 - ret]; - } - return 0; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c deleted file mode 100644 index ce5488e8226b..000000000000 --- a/arch/blackfin/mach-bf527/boards/tll6527m.c +++ /dev/null @@ -1,946 +0,0 @@ -/* File: arch/blackfin/mach-bf527/boards/tll6527m.c - * Based on: arch/blackfin/mach-bf527/boards/ezkit.c - * Author: Ashish Gupta - * - * Copyright: 2010 - The Learning Labs Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) -#include -#define LCD_BACKLIGHT_GPIO 0x40 -/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for - * LCD Backlight Enable - */ -#endif - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "TLL6527M"; -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xffc03800, - .end = 0xffc03cff, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_INT0, - .end = IRQ_USB_INT0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 0, - .dyn_fifo = 0, - .soft_con = 1, - .dma = 1, - .num_eps = 8, - .dma_channels = 8, - /*.gpio_vrsel = GPIO_PG13,*/ - /* Some custom boards need to be active low, just set it to "0" - * if it is the case. - */ - .gpio_vrsel_active = 1, -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_OTG) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC_HCD) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) -#include - -static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { - .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, - .ppi_mode = USE_RGB565_16_BIT_PPI, - .use_bl = 1, - .gpio_bl = LCD_BACKLIGHT_GPIO, -}; - -static struct resource bfin_lq035q1_resources[] = { - { - .start = IRQ_PPI_ERROR, - .end = IRQ_PPI_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_lq035q1_device = { - .name = "bfin-lq035q1", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), - .resource = bfin_lq035q1_resources, - .dev = { - .platform_data = &bfin_lq035q1_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) -static struct mtd_partition tll6527m_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0xA0000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0xD00000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data tll6527m_flash_data = { - .width = 2, - .parts = tll6527m_partitions, - .nr_parts = ARRAY_SIZE(tll6527m_partitions), -}; - -static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 }; - -static struct resource tll6527m_flash_resource[] = { - { - .name = "cfi_probe", - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, - }, { - .start = (unsigned long)tll6527m_flash_gpios, - .end = ARRAY_SIZE(tll6527m_flash_gpios), - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device tll6527m_flash_device = { - .name = "gpio-addr-flash", - .id = 0, - .dev = { - .platform_data = &tll6527m_flash_data, - }, - .num_resources = ARRAY_SIZE(tll6527m_flash_resource), - .resource = tll6527m_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_GPIO_DECODER) -/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented - * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0. - * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being - * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS - */ -#include -#define EXP_GPIO_SPISEL_BASE 0x64 -static unsigned gpio_addr_inputs[] = { - GPIO_PG1, GPIO_PH9, GPIO_PH10 -}; - -static struct gpio_decoder_platform_data spi_decoded_cs = { - .base = EXP_GPIO_SPISEL_BASE, - .input_addrs = gpio_addr_inputs, - .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs), - .default_output = 0, -/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */ -}; - -static struct platform_device spi_decoded_gpio = { - .name = "gpio-decoder", - .id = 0, - .dev = { - .platform_data = &spi_decoded_cs, - }, -}; - -#else -#define EXP_GPIO_SPISEL_BASE 0x0 - -#endif - -#if IS_ENABLED(CONFIG_INPUT_ADXL34X) -#include -static const struct adxl34x_platform_data adxl345_info = { - .x_axis_offset = 0, - .y_axis_offset = 0, - .z_axis_offset = 0, - .tap_threshold = 0x31, - .tap_duration = 0x10, - .tap_latency = 0x60, - .tap_window = 0xF0, - .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, - .act_axis_control = 0xFF, - .activity_threshold = 5, - .inactivity_threshold = 2, - .inactivity_time = 2, - .free_fall_threshold = 0x7, - .free_fall_time = 0x20, - .data_rate = 0x8, - .data_range = ADXL_FULL_RES, - - .ev_type = EV_ABS, - .ev_code_x = ABS_X, /* EV_REL */ - .ev_code_y = ABS_Y, /* EV_REL */ - .ev_code_z = ABS_Z, /* EV_REL */ - - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ - -/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ - .ev_code_act_inactivity = KEY_A, /* EV_KEY */ - .use_int2 = 1, - .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, - .fifo_mode = ADXL_FIFO_STREAM, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_RMII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_RMII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) -static const struct ad7879_platform_data bfin_ad7879_ts_info = { - .model = 7879, /* Model = AD7879 */ - .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ - .pressure_max = 10000, - .pressure_min = 0, - .first_conversion_delay = 3, - /* wait 512us before do a first conversion */ - .acquisition_time = 1, /* 4us acquisition time per sample */ - .median = 2, /* do 8 measurements */ - .averaging = 1, - /* take the average of 4 middle samples */ - .pen_down_acc_interval = 255, /* 9.4 ms */ - .gpio_export = 1, /* configure AUX as GPIO output*/ - .gpio_base = LCD_BACKLIGHT_GPIO, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) -#include -static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = { - .spi_present_mask = BIT(0), - .base = 0x30, -}; -static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = { - .spi_present_mask = BIT(2), - .base = 0x38, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, - /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS, - /* Can be connected to TLL6527M GPIO connector */ - /* Either SPI_ADC or M25P80 FLASH can be installed at a time */ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", -/* - * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to - * SPI buffer limitations - */ - .max_speed_hz = 10000000, - /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI) - { - .modalias = "ad7879", - .platform_data = &bfin_ad7879_ts_info, - .irq = IRQ_PH14, - .max_speed_hz = 5000000, - /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 10000000, - /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */ - .bus_num = 0, - .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - { - .modalias = "bfin-lq035q1-spi", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) - { - .modalias = "mcp23s08", - .platform_data = &bfin_mcp23s08_sys_gpio_info, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS, - .mode = SPI_CPHA | SPI_CPOL, - }, - { - .modalias = "mcp23s08", - .platform_data = &bfin_mcp23s08_usr_gpio_info, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS, - /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */ - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, - /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin */ - .start = GPIO_PF9, - .end = GPIO_PF9, - .flags = IORESOURCE_IO, - }, - { /* RTS pin */ - .start = GPIO_PF10, - .end = GPIO_PF10, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, - /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C) - { - I2C_BOARD_INFO("ad7879", 0x2C), - .irq = IRQ_PH14, - .platform_data = (void *)&bfin_ad7879_ts_info, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) - { - I2C_BOARD_INFO("ssm2602", 0x1b), - }, -#endif - { - I2C_BOARD_INFO("adm1192", 0x2e), - }, - - { - I2C_BOARD_INFO("ltc3576", 0x09), - }, -#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C) - { - I2C_BOARD_INFO("adxl34x", 0x53), - .irq = IRQ_PH13, - .platform_data = (void *)&adxl345_info, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, - /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, - /* Passed to driver */ - }, -}; -#endif -#endif - -static const unsigned int cclk_vlev_datasheet[] = { - VRPAIR(VLEV_100, 400000000), - VRPAIR(VLEV_105, 426000000), - VRPAIR(VLEV_110, 500000000), - VRPAIR(VLEV_115, 533000000), - VRPAIR(VLEV_120, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *tll6527m_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - &bfin_lq035q1_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) - &tll6527m_flash_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_GPIO_DECODER) - &spi_decoded_gpio, -#endif -}; - -static int __init tll6527m_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices)); - spi_register_board_info(bfin_spi_board_info, - ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(tll6527m_init); - -static struct platform_device *tll6527m_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(tll6527m_early_devices, - ARRAY_SIZE(tll6527m_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -int bfin_get_ether_addr(char *addr) -{ - /* the MAC is stored in OTP memory page 0xDF */ - u32 ret; - u64 otp_mac; - u32 (*otp_read)(u32 page, u32 flags, - u64 *page_content) = (void *)0xEF00001A; - - ret = otp_read(0xDF, 0x00, &otp_mac); - if (!(ret & 0x1)) { - char *otp_mac_p = (char *)&otp_mac; - for (ret = 0; ret < 6; ++ret) - addr[ret] = otp_mac_p[5 - ret]; - } - return 0; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c deleted file mode 100644 index 1fabdefea73a..000000000000 --- a/arch/blackfin/mach-bf527/dma.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file contains the simple DMA Implementation for Blackfin - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) DMA8_NEXT_DESC_PTR, - (struct dma_register *) DMA9_NEXT_DESC_PTR, - (struct dma_register *) DMA10_NEXT_DESC_PTR, - (struct dma_register *) DMA11_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI: - ret_irq = IRQ_PPI; - break; - - case CH_EMAC_RX: - ret_irq = IRQ_MAC_RX; - break; - - case CH_EMAC_TX: - ret_irq = IRQ_MAC_TX; - break; - - case CH_UART1_RX: - ret_irq = IRQ_UART1_RX; - break; - - case CH_UART1_TX: - ret_irq = IRQ_UART1_TX; - break; - - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - - case CH_SPI: - ret_irq = IRQ_SPI; - break; - - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h deleted file mode 100644 index 2f9cc33deec4..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support old silicon - sorry */ -#if __SILICON_REVISION__ < 0 -# error will not work on BF526/BF527 silicon version -#endif - -#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) -# define ANOMALY_BF526 1 -#else -# define ANOMALY_BF526 0 -#endif -#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) -# define ANOMALY_BF527 1 -#else -# define ANOMALY_BF527 0 -#endif - -#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526) -#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) -#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (1) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) -/* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (_ANOMALY_BF527(< 2)) -/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) -/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (_ANOMALY_BF527(< 2)) -/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ -#define ANOMALY_05000342 (_ANOMALY_BF527(< 2)) -/* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* USB Calibration Value to use */ -#define ANOMALY_05000346_value 0xE510 -/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (_ANOMALY_BF527(< 2)) -/* Security Features Are Not Functional */ -#define ANOMALY_05000348 (_ANOMALY_BF527(< 1)) -/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (_ANOMALY_BF526(< 1)) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (_ANOMALY_BF527(< 2)) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (_ANOMALY_BF527(< 2)) -/* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000364 (_ANOMALY_BF527(== 1)) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Incorrect Default CSEL Value in PLL_DIV */ -#define ANOMALY_05000368 (_ANOMALY_BF527(< 2)) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (_ANOMALY_BF527(< 2)) -/* Authentication Fails To Initiate */ -#define ANOMALY_05000376 (_ANOMALY_BF527(< 2)) -/* Data Read From L3 Memory by USB DMA May be Corrupted */ -#define ANOMALY_05000380 (_ANOMALY_BF527(< 2)) -/* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (_ANOMALY_BF527(< 2)) -/* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (_ANOMALY_BF527(< 2)) -/* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (_ANOMALY_BF527(< 2)) -/* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (_ANOMALY_BF527(< 2)) -/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (_ANOMALY_BF527(< 2)) -/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (_ANOMALY_BF527(< 2)) -/* Log Buffer Not Functional */ -#define ANOMALY_05000394 (_ANOMALY_BF527(< 2)) -/* Hook Routine Not Functional */ -#define ANOMALY_05000395 (_ANOMALY_BF527(< 2)) -/* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (_ANOMALY_BF527(< 2)) -/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (_ANOMALY_BF527(< 2)) -/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ -#define ANOMALY_05000398 (_ANOMALY_BF527(< 2)) -/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ -#define ANOMALY_05000399 (_ANOMALY_BF527(< 2)) -/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ -#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ -#define ANOMALY_05000405 (1) -/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ -#define ANOMALY_05000408 (1) -/* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Incorrect Default Internal Voltage Regulator Setting */ -#define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) -/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (_ANOMALY_BF526(< 1)) -/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* DEB2_URGENT Bit Not Functional */ -#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ -#define ANOMALY_05000417 (_ANOMALY_BF527(< 2)) -/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ -#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ -#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ -#define ANOMALY_05000421 (1) -/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ -#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1)) -/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ -#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Internal Voltage Regulator Not Trimmed */ -#define ANOMALY_05000424 (_ANOMALY_BF527(< 2)) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ -#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2)) -/* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (_ANOMALY_BF527(> 1)) -/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ -#define ANOMALY_05000431 (1) -/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ -#define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) -/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ -#define ANOMALY_05000434 (1) -/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ -#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) -/* Preboot Cannot be Used to Alter the PLL_DIV Register */ -#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0)) -/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ -#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0)) -/* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (_ANOMALY_BF527(< 1)) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* The WURESET Bit in the SYSCR Register is not Functional */ -#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0)) -/* USB DMA Short Packet Data Corruption */ -#define ANOMALY_05000450 (1) -/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ -#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0)) -/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) -/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ -#define ANOMALY_05000456 (1) -/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ -#define ANOMALY_05000457 (1) -/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ -#define ANOMALY_05000460 (1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* USB Rx DMA Hang */ -#define ANOMALY_05000465 (1) -/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ -#define ANOMALY_05000466 (1) -/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ -#define ANOMALY_05000467 (1) -/* PLL Latches Incorrect Settings During Reset */ -#define ANOMALY_05000469 (1) -/* Incorrect Default MSEL Value in PLL_CTL */ -#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* Possible Lockup Condition when Modifying PLL from External Memory */ -#define ANOMALY_05000475 (1) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ -#define ANOMALY_05000483 (1) -/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0)) -/* The CODEC Zero-Cross Detect Feature is not Functional */ -#define ANOMALY_05000487 (1) -/* SPI Master Boot Can Fail Under Certain Conditions */ -#define ANOMALY_05000490 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ -#define ANOMALY_05000498 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000099 (0) -#define ANOMALY_05000120 (0) -#define ANOMALY_05000125 (0) -#define ANOMALY_05000149 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000179 (0) -#define ANOMALY_05000182 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000189 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000202 (0) -#define ANOMALY_05000215 (0) -#define ANOMALY_05000219 (0) -#define ANOMALY_05000220 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000231 (0) -#define ANOMALY_05000233 (0) -#define ANOMALY_05000234 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000248 (0) -#define ANOMALY_05000250 (0) -#define ANOMALY_05000257 (0) -#define ANOMALY_05000261 (0) -#define ANOMALY_05000263 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000278 (0) -#define ANOMALY_05000281 (0) -#define ANOMALY_05000283 (0) -#define ANOMALY_05000285 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000301 (0) -#define ANOMALY_05000305 (0) -#define ANOMALY_05000307 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000312 (0) -#define ANOMALY_05000315 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000383 (0) -#define ANOMALY_05000400 (0) -#define ANOMALY_05000402 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000474 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h deleted file mode 100644 index 8ff155b34f64..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/bf527.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF527_H__ -#define __MACH_BF527_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) - -/**************************** Hysteresis Settings ****************************/ - -#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL -#ifdef CONFIG_GPIO_HYST_PORTF_0_7 -#define HYST_PORTF_0_7 (1 << 0) -#else -#define HYST_PORTF_0_7 (0 << 0) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_8_9 -#define HYST_PORTF_8_9 (1 << 2) -#else -#define HYST_PORTF_8_9 (0 << 2) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_10 -#define HYST_PORTF_10 (1 << 4) -#else -#define HYST_PORTF_10 (0 << 4) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_11 -#define HYST_PORTF_11 (1 << 6) -#else -#define HYST_PORTF_11 (0 << 6) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_12_13 -#define HYST_PORTF_12_13 (1 << 8) -#else -#define HYST_PORTF_12_13 (0 << 8) -#endif -#ifdef CONFIG_GPIO_HYST_PORTF_14_15 -#define HYST_PORTF_14_15 (1 << 10) -#else -#define HYST_PORTF_14_15 (0 << 10) -#endif - -#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \ - HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15) - -#ifdef CONFIG_GPIO_HYST_PORTG_0 -#define HYST_PORTG_0 (1 << 0) -#else -#define HYST_PORTG_0 (0 << 0) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_1_4 -#define HYST_PORTG_1_4 (1 << 2) -#else -#define HYST_PORTG_1_4 (0 << 2) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_5_6 -#define HYST_PORTG_5_6 (1 << 4) -#else -#define HYST_PORTG_5_6 (0 << 4) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_7_8 -#define HYST_PORTG_7_8 (1 << 6) -#else -#define HYST_PORTG_7_8 (0 << 6) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_9 -#define HYST_PORTG_9 (1 << 8) -#else -#define HYST_PORTG_9 (0 << 8) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_10 -#define HYST_PORTG_10 (1 << 10) -#else -#define HYST_PORTG_10 (0 << 10) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_11_13 -#define HYST_PORTG_11_13 (1 << 12) -#else -#define HYST_PORTG_11_13 (0 << 12) -#endif -#ifdef CONFIG_GPIO_HYST_PORTG_14_15 -#define HYST_PORTG_14_15 (1 << 14) -#else -#define HYST_PORTG_14_15 (0 << 14) -#endif - -#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \ - HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \ - HYST_PORTG_11_13 | HYST_PORTG_14_15) - -#ifdef CONFIG_GPIO_HYST_PORTH_0_7 -#define HYST_PORTH_0_7 (1 << 0) -#else -#define HYST_PORTH_0_7 (0 << 0) -#endif -#ifdef CONFIG_GPIO_HYST_PORTH_8 -#define HYST_PORTH_8 (1 << 2) -#else -#define HYST_PORTH_8 (0 << 2) -#endif -#ifdef CONFIG_GPIO_HYST_PORTH_9_15 -#define HYST_PORTH_9_15 (1 << 4) -#else -#define HYST_PORTH_9_15 (0 << 4) -#endif - -#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15) - -#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK -#define HYST_TMR0_FS1_PPICLK (1 << 0) -#else -#define HYST_TMR0_FS1_PPICLK (0 << 0) -#endif -#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE -#define HYST_NMI_RST_BMODE (1 << 2) -#else -#define HYST_NMI_RST_BMODE (0 << 2) -#endif -#ifdef CONFIG_NONEGPIO_HYST_JTAG -#define HYST_JTAG (1 << 4) -#else -#define HYST_JTAG (0 << 4) -#endif - -#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG) -#define HYST_NONEGPIO_MASK (0x3F) -#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */ - -#ifdef CONFIG_BF527 -#define CPU "BF527" -#define CPUID 0x27e0 -#endif -#ifdef CONFIG_BF526 -#define CPU "BF526" -#define CPUID 0x27e4 -#endif -#ifdef CONFIG_BF525 -#define CPU "BF525" -#define CPUID 0x27e0 -#endif -#ifdef CONFIG_BF524 -#define CPU "BF524" -#define CPUID 0x27e4 -#endif -#ifdef CONFIG_BF523 -#define CPU "BF523" -#define CPUID 0x27e0 -#endif -#ifdef CONFIG_BF522 -#define CPU "BF522" -#define CPUID 0x27e4 -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF527_H__ */ diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h deleted file mode 100644 index 00c603fe8218..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 2 - -#endif diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h deleted file mode 100644 index e1d279274487..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#include "bf527.h" -#include "anomaly.h" - -#include -#if defined(CONFIG_BF523) || defined(CONFIG_BF522) -# include "defBF522.h" -#endif -#if defined(CONFIG_BF525) || defined(CONFIG_BF524) -# include "defBF525.h" -#endif -#if defined(CONFIG_BF527) || defined(CONFIG_BF526) -# include "defBF527.h" -#endif - -#if !defined(__ASSEMBLY__) -# include -# if defined(CONFIG_BF523) || defined(CONFIG_BF522) -# include "cdefBF522.h" -# endif -# if defined(CONFIG_BF525) || defined(CONFIG_BF524) -# include "cdefBF525.h" -# endif -# if defined(CONFIG_BF527) || defined(CONFIG_BF526) -# include "cdefBF527.h" -# endif -#endif - -#endif diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h deleted file mode 100644 index 2c12e879aa4e..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h +++ /dev/null @@ -1,1095 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF522_H -#define _CDEF_BF522_H - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) - - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) - -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) - -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) - -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) - -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) -#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) - -/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ - -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) -#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) - - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) - - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) - -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) - -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) - -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) - -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) - -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) - -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) - -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) - -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) - - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) - - -/* DMA Traffic Control Registers */ -#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) -#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val) -#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) -#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val) - -/* DMA Controller */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) - -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) - -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) - -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) - -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) - -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) - -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) - -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) - -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) - -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) - -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) - -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) - -/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */ - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) -#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) - -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) - -/* ==== end from cdefBF534.h ==== */ - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ - -#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) -#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) -#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) - -#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) -#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) -#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) -#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) -#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) -#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) -#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) -#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) -#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) -#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) -#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) -#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) -#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) -#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) -#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) -#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) -#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) -#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) -#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) -#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) -#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) -#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS) -#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val) - -/* HOST Port Registers */ - -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) - -/* Counter Registers */ - -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) - -/* Security Registers */ - -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) - -/* NFC Registers */ - -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) - -#endif /* _CDEF_BF522_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h deleted file mode 100644 index bd045318a250..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF525_H -#define _CDEF_BF525_H - -/* BF525 is BF522 + USB */ -#include "cdefBF522.h" - -/* USB Control Registers */ - -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) - -/* USB Packet Control Registers */ - -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) - -/* USB Endpoint FIFO Registers */ - -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) - -/* USB OTG Control Registers */ - -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) - -/* USB Phy Control Registers */ - -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) - -/* (APHY_CNTRL is for ADI usage only) */ - -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) - -/* (APHY_CALIB is for ADI usage only) */ - -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) - -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) - -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) - -/* USB Endpoint 0 Control Registers */ - -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) - -/* USB Endpoint 1 Control Registers */ - -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) - -/* USB Endpoint 2 Control Registers */ - -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) - -/* USB Endpoint 3 Control Registers */ - -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) - -/* USB Endpoint 4 Control Registers */ - -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) - -/* USB Endpoint 5 Control Registers */ - -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) - -/* USB Endpoint 6 Control Registers */ - -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) - -/* USB Endpoint 7 Control Registers */ - -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) - -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) - -/* USB Channel 0 Config Registers */ - -#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) -#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) -#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) -#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) -#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) -#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) -#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) -#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) -#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) -#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) - -/* USB Channel 1 Config Registers */ - -#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) -#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) -#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) -#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) -#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) -#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) -#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) -#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) -#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) -#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) - -/* USB Channel 2 Config Registers */ - -#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) -#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) -#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) -#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) -#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) -#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) -#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) -#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) -#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) -#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) - -/* USB Channel 3 Config Registers */ - -#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) -#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) -#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) -#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) -#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) -#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) -#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) -#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) -#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) -#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) - -/* USB Channel 4 Config Registers */ - -#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) -#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) -#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) -#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) -#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) -#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) -#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) -#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) -#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) -#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) - -/* USB Channel 5 Config Registers */ - -#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) -#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) -#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) -#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) -#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) -#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) -#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) -#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) -#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) -#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) - -/* USB Channel 6 Config Registers */ - -#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) -#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) -#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) -#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) -#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) -#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) -#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) -#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) -#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) -#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) - -/* USB Channel 7 Config Registers */ - -#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) -#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) -#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) -#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) -#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) -#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) -#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) -#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) -#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) -#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) - -#endif /* _CDEF_BF525_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h deleted file mode 100644 index eb22f5866105..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF527_H -#define _CDEF_BF527_H - -/* BF527 is BF525 + EMAC */ -#include "cdefBF525.h" - -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ - -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) - -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) - -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) - -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) - -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) - -#endif /* _CDEF_BF527_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h deleted file mode 100644 index e007017cf958..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/defBF522.h +++ /dev/null @@ -1,1309 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF522_H -#define _DEF_BF522_H - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */ -/* ************************************************************** */ - -/* ==== begin from defBF534.h ==== */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 /* Device ID Register */ - - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ - -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ - -/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ -#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ -#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ -#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ -#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ -#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ -#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ -#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ - - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ - -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ - -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ - -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ - -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ - -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ - - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - - -/* DMA Traffic Control Registers */ -#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ - -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ - -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ - -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ - - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define TWI0_REGBASE 0xFFC01400 -#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ - - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - - -/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */ - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ - - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ - -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ - -/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ -#define PORTF_MUX 0xFFC03210 /* Port F mux control */ -#define PORTG_MUX 0xFFC03214 /* Port G mux control */ -#define PORTH_MUX 0xFFC03218 /* Port H mux control */ -#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ -#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ -#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ -#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ -#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ -#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ -#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ -#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ -#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ -#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ -#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ -#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */ - - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ -/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ - -#if 0 -#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ - -#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ -#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ -#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ -#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ -#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ -#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ -#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ - -#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ -#define IRQ_TWI 0x00000200 /* TWI Interrupt */ -#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ -#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ -#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ -#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ -#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ -#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ - -#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ -#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ -#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ -#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ -#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ -#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ -#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ -#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ -#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ -#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ - -#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ -#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ -#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ -#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ -#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ -#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ -#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ -#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ -#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ -#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ -#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ -#endif - -/* SIC_IAR0 Macros */ -#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Macros */ -#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Macros */ -#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IAR3 Macros */ -#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ -#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ -#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ -#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ -#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ -#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ -#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ -#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ - - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ - -/* **************** GENERAL PURPOSE TIMER MASKS **********************/ -/* TIMER_ENABLE Masks */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ -#define TIMEN3 0x0008 /* Enable Timer 3 */ -#define TIMEN4 0x0010 /* Enable Timer 4 */ -#define TIMEN5 0x0020 /* Enable Timer 5 */ -#define TIMEN6 0x0040 /* Enable Timer 6 */ -#define TIMEN7 0x0080 /* Enable Timer 7 */ - -/* TIMER_DISABLE Masks */ -#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ -#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ -#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ -#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ -#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ -#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ -#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ -#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ - -/* TIMER_STATUS Masks */ -#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ -#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ -#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ -#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ -#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ -#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ -#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ -#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 - -/* TIMERx_CONFIG Masks */ -#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ -#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ -#define EXT_CLK 0x0003 /* External Clock Mode */ -#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ -#define PERIOD_CNT 0x0008 /* Period Count */ -#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ -#define TIN_SEL 0x0020 /* Timer Input Select */ -#define OUT_DIS 0x0040 /* Output Pad Disable */ -#define CLK_SEL 0x0080 /* Timer Clock Select */ -#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ -#define EMU_RUN 0x0200 /* Emulation Behavior Select */ -#define ERR_TYP 0xC000 /* Error Type */ - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ -#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ -#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ -#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ -#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ -#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ -#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ - -#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ -#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ -#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ -#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ -#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ -#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ -#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ -#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ -#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ -#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ -#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ -#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ -#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ - -#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ -#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ -#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ -#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ -#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ -#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ -#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ - - -/* ********************** SDRAM CONTROLLER MASKS **********************************************/ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SDRAM Signals */ -#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ -#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ -#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ -#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ -#define EBUFE 0x02000000 /* Enable External Buffering Timing */ -#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ -#define EMREN 0x10000000 /* Extended Mode Register Enable */ -#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ -#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x0001 /* Enable SDRAM External Bank */ -#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ -#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ -#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ -#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ -#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ -#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ -#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x0001 /* SDRAM Controller Idle */ -#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ -#define SDPUA 0x0004 /* SDRAM Power-Up Active */ -#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ -#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ -#define BGSTAT 0x0020 /* Bus Grant Status */ - - -/* ************************** DMA CONTROLLER MASKS ********************************/ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ -#define PMAP_PPI 0x0000 /* PPI Port DMA */ -#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ -#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ -#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ -#define PMAP_SPI 0x7000 /* SPI Port DMA */ -#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ -#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ -#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ -#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ - -/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - - -/* Omit CAN masks from defBF534.h */ - -/* ******************* PIN CONTROL REGISTER MASKS ************************/ -/* PORT_MUX Masks */ -#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ -#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ -#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ - -#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ -#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ -#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ -#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ - -#define PFDE 0x0008 /* Port F DMA Request Enable */ -#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ -#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ - -#define PFTE 0x0010 /* Port F Timer Enable */ -#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ -#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ - -#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ -#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ -#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ - -#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ -#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ -#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ - -#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ -#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ -#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ - -#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ -#define PFFE_TIMER 0x0000 /* Enable TMR2 */ -#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ - -#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ -#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ -#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ - -#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ -#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ -#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ - -#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ -#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ -#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - -/* entry addresses of the user-callable Boot ROM functions */ - -#define _BOOTROM_RESET 0xEF000000 -#define _BOOTROM_FINAL_INIT 0xEF000002 -#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 -#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 -#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A -#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C -#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 -#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 -#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define PGDE_UART PFDE_UART -#define PGDE_DMA PFDE_DMA -#define CKELOW SCKELOW - -/* ==== end from defBF534.h ==== */ - -/* HOST Port Registers */ - -#define HOST_CONTROL 0xffc03400 /* HOST Control Register */ -#define HOST_STATUS 0xffc03404 /* HOST Status Register */ -#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ - -/* Counter Registers */ - -#define CNT_CONFIG 0xffc03500 /* Configuration Register */ -#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ -#define CNT_STATUS 0xffc03508 /* Status Register */ -#define CNT_COMMAND 0xffc0350c /* Command Register */ -#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ -#define CNT_COUNTER 0xffc03514 /* Counter Register */ -#define CNT_MAX 0xffc03518 /* Maximal Count Register */ -#define CNT_MIN 0xffc0351c /* Minimal Count Register */ - -/* OTP/FUSE Registers */ - -#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ -#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ - -/* Security Registers */ - -#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ -#define SECURE_CONTROL 0xffc03624 /* Secure Control */ -#define SECURE_STATUS 0xffc03628 /* Secure Status */ - -/* OTP Read/Write Data Buffer Registers */ - -#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ - -/* NFC Registers */ - -#define NFC_CTL 0xffc03700 /* NAND Control Register */ -#define NFC_STAT 0xffc03704 /* NAND Status Register */ -#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */ -#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */ -#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */ -#define NFC_READ 0xffc0372c /* NAND Read Data Register */ -#define NFC_ADDR 0xffc03740 /* NAND Address Register */ -#define NFC_CMD 0xffc03744 /* NAND Command Register */ -#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */ - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for HOST_CONTROL */ - -#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ -#define HOST_CNTR_nHOST_EN 0x0 -#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ -#define HOST_CNTR_nHOST_END 0x0 -#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ -#define HOST_CNTR_nDATA_SIZE 0x0 -#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ -#define HOST_CNTR_nHOST_RST 0x0 -#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ -#define HOST_CNTR_nHRDY_OVR 0x0 -#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ -#define HOST_CNTR_nINT_MODE 0x0 -#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ -#define HOST_CNTR_ nBT_EN 0x0 -#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ -#define HOST_CNTR_nEHW 0x0 -#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ -#define HOST_CNTR_nEHR 0x0 -#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ -#define HOST_CNTR_nBDR 0x0 - -/* Bit masks for HOST_STATUS */ - -#define HOST_STAT_READY 0x1 /* DMA Ready */ -#define HOST_STAT_nREADY 0x0 -#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ -#define HOST_STAT_nFIFOFULL 0x0 -#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ -#define HOST_STAT_nFIFOEMPTY 0x0 -#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ -#define HOST_STAT_nCOMPLETE 0x0 -#define HOST_STAT_HSHK 0x10 /* Host Handshake */ -#define HOST_STAT_nHSHK 0x0 -#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ -#define HOST_STAT_nTIMEOUT 0x0 -#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ -#define HOST_STAT_nHIRQ 0x0 -#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define HOST_STAT_nALLOW_CNFG 0x0 -#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ -#define HOST_STAT_nDMA_DIR 0x0 -#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ -#define HOST_STAT_nBTE 0x0 -#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ -#define HOST_STAT_nHOSTRD_DONE 0x0 - -/* Bit masks for HOST_TIMEOUT */ - -#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ - -/* Bit masks for SECURE_SYSSWT */ - -#define EMUDABL 0x1 /* Emulation Disable. */ -#define nEMUDABL 0x0 -#define RSTDABL 0x2 /* Reset Disable */ -#define nRSTDABL 0x0 -#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ -#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ -#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ -#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define nDMA0OVR 0x0 -#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define nDMA1OVR 0x0 -#define EMUOVR 0x4000 /* Emulation Override */ -#define nEMUOVR 0x0 -#define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define nOTPSEN 0x0 -#define L2DABL 0x70000 /* L2 Memory Disable. */ - -/* Bit masks for SECURE_CONTROL */ - -#define SECURE0 0x1 /* SECURE 0 */ -#define nSECURE0 0x0 -#define SECURE1 0x2 /* SECURE 1 */ -#define nSECURE1 0x0 -#define SECURE2 0x4 /* SECURE 2 */ -#define nSECURE2 0x0 -#define SECURE3 0x8 /* SECURE 3 */ -#define nSECURE3 0x0 - -/* Bit masks for SECURE_STATUS */ - -#define SECMODE 0x3 /* Secured Mode Control State */ -#define NMI 0x4 /* Non Maskable Interrupt */ -#define nNMI 0x0 -#define AFVALID 0x8 /* Authentication Firmware Valid */ -#define nAFVALID 0x0 -#define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define nAFEXIT 0x0 -#define SECSTAT 0xe0 /* Secure Status */ - -#endif /* _DEF_BF522_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h deleted file mode 100644 index 591e00ff620a..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/defBF525.h +++ /dev/null @@ -1,678 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF525_H -#define _DEF_BF525_H - -/* BF525 is BF522 + USB */ -#include "defBF522.h" - -/* USB Control Registers */ - -#define USB_FADDR 0xffc03800 /* Function address register */ -#define USB_POWER 0xffc03804 /* Power management register */ -#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xffc03820 /* USB frame number */ -#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ - -/* USB Packet Control Registers */ - -#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* USB Endpoint FIFO Registers */ - -#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ - -/* USB OTG Control Registers */ - -#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ - -/* USB Phy Control Registers */ - -#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ - -/* (APHY_CNTRL is for ADI usage only) */ - -#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ - -/* (APHY_CALIB is for ADI usage only) */ - -#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ - -#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ - -#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ - -/* USB Endpoint 0 Control Registers */ - -#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ - -/* USB Endpoint 1 Control Registers */ - -#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ - -/* USB Endpoint 2 Control Registers */ - -#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ - -/* USB Endpoint 3 Control Registers */ - -#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ - -/* USB Endpoint 4 Control Registers */ - -#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ - -/* USB Endpoint 5 Control Registers */ - -#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ - -/* USB Endpoint 6 Control Registers */ - -#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ - -/* USB Endpoint 7 Control Registers */ - -#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ - -#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ - -/* USB Channel 0 Config Registers */ - -#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ -#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ - -/* USB Channel 1 Config Registers */ - -#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ -#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ - -/* USB Channel 2 Config Registers */ - -#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ -#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ - -/* USB Channel 3 Config Registers */ - -#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ -#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ - -/* USB Channel 4 Config Registers */ - -#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ -#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ - -/* USB Channel 5 Config Registers */ - -#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ -#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ - -/* USB Channel 6 Config Registers */ - -#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ -#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ - -/* USB Channel 7 Config Registers */ - -#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ -#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -/* Bit masks for USB_FADDR */ - -#define FUNCTION_ADDRESS 0x7f /* Function address */ - -/* Bit masks for USB_POWER */ - -#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 -#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 -#define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 -#define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 -#define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 -#define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 -#define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 -#define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 - -/* Bit masks for USB_INTRTX */ - -#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 -#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 -#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 -#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 -#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 -#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 -#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 -#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 - -/* Bit masks for USB_INTRRX */ - -#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 -#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 -#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 -#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 -#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 -#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 -#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 - -/* Bit masks for USB_INTRTXE */ - -#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 -#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 -#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 -#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 -#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 -#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 -#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 -#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 - -/* Bit masks for USB_INTRRXE */ - -#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 -#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 -#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 -#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 -#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 -#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 -#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 - -/* Bit masks for USB_INTRUSB */ - -#define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 -#define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 -#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 -#define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 -#define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 -#define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 -#define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 -#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 - -/* Bit masks for USB_INTRUSBE */ - -#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 -#define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 -#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 -#define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 -#define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 -#define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 -#define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 -#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 - -/* Bit masks for USB_FRAME */ - -#define FRAME_NUMBER 0x7ff /* Frame number */ - -/* Bit masks for USB_INDEX */ - -#define SELECTED_ENDPOINT 0xf /* selected endpoint */ - -/* Bit masks for USB_GLOBAL_CTL */ - -#define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 -#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 -#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 -#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 -#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 -#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 -#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 -#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 -#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 -#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 -#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 -#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 -#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 -#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 -#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 - -/* Bit masks for USB_OTG_DEV_CTL */ - -#define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 -#define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 -#define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 -#define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 -#define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 -#define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 -#define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 -#define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 - -/* Bit masks for USB_OTG_VBUS_IRQ */ - -#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 -#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 -#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 -#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 -#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 -#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 - -/* Bit masks for USB_OTG_VBUS_MASK */ - -#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 -#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 -#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 -#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 -#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 -#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 - -/* Bit masks for USB_CSR0 */ - -#define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 -#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 -#define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 -#define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 -#define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 -#define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 -#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 -#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 -#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 -#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 -#define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 -#define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 -#define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 -#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 -#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 - -/* Bit masks for USB_COUNT0 */ - -#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ - -/* Bit masks for USB_NAKLIMIT0 */ - -#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ - -/* Bit masks for USB_TX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_RX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_TXCSR */ - -#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 -#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 -#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 -#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 -#define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 -#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 -#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 -#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 -#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 -#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 -#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 -#define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 -#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 -#define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 -#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 -#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 - -/* Bit masks for USB_TXCOUNT */ - -#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* Bit masks for USB_RXCSR */ - -#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 -#define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 -#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 -#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 -#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 -#define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 -#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 -#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 -#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 -#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 -#define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 -#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 -#define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 -#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 -#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 -#define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 -#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 -#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 -#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 -#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 - -/* Bit masks for USB_RXCOUNT */ - -#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ - -/* Bit masks for USB_TXTYPE */ - -#define TARGET_EP_NO_T 0xf /* EP number */ -#define PROTOCOL_T 0xc /* transfer type */ - -/* Bit masks for USB_TXINTERVAL */ - -#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ - -/* Bit masks for USB_RXTYPE */ - -#define TARGET_EP_NO_R 0xf /* EP number */ -#define PROTOCOL_R 0xc /* transfer type */ - -/* Bit masks for USB_RXINTERVAL */ - -#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ - -/* Bit masks for USB_DMA_INTERRUPT */ - -#define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 -#define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 -#define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 -#define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 -#define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 -#define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 -#define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 -#define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 - -/* Bit masks for USB_DMAxCONTROL */ - -#define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 -#define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 -#define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 -#define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 -#define EPNUM 0xf0 /* EP number */ -#define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 - -/* Bit masks for USB_DMAxADDRHIGH */ - -#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxADDRLOW */ - -#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTHIGH */ - -#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTLOW */ - -#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ - -#endif /* _DEF_BF525_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h deleted file mode 100644 index aeb84795b35e..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/defBF527.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF527_H -#define _DEF_BF527_H - -/* BF527 is BF525 + EMAC */ -#include "defBF525.h" - -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ - -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ - -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ - -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ - -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ - -/* Listing for IEEE-Supported Count Registers */ - -#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ -#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ -#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ -#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ -#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ -#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ -#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ -#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ -#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ -#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ -#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ -#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ -#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ -#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ -#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ -#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ -#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ -#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ -#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ -#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ -#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ -#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ -#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ -#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ -#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ -#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ -#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ -#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ -#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ -#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ -#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ -#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ -#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ -#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ -#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ -#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ -#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ - -/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ - -/* EMAC_OPMODE Masks */ - -#define RE 0x00000001 /* Receiver Enable */ -#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ -#define HU 0x00000010 /* Hash Filter Unicast Address */ -#define HM 0x00000020 /* Hash Filter Multicast Address */ -#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ -#define PR 0x00000080 /* Promiscuous Mode Enable */ -#define IFE 0x00000100 /* Inverse Filtering Enable */ -#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ -#define PBF 0x00000400 /* Pass Bad Frames Enable */ -#define PSF 0x00000800 /* Pass Short Frames Enable */ -#define RAF 0x00001000 /* Receive-All Mode */ -#define TE 0x00010000 /* Transmitter Enable */ -#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ -#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ -#define DC 0x00080000 /* Deferral Check */ -#define BOLMT 0x00300000 /* Back-Off Limit */ -#define BOLMT_10 0x00000000 /* 10-bit range */ -#define BOLMT_8 0x00100000 /* 8-bit range */ -#define BOLMT_4 0x00200000 /* 4-bit range */ -#define BOLMT_1 0x00300000 /* 1-bit range */ -#define DRTY 0x00400000 /* Disable TX Retry On Collision */ -#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ -#define RMII 0x01000000 /* RMII/MII* Mode */ -#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ -#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ -#define LB 0x08000000 /* Internal Loopback Enable */ -#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ - -/* EMAC_STAADD Masks */ - -#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ -#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ -#define STADISPRE 0x00000004 /* Disable Preamble Generation */ -#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ -#define REGAD 0x000007C0 /* STA Register Address */ -#define PHYAD 0x0000F800 /* PHY Device Address */ - -#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ -#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ - -/* EMAC_STADAT Mask */ - -#define STADATA 0x0000FFFF /* Station Management Data */ - -/* EMAC_FLC Masks */ - -#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ -#define FLCE 0x00000002 /* Flow Control Enable */ -#define PCF 0x00000004 /* Pass Control Frames */ -#define BKPRSEN 0x00000008 /* Enable Backpressure */ -#define FLCPAUSE 0xFFFF0000 /* Pause Time */ - -#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ - -/* EMAC_WKUP_CTL Masks */ - -#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ -#define MPKE 0x00000002 /* Magic Packet Enable */ -#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ -#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ -#define MPKS 0x00000020 /* Magic Packet Received Status */ -#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ - -/* EMAC_WKUP_FFCMD Masks */ - -#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ -#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ -#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ -#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ -#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ -#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ -#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ -#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ - -/* EMAC_WKUP_FFOFF Masks */ - -#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ -#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ -#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ -#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ - -#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ -#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ -#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ -#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ -/* Set ALL Offsets */ -#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) - -/* EMAC_WKUP_FFCRC0 Masks */ - -#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ -#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ - -#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ -#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ - -/* EMAC_WKUP_FFCRC1 Masks */ - -#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ -#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ - -#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ -#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ - -/* EMAC_SYSCTL Masks */ - -#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ -#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ -#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ -#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ -#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ - -#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ - -/* EMAC_SYSTAT Masks */ - -#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ -#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ -#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ -#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ -#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ -#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ -#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ -#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ - -/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ - -#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ -#define RX_COMP 0x00001000 /* RX Frame Complete */ -#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ -#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ -#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ -#define RX_CRC 0x00010000 /* RX Frame CRC Error */ -#define RX_LEN 0x00020000 /* RX Frame Length Error */ -#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ -#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ -#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ -#define RX_PHY 0x00200000 /* RX Frame PHY Error */ -#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ -#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ -#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ -#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ -#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ -#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ -#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ -#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ -#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ -#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ - -/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ - -#define TX_COMP 0x00000001 /* TX Frame Complete */ -#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ -#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ -#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ -#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ -#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ -#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ -#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ -#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ -#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ -#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ -#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ -#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ -#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ -#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ - -/* EMAC_MMC_CTL Masks */ -#define RSTC 0x00000001 /* Reset All Counters */ -#define CROLL 0x00000002 /* Counter Roll-Over Enable */ -#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ -#define MMCE 0x00000008 /* Enable MMC Counter Operation */ - -/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ -#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ -#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ -#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ -#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ -#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ -#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ -#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ -#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ -#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ -#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ -#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ -#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ -#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ -#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ -#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ -#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ -#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ -#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ -#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ -#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ -#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ -#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ -#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ -#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ - -/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ - -#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ -#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ -#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ -#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ -#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ -#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ -#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ -#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ -#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ -#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ -#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ -#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ -#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ -#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ -#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ -#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ -#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ -#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ -#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ -#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ -#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ -#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ -#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ - -#endif /* _DEF_BF527_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h deleted file mode 100644 index eb287da101a2..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/dma.h +++ /dev/null @@ -1,38 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define MAX_DMA_CHANNELS 16 - -#define CH_PPI 0 /* PPI receive/transmit or NFC */ -#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ -#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */ -#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */ -#define CH_SPORT0_RX 3 /* SPORT0 receive */ -#define CH_SPORT0_TX 4 /* SPORT0 transmit */ -#define CH_SPORT1_RX 5 /* SPORT1 receive */ -#define CH_SPORT1_TX 6 /* SPORT1 transmit */ -#define CH_SPI 7 /* SPI transmit/receive */ -#define CH_UART0_RX 8 /* UART0 receive */ -#define CH_UART0_TX 9 /* UART0 transmit */ -#define CH_UART1_RX 10 /* UART1 receive */ -#define CH_UART1_TX 11 /* UART1 transmit */ - -#define CH_MEM_STREAM0_DEST 12 /* TX */ -#define CH_MEM_STREAM0_SRC 13 /* RX */ -#define CH_MEM_STREAM1_DEST 14 /* TX */ -#define CH_MEM_STREAM1_SRC 15 /* RX */ - -#if defined(CONFIG_BF527_NAND_D_PORTF) -#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */ -#elif defined(CONFIG_BF527_NAND_D_PORTH) -#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ -#endif - -#endif diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h deleted file mode 100644 index fba606b699c3..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/gpio.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 48 - -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 -#define GPIO_PG0 16 -#define GPIO_PG1 17 -#define GPIO_PG2 18 -#define GPIO_PG3 19 -#define GPIO_PG4 20 -#define GPIO_PG5 21 -#define GPIO_PG6 22 -#define GPIO_PG7 23 -#define GPIO_PG8 24 -#define GPIO_PG9 25 -#define GPIO_PG10 26 -#define GPIO_PG11 27 -#define GPIO_PG12 28 -#define GPIO_PG13 29 -#define GPIO_PG14 30 -#define GPIO_PG15 31 -#define GPIO_PH0 32 -#define GPIO_PH1 33 -#define GPIO_PH2 34 -#define GPIO_PH3 35 -#define GPIO_PH4 36 -#define GPIO_PH5 37 -#define GPIO_PH6 38 -#define GPIO_PH7 39 -#define GPIO_PH8 40 -#define GPIO_PH9 41 -#define GPIO_PH10 42 -#define GPIO_PH11 43 -#define GPIO_PH12 44 -#define GPIO_PH13 45 -#define GPIO_PH14 46 -#define GPIO_PH15 47 - -#define PORT_F GPIO_PF0 -#define PORT_G GPIO_PG0 -#define PORT_H GPIO_PH0 - -#include -#include -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h deleted file mode 100644 index ed7310ff819b..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/irq.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BF527_IRQ_H_ -#define _BF527_IRQ_H_ - -#include - -#define NR_PERI_INTS (2 * 32) - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ -#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ -#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */ -#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */ -#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */ -#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */ -#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */ -#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */ -#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */ -#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ -#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ -#define IRQ_RTC BFIN_IRQ(14) /* RTC */ -#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ -#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ -#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ -#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ -#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ -#define IRQ_TWI BFIN_IRQ(20) /* TWI */ -#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ -#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ -#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ -#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ -#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ -#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ -#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ -#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ -#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ -#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ -#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ -#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ -#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ -#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ -#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ -#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ -#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ -#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ -#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ -#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ -#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ -#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ -#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ -#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */ -#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */ -#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */ -#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */ -#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */ -#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */ -#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */ -#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */ -#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */ -#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */ -#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */ -#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ -#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ - -#define SYS_IRQS BFIN_IRQ(63) /* 70 */ - -#define IRQ_PF0 71 -#define IRQ_PF1 72 -#define IRQ_PF2 73 -#define IRQ_PF3 74 -#define IRQ_PF4 75 -#define IRQ_PF5 76 -#define IRQ_PF6 77 -#define IRQ_PF7 78 -#define IRQ_PF8 79 -#define IRQ_PF9 80 -#define IRQ_PF10 81 -#define IRQ_PF11 82 -#define IRQ_PF12 83 -#define IRQ_PF13 84 -#define IRQ_PF14 85 -#define IRQ_PF15 86 - -#define IRQ_PG0 87 -#define IRQ_PG1 88 -#define IRQ_PG2 89 -#define IRQ_PG3 90 -#define IRQ_PG4 91 -#define IRQ_PG5 92 -#define IRQ_PG6 93 -#define IRQ_PG7 94 -#define IRQ_PG8 95 -#define IRQ_PG9 96 -#define IRQ_PG10 97 -#define IRQ_PG11 98 -#define IRQ_PG12 99 -#define IRQ_PG13 100 -#define IRQ_PG14 101 -#define IRQ_PG15 102 - -#define IRQ_PH0 103 -#define IRQ_PH1 104 -#define IRQ_PH2 105 -#define IRQ_PH3 106 -#define IRQ_PH4 107 -#define IRQ_PH5 108 -#define IRQ_PH6 109 -#define IRQ_PH7 110 -#define IRQ_PH8 111 -#define IRQ_PH9 112 -#define IRQ_PH10 113 -#define IRQ_PH11 114 -#define IRQ_PH12 115 -#define IRQ_PH13 116 -#define IRQ_PH14 117 -#define IRQ_PH15 118 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ -#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ -#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ -#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ -#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ -#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ -#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ -#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ - -#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) - -/* IAR0 BIT FIELDS */ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA0_ERROR_POS 4 -#define IRQ_DMAR0_BLK_POS 8 -#define IRQ_DMAR1_BLK_POS 12 -#define IRQ_DMAR0_OVR_POS 16 -#define IRQ_DMAR1_OVR_POS 20 -#define IRQ_PPI_ERROR_POS 24 -#define IRQ_MAC_ERROR_POS 28 - -/* IAR1 BIT FIELDS */ -#define IRQ_SPORT0_ERROR_POS 0 -#define IRQ_SPORT1_ERROR_POS 4 -#define IRQ_UART0_ERROR_POS 16 -#define IRQ_UART1_ERROR_POS 20 -#define IRQ_RTC_POS 24 -#define IRQ_PPI_POS 28 - -/* IAR2 BIT FIELDS */ -#define IRQ_SPORT0_RX_POS 0 -#define IRQ_SPORT0_TX_POS 4 -#define IRQ_SPORT1_RX_POS 8 -#define IRQ_SPORT1_TX_POS 12 -#define IRQ_TWI_POS 16 -#define IRQ_SPI_POS 20 -#define IRQ_UART0_RX_POS 24 -#define IRQ_UART0_TX_POS 28 - -/* IAR3 BIT FIELDS */ -#define IRQ_UART1_RX_POS 0 -#define IRQ_UART1_TX_POS 4 -#define IRQ_OPTSEC_POS 8 -#define IRQ_CNT_POS 12 -#define IRQ_MAC_RX_POS 16 -#define IRQ_PORTH_INTA_POS 20 -#define IRQ_MAC_TX_POS 24 -#define IRQ_PORTH_INTB_POS 28 - -/* IAR4 BIT FIELDS */ -#define IRQ_TIMER0_POS 0 -#define IRQ_TIMER1_POS 4 -#define IRQ_TIMER2_POS 8 -#define IRQ_TIMER3_POS 12 -#define IRQ_TIMER4_POS 16 -#define IRQ_TIMER5_POS 20 -#define IRQ_TIMER6_POS 24 -#define IRQ_TIMER7_POS 28 - -/* IAR5 BIT FIELDS */ -#define IRQ_PORTG_INTA_POS 0 -#define IRQ_PORTG_INTB_POS 4 -#define IRQ_MEM_DMA0_POS 8 -#define IRQ_MEM_DMA1_POS 12 -#define IRQ_WATCH_POS 16 -#define IRQ_PORTF_INTA_POS 20 -#define IRQ_PORTF_INTB_POS 24 -#define IRQ_SPI_ERROR_POS 28 - -/* IAR6 BIT FIELDS */ -#define IRQ_NFC_ERROR_POS 0 -#define IRQ_HDMA_ERROR_POS 4 -#define IRQ_HDMA_POS 8 -#define IRQ_USB_EINT_POS 12 -#define IRQ_USB_INT0_POS 16 -#define IRQ_USB_INT1_POS 20 -#define IRQ_USB_INT2_POS 24 -#define IRQ_USB_DMA_POS 28 - -#endif diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h deleted file mode 100644 index d96e894afd2c..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/mem_map.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * BF52x memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x8000 - -/* Level 1 Memory */ - -/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */ - -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#else -#define BFIN_ICACHESIZE (0*1024) -#endif - -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#define L1_CODE_LENGTH 0xC000 - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE */ - -#endif diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h deleted file mode 100644 index 94cca674d835..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h deleted file mode 100644 index 08bae421f5c9..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/portmux.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define MAX_RESOURCES MAX_BLACKFIN_GPIOS - -#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) -#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) -#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) -#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) - -#if defined(CONFIG_BF527_SPORT0_PORTF) -#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) -#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) -#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) -#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) -#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) -#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) -#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) -#elif defined(CONFIG_BF527_SPORT0_PORTG) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) -#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) -#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) -#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) -#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) -#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) -#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10) -#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) -#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14) -#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) -#endif -#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) -#endif - -#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) -#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) -#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) -#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) -#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) -#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) -#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) -#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) - -#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) -#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) - -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) - -#if defined(CONFIG_BF527_UART1_PORTF) -#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) -#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) -#elif defined(CONFIG_BF527_UART1_PORTG) -#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) -#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) -#endif - -#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3)) -#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3)) -#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3)) - -#define P_HWAIT (P_DONTCARE) - -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 - -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) -#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) -#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) -#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) -#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) -#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) -#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) -#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) -#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) -#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) -/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */ -#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) -#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) -#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) -#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) -#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) -#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) -#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) - -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) -#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) -#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) - -#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) -#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) -#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) -#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) -#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) - -#if defined(CONFIG_BF527_NAND_D_PORTF) -#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) -#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) -#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) -#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) -#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) -#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) -#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) -#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) -#elif defined(CONFIG_BF527_NAND_D_PORTH) -#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) -#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) -#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) -#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) -#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) -#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) -#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) -#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) -#endif - -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) -#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) -#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) -#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) -#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) -#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) -#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) - -#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2)) -#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2)) -#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) -#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) -#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) -#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2)) -#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2)) -#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2)) -#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2)) -#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2)) -#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2)) -#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2)) -#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2)) -#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2)) -#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2)) -#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2)) - -#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) -#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) -#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1)) -#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1)) -#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) -#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) -#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) -#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) -#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1)) -#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1)) -#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1)) -#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1)) -#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1)) -#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) -#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) -#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) -#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) -#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) - -#define P_TWI0_SCL (P_DONTCARE) -#define P_TWI0_SDA (P_DONTCARE) -#define P_PPI0_FS1 (P_DONTCARE) -#define P_TMR0 (P_DONTCARE) -#define P_TMRCLK (P_DONTCARE) -#define P_PPI0_CLK (P_DONTCARE) - -#define P_MII0 {\ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxD2, \ - P_MII0_ETxD3, \ - P_MII0_ETxEN, \ - P_MII0_TxCLK, \ - P_MII0_PHYINT, \ - P_MII0_COL, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxD2, \ - P_MII0_ERxD3, \ - P_MII0_ERxDV, \ - P_MII0_ERxCLK, \ - P_MII0_ERxER, \ - P_MII0_CRS, \ - P_MDC, \ - P_MDIO, 0} - -#define P_RMII0 {\ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxEN, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxER, \ - P_RMII0_REF_CLK, \ - P_RMII0_MDINT, \ - P_RMII0_CRS_DV, \ - P_MDC, \ - P_MDIO, 0} - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c deleted file mode 100644 index 44ca215bf164..000000000000 --- a/arch/blackfin/mach-bf527/ints-priority.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | - ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) | - ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) | - ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) | - ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) | - ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) | - ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) | - ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS)); - - - bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | - ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) | - ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) | - ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) | - ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) | - ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS)); - - bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | - ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | - ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | - ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | - ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) | - ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) | - ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | - ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); - - bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | - ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | - ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) | - ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) | - ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) | - ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) | - ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | - ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); - - bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | - ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | - ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | - ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | - ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | - ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | - ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | - ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS)); - - bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | - ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | - ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) | - ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) | - ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) | - ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) | - ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) | - ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS)); - - bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) | - ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) | - ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) | - ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) | - ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) | - ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) | - ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) | - ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS)); - - SSYNC(); -} diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig deleted file mode 100644 index 4e1a05be7137..000000000000 --- a/arch/blackfin/mach-bf533/Kconfig +++ /dev/null @@ -1,96 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if (BF533 || BF532 || BF531) - -source "arch/blackfin/mach-bf533/boards/Kconfig" - -menu "BF533/2/1 Specific Configuration" - -comment "Interrupt Priority Assignment" -menu "Priority" - -config UART_ERROR - int "UART ERROR" - default 7 -config SPORT0_ERROR - int "SPORT0 ERROR" - default 7 -config SPI_ERROR - int "SPI ERROR" - default 7 -config SPORT1_ERROR - int "SPORT1 ERROR" - default 7 -config PPI_ERROR - int "PPI ERROR" - default 7 -config DMA_ERROR - int "DMA ERROR" - default 7 -config PLLWAKE_ERROR - int "PLL WAKEUP ERROR" - default 7 - -config RTC_ERROR - int "RTC ERROR" - default 8 -config DMA0_PPI - int "DMA0 PPI" - default 8 - -config DMA1_SPORT0RX - int "DMA1 (SPORT0 RX)" - default 9 -config DMA2_SPORT0TX - int "DMA2 (SPORT0 TX)" - default 9 -config DMA3_SPORT1RX - int "DMA3 (SPORT1 RX)" - default 9 -config DMA4_SPORT1TX - int "DMA4 (SPORT1 TX)" - default 9 -config DMA5_SPI - int "DMA5 (SPI)" - default 10 -config DMA6_UARTRX - int "DMA6 (UART0 RX)" - default 10 -config DMA7_UARTTX - int "DMA7 (UART0 TX)" - default 10 -config TIMER0 - int "TIMER0" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config TIMER1 - int "TIMER1" - default 11 -config TIMER2 - int "TIMER2" - default 11 -config PFA - int "PF Interrupt A" - default 12 -config PFB - int "PF Interrupt B" - default 12 -config MEMDMA0 - int "MEMORY DMA0" - default 13 -config MEMDMA1 - int "MEMORY DMA1" - default 13 -config WDTIMER - int "WATCH DOG TIMER" - default 13 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile deleted file mode 100644 index 874840f76028..000000000000 --- a/arch/blackfin/mach-bf533/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf533/Makefile -# - -obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c deleted file mode 100644 index 01300f40db15..000000000000 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2007-2008 HV Sistemas S.L. - * Javier Herrero - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include - -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "HV Sistemas H8606"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* -* Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_DM9000) -static struct resource dm9000_resources[] = { - [0] = { - .start = 0x20300000, - .end = 0x20300002, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x20300004, - .end = 0x20300006, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | - IORESOURCE_IRQ_SHAREABLE), - }, -}; - -static struct platform_device dm9000_device = { - .id = 0, - .name = "dm9000", - .resource = dm9000_resources, - .num_resources = ARRAY_SIZE(dm9000_resources), -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PROG_INTB, - .end = IRQ_PROG_INTB, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader (spi)", - .size = 0x40000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "fpga (spi)", - .size = 0x30000, - .offset = 0x40000 - }, { - .name = "linux kernel (spi)", - .size = 0x150000, - .offset = 0x70000 - }, { - .name = "jffs2 root file system (spi)", - .size = 0x640000, - .offset = 0x1c0000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -/* Notice: for blackfin, the speed_hz is the value of register - * SPI_BAUD, not the real baudrate */ -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - /* this value is the baudrate divisor */ - .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 16, - .bus_num = 1, - .chip_select = 4, - }, -#endif - -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_8250) - -#include -#include - -/* - * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010. - * running at half system clock, both with interrupt output or-ed to PF8. Change to - * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus - */ - -static struct plat_serial8250_port serial8250_platform_data [] = { - { - .membase = (void *)0x20200000, - .mapbase = 0x20200000, - .irq = IRQ_PF8, - .irqflags = IRQF_TRIGGER_HIGH, - .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, - .iotype = UPIO_MEM, - .regshift = 1, - .uartclk = 66666667, - }, { - .membase = (void *)0x20200010, - .mapbase = 0x20200010, - .irq = IRQ_PF8, - .irqflags = IRQF_TRIGGER_HIGH, - .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, - .iotype = UPIO_MEM, - .regshift = 1, - .uartclk = 66666667, - }, { - } -}; - -static struct platform_device serial8250_device = { - .id = PLAT8250_DEV_PLATFORM, - .name = "serial8250", - .dev = { - .platform_data = serial8250_platform_data, - }, -}; - -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES) - -/* - * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030, - * interrupt output wired to PF9. Change to suit different FPGA configuration - */ - -static struct resource opencores_kbd_resources[] = { - [0] = { - .start = 0x20200030, - .end = 0x20300030 + 2, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device opencores_kbd_device = { - .id = -1, - .name = "opencores-kbd", - .resource = opencores_kbd_resources, - .num_resources = ARRAY_SIZE(opencores_kbd_resources), -}; -#endif - -static struct platform_device *h8606_devices[] __initdata = { -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_DM9000) - &dm9000_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_8250) - &serial8250_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES) - &opencores_kbd_device, -#endif -}; - -static int __init H8606_init(void) -{ - printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n"); - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - return 0; -} - -arch_initcall(H8606_init); - -static struct platform_device *H8606_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(H8606_early_devices, - ARRAY_SIZE(H8606_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig deleted file mode 100644 index 3fde0df1b5f2..000000000000 --- a/arch/blackfin/mach-bf533/boards/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN533_STAMP - help - Select your board! - -config BFIN533_EZKIT - bool "BF533-EZKIT" - help - BF533-EZKIT-LITE board support. - -config BFIN533_STAMP - bool "BF533-STAMP" - help - BF533-STAMP board support. - -config BLACKSTAMP - bool "BlackStamp" - help - Support for the BlackStamp board. Hardware info available at - http://blackfin.uclinux.org/gf/project/blackstamp/ - -config BFIN533_BLUETECHNIX_CM - bool "Bluetechnix CM-BF533" - depends on (BF533) - help - CM-BF533 support for EVAL- and DEV-Board. - -config H8606_HVSISTEMAS - bool "HV Sistemas H8606" - depends on (BF532) - help - HV Sistemas H8606 board support. - -config BFIN532_IP0X - bool "IP04/IP08 IP-PBX" - depends on (BF532) - help - Core support for IP04/IP04 open hardware IP-PBX. - -endchoice diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile deleted file mode 100644 index 35256d2fc040..000000000000 --- a/arch/blackfin/mach-bf533/boards/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/mach-bf533/boards/Makefile -# - -obj-$(CONFIG_BFIN533_STAMP) += stamp.o -obj-$(CONFIG_BFIN532_IP0X) += ip0x.o -obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o -obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o -obj-$(CONFIG_BLACKSTAMP) += blackstamp.o -obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c deleted file mode 100644 index fab69c736515..000000000000 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ /dev/null @@ -1,523 +0,0 @@ -/* - * Board Info File for the BlackStamp - * - * Copyright 2004-2008 Analog Devices Inc. - * 2008 Benjamin Matthews - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * More info about the BlackStamp at: - * http://blackfin.uclinux.org/gf/project/blackstamp/ - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "BlackStamp"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF3, - .end = IRQ_PF3, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. */ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 7, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF4, 0, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF5, 0, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF6, 0, "gpio-keys: BTN2"}, -}; /* Mapped to the first three PF Test Points */ - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) -#include - -static struct gpiod_lookup_table bfin_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data i2c_gpio_data = { - .udelay = 40, -}; /* This hasn't actually been used these pins - * are (currently) free pins on the expansion connector */ - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -}; - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) - &i2c_gpio_device, -#endif -}; - -static int __init blackstamp_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); -#if IS_ENABLED(CONFIG_I2C_GPIO) - gpiod_add_lookup_table(&bfin_i2c_gpiod_table); -#endif - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - - ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - if (ret < 0) - return ret; - -#if IS_ENABLED(CONFIG_SMC91X) - /* - * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC. - * the bfin-async-map driver takes care of flipping between - * flash and ethernet when necessary. - */ - ret = gpio_request(GPIO_PF0, "enet_cpld"); - if (!ret) { - gpio_direction_output(GPIO_PF0, 1); - gpio_free(GPIO_PF0); - } -#endif - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(blackstamp_init); - -static struct platform_device *stamp_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(stamp_early_devices, - ARRAY_SIZE(stamp_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c deleted file mode 100644 index 4ef2fb0e48d5..000000000000 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix CM BF533"; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = 0x20000 - }, { - .name = "file system(spi)", - .size = 0x700000, - .offset = 0x00100000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .start = 0x20200300, - .end = 0x20200300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF0, - .end = IRQ_PF0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) -#include - -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x20308000, - .end = 0x20308000 + 0xFF, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF8, - .end = IRQ_PF8, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_16BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20308000, - .end = 0x20308000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20308004, - .end = 0x20308004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF6, - .end = IRQ_PF6, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - - - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition para_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux+rootfs(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data para_flash_data = { - .width = 2, - .parts = para_partitions, - .nr_parts = ARRAY_SIZE(para_partitions), -}; - -static struct resource para_flash_resource = { - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device para_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = ¶_flash_data, - }, - .num_resources = 1, - .resource = ¶_flash_resource, -}; -#endif - - - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cm_bf533_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) - &smsc911x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - ¶_flash_device, -#endif -}; - -static int __init cm_bf533_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - return 0; -} - -arch_initcall(cm_bf533_init); - -static struct platform_device *cm_bf533_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cm_bf533_early_devices, - ARRAY_SIZE(cm_bf533_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c deleted file mode 100644 index d64d270e9e62..000000000000 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF533-EZKIT"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* - * USB-LAN EzExtender board - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20310300, - .end = 0x20310300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezkit_partitions_a[] = { - { - .name = "bootloader(nor a)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor a)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data ezkit_flash_data_a = { - .width = 2, - .parts = ezkit_partitions_a, - .nr_parts = ARRAY_SIZE(ezkit_partitions_a), -}; - -static struct resource ezkit_flash_resource_a = { - .start = 0x20000000, - .end = 0x200fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device_a = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezkit_flash_data_a, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource_a, -}; - -static struct mtd_partition ezkit_partitions_b[] = { - { - .name = "file system(nor b)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data ezkit_flash_data_b = { - .width = 2, - .parts = ezkit_partitions_b, - .nr_parts = ARRAY_SIZE(ezkit_partitions_b), -}; - -static struct resource ezkit_flash_resource_b = { - .start = 0x20100000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device_b = { - .name = "physmap-flash", - .id = 4, - .dev = { - .platform_data = &ezkit_flash_data_b, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource_b, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PLATRAM) -static struct platdata_mtd_ram sram_data_a = { - .mapname = "Flash A SRAM", - .bankwidth = 2, -}; - -static struct resource sram_resource_a = { - .start = 0x20240000, - .end = 0x2024ffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device sram_device_a = { - .name = "mtd-ram", - .id = 8, - .dev = { - .platform_data = &sram_data_a, - }, - .num_resources = 1, - .resource = &sram_resource_a, -}; - -static struct platdata_mtd_ram sram_data_b = { - .mapname = "Flash B SRAM", - .bankwidth = 2, -}; - -static struct resource sram_resource_b = { - .start = 0x202c0000, - .end = 0x202cffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device sram_device_b = { - .name = "mtd-ram", - .id = 9, - .dev = { - .platform_data = &sram_data_b, - }, - .num_resources = 1, - .resource = &sram_resource_b, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"}, - {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) -#include - -static struct gpiod_lookup_table bfin_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data i2c_gpio_data = { - .udelay = 40, -}; - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97 = { - .name = "bfin-ac97", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -static struct platform_device *ezkit_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezkit_flash_device_a, - &ezkit_flash_device_b, -#endif - -#if IS_ENABLED(CONFIG_MTD_PLATRAM) - &sram_device_a, - &sram_device_b, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) - &i2c_gpio_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97, -#endif -}; - -static int __init ezkit_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); -#if IS_ENABLED(CONFIG_I2C_GPIO) - gpiod_add_lookup_table(&bfin_i2c_gpiod_table); -#endif - platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - return 0; -} - -arch_initcall(ezkit_init); - -static struct platform_device *ezkit_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezkit_early_devices, - ARRAY_SIZE(ezkit_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c deleted file mode 100644 index 39c8e8547b82..000000000000 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2007 David Rowe - * 2006 Intratrade Ltd. - * Ivan Danov - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "IP04/IP08"; - -/* - * Driver needs to know address, irq and flag pin. - */ -#if defined(CONFIG_BFIN532_IP0X) -#if IS_ENABLED(CONFIG_DM9000) - -#include - -static struct resource dm9000_resource1[] = { - { - .start = 0x20100000, - .end = 0x20100000 + 1, - .flags = IORESOURCE_MEM - },{ - .start = 0x20100000 + 2, - .end = 0x20100000 + 3, - .flags = IORESOURCE_MEM - },{ - .start = IRQ_PF15, - .end = IRQ_PF15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE - } -}; - -static struct resource dm9000_resource2[] = { - { - .start = 0x20200000, - .end = 0x20200000 + 1, - .flags = IORESOURCE_MEM - },{ - .start = 0x20200000 + 2, - .end = 0x20200000 + 3, - .flags = IORESOURCE_MEM - },{ - .start = IRQ_PF14, - .end = IRQ_PF14, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE - } -}; - -/* -* for the moment we limit ourselves to 16bit IO until some -* better IO routines can be written and tested -*/ -static struct dm9000_plat_data dm9000_platdata1 = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device dm9000_device1 = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9000_resource1), - .resource = dm9000_resource1, - .dev = { - .platform_data = &dm9000_platdata1, - } -}; - -static struct dm9000_plat_data dm9000_platdata2 = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device dm9000_device2 = { - .name = "dm9000", - .id = 1, - .num_resources = ARRAY_SIZE(dm9000_resource2), - .resource = dm9000_resource2, - .dev = { - .platform_data = &dm9000_platdata2, - } -}; - -#endif -#endif - - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, /* if 1 - block!!! */ -}; -#endif - -/* Notice: for blackfin, the speed_hz is the value of register - * SPI_BAUD, not the real baudrate */ -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 2, - .bus_num = 1, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - }, -#endif -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master spi_bfin_master_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ -}; - -static struct platform_device spi_bfin_master_device = { - .name = "bfin-spi-master", - .id = 1, /* Bus number */ - .dev = { - .platform_data = &spi_bfin_master_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 1, - .flags = IORESOURCE_MEM, - },{ - .start = 0x20300000 + 2, - .end = 0x20300000 + 3, - .flags = IORESOURCE_MEM, - },{ - .start = IRQ_PF11, - .end = IRQ_PF11, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, /* external OC */ - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - - -static struct platform_device *ip0x_devices[] __initdata = { -#if defined(CONFIG_BFIN532_IP0X) -#if IS_ENABLED(CONFIG_DM9000) - &dm9000_device1, - &dm9000_device2, -#endif -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &spi_bfin_master_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif -}; - -static int __init ip0x_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - - return 0; -} - -arch_initcall(ip0x_init); - -static struct platform_device *ip0x_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ip0x_early_devices, - ARRAY_SIZE(ip0x_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c deleted file mode 100644 index 27cbf2fa2c62..000000000000 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ /dev/null @@ -1,919 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF533-STAMP"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = 1, - .flags = IORESOURCE_BUS, - }, { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC) -static struct mtd_partition stamp_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data stamp_flash_data = { - .width = 2, - .parts = stamp_partitions, - .nr_parts = ARRAY_SIZE(stamp_partitions), -}; - -static struct resource stamp_flash_resource[] = { - { - .name = "cfi_probe", - .start = 0x20000000, - .end = 0x203fffff, - .flags = IORESOURCE_MEM, - }, { - .start = 0x7BB07BB0, /* AMBCTL0 setting when accessing flash */ - .end = 0x7BB07BB0, /* AMBCTL1 setting when accessing flash */ - .flags = IORESOURCE_MEM, - }, { - .start = GPIO_PF0, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device stamp_flash_device = { - .name = "bfin-async-flash", - .id = 0, - .dev = { - .platform_data = &stamp_flash_data, - }, - .num_resources = ARRAY_SIZE(stamp_flash_resource), - .resource = stamp_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -#define MMC_SPI_CARD_DETECT_INT IRQ_PF5 -static int bfin_mmc_spi_init(struct device *dev, - irqreturn_t (*detect_int)(int, void *), void *data) -{ - return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "mmc-spi-detect", data); -} - -static void bfin_mmc_spi_exit(struct device *dev, void *data) -{ - free_irq(MMC_SPI_CARD_DETECT_INT, data); -} - -static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { - .init = bfin_mmc_spi_init, - .exit = bfin_mmc_spi_exit, - .detect_delay = 100, /* msecs */ -}; - -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, - .pio_interrupt = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - { - .modalias = "ad1836", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = "ad1836", /* only includes chip name for the moment */ - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = &bfin_mmc_spi_pdata, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SPORT) -static struct resource bfin_sport0_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_TX, - .end = IRQ_SPORT0_TX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_SPORT0_TX, - .end = CH_SPORT0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_SPORT0_RX, - .end = CH_SPORT0_RX, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sport0_device = { - .name = "bfin_sport_raw", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_resources), - .resource = bfin_sport0_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) -#include - -static struct gpiod_lookup_table bfin_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data i2c_gpio_data = { - .udelay = 10, -}; - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_JOYSTICK_AD7142) - { - I2C_BOARD_INFO("ad7142_joystick", 0x2C), - .irq = 39, - }, -#endif -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = 39, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("ad5252", 0x2f), - }, -#endif -}; - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \ - IS_ENABLED(CONFIG_SND_BF5XX_AC97) - -#include - -#define SPORT_REQ(x) \ - [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \ - P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0} - -static const u16 bfin_snd_pin[][7] = { - SPORT_REQ(0), - SPORT_REQ(1), -}; - -static struct bfin_snd_platform_data bfin_snd_data[] = { - { - .pin_req = &bfin_snd_pin[0][0], - }, - { - .pin_req = &bfin_snd_pin[1][0], - }, -}; - -#define BFIN_SND_RES(x) \ - [x] = { \ - { \ - .start = SPORT##x##_TCR1, \ - .end = SPORT##x##_TCR1, \ - .flags = IORESOURCE_MEM \ - }, \ - { \ - .start = CH_SPORT##x##_RX, \ - .end = CH_SPORT##x##_RX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = CH_SPORT##x##_TX, \ - .end = CH_SPORT##x##_TX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = IRQ_SPORT##x##_ERROR, \ - .end = IRQ_SPORT##x##_ERROR, \ - .flags = IORESOURCE_IRQ, \ - } \ - } - -static struct resource bfin_snd_resources[][4] = { - BFIN_SND_RES(0), - BFIN_SND_RES(1), -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s_pcm = { - .name = "bfin-i2s-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97_pcm = { - .name = "bfin-ac97-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) -static const char * const ad1836_link[] = { - "bfin-i2s.0", - "spi0.4", -}; -static struct platform_device bfin_ad1836_machine = { - .name = "bfin-snd-ad1836", - .id = -1, - .dev = { - .platform_data = (void *)ad1836_link, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) -static const unsigned ad73311_gpio[] = { - GPIO_PF4, -}; - -static struct platform_device bfin_ad73311_machine = { - .name = "bfin-snd-ad73311", - .id = 1, - .dev = { - .platform_data = (void *)ad73311_gpio, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD73311) -static struct platform_device bfin_ad73311_codec_device = { - .name = "ad73311", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD74111) -static struct platform_device bfin_ad74111_codec_device = { - .name = "ad74111", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = - ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) -static struct platform_device bfin_ac97 = { - .name = "bfin-ac97", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = - ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) - &i2c_gpio_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC) - &stamp_flash_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - &bfin_ad1836_machine, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) - &bfin_ad73311_machine, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD73311) - &bfin_ad73311_codec_device, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD74111) - &bfin_ad74111_codec_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) - &bfin_ac97, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */ - ret = gpio_request(GPIO_PF0, "net2272"); - if (ret) - return ret; - - ret = gpio_request(GPIO_PF1, "net2272"); - if (ret) { - gpio_free(GPIO_PF0); - return ret; - } - - ret = gpio_request(GPIO_PF11, "net2272"); - if (ret) { - gpio_free(GPIO_PF0); - gpio_free(GPIO_PF1); - return ret; - } - - gpio_direction_output(GPIO_PF0, 0); - gpio_direction_output(GPIO_PF1, 1); - - /* Reset the USB chip */ - gpio_direction_output(GPIO_PF11, 0); - mdelay(2); - gpio_set_value(GPIO_PF11, 1); -#endif - - return 0; -} - -static int __init stamp_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - -#if IS_ENABLED(CONFIG_I2C_GPIO) - gpiod_add_lookup_table(&bfin_i2c_gpiod_table); -#endif - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - - ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - if (ret < 0) - return ret; - -#if IS_ENABLED(CONFIG_SMC91X) - /* - * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC. - * the bfin-async-map driver takes care of flipping between - * flash and ethernet when necessary. - */ - ret = gpio_request(GPIO_PF0, "enet_cpld"); - if (!ret) { - gpio_direction_output(GPIO_PF0, 1); - gpio_free(GPIO_PF0); - } -#endif - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(stamp_init); - -static struct platform_device *stamp_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(stamp_early_devices, - ARRAY_SIZE(stamp_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround pull up on cpld / flash pin not being strong enough */ - gpio_request(GPIO_PF0, "flash_cpld"); - gpio_direction_output(GPIO_PF0, 0); -} diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c deleted file mode 100644 index 1f5988d43139..000000000000 --- a/arch/blackfin/mach-bf533/dma.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * simple DMA Implementation for Blackfin - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI: - ret_irq = IRQ_PPI; - break; - - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - - case CH_SPI: - ret_irq = IRQ_SPI; - break; - - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h deleted file mode 100644 index 0e754efc3cf6..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ /dev/null @@ -1,383 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 or 0.2 silicon - sorry */ -#if __SILICON_REVISION__ < 3 -# error will not work on BF533 silicon version 0.0, 0.1, or 0.2 -#endif - -#if defined(__ADSPBF531__) -# define ANOMALY_BF531 1 -#else -# define ANOMALY_BF531 0 -#endif -#if defined(__ADSPBF532__) -# define ANOMALY_BF532 1 -#else -# define ANOMALY_BF532 0 -#endif -#if defined(__ADSPBF533__) -# define ANOMALY_BF533 1 -#else -# define ANOMALY_BF533 0 -#endif - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ -#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ -#define ANOMALY_05000105 (__SILICON_REVISION__ > 2) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ -#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ -#define ANOMALY_05000166 (1) -/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ -#define ANOMALY_05000167 (1) -/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ -#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ -#define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions when Speculative Fetch Is Cancelled */ -#define ANOMALY_05000189 (__SILICON_REVISION__ < 4) -/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ -#define ANOMALY_05000193 (__SILICON_REVISION__ < 4) -/* Restarting SPORT in Specific Modes May Cause Data Corruption */ -#define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses when Preceding Memory Read Stalls */ -#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) -/* Current DMA Address Shows Wrong Value During Carry Fix */ -#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) -/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ -#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) -/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ -#define ANOMALY_05000201 (__SILICON_REVISION__ == 3) -/* Possible Infinite Stall with Specific Dual-DAG Situation */ -#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ -#define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ -#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) -/* Recovery from "Brown-Out" Condition */ -#define ANOMALY_05000207 (__SILICON_REVISION__ < 4) -/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ -#define ANOMALY_05000208 (1) -/* Speed Path in Computational Unit Affects Certain Instructions */ -#define ANOMALY_05000209 (__SILICON_REVISION__ < 4) -/* UART TX Interrupt Masked Erroneously */ -#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) -/* NMI Event at Boot Time Results in Unpredictable State */ -#define ANOMALY_05000219 (1) -/* Incorrect Pulse-Width of UART Start Bit */ -#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) -/* Scratchpad Memory Bank Reads May Return Incorrect Data */ -#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) -/* SPI Slave Boot Mode Modifies Registers from Reset Value */ -#define ANOMALY_05000229 (1) -/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ -#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) -/* UART STB Bit Incorrectly Affects Receiver Setting */ -#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ -#define ANOMALY_05000233 (__SILICON_REVISION__ < 6) -/* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) -/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent False Hardware Errors */ -#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) -/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ -#define ANOMALY_05000250 (__SILICON_REVISION__ == 4) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (__SILICON_REVISION__ > 4) -/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ -#define ANOMALY_05000255 (__SILICON_REVISION__ < 5) -/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) -/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ -#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) -/* ICPLB_STATUS MMR Register May Be Corrupted */ -#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) -/* Stores To Data Cache May Be Lost */ -#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) -/* Hardware Loop Corrupted When Taking an ICPLB Exception */ -#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) -/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ -#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ -#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (__SILICON_REVISION__ < 5) -/* Spontaneous Reset of Internal Voltage Regulator */ -#define ANOMALY_05000271 (__SILICON_REVISION__ == 3) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (__SILICON_REVISION__ < 6) -/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ -#define ANOMALY_05000276 (1) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) -/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ -#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ -#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) -/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ -#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ -#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ -#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) -/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ -#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (__SILICON_REVISION__ < 6) -/* UART Break Signal Issues */ -#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (__SILICON_REVISION__ < 6) -/* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ -#define ANOMALY_05000471 (1) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* Possible Lockup Condition when Modifying PLL from External Memory */ -#define ANOMALY_05000475 (1) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* PLL May Latch Incorrect Values Coming Out of Reset */ -#define ANOMALY_05000489 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) - -/* - * These anomalies have been "phased" out of analog.com anomaly sheets and are - * here to show running on older silicon just isn't feasible. - */ - -/* Internal voltage regulator can't be modified via register writes */ -#define ANOMALY_05000066 (__SILICON_REVISION__ < 2) -/* Watchpoints (Hardware Breakpoints) are not supported */ -#define ANOMALY_05000067 (__SILICON_REVISION__ < 3) -/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ -#define ANOMALY_05000070 (__SILICON_REVISION__ < 2) -/* Writing FIO_DIR can corrupt a programmable flag's data */ -#define ANOMALY_05000079 (__SILICON_REVISION__ < 2) -/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ -#define ANOMALY_05000086 (__SILICON_REVISION__ < 2) -/* Internal Clocking Modes on SPORT0 not supported */ -#define ANOMALY_05000088 (__SILICON_REVISION__ < 2) -/* Internal voltage regulator does not wake up from an RTC wakeup */ -#define ANOMALY_05000092 (__SILICON_REVISION__ < 2) -/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ -#define ANOMALY_05000093 (__SILICON_REVISION__ < 2) -/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ -#define ANOMALY_05000095 (__SILICON_REVISION__ < 2) -/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ -#define ANOMALY_05000096 (__SILICON_REVISION__ < 2) -/* Performance Monitor 0 and 1 are swapped when monitoring memory events */ -#define ANOMALY_05000097 (__SILICON_REVISION__ < 2) -/* 32-bit SPORT DMA will be word reversed */ -#define ANOMALY_05000098 (__SILICON_REVISION__ < 2) -/* Incorrect status in the UART_IIR register */ -#define ANOMALY_05000100 (__SILICON_REVISION__ < 2) -/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ -#define ANOMALY_05000101 (__SILICON_REVISION__ < 2) -/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ -#define ANOMALY_05000102 (__SILICON_REVISION__ < 2) -/* Incorrect Value Written to the Cycle Counters */ -#define ANOMALY_05000103 (__SILICON_REVISION__ < 2) -/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ -#define ANOMALY_05000104 (__SILICON_REVISION__ < 2) -/* Programmable Flag (PF3) functionality not supported in all PPI modes */ -#define ANOMALY_05000106 (__SILICON_REVISION__ < 2) -/* Data store can be lost when targeting a cache line fill */ -#define ANOMALY_05000107 (__SILICON_REVISION__ < 2) -/* Reserved Bits in SYSCFG Register Not Set at Power-On */ -#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) -/* Infinite Core Stall */ -#define ANOMALY_05000114 (__SILICON_REVISION__ < 2) -/* PPI_FSx may glitch when generated by the on chip Timers. */ -#define ANOMALY_05000115 (__SILICON_REVISION__ < 2) -/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ -#define ANOMALY_05000117 (__SILICON_REVISION__ < 2) -/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ -#define ANOMALY_05000118 (__SILICON_REVISION__ < 2) -/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ -#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous Exception when Enabling Cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* SPI clock polarity and phase bits incorrect during booting */ -#define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> Is Not Set on Reset */ -#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) -/* SPI boot will not complete if there is a zero fill block in the loader file */ -#define ANOMALY_05000138 (__SILICON_REVISION__ == 2) -/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ -#define ANOMALY_05000139 (__SILICON_REVISION__ < 2) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000143 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ -#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) -/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ -#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ -#define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ -#define ANOMALY_05000169 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) -/* Cache Fill Buffer Data lost */ -#define ANOMALY_05000174 (__SILICON_REVISION__ < 3) -/* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ -#define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI Resets the PPI Configuration Registers */ -#define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000185 (__SILICON_REVISION__ < 3) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ -#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) -/* Internal Voltage Regulator may not start up */ -#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000120 (0) -#define ANOMALY_05000149 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000182 (0) -#define ANOMALY_05000220 (0) -#define ANOMALY_05000248 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000364 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000383 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000389 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000440 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000456 (0) -#define ANOMALY_05000450 (0) -#define ANOMALY_05000465 (0) -#define ANOMALY_05000467 (0) -#define ANOMALY_05000474 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_05000485 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h deleted file mode 100644 index e3e05f8f7af9..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/bf533.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF533_H__ -#define __MACH_BF533_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/* IAR0 BIT FIELDS*/ -#define RTC_ERROR_BIT 0x0FFFFFFF -#define UART_ERROR_BIT 0xF0FFFFFF -#define SPORT1_ERROR_BIT 0xFF0FFFFF -#define SPI_ERROR_BIT 0xFFF0FFFF -#define SPORT0_ERROR_BIT 0xFFFF0FFF -#define PPI_ERROR_BIT 0xFFFFF0FF -#define DMA_ERROR_BIT 0xFFFFFF0F -#define PLLWAKE_ERROR_BIT 0xFFFFFFFF - -/* IAR1 BIT FIELDS*/ -#define DMA7_UARTTX_BIT 0x0FFFFFFF -#define DMA6_UARTRX_BIT 0xF0FFFFFF -#define DMA5_SPI_BIT 0xFF0FFFFF -#define DMA4_SPORT1TX_BIT 0xFFF0FFFF -#define DMA3_SPORT1RX_BIT 0xFFFF0FFF -#define DMA2_SPORT0TX_BIT 0xFFFFF0FF -#define DMA1_SPORT0RX_BIT 0xFFFFFF0F -#define DMA0_PPI_BIT 0xFFFFFFFF - -/* IAR2 BIT FIELDS*/ -#define WDTIMER_BIT 0x0FFFFFFF -#define MEMDMA1_BIT 0xF0FFFFFF -#define MEMDMA0_BIT 0xFF0FFFFF -#define PFB_BIT 0xFFF0FFFF -#define PFA_BIT 0xFFFF0FFF -#define TIMER2_BIT 0xFFFFF0FF -#define TIMER1_BIT 0xFFFFFF0F -#define TIMER0_BIT 0xFFFFFFFF - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) - -#ifdef CONFIG_BF533 -#define CPU "BF533" -#define CPUID 0x27a5 -#endif -#ifdef CONFIG_BF532 -#define CPU "BF532" -#define CPUID 0x27a5 -#endif -#ifdef CONFIG_BF531 -#define CPU "BF531" -#define CPUID 0x27a5 -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF533_H__ */ diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h deleted file mode 100644 index 08072c86d5dc..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 1 - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h deleted file mode 100644 index e366207fbf12..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#define BF533_FAMILY - -#include "bf533.h" -#include "anomaly.h" - -#include -#include "defBF532.h" - -#ifndef __ASSEMBLY__ -# include -# include "cdefBF532.h" -#endif - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h deleted file mode 100644 index fd0cbe4df21a..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ /dev/null @@ -1,682 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _CDEF_BF532_H -#define _CDEF_BF532_H - -/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) - -/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST,val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) -#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) -#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) -#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) -#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val) -#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) -#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val) - -/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val) - -/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val) -#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) -#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) - -/* DMA Traffic controls */ -#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) -#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) -#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) -#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) - -/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ -#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) -#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) -#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) -#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val) -#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) -#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val) -#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) -#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val) -#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) -#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val) -#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) -#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val) -#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) -#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val) -#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) -#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val) -#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) -#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val) -#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) -#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val) -#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) -#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val) -#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) -#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val) -#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) -#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) - -#if ANOMALY_05000311 -/* Keep at the CPP expansion to avoid circular header dependency loops */ -#define BFIN_WRITE_FIO_FLAG(name, val) \ - do { \ - unsigned long __flags; \ - __flags = hard_local_irq_save(); \ - bfin_write16(FIO_FLAG_##name, val); \ - bfin_read_CHIPID(); \ - hard_local_irq_restore(__flags); \ - } while (0) -#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val) -#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val) -#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val) -#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val) - -#define BFIN_READ_FIO_FLAG(name) \ - ({ \ - unsigned long __flags; \ - u16 __ret; \ - __flags = hard_local_irq_save(); \ - __ret = bfin_read16(FIO_FLAG_##name); \ - bfin_read_CHIPID(); \ - hard_local_irq_restore(__flags); \ - __ret; \ - }) -#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D) -#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C) -#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S) -#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T) - -#else -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#endif - -/* DMA Controller */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val) - -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val) - -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val) - -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val) - -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val) - -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val) - -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val) - -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) - -/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) - -/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val) - -/* UART Controller */ -#define bfin_read_UART_THR() bfin_read16(UART_THR) -#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) -#define bfin_read_UART_RBR() bfin_read16(UART_RBR) -#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) -#define bfin_read_UART_DLL() bfin_read16(UART_DLL) -#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) -#define bfin_read_UART_IER() bfin_read16(UART_IER) -#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) -#define bfin_read_UART_DLH() bfin_read16(UART_DLH) -#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) -#define bfin_read_UART_IIR() bfin_read16(UART_IIR) -#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) -#define bfin_read_UART_LCR() bfin_read16(UART_LCR) -#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) -#define bfin_read_UART_MCR() bfin_read16(UART_MCR) -#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) -#define bfin_read_UART_LSR() bfin_read16(UART_LSR) -#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) -/* -#define UART_MSR -*/ -#define bfin_read_UART_SCR() bfin_read16(UART_SCR) -#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) -#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) -#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) - -/* SPI Controller */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) - -/* TIMER 0, 1, 2 Registers */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) - -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) - -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) - -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val) -#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val) - -/* SPORT0 Controller */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) - -/* SPORT1 Controller */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) - -/* Parallel Peripheral Interface (PPI) */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val) -#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) - -#endif /* _CDEF_BF532_H */ diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h deleted file mode 100644 index d438150b1025..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ /dev/null @@ -1,831 +0,0 @@ -/* - * System & MMR bit and Address definitions for ADSP-BF532 - * - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF532_H -#define _DEF_BF532_H - -/*********************************************************************************** */ -/* System MMR Register Map */ -/*********************************************************************************** */ -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ - -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID Register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration registe */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ - -/* - * Because include/linux/serial_reg.h have defined UART_*, - * So we define blackfin uart regs to BFIN_UART_*. - */ -#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ -#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ -#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ -#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ -#if 0 -#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ -#endif -#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ - -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ - -#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ -#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ -#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ -#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ -#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ -#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ -#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ -#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ -#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ -#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ -#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ -#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ -#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ -#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ -#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ -#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ -#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ - -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Traffic controls */ -#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ - -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ - -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ - -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ - -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ - -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ - -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ - -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ - -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ - -#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ - -#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ - -#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ - -/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ - -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - -/*********************************************************************************** */ -/* System MMR Register Bits */ -/******************************************************************************* */ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SWRST Mask */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ - - /* SIC_IAR0 Masks */ - -#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Masks */ - -#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Masks */ -#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ - -/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 /* PPI Port Enable */ -#define PORT_DIR 0x00000002 /* PPI Port Direction */ -#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ -#define PORT_CFG 0x00000030 /* PPI Port Configuration */ -#define FLD_SEL 0x00000040 /* PPI Active Field Select */ -#define PACK_EN 0x00000080 /* PPI Packing Mode */ -#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x00003800 /* PPI Data Length */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#define POL 0x0000C000 /* PPI Signal Polarities */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 /* Field Indicator */ -#define FT_ERR 0x00000800 /* Frame Track Error */ -#define OVR 0x00001000 /* FIFO Overflow Error */ -#define UNDR 0x00002000 /* FIFO Underrun Error */ -#define ERR_DET 0x00004000 /* Error Detected Indicator */ -#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ - -/* ********** DMA CONTROLLER MASKS *********************8 */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ - -#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ -#define PMAP 0x00007000 /* DMA Peripheral Map Field */ - -#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ -#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ -#define PMAP_SPI 0x5000 /* PMAP SPI DMA */ -#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */ -#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */ - -/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ - -/* PWM Timer bit definitions */ - -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x0001 -#define TIMIL1 0x0002 -#define TIMIL2 0x0004 -#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ -#define TRUN0 0x1000 -#define TRUN1 0x2000 -#define TRUN2 0x4000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TOVF_ERR0_P 0x04 -#define TOVF_ERR1_P 0x05 -#define TOVF_ERR2_P 0x06 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR0_P TOVF_ERR0_P -#define TOVL_ERR1_P TOVF_ERR1_P -#define TOVL_ERR2_P TOVF_ERR2_P - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ - -/* AMGCTL Masks */ -#define AMCKEN 0x00000001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x00000000 /* All Banks Disabled */ -#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ - -/* AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ - -/* AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* ********************** SDRAM CONTROLLER MASKS *************************** */ - -/* SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /*Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x00000001 /* Enable SDRAM external bank */ -#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - - -#endif /* _DEF_BF532_H */ diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h deleted file mode 100644 index fb34934c5ba8..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/dma.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define MAX_DMA_CHANNELS 12 - -#define CH_PPI 0 -#define CH_SPORT0_RX 1 -#define CH_SPORT0_TX 2 -#define CH_SPORT1_RX 3 -#define CH_SPORT1_TX 4 -#define CH_SPI 5 -#define CH_UART0_RX 6 -#define CH_UART0_TX 7 -#define CH_MEM_STREAM0_DEST 8 /* TX */ -#define CH_MEM_STREAM0_SRC 9 /* RX */ -#define CH_MEM_STREAM1_DEST 10 /* TX */ -#define CH_MEM_STREAM1_SRC 11 /* RX */ - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h deleted file mode 100644 index cce4f8fb3785..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/gpio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 16 - -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 - -#define PORT_F GPIO_PF0 - -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h deleted file mode 100644 index 709733754142..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/irq.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BF533_IRQ_H_ -#define _BF533_IRQ_H_ - -#include - -#define NR_PERI_INTS 24 - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */ -#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */ -#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */ -#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */ -#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ -#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */ -#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */ -#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */ -#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */ -#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */ -#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */ -#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */ -#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */ -#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */ -#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */ -#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */ -#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */ -#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */ -#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */ -#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */ -#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */ - -#define SYS_IRQS 31 - -#define IRQ_PF0 33 -#define IRQ_PF1 34 -#define IRQ_PF2 35 -#define IRQ_PF3 36 -#define IRQ_PF4 37 -#define IRQ_PF5 38 -#define IRQ_PF6 39 -#define IRQ_PF7 40 -#define IRQ_PF8 41 -#define IRQ_PF9 42 -#define IRQ_PF10 43 -#define IRQ_PF11 44 -#define IRQ_PF12 45 -#define IRQ_PF13 46 -#define IRQ_PF14 47 -#define IRQ_PF15 48 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define NR_MACH_IRQS (IRQ_PF15 + 1) - -/* IAR0 BIT FIELDS */ -#define RTC_ERROR_POS 28 -#define UART_ERROR_POS 24 -#define SPORT1_ERROR_POS 20 -#define SPI_ERROR_POS 16 -#define SPORT0_ERROR_POS 12 -#define PPI_ERROR_POS 8 -#define DMA_ERROR_POS 4 -#define PLLWAKE_ERROR_POS 0 - -/* IAR1 BIT FIELDS */ -#define DMA7_UARTTX_POS 28 -#define DMA6_UARTRX_POS 24 -#define DMA5_SPI_POS 20 -#define DMA4_SPORT1TX_POS 16 -#define DMA3_SPORT1RX_POS 12 -#define DMA2_SPORT0TX_POS 8 -#define DMA1_SPORT0RX_POS 4 -#define DMA0_PPI_POS 0 - -/* IAR2 BIT FIELDS */ -#define WDTIMER_POS 28 -#define MEMDMA1_POS 24 -#define MEMDMA0_POS 20 -#define PFB_POS 16 -#define PFA_POS 12 -#define TIMER2_POS 8 -#define TIMER1_POS 4 -#define TIMER0_POS 0 - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h deleted file mode 100644 index 197af1a398ac..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/mem_map.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * BF533 memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x400 - -/* Level 1 Memory */ - -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#else -#define BFIN_ICACHESIZE (0*1024) -#endif - -/* Memory Map for ADSP-BF533 processors */ - -#ifdef CONFIG_BF533 -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#ifdef CONFIG_BFIN_ICACHE -#define L1_CODE_LENGTH (0x14000 - 0x4000) -#else -#define L1_CODE_LENGTH 0x14000 -#endif - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ -#endif - -/* Memory Map for ADSP-BF532 processors */ - -#ifdef CONFIG_BF532 -#define L1_CODE_START 0xFFA08000 -#define L1_DATA_A_START 0xFF804000 -#define L1_DATA_B_START 0xFF904000 - -#ifdef CONFIG_BFIN_ICACHE -#define L1_CODE_LENGTH (0xC000 - 0x4000) -#else -#define L1_CODE_LENGTH 0xC000 -#endif - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define L1_DATA_B_LENGTH 0x4000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 - -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define L1_DATA_B_LENGTH (0x4000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x4000 -#define L1_DATA_B_LENGTH 0x4000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ -#endif - -/* Memory Map for ADSP-BF531 processors */ - -#ifdef CONFIG_BF531 -#define L1_CODE_START 0xFFA08000 -#define L1_DATA_A_START 0xFF804000 -#define L1_DATA_B_START 0xFF904000 -#define L1_CODE_LENGTH 0x4000 -#define L1_DATA_B_LENGTH 0x0000 - - -#ifdef CONFIG_BFIN_DCACHE -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x4000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif - -#endif - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h deleted file mode 100644 index 94cca674d835..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h deleted file mode 100644 index 96f5d9129f20..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/portmux.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define MAX_RESOURCES MAX_BLACKFIN_GPIOS - -#define P_PPI0_CLK (P_DONTCARE) -#define P_PPI0_FS1 (P_DONTCARE) -#define P_PPI0_FS2 (P_DONTCARE) -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) -#define P_PPI0_D0 (P_DONTCARE) -#define P_PPI0_D1 (P_DONTCARE) -#define P_PPI0_D2 (P_DONTCARE) -#define P_PPI0_D3 (P_DONTCARE) -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) - -#define P_SPORT1_TSCLK (P_DONTCARE) -#define P_SPORT1_RSCLK (P_DONTCARE) -#define P_SPORT0_TSCLK (P_DONTCARE) -#define P_SPORT0_RSCLK (P_DONTCARE) -#define P_UART0_RX (P_DONTCARE) -#define P_UART0_TX (P_DONTCARE) -#define P_SPORT1_DRSEC (P_DONTCARE) -#define P_SPORT1_RFS (P_DONTCARE) -#define P_SPORT1_DTPRI (P_DONTCARE) -#define P_SPORT1_DTSEC (P_DONTCARE) -#define P_SPORT1_TFS (P_DONTCARE) -#define P_SPORT1_DRPRI (P_DONTCARE) -#define P_SPORT0_DRSEC (P_DONTCARE) -#define P_SPORT0_RFS (P_DONTCARE) -#define P_SPORT0_DTPRI (P_DONTCARE) -#define P_SPORT0_DTSEC (P_DONTCARE) -#define P_SPORT0_TFS (P_DONTCARE) -#define P_SPORT0_DRPRI (P_DONTCARE) - -#define P_SPI0_MOSI (P_DONTCARE) -#define P_SPI0_MISO (P_DONTCARE) -#define P_SPI0_SCK (P_DONTCARE) -#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 - -#define P_TMR2 (P_DONTCARE) -#define P_TMR1 (P_DONTCARE) -#define P_TMR0 (P_DONTCARE) -#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c deleted file mode 100644 index 8f714cf8135b..000000000000 --- a/arch/blackfin/mach-bf533/ints-priority.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) | - ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) | - ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) | - ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) | - ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) | - ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) | - ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) | - ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS)); - - bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) | - ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) | - ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) | - ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) | - ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) | - ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) | - ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) | - ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS)); - - bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) | - ((CONFIG_TIMER1 - 7) << TIMER1_POS) | - ((CONFIG_TIMER2 - 7) << TIMER2_POS) | - ((CONFIG_PFA - 7) << PFA_POS) | - ((CONFIG_PFB - 7) << PFB_POS) | - ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) | - ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) | - ((CONFIG_WDTIMER - 7) << WDTIMER_POS)); - - SSYNC(); -} diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig deleted file mode 100644 index 1d69b043afd4..000000000000 --- a/arch/blackfin/mach-bf537/Kconfig +++ /dev/null @@ -1,118 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if (BF537 || BF534 || BF536) - -source "arch/blackfin/mach-bf537/boards/Kconfig" - -menu "BF537 Specific Configuration" - -comment "Interrupt Priority Assignment" -menu "Priority" - -config IRQ_PLL_WAKEUP - int "IRQ_PLL_WAKEUP" - default 7 -config IRQ_DMA_ERROR - int "IRQ_DMA_ERROR Generic" - default 7 -config IRQ_ERROR - int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1" - default 11 -config IRQ_RTC - int "IRQ_RTC" - default 8 -config IRQ_PPI - int "IRQ_PPI" - default 8 -config IRQ_SPORT0_RX - int "IRQ_SPORT0_RX" - default 9 -config IRQ_SPORT0_TX - int "IRQ_SPORT0_TX" - default 9 -config IRQ_SPORT1_RX - int "IRQ_SPORT1_RX" - default 9 -config IRQ_SPORT1_TX - int "IRQ_SPORT1_TX" - default 9 -config IRQ_TWI - int "IRQ_TWI" - default 10 -config IRQ_SPI - int "IRQ_SPI" - default 10 -config IRQ_UART0_RX - int "IRQ_UART0_RX" - default 10 -config IRQ_UART0_TX - int "IRQ_UART0_TX" - default 10 -config IRQ_UART1_RX - int "IRQ_UART1_RX" - default 10 -config IRQ_UART1_TX - int "IRQ_UART1_TX" - default 10 -config IRQ_CAN_RX - int "IRQ_CAN_RX" - default 11 -config IRQ_CAN_TX - int "IRQ_CAN_TX" - default 11 -config IRQ_MAC_RX - int "IRQ_MAC_RX" - default 11 -config IRQ_MAC_TX - int "IRQ_MAC_TX" - default 11 -config IRQ_TIMER0 - int "IRQ_TIMER0" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config IRQ_TIMER1 - int "IRQ_TIMER1" - default 12 -config IRQ_TIMER2 - int "IRQ_TIMER2" - default 12 -config IRQ_TIMER3 - int "IRQ_TIMER3" - default 12 -config IRQ_TIMER4 - int "IRQ_TIMER4" - default 12 -config IRQ_TIMER5 - int "IRQ_TIMER5" - default 12 -config IRQ_TIMER6 - int "IRQ_TIMER6" - default 12 -config IRQ_TIMER7 - int "IRQ_TIMER7" - default 12 -config IRQ_PROG_INTA - int "IRQ_PROG_INTA" - default 12 -config IRQ_PORTG_INTB - int "IRQ_PORTG_INTB" - default 12 -config IRQ_MEM_DMA0 - int "IRQ_MEM_DMA0" - default 13 -config IRQ_MEM_DMA1 - int "IRQ_MEM_DMA1" - default 13 -config IRQ_WATCH - int "IRQ_WATCH" - default 13 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile deleted file mode 100644 index 56994b675f9c..000000000000 --- a/arch/blackfin/mach-bf537/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf537/Makefile -# - -obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig deleted file mode 100644 index 60b7b29e512e..000000000000 --- a/arch/blackfin/mach-bf537/boards/Kconfig +++ /dev/null @@ -1,49 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN537_STAMP - help - Select your board! - -config BFIN537_STAMP - bool "BF537-STAMP" - help - BF537-STAMP board support. - -config BFIN537_BLUETECHNIX_CM_E - bool "Bluetechnix CM-BF537E" - depends on (BF537) - help - CM-BF537E support for EVAL- and DEV-Board. - -config BFIN537_BLUETECHNIX_CM_U - bool "Bluetechnix CM-BF537U" - depends on (BF537) - help - CM-BF537U support for EVAL- and DEV-Board. - -config BFIN537_BLUETECHNIX_TCM - bool "Bluetechnix TCM-BF537" - depends on (BF537) - help - TCM-BF537 support for EVAL- and DEV-Board. - -config PNAV10 - bool "PNAV board" - depends on (BF537) - help - PNAV board support. - -config CAMSIG_MINOTAUR - bool "Cambridge Signal Processing LTD Minotaur" - depends on (BF537) - help - Board supply package for CSP Minotaur - -config DNP5370 - bool "SSV Dil/NetPC DNP/5370" - depends on (BF537) - help - Board supply package for DNP/5370 DIL64 module - -endchoice diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile deleted file mode 100644 index 47a1acc5f389..000000000000 --- a/arch/blackfin/mach-bf537/boards/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/mach-bf537/boards/Makefile -# - -obj-$(CONFIG_BFIN537_STAMP) += stamp.o -obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_E) += cm_bf537e.o -obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o -obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o -obj-$(CONFIG_PNAV10) += pnav10.o -obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o -obj-$(CONFIG_DNP5370) += dnp5370.o diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c deleted file mode 100644 index 1e1014df5e9e..000000000000 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ /dev/null @@ -1,945 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix CM BF537E"; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = 0x20000 - }, { - .name = "file system(spi)", - .size = 0x700000, - .offset = 0x00100000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) - -/* SPORT SPI controller data */ -static struct bfin5xx_spi_master bfin_sport_spi0_info = { - .num_chipselect = MAX_BLACKFIN_GPIOS, - .enable_dma = 0, /* master don't support DMA */ - .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI, - P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0}, -}; - -static struct resource bfin_sport_spi0_resource[] = { - [0] = { - .start = SPORT0_TCR1, - .end = SPORT0_TCR1 + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_sport_spi0_device = { - .name = "bfin-sport-spi", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource), - .resource = bfin_sport_spi0_resource, - .dev = { - .platform_data = &bfin_sport_spi0_info, /* Passed to driver */ - }, -}; - -static struct bfin5xx_spi_master bfin_sport_spi1_info = { - .num_chipselect = MAX_BLACKFIN_GPIOS, - .enable_dma = 0, /* master don't support DMA */ - .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI, - P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0}, -}; - -static struct resource bfin_sport_spi1_resource[] = { - [0] = { - .start = SPORT1_TCR1, - .end = SPORT1_TCR1 + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_sport_spi1_device = { - .name = "bfin-sport-spi", - .id = 2, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource), - .resource = bfin_sport_spi1_resource, - .dev = { - .platform_data = &bfin_sport_spi1_info, /* Passed to driver */ - }, -}; - -#endif /* sport spi master and devices */ - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) -static struct platform_device hitachi_fb_device = { - .name = "hitachi-tx09", -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .start = 0x20200300, - .end = 0x20200300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF14, - .end = IRQ_PF14, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20308000, - .end = 0x20308000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20308004, - .end = 0x20308004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PG15, - .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PG13, - .end = IRQ_PG13, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) -static struct mtd_partition cm_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data cm_flash_data = { - .width = 2, - .parts = cm_partitions, - .nr_parts = ARRAY_SIZE(cm_partitions), -}; - -static unsigned cm_flash_gpios[] = { GPIO_PF4 }; - -static struct resource cm_flash_resource[] = { - { - .name = "cfi_probe", - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, - }, { - .start = (unsigned long)cm_flash_gpios, - .end = ARRAY_SIZE(cm_flash_gpios), - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device cm_flash_device = { - .name = "gpio-addr-flash", - .id = 0, - .dev = { - .platform_data = &cm_flash_data, - }, - .num_resources = ARRAY_SIZE(cm_flash_resource), - .resource = cm_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART0_CTSRTS - { - /* - * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. - */ - .start = -1, - .end = -1, - .flags = IORESOURCE_IO, - }, - { - /* - * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. - */ - .start = -1, - .end = -1, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { - /* - * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. - */ - .start = -1, - .end = -1, - .flags = IORESOURCE_IO, - }, - { - /* - * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map. - */ - .start = -1, - .end = -1, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \ -|| IS_ENABLED(CONFIG_BFIN_SPORT) -unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 -}; -#endif -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif -#if IS_ENABLED(CONFIG_BFIN_SPORT) -static struct resource bfin_sport0_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_TX, - .end = IRQ_SPORT0_TX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_SPORT0_TX, - .end = CH_SPORT0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_SPORT0_RX, - .end = CH_SPORT0_RX, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sport0_device = { - .name = "bfin_sport_raw", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_resources), - .resource = bfin_sport0_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_MII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_MII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) -#define PATA_INT IRQ_PF14 - -static struct pata_platform_info bfin_pata_platform_data = { - .ioport_shift = 2, -}; - -static struct resource bfin_pata_resources[] = { - { - .start = 0x2030C000, - .end = 0x2030C01F, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x2030D018, - .end = 0x2030D01B, - .flags = IORESOURCE_MEM, - }, - { - .start = PATA_INT, - .end = PATA_INT, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device bfin_pata_device = { - .name = "pata_platform", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pata_resources), - .resource = bfin_pata_resources, - .dev = { - .platform_data = &bfin_pata_platform_data, - } -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 500000000), - VRPAIR(VLEV_125, 533000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cm_bf537e_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_BFIN_SPORT) - &bfin_sport0_device, -#endif - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) - &hitachi_fb_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) - &bfin_sport_spi0_device, - &bfin_sport_spi1_device, -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - &bfin_pata_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) - &cm_flash_device, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - ret = gpio_request(GPIO_PG14, "net2272"); - if (ret) - return ret; - - /* Reset USB Chip, PG14 */ - gpio_direction_output(GPIO_PG14, 0); - mdelay(2); - gpio_set_value(GPIO_PG14, 1); -#endif - - return 0; -} - -static int __init cm_bf537e_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); -#endif - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - return 0; -} - -arch_initcall(cm_bf537e_init); - -static struct platform_device *cm_bf537e_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cm_bf537e_early_devices, - ARRAY_SIZE(cm_bf537e_early_devices)); -} - -int bfin_get_ether_addr(char *addr) -{ - return 1; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c deleted file mode 100644 index d056db9e5592..000000000000 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ /dev/null @@ -1,802 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix CM BF537U"; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = 0x20000 - }, { - .name = "file system(spi)", - .size = 0x700000, - .offset = 0x00100000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) -static struct platform_device hitachi_fb_device = { - .name = "hitachi-tx09", -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .start = 0x20200300, - .end = 0x20200300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF14, - .end = IRQ_PF14, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20308000, - .end = 0x20308000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20308004, - .end = 0x20308004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PG15, - .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20200000, - .end = 0x20200000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PH14, - .end = IRQ_PH14, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) -static struct mtd_partition cm_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data cm_flash_data = { - .width = 2, - .parts = cm_partitions, - .nr_parts = ARRAY_SIZE(cm_partitions), -}; - -static unsigned cm_flash_gpios[] = { GPIO_PH0 }; - -static struct resource cm_flash_resource[] = { - { - .name = "cfi_probe", - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, - }, { - .start = (unsigned long)cm_flash_gpios, - .end = ARRAY_SIZE(cm_flash_gpios), - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device cm_flash_device = { - .name = "gpio-addr-flash", - .id = 0, - .dev = { - .platform_data = &cm_flash_data, - }, - .num_resources = ARRAY_SIZE(cm_flash_resource), - .resource = cm_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_MII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_MII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) -#define PATA_INT IRQ_PF14 - -static struct pata_platform_info bfin_pata_platform_data = { - .ioport_shift = 2, -}; - -static struct resource bfin_pata_resources[] = { - { - .start = 0x2030C000, - .end = 0x2030C01F, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x2030D018, - .end = 0x2030D01B, - .flags = IORESOURCE_MEM, - }, - { - .start = PATA_INT, - .end = PATA_INT, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device bfin_pata_device = { - .name = "pata_platform", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pata_resources), - .resource = bfin_pata_resources, - .dev = { - .platform_data = &bfin_pata_platform_data, - } -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 500000000), - VRPAIR(VLEV_125, 533000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cm_bf537u_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) - &hitachi_fb_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - &bfin_pata_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) - &cm_flash_device, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - ret = gpio_request(GPIO_PH15, driver_name); - if (ret) - return ret; - - ret = gpio_request(GPIO_PH13, "net2272"); - if (ret) { - gpio_free(GPIO_PH15); - return ret; - } - - /* Set PH15 Low make /AMS2 work properly */ - gpio_direction_output(GPIO_PH15, 0); - - /* enable CLKBUF output */ - bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); - - /* Reset the USB chip */ - gpio_direction_output(GPIO_PH13, 0); - mdelay(2); - gpio_set_value(GPIO_PH13, 1); -#endif - - return 0; -} - -static int __init cm_bf537u_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); -#endif - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - return 0; -} - -arch_initcall(cm_bf537u_init); - -static struct platform_device *cm_bf537u_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cm_bf537u_early_devices, - ARRAY_SIZE(cm_bf537u_early_devices)); -} - -int bfin_get_ether_addr(char *addr) -{ - return 1; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c deleted file mode 100644 index c4a8ffb15417..000000000000 --- a/arch/blackfin/mach-bf537/boards/dnp5370.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * This is the configuration for SSV Dil/NetPC DNP/5370 board. - * - * DIL module: http://www.dilnetpc.com/dnp0086.htm - * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm - * - * Copyright 2010 3ality Digital Systems - * Copyright 2005 National ICT Australia (NICTA) - * Copyright 2004-2006 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "DNP/5370"; -#define FLASH_MAC 0x202f0000 -#define CONFIG_MTD_PHYSMAP_LEN 0x300000 - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_RMII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = PHY_POLL, /* IRQ_MAC_PHYINT */ - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_RMII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition asmb_flash_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x30000, - .offset = 0, - }, { - .name = "linux kernel and rootfs(nor)", - .size = 0x300000 - 0x30000 - 0x10000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "MAC address(nor)", - .size = 0x10000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE, - } -}; - -static struct physmap_flash_data asmb_flash_data = { - .width = 1, - .parts = asmb_flash_partitions, - .nr_parts = ARRAY_SIZE(asmb_flash_partitions), -}; - -static struct resource asmb_flash_resource = { - .start = 0x20000000, - .end = 0x202fffff, - .flags = IORESOURCE_MEM, -}; - -/* 4 MB NOR flash attached to async memory banks 0-2, - * therefore only 3 MB visible. - */ -static struct platform_device asmb_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &asmb_flash_data, - }, - .num_resources = 1, - .resource = &asmb_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - -#if IS_ENABLED(CONFIG_MMC_SPI) - -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, /* use no dma transfer with this chip*/ -}; - -#endif - -#if IS_ENABLED(CONFIG_MTD_DATAFLASH) -/* This mapping is for at45db642 it has 1056 page size, - * partition size and offset should be page aligned - */ -static struct mtd_partition bfin_spi_dataflash_partitions[] = { - { - .name = "JFFS2 dataflash(nor)", -#ifdef CONFIG_MTD_PAGESIZE_1024 - .offset = 0x40000, - .size = 0x7C0000, -#else - .offset = 0x0, - .size = 0x840000, -#endif - } -}; - -static struct flash_platform_data bfin_spi_dataflash_data = { - .name = "mtd_dataflash", - .parts = bfin_spi_dataflash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), - .type = "mtd_dataflash", -}; - -static struct bfin5xx_spi_chip spi_dataflash_chip_info = { - .enable_dma = 0, /* use no dma transfer with this chip*/ -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -/* SD/MMC card reader at SPI bus */ -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 1, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -/* 8 Megabyte Atmel NOR flash chip at SPI bus */ -#if IS_ENABLED(CONFIG_MTD_DATAFLASH) - { - .modalias = "mtd_dataflash", - .max_speed_hz = 16700000, - .bus_num = 0, - .chip_select = 2, - .platform_data = &bfin_spi_dataflash_data, - .controller_data = &spi_dataflash_chip_info, - .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */ - }, -#endif -}; - -/* SPI controller data */ -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct bfin5xx_spi_master spi_bfin_master_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device spi_bfin_master_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &spi_bfin_master_info, /* Passed to driver */ - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif - -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE + 0xff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -static struct platform_device *dnp5370_devices[] __initdata = { - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &asmb_flash_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &spi_bfin_master_device, -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -}; - -static int __init dnp5370_init(void) -{ - printk(KERN_INFO "DNP/5370: registering device resources\n"); - platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices)); - printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n", - ARRAY_SIZE(bfin_spi_board_info)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC); - return 0; -} -arch_initcall(dnp5370_init); - -/* - * Currently the MAC address is saved in Flash by U-Boot - */ -int bfin_get_ether_addr(char *addr) -{ - *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); - *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); - return 0; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c deleted file mode 100644 index dd7bda07bf90..000000000000 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Cambridge Signal Processing - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "CamSig Minotaur BF537"; - -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) -static struct resource bfin_pcmcia_cf_resources[] = { - { - .start = 0x20310000, /* IO PORT */ - .end = 0x20312000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20311000, /* Attribute Memory */ - .end = 0x20311FFF, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, { - .start = IRQ_PF6, /* Card Detect PF6 */ - .end = IRQ_PF6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pcmcia_cf_device = { - .name = "bfin_cf_pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), - .resource = bfin_pcmcia_cf_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_MII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_MII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) - -/* Partition sizes */ -#define FLASH_SIZE 0x00400000 -#define PSIZE_UBOOT 0x00030000 -#define PSIZE_INITRAMFS 0x00240000 - -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = PSIZE_UBOOT, - .offset = 0x000000, - .mask_flags = MTD_CAP_ROM - }, { - .name = "initramfs(spi)", - .size = PSIZE_INITRAMFS, - .offset = PSIZE_UBOOT - }, { - .name = "opt(spi)", - .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS), - .offset = PSIZE_UBOOT + PSIZE_INITRAMFS, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -static struct platform_device *minotaur_devices[] __initdata = { -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) - &bfin_pcmcia_cf_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -}; - -static int __init minotaur_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, - ARRAY_SIZE(bfin_spi_board_info)); -#endif - - return 0; -} - -arch_initcall(minotaur_init); - -static struct platform_device *minotaur_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(minotaur_early_devices, - ARRAY_SIZE(minotaur_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c deleted file mode 100644 index 06a50ddb54c0..000000000000 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ /dev/null @@ -1,538 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI PNAV-1.0"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) -static struct resource bfin_pcmcia_cf_resources[] = { - { - .start = 0x20310000, /* IO PORT */ - .end = 0x20312000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20311000, /* Attribute Memory */ - .end = 0x20311FFF, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, { - .start = 6, /* Card Detect PF6 */ - .end = 6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pcmcia_cf_device = { - .name = "bfin_cf_pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), - .resource = bfin_pcmcia_cf_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_RMII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_RMII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = 0x20000 - }, { - .name = "file system(spi)", - .size = 0x700000, - .offset = 0x00100000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -{ - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PF2, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, -}, -#endif - -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_FB_BF537_LQ035) -static struct platform_device bfin_fb_device = { - .name = "bf537-lq035", -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -static struct platform_device *stamp_devices[] __initdata = { -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) - &bfin_pcmcia_cf_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_FB_BF537_LQ035) - &bfin_fb_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif -}; - -static int __init pnav_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, - ARRAY_SIZE(bfin_spi_board_info)); -#endif - return 0; -} - -arch_initcall(pnav_init); - -static struct platform_device *stamp_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(stamp_early_devices, - ARRAY_SIZE(stamp_early_devices)); -} - -int bfin_get_ether_addr(char *addr) -{ - return 1; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c deleted file mode 100644 index 400e6693643e..000000000000 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ /dev/null @@ -1,3019 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE -#include -#endif -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF537-STAMP"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x203C0000, - .end = 0x203C0000 + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"}, - {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) -static struct resource bfin_pcmcia_cf_resources[] = { - { - .start = 0x20310000, /* IO PORT */ - .end = 0x20312000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20311000, /* Attribute Memory */ - .end = 0x20311FFF, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, { - .start = 6, /* Card Detect PF6 */ - .end = 6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pcmcia_cf_device = { - .name = "bfin_cf_pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), - .resource = bfin_pcmcia_cf_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_DM9000) -static struct resource dm9000_resources[] = { - [0] = { - .start = 0x203FB800, - .end = 0x203FB800 + 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x203FB804, - .end = 0x203FB804 + 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), - }, -}; - -static struct platform_device dm9000_device = { - .name = "dm9000", - .id = -1, - .num_resources = ARRAY_SIZE(dm9000_resources), - .resource = dm9000_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_SL811_HCD) -static struct resource sl811_hcd_resources[] = { - { - .start = 0x20340000, - .end = 0x20340000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20340004, - .end = 0x20340004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) -void sl811_port_power(struct device *dev, int is_on) -{ - gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); - gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); -} -#endif - -static struct sl811_platform_data sl811_priv = { - .potpg = 10, - .power = 250, /* == 500mA */ -#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) - .port_power = &sl811_port_power, -#endif -}; - -static struct platform_device sl811_hcd_device = { - .name = "sl811-hcd", - .id = 0, - .dev = { - .platform_data = &sl811_priv, - }, - .num_resources = ARRAY_SIZE(sl811_hcd_resources), - .resource = sl811_hcd_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20360000, - .end = 0x20360000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20360004, - .end = 0x20360004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF3, - .end = IRQ_PF3, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) -static unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN_RX, - .end = IRQ_CAN_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_TX, - .end = IRQ_CAN_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_ERROR, - .end = IRQ_CAN_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_MII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = PHY_POLL, /* IRQ_MAC_PHYINT */ - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_MII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = 1, - .flags = IORESOURCE_BUS, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) -const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; - -static struct mtd_partition bfin_plat_nand_partitions[] = { - { - .name = "linux kernel(nand)", - .size = 0x400000, - .offset = 0, - }, { - .name = "file system(nand)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -#define BFIN_NAND_PLAT_CLE 2 -#define BFIN_NAND_PLAT_ALE 1 -static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE)); - else - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE)); -} - -#define BFIN_NAND_PLAT_READY GPIO_PF3 -static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(BFIN_NAND_PLAT_READY); -} - -static struct platform_nand_data bfin_plat_nand_data = { - .chip = { - .nr_chips = 1, - .chip_delay = 30, - .part_probe_types = part_probes, - .partitions = bfin_plat_nand_partitions, - .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), - }, - .ctrl = { - .cmd_ctrl = bfin_plat_nand_cmd_ctrl, - .dev_ready = bfin_plat_nand_dev_ready, - }, -}; - -#define MAX(x, y) (x > y ? x : y) -static struct resource bfin_plat_nand_resources = { - .start = 0x20212000, - .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_MEM, -}; - -static struct platform_device bfin_async_nand_device = { - .name = "gen_nand", - .id = -1, - .num_resources = 1, - .resource = &bfin_plat_nand_resources, - .dev = { - .platform_data = &bfin_plat_nand_data, - }, -}; - -static void bfin_plat_nand_init(void) -{ - gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); - gpio_direction_input(BFIN_NAND_PLAT_READY); -} -#else -static void bfin_plat_nand_init(void) {} -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition stamp_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = 0x400000 - 0x40000 - 0x180000 - 0x10000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "MAC Address(nor)", - .size = MTDPART_SIZ_FULL, - .offset = 0x3F0000, - .mask_flags = MTD_WRITEABLE, - } -}; - -static struct physmap_flash_data stamp_flash_data = { - .width = 2, - .parts = stamp_partitions, - .nr_parts = ARRAY_SIZE(stamp_partitions), -#ifdef CONFIG_ROMKERNEL - .probe_type = "map_rom", -#endif -}; - -static struct resource stamp_flash_resource = { - .start = 0x20000000, - .end = 0x203fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device stamp_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &stamp_flash_data, - }, - .num_resources = 1, - .resource = &stamp_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - /* .type = "m25p64", */ -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI) -#include - -static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { - { - .start_stage = 0, - .end_stage = 7, - .max_coord = 128, - }, -}; - -static struct ad714x_button_plat ad7147_spi_button_plat[] = { - { - .keycode = BTN_FORWARD, - .l_mask = 0, - .h_mask = 0x600, - }, - { - .keycode = BTN_LEFT, - .l_mask = 0, - .h_mask = 0x500, - }, - { - .keycode = BTN_MIDDLE, - .l_mask = 0, - .h_mask = 0x800, - }, - { - .keycode = BTN_RIGHT, - .l_mask = 0x100, - .h_mask = 0x400, - }, - { - .keycode = BTN_BACK, - .l_mask = 0x200, - .h_mask = 0x400, - }, -}; -static struct ad714x_platform_data ad7147_spi_platform_data = { - .slider_num = 1, - .button_num = 5, - .slider = ad7147_spi_slider_plat, - .button = ad7147_spi_button_plat, - .stage_cfg_reg = { - {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600}, - {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650}, - {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650}, - {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650}, - {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650}, - {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650}, - {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650}, - {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600}, - {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150}, - {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150}, - {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300}, - {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150}, - }, - .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0}, -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C) -#include -static struct ad714x_button_plat ad7142_i2c_button_plat[] = { - { - .keycode = BTN_1, - .l_mask = 0, - .h_mask = 0x1, - }, - { - .keycode = BTN_2, - .l_mask = 0, - .h_mask = 0x2, - }, - { - .keycode = BTN_3, - .l_mask = 0, - .h_mask = 0x4, - }, - { - .keycode = BTN_4, - .l_mask = 0x0, - .h_mask = 0x8, - }, -}; -static struct ad714x_platform_data ad7142_i2c_platform_data = { - .button_num = 4, - .button = ad7142_i2c_button_plat, - .stage_cfg_reg = { - /* fixme: figure out right setting for all comoponent according - * to hardware feature of EVAL-AD7142EB board */ - {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, - {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, - {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, - {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320}, - }, - .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0}, -}; -#endif - -#if IS_ENABLED(CONFIG_AD2S90) -static struct bfin5xx_spi_chip ad2s90_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_AD2S1200) -static unsigned short ad2s1200_platform_data[] = { - /* used as SAMPLE and RDVEL */ - GPIO_PF5, GPIO_PF6, 0 -}; - -static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_AD2S1210) -static unsigned short ad2s1210_platform_data[] = { - /* use as SAMPLE, A0, A1 */ - GPIO_PF7, GPIO_PF8, GPIO_PF9, -# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT) - /* the RES0 and RES1 pins */ - GPIO_PF4, GPIO_PF5, -# endif - 0, -}; - -static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_SENSORS_AD7314) -static struct bfin5xx_spi_chip ad7314_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_AD7816) -static unsigned short ad7816_platform_data[] = { - GPIO_PF4, /* rdwr_pin */ - GPIO_PF5, /* convert_pin */ - GPIO_PF7, /* busy_pin */ - 0, -}; - -static struct bfin5xx_spi_chip ad7816_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_ADT7310) -static unsigned long adt7310_platform_data[3] = { -/* INT bound temperature alarm event. line 1 */ - IRQ_PG4, IRQF_TRIGGER_LOW, -/* CT bound temperature alarm event irq_flags. line 0 */ - IRQF_TRIGGER_LOW, -}; - -static struct bfin5xx_spi_chip adt7310_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_AD7298) -static unsigned short ad7298_platform_data[] = { - GPIO_PF7, /* busy_pin */ - 0, -}; -#endif - -#if IS_ENABLED(CONFIG_ADT7316_SPI) -static unsigned long adt7316_spi_data[2] = { - IRQF_TRIGGER_LOW, /* interrupt flags */ - GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ -}; - -static struct bfin5xx_spi_chip adt7316_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -#define MMC_SPI_CARD_DETECT_INT IRQ_PF5 - -static int bfin_mmc_spi_init(struct device *dev, - irqreturn_t (*detect_int)(int, void *), void *data) -{ - return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, - IRQF_TRIGGER_FALLING, "mmc-spi-detect", data); -} - -static void bfin_mmc_spi_exit(struct device *dev, void *data) -{ - free_irq(MMC_SPI_CARD_DETECT_INT, data); -} - -static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { - .init = bfin_mmc_spi_init, - .exit = bfin_mmc_spi_exit, - .detect_delay = 100, /* msecs */ -}; - -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, - .pio_interrupt = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -#include -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) -#include -static const struct ad7879_platform_data bfin_ad7879_ts_info = { - .model = 7879, /* Model = AD7879 */ - .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ - .pressure_max = 10000, - .pressure_min = 0, - .first_conversion_delay = 3, /* wait 512us before do a first conversion */ - .acquisition_time = 1, /* 4us acquisition time per sample */ - .median = 2, /* do 8 measurements */ - .averaging = 1, /* take the average of 4 middle samples */ - .pen_down_acc_interval = 255, /* 9.4 ms */ - .gpio_export = 1, /* Export GPIO to gpiolib */ - .gpio_base = -1, /* Dynamic allocation */ -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_ADXL34X) -#include -static const struct adxl34x_platform_data adxl34x_info = { - .x_axis_offset = 0, - .y_axis_offset = 0, - .z_axis_offset = 0, - .tap_threshold = 0x31, - .tap_duration = 0x10, - .tap_latency = 0x60, - .tap_window = 0xF0, - .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, - .act_axis_control = 0xFF, - .activity_threshold = 5, - .inactivity_threshold = 3, - .inactivity_time = 4, - .free_fall_threshold = 0x7, - .free_fall_time = 0x20, - .data_rate = 0x8, - .data_range = ADXL_FULL_RES, - - .ev_type = EV_ABS, - .ev_code_x = ABS_X, /* EV_REL */ - .ev_code_y = ABS_Y, /* EV_REL */ - .ev_code_z = ABS_Z, /* EV_REL */ - - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ - -/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ -/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ - .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, - .fifo_mode = ADXL_FIFO_STREAM, - .orientation_enable = ADXL_EN_ORIENTATION_3D, - .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, - .divisor_length = ADXL_LP_FILTER_DIVISOR_16, - /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ - .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, -}; -#endif - -#if IS_ENABLED(CONFIG_ENC28J60) -static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { - .enable_dma = 1, -}; -#endif - -#if IS_ENABLED(CONFIG_ADF702X) -#include -#define TXREG 0x0160A470 -static const u32 adf7021_regs[] = { - 0x09608FA0, - 0x00575011, - 0x00A7F092, - 0x2B141563, - 0x81F29E94, - 0x00003155, - 0x050A4F66, - 0x00000007, - 0x00000008, - 0x000231E9, - 0x3296354A, - 0x891A2B3B, - 0x00000D9C, - 0x0000000D, - 0x0000000E, - 0x0000000F, -}; - -static struct adf702x_platform_data adf7021_platform_data = { - .regs_base = (void *)SPORT1_TCR1, - .dma_ch_rx = CH_SPORT1_RX, - .dma_ch_tx = CH_SPORT1_TX, - .irq_sport_err = IRQ_SPORT1_ERROR, - .gpio_int_rfs = GPIO_PF8, - .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI, - P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0}, - .adf702x_model = MODEL_ADF7021, - .adf702x_regs = adf7021_regs, - .tx_reg = TXREG, -}; -static inline void adf702x_mac_init(void) -{ - eth_random_addr(adf7021_platform_data.mac_addr); -} -#else -static inline void adf702x_mac_init(void) {} -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846) -#include -static int ads7873_get_pendown_state(void) -{ - return gpio_get_value(GPIO_PF6); -} - -static struct ads7846_platform_data __initdata ad7873_pdata = { - .model = 7873, /* AD7873 */ - .x_max = 0xfff, - .y_max = 0xfff, - .x_plate_ohms = 620, - .debounce_max = 1, - .debounce_rep = 0, - .debounce_tol = (~0), - .get_pendown_state = ads7873_get_pendown_state, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_DATAFLASH) - -static struct mtd_partition bfin_spi_dataflash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_dataflash_data = { - .name = "SPI Dataflash", - .parts = bfin_spi_dataflash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), -}; - -/* DataFlash chip */ -static struct bfin5xx_spi_chip data_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_AD7476) -static struct bfin5xx_spi_chip spi_ad7476_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_MTD_DATAFLASH) - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_dataflash_data, - .controller_data = &data_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - { - .modalias = "ad1836", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = "ad1836", /* only includes chip name for the moment */ - .mode = SPI_MODE_3, - }, -#endif - -#ifdef CONFIG_SND_SOC_AD193X_SPI - { - .modalias = "ad193x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X) - { - .modalias = "adav801", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI) - { - .modalias = "ad714x_captouch", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .irq = IRQ_PF4, - .bus_num = 0, - .chip_select = 5, - .mode = SPI_MODE_3, - .platform_data = &ad7147_spi_platform_data, - }, -#endif - -#if IS_ENABLED(CONFIG_AD2S90) - { - .modalias = "ad2s90", - .bus_num = 0, - .chip_select = 3, /* change it for your board */ - .mode = SPI_MODE_3, - .platform_data = NULL, - .controller_data = &ad2s90_spi_chip_info, - }, -#endif - -#if IS_ENABLED(CONFIG_AD2S1200) - { - .modalias = "ad2s1200", - .bus_num = 0, - .chip_select = 4, /* CS, change it for your board */ - .platform_data = ad2s1200_platform_data, - .controller_data = &ad2s1200_spi_chip_info, - }, -#endif - -#if IS_ENABLED(CONFIG_AD2S1210) - { - .modalias = "ad2s1210", - .max_speed_hz = 8192000, - .bus_num = 0, - .chip_select = 4, /* CS, change it for your board */ - .platform_data = ad2s1210_platform_data, - .controller_data = &ad2s1210_spi_chip_info, - }, -#endif - -#if IS_ENABLED(CONFIG_SENSORS_AD7314) - { - .modalias = "ad7314", - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 4, /* CS, change it for your board */ - .controller_data = &ad7314_spi_chip_info, - .mode = SPI_MODE_1, - }, -#endif - -#if IS_ENABLED(CONFIG_AD7816) - { - .modalias = "ad7818", - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 4, /* CS, change it for your board */ - .platform_data = ad7816_platform_data, - .controller_data = &ad7816_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_ADT7310) - { - .modalias = "adt7310", - .max_speed_hz = 1000000, - .irq = IRQ_PG5, /* CT alarm event. Line 0 */ - .bus_num = 0, - .chip_select = 4, /* CS, change it for your board */ - .platform_data = adt7310_platform_data, - .controller_data = &adt7310_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_AD7298) - { - .modalias = "ad7298", - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 4, /* CS, change it for your board */ - .platform_data = ad7298_platform_data, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_ADT7316_SPI) - { - .modalias = "adt7316", - .max_speed_hz = 1000000, - .irq = IRQ_PG5, /* interrupt line */ - .bus_num = 0, - .chip_select = 4, /* CS, change it for your board */ - .platform_data = adt7316_spi_data, - .controller_data = &adt7316_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = &bfin_mmc_spi_pdata, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PF6, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI) - { - .modalias = "ad7879", - .platform_data = &bfin_ad7879_ts_info, - .irq = IRQ_PF7, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - { - .modalias = "bfin-lq035q1-spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif -#if IS_ENABLED(CONFIG_ENC28J60) - { - .modalias = "enc28j60", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .irq = IRQ_PF6, - .bus_num = 0, - .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ - .controller_data = &enc28j60_spi_chip_info, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI) - { - .modalias = "adxl34x", - .platform_data = &adxl34x_info, - .irq = IRQ_PF6, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_ADF702X) - { - .modalias = "adf702x", - .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ - .platform_data = &adf7021_platform_data, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846) - { - .modalias = "ads7846", - .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .irq = IRQ_PF6, - .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ - .platform_data = &ad7873_pdata, - .mode = SPI_MODE_0, - }, -#endif -#if IS_ENABLED(CONFIG_AD7476) - { - .modalias = "ad7476", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_ad7476_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_ADE7753) - { - .modalias = "ade7753", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_1, - }, -#endif -#if IS_ENABLED(CONFIG_ADE7754) - { - .modalias = "ade7754", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_1, - }, -#endif -#if IS_ENABLED(CONFIG_ADE7758) - { - .modalias = "ade7758", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_1, - }, -#endif -#if IS_ENABLED(CONFIG_ADE7759) - { - .modalias = "ade7759", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_1, - }, -#endif -#if IS_ENABLED(CONFIG_ADE7854_SPI) - { - .modalias = "ade7854", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16060) - { - .modalias = "adis16060_r", - .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_0, - }, - { - .modalias = "adis16060_w", - .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, /* CS for write, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_1, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16130) - { - .modalias = "adis16130", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS for read, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16201) - { - .modalias = "adis16201", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16203) - { - .modalias = "adis16203", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16204) - { - .modalias = "adis16204", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16209) - { - .modalias = "adis16209", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16220) - { - .modalias = "adis16220", - .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16240) - { - .modalias = "adis16240", - .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16260) - { - .modalias = "adis16260", - .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16261) - { - .modalias = "adis16261", - .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16300) - { - .modalias = "adis16300", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16350) - { - .modalias = "adis16364", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - .irq = IRQ_PF4, - }, -#endif -#if IS_ENABLED(CONFIG_ADIS16400) - { - .modalias = "adis16400", - .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, /* CS, change it for your board */ - .platform_data = NULL, /* No spi_driver specific config */ - .mode = SPI_MODE_3, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) - -/* SPORT SPI controller data */ -static struct bfin5xx_spi_master bfin_sport_spi0_info = { - .num_chipselect = MAX_BLACKFIN_GPIOS, - .enable_dma = 0, /* master don't support DMA */ - .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI, - P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0}, -}; - -static struct resource bfin_sport_spi0_resource[] = { - [0] = { - .start = SPORT0_TCR1, - .end = SPORT0_TCR1 + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_sport_spi0_device = { - .name = "bfin-sport-spi", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource), - .resource = bfin_sport_spi0_resource, - .dev = { - .platform_data = &bfin_sport_spi0_info, /* Passed to driver */ - }, -}; - -static struct bfin5xx_spi_master bfin_sport_spi1_info = { - .num_chipselect = MAX_BLACKFIN_GPIOS, - .enable_dma = 0, /* master don't support DMA */ - .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI, - P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0}, -}; - -static struct resource bfin_sport_spi1_resource[] = { - [0] = { - .start = SPORT1_TCR1, - .end = SPORT1_TCR1 + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_sport_spi1_device = { - .name = "bfin-sport-spi", - .id = 2, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource), - .resource = bfin_sport_spi1_resource, - .dev = { - .platform_data = &bfin_sport_spi1_info, /* Passed to driver */ - }, -}; - -#endif /* sport spi master and devices */ - -#if IS_ENABLED(CONFIG_FB_BF537_LQ035) -static struct platform_device bfin_fb_device = { - .name = "bf537_lq035", -}; -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) -#include - -static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { - .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, - .ppi_mode = USE_RGB565_16_BIT_PPI, - .use_bl = 0, /* let something else control the LCD Blacklight */ - .gpio_bl = GPIO_PF7, -}; - -static struct resource bfin_lq035q1_resources[] = { - { - .start = IRQ_PPI_ERROR, - .end = IRQ_PPI_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_lq035q1_device = { - .name = "bfin-lq035q1", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), - .resource = bfin_lq035q1_resources, - .dev = { - .platform_data = &bfin_lq035q1_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) -#include -#include -#include - -static const unsigned short ppi_req[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const struct ppi_info ppi_info = { - .type = PPI_TYPE_PPI, - .dma_ch = CH_PPI, - .irq_err = IRQ_PPI_ERROR, - .base = (void __iomem *)PPI_CONTROL, - .pin_req = ppi_req, -}; - -#if IS_ENABLED(CONFIG_VIDEO_VS6624) -static struct v4l2_input vs6624_inputs[] = { - { - .index = 0, - .name = "Camera", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_UNKNOWN, - }, -}; - -static struct bcap_route vs6624_routes[] = { - { - .input = 0, - .output = 0, - }, -}; - -static const unsigned vs6624_ce_pin = GPIO_PF10; - -static struct bfin_capture_config bfin_capture_data = { - .card_name = "BF537", - .inputs = vs6624_inputs, - .num_inputs = ARRAY_SIZE(vs6624_inputs), - .routes = vs6624_routes, - .i2c_adapter_id = 0, - .board_info = { - .type = "vs6624", - .addr = 0x10, - .platform_data = (void *)&vs6624_ce_pin, - }, - .ppi_info = &ppi_info, - .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020), -}; -#endif - -static struct platform_device bfin_capture_device = { - .name = "bfin_capture", - .dev = { - .platform_data = &bfin_capture_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART0_CTSRTS - { /* CTS pin */ - .start = GPIO_PG7, - .end = GPIO_PG7, - .flags = IORESOURCE_IO, - }, - { /* RTS pin */ - .start = GPIO_PG6, - .end = GPIO_PG6, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588) -static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { - [0] = KEY_GRAVE, - [1] = KEY_1, - [2] = KEY_2, - [3] = KEY_3, - [4] = KEY_4, - [5] = KEY_5, - [6] = KEY_6, - [7] = KEY_7, - [8] = KEY_8, - [9] = KEY_9, - [10] = KEY_0, - [11] = KEY_MINUS, - [12] = KEY_EQUAL, - [13] = KEY_BACKSLASH, - [15] = KEY_KP0, - [16] = KEY_Q, - [17] = KEY_W, - [18] = KEY_E, - [19] = KEY_R, - [20] = KEY_T, - [21] = KEY_Y, - [22] = KEY_U, - [23] = KEY_I, - [24] = KEY_O, - [25] = KEY_P, - [26] = KEY_LEFTBRACE, - [27] = KEY_RIGHTBRACE, - [29] = KEY_KP1, - [30] = KEY_KP2, - [31] = KEY_KP3, - [32] = KEY_A, - [33] = KEY_S, - [34] = KEY_D, - [35] = KEY_F, - [36] = KEY_G, - [37] = KEY_H, - [38] = KEY_J, - [39] = KEY_K, - [40] = KEY_L, - [41] = KEY_SEMICOLON, - [42] = KEY_APOSTROPHE, - [43] = KEY_BACKSLASH, - [45] = KEY_KP4, - [46] = KEY_KP5, - [47] = KEY_KP6, - [48] = KEY_102ND, - [49] = KEY_Z, - [50] = KEY_X, - [51] = KEY_C, - [52] = KEY_V, - [53] = KEY_B, - [54] = KEY_N, - [55] = KEY_M, - [56] = KEY_COMMA, - [57] = KEY_DOT, - [58] = KEY_SLASH, - [60] = KEY_KPDOT, - [61] = KEY_KP7, - [62] = KEY_KP8, - [63] = KEY_KP9, - [64] = KEY_SPACE, - [65] = KEY_BACKSPACE, - [66] = KEY_TAB, - [67] = KEY_KPENTER, - [68] = KEY_ENTER, - [69] = KEY_ESC, - [70] = KEY_DELETE, - [74] = KEY_KPMINUS, - [76] = KEY_UP, - [77] = KEY_DOWN, - [78] = KEY_RIGHT, - [79] = KEY_LEFT, -}; - -static struct adp5588_kpad_platform_data adp5588_kpad_data = { - .rows = 8, - .cols = 10, - .keymap = adp5588_keymap, - .keymapsize = ARRAY_SIZE(adp5588_keymap), - .repeat = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_PMIC_ADP5520) -#include - - /* - * ADP5520/5501 Backlight Data - */ - -static struct adp5520_backlight_platform_data adp5520_backlight_data = { - .fade_in = ADP5520_FADE_T_1200ms, - .fade_out = ADP5520_FADE_T_1200ms, - .fade_led_law = ADP5520_BL_LAW_LINEAR, - .en_ambl_sens = 1, - .abml_filt = ADP5520_BL_AMBL_FILT_640ms, - .l1_daylight_max = ADP5520_BL_CUR_mA(15), - .l1_daylight_dim = ADP5520_BL_CUR_mA(0), - .l2_office_max = ADP5520_BL_CUR_mA(7), - .l2_office_dim = ADP5520_BL_CUR_mA(0), - .l3_dark_max = ADP5520_BL_CUR_mA(3), - .l3_dark_dim = ADP5520_BL_CUR_mA(0), - .l2_trip = ADP5520_L2_COMP_CURR_uA(700), - .l2_hyst = ADP5520_L2_COMP_CURR_uA(50), - .l3_trip = ADP5520_L3_COMP_CURR_uA(80), - .l3_hyst = ADP5520_L3_COMP_CURR_uA(20), -}; - - /* - * ADP5520/5501 LEDs Data - */ - -static struct led_info adp5520_leds[] = { - { - .name = "adp5520-led1", - .default_trigger = "none", - .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms, - }, -#ifdef ADP5520_EN_ALL_LEDS - { - .name = "adp5520-led2", - .default_trigger = "none", - .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1, - }, - { - .name = "adp5520-led3", - .default_trigger = "none", - .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2, - }, -#endif -}; - -static struct adp5520_leds_platform_data adp5520_leds_data = { - .num_leds = ARRAY_SIZE(adp5520_leds), - .leds = adp5520_leds, - .fade_in = ADP5520_FADE_T_600ms, - .fade_out = ADP5520_FADE_T_600ms, - .led_on_time = ADP5520_LED_ONT_600ms, -}; - - /* - * ADP5520 GPIO Data - */ - -static struct adp5520_gpio_platform_data adp5520_gpio_data = { - .gpio_start = 50, - .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, - .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, -}; - - /* - * ADP5520 Keypad Data - */ - -static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = { - [ADP5520_KEY(0, 0)] = KEY_GRAVE, - [ADP5520_KEY(0, 1)] = KEY_1, - [ADP5520_KEY(0, 2)] = KEY_2, - [ADP5520_KEY(0, 3)] = KEY_3, - [ADP5520_KEY(1, 0)] = KEY_4, - [ADP5520_KEY(1, 1)] = KEY_5, - [ADP5520_KEY(1, 2)] = KEY_6, - [ADP5520_KEY(1, 3)] = KEY_7, - [ADP5520_KEY(2, 0)] = KEY_8, - [ADP5520_KEY(2, 1)] = KEY_9, - [ADP5520_KEY(2, 2)] = KEY_0, - [ADP5520_KEY(2, 3)] = KEY_MINUS, - [ADP5520_KEY(3, 0)] = KEY_EQUAL, - [ADP5520_KEY(3, 1)] = KEY_BACKSLASH, - [ADP5520_KEY(3, 2)] = KEY_BACKSPACE, - [ADP5520_KEY(3, 3)] = KEY_ENTER, -}; - -static struct adp5520_keys_platform_data adp5520_keys_data = { - .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0, - .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0, - .keymap = adp5520_keymap, - .keymapsize = ARRAY_SIZE(adp5520_keymap), - .repeat = 0, -}; - - /* - * ADP5520/5501 Multifunction Device Init Data - */ - -static struct adp5520_platform_data adp5520_pdev_data = { - .backlight = &adp5520_backlight_data, - .leds = &adp5520_leds_data, - .gpio = &adp5520_gpio_data, - .keys = &adp5520_keys_data, -}; - -#endif - -#if IS_ENABLED(CONFIG_GPIO_ADP5588) -static struct adp5588_gpio_platform_data adp5588_gpio_data = { - .gpio_start = 50, - .pullup_dis_mask = 0, -}; -#endif - -#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870) -#include -static struct led_info adp8870_leds[] = { - { - .name = "adp8870-led7", - .default_trigger = "none", - .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms, - }, -}; - - -static struct adp8870_backlight_platform_data adp8870_pdata = { - .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 | - ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */ - .pwm_assign = 0, /* 1 = Enables PWM mode */ - - .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */ - .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */ - .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */ - - .en_ambl_sens = 1, /* 1 = enable ambient light sensor */ - .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */ - - .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - - .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ - .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ - .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ - .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ - .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - - .leds = adp8870_leds, - .num_leds = ARRAY_SIZE(adp8870_leds), - .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */ - .led_fade_in = ADP8870_FADE_T_600ms, - .led_fade_out = ADP8870_FADE_T_600ms, - .led_on_time = ADP8870_LED_ONT_200ms, -}; -#endif - -#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860) -#include -static struct led_info adp8860_leds[] = { - { - .name = "adp8860-led7", - .default_trigger = "none", - .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms, - }, -}; - -static struct adp8860_backlight_platform_data adp8860_pdata = { - .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 | - ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6, /* 1 = Backlight 0 = Individual LED */ - - .bl_fade_in = ADP8860_FADE_T_1200ms, /* Backlight Fade-In Timer */ - .bl_fade_out = ADP8860_FADE_T_1200ms, /* Backlight Fade-Out Timer */ - .bl_fade_law = ADP8860_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */ - - .en_ambl_sens = 1, /* 1 = enable ambient light sensor */ - .abml_filt = ADP8860_BL_AMBL_FILT_320ms, /* Light sensor filter time */ - - .l1_daylight_max = ADP8860_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l1_daylight_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_office_max = ADP8860_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_office_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_dark_max = ADP8860_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_dark_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - - .l2_trip = ADP8860_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l2_hyst = ADP8860_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l3_trip = ADP8860_L3_COMP_CURR_uA(43), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - .l3_hyst = ADP8860_L3_COMP_CURR_uA(11), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - - .leds = adp8860_leds, - .num_leds = ARRAY_SIZE(adp8860_leds), - .led_fade_law = ADP8860_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */ - .led_fade_in = ADP8860_FADE_T_600ms, - .led_fade_out = ADP8860_FADE_T_600ms, - .led_on_time = ADP8860_LED_ONT_200ms, -}; -#endif - -#if IS_ENABLED(CONFIG_REGULATOR_AD5398) -static struct regulator_consumer_supply ad5398_consumer = { - .supply = "current", -}; - -static struct regulator_init_data ad5398_regulator_data = { - .constraints = { - .name = "current range", - .max_uA = 120000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &ad5398_consumer, -}; - -#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER) -static struct platform_device ad5398_virt_consumer_device = { - .name = "reg-virt-consumer", - .id = 0, - .dev = { - .platform_data = "current", /* Passed to driver */ - }, -}; -#endif -#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) -static struct regulator_bulk_data ad5398_bulk_data = { - .supply = "current", -}; - -static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = { - .name = "ad5398", - .num_supplies = 1, - .supplies = &ad5398_bulk_data, -}; - -static struct platform_device ad5398_userspace_consumer_device = { - .name = "reg-userspace-consumer", - .id = 0, - .dev = { - .platform_data = &ad5398_userspace_comsumer_data, - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_ADT7410) -/* INT bound temperature alarm event. line 1 */ -static unsigned long adt7410_platform_data[2] = { - IRQ_PG4, IRQF_TRIGGER_LOW, -}; -#endif - -#if IS_ENABLED(CONFIG_ADT7316_I2C) -/* INT bound temperature alarm event. line 1 */ -static unsigned long adt7316_i2c_data[2] = { - IRQF_TRIGGER_LOW, /* interrupt flags */ - GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#ifdef CONFIG_SND_SOC_AD193X_I2C - { - I2C_BOARD_INFO("ad1937", 0x04), - }, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X) - { - I2C_BOARD_INFO("adav803", 0x10), - }, -#endif - -#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C) - { - I2C_BOARD_INFO("ad7142_captouch", 0x2C), - .irq = IRQ_PG5, - .platform_data = (void *)&ad7142_i2c_platform_data, - }, -#endif - -#if IS_ENABLED(CONFIG_AD7150) - { - I2C_BOARD_INFO("ad7150", 0x48), - .irq = IRQ_PG5, /* fixme: use real interrupt number */ - }, -#endif - -#if IS_ENABLED(CONFIG_AD7152) - { - I2C_BOARD_INFO("ad7152", 0x48), - }, -#endif - -#if IS_ENABLED(CONFIG_AD774X) - { - I2C_BOARD_INFO("ad774x", 0x48), - }, -#endif - -#if IS_ENABLED(CONFIG_ADE7854_I2C) - { - I2C_BOARD_INFO("ade7854", 0x38), - }, -#endif - -#if IS_ENABLED(CONFIG_SENSORS_LM75) - { - I2C_BOARD_INFO("adt75", 0x9), - .irq = IRQ_PG5, - }, -#endif - -#if IS_ENABLED(CONFIG_ADT7410) - { - I2C_BOARD_INFO("adt7410", 0x48), - /* CT critical temperature event. line 0 */ - .irq = IRQ_PG5, - .platform_data = (void *)&adt7410_platform_data, - }, -#endif - -#if IS_ENABLED(CONFIG_AD7291) - { - I2C_BOARD_INFO("ad7291", 0x20), - .irq = IRQ_PG5, - }, -#endif - -#if IS_ENABLED(CONFIG_ADT7316_I2C) - { - I2C_BOARD_INFO("adt7316", 0x48), - .irq = IRQ_PG6, - .platform_data = (void *)&adt7316_i2c_data, - }, -#endif - -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = IRQ_PG6, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C) - { - I2C_BOARD_INFO("ad7879", 0x2F), - .irq = IRQ_PG5, - .platform_data = (void *)&bfin_ad7879_ts_info, - }, -#endif -#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588) - { - I2C_BOARD_INFO("adp5588-keys", 0x34), - .irq = IRQ_PG0, - .platform_data = (void *)&adp5588_kpad_data, - }, -#endif -#if IS_ENABLED(CONFIG_PMIC_ADP5520) - { - I2C_BOARD_INFO("pmic-adp5520", 0x32), - .irq = IRQ_PG0, - .platform_data = (void *)&adp5520_pdev_data, - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C) - { - I2C_BOARD_INFO("adxl34x", 0x53), - .irq = IRQ_PG3, - .platform_data = (void *)&adxl34x_info, - }, -#endif -#if IS_ENABLED(CONFIG_GPIO_ADP5588) - { - I2C_BOARD_INFO("adp5588-gpio", 0x34), - .platform_data = (void *)&adp5588_gpio_data, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -#if IS_ENABLED(CONFIG_FB_BF537_LQ035) - { - I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F), - }, -#endif -#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870) - { - I2C_BOARD_INFO("adp8870", 0x2B), - .platform_data = (void *)&adp8870_pdata, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371) - { - I2C_BOARD_INFO("adau1371", 0x1A), - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761) - { - I2C_BOARD_INFO("adau1761", 0x38), - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361) - { - I2C_BOARD_INFO("adau1361", 0x38), - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701) - { - I2C_BOARD_INFO("adau1701", 0x34), - }, -#endif -#if IS_ENABLED(CONFIG_AD525X_DPOT) - { - I2C_BOARD_INFO("ad5258", 0x18), - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) - { - I2C_BOARD_INFO("ssm2602", 0x1b), - }, -#endif -#if IS_ENABLED(CONFIG_REGULATOR_AD5398) - { - I2C_BOARD_INFO("ad5398", 0xC), - .platform_data = (void *)&ad5398_regulator_data, - }, -#endif -#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860) - { - I2C_BOARD_INFO("adp8860", 0x2A), - .platform_data = (void *)&adp8860_pdata, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373) - { - I2C_BOARD_INFO("adau1373", 0x1A), - }, -#endif -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("ad5252", 0x2e), - }, -#endif -}; -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \ -|| IS_ENABLED(CONFIG_BFIN_SPORT) -unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 -}; -#endif -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif -#if IS_ENABLED(CONFIG_BFIN_SPORT) -static struct resource bfin_sport0_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_TX, - .end = IRQ_SPORT0_TX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_SPORT0_TX, - .end = CH_SPORT0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_SPORT0_RX, - .end = CH_SPORT0_RX, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sport0_device = { - .name = "bfin_sport_raw", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_resources), - .resource = bfin_sport0_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#if IS_ENABLED(CONFIG_PATA_PLATFORM) -#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE -/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */ - -#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE -#define PATA_INT IRQ_PF5 -static struct pata_platform_info bfin_pata_platform_data = { - .ioport_shift = 1, -}; - -static struct resource bfin_pata_resources[] = { - { - .start = 0x20314020, - .end = 0x2031403F, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x2031401C, - .end = 0x2031401F, - .flags = IORESOURCE_MEM, - }, - { - .start = PATA_INT, - .end = PATA_INT, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE) -static struct pata_platform_info bfin_pata_platform_data = { - .ioport_shift = 0, -}; -/* CompactFlash Storage Card Memory Mapped Addressing - * /REG = A11 = 1 - */ -static struct resource bfin_pata_resources[] = { - { - .start = 0x20211800, - .end = 0x20211807, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x2021180E, /* Device Ctl */ - .end = 0x2021180E, - .flags = IORESOURCE_MEM, - }, -}; -#endif - -static struct platform_device bfin_pata_device = { - .name = "pata_platform", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pata_resources), - .resource = bfin_pata_resources, - .dev = { - .platform_data = &bfin_pata_platform_data, - } -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 500000000), - VRPAIR(VLEV_125, 533000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \ - IS_ENABLED(CONFIG_SND_BF5XX_AC97) - -#define SPORT_REQ(x) \ - [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \ - P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0} - -static const u16 bfin_snd_pin[][7] = { - SPORT_REQ(0), - SPORT_REQ(1), -}; - -static struct bfin_snd_platform_data bfin_snd_data[] = { - { - .pin_req = &bfin_snd_pin[0][0], - }, - { - .pin_req = &bfin_snd_pin[1][0], - }, -}; - -#define BFIN_SND_RES(x) \ - [x] = { \ - { \ - .start = SPORT##x##_TCR1, \ - .end = SPORT##x##_TCR1, \ - .flags = IORESOURCE_MEM \ - }, \ - { \ - .start = CH_SPORT##x##_RX, \ - .end = CH_SPORT##x##_RX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = CH_SPORT##x##_TX, \ - .end = CH_SPORT##x##_TX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = IRQ_SPORT##x##_ERROR, \ - .end = IRQ_SPORT##x##_ERROR, \ - .flags = IORESOURCE_IRQ, \ - } \ - } - -static struct resource bfin_snd_resources[][4] = { - BFIN_SND_RES(0), - BFIN_SND_RES(1), -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s_pcm = { - .name = "bfin-i2s-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97_pcm = { - .name = "bfin-ac97-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) -static const char * const ad1836_link[] = { - "bfin-i2s.0", - "spi0.4", -}; -static struct platform_device bfin_ad1836_machine = { - .name = "bfin-snd-ad1836", - .id = -1, - .dev = { - .platform_data = (void *)ad1836_link, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) -static const unsigned ad73311_gpio[] = { - GPIO_PF4, -}; - -static struct platform_device bfin_ad73311_machine = { - .name = "bfin-snd-ad73311", - .id = 1, - .dev = { - .platform_data = (void *)ad73311_gpio, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD73311) -static struct platform_device bfin_ad73311_codec_device = { - .name = "ad73311", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) -static struct platform_device bfin_eval_adav801_device = { - .name = "bfin-eval-adav801", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) -static struct platform_device bfin_ac97 = { - .name = "bfin-ac97", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE) -#define REGULATOR_ADP122 "adp122" -#define REGULATOR_ADP122_UV 2500000 - -static struct regulator_consumer_supply adp122_consumers = { - .supply = REGULATOR_ADP122, -}; - -static struct regulator_init_data adp_switch_regulator_data = { - .constraints = { - .name = REGULATOR_ADP122, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .min_uV = REGULATOR_ADP122_UV, - .max_uV = REGULATOR_ADP122_UV, - .min_uA = 0, - .max_uA = 300000, - }, - .num_consumer_supplies = 1, /* only 1 */ - .consumer_supplies = &adp122_consumers, -}; - -static struct fixed_voltage_config adp_switch_pdata = { - .supply_name = REGULATOR_ADP122, - .microvolts = REGULATOR_ADP122_UV, - .gpio = GPIO_PF2, - .enable_high = 1, - .enabled_at_boot = 0, - .init_data = &adp_switch_regulator_data, -}; - -static struct platform_device adp_switch_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &adp_switch_pdata, - }, -}; - -#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) -static struct regulator_bulk_data adp122_bulk_data = { - .supply = REGULATOR_ADP122, -}; - -static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = { - .name = REGULATOR_ADP122, - .num_supplies = 1, - .supplies = &adp122_bulk_data, -}; - -static struct platform_device adp122_userspace_consumer_device = { - .name = "reg-userspace-consumer", - .id = 0, - .dev = { - .platform_data = &adp122_userspace_comsumer_data, - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER) - -static struct resource iio_gpio_trigger_resources[] = { - [0] = { - .start = IRQ_PF5, - .end = IRQ_PF5, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device iio_gpio_trigger = { - .name = "iio_gpio_trigger", - .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources), - .resource = iio_gpio_trigger_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) -static struct platform_device bf5xx_adau1373_device = { - .name = "bfin-eval-adau1373", -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) -static struct platform_device bf5xx_adau1701_device = { - .name = "bfin-eval-adau1701", -}; -#endif - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, -#if IS_ENABLED(CONFIG_BFIN_SPORT) - &bfin_sport0_device, -#endif -#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA) - &bfin_pcmcia_cf_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_SL811_HCD) - &sl811_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) - &bfin_isp1760_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_DM9000) - &dm9000_device, -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) - &bfin_can_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT) - &bfin_sport_spi0_device, - &bfin_sport_spi1_device, -#endif - -#if IS_ENABLED(CONFIG_FB_BF537_LQ035) - &bfin_fb_device, -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - &bfin_lq035q1_device, -#endif - -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) - &bfin_capture_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - &bfin_pata_device, -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) - &bfin_async_nand_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &stamp_flash_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - &bfin_ad1836_machine, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) - &bfin_ad73311_machine, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD73311) - &bfin_ad73311_codec_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) - &bfin_ac97, -#endif - -#if IS_ENABLED(CONFIG_REGULATOR_AD5398) -#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER) - &ad5398_virt_consumer_device, -#endif -#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) - &ad5398_userspace_consumer_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE) - &adp_switch_device, -#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER) - &adp122_userspace_consumer_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER) - &iio_gpio_trigger, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) - &bf5xx_adau1373_device, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) - &bf5xx_adau1701_device, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) - &bfin_eval_adav801_device, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - ret = gpio_request(GPIO_PF6, "net2272"); - if (ret) - return ret; - - /* Reset the USB chip */ - gpio_direction_output(GPIO_PF6, 0); - mdelay(2); - gpio_set_value(GPIO_PF6, 1); -#endif - - return 0; -} - -static int __init stamp_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - bfin_plat_nand_init(); - adf702x_mac_init(); - platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - return 0; -} - -arch_initcall(stamp_init); - - -static struct platform_device *stamp_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(stamp_early_devices, - ARRAY_SIZE(stamp_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround reboot hang when booting from SPI */ - if ((bfin_read_SYSCR() & 0x7) == 0x3) - bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); -} - -/* - * Currently the MAC address is saved in Flash by U-Boot - */ -#define FLASH_MAC 0x203f0000 -int bfin_get_ether_addr(char *addr) -{ - *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); - *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); - return 0; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c deleted file mode 100644 index ed309c9a62b6..000000000000 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ /dev/null @@ -1,792 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix TCM BF537"; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = 0x20000 - }, { - .name = "file system(spi)", - .size = 0x700000, - .offset = 0x00100000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) -static struct platform_device hitachi_fb_device = { - .name = "hitachi-tx09", -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .start = 0x20200300, - .end = 0x20200300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF14, - .end = IRQ_PF14, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20308000, - .end = 0x20308000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20308004, - .end = 0x20308004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PG15, - .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PG13, - .end = IRQ_PG13, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) -static struct mtd_partition cm_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data cm_flash_data = { - .width = 2, - .parts = cm_partitions, - .nr_parts = ARRAY_SIZE(cm_partitions), -}; - -static unsigned cm_flash_gpios[] = { GPIO_PF4, GPIO_PF5 }; - -static struct resource cm_flash_resource[] = { - { - .name = "cfi_probe", - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, - }, { - .start = (unsigned long)cm_flash_gpios, - .end = ARRAY_SIZE(cm_flash_gpios), - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device cm_flash_device = { - .name = "gpio-addr-flash", - .id = 0, - .dev = { - .platform_data = &cm_flash_data, - }, - .num_resources = ARRAY_SIZE(cm_flash_resource), - .resource = cm_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI, - .end = IRQ_TWI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) -#include -static const unsigned short bfin_mac_peripherals[] = P_MII0; - -static struct bfin_phydev_platform_data bfin_phydev_data[] = { - { - .addr = 1, - .irq = IRQ_MAC_PHYINT, - }, -}; - -static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { - .phydev_number = 1, - .phydev_data = bfin_phydev_data, - .phy_mode = PHY_INTERFACE_MODE_MII, - .mac_peripherals = bfin_mac_peripherals, -}; - -static struct platform_device bfin_mii_bus = { - .name = "bfin_mii_bus", - .dev = { - .platform_data = &bfin_mii_bus_data, - } -}; - -static struct platform_device bfin_mac_device = { - .name = "bfin_mac", - .dev = { - .platform_data = &bfin_mii_bus, - } -}; -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) -#define PATA_INT IRQ_PF14 - -static struct pata_platform_info bfin_pata_platform_data = { - .ioport_shift = 2, -}; - -static struct resource bfin_pata_resources[] = { - { - .start = 0x2030C000, - .end = 0x2030C01F, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x2030D018, - .end = 0x2030D01B, - .flags = IORESOURCE_MEM, - }, - { - .start = PATA_INT, - .end = PATA_INT, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device bfin_pata_device = { - .name = "pata_platform", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pata_resources), - .resource = bfin_pata_resources, - .dev = { - .platform_data = &bfin_pata_platform_data, - } -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 500000000), - VRPAIR(VLEV_125, 533000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cm_bf537_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) - &hitachi_fb_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_MAC) - &bfin_mii_bus, - &bfin_mac_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - &bfin_pata_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) - &cm_flash_device, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - ret = gpio_request(GPIO_PG14, "net2272"); - if (ret) - return ret; - - /* Reset USB Chip, PG14 */ - gpio_direction_output(GPIO_PG14, 0); - mdelay(2); - gpio_set_value(GPIO_PG14, 1); -#endif - - return 0; -} - -static int __init tcm_bf537_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); -#endif - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - return 0; -} - -arch_initcall(tcm_bf537_init); - -static struct platform_device *cm_bf537_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cm_bf537_early_devices, - ARRAY_SIZE(cm_bf537_early_devices)); -} - -int bfin_get_ether_addr(char *addr) -{ - return 1; -} -EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c deleted file mode 100644 index 5c62e99c9fac..000000000000 --- a/arch/blackfin/mach-bf537/dma.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - * This file contains the simple DMA Implementation for Blackfin - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) DMA8_NEXT_DESC_PTR, - (struct dma_register *) DMA9_NEXT_DESC_PTR, - (struct dma_register *) DMA10_NEXT_DESC_PTR, - (struct dma_register *) DMA11_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI: - ret_irq = IRQ_PPI; - break; - - case CH_EMAC_RX: - ret_irq = IRQ_MAC_RX; - break; - - case CH_EMAC_TX: - ret_irq = IRQ_MAC_TX; - break; - - case CH_UART1_RX: - ret_irq = IRQ_UART1_RX; - break; - - case CH_UART1_TX: - ret_irq = IRQ_UART1_TX; - break; - - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - - case CH_SPI: - ret_irq = IRQ_SPI; - break; - - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h deleted file mode 100644 index 2bc70c5b9415..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 silicon - sorry */ -#if __SILICON_REVISION__ < 2 -# error will not work on BF537 silicon version 0.0 or 0.1 -#endif - -#if defined(__ADSPBF534__) -# define ANOMALY_BF534 1 -#else -# define ANOMALY_BF534 0 -#endif -#if defined(__ADSPBF536__) -# define ANOMALY_BF536 1 -#else -# define ANOMALY_BF536 0 -#endif -#if defined(__ADSPBF537__) -# define ANOMALY_BF537 1 -#else -# define ANOMALY_BF537 0 -#endif - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ -#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) -/* EMAC TX DMA Error After an Early Frame Abort */ -#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) -/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ -#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) -/* EMAC MDIO Input Latched on Wrong MDC Edge */ -#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) -/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) -/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ -#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) -/* ICPLB_STATUS MMR Register May Be Corrupted */ -#define ANOMALY_05000260 (__SILICON_REVISION__ == 2) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) -/* Stores To Data Cache May Be Lost */ -#define ANOMALY_05000262 (__SILICON_REVISION__ < 3) -/* Hardware Loop Corrupted When Taking an ICPLB Exception */ -#define ANOMALY_05000263 (__SILICON_REVISION__ == 2) -/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ -#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ -#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (__SILICON_REVISION__ < 3) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) -/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ -#define ANOMALY_05000280 (1) -/* False Hardware Error when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) -/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) -/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ -#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) -/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ -#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) -/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) -/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ -#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ -#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) -/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ -#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) -/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ -#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) -/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ -#define ANOMALY_05000322 (1) -/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* UART Gets Disabled after UART Boot */ -#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (1) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ -#define ANOMALY_05000359 (1) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 2) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* Possible Lockup Condition when Modifying PLL from External Memory */ -#define ANOMALY_05000475 (1) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */ -#define ANOMALY_05000480 (__SILICON_REVISION__ < 3) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* PLL May Latch Incorrect Values Coming Out of Reset */ -#define ANOMALY_05000489 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) - -/* - * These anomalies have been "phased" out of analog.com anomaly sheets and are - * here to show running on older silicon just isn't feasible. - */ - -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) -/* Instruction Cache Is Not Functional */ -#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) -/* Buffered CLKIN Output Is Disabled by Default */ -#define ANOMALY_05000247 (__SILICON_REVISION__ < 2) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000099 (0) -#define ANOMALY_05000120 (0) -#define ANOMALY_05000125 (0) -#define ANOMALY_05000149 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000179 (0) -#define ANOMALY_05000182 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000189 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000202 (0) -#define ANOMALY_05000215 (0) -#define ANOMALY_05000219 (0) -#define ANOMALY_05000220 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000231 (0) -#define ANOMALY_05000233 (0) -#define ANOMALY_05000234 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000248 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000364 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000383 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000389 (0) -#define ANOMALY_05000400 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000440 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000456 (0) -#define ANOMALY_05000450 (0) -#define ANOMALY_05000465 (0) -#define ANOMALY_05000467 (0) -#define ANOMALY_05000474 (0) -#define ANOMALY_05000485 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h deleted file mode 100644 index 8b291418ca32..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/bf537.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * System MMR Register and memory map for ADSP-BF537 - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF537_H__ -#define __MACH_BF537_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) - -#ifdef CONFIG_BF537 -#define CPU "BF537" -#define CPUID 0x27c8 -#endif -#ifdef CONFIG_BF536 -#define CPU "BF536" -#define CPUID 0x27c8 -#endif -#ifdef CONFIG_BF534 -#define CPU "BF534" -#define CPUID 0x27c6 -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF537_H__ */ diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h deleted file mode 100644 index 00c603fe8218..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 2 - -#endif diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h deleted file mode 100644 index baa096fc724a..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#define BF537_FAMILY - -#include "bf537.h" -#include "anomaly.h" - -#include -#ifdef CONFIG_BF534 -# include "defBF534.h" -#endif -#if defined(CONFIG_BF537) || defined(CONFIG_BF536) -# include "defBF537.h" -#endif - -#if !defined(__ASSEMBLY__) -# include -# ifdef CONFIG_BF534 -# include "cdefBF534.h" -# endif -# if defined(CONFIG_BF537) || defined(CONFIG_BF536) -# include "cdefBF537.h" -# endif -#endif - -#endif diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h deleted file mode 100644 index 563ede907336..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h +++ /dev/null @@ -1,1736 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _CDEF_BF534_H -#define _CDEF_BF534_H - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST,val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val) -#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) -#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) -#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) -#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val) -#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) -#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val) - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val) - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val) -#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) -#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val) - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) - -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) - -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) - -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val) - -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val) - -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val) - -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val) - -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val) - -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val) -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val) - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val) - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) - -/* DMA Traffic Control Registers */ -#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) -#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) -#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) -#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) - -/* DMA Controller */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val) - -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val) - -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val) - -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val) - -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val) - -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val) - -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val) - -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val) - -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val) -#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val) -#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val) - -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val) -#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val) -#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val) - -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val) -#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val) -#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val) - -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val) -#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val) -#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val) -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val) -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val) -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val) -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val) -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val) -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val) -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val) -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val) -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val) -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val) -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val) -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val) -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val) -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val) -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val) -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val) - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val) -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val) -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val) -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val) -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val) -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val) -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val) -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val) -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val) -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val) -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val) -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val) -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val) -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val) -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val) -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val) -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val) - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val) - -/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ -/* For Mailboxes 0-15 */ -#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) -#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val) -#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) -#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val) -#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) -#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val) -#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) -#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val) -#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) -#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val) -#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) -#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val) -#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) -#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val) -#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) -#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val) -#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) -#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val) -#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) -#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val) -#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) -#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val) -#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) -#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val) -#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) -#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val) - -/* For Mailboxes 16-31 */ -#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) -#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val) -#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) -#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val) -#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) -#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val) -#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) -#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val) -#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) -#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val) -#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) -#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val) -#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) -#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val) -#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) -#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val) -#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) -#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val) -#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) -#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val) -#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) -#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val) -#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) -#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val) -#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) -#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val) - -#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) -#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val) -#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) -#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val) -#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) -#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val) -#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) -#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val) -#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) -#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val) -#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) -#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val) -#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) -#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val) -#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) -#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val) -#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) -#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val) -#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) -#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val) -#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER) -#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val) -#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) -#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val) -#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) -#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val) -#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) -#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val) -#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) -#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val) -#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) -#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val) -#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) -#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val) -#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) -#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val) - -/* Mailbox Acceptance Masks */ -#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) -#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val) -#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) -#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val) -#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) -#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val) -#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) -#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val) -#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) -#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val) -#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) -#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val) -#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) -#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val) -#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) -#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val) -#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) -#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val) -#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) -#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val) -#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) -#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val) -#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) -#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val) -#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) -#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val) -#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) -#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val) -#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) -#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val) -#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) -#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val) -#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) -#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val) -#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) -#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val) -#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) -#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val) -#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) -#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val) -#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) -#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val) -#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) -#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val) -#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) -#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val) -#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) -#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val) -#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) -#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val) -#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) -#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val) -#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) -#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val) -#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) -#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val) -#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) -#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val) -#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) -#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val) -#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) -#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val) -#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) -#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val) - -#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) -#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val) -#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) -#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val) -#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) -#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val) -#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) -#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val) -#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) -#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val) -#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) -#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val) -#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) -#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val) -#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) -#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val) -#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) -#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val) -#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) -#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val) -#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) -#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val) -#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) -#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val) -#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) -#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val) -#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) -#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val) -#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) -#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val) -#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) -#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val) -#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) -#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val) -#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) -#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val) -#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) -#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val) -#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) -#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val) -#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) -#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val) -#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) -#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val) -#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) -#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val) -#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) -#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val) -#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) -#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val) -#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) -#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val) -#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) -#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val) -#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) -#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val) -#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) -#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val) -#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) -#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val) -#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) -#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val) -#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) -#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val) - -/* CAN Acceptance Mask Area Macros */ -#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x)) -#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val) -#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x)) -#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val) - -/* Mailbox Registers */ -#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) -#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val) -#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) -#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val) -#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) -#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val) -#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) -#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val) -#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) -#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val) -#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) -#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val) -#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) -#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val) -#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) -#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val) - -#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) -#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val) -#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) -#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val) -#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) -#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val) -#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) -#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val) -#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) -#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val) -#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) -#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val) -#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) -#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val) -#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) -#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val) - -#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) -#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val) -#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) -#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val) -#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) -#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val) -#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) -#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val) -#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) -#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val) -#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) -#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val) -#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) -#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val) -#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) -#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val) - -#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) -#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val) -#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) -#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val) -#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) -#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val) -#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) -#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val) -#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) -#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val) -#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) -#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val) -#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) -#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val) -#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) -#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val) - -#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) -#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val) -#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) -#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val) -#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) -#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val) -#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) -#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val) -#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) -#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val) -#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) -#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val) -#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) -#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val) -#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) -#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val) - -#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) -#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val) -#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) -#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val) -#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) -#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val) -#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) -#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val) -#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) -#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val) -#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) -#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val) -#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) -#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val) -#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) -#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val) - -#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) -#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val) -#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) -#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val) -#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) -#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val) -#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) -#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val) -#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) -#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val) -#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) -#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val) -#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) -#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val) -#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) -#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val) - -#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) -#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val) -#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) -#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val) -#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) -#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val) -#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) -#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val) -#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) -#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val) -#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) -#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val) -#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) -#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val) -#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) -#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val) - -#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) -#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val) -#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) -#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val) -#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) -#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val) -#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) -#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val) -#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) -#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val) -#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) -#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val) -#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) -#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val) -#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) -#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val) - -#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) -#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val) -#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) -#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val) -#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) -#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val) -#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) -#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val) -#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) -#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val) -#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) -#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val) -#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) -#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val) -#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) -#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val) - -#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) -#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val) -#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) -#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val) -#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) -#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val) -#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) -#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val) -#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) -#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val) -#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) -#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val) -#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) -#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val) -#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) -#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val) - -#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) -#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val) -#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) -#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val) -#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) -#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val) -#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) -#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val) -#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) -#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val) -#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) -#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val) -#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) -#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val) -#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) -#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val) - -#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) -#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val) -#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) -#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val) -#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) -#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val) -#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) -#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val) -#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) -#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val) -#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) -#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val) -#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) -#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val) -#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) -#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val) - -#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) -#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val) -#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) -#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val) -#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) -#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val) -#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) -#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val) -#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) -#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val) -#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) -#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val) -#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) -#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val) -#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) -#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val) - -#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) -#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val) -#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) -#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val) -#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) -#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val) -#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) -#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val) -#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) -#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val) -#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) -#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val) -#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) -#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val) -#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) -#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val) - -#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) -#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val) -#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) -#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val) -#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) -#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val) -#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) -#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val) -#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) -#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val) -#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) -#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val) -#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) -#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val) -#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) -#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val) - -#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) -#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val) -#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) -#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val) -#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) -#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val) -#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) -#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val) -#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) -#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val) -#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) -#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val) -#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) -#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val) -#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) -#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val) - -#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) -#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val) -#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) -#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val) -#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) -#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val) -#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) -#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val) -#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) -#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val) -#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) -#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val) -#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) -#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val) -#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) -#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val) - -#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) -#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val) -#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) -#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val) -#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) -#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val) -#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) -#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val) -#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) -#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val) -#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) -#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val) -#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) -#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val) -#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) -#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val) - -#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) -#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val) -#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) -#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val) -#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) -#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val) -#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) -#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val) -#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) -#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val) -#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) -#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val) -#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) -#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val) -#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) -#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val) - -#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) -#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val) -#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) -#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val) -#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) -#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val) -#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) -#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val) -#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) -#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val) -#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) -#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val) -#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) -#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val) -#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) -#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val) - -#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) -#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val) -#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) -#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val) -#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) -#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val) -#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) -#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val) -#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) -#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val) -#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) -#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val) -#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) -#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val) -#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) -#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val) - -#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) -#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val) -#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) -#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val) -#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) -#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val) -#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) -#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val) -#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) -#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val) -#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) -#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val) -#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) -#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val) -#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) -#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val) - -#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) -#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val) -#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) -#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val) -#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) -#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val) -#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) -#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val) -#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) -#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val) -#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) -#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val) -#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) -#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val) -#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) -#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val) - -#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) -#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val) -#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) -#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val) -#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) -#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val) -#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) -#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val) -#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) -#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val) -#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) -#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val) -#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) -#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val) -#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) -#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val) - -#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) -#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val) -#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) -#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val) -#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) -#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val) -#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) -#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val) -#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) -#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val) -#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) -#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val) -#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) -#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val) -#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) -#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val) - -#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) -#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val) -#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) -#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val) -#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) -#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val) -#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) -#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val) -#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) -#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val) -#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) -#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val) -#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) -#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val) -#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) -#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val) - -#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) -#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val) -#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) -#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val) -#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) -#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val) -#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) -#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val) -#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) -#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val) -#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) -#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val) -#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) -#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val) -#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) -#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val) - -#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) -#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val) -#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) -#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val) -#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) -#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val) -#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) -#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val) -#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) -#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val) -#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) -#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val) -#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) -#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val) -#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) -#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val) - -#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) -#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val) -#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) -#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val) -#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) -#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val) -#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) -#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val) -#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) -#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val) -#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) -#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val) -#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) -#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val) -#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) -#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val) - -#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) -#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val) -#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) -#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val) -#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) -#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val) -#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) -#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val) -#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) -#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val) -#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) -#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val) -#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) -#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val) -#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) -#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val) - -#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) -#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val) -#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) -#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val) -#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) -#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val) -#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) -#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val) -#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) -#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val) -#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) -#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val) -#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) -#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val) -#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) -#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val) - -/* CAN Mailbox Area Macros */ -#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x)) -#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val) -#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x)) -#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val) -#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x)) -#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val) -#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x)) -#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val) -#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x)) -#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val) -#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x)) -#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val) -#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x)) -#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val) -#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x)) -#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val) - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val) -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val) -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val) -#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX) -#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val) - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val) - -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) - -#endif /* _CDEF_BF534_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h deleted file mode 100644 index 19ec21ea150a..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _CDEF_BF537_H -#define _CDEF_BF537_H - -/* Include MMRs Common to BF534 */ -#include "cdefBF534.h" - -/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */ -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val) -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val) -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val) -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val) -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val) -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val) -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val) -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val) -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val) -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val) -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val) -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val) -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val) -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val) -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val) -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val) -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val) -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val) -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val) - -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val) -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val) -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val) -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val) -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val) -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val) -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val) -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val) - -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val) -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val) -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val) -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val) -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val) - -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val) -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val) -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val) -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val) -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val) -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val) -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val) -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val) -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val) -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val) -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val) -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val) -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val) -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val) -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val) -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val) -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val) -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val) -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val) -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val) -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val) -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val) -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val) -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val) - -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val) -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val) -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val) -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val) -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val) -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val) -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val) -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val) -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val) -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val) -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val) -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val) -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val) -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val) -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val) -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val) -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val) -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val) -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val) -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val) -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val) -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val) -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val) - -#endif /* _CDEF_BF537_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h deleted file mode 100644 index ef6a98cdfd44..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ /dev/null @@ -1,1470 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF534_H -#define _DEF_BF534_H - -/************************************************************************************ -** System MMR Register Map -*************************************************************************************/ -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 /* Chip ID Register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ - -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ - -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ - -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ - -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ - -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ - -/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Traffic Control Registers */ -#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ - -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ - -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ - -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ - -/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define TWI0_REGBASE 0xFFC01400 -#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - -/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ - -/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - -/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ -/* For Mailboxes 0-15 */ -#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ -#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ -#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ -#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ -#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ -#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ -#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ -#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ -#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ -#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ -#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ -#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ -#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */ - -/* For Mailboxes 16-31 */ -#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ -#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ -#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ -#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ -#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ -#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ -#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ -#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ -#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ -#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ -#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ -#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ -#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */ - -/* CAN Configuration, Control, and Status Registers */ -#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ -#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ -#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ -#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ -#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ -#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ -#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ -#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ -#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ -#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ - -#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ -#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ -#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ -#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ -#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ -#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ -#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ - -/* Mailbox Acceptance Masks */ -#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ -#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ -#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ -#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ -#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ -#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ -#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ -#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ -#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ -#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ -#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ -#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ -#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ -#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ -#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ -#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ -#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ -#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ -#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ -#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ -#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ -#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ -#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ -#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ -#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ -#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ -#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ -#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ -#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ -#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ -#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ -#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ - -#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ -#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ -#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ -#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ -#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ -#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ -#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ -#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ -#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ -#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ -#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ -#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ -#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ -#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ -#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ -#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ -#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ -#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ -#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ -#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ -#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ -#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ -#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ -#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ -#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ -#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ -#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ -#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ -#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ -#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ -#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ -#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ - -/* CAN Acceptance Mask Macros */ -#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) -#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) - -/* Mailbox Registers */ -#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ -#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ -#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ -#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ -#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ -#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ -#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ -#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ - -#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ -#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ -#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ -#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ -#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ -#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ -#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ -#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ - -#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ -#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ -#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ -#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ -#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ -#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ -#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ -#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ - -#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ -#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ -#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ -#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ -#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ -#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ -#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ -#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ - -#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ -#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ -#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ -#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ -#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ -#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ -#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ -#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ - -#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ -#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ -#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ -#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ -#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ -#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ -#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ -#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ - -#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ -#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ -#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ -#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ -#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ -#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ -#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ -#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ - -#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ -#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ -#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ -#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ -#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ -#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ -#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ -#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ - -#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ -#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ -#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ -#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ -#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ -#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ -#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ -#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ - -#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ -#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ -#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ -#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ -#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ -#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ -#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ -#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ - -#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ -#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ -#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ -#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ -#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ -#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ -#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ -#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ - -#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ -#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ -#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ -#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ -#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ -#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ -#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ -#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ - -#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ -#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ -#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ -#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ -#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ -#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ -#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ -#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ - -#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ -#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ -#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ -#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ -#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ -#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ -#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ -#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ - -#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ -#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ -#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ -#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ -#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ -#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ -#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ -#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ - -#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ -#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ -#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ -#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ -#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ -#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ -#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ -#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ - -#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ -#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ -#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ -#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ -#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ -#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ -#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ -#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ - -#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ -#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ -#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ -#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ -#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ -#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ -#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ -#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ - -#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ -#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ -#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ -#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ -#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ -#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ -#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ -#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ - -#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ -#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ -#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ -#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ -#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ -#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ -#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ -#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ - -#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ -#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ -#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ -#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ -#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ -#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ -#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ -#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ - -#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ -#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ -#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ -#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ -#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ -#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ -#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ -#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ - -#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ -#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ -#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ -#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ -#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ -#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ -#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ -#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ - -#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ -#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ -#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ -#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ -#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ -#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ -#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ -#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ - -#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ -#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ -#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ -#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ -#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ -#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ -#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ -#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ - -#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ -#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ -#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ -#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ -#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ -#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ -#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ -#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ - -#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ -#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ -#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ -#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ -#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ -#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ -#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ -#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ - -#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ -#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ -#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ -#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ -#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ -#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ -#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ -#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ - -#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ -#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ -#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ -#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ -#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ -#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ -#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ -#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ - -#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ -#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ -#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ -#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ -#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ -#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ -#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ -#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ - -#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ -#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ -#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ -#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ -#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ -#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ -#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ -#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ - -#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ -#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ -#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ -#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ -#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ -#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ -#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ -#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ - -/* CAN Mailbox Area Macros */ -#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) -#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) -#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) -#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) -#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) -#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) -#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) -#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) - -/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ - -/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ - -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ - -/* SIC_IAR0 Macros */ -#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Macros */ -#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Macros */ -#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IAR3 Macros */ -#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ -#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ -#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ -#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ -#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ -#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ -#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ -#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ - -/* **************** GENERAL PURPOSE TIMER MASKS **********************/ -/* TIMER_ENABLE Masks */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ -#define TIMEN3 0x0008 /* Enable Timer 3 */ -#define TIMEN4 0x0010 /* Enable Timer 4 */ -#define TIMEN5 0x0020 /* Enable Timer 5 */ -#define TIMEN6 0x0040 /* Enable Timer 6 */ -#define TIMEN7 0x0080 /* Enable Timer 7 */ - -/* TIMER_DISABLE Masks */ -#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ -#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ -#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ -#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ -#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ -#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ -#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ -#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ - -/* TIMER_STATUS Masks */ -#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ -#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ -#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ -#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ -#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ -#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ -#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ -#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 -/* TIMERx_CONFIG Masks */ -#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ -#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ -#define EXT_CLK 0x0003 /* External Clock Mode */ -#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ -#define PERIOD_CNT 0x0008 /* Period Count */ -#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ -#define TIN_SEL 0x0020 /* Timer Input Select */ -#define OUT_DIS 0x0040 /* Output Pad Disable */ -#define CLK_SEL 0x0080 /* Timer Clock Select */ -#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ -#define EMU_RUN 0x0200 /* Emulation Behavior Select */ -#define ERR_TYP 0xC000 /* Error Type */ - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ -#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ -#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ -#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ -#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ -#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ -#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ - -#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ -#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ -#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ -#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ -#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ -#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ -#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ -#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ -#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ -#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ -#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ -#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ -#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ - -#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ -#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ -#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ -#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ -#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ -#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ -#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ -#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ -#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ -#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ -#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ -#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ -#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ -#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ -#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ - -/* ********************** SDRAM CONTROLLER MASKS **********************************************/ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SDRAM Signals */ -#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ -#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ -#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ -#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ -#define EBUFE 0x02000000 /* Enable External Buffering Timing */ -#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ -#define EMREN 0x10000000 /* Extended Mode Register Enable */ -#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ -#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x0001 /* Enable SDRAM External Bank */ -#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ -#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ -#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ -#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ -#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ -#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ -#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x0001 /* SDRAM Controller Idle */ -#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ -#define SDPUA 0x0004 /* SDRAM Power-Up Active */ -#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ -#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ -#define BGSTAT 0x0020 /* Bus Grant Status */ - -/* ************************** DMA CONTROLLER MASKS ********************************/ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ -#define PMAP_PPI 0x0000 /* PPI Port DMA */ -#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ -#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ -#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ -#define PMAP_SPI 0x7000 /* SPI Port DMA */ -#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ -#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ -#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ -#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ - -/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - - -/* ******************* PIN CONTROL REGISTER MASKS ************************/ -/* PORT_MUX Masks */ -#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ -#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ -#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ - -#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ -#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ -#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ -#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ - -#define PFDE 0x0008 /* Port F DMA Request Enable */ -#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ -#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ - -#define PFTE 0x0010 /* Port F Timer Enable */ -#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ -#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ - -#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ -#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ -#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ - -#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ -#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ -#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ - -#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ -#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ -#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ - -#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ -#define PFFE_TIMER 0x0000 /* Enable TMR2 */ -#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ - -#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ -#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ -#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ - -#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ -#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ -#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ - -#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ -#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ -#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ - -/* entry addresses of the user-callable Boot ROM functions */ - -#define _BOOTROM_RESET 0xEF000000 -#define _BOOTROM_FINAL_INIT 0xEF000002 -#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 -#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 -#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A -#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C -#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 -#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 -#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define PGDE_UART PFDE_UART -#define PGDE_DMA PFDE_DMA -#define CKELOW SCKELOW -#endif /* _DEF_BF534_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h deleted file mode 100644 index e10332c9f660..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/defBF537.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF537_H -#define _DEF_BF537_H - -/* Include all MMR and bit defines common to BF534 */ -#include "defBF534.h" - -/************************************************************************************ -** Define EMAC Section Unique to BF536/BF537 -*************************************************************************************/ - -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ - -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ - -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ - -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ - -/* Listing for IEEE-Supported Count Registers */ -#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ -#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ -#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ -#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ -#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ -#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ -#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ -#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ -#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ -#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ -#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ -#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ -#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ -#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ -#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ -#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ -#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ -#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ -#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ - -#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ -#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ -#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ -#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ -#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ -#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ -#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ -#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ -#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ -#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ -#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ -#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ -#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ -#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ -#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ -#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ -#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ -#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ - -/*********************************************************************************** -** System MMR Register Bits And Macros -** -** Disclaimer: All macros are intended to make C and Assembly code more readable. -** Use these macros carefully, as any that do left shifts for field -** depositing will result in the lower order bits being destroyed. Any -** macro that shifts left to properly position the bit-field should be -** used as part of an OR to initialize a register and NOT as a dynamic -** modifier UNLESS the lower order bits are saved and ORed back in when -** the macro is used. -*************************************************************************************/ -/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ -/* EMAC_OPMODE Masks */ -#define RE 0x00000001 /* Receiver Enable */ -#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ -#define HU 0x00000010 /* Hash Filter Unicast Address */ -#define HM 0x00000020 /* Hash Filter Multicast Address */ -#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ -#define PR 0x00000080 /* Promiscuous Mode Enable */ -#define IFE 0x00000100 /* Inverse Filtering Enable */ -#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ -#define PBF 0x00000400 /* Pass Bad Frames Enable */ -#define PSF 0x00000800 /* Pass Short Frames Enable */ -#define RAF 0x00001000 /* Receive-All Mode */ -#define TE 0x00010000 /* Transmitter Enable */ -#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ -#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ -#define DC 0x00080000 /* Deferral Check */ -#define BOLMT 0x00300000 /* Back-Off Limit */ -#define BOLMT_10 0x00000000 /* 10-bit range */ -#define BOLMT_8 0x00100000 /* 8-bit range */ -#define BOLMT_4 0x00200000 /* 4-bit range */ -#define BOLMT_1 0x00300000 /* 1-bit range */ -#define DRTY 0x00400000 /* Disable TX Retry On Collision */ -#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ -#define RMII 0x01000000 /* RMII/MII* Mode */ -#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ -#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ -#define LB 0x08000000 /* Internal Loopback Enable */ -#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ - -/* EMAC_STAADD Masks */ -#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ -#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ -#define STADISPRE 0x00000004 /* Disable Preamble Generation */ -#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ -#define REGAD 0x000007C0 /* STA Register Address */ -#define PHYAD 0x0000F800 /* PHY Device Address */ - -#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ -#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ - -/* EMAC_STADAT Mask */ -#define STADATA 0x0000FFFF /* Station Management Data */ - -/* EMAC_FLC Masks */ -#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ -#define FLCE 0x00000002 /* Flow Control Enable */ -#define PCF 0x00000004 /* Pass Control Frames */ -#define BKPRSEN 0x00000008 /* Enable Backpressure */ -#define FLCPAUSE 0xFFFF0000 /* Pause Time */ - -#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ - -/* EMAC_WKUP_CTL Masks */ -#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ -#define MPKE 0x00000002 /* Magic Packet Enable */ -#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ -#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ -#define MPKS 0x00000020 /* Magic Packet Received Status */ -#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ - -/* EMAC_WKUP_FFCMD Masks */ -#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ -#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ -#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ -#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ -#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ -#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ -#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ -#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ - -/* EMAC_WKUP_FFOFF Masks */ -#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ -#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ -#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ -#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ - -#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ -#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ -#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ -#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ -/* Set ALL Offsets */ -#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) - -/* EMAC_WKUP_FFCRC0 Masks */ -#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ -#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ - -#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ -#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ - -/* EMAC_WKUP_FFCRC1 Masks */ -#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ -#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ - -#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ -#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ - -/* EMAC_SYSCTL Masks */ -#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ -#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ -#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ -#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ -#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ - -#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ - -/* EMAC_SYSTAT Masks */ -#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ -#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ -#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ -#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ -#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ -#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ -#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ -#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ - -/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ -#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ -#define RX_COMP 0x00001000 /* RX Frame Complete */ -#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ -#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ -#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ -#define RX_CRC 0x00010000 /* RX Frame CRC Error */ -#define RX_LEN 0x00020000 /* RX Frame Length Error */ -#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ -#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ -#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ -#define RX_PHY 0x00200000 /* RX Frame PHY Error */ -#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ -#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ -#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ -#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ -#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ -#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ -#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ -#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ -#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ -#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ - -/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ -#define TX_COMP 0x00000001 /* TX Frame Complete */ -#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ -#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ -#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ -#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ -#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ -#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ -#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ -#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ -#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ -#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ -#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ -#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ -#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ -#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ - -/* EMAC_MMC_CTL Masks */ -#define RSTC 0x00000001 /* Reset All Counters */ -#define CROLL 0x00000002 /* Counter Roll-Over Enable */ -#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ -#define MMCE 0x00000008 /* Enable MMC Counter Operation */ - -/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ -#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ -#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ -#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ -#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ -#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ -#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ -#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ -#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ -#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ -#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ -#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ -#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ -#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ -#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ -#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ -#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ -#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ -#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ -#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ -#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ -#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ -#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ -#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ -#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ - -/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ -#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ -#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ -#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ -#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ -#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ -#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ -#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ -#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ -#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ -#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ -#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ -#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ -#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ -#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ -#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ -#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ -#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ -#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ -#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ -#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ -#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ -#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ -#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ - -#endif /* _DEF_BF537_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h deleted file mode 100644 index 5ae83b1183a1..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/dma.h +++ /dev/null @@ -1,31 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define MAX_DMA_CHANNELS 16 - -#define CH_PPI 0 -#define CH_EMAC_RX 1 -#define CH_EMAC_TX 2 -#define CH_SPORT0_RX 3 -#define CH_SPORT0_TX 4 -#define CH_SPORT1_RX 5 -#define CH_SPORT1_TX 6 -#define CH_SPI 7 -#define CH_UART0_RX 8 -#define CH_UART0_TX 9 -#define CH_UART1_RX 10 -#define CH_UART1_TX 11 - -#define CH_MEM_STREAM0_DEST 12 /* TX */ -#define CH_MEM_STREAM0_SRC 13 /* RX */ -#define CH_MEM_STREAM1_DEST 14 /* TX */ -#define CH_MEM_STREAM1_SRC 15 /* RX */ - -#endif diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h deleted file mode 100644 index fba606b699c3..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/gpio.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 48 - -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 -#define GPIO_PG0 16 -#define GPIO_PG1 17 -#define GPIO_PG2 18 -#define GPIO_PG3 19 -#define GPIO_PG4 20 -#define GPIO_PG5 21 -#define GPIO_PG6 22 -#define GPIO_PG7 23 -#define GPIO_PG8 24 -#define GPIO_PG9 25 -#define GPIO_PG10 26 -#define GPIO_PG11 27 -#define GPIO_PG12 28 -#define GPIO_PG13 29 -#define GPIO_PG14 30 -#define GPIO_PG15 31 -#define GPIO_PH0 32 -#define GPIO_PH1 33 -#define GPIO_PH2 34 -#define GPIO_PH3 35 -#define GPIO_PH4 36 -#define GPIO_PH5 37 -#define GPIO_PH6 38 -#define GPIO_PH7 39 -#define GPIO_PH8 40 -#define GPIO_PH9 41 -#define GPIO_PH10 42 -#define GPIO_PH11 43 -#define GPIO_PH12 44 -#define GPIO_PH13 45 -#define GPIO_PH14 46 -#define GPIO_PH15 47 - -#define PORT_F GPIO_PF0 -#define PORT_G GPIO_PG0 -#define PORT_H GPIO_PH0 - -#include -#include -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h deleted file mode 100644 index b6ed8235bda4..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/irq.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BF537_IRQ_H_ -#define _BF537_IRQ_H_ - -#include - -#define NR_PERI_INTS 32 - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */ -#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */ -#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */ -#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */ -#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */ -#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */ -#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */ -#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */ -#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */ -#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */ -#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */ -#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */ -#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */ -#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */ -#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */ -#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */ -#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */ -#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */ -#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */ -#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */ -#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */ -#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */ -#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */ -#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */ -#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */ -#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */ -#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */ -#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */ -#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */ -#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */ -#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */ - -#define SYS_IRQS 39 - -#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */ -#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */ -#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */ -#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */ -#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */ -#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */ - -#define IRQ_PF0 50 -#define IRQ_PF1 51 -#define IRQ_PF2 52 -#define IRQ_PF3 53 -#define IRQ_PF4 54 -#define IRQ_PF5 55 -#define IRQ_PF6 56 -#define IRQ_PF7 57 -#define IRQ_PF8 58 -#define IRQ_PF9 59 -#define IRQ_PF10 60 -#define IRQ_PF11 61 -#define IRQ_PF12 62 -#define IRQ_PF13 63 -#define IRQ_PF14 64 -#define IRQ_PF15 65 - -#define IRQ_PG0 66 -#define IRQ_PG1 67 -#define IRQ_PG2 68 -#define IRQ_PG3 69 -#define IRQ_PG4 70 -#define IRQ_PG5 71 -#define IRQ_PG6 72 -#define IRQ_PG7 73 -#define IRQ_PG8 74 -#define IRQ_PG9 75 -#define IRQ_PG10 76 -#define IRQ_PG11 77 -#define IRQ_PG12 78 -#define IRQ_PG13 79 -#define IRQ_PG14 80 -#define IRQ_PG15 81 - -#define IRQ_PH0 82 -#define IRQ_PH1 83 -#define IRQ_PH2 84 -#define IRQ_PH3 85 -#define IRQ_PH4 86 -#define IRQ_PH5 87 -#define IRQ_PH6 88 -#define IRQ_PH7 89 -#define IRQ_PH8 90 -#define IRQ_PH9 91 -#define IRQ_PH10 92 -#define IRQ_PH11 93 -#define IRQ_PH12 94 -#define IRQ_PH13 95 -#define IRQ_PH14 96 -#define IRQ_PH15 97 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */ -#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */ -#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */ -#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */ -#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */ -#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */ -#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ -#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ - -#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */ -#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */ - -#if 0 /* No Interrupt B support (yet) */ -#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */ -#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */ -#else -#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX -#endif - -#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */ -#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */ - -#if 0 /* No Interrupt B support (yet) */ -#define IRQ_WATCH 112 /* Watchdog Timer */ -#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */ -#else -#define IRQ_WATCH IRQ_PF_INTB_WATCH -#endif - -#define NR_MACH_IRQS (113 + 1) - -/* IAR0 BIT FIELDS */ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA_ERROR_POS 4 -#define IRQ_ERROR_POS 8 -#define IRQ_RTC_POS 12 -#define IRQ_PPI_POS 16 -#define IRQ_SPORT0_RX_POS 20 -#define IRQ_SPORT0_TX_POS 24 -#define IRQ_SPORT1_RX_POS 28 - -/* IAR1 BIT FIELDS */ -#define IRQ_SPORT1_TX_POS 0 -#define IRQ_TWI_POS 4 -#define IRQ_SPI_POS 8 -#define IRQ_UART0_RX_POS 12 -#define IRQ_UART0_TX_POS 16 -#define IRQ_UART1_RX_POS 20 -#define IRQ_UART1_TX_POS 24 -#define IRQ_CAN_RX_POS 28 - -/* IAR2 BIT FIELDS */ -#define IRQ_CAN_TX_POS 0 -#define IRQ_MAC_RX_POS 4 -#define IRQ_MAC_TX_POS 8 -#define IRQ_TIMER0_POS 12 -#define IRQ_TIMER1_POS 16 -#define IRQ_TIMER2_POS 20 -#define IRQ_TIMER3_POS 24 -#define IRQ_TIMER4_POS 28 - -/* IAR3 BIT FIELDS */ -#define IRQ_TIMER5_POS 0 -#define IRQ_TIMER6_POS 4 -#define IRQ_TIMER7_POS 8 -#define IRQ_PROG_INTA_POS 12 -#define IRQ_PORTG_INTB_POS 16 -#define IRQ_MEM_DMA0_POS 20 -#define IRQ_MEM_DMA1_POS 24 -#define IRQ_WATCH_POS 28 - -#define init_mach_irq init_mach_irq - -#endif diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h deleted file mode 100644 index 942f08de306b..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/mem_map.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * BF537 memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x800 - -/* Level 1 Memory */ - -/* Memory Map for ADSP-BF537 processors */ - -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#else -#define BFIN_ICACHESIZE (0*1024) -#endif - - -#ifdef CONFIG_BF537 -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#define L1_CODE_LENGTH 0xC000 - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ - -#endif /*CONFIG_BF537*/ - -/* Memory Map for ADSP-BF536 processors */ - -#ifdef CONFIG_BF536 -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF804000 -#define L1_DATA_B_START 0xFF904000 - -#define L1_CODE_LENGTH 0xC000 - - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define L1_DATA_B_LENGTH 0x4000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 - -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define L1_DATA_B_LENGTH (0x4000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x4000 -#define L1_DATA_B_LENGTH 0x4000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ - -#endif - -/* Memory Map for ADSP-BF534 processors */ - -#ifdef CONFIG_BF534 -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#define L1_CODE_LENGTH 0xC000 - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 - -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ - -#endif - -#endif diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h deleted file mode 100644 index 94cca674d835..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h deleted file mode 100644 index 71d9eaeb579e..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/portmux.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ - -#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) -#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) -#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) -#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) -#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) -#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) -#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) -#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) -#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) -#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) -#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) -#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) -#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) -#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) -#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) -#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) -#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) -#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) -#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) -#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) -#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) -#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) -#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 - -#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) -#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) -#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) -#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) -#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) -#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) -#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) -#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) -#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) -#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) -#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) -#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) - -#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) -#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) -#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) -#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) -#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) -#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) -#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) -#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) -#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) -#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) -#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) -#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) -#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) -#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) -#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) -#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) -#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) -#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) -#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) - -#define PORT_PJ0 (GPIO_PH15 + 1) -#define PORT_PJ1 (GPIO_PH15 + 2) -#define PORT_PJ2 (GPIO_PH15 + 3) -#define PORT_PJ3 (GPIO_PH15 + 4) -#define PORT_PJ4 (GPIO_PH15 + 5) -#define PORT_PJ5 (GPIO_PH15 + 6) -#define PORT_PJ6 (GPIO_PH15 + 7) -#define PORT_PJ7 (GPIO_PH15 + 8) -#define PORT_PJ8 (GPIO_PH15 + 9) -#define PORT_PJ9 (GPIO_PH15 + 10) -#define PORT_PJ10 (GPIO_PH15 + 11) -#define PORT_PJ11 (GPIO_PH15 + 12) - -#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0)) -#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0)) -#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0)) -#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0)) -#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0)) -#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0)) -#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0)) -#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0)) -#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) -#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) -#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0)) -#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) -#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) -#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2)) - -#define P_MII0 {\ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxD2, \ - P_MII0_ETxD3, \ - P_MII0_ETxEN, \ - P_MII0_TxCLK, \ - P_MII0_PHYINT, \ - P_MII0_COL, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxD2, \ - P_MII0_ERxD3, \ - P_MII0_ERxDV, \ - P_MII0_ERxCLK, \ - P_MII0_ERxER, \ - P_MII0_CRS, \ - P_MDC, \ - P_MDIO, 0} - -#define P_RMII0 {\ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxEN, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxER, \ - P_RMII0_REF_CLK, \ - P_RMII0_MDINT, \ - P_RMII0_CRS_DV, \ - P_MDC, \ - P_MDIO, 0} - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c deleted file mode 100644 index a48baae4384d..000000000000 --- a/arch/blackfin/mach-bf537/ints-priority.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - * Set up the interrupt priorities - */ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | - ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) | - ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) | - ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) | - ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) | - ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | - ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | - ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS)); - - bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | - ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) | - ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) | - ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | - ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) | - ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | - ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | - ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS)); - - bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) | - ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) | - ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | - ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | - ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | - ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | - ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | - ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); - - bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | - ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | - ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | - ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) | - ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | - ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) | - ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) | - ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS)); - - SSYNC(); -} - -#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */ -#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */ -#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ -#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ -#define UART_ERR_MASK (0x6) /* UART_IIR */ -#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ - -static int error_int_mask; - -static void bf537_generic_error_mask_irq(struct irq_data *d) -{ - error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR)); - if (!error_int_mask) - bfin_internal_mask_irq(IRQ_GENERIC_ERROR); -} - -static void bf537_generic_error_unmask_irq(struct irq_data *d) -{ - bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); - error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR); -} - -static struct irq_chip bf537_generic_error_irqchip = { - .name = "ERROR", - .irq_ack = bfin_ack_noop, - .irq_mask_ack = bf537_generic_error_mask_irq, - .irq_mask = bf537_generic_error_mask_irq, - .irq_unmask = bf537_generic_error_unmask_irq, -}; - -static void bf537_demux_error_irq(struct irq_desc *inta_desc) -{ - int irq = 0; - -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) - if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) - irq = IRQ_MAC_ERROR; - else -#endif - if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) - irq = IRQ_SPORT0_ERROR; - else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) - irq = IRQ_SPORT1_ERROR; - else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) - irq = IRQ_PPI_ERROR; - else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) - irq = IRQ_CAN_ERROR; - else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) - irq = IRQ_SPI_ERROR; - else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK) - irq = IRQ_UART0_ERROR; - else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK) - irq = IRQ_UART1_ERROR; - - if (irq) { - if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) - bfin_handle_irq(irq); - else { - - switch (irq) { - case IRQ_PPI_ERROR: - bfin_write_PPI_STATUS(PPI_ERR_MASK); - break; -#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) - case IRQ_MAC_ERROR: - bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); - break; -#endif - case IRQ_SPORT0_ERROR: - bfin_write_SPORT0_STAT(SPORT_ERR_MASK); - break; - - case IRQ_SPORT1_ERROR: - bfin_write_SPORT1_STAT(SPORT_ERR_MASK); - break; - - case IRQ_CAN_ERROR: - bfin_write_CAN_GIS(CAN_ERR_MASK); - break; - - case IRQ_SPI_ERROR: - bfin_write_SPI_STAT(SPI_ERR_MASK); - break; - - default: - break; - } - - pr_debug("IRQ %d:" - " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", - irq); - } - } else - pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", - __func__); - -} - -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) -static int mac_rx_int_mask; - -static void bf537_mac_rx_mask_irq(struct irq_data *d) -{ - mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX)); - if (!mac_rx_int_mask) - bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX); -} - -static void bf537_mac_rx_unmask_irq(struct irq_data *d) -{ - bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX); - mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX); -} - -static struct irq_chip bf537_mac_rx_irqchip = { - .name = "ERROR", - .irq_ack = bfin_ack_noop, - .irq_mask_ack = bf537_mac_rx_mask_irq, - .irq_mask = bf537_mac_rx_mask_irq, - .irq_unmask = bf537_mac_rx_unmask_irq, -}; - -static void bf537_demux_mac_rx_irq(struct irq_desc *desc) -{ - if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR)) - bfin_handle_irq(IRQ_MAC_RX); - else - bfin_demux_gpio_irq(desc); -} -#endif - -void __init init_mach_irq(void) -{ - int irq; - -#if defined(CONFIG_BF537) || defined(CONFIG_BF536) - /* Clear EMAC Interrupt Status bits so we can demux it later */ - bfin_write_EMAC_SYSTAT(-1); -#endif - - irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq); - for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) - irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip, - handle_level_irq); - -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) - irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq); - irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq); - irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq); - - irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); -#endif -} diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig deleted file mode 100644 index 4aea85e4e5cf..000000000000 --- a/arch/blackfin/mach-bf538/Kconfig +++ /dev/null @@ -1,166 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if (BF538 || BF539) - -source "arch/blackfin/mach-bf538/boards/Kconfig" - -menu "BF538 Specific Configuration" - -comment "Interrupt Priority Assignment" -menu "Priority" - -config IRQ_PLL_WAKEUP - int "IRQ_PLL_WAKEUP" - default 7 -config IRQ_DMA0_ERROR - int "IRQ_DMA0_ERROR" - default 7 -config IRQ_PPI_ERROR - int "IRQ_PPI_ERROR" - default 7 -config IRQ_SPORT0_ERROR - int "IRQ_SPORT0_ERROR" - default 7 -config IRQ_SPORT1_ERROR - int "IRQ_SPORT1_ERROR" - default 7 -config IRQ_SPI0_ERROR - int "IRQ_SPI0_ERROR" - default 7 -config IRQ_UART0_ERROR - int "IRQ_UART0_ERROR" - default 7 -config IRQ_RTC - int "IRQ_RTC" - default 8 -config IRQ_PPI - int "IRQ_PPI" - default 8 -config IRQ_SPORT0_RX - int "IRQ_SPORT0_RX" - default 9 -config IRQ_SPORT0_TX - int "IRQ_SPORT0_TX" - default 9 -config IRQ_SPORT1_RX - int "IRQ_SPORT1_RX" - default 9 -config IRQ_SPORT1_TX - int "IRQ_SPORT1_TX" - default 9 -config IRQ_SPI0 - int "IRQ_SPI0" - default 10 -config IRQ_UART0_RX - int "IRQ_UART0_RX" - default 10 -config IRQ_UART0_TX - int "IRQ_UART0_TX" - default 10 -config IRQ_TIMER0 - int "IRQ_TIMER0" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config IRQ_TIMER1 - int "IRQ_TIMER1" - default 11 -config IRQ_TIMER2 - int "IRQ_TIMER2" - default 11 -config IRQ_PORTF_INTA - int "IRQ_PORTF_INTA" - default 12 -config IRQ_PORTF_INTB - int "IRQ_PORTF_INTB" - default 12 -config IRQ_MEM0_DMA0 - int "IRQ_MEM0_DMA0" - default 13 -config IRQ_MEM0_DMA1 - int "IRQ_MEM0_DMA1" - default 13 -config IRQ_WATCH - int "IRQ_WATCH" - default 13 -config IRQ_DMA1_ERROR - int "IRQ_DMA1_ERROR" - default 7 -config IRQ_SPORT2_ERROR - int "IRQ_SPORT2_ERROR" - default 7 -config IRQ_SPORT3_ERROR - int "IRQ_SPORT3_ERROR" - default 7 -config IRQ_SPI1_ERROR - int "IRQ_SPI1_ERROR" - default 7 -config IRQ_SPI2_ERROR - int "IRQ_SPI2_ERROR" - default 7 -config IRQ_UART1_ERROR - int "IRQ_UART1_ERROR" - default 7 -config IRQ_UART2_ERROR - int "IRQ_UART2_ERROR" - default 7 -config IRQ_CAN_ERROR - int "IRQ_CAN_ERROR" - default 7 -config IRQ_SPORT2_RX - int "IRQ_SPORT2_RX" - default 9 -config IRQ_SPORT2_TX - int "IRQ_SPORT2_TX" - default 9 -config IRQ_SPORT3_RX - int "IRQ_SPORT3_RX" - default 9 -config IRQ_SPORT3_TX - int "IRQ_SPORT3_TX" - default 9 -config IRQ_SPI1 - int "IRQ_SPI1" - default 10 -config IRQ_SPI2 - int "IRQ_SPI2" - default 10 -config IRQ_UART1_RX - int "IRQ_UART1_RX" - default 10 -config IRQ_UART1_TX - int "IRQ_UART1_TX" - default 10 -config IRQ_UART2_RX - int "IRQ_UART2_RX" - default 10 -config IRQ_UART2_TX - int "IRQ_UART2_TX" - default 10 -config IRQ_TWI0 - int "IRQ_TWI0" - default 11 -config IRQ_TWI1 - int "IRQ_TWI1" - default 11 -config IRQ_CAN_RX - int "IRQ_CAN_RX" - default 11 -config IRQ_CAN_TX - int "IRQ_CAN_TX" - default 11 -config IRQ_MEM1_DMA0 - int "IRQ_MEM1_DMA0" - default 13 -config IRQ_MEM1_DMA1 - int "IRQ_MEM1_DMA1" - default 13 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile deleted file mode 100644 index c0be54f2cd2b..000000000000 --- a/arch/blackfin/mach-bf538/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# arch/blackfin/mach-bf538/Makefile -# - -obj-y := ints-priority.o dma.o -obj-$(CONFIG_GPIOLIB) += ext-gpio.o diff --git a/arch/blackfin/mach-bf538/boards/Kconfig b/arch/blackfin/mach-bf538/boards/Kconfig deleted file mode 100644 index 114cff440d43..000000000000 --- a/arch/blackfin/mach-bf538/boards/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN538_EZKIT - help - Select your board! - -config BFIN538_EZKIT - bool "BF538-EZKIT" - help - BF538-EZKIT-LITE board support. - -endchoice diff --git a/arch/blackfin/mach-bf538/boards/Makefile b/arch/blackfin/mach-bf538/boards/Makefile deleted file mode 100644 index 6143b320d585..000000000000 --- a/arch/blackfin/mach-bf538/boards/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf538/boards/Makefile -# - -obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c deleted file mode 100644 index 1b6a52ad8a0e..000000000000 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ /dev/null @@ -1,987 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF538-EZKIT"; - -/* - * Driver needs to know address, irq and flag pin. - */ - - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif /* CONFIG_RTC_DRV_BFIN */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_THR, - .end = UART0_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART0_CTSRTS - { /* CTS pin */ - .start = GPIO_PG7, - .end = GPIO_PG7, - .flags = IORESOURCE_IO, - }, - { /* RTS pin */ - .start = GPIO_PG6, - .end = GPIO_PG6, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_SERIAL_BFIN_UART0 */ -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_THR, - .end = UART1_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_SERIAL_BFIN_UART1 */ -#ifdef CONFIG_SERIAL_BFIN_UART2 -static struct resource bfin_uart2_resources[] = { - { - .start = UART2_THR, - .end = UART2_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART2_TX, - .end = IRQ_UART2_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART2_RX, - .end = IRQ_UART2_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART2_ERROR, - .end = IRQ_UART2_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART2_TX, - .end = CH_UART2_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART2_RX, - .end = CH_UART2_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart2_peripherals[] = { - P_UART2_TX, P_UART2_RX, 0 -}; - -static struct platform_device bfin_uart2_device = { - .name = "bfin-uart", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_uart2_resources), - .resource = bfin_uart2_resources, - .dev = { - .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_SERIAL_BFIN_UART2 */ -#endif /* CONFIG_SERIAL_BFIN */ - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif /* CONFIG_BFIN_SIR0 */ -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif /* CONFIG_BFIN_SIR1 */ -#ifdef CONFIG_BFIN_SIR2 -static struct resource bfin_sir2_resources[] = { - { - .start = 0xFFC02100, - .end = 0xFFC021FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART2_RX, - .end = IRQ_UART2_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART2_RX, - .end = CH_UART2_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir2_device = { - .name = "bfin_sir", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_sir2_resources), - .resource = bfin_sir2_resources, -}; -#endif /* CONFIG_BFIN_SIR2 */ -#endif /* CONFIG_BFIN_SIR */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */ -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */ -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART -static struct resource bfin_sport2_uart_resources[] = { - { - .start = SPORT2_TCR1, - .end = SPORT2_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT2_RX, - .end = IRQ_SPORT2_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT2_ERROR, - .end = IRQ_SPORT2_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport2_peripherals[] = { - P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, - P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 -}; - -static struct platform_device bfin_sport2_uart_device = { - .name = "bfin-sport-uart", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), - .resource = bfin_sport2_uart_resources, - .dev = { - .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */ -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART -static struct resource bfin_sport3_uart_resources[] = { - { - .start = SPORT3_TCR1, - .end = SPORT3_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT3_RX, - .end = IRQ_SPORT3_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT3_ERROR, - .end = IRQ_SPORT3_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport3_peripherals[] = { - P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, - P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 -}; - -static struct platform_device bfin_sport3_uart_device = { - .name = "bfin-sport-uart", - .id = 3, - .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources), - .resource = bfin_sport3_uart_resources, - .dev = { - .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */ -#endif /* CONFIG_SERIAL_BFIN_SPORT */ - -#if IS_ENABLED(CONFIG_CAN_BFIN) -static unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN_RX, - .end = IRQ_CAN_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_TX, - .end = IRQ_CAN_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_ERROR, - .end = IRQ_CAN_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif /* CONFIG_CAN_BFIN */ - -/* - * USB-LAN EzExtender board - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20310300, - .end = 0x20310300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF0, - .end = IRQ_PF0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif /* CONFIG_SMC91X */ - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ -#if IS_ENABLED(CONFIG_MTD_M25P80) -/* SPI flash chip (m25p16) */ -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x1c0000, - .offset = 0x40000 - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif /* CONFIG_MTD_M25P80 */ -#endif /* CONFIG_SPI_BFIN5XX */ - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) -#include -static const struct ad7879_platform_data bfin_ad7879_ts_info = { - .model = 7879, /* Model = AD7879 */ - .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ - .pressure_max = 10000, - .pressure_min = 0, - .first_conversion_delay = 3, /* wait 512us before do a first conversion */ - .acquisition_time = 1, /* 4us acquisition time per sample */ - .median = 2, /* do 8 measurements */ - .averaging = 1, /* take the average of 4 middle samples */ - .pen_down_acc_interval = 255, /* 9.4 ms */ - .gpio_export = 1, /* Export GPIO to gpiolib */ - .gpio_base = -1, /* Dynamic allocation */ -}; -#endif /* CONFIG_TOUCHSCREEN_AD7879 */ - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) -#include - -static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { - .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, - .ppi_mode = USE_RGB565_16_BIT_PPI, - .use_bl = 0, /* let something else control the LCD Blacklight */ - .gpio_bl = GPIO_PF7, -}; - -static struct resource bfin_lq035q1_resources[] = { - { - .start = IRQ_PPI_ERROR, - .end = IRQ_PPI_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_lq035q1_device = { - .name = "bfin-lq035q1", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), - .resource = bfin_lq035q1_resources, - .dev = { - .platform_data = &bfin_lq035q1_data, - }, -}; -#endif /* CONFIG_FB_BFIN_LQ035Q1 */ - -static struct spi_board_info bf538_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* SPI_SSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif /* CONFIG_MTD_M25P80 */ -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI) - { - .modalias = "ad7879", - .platform_data = &bfin_ad7879_ts_info, - .irq = IRQ_PF3, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */ -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - { - .modalias = "bfin-lq035q1-spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - .mode = SPI_CPHA | SPI_CPOL, - }, -#endif /* CONFIG_FB_BFIN_LQ035Q1 */ -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif /* CONFIG_SPI_SPIDEV */ -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI0, - .end = CH_SPI0, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI (1) */ -static struct resource bfin_spi1_resource[] = { - [0] = { - .start = SPI1_REGBASE, - .end = SPI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI1, - .end = CH_SPI1, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI (2) */ -static struct resource bfin_spi2_resource[] = { - [0] = { - .start = SPI2_REGBASE, - .end = SPI2_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI2, - .end = CH_SPI2, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI2, - .end = IRQ_SPI2, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bf538_spi_master_info0 = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bf538_spi_master0 = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bf538_spi_master_info0, /* Passed to driver */ - }, -}; - -static struct bfin5xx_spi_master bf538_spi_master_info1 = { - .num_chipselect = 2, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, -}; - -static struct platform_device bf538_spi_master1 = { - .name = "bfin-spi", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi1_resource), - .resource = bfin_spi1_resource, - .dev = { - .platform_data = &bf538_spi_master_info1, /* Passed to driver */ - }, -}; - -static struct bfin5xx_spi_master bf538_spi_master_info2 = { - .num_chipselect = 2, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0}, -}; - -static struct platform_device bf538_spi_master2 = { - .name = "bfin-spi", - .id = 2, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi2_resource), - .resource = bfin_spi2_resource, - .dev = { - .platform_data = &bf538_spi_master_info2, /* Passed to driver */ - }, -}; - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI0, - .end = IRQ_TWI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi0_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; - -static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; - -static struct resource bfin_twi1_resource[] = { - [0] = { - .start = TWI1_REGBASE, - .end = TWI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI1, - .end = IRQ_TWI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi1_device = { - .name = "i2c-bfin-twi", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_twi1_resource), - .resource = bfin_twi1_resource, -}; -#endif /* CONFIG_I2C_BLACKFIN_TWI */ - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ -/* - * Internal VLEV BF538SBBC1533 - ****temporarily using these values until data sheet is updated - */ - VRPAIR(VLEV_100, 150000000), - VRPAIR(VLEV_100, 250000000), - VRPAIR(VLEV_110, 276000000), - VRPAIR(VLEV_115, 301000000), - VRPAIR(VLEV_120, 525000000), - VRPAIR(VLEV_125, 550000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezkit_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data ezkit_flash_data = { - .width = 2, - .parts = ezkit_partitions, - .nr_parts = ARRAY_SIZE(ezkit_partitions), -}; - -static struct resource ezkit_flash_resource = { - .start = 0x20000000, -#if IS_ENABLED(CONFIG_SMC91X) - .end = 0x202fffff, -#else - .end = 0x203fffff, -#endif - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezkit_flash_data, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource, -}; -#endif - -static struct platform_device *cm_bf538_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 - &bfin_uart2_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bf538_spi_master0, - &bf538_spi_master1, - &bf538_spi_master2, -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi0_device, - &i2c_bfin_twi1_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#ifdef CONFIG_BFIN_SIR2 - &bfin_sir2_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART - &bfin_sport2_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART - &bfin_sport3_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) - &bfin_can_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) - &bfin_lq035q1_device, -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezkit_flash_device, -#endif -}; - -static int __init ezkit_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices)); - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bf538_spi_board_info, - ARRAY_SIZE(bf538_spi_board_info)); -#endif - - return 0; -} - -arch_initcall(ezkit_init); - -static struct platform_device *ezkit_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 - &bfin_uart2_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART - &bfin_sport2_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART - &bfin_sport3_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezkit_early_devices, - ARRAY_SIZE(ezkit_early_devices)); -} diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c deleted file mode 100644 index cce8ef5a5cec..000000000000 --- a/arch/blackfin/mach-bf538/dma.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * the simple DMA Implementation for Blackfin - * - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) DMA8_NEXT_DESC_PTR, - (struct dma_register *) DMA9_NEXT_DESC_PTR, - (struct dma_register *) DMA10_NEXT_DESC_PTR, - (struct dma_register *) DMA11_NEXT_DESC_PTR, - (struct dma_register *) DMA12_NEXT_DESC_PTR, - (struct dma_register *) DMA13_NEXT_DESC_PTR, - (struct dma_register *) DMA14_NEXT_DESC_PTR, - (struct dma_register *) DMA15_NEXT_DESC_PTR, - (struct dma_register *) DMA16_NEXT_DESC_PTR, - (struct dma_register *) DMA17_NEXT_DESC_PTR, - (struct dma_register *) DMA18_NEXT_DESC_PTR, - (struct dma_register *) DMA19_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI: - ret_irq = IRQ_PPI; - break; - - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - - case CH_UART1_RX: - ret_irq = IRQ_UART1_RX; - break; - - case CH_UART1_TX: - ret_irq = IRQ_UART1_TX; - break; - - case CH_UART2_RX: - ret_irq = IRQ_UART2_RX; - break; - - case CH_UART2_TX: - ret_irq = IRQ_UART2_TX; - break; - - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - - case CH_SPORT2_RX: - ret_irq = IRQ_SPORT2_RX; - break; - - case CH_SPORT2_TX: - ret_irq = IRQ_SPORT2_TX; - break; - - case CH_SPORT3_RX: - ret_irq = IRQ_SPORT3_RX; - break; - - case CH_SPORT3_TX: - ret_irq = IRQ_SPORT3_TX; - break; - - case CH_SPI0: - ret_irq = IRQ_SPI0; - break; - - case CH_SPI1: - ret_irq = IRQ_SPI1; - break; - - case CH_SPI2: - ret_irq = IRQ_SPI2; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM0_DMA0; - break; - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM0_DMA1; - break; - case CH_MEM_STREAM2_SRC: - case CH_MEM_STREAM2_DEST: - ret_irq = IRQ_MEM1_DMA0; - break; - case CH_MEM_STREAM3_SRC: - case CH_MEM_STREAM3_DEST: - ret_irq = IRQ_MEM1_DMA1; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c deleted file mode 100644 index 48c100228f2d..000000000000 --- a/arch/blackfin/mach-bf538/ext-gpio.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs - * - * Copyright 2009-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include - -#define DEFINE_REG(reg, off) \ -static inline u16 read_##reg(void __iomem *port) \ - { return bfin_read16(port + off); } \ -static inline void write_##reg(void __iomem *port, u16 v) \ - { bfin_write16(port + off, v); } - -DEFINE_REG(PORTIO, 0x00) -DEFINE_REG(PORTIO_CLEAR, 0x10) -DEFINE_REG(PORTIO_SET, 0x20) -DEFINE_REG(PORTIO_DIR, 0x40) -DEFINE_REG(PORTIO_INEN, 0x50) - -static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip) -{ - switch (chip->base) { - default: /* not really needed, but keeps gcc happy */ - case GPIO_PC0: return (void __iomem *)PORTCIO; - case GPIO_PD0: return (void __iomem *)PORTDIO; - case GPIO_PE0: return (void __iomem *)PORTEIO; - } -} - -static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - return !!(read_PORTIO(port) & (1u << gpio)); -} - -static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - if (value) - write_PORTIO_SET(port, (1u << gpio)); - else - write_PORTIO_CLEAR(port, (1u << gpio)); -} - -static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio)); - write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio)); - return 0; -} - -static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio)); - bf538_gpio_set_value(port, gpio, value); - write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio)); - return 0; -} - -static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_special_gpio_request(chip->base + gpio, chip->label); -} - -static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_special_gpio_free(chip->base + gpio); -} - -/* We don't set the irq fields as these banks cannot generate interrupts */ - -static struct gpio_chip bf538_portc_chip = { - .label = "GPIO-PC", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PC0, - .ngpio = GPIO_PC9 - GPIO_PC0 + 1, -}; - -static struct gpio_chip bf538_portd_chip = { - .label = "GPIO-PD", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PD0, - .ngpio = GPIO_PD13 - GPIO_PD0 + 1, -}; - -static struct gpio_chip bf538_porte_chip = { - .label = "GPIO-PE", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PE0, - .ngpio = GPIO_PE15 - GPIO_PE0 + 1, -}; - -static int __init bf538_extgpio_setup(void) -{ - return gpiochip_add_data(&bf538_portc_chip, NULL) | - gpiochip_add_data(&bf538_portd_chip, NULL) | - gpiochip_add_data(&bf538_porte_chip, NULL); -} -arch_initcall(bf538_extgpio_setup); - -#ifdef CONFIG_PM -static struct { - u16 data, dir, inen; -} gpio_bank_saved[3]; - -static void __iomem * const port_bases[3] = { - (void *)PORTCIO, - (void *)PORTDIO, - (void *)PORTEIO, -}; - -void bfin_special_gpio_pm_hibernate_suspend(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(port_bases); ++i) { - gpio_bank_saved[i].data = read_PORTIO(port_bases[i]); - gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]); - gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]); - } -} - -void bfin_special_gpio_pm_hibernate_restore(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(port_bases); ++i) { - write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen); - write_PORTIO_SET(port_bases[i], - gpio_bank_saved[i].data & gpio_bank_saved[i].dir); - write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir); - } -} -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h deleted file mode 100644 index eaac26973f6a..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List - * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support old silicon - sorry */ -#if __SILICON_REVISION__ < 4 -# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3 -#endif - -#if defined(__ADSPBF538__) -# define ANOMALY_BF538 1 -#else -# define ANOMALY_BF538 0 -#endif -#if defined(__ADSPBF539__) -# define ANOMALY_BF539 1 -#else -# define ANOMALY_BF539 0 -#endif - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ -#define ANOMALY_05000166 (1) -/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ -#define ANOMALY_05000179 (1) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ -#define ANOMALY_05000193 (1) -/* Current DMA Address Shows Wrong Value During Carry Fix */ -#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) -/* NMI Event at Boot Time Results in Unpredictable State */ -#define ANOMALY_05000219 (1) -/* SPI Slave Boot Mode Modifies Registers from Reset Value */ -#define ANOMALY_05000229 (1) -/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ -#define ANOMALY_05000233 (1) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (__SILICON_REVISION__ < 4) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (ANOMALY_BF538) -/* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (__SILICON_REVISION__ < 4) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) -/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) -/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ -#define ANOMALY_05000283 (__SILICON_REVISION__ < 4) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 4) -/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */ -#define ANOMALY_05000291 (__SILICON_REVISION__ < 4) -/* Hibernate Leakage Current Is Higher Than Specified */ -#define ANOMALY_05000293 (__SILICON_REVISION__ < 4) -/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ -#define ANOMALY_05000294 (1) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (__SILICON_REVISION__ < 4) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 4) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (__SILICON_REVISION__ < 4) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 5) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) -/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ -#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) -/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */ -#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */ -/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ -#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */ -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (__SILICON_REVISION__ < 5) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (__SILICON_REVISION__ < 5) -/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ -#define ANOMALY_05000374 (__SILICON_REVISION__ == 4) -/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ -#define ANOMALY_05000375 (__SILICON_REVISION__ < 4) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 3) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* Specific GPIO Pins May Change State when Entering Hibernate */ -#define ANOMALY_05000436 (__SILICON_REVISION__ > 3) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* Possible Lockup Condition when Modifying PLL from External Memory */ -#define ANOMALY_05000475 (1) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* PLL May Latch Incorrect Values Coming Out of Reset */ -#define ANOMALY_05000489 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) - -/* - * These anomalies have been "phased" out of analog.com anomaly sheets and are - * here to show running on older silicon just isn't feasible. - */ - -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000099 (0) -#define ANOMALY_05000120 (0) -#define ANOMALY_05000125 (0) -#define ANOMALY_05000149 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000182 (0) -#define ANOMALY_05000189 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000202 (0) -#define ANOMALY_05000215 (0) -#define ANOMALY_05000220 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000231 (0) -#define ANOMALY_05000234 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000248 (0) -#define ANOMALY_05000250 (0) -#define ANOMALY_05000254 (0) -#define ANOMALY_05000257 (0) -#define ANOMALY_05000263 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000305 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000364 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000383 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000389 (0) -#define ANOMALY_05000400 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000440 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000456 (0) -#define ANOMALY_05000450 (0) -#define ANOMALY_05000465 (0) -#define ANOMALY_05000467 (0) -#define ANOMALY_05000474 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_05000485 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/bf538.h b/arch/blackfin/mach-bf538/include/mach/bf538.h deleted file mode 100644 index 0cf5bf8dab84..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/bf538.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538 - * - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF538_H__ -#define __MACH_BF538_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) - -#ifdef CONFIG_BF538 -#define CPU "BF538" -#define CPUID 0x27C4 -#endif -#ifdef CONFIG_BF539 -#define CPU "BF539" -#define CPUID 0x27C4 /* FXIME:? */ -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF538_H__ */ diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h deleted file mode 100644 index c66e2760aad3..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 3 - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h deleted file mode 100644 index 791d08400cf0..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#define BF538_FAMILY - -#include "bf538.h" -#include "anomaly.h" - -#include -#ifdef CONFIG_BF538 -# include "defBF538.h" -#endif -#ifdef CONFIG_BF539 -# include "defBF539.h" -#endif - -#ifndef __ASSEMBLY__ -# include -# ifdef CONFIG_BF538 -# include "cdefBF538.h" -# endif -# ifdef CONFIG_BF539 -# include "cdefBF539.h" -# endif -#endif - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h deleted file mode 100644 index f6a56792180b..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ /dev/null @@ -1,1960 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF538_H -#define _CDEF_BF538_H - -#define bfin_writePTR(addr, val) bfin_write32(addr, val) - -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val) -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0)) -#define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val) -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0)) -#define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define bfin_read_UART2_THR() bfin_read16(UART2_THR) -#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) -#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) -#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) -#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) -#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) -#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define bfin_read_UART2_IER() bfin_read16(UART2_IER) -#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val) -#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR) -#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val) -#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) -#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) -#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) -#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) -#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) -#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) -#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) -#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) -#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) -#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) -#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) -#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) -#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) -#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) -#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) -#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) -#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) -#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) -#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) -#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) -#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) -#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) -#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) -#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) -#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) -#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) -#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) -#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) -#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) -#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) -#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) -#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) -#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) -#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) -#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) -#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) -#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) -#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) -#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) -#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) -#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) -#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) -#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) -#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) -#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) -#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) -#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) -#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) -#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) -#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) -#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) -#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) -#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) -#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) -#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) -#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) -#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) -#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) -#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) -#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) -#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) -#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) -#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) -#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) -#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) -#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) -#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) -#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER) -#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val) -#define bfin_read_PORTCIO() bfin_read16(PORTCIO) -#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val) -#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR) -#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val) -#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET) -#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val) -#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE) -#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val) -#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR) -#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val) -#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN) -#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val) -#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER) -#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val) -#define bfin_read_PORTDIO() bfin_read16(PORTDIO) -#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val) -#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR) -#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val) -#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET) -#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val) -#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE) -#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val) -#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR) -#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val) -#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN) -#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val) -#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER) -#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val) -#define bfin_read_PORTEIO() bfin_read16(PORTEIO) -#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val) -#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR) -#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val) -#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET) -#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val) -#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE) -#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val) -#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR) -#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val) -#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN) -#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val) -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) -#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val) -#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) -#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) -#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val) -#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) -#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) -#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) -#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) -#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) -#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) -#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) -#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) -#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) -#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) -#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) -#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) -#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) -#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) -#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) -#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) -#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) -#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) -#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) -#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) -#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) -#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) -#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) -#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) -#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) -#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) -#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) -#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) -#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) -#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) -#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) -#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) -#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) -#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) -#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) -#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) -#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) -#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) -#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) -#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) -#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) -#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) -#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) -#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) -#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) -#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) -#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) -#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) -#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) -#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) -#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) -#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) -#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) -#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) -#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) -#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) -#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) -#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) -#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) -#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) -#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) -#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) -#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) -#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) -#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) -#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) -#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) -#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) -#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) -#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) -#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) -#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) -#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) -#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) -#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) -#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) -#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) -#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) -#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) -#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) -#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) -#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) -#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) -#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) -#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) -#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) -#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) -#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) -#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) -#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) -#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) -#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) -#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) -#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) -#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) -#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) -#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) -#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) -#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) -#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) -#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) -#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) -#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) -#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) -#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) -#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) -#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) -#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) -#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) -#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) -#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) -#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) -#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) -#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) -#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) -#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) -#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) -#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) -#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) -#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) -#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) -#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) -#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) -#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) -#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) -#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) -#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) -#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) -#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) -#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) -#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) -#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) -#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) -#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) -#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) -#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) -#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) -#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) -#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) -#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) -#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) -#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) -#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) -#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) -#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) -#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) -#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) -#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) -#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) -#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) -#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) -#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) -#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) -#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) -#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) -#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) -#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) -#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) -#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) -#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) -#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) -#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) -#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) -#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) -#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) -#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) -#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) -#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) -#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) -#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) -#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) -#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) -#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) -#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) -#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) -#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) -#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) -#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) -#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) -#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) -#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) -#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) -#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) -#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) -#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) -#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) -#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) -#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) -#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) -#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) -#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) -#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) -#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) -#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) -#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) -#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) -#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) -#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) -#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) -#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) -#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) -#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) -#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) -#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) -#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) -#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) -#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) -#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) -#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) -#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) -#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) -#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) -#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) -#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) -#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) -#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) -#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) -#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) -#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) -#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) -#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) -#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) -#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) -#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) -#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) -#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) -#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) -#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) -#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) -#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) -#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) -#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) -#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) -#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) -#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) -#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) -#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) -#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) -#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) -#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) -#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) -#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) -#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) -#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) -#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) -#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) -#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) -#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) -#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) -#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) -#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) -#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) -#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) -#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) -#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) -#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) -#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) -#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) -#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) -#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) -#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) -#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) -#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) -#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) -#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) -#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) -#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) -#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) -#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) -#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) -#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) -#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) -#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) -#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) -#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) -#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) -#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) -#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) -#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) -#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) -#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) -#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) -#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) -#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) -#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) -#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) -#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) -#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) -#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) -#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) -#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) -#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) -#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) -#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) -#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) -#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) -#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) -#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) -#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) -#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) -#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) -#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) -#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) -#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) -#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) -#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) -#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) -#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) -#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) -#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) -#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) -#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) -#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) -#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) -#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) -#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) -#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) -#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) -#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) -#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) -#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) -#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) -#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) -#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) -#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) -#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) -#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) -#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) -#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) -#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) -#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) -#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) -#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) -#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) -#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) -#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) -#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) -#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) -#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) -#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) -#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) -#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) -#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) -#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) -#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) -#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) -#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) -#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) -#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) -#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) -#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) -#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) -#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) -#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) -#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) -#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) -#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) -#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) -#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) -#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) -#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) -#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) -#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) -#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) -#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) -#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) -#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) -#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) -#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) -#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) -#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) -#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) -#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) -#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) -#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) -#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) -#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) -#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) -#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) -#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) -#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) -#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) -#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) -#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) -#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) -#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) -#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) -#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) -#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) -#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) -#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) -#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) -#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) -#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) -#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) -#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) -#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) -#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) -#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) -#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) -#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) -#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) -#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) -#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) -#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) -#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) -#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) -#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) -#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) -#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) -#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) -#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) -#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) -#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) -#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) -#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) -#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) -#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) -#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) -#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) -#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) -#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) -#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) -#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) -#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) -#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) -#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) -#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) -#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) -#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) -#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) -#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) -#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) -#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) -#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) -#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) -#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) -#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) -#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) -#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) -#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) -#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) -#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) -#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) -#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) -#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) -#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) -#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) -#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) -#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) -#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) -#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) -#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) -#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) -#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) -#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) -#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) -#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) -#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) -#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) -#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) -#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) -#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) -#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) -#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) -#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) -#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) -#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) -#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) -#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) -#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) -#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) -#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) -#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) -#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) -#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) -#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) -#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) -#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) -#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) -#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) -#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) -#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) -#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) -#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) -#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) -#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) -#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) -#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) -#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) -#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) -#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) -#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) -#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) -#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) -#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) -#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) -#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) -#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) -#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) -#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) -#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) -#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) -#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) -#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) -#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) -#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) -#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) -#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) -#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) -#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) -#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) -#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) -#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) -#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) -#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) -#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) -#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) -#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) -#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) -#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) -#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) -#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) -#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) -#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) -#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) -#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) -#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) -#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) -#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) -#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) -#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) -#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) -#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) -#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) -#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) -#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) -#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) -#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) -#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) -#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) -#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) -#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) -#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) -#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) -#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) -#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) -#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) -#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) -#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) -#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) -#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) -#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) -#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) -#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) -#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) -#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) -#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) -#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) -#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) -#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) -#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) -#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) -#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) -#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) -#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) -#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) -#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) -#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) -#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) -#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) -#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) -#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) -#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) -#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) -#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) -#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) -#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) -#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) -#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) -#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) -#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) -#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) -#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) -#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) -#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) -#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) -#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) -#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) -#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) -#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) -#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) -#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) -#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) -#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) -#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) -#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) -#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) -#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) -#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) -#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) -#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) -#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) -#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) -#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) -#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) -#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) -#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) -#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) -#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) -#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) -#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) -#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) -#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) -#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) -#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) -#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) -#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) -#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) -#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) -#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) -#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) -#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) -#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) -#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) -#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) -#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) -#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) -#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) -#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) -#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) -#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) -#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) -#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) -#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) -#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) -#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) -#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) -#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) -#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) -#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) -#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) -#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) -#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) -#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) -#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) -#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) -#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) -#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) -#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) -#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) -#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) -#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) -#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) -#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) -#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) -#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) -#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) -#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) -#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) -#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) -#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) -#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) -#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) -#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) -#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) -#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) -#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) -#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) -#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) -#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) -#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) -#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) -#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) -#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) -#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) -#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) -#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) -#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) -#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) -#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) -#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) -#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) -#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) -#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) -#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) -#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) -#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) -#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) -#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) -#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) -#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) -#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) -#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) -#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) -#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) -#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) -#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) -#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) -#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) -#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) -#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) -#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) -#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) -#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) -#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) -#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) -#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) -#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) -#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) -#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) -#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) -#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) -#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) -#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) -#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) -#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) -#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) -#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) -#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) -#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) -#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) -#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) -#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) -#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) -#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) -#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) -#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) -#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) -#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) -#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) -#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) -#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) -#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) -#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) -#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) -#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) -#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) -#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h deleted file mode 100644 index acc15f3aba38..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF539_H -#define _CDEF_BF539_H - -/* Include MMRs Common to BF538 */ -#include "cdefBF538.h" - -#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) -#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) -#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0) -#define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val) -#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0) -#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) -#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1) -#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) -#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0) -#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) -#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1) -#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) -#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0) -#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) -#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1) -#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) -#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION) -#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) -#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION) -#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) -#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY) -#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val) -#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY) -#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val) -#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR) -#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val) -#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR) -#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val) -#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR) -#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val) -#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0) -#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val) -#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1) -#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val) -#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2) -#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val) -#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3) -#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val) -#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4) -#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val) -#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5) -#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val) -#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6) -#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val) -#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7) -#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val) -#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8) -#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val) -#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9) -#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val) -#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10) -#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val) -#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11) -#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val) -#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12) -#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val) -#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13) -#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val) -#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14) -#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val) -#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0) -#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val) -#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1) -#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val) -#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2) -#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val) -#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3) -#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val) -#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4) -#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val) -#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5) -#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val) -#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6) -#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val) -#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7) -#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val) -#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG) -#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val) -#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR) -#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val) -#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT) -#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val) -#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR) -#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val) -#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT) -#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val) -#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG) -#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val) -#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR) -#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val) -#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT) -#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val) -#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR) -#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val) -#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT) -#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val) -#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG) -#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val) -#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR) -#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val) -#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT) -#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val) -#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR) -#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val) -#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT) -#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val) -#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG) -#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val) -#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR) -#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val) -#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT) -#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val) -#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR) -#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val) -#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT) -#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val) -#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG) -#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val) -#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR) -#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val) -#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT) -#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val) -#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR) -#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val) -#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT) -#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val) -#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG) -#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val) -#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR) -#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val) -#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT) -#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val) -#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR) -#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val) -#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT) -#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val) -#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG) -#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val) -#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR) -#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val) -#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT) -#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val) -#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR) -#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val) -#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT) -#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val) -#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG) -#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val) -#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR) -#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val) -#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT) -#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val) -#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR) -#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val) -#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT) -#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val) -#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL) -#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val) -#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR) -#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val) -#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR) -#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val) -#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR) -#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val) -#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR) -#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val) -#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL) -#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val) -#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR) -#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val) -#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR) -#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val) -#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR) -#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val) -#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR) -#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val) -#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR) -#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val) -#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR) -#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val) -#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0) -#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val) -#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0) -#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val) -#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1) -#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val) -#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1) -#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val) -#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0) -#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val) -#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1) -#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val) -#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0) -#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val) -#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1) -#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val) -#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2) -#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val) -#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3) -#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val) -#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4) -#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val) -#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5) -#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val) -#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6) -#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val) -#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7) -#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val) -#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8) -#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val) -#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9) -#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val) -#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10) -#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val) -#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11) -#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val) -#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12) -#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val) -#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13) -#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val) -#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14) -#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val) -#define bfin_read_MXVR_PLL_CTL_1() bfin_read32(MXVR_PLL_CTL_1) -#define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val) -#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT) -#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val) - -#endif /* _CDEF_BF539_H */ diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h deleted file mode 100644 index 876a77028001..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/defBF538.h +++ /dev/null @@ -1,1749 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF538_H -#define _DEF_BF538_H - -/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID Register */ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration registe */ -#define SIC_RVECT 0xFFC00108 -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ -#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ -#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ -#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ -#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ - - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ - - -/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ - - -/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ - -#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ -#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ -#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ -#define SPI0_REGBASE SPI0_CTL - - -/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ - - -/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */ -#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ -#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ -#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ -#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ -#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ -#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ -#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ -#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ -#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ -#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ -#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ -#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ -#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ -#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ -#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ -#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ -#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ - - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - - -/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -/* Asynchronous Memory Controller */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - - - -/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ - -#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ - - - -/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */ - -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ - -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ - -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ - -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ - -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ - -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ - -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ - -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ - -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ - -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ - -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ - -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ - - -/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - - -/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ -#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ -#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ -#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ - -#define TWI0_REGBASE TWI0_CLKDIV - -/* the following are for backwards compatibility */ -#define TWI0_PRESCALE TWI0_CONTROL -#define TWI0_INT_SRC TWI0_INT_STAT -#define TWI0_INT_ENABLE TWI0_INT_MASK - - -/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ - -/* GPIO Port C Register Names */ -#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ -#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ -#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ -#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ -#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ -#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ -#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ - -/* GPIO Port D Register Names */ -#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ -#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ -#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ -#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ -#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ -#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ -#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ - -/* GPIO Port E Register Names */ -#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ -#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ -#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ -#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ -#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ -#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ -#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ - -/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ - -#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ - - - -/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ -#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ - -#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ - -#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ - -#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ - -#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ - -#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ - -#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ - -#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ - -#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ - -#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ - -#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ - -#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ - -#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ -#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ -#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ -#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ -#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ -#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ -#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ -#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ - -#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ -#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ -#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ -#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ -#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ -#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ -#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ -#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ - -#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ -#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ -#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ -#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ -#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ -#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ -#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ -#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ - -#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ -#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ -#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ -#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ -#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ -#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ -#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ -#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ - - -/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ - - -/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ -#define UART2_THR 0xFFC02100 /* Transmit Holding register */ -#define UART2_RBR 0xFFC02100 /* Receive Buffer register */ -#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ -#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ -#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ -#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ -#define UART2_LCR 0xFFC0210C /* Line Control Register */ -#define UART2_MCR 0xFFC02110 /* Modem Control Register */ -#define UART2_LSR 0xFFC02114 /* Line Status Register */ -#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ -#define UART2_GCTL 0xFFC02124 /* Global Control Register */ - - -/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ -#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ -#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ -#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ -#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ -#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ -#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ -#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ -#define TWI1_REGBASE TWI1_CLKDIV - - -/* the following are for backwards compatibility */ -#define TWI1_PRESCALE TWI1_CONTROL -#define TWI1_INT_SRC TWI1_INT_STAT -#define TWI1_INT_ENABLE TWI1_INT_MASK - - -/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ -#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ -#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ -#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ -#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ -#define SPI1_REGBASE SPI1_CTL - -/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ -#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ -#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ -#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ -#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ -#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ -#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ -#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ -#define SPI2_REGBASE SPI2_CTL - -/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ -#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ -#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ -#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ -#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ -#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ -#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ -#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ -#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ -#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ -#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ - - -/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ -#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ -#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ -#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ -#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ -#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ -#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ -#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ -#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ -#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ -#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */ - - -/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ -/* For Mailboxes 0-15 */ -#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ -#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ -#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ -#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ -#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ -#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ -#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ -#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ -#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ -#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ -#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ -#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ -#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ - -/* For Mailboxes 16-31 */ -#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ -#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ -#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ -#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ -#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ -#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ -#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ -#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ -#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ -#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ -#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ -#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ -#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ - -#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ -#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ - -#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ -/* the following is for backwards compatibility */ -#define CAN_CNF CAN_DEBUG - -#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ -#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ -#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ -#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ -#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ -#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ -#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ -#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ -#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ -#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ -#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ -#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ -#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ - -/* Mailbox Acceptance Masks */ -#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ -#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ -#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ -#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ -#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ -#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ -#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ -#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ -#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ -#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ -#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ -#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ -#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ -#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ -#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ -#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ -#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ -#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ -#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ -#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ -#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ -#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ -#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ -#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ -#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ -#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ -#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ -#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ -#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ -#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ -#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ -#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ - -#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ -#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ -#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ -#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ -#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ -#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ -#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ -#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ -#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ -#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ -#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ -#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ -#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ -#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ -#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ -#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ -#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ -#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ -#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ -#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ -#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ -#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ -#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ -#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ -#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ -#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ -#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ -#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ -#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ -#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ -#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ -#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ - -/* CAN Acceptance Mask Macros */ -#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) -#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) - -/* Mailbox Registers */ -#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ -#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ -#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ -#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ -#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ -#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ -#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ -#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ - -#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ -#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ -#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ -#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ -#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ -#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ -#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ -#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ - -#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ -#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ -#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ -#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ -#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ -#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ -#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ -#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ - -#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ -#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ -#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ -#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ -#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ -#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ -#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ -#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ - -#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ -#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ -#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ -#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ -#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ -#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ -#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ -#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ - -#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ -#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ -#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ -#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ -#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ -#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ -#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ -#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ - -#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ -#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ -#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ -#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ -#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ -#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ -#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ -#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ - -#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ -#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ -#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ -#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ -#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ -#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ -#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ -#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ - -#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ -#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ -#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ -#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ -#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ -#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ -#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ -#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ - -#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ -#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ -#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ -#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ -#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ -#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ -#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ -#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ - -#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ -#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ -#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ -#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ -#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ -#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ -#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ -#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ - -#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ -#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ -#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ -#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ -#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ -#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ -#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ -#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ - -#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ -#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ -#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ -#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ -#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ -#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ -#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ -#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ - -#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ -#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ -#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ -#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ -#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ -#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ -#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ -#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ - -#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ -#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ -#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ -#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ -#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ -#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ -#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ -#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ - -#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ -#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ -#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ -#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ -#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ -#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ -#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ -#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ - -#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ -#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ -#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ -#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ -#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ -#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ -#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ -#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ - -#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ -#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ -#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ -#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ -#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ -#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ -#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ -#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ - -#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ -#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ -#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ -#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ -#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ -#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ -#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ -#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ - -#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ -#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ -#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ -#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ -#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ -#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ -#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ -#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ - -#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ -#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ -#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ -#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ -#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ -#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ -#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ -#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ - -#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ -#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ -#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ -#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ -#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ -#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ -#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ -#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ - -#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ -#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ -#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ -#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ -#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ -#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ -#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ -#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ - -#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ -#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ -#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ -#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ -#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ -#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ -#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ -#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ - -#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ -#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ -#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ -#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ -#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ -#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ -#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ -#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ - -#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ -#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ -#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ -#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ -#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ -#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ -#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ -#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ - -#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ -#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ -#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ -#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ -#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ -#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ -#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ -#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ - -#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ -#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ -#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ -#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ -#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ -#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ -#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ -#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ - -#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ -#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ -#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ -#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ -#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ -#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ -#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ -#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ - -#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ -#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ -#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ -#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ -#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ -#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ -#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ -#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ - -#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ -#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ -#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ -#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ -#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ -#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ -#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ -#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ - -#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ -#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ -#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ -#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ -#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ -#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ -#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ -#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ - -/* CAN Mailbox Area Macros */ -#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) -#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) -#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) -#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) -#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) -#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) -#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) -#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) - - -/*********************************************************************************** */ -/* System MMR Register Bits and Macros */ -/******************************************************************************* */ - -/* SWRST Mask */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ - -/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */ -#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */ -#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */ -#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */ -#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */ -#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */ -#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */ -#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */ -#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */ -#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */ -#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */ -#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */ -#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */ -#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */ -#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */ -#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */ -#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */ -#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */ -#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */ -#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */ -#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */ -#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */ -#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */ -#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */ -#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */ -#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */ -#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */ -#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */ -#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */ -#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */ -#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */ -#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */ -#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */ - -/* the following are for backwards compatibility */ -#define DMA0_ERR_IRQ DMAC0_ERR_IRQ -#define DMA1_ERR_IRQ DMAC1_ERR_IRQ - - -/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ -#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */ -#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */ -#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */ -#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */ -#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */ -#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */ -#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */ -#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */ -#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */ -#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */ -#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */ -#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */ -#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */ -#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */ -#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */ -#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */ -#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */ -#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */ -#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */ -#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */ -#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */ -#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */ - -/* the following are for backwards compatibility */ -#define MDMA0_IRQ MDMA1_0_IRQ -#define MDMA1_IRQ MDMA1_1_IRQ - -#ifdef _MISRA_RULES -#define _MF15 0xFu -#define _MF7 7u -#else -#define _MF15 0xF -#define _MF7 7 -#endif /* _MISRA_RULES */ - -/* SIC_IMASKx Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#ifdef _MISRA_RULES -#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */ -#else -#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ -#endif /* _MISRA_RULES */ - -/* SIC_IWRx Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#ifdef _MISRA_RULES -#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */ -#else -#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ -#endif /* _MISRA_RULES */ - -/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#ifdef _MISRA_RULES -#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#else -#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#endif /* _MISRA_RULES */ -#define POL 0xC000 /* PPI Signal Polarities */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - - -/* ********** DMA CONTROLLER MASKS ***********************/ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ - -#define CTYPE 0x0040 /* DMA Channel Type Indicator */ -#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x0400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x0800 /* DMA Read Operation Indicator */ -#define PMAP 0xF000 /* DMA Peripheral Map Field */ - -/* PMAP Encodings For DMA Controller 0 */ -#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ -#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ -#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */ -#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */ -#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */ - -/* PMAP Encodings For DMA Controller 1 */ -#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */ -#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */ -#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */ -#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */ -#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */ -#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */ -#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */ -#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */ -#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */ -#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */ - - -/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ -/* PWM Timer bit definitions */ -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 /* Disable Timer 0 */ -#define TIMDIS1 0x0002 /* Disable Timer 1 */ -#define TIMDIS2 0x0004 /* Disable Timer 2 */ - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x0001 /* Timer 0 Interrupt */ -#define TIMIL1 0x0002 /* Timer 1 Interrupt */ -#define TIMIL2 0x0004 /* Timer 2 Interrupt */ -#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ -#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TOVF_ERR0_P 0x04 -#define TOVF_ERR1_P 0x05 -#define TOVF_ERR2_P 0x06 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR0_P TOVF_ERR0_P -#define TOVL_ERR1_P TOVF_ERR1_P -#define TOVL_ERR2_P TOVF_ERR2_P - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#ifdef _MISRA_RULES -#define ERR_TYP(x) (((x) & 0x03u) << 14) -#else -#define ERR_TYP(x) (((x) & 0x03) << 14) -#endif /* _MISRA_RULES */ - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ -#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */ - -/* EBIU_AMGCTL Bit Positions */ -#define AMCKEN_P 0x0000 /* Enable CLKOUT */ -#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* ********************** SDRAM CONTROLLER MASKS *************************** */ -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /*Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x00000001 /* Enable SDRAM external bank */ -#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h deleted file mode 100644 index 199e871634b4..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF539_H -#define _DEF_BF539_H - -#include "defBF538.h" - -/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */ - -#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */ -#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */ - -#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */ -#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */ - -#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */ -#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */ - -#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */ -#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */ - -#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */ -#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */ - -#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */ -#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */ - -#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */ -#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */ -#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */ - -#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */ -#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */ -#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */ -#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */ -#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */ -#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */ -#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */ -#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */ -#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */ -#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */ -#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */ -#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */ -#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */ -#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */ -#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */ - -#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ -#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */ -#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ -#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ -#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ -#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */ -#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ -#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ - -#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */ -#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */ -#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */ -#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */ -#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */ - -#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */ -#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */ -#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */ -#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */ -#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */ - -#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */ -#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */ -#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */ -#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */ -#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */ - -#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */ -#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */ -#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */ -#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */ -#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */ - -#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */ -#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */ -#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */ -#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */ -#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */ - -#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */ -#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */ -#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */ -#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */ -#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */ - -#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */ -#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */ -#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */ -#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */ -#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */ - -#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */ -#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */ -#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */ -#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */ -#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */ - -#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */ -#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */ -#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */ -#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */ -#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */ - -#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */ -#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */ -#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */ -#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */ -#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */ - -#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */ -#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */ - -#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */ -#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */ -#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */ -#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */ - -#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */ -#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */ - -#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */ -#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */ -#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */ -#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */ -#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */ -#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */ -#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */ -#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */ -#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */ -#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */ -#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */ -#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */ -#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */ -#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */ -#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */ - -#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */ -#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */ -#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */ - -#endif /* _DEF_BF539_H */ diff --git a/arch/blackfin/mach-bf538/include/mach/dma.h b/arch/blackfin/mach-bf538/include/mach/dma.h deleted file mode 100644 index eb05cacbf4d3..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/dma.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define CH_PPI 0 -#define CH_SPORT0_RX 1 -#define CH_SPORT0_TX 2 -#define CH_SPORT1_RX 3 -#define CH_SPORT1_TX 4 -#define CH_SPI0 5 -#define CH_UART0_RX 6 -#define CH_UART0_TX 7 -#define CH_SPORT2_RX 8 -#define CH_SPORT2_TX 9 -#define CH_SPORT3_RX 10 -#define CH_SPORT3_TX 11 -#define CH_SPI1 14 -#define CH_SPI2 15 -#define CH_UART1_RX 16 -#define CH_UART1_TX 17 -#define CH_UART2_RX 18 -#define CH_UART2_TX 19 - -#define CH_MEM_STREAM0_DEST 20 -#define CH_MEM_STREAM0_SRC 21 -#define CH_MEM_STREAM1_DEST 22 -#define CH_MEM_STREAM1_SRC 23 -#define CH_MEM_STREAM2_DEST 24 -#define CH_MEM_STREAM2_SRC 25 -#define CH_MEM_STREAM3_DEST 26 -#define CH_MEM_STREAM3_SRC 27 - -#define MAX_DMA_CHANNELS 28 - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h deleted file mode 100644 index 3561c7d8935b..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/gpio.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2008-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 16 -#ifdef CONFIG_GPIOLIB -/* We only use the special logic with GPIOLIB devices */ -#define BFIN_SPECIAL_GPIO_BANKS 3 -#endif - -#define GPIO_PF0 0 /* PF */ -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 -#define GPIO_PC0 16 /* PC */ -#define GPIO_PC1 17 -#define GPIO_PC4 20 -#define GPIO_PC5 21 -#define GPIO_PC6 22 -#define GPIO_PC7 23 -#define GPIO_PC8 24 -#define GPIO_PC9 25 -#define GPIO_PD0 32 /* PD */ -#define GPIO_PD1 33 -#define GPIO_PD2 34 -#define GPIO_PD3 35 -#define GPIO_PD4 36 -#define GPIO_PD5 37 -#define GPIO_PD6 38 -#define GPIO_PD7 39 -#define GPIO_PD8 40 -#define GPIO_PD9 41 -#define GPIO_PD10 42 -#define GPIO_PD11 43 -#define GPIO_PD12 44 -#define GPIO_PD13 45 -#define GPIO_PE0 48 /* PE */ -#define GPIO_PE1 49 -#define GPIO_PE2 50 -#define GPIO_PE3 51 -#define GPIO_PE4 52 -#define GPIO_PE5 53 -#define GPIO_PE6 54 -#define GPIO_PE7 55 -#define GPIO_PE8 56 -#define GPIO_PE9 57 -#define GPIO_PE10 58 -#define GPIO_PE11 59 -#define GPIO_PE12 60 -#define GPIO_PE13 61 -#define GPIO_PE14 62 -#define GPIO_PE15 63 - -#define PORT_F GPIO_PF0 -#define PORT_C GPIO_PC0 -#define PORT_D GPIO_PD0 -#define PORT_E GPIO_PE0 - -#include -#include -#include -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h deleted file mode 100644 index 07ca069d37cd..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/irq.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BF538_IRQ_H_ -#define _BF538_IRQ_H_ - -#include - -#define NR_PERI_INTS (2 * 32) - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ -#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */ -#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */ -#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */ -#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */ -#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */ -#define IRQ_RTC BFIN_IRQ(7) /* RTC */ -#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */ -#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */ -#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */ -#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */ -#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */ -#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */ -#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */ -#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */ -#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */ -#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */ -#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */ -#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */ -#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */ -#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */ -#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */ -#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */ -#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */ -#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */ -#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */ -#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */ -#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */ -#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */ -#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */ -#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */ -#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */ -#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */ -#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */ -#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */ -#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */ -#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */ -#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */ -#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */ -#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */ -#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */ -#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */ -#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */ -#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */ -#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */ -#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */ -#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */ - -#define SYS_IRQS BFIN_IRQ(63) /* 70 */ - -#define IRQ_PF0 71 -#define IRQ_PF1 72 -#define IRQ_PF2 73 -#define IRQ_PF3 74 -#define IRQ_PF4 75 -#define IRQ_PF5 76 -#define IRQ_PF6 77 -#define IRQ_PF7 78 -#define IRQ_PF8 79 -#define IRQ_PF9 80 -#define IRQ_PF10 81 -#define IRQ_PF11 82 -#define IRQ_PF12 83 -#define IRQ_PF13 84 -#define IRQ_PF14 85 -#define IRQ_PF15 86 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define NR_MACH_IRQS (IRQ_PF15 + 1) - -/* IAR0 BIT FIELDS */ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA0_ERROR_POS 4 -#define IRQ_PPI_ERROR_POS 8 -#define IRQ_SPORT0_ERROR_POS 12 -#define IRQ_SPORT1_ERROR_POS 16 -#define IRQ_SPI0_ERROR_POS 20 -#define IRQ_UART0_ERROR_POS 24 -#define IRQ_RTC_POS 28 - -/* IAR1 BIT FIELDS */ -#define IRQ_PPI_POS 0 -#define IRQ_SPORT0_RX_POS 4 -#define IRQ_SPORT0_TX_POS 8 -#define IRQ_SPORT1_RX_POS 12 -#define IRQ_SPORT1_TX_POS 16 -#define IRQ_SPI0_POS 20 -#define IRQ_UART0_RX_POS 24 -#define IRQ_UART0_TX_POS 28 - -/* IAR2 BIT FIELDS */ -#define IRQ_TIMER0_POS 0 -#define IRQ_TIMER1_POS 4 -#define IRQ_TIMER2_POS 8 -#define IRQ_PORTF_INTA_POS 12 -#define IRQ_PORTF_INTB_POS 16 -#define IRQ_MEM0_DMA0_POS 20 -#define IRQ_MEM0_DMA1_POS 24 -#define IRQ_WATCH_POS 28 - -/* IAR3 BIT FIELDS */ -#define IRQ_DMA1_ERROR_POS 0 -#define IRQ_SPORT2_ERROR_POS 4 -#define IRQ_SPORT3_ERROR_POS 8 -#define IRQ_SPI1_ERROR_POS 16 -#define IRQ_SPI2_ERROR_POS 20 -#define IRQ_UART1_ERROR_POS 24 -#define IRQ_UART2_ERROR_POS 28 - -/* IAR4 BIT FIELDS */ -#define IRQ_CAN_ERROR_POS 0 -#define IRQ_SPORT2_RX_POS 4 -#define IRQ_SPORT2_TX_POS 8 -#define IRQ_SPORT3_RX_POS 12 -#define IRQ_SPORT3_TX_POS 16 -#define IRQ_SPI1_POS 28 - -/* IAR5 BIT FIELDS */ -#define IRQ_SPI2_POS 0 -#define IRQ_UART1_RX_POS 4 -#define IRQ_UART1_TX_POS 8 -#define IRQ_UART2_RX_POS 12 -#define IRQ_UART2_TX_POS 16 -#define IRQ_TWI0_POS 20 -#define IRQ_TWI1_POS 24 -#define IRQ_CAN_RX_POS 28 - -/* IAR6 BIT FIELDS */ -#define IRQ_CAN_TX_POS 0 -#define IRQ_MEM1_DMA0_POS 4 -#define IRQ_MEM1_DMA1_POS 8 - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h deleted file mode 100644 index aff00f453e9e..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/mem_map.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * BF538 memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x400 - -/* Level 1 Memory */ - -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#else -#define BFIN_ICACHESIZE (0*1024) -#endif - -/* Memory Map for ADSP-BF538/9 processors */ - -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#ifdef CONFIG_BFIN_ICACHE -#define L1_CODE_LENGTH (0x14000 - 0x4000) -#else -#define L1_CODE_LENGTH 0x14000 -#endif - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ - -#endif diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h deleted file mode 100644 index 94cca674d835..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h deleted file mode 100644 index b773c5fdbc72..000000000000 --- a/arch/blackfin/mach-bf538/include/mach/portmux.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define MAX_RESOURCES 64 - -#define P_TMR2 (P_DONTCARE) -#define P_TMR1 (P_DONTCARE) -#define P_TMR0 (P_DONTCARE) -#define P_TMRCLK (P_DONTCARE) -#define P_PPI0_CLK (P_DONTCARE) -#define P_PPI0_FS1 (P_DONTCARE) -#define P_PPI0_FS2 (P_DONTCARE) - -#define P_TWI0_SCL (P_DONTCARE) -#define P_TWI0_SDA (P_DONTCARE) -#define P_TWI1_SCL (P_DONTCARE) -#define P_TWI1_SDA (P_DONTCARE) - -#define P_SPORT1_TSCLK (P_DONTCARE) -#define P_SPORT1_RSCLK (P_DONTCARE) -#define P_SPORT0_TSCLK (P_DONTCARE) -#define P_SPORT0_RSCLK (P_DONTCARE) -#define P_SPORT1_DRSEC (P_DONTCARE) -#define P_SPORT1_RFS (P_DONTCARE) -#define P_SPORT1_DTPRI (P_DONTCARE) -#define P_SPORT1_DTSEC (P_DONTCARE) -#define P_SPORT1_TFS (P_DONTCARE) -#define P_SPORT1_DRPRI (P_DONTCARE) -#define P_SPORT0_DRSEC (P_DONTCARE) -#define P_SPORT0_RFS (P_DONTCARE) -#define P_SPORT0_DTPRI (P_DONTCARE) -#define P_SPORT0_DTSEC (P_DONTCARE) -#define P_SPORT0_TFS (P_DONTCARE) -#define P_SPORT0_DRPRI (P_DONTCARE) - -#define P_UART0_RX (P_DONTCARE) -#define P_UART0_TX (P_DONTCARE) - -#define P_SPI0_MOSI (P_DONTCARE) -#define P_SPI0_MISO (P_DONTCARE) -#define P_SPI0_SCK (P_DONTCARE) - -#define P_PPI0_D0 (P_DONTCARE) -#define P_PPI0_D1 (P_DONTCARE) -#define P_PPI0_D2 (P_DONTCARE) -#define P_PPI0_D3 (P_DONTCARE) - -#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0)) -#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1)) - -#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0)) -#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1)) -#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2)) -#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3)) -#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4)) -#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5)) -#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6)) -#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7)) -#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8)) -#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9)) -#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10)) -#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11)) -#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12)) -#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13)) - -#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0)) -#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1)) -#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2)) -#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3)) -#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4)) -#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5)) -#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6)) -#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7)) -#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8)) -#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9)) -#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10)) -#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11)) -#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12)) -#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13)) -#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14)) -#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15)) - -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) - -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) -#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c deleted file mode 100644 index 1fa793ced347..000000000000 --- a/arch/blackfin/mach-bf538/ints-priority.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -void __init program_IAR(void) -{ - - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | - ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) | - ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) | - ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | - ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) | - ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) | - ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) | - ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS)); - - bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) | - ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | - ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | - ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | - ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | - ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) | - ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | - ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); - - bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | - ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | - ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | - ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) | - ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) | - ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) | - ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) | - ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS)); - - bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | - ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) | - ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) | - ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) | - ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) | - ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) | - ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS)); - - bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) | - ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) | - ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) | - ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) | - ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) | - ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS)); - - bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) | - ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | - ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | - ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) | - ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) | - ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) | - ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) | - ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS)); - - bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) | - ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) | - ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS)); - - SSYNC(); -} diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig deleted file mode 100644 index 71c2a765af1d..000000000000 --- a/arch/blackfin/mach-bf548/Kconfig +++ /dev/null @@ -1,383 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config BF542 - def_bool y - depends on BF542_std || BF542M -config BF544 - def_bool y - depends on BF544_std || BF544M -config BF547 - def_bool y - depends on BF547_std || BF547M -config BF548 - def_bool y - depends on BF548_std || BF548M -config BF549 - def_bool y - depends on BF549_std || BF549M - -config BF54xM - def_bool y - depends on (BF542M || BF544M || BF547M || BF548M || BF549M) - -config BF54x - def_bool y - depends on (BF542 || BF544 || BF547 || BF548 || BF549) - -if (BF54x) - -source "arch/blackfin/mach-bf548/boards/Kconfig" - -menu "BF548 Specific Configuration" - -config DEB_DMA_URGENT - bool "DMA has priority over core for ext. accesses" - depends on BF54x - default y - help - Treat any DEB1, DEB2 and DEB3 request as Urgent - -config BF548_ATAPI_ALTERNATIVE_PORT - bool "BF548 ATAPI alternative port via GPIO" - help - BF548 ATAPI data and address PINs can be routed through - async address or GPIO port F and G. Select y to route it - to GPIO. - -choice - prompt "UART2 DMA channel selection" - depends on SERIAL_BFIN_UART2 - default UART2_DMA_RX_ON_DMA18 - help - UART2 DMA channel selection - RX -> DMA18 - TX -> DMA19 - or - RX -> DMA13 - TX -> DMA14 - -config UART2_DMA_RX_ON_DMA18 - bool "UART2 DMA RX -> DMA18 TX -> DMA19" - help - UART2 DMA channel assignment - RX -> DMA18 - TX -> DMA19 - use SPORT2 default DMA channel - -config UART2_DMA_RX_ON_DMA13 - bool "UART2 DMA RX -> DMA13 TX -> DMA14" - help - UART2 DMA channel assignment - RX -> DMA13 - TX -> DMA14 - use EPPI1 EPPI2 default DMA channel -endchoice - -choice - prompt "UART3 DMA channel selection" - depends on SERIAL_BFIN_UART3 - default UART3_DMA_RX_ON_DMA20 - help - UART3 DMA channel selection - RX -> DMA20 - TX -> DMA21 - or - RX -> DMA15 - TX -> DMA16 - -config UART3_DMA_RX_ON_DMA20 - bool "UART3 DMA RX -> DMA20 TX -> DMA21" - help - UART3 DMA channel assignment - RX -> DMA20 - TX -> DMA21 - use SPORT3 default DMA channel - -config UART3_DMA_RX_ON_DMA15 - bool "UART3 DMA RX -> DMA15 TX -> DMA16" - help - UART3 DMA channel assignment - RX -> DMA15 - TX -> DMA16 - use PIXC default DMA channel - -endchoice - -comment "Interrupt Priority Assignment" -menu "Priority" - -config IRQ_PLL_WAKEUP - int "IRQ_PLL_WAKEUP" - default 7 -config IRQ_DMAC0_ERR - int "IRQ_DMAC0_ERR" - default 7 -config IRQ_EPPI0_ERR - int "IRQ_EPPI0_ERR" - default 7 -config IRQ_SPORT0_ERR - int "IRQ_SPORT0_ERR" - default 7 -config IRQ_SPORT1_ERR - int "IRQ_SPORT1_ERR" - default 7 -config IRQ_SPI0_ERR - int "IRQ_SPI0_ERR" - default 7 -config IRQ_UART0_ERR - int "IRQ_UART0_ERR" - default 7 -config IRQ_RTC - int "IRQ_RTC" - default 8 -config IRQ_EPPI0 - int "IRQ_EPPI0" - default 8 -config IRQ_SPORT0_RX - int "IRQ_SPORT0_RX" - default 9 -config IRQ_SPORT0_TX - int "IRQ_SPORT0_TX" - default 9 -config IRQ_SPORT1_RX - int "IRQ_SPORT1_RX" - default 9 -config IRQ_SPORT1_TX - int "IRQ_SPORT1_TX" - default 9 -config IRQ_SPI0 - int "IRQ_SPI0" - default 10 -config IRQ_UART0_RX - int "IRQ_UART0_RX" - default 10 -config IRQ_UART0_TX - int "IRQ_UART0_TX" - default 10 -config IRQ_TIMER8 - int "IRQ_TIMER8" - default 11 -config IRQ_TIMER9 - int "IRQ_TIMER9" - default 11 -config IRQ_TIMER10 - int "IRQ_TIMER10" - default 11 -config IRQ_PINT0 - int "IRQ_PINT0" - default 12 -config IRQ_PINT1 - int "IRQ_PINT0" - default 12 -config IRQ_MDMAS0 - int "IRQ_MDMAS0" - default 13 -config IRQ_MDMAS1 - int "IRQ_DMDMAS1" - default 13 -config IRQ_WATCHDOG - int "IRQ_WATCHDOG" - default 13 -config IRQ_DMAC1_ERR - int "IRQ_DMAC1_ERR" - default 7 -config IRQ_SPORT2_ERR - int "IRQ_SPORT2_ERR" - default 7 -config IRQ_SPORT3_ERR - int "IRQ_SPORT3_ERR" - default 7 -config IRQ_MXVR_DATA - int "IRQ MXVR Data" - default 7 -config IRQ_SPI1_ERR - int "IRQ_SPI1_ERR" - default 7 -config IRQ_SPI2_ERR - int "IRQ_SPI2_ERR" - default 7 -config IRQ_UART1_ERR - int "IRQ_UART1_ERR" - default 7 -config IRQ_UART2_ERR - int "IRQ_UART2_ERR" - default 7 -config IRQ_CAN0_ERR - int "IRQ_CAN0_ERR" - default 7 -config IRQ_SPORT2_RX - int "IRQ_SPORT2_RX" - default 9 -config IRQ_SPORT2_TX - int "IRQ_SPORT2_TX" - default 9 -config IRQ_SPORT3_RX - int "IRQ_SPORT3_RX" - default 9 -config IRQ_SPORT3_TX - int "IRQ_SPORT3_TX" - default 9 -config IRQ_EPPI1 - int "IRQ_EPPI1" - default 9 -config IRQ_EPPI2 - int "IRQ_EPPI2" - default 9 -config IRQ_SPI1 - int "IRQ_SPI1" - default 10 -config IRQ_SPI2 - int "IRQ_SPI2" - default 10 -config IRQ_UART1_RX - int "IRQ_UART1_RX" - default 10 -config IRQ_UART1_TX - int "IRQ_UART1_TX" - default 10 -config IRQ_ATAPI_RX - int "IRQ_ATAPI_RX" - default 10 -config IRQ_ATAPI_TX - int "IRQ_ATAPI_TX" - default 10 -config IRQ_TWI0 - int "IRQ_TWI0" - default 11 -config IRQ_TWI1 - int "IRQ_TWI1" - default 11 -config IRQ_CAN0_RX - int "IRQ_CAN_RX" - default 11 -config IRQ_CAN0_TX - int "IRQ_CAN_TX" - default 11 -config IRQ_MDMAS2 - int "IRQ_MDMAS2" - default 13 -config IRQ_MDMAS3 - int "IRQ_DMMAS3" - default 13 -config IRQ_MXVR_ERR - int "IRQ_MXVR_ERR" - default 11 -config IRQ_MXVR_MSG - int "IRQ_MXVR_MSG" - default 11 -config IRQ_MXVR_PKT - int "IRQ_MXVR_PKT" - default 11 -config IRQ_EPPI1_ERR - int "IRQ_EPPI1_ERR" - default 7 -config IRQ_EPPI2_ERR - int "IRQ_EPPI2_ERR" - default 7 -config IRQ_UART3_ERR - int "IRQ_UART3_ERR" - default 7 -config IRQ_HOST_ERR - int "IRQ_HOST_ERR" - default 7 -config IRQ_PIXC_ERR - int "IRQ_PIXC_ERR" - default 7 -config IRQ_NFC_ERR - int "IRQ_NFC_ERR" - default 7 -config IRQ_ATAPI_ERR - int "IRQ_ATAPI_ERR" - default 7 -config IRQ_CAN1_ERR - int "IRQ_CAN1_ERR" - default 7 -config IRQ_HS_DMA_ERR - int "IRQ Handshake DMA Status" - default 7 -config IRQ_PIXC_IN0 - int "IRQ PIXC IN0" - default 8 -config IRQ_PIXC_IN1 - int "IRQ PIXC IN1" - default 8 -config IRQ_PIXC_OUT - int "IRQ PIXC OUT" - default 8 -config IRQ_SDH - int "IRQ SDH" - default 8 -config IRQ_CNT - int "IRQ CNT" - default 8 -config IRQ_KEY - int "IRQ KEY" - default 8 -config IRQ_CAN1_RX - int "IRQ CAN1 RX" - default 11 -config IRQ_CAN1_TX - int "IRQ_CAN1_TX" - default 11 -config IRQ_SDH_MASK0 - int "IRQ_SDH_MASK0" - default 11 -config IRQ_SDH_MASK1 - int "IRQ_SDH_MASK1" - default 11 -config IRQ_USB_INT0 - int "IRQ USB INT0" - default 11 -config IRQ_USB_INT1 - int "IRQ USB INT1" - default 11 -config IRQ_USB_INT2 - int "IRQ USB INT2" - default 11 -config IRQ_USB_DMA - int "IRQ USB DMA" - default 11 -config IRQ_OTPSEC - int "IRQ OPTSEC" - default 11 -config IRQ_TIMER0 - int "IRQ_TIMER0" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config IRQ_TIMER1 - int "IRQ_TIMER1" - default 11 -config IRQ_TIMER2 - int "IRQ_TIMER2" - default 11 -config IRQ_TIMER3 - int "IRQ_TIMER3" - default 11 -config IRQ_TIMER4 - int "IRQ_TIMER4" - default 11 -config IRQ_TIMER5 - int "IRQ_TIMER5" - default 11 -config IRQ_TIMER6 - int "IRQ_TIMER6" - default 11 -config IRQ_TIMER7 - int "IRQ_TIMER7" - default 11 -config IRQ_PINT2 - int "IRQ_PIN2" - default 11 -config IRQ_PINT3 - int "IRQ_PIN3" - default 11 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile deleted file mode 100644 index 56994b675f9c..000000000000 --- a/arch/blackfin/mach-bf548/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf537/Makefile -# - -obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf548/boards/Kconfig b/arch/blackfin/mach-bf548/boards/Kconfig deleted file mode 100644 index e8ce579ae8f0..000000000000 --- a/arch/blackfin/mach-bf548/boards/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN548_EZKIT - help - Select your board! - -config BFIN548_EZKIT - bool "BF548-EZKIT" - help - BFIN548-EZKIT board support. - -config BFIN548_BLUETECHNIX_CM - bool "Bluetechnix CM-BF548" - depends on (BF548) - help - CM-BF548 support for DEV-Board. - -endchoice diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile deleted file mode 100644 index 319ef54c4221..000000000000 --- a/arch/blackfin/mach-bf548/boards/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# arch/blackfin/mach-bf548/boards/Makefile -# - -obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o -obj-$(CONFIG_BFIN548_BLUETECHNIX_CM) += cm_bf548.o diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c deleted file mode 100644 index 120c9941c242..000000000000 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ /dev/null @@ -1,1268 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix CM-BF548"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_FB_BF54X_LQ043) - -#include - -static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { - .width = 480, - .height = 272, - .xres = {480, 480, 480}, - .yres = {272, 272, 272}, - .bpp = {24, 24, 24}, - .disp = GPIO_PE3, -}; - -static struct resource bf54x_lq043_resources[] = { - { - .start = IRQ_EPPI0_ERR, - .end = IRQ_EPPI0_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf54x_lq043_device = { - .name = "bf54x-lq043", - .id = -1, - .num_resources = ARRAY_SIZE(bf54x_lq043_resources), - .resource = bf54x_lq043_resources, - .dev = { - .platform_data = &bf54x_lq043_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_BFIN) -static unsigned int bf548_keymap[] = { - KEYVAL(0, 0, KEY_ENTER), - KEYVAL(0, 1, KEY_HELP), - KEYVAL(0, 2, KEY_0), - KEYVAL(0, 3, KEY_BACKSPACE), - KEYVAL(1, 0, KEY_TAB), - KEYVAL(1, 1, KEY_9), - KEYVAL(1, 2, KEY_8), - KEYVAL(1, 3, KEY_7), - KEYVAL(2, 0, KEY_DOWN), - KEYVAL(2, 1, KEY_6), - KEYVAL(2, 2, KEY_5), - KEYVAL(2, 3, KEY_4), - KEYVAL(3, 0, KEY_UP), - KEYVAL(3, 1, KEY_3), - KEYVAL(3, 2, KEY_2), - KEYVAL(3, 3, KEY_1), -}; - -static struct bfin_kpad_platform_data bf54x_kpad_data = { - .rows = 4, - .cols = 4, - .keymap = bf548_keymap, - .keymapsize = ARRAY_SIZE(bf548_keymap), - .repeat = 0, - .debounce_time = 5000, /* ns (5ms) */ - .coldrive_time = 1000, /* ns (1ms) */ - .keyup_test_interval = 50, /* ms (50ms) */ -}; - -static struct resource bf54x_kpad_resources[] = { - { - .start = IRQ_KEY, - .end = IRQ_KEY, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf54x_kpad_device = { - .name = "bf54x-keys", - .id = -1, - .num_resources = ARRAY_SIZE(bf54x_kpad_resources), - .resource = bf54x_kpad_resources, - .dev = { - .platform_data = &bf54x_kpad_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_DLL, - .end = UART0_RBR+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_DLL, - .end = UART1_RBR+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin -- 0 means not supported */ - .start = GPIO_PE10, - .end = GPIO_PE10, - .flags = IORESOURCE_IO, - }, - { /* RTS pin -- 0 means not supported */ - .start = GPIO_PE9, - .end = GPIO_PE9, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, -#ifdef CONFIG_BFIN_UART1_CTSRTS - P_UART1_RTS, P_UART1_CTS, -#endif - 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 -static struct resource bfin_uart2_resources[] = { - { - .start = UART2_DLL, - .end = UART2_RBR+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART2_TX, - .end = IRQ_UART2_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART2_RX, - .end = IRQ_UART2_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART2_ERROR, - .end = IRQ_UART2_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART2_TX, - .end = CH_UART2_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART2_RX, - .end = CH_UART2_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart2_peripherals[] = { - P_UART2_TX, P_UART2_RX, 0 -}; - -static struct platform_device bfin_uart2_device = { - .name = "bfin-uart", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_uart2_resources), - .resource = bfin_uart2_resources, - .dev = { - .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART3 -static struct resource bfin_uart3_resources[] = { - { - .start = UART3_DLL, - .end = UART3_RBR+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART3_TX, - .end = IRQ_UART3_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART3_RX, - .end = IRQ_UART3_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART3_ERROR, - .end = IRQ_UART3_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART3_TX, - .end = CH_UART3_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART3_RX, - .end = CH_UART3_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART3_CTSRTS - { /* CTS pin -- 0 means not supported */ - .start = GPIO_PB3, - .end = GPIO_PB3, - .flags = IORESOURCE_IO, - }, - { /* RTS pin -- 0 means not supported */ - .start = GPIO_PB2, - .end = GPIO_PB2, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart3_peripherals[] = { - P_UART3_TX, P_UART3_RX, -#ifdef CONFIG_BFIN_UART3_CTSRTS - P_UART3_RTS, P_UART3_CTS, -#endif - 0 -}; - -static struct platform_device bfin_uart3_device = { - .name = "bfin-uart", - .id = 3, - .num_resources = ARRAY_SIZE(bfin_uart3_resources), - .resource = bfin_uart3_resources, - .dev = { - .platform_data = &bfin_uart3_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR2 -static struct resource bfin_sir2_resources[] = { - { - .start = 0xFFC02100, - .end = 0xFFC021FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART2_RX, - .end = IRQ_UART2_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART2_RX, - .end = CH_UART2_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir2_device = { - .name = "bfin_sir", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_sir2_resources), - .resource = bfin_sir2_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR3 -static struct resource bfin_sir3_resources[] = { - { - .start = 0xFFC03100, - .end = 0xFFC031FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART3_RX, - .end = IRQ_UART3_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART3_RX, - .end = CH_UART3_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir3_device = { - .name = "bfin_sir", - .id = 3, - .num_resources = ARRAY_SIZE(bfin_sir3_resources), - .resource = bfin_sir3_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) -#include - -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x24000000, - .end = 0x24000000 + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PE6, - .end = IRQ_PE6, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_16BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xFFC03C00, - .end = 0xFFC040FF, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_INT0, - .end = IRQ_USB_INT0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "mc" - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "dma" - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 0, - .dyn_fifo = 0, - .soft_con = 1, - .dma = 1, - .num_eps = 8, - .dma_channels = 8, - .gpio_vrsel = GPIO_PH6, - /* Some custom boards need to be active low, just set it to "0" - * if it is the case. - */ - .gpio_vrsel_active = 1, - .clkin = 24, /* musb CLKIN in MHZ */ -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_OTG) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC_HCD) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART -static struct resource bfin_sport2_uart_resources[] = { - { - .start = SPORT2_TCR1, - .end = SPORT2_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT2_RX, - .end = IRQ_SPORT2_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT2_ERROR, - .end = IRQ_SPORT2_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport2_peripherals[] = { - P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, - P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 -}; - -static struct platform_device bfin_sport2_uart_device = { - .name = "bfin-sport-uart", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), - .resource = bfin_sport2_uart_resources, - .dev = { - .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART -static struct resource bfin_sport3_uart_resources[] = { - { - .start = SPORT3_TCR1, - .end = SPORT3_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT3_RX, - .end = IRQ_SPORT3_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT3_ERROR, - .end = IRQ_SPORT3_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport3_peripherals[] = { - P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, - P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 -}; - -static struct platform_device bfin_sport3_uart_device = { - .name = "bfin-sport-uart", - .id = 3, - .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources), - .resource = bfin_sport3_uart_resources, - .dev = { - .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_PATA_BF54X) -static struct resource bfin_atapi_resources[] = { - { - .start = 0xFFC03800, - .end = 0xFFC0386F, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ATAPI_ERR, - .end = IRQ_ATAPI_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_atapi_device = { - .name = "pata-bf54x", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_atapi_resources), - .resource = bfin_atapi_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) -static struct mtd_partition partition_info[] = { - { - .name = "linux kernel(nand)", - .offset = 0, - .size = 4 * 1024 * 1024, - }, - { - .name = "file system(nand)", - .offset = 4 * 1024 * 1024, - .size = (256 - 4) * 1024 * 1024, - }, -}; - -static struct bf5xx_nand_platform bf5xx_nand_platform = { - .data_width = NFC_NWIDTH_8, - .partitions = partition_info, - .nr_partitions = ARRAY_SIZE(partition_info), - .rd_dly = 3, - .wr_dly = 3, -}; - -static struct resource bf5xx_nand_resources[] = { - { - .start = 0xFFC03B00, - .end = 0xFFC03B4F, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_NFC, - .end = CH_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf5xx_nand_device = { - .name = "bf5xx-nand", - .id = 0, - .num_resources = ARRAY_SIZE(bf5xx_nand_resources), - .resource = bf5xx_nand_resources, - .dev = { - .platform_data = &bf5xx_nand_platform, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) -static struct bfin_sd_host bfin_sdh_data = { - .dma_chan = CH_SDH, - .irq_int0 = IRQ_SDH_MASK0, - .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, -}; - -static struct platform_device bf54x_sdh_device = { - .name = "bfin-sdh", - .id = 0, - .dev = { - .platform_data = &bfin_sdh_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) -static unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN0_RX, - .end = IRQ_CAN0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_TX, - .end = IRQ_CAN0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_ERROR, - .end = IRQ_CAN0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition para_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data para_flash_data = { - .width = 2, - .parts = para_partitions, - .nr_parts = ARRAY_SIZE(para_partitions), -}; - -static struct resource para_flash_resource = { - .start = 0x20000000, - .end = 0x207fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device para_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = ¶_flash_data, - }, - .num_resources = 1, - .resource = ¶_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ -#if IS_ENABLED(CONFIG_MTD_M25P80) -/* SPI flash chip (m25p16) */ -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x1c0000, - .offset = 0x40000 - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -static struct spi_board_info bf54x_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* SPI_SSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -{ - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PJ11, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, -}, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI0, - .end = CH_SPI0, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI (1) */ -static struct resource bfin_spi1_resource[] = { - [0] = { - .start = SPI1_REGBASE, - .end = SPI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI1, - .end = CH_SPI1, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bf54x_spi_master_info0 = { - .num_chipselect = 4, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bf54x_spi_master0 = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bf54x_spi_master_info0, /* Passed to driver */ - }, -}; - -static struct bfin5xx_spi_master bf54x_spi_master_info1 = { - .num_chipselect = 4, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, -}; - -static struct platform_device bf54x_spi_master1 = { - .name = "bfin-spi", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi1_resource), - .resource = bfin_spi1_resource, - .dev = { - .platform_data = &bf54x_spi_master_info1, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI0, - .end = IRQ_TWI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi0_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; - -#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ -static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; - -static struct resource bfin_twi1_resource[] = { - [0] = { - .start = TWI1_REGBASE, - .end = TWI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI1, - .end = IRQ_TWI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi1_device = { - .name = "i2c-bfin-twi", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_twi1_resource), - .resource = bfin_twi1_resource, - .dev = { - .platform_data = &bfin_twi1_pins, - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ -/* - * Internal VLEV BF54XSBBC1533 - ****temporarily using these values until data sheet is updated - */ - VRPAIR(VLEV_085, 150000000), - VRPAIR(VLEV_090, 250000000), - VRPAIR(VLEV_110, 276000000), - VRPAIR(VLEV_115, 301000000), - VRPAIR(VLEV_120, 525000000), - VRPAIR(VLEV_125, 550000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cm_bf548_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 - &bfin_uart2_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART3 - &bfin_uart3_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#ifdef CONFIG_BFIN_SIR2 - &bfin_sir2_device, -#endif -#ifdef CONFIG_BFIN_SIR3 - &bfin_sir3_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_FB_BF54X_LQ043) - &bf54x_lq043_device, -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) - &smsc911x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART - &bfin_sport2_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART - &bfin_sport3_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_PATA_BF54X) - &bfin_atapi_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) - &bf5xx_nand_device, -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - &bf54x_sdh_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bf54x_spi_master0, - &bf54x_spi_master1, -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_BFIN) - &bf54x_kpad_device, -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi0_device, -#if !defined(CONFIG_BF542) - &i2c_bfin_twi1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - ¶_flash_device, -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) - &bfin_can_device, -#endif - -}; - -static int __init cm_bf548_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices)); - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bf54x_spi_board_info, - ARRAY_SIZE(bf54x_spi_board_info)); -#endif - - return 0; -} - -arch_initcall(cm_bf548_init); - -static struct platform_device *cm_bf548_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 - &bfin_uart2_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART3 - &bfin_uart3_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART - &bfin_sport2_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART - &bfin_sport3_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cm_bf548_early_devices, - ARRAY_SIZE(cm_bf548_early_devices)); -} diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c deleted file mode 100644 index 3cdd4835a9f7..000000000000 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ /dev/null @@ -1,2199 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF548-EZKIT"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x2C0C0000, - .end = 0x2C0C0000 + 0xfffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PG7, - .end = IRQ_PG7, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_FB_BF54X_LQ043) - -#include - -static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { - .width = 95, - .height = 54, - .xres = {480, 480, 480}, - .yres = {272, 272, 272}, - .bpp = {24, 24, 24}, - .disp = GPIO_PE3, -}; - -static struct resource bf54x_lq043_resources[] = { - { - .start = IRQ_EPPI0_ERR, - .end = IRQ_EPPI0_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf54x_lq043_device = { - .name = "bf54x-lq043", - .id = -1, - .num_resources = ARRAY_SIZE(bf54x_lq043_resources), - .resource = bf54x_lq043_resources, - .dev = { - .platform_data = &bf54x_lq043_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_BFIN) -static const unsigned int bf548_keymap[] = { - KEYVAL(0, 0, KEY_ENTER), - KEYVAL(0, 1, KEY_HELP), - KEYVAL(0, 2, KEY_0), - KEYVAL(0, 3, KEY_BACKSPACE), - KEYVAL(1, 0, KEY_TAB), - KEYVAL(1, 1, KEY_9), - KEYVAL(1, 2, KEY_8), - KEYVAL(1, 3, KEY_7), - KEYVAL(2, 0, KEY_DOWN), - KEYVAL(2, 1, KEY_6), - KEYVAL(2, 2, KEY_5), - KEYVAL(2, 3, KEY_4), - KEYVAL(3, 0, KEY_UP), - KEYVAL(3, 1, KEY_3), - KEYVAL(3, 2, KEY_2), - KEYVAL(3, 3, KEY_1), -}; - -static struct bfin_kpad_platform_data bf54x_kpad_data = { - .rows = 4, - .cols = 4, - .keymap = bf548_keymap, - .keymapsize = ARRAY_SIZE(bf548_keymap), - .repeat = 0, - .debounce_time = 5000, /* ns (5ms) */ - .coldrive_time = 1000, /* ns (1ms) */ - .keyup_test_interval = 50, /* ms (50ms) */ -}; - -static struct resource bf54x_kpad_resources[] = { - { - .start = IRQ_KEY, - .end = IRQ_KEY, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf54x_kpad_device = { - .name = "bf54x-keys", - .id = -1, - .num_resources = ARRAY_SIZE(bf54x_kpad_resources), - .resource = bf54x_kpad_resources, - .dev = { - .platform_data = &bf54x_kpad_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) -#include - -static struct bfin_rotary_platform_data bfin_rotary_data = { - /*.rotary_up_key = KEY_UP,*/ - /*.rotary_down_key = KEY_DOWN,*/ - .rotary_rel_code = REL_WHEEL, - .rotary_button_key = KEY_ENTER, - .debounce = 10, /* 0..17 */ - .mode = ROT_QUAD_ENC | ROT_DEBE, - .pm_wakeup = 1, -}; - -static struct resource bfin_rotary_resources[] = { - { - .start = CNT_CONFIG, - .end = CNT_CONFIG + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CNT, - .end = IRQ_CNT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_rotary_device = { - .name = "bfin-rotary", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_rotary_resources), - .resource = bfin_rotary_resources, - .dev = { - .platform_data = &bfin_rotary_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_ADXL34X) -#include -static const struct adxl34x_platform_data adxl34x_info = { - .x_axis_offset = 0, - .y_axis_offset = 0, - .z_axis_offset = 0, - .tap_threshold = 0x31, - .tap_duration = 0x10, - .tap_latency = 0x60, - .tap_window = 0xF0, - .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, - .act_axis_control = 0xFF, - .activity_threshold = 5, - .inactivity_threshold = 3, - .inactivity_time = 4, - .free_fall_threshold = 0x7, - .free_fall_time = 0x20, - .data_rate = 0x8, - .data_range = ADXL_FULL_RES, - - .ev_type = EV_ABS, - .ev_code_x = ABS_X, /* EV_REL */ - .ev_code_y = ABS_Y, /* EV_REL */ - .ev_code_z = ABS_Z, /* EV_REL */ - - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ - -/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ -/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ - .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, - .fifo_mode = ADXL_FIFO_STREAM, - .orientation_enable = ADXL_EN_ORIENTATION_3D, - .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, - .divisor_length = ADXL_LP_FILTER_DIVISOR_16, - /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ - .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_DLL, - .end = UART0_RBR+2, - .flags = IORESOURCE_MEM, - }, -#ifdef CONFIG_EARLY_PRINTK - { - .start = PORTE_FER, - .end = PORTE_FER+2, - .flags = IORESOURCE_REG, - }, -#endif - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_DLL, - .end = UART1_RBR+2, - .flags = IORESOURCE_MEM, - }, -#ifdef CONFIG_EARLY_PRINTK - { - .start = PORTH_FER, - .end = PORTH_FER+2, - .flags = IORESOURCE_REG, - }, -#endif - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_ERROR, - .end = IRQ_UART1_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin -- 0 means not supported */ - .start = GPIO_PE10, - .end = GPIO_PE10, - .flags = IORESOURCE_IO, - }, - { /* RTS pin -- 0 means not supported */ - .start = GPIO_PE9, - .end = GPIO_PE9, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, -#ifdef CONFIG_BFIN_UART1_CTSRTS - P_UART1_RTS, P_UART1_CTS, -#endif - 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 -static struct resource bfin_uart2_resources[] = { - { - .start = UART2_DLL, - .end = UART2_RBR+2, - .flags = IORESOURCE_MEM, - }, -#ifdef CONFIG_EARLY_PRINTK - { - .start = PORTB_FER, - .end = PORTB_FER+2, - .flags = IORESOURCE_REG, - }, -#endif - { - .start = IRQ_UART2_TX, - .end = IRQ_UART2_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART2_RX, - .end = IRQ_UART2_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART2_ERROR, - .end = IRQ_UART2_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART2_TX, - .end = CH_UART2_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART2_RX, - .end = CH_UART2_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart2_peripherals[] = { - P_UART2_TX, P_UART2_RX, 0 -}; - -static struct platform_device bfin_uart2_device = { - .name = "bfin-uart", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_uart2_resources), - .resource = bfin_uart2_resources, - .dev = { - .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART3 -static struct resource bfin_uart3_resources[] = { - { - .start = UART3_DLL, - .end = UART3_RBR+2, - .flags = IORESOURCE_MEM, - }, -#ifdef CONFIG_EARLY_PRINTK - { - .start = PORTB_FER, - .end = PORTB_FER+2, - .flags = IORESOURCE_REG, - }, -#endif - { - .start = IRQ_UART3_TX, - .end = IRQ_UART3_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART3_RX, - .end = IRQ_UART3_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART3_ERROR, - .end = IRQ_UART3_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART3_TX, - .end = CH_UART3_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART3_RX, - .end = CH_UART3_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART3_CTSRTS - { /* CTS pin -- 0 means not supported */ - .start = GPIO_PB3, - .end = GPIO_PB3, - .flags = IORESOURCE_IO, - }, - { /* RTS pin -- 0 means not supported */ - .start = GPIO_PB2, - .end = GPIO_PB2, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart3_peripherals[] = { - P_UART3_TX, P_UART3_RX, -#ifdef CONFIG_BFIN_UART3_CTSRTS - P_UART3_RTS, P_UART3_CTS, -#endif - 0 -}; - -static struct platform_device bfin_uart3_device = { - .name = "bfin-uart", - .id = 3, - .num_resources = ARRAY_SIZE(bfin_uart3_resources), - .resource = bfin_uart3_resources, - .dev = { - .platform_data = &bfin_uart3_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR2 -static struct resource bfin_sir2_resources[] = { - { - .start = 0xFFC02100, - .end = 0xFFC021FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART2_RX, - .end = IRQ_UART2_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART2_RX, - .end = CH_UART2_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir2_device = { - .name = "bfin_sir", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_sir2_resources), - .resource = bfin_sir2_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR3 -static struct resource bfin_sir3_resources[] = { - { - .start = 0xFFC03100, - .end = 0xFFC031FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART3_RX, - .end = IRQ_UART3_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART3_RX, - .end = CH_UART3_RX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir3_device = { - .name = "bfin_sir", - .id = 3, - .num_resources = ARRAY_SIZE(bfin_sir3_resources), - .resource = bfin_sir3_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) -#include - -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x24000000, - .end = 0x24000000 + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PE8, - .end = IRQ_PE8, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_32BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xFFC03C00, - .end = 0xFFC040FF, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_INT0, - .end = IRQ_USB_INT0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "mc" - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "dma" - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 0, - .dyn_fifo = 0, - .soft_con = 1, - .dma = 1, - .num_eps = 8, - .dma_channels = 8, - .gpio_vrsel = GPIO_PE7, - /* Some custom boards need to be active low, just set it to "0" - * if it is the case. - */ - .gpio_vrsel_active = 1, - .clkin = 24, /* musb CLKIN in MHZ */ -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART -static struct resource bfin_sport2_uart_resources[] = { - { - .start = SPORT2_TCR1, - .end = SPORT2_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT2_RX, - .end = IRQ_SPORT2_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT2_ERROR, - .end = IRQ_SPORT2_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport2_peripherals[] = { - P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, - P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 -}; - -static struct platform_device bfin_sport2_uart_device = { - .name = "bfin-sport-uart", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), - .resource = bfin_sport2_uart_resources, - .dev = { - .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART -static struct resource bfin_sport3_uart_resources[] = { - { - .start = SPORT3_TCR1, - .end = SPORT3_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT3_RX, - .end = IRQ_SPORT3_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT3_ERROR, - .end = IRQ_SPORT3_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport3_peripherals[] = { - P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, - P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 -}; - -static struct platform_device bfin_sport3_uart_device = { - .name = "bfin-sport-uart", - .id = 3, - .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources), - .resource = bfin_sport3_uart_resources, - .dev = { - .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) - -static unsigned short bfin_can0_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can0_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN0_RX, - .end = IRQ_CAN0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_TX, - .end = IRQ_CAN0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_ERROR, - .end = IRQ_CAN0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can0_device = { - .name = "bfin_can", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_can0_resources), - .resource = bfin_can0_resources, - .dev = { - .platform_data = &bfin_can0_peripherals, /* Passed to driver */ - }, -}; - -static unsigned short bfin_can1_peripherals[] = { - P_CAN1_RX, P_CAN1_TX, 0 -}; - -static struct resource bfin_can1_resources[] = { - { - .start = 0xFFC03200, - .end = 0xFFC037FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN1_RX, - .end = IRQ_CAN1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN1_TX, - .end = IRQ_CAN1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN1_ERROR, - .end = IRQ_CAN1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can1_device = { - .name = "bfin_can", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_can1_resources), - .resource = bfin_can1_resources, - .dev = { - .platform_data = &bfin_can1_peripherals, /* Passed to driver */ - }, -}; - -#endif - -#if IS_ENABLED(CONFIG_PATA_BF54X) -static struct resource bfin_atapi_resources[] = { - { - .start = 0xFFC03800, - .end = 0xFFC0386F, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ATAPI_ERR, - .end = IRQ_ATAPI_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_atapi_device = { - .name = "pata-bf54x", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_atapi_resources), - .resource = bfin_atapi_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) -static struct mtd_partition partition_info[] = { - { - .name = "bootloader(nand)", - .offset = 0, - .size = 0x80000, - }, { - .name = "linux kernel(nand)", - .offset = MTDPART_OFS_APPEND, - .size = 4 * 1024 * 1024, - }, - { - .name = "file system(nand)", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct bf5xx_nand_platform bf5xx_nand_platform = { - .data_width = NFC_NWIDTH_8, - .partitions = partition_info, - .nr_partitions = ARRAY_SIZE(partition_info), - .rd_dly = 3, - .wr_dly = 3, -}; - -static struct resource bf5xx_nand_resources[] = { - { - .start = 0xFFC03B00, - .end = 0xFFC03B4F, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_NFC, - .end = CH_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bf5xx_nand_device = { - .name = "bf5xx-nand", - .id = 0, - .num_resources = ARRAY_SIZE(bf5xx_nand_resources), - .resource = bf5xx_nand_resources, - .dev = { - .platform_data = &bf5xx_nand_platform, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - -static struct bfin_sd_host bfin_sdh_data = { - .dma_chan = CH_SDH, - .irq_int0 = IRQ_SDH_MASK0, - .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, -}; - -static struct platform_device bf54x_sdh_device = { - .name = "bfin-sdh", - .id = 0, - .dev = { - .platform_data = &bfin_sdh_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezkit_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x80000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x400000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "config(nor)", - .size = 0x8000 * 3, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "u-boot env(nor)", - .size = 0x8000, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data ezkit_flash_data = { - .width = 2, - .parts = ezkit_partitions, - .nr_parts = ARRAY_SIZE(ezkit_partitions), -}; - -static struct resource ezkit_flash_resource = { - .start = 0x20000000, - .end = 0x21ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezkit_flash_data, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -/* SPI flash chip (m25p16) */ -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00080000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p16", -}; - -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -#ifdef CONFIG_PINCTRL_ADI2 - -# define ADI_PINT_DEVNAME "adi-gpio-pint" -# define ADI_GPIO_DEVNAME "adi-gpio" -# define ADI_PINCTRL_DEVNAME "pinctrl-adi2" - -static struct platform_device bfin_pinctrl_device = { - .name = ADI_PINCTRL_DEVNAME, - .id = 0, -}; - -static struct resource bfin_pint0_resources[] = { - { - .start = PINT0_MASK_SET, - .end = PINT0_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT0, - .end = IRQ_PINT0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint0_device = { - .name = ADI_PINT_DEVNAME, - .id = 0, - .num_resources = ARRAY_SIZE(bfin_pint0_resources), - .resource = bfin_pint0_resources, -}; - -static struct resource bfin_pint1_resources[] = { - { - .start = PINT1_MASK_SET, - .end = PINT1_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT1, - .end = IRQ_PINT1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint1_device = { - .name = ADI_PINT_DEVNAME, - .id = 1, - .num_resources = ARRAY_SIZE(bfin_pint1_resources), - .resource = bfin_pint1_resources, -}; - -static struct resource bfin_pint2_resources[] = { - { - .start = PINT2_MASK_SET, - .end = PINT2_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT2, - .end = IRQ_PINT2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint2_device = { - .name = ADI_PINT_DEVNAME, - .id = 2, - .num_resources = ARRAY_SIZE(bfin_pint2_resources), - .resource = bfin_pint2_resources, -}; - -static struct resource bfin_pint3_resources[] = { - { - .start = PINT3_MASK_SET, - .end = PINT3_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT3, - .end = IRQ_PINT3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint3_device = { - .name = ADI_PINT_DEVNAME, - .id = 3, - .num_resources = ARRAY_SIZE(bfin_pint3_resources), - .resource = bfin_pint3_resources, -}; - -static struct resource bfin_gpa_resources[] = { - { - .start = PORTA_FER, - .end = PORTA_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { /* optional */ - .start = IRQ_PA0, - .end = IRQ_PA0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = { - .port_gpio_base = GPIO_PA0, /* Optional */ - .port_pin_base = GPIO_PA0, - .port_width = GPIO_BANKSIZE, - .pint_id = 0, /* PINT0 */ - .pint_assign = true, /* PINT upper 16 bit */ - .pint_map = 0, /* mapping mask in PINT */ -}; - -static struct platform_device bfin_gpa_device = { - .name = ADI_GPIO_DEVNAME, - .id = 0, - .num_resources = ARRAY_SIZE(bfin_gpa_resources), - .resource = bfin_gpa_resources, - .dev = { - .platform_data = &bfin_gpa_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpb_resources[] = { - { - .start = PORTB_FER, - .end = PORTB_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PB0, - .end = IRQ_PB0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = { - .port_gpio_base = GPIO_PB0, - .port_pin_base = GPIO_PB0, - .port_width = 15, - .pint_id = 0, - .pint_assign = true, - .pint_map = 1, -}; - -static struct platform_device bfin_gpb_device = { - .name = ADI_GPIO_DEVNAME, - .id = 1, - .num_resources = ARRAY_SIZE(bfin_gpb_resources), - .resource = bfin_gpb_resources, - .dev = { - .platform_data = &bfin_gpb_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpc_resources[] = { - { - .start = PORTC_FER, - .end = PORTC_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PC0, - .end = IRQ_PC0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = { - .port_gpio_base = GPIO_PC0, - .port_pin_base = GPIO_PC0, - .port_width = 14, - .pint_id = 2, - .pint_assign = true, - .pint_map = 0, -}; - -static struct platform_device bfin_gpc_device = { - .name = ADI_GPIO_DEVNAME, - .id = 2, - .num_resources = ARRAY_SIZE(bfin_gpc_resources), - .resource = bfin_gpc_resources, - .dev = { - .platform_data = &bfin_gpc_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpd_resources[] = { - { - .start = PORTD_FER, - .end = PORTD_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PD0, - .end = IRQ_PD0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = { - .port_gpio_base = GPIO_PD0, - .port_pin_base = GPIO_PD0, - .port_width = GPIO_BANKSIZE, - .pint_id = 2, - .pint_assign = false, - .pint_map = 1, -}; - -static struct platform_device bfin_gpd_device = { - .name = ADI_GPIO_DEVNAME, - .id = 3, - .num_resources = ARRAY_SIZE(bfin_gpd_resources), - .resource = bfin_gpd_resources, - .dev = { - .platform_data = &bfin_gpd_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpe_resources[] = { - { - .start = PORTE_FER, - .end = PORTE_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PE0, - .end = IRQ_PE0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = { - .port_gpio_base = GPIO_PE0, - .port_pin_base = GPIO_PE0, - .port_width = GPIO_BANKSIZE, - .pint_id = 3, - .pint_assign = true, - .pint_map = 2, -}; - -static struct platform_device bfin_gpe_device = { - .name = ADI_GPIO_DEVNAME, - .id = 4, - .num_resources = ARRAY_SIZE(bfin_gpe_resources), - .resource = bfin_gpe_resources, - .dev = { - .platform_data = &bfin_gpe_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpf_resources[] = { - { - .start = PORTF_FER, - .end = PORTF_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PF0, - .end = IRQ_PF0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = { - .port_gpio_base = GPIO_PF0, - .port_pin_base = GPIO_PF0, - .port_width = GPIO_BANKSIZE, - .pint_id = 3, - .pint_assign = false, - .pint_map = 3, -}; - -static struct platform_device bfin_gpf_device = { - .name = ADI_GPIO_DEVNAME, - .id = 5, - .num_resources = ARRAY_SIZE(bfin_gpf_resources), - .resource = bfin_gpf_resources, - .dev = { - .platform_data = &bfin_gpf_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpg_resources[] = { - { - .start = PORTG_FER, - .end = PORTG_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PG0, - .end = IRQ_PG0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = { - .port_gpio_base = GPIO_PG0, - .port_pin_base = GPIO_PG0, - .port_width = GPIO_BANKSIZE, - .pint_id = -1, -}; - -static struct platform_device bfin_gpg_device = { - .name = ADI_GPIO_DEVNAME, - .id = 6, - .num_resources = ARRAY_SIZE(bfin_gpg_resources), - .resource = bfin_gpg_resources, - .dev = { - .platform_data = &bfin_gpg_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gph_resources[] = { - { - .start = PORTH_FER, - .end = PORTH_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PH0, - .end = IRQ_PH0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = { - .port_gpio_base = GPIO_PH0, - .port_pin_base = GPIO_PH0, - .port_width = 14, - .pint_id = -1, -}; - -static struct platform_device bfin_gph_device = { - .name = ADI_GPIO_DEVNAME, - .id = 7, - .num_resources = ARRAY_SIZE(bfin_gph_resources), - .resource = bfin_gph_resources, - .dev = { - .platform_data = &bfin_gph_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpi_resources[] = { - { - .start = PORTI_FER, - .end = PORTI_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PI0, - .end = IRQ_PI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = { - .port_gpio_base = GPIO_PI0, - .port_pin_base = GPIO_PI0, - .port_width = GPIO_BANKSIZE, - .pint_id = -1, -}; - -static struct platform_device bfin_gpi_device = { - .name = ADI_GPIO_DEVNAME, - .id = 8, - .num_resources = ARRAY_SIZE(bfin_gpi_resources), - .resource = bfin_gpi_resources, - .dev = { - .platform_data = &bfin_gpi_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpj_resources[] = { - { - .start = PORTJ_FER, - .end = PORTJ_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PJ0, - .end = IRQ_PJ0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = { - .port_gpio_base = GPIO_PJ0, - .port_pin_base = GPIO_PJ0, - .port_width = 14, - .pint_id = -1, -}; - -static struct platform_device bfin_gpj_device = { - .name = ADI_GPIO_DEVNAME, - .id = 9, - .num_resources = ARRAY_SIZE(bfin_gpj_resources), - .resource = bfin_gpj_resources, - .dev = { - .platform_data = &bfin_gpj_pdata, /* Passed to driver */ - }, -}; - -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */ - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */ - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */ - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI) - { - .modalias = "adxl34x", - .platform_data = &adxl34x_info, - .irq = IRQ_PC5, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */ - .mode = SPI_MODE_3, - }, -#endif -}; -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI0, - .end = CH_SPI0, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI (1) */ -static struct resource bfin_spi1_resource[] = { - [0] = { - .start = SPI1_REGBASE, - .end = SPI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI1, - .end = CH_SPI1, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bf54x_spi_master_info0 = { - .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bf54x_spi_master0 = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bf54x_spi_master_info0, /* Passed to driver */ - }, -}; - -static struct bfin5xx_spi_master bf54x_spi_master_info1 = { - .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, -}; - -static struct platform_device bf54x_spi_master1 = { - .name = "bfin-spi", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi1_resource), - .resource = bfin_spi1_resource, - .dev = { - .platform_data = &bf54x_spi_master_info1, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) -#include -#include -#include - -static const unsigned short ppi_req[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const struct ppi_info ppi_info = { - .type = PPI_TYPE_EPPI, - .dma_ch = CH_EPPI1, - .irq_err = IRQ_EPPI1_ERROR, - .base = (void __iomem *)EPPI1_STATUS, - .pin_req = ppi_req, -}; - -#if IS_ENABLED(CONFIG_VIDEO_VS6624) -static struct v4l2_input vs6624_inputs[] = { - { - .index = 0, - .name = "Camera", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_UNKNOWN, - }, -}; - -static struct bcap_route vs6624_routes[] = { - { - .input = 0, - .output = 0, - }, -}; - -static const unsigned vs6624_ce_pin = GPIO_PG6; - -static struct bfin_capture_config bfin_capture_data = { - .card_name = "BF548", - .inputs = vs6624_inputs, - .num_inputs = ARRAY_SIZE(vs6624_inputs), - .routes = vs6624_routes, - .i2c_adapter_id = 0, - .board_info = { - .type = "vs6624", - .addr = 0x10, - .platform_data = (void *)&vs6624_ce_pin, - }, - .ppi_info = &ppi_info, - .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20), - .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */ - .blank_clocks = 8, /* 8 clocks as SAV and EAV */ -}; -#endif - -static struct platform_device bfin_capture_device = { - .name = "bfin_capture", - .dev = { - .platform_data = &bfin_capture_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_REGBASE, - .end = TWI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI0, - .end = IRQ_TWI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi0_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; - -#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ -static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; - -static struct resource bfin_twi1_resource[] = { - [0] = { - .start = TWI1_REGBASE, - .end = TWI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI1, - .end = IRQ_TWI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi1_device = { - .name = "i2c-bfin-twi", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_twi1_resource), - .resource = bfin_twi1_resource, - .dev = { - .platform_data = &bfin_twi1_pins, - }, -}; -#endif -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { -#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) - { - I2C_BOARD_INFO("ssm2602", 0x1b), - }, -#endif -}; - -#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ -static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = 212, - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C) - { - I2C_BOARD_INFO("adxl34x", 0x53), - .irq = IRQ_PC5, - .platform_data = (void *)&adxl34x_info, - }, -#endif -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("ad5252", 0x2f), - }, -#endif -}; -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"}, - {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ -/* - * Internal VLEV BF54XSBBC1533 - ****temporarily using these values until data sheet is updated - */ - VRPAIR(VLEV_085, 150000000), - VRPAIR(VLEV_090, 250000000), - VRPAIR(VLEV_110, 276000000), - VRPAIR(VLEV_115, 301000000), - VRPAIR(VLEV_120, 525000000), - VRPAIR(VLEV_125, 550000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \ - IS_ENABLED(CONFIG_SND_BF5XX_AC97) - -#define SPORT_REQ(x) \ - [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \ - P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0} - -static const u16 bfin_snd_pin[][7] = { - SPORT_REQ(0), - SPORT_REQ(1), - SPORT_REQ(2), - SPORT_REQ(3), -}; - -static struct bfin_snd_platform_data bfin_snd_data[] = { - { - .pin_req = &bfin_snd_pin[0][0], - }, - { - .pin_req = &bfin_snd_pin[1][0], - }, - { - .pin_req = &bfin_snd_pin[2][0], - }, - { - .pin_req = &bfin_snd_pin[3][0], - }, -}; - -#define BFIN_SND_RES(x) \ - [x] = { \ - { \ - .start = SPORT##x##_TCR1, \ - .end = SPORT##x##_TCR1, \ - .flags = IORESOURCE_MEM \ - }, \ - { \ - .start = CH_SPORT##x##_RX, \ - .end = CH_SPORT##x##_RX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = CH_SPORT##x##_TX, \ - .end = CH_SPORT##x##_TX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = IRQ_SPORT##x##_ERROR, \ - .end = IRQ_SPORT##x##_ERROR, \ - .flags = IORESOURCE_IRQ, \ - } \ - } - -static struct resource bfin_snd_resources[][4] = { - BFIN_SND_RES(0), - BFIN_SND_RES(1), - BFIN_SND_RES(2), - BFIN_SND_RES(3), -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s_pcm = { - .name = "bfin-i2s-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97_pcm = { - .name = "bfin-ac97-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) -static struct platform_device bfin_ad73311_codec_device = { - .name = "ad73311", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980) -static struct platform_device bfin_ad1980_codec_device = { - .name = "ad1980", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) -static struct platform_device bfin_ac97 = { - .name = "bfin-ac97", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -static struct platform_device *ezkit_devices[] __initdata = { - - &bfin_dpmc, -#if defined(CONFIG_PINCTRL_ADI2) - &bfin_pinctrl_device, - &bfin_pint0_device, - &bfin_pint1_device, - &bfin_pint2_device, - &bfin_pint3_device, - &bfin_gpa_device, - &bfin_gpb_device, - &bfin_gpc_device, - &bfin_gpd_device, - &bfin_gpe_device, - &bfin_gpf_device, - &bfin_gpg_device, - &bfin_gph_device, - &bfin_gpi_device, - &bfin_gpj_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 - &bfin_uart2_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART3 - &bfin_uart3_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#ifdef CONFIG_BFIN_SIR2 - &bfin_sir2_device, -#endif -#ifdef CONFIG_BFIN_SIR3 - &bfin_sir3_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_FB_BF54X_LQ043) - &bf54x_lq043_device, -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) - &smsc911x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) - &bfin_isp1760_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART - &bfin_sport2_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART - &bfin_sport3_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) - &bfin_can0_device, - &bfin_can1_device, -#endif - -#if IS_ENABLED(CONFIG_PATA_BF54X) - &bfin_atapi_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) - &bf5xx_nand_device, -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - &bf54x_sdh_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bf54x_spi_master0, - &bf54x_spi_master1, -#endif -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) - &bfin_capture_device, -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_BFIN) - &bf54x_kpad_device, -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) - &bfin_rotary_device, -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi0_device, -#if !defined(CONFIG_BF542) - &i2c_bfin_twi1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezkit_flash_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980) - &bfin_ad1980_codec_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97, -#endif -}; - -/* Pin control settings */ -static struct pinctrl_map __initdata bfin_pinmux_map[] = { - /* per-device maps */ - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"), -#ifdef CONFIG_BFIN_UART1_CTSRTS - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"), -#endif - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"), -#ifdef CONFIG_BFIN_UART3_CTSRTS - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"), -#endif - PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"), - PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"), -#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ - PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"), -#endif - PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"), - PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"), - PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"), -#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT - PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"), -#endif - PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"), - PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", "keys_4x4grp", "keys"), - PIN_MAP_MUX_GROUP("bf54x-keys", "4bit", "pinctrl-adi2.0", "keys_4x4grp", "keys"), - PIN_MAP_MUX_GROUP("bf54x-keys", "8bit", "pinctrl-adi2.0", "keys_8x8grp", "keys"), -}; - -static int __init ezkit_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - - /* Initialize pinmuxing */ - pinctrl_register_mappings(bfin_pinmux_map, - ARRAY_SIZE(bfin_pinmux_map)); - - i2c_register_board_info(0, bfin_i2c_board_info0, - ARRAY_SIZE(bfin_i2c_board_info0)); -#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ - i2c_register_board_info(1, bfin_i2c_board_info1, - ARRAY_SIZE(bfin_i2c_board_info1)); -#endif - - platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - - return 0; -} - -arch_initcall(ezkit_init); - -static struct platform_device *ezkit_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART2 - &bfin_uart2_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART3 - &bfin_uart3_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezkit_early_devices, - ARRAY_SIZE(ezkit_early_devices)); -} diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c deleted file mode 100644 index 69ead33cbf91..000000000000 --- a/arch/blackfin/mach-bf548/dma.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * the simple DMA Implementation for Blackfin - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) DMA8_NEXT_DESC_PTR, - (struct dma_register *) DMA9_NEXT_DESC_PTR, - (struct dma_register *) DMA10_NEXT_DESC_PTR, - (struct dma_register *) DMA11_NEXT_DESC_PTR, - (struct dma_register *) DMA12_NEXT_DESC_PTR, - (struct dma_register *) DMA13_NEXT_DESC_PTR, - (struct dma_register *) DMA14_NEXT_DESC_PTR, - (struct dma_register *) DMA15_NEXT_DESC_PTR, - (struct dma_register *) DMA16_NEXT_DESC_PTR, - (struct dma_register *) DMA17_NEXT_DESC_PTR, - (struct dma_register *) DMA18_NEXT_DESC_PTR, - (struct dma_register *) DMA19_NEXT_DESC_PTR, - (struct dma_register *) DMA20_NEXT_DESC_PTR, - (struct dma_register *) DMA21_NEXT_DESC_PTR, - (struct dma_register *) DMA22_NEXT_DESC_PTR, - (struct dma_register *) DMA23_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - case CH_SPI0: - ret_irq = IRQ_SPI0; - break; - case CH_SPI1: - ret_irq = IRQ_SPI1; - break; - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - case CH_UART1_RX: - ret_irq = IRQ_UART1_RX; - break; - case CH_UART1_TX: - ret_irq = IRQ_UART1_TX; - break; - case CH_EPPI0: - ret_irq = IRQ_EPPI0; - break; - case CH_EPPI1: - ret_irq = IRQ_EPPI1; - break; - case CH_EPPI2: - ret_irq = IRQ_EPPI2; - break; - case CH_PIXC_IMAGE: - ret_irq = IRQ_PIXC_IN0; - break; - case CH_PIXC_OVERLAY: - ret_irq = IRQ_PIXC_IN1; - break; - case CH_PIXC_OUTPUT: - ret_irq = IRQ_PIXC_OUT; - break; - case CH_SPORT2_RX: - ret_irq = IRQ_SPORT2_RX; - break; - case CH_SPORT2_TX: - ret_irq = IRQ_SPORT2_TX; - break; - case CH_SPORT3_RX: - ret_irq = IRQ_SPORT3_RX; - break; - case CH_SPORT3_TX: - ret_irq = IRQ_SPORT3_TX; - break; - case CH_SDH: - ret_irq = IRQ_SDH; - break; - case CH_SPI2: - ret_irq = IRQ_SPI2; - break; - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MDMAS0; - break; - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MDMAS1; - break; - case CH_MEM_STREAM2_SRC: - case CH_MEM_STREAM2_DEST: - ret_irq = IRQ_MDMAS2; - break; - case CH_MEM_STREAM3_SRC: - case CH_MEM_STREAM3_DEST: - ret_irq = IRQ_MDMAS3; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h deleted file mode 100644 index 098fad63e03b..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ /dev/null @@ -1,301 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.0 or 0.1 silicon - sorry */ -#if __SILICON_REVISION__ < 2 -# error will not work on BF548 silicon version 0.0, or 0.1 -#endif - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ -#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* FIFO Boot Mode Not Functional */ -#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) -/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -/* - * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing - * shows that the fix itself does not cover all cases. - */ -#define ANOMALY_05000353 (1) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* External Memory Read Access Hangs Core With PLL Bypass */ -#define ANOMALY_05000360 (1) -/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ -#define ANOMALY_05000365 (1) -/* Addressing Conflict between Boot ROM and Asynchronous Memory */ -#define ANOMALY_05000369 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) -/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ -#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) -/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ -#define ANOMALY_05000379 (1) -/* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) -/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ -#define ANOMALY_05000405 (1) -/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ -#define ANOMALY_05000406 (__SILICON_REVISION__ < 2) -/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) -/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ -#define ANOMALY_05000408 (1) -/* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) -/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) -/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ -#define ANOMALY_05000413 (__SILICON_REVISION__ < 2) -/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (__SILICON_REVISION__ < 4) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ -#define ANOMALY_05000427 (__SILICON_REVISION__ < 2) -/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ -#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) -/* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) -/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ -#define ANOMALY_05000431 (__SILICON_REVISION__ < 3) -/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ -#define ANOMALY_05000434 (1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ -#define ANOMALY_05000446 (1) -/* UART IrDA Receiver Fails on Extended Bit Pulses */ -#define ANOMALY_05000447 (1) -/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */ -#define ANOMALY_05000448 (__SILICON_REVISION__ == 1) -/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ -#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) -/* USB DMA Short Packet Data Corruption */ -#define ANOMALY_05000450 (1) -/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ -#define ANOMALY_05000456 (1) -/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ -#define ANOMALY_05000457 (1) -/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ -#define ANOMALY_05000460 (__SILICON_REVISION__ < 4) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (__SILICON_REVISION__ < 4) -/* USB DMA RX Data Corruption */ -#define ANOMALY_05000463 (__SILICON_REVISION__ < 4) -/* USB TX DMA Hang */ -#define ANOMALY_05000464 (__SILICON_REVISION__ < 4) -/* USB Rx DMA Hang */ -#define ANOMALY_05000465 (1) -/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ -#define ANOMALY_05000466 (__SILICON_REVISION__ < 4) -/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ -#define ANOMALY_05000467 (__SILICON_REVISION__ < 4) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */ -#define ANOMALY_05000474 (__SILICON_REVISION__ < 4) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ -#define ANOMALY_05000483 (1) -/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */ -#define ANOMALY_05000484 (__SILICON_REVISION__ < 3) -/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4) -/* PLL May Latch Incorrect Values Coming Out of Reset */ -#define ANOMALY_05000489 (1) -/* SPI Master Boot Can Fail Under Certain Conditions */ -#define ANOMALY_05000490 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ -#define ANOMALY_05000498 (1) -/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */ -#define ANOMALY_05000500 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) -/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */ -#define ANOMALY_05000502 (1) - -/* - * These anomalies have been "phased" out of analog.com anomaly sheets and are - * here to show running on older silicon just isn't feasible. - */ - -/* False Hardware Error when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) -/* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) -/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) -/* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) -/* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) -/* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) -/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) -/* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) -/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) -/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) -/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) -/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) -/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) -/* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) -/* USB Calibration Value to use */ -#define ANOMALY_05000346_value 0x5411 -/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) -/* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) -/* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) -/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ -#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) -/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ -#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) -/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ -#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) -/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ -#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) -/* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) -/* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) -/* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) -/* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) -/* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) -/* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) -/* Changed Meaning of BCODE Field in SYSCR Register */ -#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) -/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ -#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) -/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) -/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) -/* Log Buffer Not Functional */ -#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) -/* Hook Routine Not Functional */ -#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) -/* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) -/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) -/* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) -/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000099 (0) -#define ANOMALY_05000120 (0) -#define ANOMALY_05000125 (0) -#define ANOMALY_05000149 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000179 (0) -#define ANOMALY_05000182 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000189 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000202 (0) -#define ANOMALY_05000215 (0) -#define ANOMALY_05000219 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000231 (0) -#define ANOMALY_05000233 (0) -#define ANOMALY_05000234 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000248 (0) -#define ANOMALY_05000250 (0) -#define ANOMALY_05000254 (0) -#define ANOMALY_05000257 (0) -#define ANOMALY_05000261 (0) -#define ANOMALY_05000263 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000278 (0) -#define ANOMALY_05000283 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000301 (0) -#define ANOMALY_05000305 (0) -#define ANOMALY_05000307 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000315 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000364 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000400 (0) -#define ANOMALY_05000402 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000440 (0) -#define ANOMALY_05000475 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h deleted file mode 100644 index 751e5e11ecf8..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/bf548.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF548_H__ -#define __MACH_BF548_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN) - -#if defined(CONFIG_BF542) -# define CPU "BF542" -# define CPUID 0x27de -#elif defined(CONFIG_BF544) -# define CPU "BF544" -# define CPUID 0x27de -#elif defined(CONFIG_BF547) -# define CPU "BF547" -# define CPUID 0x27de -#elif defined(CONFIG_BF548) -# define CPU "BF548" -# define CPUID 0x27de -#elif defined(CONFIG_BF549) -# define CPU "BF549" -# define CPUID 0x27de -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF48_H__ */ diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h deleted file mode 100644 index 8821efe57fbc..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef BF54X_LQ043_H -#define BF54X_LQ043_H - -struct bfin_bf54xfb_val { - unsigned int defval; - unsigned int min; - unsigned int max; -}; - -struct bfin_bf54xfb_mach_info { - unsigned char fixed_syncs; /* do not update sync/border */ - - /* LCD types */ - int type; - - /* Screen size */ - int width; - int height; - - /* Screen info */ - struct bfin_bf54xfb_val xres; - struct bfin_bf54xfb_val yres; - struct bfin_bf54xfb_val bpp; - - /* GPIOs */ - unsigned short disp; - -}; - -#endif /* BF54X_LQ043_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h deleted file mode 100644 index 49338ae299ab..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_KPAD_H -#define _BFIN_KPAD_H - -struct bfin_kpad_platform_data { - int rows; - int cols; - const unsigned int *keymap; - unsigned short keymapsize; - unsigned short repeat; - u32 debounce_time; /* in ns */ - u32 coldrive_time; /* in ns */ - u32 keyup_test_interval; /* in ms */ -}; - -#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val)) - -#endif diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h deleted file mode 100644 index a77109f99720..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 4 - -#define BFIN_UART_BF54X_STYLE - -#endif diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h deleted file mode 100644 index 72da721a77f5..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#include "bf548.h" -#include "anomaly.h" - -#include -#ifdef CONFIG_BF542 -# include "defBF542.h" -#endif -#ifdef CONFIG_BF544 -# include "defBF544.h" -#endif -#ifdef CONFIG_BF547 -# include "defBF547.h" -#endif -#ifdef CONFIG_BF548 -# include "defBF548.h" -#endif -#ifdef CONFIG_BF549 -# include "defBF549.h" -#endif - -#ifndef __ASSEMBLY__ -# include -# ifdef CONFIG_BF542 -# include "cdefBF542.h" -# endif -# ifdef CONFIG_BF544 -# include "cdefBF544.h" -# endif -# ifdef CONFIG_BF547 -# include "cdefBF547.h" -# endif -# ifdef CONFIG_BF548 -# include "cdefBF548.h" -# endif -# ifdef CONFIG_BF549 -# include "cdefBF549.h" -# endif -#endif - -#endif diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h deleted file mode 100644 index 916347901d5a..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h +++ /dev/null @@ -1,554 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF542_H -#define _CDEF_BF542_H - -/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ -#include "cdefBF54x_base.h" - -/* The following are the #defines needed by ADSP-BF542 that are not in the common header */ - -/* ATAPI Registers */ - -#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) -#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) -#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) -#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) -#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) -#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) -#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) -#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) -#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) -#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) -#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) -#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) -#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) -#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) -#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) -#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) -#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) -#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) -#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) -#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) -#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) -#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) -#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) -#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) -#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) -#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) - -/* SDH Registers */ - -#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) -#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) -#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) -#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) -#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) -#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) -#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) -#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) -#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) -#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) -#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) -#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) -#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) -#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) -#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) -#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) -#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) -#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) -#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) -#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) -#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) -#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) -#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) -#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) -#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) -#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) -#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) -#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) -#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) -#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) -#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) - -/* USB Control Registers */ - -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) - -/* USB Packet Control Registers */ - -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) - -/* USB Endbfin_read_()oint FIFO Registers */ - -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) - -/* USB OTG Control Registers */ - -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) - -/* USB Phy Control Registers */ - -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) - -/* (APHY_CNTRL is for ADI usage only) */ - -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) - -/* (APHY_CALIB is for ADI usage only) */ - -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) - -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) - -/* USB Endbfin_read_()oint 0 Control Registers */ - -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 1 Control Registers */ - -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 2 Control Registers */ - -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 3 Control Registers */ - -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 4 Control Registers */ - -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 5 Control Registers */ - -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 6 Control Registers */ - -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 7 Control Registers */ - -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) - -/* USB Channel 0 Config Registers */ - -#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) -#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) -#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) -#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) -#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) -#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) -#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) -#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) -#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) -#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) - -/* USB Channel 1 Config Registers */ - -#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) -#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) -#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) -#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) -#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) -#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) -#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) -#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) -#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) -#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) - -/* USB Channel 2 Config Registers */ - -#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) -#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) -#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) -#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) -#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) -#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) -#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) -#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) -#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) -#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) - -/* USB Channel 3 Config Registers */ - -#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) -#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) -#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) -#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) -#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) -#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) -#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) -#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) -#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) -#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) - -/* USB Channel 4 Config Registers */ - -#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) -#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) -#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) -#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) -#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) -#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) -#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) -#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) -#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) -#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) - -/* USB Channel 5 Config Registers */ - -#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) -#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) -#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) -#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) -#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) -#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) -#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) -#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) -#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) -#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) - -/* USB Channel 6 Config Registers */ - -#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) -#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) -#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) -#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) -#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) -#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) -#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) -#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) -#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) -#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) - -/* USB Channel 7 Config Registers */ - -#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) -#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) -#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) -#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) -#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) -#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) -#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) -#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) -#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) -#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) - -/* Keybfin_read_()ad Registers */ - -#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) -#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) -#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) -#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) -#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) -#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) -#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) - -#endif /* _CDEF_BF542_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h deleted file mode 100644 index 33ec8102ceda..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h +++ /dev/null @@ -1,913 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF544_H -#define _CDEF_BF544_H - -/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ -#include "cdefBF54x_base.h" - -/* The following are the #defines needed by ADSP-BF544 that are not in the common header */ - -/* Timer Registers */ - -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) - -/* Timer Groubfin_read_() of 3 */ - -#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) -#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) -#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) -#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) - -/* EPPI0 Registers */ - -#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) -#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) -#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) -#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) -#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) -#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) -#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) -#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) -#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) -#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) -#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) -#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) -#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) -#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) -#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) - -/* Two Wire Interface Registers (TWI1) */ - -/* CAN Controller 1 Config 1 Registers */ - -#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) -#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) -#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) -#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) -#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) -#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) -#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) -#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) -#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) -#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) -#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) -#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) -#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) -#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) - -/* CAN Controller 1 Config 2 Registers */ - -#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) -#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) -#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) -#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) -#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) -#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) -#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) -#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) -#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) -#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) -#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) -#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) -#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) -#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) - -/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */ - -#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) -#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) -#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) -#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) -#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) -#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) -#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) -#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) -#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) -#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) -#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) -#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) -#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) -#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) -#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) -#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) -#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) - -/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ - -#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) -#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) -#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) -#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) -#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) -#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) -#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) -#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) -#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) -#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) -#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) -#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) -#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) -#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) -#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) -#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) -#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) -#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) -#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) -#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) -#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) -#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) -#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) -#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) -#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) -#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) -#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) -#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) -#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) -#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) -#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) -#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) -#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) - -/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ - -#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) -#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) -#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) -#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) -#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) -#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) -#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) -#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) -#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) -#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) -#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) -#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) -#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) -#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) -#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) -#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) -#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) -#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) -#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) -#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) -#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) -#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) -#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) -#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) -#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) -#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) -#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) -#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) -#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) -#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) -#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) -#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) -#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) - -/* CAN Controller 1 Mailbox Data Registers */ - -#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) -#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) -#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) -#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) -#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) -#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) -#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) -#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) -#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) -#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) -#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) -#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) -#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) -#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) -#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) -#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) -#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) -#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) -#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) -#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) -#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) -#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) -#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) -#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) -#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) -#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) -#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) -#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) -#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) -#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) -#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) -#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) -#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) -#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) -#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) -#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) -#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) -#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) -#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) -#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) -#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) -#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) -#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) -#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) -#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) -#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) -#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) -#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) -#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) -#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) -#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) -#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) -#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) -#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) -#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) -#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) -#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) -#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) -#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) -#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) -#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) -#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) -#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) -#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) -#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) -#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) -#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) -#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) -#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) -#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) -#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) -#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) -#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) -#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) -#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) -#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) -#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) -#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) -#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) -#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) -#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) -#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) -#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) -#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) -#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) -#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) -#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) -#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) -#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) -#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) -#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) -#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) -#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) -#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) -#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) -#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) -#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) -#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) -#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) -#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) -#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) -#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) -#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) -#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) -#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) -#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) -#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) -#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) -#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) -#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) -#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) -#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) -#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) -#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) -#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) -#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) -#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) -#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) -#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) -#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) -#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) -#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) -#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) -#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) -#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) -#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) -#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) -#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) -#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) - -/* CAN Controller 1 Mailbox Data Registers */ - -#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) -#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) -#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) -#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) -#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) -#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) -#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) -#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) -#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) -#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) -#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) -#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) -#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) -#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) -#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) -#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) -#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) -#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) -#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) -#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) -#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) -#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) -#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) -#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) -#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) -#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) -#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) -#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) -#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) -#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) -#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) -#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) -#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) -#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) -#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) -#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) -#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) -#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) -#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) -#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) -#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) -#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) -#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) -#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) -#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) -#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) -#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) -#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) -#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) -#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) -#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) -#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) -#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) -#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) -#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) -#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) -#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) -#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) -#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) -#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) -#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) -#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) -#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) -#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) -#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) -#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) -#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) -#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) -#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) -#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) -#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) -#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) -#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) -#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) -#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) -#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) -#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) -#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) -#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) -#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) -#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) -#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) -#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) -#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) -#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) -#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) -#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) -#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) -#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) -#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) -#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) -#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) -#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) -#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) -#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) -#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) -#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) -#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) -#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) -#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) -#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) -#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) -#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) -#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) -#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) -#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) -#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) -#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) -#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) -#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) -#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) -#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) -#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) -#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) -#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) -#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) -#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) -#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) -#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) -#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) -#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) -#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) -#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) -#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) -#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) -#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) -#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) -#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) -#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) - -/* HOST Port Registers */ - -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) - -/* Pixel Combfin_read_()ositor (PIXC) Registers */ - -#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) -#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) -#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) -#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) -#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) -#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) -#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) -#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) -#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) -#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) -#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) -#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) -#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) -#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) -#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) -#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) -#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) -#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) -#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) -#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) - -/* Handshake MDMA 0 Registers */ - -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) - -/* Handshake MDMA 1 Registers */ - -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) - -#endif /* _CDEF_BF544_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h deleted file mode 100644 index be83f645bba8..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h +++ /dev/null @@ -1,796 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF547_H -#define _CDEF_BF547_H - -/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ -#include "cdefBF54x_base.h" - -/* The following are the #defines needed by ADSP-BF547 that are not in the common header */ - -/* Timer Registers */ - -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) - -/* Timer Groubfin_read_() of 3 */ - -#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) -#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) -#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) -#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) - -/* SPORT0 Registers */ - -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) - -/* EPPI0 Registers */ - -#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) -#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) -#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) -#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) -#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) -#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) -#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) -#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) -#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) -#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) -#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) -#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) -#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) -#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) -#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) - -/* UART2 Registers */ - -#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) -#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) -#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) -#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) -#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) -#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) -#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) -#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) -#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) -#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) -#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) -#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) -#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) -#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) -#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) - -/* Two Wire Interface Registers (TWI1) */ - -/* SPI2 Registers */ - -#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) -#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) -#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) -#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) -#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) -#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) -#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) -#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) - -/* ATAPI Registers */ - -#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) -#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) -#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) -#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) -#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) -#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) -#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) -#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) -#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) -#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) -#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) -#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) -#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) -#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) -#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) -#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) -#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) -#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) -#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) -#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) -#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) -#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) -#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) -#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) -#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) -#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) - -/* SDH Registers */ - -#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) -#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) -#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) -#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) -#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) -#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) -#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) -#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) -#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) -#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) -#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) -#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) -#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) -#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) -#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) -#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) -#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) -#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) -#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) -#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) -#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) -#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) -#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) -#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) -#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) -#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) -#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) -#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) -#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) -#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) -#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) - -/* HOST Port Registers */ - -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) - -/* USB Control Registers */ - -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) - -/* USB Packet Control Registers */ - -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) - -/* USB Endbfin_read_()oint FIFO Registers */ - -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) - -/* USB OTG Control Registers */ - -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) - -/* USB Phy Control Registers */ - -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) - -/* (APHY_CNTRL is for ADI usage only) */ - -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) - -/* (APHY_CALIB is for ADI usage only) */ - -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) - -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) - -/* USB Endbfin_read_()oint 0 Control Registers */ - -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 1 Control Registers */ - -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 2 Control Registers */ - -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 3 Control Registers */ - -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 4 Control Registers */ - -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 5 Control Registers */ - -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 6 Control Registers */ - -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) - -/* USB Endbfin_read_()oint 7 Control Registers */ - -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) - -/* USB Channel 0 Config Registers */ - -#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) -#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) -#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) -#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) -#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) -#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) -#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) -#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) -#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) -#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) - -/* USB Channel 1 Config Registers */ - -#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) -#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) -#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) -#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) -#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) -#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) -#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) -#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) -#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) -#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) - -/* USB Channel 2 Config Registers */ - -#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) -#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) -#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) -#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) -#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) -#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) -#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) -#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) -#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) -#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) - -/* USB Channel 3 Config Registers */ - -#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) -#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) -#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) -#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) -#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) -#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) -#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) -#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) -#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) -#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) - -/* USB Channel 4 Config Registers */ - -#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) -#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) -#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) -#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) -#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) -#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) -#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) -#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) -#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) -#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) - -/* USB Channel 5 Config Registers */ - -#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) -#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) -#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) -#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) -#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) -#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) -#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) -#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) -#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) -#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) - -/* USB Channel 6 Config Registers */ - -#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) -#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) -#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) -#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) -#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) -#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) -#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) -#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) -#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) -#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) - -/* USB Channel 7 Config Registers */ - -#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) -#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) -#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) -#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) -#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) -#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) -#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) -#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) -#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) -#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) - -/* Keybfin_read_()ad Registers */ - -#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) -#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) -#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) -#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) -#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) -#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) -#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) - -/* Pixel Combfin_read_()ositor (PIXC) Registers */ - -#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) -#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) -#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) -#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) -#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) -#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) -#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) -#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) -#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) -#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) -#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) -#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) -#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) -#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) -#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) -#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) -#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) -#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) -#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) -#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) - -/* Handshake MDMA 0 Registers */ - -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) - -/* Handshake MDMA 1 Registers */ - -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) - -#endif /* _CDEF_BF547_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h deleted file mode 100644 index bae67a65633e..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h +++ /dev/null @@ -1,761 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF548_H -#define _CDEF_BF548_H - -/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ -#include "cdefBF54x_base.h" - -/* The BF548 is like the BF547, but has additional CANs */ -#include "cdefBF547.h" - -/* CAN Controller 1 Config 1 Registers */ - -#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) -#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) -#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) -#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) -#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) -#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) -#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) -#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) -#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) -#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) -#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) -#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) -#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) -#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) - -/* CAN Controller 1 Config 2 Registers */ - -#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) -#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) -#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) -#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) -#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) -#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) -#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) -#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) -#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) -#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) -#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) -#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) -#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) -#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) - -/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */ - -#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) -#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) -#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) -#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) -#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) -#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) -#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) -#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) -#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) -#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) -#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) -#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) -#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) -#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) -#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) -#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) -#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) - -/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ - -#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) -#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) -#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) -#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) -#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) -#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) -#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) -#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) -#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) -#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) -#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) -#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) -#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) -#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) -#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) -#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) -#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) -#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) -#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) -#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) -#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) -#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) -#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) -#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) -#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) -#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) -#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) -#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) -#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) -#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) -#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) -#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) -#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) - -/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ - -#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) -#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) -#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) -#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) -#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) -#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) -#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) -#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) -#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) -#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) -#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) -#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) -#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) -#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) -#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) -#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) -#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) -#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) -#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) -#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) -#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) -#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) -#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) -#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) -#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) -#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) -#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) -#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) -#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) -#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) -#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) -#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) -#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) - -/* CAN Controller 1 Mailbox Data Registers */ - -#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) -#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) -#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) -#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) -#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) -#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) -#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) -#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) -#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) -#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) -#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) -#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) -#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) -#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) -#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) -#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) -#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) -#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) -#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) -#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) -#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) -#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) -#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) -#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) -#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) -#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) -#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) -#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) -#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) -#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) -#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) -#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) -#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) -#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) -#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) -#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) -#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) -#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) -#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) -#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) -#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) -#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) -#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) -#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) -#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) -#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) -#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) -#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) -#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) -#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) -#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) -#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) -#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) -#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) -#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) -#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) -#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) -#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) -#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) -#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) -#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) -#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) -#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) -#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) -#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) -#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) -#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) -#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) -#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) -#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) -#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) -#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) -#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) -#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) -#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) -#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) -#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) -#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) -#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) -#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) -#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) -#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) -#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) -#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) -#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) -#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) -#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) -#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) -#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) -#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) -#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) -#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) -#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) -#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) -#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) -#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) -#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) -#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) -#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) -#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) -#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) -#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) -#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) -#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) -#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) -#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) -#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) -#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) -#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) -#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) -#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) -#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) -#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) -#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) -#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) -#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) -#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) -#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) -#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) -#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) -#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) -#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) -#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) -#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) -#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) -#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) -#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) -#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) -#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) - -/* CAN Controller 1 Mailbox Data Registers */ - -#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) -#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) -#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) -#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) -#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) -#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) -#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) -#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) -#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) -#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) -#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) -#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) -#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) -#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) -#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) -#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) -#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) -#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) -#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) -#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) -#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) -#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) -#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) -#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) -#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) -#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) -#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) -#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) -#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) -#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) -#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) -#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) -#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) -#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) -#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) -#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) -#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) -#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) -#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) -#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) -#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) -#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) -#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) -#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) -#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) -#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) -#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) -#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) -#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) -#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) -#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) -#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) -#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) -#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) -#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) -#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) -#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) -#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) -#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) -#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) -#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) -#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) -#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) -#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) -#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) -#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) -#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) -#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) -#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) -#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) -#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) -#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) -#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) -#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) -#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) -#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) -#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) -#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) -#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) -#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) -#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) -#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) -#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) -#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) -#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) -#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) -#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) -#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) -#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) -#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) -#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) -#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) -#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) -#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) -#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) -#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) -#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) -#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) -#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) -#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) -#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) -#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) -#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) -#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) -#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) -#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) -#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) -#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) -#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) -#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) -#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) -#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) -#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) -#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) -#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) -#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) -#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) -#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) -#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) -#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) -#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) -#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) -#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) -#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) -#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) -#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) -#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) -#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) -#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) - -#endif /* _CDEF_BF548_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h deleted file mode 100644 index 002136ad5a44..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF549_H -#define _CDEF_BF549_H - -/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ -#include "cdefBF54x_base.h" - -/* The BF549 is like the BF544, but has MXVR */ -#include "cdefBF547.h" - -/* MXVR Registers */ - -#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) -#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) -#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0) -#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) -#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1) -#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) -#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0) -#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) -#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1) -#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) -#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0) -#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) -#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1) -#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) -#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION) -#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) -#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION) -#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) -#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY) -#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val) -#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY) -#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val) -#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR) -#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val) -#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR) -#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val) -#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR) -#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val) - -/* MXVR Allocation Table Registers */ - -#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0) -#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val) -#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1) -#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val) -#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2) -#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val) -#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3) -#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val) -#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4) -#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val) -#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5) -#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val) -#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6) -#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val) -#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7) -#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val) -#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8) -#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val) -#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9) -#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val) -#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10) -#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val) -#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11) -#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val) -#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12) -#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val) -#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13) -#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val) -#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14) -#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val) - -/* MXVR Channel Assign Registers */ - -#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0) -#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val) -#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1) -#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val) -#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2) -#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val) -#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3) -#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val) -#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4) -#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val) -#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5) -#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val) -#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6) -#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val) -#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7) -#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val) - -/* MXVR DMA0 Registers */ - -#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG) -#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val) -#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR) -#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR) -#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT) -#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val) -#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR) -#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR) -#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT) -#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val) - -/* MXVR DMA1 Registers */ - -#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG) -#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val) -#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR) -#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR) -#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT) -#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val) -#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR) -#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR) -#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT) -#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val) - -/* MXVR DMA2 Registers */ - -#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG) -#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val) -#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR) -#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR) -#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT) -#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val) -#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR) -#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR) -#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT) -#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val) - -/* MXVR DMA3 Registers */ - -#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG) -#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val) -#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR) -#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR) -#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT) -#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val) -#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR) -#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR) -#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT) -#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val) - -/* MXVR DMA4 Registers */ - -#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG) -#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val) -#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR) -#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR) -#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT) -#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val) -#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR) -#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR) -#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT) -#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val) - -/* MXVR DMA5 Registers */ - -#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG) -#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val) -#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR) -#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR) -#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT) -#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val) -#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR) -#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR) -#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT) -#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val) - -/* MXVR DMA6 Registers */ - -#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG) -#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val) -#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR) -#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR) -#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT) -#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val) -#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR) -#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR) -#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT) -#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val) - -/* MXVR DMA7 Registers */ - -#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG) -#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val) -#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR) -#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR) -#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT) -#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val) -#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR) -#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR) -#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT) -#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val) - -/* MXVR Asynch Packet Registers */ - -#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL) -#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val) -#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR) -#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR) -#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR) -#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR) -#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR) -#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR) -#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR) -#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR) - -/* MXVR Control Message Registers */ - -#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL) -#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val) -#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR) -#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR) -#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR) -#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR) -#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR) -#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR) -#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR) -#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR) - -/* MXVR Remote Read Registers */ - -#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR) -#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR) -#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR) -#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR) - -/* MXVR Pattern Data Registers */ - -#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0) -#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val) -#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0) -#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val) -#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1) -#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val) -#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1) -#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val) - -/* MXVR Frame Counter Registers */ - -#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0) -#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val) -#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1) -#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val) - -/* MXVR Routing Table Registers */ - -#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0) -#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val) -#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1) -#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val) -#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2) -#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val) -#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3) -#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val) -#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4) -#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val) -#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5) -#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val) -#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6) -#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val) -#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7) -#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val) -#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8) -#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val) -#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9) -#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val) -#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10) -#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val) -#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11) -#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val) -#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12) -#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val) -#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13) -#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val) -#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14) -#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val) - -/* MXVR Counter-Clock-Control Registers */ - -#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT) -#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val) -#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL) -#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val) -#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL) -#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val) -#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL) -#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val) -#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL) -#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val) -#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) -#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) - -#endif /* _CDEF_BF549_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h deleted file mode 100644 index 50c89c8052f3..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ /dev/null @@ -1,2633 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF54X_H -#define _CDEF_BF54X_H - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ -/* ************************************************************** */ - -/* PLL Registers */ - -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) - -/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ - -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) - -/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ - -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) - -/* SIC Registers */ - -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) -#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) - -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) -#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) - -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) -#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) -#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) -#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) -#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) -#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) - -/* Watchdog Timer Registers */ - -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) - -/* RTC Registers */ - -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) - -/* UART0 Registers */ - -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) -#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) -#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) - -/* SPI0 Registers */ - -#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) -#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) -#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) -#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) -#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) -#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) - -/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ - -/* Two Wire Interface Registers (TWI0) */ - -/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ - -/* SPORT1 Registers */ - -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) - -/* Asynchronous Memory Control Registers */ - -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL) -#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val) -#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) -#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) -#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL) -#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val) - -/* DDR Memory Control Registers */ - -#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) -#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) -#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) -#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) -#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) -#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val) -#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) -#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) -#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) - -/* DDR BankRead and Write Count Registers */ - -#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) -#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) -#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) -#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) -#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) -#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) -#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) -#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) -#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) -#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) -#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) -#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) -#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) -#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) -#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) -#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) -#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) -#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) -#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) -#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) -#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) -#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) -#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) -#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) -#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) -#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) - -/* DMAC0 Registers */ - -#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) -#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val) -#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) -#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val) - -/* DMA Channel 0 Registers */ - -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) - -/* DMA Channel 1 Registers */ - -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) - -/* DMA Channel 2 Registers */ - -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) - -/* DMA Channel 3 Registers */ - -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) - -/* DMA Channel 4 Registers */ - -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) - -/* DMA Channel 5 Registers */ - -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) - -/* DMA Channel 6 Registers */ - -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) - -/* DMA Channel 7 Registers */ - -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) - -/* DMA Channel 8 Registers */ - -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) - -/* DMA Channel 9 Registers */ - -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) - -/* DMA Channel 10 Registers */ - -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) - -/* DMA Channel 11 Registers */ - -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) - -/* MDMA Stream 0 Registers */ - -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) - -/* MDMA Stream 1 Registers */ - -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) - -/* EPPI1 Registers */ - -#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) -#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) -#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) -#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) -#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) -#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) -#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) -#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) -#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) -#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) -#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) -#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) -#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) -#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) -#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) - -/* Port Interrubfin_read_()t 0 Registers (32-bit) */ - -#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) -#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) -#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST) -#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val) -#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) -#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) -#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) -#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) -#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) -#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) -#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) -#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) - -/* Port Interrubfin_read_()t 1 Registers (32-bit) */ - -#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) -#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) -#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST) -#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val) -#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) -#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) -#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) -#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) -#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) -#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) -#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) -#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) - -/* Port Interrubfin_read_()t 2 Registers (32-bit) */ - -#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) -#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) -#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST) -#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val) -#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) -#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) -#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) -#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) -#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) -#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) -#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) -#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) - -/* Port Interrubfin_read_()t 3 Registers (32-bit) */ - -#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) -#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) -#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST) -#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val) -#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) -#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) -#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) -#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) -#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) -#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) -#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) -#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) - -/* Port A Registers */ - -#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) -#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define bfin_read_PORTA() bfin_read16(PORTA) -#define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) -#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) -#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) -#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) -#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) -#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) -#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) - -/* Port B Registers */ - -#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) -#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define bfin_read_PORTB() bfin_read16(PORTB) -#define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) -#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) -#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) -#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) -#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) -#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) -#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) - -/* Port C Registers */ - -#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) -#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define bfin_read_PORTC() bfin_read16(PORTC) -#define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) -#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) -#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) -#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) -#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) -#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) -#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) - -/* Port D Registers */ - -#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) -#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define bfin_read_PORTD() bfin_read16(PORTD) -#define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) -#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) -#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) -#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) -#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) -#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) -#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) - -/* Port E Registers */ - -#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) -#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define bfin_read_PORTE() bfin_read16(PORTE) -#define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) -#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) -#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) -#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) -#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) -#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) -#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) - -/* Port F Registers */ - -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define bfin_read_PORTF() bfin_read16(PORTF) -#define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) -#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) -#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) -#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) -#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) -#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) - -/* Port G Registers */ - -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define bfin_read_PORTG() bfin_read16(PORTG) -#define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) -#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) -#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) -#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) -#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) -#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) - -/* Port H Registers */ - -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define bfin_read_PORTH() bfin_read16(PORTH) -#define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) -#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) -#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) -#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) -#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) -#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) - -/* Port I Registers */ - -#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) -#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define bfin_read_PORTI() bfin_read16(PORTI) -#define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) -#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) -#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) -#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) -#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) -#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) -#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) - -/* Port J Registers */ - -#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) -#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define bfin_read_PORTJ() bfin_read16(PORTJ) -#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) -#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) -#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) -#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) -#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) -#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) -#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) - -/* PWM Timer Registers */ - -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) - -/* Timer Groubfin_read_() of 8 */ - -#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) -#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) -#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) -#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) - -/* DMAC1 Registers */ - -#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) -#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val) -#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) -#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val) - -/* DMA Channel 12 Registers */ - -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) -#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) -#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) -#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) -#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) -#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) - -/* DMA Channel 13 Registers */ - -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) -#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) -#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) -#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) -#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) -#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) - -/* DMA Channel 14 Registers */ - -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) -#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) -#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) -#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) -#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) -#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) - -/* DMA Channel 15 Registers */ - -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) -#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) -#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) -#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) -#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) -#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) - -/* DMA Channel 16 Registers */ - -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) -#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) -#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) -#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) -#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) -#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) - -/* DMA Channel 17 Registers */ - -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) -#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) -#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) -#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) -#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) -#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) - -/* DMA Channel 18 Registers */ - -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) -#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) -#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) -#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) -#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) -#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) - -/* DMA Channel 19 Registers */ - -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) -#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) -#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) -#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) -#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) -#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) - -/* DMA Channel 20 Registers */ - -#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) -#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) -#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) -#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) -#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) -#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) -#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) -#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) -#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) -#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) -#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) -#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) - -/* DMA Channel 21 Registers */ - -#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val) -#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val) -#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) -#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) -#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) -#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val) -#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val) -#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) -#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) -#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) -#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) -#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) - -/* DMA Channel 22 Registers */ - -#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val) -#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val) -#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) -#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) -#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) -#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val) -#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val) -#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) -#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) -#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) -#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) -#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) - -/* DMA Channel 23 Registers */ - -#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val) -#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val) -#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) -#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) -#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) -#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val) -#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val) -#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) -#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) -#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) -#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) -#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) - -/* MDMA Stream 2 Registers */ - -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val) -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val) -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val) -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val) -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) - -/* MDMA Stream 3 Registers */ - -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val) -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val) -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val) -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val) -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) - -/* UART1 Registers */ - -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) -#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) -#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) - -/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ - -/* SPI1 Registers */ - -#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) -#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) -#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) -#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) -#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) -#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) - -/* SPORT2 Registers */ - -#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) -#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) -#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) -#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) -#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) -#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) -#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) -#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) -#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) -#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) -#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) -#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) -#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) -#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) -#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) -#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) -#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) -#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) -#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) -#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) -#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) -#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) -#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) - -/* SPORT3 Registers */ - -#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) -#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) -#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) -#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) -#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) -#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) -#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) -#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) -#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) -#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) -#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) -#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) -#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) -#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) -#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) -#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) -#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) -#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) -#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) -#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) -#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) -#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) -#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) - -/* EPPI2 Registers */ - -#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) -#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) -#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) -#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) -#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) -#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) -#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) -#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) -#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) -#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) -#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) -#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) -#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) -#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) -#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) - -/* CAN Controller 0 Config 1 Registers */ - -#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) -#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) -#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) -#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) -#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) -#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) -#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) -#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) -#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) -#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) -#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) -#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) -#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) -#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) - -/* CAN Controller 0 Config 2 Registers */ - -#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) -#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) -#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) -#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) -#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) -#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) -#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) -#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) -#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) -#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) -#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) -#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) -#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) -#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) - -/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */ - -#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) -#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) -#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) -#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) -#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) -#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) -#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) -#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) -#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) -#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) -#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) -#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) -#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) -#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) -#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) -#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) -#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) - -/* CAN Controller 0 Accebfin_read_()tance Registers */ - -#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) -#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) -#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) -#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) -#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) -#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) -#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) -#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) -#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) -#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) -#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) -#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) -#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) -#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) -#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) -#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) -#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) -#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) -#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) -#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) -#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) -#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) -#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) -#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) -#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) -#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) -#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) -#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) -#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) -#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) -#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) -#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) -#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) - -/* CAN Controller 0 Accebfin_read_()tance Registers */ - -#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) -#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) -#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) -#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) -#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) -#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) -#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) -#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) -#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) -#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) -#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) -#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) -#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) -#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) -#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) -#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) -#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) -#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) -#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) -#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) -#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) -#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) -#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) -#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) -#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) -#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) -#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) -#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) -#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) -#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) -#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) -#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) -#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) - -/* CAN Controller 0 Mailbox Data Registers */ - -#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) -#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) -#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) -#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) -#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) -#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) -#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) -#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) -#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) -#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) -#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) -#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) -#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) -#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) -#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) -#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) -#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) -#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) -#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) -#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) -#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) -#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) -#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) -#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) -#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) -#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) -#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) -#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) -#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) -#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) -#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) -#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) -#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) -#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) -#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) -#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) -#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) -#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) -#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) -#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) -#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) -#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) -#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) -#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) -#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) -#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) -#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) -#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) -#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) -#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) -#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) -#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) -#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) -#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) -#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) -#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) -#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) -#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) -#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) -#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) -#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) -#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) -#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) -#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) -#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) -#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) -#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) -#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) -#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) -#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) -#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) -#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) -#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) -#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) -#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) -#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) -#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) -#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) -#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) -#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) -#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) -#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) -#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) -#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) -#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) -#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) -#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) -#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) -#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) -#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) -#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) -#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) -#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) -#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) -#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) -#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) -#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) -#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) -#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) -#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) -#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) -#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) -#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) -#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) -#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) -#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) -#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) -#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) -#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) -#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) -#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) -#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) -#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) -#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) -#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) -#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) -#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) -#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) -#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) -#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) -#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) -#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) -#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) -#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) -#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) -#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) -#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) -#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) -#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) - -/* CAN Controller 0 Mailbox Data Registers */ - -#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) -#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) -#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) -#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) -#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) -#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) -#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) -#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) -#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) -#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) -#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) -#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) -#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) -#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) -#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) -#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) -#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) -#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) -#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) -#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) -#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) -#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) -#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) -#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) -#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) -#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) -#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) -#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) -#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) -#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) -#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) -#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) -#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) -#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) -#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) -#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) -#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) -#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) -#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) -#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) -#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) -#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) -#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) -#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) -#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) -#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) -#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) -#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) -#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) -#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) -#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) -#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) -#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) -#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) -#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) -#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) -#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) -#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) -#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) -#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) -#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) -#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) -#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) -#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) -#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) -#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) -#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) -#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) -#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) -#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) -#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) -#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) -#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) -#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) -#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) -#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) -#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) -#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) -#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) -#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) -#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) -#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) -#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) -#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) -#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) -#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) -#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) -#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) -#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) -#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) -#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) -#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) -#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) -#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) -#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) -#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) -#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) -#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) -#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) -#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) -#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) -#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) -#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) -#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) -#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) -#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) -#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) -#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) -#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) -#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) -#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) -#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) -#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) -#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) -#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) -#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) -#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) -#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) -#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) -#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) -#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) -#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) -#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) -#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) -#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) -#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) -#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) -#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) -#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) - -/* UART3 Registers */ - -#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) -#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) -#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) -#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) -#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) -#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) -#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) -#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) -#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) -#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) -#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define bfin_read_UART3_THR() bfin_read16(UART3_THR) -#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) -#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) - -/* NFC Registers */ - -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) - -/* Counter Registers */ - -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) - -/* Security Registers */ - -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) - -/* DMA Peribfin_read_()heral Mux Register */ - -#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) -#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) - -/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ - -#endif /* _CDEF_BF54X_H */ - diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h deleted file mode 100644 index ae4b889e3606..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/defBF542.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF542_H -#define _DEF_BF542_H - -/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ -#include "defBF54x_base.h" - -/* The following are the #defines needed by ADSP-BF542 that are not in the common header */ - -/* ATAPI Registers */ - -#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ -#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ -#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ -#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ -#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ -#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ -#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ -#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ -#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ -#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ -#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ -#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ -#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ -#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ -#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ -#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ -#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ -#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ -#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ -#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ -#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ -#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ -#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ - -/* SDH Registers */ - -#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ -#define SDH_COMMAND 0xffc0390c /* SDH Command */ -#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ -#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ -#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ -#define SDH_STATUS 0xffc03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ -#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ -#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ -#define SDH_CFG 0xffc039c8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ -#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ - -/* USB Control Registers */ - -#define USB_FADDR 0xffc03c00 /* Function address register */ -#define USB_POWER 0xffc03c04 /* Power management register */ -#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xffc03c20 /* USB frame number */ -#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ - -/* USB Packet Control Registers */ - -#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* USB Endpoint FIFO Registers */ - -#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ - -/* USB OTG Control Registers */ - -#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ - -/* USB Phy Control Registers */ - -#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ - -/* (APHY_CNTRL is for ADI usage only) */ - -#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ - -/* (APHY_CALIB is for ADI usage only) */ - -#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ - -#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ - -/* USB Endpoint 0 Control Registers */ - -#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ - -/* USB Endpoint 1 Control Registers */ - -#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ - -/* USB Endpoint 2 Control Registers */ - -#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ - -/* USB Endpoint 3 Control Registers */ - -#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ - -/* USB Endpoint 4 Control Registers */ - -#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ - -/* USB Endpoint 5 Control Registers */ - -#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ - -/* USB Endpoint 6 Control Registers */ - -#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ - -/* USB Endpoint 7 Control Registers */ - -#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ - -/* USB Channel 0 Config Registers */ - -#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ -#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ - -/* USB Channel 1 Config Registers */ - -#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ -#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ - -/* USB Channel 2 Config Registers */ - -#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ -#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ - -/* USB Channel 3 Config Registers */ - -#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ -#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ - -/* USB Channel 4 Config Registers */ - -#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ -#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ - -/* USB Channel 5 Config Registers */ - -#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ -#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ - -/* USB Channel 6 Config Registers */ - -#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ -#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ - -/* USB Channel 7 Config Registers */ - -#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ -#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -/* Keypad Registers */ - -#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ -#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ -#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ -#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ -#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ -#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ - - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for KPAD_CTL */ - -#define KPAD_EN 0x1 /* Keypad Enable */ -#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ -#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ -#define KPAD_COLEN 0xe000 /* Column Enable Width */ - -/* Bit masks for KPAD_PRESCALE */ - -#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ - -/* Bit masks for KPAD_MSEL */ - -#define DBON_SCALE 0xff /* Debounce Scale Value */ -#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ - -/* Bit masks for KPAD_ROWCOL */ - -#define KPAD_ROW 0xff /* Rows Pressed */ -#define KPAD_COL 0xff00 /* Columns Pressed */ - -/* Bit masks for KPAD_STAT */ - -#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ -#define KPAD_PRESSED 0x8 /* Key press current status */ - -/* Bit masks for KPAD_SOFTEVAL */ - -#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ - -/* Bit masks for ATAPI_CONTROL */ - -#define PIO_START 0x1 /* Start PIO/Reg Op */ -#define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define XFER_DIR 0x8 /* Transfer Direction */ -#define IORDY_EN 0x10 /* IORDY Enable */ -#define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define SOFT_RST 0x40 /* Soft Reset */ -#define DEV_RST 0x80 /* Device Reset */ -#define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define END_ON_TERM 0x200 /* End/Terminate Select */ -#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ - -/* Bit masks for ATAPI_STATUS */ - -#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ - -/* Bit masks for ATAPI_DEV_ADDR */ - -#define DEV_ADDR 0x1f /* Device Address */ - -/* Bit masks for ATAPI_INT_MASK */ - -#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ - -/* Bit masks for ATAPI_INT_STATUS */ - -#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ - -/* Bit masks for ATAPI_LINE_STATUS */ - -#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define ATAPI_ADDR 0x70 /* ATAPI address line status */ -#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_SM_STATE */ - -#define PIO_CSTATE 0xf /* PIO mode state machine current state */ -#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ -#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ -#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_TERMINATE */ - -#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ - -/* Bit masks for ATAPI_REG_TIM_0 */ - -#define T2_REG 0xff /* End of cycle time for register access transfers */ -#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ - -/* Bit masks for ATAPI_PIO_TIM_0 */ - -#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ -#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ -#define T4_REG 0xf000 /* DIOW data hold */ - -/* Bit masks for ATAPI_PIO_TIM_1 */ - -#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ - -/* Bit masks for ATAPI_MULTI_TIM_0 */ - -#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ -#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ - -/* Bit masks for ATAPI_MULTI_TIM_1 */ - -#define TKW 0xff /* Selects DIOW negated pulsewidth */ -#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ - -/* Bit masks for ATAPI_MULTI_TIM_2 */ - -#define TH 0xff /* Selects DIOW data hold */ -#define TEOC 0xff00 /* Selects end of cycle for DMA */ - -/* Bit masks for ATAPI_ULTRA_TIM_0 */ - -#define TACK 0xff /* Selects setup and hold times for TACK */ -#define TENV 0xff00 /* Selects envelope time */ - -/* Bit masks for ATAPI_ULTRA_TIM_1 */ - -#define TDVS 0xff /* Selects data valid setup time */ -#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ - -/* Bit masks for ATAPI_ULTRA_TIM_2 */ - -#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ -#define TMLI 0xff00 /* Selects interlock time */ - -/* Bit masks for ATAPI_ULTRA_TIM_3 */ - -#define TZAH 0xff /* Selects minimum delay required for output */ -#define READY_PAUSE 0xff00 /* Selects ready to pause */ - -/* Bit masks for USB_FADDR */ - -#define FUNCTION_ADDRESS 0x7f /* Function address */ - -/* Bit masks for USB_POWER */ - -#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define RESUME_MODE 0x4 /* DMA Mode */ -#define RESET 0x8 /* Reset indicator */ -#define HS_MODE 0x10 /* High Speed mode indicator */ -#define HS_ENABLE 0x20 /* high Speed Enable */ -#define SOFT_CONN 0x40 /* Soft connect */ -#define ISO_UPDATE 0x80 /* Isochronous update */ - -/* Bit masks for USB_INTRTX */ - -#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ - -/* Bit masks for USB_INTRRX */ - -#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ - -/* Bit masks for USB_INTRTXE */ - -#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ - -/* Bit masks for USB_INTRRXE */ - -#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ - -/* Bit masks for USB_INTRUSB */ - -#define SUSPEND_B 0x1 /* Suspend indicator */ -#define RESUME_B 0x2 /* Resume indicator */ -#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define SOF_B 0x8 /* Start of frame */ -#define CONN_B 0x10 /* Connection indicator */ -#define DISCON_B 0x20 /* Disconnect indicator */ -#define SESSION_REQ_B 0x40 /* Session Request */ -#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ - -/* Bit masks for USB_INTRUSBE */ - -#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define RESUME_BE 0x2 /* Resume indicator int enable */ -#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define SOF_BE 0x8 /* Start of frame int enable */ -#define CONN_BE 0x10 /* Connection indicator int enable */ -#define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ - -/* Bit masks for USB_FRAME */ - -#define FRAME_NUMBER 0x7ff /* Frame number */ - -/* Bit masks for USB_INDEX */ - -#define SELECTED_ENDPOINT 0xf /* selected endpoint */ - -/* Bit masks for USB_GLOBAL_CTL */ - -#define GLOBAL_ENA 0x1 /* enables USB module */ -#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ - -/* Bit masks for USB_OTG_DEV_CTL */ - -#define SESSION 0x1 /* session indicator */ -#define HOST_REQ 0x2 /* Host negotiation request */ -#define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define VBUS0 0x8 /* Vbus level indicator[0] */ -#define VBUS1 0x10 /* Vbus level indicator[1] */ -#define LSDEV 0x20 /* Low-speed indicator */ -#define FSDEV 0x40 /* Full or High-speed indicator */ -#define B_DEVICE 0x80 /* A' or 'B' device indicator */ - -/* Bit masks for USB_OTG_VBUS_IRQ */ - -#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ - -/* Bit masks for USB_OTG_VBUS_MASK */ - -#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ - -/* Bit masks for USB_CSR0 */ - -#define RXPKTRDY 0x1 /* data packet receive indicator */ -#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define STALL_SENT 0x4 /* STALL handshake sent */ -#define DATAEND 0x8 /* Data end indicator */ -#define SETUPEND 0x10 /* Setup end */ -#define SENDSTALL 0x20 /* Send STALL handshake */ -#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define ERROR_H 0x10 /* timeout error indicator host mode */ -#define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ - -/* Bit masks for USB_COUNT0 */ - -#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ - -/* Bit masks for USB_NAKLIMIT0 */ - -#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ - -/* Bit masks for USB_TX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_RX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_TXCSR */ - -#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define ISO_T 0x4000 /* enable Isochronous transfers */ -#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define ERROR_TH 0x4 /* error condition host mode */ -#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ - -/* Bit masks for USB_TXCOUNT */ - -#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* Bit masks for USB_RXCSR */ - -#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define ISO_R 0x4000 /* enable Isochronous transfers */ -#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ - -/* Bit masks for USB_RXCOUNT */ - -#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ - -/* Bit masks for USB_TXTYPE */ - -#define TARGET_EP_NO_T 0xf /* EP number */ -#define PROTOCOL_T 0xc /* transfer type */ - -/* Bit masks for USB_TXINTERVAL */ - -#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ - -/* Bit masks for USB_RXTYPE */ - -#define TARGET_EP_NO_R 0xf /* EP number */ -#define PROTOCOL_R 0xc /* transfer type */ - -/* Bit masks for USB_RXINTERVAL */ - -#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ - -/* Bit masks for USB_DMA_INTERRUPT */ - -#define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define DMA7_INT 0x80 /* DMA7 pending interrupt */ - -/* Bit masks for USB_DMAxCONTROL */ - -#define DMA_ENA 0x1 /* DMA enable */ -#define DIRECTION 0x2 /* direction of DMA transfer */ -#define MODE 0x4 /* DMA Bus error */ -#define INT_ENA 0x8 /* Interrupt enable */ -#define EPNUM 0xf0 /* EP number */ -#define BUSERROR 0x100 /* DMA Bus error */ - -/* Bit masks for USB_DMAxADDRHIGH */ - -#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxADDRLOW */ - -#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTHIGH */ - -#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTLOW */ - -#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ - - -/* ******************************************* */ -/* MULTI BIT MACRO ENUMERATIONS */ -/* ******************************************* */ - - -#endif /* _DEF_BF542_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h deleted file mode 100644 index 018ebfc27f5a..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ /dev/null @@ -1,630 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF544_H -#define _DEF_BF544_H - -/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ -#include "defBF54x_base.h" - -/* The following are the #defines needed by ADSP-BF544 that are not in the common header */ - -/* Timer Registers */ - -#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ -#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ -#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ -#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ -#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ -#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ -#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ -#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ -#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ -#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ -#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ -#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ - -/* Timer Group of 3 Registers */ - -#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ -#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ -#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ - -/* EPPI0 Registers */ - -#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ -#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ -#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ -#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ -#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ -#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ - -/* Two Wire Interface Registers (TWI1) */ - -#define TWI1_REGBASE 0xffc02200 -#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ -#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ -#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ -#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ -#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ -#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ - -/* CAN Controller 1 Config 1 Registers */ - -#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ -#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ -#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ -#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ -#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ - -/* CAN Controller 1 Config 2 Registers */ - -#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ -#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ -#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ -#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ -#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ - -/* CAN Controller 1 Clock/Interrupt/Counter Registers */ - -#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ -#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ -#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ -#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ -#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ -#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ -#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ -#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ -#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ -#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ -#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ -#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ -#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ -#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ -#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ - -/* CAN Controller 1 Mailbox Acceptance Registers */ - -#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ - -/* CAN Controller 1 Mailbox Acceptance Registers */ - -#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ - -/* CAN Controller 1 Mailbox Data Registers */ - -#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ -#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ -#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ -#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ -#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ -#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ -#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ -#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ -#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ -#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ -#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ -#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ -#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ -#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ -#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ -#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ -#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ - -/* CAN Controller 1 Mailbox Data Registers */ - -#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ -#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ -#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ -#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ -#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ -#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ -#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ -#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ -#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ -#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ -#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ -#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ -#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ -#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ -#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ -#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ -#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ - -/* HOST Port Registers */ - -#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ -#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ -#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ - -/* Pixel Compositor (PIXC) Registers */ - -#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ -#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ -#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ -#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ -#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ -#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ -#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ -#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ -#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ -#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ -#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ -#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ -#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ -#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ -#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ - -/* Handshake MDMA 0 Registers */ - -#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ -#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ - -/* Handshake MDMA 1 Registers */ - -#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ -#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ - - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for PIXC_CTL */ - -#define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define OVR_A_EN 0x2 /* Overlay A Enable */ -#define OVR_B_EN 0x4 /* Overlay B Enable */ -#define IMG_FORM 0x8 /* Image Data Format */ -#define OVR_FORM 0x10 /* Overlay Data Format */ -#define OUT_FORM 0x20 /* Output Data Format */ -#define UDS_MOD 0x40 /* Resampling Mode */ -#define TC_EN 0x80 /* Transparent Color Enable */ -#define IMG_STAT 0x300 /* Image FIFO Status */ -#define OVR_STAT 0xc00 /* Overlay FIFO Status */ -#define WM_LVL 0x3000 /* FIFO Watermark Level */ - -/* Bit masks for PIXC_AHSTART */ - -#define A_HSTART 0xfff /* Horizontal Start Coordinates */ - -/* Bit masks for PIXC_AHEND */ - -#define A_HEND 0xfff /* Horizontal End Coordinates */ - -/* Bit masks for PIXC_AVSTART */ - -#define A_VSTART 0x3ff /* Vertical Start Coordinates */ - -/* Bit masks for PIXC_AVEND */ - -#define A_VEND 0x3ff /* Vertical End Coordinates */ - -/* Bit masks for PIXC_ATRANSP */ - -#define A_TRANSP 0xf /* Transparency Value */ - -/* Bit masks for PIXC_BHSTART */ - -#define B_HSTART 0xfff /* Horizontal Start Coordinates */ - -/* Bit masks for PIXC_BHEND */ - -#define B_HEND 0xfff /* Horizontal End Coordinates */ - -/* Bit masks for PIXC_BVSTART */ - -#define B_VSTART 0x3ff /* Vertical Start Coordinates */ - -/* Bit masks for PIXC_BVEND */ - -#define B_VEND 0x3ff /* Vertical End Coordinates */ - -/* Bit masks for PIXC_BTRANSP */ - -#define B_TRANSP 0xf /* Transparency Value */ - -/* Bit masks for PIXC_INTRSTAT */ - -#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ - -/* Bit masks for PIXC_RYCON */ - -#define A11 0x3ff /* A11 in the Coefficient Matrix */ -#define A12 0xffc00 /* A12 in the Coefficient Matrix */ -#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ -#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ - -/* Bit masks for PIXC_GUCON */ - -#define A21 0x3ff /* A21 in the Coefficient Matrix */ -#define A22 0xffc00 /* A22 in the Coefficient Matrix */ -#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ -#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ - -/* Bit masks for PIXC_BVCON */ - -#define A31 0x3ff /* A31 in the Coefficient Matrix */ -#define A32 0xffc00 /* A32 in the Coefficient Matrix */ -#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ -#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ - -/* Bit masks for PIXC_CCBIAS */ - -#define A14 0x3ff /* A14 in the Bias Vector */ -#define A24 0xffc00 /* A24 in the Bias Vector */ -#define A34 0x3ff00000 /* A34 in the Bias Vector */ - -/* Bit masks for PIXC_TC */ - -#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ -#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ -#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ - -/* Bit masks for TIMER_ENABLE1 */ - -#define TIMEN8 0x1 /* Timer 8 Enable */ -#define TIMEN9 0x2 /* Timer 9 Enable */ -#define TIMEN10 0x4 /* Timer 10 Enable */ - -/* Bit masks for TIMER_DISABLE1 */ - -#define TIMDIS8 0x1 /* Timer 8 Disable */ -#define TIMDIS9 0x2 /* Timer 9 Disable */ -#define TIMDIS10 0x4 /* Timer 10 Disable */ - -/* Bit masks for TIMER_STATUS1 */ - -#define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ - -/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ - -#endif /* _DEF_BF544_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h deleted file mode 100644 index 7cc7928a3c73..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ /dev/null @@ -1,1034 +0,0 @@ -/* - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF547_H -#define _DEF_BF547_H - -/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ -#include "defBF54x_base.h" - -/* The following are the #defines needed by ADSP-BF547 that are not in the common header */ - -/* Timer Registers */ - -#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ -#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ -#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ -#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ -#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ -#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ -#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ -#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ -#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ -#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ -#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ -#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ - -/* Timer Group of 3 Registers */ - -#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ -#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ -#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ - -/* SPORT0 Registers */ - -#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ -#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ -#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ -#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ -#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ -#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ -#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ -#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ - -/* EPPI0 Registers */ - -#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ -#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ -#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ -#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ -#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ -#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ - -/* UART2 Registers */ - -#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ -#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ -#define UART2_GCTL 0xffc02108 /* Global Control Register */ -#define UART2_LCR 0xffc0210c /* Line Control Register */ -#define UART2_MCR 0xffc02110 /* Modem Control Register */ -#define UART2_LSR 0xffc02114 /* Line Status Register */ -#define UART2_MSR 0xffc02118 /* Modem Status Register */ -#define UART2_SCR 0xffc0211c /* Scratch Register */ -#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ -#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ -#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ - -/* Two Wire Interface Registers (TWI1) */ - -#define TWI1_REGBASE 0xffc02200 -#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ -#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ -#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ -#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ -#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ -#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ - -/* SPI2 Registers */ - -#define SPI2_REGBASE 0xffc02400 -#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ -#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ -#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ -#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ -#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ -#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ -#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ - -/* ATAPI Registers */ - -#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ -#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ -#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ -#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ -#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ -#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ -#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ -#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ -#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ -#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ -#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ -#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ -#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ -#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ -#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ -#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ -#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ -#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ -#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ -#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ -#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ -#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ -#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ - -/* SDH Registers */ - -#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ -#define SDH_COMMAND 0xffc0390c /* SDH Command */ -#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ -#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ -#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ -#define SDH_STATUS 0xffc03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ -#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ -#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ -#define SDH_CFG 0xffc039c8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ -#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ - -/* HOST Port Registers */ - -#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ -#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ -#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ - -/* USB Control Registers */ - -#define USB_FADDR 0xffc03c00 /* Function address register */ -#define USB_POWER 0xffc03c04 /* Power management register */ -#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xffc03c20 /* USB frame number */ -#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ - -/* USB Packet Control Registers */ - -#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* USB Endpoint FIFO Registers */ - -#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ - -/* USB OTG Control Registers */ - -#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ - -/* USB Phy Control Registers */ - -#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ - -/* (APHY_CNTRL is for ADI usage only) */ - -#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ - -/* (APHY_CALIB is for ADI usage only) */ - -#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ - -#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ - -/* USB Endpoint 0 Control Registers */ - -#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ - -/* USB Endpoint 1 Control Registers */ - -#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ - -/* USB Endpoint 2 Control Registers */ - -#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ - -/* USB Endpoint 3 Control Registers */ - -#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ - -/* USB Endpoint 4 Control Registers */ - -#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ - -/* USB Endpoint 5 Control Registers */ - -#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ - -/* USB Endpoint 6 Control Registers */ - -#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ - -/* USB Endpoint 7 Control Registers */ - -#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ - -#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ - -/* USB Channel 0 Config Registers */ - -#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ -#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ - -/* USB Channel 1 Config Registers */ - -#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ -#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ - -/* USB Channel 2 Config Registers */ - -#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ -#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ - -/* USB Channel 3 Config Registers */ - -#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ -#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ - -/* USB Channel 4 Config Registers */ - -#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ -#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ - -/* USB Channel 5 Config Registers */ - -#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ -#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ - -/* USB Channel 6 Config Registers */ - -#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ -#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ - -/* USB Channel 7 Config Registers */ - -#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ -#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -/* Keypad Registers */ - -#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ -#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ -#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ -#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ -#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ -#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ - -/* Pixel Compositor (PIXC) Registers */ - -#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ -#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ -#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ -#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ -#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ -#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ -#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ -#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ -#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ -#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ -#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ -#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ -#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ -#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ -#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ - -/* Handshake MDMA 0 Registers */ - -#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ -#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ - -/* Handshake MDMA 1 Registers */ - -#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ -#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ - - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for PIXC_CTL */ - -#define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define OVR_A_EN 0x2 /* Overlay A Enable */ -#define OVR_B_EN 0x4 /* Overlay B Enable */ -#define IMG_FORM 0x8 /* Image Data Format */ -#define OVR_FORM 0x10 /* Overlay Data Format */ -#define OUT_FORM 0x20 /* Output Data Format */ -#define UDS_MOD 0x40 /* Resampling Mode */ -#define TC_EN 0x80 /* Transparent Color Enable */ -#define IMG_STAT 0x300 /* Image FIFO Status */ -#define OVR_STAT 0xc00 /* Overlay FIFO Status */ -#define WM_LVL 0x3000 /* FIFO Watermark Level */ - -/* Bit masks for PIXC_AHSTART */ - -#define A_HSTART 0xfff /* Horizontal Start Coordinates */ - -/* Bit masks for PIXC_AHEND */ - -#define A_HEND 0xfff /* Horizontal End Coordinates */ - -/* Bit masks for PIXC_AVSTART */ - -#define A_VSTART 0x3ff /* Vertical Start Coordinates */ - -/* Bit masks for PIXC_AVEND */ - -#define A_VEND 0x3ff /* Vertical End Coordinates */ - -/* Bit masks for PIXC_ATRANSP */ - -#define A_TRANSP 0xf /* Transparency Value */ - -/* Bit masks for PIXC_BHSTART */ - -#define B_HSTART 0xfff /* Horizontal Start Coordinates */ - -/* Bit masks for PIXC_BHEND */ - -#define B_HEND 0xfff /* Horizontal End Coordinates */ - -/* Bit masks for PIXC_BVSTART */ - -#define B_VSTART 0x3ff /* Vertical Start Coordinates */ - -/* Bit masks for PIXC_BVEND */ - -#define B_VEND 0x3ff /* Vertical End Coordinates */ - -/* Bit masks for PIXC_BTRANSP */ - -#define B_TRANSP 0xf /* Transparency Value */ - -/* Bit masks for PIXC_INTRSTAT */ - -#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ - -/* Bit masks for PIXC_RYCON */ - -#define A11 0x3ff /* A11 in the Coefficient Matrix */ -#define A12 0xffc00 /* A12 in the Coefficient Matrix */ -#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ -#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ - -/* Bit masks for PIXC_GUCON */ - -#define A21 0x3ff /* A21 in the Coefficient Matrix */ -#define A22 0xffc00 /* A22 in the Coefficient Matrix */ -#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ -#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ - -/* Bit masks for PIXC_BVCON */ - -#define A31 0x3ff /* A31 in the Coefficient Matrix */ -#define A32 0xffc00 /* A32 in the Coefficient Matrix */ -#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ -#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ - -/* Bit masks for PIXC_CCBIAS */ - -#define A14 0x3ff /* A14 in the Bias Vector */ -#define A24 0xffc00 /* A24 in the Bias Vector */ -#define A34 0x3ff00000 /* A34 in the Bias Vector */ - -/* Bit masks for PIXC_TC */ - -#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ -#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ -#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ - -/* Bit masks for KPAD_CTL */ - -#define KPAD_EN 0x1 /* Keypad Enable */ -#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ -#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ -#define KPAD_COLEN 0xe000 /* Column Enable Width */ - -/* Bit masks for KPAD_PRESCALE */ - -#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ - -/* Bit masks for KPAD_MSEL */ - -#define DBON_SCALE 0xff /* Debounce Scale Value */ -#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ - -/* Bit masks for KPAD_ROWCOL */ - -#define KPAD_ROW 0xff /* Rows Pressed */ -#define KPAD_COL 0xff00 /* Columns Pressed */ - -/* Bit masks for KPAD_STAT */ - -#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ -#define KPAD_PRESSED 0x8 /* Key press current status */ - -/* Bit masks for KPAD_SOFTEVAL */ - -#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ - -/* Bit masks for ATAPI_CONTROL */ - -#define PIO_START 0x1 /* Start PIO/Reg Op */ -#define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define XFER_DIR 0x8 /* Transfer Direction */ -#define IORDY_EN 0x10 /* IORDY Enable */ -#define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define SOFT_RST 0x40 /* Soft Reset */ -#define DEV_RST 0x80 /* Device Reset */ -#define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define END_ON_TERM 0x200 /* End/Terminate Select */ -#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ - -/* Bit masks for ATAPI_STATUS */ - -#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ - -/* Bit masks for ATAPI_DEV_ADDR */ - -#define DEV_ADDR 0x1f /* Device Address */ - -/* Bit masks for ATAPI_INT_MASK */ - -#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ - -/* Bit masks for ATAPI_INT_STATUS */ - -#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ - -/* Bit masks for ATAPI_LINE_STATUS */ - -#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define ATAPI_ADDR 0x70 /* ATAPI address line status */ -#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_SM_STATE */ - -#define PIO_CSTATE 0xf /* PIO mode state machine current state */ -#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ -#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ -#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_TERMINATE */ - -#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ - -/* Bit masks for ATAPI_REG_TIM_0 */ - -#define T2_REG 0xff /* End of cycle time for register access transfers */ -#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ - -/* Bit masks for ATAPI_PIO_TIM_0 */ - -#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ -#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ -#define T4_REG 0xf000 /* DIOW data hold */ - -/* Bit masks for ATAPI_PIO_TIM_1 */ - -#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ - -/* Bit masks for ATAPI_MULTI_TIM_0 */ - -#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ -#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ - -/* Bit masks for ATAPI_MULTI_TIM_1 */ - -#define TKW 0xff /* Selects DIOW negated pulsewidth */ -#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ - -/* Bit masks for ATAPI_MULTI_TIM_2 */ - -#define TH 0xff /* Selects DIOW data hold */ -#define TEOC 0xff00 /* Selects end of cycle for DMA */ - -/* Bit masks for ATAPI_ULTRA_TIM_0 */ - -#define TACK 0xff /* Selects setup and hold times for TACK */ -#define TENV 0xff00 /* Selects envelope time */ - -/* Bit masks for ATAPI_ULTRA_TIM_1 */ - -#define TDVS 0xff /* Selects data valid setup time */ -#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ - -/* Bit masks for ATAPI_ULTRA_TIM_2 */ - -#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ -#define TMLI 0xff00 /* Selects interlock time */ - -/* Bit masks for ATAPI_ULTRA_TIM_3 */ - -#define TZAH 0xff /* Selects minimum delay required for output */ -#define READY_PAUSE 0xff00 /* Selects ready to pause */ - -/* Bit masks for TIMER_ENABLE1 */ - -#define TIMEN8 0x1 /* Timer 8 Enable */ -#define TIMEN9 0x2 /* Timer 9 Enable */ -#define TIMEN10 0x4 /* Timer 10 Enable */ - -/* Bit masks for TIMER_DISABLE1 */ - -#define TIMDIS8 0x1 /* Timer 8 Disable */ -#define TIMDIS9 0x2 /* Timer 9 Disable */ -#define TIMDIS10 0x4 /* Timer 10 Disable */ - -/* Bit masks for TIMER_STATUS1 */ - -#define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ - -/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ - -/* Bit masks for USB_FADDR */ - -#define FUNCTION_ADDRESS 0x7f /* Function address */ - -/* Bit masks for USB_POWER */ - -#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define RESUME_MODE 0x4 /* DMA Mode */ -#define RESET 0x8 /* Reset indicator */ -#define HS_MODE 0x10 /* High Speed mode indicator */ -#define HS_ENABLE 0x20 /* high Speed Enable */ -#define SOFT_CONN 0x40 /* Soft connect */ -#define ISO_UPDATE 0x80 /* Isochronous update */ - -/* Bit masks for USB_INTRTX */ - -#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ - -/* Bit masks for USB_INTRRX */ - -#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ - -/* Bit masks for USB_INTRTXE */ - -#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ - -/* Bit masks for USB_INTRRXE */ - -#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ - -/* Bit masks for USB_INTRUSB */ - -#define SUSPEND_B 0x1 /* Suspend indicator */ -#define RESUME_B 0x2 /* Resume indicator */ -#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define SOF_B 0x8 /* Start of frame */ -#define CONN_B 0x10 /* Connection indicator */ -#define DISCON_B 0x20 /* Disconnect indicator */ -#define SESSION_REQ_B 0x40 /* Session Request */ -#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ - -/* Bit masks for USB_INTRUSBE */ - -#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define RESUME_BE 0x2 /* Resume indicator int enable */ -#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define SOF_BE 0x8 /* Start of frame int enable */ -#define CONN_BE 0x10 /* Connection indicator int enable */ -#define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ - -/* Bit masks for USB_FRAME */ - -#define FRAME_NUMBER 0x7ff /* Frame number */ - -/* Bit masks for USB_INDEX */ - -#define SELECTED_ENDPOINT 0xf /* selected endpoint */ - -/* Bit masks for USB_GLOBAL_CTL */ - -#define GLOBAL_ENA 0x1 /* enables USB module */ -#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ - -/* Bit masks for USB_OTG_DEV_CTL */ - -#define SESSION 0x1 /* session indicator */ -#define HOST_REQ 0x2 /* Host negotiation request */ -#define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define VBUS0 0x8 /* Vbus level indicator[0] */ -#define VBUS1 0x10 /* Vbus level indicator[1] */ -#define LSDEV 0x20 /* Low-speed indicator */ -#define FSDEV 0x40 /* Full or High-speed indicator */ -#define B_DEVICE 0x80 /* A' or 'B' device indicator */ - -/* Bit masks for USB_OTG_VBUS_IRQ */ - -#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ - -/* Bit masks for USB_OTG_VBUS_MASK */ - -#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ - -/* Bit masks for USB_CSR0 */ - -#define RXPKTRDY 0x1 /* data packet receive indicator */ -#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define STALL_SENT 0x4 /* STALL handshake sent */ -#define DATAEND 0x8 /* Data end indicator */ -#define SETUPEND 0x10 /* Setup end */ -#define SENDSTALL 0x20 /* Send STALL handshake */ -#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define ERROR_H 0x10 /* timeout error indicator host mode */ -#define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ - -/* Bit masks for USB_COUNT0 */ - -#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ - -/* Bit masks for USB_NAKLIMIT0 */ - -#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ - -/* Bit masks for USB_TX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_RX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_TXCSR */ - -#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define ISO_T 0x4000 /* enable Isochronous transfers */ -#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define ERROR_TH 0x4 /* error condition host mode */ -#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ - -/* Bit masks for USB_TXCOUNT */ - -#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ - -/* Bit masks for USB_RXCSR */ - -#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define ISO_R 0x4000 /* enable Isochronous transfers */ -#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ - -/* Bit masks for USB_RXCOUNT */ - -#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ - -/* Bit masks for USB_TXTYPE */ - -#define TARGET_EP_NO_T 0xf /* EP number */ -#define PROTOCOL_T 0xc /* transfer type */ - -/* Bit masks for USB_TXINTERVAL */ - -#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ - -/* Bit masks for USB_RXTYPE */ - -#define TARGET_EP_NO_R 0xf /* EP number */ -#define PROTOCOL_R 0xc /* transfer type */ - -/* Bit masks for USB_RXINTERVAL */ - -#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ - -/* Bit masks for USB_DMA_INTERRUPT */ - -#define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define DMA7_INT 0x80 /* DMA7 pending interrupt */ - -/* Bit masks for USB_DMAxCONTROL */ - -#define DMA_ENA 0x1 /* DMA enable */ -#define DIRECTION 0x2 /* direction of DMA transfer */ -#define MODE 0x4 /* DMA Bus error */ -#define INT_ENA 0x8 /* Interrupt enable */ -#define EPNUM 0xf0 /* EP number */ -#define BUSERROR 0x100 /* DMA Bus error */ - -/* Bit masks for USB_DMAxADDRHIGH */ - -#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxADDRLOW */ - -#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTHIGH */ - -#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ - -/* Bit masks for USB_DMAxCOUNTLOW */ - -#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ - -#endif /* _DEF_BF547_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h deleted file mode 100644 index 27f29481e283..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/defBF548.h +++ /dev/null @@ -1,399 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF548_H -#define _DEF_BF548_H - -/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ -#include "defBF54x_base.h" - -/* The BF548 is like the BF547, but has additional CANs */ -#include "defBF547.h" - -/* CAN Controller 1 Config 1 Registers */ - -#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ -#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ -#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ -#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ -#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ - -/* CAN Controller 1 Config 2 Registers */ - -#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ -#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ -#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ -#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ -#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ - -/* CAN Controller 1 Clock/Interrupt/Counter Registers */ - -#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ -#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ -#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ -#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ -#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ -#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ -#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ -#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ -#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ -#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ -#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ -#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ -#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ -#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ -#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ - -/* CAN Controller 1 Mailbox Acceptance Registers */ - -#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ - -/* CAN Controller 1 Mailbox Acceptance Registers */ - -#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ - -/* CAN Controller 1 Mailbox Data Registers */ - -#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ -#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ -#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ -#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ -#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ -#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ -#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ -#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ -#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ -#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ -#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ -#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ -#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ -#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ -#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ -#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ -#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ - -/* CAN Controller 1 Mailbox Data Registers */ - -#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ -#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ -#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ -#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ -#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ -#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ -#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ -#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ -#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ -#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ -#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ -#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ -#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ -#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ -#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ -#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ -#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ - -#endif /* _DEF_BF548_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h deleted file mode 100644 index ac569fc12972..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/defBF549.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF549_H -#define _DEF_BF549_H - -/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ -#include "defBF54x_base.h" - -/* The BF549 is like the BF544, but has MXVR */ -#include "defBF547.h" - -/* MXVR Registers */ - -#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */ -#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */ -#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */ -#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */ -#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */ -#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */ -#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */ -#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */ -#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */ -#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */ -#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */ -#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */ -#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */ -#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */ - -/* MXVR Allocation Table Registers */ - -#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */ -#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */ -#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */ -#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */ -#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */ -#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */ -#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */ -#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */ -#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */ -#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */ -#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */ -#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */ -#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */ -#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */ -#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */ - -/* MXVR Channel Assign Registers */ - -#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ -#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */ -#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ -#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ -#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ -#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */ -#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ -#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ - -/* MXVR DMA0 Registers */ - -#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */ -#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */ -#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */ -#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */ -#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */ - -/* MXVR DMA1 Registers */ - -#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */ -#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */ -#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */ -#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */ -#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */ - -/* MXVR DMA2 Registers */ - -#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */ -#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */ -#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */ -#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */ -#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */ - -/* MXVR DMA3 Registers */ - -#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */ -#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */ -#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */ -#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */ -#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */ - -/* MXVR DMA4 Registers */ - -#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */ -#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */ -#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */ -#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */ -#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */ - -/* MXVR DMA5 Registers */ - -#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */ -#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */ -#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */ -#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */ -#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */ - -/* MXVR DMA6 Registers */ - -#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */ -#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */ -#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */ -#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */ -#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */ - -/* MXVR DMA7 Registers */ - -#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */ -#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */ -#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */ -#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */ -#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */ - -/* MXVR Asynch Packet Registers */ - -#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */ -#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */ -#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */ -#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */ -#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */ - -/* MXVR Control Message Registers */ - -#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */ -#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */ -#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */ -#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */ -#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */ - -/* MXVR Remote Read Registers */ - -#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */ -#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */ - -/* MXVR Pattern Data Registers */ - -#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */ -#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */ -#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */ -#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */ - -/* MXVR Frame Counter Registers */ - -#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */ -#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */ - -/* MXVR Routing Table Registers */ - -#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */ -#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */ -#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */ -#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */ -#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */ -#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */ -#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */ -#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */ -#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */ -#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */ -#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */ -#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */ -#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */ -#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */ -#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */ - -/* MXVR Counter-Clock-Control Registers */ - -#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */ -#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */ -#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */ -#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */ -#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ -#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ - -#endif /* _DEF_BF549_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h deleted file mode 100644 index 8f6e1925779d..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ /dev/null @@ -1,2294 +0,0 @@ -/* - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF54X_H -#define _DEF_BF54X_H - - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ -/* ************************************************************** */ - -/* PLL Registers */ - -#define PLL_CTL 0xffc00000 /* PLL Control Register */ -#define PLL_DIV 0xffc00004 /* PLL Divisor Register */ -#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xffc0000c /* PLL Status Register */ -#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */ - -/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ - -#define CHIPID 0xffc00014 -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ - -#define SWRST 0xffc00100 /* Software Reset Register */ -#define SYSCR 0xffc00104 /* System Configuration register */ - -/* SIC Registers */ - -#define SIC_RVECT 0xffc00108 -#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ -#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ -#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ -#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ -#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ -#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */ -#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ -#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */ -#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */ -#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */ -#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */ -#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */ -#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */ -#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */ -#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */ -#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */ - -/* Watchdog Timer Registers */ - -#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */ - -/* RTC Registers */ - -#define RTC_STAT 0xffc00300 /* RTC Status Register */ -#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */ -#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */ - -/* UART0 Registers */ - -#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */ -#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */ -#define UART0_GCTL 0xffc00408 /* Global Control Register */ -#define UART0_LCR 0xffc0040c /* Line Control Register */ -#define UART0_MCR 0xffc00410 /* Modem Control Register */ -#define UART0_LSR 0xffc00414 /* Line Status Register */ -#define UART0_MSR 0xffc00418 /* Modem Status Register */ -#define UART0_SCR 0xffc0041c /* Scratch Register */ -#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */ -#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */ -#define UART0_THR 0xffc00428 /* Transmit Hold Register */ -#define UART0_RBR 0xffc0042c /* Receive Buffer Register */ - -/* SPI0 Registers */ - -#define SPI0_REGBASE 0xffc00500 -#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ -#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ -#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */ -#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */ - -/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ - -/* Two Wire Interface Registers (TWI0) */ - -#define TWI0_REGBASE 0xffc00700 -#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ -#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ -#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */ -#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ -#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */ - -/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ - -/* SPORT1 Registers */ - -#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */ -#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */ -#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */ -#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */ -#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */ -#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */ -#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */ -#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */ - -/* Asynchronous Memory Control Registers */ - -#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */ -#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */ -#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */ -#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */ -#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */ -#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */ - -/* DDR Memory Control Registers */ - -#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */ -#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */ -#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */ -#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */ -#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */ -#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */ -#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */ -#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */ - -/* DDR BankRead and Write Count Registers */ - -#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */ -#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */ -#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */ -#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */ -#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */ -#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */ -#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */ -#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */ -#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */ -#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */ -#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */ -#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */ -#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */ -#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */ -#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */ -#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */ -#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */ -#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */ -#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */ -#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */ -#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */ -#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */ -#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */ -#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */ -#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */ - -/* DMAC0 Registers */ - -#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ - -/* DMA Channel 0 Registers */ - -#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */ - -/* DMA Channel 1 Registers */ - -#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */ - -/* DMA Channel 2 Registers */ - -#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */ - -/* DMA Channel 3 Registers */ - -#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */ - -/* DMA Channel 4 Registers */ - -#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */ - -/* DMA Channel 5 Registers */ - -#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */ - -/* DMA Channel 6 Registers */ - -#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */ - -/* DMA Channel 7 Registers */ - -#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */ - -/* DMA Channel 8 Registers */ - -#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */ - -/* DMA Channel 9 Registers */ - -#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */ - -/* DMA Channel 10 Registers */ - -#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */ - -/* DMA Channel 11 Registers */ - -#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */ - -/* MDMA Stream 0 Registers */ - -#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */ - -/* MDMA Stream 1 Registers */ - -#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */ - -/* UART3 Registers */ - -#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ -#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ -#define UART3_GCTL 0xffc03108 /* Global Control Register */ -#define UART3_LCR 0xffc0310c /* Line Control Register */ -#define UART3_MCR 0xffc03110 /* Modem Control Register */ -#define UART3_LSR 0xffc03114 /* Line Status Register */ -#define UART3_MSR 0xffc03118 /* Modem Status Register */ -#define UART3_SCR 0xffc0311c /* Scratch Register */ -#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ -#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ -#define UART3_THR 0xffc03128 /* Transmit Hold Register */ -#define UART3_RBR 0xffc0312c /* Receive Buffer Register */ - -/* EPPI1 Registers */ - -#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */ -#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */ -#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */ -#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */ -#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */ -#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */ -#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */ -#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */ -#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */ -#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */ - -/* Port Interrupt 0 Registers (32-bit) */ - -#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */ -#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */ -#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */ -#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */ -#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */ -#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */ -#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */ -#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */ - -/* Port Interrupt 1 Registers (32-bit) */ - -#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */ -#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */ -#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */ -#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */ -#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */ -#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */ -#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */ -#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */ - -/* Port Interrupt 2 Registers (32-bit) */ - -#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */ -#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */ -#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */ -#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */ -#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */ -#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */ -#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */ -#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */ - -/* Port Interrupt 3 Registers (32-bit) */ - -#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */ -#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */ -#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */ -#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */ -#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */ -#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */ -#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */ -#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */ - -/* Port A Registers */ - -#define PORTA_FER 0xffc014c0 /* Function Enable Register */ -#define PORTA 0xffc014c4 /* GPIO Data Register */ -#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */ -#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */ -#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */ -#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */ -#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */ -#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */ - -/* Port B Registers */ - -#define PORTB_FER 0xffc014e0 /* Function Enable Register */ -#define PORTB 0xffc014e4 /* GPIO Data Register */ -#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */ -#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */ -#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */ -#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */ -#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */ -#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */ - -/* Port C Registers */ - -#define PORTC_FER 0xffc01500 /* Function Enable Register */ -#define PORTC 0xffc01504 /* GPIO Data Register */ -#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */ -#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */ -#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */ -#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */ -#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */ -#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */ - -/* Port D Registers */ - -#define PORTD_FER 0xffc01520 /* Function Enable Register */ -#define PORTD 0xffc01524 /* GPIO Data Register */ -#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */ -#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */ -#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */ -#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */ -#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */ -#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */ - -/* Port E Registers */ - -#define PORTE_FER 0xffc01540 /* Function Enable Register */ -#define PORTE 0xffc01544 /* GPIO Data Register */ -#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */ -#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */ -#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */ -#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */ -#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */ -#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */ - -/* Port F Registers */ - -#define PORTF_FER 0xffc01560 /* Function Enable Register */ -#define PORTF 0xffc01564 /* GPIO Data Register */ -#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */ -#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */ -#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */ -#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */ -#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */ -#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */ - -/* Port G Registers */ - -#define PORTG_FER 0xffc01580 /* Function Enable Register */ -#define PORTG 0xffc01584 /* GPIO Data Register */ -#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */ -#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */ -#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */ -#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */ -#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */ -#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */ - -/* Port H Registers */ - -#define PORTH_FER 0xffc015a0 /* Function Enable Register */ -#define PORTH 0xffc015a4 /* GPIO Data Register */ -#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */ -#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */ -#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */ -#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */ -#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */ -#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */ - -/* Port I Registers */ - -#define PORTI_FER 0xffc015c0 /* Function Enable Register */ -#define PORTI 0xffc015c4 /* GPIO Data Register */ -#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */ -#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */ -#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */ -#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */ -#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */ -#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */ - -/* Port J Registers */ - -#define PORTJ_FER 0xffc015e0 /* Function Enable Register */ -#define PORTJ 0xffc015e4 /* GPIO Data Register */ -#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */ -#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */ -#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */ -#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */ -#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */ -#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */ - -/* PWM Timer Registers */ - -#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */ -#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */ - -/* Timer Group of 8 */ - -#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */ -#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */ -#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */ - -/* DMAC1 Registers */ - -#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ - -/* DMA Channel 12 Registers */ - -#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */ - -/* DMA Channel 13 Registers */ - -#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */ - -/* DMA Channel 14 Registers */ - -#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */ - -/* DMA Channel 15 Registers */ - -#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */ - -/* DMA Channel 16 Registers */ - -#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */ - -/* DMA Channel 17 Registers */ - -#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */ - -/* DMA Channel 18 Registers */ - -#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */ - -/* DMA Channel 19 Registers */ - -#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */ - -/* DMA Channel 20 Registers */ - -#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */ -#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */ -#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */ -#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */ -#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */ -#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */ -#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */ -#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */ -#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */ -#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */ -#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */ -#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */ -#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */ - -/* DMA Channel 21 Registers */ - -#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */ -#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */ -#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */ -#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */ -#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */ -#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */ -#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */ -#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */ -#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */ -#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */ -#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */ -#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */ -#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */ - -/* DMA Channel 22 Registers */ - -#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */ -#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */ -#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */ -#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */ -#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */ -#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */ -#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */ -#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */ -#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */ -#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */ -#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */ -#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */ -#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */ - -/* DMA Channel 23 Registers */ - -#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */ -#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */ -#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */ -#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */ -#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */ -#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */ -#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */ -#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */ -#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */ -#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */ -#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */ -#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */ -#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */ - -/* MDMA Stream 2 Registers */ - -#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */ -#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */ -#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */ -#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */ -#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */ -#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */ -#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */ -#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */ -#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */ -#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */ -#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */ -#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */ -#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */ -#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */ -#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */ -#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */ -#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */ - -/* MDMA Stream 3 Registers */ - -#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */ -#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */ -#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */ -#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */ -#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */ -#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */ -#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */ -#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */ -#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */ -#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */ -#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */ -#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */ -#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */ -#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */ -#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */ -#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */ -#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */ - -/* UART1 Registers */ - -#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */ -#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */ -#define UART1_GCTL 0xffc02008 /* Global Control Register */ -#define UART1_LCR 0xffc0200c /* Line Control Register */ -#define UART1_MCR 0xffc02010 /* Modem Control Register */ -#define UART1_LSR 0xffc02014 /* Line Status Register */ -#define UART1_MSR 0xffc02018 /* Modem Status Register */ -#define UART1_SCR 0xffc0201c /* Scratch Register */ -#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */ -#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */ -#define UART1_THR 0xffc02028 /* Transmit Hold Register */ -#define UART1_RBR 0xffc0202c /* Receive Buffer Register */ - -/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ - -/* SPI1 Registers */ - -#define SPI1_REGBASE 0xffc02300 -#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ -#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ -#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */ -#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */ - -/* SPORT2 Registers */ - -#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */ -#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */ -#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */ -#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */ -#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */ -#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */ -#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */ -#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */ -#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */ -#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */ -#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */ - -/* SPORT3 Registers */ - -#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */ -#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */ -#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */ -#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */ -#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */ -#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */ -#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */ -#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */ -#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */ -#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */ -#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */ - -/* EPPI2 Registers */ - -#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */ -#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */ -#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */ -#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */ -#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */ -#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */ -#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */ -#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */ -#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */ -#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */ - -/* CAN Controller 0 Config 1 Registers */ - -#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */ -#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */ -#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */ -#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */ -#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ - -/* CAN Controller 0 Config 2 Registers */ - -#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */ -#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */ -#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */ -#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */ -#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ - -/* CAN Controller 0 Clock/Interrupt/Counter Registers */ - -#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */ -#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */ -#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */ -#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */ -#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */ -#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */ -#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */ -#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */ -#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */ -#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */ -#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */ -#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */ -#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */ -#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */ -#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */ - -/* CAN Controller 0 Acceptance Registers */ - -#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ - -/* CAN Controller 0 Acceptance Registers */ - -#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ - -/* CAN Controller 0 Mailbox Data Registers */ - -#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */ -#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */ -#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */ -#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */ -#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */ -#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */ -#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */ -#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */ -#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */ -#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */ -#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */ -#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */ -#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */ -#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */ -#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */ -#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */ -#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */ - -/* CAN Controller 0 Mailbox Data Registers */ - -#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */ -#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */ -#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */ -#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */ -#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */ -#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */ -#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */ -#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */ -#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */ -#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */ -#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */ -#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */ -#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */ -#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */ -#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */ -#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */ -#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */ - -/* UART3 Registers */ - -#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ -#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ -#define UART3_GCTL 0xffc03108 /* Global Control Register */ -#define UART3_LCR 0xffc0310c /* Line Control Register */ -#define UART3_MCR 0xffc03110 /* Modem Control Register */ -#define UART3_LSR 0xffc03114 /* Line Status Register */ -#define UART3_MSR 0xffc03118 /* Modem Status Register */ -#define UART3_SCR 0xffc0311c /* Scratch Register */ -#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ -#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ -#define UART3_THR 0xffc03128 /* Transmit Hold Register */ -#define UART3_RBR 0xffc0312c /* Receive Buffer Register */ - -/* NFC Registers */ - -#define NFC_CTL 0xffc03b00 /* NAND Control Register */ -#define NFC_STAT 0xffc03b04 /* NAND Status Register */ -#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */ -#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */ -#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */ -#define NFC_READ 0xffc03b2c /* NAND Read Data Register */ -#define NFC_ADDR 0xffc03b40 /* NAND Address Register */ -#define NFC_CMD 0xffc03b44 /* NAND Command Register */ -#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */ - -/* Counter Registers */ - -#define CNT_CONFIG 0xffc04200 /* Configuration Register */ -#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */ -#define CNT_STATUS 0xffc04208 /* Status Register */ -#define CNT_COMMAND 0xffc0420c /* Command Register */ -#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */ -#define CNT_COUNTER 0xffc04214 /* Counter Register */ -#define CNT_MAX 0xffc04218 /* Maximal Count Register */ -#define CNT_MIN 0xffc0421c /* Minimal Count Register */ - -/* OTP/FUSE Registers */ - -#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */ -#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */ - -/* Security Registers */ - -#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */ -#define SECURE_CONTROL 0xffc04324 /* Secure Control */ -#define SECURE_STATUS 0xffc04328 /* Secure Status */ - -/* DMA Peripheral Mux Register */ - -#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */ - -/* OTP Read/Write Data Buffer Registers */ - -#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ - -/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */ - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ - -/* Bit masks for SIC_IAR0 */ - -#define PLL_WAKEUP 0x1 /* PLL Wakeup */ - -/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ - -#define DMA0_ERR 0x2 /* DMA Controller 0 Error */ -#define EPPI0_ERR 0x4 /* EPPI0 Error */ -#define SPORT0_ERR 0x8 /* SPORT0 Error */ -#define SPORT1_ERR 0x10 /* SPORT1 Error */ -#define SPI0_ERR 0x20 /* SPI0 Error */ -#define UART0_ERR 0x40 /* UART0 Error */ -#define RTC 0x80 /* Real-Time Clock */ -#define DMA12 0x100 /* DMA Channel 12 */ -#define DMA0 0x200 /* DMA Channel 0 */ -#define DMA1 0x400 /* DMA Channel 1 */ -#define DMA2 0x800 /* DMA Channel 2 */ -#define DMA3 0x1000 /* DMA Channel 3 */ -#define DMA4 0x2000 /* DMA Channel 4 */ -#define DMA6 0x4000 /* DMA Channel 6 */ -#define DMA7 0x8000 /* DMA Channel 7 */ -#define PINT0 0x80000 /* Pin Interrupt 0 */ -#define PINT1 0x100000 /* Pin Interrupt 1 */ -#define MDMA0 0x200000 /* Memory DMA Stream 0 */ -#define MDMA1 0x400000 /* Memory DMA Stream 1 */ -#define WDOG 0x800000 /* Watchdog Timer */ -#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ -#define SPORT2_ERR 0x2000000 /* SPORT2 Error */ -#define SPORT3_ERR 0x4000000 /* SPORT3 Error */ -#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */ -#define SPI1_ERR 0x10000000 /* SPI1 Error */ -#define SPI2_ERR 0x20000000 /* SPI2 Error */ -#define UART1_ERR 0x40000000 /* UART1 Error */ -#define UART2_ERR 0x80000000 /* UART2 Error */ - -/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ - -#define CAN0_ERR 0x1 /* CAN0 Error */ -#define DMA18 0x2 /* DMA Channel 18 */ -#define DMA19 0x4 /* DMA Channel 19 */ -#define DMA20 0x8 /* DMA Channel 20 */ -#define DMA21 0x10 /* DMA Channel 21 */ -#define DMA13 0x20 /* DMA Channel 13 */ -#define DMA14 0x40 /* DMA Channel 14 */ -#define DMA5 0x80 /* DMA Channel 5 */ -#define DMA23 0x100 /* DMA Channel 23 */ -#define DMA8 0x200 /* DMA Channel 8 */ -#define DMA9 0x400 /* DMA Channel 9 */ -#define DMA10 0x800 /* DMA Channel 10 */ -#define DMA11 0x1000 /* DMA Channel 11 */ -#define TWI0 0x2000 /* TWI0 */ -#define TWI1 0x4000 /* TWI1 */ -#define CAN0_RX 0x8000 /* CAN0 Receive */ -#define CAN0_TX 0x10000 /* CAN0 Transmit */ -#define MDMA2 0x20000 /* Memory DMA Stream 0 */ -#define MDMA3 0x40000 /* Memory DMA Stream 1 */ -#define MXVR_STAT 0x80000 /* MXVR Status */ -#define MXVR_CM 0x100000 /* MXVR Control Message */ -#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ -#define EPPI1_ERR 0x400000 /* EPPI1 Error */ -#define EPPI2_ERR 0x800000 /* EPPI2 Error */ -#define UART3_ERR 0x1000000 /* UART3 Error */ -#define HOST_ERR 0x2000000 /* Host DMA Port Error */ -#define USB_ERR 0x4000000 /* USB Error */ -#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */ -#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */ -#define ATAPI_ERR 0x20000000 /* ATAPI Error */ -#define CAN1_ERR 0x40000000 /* CAN1 Error */ -#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ -#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ -#define DMAR0 0x80000000 /* DMAR0 Block */ -#define DMAR1 0x80000000 /* DMAR1 Block */ - -/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ - -#define DMA15 0x1 /* DMA Channel 15 */ -#define DMA16 0x2 /* DMA Channel 16 */ -#define DMA17 0x4 /* DMA Channel 17 */ -#define DMA22 0x8 /* DMA Channel 22 */ -#define CNT 0x10 /* Counter */ -#define KEY 0x20 /* Keypad */ -#define CAN1_RX 0x40 /* CAN1 Receive */ -#define CAN1_TX 0x80 /* CAN1 Transmit */ -#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */ -#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */ -#define USB_EINT 0x400 /* USB Exception */ -#define USB_INT0 0x800 /* USB Interrupt 0 */ -#define USB_INT1 0x1000 /* USB Interrupt 1 */ -#define USB_INT2 0x2000 /* USB Interrupt 2 */ -#define USB_DMAINT 0x4000 /* USB DMA */ -#define OTPSEC 0x8000 /* OTP Access Complete */ -#define TIMER0 0x400000 /* Timer 0 */ -#define TIMER1 0x800000 /* Timer 1 */ -#define TIMER2 0x1000000 /* Timer 2 */ -#define TIMER3 0x2000000 /* Timer 3 */ -#define TIMER4 0x4000000 /* Timer 4 */ -#define TIMER5 0x8000000 /* Timer 5 */ -#define TIMER6 0x10000000 /* Timer 6 */ -#define TIMER7 0x20000000 /* Timer 7 */ -#define PINT2 0x40000000 /* Pin Interrupt 2 */ -#define PINT3 0x80000000 /* Pin Interrupt 3 */ - -/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ - -#define CTYPE 0x40 /* DMA Channel Type */ -#define PMAP 0xf000 /* Peripheral Mapped To This Channel */ - -/* Bit masks for DMACx_TC_PER */ - -#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ -#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ -#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ -#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ - -/* Bit masks for DMACx_TC_CNT */ - -#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ -#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ -#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */ -#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */ - -/* Bit masks for DMAC1_PERIMUX */ - -#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ - - -/* Bit masks for EBIU_AMBCTL0 */ - -#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ -#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ -#define B0TT 0xc /* Bank 0 transition time */ -#define B0ST 0x30 /* Bank 0 Setup time */ -#define B0HT 0xc0 /* Bank 0 Hold time */ -#define B0RAT 0xf00 /* Bank 0 Read access time */ -#define B0WAT 0xf000 /* Bank 0 write access time */ -#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ -#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ -#define B1TT 0xc0000 /* Bank 1 transition time */ -#define B1ST 0x300000 /* Bank 1 Setup time */ -#define B1HT 0xc00000 /* Bank 1 Hold time */ -#define B1RAT 0xf000000 /* Bank 1 Read access time */ -#define B1WAT 0xf0000000 /* Bank 1 write access time */ - -/* Bit masks for EBIU_AMBCTL1 */ - -#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ -#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ -#define B2TT 0xc /* Bank 2 transition time */ -#define B2ST 0x30 /* Bank 2 Setup time */ -#define B2HT 0xc0 /* Bank 2 Hold time */ -#define B2RAT 0xf00 /* Bank 2 Read access time */ -#define B2WAT 0xf000 /* Bank 2 write access time */ -#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ -#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ -#define B3TT 0xc0000 /* Bank 3 transition time */ -#define B3ST 0x300000 /* Bank 3 Setup time */ -#define B3HT 0xc00000 /* Bank 3 Hold time */ -#define B3RAT 0xf000000 /* Bank 3 Read access time */ -#define B3WAT 0xf0000000 /* Bank 3 write access time */ - -/* Bit masks for EBIU_MBSCTL */ - -#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */ -#define AMSB1CTL 0xc /* Async Memory Bank 1 select */ -#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */ -#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */ - -/* Bit masks for EBIU_MODE */ - -#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */ -#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */ -#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */ -#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */ - -/* Bit masks for EBIU_FCTL */ - -#define TESTSETLOCK 0x1 /* Test set lock */ -#define BCLK 0x6 /* Burst clock frequency */ -#define PGWS 0x38 /* Page wait states */ -#define PGSZ 0x40 /* Page size */ -#define RDDL 0x380 /* Read data delay */ - -/* Bit masks for EBIU_ARBSTAT */ - -#define ARBSTAT 0x1 /* Arbitration status */ -#define BGSTAT 0x2 /* Bus grant status */ - -/* Bit masks for EBIU_DDRCTL0 */ - -#define TREFI 0x3fff /* Refresh Interval */ -#define TRFC 0x3c000 /* Auto-refresh command period */ -#define TRP 0x3c0000 /* Pre charge-to-active command period */ -#define TRAS 0x3c00000 /* Min Active-to-pre charge time */ -#define TRC 0x3c000000 /* Active-to-active time */ -#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */ -#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */ -#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */ -#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */ -#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */ - -/* Bit masks for EBIU_DDRCTL1 */ - -#define TRCD 0xf /* Active-to-Read/write delay */ -#define TMRD 0xf0 /* Mode register set to active */ -#define TWR 0x300 /* Write Recovery time */ -#define DDRDATWIDTH 0x3000 /* DDR data width */ -#define EXTBANKS 0xc000 /* External banks */ -#define DDRDEVWIDTH 0x30000 /* DDR device width */ -#define DDRDEVSIZE 0xc0000 /* DDR device size */ -#define TWTR 0xf0000000 /* Write-to-read delay */ -#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */ -#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */ -#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */ -#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */ -#define DDR_DATWIDTH 0x2000 /* DDR data width */ -#define EXTBANK_1 0 /* 1 external bank */ -#define EXTBANK_2 0x4000 /* 2 external banks */ -#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */ -#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */ -#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */ -#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */ -#define DEVWD_4 0 /* DDR Device Width = 4 Bits */ -#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */ -#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */ - -/* Bit masks for EBIU_DDRCTL2 */ - -#define BURSTLENGTH 0x7 /* Burst length */ -#define CASLATENCY 0x70 /* CAS latency */ -#define DLLRESET 0x100 /* DLL Reset */ -#define REGE 0x1000 /* Register mode enable */ -#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */ -#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */ -#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */ -#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */ - -/* Bit masks for EBIU_DDRCTL3 */ - -#define PASR 0x7 /* Partial array self-refresh */ - -/* Bit masks for EBIU_DDRQUE */ - -#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */ -#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */ -#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ -#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ -#define DEB1_URGENT 0x1000 /* DEB1 Urgent */ -#define DEB2_URGENT 0x2000 /* DEB2 Urgent */ -#define DEB3_URGENT 0x4000 /* DEB3 Urgent */ - -/* Bit masks for EBIU_ERRMST */ - -#define DEB1_ERROR 0x1 /* DEB1 Error */ -#define DEB2_ERROR 0x2 /* DEB2 Error */ -#define DEB3_ERROR 0x4 /* DEB3 Error */ -#define CORE_ERROR 0x8 /* Core error */ -#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ -#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ -#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ -#define CORE_MERROR 0x80 /* Core Error (2nd) */ - -/* Bit masks for EBIU_RSTCTL */ - -#define DDRSRESET 0x1 /* DDR soft reset */ -#define PFTCHSRESET 0x4 /* DDR prefetch reset */ -#define SRREQ 0x8 /* Self-refresh request */ -#define SRACK 0x10 /* Self-refresh acknowledge */ -#define MDDRENABLE 0x20 /* Mobile DDR enable */ - -/* Bit masks for EBIU_DDRMCEN */ - -#define B0WCENABLE 0x1 /* Bank 0 write count enable */ -#define B1WCENABLE 0x2 /* Bank 1 write count enable */ -#define B2WCENABLE 0x4 /* Bank 2 write count enable */ -#define B3WCENABLE 0x8 /* Bank 3 write count enable */ -#define B4WCENABLE 0x10 /* Bank 4 write count enable */ -#define B5WCENABLE 0x20 /* Bank 5 write count enable */ -#define B6WCENABLE 0x40 /* Bank 6 write count enable */ -#define B7WCENABLE 0x80 /* Bank 7 write count enable */ -#define B0RCENABLE 0x100 /* Bank 0 read count enable */ -#define B1RCENABLE 0x200 /* Bank 1 read count enable */ -#define B2RCENABLE 0x400 /* Bank 2 read count enable */ -#define B3RCENABLE 0x800 /* Bank 3 read count enable */ -#define B4RCENABLE 0x1000 /* Bank 4 read count enable */ -#define B5RCENABLE 0x2000 /* Bank 5 read count enable */ -#define B6RCENABLE 0x4000 /* Bank 6 read count enable */ -#define B7RCENABLE 0x8000 /* Bank 7 read count enable */ -#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ -#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ -#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ -#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ -#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ -#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ -#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ -#define GCCONTROL 0x3000000 /* DDR Grant Count Control */ - -/* Bit masks for EBIU_DDRMCCL */ - -#define CB0WCOUNT 0x1 /* Clear write count 0 */ -#define CB1WCOUNT 0x2 /* Clear write count 1 */ -#define CB2WCOUNT 0x4 /* Clear write count 2 */ -#define CB3WCOUNT 0x8 /* Clear write count 3 */ -#define CB4WCOUNT 0x10 /* Clear write count 4 */ -#define CB5WCOUNT 0x20 /* Clear write count 5 */ -#define CB6WCOUNT 0x40 /* Clear write count 6 */ -#define CB7WCOUNT 0x80 /* Clear write count 7 */ -#define CBRCOUNT 0x100 /* Clear read count 0 */ -#define CB1RCOUNT 0x200 /* Clear read count 1 */ -#define CB2RCOUNT 0x400 /* Clear read count 2 */ -#define CB3RCOUNT 0x800 /* Clear read count 3 */ -#define CB4RCOUNT 0x1000 /* Clear read count 4 */ -#define CB5RCOUNT 0x2000 /* Clear read count 5 */ -#define CB6RCOUNT 0x4000 /* Clear read count 6 */ -#define CB7RCOUNT 0x8000 /* Clear read count 7 */ -#define CRACOUNT 0x10000 /* Clear row activation count */ -#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ -#define CARCOUNT 0x40000 /* Clear auto-refresh count */ -#define CG0COUNT 0x100000 /* Clear grant count 0 */ -#define CG1COUNT 0x200000 /* Clear grant count 1 */ -#define CG2COUNT 0x400000 /* Clear grant count 2 */ -#define CG3COUNT 0x800000 /* Clear grant count 3 */ - -/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ - -#define Px0 0x1 /* GPIO 0 */ -#define Px1 0x2 /* GPIO 1 */ -#define Px2 0x4 /* GPIO 2 */ -#define Px3 0x8 /* GPIO 3 */ -#define Px4 0x10 /* GPIO 4 */ -#define Px5 0x20 /* GPIO 5 */ -#define Px6 0x40 /* GPIO 6 */ -#define Px7 0x80 /* GPIO 7 */ -#define Px8 0x100 /* GPIO 8 */ -#define Px9 0x200 /* GPIO 9 */ -#define Px10 0x400 /* GPIO 10 */ -#define Px11 0x800 /* GPIO 11 */ -#define Px12 0x1000 /* GPIO 12 */ -#define Px13 0x2000 /* GPIO 13 */ -#define Px14 0x4000 /* GPIO 14 */ -#define Px15 0x8000 /* GPIO 15 */ - -/* Bit masks for PORTA_MUX - PORTJ_MUX */ - -#define PxM0 0x3 /* GPIO Mux 0 */ -#define PxM1 0xc /* GPIO Mux 1 */ -#define PxM2 0x30 /* GPIO Mux 2 */ -#define PxM3 0xc0 /* GPIO Mux 3 */ -#define PxM4 0x300 /* GPIO Mux 4 */ -#define PxM5 0xc00 /* GPIO Mux 5 */ -#define PxM6 0x3000 /* GPIO Mux 6 */ -#define PxM7 0xc000 /* GPIO Mux 7 */ -#define PxM8 0x30000 /* GPIO Mux 8 */ -#define PxM9 0xc0000 /* GPIO Mux 9 */ -#define PxM10 0x300000 /* GPIO Mux 10 */ -#define PxM11 0xc00000 /* GPIO Mux 11 */ -#define PxM12 0x3000000 /* GPIO Mux 12 */ -#define PxM13 0xc000000 /* GPIO Mux 13 */ -#define PxM14 0x30000000 /* GPIO Mux 14 */ -#define PxM15 0xc0000000 /* GPIO Mux 15 */ - - -/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ - -#define IB0 0x1 /* Interrupt Bit 0 */ -#define IB1 0x2 /* Interrupt Bit 1 */ -#define IB2 0x4 /* Interrupt Bit 2 */ -#define IB3 0x8 /* Interrupt Bit 3 */ -#define IB4 0x10 /* Interrupt Bit 4 */ -#define IB5 0x20 /* Interrupt Bit 5 */ -#define IB6 0x40 /* Interrupt Bit 6 */ -#define IB7 0x80 /* Interrupt Bit 7 */ -#define IB8 0x100 /* Interrupt Bit 8 */ -#define IB9 0x200 /* Interrupt Bit 9 */ -#define IB10 0x400 /* Interrupt Bit 10 */ -#define IB11 0x800 /* Interrupt Bit 11 */ -#define IB12 0x1000 /* Interrupt Bit 12 */ -#define IB13 0x2000 /* Interrupt Bit 13 */ -#define IB14 0x4000 /* Interrupt Bit 14 */ -#define IB15 0x8000 /* Interrupt Bit 15 */ - -/* Bit masks for TIMERx_CONFIG */ - -#define TMODE 0x3 /* Timer Mode */ -#define PULSE_HI 0x4 /* Pulse Polarity */ -#define PERIOD_CNT 0x8 /* Period Count */ -#define IRQ_ENA 0x10 /* Interrupt Request Enable */ -#define TIN_SEL 0x20 /* Timer Input Select */ -#define OUT_DIS 0x40 /* Output Pad Disable */ -#define CLK_SEL 0x80 /* Timer Clock Select */ -#define TOGGLE_HI 0x100 /* Toggle Mode */ -#define EMU_RUN 0x200 /* Emulation Behavior Select */ -#define ERR_TYP 0xc000 /* Error Type */ - -/* Bit masks for TIMER_ENABLE0 */ - -#define TIMEN0 0x1 /* Timer 0 Enable */ -#define TIMEN1 0x2 /* Timer 1 Enable */ -#define TIMEN2 0x4 /* Timer 2 Enable */ -#define TIMEN3 0x8 /* Timer 3 Enable */ -#define TIMEN4 0x10 /* Timer 4 Enable */ -#define TIMEN5 0x20 /* Timer 5 Enable */ -#define TIMEN6 0x40 /* Timer 6 Enable */ -#define TIMEN7 0x80 /* Timer 7 Enable */ - -/* Bit masks for TIMER_DISABLE0 */ - -#define TIMDIS0 0x1 /* Timer 0 Disable */ -#define TIMDIS1 0x2 /* Timer 1 Disable */ -#define TIMDIS2 0x4 /* Timer 2 Disable */ -#define TIMDIS3 0x8 /* Timer 3 Disable */ -#define TIMDIS4 0x10 /* Timer 4 Disable */ -#define TIMDIS5 0x20 /* Timer 5 Disable */ -#define TIMDIS6 0x40 /* Timer 6 Disable */ -#define TIMDIS7 0x80 /* Timer 7 Disable */ - -/* Bit masks for TIMER_STATUS0 */ - -#define TIMIL0 0x1 /* Timer 0 Interrupt */ -#define TIMIL1 0x2 /* Timer 1 Interrupt */ -#define TIMIL2 0x4 /* Timer 2 Interrupt */ -#define TIMIL3 0x8 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ -#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x10000 /* Timer 4 Interrupt */ -#define TIMIL5 0x20000 /* Timer 5 Interrupt */ -#define TIMIL6 0x40000 /* Timer 6 Interrupt */ -#define TIMIL7 0x80000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Bit masks for SECURE_SYSSWT */ - -#define EMUDABL 0x1 /* Emulation Disable. */ -#define RSTDABL 0x2 /* Reset Disable */ -#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ -#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ -#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ -#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define EMUOVR 0x4000 /* Emulation Override */ -#define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define L2DABL 0x70000 /* L2 Memory Disable. */ - -/* Bit masks for SECURE_CONTROL */ - -#define SECURE0 0x1 /* SECURE 0 */ -#define SECURE1 0x2 /* SECURE 1 */ -#define SECURE2 0x4 /* SECURE 2 */ -#define SECURE3 0x8 /* SECURE 3 */ - -/* Bit masks for SECURE_STATUS */ - -#define SECMODE 0x3 /* Secured Mode Control State */ -#define NMI 0x4 /* Non Maskable Interrupt */ -#define AFVALID 0x8 /* Authentication Firmware Valid */ -#define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define SECSTAT 0xe0 /* Secure Status */ - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* Bit masks for EPPIx_STATUS */ - -#define CFIFO_ERR 0x1 /* Chroma FIFO Error */ -#define YFIFO_ERR 0x2 /* Luma FIFO Error */ -#define LTERR_OVR 0x4 /* Line Track Overflow */ -#define LTERR_UNDR 0x8 /* Line Track Underflow */ -#define FTERR_OVR 0x10 /* Frame Track Overflow */ -#define FTERR_UNDR 0x20 /* Frame Track Underflow */ -#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ -#define DMA1URQ 0x80 /* DMA1 Urgent Request */ -#define DMA0URQ 0x100 /* DMA0 Urgent Request */ -#define ERR_DET 0x4000 /* Preamble Error Detected */ -#define FLD 0x8000 /* Field */ - -/* Bit masks for EPPIx_CONTROL */ - -#define EPPI_EN 0x1 /* Enable */ -#define EPPI_DIR 0x2 /* Direction */ -#define XFR_TYPE 0xc /* Operating Mode */ -#define FS_CFG 0x30 /* Frame Sync Configuration */ -#define FLD_SEL 0x40 /* Field Select/Trigger */ -#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ -#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ -#define ICLKGEN 0x200 /* Internal Clock Generation */ -#define IFSGEN 0x400 /* Internal Frame Sync Generation */ -#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ -#define POLS 0x6000 /* Frame Sync Polarity */ -#define DLENGTH 0x38000 /* Data Length */ -#define SKIP_EN 0x40000 /* Skip Enable */ -#define SKIP_EO 0x80000 /* Skip Even or Odd */ -#define PACKEN 0x100000 /* Packing/Unpacking Enable */ -#define SWAPEN 0x200000 /* Swap Enable */ -#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ -#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ -#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ -#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ -#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ -#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ -#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ - -#define DLEN_8 (0 << 15) /* 000 - 8 bits */ -#define DLEN_10 (1 << 15) /* 001 - 10 bits */ -#define DLEN_12 (2 << 15) /* 010 - 12 bits */ -#define DLEN_14 (3 << 15) /* 011 - 14 bits */ -#define DLEN_16 (4 << 15) /* 100 - 16 bits */ -#define DLEN_18 (5 << 15) /* 101 - 18 bits */ -#define DLEN_24 (6 << 15) /* 110 - 24 bits */ - - -/* Bit masks for EPPIx_FS2W_LVB */ - -#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ -#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */ -#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */ -#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */ - -/* Bit masks for EPPIx_FS2W_LAVF */ - -#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */ -#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */ - -/* Bit masks for EPPIx_CLIP */ - -#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */ -#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */ -#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ -#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ - - -/* ******************************************* */ -/* MULTI BIT MACRO ENUMERATIONS */ -/* ******************************************* */ - -/* BCODE bit field options (SYSCFG register) */ - -#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ -#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ -#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ -#define BCODE_NOBOOT 0x0030 /* always perform full boot */ - -/* TMODE in TIMERx_CONFIG bit field options */ - -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 - -/* PINTx Register Bit Definitions */ - -#define PIQ0 0x00000001 -#define PIQ1 0x00000002 -#define PIQ2 0x00000004 -#define PIQ3 0x00000008 - -#define PIQ4 0x00000010 -#define PIQ5 0x00000020 -#define PIQ6 0x00000040 -#define PIQ7 0x00000080 - -#define PIQ8 0x00000100 -#define PIQ9 0x00000200 -#define PIQ10 0x00000400 -#define PIQ11 0x00000800 - -#define PIQ12 0x00001000 -#define PIQ13 0x00002000 -#define PIQ14 0x00004000 -#define PIQ15 0x00008000 - -#define PIQ16 0x00010000 -#define PIQ17 0x00020000 -#define PIQ18 0x00040000 -#define PIQ19 0x00080000 - -#define PIQ20 0x00100000 -#define PIQ21 0x00200000 -#define PIQ22 0x00400000 -#define PIQ23 0x00800000 - -#define PIQ24 0x01000000 -#define PIQ25 0x02000000 -#define PIQ26 0x04000000 -#define PIQ27 0x08000000 - -#define PIQ28 0x10000000 -#define PIQ29 0x20000000 -#define PIQ30 0x40000000 -#define PIQ31 0x80000000 - -/* Port Muxing Bit Fields for PORTx_MUX Registers */ - -#define MUX0 0x00000003 -#define MUX0_0 0x00000000 -#define MUX0_1 0x00000001 -#define MUX0_2 0x00000002 -#define MUX0_3 0x00000003 - -#define MUX1 0x0000000C -#define MUX1_0 0x00000000 -#define MUX1_1 0x00000004 -#define MUX1_2 0x00000008 -#define MUX1_3 0x0000000C - -#define MUX2 0x00000030 -#define MUX2_0 0x00000000 -#define MUX2_1 0x00000010 -#define MUX2_2 0x00000020 -#define MUX2_3 0x00000030 - -#define MUX3 0x000000C0 -#define MUX3_0 0x00000000 -#define MUX3_1 0x00000040 -#define MUX3_2 0x00000080 -#define MUX3_3 0x000000C0 - -#define MUX4 0x00000300 -#define MUX4_0 0x00000000 -#define MUX4_1 0x00000100 -#define MUX4_2 0x00000200 -#define MUX4_3 0x00000300 - -#define MUX5 0x00000C00 -#define MUX5_0 0x00000000 -#define MUX5_1 0x00000400 -#define MUX5_2 0x00000800 -#define MUX5_3 0x00000C00 - -#define MUX6 0x00003000 -#define MUX6_0 0x00000000 -#define MUX6_1 0x00001000 -#define MUX6_2 0x00002000 -#define MUX6_3 0x00003000 - -#define MUX7 0x0000C000 -#define MUX7_0 0x00000000 -#define MUX7_1 0x00004000 -#define MUX7_2 0x00008000 -#define MUX7_3 0x0000C000 - -#define MUX8 0x00030000 -#define MUX8_0 0x00000000 -#define MUX8_1 0x00010000 -#define MUX8_2 0x00020000 -#define MUX8_3 0x00030000 - -#define MUX9 0x000C0000 -#define MUX9_0 0x00000000 -#define MUX9_1 0x00040000 -#define MUX9_2 0x00080000 -#define MUX9_3 0x000C0000 - -#define MUX10 0x00300000 -#define MUX10_0 0x00000000 -#define MUX10_1 0x00100000 -#define MUX10_2 0x00200000 -#define MUX10_3 0x00300000 - -#define MUX11 0x00C00000 -#define MUX11_0 0x00000000 -#define MUX11_1 0x00400000 -#define MUX11_2 0x00800000 -#define MUX11_3 0x00C00000 - -#define MUX12 0x03000000 -#define MUX12_0 0x00000000 -#define MUX12_1 0x01000000 -#define MUX12_2 0x02000000 -#define MUX12_3 0x03000000 - -#define MUX13 0x0C000000 -#define MUX13_0 0x00000000 -#define MUX13_1 0x04000000 -#define MUX13_2 0x08000000 -#define MUX13_3 0x0C000000 - -#define MUX14 0x30000000 -#define MUX14_0 0x00000000 -#define MUX14_1 0x10000000 -#define MUX14_2 0x20000000 -#define MUX14_3 0x30000000 - -#define MUX15 0xC0000000 -#define MUX15_0 0x00000000 -#define MUX15_1 0x40000000 -#define MUX15_2 0x80000000 -#define MUX15_3 0xC0000000 - -#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \ - ((((b15)&3) << 30) | \ - (((b14)&3) << 28) | \ - (((b13)&3) << 26) | \ - (((b12)&3) << 24) | \ - (((b11)&3) << 22) | \ - (((b10)&3) << 20) | \ - (((b9) &3) << 18) | \ - (((b8) &3) << 16) | \ - (((b7) &3) << 14) | \ - (((b6) &3) << 12) | \ - (((b5) &3) << 10) | \ - (((b4) &3) << 8) | \ - (((b3) &3) << 6) | \ - (((b2) &3) << 4) | \ - (((b1) &3) << 2) | \ - (((b0) &3))) - -/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */ - -#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */ -#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */ -#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */ -#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */ -#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */ -#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */ -#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */ -#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */ -#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */ -#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */ -#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */ -#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */ - -/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */ - -#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */ -#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */ -#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */ -#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */ -#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */ -#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */ -#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ -#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ - -#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ -#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ -#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ -#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ -#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */ -#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */ -#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ -#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ - -#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ -#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ -#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ -#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ -#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ -#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ -#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ -#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ - -#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ -#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ -#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ -#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ -#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ -#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ -#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ -#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ - -#endif /* _DEF_BF54X_H */ diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h deleted file mode 100644 index 1a1091b071fd..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/dma.h +++ /dev/null @@ -1,72 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define CH_SPORT0_RX 0 -#define CH_SPORT0_TX 1 -#define CH_SPORT1_RX 2 -#define CH_SPORT1_TX 3 -#define CH_SPI0 4 -#define CH_SPI1 5 -#define CH_UART0_RX 6 -#define CH_UART0_TX 7 -#define CH_UART1_RX 8 -#define CH_UART1_TX 9 -#define CH_ATAPI_RX 10 -#define CH_ATAPI_TX 11 -#define CH_EPPI0 12 -#define CH_EPPI1 13 -#define CH_EPPI2 14 -#define CH_PIXC_IMAGE 15 -#define CH_PIXC_OVERLAY 16 -#define CH_PIXC_OUTPUT 17 -#define CH_SPORT2_RX 18 -#define CH_SPORT2_TX 19 -#define CH_SPORT3_RX 20 -#define CH_SPORT3_TX 21 -#define CH_SDH 22 -#define CH_NFC 22 -#define CH_SPI2 23 - -#if defined(CONFIG_UART2_DMA_RX_ON_DMA13) -#define CH_UART2_RX 13 -#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */ -#define CH_UART2_TX 14 -#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */ -#else /* Default USE SPORT2's DMA Channel */ -#define CH_UART2_RX 18 -#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ -#define CH_UART2_TX 19 -#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ -#endif - -#if defined(CONFIG_UART3_DMA_RX_ON_DMA15) -#define CH_UART3_RX 15 -#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */ -#define CH_UART3_TX 16 -#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */ -#else /* Default USE SPORT3's DMA Channel */ -#define CH_UART3_RX 20 -#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ -#define CH_UART3_TX 21 -#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ -#endif - -#define CH_MEM_STREAM0_DEST 24 -#define CH_MEM_STREAM0_SRC 25 -#define CH_MEM_STREAM1_DEST 26 -#define CH_MEM_STREAM1_SRC 27 -#define CH_MEM_STREAM2_DEST 28 -#define CH_MEM_STREAM2_SRC 29 -#define CH_MEM_STREAM3_DEST 30 -#define CH_MEM_STREAM3_SRC 31 - -#define MAX_DMA_CHANNELS 32 - -#endif diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h deleted file mode 100644 index 006da1edcf84..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/gpio.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define GPIO_PA0 0 -#define GPIO_PA1 1 -#define GPIO_PA2 2 -#define GPIO_PA3 3 -#define GPIO_PA4 4 -#define GPIO_PA5 5 -#define GPIO_PA6 6 -#define GPIO_PA7 7 -#define GPIO_PA8 8 -#define GPIO_PA9 9 -#define GPIO_PA10 10 -#define GPIO_PA11 11 -#define GPIO_PA12 12 -#define GPIO_PA13 13 -#define GPIO_PA14 14 -#define GPIO_PA15 15 -#define GPIO_PB0 16 -#define GPIO_PB1 17 -#define GPIO_PB2 18 -#define GPIO_PB3 19 -#define GPIO_PB4 20 -#define GPIO_PB5 21 -#define GPIO_PB6 22 -#define GPIO_PB7 23 -#define GPIO_PB8 24 -#define GPIO_PB9 25 -#define GPIO_PB10 26 -#define GPIO_PB11 27 -#define GPIO_PB12 28 -#define GPIO_PB13 29 -#define GPIO_PB14 30 -#define GPIO_PB15 31 /* N/A */ -#define GPIO_PC0 32 -#define GPIO_PC1 33 -#define GPIO_PC2 34 -#define GPIO_PC3 35 -#define GPIO_PC4 36 -#define GPIO_PC5 37 -#define GPIO_PC6 38 -#define GPIO_PC7 39 -#define GPIO_PC8 40 -#define GPIO_PC9 41 -#define GPIO_PC10 42 -#define GPIO_PC11 43 -#define GPIO_PC12 44 -#define GPIO_PC13 45 -#define GPIO_PC14 46 /* N/A */ -#define GPIO_PC15 47 /* N/A */ -#define GPIO_PD0 48 -#define GPIO_PD1 49 -#define GPIO_PD2 50 -#define GPIO_PD3 51 -#define GPIO_PD4 52 -#define GPIO_PD5 53 -#define GPIO_PD6 54 -#define GPIO_PD7 55 -#define GPIO_PD8 56 -#define GPIO_PD9 57 -#define GPIO_PD10 58 -#define GPIO_PD11 59 -#define GPIO_PD12 60 -#define GPIO_PD13 61 -#define GPIO_PD14 62 -#define GPIO_PD15 63 -#define GPIO_PE0 64 -#define GPIO_PE1 65 -#define GPIO_PE2 66 -#define GPIO_PE3 67 -#define GPIO_PE4 68 -#define GPIO_PE5 69 -#define GPIO_PE6 70 -#define GPIO_PE7 71 -#define GPIO_PE8 72 -#define GPIO_PE9 73 -#define GPIO_PE10 74 -#define GPIO_PE11 75 -#define GPIO_PE12 76 -#define GPIO_PE13 77 -#define GPIO_PE14 78 -#define GPIO_PE15 79 -#define GPIO_PF0 80 -#define GPIO_PF1 81 -#define GPIO_PF2 82 -#define GPIO_PF3 83 -#define GPIO_PF4 84 -#define GPIO_PF5 85 -#define GPIO_PF6 86 -#define GPIO_PF7 87 -#define GPIO_PF8 88 -#define GPIO_PF9 89 -#define GPIO_PF10 90 -#define GPIO_PF11 91 -#define GPIO_PF12 92 -#define GPIO_PF13 93 -#define GPIO_PF14 94 -#define GPIO_PF15 95 -#define GPIO_PG0 96 -#define GPIO_PG1 97 -#define GPIO_PG2 98 -#define GPIO_PG3 99 -#define GPIO_PG4 100 -#define GPIO_PG5 101 -#define GPIO_PG6 102 -#define GPIO_PG7 103 -#define GPIO_PG8 104 -#define GPIO_PG9 105 -#define GPIO_PG10 106 -#define GPIO_PG11 107 -#define GPIO_PG12 108 -#define GPIO_PG13 109 -#define GPIO_PG14 110 -#define GPIO_PG15 111 -#define GPIO_PH0 112 -#define GPIO_PH1 113 -#define GPIO_PH2 114 -#define GPIO_PH3 115 -#define GPIO_PH4 116 -#define GPIO_PH5 117 -#define GPIO_PH6 118 -#define GPIO_PH7 119 -#define GPIO_PH8 120 -#define GPIO_PH9 121 -#define GPIO_PH10 122 -#define GPIO_PH11 123 -#define GPIO_PH12 124 -#define GPIO_PH13 125 -#define GPIO_PH14 126 /* N/A */ -#define GPIO_PH15 127 /* N/A */ -#define GPIO_PI0 128 -#define GPIO_PI1 129 -#define GPIO_PI2 130 -#define GPIO_PI3 131 -#define GPIO_PI4 132 -#define GPIO_PI5 133 -#define GPIO_PI6 134 -#define GPIO_PI7 135 -#define GPIO_PI8 136 -#define GPIO_PI9 137 -#define GPIO_PI10 138 -#define GPIO_PI11 139 -#define GPIO_PI12 140 -#define GPIO_PI13 141 -#define GPIO_PI14 142 -#define GPIO_PI15 143 -#define GPIO_PJ0 144 -#define GPIO_PJ1 145 -#define GPIO_PJ2 146 -#define GPIO_PJ3 147 -#define GPIO_PJ4 148 -#define GPIO_PJ5 149 -#define GPIO_PJ6 150 -#define GPIO_PJ7 151 -#define GPIO_PJ8 152 -#define GPIO_PJ9 153 -#define GPIO_PJ10 154 -#define GPIO_PJ11 155 -#define GPIO_PJ12 156 -#define GPIO_PJ13 157 -#define GPIO_PJ14 158 /* N/A */ -#define GPIO_PJ15 159 /* N/A */ - -#define MAX_BLACKFIN_GPIOS 160 - -#define BFIN_GPIO_PINT 1 -#define NR_PINT_SYS_IRQS 4 -#define NR_PINTS 160 - -#ifndef __ASSEMBLY__ - -struct gpio_port_t { - unsigned short port_fer; - unsigned short dummy1; - unsigned short data; - unsigned short dummy2; - unsigned short data_set; - unsigned short dummy3; - unsigned short data_clear; - unsigned short dummy4; - unsigned short dir_set; - unsigned short dummy5; - unsigned short dir_clear; - unsigned short dummy6; - unsigned short inen; - unsigned short dummy7; - unsigned int port_mux; -}; - -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h deleted file mode 100644 index cf7cb725cfa2..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BF548_IRQ_H_ -#define _BF548_IRQ_H_ - -#include - -#define NR_PERI_INTS (3 * 32) - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ -#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ -#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ -#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ -#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ -#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ -#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ -#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ -#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ -#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ -#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ -#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ -#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ -#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ -#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ -#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ -#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ -#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ -#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ -#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ -#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ -#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */ -#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ -#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ -#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ -#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ -#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ -#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ -#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ -#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ -#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ -#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ -#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ -#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ -#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ -#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ -#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ -#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ -#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ -#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ -#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ -#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ -#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ -#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ -#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ -#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ -#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ -#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ -#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ -#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ -#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ -#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ -#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ -#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ -#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ -#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ -#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ -#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */ -#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */ -#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ -#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ -#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ -#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ -#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ -#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ -#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ -#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ -#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ -#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ -#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ -#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ -#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ -#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ -#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ -#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ -#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ -#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ -#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ -#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ -#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ -#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ -#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ -#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ -#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ -#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ -#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ - -#define SYS_IRQS IRQ_PINT3 - -#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) -#define IRQ_PA0 BFIN_PA_IRQ(0) -#define IRQ_PA1 BFIN_PA_IRQ(1) -#define IRQ_PA2 BFIN_PA_IRQ(2) -#define IRQ_PA3 BFIN_PA_IRQ(3) -#define IRQ_PA4 BFIN_PA_IRQ(4) -#define IRQ_PA5 BFIN_PA_IRQ(5) -#define IRQ_PA6 BFIN_PA_IRQ(6) -#define IRQ_PA7 BFIN_PA_IRQ(7) -#define IRQ_PA8 BFIN_PA_IRQ(8) -#define IRQ_PA9 BFIN_PA_IRQ(9) -#define IRQ_PA10 BFIN_PA_IRQ(10) -#define IRQ_PA11 BFIN_PA_IRQ(11) -#define IRQ_PA12 BFIN_PA_IRQ(12) -#define IRQ_PA13 BFIN_PA_IRQ(13) -#define IRQ_PA14 BFIN_PA_IRQ(14) -#define IRQ_PA15 BFIN_PA_IRQ(15) - -#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) -#define IRQ_PB0 BFIN_PB_IRQ(0) -#define IRQ_PB1 BFIN_PB_IRQ(1) -#define IRQ_PB2 BFIN_PB_IRQ(2) -#define IRQ_PB3 BFIN_PB_IRQ(3) -#define IRQ_PB4 BFIN_PB_IRQ(4) -#define IRQ_PB5 BFIN_PB_IRQ(5) -#define IRQ_PB6 BFIN_PB_IRQ(6) -#define IRQ_PB7 BFIN_PB_IRQ(7) -#define IRQ_PB8 BFIN_PB_IRQ(8) -#define IRQ_PB9 BFIN_PB_IRQ(9) -#define IRQ_PB10 BFIN_PB_IRQ(10) -#define IRQ_PB11 BFIN_PB_IRQ(11) -#define IRQ_PB12 BFIN_PB_IRQ(12) -#define IRQ_PB13 BFIN_PB_IRQ(13) -#define IRQ_PB14 BFIN_PB_IRQ(14) -#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ - -#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) -#define IRQ_PC0 BFIN_PC_IRQ(0) -#define IRQ_PC1 BFIN_PC_IRQ(1) -#define IRQ_PC2 BFIN_PC_IRQ(2) -#define IRQ_PC3 BFIN_PC_IRQ(3) -#define IRQ_PC4 BFIN_PC_IRQ(4) -#define IRQ_PC5 BFIN_PC_IRQ(5) -#define IRQ_PC6 BFIN_PC_IRQ(6) -#define IRQ_PC7 BFIN_PC_IRQ(7) -#define IRQ_PC8 BFIN_PC_IRQ(8) -#define IRQ_PC9 BFIN_PC_IRQ(9) -#define IRQ_PC10 BFIN_PC_IRQ(10) -#define IRQ_PC11 BFIN_PC_IRQ(11) -#define IRQ_PC12 BFIN_PC_IRQ(12) -#define IRQ_PC13 BFIN_PC_IRQ(13) -#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ -#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ - -#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) -#define IRQ_PD0 BFIN_PD_IRQ(0) -#define IRQ_PD1 BFIN_PD_IRQ(1) -#define IRQ_PD2 BFIN_PD_IRQ(2) -#define IRQ_PD3 BFIN_PD_IRQ(3) -#define IRQ_PD4 BFIN_PD_IRQ(4) -#define IRQ_PD5 BFIN_PD_IRQ(5) -#define IRQ_PD6 BFIN_PD_IRQ(6) -#define IRQ_PD7 BFIN_PD_IRQ(7) -#define IRQ_PD8 BFIN_PD_IRQ(8) -#define IRQ_PD9 BFIN_PD_IRQ(9) -#define IRQ_PD10 BFIN_PD_IRQ(10) -#define IRQ_PD11 BFIN_PD_IRQ(11) -#define IRQ_PD12 BFIN_PD_IRQ(12) -#define IRQ_PD13 BFIN_PD_IRQ(13) -#define IRQ_PD14 BFIN_PD_IRQ(14) -#define IRQ_PD15 BFIN_PD_IRQ(15) - -#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) -#define IRQ_PE0 BFIN_PE_IRQ(0) -#define IRQ_PE1 BFIN_PE_IRQ(1) -#define IRQ_PE2 BFIN_PE_IRQ(2) -#define IRQ_PE3 BFIN_PE_IRQ(3) -#define IRQ_PE4 BFIN_PE_IRQ(4) -#define IRQ_PE5 BFIN_PE_IRQ(5) -#define IRQ_PE6 BFIN_PE_IRQ(6) -#define IRQ_PE7 BFIN_PE_IRQ(7) -#define IRQ_PE8 BFIN_PE_IRQ(8) -#define IRQ_PE9 BFIN_PE_IRQ(9) -#define IRQ_PE10 BFIN_PE_IRQ(10) -#define IRQ_PE11 BFIN_PE_IRQ(11) -#define IRQ_PE12 BFIN_PE_IRQ(12) -#define IRQ_PE13 BFIN_PE_IRQ(13) -#define IRQ_PE14 BFIN_PE_IRQ(14) -#define IRQ_PE15 BFIN_PE_IRQ(15) - -#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) -#define IRQ_PF0 BFIN_PF_IRQ(0) -#define IRQ_PF1 BFIN_PF_IRQ(1) -#define IRQ_PF2 BFIN_PF_IRQ(2) -#define IRQ_PF3 BFIN_PF_IRQ(3) -#define IRQ_PF4 BFIN_PF_IRQ(4) -#define IRQ_PF5 BFIN_PF_IRQ(5) -#define IRQ_PF6 BFIN_PF_IRQ(6) -#define IRQ_PF7 BFIN_PF_IRQ(7) -#define IRQ_PF8 BFIN_PF_IRQ(8) -#define IRQ_PF9 BFIN_PF_IRQ(9) -#define IRQ_PF10 BFIN_PF_IRQ(10) -#define IRQ_PF11 BFIN_PF_IRQ(11) -#define IRQ_PF12 BFIN_PF_IRQ(12) -#define IRQ_PF13 BFIN_PF_IRQ(13) -#define IRQ_PF14 BFIN_PF_IRQ(14) -#define IRQ_PF15 BFIN_PF_IRQ(15) - -#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) -#define IRQ_PG0 BFIN_PG_IRQ(0) -#define IRQ_PG1 BFIN_PG_IRQ(1) -#define IRQ_PG2 BFIN_PG_IRQ(2) -#define IRQ_PG3 BFIN_PG_IRQ(3) -#define IRQ_PG4 BFIN_PG_IRQ(4) -#define IRQ_PG5 BFIN_PG_IRQ(5) -#define IRQ_PG6 BFIN_PG_IRQ(6) -#define IRQ_PG7 BFIN_PG_IRQ(7) -#define IRQ_PG8 BFIN_PG_IRQ(8) -#define IRQ_PG9 BFIN_PG_IRQ(9) -#define IRQ_PG10 BFIN_PG_IRQ(10) -#define IRQ_PG11 BFIN_PG_IRQ(11) -#define IRQ_PG12 BFIN_PG_IRQ(12) -#define IRQ_PG13 BFIN_PG_IRQ(13) -#define IRQ_PG14 BFIN_PG_IRQ(14) -#define IRQ_PG15 BFIN_PG_IRQ(15) - -#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) -#define IRQ_PH0 BFIN_PH_IRQ(0) -#define IRQ_PH1 BFIN_PH_IRQ(1) -#define IRQ_PH2 BFIN_PH_IRQ(2) -#define IRQ_PH3 BFIN_PH_IRQ(3) -#define IRQ_PH4 BFIN_PH_IRQ(4) -#define IRQ_PH5 BFIN_PH_IRQ(5) -#define IRQ_PH6 BFIN_PH_IRQ(6) -#define IRQ_PH7 BFIN_PH_IRQ(7) -#define IRQ_PH8 BFIN_PH_IRQ(8) -#define IRQ_PH9 BFIN_PH_IRQ(9) -#define IRQ_PH10 BFIN_PH_IRQ(10) -#define IRQ_PH11 BFIN_PH_IRQ(11) -#define IRQ_PH12 BFIN_PH_IRQ(12) -#define IRQ_PH13 BFIN_PH_IRQ(13) -#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ -#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ - -#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) -#define IRQ_PI0 BFIN_PI_IRQ(0) -#define IRQ_PI1 BFIN_PI_IRQ(1) -#define IRQ_PI2 BFIN_PI_IRQ(2) -#define IRQ_PI3 BFIN_PI_IRQ(3) -#define IRQ_PI4 BFIN_PI_IRQ(4) -#define IRQ_PI5 BFIN_PI_IRQ(5) -#define IRQ_PI6 BFIN_PI_IRQ(6) -#define IRQ_PI7 BFIN_PI_IRQ(7) -#define IRQ_PI8 BFIN_PI_IRQ(8) -#define IRQ_PI9 BFIN_PI_IRQ(9) -#define IRQ_PI10 BFIN_PI_IRQ(10) -#define IRQ_PI11 BFIN_PI_IRQ(11) -#define IRQ_PI12 BFIN_PI_IRQ(12) -#define IRQ_PI13 BFIN_PI_IRQ(13) -#define IRQ_PI14 BFIN_PI_IRQ(14) -#define IRQ_PI15 BFIN_PI_IRQ(15) - -#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) -#define IRQ_PJ0 BFIN_PJ_IRQ(0) -#define IRQ_PJ1 BFIN_PJ_IRQ(1) -#define IRQ_PJ2 BFIN_PJ_IRQ(2) -#define IRQ_PJ3 BFIN_PJ_IRQ(3) -#define IRQ_PJ4 BFIN_PJ_IRQ(4) -#define IRQ_PJ5 BFIN_PJ_IRQ(5) -#define IRQ_PJ6 BFIN_PJ_IRQ(6) -#define IRQ_PJ7 BFIN_PJ_IRQ(7) -#define IRQ_PJ8 BFIN_PJ_IRQ(8) -#define IRQ_PJ9 BFIN_PJ_IRQ(9) -#define IRQ_PJ10 BFIN_PJ_IRQ(10) -#define IRQ_PJ11 BFIN_PJ_IRQ(11) -#define IRQ_PJ12 BFIN_PJ_IRQ(12) -#define IRQ_PJ13 BFIN_PJ_IRQ(13) -#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ -#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ - -#define GPIO_IRQ_BASE IRQ_PA0 - -#define NR_MACH_IRQS (IRQ_PJ15 + 1) - -/* For compatibility reasons with existing code */ - -#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR -#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR -#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR -#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR -#define IRQ_SPI0_ERR IRQ_SPI0_ERROR -#define IRQ_UART0_ERR IRQ_UART0_ERROR -#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR -#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR -#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR -#define IRQ_SPI1_ERR IRQ_SPI1_ERROR -#define IRQ_SPI2_ERR IRQ_SPI2_ERROR -#define IRQ_UART1_ERR IRQ_UART1_ERROR -#define IRQ_UART2_ERR IRQ_UART2_ERROR -#define IRQ_CAN0_ERR IRQ_CAN0_ERROR -#define IRQ_MXVR_ERR IRQ_MXVR_ERROR -#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR -#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR -#define IRQ_UART3_ERR IRQ_UART3_ERROR -#define IRQ_HOST_ERR IRQ_HOST_ERROR -#define IRQ_PIXC_ERR IRQ_PIXC_ERROR -#define IRQ_NFC_ERR IRQ_NFC_ERROR -#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR -#define IRQ_CAN1_ERR IRQ_CAN1_ERROR -#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR - -/* IAR0 BIT FIELDS */ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMAC0_ERR_POS 4 -#define IRQ_EPPI0_ERR_POS 8 -#define IRQ_SPORT0_ERR_POS 12 -#define IRQ_SPORT1_ERR_POS 16 -#define IRQ_SPI0_ERR_POS 20 -#define IRQ_UART0_ERR_POS 24 -#define IRQ_RTC_POS 28 - -/* IAR1 BIT FIELDS */ -#define IRQ_EPPI0_POS 0 -#define IRQ_SPORT0_RX_POS 4 -#define IRQ_SPORT0_TX_POS 8 -#define IRQ_SPORT1_RX_POS 12 -#define IRQ_SPORT1_TX_POS 16 -#define IRQ_SPI0_POS 20 -#define IRQ_UART0_RX_POS 24 -#define IRQ_UART0_TX_POS 28 - -/* IAR2 BIT FIELDS */ -#define IRQ_TIMER8_POS 0 -#define IRQ_TIMER9_POS 4 -#define IRQ_TIMER10_POS 8 -#define IRQ_PINT0_POS 12 -#define IRQ_PINT1_POS 16 -#define IRQ_MDMAS0_POS 20 -#define IRQ_MDMAS1_POS 24 -#define IRQ_WATCH_POS 28 - -/* IAR3 BIT FIELDS */ -#define IRQ_DMAC1_ERR_POS 0 -#define IRQ_SPORT2_ERR_POS 4 -#define IRQ_SPORT3_ERR_POS 8 -#define IRQ_MXVR_DATA_POS 12 -#define IRQ_SPI1_ERR_POS 16 -#define IRQ_SPI2_ERR_POS 20 -#define IRQ_UART1_ERR_POS 24 -#define IRQ_UART2_ERR_POS 28 - -/* IAR4 BIT FILEDS */ -#define IRQ_CAN0_ERR_POS 0 -#define IRQ_SPORT2_RX_POS 4 -#define IRQ_UART2_RX_POS 4 -#define IRQ_SPORT2_TX_POS 8 -#define IRQ_UART2_TX_POS 8 -#define IRQ_SPORT3_RX_POS 12 -#define IRQ_UART3_RX_POS 12 -#define IRQ_SPORT3_TX_POS 16 -#define IRQ_UART3_TX_POS 16 -#define IRQ_EPPI1_POS 20 -#define IRQ_EPPI2_POS 24 -#define IRQ_SPI1_POS 28 - -/* IAR5 BIT FIELDS */ -#define IRQ_SPI2_POS 0 -#define IRQ_UART1_RX_POS 4 -#define IRQ_UART1_TX_POS 8 -#define IRQ_ATAPI_RX_POS 12 -#define IRQ_ATAPI_TX_POS 16 -#define IRQ_TWI0_POS 20 -#define IRQ_TWI1_POS 24 -#define IRQ_CAN0_RX_POS 28 - -/* IAR6 BIT FIELDS */ -#define IRQ_CAN0_TX_POS 0 -#define IRQ_MDMAS2_POS 4 -#define IRQ_MDMAS3_POS 8 -#define IRQ_MXVR_ERR_POS 12 -#define IRQ_MXVR_MSG_POS 16 -#define IRQ_MXVR_PKT_POS 20 -#define IRQ_EPPI1_ERR_POS 24 -#define IRQ_EPPI2_ERR_POS 28 - -/* IAR7 BIT FIELDS */ -#define IRQ_UART3_ERR_POS 0 -#define IRQ_HOST_ERR_POS 4 -#define IRQ_PIXC_ERR_POS 12 -#define IRQ_NFC_ERR_POS 16 -#define IRQ_ATAPI_ERR_POS 20 -#define IRQ_CAN1_ERR_POS 24 -#define IRQ_HS_DMA_ERR_POS 28 - -/* IAR8 BIT FIELDS */ -#define IRQ_PIXC_IN0_POS 0 -#define IRQ_PIXC_IN1_POS 4 -#define IRQ_PIXC_OUT_POS 8 -#define IRQ_SDH_POS 12 -#define IRQ_CNT_POS 16 -#define IRQ_KEY_POS 20 -#define IRQ_CAN1_RX_POS 24 -#define IRQ_CAN1_TX_POS 28 - -/* IAR9 BIT FIELDS */ -#define IRQ_SDH_MASK0_POS 0 -#define IRQ_SDH_MASK1_POS 4 -#define IRQ_USB_INT0_POS 12 -#define IRQ_USB_INT1_POS 16 -#define IRQ_USB_INT2_POS 20 -#define IRQ_USB_DMA_POS 24 -#define IRQ_OTPSEC_POS 28 - -/* IAR10 BIT FIELDS */ -#define IRQ_TIMER0_POS 24 -#define IRQ_TIMER1_POS 28 - -/* IAR11 BIT FIELDS */ -#define IRQ_TIMER2_POS 0 -#define IRQ_TIMER3_POS 4 -#define IRQ_TIMER4_POS 8 -#define IRQ_TIMER5_POS 12 -#define IRQ_TIMER6_POS 16 -#define IRQ_TIMER7_POS 20 -#define IRQ_PINT2_POS 24 -#define IRQ_PINT3_POS 28 - -#ifndef __ASSEMBLY__ -#include - -/* - * gpio pint registers layout - */ -struct bfin_pint_regs { - u32 mask_set; - u32 mask_clear; - u32 request; - u32 assign; - u32 edge_set; - u32 edge_clear; - u32 invert_set; - u32 invert_clear; - u32 pinstate; - u32 latch; - u32 __pad0[2]; -}; - -#endif - -#endif diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h deleted file mode 100644 index caac2dfb41eb..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/mem_map.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * BF548 memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x1000 - -/* L1 Instruction ROM */ - -#define L1_ROM_START 0xFFA14000 -#define L1_ROM_LENGTH 0x10000 - -/* Level 1 Memory */ - -/* Memory Map for ADSP-BF548 processors */ -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#else -#define BFIN_ICACHESIZE (0*1024) -#endif - -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#define L1_CODE_LENGTH 0xC000 - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ - -/* Level 2 Memory */ -#define L2_START 0xFEB00000 -#if defined(CONFIG_BF542) -# define L2_LENGTH 0 -#elif defined(CONFIG_BF544) -# define L2_LENGTH 0x10000 -#else -# define L2_LENGTH 0x20000 -#endif - -#endif diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h deleted file mode 100644 index 94cca674d835..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h deleted file mode 100644 index d9f8632d7d09..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/portmux.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) -#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) -#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) -#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) -#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) -#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) -#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) -#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) -#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) -#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) -#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) -#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) -#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) -#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) -#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) -#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) -#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) -#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) -#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) -#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) - -#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) -#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) -#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) -#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) -#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) -#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) -#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) -#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) -#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) -#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0)) -#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) -#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) -#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0)) -#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) -#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) -#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) -#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1)) -#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1)) -#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1)) - -#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) -#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) -#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) -#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) -#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) -#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) -#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) -#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0)) -#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) -#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0)) -#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0)) -#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) -#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) -#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) -#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) - -#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) -#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) -#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) -#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) -#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) -#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) -#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) -#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0)) -#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0)) -#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) -#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) -#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) -#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) -#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) -#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) -#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0)) - -#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) -#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) -#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1)) -#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1)) -#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1)) -#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1)) -#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) -#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) -#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) -#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) -#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) -#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1)) -#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) -#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1)) -#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1)) -#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) -#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) -#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) -#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2)) -#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2)) -#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2)) -#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2)) -#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2)) -#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2)) -#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2)) -#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) -#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) -#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2)) -#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) -#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2)) -#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2)) -#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) -#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3)) -#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3)) -#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3)) -#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3)) -#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3)) -#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3)) -#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3)) -#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3)) -#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3)) -#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) -#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) -#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3)) -#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) -#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) - -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 -#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) -#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) -#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0)) -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) -#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) -#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0)) -#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0)) -#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) -#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) -#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) -#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) -#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) -#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) -#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) -#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) -#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) -#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) -#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) -#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) -#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) -#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) - -#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) -#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) -#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) -#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) - -#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT -# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) -# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) -# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) -# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) -# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) -# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) -# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) -# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) -# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) -# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) -# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) -# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) -# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) -# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) -# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) -# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) -#else -# define P_ATAPI_D0A (P_DONTCARE) -# define P_ATAPI_D1A (P_DONTCARE) -# define P_ATAPI_D2A (P_DONTCARE) -# define P_ATAPI_D3A (P_DONTCARE) -# define P_ATAPI_D4A (P_DONTCARE) -# define P_ATAPI_D5A (P_DONTCARE) -# define P_ATAPI_D6A (P_DONTCARE) -# define P_ATAPI_D7A (P_DONTCARE) -# define P_ATAPI_D8A (P_DONTCARE) -# define P_ATAPI_D9A (P_DONTCARE) -# define P_ATAPI_D10A (P_DONTCARE) -# define P_ATAPI_D11A (P_DONTCARE) -# define P_ATAPI_D12A (P_DONTCARE) -# define P_ATAPI_D13A (P_DONTCARE) -# define P_ATAPI_D14A (P_DONTCARE) -# define P_ATAPI_D15A (P_DONTCARE) -#endif - -#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) -#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) -#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) -#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) -#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) -#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) -#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) -#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) -#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) -#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) -#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) -#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) -#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) -#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) -#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) -#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) -#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT -# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) -# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) -# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) -#else -# define P_ATAPI_A0A (P_DONTCARE) -# define P_ATAPI_A1A (P_DONTCARE) -# define P_ATAPI_A2A (P_DONTCARE) -#endif -#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) -#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) -#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) -#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) -#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) -#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) -#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) -#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3)) - -#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) -#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) -#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) -#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) -#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) -#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) -#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) -#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) -#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) -#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) -#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) -#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) -#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) -#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) -#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) -#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) -#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) -#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) -#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) -#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) -#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) -#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) -#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) - -#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0)) -#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0)) -#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0)) -#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0)) -#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0)) -#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0)) -#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0)) -#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0)) -#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0)) -#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0)) -#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0)) -#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0)) -#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0)) -#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0)) -#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0)) -#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0)) -#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1)) - -#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0)) -#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0)) -#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0)) -#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0)) -#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0)) -#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0)) -#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0)) -#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0)) -#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0)) -#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0)) -#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0)) -#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0)) -#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) -#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) - - -#define P_NAND_D0 (P_DONTCARE) -#define P_NAND_D1 (P_DONTCARE) -#define P_NAND_D2 (P_DONTCARE) -#define P_NAND_D3 (P_DONTCARE) -#define P_NAND_D4 (P_DONTCARE) -#define P_NAND_D5 (P_DONTCARE) -#define P_NAND_D6 (P_DONTCARE) -#define P_NAND_D7 (P_DONTCARE) -#define P_NAND_WE (P_DONTCARE) -#define P_NAND_RE (P_DONTCARE) -#define P_NAND_CLE (P_DONTCARE) -#define P_NAND_ALE (P_DONTCARE) - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c deleted file mode 100644 index 48dd3a4bc4a5..000000000000 --- a/arch/blackfin/mach-bf548/ints-priority.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - * Set up the interrupt priorities - */ - -#include -#include -#include - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | - ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) | - ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) | - ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) | - ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) | - ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) | - ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) | - ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS)); - - bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) | - ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | - ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | - ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | - ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | - ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) | - ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | - ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); - - bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | - ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) | - ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) | - ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) | - ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) | - ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) | - ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS)); - - bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) | - ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) | - ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) | - ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) | - ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) | - ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) | - ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) | - ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS)); - - bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) | - ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) | - ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) | - ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) | - ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) | - ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) | - ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) | - ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS)); - - bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) | - ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | - ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | - ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) | - ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) | - ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) | - ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) | - ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS)); - - bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) | - ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) | - ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) | - ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) | - ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) | - ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) | - ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) | - ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS)); - - bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) | - ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) | - ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) | - ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) | - ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) | - ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) | - ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS)); - - bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) | - ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) | - ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) | - ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) | - ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) | - ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) | - ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) | - ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS)); - - bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) | - ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) | - ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) | - ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) | - ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) | - ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) | - ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS)); - - bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | - ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS)); - - bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | - ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | - ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | - ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | - ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | - ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | - ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) | - ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS)); - - SSYNC(); -} diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig deleted file mode 100644 index 059c3cbdb5ec..000000000000 --- a/arch/blackfin/mach-bf561/Kconfig +++ /dev/null @@ -1,213 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if (BF561) - -source "arch/blackfin/mach-bf561/boards/Kconfig" - -menu "BF561 Specific Configuration" - -if (!SMP) - -comment "Core B Support" - -config BF561_COREB - bool "Enable Core B loader" - default y - -endif - -comment "Interrupt Priority Assignment" - -menu "Priority" - -config IRQ_PLL_WAKEUP - int "PLL Wakeup Interrupt" - default 7 -config IRQ_DMA1_ERROR - int "DMA1 Error (generic)" - default 7 -config IRQ_DMA2_ERROR - int "DMA2 Error (generic)" - default 7 -config IRQ_IMDMA_ERROR - int "IMDMA Error (generic)" - default 7 -config IRQ_PPI0_ERROR - int "PPI0 Error Interrupt" - default 7 -config IRQ_PPI1_ERROR - int "PPI1 Error Interrupt" - default 7 -config IRQ_SPORT0_ERROR - int "SPORT0 Error Interrupt" - default 7 -config IRQ_SPORT1_ERROR - int "SPORT1 Error Interrupt" - default 7 -config IRQ_SPI_ERROR - int "SPI Error Interrupt" - default 7 -config IRQ_UART_ERROR - int "UART Error Interrupt" - default 7 -config IRQ_RESERVED_ERROR - int "Reserved Interrupt" - default 7 -config IRQ_DMA1_0 - int "DMA1 0 Interrupt(PPI1)" - default 8 -config IRQ_DMA1_1 - int "DMA1 1 Interrupt(PPI2)" - default 8 -config IRQ_DMA1_2 - int "DMA1 2 Interrupt" - default 8 -config IRQ_DMA1_3 - int "DMA1 3 Interrupt" - default 8 -config IRQ_DMA1_4 - int "DMA1 4 Interrupt" - default 8 -config IRQ_DMA1_5 - int "DMA1 5 Interrupt" - default 8 -config IRQ_DMA1_6 - int "DMA1 6 Interrupt" - default 8 -config IRQ_DMA1_7 - int "DMA1 7 Interrupt" - default 8 -config IRQ_DMA1_8 - int "DMA1 8 Interrupt" - default 8 -config IRQ_DMA1_9 - int "DMA1 9 Interrupt" - default 8 -config IRQ_DMA1_10 - int "DMA1 10 Interrupt" - default 8 -config IRQ_DMA1_11 - int "DMA1 11 Interrupt" - default 8 -config IRQ_DMA2_0 - int "DMA2 0 (SPORT0 RX)" - default 9 -config IRQ_DMA2_1 - int "DMA2 1 (SPORT0 TX)" - default 9 -config IRQ_DMA2_2 - int "DMA2 2 (SPORT1 RX)" - default 9 -config IRQ_DMA2_3 - int "DMA2 3 (SPORT2 TX)" - default 9 -config IRQ_DMA2_4 - int "DMA2 4 (SPI)" - default 9 -config IRQ_DMA2_5 - int "DMA2 5 (UART RX)" - default 9 -config IRQ_DMA2_6 - int "DMA2 6 (UART TX)" - default 9 -config IRQ_DMA2_7 - int "DMA2 7 Interrupt" - default 9 -config IRQ_DMA2_8 - int "DMA2 8 Interrupt" - default 9 -config IRQ_DMA2_9 - int "DMA2 9 Interrupt" - default 9 -config IRQ_DMA2_10 - int "DMA2 10 Interrupt" - default 9 -config IRQ_DMA2_11 - int "DMA2 11 Interrupt" - default 9 -config IRQ_TIMER0 - int "TIMER 0 Interrupt" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config IRQ_TIMER1 - int "TIMER 1 Interrupt" - default 10 -config IRQ_TIMER2 - int "TIMER 2 Interrupt" - default 10 -config IRQ_TIMER3 - int "TIMER 3 Interrupt" - default 10 -config IRQ_TIMER4 - int "TIMER 4 Interrupt" - default 10 -config IRQ_TIMER5 - int "TIMER 5 Interrupt" - default 10 -config IRQ_TIMER6 - int "TIMER 6 Interrupt" - default 10 -config IRQ_TIMER7 - int "TIMER 7 Interrupt" - default 10 -config IRQ_TIMER8 - int "TIMER 8 Interrupt" - default 10 -config IRQ_TIMER9 - int "TIMER 9 Interrupt" - default 10 -config IRQ_TIMER10 - int "TIMER 10 Interrupt" - default 10 -config IRQ_TIMER11 - int "TIMER 11 Interrupt" - default 10 -config IRQ_PROG0_INTA - int "Programmable Flags0 A (8)" - default 11 -config IRQ_PROG0_INTB - int "Programmable Flags0 B (8)" - default 11 -config IRQ_PROG1_INTA - int "Programmable Flags1 A (8)" - default 11 -config IRQ_PROG1_INTB - int "Programmable Flags1 B (8)" - default 11 -config IRQ_PROG2_INTA - int "Programmable Flags2 A (8)" - default 11 -config IRQ_PROG2_INTB - int "Programmable Flags2 B (8)" - default 11 -config IRQ_DMA1_WRRD0 - int "MDMA1 0 write/read INT" - default 8 -config IRQ_DMA1_WRRD1 - int "MDMA1 1 write/read INT" - default 8 -config IRQ_DMA2_WRRD0 - int "MDMA2 0 write/read INT" - default 9 -config IRQ_DMA2_WRRD1 - int "MDMA2 1 write/read INT" - default 9 -config IRQ_IMDMA_WRRD0 - int "IMDMA 0 write/read INT" - default 12 -config IRQ_IMDMA_WRRD1 - int "IMDMA 1 write/read INT" - default 12 -config IRQ_WDTIMER - int "Watch Dog Timer" - default 13 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile deleted file mode 100644 index b34029718318..000000000000 --- a/arch/blackfin/mach-bf561/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# arch/blackfin/mach-bf561/Makefile -# - -obj-y := ints-priority.o dma.o - -obj-$(CONFIG_BF561_COREB) += coreb.o -obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S deleted file mode 100644 index 1e2989c5d6b2..000000000000 --- a/arch/blackfin/mach-bf561/atomic.S +++ /dev/null @@ -1,945 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * Philippe Gerum - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include - -.text - -.macro coreslot_loadaddr reg:req - \reg\().l = _corelock; - \reg\().h = _corelock; -.endm - -.macro safe_testset addr:req, scratch:req -#if ANOMALY_05000477 - cli \scratch; - testset (\addr); - sti \scratch; -#else - testset (\addr); -#endif -.endm - -/* - * r0 = address of atomic data to flush and invalidate (32bit). - * - * Clear interrupts and return the old mask. - * We assume that no atomic data can span cachelines. - * - * Clobbers: r2:0, p0 - */ -ENTRY(_get_core_lock) - r1 = -L1_CACHE_BYTES; - r1 = r0 & r1; - cli r0; - coreslot_loadaddr p0; -.Lretry_corelock: - safe_testset p0, r2; - if cc jump .Ldone_corelock; - SSYNC(r2); - jump .Lretry_corelock -.Ldone_corelock: - p0 = r1; - /* flush core internal write buffer before invalidate dcache */ - CSYNC(r2); - flushinv[p0]; - SSYNC(r2); - rts; -ENDPROC(_get_core_lock) - -/* - * r0 = address of atomic data in uncacheable memory region (32bit). - * - * Clear interrupts and return the old mask. - * - * Clobbers: r0, p0 - */ -ENTRY(_get_core_lock_noflush) - cli r0; - coreslot_loadaddr p0; -.Lretry_corelock_noflush: - safe_testset p0, r2; - if cc jump .Ldone_corelock_noflush; - SSYNC(r2); - jump .Lretry_corelock_noflush -.Ldone_corelock_noflush: - /* - * SMP kgdb runs into dead loop without NOP here, when one core - * single steps over get_core_lock_noflush and the other executes - * get_core_lock as a slave node. - */ - nop; - CSYNC(r2); - rts; -ENDPROC(_get_core_lock_noflush) - -/* - * r0 = interrupt mask to restore. - * r1 = address of atomic data to flush and invalidate (32bit). - * - * Interrupts are masked on entry (see _get_core_lock). - * Clobbers: r2:0, p0 - */ -ENTRY(_put_core_lock) - /* Write-through cache assumed, so no flush needed here. */ - coreslot_loadaddr p0; - r1 = 0; - [p0] = r1; - SSYNC(r2); - sti r0; - rts; -ENDPROC(_put_core_lock) - -#ifdef __ARCH_SYNC_CORE_DCACHE - -ENTRY(___raw_smp_mark_barrier_asm) - [--sp] = rets; - [--sp] = ( r7:5 ); - [--sp] = r0; - [--sp] = p1; - [--sp] = p0; - call _get_core_lock_noflush; - - /* - * Calculate current core mask - */ - GET_CPUID(p1, r7); - r6 = 1; - r6 <<= r7; - - /* - * Set bit of other cores in barrier mask. Don't change current core bit. - */ - p1.l = _barrier_mask; - p1.h = _barrier_mask; - r7 = [p1]; - r5 = r7 & r6; - r7 = ~r6; - cc = r5 == 0; - if cc jump 1f; - r7 = r7 | r6; -1: - [p1] = r7; - SSYNC(r2); - - call _put_core_lock; - p0 = [sp++]; - p1 = [sp++]; - r0 = [sp++]; - ( r7:5 ) = [sp++]; - rets = [sp++]; - rts; -ENDPROC(___raw_smp_mark_barrier_asm) - -ENTRY(___raw_smp_check_barrier_asm) - [--sp] = rets; - [--sp] = ( r7:5 ); - [--sp] = r0; - [--sp] = p1; - [--sp] = p0; - call _get_core_lock_noflush; - - /* - * Calculate current core mask - */ - GET_CPUID(p1, r7); - r6 = 1; - r6 <<= r7; - - /* - * Clear current core bit in barrier mask if it is set. - */ - p1.l = _barrier_mask; - p1.h = _barrier_mask; - r7 = [p1]; - r5 = r7 & r6; - cc = r5 == 0; - if cc jump 1f; - r6 = ~r6; - r7 = r7 & r6; - [p1] = r7; - SSYNC(r2); - - call _put_core_lock; - - /* - * Invalidate the entire D-cache of current core. - */ - sp += -12; - call _resync_core_dcache - sp += 12; - jump 2f; -1: - call _put_core_lock; -2: - p0 = [sp++]; - p1 = [sp++]; - r0 = [sp++]; - ( r7:5 ) = [sp++]; - rets = [sp++]; - rts; -ENDPROC(___raw_smp_check_barrier_asm) - -/* - * r0 = irqflags - * r1 = address of atomic data - * - * Clobbers: r2:0, p1:0 - */ -_start_lock_coherent: - - [--sp] = rets; - [--sp] = ( r7:6 ); - r7 = r0; - p1 = r1; - - /* - * Determine whether the atomic data was previously - * owned by another CPU (=r6). - */ - GET_CPUID(p0, r2); - r1 = 1; - r1 <<= r2; - r2 = ~r1; - - r1 = [p1]; - r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */ - r6 = r1 & r2; - r1 = [p1]; - r1 <<= 4; - r1 >>= 4; - [p1] = r1; - - /* - * Release the core lock now, but keep IRQs disabled while we are - * performing the remaining housekeeping chores for the current CPU. - */ - coreslot_loadaddr p0; - r1 = 0; - [p0] = r1; - - /* - * If another CPU has owned the same atomic section before us, - * then our D-cached copy of the shared data protected by the - * current spin/write_lock may be obsolete. - */ - cc = r6 == 0; - if cc jump .Lcache_synced - - /* - * Invalidate the entire D-cache of the current core. - */ - sp += -12; - call _resync_core_dcache - sp += 12; - -.Lcache_synced: - SSYNC(r2); - sti r7; - ( r7:6 ) = [sp++]; - rets = [sp++]; - rts - -/* - * r0 = irqflags - * r1 = address of atomic data - * - * Clobbers: r2:0, p1:0 - */ -_end_lock_coherent: - - p1 = r1; - GET_CPUID(p0, r2); - r2 += 28; - r1 = 1; - r1 <<= r2; - r2 = [p1]; - r2 = r1 | r2; - [p1] = r2; - r1 = p1; - jump _put_core_lock; - -#endif /* __ARCH_SYNC_CORE_DCACHE */ - -/* - * r0 = &spinlock->lock - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_spin_is_locked_asm) - p1 = r0; - [--sp] = rets; - call _get_core_lock; - r3 = [p1]; - cc = bittst( r3, 0 ); - r3 = cc; - r1 = p1; - call _put_core_lock; - rets = [sp++]; - r0 = r3; - rts; -ENDPROC(___raw_spin_is_locked_asm) - -/* - * r0 = &spinlock->lock - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_spin_lock_asm) - p1 = r0; - [--sp] = rets; -.Lretry_spinlock: - call _get_core_lock; - r1 = p1; - r2 = [p1]; - cc = bittst( r2, 0 ); - if cc jump .Lbusy_spinlock -#ifdef __ARCH_SYNC_CORE_DCACHE - r3 = p1; - bitset ( r2, 0 ); /* Raise the lock bit. */ - [p1] = r2; - call _start_lock_coherent -#else - r2 = 1; - [p1] = r2; - call _put_core_lock; -#endif - rets = [sp++]; - rts; - -.Lbusy_spinlock: - /* We don't touch the atomic area if busy, so that flush - will behave like nop in _put_core_lock. */ - call _put_core_lock; - SSYNC(r2); - r0 = p1; - jump .Lretry_spinlock -ENDPROC(___raw_spin_lock_asm) - -/* - * r0 = &spinlock->lock - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_spin_trylock_asm) - p1 = r0; - [--sp] = rets; - call _get_core_lock; - r1 = p1; - r3 = [p1]; - cc = bittst( r3, 0 ); - if cc jump .Lfailed_trylock -#ifdef __ARCH_SYNC_CORE_DCACHE - bitset ( r3, 0 ); /* Raise the lock bit. */ - [p1] = r3; - call _start_lock_coherent -#else - r2 = 1; - [p1] = r2; - call _put_core_lock; -#endif - r0 = 1; - rets = [sp++]; - rts; -.Lfailed_trylock: - call _put_core_lock; - r0 = 0; - rets = [sp++]; - rts; -ENDPROC(___raw_spin_trylock_asm) - -/* - * r0 = &spinlock->lock - * - * Clobbers: r2:0, p1:0 - */ -ENTRY(___raw_spin_unlock_asm) - p1 = r0; - [--sp] = rets; - call _get_core_lock; - r2 = [p1]; - bitclr ( r2, 0 ); - [p1] = r2; - r1 = p1; -#ifdef __ARCH_SYNC_CORE_DCACHE - call _end_lock_coherent -#else - call _put_core_lock; -#endif - rets = [sp++]; - rts; -ENDPROC(___raw_spin_unlock_asm) - -/* - * r0 = &rwlock->lock - * - * Clobbers: r2:0, p1:0 - */ -ENTRY(___raw_read_lock_asm) - p1 = r0; - [--sp] = rets; - call _get_core_lock; -.Lrdlock_try: - r1 = [p1]; - r1 += -1; - [p1] = r1; - cc = r1 < 0; - if cc jump .Lrdlock_failed - r1 = p1; -#ifdef __ARCH_SYNC_CORE_DCACHE - call _start_lock_coherent -#else - call _put_core_lock; -#endif - rets = [sp++]; - rts; - -.Lrdlock_failed: - r1 += 1; - [p1] = r1; -.Lrdlock_wait: - r1 = p1; - call _put_core_lock; - SSYNC(r2); - r0 = p1; - call _get_core_lock; - r1 = [p1]; - cc = r1 < 2; - if cc jump .Lrdlock_wait; - jump .Lrdlock_try -ENDPROC(___raw_read_lock_asm) - -/* - * r0 = &rwlock->lock - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_read_trylock_asm) - p1 = r0; - [--sp] = rets; - call _get_core_lock; - r1 = [p1]; - cc = r1 <= 0; - if cc jump .Lfailed_tryrdlock; - r1 += -1; - [p1] = r1; - r1 = p1; -#ifdef __ARCH_SYNC_CORE_DCACHE - call _start_lock_coherent -#else - call _put_core_lock; -#endif - rets = [sp++]; - r0 = 1; - rts; -.Lfailed_tryrdlock: - r1 = p1; - call _put_core_lock; - rets = [sp++]; - r0 = 0; - rts; -ENDPROC(___raw_read_trylock_asm) - -/* - * r0 = &rwlock->lock - * - * Note: Processing controlled by a reader lock should not have - * any side-effect on cache issues with the other core, so we - * just release the core lock and exit (no _end_lock_coherent). - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_read_unlock_asm) - p1 = r0; - [--sp] = rets; - call _get_core_lock; - r1 = [p1]; - r1 += 1; - [p1] = r1; - r1 = p1; - call _put_core_lock; - rets = [sp++]; - rts; -ENDPROC(___raw_read_unlock_asm) - -/* - * r0 = &rwlock->lock - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_write_lock_asm) - p1 = r0; - r3.l = lo(RW_LOCK_BIAS); - r3.h = hi(RW_LOCK_BIAS); - [--sp] = rets; - call _get_core_lock; -.Lwrlock_try: - r1 = [p1]; - r1 = r1 - r3; -#ifdef __ARCH_SYNC_CORE_DCACHE - r2 = r1; - r2 <<= 4; - r2 >>= 4; - cc = r2 == 0; -#else - cc = r1 == 0; -#endif - if !cc jump .Lwrlock_wait - [p1] = r1; - r1 = p1; -#ifdef __ARCH_SYNC_CORE_DCACHE - call _start_lock_coherent -#else - call _put_core_lock; -#endif - rets = [sp++]; - rts; - -.Lwrlock_wait: - r1 = p1; - call _put_core_lock; - SSYNC(r2); - r0 = p1; - call _get_core_lock; - r1 = [p1]; -#ifdef __ARCH_SYNC_CORE_DCACHE - r1 <<= 4; - r1 >>= 4; -#endif - cc = r1 == r3; - if !cc jump .Lwrlock_wait; - jump .Lwrlock_try -ENDPROC(___raw_write_lock_asm) - -/* - * r0 = &rwlock->lock - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_write_trylock_asm) - p1 = r0; - [--sp] = rets; - call _get_core_lock; - r1 = [p1]; - r2.l = lo(RW_LOCK_BIAS); - r2.h = hi(RW_LOCK_BIAS); - cc = r1 == r2; - if !cc jump .Lfailed_trywrlock; -#ifdef __ARCH_SYNC_CORE_DCACHE - r1 >>= 28; - r1 <<= 28; -#else - r1 = 0; -#endif - [p1] = r1; - r1 = p1; -#ifdef __ARCH_SYNC_CORE_DCACHE - call _start_lock_coherent -#else - call _put_core_lock; -#endif - rets = [sp++]; - r0 = 1; - rts; - -.Lfailed_trywrlock: - r1 = p1; - call _put_core_lock; - rets = [sp++]; - r0 = 0; - rts; -ENDPROC(___raw_write_trylock_asm) - -/* - * r0 = &rwlock->lock - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_write_unlock_asm) - p1 = r0; - r3.l = lo(RW_LOCK_BIAS); - r3.h = hi(RW_LOCK_BIAS); - [--sp] = rets; - call _get_core_lock; - r1 = [p1]; - r1 = r1 + r3; - [p1] = r1; - r1 = p1; -#ifdef __ARCH_SYNC_CORE_DCACHE - call _end_lock_coherent -#else - call _put_core_lock; -#endif - rets = [sp++]; - rts; -ENDPROC(___raw_write_unlock_asm) - -/* - * r0 = ptr - * r1 = value - * - * ADD a signed value to a 32bit word and return the new value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_atomic_add_asm) - p1 = r0; - r3 = r1; - [--sp] = rets; - call _get_core_lock; - r2 = [p1]; - r3 = r3 + r2; - [p1] = r3; - r1 = p1; - call _put_core_lock; - r0 = r3; - rets = [sp++]; - rts; -ENDPROC(___raw_atomic_add_asm) - -/* - * r0 = ptr - * r1 = value - * - * ADD a signed value to a 32bit word and return the old value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_atomic_xadd_asm) - p1 = r0; - r3 = r1; - [--sp] = rets; - call _get_core_lock; - r3 = [p1]; - r2 = r3 + r2; - [p1] = r2; - r1 = p1; - call _put_core_lock; - r0 = r3; - rets = [sp++]; - rts; -ENDPROC(___raw_atomic_add_asm) - -/* - * r0 = ptr - * r1 = mask - * - * AND the mask bits from a 32bit word and return the old 32bit value - * atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_atomic_and_asm) - p1 = r0; - r3 = r1; - [--sp] = rets; - call _get_core_lock; - r3 = [p1]; - r2 = r2 & r3; - [p1] = r2; - r1 = p1; - call _put_core_lock; - r0 = r3; - rets = [sp++]; - rts; -ENDPROC(___raw_atomic_and_asm) - -/* - * r0 = ptr - * r1 = mask - * - * OR the mask bits into a 32bit word and return the old 32bit value - * atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_atomic_or_asm) - p1 = r0; - r3 = r1; - [--sp] = rets; - call _get_core_lock; - r3 = [p1]; - r2 = r2 | r3; - [p1] = r2; - r1 = p1; - call _put_core_lock; - r0 = r3; - rets = [sp++]; - rts; -ENDPROC(___raw_atomic_or_asm) - -/* - * r0 = ptr - * r1 = mask - * - * XOR the mask bits with a 32bit word and return the old 32bit value - * atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_atomic_xor_asm) - p1 = r0; - r3 = r1; - [--sp] = rets; - call _get_core_lock; - r3 = [p1]; - r2 = r2 ^ r3; - [p1] = r2; - r1 = p1; - call _put_core_lock; - r0 = r3; - rets = [sp++]; - rts; -ENDPROC(___raw_atomic_xor_asm) - -/* - * r0 = ptr - * r1 = mask - * - * Perform a logical AND between the mask bits and a 32bit word, and - * return the masked value. We need this on this architecture in - * order to invalidate the local cache before testing. - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_atomic_test_asm) - p1 = r0; - r3 = r1; - r1 = -L1_CACHE_BYTES; - r1 = r0 & r1; - p0 = r1; - /* flush core internal write buffer before invalidate dcache */ - CSYNC(r2); - flushinv[p0]; - SSYNC(r2); - r0 = [p1]; - r0 = r0 & r3; - rts; -ENDPROC(___raw_atomic_test_asm) - -/* - * r0 = ptr - * r1 = value - * - * Swap *ptr with value and return the old 32bit value atomically. - * Clobbers: r3:0, p1:0 - */ -#define __do_xchg(src, dst) \ - p1 = r0; \ - r3 = r1; \ - [--sp] = rets; \ - call _get_core_lock; \ - r2 = src; \ - dst = r3; \ - r3 = r2; \ - r1 = p1; \ - call _put_core_lock; \ - r0 = r3; \ - rets = [sp++]; \ - rts; - -ENTRY(___raw_xchg_1_asm) - __do_xchg(b[p1] (z), b[p1]) -ENDPROC(___raw_xchg_1_asm) - -ENTRY(___raw_xchg_2_asm) - __do_xchg(w[p1] (z), w[p1]) -ENDPROC(___raw_xchg_2_asm) - -ENTRY(___raw_xchg_4_asm) - __do_xchg([p1], [p1]) -ENDPROC(___raw_xchg_4_asm) - -/* - * r0 = ptr - * r1 = new - * r2 = old - * - * Swap *ptr with new if *ptr == old and return the previous *ptr - * value atomically. - * - * Clobbers: r3:0, p1:0 - */ -#define __do_cmpxchg(src, dst) \ - [--sp] = rets; \ - [--sp] = r4; \ - p1 = r0; \ - r3 = r1; \ - r4 = r2; \ - call _get_core_lock; \ - r2 = src; \ - cc = r2 == r4; \ - if !cc jump 1f; \ - dst = r3; \ - 1: r3 = r2; \ - r1 = p1; \ - call _put_core_lock; \ - r0 = r3; \ - r4 = [sp++]; \ - rets = [sp++]; \ - rts; - -ENTRY(___raw_cmpxchg_1_asm) - __do_cmpxchg(b[p1] (z), b[p1]) -ENDPROC(___raw_cmpxchg_1_asm) - -ENTRY(___raw_cmpxchg_2_asm) - __do_cmpxchg(w[p1] (z), w[p1]) -ENDPROC(___raw_cmpxchg_2_asm) - -ENTRY(___raw_cmpxchg_4_asm) - __do_cmpxchg([p1], [p1]) -ENDPROC(___raw_cmpxchg_4_asm) - -/* - * r0 = ptr - * r1 = bitnr - * - * Set a bit in a 32bit word and return the old 32bit value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_bit_set_asm) - r2 = r1; - r1 = 1; - r1 <<= r2; - jump ___raw_atomic_or_asm -ENDPROC(___raw_bit_set_asm) - -/* - * r0 = ptr - * r1 = bitnr - * - * Clear a bit in a 32bit word and return the old 32bit value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_bit_clear_asm) - r2 = 1; - r2 <<= r1; - r1 = ~r2; - jump ___raw_atomic_and_asm -ENDPROC(___raw_bit_clear_asm) - -/* - * r0 = ptr - * r1 = bitnr - * - * Toggle a bit in a 32bit word and return the old 32bit value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_bit_toggle_asm) - r2 = r1; - r1 = 1; - r1 <<= r2; - jump ___raw_atomic_xor_asm -ENDPROC(___raw_bit_toggle_asm) - -/* - * r0 = ptr - * r1 = bitnr - * - * Test-and-set a bit in a 32bit word and return the old bit value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_bit_test_set_asm) - [--sp] = rets; - [--sp] = r1; - call ___raw_bit_set_asm - r1 = [sp++]; - r2 = 1; - r2 <<= r1; - r0 = r0 & r2; - cc = r0 == 0; - if cc jump 1f - r0 = 1; -1: - rets = [sp++]; - rts; -ENDPROC(___raw_bit_test_set_asm) - -/* - * r0 = ptr - * r1 = bitnr - * - * Test-and-clear a bit in a 32bit word and return the old bit value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_bit_test_clear_asm) - [--sp] = rets; - [--sp] = r1; - call ___raw_bit_clear_asm - r1 = [sp++]; - r2 = 1; - r2 <<= r1; - r0 = r0 & r2; - cc = r0 == 0; - if cc jump 1f - r0 = 1; -1: - rets = [sp++]; - rts; -ENDPROC(___raw_bit_test_clear_asm) - -/* - * r0 = ptr - * r1 = bitnr - * - * Test-and-toggle a bit in a 32bit word, - * and return the old bit value atomically. - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_bit_test_toggle_asm) - [--sp] = rets; - [--sp] = r1; - call ___raw_bit_toggle_asm - r1 = [sp++]; - r2 = 1; - r2 <<= r1; - r0 = r0 & r2; - cc = r0 == 0; - if cc jump 1f - r0 = 1; -1: - rets = [sp++]; - rts; -ENDPROC(___raw_bit_test_toggle_asm) - -/* - * r0 = ptr - * r1 = bitnr - * - * Test a bit in a 32bit word and return its value. - * We need this on this architecture in order to invalidate - * the local cache before testing. - * - * Clobbers: r3:0, p1:0 - */ -ENTRY(___raw_bit_test_asm) - r2 = r1; - r1 = 1; - r1 <<= r2; - jump ___raw_atomic_test_asm -ENDPROC(___raw_bit_test_asm) - -/* - * r0 = ptr - * - * Fetch and return an uncached 32bit value. - * - * Clobbers: r2:0, p1:0 - */ -ENTRY(___raw_uncached_fetch_asm) - p1 = r0; - r1 = -L1_CACHE_BYTES; - r1 = r0 & r1; - p0 = r1; - /* flush core internal write buffer before invalidate dcache */ - CSYNC(r2); - flushinv[p0]; - SSYNC(r2); - r0 = [p1]; - rts; -ENDPROC(___raw_uncached_fetch_asm) diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig deleted file mode 100644 index 10e977b56710..000000000000 --- a/arch/blackfin/mach-bf561/boards/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN561_EZKIT - help - Select your board! - -config BFIN561_EZKIT - bool "BF561-EZKIT" - help - BF561-EZKIT-LITE board support. - -config BFIN561_TEPLA - bool "BF561-TEPLA" - help - BF561-TEPLA board support. - -config BFIN561_BLUETECHNIX_CM - bool "Bluetechnix CM-BF561" - help - CM-BF561 support for EVAL- and DEV-Board. - -config BFIN561_ACVILON - bool "BF561-ACVILON" - help - BF561-ACVILON System On Module support (SO-DIMM 144). - For more information about Acvilon BF561 SoM - please go to http://www.niistt.ru/ - -endchoice diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile deleted file mode 100644 index a5879f7857ad..000000000000 --- a/arch/blackfin/mach-bf561/boards/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# arch/blackfin/mach-bf561/boards/Makefile -# - -obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o -obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o -obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o -obj-$(CONFIG_BFIN561_TEPLA) += tepla.o diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c deleted file mode 100644 index 696cc9d7820a..000000000000 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * File: arch/blackfin/mach-bf561/acvilon.c - * Based on: arch/blackfin/mach-bf561/ezkit.c - * Author: - * - * Created: - * Description: - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * Copyright 2009 CJSC "NII STT" - * - * Bugs: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * - * For more information about Acvilon BF561 SoM please - * go to http://www.niistt.ru/ - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Acvilon board"; - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x20000000, - .end = 0x20000000 + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF15, - .end = IRQ_PF15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .port1_disable = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760-hcd", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -static struct resource bfin_i2c_pca_resources[] = { - { - .name = "pca9564-regs", - .start = 0x2C000000, - .end = 0x2C000000 + 16, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, - }, { - - .start = IRQ_PF8, - .end = IRQ_PF8, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -struct i2c_pca9564_pf_platform_data pca9564_platform_data = { - .gpio = -1, - .i2c_clock_speed = 330000, - .timeout = HZ, -}; - -/* PCA9564 I2C Bus driver */ -static struct platform_device bfin_i2c_pca_device = { - .name = "i2c-pca-platform", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources), - .resource = bfin_i2c_pca_resources, - .dev = { - .platform_data = &pca9564_platform_data, - } -}; - -/* I2C devices fitted. */ -static struct i2c_board_info acvilon_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("ds1339", 0x68), - }, - { - I2C_BOARD_INFO("tcn75", 0x49), - }, -}; - -#if IS_ENABLED(CONFIG_MTD_PLATRAM) -static struct platdata_mtd_ram mtd_ram_data = { - .mapname = "rootfs(RAM)", - .bankwidth = 4, -}; - -static struct resource mtd_ram_resource = { - .start = 0x4000000, - .end = 0x5ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mtd_ram_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &mtd_ram_data, - }, - .num_resources = 1, - .resource = &mtd_ram_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) -#include -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x28000000, - .end = 0x28000000 + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL + 2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART_TX, - .end = IRQ_UART_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_RX, - .end = IRQ_UART_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_ERROR, - .end = IRQ_UART_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART_TX, - .end = CH_UART_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART_RX, - .end = CH_UART_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - /* Passed to driver */ - .platform_data = &bfin_uart0_peripherals, - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) - -static struct mtd_partition bfin_plat_nand_partitions[] = { - { - .name = "params(nand)", - .size = 32 * 1024 * 1024, - .offset = 0, - }, { - .name = "userfs(nand)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -#define BFIN_NAND_PLAT_CLE 2 -#define BFIN_NAND_PLAT_ALE 3 - -static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE)); - else - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE)); -} - -#define BFIN_NAND_PLAT_READY GPIO_PF10 -static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(BFIN_NAND_PLAT_READY); -} - -static struct platform_nand_data bfin_plat_nand_data = { - .chip = { - .nr_chips = 1, - .chip_delay = 30, - .partitions = bfin_plat_nand_partitions, - .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), - }, - .ctrl = { - .cmd_ctrl = bfin_plat_nand_cmd_ctrl, - .dev_ready = bfin_plat_nand_dev_ready, - }, -}; - -#define MAX(x, y) (x > y ? x : y) -static struct resource bfin_plat_nand_resources = { - .start = 0x24000000, - .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_MEM, -}; - -static struct platform_device bfin_async_nand_device = { - .name = "gen_nand", - .id = -1, - .num_resources = 1, - .resource = &bfin_plat_nand_resources, - .dev = { - .platform_data = &bfin_plat_nand_data, - }, -}; - -static void bfin_plat_nand_init(void) -{ - gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); -} -#else -static void bfin_plat_nand_init(void) -{ -} -#endif - -#if IS_ENABLED(CONFIG_MTD_DATAFLASH) -static struct mtd_partition bfin_spi_dataflash_partitions[] = { - { - .name = "bootloader", - .size = 0x4200, - .offset = 0, - .mask_flags = MTD_CAP_ROM}, - { - .name = "u-boot", - .size = 0x42000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "u-boot(params)", - .size = 0x4200, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "kernel", - .size = 0x294000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "params", - .size = 0x42000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "rootfs", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_dataflash_data = { - .name = "SPI Dataflash", - .parts = bfin_spi_dataflash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), -}; - -/* DataFlash chip */ -static struct bfin5xx_spi_chip data_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip */ -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 3, - }, -#endif -#if IS_ENABLED(CONFIG_MTD_DATAFLASH) - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select */ - .platform_data = &bfin_spi_dataflash_data, - .controller_data = &data_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -static struct resource bfin_gpios_resources = { - .start = 31, -/* .end = MAX_BLACKFIN_GPIOS - 1, */ - .end = 32, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device bfin_gpios_device = { - .name = "simple-gpio", - .id = -1, - .num_resources = 1, - .resource = &bfin_gpios_resources, -}; - -static const unsigned int cclk_vlev_datasheet[] = { - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 300000000), - VRPAIR(VLEV_095, 313000000), - VRPAIR(VLEV_100, 350000000), - VRPAIR(VLEV_105, 400000000), - VRPAIR(VLEV_110, 444000000), - VRPAIR(VLEV_115, 450000000), - VRPAIR(VLEV_120, 475000000), - VRPAIR(VLEV_125, 500000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */ , -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *acvilon_devices[] __initdata = { - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - - &bfin_gpios_device, - -#if IS_ENABLED(CONFIG_SMSC911X) - &smsc911x_device, -#endif - - &bfin_i2c_pca_device, - -#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) - &bfin_async_nand_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PLATRAM) - &mtd_ram_device, -#endif - -}; - -static int __init acvilon_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - - bfin_plat_nand_init(); - ret = - platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices)); - if (ret < 0) - return ret; - - i2c_register_board_info(0, acvilon_i2c_devs, - ARRAY_SIZE(acvilon_i2c_devs)); - - bfin_write_FIO0_FLAG_C(1 << 14); - msleep(5); - bfin_write_FIO0_FLAG_S(1 << 14); - - spi_register_board_info(bfin_spi_board_info, - ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(acvilon_init); - -static struct platform_device *acvilon_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(acvilon_early_devices, - ARRAY_SIZE(acvilon_early_devices)); -} diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c deleted file mode 100644 index 10c57771822d..000000000000 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ /dev/null @@ -1,556 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix CM BF561"; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = 0x20000 - }, { - .name = "file system(spi)", - .size = 0x700000, - .offset = 0x00100000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_3, - }, -#endif -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) -static struct platform_device hitachi_fb_device = { - .name = "hitachi-tx09", -}; -#endif - - -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT | - SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x28000300, - .end = 0x28000300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF0, - .end = IRQ_PF0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) -#include - -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x24008000, - .end = 0x24008000 + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PF43, - .end = IRQ_PF43, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_16BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x24000000, - .end = 0x24000000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF45, - .end = IRQ_PF45, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x24008000, - .end = 0x24008000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x24008004, - .end = 0x24008004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF47, - .end = IRQ_PF47, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART_TX, - .end = IRQ_UART_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_RX, - .end = IRQ_UART_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_ERROR, - .end = IRQ_UART_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART_TX, - .end = CH_UART_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART_RX, - .end = CH_UART_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) -#define PATA_INT IRQ_PF46 - -static struct pata_platform_info bfin_pata_platform_data = { - .ioport_shift = 2, -}; - -static struct resource bfin_pata_resources[] = { - { - .start = 0x2400C000, - .end = 0x2400C001F, - .flags = IORESOURCE_MEM, - }, - { - .start = 0x2400D018, - .end = 0x2400D01B, - .flags = IORESOURCE_MEM, - }, - { - .start = PATA_INT, - .end = PATA_INT, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device bfin_pata_device = { - .name = "pata_platform", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_pata_resources), - .resource = bfin_pata_resources, - .dev = { - .platform_data = &bfin_pata_platform_data, - } -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition para_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data para_flash_data = { - .width = 2, - .parts = para_partitions, - .nr_parts = ARRAY_SIZE(para_partitions), -}; - -static struct resource para_flash_resource = { - .start = 0x20000000, - .end = 0x207fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device para_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = ¶_flash_data, - }, - .num_resources = 1, - .resource = ¶_flash_resource, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 300000000), - VRPAIR(VLEV_095, 313000000), - VRPAIR(VLEV_100, 350000000), - VRPAIR(VLEV_105, 400000000), - VRPAIR(VLEV_110, 444000000), - VRPAIR(VLEV_115, 450000000), - VRPAIR(VLEV_120, 475000000), - VRPAIR(VLEV_125, 500000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cm_bf561_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_FB_HITACHI_TX09) - &hitachi_fb_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) - &smsc911x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - &bfin_pata_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - ¶_flash_device, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - ret = gpio_request(GPIO_PF46, "net2272"); - if (ret) - return ret; - - /* Reset USB Chip, PF46 */ - gpio_direction_output(GPIO_PF46, 0); - mdelay(2); - gpio_set_value(GPIO_PF46, 1); -#endif - - return 0; -} - -static int __init cm_bf561_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - -#if IS_ENABLED(CONFIG_PATA_PLATFORM) - irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); -#endif - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - return 0; -} - -arch_initcall(cm_bf561_init); - -static struct platform_device *cm_bf561_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cm_bf561_early_devices, - ARRAY_SIZE(cm_bf561_early_devices)); -} diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c deleted file mode 100644 index acc5363f60c6..000000000000 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ /dev/null @@ -1,688 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF561-EZKIT"; - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x2C0F0000, - .end = 0x203C0000 + 0xfffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include - -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x2c060000, - .end = 0x2c060000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x2c060004, - .end = 0x2c060004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF8, - .end = IRQ_PF8, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x2C000000, - .end = 0x2C000000 + 0x7F, - .flags = IORESOURCE_MEM, - }, { - .start = 1, - .flags = IORESOURCE_BUS, - }, { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -/* - * USB-LAN EzExtender board - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT | - SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x2C010300, - .end = 0x2C010300 + 16, - .flags = IORESOURCE_MEM, - }, { - - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART_TX, - .end = IRQ_UART_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_RX, - .end = IRQ_UART_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_ERROR, - .end = IRQ_UART_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART_TX, - .end = CH_UART_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART_RX, - .end = CH_UART_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezkit_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x1C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "config(nor)", - .size = 0x2000 * 7, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "u-boot env(nor)", - .size = 0x2000, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data ezkit_flash_data = { - .width = 2, - .parts = ezkit_partitions, - .nr_parts = ARRAY_SIZE(ezkit_partitions), -}; - -static struct resource ezkit_flash_resource = { - .start = 0x20000000, - .end = 0x207fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezkit_flash_data, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = "ad1836", /* only includes chip name for the moment */ - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"}, - {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) -#include - -static struct gpiod_lookup_table bfin_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data i2c_gpio_data = { - .udelay = 10, -}; - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 300000000), - VRPAIR(VLEV_095, 313000000), - VRPAIR(VLEV_100, 350000000), - VRPAIR(VLEV_105, 400000000), - VRPAIR(VLEV_110, 444000000), - VRPAIR(VLEV_115, 450000000), - VRPAIR(VLEV_120, 475000000), - VRPAIR(VLEV_125, 500000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) -#include -#include -#include - -static const unsigned short ppi_req[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const struct ppi_info ppi_info = { - .type = PPI_TYPE_PPI, - .dma_ch = CH_PPI0, - .irq_err = IRQ_PPI1_ERROR, - .base = (void __iomem *)PPI0_CONTROL, - .pin_req = ppi_req, -}; - -#if IS_ENABLED(CONFIG_VIDEO_ADV7183) -#include -static struct v4l2_input adv7183_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_ALL, - .capabilities = V4L2_IN_CAP_STD, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_ALL, - .capabilities = V4L2_IN_CAP_STD, - }, - { - .index = 2, - .name = "Component", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_ALL, - .capabilities = V4L2_IN_CAP_STD, - }, -}; - -static struct bcap_route adv7183_routes[] = { - { - .input = ADV7183_COMPOSITE4, - .output = ADV7183_8BIT_OUT, - }, - { - .input = ADV7183_SVIDEO0, - .output = ADV7183_8BIT_OUT, - }, - { - .input = ADV7183_COMPONENT0, - .output = ADV7183_8BIT_OUT, - }, -}; - - -static const unsigned adv7183_gpio[] = { - GPIO_PF13, /* reset pin */ - GPIO_PF2, /* output enable pin */ -}; - -static struct bfin_capture_config bfin_capture_data = { - .card_name = "BF561", - .inputs = adv7183_inputs, - .num_inputs = ARRAY_SIZE(adv7183_inputs), - .routes = adv7183_routes, - .i2c_adapter_id = 0, - .board_info = { - .type = "adv7183", - .addr = 0x20, - .platform_data = (void *)adv7183_gpio, - }, - .ppi_info = &ppi_info, - .ppi_control = (PACK_EN | DLEN_8 | DMA32 | FLD_SEL), -}; -#endif - -static struct platform_device bfin_capture_device = { - .name = "bfin_capture", - .dev = { - .platform_data = &bfin_capture_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97 = { - .name = "bfin-ac97", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) -static const char * const ad1836_link[] = { - "bfin-i2s.0", - "spi0.4", -}; -static struct platform_device bfin_ad1836_machine = { - .name = "bfin-snd-ad1836", - .id = -1, - .dev = { - .platform_data = (void *)ad1836_link, - }, -}; -#endif - -static struct platform_device *ezkit_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) - &bfin_isp1760_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) - &i2c_gpio_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezkit_flash_device, -#endif - -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) - &bfin_capture_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - &bfin_ad1836_machine, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - ret = gpio_request(GPIO_PF11, "net2272"); - if (ret) - return ret; - - /* Reset the USB chip */ - gpio_direction_output(GPIO_PF11, 0); - mdelay(2); - gpio_set_value(GPIO_PF11, 1); -#endif - - return 0; -} - -static int __init ezkit_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - -#if IS_ENABLED(CONFIG_I2C_GPIO) - gpiod_add_lookup_table(&bfin_i2c_gpiod_table); -#endif - ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); - if (ret < 0) - return ret; - -#if IS_ENABLED(CONFIG_SMC91X) - bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12)); - SSYNC(); -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15)); - bfin_write_FIO0_FLAG_S(1 << 15); - SSYNC(); - /* - * This initialization lasts for approximately 4500 MCLKs. - * MCLK = 12.288MHz - */ - udelay(400); -#endif - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(ezkit_init); - -static struct platform_device *ezkit_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezkit_early_devices, - ARRAY_SIZE(ezkit_early_devices)); -} diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c deleted file mode 100644 index f87b8cc0cd4c..000000000000 --- a/arch/blackfin/mach-bf561/boards/tepla.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright 2004-2007 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Thanks to Jamey Hicks. - * - * Only SMSC91C1111 was registered, may do more later. - * - * Licensed under the GPL-2 - */ - -#include -#include -#include - -const char bfin_board_name[] = "Tepla-BF561"; - -/* - * Driver needs to know address, irq and flag pin. - */ -static struct resource smc91x_resources[] = { - { - .start = 0x2C000300, - .end = 0x2C000320, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PROG_INTB, - .end = IRQ_PROG_INTB, - .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART_TX, - .end = IRQ_UART_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_RX, - .end = IRQ_UART_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_ERROR, - .end = IRQ_UART_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART_TX, - .end = CH_UART_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART_RX, - .end = CH_UART_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -static struct platform_device *tepla_devices[] __initdata = { - &smc91x_device, - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif -}; - -static int __init tepla_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices)); -} - -arch_initcall(tepla_init); - -static struct platform_device *tepla_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(tepla_early_devices, - ARRAY_SIZE(tepla_early_devices)); -} diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c deleted file mode 100644 index cf27554e76bf..000000000000 --- a/arch/blackfin/mach-bf561/coreb.c +++ /dev/null @@ -1,64 +0,0 @@ -/* Load firmware into Core B on a BF561 - * - * Author: Bas Vermeulen - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* The Core B reset func requires code in the application that is loaded into - * Core B. In order to reset, the application needs to install an interrupt - * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and - * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core - * B to stall when Supplemental Interrupt 0 is set, and will reset PC to - * 0xff600000 when COREB_SRAM_INIT is cleared. - */ - -#include -#include -#include -#include -#include - -#define CMD_COREB_START _IO('b', 0) -#define CMD_COREB_STOP _IO('b', 1) -#define CMD_COREB_RESET _IO('b', 2) - -static long -coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - int ret = 0; - - switch (cmd) { - case CMD_COREB_START: - bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); - break; - case CMD_COREB_STOP: - bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020); - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); - break; - case CMD_COREB_RESET: - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); - break; - default: - ret = -EINVAL; - break; - } - - CSYNC(); - - return ret; -} - -static const struct file_operations coreb_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = coreb_ioctl, - .llseek = noop_llseek, -}; - -static struct miscdevice coreb_dev = { - .minor = MISC_DYNAMIC_MINOR, - .name = "coreb", - .fops = &coreb_fops, -}; -builtin_misc_device(coreb_dev); diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c deleted file mode 100644 index 8ffdd6b4a242..000000000000 --- a/arch/blackfin/mach-bf561/dma.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * the simple DMA Implementation for Blackfin - * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA1_0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_1_NEXT_DESC_PTR, - (struct dma_register *) DMA1_2_NEXT_DESC_PTR, - (struct dma_register *) DMA1_3_NEXT_DESC_PTR, - (struct dma_register *) DMA1_4_NEXT_DESC_PTR, - (struct dma_register *) DMA1_5_NEXT_DESC_PTR, - (struct dma_register *) DMA1_6_NEXT_DESC_PTR, - (struct dma_register *) DMA1_7_NEXT_DESC_PTR, - (struct dma_register *) DMA1_8_NEXT_DESC_PTR, - (struct dma_register *) DMA1_9_NEXT_DESC_PTR, - (struct dma_register *) DMA1_10_NEXT_DESC_PTR, - (struct dma_register *) DMA1_11_NEXT_DESC_PTR, - (struct dma_register *) DMA2_0_NEXT_DESC_PTR, - (struct dma_register *) DMA2_1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_2_NEXT_DESC_PTR, - (struct dma_register *) DMA2_3_NEXT_DESC_PTR, - (struct dma_register *) DMA2_4_NEXT_DESC_PTR, - (struct dma_register *) DMA2_5_NEXT_DESC_PTR, - (struct dma_register *) DMA2_6_NEXT_DESC_PTR, - (struct dma_register *) DMA2_7_NEXT_DESC_PTR, - (struct dma_register *) DMA2_8_NEXT_DESC_PTR, - (struct dma_register *) DMA2_9_NEXT_DESC_PTR, - (struct dma_register *) DMA2_10_NEXT_DESC_PTR, - (struct dma_register *) DMA2_11_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI0: - ret_irq = IRQ_PPI0; - break; - case CH_PPI1: - ret_irq = IRQ_PPI1; - break; - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - case CH_SPI: - ret_irq = IRQ_SPI; - break; - case CH_UART_RX: - ret_irq = IRQ_UART_RX; - break; - case CH_UART_TX: - ret_irq = IRQ_UART_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - case CH_MEM_STREAM2_SRC: - case CH_MEM_STREAM2_DEST: - ret_irq = IRQ_MEM_DMA2; - break; - case CH_MEM_STREAM3_SRC: - case CH_MEM_STREAM3_DEST: - ret_irq = IRQ_MEM_DMA3; - break; - - case CH_IMEM_STREAM0_SRC: - case CH_IMEM_STREAM0_DEST: - ret_irq = IRQ_IMEM_DMA0; - break; - case CH_IMEM_STREAM1_SRC: - case CH_IMEM_STREAM1_DEST: - ret_irq = IRQ_IMEM_DMA1; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c deleted file mode 100644 index 0123117b8ff2..000000000000 --- a/arch/blackfin/mach-bf561/hotplug.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * Graff Yang - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -int hotplug_coreb; - -void platform_cpu_die(void) -{ - unsigned long iwr; - - hotplug_coreb = 1; - - /* - * When CoreB wakes up, the code in _coreb_trampoline_start cannot - * turn off the data cache. This causes the CoreB failed to boot. - * As a workaround, we invalidate all the data cache before sleep. - */ - blackfin_invalidate_entire_dcache(); - - /* disable core timer */ - bfin_write_TCNTL(0); - - /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */ - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1))); - SSYNC(); - - /* set CoreB wakeup by ipi0, iwr will be discarded */ - bfin_iwr_set_sup0(&iwr, &iwr, &iwr); - SSYNC(); - - coreb_die(); -} diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h deleted file mode 100644 index 038249c1d0d4..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ /dev/null @@ -1,353 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ -#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 -# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 -#endif - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ -#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ -#define ANOMALY_05000120 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* SIGNBITS Instruction Not Functional under Certain Conditions */ -#define ANOMALY_05000127 (1) -/* IMDMA S1/D1 Channel May Stall */ -#define ANOMALY_05000149 (1) -/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ -#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ -#define ANOMALY_05000166 (1) -/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ -#define ANOMALY_05000167 (1) -/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ -#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ -#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ -#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) -/* Cache Fill Buffer Data lost */ -#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) -/* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ -#define ANOMALY_05000176 (__SILICON_REVISION__ < 5) -/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ -#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* Disabling the PPI Resets the PPI Configuration Registers */ -#define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* Internal Memory DMA Does Not Operate at Full Speed */ -#define ANOMALY_05000182 (1) -/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ -#define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ -#define ANOMALY_05000186 (__SILICON_REVISION__ < 5) -/* IMDMA Corrupted Data after a Halt */ -#define ANOMALY_05000187 (1) -/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ -#define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions when Speculative Fetch Is Cancelled */ -#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI Not Functional at Core Voltage < 1Volt */ -#define ANOMALY_05000190 (1) -/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ -#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) -/* Restarting SPORT in Specific Modes May Cause Data Corruption */ -#define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses when Preceding Memory Read Stalls */ -#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) -/* Current DMA Address Shows Wrong Value During Carry Fix */ -#define ANOMALY_05000199 (__SILICON_REVISION__ < 5) -/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ -#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) -/* Possible Infinite Stall with Specific Dual-DAG Situation */ -#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ -#define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ -#define ANOMALY_05000205 (__SILICON_REVISION__ < 5) -/* Recovery from "Brown-Out" Condition */ -#define ANOMALY_05000207 (__SILICON_REVISION__ < 5) -/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ -#define ANOMALY_05000208 (1) -/* Speed Path in Computational Unit Affects Certain Instructions */ -#define ANOMALY_05000209 (__SILICON_REVISION__ < 5) -/* UART TX Interrupt Masked Erroneously */ -#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) -/* NMI Event at Boot Time Results in Unpredictable State */ -#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) -/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ -#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) -/* Incorrect Pulse-Width of UART Start Bit */ -#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) -/* Scratchpad Memory Bank Reads May Return Incorrect Data */ -#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) -/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ -#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) -/* UART STB Bit Incorrectly Affects Receiver Setting */ -#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ -#define ANOMALY_05000232 (__SILICON_REVISION__ < 5) -/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET Operation Forces Stall on the Other Core */ -#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) -/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ -#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) -/* Exception Not Generated for MMR Accesses in Reserved Region */ -#define ANOMALY_05000251 (__SILICON_REVISION__ < 5) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (__SILICON_REVISION__ > 3) -/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception - * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change - * after the behavior and the root cause are confirmed with hardware team. - */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP)) -/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ -#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) -/* ICPLB_STATUS MMR Register May Be Corrupted */ -#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) -/* Stores To Data Cache May Be Lost */ -#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) -/* Hardware Loop Corrupted When Taking an ICPLB Exception */ -#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) -/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ -#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ -#define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA May Corrupt Data under Certain Conditions */ -#define ANOMALY_05000267 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ -#define ANOMALY_05000269 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (1) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* Data Cache Write Back to External Synchronous Memory May Be Lost */ -#define ANOMALY_05000274 (1) -/* PPI Timing and Sampling Information Updates */ -#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) -/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ -#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 5) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error when ISR Context Is Not Restored */ -/* Temporarily walk around for bug 5423 till this issue is confirmed by - * official anomaly document. It looks 05000281 still exists on bf561 - * v0.5. - */ -#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5) -/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ -#define ANOMALY_05000283 (1) -/* Reads Will Receive Incorrect Data under Certain Conditions */ -#define ANOMALY_05000287 (__SILICON_REVISION__ < 5) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 5) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ -#define ANOMALY_05000302 (1) -/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ -#define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted after SPI Master Boot */ -#define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ -#define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ -#define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* 24-Bit SPI Boot Mode Is Not Functional */ -#define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* Slave SPI Boot Mode Is Not Functional */ -#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ -#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000339 (__SILICON_REVISION__ < 5) -/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ -#define ANOMALY_05000343 (__SILICON_REVISION__ < 5) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* Conflicting Column Address Widths Causes SDRAM Errors */ -#define ANOMALY_05000362 (1) -/* UART Break Signal Issues */ -#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ -#define ANOMALY_05000412 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */ -#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* SCKELOW Feature Is Not Functional */ -#define ANOMALY_05000458 (1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ -#define ANOMALY_05000471 (1) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* Possible Lockup Condition when Modifying PLL from External Memory */ -#define ANOMALY_05000475 (1) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* PLL May Latch Incorrect Values Coming Out of Reset */ -#define ANOMALY_05000489 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) - -/* - * These anomalies have been "phased" out of analog.com anomaly sheets and are - * here to show running on older silicon just isn't feasible. - */ - -/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Erroneous Exception when Enabling Cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ -#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) -/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ -#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) -/* Stall in multi-unit DMA operations */ -#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* DMA engine may lose data due to incorrect handshaking */ -#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) -/* DMA stalls when all three controllers read data from the same source */ -#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) -/* Execution stall when executing in L2 and doing external accesses */ -#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) -/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> is not set on Reset */ -#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* DSPID register values incorrect */ -#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000119 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000233 (0) -#define ANOMALY_05000234 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000364 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000383 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000389 (0) -#define ANOMALY_05000400 (0) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000440 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000456 (0) -#define ANOMALY_05000450 (0) -#define ANOMALY_05000465 (0) -#define ANOMALY_05000467 (0) -#define ANOMALY_05000474 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_05000485 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h deleted file mode 100644 index 9f9a367e6a24..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/bf561.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF561_H__ -#define __MACH_BF561_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/*************************** - * Blackfin Cache setup - */ - - -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/* IAR0 BIT FIELDS */ -#define PLL_WAKEUP_BIT 0xFFFFFFFF -#define DMA1_ERROR_BIT 0xFFFFFF0F -#define DMA2_ERROR_BIT 0xFFFFF0FF -#define IMDMA_ERROR_BIT 0xFFFF0FFF -#define PPI1_ERROR_BIT 0xFFF0FFFF -#define PPI2_ERROR_BIT 0xFF0FFFFF -#define SPORT0_ERROR_BIT 0xF0FFFFFF -#define SPORT1_ERROR_BIT 0x0FFFFFFF -/* IAR1 BIT FIELDS */ -#define SPI_ERROR_BIT 0xFFFFFFFF -#define UART_ERROR_BIT 0xFFFFFF0F -#define RESERVED_ERROR_BIT 0xFFFFF0FF -#define DMA1_0_BIT 0xFFFF0FFF -#define DMA1_1_BIT 0xFFF0FFFF -#define DMA1_2_BIT 0xFF0FFFFF -#define DMA1_3_BIT 0xF0FFFFFF -#define DMA1_4_BIT 0x0FFFFFFF -/* IAR2 BIT FIELDS */ -#define DMA1_5_BIT 0xFFFFFFFF -#define DMA1_6_BIT 0xFFFFFF0F -#define DMA1_7_BIT 0xFFFFF0FF -#define DMA1_8_BIT 0xFFFF0FFF -#define DMA1_9_BIT 0xFFF0FFFF -#define DMA1_10_BIT 0xFF0FFFFF -#define DMA1_11_BIT 0xF0FFFFFF -#define DMA2_0_BIT 0x0FFFFFFF -/* IAR3 BIT FIELDS */ -#define DMA2_1_BIT 0xFFFFFFFF -#define DMA2_2_BIT 0xFFFFFF0F -#define DMA2_3_BIT 0xFFFFF0FF -#define DMA2_4_BIT 0xFFFF0FFF -#define DMA2_5_BIT 0xFFF0FFFF -#define DMA2_6_BIT 0xFF0FFFFF -#define DMA2_7_BIT 0xF0FFFFFF -#define DMA2_8_BIT 0x0FFFFFFF -/* IAR4 BIT FIELDS */ -#define DMA2_9_BIT 0xFFFFFFFF -#define DMA2_10_BIT 0xFFFFFF0F -#define DMA2_11_BIT 0xFFFFF0FF -#define TIMER0_BIT 0xFFFF0FFF -#define TIMER1_BIT 0xFFF0FFFF -#define TIMER2_BIT 0xFF0FFFFF -#define TIMER3_BIT 0xF0FFFFFF -#define TIMER4_BIT 0x0FFFFFFF -/* IAR5 BIT FIELDS */ -#define TIMER5_BIT 0xFFFFFFFF -#define TIMER6_BIT 0xFFFFFF0F -#define TIMER7_BIT 0xFFFFF0FF -#define TIMER8_BIT 0xFFFF0FFF -#define TIMER9_BIT 0xFFF0FFFF -#define TIMER10_BIT 0xFF0FFFFF -#define TIMER11_BIT 0xF0FFFFFF -#define PROG0_INTA_BIT 0x0FFFFFFF -/* IAR6 BIT FIELDS */ -#define PROG0_INTB_BIT 0xFFFFFFFF -#define PROG1_INTA_BIT 0xFFFFFF0F -#define PROG1_INTB_BIT 0xFFFFF0FF -#define PROG2_INTA_BIT 0xFFFF0FFF -#define PROG2_INTB_BIT 0xFFF0FFFF -#define DMA1_WRRD0_BIT 0xFF0FFFFF -#define DMA1_WRRD1_BIT 0xF0FFFFFF -#define DMA2_WRRD0_BIT 0x0FFFFFFF -/* IAR7 BIT FIELDS */ -#define DMA2_WRRD1_BIT 0xFFFFFFFF -#define IMDMA_WRRD0_BIT 0xFFFFFF0F -#define IMDMA_WRRD1_BIT 0xFFFFF0FF -#define WATCH_BIT 0xFFFF0FFF -#define RESERVED_1_BIT 0xFFF0FFFF -#define RESERVED_2_BIT 0xFF0FFFFF -#define SUPPLE_0_BIT 0xF0FFFFFF -#define SUPPLE_1_BIT 0x0FFFFFFF - -/* Miscellaneous Values */ - -/****************************** EBIU Settings ********************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#if defined(CONFIG_C_AMBEN_ALL) -#define V_AMBEN AMBEN_ALL -#elif defined(CONFIG_C_AMBEN) -#define V_AMBEN 0x0 -#elif defined(CONFIG_C_AMBEN_B0) -#define V_AMBEN AMBEN_B0 -#elif defined(CONFIG_C_AMBEN_B0_B1) -#define V_AMBEN AMBEN_B0_B1 -#elif defined(CONFIG_C_AMBEN_B0_B1_B2) -#define V_AMBEN AMBEN_B0_B1_B2 -#endif - -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif - -#ifdef CONFIG_C_B0PEN -#define V_B0PEN 0x10 -#else -#define V_B0PEN 0x00 -#endif - -#ifdef CONFIG_C_B1PEN -#define V_B1PEN 0x20 -#else -#define V_B1PEN 0x00 -#endif - -#ifdef CONFIG_C_B2PEN -#define V_B2PEN 0x40 -#else -#define V_B2PEN 0x00 -#endif - -#ifdef CONFIG_C_B3PEN -#define V_B3PEN 0x80 -#else -#define V_B3PEN 0x00 -#endif - -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) - -#ifdef CONFIG_BF561 -#define CPU "BF561" -#define CPUID 0x27bb -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF561_H__ */ diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h deleted file mode 100644 index 08072c86d5dc..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 1 - -#endif diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h deleted file mode 100644 index dc470534c085..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#define BF561_FAMILY - -#include "bf561.h" -#include "anomaly.h" - -#include -#include "defBF561.h" - -#ifndef __ASSEMBLY__ -# include -# include "cdefBF561.h" -#endif - -#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D() -#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val) -#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR() -#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val) -#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() -#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) - -/* Weird muxer funcs which pick SIC regs from IMASK base */ -#define __SIC_MUX(base, x) ((base) + ((x) << 2)) -#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val) -#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x)) -#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val) -#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x)) -#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val) -#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) -#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) - -#endif /* _MACH_BLACKFIN_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h deleted file mode 100644 index 753331597207..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ /dev/null @@ -1,1460 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF561_H -#define _CDEF_BF561_H - -/*********************************************************************************** */ -/* System MMR Register Map */ -/*********************************************************************************** */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) - -/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST,val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) -#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val) -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val) -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val) -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val) -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val) - -/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ -#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) -#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val) -#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR) -#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val) -#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT) -#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val) -#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0) -#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val) -#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1) -#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val) -#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0) -#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val) -#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1) -#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val) -#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2) -#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val) -#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3) -#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val) -#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4) -#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val) -#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5) -#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val) -#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6) -#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val) -#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7) -#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val) -#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0) -#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val) -#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1) -#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val) -#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0) -#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val) -#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1) -#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val) -/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ -#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL) -#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val) -#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT) -#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val) -#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT) -#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val) - -/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ -#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL) -#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val) -#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT) -#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val) -#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT) -#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val) - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ -#define bfin_read_UART_THR() bfin_read16(UART_THR) -#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) -#define bfin_read_UART_RBR() bfin_read16(UART_RBR) -#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) -#define bfin_read_UART_DLL() bfin_read16(UART_DLL) -#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) -#define bfin_read_UART_IER() bfin_read16(UART_IER) -#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) -#define bfin_read_UART_DLH() bfin_read16(UART_DLH) -#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) -#define bfin_read_UART_IIR() bfin_read16(UART_IIR) -#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) -#define bfin_read_UART_LCR() bfin_read16(UART_LCR) -#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) -#define bfin_read_UART_MCR() bfin_read16(UART_MCR) -#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) -#define bfin_read_UART_LSR() bfin_read16(UART_LSR) -#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) -#define bfin_read_UART_MSR() bfin_read16(UART_MSR) -#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val) -#define bfin_read_UART_SCR() bfin_read16(UART_SCR) -#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) -#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) -#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) - -/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val) -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val) -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val) -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val) -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val) - -/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ -#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE) -#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val) -#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE) -#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val) -#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS) -#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val) -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val) -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val) -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val) -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val) -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val) -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val) -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val) -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val) -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val) -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val) -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val) -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val) -#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG) -#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val) -#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER) -#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val) -#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD) -#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val) -#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH) -#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val) -#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE) -#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val) -#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE) -#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val) -#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS) -#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val) - -/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ -#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D) -#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val) -#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C) -#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val) -#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S) -#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val) -#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T) -#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val) -#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D) -#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val) -#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C) -#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val) -#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S) -#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val) -#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T) -#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val) -#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D) -#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val) -#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C) -#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val) -#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S) -#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val) -#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T) -#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val) -#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR) -#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val) -#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR) -#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val) -#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE) -#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val) -#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH) -#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val) -#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN) -#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val) -/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ -#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D) -#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val) -#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C) -#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val) -#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S) -#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val) -#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T) -#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val) -#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D) -#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val) -#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C) -#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val) -#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S) -#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val) -#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T) -#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val) -#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D) -#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val) -#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C) -#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val) -#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S) -#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val) -#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T) -#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val) -#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR) -#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val) -#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR) -#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val) -#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE) -#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val) -#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH) -#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val) -#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN) -#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val) -/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ -#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D) -#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val) -#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C) -#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val) -#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S) -#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val) -#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T) -#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val) -#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D) -#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val) -#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C) -#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val) -#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S) -#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val) -#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T) -#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val) -#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D) -#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val) -#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C) -#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val) -#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S) -#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val) -#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T) -#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val) -#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR) -#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val) -#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR) -#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val) -#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE) -#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val) -#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH) -#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val) -#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN) -#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val) -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) -#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) -/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ -#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL) -#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val) -#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS) -#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val) -#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS() -#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT) -#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val) -#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY) -#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val) -#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME) -#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val) -/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ -#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL) -#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val) -#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS) -#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val) -#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS() -#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT) -#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val) -#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY) -#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val) -#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) -#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val) -/*DMA traffic control registers */ -#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) -#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val) -#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) -#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val) -#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) -#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val) -#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) -#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val) -/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ -#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) -#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val) -#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR) -#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR) -#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val) -#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT) -#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val) -#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT) -#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val) -#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY) -#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val) -#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY) -#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val) -#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR) -#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val) -#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR) -#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val) -#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT) -#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val) -#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT) -#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val) -#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS) -#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val) -#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP) -#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG) -#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val) -#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR) -#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR) -#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val) -#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT) -#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val) -#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT) -#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val) -#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY) -#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val) -#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY) -#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val) -#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR) -#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val) -#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR) -#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val) -#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT) -#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val) -#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT) -#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val) -#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS) -#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val) -#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP) -#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG) -#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val) -#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR) -#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR) -#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val) -#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT) -#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val) -#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT) -#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val) -#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY) -#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val) -#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY) -#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val) -#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR) -#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val) -#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR) -#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val) -#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT) -#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val) -#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT) -#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val) -#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS) -#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val) -#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP) -#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG) -#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val) -#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR) -#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR) -#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val) -#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT) -#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val) -#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT) -#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val) -#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY) -#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val) -#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY) -#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val) -#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR) -#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val) -#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR) -#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val) -#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT) -#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val) -#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT) -#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val) -#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS) -#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val) -#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP) -#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG) -#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val) -#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR) -#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR) -#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val) -#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT) -#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val) -#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT) -#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val) -#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY) -#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val) -#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY) -#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val) -#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR) -#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val) -#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR) -#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val) -#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT) -#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val) -#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT) -#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val) -#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS) -#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val) -#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP) -#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG) -#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val) -#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR) -#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR) -#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val) -#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT) -#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val) -#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT) -#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val) -#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY) -#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val) -#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY) -#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val) -#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR) -#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val) -#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR) -#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val) -#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT) -#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val) -#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT) -#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val) -#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS) -#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val) -#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP) -#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG) -#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val) -#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR) -#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR) -#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val) -#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT) -#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val) -#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT) -#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val) -#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY) -#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val) -#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY) -#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val) -#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR) -#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val) -#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR) -#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val) -#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT) -#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val) -#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT) -#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val) -#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS) -#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val) -#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP) -#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG) -#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val) -#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR) -#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR) -#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val) -#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT) -#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val) -#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT) -#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val) -#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY) -#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val) -#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY) -#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val) -#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR) -#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val) -#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR) -#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val) -#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT) -#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val) -#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT) -#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val) -#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS) -#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val) -#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP) -#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG) -#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val) -#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR) -#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR) -#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val) -#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT) -#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val) -#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT) -#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val) -#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY) -#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val) -#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY) -#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val) -#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR) -#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val) -#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR) -#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val) -#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT) -#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val) -#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT) -#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val) -#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS) -#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val) -#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP) -#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG) -#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val) -#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR) -#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR) -#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val) -#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT) -#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val) -#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT) -#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val) -#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY) -#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val) -#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY) -#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val) -#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR) -#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val) -#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR) -#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val) -#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT) -#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val) -#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT) -#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val) -#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS) -#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val) -#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP) -#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG) -#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val) -#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR) -#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR) -#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val) -#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT) -#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val) -#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT) -#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val) -#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY) -#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val) -#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY) -#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val) -#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR) -#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val) -#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR) -#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val) -#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT) -#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val) -#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT) -#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val) -#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS) -#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val) -#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP) -#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val) -#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG) -#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val) -#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR) -#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR) -#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val) -#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT) -#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val) -#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT) -#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val) -#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY) -#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val) -#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY) -#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val) -#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR) -#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val) -#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR) -#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val) -#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT) -#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val) -#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT) -#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val) -#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS) -#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val) -#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) -#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val) -/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val) -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val) -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val) -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val) -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val) -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val) -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val) -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val) -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val) -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val) -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val) -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val) -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val) -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val) -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val) -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val) -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val) -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val) -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val) -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val) -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val) -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val) -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val) -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val) -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val) -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val) -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val) -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val) -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val) -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val) -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val) -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val) -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val) -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val) -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val) -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val) -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val) -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val) -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val) -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val) -/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ -#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) -#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val) -#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR) -#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR) -#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val) -#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT) -#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val) -#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT) -#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val) -#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY) -#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val) -#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY) -#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val) -#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR) -#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val) -#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR) -#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val) -#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT) -#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val) -#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT) -#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val) -#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS) -#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val) -#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP) -#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG) -#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val) -#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR) -#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR) -#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val) -#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT) -#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val) -#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT) -#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val) -#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY) -#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val) -#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY) -#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val) -#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR) -#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val) -#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR) -#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val) -#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT) -#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val) -#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT) -#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val) -#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS) -#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val) -#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP) -#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG) -#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val) -#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR) -#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR) -#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val) -#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT) -#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val) -#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT) -#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val) -#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY) -#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val) -#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY) -#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val) -#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR) -#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val) -#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR) -#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val) -#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT) -#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val) -#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT) -#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val) -#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS) -#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val) -#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP) -#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG) -#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val) -#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR) -#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR) -#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val) -#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT) -#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val) -#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT) -#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val) -#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY) -#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val) -#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY) -#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val) -#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR) -#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val) -#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR) -#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val) -#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT) -#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val) -#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT) -#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val) -#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS) -#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val) -#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP) -#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG) -#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val) -#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR) -#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR) -#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val) -#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT) -#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val) -#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT) -#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val) -#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY) -#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val) -#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY) -#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val) -#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR) -#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val) -#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR) -#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val) -#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT) -#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val) -#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT) -#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val) -#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS) -#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val) -#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP) -#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG) -#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val) -#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR) -#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR) -#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val) -#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT) -#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val) -#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT) -#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val) -#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY) -#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val) -#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY) -#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val) -#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR) -#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val) -#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR) -#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val) -#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT) -#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val) -#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT) -#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val) -#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS) -#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val) -#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP) -#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG) -#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val) -#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR) -#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR) -#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val) -#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT) -#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val) -#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT) -#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val) -#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY) -#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val) -#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY) -#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val) -#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR) -#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val) -#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR) -#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val) -#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT) -#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val) -#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT) -#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val) -#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS) -#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val) -#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP) -#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG) -#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val) -#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR) -#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR) -#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val) -#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT) -#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val) -#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT) -#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val) -#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY) -#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val) -#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY) -#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val) -#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR) -#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val) -#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR) -#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val) -#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT) -#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val) -#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT) -#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val) -#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS) -#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val) -#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP) -#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG) -#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val) -#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR) -#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR) -#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val) -#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT) -#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val) -#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT) -#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val) -#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY) -#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val) -#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY) -#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val) -#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR) -#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val) -#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR) -#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val) -#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT) -#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val) -#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT) -#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val) -#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS) -#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val) -#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP) -#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG) -#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val) -#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR) -#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR) -#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val) -#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT) -#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val) -#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT) -#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val) -#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY) -#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val) -#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY) -#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val) -#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR) -#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val) -#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR) -#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val) -#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT) -#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val) -#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT) -#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val) -#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS) -#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val) -#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP) -#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG) -#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val) -#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR) -#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR) -#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val) -#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT) -#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val) -#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT) -#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val) -#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY) -#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val) -#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY) -#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val) -#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR) -#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val) -#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR) -#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val) -#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT) -#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val) -#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT) -#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val) -#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS) -#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val) -#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP) -#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val) -#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG) -#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val) -#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR) -#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR) -#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val) -#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT) -#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val) -#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT) -#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val) -#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY) -#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val) -#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY) -#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val) -#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR) -#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val) -#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR) -#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val) -#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT) -#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val) -#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT) -#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val) -#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS) -#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val) -#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) -#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val) -/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) -/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ -#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) -#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val) -#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR) -#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val) -#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR) -#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val) -#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT) -#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val) -#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT) -#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val) -#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY) -#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val) -#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY) -#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val) -#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR) -#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val) -#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR) -#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val) -#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT) -#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val) -#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT) -#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val) -#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS) -#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val) -#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG) -#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val) -#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR) -#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val) -#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR) -#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val) -#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT) -#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val) -#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT) -#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val) -#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY) -#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val) -#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY) -#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val) -#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR) -#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val) -#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR) -#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val) -#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT) -#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val) -#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT) -#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val) -#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS) -#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val) -#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG) -#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val) -#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR) -#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val) -#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR) -#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val) -#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT) -#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val) -#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT) -#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val) -#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY) -#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val) -#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY) -#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val) -#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR) -#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val) -#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR) -#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val) -#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT) -#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val) -#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT) -#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val) -#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS) -#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val) -#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG) -#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val) -#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR) -#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val) -#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR) -#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val) -#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT) -#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val) -#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT) -#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val) -#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY) -#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val) -#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY) -#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val) -#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR) -#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val) -#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR) -#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val) -#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT) -#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val) -#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT) -#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val) -#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) -#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val) - -#endif /* _CDEF_BF561_H */ diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h deleted file mode 100644 index 9f21f768c63a..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ /dev/null @@ -1,1402 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF561_H -#define _DEF_BF561_H - -/*********************************************************************************** */ -/* System MMR Register Map */ -/*********************************************************************************** */ - -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ - -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID Register */ - -/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ -#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) -#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) -#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) -#define RESET_SOFTWARE (SWRST_OCCURRED) - -/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define SWRST 0xFFC00100 /* Software Reset register */ -#define SYSCR 0xFFC00104 /* System Reset Configuration register */ -#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ -#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ -#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ -#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ -#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ -#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ -#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ -#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ -#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ -#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ - -/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ -#define SICB_SWRST 0xFFC01100 /* reserved */ -#define SICB_SYSCR 0xFFC01104 /* reserved */ -#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */ -#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ -#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */ -#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */ -#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */ -#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */ -#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */ -#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */ -#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */ -#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */ -#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */ -#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */ -#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */ -#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */ -#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */ - -/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ -#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */ -#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */ -#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */ - -/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ -#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */ -#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */ -#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ - -/* - * Because include/linux/serial_reg.h have defined UART_*, - * So we define blackfin uart regs to BFIN_UART0_*. - */ -#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ -#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ -#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ -#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ -#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */ -#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */ - -#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */ - -#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */ - -#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */ - -#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */ - -#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */ - -#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */ -#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */ - -/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ -#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */ -#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */ -#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */ -#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */ - -#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */ -#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */ -#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */ -#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */ - -#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */ -#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */ -#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */ -#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */ - -#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */ -#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */ -#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */ -#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */ - -#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */ -#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */ -#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */ - -/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ -#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */ -#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */ -#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */ -#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */ -#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */ -#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */ -#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */ -#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */ -#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */ -#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */ -#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */ -#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */ -#define FIO0_DIR 0xFFC00730 /* Flag Direction register */ -#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */ -#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */ -#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */ -#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */ - -/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ -#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */ -#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */ -#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */ -#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */ -#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */ -#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */ -#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */ -#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */ -#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */ -#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */ -#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */ -#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */ -#define FIO1_DIR 0xFFC01530 /* Flag Direction register */ -#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */ -#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */ -#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */ -#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */ - -/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ -#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */ -#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */ -#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */ -#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */ -#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */ -#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */ -#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */ -#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */ -#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */ -#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */ -#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */ -#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */ -#define FIO2_DIR 0xFFC01730 /* Flag Direction register */ -#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */ -#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */ -#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */ -#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ -#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */ -#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */ -#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */ -#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */ -#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */ - -/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ -#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */ -#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */ -#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */ -#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */ -#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ - -/*DMA traffic control registers */ -#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */ -#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */ -#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */ -#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ - -/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ -#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ -#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */ -#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */ -#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */ -#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */ -#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */ -#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */ -#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ -#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ -#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ -#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ -#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */ -#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */ - -#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */ -#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */ -#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */ -#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */ -#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */ -#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */ -#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */ -#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */ -#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */ -#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */ -#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */ -#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */ -#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */ - -#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */ -#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */ -#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */ -#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */ -#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */ -#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */ -#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */ -#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */ -#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */ -#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */ -#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */ -#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */ -#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */ - -#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */ -#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */ -#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */ -#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */ -#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */ -#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */ -#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */ -#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */ -#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */ -#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */ -#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */ -#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */ -#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */ - -#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */ -#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */ -#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */ -#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */ -#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */ -#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */ -#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */ -#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */ -#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */ -#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */ -#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */ -#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */ -#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */ - -#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */ -#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */ -#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */ -#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */ -#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */ -#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */ -#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */ -#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */ -#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */ -#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */ -#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */ -#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */ -#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */ - -#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */ -#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */ -#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */ -#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */ -#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */ -#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */ -#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */ -#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */ -#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */ -#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */ -#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */ -#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */ -#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */ - -#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */ -#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */ -#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */ -#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */ -#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */ -#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */ -#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */ -#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */ -#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */ -#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */ -#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */ -#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */ -#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */ - -#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */ -#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */ -#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */ -#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */ -#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */ -#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */ -#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */ -#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */ -#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */ -#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */ -#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */ -#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */ -#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */ - -#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */ -#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */ -#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */ -#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */ -#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */ -#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */ -#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */ -#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */ -#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */ -#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */ -#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */ -#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */ -#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */ - -#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */ -#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */ -#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */ -#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */ -#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */ -#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */ -#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */ -#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */ -#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */ -#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */ -#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */ -#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */ -#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */ - -#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */ -#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */ -#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */ -#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */ -#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */ -#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */ -#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */ -#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */ -#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */ -#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */ -#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */ -#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */ -#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ - -/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ -#define MDMA_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ -#define MDMA_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ -#define MDMA_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ -#define MDMA_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ -#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ -#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ - -#define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ -#define MDMA_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ -#define MDMA_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ -#define MDMA_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ -#define MDMA_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ -#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ -#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ - -#define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ -#define MDMA_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ -#define MDMA_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ -#define MDMA_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ -#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ -#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ -#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ - -#define MDMA_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ -#define MDMA_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ -#define MDMA_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ -#define MDMA_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ -#define MDMA_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ -#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ -#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ - -/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ -#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ -#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ -#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ -#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ -#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ -#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ -#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ -#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ -#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ -#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ -#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ -#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */ -#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ - -#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ -#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ -#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ -#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ -#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ -#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ -#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ -#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ -#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ -#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ -#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ -#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */ -#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ - -#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ -#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ -#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ -#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ -#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ -#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ -#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ -#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ -#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ -#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ -#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ -#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */ -#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ - -#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ -#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ -#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ -#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ -#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ -#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ -#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ -#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ -#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ -#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ -#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ -#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */ -#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ - -#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ -#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ -#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ -#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ -#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ -#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ -#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ -#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ -#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ -#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ -#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ -#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */ -#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ - -#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ -#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ -#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ -#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ -#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ -#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ -#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ -#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ -#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ -#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ -#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ -#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */ -#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ - -#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ -#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ -#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ -#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ -#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ -#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ -#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ -#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ -#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ -#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ -#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ -#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */ -#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ - -#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */ -#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */ -#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */ -#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */ -#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */ -#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */ -#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */ -#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ -#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ -#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ -#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ -#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */ -#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */ - -#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */ -#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */ -#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */ -#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */ -#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */ -#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */ -#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */ -#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ -#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ -#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ -#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ -#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */ -#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */ - -#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */ -#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */ -#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */ -#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */ -#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */ -#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */ -#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */ -#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ -#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ -#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ -#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ -#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */ -#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */ - -#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */ -#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */ -#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */ -#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */ -#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */ -#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */ -#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */ -#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ -#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ -#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ -#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ -#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */ -#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */ - -#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */ -#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */ -#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */ -#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */ -#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */ -#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */ -#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */ -#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ -#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ -#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ -#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ -#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */ -#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ - -/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ -#define MDMA_D2_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ -#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ -#define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ -#define MDMA_D2_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ -#define MDMA_D2_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ -#define MDMA_D2_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ -#define MDMA_D2_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ -#define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ -#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ -#define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ - -#define MDMA_S2_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ -#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ -#define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ -#define MDMA_S2_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ -#define MDMA_S2_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ -#define MDMA_S2_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ -#define MDMA_S2_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ -#define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ -#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ -#define MDMA_S2_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ - -#define MDMA_D3_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ -#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ -#define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ -#define MDMA_D3_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ -#define MDMA_D3_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ -#define MDMA_D3_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ -#define MDMA_D3_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ -#define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ -#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ -#define MDMA_D3_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ - -#define MDMA_S3_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ -#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ -#define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ -#define MDMA_S3_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ -#define MDMA_S3_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ -#define MDMA_S3_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ -#define MDMA_S3_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ -#define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ -#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ -#define MDMA_S3_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ - -/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ -#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ -#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ -#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */ -#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */ -#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */ -#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */ -#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */ -#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */ -#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */ -#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */ -#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */ -#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */ - -#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */ -#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */ -#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */ -#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */ -#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */ -#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */ -#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */ -#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */ -#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */ -#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */ -#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */ -#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */ - -#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */ -#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */ -#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */ -#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */ -#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */ -#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */ -#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */ -#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */ -#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */ -#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */ -#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */ -#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */ - -#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */ -#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */ -#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */ -#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */ -#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */ -#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */ -#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */ -#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */ -#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */ -#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */ -#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */ -#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */ - -/*********************************************************************************** */ -/* System MMR Register Bits */ -/******************************************************************************* */ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SICA_SYSCR Masks */ -#define COREB_SRAM_INIT 0x0020 - -/* SWRST Mask */ -#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ -#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ -#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */ -#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */ -#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */ -#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */ -#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */ -#define SWRST_OCCURRED 0x8000 /* SWRST Status */ - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ - -/* SICu_IARv Masks */ -/* u = A or B */ -/* v = 0 to 7 */ -/* w = 0 or 1 */ - -/* Per_number = 0 to 63 */ -/* IVG_number = 7 to 15 */ -#define Peripheral_IVG(Per_number, IVG_number) \ - ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */ - /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */ - /* r0.h = hi(Peripheral_IVG(62, 10)); */ - -/* SICx_IMASKw Masks */ -/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -/* x = pos 0 to 31, for 32-63 use value-32 */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ - -/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 /* PPI Port Enable */ -#define PORT_DIR 0x00000002 /* PPI Port Direction */ -#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ -#define PORT_CFG 0x00000030 /* PPI Port Configuration */ -#define FLD_SEL 0x00000040 /* PPI Active Field Select */ -#define PACK_EN 0x00000080 /* PPI Packing Mode */ -#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x00003800 /* PPI Data Length */ -#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ -#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#define DLEN_10 0x00000800 /* Data Length = 10 Bits */ -#define DLEN_11 0x00001000 /* Data Length = 11 Bits */ -#define DLEN_12 0x00001800 /* Data Length = 12 Bits */ -#define DLEN_13 0x00002000 /* Data Length = 13 Bits */ -#define DLEN_14 0x00002800 /* Data Length = 14 Bits */ -#define DLEN_15 0x00003000 /* Data Length = 15 Bits */ -#define DLEN_16 0x00003800 /* Data Length = 16 Bits */ -#define POL 0x0000C000 /* PPI Signal Polarities */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 /* Field Indicator */ -#define FT_ERR 0x00000800 /* Frame Track Error */ -#define OVR 0x00001000 /* FIFO Overflow Error */ -#define UNDR 0x00002000 /* FIFO Underrun Error */ -#define ERR_DET 0x00004000 /* Error Detected Indicator */ -#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ - -/* ********** DMA CONTROLLER MASKS *********************8 */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ - -#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ -#define PMAP 0x00007000 /* DMA Peripheral Map Field */ - -/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ - -/* PWM Timer bit definitions */ - -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 -#define TIMEN3 0x0008 -#define TIMEN4 0x0010 -#define TIMEN5 0x0020 -#define TIMEN6 0x0040 -#define TIMEN7 0x0080 -#define TIMEN8 0x0001 -#define TIMEN9 0x0002 -#define TIMEN10 0x0004 -#define TIMEN11 0x0008 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 -#define TIMEN3_P 0x03 -#define TIMEN4_P 0x04 -#define TIMEN5_P 0x05 -#define TIMEN6_P 0x06 -#define TIMEN7_P 0x07 -#define TIMEN8_P 0x00 -#define TIMEN9_P 0x01 -#define TIMEN10_P 0x02 -#define TIMEN11_P 0x03 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 -#define TIMDIS3 0x0008 -#define TIMDIS4 0x0010 -#define TIMDIS5 0x0020 -#define TIMDIS6 0x0040 -#define TIMDIS7 0x0080 -#define TIMDIS8 0x0001 -#define TIMDIS9 0x0002 -#define TIMDIS10 0x0004 -#define TIMDIS11 0x0008 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 -#define TIMDIS3_P 0x03 -#define TIMDIS4_P 0x04 -#define TIMDIS5_P 0x05 -#define TIMDIS6_P 0x06 -#define TIMDIS7_P 0x07 -#define TIMDIS8_P 0x00 -#define TIMDIS9_P 0x01 -#define TIMDIS10_P 0x02 -#define TIMDIS11_P 0x03 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x00000001 -#define TIMIL1 0x00000002 -#define TIMIL2 0x00000004 -#define TIMIL3 0x00000008 -#define TIMIL4 0x00010000 -#define TIMIL5 0x00020000 -#define TIMIL6 0x00040000 -#define TIMIL7 0x00080000 -#define TIMIL8 0x0001 -#define TIMIL9 0x0002 -#define TIMIL10 0x0004 -#define TIMIL11 0x0008 -#define TOVF_ERR0 0x00000010 -#define TOVF_ERR1 0x00000020 -#define TOVF_ERR2 0x00000040 -#define TOVF_ERR3 0x00000080 -#define TOVF_ERR4 0x00100000 -#define TOVF_ERR5 0x00200000 -#define TOVF_ERR6 0x00400000 -#define TOVF_ERR7 0x00800000 -#define TOVF_ERR8 0x0010 -#define TOVF_ERR9 0x0020 -#define TOVF_ERR10 0x0040 -#define TOVF_ERR11 0x0080 -#define TRUN0 0x00001000 -#define TRUN1 0x00002000 -#define TRUN2 0x00004000 -#define TRUN3 0x00008000 -#define TRUN4 0x10000000 -#define TRUN5 0x20000000 -#define TRUN6 0x40000000 -#define TRUN7 0x80000000 -#define TRUN8 0x1000 -#define TRUN9 0x2000 -#define TRUN10 0x4000 -#define TRUN11 0x8000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TIMIL3_P 0x03 -#define TIMIL4_P 0x10 -#define TIMIL5_P 0x11 -#define TIMIL6_P 0x12 -#define TIMIL7_P 0x13 -#define TIMIL8_P 0x00 -#define TIMIL9_P 0x01 -#define TIMIL10_P 0x02 -#define TIMIL11_P 0x03 -#define TOVF_ERR0_P 0x04 -#define TOVF_ERR1_P 0x05 -#define TOVF_ERR2_P 0x06 -#define TOVF_ERR3_P 0x07 -#define TOVF_ERR4_P 0x14 -#define TOVF_ERR5_P 0x15 -#define TOVF_ERR6_P 0x16 -#define TOVF_ERR7_P 0x17 -#define TOVF_ERR8_P 0x04 -#define TOVF_ERR9_P 0x05 -#define TOVF_ERR10_P 0x06 -#define TOVF_ERR11_P 0x07 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E -#define TRUN3_P 0x0F -#define TRUN4_P 0x1C -#define TRUN5_P 0x1D -#define TRUN6_P 0x1E -#define TRUN7_P 0x1F -#define TRUN8_P 0x0C -#define TRUN9_P 0x0D -#define TRUN10_P 0x0E -#define TRUN11_P 0x0F - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 -#define TOVL_ERR8 TOVF_ERR8 -#define TOVL_ERR9 TOVF_ERR9 -#define TOVL_ERR10 TOVF_ERR10 -#define TOVL_ERR11 TOVF_ERR11 -#define TOVL_ERR0_P TOVF_ERR0_P -#define TOVL_ERR1_P TOVF_ERR1_P -#define TOVL_ERR2_P TOVF_ERR2_P -#define TOVL_ERR3_P TOVF_ERR3_P -#define TOVL_ERR4_P TOVF_ERR4_P -#define TOVL_ERR5_P TOVF_ERR5_P -#define TOVL_ERR6_P TOVF_ERR6_P -#define TOVL_ERR7_P TOVF_ERR7_P -#define TOVL_ERR8_P TOVF_ERR8_P -#define TOVL_ERR9_P TOVF_ERR9_P -#define TOVL_ERR10_P TOVF_ERR10_P -#define TOVL_ERR11_P TOVF_ERR11_P - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ - -/* AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ -#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ -#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ -#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ -#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ - -/* AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ -#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */ -#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */ -#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */ -#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */ - -/* AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* ********************** SDRAM CONTROLLER MASKS *************************** */ - -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /*Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */ -#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */ -#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */ -#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */ -#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */ -#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */ -#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */ -#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */ - -#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */ -#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */ -#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */ -#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */ -#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */ -#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */ -#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */ - -#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */ -#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */ -#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */ -#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */ -#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */ -#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */ -#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - -#endif /* _DEF_BF561_H */ diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h deleted file mode 100644 index 13647c71f1c7..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/dma.h +++ /dev/null @@ -1,39 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define MAX_DMA_CHANNELS 36 - -/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */ -#define MAX_DMA_SUSPEND_CHANNELS 32 - -#define CH_PPI0 0 -#define CH_PPI (CH_PPI0) -#define CH_PPI1 1 -#define CH_SPORT0_RX 12 -#define CH_SPORT0_TX 13 -#define CH_SPORT1_RX 14 -#define CH_SPORT1_TX 15 -#define CH_SPI 16 -#define CH_UART_RX 17 -#define CH_UART_TX 18 -#define CH_MEM_STREAM0_DEST 24 /* TX */ -#define CH_MEM_STREAM0_SRC 25 /* RX */ -#define CH_MEM_STREAM1_DEST 26 /* TX */ -#define CH_MEM_STREAM1_SRC 27 /* RX */ -#define CH_MEM_STREAM2_DEST 28 -#define CH_MEM_STREAM2_SRC 29 -#define CH_MEM_STREAM3_DEST 30 -#define CH_MEM_STREAM3_SRC 31 -#define CH_IMEM_STREAM0_DEST 32 -#define CH_IMEM_STREAM0_SRC 33 -#define CH_IMEM_STREAM1_DEST 34 -#define CH_IMEM_STREAM1_SRC 35 - -#endif diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h deleted file mode 100644 index f9f8b2adf4ba..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/gpio.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 48 - -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 -#define GPIO_PF16 16 -#define GPIO_PF17 17 -#define GPIO_PF18 18 -#define GPIO_PF19 19 -#define GPIO_PF20 20 -#define GPIO_PF21 21 -#define GPIO_PF22 22 -#define GPIO_PF23 23 -#define GPIO_PF24 24 -#define GPIO_PF25 25 -#define GPIO_PF26 26 -#define GPIO_PF27 27 -#define GPIO_PF28 28 -#define GPIO_PF29 29 -#define GPIO_PF30 30 -#define GPIO_PF31 31 -#define GPIO_PF32 32 -#define GPIO_PF33 33 -#define GPIO_PF34 34 -#define GPIO_PF35 35 -#define GPIO_PF36 36 -#define GPIO_PF37 37 -#define GPIO_PF38 38 -#define GPIO_PF39 39 -#define GPIO_PF40 40 -#define GPIO_PF41 41 -#define GPIO_PF42 42 -#define GPIO_PF43 43 -#define GPIO_PF44 44 -#define GPIO_PF45 45 -#define GPIO_PF46 46 -#define GPIO_PF47 47 - -#define PORT_FIO0 GPIO_PF0 -#define PORT_FIO1 GPIO_PF16 -#define PORT_FIO2 GPIO_PF32 - -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h deleted file mode 100644 index d6998520f70f..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/irq.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BF561_IRQ_H_ -#define _BF561_IRQ_H_ - -#include - -#define NR_PERI_INTS (2 * 32) - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */ -#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ -#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */ -#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */ -#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */ -#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ -#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */ -#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */ -#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */ -#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */ -#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */ -#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ -#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ -#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */ -#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ -#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */ -#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */ -#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */ -#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */ -#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */ -#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */ -#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */ -#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */ -#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */ -#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */ -#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */ -#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ -#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */ -#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ -#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */ -#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ -#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */ -#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ -#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */ -#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ -#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */ -#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ -#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */ -#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ -#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */ -#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */ -#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */ -#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */ -#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */ -#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */ -#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */ -#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */ -#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */ -#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */ -#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */ -#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */ -#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */ -#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */ -#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */ -#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */ -#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */ -#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */ -#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ -#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */ -#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ -#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */ -#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */ -#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */ -#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */ -#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */ -#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ -#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 -#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */ -#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ -#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 -#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */ -#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 -#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */ -#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 -#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */ -#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 -#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */ -#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 -#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */ -#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */ -#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */ -#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */ -#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */ - -#define SYS_IRQS 71 - -#define IRQ_PF0 73 -#define IRQ_PF1 74 -#define IRQ_PF2 75 -#define IRQ_PF3 76 -#define IRQ_PF4 77 -#define IRQ_PF5 78 -#define IRQ_PF6 79 -#define IRQ_PF7 80 -#define IRQ_PF8 81 -#define IRQ_PF9 82 -#define IRQ_PF10 83 -#define IRQ_PF11 84 -#define IRQ_PF12 85 -#define IRQ_PF13 86 -#define IRQ_PF14 87 -#define IRQ_PF15 88 -#define IRQ_PF16 89 -#define IRQ_PF17 90 -#define IRQ_PF18 91 -#define IRQ_PF19 92 -#define IRQ_PF20 93 -#define IRQ_PF21 94 -#define IRQ_PF22 95 -#define IRQ_PF23 96 -#define IRQ_PF24 97 -#define IRQ_PF25 98 -#define IRQ_PF26 99 -#define IRQ_PF27 100 -#define IRQ_PF28 101 -#define IRQ_PF29 102 -#define IRQ_PF30 103 -#define IRQ_PF31 104 -#define IRQ_PF32 105 -#define IRQ_PF33 106 -#define IRQ_PF34 107 -#define IRQ_PF35 108 -#define IRQ_PF36 109 -#define IRQ_PF37 110 -#define IRQ_PF38 111 -#define IRQ_PF39 112 -#define IRQ_PF40 113 -#define IRQ_PF41 114 -#define IRQ_PF42 115 -#define IRQ_PF43 116 -#define IRQ_PF44 117 -#define IRQ_PF45 118 -#define IRQ_PF46 119 -#define IRQ_PF47 120 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define NR_MACH_IRQS (IRQ_PF47 + 1) - -/* IAR0 BIT FIELDS */ -#define IRQ_PLL_WAKEUP_POS 0 -#define IRQ_DMA1_ERROR_POS 4 -#define IRQ_DMA2_ERROR_POS 8 -#define IRQ_IMDMA_ERROR_POS 12 -#define IRQ_PPI0_ERROR_POS 16 -#define IRQ_PPI1_ERROR_POS 20 -#define IRQ_SPORT0_ERROR_POS 24 -#define IRQ_SPORT1_ERROR_POS 28 - -/* IAR1 BIT FIELDS */ -#define IRQ_SPI_ERROR_POS 0 -#define IRQ_UART_ERROR_POS 4 -#define IRQ_RESERVED_ERROR_POS 8 -#define IRQ_DMA1_0_POS 12 -#define IRQ_DMA1_1_POS 16 -#define IRQ_DMA1_2_POS 20 -#define IRQ_DMA1_3_POS 24 -#define IRQ_DMA1_4_POS 28 - -/* IAR2 BIT FIELDS */ -#define IRQ_DMA1_5_POS 0 -#define IRQ_DMA1_6_POS 4 -#define IRQ_DMA1_7_POS 8 -#define IRQ_DMA1_8_POS 12 -#define IRQ_DMA1_9_POS 16 -#define IRQ_DMA1_10_POS 20 -#define IRQ_DMA1_11_POS 24 -#define IRQ_DMA2_0_POS 28 - -/* IAR3 BIT FIELDS */ -#define IRQ_DMA2_1_POS 0 -#define IRQ_DMA2_2_POS 4 -#define IRQ_DMA2_3_POS 8 -#define IRQ_DMA2_4_POS 12 -#define IRQ_DMA2_5_POS 16 -#define IRQ_DMA2_6_POS 20 -#define IRQ_DMA2_7_POS 24 -#define IRQ_DMA2_8_POS 28 - -/* IAR4 BIT FIELDS */ -#define IRQ_DMA2_9_POS 0 -#define IRQ_DMA2_10_POS 4 -#define IRQ_DMA2_11_POS 8 -#define IRQ_TIMER0_POS 12 -#define IRQ_TIMER1_POS 16 -#define IRQ_TIMER2_POS 20 -#define IRQ_TIMER3_POS 24 -#define IRQ_TIMER4_POS 28 - -/* IAR5 BIT FIELDS */ -#define IRQ_TIMER5_POS 0 -#define IRQ_TIMER6_POS 4 -#define IRQ_TIMER7_POS 8 -#define IRQ_TIMER8_POS 12 -#define IRQ_TIMER9_POS 16 -#define IRQ_TIMER10_POS 20 -#define IRQ_TIMER11_POS 24 -#define IRQ_PROG0_INTA_POS 28 - -/* IAR6 BIT FIELDS */ -#define IRQ_PROG0_INTB_POS 0 -#define IRQ_PROG1_INTA_POS 4 -#define IRQ_PROG1_INTB_POS 8 -#define IRQ_PROG2_INTA_POS 12 -#define IRQ_PROG2_INTB_POS 16 -#define IRQ_DMA1_WRRD0_POS 20 -#define IRQ_DMA1_WRRD1_POS 24 -#define IRQ_DMA2_WRRD0_POS 28 - -/* IAR7 BIT FIELDS */ -#define IRQ_DMA2_WRRD1_POS 0 -#define IRQ_IMDMA_WRRD0_POS 4 -#define IRQ_IMDMA_WRRD1_POS 8 -#define IRQ_WDTIMER_POS 12 -#define IRQ_RESERVED_1_POS 16 -#define IRQ_RESERVED_2_POS 20 -#define IRQ_SUPPLE_0_POS 24 -#define IRQ_SUPPLE_1_POS 28 - -#endif diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h deleted file mode 100644 index 4cc91995f781..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * BF561 memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x800 - -/* Level 1 Memory */ - -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#else -#define BFIN_ICACHESIZE (0*1024) -#endif - -/* Memory Map for ADSP-BF561 processors */ - -#define COREA_L1_CODE_START 0xFFA00000 -#define COREA_L1_DATA_A_START 0xFF800000 -#define COREA_L1_DATA_B_START 0xFF900000 -#define COREB_L1_CODE_START 0xFF600000 -#define COREB_L1_DATA_A_START 0xFF400000 -#define COREB_L1_DATA_B_START 0xFF500000 - -#define L1_CODE_START COREA_L1_CODE_START -#define L1_DATA_A_START COREA_L1_DATA_A_START -#define L1_DATA_B_START COREA_L1_DATA_B_START - -#define L1_CODE_LENGTH 0x4000 - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ - -/* - * If we are in SMP mode, then the cache settings of Core B will match - * the settings of Core A. If we aren't, then we assume Core B is not - * using any cache. This allows the rest of the kernel to work with - * the core in either mode as we are only loading user code into it and - * it is the user's problem to make sure they aren't doing something - * stupid there. - * - * Note that we treat the L1 code region as a contiguous blob to make - * the rest of the kernel simpler. Easier to check one region than a - * bunch of small ones. Again, possible misbehavior here is the fault - * of the user -- don't try to use memory that doesn't exist. - */ -#ifdef CONFIG_SMP -# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH -# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH -# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH -#else -# define COREB_L1_CODE_LENGTH 0x14000 -# define COREB_L1_DATA_A_LENGTH 0x8000 -# define COREB_L1_DATA_B_LENGTH 0x8000 -#endif - -/* Level 2 Memory */ -#define L2_START 0xFEB00000 -#define L2_LENGTH 0x20000 - -/* Scratch Pad Memory */ - -#define COREA_L1_SCRATCH_START 0xFFB00000 -#define COREB_L1_SCRATCH_START 0xFF700000 - -#ifdef CONFIG_SMP - -/* - * The following macros both return the address of the PDA for the - * current core. - * - * In its first safe (and hairy) form, the macro neither clobbers any - * register aside of the output Preg, nor uses the stack, since it - * could be called with an invalid stack pointer, or the current stack - * space being uncovered by any CPLB (e.g. early exception handling). - * - * The constraints on the second form are a bit relaxed, and the code - * is allowed to use the specified Dreg for determining the PDA - * address to be returned into Preg. - */ -# define GET_PDA_SAFE(preg) \ - preg.l = lo(DSPID); \ - preg.h = hi(DSPID); \ - preg = [preg]; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - preg = preg << 2; \ - if cc jump 2f; \ - cc = preg == 0x0; \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; \ - if !cc jump 3f; \ -1: \ - /* preg = 0x0; */ \ - cc = !cc; /* restore cc to 0 */ \ - jump 4f; \ -2: \ - cc = preg == 0x0; \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; \ - if cc jump 4f; \ - /* preg = 0x1000000; */ \ - cc = !cc; /* restore cc to 1 */ \ -3: \ - preg = [preg]; \ -4: - -# define GET_PDA(preg, dreg) \ - preg.l = lo(DSPID); \ - preg.h = hi(DSPID); \ - dreg = [preg]; \ - preg.l = _cpu_pda; \ - preg.h = _cpu_pda; \ - cc = bittst(dreg, 0); \ - if !cc jump 1f; \ - preg = [preg]; \ -1: \ - -# define GET_CPUID(preg, dreg) \ - preg.l = lo(DSPID); \ - preg.h = hi(DSPID); \ - dreg = [preg]; \ - dreg = ROT dreg BY -1; \ - dreg = CC; - -# ifndef __ASSEMBLY__ - -# include - -static inline unsigned long get_l1_scratch_start_cpu(int cpu) -{ - return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; -} -static inline unsigned long get_l1_code_start_cpu(int cpu) -{ - return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START; -} -static inline unsigned long get_l1_data_a_start_cpu(int cpu) -{ - return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; -} -static inline unsigned long get_l1_data_b_start_cpu(int cpu) -{ - return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; -} - -static inline unsigned long get_l1_scratch_start(void) -{ - return get_l1_scratch_start_cpu(blackfin_core_id()); -} -static inline unsigned long get_l1_code_start(void) -{ - return get_l1_code_start_cpu(blackfin_core_id()); -} -static inline unsigned long get_l1_data_a_start(void) -{ - return get_l1_data_a_start_cpu(blackfin_core_id()); -} -static inline unsigned long get_l1_data_b_start(void) -{ - return get_l1_data_b_start_cpu(blackfin_core_id()); -} - -# endif /* __ASSEMBLY__ */ -#endif /* CONFIG_SMP */ - -#endif diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h deleted file mode 100644 index 00bdacee9cc2..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/pll.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_PLL_H -#define _MACH_PLL_H - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_SMP - -#include -#include -#include - -#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32) -#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32) - -static inline void -bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2) -{ - unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0); - - bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0); - bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1); -} -#define bfin_iwr_restore bfin_iwr_restore - -static inline void -bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2, - unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) -{ - unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0); - - *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF); - *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF); - bfin_iwr_restore(niwr0, niwr1, niwr2); -} -#define bfin_iwr_save bfin_iwr_save - -static inline void -bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) -{ - bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) | - IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2); -} - -#endif - -#endif - -#include - -#endif diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h deleted file mode 100644 index 2339ffd0dde8..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/portmux.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define MAX_RESOURCES MAX_BLACKFIN_GPIOS - -#define P_PPI0_CLK (P_DONTCARE) -#define P_PPI0_FS1 (P_DONTCARE) -#define P_PPI0_FS2 (P_DONTCARE) -#define P_PPI0_FS3 (P_DONTCARE) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) -#define P_PPI0_D0 (P_DONTCARE) -#define P_PPI0_D1 (P_DONTCARE) -#define P_PPI0_D2 (P_DONTCARE) -#define P_PPI0_D3 (P_DONTCARE) -#define P_PPI0_D4 (P_DONTCARE) -#define P_PPI0_D5 (P_DONTCARE) -#define P_PPI0_D6 (P_DONTCARE) -#define P_PPI0_D7 (P_DONTCARE) -#define P_PPI1_CLK (P_DONTCARE) -#define P_PPI1_FS1 (P_DONTCARE) -#define P_PPI1_FS2 (P_DONTCARE) -#define P_PPI1_FS3 (P_DONTCARE) -#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) -#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) -#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) -#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) -#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) -#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) -#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) -#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) -#define P_PPI1_D0 (P_DONTCARE) -#define P_PPI1_D1 (P_DONTCARE) -#define P_PPI1_D2 (P_DONTCARE) -#define P_PPI1_D3 (P_DONTCARE) -#define P_PPI1_D4 (P_DONTCARE) -#define P_PPI1_D5 (P_DONTCARE) -#define P_PPI1_D6 (P_DONTCARE) -#define P_PPI1_D7 (P_DONTCARE) -#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) -#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) -#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) -#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) -#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) -#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) -#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) -#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) -#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) -#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) -#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) -#define P_SPORT1_DRPRI (P_DONTCARE) -#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) -#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) -#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) -#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) -#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) -#define P_SPORT0_DRPRI (P_DONTCARE) -#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) -#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) -#define P_TMR11 (P_DONTCARE) -#define P_TMR10 (P_DONTCARE) -#define P_TMR9 (P_DONTCARE) -#define P_TMR8 (P_DONTCARE) -#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) -#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) -#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) -#define P_SPI0_MOSI (P_DONTCARE) -#define P_SPI0_MISO (P_DONTCARE) -#define P_SPI0_SCK (P_DONTCARE) -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h deleted file mode 100644 index 346c60589be6..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/smp.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BF561_SMP -#define _MACH_BF561_SMP - -/* This header has to stand alone to avoid circular deps */ - -struct task_struct; - -void platform_init_cpus(void); - -void platform_prepare_cpus(unsigned int max_cpus); - -int platform_boot_secondary(unsigned int cpu, struct task_struct *idle); - -void platform_secondary_init(unsigned int cpu); - -void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler); - -void platform_send_ipi(cpumask_t callmap, int irq); - -void platform_send_ipi_cpu(unsigned int cpu, int irq); - -void platform_clear_ipi(unsigned int cpu, int irq); - -void bfin_local_timer_setup(void); - -#endif /* !_MACH_BF561_SMP */ diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c deleted file mode 100644 index 7ee9262fe132..000000000000 --- a/arch/blackfin/mach-bf561/ints-priority.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | - ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | - ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | - ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | - ((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) | - ((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) | - ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | - ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); - - bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | - ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | - ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | - ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | - ((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) | - ((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) | - ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | - ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); - - bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | - ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | - ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | - ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | - ((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) | - ((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) | - ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | - ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); - - bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | - ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | - ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | - ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | - ((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) | - ((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) | - ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | - ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); - - bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | - ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | - ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | - ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | - ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | - ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | - ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | - ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); - - bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | - ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | - ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | - ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | - ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) | - ((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) | - ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | - ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); - - bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | - ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | - ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | - ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | - ((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) | - ((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) | - ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | - ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); - - bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | - ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | - ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | - ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | - (0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) | - (0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS)); - - SSYNC(); -} diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S deleted file mode 100644 index 01e5408620ac..000000000000 --- a/arch/blackfin/mach-bf561/secondary.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * BF561 coreB bootstrap file - * - * Copyright 2007-2009 Analog Devices Inc. - * Philippe Gerum - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include - -/* - * This code must come first as CoreB is hardcoded (in hardware) - * to start at the beginning of its L1 instruction memory. - */ -.section .l1.text.head - -/* Lay the initial stack into the L1 scratch area of Core B */ -#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) - -ENTRY(_coreb_trampoline_start) - /* Enable Cycle Counter and Nesting Of Interrupts */ -#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES - R0 = SYSCFG_SNEN; -#else - R0 = SYSCFG_SNEN | SYSCFG_CCEN; -#endif - SYSCFG = R0; - - /* Optimization register tricks: keep a base value in the - * reserved P registers so we use the load/store with an - * offset syntax. R0 = [P5 + ]; - * P5 - core MMR base - * R6 - 0 - */ - r6 = 0; - p5.l = 0; - p5.h = hi(COREMMR_BASE); - - /* Zero out registers required by Blackfin ABI */ - - /* Disable circular buffers */ - L0 = r6; - L1 = r6; - L2 = r6; - L3 = r6; - - /* Disable hardware loops in case we were started by 'go' */ - LC0 = r6; - LC1 = r6; - - /* - * Clear ITEST_COMMAND and DTEST_COMMAND registers, - * Leaving these as non-zero can confuse the emulator - */ - [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6; - [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6; - CSYNC; - - trace_buffer_init(p0,r0); - - /* Turn off the icache */ - r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)]; - BITCLR (r1, ENICPLB_P); - [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1; - SSYNC; - - /* Turn off the dcache */ - r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)]; - BITCLR (r1, ENDCPLB_P); - [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1; - SSYNC; - - /* in case of double faults, save a few things */ - p1.l = _initial_pda_coreb; - p1.h = _initial_pda_coreb; - r4 = RETX; -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* Only save these if we are storing them, - * This happens here, since L1 gets clobbered - * below - */ - GET_PDA(p0, r0); - r0 = [p0 + PDA_DF_RETX]; - r1 = [p0 + PDA_DF_DCPLB]; - r2 = [p0 + PDA_DF_ICPLB]; - r3 = [p0 + PDA_DF_SEQSTAT]; - [p1 + PDA_INIT_DF_RETX] = r0; - [p1 + PDA_INIT_DF_DCPLB] = r1; - [p1 + PDA_INIT_DF_ICPLB] = r2; - [p1 + PDA_INIT_DF_SEQSTAT] = r3; -#endif - [p1 + PDA_INIT_RETX] = r4; - - /* Initialize stack pointer */ - sp.l = lo(INITIAL_STACK); - sp.h = hi(INITIAL_STACK); - fp = sp; - usp = sp; - - /* This section keeps the processor in supervisor mode - * during core B startup. Branches to the idle task. - */ - - /* EVT15 = _real_start */ - - p1.l = _coreb_start; - p1.h = _coreb_start; - [p5 + (EVT15 - COREMMR_BASE)] = p1; - csync; - - r0 = EVT_IVG15 (z); - sti r0; - - raise 15; - p0.l = .LWAIT_HERE; - p0.h = .LWAIT_HERE; - reti = p0; -#if defined(ANOMALY_05000281) - nop; nop; nop; -#endif - rti; - -.LWAIT_HERE: - jump .LWAIT_HERE; -ENDPROC(_coreb_trampoline_start) - -#ifdef CONFIG_HOTPLUG_CPU -.section ".text" -ENTRY(_coreb_die) - sp.l = lo(INITIAL_STACK); - sp.h = hi(INITIAL_STACK); - fp = sp; - usp = sp; - - CLI R2; - SSYNC; - IDLE; - STI R2; - - R0 = IWR_DISABLE_ALL; - P0.H = hi(SYSMMR_BASE); - P0.L = lo(SYSMMR_BASE); - [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0; - [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0; - SSYNC; - - p0.h = hi(COREB_L1_CODE_START); - p0.l = lo(COREB_L1_CODE_START); - jump (p0); -ENDPROC(_coreb_die) -#endif - -__INIT -ENTRY(_coreb_start) - [--sp] = reti; - - p0.l = lo(WDOGB_CTL); - p0.h = hi(WDOGB_CTL); - r0 = 0xAD6(z); - w[p0] = r0; /* Clear the watchdog. */ - ssync; - - /* - * switch to IDLE stack. - */ - p0.l = _secondary_stack; - p0.h = _secondary_stack; - sp = [p0]; - usp = sp; - fp = sp; -#ifdef CONFIG_HOTPLUG_CPU - p0.l = _hotplug_coreb; - p0.h = _hotplug_coreb; - r0 = [p0]; - cc = BITTST(r0, 0); - if cc jump 3f; -#endif - sp += -12; - call _init_pda - sp += 12; -#ifdef CONFIG_HOTPLUG_CPU -3: -#endif - call _secondary_start_kernel; -.L_exit: - jump.s .L_exit; -ENDPROC(_coreb_start) diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c deleted file mode 100644 index 8c0c80fd1a45..000000000000 --- a/arch/blackfin/mach-bf561/smp.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * Philippe Gerum - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include - -static DEFINE_SPINLOCK(boot_lock); - -/* - * platform_init_cpus() - Tell the world about how many cores we - * have. This is called while setting up the architecture support - * (setup_arch()), so don't be too demanding here with respect to - * available kernel services. - */ - -void __init platform_init_cpus(void) -{ - struct cpumask mask; - - cpumask_set_cpu(0, &mask); /* CoreA */ - cpumask_set_cpu(1, &mask); /* CoreB */ - init_cpu_possible(&mask); -} - -void __init platform_prepare_cpus(unsigned int max_cpus) -{ - struct cpumask mask; - - bfin_relocate_coreb_l1_mem(); - - /* Both cores ought to be present on a bf561! */ - cpumask_set_cpu(0, &mask); /* CoreA */ - cpumask_set_cpu(1, &mask); /* CoreB */ - init_cpu_present(&mask); -} - -int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ -{ - return -EINVAL; -} - -void platform_secondary_init(unsigned int cpu) -{ - /* Clone setup for peripheral interrupt sources from CoreA. */ - bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0()); - bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1()); - SSYNC(); - - /* Clone setup for IARs from CoreA. */ - bfin_write_SICB_IAR0(bfin_read_SIC_IAR0()); - bfin_write_SICB_IAR1(bfin_read_SIC_IAR1()); - bfin_write_SICB_IAR2(bfin_read_SIC_IAR2()); - bfin_write_SICB_IAR3(bfin_read_SIC_IAR3()); - bfin_write_SICB_IAR4(bfin_read_SIC_IAR4()); - bfin_write_SICB_IAR5(bfin_read_SIC_IAR5()); - bfin_write_SICB_IAR6(bfin_read_SIC_IAR6()); - bfin_write_SICB_IAR7(bfin_read_SIC_IAR7()); - bfin_write_SICB_IWR0(IWR_DISABLE_ALL); - bfin_write_SICB_IWR1(IWR_DISABLE_ALL); - SSYNC(); - - /* We are done with local CPU inits, unblock the boot CPU. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int platform_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - printk(KERN_INFO "Booting Core B.\n"); - - spin_lock(&boot_lock); - - if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) { - /* CoreB already running, sending ipi to wakeup it */ - smp_send_reschedule(cpu); - } else { - /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ - bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT); - SSYNC(); - } - - timeout = jiffies + HZ; - /* release the lock and let coreb run */ - spin_unlock(&boot_lock); - while (time_before(jiffies, timeout)) { - if (cpu_online(cpu)) - break; - udelay(100); - barrier(); - } - - if (cpu_online(cpu)) { - return 0; - } else - panic("CPU%u: processor failed to boot\n", cpu); -} - -static const char supple0[] = "IRQ_SUPPLE_0"; -static const char supple1[] = "IRQ_SUPPLE_1"; -void __init platform_request_ipi(int irq, void *handler) -{ - int ret; - const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1; - - ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND | - IRQF_FORCE_RESUME, name, handler); - if (ret) - panic("Cannot request %s for IPI service", name); -} - -void platform_send_ipi(cpumask_t callmap, int irq) -{ - unsigned int cpu; - int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8; - - for_each_cpu(cpu, &callmap) { - BUG_ON(cpu >= 2); - SSYNC(); - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); - SSYNC(); - } -} - -void platform_send_ipi_cpu(unsigned int cpu, int irq) -{ - int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8; - BUG_ON(cpu >= 2); - SSYNC(); - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); - SSYNC(); -} - -void platform_clear_ipi(unsigned int cpu, int irq) -{ - int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12; - BUG_ON(cpu >= 2); - SSYNC(); - bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); - SSYNC(); -} - -/* - * Setup core B's local core timer. - * In SMP, core timer is used for clock event device. - */ -void bfin_local_timer_setup(void) -{ -#if defined(CONFIG_TICKSOURCE_CORETMR) - struct irq_data *data = irq_get_irq_data(IRQ_CORETMR); - struct irq_chip *chip = irq_data_get_irq_chip(data); - - bfin_coretmr_init(); - bfin_coretmr_clockevent_init(); - - chip->irq_unmask(data); -#else - /* Power down the core timer, just to play safe. */ - bfin_write_TCNTL(0); -#endif - -} diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig deleted file mode 100644 index 7d6a8b8926ba..000000000000 --- a/arch/blackfin/mach-bf609/Kconfig +++ /dev/null @@ -1,1684 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config BF60x - def_bool y - depends on (BF609) - select IRQ_PREFLOW_FASTEOI - -if (BF60x) - -source "arch/blackfin/mach-bf609/boards/Kconfig" - -menu "BF609 Specific Configuration" - -config SEC_IRQ_PRIORITY_LEVELS - int "SEC interrupt priority levels" - default 7 - range 0 7 - help - Divide the total number of interrupt priority levels into sub-levels. - There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels. - -config L1_PARITY_CHECK - bool "Enable L1 parity check" - default n - help - Enable the L1 parity check in L1 sram. A fault event is raised - when L1 parity error is found. - -comment "System Cross Bar Priority Assignment" - -config SCB_PRIORITY - bool "Init System Cross Bar Priority" - default n - -menuconfig SCB0_MI0 - bool "SCB0 Master Interface 0 (DDR)" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - Core 0 -- 0 - Core 1 -- 2 - SCB1 -- 9 - SCB2 -- 10 - SCB3 -- 11 - SCB4 -- 12 - SCB5 -- 5 - SCB6 -- 6 - SCB7 -- 8 - SCB8 -- 7 - SCB9 -- 4 - USB -- 13 - -if SCB0_MI0 - -config SCB0_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 13 - -config SCB0_MI0_SLOT1 - int "Slot 1 slave interface id" - default 2 - range 0 13 - -config SCB0_MI0_SLOT2 - int "Slot 2 slave interface id" - default 4 - range 0 13 - -config SCB0_MI0_SLOT3 - int "Slot 3 slave interface id" - default 5 - range 0 13 - -config SCB0_MI0_SLOT4 - int "Slot 4 slave interface id" - default 6 - range 0 13 - -config SCB0_MI0_SLOT5 - int "Slot 5 slave interface id" - default 7 - range 0 13 - -config SCB0_MI0_SLOT6 - int "Slot 6 slave interface id" - default 8 - range 0 13 - -config SCB0_MI0_SLOT7 - int "Slot 7 slave interface id" - default 9 - range 0 13 - -config SCB0_MI0_SLOT8 - int "Slot 8 slave interface id" - default 10 - range 0 13 - -config SCB0_MI0_SLOT9 - int "Slot 9 slave interface id" - default 11 - range 0 13 - -config SCB0_MI0_SLOT10 - int "Slot 10 slave interface id" - default 13 - range 0 13 - -config SCB0_MI0_SLOT11 - int "Slot 11 slave interface id" - default 12 - range 0 13 - -config SCB0_MI0_SLOT12 - int "Slot 12 slave interface id" - default 0 - range 0 13 - -config SCB0_MI0_SLOT13 - int "Slot 13 slave interface id" - default 2 - range 0 13 - -config SCB0_MI0_SLOT14 - int "Slot 14 slave interface id" - default 4 - range 0 13 - -config SCB0_MI0_SLOT15 - int "Slot 15 slave interface id" - default 5 - range 0 13 - -config SCB0_MI0_SLOT16 - int "Slot 16 slave interface id" - default 6 - range 0 13 - -config SCB0_MI0_SLOT17 - int "Slot 17 slave interface id" - default 7 - range 0 13 - -config SCB0_MI0_SLOT18 - int "Slot 18 slave interface id" - default 8 - range 0 13 - -config SCB0_MI0_SLOT19 - int "Slot 19 slave interface id" - default 9 - range 0 13 - -config SCB0_MI0_SLOT20 - int "Slot 20 slave interface id" - default 10 - range 0 13 - -config SCB0_MI0_SLOT21 - int "Slot 21 slave interface id" - default 11 - range 0 13 - -config SCB0_MI0_SLOT22 - int "Slot 22 slave interface id" - default 13 - range 0 13 - -config SCB0_MI0_SLOT23 - int "Slot 23 slave interface id" - default 12 - range 0 13 - -config SCB0_MI0_SLOT24 - int "Slot 24 slave interface id" - default 0 - range 0 13 - -config SCB0_MI0_SLOT25 - int "Slot 25 slave interface id" - default 2 - range 0 13 - -config SCB0_MI0_SLOT26 - int "Slot 26 slave interface id" - default 4 - range 0 13 - -config SCB0_MI0_SLOT27 - int "Slot 27 slave interface id" - default 5 - range 0 13 - -config SCB0_MI0_SLOT28 - int "Slot 28 slave interface id" - default 6 - range 0 13 - -config SCB0_MI0_SLOT29 - int "Slot 29 slave interface id" - default 7 - range 0 13 - -config SCB0_MI0_SLOT30 - int "Slot 30 slave interface id" - default 8 - range 0 13 - -config SCB0_MI0_SLOT31 - int "Slot 31 slave interface id" - default 13 - range 0 13 - -endif # SCB0_MI0 - -menuconfig SCB0_MI1 - bool "SCB0 Master Interface 1 (SMC)" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - Core 0 -- 0 - Core 1 -- 2 - SCB1 -- 9 - SCB2 -- 10 - SCB3 -- 11 - SCB4 -- 12 - SCB5 -- 5 - SCB6 -- 6 - SCB7 -- 8 - SCB8 -- 7 - SCB9 -- 4 - USB -- 13 - -if SCB0_MI1 - -config SCB0_MI1_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 13 - -config SCB0_MI1_SLOT1 - int "Slot 1 slave interface id" - default 2 - range 0 13 - -config SCB0_MI1_SLOT2 - int "Slot 2 slave interface id" - default 4 - range 0 13 - -config SCB0_MI1_SLOT3 - int "Slot 3 slave interface id" - default 5 - range 0 13 - -config SCB0_MI1_SLOT4 - int "Slot 4 slave interface id" - default 6 - range 0 13 - -config SCB0_MI1_SLOT5 - int "Slot 5 slave interface id" - default 7 - range 0 13 - -config SCB0_MI1_SLOT6 - int "Slot 6 slave interface id" - default 8 - range 0 13 - -config SCB0_MI1_SLOT7 - int "Slot 7 slave interface id" - default 9 - range 0 13 - -config SCB0_MI1_SLOT8 - int "Slot 8 slave interface id" - default 10 - range 0 13 - -config SCB0_MI1_SLOT9 - int "Slot 9 slave interface id" - default 11 - range 0 13 - -config SCB0_MI1_SLOT10 - int "Slot 10 slave interface id" - default 13 - range 0 13 - -config SCB0_MI1_SLOT11 - int "Slot 11 slave interface id" - default 12 - range 0 13 - -config SCB0_MI1_SLOT12 - int "Slot 12 slave interface id" - default 0 - range 0 13 - -config SCB0_MI1_SLOT13 - int "Slot 13 slave interface id" - default 2 - range 0 13 - -config SCB0_MI1_SLOT14 - int "Slot 14 slave interface id" - default 4 - range 0 13 - -config SCB0_MI1_SLOT15 - int "Slot 15 slave interface id" - default 5 - range 0 13 - -config SCB0_MI1_SLOT16 - int "Slot 16 slave interface id" - default 6 - range 0 13 - -config SCB0_MI1_SLOT17 - int "Slot 17 slave interface id" - default 7 - range 0 13 - -config SCB0_MI1_SLOT18 - int "Slot 18 slave interface id" - default 8 - range 0 13 - -config SCB0_MI1_SLOT19 - int "Slot 19 slave interface id" - default 9 - range 0 13 - -config SCB0_MI1_SLOT20 - int "Slot 20 slave interface id" - default 10 - range 0 13 - -config SCB0_MI1_SLOT21 - int "Slot 21 slave interface id" - default 11 - range 0 13 - -config SCB0_MI1_SLOT22 - int "Slot 22 slave interface id" - default 13 - range 0 13 - -config SCB0_MI1_SLOT23 - int "Slot 23 slave interface id" - default 12 - range 0 13 - -config SCB0_MI1_SLOT24 - int "Slot 24 slave interface id" - default 0 - range 0 13 - -config SCB0_MI1_SLOT25 - int "Slot 25 slave interface id" - default 2 - range 0 13 - -config SCB0_MI1_SLOT26 - int "Slot 26 slave interface id" - default 4 - range 0 13 - -config SCB0_MI1_SLOT27 - int "Slot 27 slave interface id" - default 5 - range 0 13 - -config SCB0_MI1_SLOT28 - int "Slot 28 slave interface id" - default 6 - range 0 13 - -config SCB0_MI1_SLOT29 - int "Slot 29 slave interface id" - default 7 - range 0 13 - -config SCB0_MI1_SLOT30 - int "Slot 30 slave interface id" - default 8 - range 0 13 - -config SCB0_MI1_SLOT31 - int "Slot 31 slave interface id" - default 13 - range 0 13 - -endif # SCB0_MI1 - -menuconfig SCB0_MI2 - bool "SCB0 Master Interface 2 (Data L2)" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - Core 0 -- 0 - Core 1 -- 2 - SCB1 -- 9 - SCB2 -- 10 - SCB3 -- 11 - SCB4 -- 12 - SCB5 -- 5 - SCB6 -- 6 - SCB7 -- 8 - SCB8 -- 7 - SCB9 -- 4 - USB -- 13 - -if SCB0_MI2 - -config SCB0_MI2_SLOT0 - int "Slot 0 slave interface id" - default 4 - range 0 13 - -config SCB0_MI2_SLOT1 - int "Slot 1 slave interface id" - default 5 - range 0 13 - -config SCB0_MI2_SLOT2 - int "Slot 2 slave interface id" - default 6 - range 0 13 - -config SCB0_MI2_SLOT3 - int "Slot 3 slave interface id" - default 7 - range 0 13 - -config SCB0_MI2_SLOT4 - int "Slot 4 slave interface id" - default 8 - range 0 13 - -config SCB0_MI2_SLOT5 - int "Slot 5 slave interface id" - default 9 - range 0 13 - -config SCB0_MI2_SLOT6 - int "Slot 6 slave interface id" - default 10 - range 0 13 - -config SCB0_MI2_SLOT7 - int "Slot 7 slave interface id" - default 11 - range 0 13 - -config SCB0_MI2_SLOT8 - int "Slot 8 slave interface id" - default 13 - range 0 13 - -config SCB0_MI2_SLOT9 - int "Slot 9 slave interface id" - default 12 - range 0 13 - -config SCB0_MI2_SLOT10 - int "Slot 10 slave interface id" - default 4 - range 0 13 - -config SCB0_MI2_SLOT11 - int "Slot 11 slave interface id" - default 5 - range 0 13 - -config SCB0_MI2_SLOT12 - int "Slot 12 slave interface id" - default 6 - range 0 13 - -config SCB0_MI2_SLOT13 - int "Slot 13 slave interface id" - default 7 - range 0 13 - -config SCB0_MI2_SLOT14 - int "Slot 14 slave interface id" - default 8 - range 0 13 - -config SCB0_MI2_SLOT15 - int "Slot 15 slave interface id" - default 9 - range 0 13 - -config SCB0_MI2_SLOT16 - int "Slot 16 slave interface id" - default 10 - range 0 13 - -config SCB0_MI2_SLOT17 - int "Slot 17 slave interface id" - default 11 - range 0 13 - -config SCB0_MI2_SLOT18 - int "Slot 18 slave interface id" - default 13 - range 0 13 - -config SCB0_MI2_SLOT19 - int "Slot 19 slave interface id" - default 12 - range 0 13 - -config SCB0_MI2_SLOT20 - int "Slot 20 slave interface id" - default 4 - range 0 13 - -config SCB0_MI2_SLOT21 - int "Slot 21 slave interface id" - default 5 - range 0 13 - -config SCB0_MI2_SLOT22 - int "Slot 22 slave interface id" - default 6 - range 0 13 - -config SCB0_MI2_SLOT23 - int "Slot 23 slave interface id" - default 7 - range 0 13 - -config SCB0_MI2_SLOT24 - int "Slot 24 slave interface id" - default 8 - range 0 13 - -config SCB0_MI2_SLOT25 - int "Slot 25 slave interface id" - default 9 - range 0 13 - -config SCB0_MI2_SLOT26 - int "Slot 26 slave interface id" - default 10 - range 0 13 - -config SCB0_MI2_SLOT27 - int "Slot 27 slave interface id" - default 11 - range 0 13 - -config SCB0_MI2_SLOT28 - int "Slot 28 slave interface id" - default 13 - range 0 13 - -config SCB0_MI2_SLOT29 - int "Slot 29 slave interface id" - default 12 - range 0 13 - -config SCB0_MI2_SLOT30 - int "Slot 30 slave interface id" - default 4 - range 0 13 - -config SCB0_MI2_SLOT31 - int "Slot 31 slave interface id" - default 7 - range 0 13 - -endif # SCB0_MI2 - -menuconfig SCB0_MI3 - bool "SCB0 Master Interface 3 (L1A)" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - Core 0 -- 0 - Core 1 -- 2 - SCB1 -- 9 - SCB2 -- 10 - SCB3 -- 11 - SCB4 -- 12 - SCB5 -- 5 - SCB6 -- 6 - SCB7 -- 8 - SCB8 -- 7 - SCB9 -- 4 - USB -- 13 - -if SCB0_MI3 - -config SCB0_MI3_SLOT0 - int "Slot 0 slave interface id" - default 4 - range 0 13 - -config SCB0_MI3_SLOT1 - int "Slot 1 slave interface id" - default 5 - range 0 13 - -config SCB0_MI3_SLOT2 - int "Slot 2 slave interface id" - default 6 - range 0 13 - -config SCB0_MI3_SLOT3 - int "Slot 3 slave interface id" - default 7 - range 0 13 - -config SCB0_MI3_SLOT4 - int "Slot 4 slave interface id" - default 8 - range 0 13 - -config SCB0_MI3_SLOT5 - int "Slot 5 slave interface id" - default 9 - range 0 13 - -config SCB0_MI3_SLOT6 - int "Slot 6 slave interface id" - default 10 - range 0 13 - -config SCB0_MI3_SLOT7 - int "Slot 7 slave interface id" - default 11 - range 0 13 - -config SCB0_MI3_SLOT8 - int "Slot 8 slave interface id" - default 13 - range 0 13 - -config SCB0_MI3_SLOT9 - int "Slot 9 slave interface id" - default 12 - range 0 13 - -config SCB0_MI3_SLOT10 - int "Slot 10 slave interface id" - default 4 - range 0 13 - -config SCB0_MI3_SLOT11 - int "Slot 11 slave interface id" - default 5 - range 0 13 - -config SCB0_MI3_SLOT12 - int "Slot 12 slave interface id" - default 6 - range 0 13 - -config SCB0_MI3_SLOT13 - int "Slot 13 slave interface id" - default 7 - range 0 13 - -config SCB0_MI3_SLOT14 - int "Slot 14 slave interface id" - default 8 - range 0 13 - -config SCB0_MI3_SLOT15 - int "Slot 15 slave interface id" - default 9 - range 0 13 - -config SCB0_MI3_SLOT16 - int "Slot 16 slave interface id" - default 10 - range 0 13 - -config SCB0_MI3_SLOT17 - int "Slot 17 slave interface id" - default 11 - range 0 13 - -config SCB0_MI3_SLOT18 - int "Slot 18 slave interface id" - default 13 - range 0 13 - -config SCB0_MI3_SLOT19 - int "Slot 19 slave interface id" - default 12 - range 0 13 - -config SCB0_MI3_SLOT20 - int "Slot 20 slave interface id" - default 4 - range 0 13 - -config SCB0_MI3_SLOT21 - int "Slot 21 slave interface id" - default 5 - range 0 13 - -config SCB0_MI3_SLOT22 - int "Slot 22 slave interface id" - default 6 - range 0 13 - -config SCB0_MI3_SLOT23 - int "Slot 23 slave interface id" - default 7 - range 0 13 - -config SCB0_MI3_SLOT24 - int "Slot 24 slave interface id" - default 8 - range 0 13 - -config SCB0_MI3_SLOT25 - int "Slot 25 slave interface id" - default 9 - range 0 13 - -config SCB0_MI3_SLOT26 - int "Slot 26 slave interface id" - default 10 - range 0 13 - -config SCB0_MI3_SLOT27 - int "Slot 27 slave interface id" - default 11 - range 0 13 - -config SCB0_MI3_SLOT28 - int "Slot 28 slave interface id" - default 13 - range 0 13 - -config SCB0_MI3_SLOT29 - int "Slot 29 slave interface id" - default 12 - range 0 13 - -config SCB0_MI3_SLOT30 - int "Slot 30 slave interface id" - default 4 - range 0 13 - -config SCB0_MI3_SLOT31 - int "Slot 31 slave interface id" - default 7 - range 0 13 - -endif # SCB0_MI3 - -menuconfig SCB0_MI4 - bool "SCB0 Master Interface 4 (L1B)" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - Core 0 -- 0 - Core 1 -- 2 - SCB1 -- 9 - SCB2 -- 10 - SCB3 -- 11 - SCB4 -- 12 - SCB5 -- 5 - SCB6 -- 6 - SCB7 -- 8 - SCB8 -- 7 - SCB9 -- 4 - USB -- 13 - -if SCB0_MI4 - -config SCB0_MI4_SLOT0 - int "Slot 0 slave interface id" - default 4 - range 0 13 - -config SCB0_MI4_SLOT1 - int "Slot 1 slave interface id" - default 5 - range 0 13 - -config SCB0_MI4_SLOT2 - int "Slot 2 slave interface id" - default 6 - range 0 13 - -config SCB0_MI4_SLOT3 - int "Slot 3 slave interface id" - default 7 - range 0 13 - -config SCB0_MI4_SLOT4 - int "Slot 4 slave interface id" - default 8 - range 0 13 - -config SCB0_MI4_SLOT5 - int "Slot 5 slave interface id" - default 9 - range 0 13 - -config SCB0_MI4_SLOT6 - int "Slot 6 slave interface id" - default 10 - range 0 13 - -config SCB0_MI4_SLOT7 - int "Slot 7 slave interface id" - default 11 - range 0 13 - -config SCB0_MI4_SLOT8 - int "Slot 8 slave interface id" - default 13 - range 0 13 - -config SCB0_MI4_SLOT9 - int "Slot 9 slave interface id" - default 12 - range 0 13 - -config SCB0_MI4_SLOT10 - int "Slot 10 slave interface id" - default 4 - range 0 13 - -config SCB0_MI4_SLOT11 - int "Slot 11 slave interface id" - default 5 - range 0 13 - -config SCB0_MI4_SLOT12 - int "Slot 12 slave interface id" - default 6 - range 0 13 - -config SCB0_MI4_SLOT13 - int "Slot 13 slave interface id" - default 7 - range 0 13 - -config SCB0_MI4_SLOT14 - int "Slot 14 slave interface id" - default 8 - range 0 13 - -config SCB0_MI4_SLOT15 - int "Slot 15 slave interface id" - default 9 - range 0 13 - -config SCB0_MI4_SLOT16 - int "Slot 16 slave interface id" - default 10 - range 0 13 - -config SCB0_MI4_SLOT17 - int "Slot 17 slave interface id" - default 11 - range 0 13 - -config SCB0_MI4_SLOT18 - int "Slot 18 slave interface id" - default 13 - range 0 13 - -config SCB0_MI4_SLOT19 - int "Slot 19 slave interface id" - default 12 - range 0 13 - -config SCB0_MI4_SLOT20 - int "Slot 20 slave interface id" - default 4 - range 0 13 - -config SCB0_MI4_SLOT21 - int "Slot 21 slave interface id" - default 5 - range 0 13 - -config SCB0_MI4_SLOT22 - int "Slot 22 slave interface id" - default 6 - range 0 13 - -config SCB0_MI4_SLOT23 - int "Slot 23 slave interface id" - default 7 - range 0 13 - -config SCB0_MI4_SLOT24 - int "Slot 24 slave interface id" - default 8 - range 0 13 - -config SCB0_MI4_SLOT25 - int "Slot 25 slave interface id" - default 9 - range 0 13 - -config SCB0_MI4_SLOT26 - int "Slot 26 slave interface id" - default 10 - range 0 13 - -config SCB0_MI4_SLOT27 - int "Slot 27 slave interface id" - default 11 - range 0 13 - -config SCB0_MI4_SLOT28 - int "Slot 28 slave interface id" - default 13 - range 0 13 - -config SCB0_MI4_SLOT29 - int "Slot 29 slave interface id" - default 12 - range 0 13 - -config SCB0_MI4_SLOT30 - int "Slot 30 slave interface id" - default 4 - range 0 13 - -config SCB0_MI4_SLOT31 - int "Slot 31 slave interface id" - default 7 - range 0 13 - -endif # SCB0_MI4 - -menuconfig SCB0_MI5 - bool "SCB0 Master Interface 5 (SMMR)" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - MMR0 -- 1 - MMR1 -- 3 - SCB2 -- 10 - SCB4 -- 12 - -if SCB0_MI5 - -config SCB0_MI5_SLOT0 - int "Slot 0 slave interface id" - default 1 - range 0 13 - -config SCB0_MI5_SLOT1 - int "Slot 1 slave interface id" - default 3 - range 0 13 - -config SCB0_MI5_SLOT2 - int "Slot 2 slave interface id" - default 10 - range 0 13 - -config SCB0_MI5_SLOT3 - int "Slot 3 slave interface id" - default 12 - range 0 13 - -config SCB0_MI5_SLOT4 - int "Slot 4 slave interface id" - default 1 - range 0 13 - -config SCB0_MI5_SLOT5 - int "Slot 5 slave interface id" - default 3 - range 0 13 - -config SCB0_MI5_SLOT6 - int "Slot 6 slave interface id" - default 10 - range 0 13 - -config SCB0_MI5_SLOT7 - int "Slot 7 slave interface id" - default 12 - range 0 13 - -config SCB0_MI5_SLOT8 - int "Slot 8 slave interface id" - default 1 - range 0 13 - -config SCB0_MI5_SLOT9 - int "Slot 9 slave interface id" - default 3 - range 0 13 - -config SCB0_MI5_SLOT10 - int "Slot 10 slave interface id" - default 10 - range 0 13 - -config SCB0_MI5_SLOT11 - int "Slot 11 slave interface id" - default 12 - range 0 13 - -config SCB0_MI5_SLOT12 - int "Slot 12 slave interface id" - default 1 - range 0 13 - -config SCB0_MI5_SLOT13 - int "Slot 13 slave interface id" - default 3 - range 0 13 - -config SCB0_MI5_SLOT14 - int "Slot 14 slave interface id" - default 10 - range 0 13 - -config SCB0_MI5_SLOT15 - int "Slot 15 slave interface id" - default 12 - range 0 13 - -endif # SCB0_MI5 - -menuconfig SCB1_MI0 - bool "SCB1 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - SPORT0A -- 0 - SPORT0B -- 1 - SPORT1A -- 2 - SPORT1B -- 3 - SPORT2A -- 4 - SPORT2B -- 5 - SPI0TX -- 6 - SPI0RX -- 7 - SPI1TX -- 8 - SPI1RX -- 9 - -if SCB1_MI0 - -config SCB1_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 9 - -config SCB1_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 9 - -config SCB1_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 9 - -config SCB1_MI0_SLOT3 - int "Slot 3 slave interface id" - default 3 - range 0 9 - -config SCB1_MI0_SLOT4 - int "Slot 4 slave interface id" - default 4 - range 0 9 - -config SCB1_MI0_SLOT5 - int "Slot 5 slave interface id" - default 5 - range 0 9 - -config SCB1_MI0_SLOT6 - int "Slot 6 slave interface id" - default 6 - range 0 9 - -config SCB1_MI0_SLOT7 - int "Slot 7 slave interface id" - default 7 - range 0 9 - -config SCB1_MI0_SLOT8 - int "Slot 8 slave interface id" - default 8 - range 0 9 - -config SCB1_MI0_SLOT9 - int "Slot 9 slave interface id" - default 9 - range 0 9 - -config SCB1_MI0_SLOT10 - int "Slot 10 slave interface id" - default 0 - range 0 9 - -config SCB1_MI0_SLOT11 - int "Slot 11 slave interface id" - default 1 - range 0 9 - -config SCB1_MI0_SLOT12 - int "Slot 12 slave interface id" - default 2 - range 0 9 - -config SCB1_MI0_SLOT13 - int "Slot 13 slave interface id" - default 3 - range 0 9 - -config SCB1_MI0_SLOT14 - int "Slot 14 slave interface id" - default 4 - range 0 9 - -config SCB1_MI0_SLOT15 - int "Slot 15 slave interface id" - default 5 - range 0 9 - -config SCB1_MI0_SLOT16 - int "Slot 16 slave interface id" - default 6 - range 0 13 - -config SCB1_MI0_SLOT17 - int "Slot 17 slave interface id" - default 7 - range 0 13 - -config SCB1_MI0_SLOT18 - int "Slot 18 slave interface id" - default 8 - range 0 13 - -config SCB1_MI0_SLOT19 - int "Slot 19 slave interface id" - default 9 - range 0 13 - -endif # SCB1_MI0 - -menuconfig SCB2_MI0 - bool "SCB2 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - RSI -- 0 - SDU DMA -- 1 - SDU -- 2 - EMAC0 -- 3 - EMAC1 -- 4 - -if SCB2_MI0 - -config SCB2_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 4 - -config SCB2_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 4 - -config SCB2_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 4 - -config SCB2_MI0_SLOT3 - int "Slot 3 slave interface id" - default 3 - range 0 4 - -config SCB2_MI0_SLOT4 - int "Slot 4 slave interface id" - default 4 - range 0 4 - -config SCB2_MI0_SLOT5 - int "Slot 5 slave interface id" - default 0 - range 0 4 - -config SCB2_MI0_SLOT6 - int "Slot 6 slave interface id" - default 1 - range 0 4 - -config SCB2_MI0_SLOT7 - int "Slot 7 slave interface id" - default 2 - range 0 4 - -config SCB2_MI0_SLOT8 - int "Slot 8 slave interface id" - default 3 - range 0 4 - -config SCB2_MI0_SLOT9 - int "Slot 9 slave interface id" - default 4 - range 0 4 - -endif # SCB2_MI0 - -menuconfig SCB3_MI0 - bool "SCB3 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - LP0 -- 0 - LP1 -- 1 - LP2 -- 2 - LP3 -- 3 - UART0TX -- 4 - UART0RX -- 5 - UART1TX -- 4 - UART1RX -- 5 - -if SCB3_MI0 - -config SCB3_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 7 - -config SCB3_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 7 - -config SCB3_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 7 - -config SCB3_MI0_SLOT3 - int "Slot 3 slave interface id" - default 3 - range 0 7 - -config SCB3_MI0_SLOT4 - int "Slot 4 slave interface id" - default 4 - range 0 7 - -config SCB3_MI0_SLOT5 - int "Slot 5 slave interface id" - default 5 - range 0 7 - -config SCB3_MI0_SLOT6 - int "Slot 6 slave interface id" - default 6 - range 0 7 - -config SCB3_MI0_SLOT7 - int "Slot 7 slave interface id" - default 7 - range 0 7 - -config SCB3_MI0_SLOT8 - int "Slot 8 slave interface id" - default 0 - range 0 7 - -config SCB3_MI0_SLOT9 - int "Slot 9 slave interface id" - default 1 - range 0 7 - -config SCB3_MI0_SLOT10 - int "Slot 10 slave interface id" - default 2 - range 0 7 - -config SCB3_MI0_SLOT11 - int "Slot 11 slave interface id" - default 3 - range 0 7 - -config SCB3_MI0_SLOT12 - int "Slot 12 slave interface id" - default 4 - range 0 7 - -config SCB3_MI0_SLOT13 - int "Slot 13 slave interface id" - default 5 - range 0 7 - -config SCB3_MI0_SLOT14 - int "Slot 14 slave interface id" - default 6 - range 0 7 - -config SCB3_MI0_SLOT15 - int "Slot 15 slave interface id" - default 7 - range 0 7 - -endif # SCB3_MI0 - -menuconfig SCB4_MI0 - bool "SCB4 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - MDA21 -- 0 - MDA22 -- 1 - MDA23 -- 2 - MDA24 -- 3 - MDA25 -- 4 - MDA26 -- 5 - MDA27 -- 6 - MDA28 -- 7 - -if SCB4_MI0 - -config SCB4_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 7 - -config SCB4_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 7 - -config SCB4_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 7 - -config SCB4_MI0_SLOT3 - int "Slot 3 slave interface id" - default 3 - range 0 7 - -config SCB4_MI0_SLOT4 - int "Slot 4 slave interface id" - default 4 - range 0 7 - -config SCB4_MI0_SLOT5 - int "Slot 5 slave interface id" - default 5 - range 0 7 - -config SCB4_MI0_SLOT6 - int "Slot 6 slave interface id" - default 6 - range 0 7 - -config SCB4_MI0_SLOT7 - int "Slot 7 slave interface id" - default 7 - range 0 7 - -config SCB4_MI0_SLOT8 - int "Slot 8 slave interface id" - default 0 - range 0 7 - -config SCB4_MI0_SLOT9 - int "Slot 9 slave interface id" - default 1 - range 0 7 - -config SCB4_MI0_SLOT10 - int "Slot 10 slave interface id" - default 2 - range 0 7 - -config SCB4_MI0_SLOT11 - int "Slot 11 slave interface id" - default 3 - range 0 7 - -config SCB4_MI0_SLOT12 - int "Slot 12 slave interface id" - default 4 - range 0 7 - -config SCB4_MI0_SLOT13 - int "Slot 13 slave interface id" - default 5 - range 0 7 - -config SCB4_MI0_SLOT14 - int "Slot 14 slave interface id" - default 6 - range 0 7 - -config SCB4_MI0_SLOT15 - int "Slot 15 slave interface id" - default 7 - range 0 7 - -endif # SCB4_MI0 - -menuconfig SCB5_MI0 - bool "SCB5 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - PPI0 MDA29 -- 0 - PPI0 MDA30 -- 1 - PPI2 MDA31 -- 2 - PPI2 MDA32 -- 3 - -if SCB5_MI0 - -config SCB5_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 3 - -config SCB5_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 3 - -config SCB5_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 3 - -config SCB5_MI0_SLOT3 - int "Slot 3 slave interface id" - default 3 - range 0 3 - -config SCB5_MI0_SLOT4 - int "Slot 4 slave interface id" - default 0 - range 0 3 - -config SCB5_MI0_SLOT5 - int "Slot 5 slave interface id" - default 1 - range 0 3 - -config SCB5_MI0_SLOT6 - int "Slot 6 slave interface id" - default 2 - range 0 3 - -config SCB5_MI0_SLOT7 - int "Slot 7 slave interface id" - default 3 - range 0 3 - -endif # SCB5_MI0 - -menuconfig SCB6_MI0 - bool "SCB6 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - PPI1 MDA33 -- 0 - PPI1 MDA34 -- 1 - -if SCB6_MI0 - -config SCB6_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 1 - -config SCB6_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 1 - -config SCB6_MI0_SLOT2 - int "Slot 2 slave interface id" - default 0 - range 0 1 - -config SCB6_MI0_SLOT3 - int "Slot 3 slave interface id" - default 1 - range 0 1 - -endif # SCB6_MI0 - -menuconfig SCB7_MI0 - bool "SCB7 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - PIXC0 -- 0 - PIXC1 -- 1 - PIXC2 -- 2 - -if SCB7_MI0 - -config SCB7_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 2 - -config SCB7_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 2 - -config SCB7_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 2 - -config SCB7_MI0_SLOT3 - int "Slot 3 slave interface id" - default 0 - range 0 2 - -config SCB7_MI0_SLOT4 - int "Slot 4 slave interface id" - default 1 - range 0 2 - -config SCB7_MI0_SLOT5 - int "Slot 5 slave interface id" - default 2 - range 0 2 - -endif # SCB7_MI0 - -menuconfig SCB8_MI0 - bool "SCB8 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - PVP CPDOB -- 0 - PVP CPDOC -- 1 - PVP CPCO -- 2 - PVP CPCI -- 3 - -if SCB8_MI0 - -config SCB8_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 3 - -config SCB8_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 3 - -config SCB8_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 3 - -config SCB8_MI0_SLOT3 - int "Slot 3 slave interface id" - default 3 - range 0 3 - -config SCB8_MI0_SLOT4 - int "Slot 4 slave interface id" - default 0 - range 0 3 - -config SCB8_MI0_SLOT5 - int "Slot 5 slave interface id" - default 1 - range 0 3 - -config SCB8_MI0_SLOT6 - int "Slot 6 slave interface id" - default 2 - range 0 3 - -config SCB8_MI0_SLOT7 - int "Slot 7 slave interface id" - default 3 - range 0 3 - -endif # SCB8_MI0 - -menuconfig SCB9_MI0 - bool "SCB9 Master Interface 0" - default n - depends on SCB_PRIORITY - help - The slave interface id of each slot should be set according following table. - PVP MPDO -- 0 - PVP MPDI -- 1 - PVP MPCO -- 2 - PVP MPCI -- 3 - PVP CPDOA -- 4 - -if SCB9_MI0 - -config SCB9_MI0_SLOT0 - int "Slot 0 slave interface id" - default 0 - range 0 4 - -config SCB9_MI0_SLOT1 - int "Slot 1 slave interface id" - default 1 - range 0 4 - -config SCB9_MI0_SLOT2 - int "Slot 2 slave interface id" - default 2 - range 0 4 - -config SCB9_MI0_SLOT3 - int "Slot 3 slave interface id" - default 3 - range 0 4 - -config SCB9_MI0_SLOT4 - int "Slot 4 slave interface id" - default 4 - range 0 4 - -config SCB9_MI0_SLOT5 - int "Slot 5 slave interface id" - default 0 - range 0 4 - -config SCB9_MI0_SLOT6 - int "Slot 6 slave interface id" - default 1 - range 0 4 - -config SCB9_MI0_SLOT7 - int "Slot 7 slave interface id" - default 2 - range 0 4 - -config SCB9_MI0_SLOT8 - int "Slot 8 slave interface id" - default 3 - range 0 4 - -config SCB9_MI0_SLOT9 - int "Slot 9 slave interface id" - default 4 - range 0 4 - -endif # SCB9_MI0 - -endmenu - -endif diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile deleted file mode 100644 index 60ffaf85d303..000000000000 --- a/arch/blackfin/mach-bf609/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# arch/blackfin/mach-bf609/Makefile -# - -obj-y := dma.o clock.o ints-priority.o -obj-$(CONFIG_PM) += pm.o dpm.o -obj-$(CONFIG_SCB_PRIORITY) += scb.o diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig deleted file mode 100644 index 350154b2a3ee..000000000000 --- a/arch/blackfin/mach-bf609/boards/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN609_EZKIT - help - Select your board! - -config BFIN609_EZKIT - bool "BF609-EZKIT" - help - BFIN609-EZKIT board support. - -endchoice diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile deleted file mode 100644 index 11f98b0882ea..000000000000 --- a/arch/blackfin/mach-bf609/boards/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf609/boards/Makefile -# - -obj-$(CONFIG_BFIN609_EZKIT) += ezkit.o diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c deleted file mode 100644 index 51157a255824..000000000000 --- a/arch/blackfin/mach-bf609/boards/ezkit.c +++ /dev/null @@ -1,2191 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF609-EZKIT"; - -/* - * Driver needs to know address, irq and flag pin. - */ - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x2C0C0000, - .end = 0x2C0C0000 + 0xfffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PG7, - .end = IRQ_PG7, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) -#include - -static struct bfin_rotary_platform_data bfin_rotary_data = { - /*.rotary_up_key = KEY_UP,*/ - /*.rotary_down_key = KEY_DOWN,*/ - .rotary_rel_code = REL_WHEEL, - .rotary_button_key = KEY_ENTER, - .debounce = 10, /* 0..17 */ - .mode = ROT_QUAD_ENC | ROT_DEBE, -}; - -static struct resource bfin_rotary_resources[] = { - { - .start = CNT_CONFIG, - .end = CNT_CONFIG + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CNT, - .end = IRQ_CNT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_rotary_device = { - .name = "bfin-rotary", - .id = -1, - .num_resources = ARRAY_SIZE(bfin_rotary_resources), - .resource = bfin_rotary_resources, - .dev = { - .platform_data = &bfin_rotary_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_STMMAC_ETH) -#include -#include - -static struct stmmac_mdio_bus_data phy_private_data = { - .phy_mask = 1, -}; - -static struct stmmac_dma_cfg eth_dma_cfg = { - .pbl = 2, -}; - -int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv) -{ - bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0); - return 0; -} - -static struct plat_stmmacenet_data eth_private_data = { - .has_gmac = 1, - .bus_id = 0, - .enh_desc = 1, - .phy_addr = 1, - .mdio_bus_data = &phy_private_data, - .dma_cfg = ð_dma_cfg, - .force_thresh_dma_mode = 1, - .interface = PHY_INTERFACE_MODE_RMII, - .init = stmmac_ptp_clk_init, -}; - -static struct platform_device bfin_eth_device = { - .name = "stmmaceth", - .id = 0, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = EMAC0_MACCFG, - .end = EMAC0_MACCFG + 0x1274, - .flags = IORESOURCE_MEM, - }, - { - .name = "macirq", - .start = IRQ_EMAC0_STAT, - .end = IRQ_EMAC0_STAT, - .flags = IORESOURCE_IRQ, - }, - }, - .dev = { - .power.can_wakeup = 1, - .platform_data = ð_private_data, - } -}; -#endif - -#if IS_ENABLED(CONFIG_INPUT_ADXL34X) -#include -static const struct adxl34x_platform_data adxl34x_info = { - .x_axis_offset = 0, - .y_axis_offset = 0, - .z_axis_offset = 0, - .tap_threshold = 0x31, - .tap_duration = 0x10, - .tap_latency = 0x60, - .tap_window = 0xF0, - .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, - .act_axis_control = 0xFF, - .activity_threshold = 5, - .inactivity_threshold = 3, - .inactivity_time = 4, - .free_fall_threshold = 0x7, - .free_fall_time = 0x20, - .data_rate = 0x8, - .data_range = ADXL_FULL_RES, - - .ev_type = EV_ABS, - .ev_code_x = ABS_X, /* EV_REL */ - .ev_code_y = ABS_Y, /* EV_REL */ - .ev_code_z = ABS_Z, /* EV_REL */ - - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ - -/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ -/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ - .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, - .fifo_mode = ADXL_FIFO_STREAM, - .orientation_enable = ADXL_EN_ORIENTATION_3D, - .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, - .divisor_length = ADXL_LP_FILTER_DIVISOR_16, - /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ - .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, -}; -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = UART0_REVID, - .end = UART0_RXDIV+4, - .flags = IORESOURCE_MEM, - }, -#ifdef CONFIG_EARLY_PRINTK - { - .start = PORTD_FER, - .end = PORTD_FER+2, - .flags = IORESOURCE_REG, - }, - { - .start = PORTD_MUX, - .end = PORTD_MUX+3, - .flags = IORESOURCE_REG, - }, -#endif - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_STAT, - .end = IRQ_UART0_STAT, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART0_CTSRTS - { /* CTS pin -- 0 means not supported */ - .start = GPIO_PD10, - .end = GPIO_PD10, - .flags = IORESOURCE_IO, - }, - { /* RTS pin -- 0 means not supported */ - .start = GPIO_PD9, - .end = GPIO_PD9, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, -#ifdef CONFIG_BFIN_UART0_CTSRTS - P_UART0_RTS, P_UART0_CTS, -#endif - 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 -static struct resource bfin_uart1_resources[] = { - { - .start = UART1_REVID, - .end = UART1_RXDIV+4, - .flags = IORESOURCE_MEM, - }, -#ifdef CONFIG_EARLY_PRINTK - { - .start = PORTG_FER_SET, - .end = PORTG_FER_SET+2, - .flags = IORESOURCE_REG, - }, -#endif - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_RX, - .end = IRQ_UART1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART1_STAT, - .end = IRQ_UART1_STAT, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART1_RX, - .end = CH_UART1_RX, - .flags = IORESOURCE_DMA, - }, -#ifdef CONFIG_BFIN_UART1_CTSRTS - { /* CTS pin -- 0 means not supported */ - .start = GPIO_PG13, - .end = GPIO_PG13, - .flags = IORESOURCE_IO, - }, - { /* RTS pin -- 0 means not supported */ - .start = GPIO_PG10, - .end = GPIO_PG10, - .flags = IORESOURCE_IO, - }, -#endif -}; - -static unsigned short bfin_uart1_peripherals[] = { - P_UART1_TX, P_UART1_RX, -#ifdef CONFIG_BFIN_UART1_CTSRTS - P_UART1_RTS, P_UART1_CTS, -#endif - 0 -}; - -static struct platform_device bfin_uart1_device = { - .name = "bfin-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_uart1_resources), - .resource = bfin_uart1_resources, - .dev = { - .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#ifdef CONFIG_BFIN_SIR1 -static struct resource bfin_sir1_resources[] = { - { - .start = 0xFFC02000, - .end = 0xFFC020FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART1_TX, - .end = IRQ_UART1_TX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART1_TX, - .end = CH_UART1_TX+1, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sir1_device = { - .name = "bfin_sir", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sir1_resources), - .resource = bfin_sir1_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct resource musb_resources[] = { - [0] = { - .start = 0xFFCC1000, - .end = 0xFFCC1398, - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = IRQ_USB_STAT, - .end = IRQ_USB_STAT, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "mc" - }, - [2] = { /* DMA IRQ */ - .start = IRQ_USB_DMA, - .end = IRQ_USB_DMA, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - .name = "dma" - }, -}; - -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 0, - .dma = 1, - .num_eps = 16, - .dma_channels = 8, - .clkin = 48, /* musb CLKIN in MHZ */ -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_OTG, -#elif defined(CONFIG_USB_MUSB_HDRC) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, -}; - -static u64 musb_dmamask = ~(u32)0; - -static struct platform_device musb_device = { - .name = "musb-blackfin", - .id = 0, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &musb_plat, - }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART -static struct resource bfin_sport2_uart_resources[] = { - { - .start = SPORT2_TCR1, - .end = SPORT2_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT2_RX, - .end = IRQ_SPORT2_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT2_ERROR, - .end = IRQ_SPORT2_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport2_peripherals[] = { - P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, - P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 -}; - -static struct platform_device bfin_sport2_uart_device = { - .name = "bfin-sport-uart", - .id = 2, - .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), - .resource = bfin_sport2_uart_resources, - .dev = { - .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) - -static unsigned short bfin_can0_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can0_resources[] = { - { - .start = 0xFFC00A00, - .end = 0xFFC00FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN0_RX, - .end = IRQ_CAN0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_TX, - .end = IRQ_CAN0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_STAT, - .end = IRQ_CAN0_STAT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can0_device = { - .name = "bfin_can", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_can0_resources), - .resource = bfin_can0_resources, - .dev = { - .platform_data = &bfin_can0_peripherals, /* Passed to driver */ - }, -}; - -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) -static struct mtd_partition partition_info[] = { - { - .name = "bootloader(nand)", - .offset = 0, - .size = 0x80000, - }, { - .name = "linux kernel(nand)", - .offset = MTDPART_OFS_APPEND, - .size = 4 * 1024 * 1024, - }, - { - .name = "file system(nand)", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct bf5xx_nand_platform bfin_nand_platform = { - .data_width = NFC_NWIDTH_8, - .partitions = partition_info, - .nr_partitions = ARRAY_SIZE(partition_info), - .rd_dly = 3, - .wr_dly = 3, -}; - -static struct resource bfin_nand_resources[] = { - { - .start = 0xFFC03B00, - .end = 0xFFC03B4F, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_NFC, - .end = CH_NFC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_nand_device = { - .name = "bfin-nand", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_nand_resources), - .resource = bfin_nand_resources, - .dev = { - .platform_data = &bfin_nand_platform, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - -static struct bfin_sd_host bfin_sdh_data = { - .dma_chan = CH_RSI, - .irq_int0 = IRQ_RSI_INT0, - .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, -}; - -static struct platform_device bfin_sdh_device = { - .name = "bfin-sdh", - .id = 0, - .dev = { - .platform_data = &bfin_sdh_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezkit_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x80000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x400000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = 0x1000000 - 0x80000 - 0x400000, - .offset = MTDPART_OFS_APPEND, - }, -}; - -int bf609_nor_flash_init(struct platform_device *pdev) -{ -#define CONFIG_SMC_GCTL_VAL 0x00000010 - - bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL); - bfin_write32(SMC_B0CTL, 0x01002011); - bfin_write32(SMC_B0TIM, 0x08170977); - bfin_write32(SMC_B0ETIM, 0x00092231); - return 0; -} - -void bf609_nor_flash_exit(struct platform_device *pdev) -{ - bfin_write32(SMC_GCTL, 0); -} - -static struct physmap_flash_data ezkit_flash_data = { - .width = 2, - .parts = ezkit_partitions, - .init = bf609_nor_flash_init, - .exit = bf609_nor_flash_exit, - .nr_parts = ARRAY_SIZE(ezkit_partitions), -#ifdef CONFIG_ROMKERNEL - .probe_type = "map_rom", -#endif -}; - -static struct resource ezkit_flash_resource = { - .start = 0xb0000000, - .end = 0xb0ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezkit_flash_data, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -/* SPI flash chip (w25q32) */ -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00080000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x00180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "w25q32", -}; - -static struct adi_spi3_chip spi_flash_chip_info = { - .enable_dma = true, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_SPIDEV) -static struct adi_spi3_chip spidev_chip_info = { - .enable_dma = true, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF6XX_PCM) -static struct platform_device bfin_pcm = { - .name = "bfin-i2s-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S) -#include -static struct resource bfin_snd_resources[] = { - { - .start = SPORT0_CTL_A, - .end = SPORT0_CTL_A, - .flags = IORESOURCE_MEM, - }, - { - .start = SPORT0_CTL_B, - .end = SPORT0_CTL_B, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_SPORT0_TX, - .end = CH_SPORT0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_SPORT0_RX, - .end = CH_SPORT0_RX, - .flags = IORESOURCE_DMA, - }, - { - .start = IRQ_SPORT0_TX_STAT, - .end = IRQ_SPORT0_TX_STAT, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_RX_STAT, - .end = IRQ_SPORT0_RX_STAT, - .flags = IORESOURCE_IRQ, - }, -}; - -static const unsigned short bfin_snd_pin[] = { - P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK, - P_SPORT0_BFS, P_SPORT0_BD0, 0, -}; - -static struct bfin_snd_platform_data bfin_snd_data = { - .pin_req = bfin_snd_pin, -}; - -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .num_resources = ARRAY_SIZE(bfin_snd_resources), - .resource = bfin_snd_resources, - .dev = { - .platform_data = &bfin_snd_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) -static const char * const ad1836_link[] = { - "bfin-i2s.0", - "spi0.76", -}; -static struct platform_device bfin_ad1836_machine = { - .name = "bfin-snd-ad1836", - .id = -1, - .dev = { - .platform_data = (void *)ad1836_link, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) -static struct platform_device adau1761_device = { - .name = "bfin-eval-adau1x61", -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761) -#include -static struct adau1761_platform_data adau1761_info = { - .lineout_mode = ADAU1761_OUTPUT_MODE_LINE, - .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS, -}; -#endif - -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) -#include -#include -#include - -static const unsigned short ppi_req[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, -#if !IS_ENABLED(CONFIG_VIDEO_VS6624) - P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, - P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, -#endif - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const struct ppi_info ppi_info = { - .type = PPI_TYPE_EPPI3, - .dma_ch = CH_EPPI0_CH0, - .irq_err = IRQ_EPPI0_STAT, - .base = (void __iomem *)EPPI0_STAT, - .pin_req = ppi_req, -}; - -#if IS_ENABLED(CONFIG_VIDEO_VS6624) -static struct v4l2_input vs6624_inputs[] = { - { - .index = 0, - .name = "Camera", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_UNKNOWN, - }, -}; - -static struct bcap_route vs6624_routes[] = { - { - .input = 0, - .output = 0, - }, -}; - -static const unsigned vs6624_ce_pin = GPIO_PE4; - -static struct bfin_capture_config bfin_capture_data = { - .card_name = "BF609", - .inputs = vs6624_inputs, - .num_inputs = ARRAY_SIZE(vs6624_inputs), - .routes = vs6624_routes, - .i2c_adapter_id = 0, - .board_info = { - .type = "vs6624", - .addr = 0x10, - .platform_data = (void *)&vs6624_ce_pin, - }, - .ppi_info = &ppi_info, - .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI - | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656), - .blank_pixels = 4, -}; -#endif - -#if IS_ENABLED(CONFIG_VIDEO_ADV7842) -#include - -static struct v4l2_input adv7842_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_ALL, - .capabilities = V4L2_IN_CAP_STD, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = V4L2_STD_ALL, - .capabilities = V4L2_IN_CAP_STD, - }, - { - .index = 2, - .name = "Component", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_DV_TIMINGS, - }, - { - .index = 3, - .name = "VGA", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_DV_TIMINGS, - }, - { - .index = 4, - .name = "HDMI", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_DV_TIMINGS, - }, -}; - -static struct bcap_route adv7842_routes[] = { - { - .input = 3, - .output = 0, - .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL - | EPPI_CTL_ACTIVE656), - }, - { - .input = 4, - .output = 0, - }, - { - .input = 2, - .output = 0, - }, - { - .input = 1, - .output = 0, - }, - { - .input = 0, - .output = 1, - .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16 - | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2 - | EPPI_CTL_SYNC2 | EPPI_CTL_NON656), - }, -}; - -static struct adv7842_output_format adv7842_opf[] = { - { - .op_ch_sel = ADV7842_OP_CH_SEL_BRG, - .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8, - .blank_data = 1, - .insert_av_codes = 1, - }, - { - .op_ch_sel = ADV7842_OP_CH_SEL_RGB, - .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16, - .blank_data = 1, - }, -}; - -static struct adv7842_platform_data adv7842_data = { - .opf = adv7842_opf, - .num_opf = ARRAY_SIZE(adv7842_opf), - .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1, - .prim_mode = ADV7842_PRIM_MODE_SDP, - .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1, - .hdmi_free_run_enable = 1, - .sdp_free_run_auto = 1, - .llc_dll_phase = 0x10, - .i2c_sdp_io = 0x40, - .i2c_sdp = 0x41, - .i2c_cp = 0x42, - .i2c_vdp = 0x43, - .i2c_afe = 0x44, - .i2c_hdmi = 0x45, - .i2c_repeater = 0x46, - .i2c_edid = 0x47, - .i2c_infoframe = 0x48, - .i2c_cec = 0x49, - .i2c_avlink = 0x4a, -}; - -static struct bfin_capture_config bfin_capture_data = { - .card_name = "BF609", - .inputs = adv7842_inputs, - .num_inputs = ARRAY_SIZE(adv7842_inputs), - .routes = adv7842_routes, - .i2c_adapter_id = 0, - .board_info = { - .type = "adv7842", - .addr = 0x20, - .platform_data = (void *)&adv7842_data, - }, - .ppi_info = &ppi_info, - .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL - | EPPI_CTL_ACTIVE656), -}; -#endif - -static struct platform_device bfin_capture_device = { - .name = "bfin_capture", - .dev = { - .platform_data = &bfin_capture_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY) -#include -#include -#include - -static const unsigned short ppi_req_disp[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const struct ppi_info ppi_info = { - .type = PPI_TYPE_EPPI3, - .dma_ch = CH_EPPI0_CH0, - .irq_err = IRQ_EPPI0_STAT, - .base = (void __iomem *)EPPI0_STAT, - .pin_req = ppi_req_disp, -}; - -#if IS_ENABLED(CONFIG_VIDEO_ADV7511) -#include - -static struct v4l2_output adv7511_outputs[] = { - { - .index = 0, - .name = "HDMI", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_OUT_CAP_DV_TIMINGS, - }, -}; - -static struct disp_route adv7511_routes[] = { - { - .output = 0, - }, -}; - -static struct adv7511_platform_data adv7511_data = { - .edid_addr = 0x7e, -}; - -static struct bfin_display_config bfin_display_data = { - .card_name = "BF609", - .outputs = adv7511_outputs, - .num_outputs = ARRAY_SIZE(adv7511_outputs), - .routes = adv7511_routes, - .i2c_adapter_id = 0, - .board_info = { - .type = "adv7511", - .addr = 0x39, - .platform_data = (void *)&adv7511_data, - }, - .ppi_info = &ppi_info, - .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16 - | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3 - | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2 - | EPPI_CTL_NON656 | EPPI_CTL_DIR), -}; -#endif - -#if IS_ENABLED(CONFIG_VIDEO_ADV7343) -#include - -static struct v4l2_output adv7343_outputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = V4L2_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = V4L2_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - { - .index = 2, - .name = "Component", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = V4L2_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - -}; - -static struct disp_route adv7343_routes[] = { - { - .output = ADV7343_COMPOSITE_ID, - }, - { - .output = ADV7343_SVIDEO_ID, - }, - { - .output = ADV7343_COMPONENT_ID, - }, -}; - -static struct adv7343_platform_data adv7343_data = { - .mode_config = { - .sleep_mode = false, - .pll_control = false, - .dac_1 = true, - .dac_2 = true, - .dac_3 = true, - .dac_4 = true, - .dac_5 = true, - .dac_6 = true, - }, - .sd_config = { - .sd_dac_out1 = false, - .sd_dac_out2 = false, - }, -}; - -static struct bfin_display_config bfin_display_data = { - .card_name = "BF609", - .outputs = adv7343_outputs, - .num_outputs = ARRAY_SIZE(adv7343_outputs), - .routes = adv7343_routes, - .i2c_adapter_id = 0, - .board_info = { - .type = "adv7343", - .addr = 0x2b, - .platform_data = (void *)&adv7343_data, - }, - .ppi_info = &ppi_info_disp, - .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO - | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2 - | EPPI_CTL_NON656 | EPPI_CTL_DIR), -}; -#endif - -static struct platform_device bfin_display_device = { - .name = "bfin_display", - .dev = { - .platform_data = &bfin_display_data, - }, -}; -#endif - -#if defined(CONFIG_FB_BF609_NL8048) \ - || defined(CONFIG_FB_BF609_NL8048_MODULE) -static struct resource nl8048_resources[] = { - { - .start = EPPI2_STAT, - .end = EPPI2_STAT, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_EPPI2_CH0, - .end = CH_EPPI2_CH0, - .flags = IORESOURCE_DMA, - }, - { - .start = IRQ_EPPI2_STAT, - .end = IRQ_EPPI2_STAT, - .flags = IORESOURCE_IRQ, - }, -}; -static struct platform_device bfin_fb_device = { - .name = "bf609_nl8048", - .num_resources = ARRAY_SIZE(nl8048_resources), - .resource = nl8048_resources, - .dev = { - .platform_data = (void *)GPIO_PC15, - }, -}; -#endif - -#if defined(CONFIG_BFIN_CRC) -#define BFIN_CRC_NAME "bfin-crc" - -static struct resource bfin_crc0_resources[] = { - { - .start = REG_CRC0_CTL, - .end = REG_CRC0_REVID+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CRC0_DCNTEXP, - .end = IRQ_CRC0_DCNTEXP, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_MEM_STREAM0_SRC_CRC0, - .end = CH_MEM_STREAM0_SRC_CRC0, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_MEM_STREAM0_DEST_CRC0, - .end = CH_MEM_STREAM0_DEST_CRC0, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_crc0_device = { - .name = BFIN_CRC_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(bfin_crc0_resources), - .resource = bfin_crc0_resources, -}; - -static struct resource bfin_crc1_resources[] = { - { - .start = REG_CRC1_CTL, - .end = REG_CRC1_REVID+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CRC1_DCNTEXP, - .end = IRQ_CRC1_DCNTEXP, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_MEM_STREAM1_SRC_CRC1, - .end = CH_MEM_STREAM1_SRC_CRC1, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_MEM_STREAM1_DEST_CRC1, - .end = CH_MEM_STREAM1_DEST_CRC1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_crc1_device = { - .name = BFIN_CRC_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(bfin_crc1_resources), - .resource = bfin_crc1_resources, -}; -#endif - -#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC) -#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc" -#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c - -static struct resource bfin_crypto_crc_resources[] = { - { - .start = REG_CRC0_CTL, - .end = REG_CRC0_REVID+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CRC0_DCNTEXP, - .end = IRQ_CRC0_DCNTEXP, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_MEM_STREAM0_SRC_CRC0, - .end = CH_MEM_STREAM0_SRC_CRC0, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_crypto_crc_device = { - .name = BFIN_CRYPTO_CRC_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources), - .resource = bfin_crypto_crc_resources, - .dev = { - .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) -static const struct ad7877_platform_data bfin_ad7877_ts_info = { - .model = 7877, - .vref_delay_usecs = 50, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1000, - .pressure_min = 0, - .stopacq_polarity = 1, - .first_conversion_delay = 3, - .acquisition_time = 1, - .averaging = 1, - .pen_down_acc_interval = 1, -}; -#endif - -#ifdef CONFIG_PINCTRL_ADI2 - -# define ADI_PINT_DEVNAME "adi-gpio-pint" -# define ADI_GPIO_DEVNAME "adi-gpio" -# define ADI_PINCTRL_DEVNAME "pinctrl-adi2" - -static struct platform_device bfin_pinctrl_device = { - .name = ADI_PINCTRL_DEVNAME, - .id = 0, -}; - -static struct resource bfin_pint0_resources[] = { - { - .start = PINT0_MASK_SET, - .end = PINT0_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT0, - .end = IRQ_PINT0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint0_device = { - .name = ADI_PINT_DEVNAME, - .id = 0, - .num_resources = ARRAY_SIZE(bfin_pint0_resources), - .resource = bfin_pint0_resources, -}; - -static struct resource bfin_pint1_resources[] = { - { - .start = PINT1_MASK_SET, - .end = PINT1_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT1, - .end = IRQ_PINT1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint1_device = { - .name = ADI_PINT_DEVNAME, - .id = 1, - .num_resources = ARRAY_SIZE(bfin_pint1_resources), - .resource = bfin_pint1_resources, -}; - -static struct resource bfin_pint2_resources[] = { - { - .start = PINT2_MASK_SET, - .end = PINT2_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT2, - .end = IRQ_PINT2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint2_device = { - .name = ADI_PINT_DEVNAME, - .id = 2, - .num_resources = ARRAY_SIZE(bfin_pint2_resources), - .resource = bfin_pint2_resources, -}; - -static struct resource bfin_pint3_resources[] = { - { - .start = PINT3_MASK_SET, - .end = PINT3_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT3, - .end = IRQ_PINT3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint3_device = { - .name = ADI_PINT_DEVNAME, - .id = 3, - .num_resources = ARRAY_SIZE(bfin_pint3_resources), - .resource = bfin_pint3_resources, -}; - -static struct resource bfin_pint4_resources[] = { - { - .start = PINT4_MASK_SET, - .end = PINT4_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT4, - .end = IRQ_PINT4, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint4_device = { - .name = ADI_PINT_DEVNAME, - .id = 4, - .num_resources = ARRAY_SIZE(bfin_pint4_resources), - .resource = bfin_pint4_resources, -}; - -static struct resource bfin_pint5_resources[] = { - { - .start = PINT5_MASK_SET, - .end = PINT5_LATCH + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PINT5, - .end = IRQ_PINT5, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_pint5_device = { - .name = ADI_PINT_DEVNAME, - .id = 5, - .num_resources = ARRAY_SIZE(bfin_pint5_resources), - .resource = bfin_pint5_resources, -}; - -static struct resource bfin_gpa_resources[] = { - { - .start = PORTA_FER, - .end = PORTA_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { /* optional */ - .start = IRQ_PA0, - .end = IRQ_PA0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = { - .port_pin_base = GPIO_PA0, - .port_width = GPIO_BANKSIZE, - .pint_id = 0, /* PINT0 */ - .pint_assign = true, /* PINT upper 16 bit */ - .pint_map = 0, /* mapping mask in PINT */ -}; - -static struct platform_device bfin_gpa_device = { - .name = ADI_GPIO_DEVNAME, - .id = 0, - .num_resources = ARRAY_SIZE(bfin_gpa_resources), - .resource = bfin_gpa_resources, - .dev = { - .platform_data = &bfin_gpa_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpb_resources[] = { - { - .start = PORTB_FER, - .end = PORTB_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PB0, - .end = IRQ_PB0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = { - .port_pin_base = GPIO_PB0, - .port_width = GPIO_BANKSIZE, - .pint_id = 0, - .pint_assign = false, - .pint_map = 1, -}; - -static struct platform_device bfin_gpb_device = { - .name = ADI_GPIO_DEVNAME, - .id = 1, - .num_resources = ARRAY_SIZE(bfin_gpb_resources), - .resource = bfin_gpb_resources, - .dev = { - .platform_data = &bfin_gpb_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpc_resources[] = { - { - .start = PORTC_FER, - .end = PORTC_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PC0, - .end = IRQ_PC0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = { - .port_pin_base = GPIO_PC0, - .port_width = GPIO_BANKSIZE, - .pint_id = 1, - .pint_assign = false, - .pint_map = 1, -}; - -static struct platform_device bfin_gpc_device = { - .name = ADI_GPIO_DEVNAME, - .id = 2, - .num_resources = ARRAY_SIZE(bfin_gpc_resources), - .resource = bfin_gpc_resources, - .dev = { - .platform_data = &bfin_gpc_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpd_resources[] = { - { - .start = PORTD_FER, - .end = PORTD_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PD0, - .end = IRQ_PD0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = { - .port_pin_base = GPIO_PD0, - .port_width = GPIO_BANKSIZE, - .pint_id = 2, - .pint_assign = false, - .pint_map = 1, -}; - -static struct platform_device bfin_gpd_device = { - .name = ADI_GPIO_DEVNAME, - .id = 3, - .num_resources = ARRAY_SIZE(bfin_gpd_resources), - .resource = bfin_gpd_resources, - .dev = { - .platform_data = &bfin_gpd_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpe_resources[] = { - { - .start = PORTE_FER, - .end = PORTE_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PE0, - .end = IRQ_PE0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = { - .port_pin_base = GPIO_PE0, - .port_width = GPIO_BANKSIZE, - .pint_id = 3, - .pint_assign = false, - .pint_map = 1, -}; - -static struct platform_device bfin_gpe_device = { - .name = ADI_GPIO_DEVNAME, - .id = 4, - .num_resources = ARRAY_SIZE(bfin_gpe_resources), - .resource = bfin_gpe_resources, - .dev = { - .platform_data = &bfin_gpe_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpf_resources[] = { - { - .start = PORTF_FER, - .end = PORTF_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PF0, - .end = IRQ_PF0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = { - .port_pin_base = GPIO_PF0, - .port_width = GPIO_BANKSIZE, - .pint_id = 4, - .pint_assign = false, - .pint_map = 1, -}; - -static struct platform_device bfin_gpf_device = { - .name = ADI_GPIO_DEVNAME, - .id = 5, - .num_resources = ARRAY_SIZE(bfin_gpf_resources), - .resource = bfin_gpf_resources, - .dev = { - .platform_data = &bfin_gpf_pdata, /* Passed to driver */ - }, -}; - -static struct resource bfin_gpg_resources[] = { - { - .start = PORTG_FER, - .end = PORTG_MUX + 3, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PG0, - .end = IRQ_PG0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = { - .port_pin_base = GPIO_PG0, - .port_width = GPIO_BANKSIZE, - .pint_id = 5, - .pint_assign = false, - .pint_map = 1, -}; - -static struct platform_device bfin_gpg_device = { - .name = ADI_GPIO_DEVNAME, - .id = 6, - .num_resources = ARRAY_SIZE(bfin_gpg_resources), - .resource = bfin_gpg_resources, - .dev = { - .platform_data = &bfin_gpg_pdata, /* Passed to driver */ - }, -}; - -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include -#include - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) - { - .modalias = "ad7877", - .platform_data = &bfin_ad7877_ts_info, - .irq = IRQ_PD9, - .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */ - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/ - .controller_data = &spidev_chip_info, - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI) - { - .modalias = "adxl34x", - .platform_data = &adxl34x_info, - .irq = IRQ_PC5, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 2, - .mode = SPI_MODE_3, - }, -#endif -}; -#if IS_ENABLED(CONFIG_SPI_ADI_V3) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_SPI0_TX, - .end = CH_SPI0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_SPI0_RX, - .end = CH_SPI0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -/* SPI (1) */ -static struct resource bfin_spi1_resource[] = { - { - .start = SPI1_REGBASE, - .end = SPI1_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = CH_SPI1_TX, - .end = CH_SPI1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_SPI1_RX, - .end = CH_SPI1_RX, - .flags = IORESOURCE_DMA, - }, - -}; - -/* SPI controller data */ -static struct adi_spi3_master bf60x_spi_master_info0 = { - .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bf60x_spi_master0 = { - .name = "adi-spi3", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bf60x_spi_master_info0, /* Passed to driver */ - }, -}; - -static struct adi_spi3_master bf60x_spi_master_info1 = { - .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, - .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, -}; - -static struct platform_device bf60x_spi_master1 = { - .name = "adi-spi3", - .id = 1, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi1_resource), - .resource = bfin_spi1_resource, - .dev = { - .platform_data = &bf60x_spi_master_info1, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) -static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; - -static struct resource bfin_twi0_resource[] = { - [0] = { - .start = TWI0_CLKDIV, - .end = TWI0_CLKDIV + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI0, - .end = IRQ_TWI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi0_device = { - .name = "i2c-bfin-twi", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_twi0_resource), - .resource = bfin_twi0_resource, - .dev = { - .platform_data = &bfin_twi0_pins, - }, -}; - -static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; - -static struct resource bfin_twi1_resource[] = { - [0] = { - .start = TWI1_CLKDIV, - .end = TWI1_CLKDIV + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TWI1, - .end = IRQ_TWI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c_bfin_twi1_device = { - .name = "i2c-bfin-twi", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_twi1_resource), - .resource = bfin_twi1_resource, - .dev = { - .platform_data = &bfin_twi1_pins, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) -#include -static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = { - .base = 120, -}; -static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = { - .base = 130, -}; -static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = { - .base = 140, -}; -# if IS_ENABLED(CONFIG_VIDEO_ADV7842) -static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = { - .base = 150, -}; -# endif -# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343) -static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = { - .base = 160, -}; -# endif -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { -#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C) - { - I2C_BOARD_INFO("adxl34x", 0x53), - .irq = IRQ_PC5, - .platform_data = (void *)&adxl34x_info, - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761) - { - I2C_BOARD_INFO("adau1761", 0x38), - .platform_data = (void *)&adau1761_info - }, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) - { - I2C_BOARD_INFO("ssm2602", 0x1b), - }, -#endif -#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) - { - I2C_BOARD_INFO("mcp23017", 0x21), - .platform_data = (void *)&bfin_mcp23s08_soft_switch0 - }, - { - I2C_BOARD_INFO("mcp23017", 0x22), - .platform_data = (void *)&bfin_mcp23s08_soft_switch1 - }, - { - I2C_BOARD_INFO("mcp23017", 0x23), - .platform_data = (void *)&bfin_mcp23s08_soft_switch2 - }, -# if IS_ENABLED(CONFIG_VIDEO_ADV7842) - { - I2C_BOARD_INFO("mcp23017", 0x26), - .platform_data = (void *)&bfin_adv7842_soft_switch - }, -# endif -# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343) - { - I2C_BOARD_INFO("mcp23017", 0x25), - .platform_data = (void *)&bfin_adv7511_soft_switch - }, -# endif -#endif -}; - -static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { -}; - -static const unsigned int cclk_vlev_datasheet[] = -{ -/* - * Internal VLEV BF54XSBBC1533 - ****temporarily using these values until data sheet is updated - */ - VRPAIR(VLEV_085, 150000000), - VRPAIR(VLEV_090, 250000000), - VRPAIR(VLEV_110, 276000000), - VRPAIR(VLEV_115, 301000000), - VRPAIR(VLEV_120, 525000000), - VRPAIR(VLEV_125, 550000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *ezkit_devices[] __initdata = { - - &bfin_dpmc, -#if defined(CONFIG_PINCTRL_ADI2) - &bfin_pinctrl_device, - &bfin_pint0_device, - &bfin_pint1_device, - &bfin_pint2_device, - &bfin_pint3_device, - &bfin_pint4_device, - &bfin_pint5_device, - &bfin_gpa_device, - &bfin_gpb_device, - &bfin_gpc_device, - &bfin_gpd_device, - &bfin_gpe_device, - &bfin_gpf_device, - &bfin_gpg_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#ifdef CONFIG_BFIN_SIR1 - &bfin_sir1_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_STMMAC_ETH) - &bfin_eth_device, -#endif - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) - &musb_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) - &bfin_isp1760_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART - &bfin_sport2_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_CAN_BFIN) - &bfin_can0_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) - &bfin_nand_device, -#endif - -#if IS_ENABLED(CONFIG_SDH_BFIN) - &bfin_sdh_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_ADI_V3) - &bf60x_spi_master0, - &bf60x_spi_master1, -#endif - -#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) - &bfin_rotary_device, -#endif - -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - &i2c_bfin_twi0_device, -#if !defined(CONFIG_BF542) - &i2c_bfin_twi1_device, -#endif -#endif - -#if defined(CONFIG_BFIN_CRC) - &bfin_crc0_device, - &bfin_crc1_device, -#endif -#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC) - &bfin_crypto_crc_device, -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezkit_flash_device, -#endif -#if IS_ENABLED(CONFIG_SND_BF6XX_PCM) - &bfin_pcm, -#endif -#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S) - &bfin_i2s, -#endif -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - &bfin_ad1836_machine, -#endif -#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) - &adau1761_device, -#endif -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) - &bfin_capture_device, -#endif -#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY) - &bfin_display_device, -#endif - -}; - -/* Pin control settings */ -static struct pinctrl_map __initdata bfin_pinmux_map[] = { - /* per-device maps */ - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"), - PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"), - PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"), - PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"), - PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"), - PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"), - PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"), - PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"), - PIN_MAP_MUX_GROUP("bfin_display.0", "8bit", "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"), - PIN_MAP_MUX_GROUP("bfin_display.0", "16bit", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"), - PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit", "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"), - PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"), - PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"), -}; - -static int __init ezkit_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - - /* Initialize pinmuxing */ - pinctrl_register_mappings(bfin_pinmux_map, - ARRAY_SIZE(bfin_pinmux_map)); - - i2c_register_board_info(0, bfin_i2c_board_info0, - ARRAY_SIZE(bfin_i2c_board_info0)); - i2c_register_board_info(1, bfin_i2c_board_info1, - ARRAY_SIZE(bfin_i2c_board_info1)); - - platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - - return 0; -} - -arch_initcall(ezkit_init); - -static struct platform_device *ezkit_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_UART1 - &bfin_uart1_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezkit_early_devices, - ARRAY_SIZE(ezkit_early_devices)); -} diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c deleted file mode 100644 index 16e0b09e2197..000000000000 --- a/arch/blackfin/mach-bf609/clock.c +++ /dev/null @@ -1,409 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define CGU0_CTL_DF (1 << 0) - -#define CGU0_CTL_MSEL_SHIFT 8 -#define CGU0_CTL_MSEL_MASK (0x7f << 8) - -#define CGU0_STAT_PLLEN (1 << 0) -#define CGU0_STAT_PLLBP (1 << 1) -#define CGU0_STAT_PLLLK (1 << 2) -#define CGU0_STAT_CLKSALGN (1 << 3) -#define CGU0_STAT_CCBF0 (1 << 4) -#define CGU0_STAT_CCBF1 (1 << 5) -#define CGU0_STAT_SCBF0 (1 << 6) -#define CGU0_STAT_SCBF1 (1 << 7) -#define CGU0_STAT_DCBF (1 << 8) -#define CGU0_STAT_OCBF (1 << 9) -#define CGU0_STAT_ADDRERR (1 << 16) -#define CGU0_STAT_LWERR (1 << 17) -#define CGU0_STAT_DIVERR (1 << 18) -#define CGU0_STAT_WDFMSERR (1 << 19) -#define CGU0_STAT_WDIVERR (1 << 20) -#define CGU0_STAT_PLOCKERR (1 << 21) - -#define CGU0_DIV_CSEL_SHIFT 0 -#define CGU0_DIV_CSEL_MASK 0x0000001F -#define CGU0_DIV_S0SEL_SHIFT 5 -#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT) -#define CGU0_DIV_SYSSEL_SHIFT 8 -#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT) -#define CGU0_DIV_S1SEL_SHIFT 13 -#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT) -#define CGU0_DIV_DSEL_SHIFT 16 -#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT) -#define CGU0_DIV_OSEL_SHIFT 22 -#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT) - -#define CLK(_clk, _devname, _conname) \ - { \ - .clk = &_clk, \ - .dev_id = _devname, \ - .con_id = _conname, \ - } - -#define NEEDS_INITIALIZATION 0x11 - -static LIST_HEAD(clk_list); - -static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask) -{ - u32 val2; - - val2 = bfin_read32(reg); - val2 &= ~mask; - val2 |= val; - bfin_write32(reg, val2); -} - -int wait_for_pll_align(void) -{ - int i = 10000; - while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN)); - - if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) { - printk(KERN_CRIT "fail to align clk\n"); - return -1; - } - - return 0; -} - -int clk_enable(struct clk *clk) -{ - int ret = -EIO; - if (clk->ops && clk->ops->enable) - ret = clk->ops->enable(clk); - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - if (!clk) - return; - - if (clk->ops && clk->ops->disable) - clk->ops->disable(clk); -} -EXPORT_SYMBOL(clk_disable); - - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long ret = 0; - if (clk->ops && clk->ops->get_rate) - ret = clk->ops->get_rate(clk); - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - long ret = 0; - if (clk->ops && clk->ops->round_rate) - ret = clk->ops->round_rate(clk, rate); - return ret; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EIO; - if (clk->ops && clk->ops->set_rate) - ret = clk->ops->set_rate(clk, rate); - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -unsigned long vco_get_rate(struct clk *clk) -{ - return clk->rate; -} - -unsigned long pll_get_rate(struct clk *clk) -{ - u32 df; - u32 msel; - u32 ctl = bfin_read32(CGU0_CTL); - u32 stat = bfin_read32(CGU0_STAT); - if (stat & CGU0_STAT_PLLBP) - return 0; - msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; - df = (ctl & CGU0_CTL_DF); - clk->parent->rate = clk_get_rate(clk->parent); - return clk->parent->rate / (df + 1) * msel * 2; -} - -unsigned long pll_round_rate(struct clk *clk, unsigned long rate) -{ - u32 div; - div = rate / clk->parent->rate; - return clk->parent->rate * div; -} - -int pll_set_rate(struct clk *clk, unsigned long rate) -{ - u32 msel; - u32 stat = bfin_read32(CGU0_STAT); - if (!(stat & CGU0_STAT_PLLEN)) - return -EBUSY; - if (!(stat & CGU0_STAT_PLLLK)) - return -EBUSY; - if (wait_for_pll_align()) - return -EBUSY; - msel = rate / clk->parent->rate / 2; - clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT, - CGU0_CTL_MSEL_MASK); - clk->rate = rate; - return 0; -} - -unsigned long cclk_get_rate(struct clk *clk) -{ - if (clk->parent) - return clk->parent->rate; - else - return 0; -} - -unsigned long sys_clk_get_rate(struct clk *clk) -{ - unsigned long drate; - u32 msel; - u32 df; - u32 ctl = bfin_read32(CGU0_CTL); - u32 div = bfin_read32(CGU0_DIV); - div = (div & clk->mask) >> clk->shift; - msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; - df = (ctl & CGU0_CTL_DF); - - if (!strcmp(clk->parent->name, "SYS_CLKIN")) { - drate = clk->parent->rate / (df + 1); - drate *= msel; - drate /= div; - return drate; - } else { - clk->parent->rate = clk_get_rate(clk->parent); - return clk->parent->rate / div; - } -} - -unsigned long dummy_get_rate(struct clk *clk) -{ - clk->parent->rate = clk_get_rate(clk->parent); - return clk->parent->rate; -} - -unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long max_rate; - unsigned long drate; - int i; - u32 msel; - u32 df; - u32 ctl = bfin_read32(CGU0_CTL); - - msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; - df = (ctl & CGU0_CTL_DF); - max_rate = clk->parent->rate / (df + 1) * msel; - - if (rate > max_rate) - return 0; - - for (i = 1; i < clk->mask; i++) { - drate = max_rate / i; - if (rate >= drate) - return drate; - } - return 0; -} - -int sys_clk_set_rate(struct clk *clk, unsigned long rate) -{ - u32 div = bfin_read32(CGU0_DIV); - div = (div & clk->mask) >> clk->shift; - - rate = clk_round_rate(clk, rate); - - if (!rate) - return -EINVAL; - - div = (clk_get_rate(clk) * div) / rate; - - if (wait_for_pll_align()) - return -EBUSY; - clk_reg_write_mask(CGU0_DIV, div << clk->shift, - clk->mask); - clk->rate = rate; - return 0; -} - -static struct clk_ops vco_ops = { - .get_rate = vco_get_rate, -}; - -static struct clk_ops pll_ops = { - .get_rate = pll_get_rate, - .set_rate = pll_set_rate, -}; - -static struct clk_ops cclk_ops = { - .get_rate = cclk_get_rate, -}; - -static struct clk_ops sys_clk_ops = { - .get_rate = sys_clk_get_rate, - .set_rate = sys_clk_set_rate, - .round_rate = sys_clk_round_rate, -}; - -static struct clk_ops dummy_clk_ops = { - .get_rate = dummy_get_rate, -}; - -static struct clk sys_clkin = { - .name = "SYS_CLKIN", - .rate = CONFIG_CLKIN_HZ, - .ops = &vco_ops, -}; - -static struct clk pll_clk = { - .name = "PLLCLK", - .rate = 500000000, - .parent = &sys_clkin, - .ops = &pll_ops, - .flags = NEEDS_INITIALIZATION, -}; - -static struct clk cclk = { - .name = "CCLK", - .rate = 500000000, - .mask = CGU0_DIV_CSEL_MASK, - .shift = CGU0_DIV_CSEL_SHIFT, - .parent = &sys_clkin, - .ops = &sys_clk_ops, - .flags = NEEDS_INITIALIZATION, -}; - -static struct clk cclk0 = { - .name = "CCLK0", - .parent = &cclk, - .ops = &cclk_ops, -}; - -static struct clk cclk1 = { - .name = "CCLK1", - .parent = &cclk, - .ops = &cclk_ops, -}; - -static struct clk sysclk = { - .name = "SYSCLK", - .rate = 500000000, - .mask = CGU0_DIV_SYSSEL_MASK, - .shift = CGU0_DIV_SYSSEL_SHIFT, - .parent = &sys_clkin, - .ops = &sys_clk_ops, - .flags = NEEDS_INITIALIZATION, -}; - -static struct clk sclk0 = { - .name = "SCLK0", - .rate = 500000000, - .mask = CGU0_DIV_S0SEL_MASK, - .shift = CGU0_DIV_S0SEL_SHIFT, - .parent = &sysclk, - .ops = &sys_clk_ops, -}; - -static struct clk sclk1 = { - .name = "SCLK1", - .rate = 500000000, - .mask = CGU0_DIV_S1SEL_MASK, - .shift = CGU0_DIV_S1SEL_SHIFT, - .parent = &sysclk, - .ops = &sys_clk_ops, -}; - -static struct clk dclk = { - .name = "DCLK", - .rate = 500000000, - .mask = CGU0_DIV_DSEL_MASK, - .shift = CGU0_DIV_DSEL_SHIFT, - .parent = &sys_clkin, - .ops = &sys_clk_ops, -}; - -static struct clk oclk = { - .name = "OCLK", - .rate = 500000000, - .mask = CGU0_DIV_OSEL_MASK, - .shift = CGU0_DIV_OSEL_SHIFT, - .parent = &pll_clk, -}; - -static struct clk ethclk = { - .name = "stmmaceth", - .parent = &sclk0, - .ops = &dummy_clk_ops, -}; - -static struct clk ethpclk = { - .name = "pclk", - .parent = &sclk0, - .ops = &dummy_clk_ops, -}; - -static struct clk spiclk = { - .name = "spi", - .parent = &sclk1, - .ops = &dummy_clk_ops, -}; - -static struct clk_lookup bf609_clks[] = { - CLK(sys_clkin, NULL, "SYS_CLKIN"), - CLK(pll_clk, NULL, "PLLCLK"), - CLK(cclk, NULL, "CCLK"), - CLK(cclk0, NULL, "CCLK0"), - CLK(cclk1, NULL, "CCLK1"), - CLK(sysclk, NULL, "SYSCLK"), - CLK(sclk0, NULL, "SCLK0"), - CLK(sclk1, NULL, "SCLK1"), - CLK(dclk, NULL, "DCLK"), - CLK(oclk, NULL, "OCLK"), - CLK(ethclk, NULL, "stmmaceth"), - CLK(ethpclk, NULL, "pclk"), - CLK(spiclk, NULL, "spi"), -}; - -int __init clk_init(void) -{ - int i; - struct clk *clkp; - for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) { - clkp = bf609_clks[i].clk; - if (clkp->flags & NEEDS_INITIALIZATION) - clk_get_rate(clkp); - } - clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks)); - return 0; -} diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c deleted file mode 100644 index 1da4b38ac22c..000000000000 --- a/arch/blackfin/mach-bf609/dma.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * the simple DMA Implementation for Blackfin - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include - -#include -#include - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) DMA8_NEXT_DESC_PTR, - (struct dma_register *) DMA9_NEXT_DESC_PTR, - (struct dma_register *) DMA10_NEXT_DESC_PTR, - (struct dma_register *) DMA11_NEXT_DESC_PTR, - (struct dma_register *) DMA12_NEXT_DESC_PTR, - (struct dma_register *) DMA13_NEXT_DESC_PTR, - (struct dma_register *) DMA14_NEXT_DESC_PTR, - (struct dma_register *) DMA15_NEXT_DESC_PTR, - (struct dma_register *) DMA16_NEXT_DESC_PTR, - (struct dma_register *) DMA17_NEXT_DESC_PTR, - (struct dma_register *) DMA18_NEXT_DESC_PTR, - (struct dma_register *) DMA19_NEXT_DESC_PTR, - (struct dma_register *) DMA20_NEXT_DESC_PTR, - (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR, - (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR, - (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR, - (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR, - (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR, - (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR, - (struct dma_register *) DMA29_NEXT_DESC_PTR, - (struct dma_register *) DMA30_NEXT_DESC_PTR, - (struct dma_register *) DMA31_NEXT_DESC_PTR, - (struct dma_register *) DMA32_NEXT_DESC_PTR, - (struct dma_register *) DMA33_NEXT_DESC_PTR, - (struct dma_register *) DMA34_NEXT_DESC_PTR, - (struct dma_register *) DMA35_NEXT_DESC_PTR, - (struct dma_register *) DMA36_NEXT_DESC_PTR, - (struct dma_register *) DMA37_NEXT_DESC_PTR, - (struct dma_register *) DMA38_NEXT_DESC_PTR, - (struct dma_register *) DMA39_NEXT_DESC_PTR, - (struct dma_register *) DMA40_NEXT_DESC_PTR, - (struct dma_register *) DMA41_NEXT_DESC_PTR, - (struct dma_register *) DMA42_NEXT_DESC_PTR, - (struct dma_register *) DMA43_NEXT_DESC_PTR, - (struct dma_register *) DMA44_NEXT_DESC_PTR, - (struct dma_register *) DMA45_NEXT_DESC_PTR, - (struct dma_register *) DMA46_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - case CH_SPORT2_RX: - ret_irq = IRQ_SPORT2_RX; - break; - case CH_SPORT2_TX: - ret_irq = IRQ_SPORT2_TX; - break; - case CH_SPI0_TX: - ret_irq = IRQ_SPI0_TX; - break; - case CH_SPI0_RX: - ret_irq = IRQ_SPI0_RX; - break; - case CH_SPI1_TX: - ret_irq = IRQ_SPI1_TX; - break; - case CH_SPI1_RX: - ret_irq = IRQ_SPI1_RX; - break; - case CH_RSI: - ret_irq = IRQ_RSI; - break; - case CH_SDU: - ret_irq = IRQ_SDU; - break; - case CH_LP0: - ret_irq = IRQ_LP0; - break; - case CH_LP1: - ret_irq = IRQ_LP1; - break; - case CH_LP2: - ret_irq = IRQ_LP2; - break; - case CH_LP3: - ret_irq = IRQ_LP3; - break; - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - case CH_UART1_RX: - ret_irq = IRQ_UART1_RX; - break; - case CH_UART1_TX: - ret_irq = IRQ_UART1_TX; - break; - case CH_EPPI0_CH0: - ret_irq = IRQ_EPPI0_CH0; - break; - case CH_EPPI0_CH1: - ret_irq = IRQ_EPPI0_CH1; - break; - case CH_EPPI1_CH0: - ret_irq = IRQ_EPPI1_CH0; - break; - case CH_EPPI1_CH1: - ret_irq = IRQ_EPPI1_CH1; - break; - case CH_EPPI2_CH0: - ret_irq = IRQ_EPPI2_CH0; - break; - case CH_EPPI2_CH1: - ret_irq = IRQ_EPPI2_CH1; - break; - case CH_PIXC_CH0: - ret_irq = IRQ_PIXC_CH0; - break; - case CH_PIXC_CH1: - ret_irq = IRQ_PIXC_CH1; - break; - case CH_PIXC_CH2: - ret_irq = IRQ_PIXC_CH2; - break; - case CH_PVP_CPDOB: - ret_irq = IRQ_PVP_CPDOB; - break; - case CH_PVP_CPDOC: - ret_irq = IRQ_PVP_CPDOC; - break; - case CH_PVP_CPSTAT: - ret_irq = IRQ_PVP_CPSTAT; - break; - case CH_PVP_CPCI: - ret_irq = IRQ_PVP_CPCI; - break; - case CH_PVP_MPDO: - ret_irq = IRQ_PVP_MPDO; - break; - case CH_PVP_MPDI: - ret_irq = IRQ_PVP_MPDI; - break; - case CH_PVP_MPSTAT: - ret_irq = IRQ_PVP_MPSTAT; - break; - case CH_PVP_MPCI: - ret_irq = IRQ_PVP_MPCI; - break; - case CH_PVP_CPDOA: - ret_irq = IRQ_PVP_CPDOA; - break; - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MDMAS0; - break; - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MDMAS1; - break; - case CH_MEM_STREAM2_SRC: - case CH_MEM_STREAM2_DEST: - ret_irq = IRQ_MDMAS2; - break; - case CH_MEM_STREAM3_SRC: - case CH_MEM_STREAM3_DEST: - ret_irq = IRQ_MDMAS3; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S deleted file mode 100644 index fcb8f688a8b2..000000000000 --- a/arch/blackfin/mach-bf609/dpm.S +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include -#include -#include - -#include - -#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) - -.section .l1.text -ENTRY(_enter_hibernate) - /* switch stack to L1 scratch, prepare for ddr srfr */ - P0.H = HI(PM_STACK); - P0.L = LO(PM_STACK); - SP = P0; - - call _bf609_ddr_sr; - call _bfin_hibernate_syscontrol; - - P0.H = HI(DPM0_RESTORE4); - P0.L = LO(DPM0_RESTORE4); - P1.H = _bf609_pm_data; - P1.L = _bf609_pm_data; - [P0] = P1; - - P0.H = HI(DPM0_CTL); - P0.L = LO(DPM0_CTL); - R3.H = HI(0x00000010); - R3.L = LO(0x00000010); - - bfin_init_pm_bench_cycles; - - [P0] = R3; - - SSYNC; -ENDPROC(_enter_hibernate) - -/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK - * is disabled. This behavior differ from bf5xx serial processor. - */ -ENTRY(_dummy_deepsleep) - [--sp] = SYSCFG; - [--sp] = (R7:0,P5:0); - cli r0; - - /* get wake up interrupt ID */ - P0.l = LO(SEC_SCI_BASE + SEC_CSID); - P0.h = HI(SEC_SCI_BASE + SEC_CSID); - R0 = [P0]; - - /* ACK wake up interrupt in SEC */ - P1.l = LO(SEC_END); - P1.h = HI(SEC_END); - - [P1] = R0; - SSYNC; - - /* restore EVT 11 entry */ - p0.h = hi(EVT11); - p0.l = lo(EVT11); - p1.h = _evt_evt11; - p1.l = _evt_evt11; - - [p0] = p1; - SSYNC; - - (R7:0,P5:0) = [sp++]; - SYSCFG = [sp++]; - RTI; -ENDPROC(_dummy_deepsleep) - -ENTRY(_enter_deepsleep) - LINK 0xC; - [--sp] = (R7:0,P5:0); - - /* Change EVT 11 entry to dummy handler for wake up event */ - p0.h = hi(EVT11); - p0.l = lo(EVT11); - p1.h = _dummy_deepsleep; - p1.l = _dummy_deepsleep; - - [p0] = p1; - - P0.H = HI(PM_STACK); - P0.L = LO(PM_STACK); - - EX_SCRATCH_REG = SP; - SP = P0; - - SSYNC; - - /* should put ddr to self refresh mode before sleep */ - call _bf609_ddr_sr; - - /* Set DPM controller to deep sleep mode */ - P0.H = HI(DPM0_CTL); - P0.L = LO(DPM0_CTL); - R3.H = HI(0x00000008); - R3.L = LO(0x00000008); - [P0] = R3; - CSYNC; - - /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */ - r0.l = 0x800; - r0.h = 0; - sti r0; - SSYNC; - - bfin_init_pm_bench_cycles; - - /* Fall into deep sleep in idle*/ - idle; - SSYNC; - - /* Restore PLL after wake up from deep sleep */ - call _bf609_resume_ccbuf; - - /* turn ddr out of self refresh mode */ - call _bf609_ddr_sr_exit; - - SP = EX_SCRATCH_REG; - - (R7:0,P5:0) = [SP++]; - UNLINK; - RTS; -ENDPROC(_enter_deepsleep) - -.section .text -ENTRY(_bf609_hibernate) - bfin_cpu_reg_save; - bfin_core_mmr_save; - - P0.H = _bf609_pm_data; - P0.L = _bf609_pm_data; - R1.H = 0xDEAD; - R1.L = 0xBEEF; - R2.H = .Lpm_resume_here; - R2.L = .Lpm_resume_here; - [P0++] = R1; - [P0++] = R2; - [P0++] = SP; - - P1.H = _enter_hibernate; - P1.L = _enter_hibernate; - - call (P1); -.Lpm_resume_here: - - bfin_core_mmr_restore; - bfin_cpu_reg_restore; - - [--sp] = RETI; /* Clear Global Interrupt Disable */ - SP += 4; - - RTS; - -ENDPROC(_bf609_hibernate) - diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h deleted file mode 100644 index 696786e9a531..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/anomaly.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2012 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List - */ - -#if __SILICON_REVISION__ < 0 -# error will not work on BF609 silicon version -#endif - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */ -#define ANOMALY_16000003 (1) -/* The EPPI Data Enable (DEN) Signal is Not Functional */ -#define ANOMALY_16000004 (__SILICON_REVISION__ < 1) -/* Using L1 Instruction Cache with Parity Enabled is Unreliable */ -#define ANOMALY_16000005 (__SILICON_REVISION__ < 1) -/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */ -#define ANOMALY_16000006 (__SILICON_REVISION__ < 1) -/* DDR2 Memory Reads May Fail Intermittently */ -#define ANOMALY_16000007 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_16000008 (1) -/* TestSET Instruction Cannot Be Interrupted */ -#define ANOMALY_16000009 (1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_16000010 (1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_16000011 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_16000012 (1) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_16000013 (1) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_16000014 (1) -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_16000015 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_16000017 (1) -/* RSI Boot Cleanup Routine Does Not Clear Registers */ -#define ANOMALY_16000018 (__SILICON_REVISION__ < 1) -/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */ -#define ANOMALY_16000019 (__SILICON_REVISION__ < 1) -/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */ -#define ANOMALY_16000020 (__SILICON_REVISION__ < 1) -/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */ -#define ANOMALY_16000021 (__SILICON_REVISION__ < 1) -/* Boot Code Fails to Enable Parity Fault Detection */ -#define ANOMALY_16000022 (__SILICON_REVISION__ < 1) -/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */ -#define ANOMALY_16000023 (__SILICON_REVISION__ < 1) -/* Spurious Fault Signaled After Clearing an Externally Generated Fault */ -#define ANOMALY_16000024 (1) -/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */ -#define ANOMALY_16000025 (1) -/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */ -#define ANOMALY_16000027 (__SILICON_REVISION__ < 1) -/* Default SPI Master Boot Mode Setting is Incorrect */ -#define ANOMALY_16000028 (__SILICON_REVISION__ < 1) -/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */ -#define ANOMALY_16000027 (__SILICON_REVISION__ < 1) -/* Interrupted Core Reads of MMRs May Cause Data Loss */ -#define ANOMALY_16000030 (__SILICON_REVISION__ < 1) -/* Incorrect Default USB_PLL_OSC.PLLM Value */ -#define ANOMALY_16000031 (__SILICON_REVISION__ < 1) -/* Core Reads of System MMRs May Cause the Core to Hang */ -#define ANOMALY_16000032 (__SILICON_REVISION__ < 1) -/* PPI Data Underflow on First Word Not Reported in Certain Modes */ -#define ANOMALY_16000033 (1) -/* CNV1 Red Pixel Substitution feature not functional in the PVP */ -#define ANOMALY_16000034 (__SILICON_REVISION__ < 1) -/* IPF0 Output Port Color Separation feature not functional */ -#define ANOMALY_16000035 (__SILICON_REVISION__ < 1) -/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */ -#define ANOMALY_16000036 (__SILICON_REVISION__ < 1) -/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */ -#define ANOMALY_16000037 (__SILICON_REVISION__ < 1) -/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */ -#define ANOMALY_16000038 (__SILICON_REVISION__ < 1) -/* CGU_STAT.PLOCKERR Bit May be Unreliable */ -#define ANOMALY_16000039 (1) -/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */ -#define ANOMALY_16000040 (1) -/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */ -#define ANOMALY_16000041 (1) -/* Instruction Cache Failure When Parity Is Enabled */ -#define ANOMALY_16000042 (__SILICON_REVISION__ == 1) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000158 (0) -#define ANOMALY_05000189 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000220 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000231 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000263 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000278 (0) -#define ANOMALY_05000281 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000312 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000450 (0) -#define ANOMALY_05000456 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_05000481 (1) - -/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */ -#define ANOMALY_05000491 ANOMALY_16000008 -#define ANOMALY_05000477 ANOMALY_16000009 -#define ANOMALY_05000443 ANOMALY_16000010 -#define ANOMALY_05000461 ANOMALY_16000011 -#define ANOMALY_05000426 ANOMALY_16000012 -#define ANOMALY_05000310 ANOMALY_16000013 -#define ANOMALY_05000245 ANOMALY_16000014 -#define ANOMALY_05000074 ANOMALY_16000015 -#define ANOMALY_05000416 ANOMALY_16000017 - - -#endif diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h deleted file mode 100644 index c897c2a2fbfa..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/bf609.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF609_H__ -#define __MACH_BF609_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN) - -#if defined(CONFIG_BF609) -# define CPU "BF609" -# define CPUID 0x27fe /* temperary fake value */ -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF609_H__ */ diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h deleted file mode 100644 index 1fd398147fd9..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 2 -#define BFIN_UART_TX_FIFO_SIZE 8 - -#define BFIN_UART_BF60X_STYLE - -#endif diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h deleted file mode 100644 index b1a48c410711..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/blackfin.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#include "bf609.h" -#include "anomaly.h" - -#include -#ifdef CONFIG_BF609 -# include "defBF609.h" -#endif - -#ifndef __ASSEMBLY__ -# include -# ifdef CONFIG_BF609 -# include "cdefBF609.h" -# endif -#endif - -#endif diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h deleted file mode 100644 index c4f3fe19acda..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF609_H -#define _CDEF_BF609_H - -/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */ -#include "cdefBF60x_base.h" - -/* The following are the #defines needed by ADSP-BF609 that are not in the common header */ - -#endif /* _CDEF_BF609_H */ diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h deleted file mode 100644 index 102ee4025ac9..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h +++ /dev/null @@ -1,3254 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _CDEF_BF60X_H -#define _CDEF_BF60X_H - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */ -/* ************************************************************** */ - -/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ - -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) - -/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ - -/* SEC0 Registers */ -#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL) -#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val) -#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID) -#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val) -#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL) -#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val) - -#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL) -#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val) - -#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8)) -#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val) - -#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8)) -#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val) - -/* RCU0 Registers */ -#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL) -#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val) - -/* Watchdog Timer Registers */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) - -/* RTC Registers */ - -/* UART0 Registers */ - -#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID) -#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val) -#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val) -#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT) -#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val) -#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val) -#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK) -#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val) -#define bfin_read_UART0_IER() bfin_read32(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val) -#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET) -#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val) -#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR) -#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val) -#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val) -#define bfin_read_UART0_THR() bfin_read32(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val) -#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP) -#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val) -#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR) -#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val) -#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR) -#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val) -#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT) -#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val) -#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT) -#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val) - -/* UART1 Registers */ - -#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID) -#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val) -#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val) -#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT) -#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val) -#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val) -#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK) -#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val) -#define bfin_read_UART1_IER() bfin_read32(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val) -#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET) -#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val) -#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR) -#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val) -#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val) -#define bfin_read_UART1_THR() bfin_read32(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val) -#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP) -#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val) -#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR) -#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val) -#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR) -#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val) -#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT) -#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val) -#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT) -#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val) - - -/* SPI0 Registers */ - -#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val) -#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL) -#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val) -#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL) -#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val) -#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK) -#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val) -#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY) -#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val) -#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL) -#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val) -#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC) -#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val) -#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR) -#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val) -#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC) -#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val) -#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR) -#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val) -#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK) -#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val) -#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR) -#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val) -#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET) -#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val) -#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val) -#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT) -#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val) -#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR) -#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val) -#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO) -#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val) -#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO) -#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val) - -/* SPI1 Registers */ - -#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val) -#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL) -#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val) -#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL) -#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val) -#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK) -#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val) -#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY) -#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val) -#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL) -#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val) -#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC) -#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val) -#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR) -#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val) -#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC) -#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val) -#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR) -#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val) -#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK) -#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val) -#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR) -#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val) -#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET) -#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val) -#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val) -#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT) -#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val) -#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR) -#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val) -#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO) -#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val) -#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO) -#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val) - -/* Timer 0-7 registers */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) - - - - -/* Two Wire Interface Registers (TWI0) */ - -/* SPORT1 Registers */ - - -/* SMC Registers */ -#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL) -#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val) -#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT) -#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL) -#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val) -#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM) -#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val) -#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM) -#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val) -#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL) -#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val) -#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM) -#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val) -#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM) -#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val) -#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL) -#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val) -#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM) -#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val) -#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM) -#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val) -#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL) -#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val) -#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM) -#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val) -#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM) -#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val) - -/* DDR2 Memory Control Registers */ -#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG) -#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val) -#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0) -#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val) -#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1) -#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val) -#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2) -#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val) -#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR) -#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val) -#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1) -#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) -#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) -#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) -#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL) -#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val) -#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) -#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) -#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) -#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val) - -/* DDR BankRead and Write Count Registers */ - - -/* DMA Channel 0 Registers */ - -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val) -#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR) -#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT) -#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val) -#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT) -#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val) -#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT) -#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val) -#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT) -#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val) - -/* DMA Channel 1 Registers */ - -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val) -#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR) -#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT) -#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val) -#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT) -#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val) -#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT) -#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val) -#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT) -#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val) - -/* DMA Channel 2 Registers */ - -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val) -#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR) -#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT) -#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val) -#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT) -#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val) -#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT) -#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val) -#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT) -#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val) - -/* DMA Channel 3 Registers */ - -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val) -#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR) -#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT) -#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val) -#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT) -#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val) -#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT) -#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val) -#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT) -#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val) - -/* DMA Channel 4 Registers */ - -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val) -#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR) -#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT) -#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val) -#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT) -#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val) -#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT) -#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val) -#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT) -#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val) - -/* DMA Channel 5 Registers */ - -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val) -#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR) -#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT) -#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val) -#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT) -#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val) -#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT) -#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val) -#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT) -#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val) - -/* DMA Channel 6 Registers */ - -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val) -#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR) -#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT) -#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val) -#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT) -#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val) -#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT) -#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val) -#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT) -#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val) - -/* DMA Channel 7 Registers */ - -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val) -#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR) -#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT) -#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val) -#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT) -#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val) -#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT) -#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val) -#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT) -#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val) - -/* DMA Channel 8 Registers */ - -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) -#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val) -#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR) -#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT) -#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val) -#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT) -#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val) -#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT) -#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val) -#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT) -#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val) - -/* DMA Channel 9 Registers */ - -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) -#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val) -#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR) -#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT) -#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val) -#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT) -#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val) -#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT) -#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val) -#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT) -#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val) - -/* DMA Channel 10 Registers */ - -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) -#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val) -#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR) -#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT) -#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val) -#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT) -#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val) -#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT) -#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val) -#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT) -#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val) - -/* DMA Channel 11 Registers */ - -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) -#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val) -#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR) -#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val) -#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT) -#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val) -#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT) -#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val) -#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT) -#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val) -#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT) -#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val) - -/* DMA Channel 12 Registers */ - -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) -#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) -#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val) -#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val) -#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val) -#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val) -#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val) -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) -#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR) -#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val) -#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) -#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val) -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val) -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val) -#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT) -#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val) -#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT) -#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val) -#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT) -#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val) -#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT) -#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val) - -/* DMA Channel 13 Registers */ - -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) -#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) -#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val) -#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val) -#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val) -#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val) -#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val) -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) -#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR) -#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val) -#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) -#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val) -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val) -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val) -#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT) -#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val) -#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT) -#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val) -#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT) -#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val) -#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT) -#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val) - -/* DMA Channel 14 Registers */ - -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) -#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) -#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val) -#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val) -#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val) -#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val) -#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val) -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) -#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR) -#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val) -#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) -#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val) -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val) -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val) -#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT) -#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val) -#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT) -#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val) -#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT) -#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val) -#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT) -#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val) - -/* DMA Channel 15 Registers */ - -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) -#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) -#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val) -#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val) -#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val) -#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val) -#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val) -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) -#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR) -#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val) -#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) -#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val) -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val) -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val) -#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT) -#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val) -#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT) -#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val) -#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT) -#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val) -#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT) -#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val) - -/* DMA Channel 16 Registers */ - -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) -#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) -#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val) -#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val) -#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val) -#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val) -#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val) -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) -#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR) -#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val) -#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) -#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val) -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val) -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val) -#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT) -#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val) -#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT) -#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val) -#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT) -#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val) -#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT) -#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val) - -/* DMA Channel 17 Registers */ - -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) -#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) -#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val) -#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val) -#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val) -#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val) -#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val) -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) -#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR) -#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val) -#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) -#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val) -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val) -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val) -#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT) -#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val) -#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT) -#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val) -#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT) -#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val) -#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT) -#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val) - -/* DMA Channel 18 Registers */ - -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) -#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) -#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val) -#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val) -#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val) -#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val) -#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val) -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) -#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR) -#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val) -#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) -#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val) -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val) -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val) -#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT) -#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val) -#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT) -#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val) -#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT) -#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val) -#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT) -#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val) - -/* DMA Channel 19 Registers */ - -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) -#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) -#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val) -#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val) -#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val) -#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val) -#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val) -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) -#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR) -#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val) -#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) -#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val) -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val) -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val) -#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT) -#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val) -#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT) -#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val) -#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT) -#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val) -#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT) -#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val) - -/* DMA Channel 20 Registers */ - -#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) -#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) -#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG) -#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val) -#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT) -#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val) -#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val) -#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT) -#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val) -#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val) -#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) -#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR) -#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val) -#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) -#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS) -#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val) -#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT) -#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val) -#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT) -#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val) -#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT) -#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val) -#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT) -#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val) -#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT) -#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val) -#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT) -#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val) - - -/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */ - -#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR) -#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR) -#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val) -#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG) -#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val) -#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT) -#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val) -#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY) -#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val) -#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT) -#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val) -#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY) -#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val) -#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR) -#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val) -#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR) -#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val) -#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR) -#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val) -#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS) -#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val) -#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT) -#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val) -#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT) -#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val) -#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR) -#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR) -#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val) -#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG) -#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val) -#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT) -#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val) -#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY) -#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val) -#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT) -#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val) -#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY) -#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val) -#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR) -#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val) -#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR) -#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val) -#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR) -#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val) -#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS) -#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val) -#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT) -#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val) -#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT) -#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val) - -/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */ - -#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR) -#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val) -#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG) -#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val) -#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT) -#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val) -#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY) -#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val) -#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT) -#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val) -#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY) -#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val) -#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR) -#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val) -#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR) -#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val) -#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR) -#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val) -#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS) -#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val) -#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT) -#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val) -#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT) -#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val) -#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR) -#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val) -#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG) -#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val) -#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT) -#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val) -#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY) -#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val) -#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT) -#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val) -#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY) -#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val) -#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR) -#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val) -#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR) -#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val) -#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR) -#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val) -#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS) -#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val) -#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT) -#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val) -#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT) -#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val) - - -/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */ - -#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR) -#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val) -#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR) -#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val) -#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG) -#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val) -#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT) -#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val) -#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY) -#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val) -#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT) -#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val) -#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY) -#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val) -#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR) -#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val) -#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR) -#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val) -#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR) -#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val) -#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS) -#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val) -#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT) -#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val) -#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT) -#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val) -#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR) -#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val) -#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR) -#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val) -#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG) -#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val) -#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT) -#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val) -#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY) -#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val) -#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT) -#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val) -#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY) -#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val) -#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR) -#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val) -#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR) -#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val) -#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR) -#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val) -#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS) -#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val) -#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT) -#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val) -#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT) -#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val) - -/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */ - -#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR) -#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val) -#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR) -#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val) -#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG) -#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val) -#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT) -#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val) -#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY) -#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val) -#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT) -#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val) -#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY) -#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val) -#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR) -#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val) -#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR) -#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val) -#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR) -#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val) -#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS) -#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val) -#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT) -#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val) -#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT) -#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val) -#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR) -#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val) -#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR) -#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val) -#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG) -#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val) -#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT) -#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val) -#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY) -#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val) -#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT) -#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val) -#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY) -#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val) -#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR) -#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val) -#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR) -#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val) -#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR) -#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val) -#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS) -#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val) -#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT) -#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val) -#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT) -#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val) - - -/* DMA Channel 29 Registers */ - -#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR) -#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val) -#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR) -#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val) -#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG) -#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val) -#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT) -#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val) -#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY) -#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val) -#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT) -#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val) -#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY) -#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val) -#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR) -#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val) -#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR) -#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val) -#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR) -#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val) -#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS) -#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val) -#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT) -#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val) -#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT) -#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val) -#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT) -#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val) -#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT) -#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val) -#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT) -#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val) -#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT) -#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val) - -/* DMA Channel 30 Registers */ - -#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR) -#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val) -#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR) -#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val) -#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG) -#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val) -#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT) -#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val) -#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY) -#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val) -#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT) -#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val) -#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY) -#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val) -#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR) -#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val) -#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR) -#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val) -#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR) -#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val) -#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS) -#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val) -#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT) -#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val) -#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT) -#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val) -#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT) -#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val) -#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT) -#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val) -#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT) -#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val) -#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT) -#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val) - -/* DMA Channel 31 Registers */ - -#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR) -#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val) -#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR) -#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val) -#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG) -#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val) -#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT) -#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val) -#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY) -#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val) -#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT) -#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val) -#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY) -#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val) -#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR) -#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val) -#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR) -#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val) -#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR) -#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val) -#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS) -#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val) -#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT) -#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val) -#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT) -#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val) -#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT) -#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val) -#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT) -#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val) -#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT) -#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val) -#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT) -#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val) - -/* DMA Channel 32 Registers */ - -#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR) -#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val) -#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR) -#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val) -#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG) -#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val) -#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT) -#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val) -#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY) -#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val) -#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT) -#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val) -#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY) -#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val) -#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR) -#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val) -#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR) -#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val) -#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR) -#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val) -#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS) -#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val) -#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT) -#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val) -#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT) -#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val) -#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT) -#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val) -#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT) -#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val) -#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT) -#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val) -#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT) -#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val) - -/* DMA Channel 33 Registers */ - -#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR) -#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val) -#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR) -#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val) -#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG) -#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val) -#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT) -#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val) -#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY) -#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val) -#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT) -#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val) -#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY) -#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val) -#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR) -#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val) -#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR) -#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val) -#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR) -#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val) -#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS) -#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val) -#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT) -#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val) -#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT) -#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val) -#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT) -#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val) -#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT) -#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val) -#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT) -#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val) -#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT) -#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val) - -/* DMA Channel 34 Registers */ - -#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR) -#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val) -#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR) -#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val) -#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG) -#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val) -#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT) -#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val) -#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY) -#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val) -#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT) -#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val) -#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY) -#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val) -#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR) -#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val) -#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR) -#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val) -#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR) -#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val) -#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS) -#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val) -#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT) -#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val) -#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT) -#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val) -#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT) -#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val) -#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT) -#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val) -#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT) -#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val) -#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT) -#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val) - -/* DMA Channel 35 Registers */ - -#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR) -#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val) -#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR) -#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val) -#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG) -#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val) -#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT) -#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val) -#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY) -#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val) -#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT) -#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val) -#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY) -#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val) -#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR) -#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val) -#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR) -#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val) -#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR) -#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val) -#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS) -#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val) -#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT) -#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val) -#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT) -#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val) -#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT) -#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val) -#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT) -#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val) -#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT) -#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val) -#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT) -#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val) - -/* DMA Channel 36 Registers */ - -#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR) -#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val) -#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR) -#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val) -#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG) -#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val) -#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT) -#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val) -#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY) -#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val) -#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT) -#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val) -#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY) -#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val) -#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR) -#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val) -#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR) -#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val) -#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR) -#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val) -#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS) -#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val) -#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT) -#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val) -#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT) -#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val) -#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT) -#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val) -#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT) -#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val) -#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT) -#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val) -#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT) -#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val) - -/* DMA Channel 37 Registers */ - -#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR) -#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val) -#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR) -#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val) -#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG) -#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val) -#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT) -#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val) -#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY) -#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val) -#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT) -#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val) -#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY) -#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val) -#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR) -#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val) -#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR) -#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val) -#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR) -#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val) -#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS) -#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val) -#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT) -#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val) -#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT) -#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val) -#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT) -#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val) -#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT) -#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val) -#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT) -#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val) -#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT) -#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val) - -/* DMA Channel 38 Registers */ - -#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR) -#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val) -#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR) -#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val) -#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG) -#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val) -#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT) -#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val) -#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY) -#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val) -#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT) -#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val) -#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY) -#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val) -#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR) -#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val) -#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR) -#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val) -#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR) -#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val) -#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS) -#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val) -#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT) -#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val) -#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT) -#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val) -#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT) -#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val) -#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT) -#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val) -#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT) -#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val) -#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT) -#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val) - -/* DMA Channel 39 Registers */ - -#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR) -#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val) -#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR) -#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val) -#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG) -#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val) -#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT) -#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val) -#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY) -#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val) -#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT) -#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val) -#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY) -#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val) -#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR) -#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val) -#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR) -#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val) -#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR) -#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val) -#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS) -#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val) -#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT) -#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val) -#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT) -#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val) -#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT) -#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val) -#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT) -#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val) -#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT) -#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val) -#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT) -#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val) - -/* DMA Channel 40 Registers */ - -#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR) -#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val) -#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR) -#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val) -#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG) -#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val) -#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT) -#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val) -#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY) -#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val) -#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT) -#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val) -#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY) -#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val) -#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR) -#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val) -#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR) -#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val) -#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR) -#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val) -#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS) -#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val) -#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT) -#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val) -#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT) -#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val) -#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT) -#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val) -#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT) -#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val) -#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT) -#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val) -#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT) -#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val) - -/* DMA Channel 41 Registers */ - -#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR) -#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val) -#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR) -#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val) -#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG) -#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val) -#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT) -#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val) -#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY) -#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val) -#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT) -#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val) -#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY) -#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val) -#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR) -#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val) -#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR) -#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val) -#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR) -#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val) -#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS) -#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val) -#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT) -#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val) -#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT) -#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val) -#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT) -#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val) -#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT) -#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val) -#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT) -#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val) -#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT) -#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val) - -/* DMA Channel 42 Registers */ - -#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR) -#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val) -#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR) -#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val) -#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG) -#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val) -#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT) -#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val) -#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY) -#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val) -#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT) -#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val) -#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY) -#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val) -#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR) -#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val) -#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR) -#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val) -#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR) -#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val) -#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS) -#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val) -#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT) -#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val) -#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT) -#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val) -#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT) -#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val) -#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT) -#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val) -#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT) -#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val) -#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT) -#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val) - -/* DMA Channel 43 Registers */ - -#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR) -#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val) -#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR) -#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val) -#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG) -#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val) -#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT) -#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val) -#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY) -#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val) -#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT) -#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val) -#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY) -#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val) -#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR) -#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val) -#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR) -#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val) -#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR) -#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val) -#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS) -#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val) -#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT) -#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val) -#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT) -#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val) -#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT) -#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val) -#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT) -#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val) -#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT) -#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val) -#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT) -#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val) - -/* DMA Channel 44 Registers */ - -#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR) -#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val) -#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR) -#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val) -#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG) -#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val) -#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT) -#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val) -#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY) -#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val) -#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT) -#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val) -#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY) -#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val) -#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR) -#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val) -#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR) -#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val) -#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR) -#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val) -#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS) -#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val) -#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT) -#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val) -#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT) -#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val) -#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT) -#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val) -#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT) -#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val) -#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT) -#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val) -#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT) -#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val) - -/* DMA Channel 45 Registers */ - -#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR) -#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val) -#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR) -#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val) -#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG) -#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val) -#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT) -#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val) -#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY) -#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val) -#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT) -#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val) -#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY) -#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val) -#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR) -#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val) -#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR) -#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val) -#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR) -#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val) -#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS) -#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val) -#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT) -#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val) -#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT) -#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val) -#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT) -#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val) -#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT) -#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val) -#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT) -#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val) -#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT) -#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val) - -/* DMA Channel 46 Registers */ - -#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR) -#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val) -#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR) -#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val) -#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG) -#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val) -#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT) -#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val) -#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY) -#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val) -#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT) -#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val) -#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY) -#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val) -#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR) -#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val) -#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR) -#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val) -#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR) -#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val) -#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS) -#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val) -#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT) -#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val) -#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT) -#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val) -#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT) -#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val) -#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT) -#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val) -#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT) -#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val) -#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT) -#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val) - - -/* EPPI1 Registers */ - - -/* Port Interrubfin_read_()t 0 Registers (32-bit) */ - -#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) -#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) -#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST) -#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val) -#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) -#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) -#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) -#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) -#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) -#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) -#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) -#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) - -/* Port Interrubfin_read_()t 1 Registers (32-bit) */ - -#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) -#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) -#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST) -#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val) -#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) -#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) -#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) -#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) -#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) -#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) -#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) -#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) - -/* Port Interrubfin_read_()t 2 Registers (32-bit) */ - -#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) -#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) -#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST) -#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val) -#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) -#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) -#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) -#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) -#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) -#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) -#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) -#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) - -/* Port Interrubfin_read_()t 3 Registers (32-bit) */ - -#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) -#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) -#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST) -#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val) -#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) -#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) -#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) -#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) -#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) -#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) -#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) -#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) - -/* Port Interrubfin_read_()t 4 Registers (32-bit) */ - -#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET) -#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val) -#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR) -#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val) -#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST) -#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val) -#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN) -#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val) -#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET) -#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val) -#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR) -#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val) -#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET) -#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val) -#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR) -#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val) -#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE) -#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val) -#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH) -#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val) - -/* Port Interrubfin_read_()t 5 Registers (32-bit) */ - -#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET) -#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val) -#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR) -#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val) -#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST) -#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val) -#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN) -#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val) -#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET) -#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val) -#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR) -#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val) -#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET) -#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val) -#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR) -#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val) -#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE) -#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val) -#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH) -#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val) - -/* Port A Registers */ - -#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER) -#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val) -#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET) -#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val) -#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR) -#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val) -#define bfin_read_PORTA() bfin_read32(PORTA) -#define bfin_write_PORTA(val) bfin_write32(PORTA, val) -#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET) -#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val) -#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR) -#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val) -#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR) -#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val) -#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET) -#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val) -#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR) -#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val) -#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN) -#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val) -#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET) -#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val) -#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR) -#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val) -#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) -#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL) -#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val) -#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL) -#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val) -#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET) -#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val) -#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR) -#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val) -#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK) -#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val) -#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID) -#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val) - - - -/* Port B Registers */ -#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER) -#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val) -#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET) -#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val) -#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR) -#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val) -#define bfin_read_PORTB() bfin_read32(PORTB) -#define bfin_write_PORTB(val) bfin_write32(PORTB, val) -#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET) -#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val) -#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR) -#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val) -#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR) -#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val) -#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET) -#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val) -#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR) -#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val) -#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN) -#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val) -#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET) -#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val) -#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR) -#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val) -#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) -#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL) -#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val) -#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL) -#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val) -#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET) -#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val) -#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR) -#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val) -#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK) -#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val) -#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID) -#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val) - - -/* Port C Registers */ -#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER) -#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val) -#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET) -#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val) -#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR) -#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val) -#define bfin_read_PORTC() bfin_read32(PORTC) -#define bfin_write_PORTC(val) bfin_write32(PORTC, val) -#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET) -#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val) -#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR) -#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val) -#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR) -#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val) -#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET) -#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val) -#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR) -#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val) -#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN) -#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val) -#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET) -#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val) -#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR) -#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val) -#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) -#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL) -#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val) -#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL) -#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val) -#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET) -#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val) -#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR) -#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val) -#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK) -#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val) -#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID) -#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val) - - -/* Port D Registers */ -#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER) -#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val) -#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET) -#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val) -#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR) -#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val) -#define bfin_read_PORTD() bfin_read32(PORTD) -#define bfin_write_PORTD(val) bfin_write32(PORTD, val) -#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET) -#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val) -#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR) -#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val) -#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR) -#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val) -#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET) -#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val) -#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR) -#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val) -#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN) -#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val) -#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET) -#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val) -#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR) -#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val) -#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) -#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL) -#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val) -#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL) -#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val) -#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET) -#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val) -#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR) -#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val) -#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK) -#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val) -#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID) -#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val) - - -/* Port E Registers */ -#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER) -#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val) -#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET) -#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val) -#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR) -#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val) -#define bfin_read_PORTE() bfin_read32(PORTE) -#define bfin_write_PORTE(val) bfin_write32(PORTE, val) -#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET) -#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val) -#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR) -#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val) -#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR) -#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val) -#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET) -#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val) -#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR) -#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val) -#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN) -#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val) -#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET) -#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val) -#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR) -#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val) -#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) -#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL) -#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val) -#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL) -#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val) -#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET) -#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val) -#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR) -#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val) -#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK) -#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val) -#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID) -#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val) - - -/* Port F Registers */ -#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val) -#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET) -#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val) -#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR) -#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val) -#define bfin_read_PORTF() bfin_read32(PORTF) -#define bfin_write_PORTF(val) bfin_write32(PORTF, val) -#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET) -#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val) -#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR) -#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val) -#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR) -#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val) -#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET) -#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val) -#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR) -#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val) -#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN) -#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val) -#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET) -#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val) -#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR) -#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val) -#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL) -#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val) -#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL) -#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val) -#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET) -#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val) -#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR) -#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val) -#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK) -#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val) -#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID) -#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val) - - -/* Port G Registers */ -#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val) -#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET) -#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val) -#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR) -#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val) -#define bfin_read_PORTG() bfin_read32(PORTG) -#define bfin_write_PORTG(val) bfin_write32(PORTG, val) -#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET) -#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val) -#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR) -#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val) -#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR) -#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val) -#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET) -#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val) -#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR) -#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val) -#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN) -#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val) -#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET) -#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val) -#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR) -#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val) -#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL) -#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val) -#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL) -#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val) -#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET) -#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val) -#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR) -#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val) -#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK) -#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val) -#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID) -#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val) - - - - -/* CAN Controller 0 Config 1 Registers */ - -#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) -#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) -#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) -#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) -#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) -#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) -#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) -#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) -#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) -#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) -#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) -#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) -#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) -#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) - -/* CAN Controller 0 Config 2 Registers */ - -#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) -#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) -#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) -#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) -#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) -#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) -#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) -#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) -#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) -#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) -#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) -#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) -#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) -#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) - -/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */ - -#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) -#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) -#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) -#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) -#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) -#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) -#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) -#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) -#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) -#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) -#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) -#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) -#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) -#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) -#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) -#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) -#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) - -/* CAN Controller 0 Accebfin_read_()tance Registers */ - -#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) -#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) -#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) -#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) -#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) -#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) -#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) -#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) -#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) -#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) -#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) -#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) -#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) -#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) -#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) -#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) -#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) -#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) -#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) -#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) -#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) -#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) -#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) -#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) -#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) -#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) -#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) -#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) -#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) -#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) -#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) -#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) -#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) - -/* CAN Controller 0 Accebfin_read_()tance Registers */ - -#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) -#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) -#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) -#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) -#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) -#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) -#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) -#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) -#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) -#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) -#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) -#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) -#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) -#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) -#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) -#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) -#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) -#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) -#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) -#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) -#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) -#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) -#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) -#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) -#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) -#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) -#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) -#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) -#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) -#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) -#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) -#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) -#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) - -/* CAN Controller 0 Mailbox Data Registers */ - -#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) -#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) -#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) -#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) -#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) -#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) -#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) -#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) -#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) -#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) -#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) -#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) -#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) -#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) -#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) -#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) -#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) -#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) -#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) -#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) -#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) -#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) -#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) -#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) -#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) -#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) -#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) -#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) -#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) -#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) -#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) -#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) -#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) -#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) -#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) -#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) -#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) -#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) -#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) -#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) -#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) -#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) -#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) -#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) -#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) -#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) -#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) -#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) -#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) -#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) -#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) -#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) -#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) -#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) -#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) -#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) -#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) -#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) -#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) -#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) -#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) -#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) -#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) -#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) -#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) -#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) -#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) -#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) -#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) -#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) -#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) -#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) -#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) -#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) -#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) -#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) -#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) -#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) -#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) -#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) -#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) -#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) -#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) -#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) -#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) -#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) -#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) -#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) -#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) -#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) -#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) -#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) -#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) -#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) -#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) -#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) -#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) -#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) -#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) -#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) -#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) -#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) -#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) -#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) -#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) -#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) -#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) -#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) -#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) -#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) -#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) -#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) -#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) -#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) -#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) -#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) -#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) -#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) -#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) -#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) -#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) -#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) -#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) -#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) -#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) -#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) -#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) -#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) -#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) - -/* CAN Controller 0 Mailbox Data Registers */ - -#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) -#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) -#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) -#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) -#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) -#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) -#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) -#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) -#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) -#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) -#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) -#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) -#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) -#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) -#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) -#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) -#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) -#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) -#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) -#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) -#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) -#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) -#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) -#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) -#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) -#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) -#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) -#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) -#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) -#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) -#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) -#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) -#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) -#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) -#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) -#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) -#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) -#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) -#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) -#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) -#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) -#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) -#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) -#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) -#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) -#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) -#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) -#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) -#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) -#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) -#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) -#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) -#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) -#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) -#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) -#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) -#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) -#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) -#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) -#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) -#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) -#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) -#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) -#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) -#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) -#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) -#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) -#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) -#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) -#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) -#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) -#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) -#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) -#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) -#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) -#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) -#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) -#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) -#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) -#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) -#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) -#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) -#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) -#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) -#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) -#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) -#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) -#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) -#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) -#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) -#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) -#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) -#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) -#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) -#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) -#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) -#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) -#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) -#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) -#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) -#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) -#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) -#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) -#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) -#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) -#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) -#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) -#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) -#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) -#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) -#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) -#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) -#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) -#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) -#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) -#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) -#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) -#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) -#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) -#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) -#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) -#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) -#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) -#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) -#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) -#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) -#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) -#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) -#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) - -/* Counter Registers */ - -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) - -/* RSI Register */ -#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) -#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) -#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) -#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) -#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) -#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) -#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) -#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) -#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) -#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) -#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) -#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) -#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) -#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) -#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) -#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) -#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) -#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) -#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) -#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) -#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) -#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) -#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) -#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) -#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) -#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) -#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) -#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) -#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) -#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) -#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) -#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) -#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) -#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) -#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL) -#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val) -#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ) -#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val) -#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) -#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) -#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT) -#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val) -#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK) -#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val) -#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) -#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) -#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) -#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) -#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) -#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) -#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) -#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) -#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) -#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) -#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) -#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) - -/* usb register */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val) -#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val) -#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL) - -#endif /* _CDEF_BF60X_H */ - diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h deleted file mode 100644 index 8045ade34370..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/defBF609.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF609_H -#define _DEF_BF609_H - -/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */ -#include "defBF60x_base.h" - -/* The following are the #defines needed by ADSP-BF609 that are not in the common header */ -/* ========================= - PIXC Registers - ========================= */ - -/* ========================= - PIXC0 - ========================= */ -#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */ -#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */ -#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */ -#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */ -#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */ -#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */ -#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */ -#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */ -#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */ -#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */ -#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */ -#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */ -#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */ -#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */ -#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */ -#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */ -#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */ -#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */ -#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */ -#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */ - -/* ========================= - PVP Registers - ========================= */ - -/* ========================= - PVP0 - ========================= */ -#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */ -#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */ -#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */ -#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */ -#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */ -#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */ -#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */ -#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */ -#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */ -#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */ -#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */ -#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */ -#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */ -#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */ -#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */ -#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */ -#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */ -#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */ -#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */ -#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */ -#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */ -#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */ -#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */ -#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */ -#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */ -#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */ -#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */ -#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */ -#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */ -#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */ -#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */ -#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */ -#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */ -#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */ -#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */ -#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */ -#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */ -#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */ -#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */ -#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */ -#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */ -#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */ -#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */ -#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */ -#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */ -#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */ -#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */ -#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */ -#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */ -#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */ -#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */ -#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */ -#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */ -#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */ -#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */ -#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */ -#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */ -#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */ -#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */ -#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */ -#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */ -#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */ -#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */ -#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */ -#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */ -#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */ -#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */ -#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */ -#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */ -#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */ -#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */ -#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */ -#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */ -#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */ -#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */ -#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */ -#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */ -#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */ -#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */ -#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */ -#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */ -#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */ -#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */ -#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */ -#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */ -#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */ -#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */ -#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */ -#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */ -#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */ -#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */ -#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */ -#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */ -#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */ -#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */ -#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */ -#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */ -#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */ -#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */ -#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */ -#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */ -#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */ -#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */ -#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */ -#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */ -#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */ -#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */ -#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */ -#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */ -#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */ -#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */ -#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */ -#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */ -#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */ -#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */ -#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */ -#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */ -#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */ -#define PVP0_CNV3_C34 0xFFC1A3B4 /* PVP0 Coefficient 3, 4 */ -#define PVP0_CNV0_C40C41 0xFFC1A238 /* PVP0 Coefficients 4, 0 and 4, 1 */ -#define PVP0_CNV1_C40C41 0xFFC1A2B8 /* PVP0 Coefficients 4, 0 and 4, 1 */ -#define PVP0_CNV2_C40C41 0xFFC1A338 /* PVP0 Coefficients 4, 0 and 4, 1 */ -#define PVP0_CNV3_C40C41 0xFFC1A3B8 /* PVP0 Coefficients 4, 0 and 4, 1 */ -#define PVP0_CNV0_C42C43 0xFFC1A23C /* PVP0 Coefficients 4, 2 and 4, 3 */ -#define PVP0_CNV1_C42C43 0xFFC1A2BC /* PVP0 Coefficients 4, 2 and 4, 3 */ -#define PVP0_CNV2_C42C43 0xFFC1A33C /* PVP0 Coefficients 4, 2 and 4, 3 */ -#define PVP0_CNV3_C42C43 0xFFC1A3BC /* PVP0 Coefficients 4, 2 and 4, 3 */ -#define PVP0_CNV0_C44 0xFFC1A240 /* PVP0 Coefficient 4, 4 */ -#define PVP0_CNV1_C44 0xFFC1A2C0 /* PVP0 Coefficient 4, 4 */ -#define PVP0_CNV2_C44 0xFFC1A340 /* PVP0 Coefficient 4, 4 */ -#define PVP0_CNV3_C44 0xFFC1A3C0 /* PVP0 Coefficient 4, 4 */ -#define PVP0_CNV0_SCALE 0xFFC1A244 /* PVP0 Scaling factor */ -#define PVP0_CNV1_SCALE 0xFFC1A2C4 /* PVP0 Scaling factor */ -#define PVP0_CNV2_SCALE 0xFFC1A344 /* PVP0 Scaling factor */ -#define PVP0_CNV3_SCALE 0xFFC1A3C4 /* PVP0 Scaling factor */ -#define PVP0_THC0_CFG 0xFFC1A400 /* PVP0 Configuration */ -#define PVP0_THC1_CFG 0xFFC1A500 /* PVP0 Configuration */ -#define PVP0_THC0_CTL 0xFFC1A404 /* PVP0 Control */ -#define PVP0_THC1_CTL 0xFFC1A504 /* PVP0 Control */ -#define PVP0_THC0_HFCNT 0xFFC1A408 /* PVP0 Number of frames */ -#define PVP0_THC1_HFCNT 0xFFC1A508 /* PVP0 Number of frames */ -#define PVP0_THC0_RMAXREP 0xFFC1A40C /* PVP0 Maximum number of RLE reports */ -#define PVP0_THC1_RMAXREP 0xFFC1A50C /* PVP0 Maximum number of RLE reports */ -#define PVP0_THC0_CMINVAL 0xFFC1A410 /* PVP0 Min clip value */ -#define PVP0_THC1_CMINVAL 0xFFC1A510 /* PVP0 Min clip value */ -#define PVP0_THC0_CMINTH 0xFFC1A414 /* PVP0 Clip Min Threshold */ -#define PVP0_THC1_CMINTH 0xFFC1A514 /* PVP0 Clip Min Threshold */ -#define PVP0_THC0_CMAXTH 0xFFC1A418 /* PVP0 Clip Max Threshold */ -#define PVP0_THC1_CMAXTH 0xFFC1A518 /* PVP0 Clip Max Threshold */ -#define PVP0_THC0_CMAXVAL 0xFFC1A41C /* PVP0 Max clip value */ -#define PVP0_THC1_CMAXVAL 0xFFC1A51C /* PVP0 Max clip value */ -#define PVP0_THC0_TH0 0xFFC1A420 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH0 0xFFC1A520 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH1 0xFFC1A424 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH1 0xFFC1A524 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH2 0xFFC1A428 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH2 0xFFC1A528 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH3 0xFFC1A42C /* PVP0 Threshold Value */ -#define PVP0_THC1_TH3 0xFFC1A52C /* PVP0 Threshold Value */ -#define PVP0_THC0_TH4 0xFFC1A430 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH4 0xFFC1A530 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH5 0xFFC1A434 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH5 0xFFC1A534 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH6 0xFFC1A438 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH6 0xFFC1A538 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH7 0xFFC1A43C /* PVP0 Threshold Value */ -#define PVP0_THC1_TH7 0xFFC1A53C /* PVP0 Threshold Value */ -#define PVP0_THC0_TH8 0xFFC1A440 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH8 0xFFC1A540 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH9 0xFFC1A444 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH9 0xFFC1A544 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH10 0xFFC1A448 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH10 0xFFC1A548 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH11 0xFFC1A44C /* PVP0 Threshold Value */ -#define PVP0_THC1_TH11 0xFFC1A54C /* PVP0 Threshold Value */ -#define PVP0_THC0_TH12 0xFFC1A450 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH12 0xFFC1A550 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH13 0xFFC1A454 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH13 0xFFC1A554 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH14 0xFFC1A458 /* PVP0 Threshold Value */ -#define PVP0_THC1_TH14 0xFFC1A558 /* PVP0 Threshold Value */ -#define PVP0_THC0_TH15 0xFFC1A45C /* PVP0 Threshold Value */ -#define PVP0_THC1_TH15 0xFFC1A55C /* PVP0 Threshold Value */ -#define PVP0_THC0_HHPOS 0xFFC1A460 /* PVP0 Window start X-coordinate */ -#define PVP0_THC1_HHPOS 0xFFC1A560 /* PVP0 Window start X-coordinate */ -#define PVP0_THC0_HVPOS 0xFFC1A464 /* PVP0 Window start Y-coordinate */ -#define PVP0_THC1_HVPOS 0xFFC1A564 /* PVP0 Window start Y-coordinate */ -#define PVP0_THC0_HHCNT 0xFFC1A468 /* PVP0 Window width in X dimension */ -#define PVP0_THC1_HHCNT 0xFFC1A568 /* PVP0 Window width in X dimension */ -#define PVP0_THC0_HVCNT 0xFFC1A46C /* PVP0 Window width in Y dimension */ -#define PVP0_THC1_HVCNT 0xFFC1A56C /* PVP0 Window width in Y dimension */ -#define PVP0_THC0_RHPOS 0xFFC1A470 /* PVP0 Window start X-coordinate */ -#define PVP0_THC1_RHPOS 0xFFC1A570 /* PVP0 Window start X-coordinate */ -#define PVP0_THC0_RVPOS 0xFFC1A474 /* PVP0 Window start Y-coordinate */ -#define PVP0_THC1_RVPOS 0xFFC1A574 /* PVP0 Window start Y-coordinate */ -#define PVP0_THC0_RHCNT 0xFFC1A478 /* PVP0 Window width in X dimension */ -#define PVP0_THC1_RHCNT 0xFFC1A578 /* PVP0 Window width in X dimension */ -#define PVP0_THC0_RVCNT 0xFFC1A47C /* PVP0 Window width in Y dimension */ -#define PVP0_THC1_RVCNT 0xFFC1A57C /* PVP0 Window width in Y dimension */ -#define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */ -#define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */ -#define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */ -#define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */ -#define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */ -#define PVP0_THC0_RREP_STAT 0xFFC1A4C4 /* PVP0 Number of RLE Reports */ -#define PVP0_THC1_RREP_STAT 0xFFC1A5C4 /* PVP0 Number of RLE Reports */ -#define PVP0_PMA_CFG 0xFFC1A600 /* PVP0 PMA Configuration Register */ - -#endif /* _DEF_BF609_H */ diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h deleted file mode 100644 index 3933e912cacd..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h +++ /dev/null @@ -1,3596 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF60X_H -#define _DEF_BF60X_H - - -/* ************************************************************** */ -/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */ -/* ************************************************************** */ - - -/* ========================= - CNT Registers - ========================= */ - -/* ========================= - CNT0 - ========================= */ -#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */ -#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */ -#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */ -#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */ -#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */ -#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */ -#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */ -#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */ - - -/* ========================= - RSI Registers - ========================= */ - -#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */ -#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */ -#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */ -#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */ -#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */ -#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */ -#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */ -#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */ -#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */ -#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */ -#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */ -#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */ -#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */ -#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */ -#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */ -#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */ -#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */ -#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */ -#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */ -#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */ -#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */ -#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */ -#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */ -#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */ -#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */ -#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */ -#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */ -#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */ -#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */ -#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */ -#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */ - -/* ========================= - CAN Registers - ========================= */ - -/* ========================= - CAN0 - ========================= */ -#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */ -#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */ -#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */ -#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */ -#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */ -#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */ -#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */ -#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */ -#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */ -#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */ -#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */ -#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */ -#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */ -#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */ -#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */ -#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */ -#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */ -#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */ -#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */ -#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */ -#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */ -#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */ -#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */ -#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */ -#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */ -#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */ -#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */ -#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */ -#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */ -#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */ -#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */ -#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */ -#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */ -#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */ -#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */ -#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */ -#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */ -#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */ -#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */ -#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */ -#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */ -#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */ -#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */ -#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */ -#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */ -#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */ -#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */ -#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */ -#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */ - -/* ========================= - LINK PORT Registers - ========================= */ -#define LP0_CTL 0xFFC01000 /* LP0 Control Register */ -#define LP0_STAT 0xFFC01004 /* LP0 Status Register */ -#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */ -#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */ -#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */ -#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */ -#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */ -#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */ -#define LP1_CTL 0xFFC01100 /* LP1 Control Register */ -#define LP1_STAT 0xFFC01104 /* LP1 Status Register */ -#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */ -#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */ -#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */ -#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */ -#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */ -#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */ -#define LP2_CTL 0xFFC01200 /* LP2 Control Register */ -#define LP2_STAT 0xFFC01204 /* LP2 Status Register */ -#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */ -#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */ -#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */ -#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */ -#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */ -#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */ -#define LP3_CTL 0xFFC01300 /* LP3 Control Register */ -#define LP3_STAT 0xFFC01304 /* LP3 Status Register */ -#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */ -#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */ -#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */ -#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */ -#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */ -#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */ - -/* ========================= - TIMER Registers - ========================= */ -#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */ -#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */ -#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */ -#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */ -#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */ -#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */ -#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */ -#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */ -#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */ -#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */ -#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */ -#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */ -#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */ -#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */ -#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */ -#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */ -#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */ - -/* ========================= - TIMER0~7 - ========================= */ -#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */ -#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */ -#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */ -#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */ -#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */ - -#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */ -#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */ -#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */ -#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */ -#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */ - -#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */ -#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */ -#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */ -#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */ -#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */ - -#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */ -#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */ -#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */ -#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */ -#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */ - -#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */ -#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */ -#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */ -#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */ -#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */ - -#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */ -#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */ -#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */ -#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */ -#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */ - -#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */ -#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */ -#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */ -#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */ -#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */ - -#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */ -#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */ -#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */ -#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */ -#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */ - -/* ========================= - CRC Registers - ========================= */ - -/* ========================= - CRC0 - ========================= */ -#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */ -#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */ -#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */ -#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */ -#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */ -#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */ -#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */ -#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */ -#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */ -#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */ -#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */ -#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */ -#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */ -#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */ -#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */ - -/* ========================= - CRC1 - ========================= */ -#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */ -#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */ -#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */ -#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */ -#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */ -#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */ -#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */ -#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */ -#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */ -#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */ -#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */ -#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */ -#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */ -#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */ -#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */ - -/* ========================= - TWI Registers - ========================= */ - -/* ========================= - TWI0 - ========================= */ -#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */ -#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */ -#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */ -#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */ -#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */ -#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */ -#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */ - -/* ========================= - TWI1 - ========================= */ -#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */ -#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */ -#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */ -#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */ -#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */ -#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */ -#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */ -#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */ -#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */ -#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */ -#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */ - - -/* ========================= - UART Registers - ========================= */ - -/* ========================= - UART0 - ========================= */ -#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */ -#define UART0_CTL 0xFFC02004 /* UART0 Control Register */ -#define UART0_STAT 0xFFC02008 /* UART0 Status Register */ -#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */ -#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */ -#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */ -#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */ -#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */ -#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */ -#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */ -#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */ -#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */ -#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */ -#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */ -#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */ - -/* ========================= - UART1 - ========================= */ -#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */ -#define UART1_CTL 0xFFC02404 /* UART1 Control Register */ -#define UART1_STAT 0xFFC02408 /* UART1 Status Register */ -#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */ -#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */ -#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */ -#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */ -#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */ -#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */ -#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */ -#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */ -#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */ -#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */ -#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */ -#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */ - - -/* ========================= - PORT Registers - ========================= */ - -/* ========================= - PORTA - ========================= */ -#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */ -#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */ -#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */ -#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */ -#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */ -#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */ -#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */ -#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */ -#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */ -#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */ -#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */ -#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */ -#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */ -#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */ -#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */ -#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */ -#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */ -#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */ -#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */ - -/* ========================= - PORTB - ========================= */ -#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */ -#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */ -#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */ -#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */ -#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */ -#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */ -#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */ -#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */ -#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */ -#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */ -#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */ -#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */ -#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */ -#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */ -#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */ -#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */ -#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */ -#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */ -#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */ - -/* ========================= - PORTC - ========================= */ -#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */ -#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */ -#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */ -#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */ -#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */ -#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */ -#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */ -#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */ -#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */ -#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */ -#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */ -#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */ -#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */ -#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */ -#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */ -#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */ -#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */ -#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */ -#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */ - -/* ========================= - PORTD - ========================= */ -#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */ -#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */ -#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */ -#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */ -#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */ -#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */ -#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */ -#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */ -#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */ -#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */ -#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */ -#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */ -#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */ -#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */ -#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */ -#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */ -#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */ -#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */ -#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */ - -/* ========================= - PORTE - ========================= */ -#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */ -#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */ -#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */ -#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */ -#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */ -#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */ -#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */ -#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */ -#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */ -#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */ -#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */ -#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */ -#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */ -#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */ -#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */ -#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */ -#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */ -#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */ -#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */ - -/* ========================= - PORTF - ========================= */ -#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */ -#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */ -#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */ -#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */ -#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */ -#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */ -#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */ -#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */ -#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */ -#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */ -#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */ -#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */ -#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */ -#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */ -#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */ -#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */ -#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */ -#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */ -#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */ - -/* ========================= - PORTG - ========================= */ -#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */ -#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */ -#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */ -#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */ -#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */ -#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */ -#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */ -#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */ -#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */ -#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */ -#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */ -#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */ -#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */ -#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */ -#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */ -#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */ -#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */ -#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */ -#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */ - -/* ================================================== - Pads Controller Registers - ================================================== */ - -/* ========================= - PADS0 - ========================= */ -#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */ -#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */ -#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */ - -/* ========================= - PINT Registers - ========================= */ - -/* ========================= - PINT0 - ========================= */ -#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */ -#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */ -#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */ -#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */ -#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */ -#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */ -#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */ -#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */ -#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */ -#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */ - -/* ========================= - PINT1 - ========================= */ -#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */ -#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */ -#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */ -#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */ -#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */ -#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */ -#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */ -#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */ -#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */ -#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */ - -/* ========================= - PINT2 - ========================= */ -#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */ -#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */ -#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */ -#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */ -#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */ -#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */ -#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */ -#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */ -#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */ -#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */ - -/* ========================= - PINT3 - ========================= */ -#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */ -#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */ -#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */ -#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */ -#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */ -#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */ -#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */ -#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */ -#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */ -#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */ - -/* ========================= - PINT4 - ========================= */ -#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */ -#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */ -#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */ -#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */ -#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */ -#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */ -#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */ -#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */ -#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */ -#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */ - -/* ========================= - PINT5 - ========================= */ -#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */ -#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */ -#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */ -#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */ -#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */ -#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */ -#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */ -#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */ -#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */ -#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */ - - -/* ========================= - SMC Registers - ========================= */ - -/* ========================= - SMC0 - ========================= */ -#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */ -#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */ -#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */ -#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */ -#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */ -#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */ -#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */ -#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */ -#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */ -#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */ -#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */ -#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */ -#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */ -#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */ - - -/* ========================= - WDOG Registers - ========================= */ - -/* ========================= - WDOG0 - ========================= */ -#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */ -#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */ -#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */ -#define WDOG_CTL WDOG0_CTL -#define WDOG_CNT WDOG0_CNT -#define WDOG_STAT WDOG0_STAT - -/* ========================= - WDOG1 - ========================= */ -#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */ -#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */ -#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */ - - -/* ========================= - SDU Registers - ========================= */ - -/* ========================= - SDU0 - ========================= */ -#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */ -#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */ -#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */ -#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */ -#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */ -#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */ -#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */ -#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */ -#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */ -#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */ -#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */ -#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */ - - -/* ========================= - EMAC Registers - ========================= */ -/* ========================= - EMAC0 - ========================= */ -#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */ -#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */ -#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */ -#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */ -#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */ -#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */ -#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */ -#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */ -#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */ -#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */ -#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */ -#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */ -#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */ -#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */ -#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */ -#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */ -#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */ -#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */ -#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */ -#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */ -#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */ -#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */ -#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */ -#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */ -#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */ -#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */ -#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */ -#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */ -#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */ -#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */ -#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */ -#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */ -#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */ -#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */ -#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */ -#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */ -#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */ -#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */ -#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */ -#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */ -#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */ -#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */ -#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */ -#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */ -#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */ -#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */ -#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */ -#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */ -#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */ -#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */ -#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */ -#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */ -#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */ -#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */ -#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */ -#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */ -#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */ -#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */ -#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */ -#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */ -#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */ -#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */ -#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */ -#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */ -#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */ -#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */ -#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */ -#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */ -#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */ -#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */ -#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */ -#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */ -#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */ -#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */ -#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */ -#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */ -#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */ -#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */ -#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */ -#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */ -#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */ -#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */ -#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */ -#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */ -#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */ -#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */ -#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */ -#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */ -#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */ -#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */ -#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */ -#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */ -#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */ -#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */ -#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */ -#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */ -#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */ -#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */ -#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */ -#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */ -#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */ -#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */ -#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */ -#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */ -#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */ -#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */ -#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */ -#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */ -#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */ -#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */ -#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */ -#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */ -#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */ -#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */ -#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */ -#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */ -#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */ -#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */ -#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */ -#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */ -#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */ -#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */ -#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */ -#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */ -#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */ -#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */ -#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */ -#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */ -#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */ -#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */ -#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */ - -/* ========================= - EMAC1 - ========================= */ -#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */ -#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */ -#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */ -#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */ -#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */ -#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */ -#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */ -#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */ -#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */ -#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */ -#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */ -#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */ -#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */ -#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */ -#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */ -#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */ -#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */ -#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */ -#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */ -#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */ -#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */ -#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */ -#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */ -#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */ -#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */ -#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */ -#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */ -#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */ -#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */ -#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */ -#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */ -#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */ -#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */ -#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */ -#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */ -#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */ -#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */ -#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */ -#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */ -#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */ -#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */ -#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */ -#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */ -#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */ -#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */ -#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */ -#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */ -#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */ -#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */ -#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */ -#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */ -#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */ -#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */ -#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */ -#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */ -#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */ -#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */ -#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */ -#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */ -#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */ -#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */ -#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */ -#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */ -#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */ -#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */ -#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */ -#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */ -#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */ -#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */ -#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */ -#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */ -#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */ -#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */ -#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */ -#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */ -#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */ -#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */ -#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */ -#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */ -#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */ -#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */ -#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */ -#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */ -#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */ -#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */ -#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */ -#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */ -#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */ -#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */ -#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */ -#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */ -#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */ -#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */ -#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */ -#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */ -#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */ -#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */ -#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */ -#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */ -#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */ -#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */ -#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */ -#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */ -#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */ -#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */ -#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */ -#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */ -#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */ -#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */ -#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */ -#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */ -#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */ -#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */ -#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */ -#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */ -#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */ -#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */ -#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */ -#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */ -#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */ -#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */ -#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */ -#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */ -#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */ -#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */ -#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */ -#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */ -#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */ -#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */ -#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */ -#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */ - - -/* ========================= - SPI Registers - ========================= */ - -/* ========================= - SPI0 - ========================= */ -#define SPI0_REGBASE 0xFFC40400 -#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */ -#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */ -#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */ -#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */ -#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */ -#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */ -#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */ -#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */ -#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */ -#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */ -#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */ -#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */ -#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */ -#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */ -#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */ -#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */ -#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */ -#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */ - -/* ========================= - SPI1 - ========================= */ -#define SPI1_REGBASE 0xFFC40500 -#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */ -#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */ -#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */ -#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */ -#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */ -#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */ -#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */ -#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */ -#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */ -#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */ -#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */ -#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */ -#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */ -#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */ -#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */ -#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */ -#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */ -#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */ - -/* ========================= - SPORT Registers - ========================= */ - -/* ========================= - SPORT0 - ========================= */ -#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */ -#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */ -#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */ -#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */ -#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */ -#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */ -#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */ -#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */ -#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */ -#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */ -#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */ -#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */ -#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */ -#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */ -#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */ -#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */ -#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */ -#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */ -#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */ -#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */ -#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */ -#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */ -#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */ -#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */ -#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */ -#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */ -#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */ -#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */ -#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */ -#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */ - -/* ========================= - SPORT1 - ========================= */ -#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */ -#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */ -#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */ -#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */ -#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */ -#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */ -#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */ -#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */ -#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */ -#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */ -#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */ -#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */ -#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */ -#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */ -#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */ -#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */ -#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */ -#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */ -#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */ -#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */ -#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */ -#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */ -#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */ -#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */ -#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */ -#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */ -#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */ -#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */ -#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */ -#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */ - -/* ========================= - SPORT2 - ========================= */ -#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */ -#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */ -#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */ -#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */ -#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */ -#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */ -#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */ -#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */ -#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */ -#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */ -#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */ -#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */ -#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */ -#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */ -#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */ -#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */ -#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */ -#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */ -#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */ -#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */ -#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */ -#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */ -#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */ -#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */ -#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */ -#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */ -#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */ -#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */ -#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */ -#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */ - -/* ========================= - EPPI Registers - ========================= */ - -/* ========================= - EPPI0 - ========================= */ -#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */ -#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */ -#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */ -#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */ -#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */ -#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */ -#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */ -#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */ -#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */ -#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */ -#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */ -#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */ -#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */ -#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */ - -/* ========================= - EPPI1 - ========================= */ -#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */ -#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */ -#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */ -#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */ -#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */ -#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */ -#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */ -#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */ -#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */ -#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */ -#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */ -#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */ -#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */ -#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */ -#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */ -#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */ -#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */ -#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */ -#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */ - -/* ========================= - EPPI2 - ========================= */ -#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */ -#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */ -#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */ -#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */ -#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */ -#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */ -#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */ -#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */ -#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */ -#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */ -#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */ -#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */ -#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */ -#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */ -#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */ -#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */ -#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */ -#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */ -#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */ - - - -/* ========================= - DDE Registers - ========================= */ - -/* ========================= - DMA0 - ========================= */ -#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */ -#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */ -#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */ -#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */ -#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */ -#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */ -#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */ -#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */ -#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */ -#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */ -#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */ -#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */ -#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */ -#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */ -#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */ - -/* ========================= - DMA1 - ========================= */ -#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */ -#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */ -#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */ -#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */ -#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */ -#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */ -#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */ -#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */ -#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */ -#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */ -#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */ -#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */ -#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */ -#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */ -#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */ - -/* ========================= - DMA2 - ========================= */ -#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */ -#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */ -#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */ -#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */ -#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */ -#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */ -#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */ -#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */ -#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */ -#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */ -#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */ -#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */ -#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */ -#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */ -#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */ - -/* ========================= - DMA3 - ========================= */ -#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */ -#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */ -#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */ -#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */ -#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */ -#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */ -#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */ -#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */ -#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */ -#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */ -#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */ -#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */ -#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */ -#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */ -#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */ - -/* ========================= - DMA4 - ========================= */ -#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */ -#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */ -#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */ -#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */ -#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */ -#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */ -#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */ -#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */ -#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */ -#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */ -#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */ -#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */ -#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */ -#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */ -#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */ - -/* ========================= - DMA5 - ========================= */ -#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */ -#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */ -#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */ -#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */ -#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */ -#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */ -#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */ -#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */ -#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */ -#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */ -#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */ -#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */ -#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */ -#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */ -#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */ - -/* ========================= - DMA6 - ========================= */ -#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */ -#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */ -#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */ -#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */ -#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */ -#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */ -#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */ -#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */ -#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */ -#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */ -#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */ -#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */ -#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */ -#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */ -#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */ - -/* ========================= - DMA7 - ========================= */ -#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */ -#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */ -#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */ -#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */ -#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */ -#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */ -#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */ -#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */ -#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */ -#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */ -#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */ -#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */ -#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */ -#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */ -#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */ - -/* ========================= - DMA8 - ========================= */ -#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */ -#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */ -#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */ -#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */ -#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */ -#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */ -#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */ -#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */ -#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */ -#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */ -#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */ -#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */ -#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */ -#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */ -#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */ - -/* ========================= - DMA9 - ========================= */ -#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */ -#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */ -#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */ -#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */ -#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */ -#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */ -#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */ -#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */ -#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */ -#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */ -#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */ -#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */ -#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */ -#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */ -#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */ - -/* ========================= - DMA10 - ========================= */ -#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */ -#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */ -#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */ -#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */ -#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */ -#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */ -#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */ -#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */ -#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */ -#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */ -#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */ -#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */ -#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */ -#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */ -#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */ - -/* ========================= - DMA11 - ========================= */ -#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */ -#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */ -#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */ -#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */ -#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */ -#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */ -#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */ -#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */ -#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */ -#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */ -#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */ -#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */ -#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */ -#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */ -#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */ - -/* ========================= - DMA12 - ========================= */ -#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */ -#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */ -#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */ -#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */ -#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */ -#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */ -#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */ -#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */ -#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */ -#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */ -#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */ -#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */ -#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */ -#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */ -#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */ - -/* ========================= - DMA13 - ========================= */ -#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */ -#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */ -#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */ -#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */ -#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */ -#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */ -#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */ -#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */ -#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */ -#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */ -#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */ -#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */ -#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */ -#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */ -#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */ - -/* ========================= - DMA14 - ========================= */ -#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */ -#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */ -#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */ -#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */ -#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */ -#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */ -#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */ -#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */ -#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */ -#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */ -#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */ -#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */ -#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */ -#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */ -#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */ - -/* ========================= - DMA15 - ========================= */ -#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */ -#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */ -#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */ -#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */ -#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */ -#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */ -#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */ -#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */ -#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */ -#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */ -#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */ -#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */ -#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */ -#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */ -#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */ - -/* ========================= - DMA16 - ========================= */ -#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */ -#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */ -#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */ -#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */ -#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */ -#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */ -#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */ -#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */ -#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */ -#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */ -#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */ -#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */ -#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */ -#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */ -#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */ - -/* ========================= - DMA17 - ========================= */ -#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */ -#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */ -#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */ -#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */ -#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */ -#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */ -#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */ -#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */ -#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */ -#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */ -#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */ -#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */ -#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */ -#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */ -#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */ - -/* ========================= - DMA18 - ========================= */ -#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */ -#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */ -#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */ -#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */ -#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */ -#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */ -#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */ -#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */ -#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */ -#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */ -#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */ -#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */ -#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */ -#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */ -#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */ - -/* ========================= - DMA19 - ========================= */ -#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */ -#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */ -#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */ -#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */ -#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */ -#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */ -#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */ -#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */ -#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */ -#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */ -#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */ -#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */ -#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */ -#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */ -#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */ - -/* ========================= - DMA20 - ========================= */ -#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */ -#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */ -#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */ -#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */ -#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */ -#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */ -#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */ -#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */ -#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */ -#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */ -#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */ -#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */ -#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */ -#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */ -#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */ -#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */ - -/* ========================= - DMA21 - ========================= */ -#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */ -#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */ -#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */ -#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */ -#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */ -#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */ -#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */ -#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */ -#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */ -#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */ -#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */ -#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */ -#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */ -#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */ -#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */ -#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */ - -/* ========================= - DMA22 - ========================= */ -#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */ -#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */ -#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */ -#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */ -#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */ -#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */ -#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */ -#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */ -#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */ -#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */ -#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */ -#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */ -#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */ -#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */ -#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */ -#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */ - -/* ========================= - DMA23 - ========================= */ -#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */ -#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */ -#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */ -#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */ -#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */ -#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */ -#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */ -#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */ -#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */ -#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */ -#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */ -#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */ -#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */ -#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */ -#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */ -#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */ - -/* ========================= - DMA24 - ========================= */ -#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */ -#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */ -#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */ -#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */ -#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */ -#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */ -#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */ -#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */ -#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */ -#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */ -#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */ -#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */ -#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */ -#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */ -#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */ -#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */ - -/* ========================= - DMA25 - ========================= */ -#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */ -#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */ -#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */ -#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */ -#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */ -#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */ -#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */ -#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */ -#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */ -#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */ -#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */ -#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */ -#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */ -#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */ -#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */ -#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */ - -/* ========================= - DMA26 - ========================= */ -#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */ -#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */ -#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */ -#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */ -#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */ -#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */ -#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */ -#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */ -#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */ -#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */ -#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */ -#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */ -#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */ -#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */ -#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */ -#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */ - -/* ========================= - DMA27 - ========================= */ -#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */ -#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */ -#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */ -#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */ -#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */ -#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */ -#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */ -#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */ -#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */ -#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */ -#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */ -#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */ -#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */ -#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */ -#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */ -#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */ - -/* ========================= - DMA28 - ========================= */ -#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */ -#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */ -#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */ -#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */ -#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */ -#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */ -#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */ -#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */ -#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */ -#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */ -#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */ -#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */ -#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */ -#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */ -#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */ -#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */ - -/* ========================= - DMA29 - ========================= */ -#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */ -#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */ -#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */ -#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */ -#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */ -#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */ -#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */ -#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */ -#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */ -#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */ -#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */ -#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */ -#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */ -#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */ -#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */ -#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */ - -/* ========================= - DMA30 - ========================= */ -#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */ -#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */ -#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */ -#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */ -#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */ -#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */ -#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */ -#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */ -#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */ -#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */ -#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */ -#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */ -#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */ -#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */ -#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */ -#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */ - -/* ========================= - DMA31 - ========================= */ -#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */ -#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */ -#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */ -#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */ -#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */ -#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */ -#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */ -#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */ -#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */ -#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */ -#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */ -#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */ -#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */ -#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */ -#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */ -#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */ - -/* ========================= - DMA32 - ========================= */ -#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */ -#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */ -#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */ -#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */ -#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */ -#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */ -#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */ -#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */ -#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */ -#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */ -#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */ -#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */ -#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */ -#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */ -#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */ -#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */ - -/* ========================= - DMA33 - ========================= */ -#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */ -#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */ -#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */ -#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */ -#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */ -#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */ -#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */ -#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */ -#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */ -#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */ -#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */ -#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */ -#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */ -#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */ -#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */ -#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */ - -/* ========================= - DMA34 - ========================= */ -#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */ -#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */ -#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */ -#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */ -#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */ -#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */ -#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */ -#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */ -#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */ -#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */ -#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */ -#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */ -#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */ -#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */ -#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */ -#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */ - -/* ========================= - DMA35 - ========================= */ -#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */ -#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */ -#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */ -#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */ -#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */ -#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */ -#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */ -#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */ -#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */ -#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */ -#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */ -#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */ -#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */ -#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */ -#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */ -#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */ - -/* ========================= - DMA36 - ========================= */ -#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */ -#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */ -#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */ -#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */ -#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */ -#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */ -#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */ -#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */ -#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */ -#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */ -#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */ -#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */ -#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */ -#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */ -#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */ -#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */ - -/* ========================= - DMA37 - ========================= */ -#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */ -#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */ -#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */ -#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */ -#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */ -#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */ -#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */ -#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */ -#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */ -#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */ -#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */ -#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */ -#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */ -#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */ -#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */ -#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */ - -/* ========================= - DMA38 - ========================= */ -#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */ -#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */ -#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */ -#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */ -#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */ -#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */ -#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */ -#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */ -#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */ -#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */ -#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */ -#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */ -#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */ -#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */ -#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */ -#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */ - -/* ========================= - DMA39 - ========================= */ -#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */ -#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */ -#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */ -#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */ -#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */ -#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */ -#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */ -#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */ -#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */ -#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */ -#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */ -#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */ -#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */ -#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */ -#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */ -#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */ - -/* ========================= - DMA40 - ========================= */ -#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */ -#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */ -#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */ -#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */ -#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */ -#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */ -#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */ -#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */ -#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */ -#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */ -#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */ -#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */ -#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */ -#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */ -#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */ -#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */ - -/* ========================= - DMA41 - ========================= */ -#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */ -#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */ -#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */ -#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */ -#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */ -#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */ -#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */ -#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */ -#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */ -#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */ -#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */ -#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */ -#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */ -#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */ -#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */ -#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */ - -/* ========================= - DMA42 - ========================= */ -#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */ -#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */ -#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */ -#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */ -#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */ -#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */ -#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */ -#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */ -#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */ -#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */ -#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */ -#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */ -#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */ -#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */ -#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */ -#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */ - -/* ========================= - DMA43 - ========================= */ -#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */ -#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */ -#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */ -#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */ -#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */ -#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */ -#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */ -#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */ -#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */ -#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */ -#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */ -#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */ -#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */ -#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */ -#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */ -#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */ - -/* ========================= - DMA44 - ========================= */ -#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */ -#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */ -#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */ -#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */ -#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */ -#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */ -#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */ -#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */ -#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */ -#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */ -#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */ -#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */ -#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */ -#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */ -#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */ -#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */ - -/* ========================= - DMA45 - ========================= */ -#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */ -#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */ -#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */ -#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */ -#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */ -#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */ -#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */ -#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */ -#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */ -#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */ -#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */ -#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */ -#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */ -#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */ -#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */ -#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */ - -/* ========================= - DMA46 - ========================= */ -#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */ -#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */ -#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */ -#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */ -#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */ -#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */ -#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */ -#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */ -#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */ -#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */ -#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */ -#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */ -#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */ -#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */ -#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */ -#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */ -#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */ - - -/******************************************************************************** - DMA Alias Definitions - ********************************************************************************/ -#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR) -#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR) -#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG) -#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT) -#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY) -#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT) -#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY) -#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR) -#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR) -#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR) -#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS) -#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT) -#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT) -#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT) -#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT) -#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT) -#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT) -#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR) -#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR) -#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG) -#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT) -#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY) -#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT) -#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY) -#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR) -#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR) -#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR) -#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS) -#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT) -#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT) -#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT) -#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT) -#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT) -#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT) -#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR) -#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR) -#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG) -#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT) -#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY) -#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT) -#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY) -#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR) -#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR) -#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR) -#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS) -#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT) -#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT) -#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT) -#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT) -#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT) -#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT) -#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR) -#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR) -#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG) -#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT) -#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY) -#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT) -#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY) -#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR) -#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR) -#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR) -#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS) -#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT) -#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT) -#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT) -#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT) -#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT) -#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT) -#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR) -#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR) -#define MDMA2_DEST_CONFIG (DMA26_CONFIG) -#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT) -#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY) -#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT) -#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY) -#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR) -#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR) -#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR) -#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS) -#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT) -#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT) -#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT) -#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT) -#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT) -#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT) -#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR) -#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR) -#define MDMA2_SRC_CONFIG (DMA25_CONFIG) -#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT) -#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY) -#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT) -#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY) -#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR) -#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR) -#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR) -#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS) -#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT) -#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT) -#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT) -#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT) -#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT) -#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT) -#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR) -#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR) -#define MDMA3_DEST_CONFIG (DMA28_CONFIG) -#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT) -#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY) -#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT) -#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY) -#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR) -#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR) -#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR) -#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS) -#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT) -#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT) -#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT) -#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT) -#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT) -#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT) -#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR) -#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR) -#define MDMA3_SRC_CONFIG (DMA27_CONFIG) -#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT) -#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY) -#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT) -#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY) -#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR) -#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR) -#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR) -#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS) -#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT) -#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT) -#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT) -#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT) -#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT) -#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT) - - -/* ========================= - DMC Registers - ========================= */ - -/* ========================= - DMC0 - ========================= */ -#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */ -#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */ -#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */ -#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */ -#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */ -#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */ -#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */ -#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */ -#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */ -#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */ -#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */ -#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */ -#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */ -#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */ -#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */ -#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */ -#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */ - -#define DEVSZ_64 0x000 /* DMC External Bank Size = 64Mbit */ -#define DEVSZ_128 0x100 /* DMC External Bank Size = 128Mbit */ -#define DEVSZ_256 0x200 /* DMC External Bank Size = 256Mbit */ -#define DEVSZ_512 0x300 /* DMC External Bank Size = 512Mbit */ -#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */ -#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */ - -/* ========================= - L2CTL Registers - ========================= */ - -/* ========================= - L2CTL0 - ========================= */ -#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */ -#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */ -#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */ -#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */ -#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */ -#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */ -#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */ -#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Register */ -#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */ -#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */ -#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */ -#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */ -#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */ -#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */ -#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */ -#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */ -#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */ -#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */ -#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */ -#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */ - - -/* ========================= - SEC Registers - ========================= */ -/* ------------------------------------------------------------------------------------------------------------------------ - SEC Core Interface (SCI) Register Definitions - ------------------------------------------------------------------------------------------------------------------------ */ - -#define SEC_SCI_BASE 0xFFCA4400 -#define SEC_SCI_OFF 0x40 -#define SEC_CCTL 0x0 /* SEC Core Control Register n */ -#define SEC_CSTAT 0x4 /* SEC Core Status Register n */ -#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */ -#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */ -#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */ -#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */ -#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */ -#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */ - -#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg) -#define bfin_write_SEC_SCI(n, reg, val) \ - bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val) - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC Fault Management Interface (SFI) Register Definitions - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */ -#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */ -#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */ -#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */ -#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */ -#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */ -#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */ -#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */ -#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */ -#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC Global Register Definitions - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */ -#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */ -#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */ -#define SEC_END 0xFFCA400C /* SEC Global End Register */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC Source Interface (SSI) Register Definitions - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */ -#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */ -#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */ -#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CCTL Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */ -#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */ -#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */ -#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */ -#define SEC_CCTL_EN 0x00000001 /* EN: Enable */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CSTAT Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */ -#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */ -#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */ -#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */ -#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */ -#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */ -#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */ -#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CPND Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */ -#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CACT Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */ -#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CPMSK Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */ -#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CGMSK Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */ -#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */ -#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CPLVL Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */ -#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_CSID Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_CSID_SID 0x000000FF /* Source ID */ - - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_FCTL Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */ -#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */ -#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */ -#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */ -#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */ -#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */ -#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */ -#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */ -#define SEC_FCTL_EN 0x00000001 /* EN: Enable */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_FSTAT Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */ -#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */ -#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */ -#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */ -#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */ -#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_FSID Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */ -#define SEC_FSID_SID 0x000000FF /* Source ID */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_FEND Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */ -#define SEC_FEND_SID 0x000000FF /* Source ID */ - - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_GCTL Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_GCTL_LOCK 0x80000000 /* Lock */ -#define SEC_GCTL_RESET 0x00000002 /* Reset */ -#define SEC_GCTL_EN 0x00000001 /* Enable */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_GSTAT Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */ -#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */ -#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */ -#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */ -#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */ -#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */ -#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */ -#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_RAISE Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_END Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */ - - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_SCTL Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_SCTL_LOCK 0x80000000 /* Lock */ -#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */ -#define SEC_SCTL_GRP 0x000F0000 /* Group Select */ -#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */ -#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */ -#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */ -#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */ -#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */ -#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */ - -/* ------------------------------------------------------------------------------------------------------------------------ - SEC_SSTAT Pos/Masks Description - ------------------------------------------------------------------------------------------------------------------------ */ -#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */ -#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */ -#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */ -#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */ -#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */ -#define SEC_SSTAT_ERR 0x00000002 /* Error */ - - -/* ========================= - RCU Registers - ========================= */ - -/* ========================= - RCU0 - ========================= */ -#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */ -#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */ -#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */ -#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */ -#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */ -#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */ -#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */ -#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */ -#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */ -#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */ - - -/* ========================= - CGU0 - ========================= */ -#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */ -#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */ -#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */ -#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */ - - -/* ========================= - DPM Registers - ========================= */ - -/* ========================= - DPM0 - ========================= */ -#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */ -#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */ -#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */ -#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */ -#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */ -#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */ -#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */ -#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */ -#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */ -#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */ -#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */ -#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */ -#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */ -#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */ -#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */ -#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */ -#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */ -#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */ -#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */ -#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */ -#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */ -#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */ -#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */ -#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */ -#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */ -#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */ -#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */ -#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */ - - -/* ========================= - DBG Registers - ========================= */ - -/* USB register */ -#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */ -#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */ -#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */ -#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */ -#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */ -#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */ -#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */ -#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */ -#define USB_FRAME 0xFFCC100C /* USB Frame Number */ -#define USB_INDEX 0xFFCC100E /* USB Index */ -#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */ -#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */ -#define USB_EP_NI0_TXMAXP 0xFFCC1010 -#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */ -#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */ -#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */ -#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */ -#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */ -#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */ -#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */ -#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */ -#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */ -#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */ -#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */ -#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */ -#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */ -#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */ -#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */ -#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */ -#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */ -#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */ -#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */ -#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */ -#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */ -#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */ -#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */ -#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */ -#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */ -#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */ -#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */ -#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */ -#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */ -#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */ -#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */ -#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */ -#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */ -#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */ -#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */ -#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */ -#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */ -#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */ -#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */ -#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */ -#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */ -#define USB_EP0_FIFO 0xFFCC1020 -#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */ -#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */ -#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */ -#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */ -#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */ -#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */ -#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */ -#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */ -#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */ -#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */ -#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */ -#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */ -#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */ -#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */ -#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */ -#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */ -#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */ -#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */ -#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */ -#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */ -#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */ -#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */ -#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */ -#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */ -#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */ -#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */ -#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */ -#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */ -#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */ -#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */ -#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */ -#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */ -#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */ -#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */ -#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */ -#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */ -#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */ -#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */ -#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */ -#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */ -#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */ -#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */ -#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */ -#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */ -#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */ -#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */ -#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */ -#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */ -#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */ -#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */ -#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */ -#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */ -#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */ -#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */ -#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */ -#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */ -#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */ -#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */ -#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */ -#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */ -#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */ -#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */ -#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */ -#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */ -#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */ -#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */ -#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */ -#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */ -#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */ -#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */ -#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */ -#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */ -#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */ -#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */ -#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */ -#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */ -#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */ -#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */ -#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */ -#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */ -#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */ -#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */ -#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */ -#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */ -#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */ -#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */ -#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */ -#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */ -#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */ -#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */ -#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */ -#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */ -#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */ -#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */ -#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */ -#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */ -#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */ -#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */ -#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */ -#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */ -#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */ -#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */ -#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */ -#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */ -#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */ -#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */ -#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */ -#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */ -#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */ -#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */ -#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */ -#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */ -#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */ -#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */ -#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */ -#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */ -#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */ -#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */ -#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */ -#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */ -#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */ -#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */ -#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */ -#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */ -#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */ -#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */ -#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */ -#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */ -#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */ -#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */ -#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */ -#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */ -#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */ -#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */ -#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */ -#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */ -#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */ -#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */ -#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */ -#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */ -#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */ -#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */ -#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */ -#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */ -#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */ -#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */ -#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */ -#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */ -#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */ -#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */ -#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */ -#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */ -#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */ -#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */ -#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */ -#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */ -#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */ -#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */ -#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */ -#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */ -#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */ -#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */ -#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */ -#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */ -#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */ -#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */ -#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */ -#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */ -#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */ -#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */ -#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */ -#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */ -#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */ -#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */ -#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */ -#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */ -#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */ -#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */ -#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */ -#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */ -#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */ -#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */ -#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */ -#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */ -#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */ - - - -/* ========================= - CHIPID - ========================= */ - -#define CHIPID 0xffc00014 -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - - -#endif /* _DEF_BF60X_H */ diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h deleted file mode 100644 index 872d141ca119..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/dma.h +++ /dev/null @@ -1,116 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define CH_SPORT0_TX 0 -#define CH_SPORT0_RX 1 -#define CH_SPORT1_TX 2 -#define CH_SPORT1_RX 3 -#define CH_SPORT2_TX 4 -#define CH_SPORT2_RX 5 -#define CH_SPI0_TX 6 -#define CH_SPI0_RX 7 -#define CH_SPI1_TX 8 -#define CH_SPI1_RX 9 -#define CH_RSI 10 -#define CH_SDU 11 -#define CH_LP0 13 -#define CH_LP1 14 -#define CH_LP2 15 -#define CH_LP3 16 -#define CH_UART0_TX 17 -#define CH_UART0_RX 18 -#define CH_UART1_TX 19 -#define CH_UART1_RX 20 -#define CH_MEM_STREAM0_SRC_CRC0 21 -#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0 -#define CH_MEM_STREAM0_DEST_CRC0 22 -#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0 -#define CH_MEM_STREAM1_SRC_CRC1 23 -#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1 -#define CH_MEM_STREAM1_DEST_CRC1 24 -#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1 -#define CH_MEM_STREAM2_SRC 25 -#define CH_MEM_STREAM2_DEST 26 -#define CH_MEM_STREAM3_SRC 27 -#define CH_MEM_STREAM3_DEST 28 -#define CH_EPPI0_CH0 29 -#define CH_EPPI0_CH1 30 -#define CH_EPPI1_CH0 31 -#define CH_EPPI1_CH1 32 -#define CH_EPPI2_CH0 33 -#define CH_EPPI2_CH1 34 -#define CH_PIXC_CH0 35 -#define CH_PIXC_CH1 36 -#define CH_PIXC_CH2 37 -#define CH_PVP_CPDOB 38 -#define CH_PVP_CPDOC 39 -#define CH_PVP_CPSTAT 40 -#define CH_PVP_CPCI 41 -#define CH_PVP_MPDO 42 -#define CH_PVP_MPDI 43 -#define CH_PVP_MPSTAT 44 -#define CH_PVP_MPCI 45 -#define CH_PVP_CPDOA 46 - -#define MAX_DMA_CHANNELS 47 -#define MAX_DMA_SUSPEND_CHANNELS 0 -#define DMA_MMR_SIZE_32 - -#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG -#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG -#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS -#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS -#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR -#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT -#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY -#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT -#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY -#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG -#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG -#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS -#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS -#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR -#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT -#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY -#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT -#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY - -#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG -#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG -#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG -#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG -#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS -#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS - -#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG -#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG -#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS -#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS -#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR -#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT -#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY -#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT -#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY -#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG -#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG -#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS -#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS -#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR -#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT -#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY -#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT -#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY - -#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR -#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR -#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR -#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR - -#endif diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h deleted file mode 100644 index 07182513e794..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/gpio.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 112 - -#define GPIO_PA0 0 -#define GPIO_PA1 1 -#define GPIO_PA2 2 -#define GPIO_PA3 3 -#define GPIO_PA4 4 -#define GPIO_PA5 5 -#define GPIO_PA6 6 -#define GPIO_PA7 7 -#define GPIO_PA8 8 -#define GPIO_PA9 9 -#define GPIO_PA10 10 -#define GPIO_PA11 11 -#define GPIO_PA12 12 -#define GPIO_PA13 13 -#define GPIO_PA14 14 -#define GPIO_PA15 15 -#define GPIO_PB0 16 -#define GPIO_PB1 17 -#define GPIO_PB2 18 -#define GPIO_PB3 19 -#define GPIO_PB4 20 -#define GPIO_PB5 21 -#define GPIO_PB6 22 -#define GPIO_PB7 23 -#define GPIO_PB8 24 -#define GPIO_PB9 25 -#define GPIO_PB10 26 -#define GPIO_PB11 27 -#define GPIO_PB12 28 -#define GPIO_PB13 29 -#define GPIO_PB14 30 -#define GPIO_PB15 31 -#define GPIO_PC0 32 -#define GPIO_PC1 33 -#define GPIO_PC2 34 -#define GPIO_PC3 35 -#define GPIO_PC4 36 -#define GPIO_PC5 37 -#define GPIO_PC6 38 -#define GPIO_PC7 39 -#define GPIO_PC8 40 -#define GPIO_PC9 41 -#define GPIO_PC10 42 -#define GPIO_PC11 43 -#define GPIO_PC12 44 -#define GPIO_PC13 45 -#define GPIO_PC14 46 -#define GPIO_PC15 47 -#define GPIO_PD0 48 -#define GPIO_PD1 49 -#define GPIO_PD2 50 -#define GPIO_PD3 51 -#define GPIO_PD4 52 -#define GPIO_PD5 53 -#define GPIO_PD6 54 -#define GPIO_PD7 55 -#define GPIO_PD8 56 -#define GPIO_PD9 57 -#define GPIO_PD10 58 -#define GPIO_PD11 59 -#define GPIO_PD12 60 -#define GPIO_PD13 61 -#define GPIO_PD14 62 -#define GPIO_PD15 63 -#define GPIO_PE0 64 -#define GPIO_PE1 65 -#define GPIO_PE2 66 -#define GPIO_PE3 67 -#define GPIO_PE4 68 -#define GPIO_PE5 69 -#define GPIO_PE6 70 -#define GPIO_PE7 71 -#define GPIO_PE8 72 -#define GPIO_PE9 73 -#define GPIO_PE10 74 -#define GPIO_PE11 75 -#define GPIO_PE12 76 -#define GPIO_PE13 77 -#define GPIO_PE14 78 -#define GPIO_PE15 79 -#define GPIO_PF0 80 -#define GPIO_PF1 81 -#define GPIO_PF2 82 -#define GPIO_PF3 83 -#define GPIO_PF4 84 -#define GPIO_PF5 85 -#define GPIO_PF6 86 -#define GPIO_PF7 87 -#define GPIO_PF8 88 -#define GPIO_PF9 89 -#define GPIO_PF10 90 -#define GPIO_PF11 91 -#define GPIO_PF12 92 -#define GPIO_PF13 93 -#define GPIO_PF14 94 -#define GPIO_PF15 95 -#define GPIO_PG0 96 -#define GPIO_PG1 97 -#define GPIO_PG2 98 -#define GPIO_PG3 99 -#define GPIO_PG4 100 -#define GPIO_PG5 101 -#define GPIO_PG6 102 -#define GPIO_PG7 103 -#define GPIO_PG8 104 -#define GPIO_PG9 105 -#define GPIO_PG10 106 -#define GPIO_PG11 107 -#define GPIO_PG12 108 -#define GPIO_PG13 109 -#define GPIO_PG14 110 -#define GPIO_PG15 111 - - -#define BFIN_GPIO_PINT 1 -#define NR_PINT_SYS_IRQS 6 -#define NR_PINTS 112 - - -#ifndef __ASSEMBLY__ - -struct gpio_port_t { - unsigned long port_fer; - unsigned long port_fer_set; - unsigned long port_fer_clear; - unsigned long data; - unsigned long data_set; - unsigned long data_clear; - unsigned long dir; - unsigned long dir_set; - unsigned long dir_clear; - unsigned long inen; - unsigned long inen_set; - unsigned long inen_clear; - unsigned long port_mux; - unsigned long toggle; - unsigned long polar; - unsigned long polar_set; - unsigned long polar_clear; - unsigned long lock; - unsigned long spare; - unsigned long revid; -}; - -#endif - -#include -#include -#include -#include -#include -#include -#include - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h deleted file mode 100644 index d1cb6a86f80a..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/irq.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BF60x_IRQ_H_ -#define _BF60x_IRQ_H_ - -#include - -#define NR_PERI_INTS (5 * 32) - -#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */ -#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */ -#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */ -#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */ -#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */ -#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */ -#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */ -#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */ -#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */ -#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */ -#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */ -#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */ -#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1) - -#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */ -#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */ -#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */ -#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */ -#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */ -#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */ -#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */ -#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */ -#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */ -#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */ -#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */ -#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */ -#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */ -#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */ -#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */ -#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */ -#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */ -#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */ -#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */ -#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */ -#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */ -#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */ -#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */ -#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */ -#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */ -#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */ -#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */ -#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */ -#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */ -#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */ -#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */ -#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */ -#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */ -#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */ -#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */ -#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */ -#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */ -#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */ -#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */ -#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */ -#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */ -#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */ -#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */ -#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */ -#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */ -#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */ -#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */ -#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */ -#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */ -#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */ -#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */ -#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */ -#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */ -/* -- RESERVED -- 65 DMA12 Data (Reserved) */ -/* -- RESERVED -- 66 Reserved */ -/* -- RESERVED -- 67 Reserved */ -#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */ -/* -- RESERVED -- 69 EMAC0 Power (Reserved) */ -#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */ -/* -- RESERVED -- 71 EMAC1 Power (Reserved) */ -#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */ -#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */ -#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */ -#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */ -#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */ -#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */ -#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */ -#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */ -#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */ -#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */ -#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */ -#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */ -#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */ -#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */ -#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */ -#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */ -#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0 -#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */ -#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */ -#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */ -#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */ -#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1 -#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */ -#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */ -#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */ -#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */ -#define IRQ_MDMAS2 IRQ_MDMA2_DEST -#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */ -#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */ -#define IRQ_MDMAS3 IRQ_MDMA3_DEST -#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */ -#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */ -#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */ -#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */ -#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */ -#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */ -#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */ -#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */ -#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */ -#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */ -#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */ -#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */ -#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */ -#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */ -#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */ -#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */ -#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */ -#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */ -#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */ -#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */ -#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */ -#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */ -#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */ -#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */ -#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */ -#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */ -#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */ -#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */ -#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */ -#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */ -#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */ -#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */ -/* -- RESERVED -- 130 Reserved */ -#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */ -/* -- RESERVED -- 132 Reserved */ -#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */ -#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */ -#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */ -#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */ -#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */ -#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */ -#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */ - -#define SYS_IRQS IRQ_SWU6 - -#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) -#define IRQ_PA0 BFIN_PA_IRQ(0) -#define IRQ_PA1 BFIN_PA_IRQ(1) -#define IRQ_PA2 BFIN_PA_IRQ(2) -#define IRQ_PA3 BFIN_PA_IRQ(3) -#define IRQ_PA4 BFIN_PA_IRQ(4) -#define IRQ_PA5 BFIN_PA_IRQ(5) -#define IRQ_PA6 BFIN_PA_IRQ(6) -#define IRQ_PA7 BFIN_PA_IRQ(7) -#define IRQ_PA8 BFIN_PA_IRQ(8) -#define IRQ_PA9 BFIN_PA_IRQ(9) -#define IRQ_PA10 BFIN_PA_IRQ(10) -#define IRQ_PA11 BFIN_PA_IRQ(11) -#define IRQ_PA12 BFIN_PA_IRQ(12) -#define IRQ_PA13 BFIN_PA_IRQ(13) -#define IRQ_PA14 BFIN_PA_IRQ(14) -#define IRQ_PA15 BFIN_PA_IRQ(15) - -#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) -#define IRQ_PB0 BFIN_PB_IRQ(0) -#define IRQ_PB1 BFIN_PB_IRQ(1) -#define IRQ_PB2 BFIN_PB_IRQ(2) -#define IRQ_PB3 BFIN_PB_IRQ(3) -#define IRQ_PB4 BFIN_PB_IRQ(4) -#define IRQ_PB5 BFIN_PB_IRQ(5) -#define IRQ_PB6 BFIN_PB_IRQ(6) -#define IRQ_PB7 BFIN_PB_IRQ(7) -#define IRQ_PB8 BFIN_PB_IRQ(8) -#define IRQ_PB9 BFIN_PB_IRQ(9) -#define IRQ_PB10 BFIN_PB_IRQ(10) -#define IRQ_PB11 BFIN_PB_IRQ(11) -#define IRQ_PB12 BFIN_PB_IRQ(12) -#define IRQ_PB13 BFIN_PB_IRQ(13) -#define IRQ_PB14 BFIN_PB_IRQ(14) -#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ - -#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) -#define IRQ_PC0 BFIN_PC_IRQ(0) -#define IRQ_PC1 BFIN_PC_IRQ(1) -#define IRQ_PC2 BFIN_PC_IRQ(2) -#define IRQ_PC3 BFIN_PC_IRQ(3) -#define IRQ_PC4 BFIN_PC_IRQ(4) -#define IRQ_PC5 BFIN_PC_IRQ(5) -#define IRQ_PC6 BFIN_PC_IRQ(6) -#define IRQ_PC7 BFIN_PC_IRQ(7) -#define IRQ_PC8 BFIN_PC_IRQ(8) -#define IRQ_PC9 BFIN_PC_IRQ(9) -#define IRQ_PC10 BFIN_PC_IRQ(10) -#define IRQ_PC11 BFIN_PC_IRQ(11) -#define IRQ_PC12 BFIN_PC_IRQ(12) -#define IRQ_PC13 BFIN_PC_IRQ(13) -#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ -#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ - -#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) -#define IRQ_PD0 BFIN_PD_IRQ(0) -#define IRQ_PD1 BFIN_PD_IRQ(1) -#define IRQ_PD2 BFIN_PD_IRQ(2) -#define IRQ_PD3 BFIN_PD_IRQ(3) -#define IRQ_PD4 BFIN_PD_IRQ(4) -#define IRQ_PD5 BFIN_PD_IRQ(5) -#define IRQ_PD6 BFIN_PD_IRQ(6) -#define IRQ_PD7 BFIN_PD_IRQ(7) -#define IRQ_PD8 BFIN_PD_IRQ(8) -#define IRQ_PD9 BFIN_PD_IRQ(9) -#define IRQ_PD10 BFIN_PD_IRQ(10) -#define IRQ_PD11 BFIN_PD_IRQ(11) -#define IRQ_PD12 BFIN_PD_IRQ(12) -#define IRQ_PD13 BFIN_PD_IRQ(13) -#define IRQ_PD14 BFIN_PD_IRQ(14) -#define IRQ_PD15 BFIN_PD_IRQ(15) - -#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) -#define IRQ_PE0 BFIN_PE_IRQ(0) -#define IRQ_PE1 BFIN_PE_IRQ(1) -#define IRQ_PE2 BFIN_PE_IRQ(2) -#define IRQ_PE3 BFIN_PE_IRQ(3) -#define IRQ_PE4 BFIN_PE_IRQ(4) -#define IRQ_PE5 BFIN_PE_IRQ(5) -#define IRQ_PE6 BFIN_PE_IRQ(6) -#define IRQ_PE7 BFIN_PE_IRQ(7) -#define IRQ_PE8 BFIN_PE_IRQ(8) -#define IRQ_PE9 BFIN_PE_IRQ(9) -#define IRQ_PE10 BFIN_PE_IRQ(10) -#define IRQ_PE11 BFIN_PE_IRQ(11) -#define IRQ_PE12 BFIN_PE_IRQ(12) -#define IRQ_PE13 BFIN_PE_IRQ(13) -#define IRQ_PE14 BFIN_PE_IRQ(14) -#define IRQ_PE15 BFIN_PE_IRQ(15) - -#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) -#define IRQ_PF0 BFIN_PF_IRQ(0) -#define IRQ_PF1 BFIN_PF_IRQ(1) -#define IRQ_PF2 BFIN_PF_IRQ(2) -#define IRQ_PF3 BFIN_PF_IRQ(3) -#define IRQ_PF4 BFIN_PF_IRQ(4) -#define IRQ_PF5 BFIN_PF_IRQ(5) -#define IRQ_PF6 BFIN_PF_IRQ(6) -#define IRQ_PF7 BFIN_PF_IRQ(7) -#define IRQ_PF8 BFIN_PF_IRQ(8) -#define IRQ_PF9 BFIN_PF_IRQ(9) -#define IRQ_PF10 BFIN_PF_IRQ(10) -#define IRQ_PF11 BFIN_PF_IRQ(11) -#define IRQ_PF12 BFIN_PF_IRQ(12) -#define IRQ_PF13 BFIN_PF_IRQ(13) -#define IRQ_PF14 BFIN_PF_IRQ(14) -#define IRQ_PF15 BFIN_PF_IRQ(15) - -#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) -#define IRQ_PG0 BFIN_PG_IRQ(0) -#define IRQ_PG1 BFIN_PG_IRQ(1) -#define IRQ_PG2 BFIN_PG_IRQ(2) -#define IRQ_PG3 BFIN_PG_IRQ(3) -#define IRQ_PG4 BFIN_PG_IRQ(4) -#define IRQ_PG5 BFIN_PG_IRQ(5) -#define IRQ_PG6 BFIN_PG_IRQ(6) -#define IRQ_PG7 BFIN_PG_IRQ(7) -#define IRQ_PG8 BFIN_PG_IRQ(8) -#define IRQ_PG9 BFIN_PG_IRQ(9) -#define IRQ_PG10 BFIN_PG_IRQ(10) -#define IRQ_PG11 BFIN_PG_IRQ(11) -#define IRQ_PG12 BFIN_PG_IRQ(12) -#define IRQ_PG13 BFIN_PG_IRQ(13) -#define IRQ_PG14 BFIN_PG_IRQ(14) -#define IRQ_PG15 BFIN_PG_IRQ(15) - -#define GPIO_IRQ_BASE IRQ_PA0 - -#define NR_MACH_IRQS (IRQ_PG15 + 1) - -#define SEC_SCTL_PRIO_OFFSET 8 - -#ifndef __ASSEMBLY__ -#include - -extern u8 sec_int_priority[]; - -/* - * gpio pint registers layout - */ -struct bfin_pint_regs { - u32 mask_set; - u32 mask_clear; - u32 request; - u32 assign; - u32 edge_set; - u32 edge_clear; - u32 invert_set; - u32 invert_clear; - u32 pinstate; - u32 latch; - u32 __pad0[2]; -}; - -#endif - -#endif diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h deleted file mode 100644 index 20b65bfc5311..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/mem_map.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * BF60x memory map - * - * Copyright 2011 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ -#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xC8000000 -#define BOOT_ROM_LENGTH 0x8000 - -/* Level 1 Memory */ - -/* Memory Map for ADSP-BF60x processors */ -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#define L1_CODE_LENGTH 0x10000 -#else -#define BFIN_ICACHESIZE (0*1024) -#define L1_CODE_LENGTH 0x14000 -#endif - -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - - -#define COREA_L1_SCRATCH_START 0xFFB00000 -#define COREB_L1_SCRATCH_START 0xFF700000 - -#define COREB_L1_CODE_START 0xFF600000 -#define COREB_L1_DATA_A_START 0xFF400000 -#define COREB_L1_DATA_B_START 0xFF500000 - -#define COREB_L1_CODE_LENGTH 0x14000 -#define COREB_L1_DATA_A_LENGTH 0x8000 -#define COREB_L1_DATA_B_LENGTH 0x8000 - - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ - -/* Level 2 Memory */ -#define L2_START 0xC8080000 -#define L2_LENGTH 0x40000 - -#endif diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h deleted file mode 100644 index 1857a4a0f262..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -/* #include */ diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h deleted file mode 100644 index a1efd936dd30..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/pm.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Blackfin bf609 power management - * - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 - */ - -#ifndef __MACH_BF609_PM_H__ -#define __MACH_BF609_PM_H__ - -#include -#include - -extern int bfin609_pm_enter(suspend_state_t state); -extern int bf609_pm_prepare(void); -extern void bf609_pm_finish(void); - -void bf609_hibernate(void); -void bfin_sec_raise_irq(unsigned int sid); -void coreb_enable(void); - -int bf609_nor_flash_init(struct platform_device *pdev); -void bf609_nor_flash_exit(struct platform_device *pdev); -#endif diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h deleted file mode 100644 index c48bb71a55ce..000000000000 --- a/arch/blackfin/mach-bf609/include/mach/portmux.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -/* EMAC RMII Port Mux */ -#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) -#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) -#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) -#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) -#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) -#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) -#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) -#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) -#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) -#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) -#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) -#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0)) - -#define P_RMII0 {\ - P_MII0_ETxD0, \ - P_MII0_ETxD1, \ - P_MII0_ETxEN, \ - P_MII0_ERxD0, \ - P_MII0_ERxD1, \ - P_MII0_ERxER, \ - P_MII0_TxCLK, \ - P_MII0_PHYINT, \ - P_MII0_CRS, \ - P_MII0_PTPPPS, \ - P_MII0_MDC, \ - P_MII0_MDIO, 0} - -#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) -#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) -#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) -#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) -#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) -#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) -#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) -#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) -#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) -#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) -#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) -#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) - -#define P_RMII1 {\ - P_MII1_ETxD0, \ - P_MII1_ETxD1, \ - P_MII1_ETxEN, \ - P_MII1_ERxD0, \ - P_MII1_ERxD1, \ - P_MII1_ERxER, \ - P_MII1_TxCLK, \ - P_MII1_PHYINT, \ - P_MII1_CRS, \ - P_MII1_PTPPPS, \ - P_MII1_MDC, \ - P_MII1_MDIO, 0} - -/* PPI Port Mux */ -#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) -#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) -#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) -#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) -#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) -#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) -#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) -#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) -#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) -#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) -#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) -#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) -#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1)) -#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1)) -#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) - -#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1)) -#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) -#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1)) -#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1)) -#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1)) -#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) -#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1)) -#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1)) -#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1)) -#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1)) -#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1)) -#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1)) -#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1)) -#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1)) -#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1)) -#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1)) -#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) -#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) -#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1)) -#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1)) -#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) -#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1)) - -#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1)) -#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) -#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1)) -#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1)) -#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1)) -#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) -#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1)) -#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1)) -#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1)) -#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) -#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1)) -#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1)) -#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1)) -#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) -#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1)) -#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1)) -#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1)) -#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) -#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1)) -#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1)) -#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1)) -#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1)) - -/* SPI Port Mux */ -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) -#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) -#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) -#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) -#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) -#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) -#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) - -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) -#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) -#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) - -#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) -#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) -#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) -#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) -#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) -#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) -#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) - -#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) -#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) -#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) -#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) -#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) -#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) -#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0)) - -#define GPIO_DEFAULT_BOOT_SPI_CS -#define P_DEFAULT_BOOT_SPI_CS - -/* CORE IDLE */ -#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) -#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) -#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) - -/* UART Port Mux */ -#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) -#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) -#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) -#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) - -#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) -#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) -#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) -#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) - -/* Timer */ -#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3)) -#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2)) -#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) -#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1)) -#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) -#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) -#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) -#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) -#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) - -/* RSI */ -#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) -#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) -#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2)) -#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2)) -#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2)) -#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2)) -#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2)) -#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2)) -#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) -#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) - -/* PTP */ -#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0)) -#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2)) -#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2)) - -#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) -#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2)) -#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2)) - -/* SMC Port Mux */ -#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) -#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) -#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) -#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) -#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) -#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) -#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) -#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) -#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) -#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) -#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) -#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) -#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) -#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) -#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) -#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) -#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) -#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) -#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) -#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) -#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) -#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) -#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) -#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) - -#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) -#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) -#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) - -/* CAN */ -#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) -#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) - -/* SPORT */ -#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2)) -#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2)) -#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2)) -#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2)) -#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1)) -#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2)) -#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2)) -#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2)) -#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2)) -#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1)) - -#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2)) -#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2)) -#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) -#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) -#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) -#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2)) -#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2)) -#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2)) -#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2)) -#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) - -#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) -#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) -#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) -#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) -#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1)) -#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) -#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) -#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) -#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) -#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) - -/* LINK PORT */ -#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2)) -#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2)) -#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2)) -#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2)) -#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2)) -#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2)) -#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2)) -#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2)) -#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2)) -#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2)) - -#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2)) -#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2)) -#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2)) -#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2)) -#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2)) -#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2)) -#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2)) -#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2)) -#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2)) -#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2)) - -#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2)) -#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2)) -#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) -#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) -#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) -#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) -#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) -#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) -#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) -#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) - -#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2)) -#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2)) -#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2)) -#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) -#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) -#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) -#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) -#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) -#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) -#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) - -/* TWI */ -#define P_TWI0_SCL (P_DONTCARE) -#define P_TWI0_SDA (P_DONTCARE) -#define P_TWI1_SCL (P_DONTCARE) -#define P_TWI1_SDA (P_DONTCARE) - -/* Rotary Encoder */ -#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3)) -#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3)) -#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3)) - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c deleted file mode 100644 index f68abb9aa79e..000000000000 --- a/arch/blackfin/mach-bf609/ints-priority.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - * Set up the interrupt priorities - */ - -#include -#include -#include - -u8 sec_int_priority[] = { - 255, /* IRQ_SEC_ERR */ - 255, /* IRQ_CGU_EVT */ - 254, /* IRQ_WATCH0 */ - 254, /* IRQ_WATCH1 */ - 253, /* IRQ_L2CTL0_ECC_ERR */ - 253, /* IRQ_L2CTL0_ECC_WARN */ - 253, /* IRQ_C0_DBL_FAULT */ - 253, /* IRQ_C1_DBL_FAULT */ - 252, /* IRQ_C0_HW_ERR */ - 252, /* IRQ_C1_HW_ERR */ - 255, /* IRQ_C0_NMI_L1_PARITY_ERR */ - 255, /* IRQ_C1_NMI_L1_PARITY_ERR */ - - 50, /* IRQ_TIMER0 */ - 50, /* IRQ_TIMER1 */ - 50, /* IRQ_TIMER2 */ - 50, /* IRQ_TIMER3 */ - 50, /* IRQ_TIMER4 */ - 50, /* IRQ_TIMER5 */ - 50, /* IRQ_TIMER6 */ - 50, /* IRQ_TIMER7 */ - 50, /* IRQ_TIMER_STAT */ - 0, /* IRQ_PINT0 */ - 0, /* IRQ_PINT1 */ - 0, /* IRQ_PINT2 */ - 0, /* IRQ_PINT3 */ - 0, /* IRQ_PINT4 */ - 0, /* IRQ_PINT5 */ - 0, /* IRQ_CNT */ - 50, /* RQ_PWM0_TRIP */ - 50, /* IRQ_PWM0_SYNC */ - 50, /* IRQ_PWM1_TRIP */ - 50, /* IRQ_PWM1_SYNC */ - 0, /* IRQ_TWI0 */ - 0, /* IRQ_TWI1 */ - 10, /* IRQ_SOFT0 */ - 10, /* IRQ_SOFT1 */ - 10, /* IRQ_SOFT2 */ - 10, /* IRQ_SOFT3 */ - 0, /* IRQ_ACM_EVT_MISS */ - 0, /* IRQ_ACM_EVT_COMPLETE */ - 0, /* IRQ_CAN0_RX */ - 0, /* IRQ_CAN0_TX */ - 0, /* IRQ_CAN0_STAT */ - 100, /* IRQ_SPORT0_TX */ - 100, /* IRQ_SPORT0_TX_STAT */ - 100, /* IRQ_SPORT0_RX */ - 100, /* IRQ_SPORT0_RX_STAT */ - 100, /* IRQ_SPORT1_TX */ - 100, /* IRQ_SPORT1_TX_STAT */ - 100, /* IRQ_SPORT1_RX */ - 100, /* IRQ_SPORT1_RX_STAT */ - 100, /* IRQ_SPORT2_TX */ - 100, /* IRQ_SPORT2_TX_STAT */ - 100, /* IRQ_SPORT2_RX */ - 100, /* IRQ_SPORT2_RX_STAT */ - 0, /* IRQ_SPI0_TX */ - 0, /* IRQ_SPI0_RX */ - 0, /* IRQ_SPI0_STAT */ - 0, /* IRQ_SPI1_TX */ - 0, /* IRQ_SPI1_RX */ - 0, /* IRQ_SPI1_STAT */ - 0, /* IRQ_RSI */ - 0, /* IRQ_RSI_INT0 */ - 0, /* IRQ_RSI_INT1 */ - 0, /* DMA11 Data (SDU) */ - 0, /* DMA12 Data (Reserved) */ - 0, /* Reserved */ - 0, /* Reserved */ - 30, /* IRQ_EMAC0_STAT */ - 0, /* EMAC0 Power (Reserved) */ - 30, /* IRQ_EMAC1_STAT */ - 0, /* EMAC1 Power (Reserved) */ - 0, /* IRQ_LP0 */ - 0, /* IRQ_LP0_STAT */ - 0, /* IRQ_LP1 */ - 0, /* IRQ_LP1_STAT */ - 0, /* IRQ_LP2 */ - 0, /* IRQ_LP2_STAT */ - 0, /* IRQ_LP3 */ - 0, /* IRQ_LP3_STAT */ - 0, /* IRQ_UART0_TX */ - 0, /* IRQ_UART0_RX */ - 0, /* IRQ_UART0_STAT */ - 0, /* IRQ_UART1_TX */ - 0, /* IRQ_UART1_RX */ - 0, /* IRQ_UART1_STAT */ - 0, /* IRQ_MDMA0_SRC_CRC0 */ - 0, /* IRQ_MDMA0_DEST_CRC0 */ - 0, /* IRQ_CRC0_DCNTEXP */ - 0, /* IRQ_CRC0_ERR */ - 0, /* IRQ_MDMA1_SRC_CRC1 */ - 0, /* IRQ_MDMA1_DEST_CRC1 */ - 0, /* IRQ_CRC1_DCNTEXP */ - 0, /* IRQ_CRC1_ERR */ - 0, /* IRQ_MDMA2_SRC */ - 0, /* IRQ_MDMA2_DEST */ - 0, /* IRQ_MDMA3_SRC */ - 0, /* IRQ_MDMA3_DEST */ - 120, /* IRQ_EPPI0_CH0 */ - 120, /* IRQ_EPPI0_CH1 */ - 120, /* IRQ_EPPI0_STAT */ - 120, /* IRQ_EPPI2_CH0 */ - 120, /* IRQ_EPPI2_CH1 */ - 120, /* IRQ_EPPI2_STAT */ - 120, /* IRQ_EPPI1_CH0 */ - 120, /* IRQ_EPPI1_CH1 */ - 120, /* IRQ_EPPI1_STAT */ - 120, /* IRQ_PIXC_CH0 */ - 120, /* IRQ_PIXC_CH1 */ - 120, /* IRQ_PIXC_CH2 */ - 120, /* IRQ_PIXC_STAT */ - 120, /* IRQ_PVP_CPDOB */ - 120, /* IRQ_PVP_CPDOC */ - 120, /* IRQ_PVP_CPSTAT */ - 120, /* IRQ_PVP_CPCI */ - 120, /* IRQ_PVP_STAT0 */ - 120, /* IRQ_PVP_MPDO */ - 120, /* IRQ_PVP_MPDI */ - 120, /* IRQ_PVP_MPSTAT */ - 120, /* IRQ_PVP_MPCI */ - 120, /* IRQ_PVP_CPDOA */ - 120, /* IRQ_PVP_STAT1 */ - 0, /* IRQ_USB_STAT */ - 0, /* IRQ_USB_DMA */ - 0, /* IRQ_TRU_INT0 */ - 0, /* IRQ_TRU_INT1 */ - 0, /* IRQ_TRU_INT2 */ - 0, /* IRQ_TRU_INT3 */ - 0, /* IRQ_DMAC0_ERROR */ - 0, /* IRQ_CGU0_ERROR */ - 0, /* Reserved */ - 0, /* IRQ_DPM */ - 0, /* Reserved */ - 0, /* IRQ_SWU0 */ - 0, /* IRQ_SWU1 */ - 0, /* IRQ_SWU2 */ - 0, /* IRQ_SWU3 */ - 0, /* IRQ_SWU4 */ - 0, /* IRQ_SWU4 */ - 0, /* IRQ_SWU6 */ -}; - diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c deleted file mode 100644 index b1bfcf434d16..000000000000 --- a/arch/blackfin/mach-bf609/pm.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Blackfin bf609 power management - * - * Copyright 2011 Analog Devices Inc. - * - * Licensed under the GPL-2 - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/***********************************************************/ -/* */ -/* Wakeup Actions for DPM_RESTORE */ -/* */ -/***********************************************************/ -#define BITP_ROM_WUA_CHKHDR 24 -#define BITP_ROM_WUA_DDRLOCK 7 -#define BITP_ROM_WUA_DDRDLLEN 6 -#define BITP_ROM_WUA_DDR 5 -#define BITP_ROM_WUA_CGU 4 -#define BITP_ROM_WUA_MEMBOOT 2 -#define BITP_ROM_WUA_EN 1 - -#define BITM_ROM_WUA_CHKHDR (0xFF000000) -#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000 - -#define BITM_ROM_WUA_DDRLOCK (0x00000080) -#define BITM_ROM_WUA_DDRDLLEN (0x00000040) -#define BITM_ROM_WUA_DDR (0x00000020) -#define BITM_ROM_WUA_CGU (0x00000010) -#define BITM_ROM_WUA_MEMBOOT (0x00000002) -#define BITM_ROM_WUA_EN (0x00000001) - -/***********************************************************/ -/* */ -/* Syscontrol */ -/* */ -/***********************************************************/ -#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */ -#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24 -#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */ -#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */ -#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */ -#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */ -#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */ -#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */ -#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */ -#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */ -#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */ -#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */ -#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */ -#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */ -#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */ -#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */ -#define BITP_ROM_SYSCTRL_READ 0 /* read registers */ - -#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */ -#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */ -#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */ -#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */ -#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */ -#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */ -#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */ -#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */ -#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */ -#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */ -#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */ -#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */ -#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */ -#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */ -#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */ -#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000) -#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */ - - -/* Structures for the syscontrol() function */ -struct STRUCT_ROM_SYSCTRL { - uint32_t ulCGU_CTL; - uint32_t ulCGU_STAT; - uint32_t ulCGU_DIV; - uint32_t ulCGU_CLKOUTSEL; - uint32_t ulWUA_Flags; - uint32_t ulWUA_BootAddr; - uint32_t ulWUA_User; - uint32_t ulDDR_CTL; - uint32_t ulDDR_CFG; - uint32_t ulDDR_TR0; - uint32_t ulDDR_TR1; - uint32_t ulDDR_TR2; - uint32_t ulDDR_MR; - uint32_t ulDDR_EMR1; - uint32_t ulDDR_EMR2; - uint32_t ulDDR_PADCTL; - uint32_t ulDDR_DLLCTL; - uint32_t ulReserved; -}; - -struct bfin_pm_data { - uint32_t magic; - uint32_t resume_addr; - uint32_t sp; -}; - -struct bfin_pm_data bf609_pm_data; - -struct STRUCT_ROM_SYSCTRL configvalues; -uint32_t dactionflags; - -#define FUNC_ROM_SYSCONTROL 0xC8000080 -__attribute__((l1_data)) -static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL; - -__attribute__((l1_text)) -void bfin_cpu_suspend(void) -{ - __asm__ __volatile__( \ - ".align 8;" \ - "idle;" \ - : : \ - ); -} - -__attribute__((l1_text)) -void bf609_ddr_sr(void) -{ - dmc_enter_self_refresh(); -} - -__attribute__((l1_text)) -void bf609_ddr_sr_exit(void) -{ - dmc_exit_self_refresh(); - - /* After wake up from deep sleep and exit DDR from self refress mode, - * should wait till CGU PLL is locked. - */ - while (bfin_read32(CGU0_STAT) & CLKSALGN) - continue; -} - -__attribute__((l1_text)) -void bf609_resume_ccbuf(void) -{ - bfin_write32(DPM0_CCBF_EN, 3); - bfin_write32(DPM0_CTL, 2); - - while ((bfin_read32(DPM0_STAT) & 0xf) != 1); -} - -__attribute__((l1_text)) -void bfin_hibernate_syscontrol(void) -{ - configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN - | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN); - - dactionflags = (BITM_ROM_SYSCTRL_WUA_EN - | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU - | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN); - - bfrom_SysControl(dactionflags, &configvalues, NULL); - - bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); -} - -asmlinkage void enter_deepsleep(void); - -__attribute__((l1_text)) -void bfin_deepsleep(unsigned long mask, unsigned long pol_mask) -{ - bfin_write32(DPM0_WAKE_EN, mask); - bfin_write32(DPM0_WAKE_POL, pol_mask); - SSYNC(); - enter_deepsleep(); -} - -void bfin_hibernate(unsigned long mask, unsigned long pol_mask) -{ - bfin_write32(DPM0_WAKE_EN, mask); - bfin_write32(DPM0_WAKE_POL, pol_mask); - bfin_write32(DPM0_PGCNTR, 0x0000FFFF); - bfin_write32(DPM0_HIB_DIS, 0xFFFF); - - bf609_hibernate(); -} - -void bf609_cpu_pm_enter(suspend_state_t state) -{ - int error; - unsigned long wakeup = 0; - unsigned long wakeup_pol = 0; - -#ifdef CONFIG_PM_BFIN_WAKE_PA15 - wakeup |= PA15WE; -# if CONFIG_PM_BFIN_WAKE_PA15_POL - wakeup_pol |= PA15WE; -# endif -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_PB15 - wakeup |= PB15WE; -# if CONFIG_PM_BFIN_WAKE_PB15_POL - wakeup_pol |= PB15WE; -# endif -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_PC15 - wakeup |= PC15WE; -# if CONFIG_PM_BFIN_WAKE_PC15_POL - wakeup_pol |= PC15WE; -# endif -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_PD06 - wakeup |= PD06WE; -# if CONFIG_PM_BFIN_WAKE_PD06_POL - wakeup_pol |= PD06WE; -# endif -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_PE12 - wakeup |= PE12WE; -# if CONFIG_PM_BFIN_WAKE_PE12_POL - wakeup_pol |= PE12WE; -# endif -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_PG04 - wakeup |= PG04WE; -# if CONFIG_PM_BFIN_WAKE_PG04_POL - wakeup_pol |= PG04WE; -# endif -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_PG13 - wakeup |= PG13WE; -# if CONFIG_PM_BFIN_WAKE_PG13_POL - wakeup_pol |= PG13WE; -# endif -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_USB - wakeup |= USBWE; -# if CONFIG_PM_BFIN_WAKE_USB_POL - wakeup_pol |= USBWE; -# endif -#endif - - error = irq_set_irq_wake(255, 1); - if(error < 0) - printk(KERN_DEBUG "Unable to get irq wake\n"); - error = irq_set_irq_wake(231, 1); - if (error < 0) - printk(KERN_DEBUG "Unable to get irq wake\n"); - - if (state == PM_SUSPEND_STANDBY) - bfin_deepsleep(wakeup, wakeup_pol); - else { - bfin_hibernate(wakeup, wakeup_pol); - } - -} - -int bf609_cpu_pm_prepare(void) -{ - return 0; -} - -void bf609_cpu_pm_finish(void) -{ - -} - -static struct bfin_cpu_pm_fns bf609_cpu_pm = { - .enter = bf609_cpu_pm_enter, - .prepare = bf609_cpu_pm_prepare, - .finish = bf609_cpu_pm_finish, -}; - -#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) -static int smc_pm_syscore_suspend(void) -{ - bf609_nor_flash_exit(NULL); - return 0; -} - -static void smc_pm_syscore_resume(void) -{ - bf609_nor_flash_init(NULL); -} - -static struct syscore_ops smc_pm_syscore_ops = { - .suspend = smc_pm_syscore_suspend, - .resume = smc_pm_syscore_resume, -}; -#endif - -static irqreturn_t test_isr(int irq, void *dev_id) -{ - printk(KERN_DEBUG "gpio irq %d\n", irq); - if (irq == 231) - bfin_sec_raise_irq(BFIN_SYSIRQ(IRQ_SOFT1)); - return IRQ_HANDLED; -} - -static irqreturn_t dpm0_isr(int irq, void *dev_id) -{ - bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT)); - bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT)); - return IRQ_HANDLED; -} - -static int __init bf609_init_pm(void) -{ - int irq; - int error; - -#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) - register_syscore_ops(&smc_pm_syscore_ops); -#endif - -#ifdef CONFIG_PM_BFIN_WAKE_PE12 - irq = gpio_to_irq(GPIO_PE12); - if (irq < 0) { - error = irq; - printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n", - GPIO_PE12, error); - } - - error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND - | IRQF_FORCE_RESUME, "gpiope12", NULL); - if(error < 0) - printk(KERN_DEBUG "Unable to get irq\n"); -#endif - - error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND | - IRQF_FORCE_RESUME, "cgu0 event", NULL); - if(error < 0) - printk(KERN_DEBUG "Unable to get irq\n"); - - error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND | - IRQF_FORCE_RESUME, "dpm0 event", NULL); - if (error < 0) - printk(KERN_DEBUG "Unable to get irq\n"); - - bfin_cpu_pm = &bf609_cpu_pm; - return 0; -} - -late_initcall(bf609_init_pm); diff --git a/arch/blackfin/mach-bf609/scb.c b/arch/blackfin/mach-bf609/scb.c deleted file mode 100644 index ac1f07c33594..000000000000 --- a/arch/blackfin/mach-bf609/scb.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority - * - * Copyright 2012 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -struct scb_mi_prio scb_data[] = { -#ifdef CONFIG_SCB0_MI0 - { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, { - CONFIG_SCB0_MI0_SLOT0, - CONFIG_SCB0_MI0_SLOT1, - CONFIG_SCB0_MI0_SLOT2, - CONFIG_SCB0_MI0_SLOT3, - CONFIG_SCB0_MI0_SLOT4, - CONFIG_SCB0_MI0_SLOT5, - CONFIG_SCB0_MI0_SLOT6, - CONFIG_SCB0_MI0_SLOT7, - CONFIG_SCB0_MI0_SLOT8, - CONFIG_SCB0_MI0_SLOT9, - CONFIG_SCB0_MI0_SLOT10, - CONFIG_SCB0_MI0_SLOT11, - CONFIG_SCB0_MI0_SLOT12, - CONFIG_SCB0_MI0_SLOT13, - CONFIG_SCB0_MI0_SLOT14, - CONFIG_SCB0_MI0_SLOT15, - CONFIG_SCB0_MI0_SLOT16, - CONFIG_SCB0_MI0_SLOT17, - CONFIG_SCB0_MI0_SLOT18, - CONFIG_SCB0_MI0_SLOT19, - CONFIG_SCB0_MI0_SLOT20, - CONFIG_SCB0_MI0_SLOT21, - CONFIG_SCB0_MI0_SLOT22, - CONFIG_SCB0_MI0_SLOT23, - CONFIG_SCB0_MI0_SLOT24, - CONFIG_SCB0_MI0_SLOT25, - CONFIG_SCB0_MI0_SLOT26, - CONFIG_SCB0_MI0_SLOT27, - CONFIG_SCB0_MI0_SLOT28, - CONFIG_SCB0_MI0_SLOT29, - CONFIG_SCB0_MI0_SLOT30, - CONFIG_SCB0_MI0_SLOT31 - }, - }, -#endif -#ifdef CONFIG_SCB0_MI1 - { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, { - CONFIG_SCB0_MI1_SLOT0, - CONFIG_SCB0_MI1_SLOT1, - CONFIG_SCB0_MI1_SLOT2, - CONFIG_SCB0_MI1_SLOT3, - CONFIG_SCB0_MI1_SLOT4, - CONFIG_SCB0_MI1_SLOT5, - CONFIG_SCB0_MI1_SLOT6, - CONFIG_SCB0_MI1_SLOT7, - CONFIG_SCB0_MI1_SLOT8, - CONFIG_SCB0_MI1_SLOT9, - CONFIG_SCB0_MI1_SLOT10, - CONFIG_SCB0_MI1_SLOT11, - CONFIG_SCB0_MI1_SLOT12, - CONFIG_SCB0_MI1_SLOT13, - CONFIG_SCB0_MI1_SLOT14, - CONFIG_SCB0_MI1_SLOT15, - CONFIG_SCB0_MI1_SLOT16, - CONFIG_SCB0_MI1_SLOT17, - CONFIG_SCB0_MI1_SLOT18, - CONFIG_SCB0_MI1_SLOT19, - CONFIG_SCB0_MI1_SLOT20, - CONFIG_SCB0_MI1_SLOT21, - CONFIG_SCB0_MI1_SLOT22, - CONFIG_SCB0_MI1_SLOT23, - CONFIG_SCB0_MI1_SLOT24, - CONFIG_SCB0_MI1_SLOT25, - CONFIG_SCB0_MI1_SLOT26, - CONFIG_SCB0_MI1_SLOT27, - CONFIG_SCB0_MI1_SLOT28, - CONFIG_SCB0_MI1_SLOT29, - CONFIG_SCB0_MI1_SLOT30, - CONFIG_SCB0_MI1_SLOT31 - }, - }, -#endif -#ifdef CONFIG_SCB0_MI2 - { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, { - CONFIG_SCB0_MI2_SLOT0, - CONFIG_SCB0_MI2_SLOT1, - CONFIG_SCB0_MI2_SLOT2, - CONFIG_SCB0_MI2_SLOT3, - CONFIG_SCB0_MI2_SLOT4, - CONFIG_SCB0_MI2_SLOT5, - CONFIG_SCB0_MI2_SLOT6, - CONFIG_SCB0_MI2_SLOT7, - CONFIG_SCB0_MI2_SLOT8, - CONFIG_SCB0_MI2_SLOT9, - CONFIG_SCB0_MI2_SLOT10, - CONFIG_SCB0_MI2_SLOT11, - CONFIG_SCB0_MI2_SLOT12, - CONFIG_SCB0_MI2_SLOT13, - CONFIG_SCB0_MI2_SLOT14, - CONFIG_SCB0_MI2_SLOT15, - CONFIG_SCB0_MI2_SLOT16, - CONFIG_SCB0_MI2_SLOT17, - CONFIG_SCB0_MI2_SLOT18, - CONFIG_SCB0_MI2_SLOT19, - CONFIG_SCB0_MI2_SLOT20, - CONFIG_SCB0_MI2_SLOT21, - CONFIG_SCB0_MI2_SLOT22, - CONFIG_SCB0_MI2_SLOT23, - CONFIG_SCB0_MI2_SLOT24, - CONFIG_SCB0_MI2_SLOT25, - CONFIG_SCB0_MI2_SLOT26, - CONFIG_SCB0_MI2_SLOT27, - CONFIG_SCB0_MI2_SLOT28, - CONFIG_SCB0_MI2_SLOT29, - CONFIG_SCB0_MI2_SLOT30, - CONFIG_SCB0_MI2_SLOT31 - }, - }, -#endif -#ifdef CONFIG_SCB0_MI3 - { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, { - CONFIG_SCB0_MI3_SLOT0, - CONFIG_SCB0_MI3_SLOT1, - CONFIG_SCB0_MI3_SLOT2, - CONFIG_SCB0_MI3_SLOT3, - CONFIG_SCB0_MI3_SLOT4, - CONFIG_SCB0_MI3_SLOT5, - CONFIG_SCB0_MI3_SLOT6, - CONFIG_SCB0_MI3_SLOT7, - CONFIG_SCB0_MI3_SLOT8, - CONFIG_SCB0_MI3_SLOT9, - CONFIG_SCB0_MI3_SLOT10, - CONFIG_SCB0_MI3_SLOT11, - CONFIG_SCB0_MI3_SLOT12, - CONFIG_SCB0_MI3_SLOT13, - CONFIG_SCB0_MI3_SLOT14, - CONFIG_SCB0_MI3_SLOT15, - CONFIG_SCB0_MI3_SLOT16, - CONFIG_SCB0_MI3_SLOT17, - CONFIG_SCB0_MI3_SLOT18, - CONFIG_SCB0_MI3_SLOT19, - CONFIG_SCB0_MI3_SLOT20, - CONFIG_SCB0_MI3_SLOT21, - CONFIG_SCB0_MI3_SLOT22, - CONFIG_SCB0_MI3_SLOT23, - CONFIG_SCB0_MI3_SLOT24, - CONFIG_SCB0_MI3_SLOT25, - CONFIG_SCB0_MI3_SLOT26, - CONFIG_SCB0_MI3_SLOT27, - CONFIG_SCB0_MI3_SLOT28, - CONFIG_SCB0_MI3_SLOT29, - CONFIG_SCB0_MI3_SLOT30, - CONFIG_SCB0_MI3_SLOT31 - }, - }, -#endif -#ifdef CONFIG_SCB0_MI4 - { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, { - CONFIG_SCB0_MI4_SLOT0, - CONFIG_SCB0_MI4_SLOT1, - CONFIG_SCB0_MI4_SLOT2, - CONFIG_SCB0_MI4_SLOT3, - CONFIG_SCB0_MI4_SLOT4, - CONFIG_SCB0_MI4_SLOT5, - CONFIG_SCB0_MI4_SLOT6, - CONFIG_SCB0_MI4_SLOT7, - CONFIG_SCB0_MI4_SLOT8, - CONFIG_SCB0_MI4_SLOT9, - CONFIG_SCB0_MI4_SLOT10, - CONFIG_SCB0_MI4_SLOT11, - CONFIG_SCB0_MI4_SLOT12, - CONFIG_SCB0_MI4_SLOT13, - CONFIG_SCB0_MI4_SLOT14, - CONFIG_SCB0_MI4_SLOT15, - CONFIG_SCB0_MI4_SLOT16, - CONFIG_SCB0_MI4_SLOT17, - CONFIG_SCB0_MI4_SLOT18, - CONFIG_SCB0_MI4_SLOT19, - CONFIG_SCB0_MI4_SLOT20, - CONFIG_SCB0_MI4_SLOT21, - CONFIG_SCB0_MI4_SLOT22, - CONFIG_SCB0_MI4_SLOT23, - CONFIG_SCB0_MI4_SLOT24, - CONFIG_SCB0_MI4_SLOT25, - CONFIG_SCB0_MI4_SLOT26, - CONFIG_SCB0_MI4_SLOT27, - CONFIG_SCB0_MI4_SLOT28, - CONFIG_SCB0_MI4_SLOT29, - CONFIG_SCB0_MI4_SLOT30, - CONFIG_SCB0_MI4_SLOT31 - }, - }, -#endif -#ifdef CONFIG_SCB0_MI5 - { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, { - CONFIG_SCB0_MI5_SLOT0, - CONFIG_SCB0_MI5_SLOT1, - CONFIG_SCB0_MI5_SLOT2, - CONFIG_SCB0_MI5_SLOT3, - CONFIG_SCB0_MI5_SLOT4, - CONFIG_SCB0_MI5_SLOT5, - CONFIG_SCB0_MI5_SLOT6, - CONFIG_SCB0_MI5_SLOT7, - CONFIG_SCB0_MI5_SLOT8, - CONFIG_SCB0_MI5_SLOT9, - CONFIG_SCB0_MI5_SLOT10, - CONFIG_SCB0_MI5_SLOT11, - CONFIG_SCB0_MI5_SLOT12, - CONFIG_SCB0_MI5_SLOT13, - CONFIG_SCB0_MI5_SLOT14, - CONFIG_SCB0_MI5_SLOT15 - }, - }, -#endif -#ifdef CONFIG_SCB1_MI0 - { REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, { - CONFIG_SCB1_MI0_SLOT0, - CONFIG_SCB1_MI0_SLOT1, - CONFIG_SCB1_MI0_SLOT2, - CONFIG_SCB1_MI0_SLOT3, - CONFIG_SCB1_MI0_SLOT4, - CONFIG_SCB1_MI0_SLOT5, - CONFIG_SCB1_MI0_SLOT6, - CONFIG_SCB1_MI0_SLOT7, - CONFIG_SCB1_MI0_SLOT8, - CONFIG_SCB1_MI0_SLOT9, - CONFIG_SCB1_MI0_SLOT10, - CONFIG_SCB1_MI0_SLOT11, - CONFIG_SCB1_MI0_SLOT12, - CONFIG_SCB1_MI0_SLOT13, - CONFIG_SCB1_MI0_SLOT14, - CONFIG_SCB1_MI0_SLOT15, - CONFIG_SCB1_MI0_SLOT16, - CONFIG_SCB1_MI0_SLOT17, - CONFIG_SCB1_MI0_SLOT18, - CONFIG_SCB1_MI0_SLOT19 - }, - }, -#endif -#ifdef CONFIG_SCB2_MI0 - { REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, { - CONFIG_SCB2_MI0_SLOT0, - CONFIG_SCB2_MI0_SLOT1, - CONFIG_SCB2_MI0_SLOT2, - CONFIG_SCB2_MI0_SLOT3, - CONFIG_SCB2_MI0_SLOT4, - CONFIG_SCB2_MI0_SLOT5, - CONFIG_SCB2_MI0_SLOT6, - CONFIG_SCB2_MI0_SLOT7, - CONFIG_SCB2_MI0_SLOT8, - CONFIG_SCB2_MI0_SLOT9 - }, - }, -#endif -#ifdef CONFIG_SCB3_MI0 - { REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, { - CONFIG_SCB3_MI0_SLOT0, - CONFIG_SCB3_MI0_SLOT1, - CONFIG_SCB3_MI0_SLOT2, - CONFIG_SCB3_MI0_SLOT3, - CONFIG_SCB3_MI0_SLOT4, - CONFIG_SCB3_MI0_SLOT5, - CONFIG_SCB3_MI0_SLOT6, - CONFIG_SCB3_MI0_SLOT7, - CONFIG_SCB3_MI0_SLOT8, - CONFIG_SCB3_MI0_SLOT9, - CONFIG_SCB3_MI0_SLOT10, - CONFIG_SCB3_MI0_SLOT11, - CONFIG_SCB3_MI0_SLOT12, - CONFIG_SCB3_MI0_SLOT13, - CONFIG_SCB3_MI0_SLOT14, - CONFIG_SCB3_MI0_SLOT15 - }, - }, -#endif -#ifdef CONFIG_SCB4_MI0 - { REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, { - CONFIG_SCB4_MI0_SLOT0, - CONFIG_SCB4_MI0_SLOT1, - CONFIG_SCB4_MI0_SLOT2, - CONFIG_SCB4_MI0_SLOT3, - CONFIG_SCB4_MI0_SLOT4, - CONFIG_SCB4_MI0_SLOT5, - CONFIG_SCB4_MI0_SLOT6, - CONFIG_SCB4_MI0_SLOT7, - CONFIG_SCB4_MI0_SLOT8, - CONFIG_SCB4_MI0_SLOT9, - CONFIG_SCB4_MI0_SLOT10, - CONFIG_SCB4_MI0_SLOT11, - CONFIG_SCB4_MI0_SLOT12, - CONFIG_SCB4_MI0_SLOT13, - CONFIG_SCB4_MI0_SLOT14, - CONFIG_SCB4_MI0_SLOT15 - }, - }, -#endif -#ifdef CONFIG_SCB5_MI0 - { REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, { - CONFIG_SCB5_MI0_SLOT0, - CONFIG_SCB5_MI0_SLOT1, - CONFIG_SCB5_MI0_SLOT2, - CONFIG_SCB5_MI0_SLOT3, - CONFIG_SCB5_MI0_SLOT4, - CONFIG_SCB5_MI0_SLOT5, - CONFIG_SCB5_MI0_SLOT6, - CONFIG_SCB5_MI0_SLOT7 - }, - }, -#endif -#ifdef CONFIG_SCB6_MI0 - { REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, { - CONFIG_SCB6_MI0_SLOT0, - CONFIG_SCB6_MI0_SLOT1, - CONFIG_SCB6_MI0_SLOT2, - CONFIG_SCB6_MI0_SLOT3 - }, - }, -#endif -#ifdef CONFIG_SCB7_MI0 - { REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, { - CONFIG_SCB7_MI0_SLOT0, - CONFIG_SCB7_MI0_SLOT1, - CONFIG_SCB7_MI0_SLOT2, - CONFIG_SCB7_MI0_SLOT3, - CONFIG_SCB7_MI0_SLOT4, - CONFIG_SCB7_MI0_SLOT5 - }, - }, -#endif -#ifdef CONFIG_SCB8_MI0 - { REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, { - CONFIG_SCB8_MI0_SLOT0, - CONFIG_SCB8_MI0_SLOT1, - CONFIG_SCB8_MI0_SLOT2, - CONFIG_SCB8_MI0_SLOT3, - CONFIG_SCB8_MI0_SLOT4, - CONFIG_SCB8_MI0_SLOT5, - CONFIG_SCB8_MI0_SLOT6, - CONFIG_SCB8_MI0_SLOT7 - }, - }, -#endif -#ifdef CONFIG_SCB9_MI0 - { REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, { - CONFIG_SCB9_MI0_SLOT0, - CONFIG_SCB9_MI0_SLOT1, - CONFIG_SCB9_MI0_SLOT2, - CONFIG_SCB9_MI0_SLOT3, - CONFIG_SCB9_MI0_SLOT4, - CONFIG_SCB9_MI0_SLOT5, - CONFIG_SCB9_MI0_SLOT6, - CONFIG_SCB9_MI0_SLOT7, - CONFIG_SCB9_MI0_SLOT8, - CONFIG_SCB9_MI0_SLOT9 - }, - }, -#endif - { 0, } -}; diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile deleted file mode 100644 index fcef1c8e117f..000000000000 --- a/arch/blackfin/mach-common/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/mach-common/Makefile -# - -obj-y := \ - cache.o cache-c.o entry.o head.o \ - interrupt.o arch_checks.o ints-priority.o - -obj-$(CONFIG_PM) += pm.o -ifneq ($(CONFIG_BF60x),y) -obj-$(CONFIG_PM) += dpmc_modes.o -endif -obj-$(CONFIG_SCB_PRIORITY) += scb-init.o -obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o -obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c deleted file mode 100644 index d8643fdd0fcf..000000000000 --- a/arch/blackfin/mach-common/arch_checks.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Do some checking to make sure things are OK - * - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -#ifdef CONFIG_BFIN_KERNEL_CLOCK - -# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ) -# error "VCO selected is more than maximum value. Please change the VCO multipler" -# endif - -# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ) -# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -# endif - -# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ) -# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -# endif - -# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ) -# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK" -# endif - -# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -# error "Please select sclk less than cclk" -# endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -#if CONFIG_BOOT_LOAD < FIXED_CODE_END -# error "The kernel load address must be after the fixed code section" -#endif - -#if (CONFIG_BOOT_LOAD & 0x3) -# error "The kernel load address must be 4 byte aligned" -#endif - -/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */ -#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000 -# error "The kernel load address is too high; keep it below 10meg for safety" -#endif - -#if ANOMALY_05000263 && defined(CONFIG_MPU) -# error the MPU will not function safely while Anomaly 05000263 applies -#endif - -#if ANOMALY_05000448 -# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. -#endif - -/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ -#if ANOMALY_05000220 && \ - (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) -# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" -#endif - -#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1) -# error You need IFLUSH in L1 inst while Anomaly 05000491 applies -#endif diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c deleted file mode 100644 index f4adedc92895..000000000000 --- a/arch/blackfin/mach-common/cache-c.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Blackfin cache control code (simpler control-style functions) - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -/* Invalidate the Entire Data cache by - * clearing DMC[1:0] bits - */ -void blackfin_invalidate_entire_dcache(void) -{ - u32 dmem = bfin_read_DMEM_CONTROL(); - bfin_write_DMEM_CONTROL(dmem & ~0xc); - SSYNC(); - bfin_write_DMEM_CONTROL(dmem); - SSYNC(); -} - -/* Invalidate the Entire Instruction cache by - * clearing IMC bit - */ -void blackfin_invalidate_entire_icache(void) -{ - u32 imem = bfin_read_IMEM_CONTROL(); - bfin_write_IMEM_CONTROL(imem & ~0x4); - SSYNC(); - bfin_write_IMEM_CONTROL(imem); - SSYNC(); -} - -#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) - -static void -bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, - unsigned long cplb_data, unsigned long mem_control, - unsigned long mem_mask) -{ - int i; -#ifdef CONFIG_L1_PARITY_CHECK - u32 ctrl; - - if (cplb_addr == DCPLB_ADDR0) { - ctrl = bfin_read32(mem_control) | (1 << RDCHK); - CSYNC(); - bfin_write32(mem_control, ctrl); - SSYNC(); - } -#endif - - for (i = 0; i < MAX_CPLBS; i++) { - bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr); - bfin_write32(cplb_data + i * 4, cplb_tbl[i].data); - } - - _enable_cplb(mem_control, mem_mask); -} - -#ifdef CONFIG_BFIN_ICACHE -void bfin_icache_init(struct cplb_entry *icplb_tbl) -{ - bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL, - (IMC | ENICPLB)); -} -#endif - -#ifdef CONFIG_BFIN_DCACHE -void bfin_dcache_init(struct cplb_entry *dcplb_tbl) -{ - /* - * Anomaly notes: - * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL - * register, so that the port preferences for DAG0 and DAG1 are set - * to port B - */ - bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL, - (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); -} -#endif - -#endif diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S deleted file mode 100644 index 9f4dd35bfd74..000000000000 --- a/arch/blackfin/mach-common/cache.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Blackfin cache control code - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -/* 05000443 - IFLUSH cannot be last instruction in hardware loop */ -#if ANOMALY_05000443 -# define BROK_FLUSH_INST "IFLUSH" -#else -# define BROK_FLUSH_INST "no anomaly! yeah!" -#endif - -/* Since all L1 caches work the same way, we use the same method for flushing - * them. Only the actual flush instruction differs. We write this in asm as - * GCC can be hard to coax into writing nice hardware loops. - * - * Also, we assume the following register setup: - * R0 = start address - * R1 = end address - */ -.macro do_flush flushins:req label - - R2 = -L1_CACHE_BYTES; - - /* start = (start & -L1_CACHE_BYTES) */ - R0 = R0 & R2; - - /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ - R1 += -1; - R1 = R1 & R2; - R1 += L1_CACHE_BYTES; - - /* count = (end - start) >> L1_CACHE_SHIFT */ - R2 = R1 - R0; - R2 >>= L1_CACHE_SHIFT; - P1 = R2; - -.ifnb \label -\label : -.endif - P0 = R0; - - LSETUP (1f, 2f) LC1 = P1; -1: -.ifeqs "\flushins", BROK_FLUSH_INST - \flushins [P0++]; - nop; - nop; -2: nop; -.else -2: \flushins [P0++]; -.endif - - RTS; -.endm - -#ifdef CONFIG_ICACHE_FLUSH_L1 -.section .l1.text -#else -.text -#endif - -/* Invalidate all instruction cache lines assocoiated with this memory area */ -#ifdef CONFIG_SMP -# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1 -#endif -ENTRY(_blackfin_icache_flush_range) - do_flush IFLUSH -ENDPROC(_blackfin_icache_flush_range) - -#ifdef CONFIG_SMP -.text -# undef _blackfin_icache_flush_range -ENTRY(_blackfin_icache_flush_range) - p0.L = LO(DSPID); - p0.H = HI(DSPID); - r3 = [p0]; - r3 = r3.b (z); - p2 = r3; - p0.L = _blackfin_iflush_l1_entry; - p0.H = _blackfin_iflush_l1_entry; - p0 = p0 + (p2 << 2); - p1 = [p0]; - jump (p1); -ENDPROC(_blackfin_icache_flush_range) -#endif - -#ifdef CONFIG_DCACHE_FLUSH_L1 -.section .l1.text -#else -.text -#endif - -/* Throw away all D-cached data in specified region without any obligation to - * write them back. Since the Blackfin ISA does not have an "invalidate" - * instruction, we use flush/invalidate. Perhaps as a speed optimization we - * could bang on the DTEST MMRs ... - */ -ENTRY(_blackfin_dcache_invalidate_range) - do_flush FLUSHINV -ENDPROC(_blackfin_dcache_invalidate_range) - -/* Flush all data cache lines assocoiated with this memory area */ -ENTRY(_blackfin_dcache_flush_range) - do_flush FLUSH, .Ldfr -ENDPROC(_blackfin_dcache_flush_range) - -/* Our headers convert the page structure to an address, so just need to flush - * its contents like normal. We know the start address is page aligned (which - * greater than our cache alignment), as is the end address. So just jump into - * the middle of the dcache flush function. - */ -ENTRY(_blackfin_dflush_page) - P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); - jump .Ldfr; -ENDPROC(_blackfin_dflush_page) diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h deleted file mode 100644 index fed851a51aaf..000000000000 --- a/arch/blackfin/mach-common/clock.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __MACH_COMMON_CLKDEV_H -#define __MACH_COMMON_CLKDEV_H - -#include - -struct clk_ops { - unsigned long (*get_rate)(struct clk *clk); - unsigned long (*round_rate)(struct clk *clk, unsigned long rate); - int (*set_rate)(struct clk *clk, unsigned long rate); - int (*enable)(struct clk *clk); - int (*disable)(struct clk *clk); -}; - -struct clk { - const char *name; - unsigned long rate; - spinlock_t lock; - u32 flags; - const struct clk_ops *ops; - const struct params *params; - void __iomem *reg; - u32 mask; - u32 shift; -}; - -#endif - diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c deleted file mode 100644 index d436bd907fc8..000000000000 --- a/arch/blackfin/mach-common/clocks-init.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_BF60x - -#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) -#define CGU_DIV_VAL \ - ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \ - (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \ - (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \ - (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \ - (CONFIG_DCLK_DIV << DSEL_OFFSET)) - -#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) -#if ((CONFIG_BFIN_DCLK != 125) && \ - (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \ - (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \ - (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) -#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" -#endif - -#else -#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ -#define PLL_CTL_VAL \ - (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ - (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) -#endif - -__attribute__((l1_text)) -static void do_sync(void) -{ - __builtin_bfin_ssync(); -} - -__attribute__((l1_text)) -void init_clocks(void) -{ - /* Kill any active DMAs as they may trigger external memory accesses - * in the middle of reprogramming things, and that'll screw us up. - * For example, any automatic DMAs left by U-Boot for splash screens. - */ -#ifdef CONFIG_BF60x - init_cgu(CGU_DIV_VAL, CGU_CTL_VAL); - init_dmc(CONFIG_BFIN_DCLK); -#else - size_t i; - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - struct dma_register *dma = dma_io_base_addr[i]; - dma->cfg = 0; - } - - do_sync(); - -#ifdef SIC_IWR0 - bfin_write_SIC_IWR0(IWR_ENABLE(0)); -# ifdef SIC_IWR1 - /* BF52x system reset does not properly reset SIC_IWR1 which - * will screw up the bootrom as it relies on MDMA0/1 waking it - * up from IDLE instructions. See this report for more info: - * http://blackfin.uclinux.org/gf/tracker/4323 - */ - if (ANOMALY_05000435) - bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); - else - bfin_write_SIC_IWR1(IWR_DISABLE_ALL); -# endif -# ifdef SIC_IWR2 - bfin_write_SIC_IWR2(IWR_DISABLE_ALL); -# endif -#else - bfin_write_SIC_IWR(IWR_ENABLE(0)); -#endif - do_sync(); -#ifdef EBIU_SDGCTL - bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); - do_sync(); -#endif - -#ifdef CLKBUFOE - bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); - do_sync(); - __asm__ __volatile__("IDLE;"); -#endif - bfin_write_PLL_LOCKCNT(0x300); - do_sync(); - /* We always write PLL_CTL thus avoiding Anomaly 05000242 */ - bfin_write16(PLL_CTL, PLL_CTL_VAL); - __asm__ __volatile__("IDLE;"); - bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); -#ifdef EBIU_SDGCTL - bfin_write_EBIU_SDRRC(mem_SDRRC); - bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); -#else - bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); - do_sync(); - bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1); - bfin_write_EBIU_DDRCTL0(mem_DDRCTL0); - bfin_write_EBIU_DDRCTL1(mem_DDRCTL1); - bfin_write_EBIU_DDRCTL2(mem_DDRCTL2); -#ifdef CONFIG_MEM_EBIU_DDRQUE - bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); -#endif -#endif -#endif - do_sync(); - bfin_read16(0); - -} diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c deleted file mode 100644 index 724a8c5f5578..000000000000 --- a/arch/blackfin/mach-common/dpmc.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define DRIVER_NAME "bfin dpmc" - -struct bfin_dpmc_platform_data *pdata; - -/** - * bfin_set_vlev - Update VLEV field in VR_CTL Reg. - * Avoid BYPASS sequence - */ -static void bfin_set_vlev(unsigned int vlev) -{ - unsigned pll_lcnt; - - pll_lcnt = bfin_read_PLL_LOCKCNT(); - - bfin_write_PLL_LOCKCNT(1); - bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev); - bfin_write_PLL_LOCKCNT(pll_lcnt); -} - -/** - * bfin_get_vlev - Get CPU specific VLEV from platform device data - */ -static unsigned int bfin_get_vlev(unsigned int freq) -{ - int i; - - if (!pdata) - goto err_out; - - freq >>= 16; - - for (i = 0; i < pdata->tabsize; i++) - if (freq <= (pdata->tuple_tab[i] & 0xFFFF)) - return pdata->tuple_tab[i] >> 16; - -err_out: - printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n"); - return VLEV_120; -} - -#ifdef CONFIG_CPU_FREQ -# ifdef CONFIG_SMP -static void bfin_idle_this_cpu(void *info) -{ - unsigned long flags = 0; - unsigned long iwr0, iwr1, iwr2; - unsigned int cpu = smp_processor_id(); - - local_irq_save_hw(flags); - bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2); - - platform_clear_ipi(cpu, IRQ_SUPPLE_0); - SSYNC(); - asm("IDLE;"); - bfin_iwr_restore(iwr0, iwr1, iwr2); - - local_irq_restore_hw(flags); -} - -static void bfin_idle_cpu(void) -{ - smp_call_function(bfin_idle_this_cpu, NULL, 0); -} - -static void bfin_wakeup_cpu(void) -{ - unsigned int cpu; - unsigned int this_cpu = smp_processor_id(); - cpumask_t mask; - - cpumask_copy(&mask, cpu_online_mask); - cpumask_clear_cpu(this_cpu, &mask); - for_each_cpu(cpu, &mask) - platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); -} - -# else -static void bfin_idle_cpu(void) {} -static void bfin_wakeup_cpu(void) {} -# endif - -static int -vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) -{ - struct cpufreq_freqs *freq = data; - - if (freq->cpu != CPUFREQ_CPU) - return 0; - - if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) { - bfin_idle_cpu(); - bfin_set_vlev(bfin_get_vlev(freq->new)); - udelay(pdata->vr_settling_time); /* Wait until Volatge settled */ - bfin_wakeup_cpu(); - } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) { - bfin_idle_cpu(); - bfin_set_vlev(bfin_get_vlev(freq->new)); - bfin_wakeup_cpu(); - } - - return 0; -} - -static struct notifier_block vreg_cpufreq_notifier_block = { - .notifier_call = vreg_cpufreq_notifier -}; -#endif /* CONFIG_CPU_FREQ */ - -/** - * bfin_dpmc_probe - - * - */ -static int bfin_dpmc_probe(struct platform_device *pdev) -{ - if (pdev->dev.platform_data) - pdata = pdev->dev.platform_data; - else - return -EINVAL; - - return cpufreq_register_notifier(&vreg_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); -} - -/** - * bfin_dpmc_remove - - */ -static int bfin_dpmc_remove(struct platform_device *pdev) -{ - pdata = NULL; - return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); -} - -struct platform_driver bfin_dpmc_device_driver = { - .probe = bfin_dpmc_probe, - .remove = bfin_dpmc_remove, - .driver = { - .name = DRIVER_NAME, - } -}; -module_platform_driver(bfin_dpmc_device_driver); - -MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("cpu power management driver for Blackfin"); -MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S deleted file mode 100644 index de99f3aac2c5..000000000000 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -.section .l1.text -ENTRY(_sleep_mode) - [--SP] = (R7:4, P5:3); - [--SP] = RETS; - - call _set_sic_iwr; - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R1 = W[P0](z); - BITSET (R1, 3); - W[P0] = R1.L; - - CLI R2; - SSYNC; - IDLE; - STI R2; - - call _test_pll_locked; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R7 = w[p0](z); - BITCLR (R7, 3); - BITCLR (R7, 5); - w[p0] = R7.L; - IDLE; - - bfin_init_pm_bench_cycles; - - call _test_pll_locked; - - RETS = [SP++]; - (R7:4, P5:3) = [SP++]; - RTS; -ENDPROC(_sleep_mode) - -/* - * This func never returns as it puts the part into hibernate, and - * is only called from do_hibernate, so we don't bother saving or - * restoring any of the normal C runtime state. When we wake up, - * the entry point will be in do_hibernate and not here. - * - * We accept just one argument -- the value to write to VR_CTL. - */ - -ENTRY(_hibernate_mode) - /* Save/setup the regs we need early for minor pipeline optimization */ - R4 = R0; - - P3.H = hi(VR_CTL); - P3.L = lo(VR_CTL); - /* Disable all wakeup sources */ - R0 = IWR_DISABLE_ALL; - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - call _set_sic_iwr; - call _set_dram_srfs; - SSYNC; - - /* Finally, we climb into our cave to hibernate */ - W[P3] = R4.L; - - bfin_init_pm_bench_cycles; - - CLI R2; - IDLE; -.Lforever: - jump .Lforever; -ENDPROC(_hibernate_mode) - -ENTRY(_sleep_deeper) - [--SP] = (R7:4, P5:3); - [--SP] = RETS; - - CLI R4; - - P3 = R0; - P4 = R1; - P5 = R2; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - call _set_dram_srfs; /* Set SDRAM Self Refresh */ - - P0.H = hi(PLL_DIV); - P0.L = lo(PLL_DIV); - R6 = W[P0](z); - R0.L = 0xF; - W[P0] = R0.l; /* Set Max VCO to SCLK divider */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R5 = W[P0](z); - R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9; - W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */ - - SSYNC; - IDLE; - - call _test_pll_locked; - - P0.H = hi(VR_CTL); - P0.L = lo(VR_CTL); - R7 = W[P0](z); - R1 = 0x6; - R1 <<= 16; - R2 = 0x0404(Z); - R1 = R1|R2; - - R2 = DEPOSIT(R7, R1); - W[P0] = R2; /* Set Min Core Voltage */ - - SSYNC; - IDLE; - - call _test_pll_locked; - - R0 = P3; - R1 = P4; - R3 = P5; - call _set_sic_iwr; /* Set Awake from IDLE */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R0 = W[P0](z); - BITSET (R0, 3); - W[P0] = R0.L; /* Turn CCLK OFF */ - SSYNC; - IDLE; - - call _test_pll_locked; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; /* Set Awake from IDLE PLL */ - - P0.H = hi(VR_CTL); - P0.L = lo(VR_CTL); - W[P0]= R7; - - SSYNC; - IDLE; - - bfin_init_pm_bench_cycles; - - call _test_pll_locked; - - P0.H = hi(PLL_DIV); - P0.L = lo(PLL_DIV); - W[P0]= R6; /* Restore CCLK and SCLK divider */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - w[p0] = R5; /* Restore VCO multiplier */ - IDLE; - call _test_pll_locked; - - call _unset_dram_srfs; /* SDRAM Self Refresh Off */ - - STI R4; - - RETS = [SP++]; - (R7:4, P5:3) = [SP++]; - RTS; -ENDPROC(_sleep_deeper) - -ENTRY(_set_dram_srfs) - /* set the dram to self refresh mode */ - SSYNC; -#if defined(EBIU_RSTCTL) /* DDR */ - P0.H = hi(EBIU_RSTCTL); - P0.L = lo(EBIU_RSTCTL); - R2 = [P0]; - BITSET(R2, 3); /* SRREQ enter self-refresh mode */ - [P0] = R2; - SSYNC; -1: - R2 = [P0]; - CC = BITTST(R2, 4); - if !CC JUMP 1b; -#else /* SDRAM */ - P0.L = lo(EBIU_SDGCTL); - P0.H = hi(EBIU_SDGCTL); - P1.L = lo(EBIU_SDSTAT); - P1.H = hi(EBIU_SDSTAT); - - R2 = [P0]; - BITSET(R2, 24); /* SRFS enter self-refresh mode */ - [P0] = R2; - SSYNC; - -1: - R2 = w[P1]; - SSYNC; - cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */ - if !cc jump 1b; - - R2 = [P0]; - BITCLR(R2, 0); /* SCTLE disable CLKOUT */ - [P0] = R2; -#endif - RTS; -ENDPROC(_set_dram_srfs) - -ENTRY(_unset_dram_srfs) - /* set the dram out of self refresh mode */ - -#if defined(EBIU_RSTCTL) /* DDR */ - P0.H = hi(EBIU_RSTCTL); - P0.L = lo(EBIU_RSTCTL); - R2 = [P0]; - BITCLR(R2, 3); /* clear SRREQ bit */ - [P0] = R2; -#elif defined(EBIU_SDGCTL) /* SDRAM */ - /* release CLKOUT from self-refresh */ - P0.L = lo(EBIU_SDGCTL); - P0.H = hi(EBIU_SDGCTL); - - R2 = [P0]; - BITSET(R2, 0); /* SCTLE enable CLKOUT */ - [P0] = R2 - SSYNC; - - /* release SDRAM from self-refresh */ - R2 = [P0]; - BITCLR(R2, 24); /* clear SRFS bit */ - [P0] = R2 -#endif - - SSYNC; - RTS; -ENDPROC(_unset_dram_srfs) - -ENTRY(_set_sic_iwr) -#ifdef SIC_IWR0 - P0.H = hi(SYSMMR_BASE); - P0.L = lo(SYSMMR_BASE); - [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0; - [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1; -# ifdef SIC_IWR2 - [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2; -# endif -#else - P0.H = hi(SIC_IWR); - P0.L = lo(SIC_IWR); - [P0] = R0; -#endif - - SSYNC; - RTS; -ENDPROC(_set_sic_iwr) - -ENTRY(_test_pll_locked) - P0.H = hi(PLL_STAT); - P0.L = lo(PLL_STAT); -1: - R0 = W[P0] (Z); - CC = BITTST(R0,5); - IF !CC JUMP 1b; - RTS; -ENDPROC(_test_pll_locked) - -.section .text -ENTRY(_do_hibernate) - bfin_cpu_reg_save; - bfin_sys_mmr_save; - bfin_core_mmr_save; - - /* Setup args to hibernate mode early for pipeline optimization */ - R0 = M3; - P1.H = _hibernate_mode; - P1.L = _hibernate_mode; - - /* Save Magic, return address and Stack Pointer */ - P0 = 0; - R1.H = 0xDEAD; /* Hibernate Magic */ - R1.L = 0xBEEF; - R2.H = .Lpm_resume_here; - R2.L = .Lpm_resume_here; - [P0++] = R1; /* Store Hibernate Magic */ - [P0++] = R2; /* Save Return Address */ - [P0++] = SP; /* Save Stack Pointer */ - - /* Must use an indirect call as we need to jump to L1 */ - call (P1); /* Goodbye */ - -.Lpm_resume_here: - - bfin_core_mmr_restore; - bfin_sys_mmr_restore; - bfin_cpu_reg_restore; - - [--sp] = RETI; /* Clear Global Interrupt Disable */ - SP += 4; - - RTS; -ENDPROC(_do_hibernate) diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S deleted file mode 100644 index 8d9431e22e8c..000000000000 --- a/arch/blackfin/mach-common/entry.S +++ /dev/null @@ -1,1711 +0,0 @@ -/* - * Contains the system-call and fault low-level handling routines. - * This also contains the timer-interrupt handler, as well as all - * interrupts and faults that can result in a task-switch. - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -/* NOTE: This code handles signal-recognition, which happens every time - * after a timer-interrupt and after each system call. - */ - -#include -#include -#include -#include -#include -#include -#include /* TIF_NEED_RESCHED */ -#include -#include -#include - -#include - - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -.section .l1.text -#else -.text -#endif - -/* Slightly simplified and streamlined entry point for CPLB misses. - * This one does not lower the level to IRQ5, and thus can be used to - * patch up CPLB misses on the kernel stack. - */ -#if ANOMALY_05000261 -#define _ex_dviol _ex_workaround_261 -#define _ex_dmiss _ex_workaround_261 -#define _ex_dmult _ex_workaround_261 - -ENTRY(_ex_workaround_261) - /* - * Work around an anomaly: if we see a new DCPLB fault, return - * without doing anything. Then, if we get the same fault again, - * handle it. - */ - P4 = R7; /* Store EXCAUSE */ - - GET_PDA(p5, r7); - r7 = [p5 + PDA_LFRETX]; - r6 = retx; - [p5 + PDA_LFRETX] = r6; - cc = r6 == r7; - if !cc jump _bfin_return_from_exception; - /* fall through */ - R7 = P4; - R6 = VEC_CPLB_M; /* Data CPLB Miss */ - cc = R6 == R7; - if cc jump _ex_dcplb_miss (BP); -#ifdef CONFIG_MPU - R6 = VEC_CPLB_VL; /* Data CPLB Violation */ - cc = R6 == R7; - if cc jump _ex_dcplb_viol (BP); -#endif - /* Handle Data CPLB Protection Violation - * and Data CPLB Multiple Hits - Linux Trap Zero - */ - jump _ex_trap_c; -ENDPROC(_ex_workaround_261) - -#else -#ifdef CONFIG_MPU -#define _ex_dviol _ex_dcplb_viol -#else -#define _ex_dviol _ex_trap_c -#endif -#define _ex_dmiss _ex_dcplb_miss -#define _ex_dmult _ex_trap_c -#endif - - -ENTRY(_ex_dcplb_viol) -ENTRY(_ex_dcplb_miss) -ENTRY(_ex_icplb_miss) - (R7:6,P5:4) = [sp++]; - /* We leave the previously pushed ASTAT on the stack. */ - SAVE_CONTEXT_CPLB - - /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that - * will change the stack pointer. */ - R0 = SEQSTAT; - R1 = SP; - - DEBUG_HWTRACE_SAVE(p5, r7) - - sp += -12; - call _cplb_hdr; - sp += 12; - CC = R0 == 0; - IF !CC JUMP _handle_bad_cplb; - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* While we were processing this, did we double fault? */ - r7 = SEQSTAT; /* reason code is in bit 5:0 */ - r6.l = lo(SEQSTAT_EXCAUSE); - r6.h = hi(SEQSTAT_EXCAUSE); - r7 = r7 & r6; - r6 = 0x25; - CC = R7 == R6; - if CC JUMP _double_fault; -#endif - - DEBUG_HWTRACE_RESTORE(p5, r7) - RESTORE_CONTEXT_CPLB - ASTAT = [SP++]; - SP = EX_SCRATCH_REG; - rtx; -ENDPROC(_ex_icplb_miss) - -ENTRY(_ex_syscall) - raise 15; /* invoked by TRAP #0, for sys call */ - jump.s _bfin_return_from_exception; -ENDPROC(_ex_syscall) - -ENTRY(_ex_single_step) - /* If we just returned from an interrupt, the single step event is - for the RTI instruction. */ - r7 = retx; - r6 = reti; - cc = r7 == r6; - if cc jump _bfin_return_from_exception; - -#ifdef CONFIG_KGDB - /* Don't do single step in hardware exception handler */ - p5.l = lo(IPEND); - p5.h = hi(IPEND); - r6 = [p5]; - cc = bittst(r6, 4); - if cc jump _bfin_return_from_exception; - cc = bittst(r6, 5); - if cc jump _bfin_return_from_exception; - - /* skip single step if current interrupt priority is higher than - * that of the first instruction, from which gdb starts single step */ - r6 >>= 6; - r7 = 10; -.Lfind_priority_start: - cc = bittst(r6, 0); - if cc jump .Lfind_priority_done; - r6 >>= 1; - r7 += -1; - cc = r7 == 0; - if cc jump .Lfind_priority_done; - jump.s .Lfind_priority_start; -.Lfind_priority_done: - p4.l = _kgdb_single_step; - p4.h = _kgdb_single_step; - r6 = [p4]; - cc = r6 == 0; - if cc jump .Ldo_single_step; - r6 += -1; - cc = r6 < r7; - if cc jump 1f; -.Ldo_single_step: -#else - /* If we were in user mode, do the single step normally. */ - p5.l = lo(IPEND); - p5.h = hi(IPEND); - r6 = [p5]; - r7 = 0xffe0 (z); - r7 = r7 & r6; - cc = r7 == 0; - if !cc jump 1f; -#endif -#ifdef CONFIG_EXACT_HWERR - /* Read the ILAT, and to check to see if the process we are - * single stepping caused a previous hardware error - * If so, do not single step, (which lowers to IRQ5, and makes - * us miss the error). - */ - p5.l = lo(ILAT); - p5.h = hi(ILAT); - r7 = [p5]; - cc = bittst(r7, EVT_IVHW_P); - if cc jump 1f; -#endif - /* Single stepping only a single instruction, so clear the trace - * bit here. */ - r7 = syscfg; - bitclr (r7, SYSCFG_SSSTEP_P); - syscfg = R7; - jump _ex_trap_c; - -1: - /* - * We were in an interrupt handler. By convention, all of them save - * SYSCFG with their first instruction, so by checking whether our - * RETX points at the entry point, we can determine whether to allow - * a single step, or whether to clear SYSCFG. - * - * First, find out the interrupt level and the event vector for it. - */ - p5.l = lo(EVT0); - p5.h = hi(EVT0); - p5 += -4; -2: - r7 = rot r7 by -1; - p5 += 4; - if !cc jump 2b; - - /* What we actually do is test for the _second_ instruction in the - * IRQ handler. That way, if there are insns following the restore - * of SYSCFG after leaving the handler, we will not turn off SYSCFG - * for them. */ - - r7 = [p5]; - r7 += 2; - r6 = RETX; - cc = R7 == R6; - if !cc jump _bfin_return_from_exception; - - r7 = syscfg; - bitclr (r7, SYSCFG_SSSTEP_P); /* Turn off single step */ - syscfg = R7; - - /* Fall through to _bfin_return_from_exception. */ -ENDPROC(_ex_single_step) - -ENTRY(_bfin_return_from_exception) -#if ANOMALY_05000257 - R7=LC0; - LC0=R7; - R7=LC1; - LC1=R7; -#endif - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* While we were processing the current exception, - * did we cause another, and double fault? - */ - r7 = SEQSTAT; /* reason code is in bit 5:0 */ - r6.l = lo(SEQSTAT_EXCAUSE); - r6.h = hi(SEQSTAT_EXCAUSE); - r7 = r7 & r6; - r6 = VEC_UNCOV; - CC = R7 == R6; - if CC JUMP _double_fault; -#endif - - (R7:6,P5:4) = [sp++]; - ASTAT = [sp++]; - sp = EX_SCRATCH_REG; - rtx; -ENDPROC(_bfin_return_from_exception) - -ENTRY(_handle_bad_cplb) - DEBUG_HWTRACE_RESTORE(p5, r7) - /* To get here, we just tried and failed to change a CPLB - * so, handle things in trap_c (C code), by lowering to - * IRQ5, just like we normally do. Since this is not a - * "normal" return path, we have a do a lot of stuff to - * the stack to get ready so, we can fall through - we - * need to make a CPLB exception look like a normal exception - */ - RESTORE_CONTEXT_CPLB - /* ASTAT is still on the stack, where it is needed. */ - [--sp] = (R7:6,P5:4); - -ENTRY(_ex_replaceable) - nop; - -ENTRY(_ex_trap_c) - /* The only thing that has been saved in this context is - * (R7:6,P5:4), ASTAT & SP - don't use anything else - */ - - GET_PDA(p5, r6); - - /* Make sure we are not in a double fault */ - p4.l = lo(IPEND); - p4.h = hi(IPEND); - r7 = [p4]; - CC = BITTST (r7, 5); - if CC jump _double_fault; - [p5 + PDA_EXIPEND] = r7; - - /* Call C code (trap_c) to handle the exception, which most - * likely involves sending a signal to the current process. - * To avoid double faults, lower our priority to IRQ5 first. - */ - r7.h = _exception_to_level5; - r7.l = _exception_to_level5; - p4.l = lo(EVT5); - p4.h = hi(EVT5); - [p4] = r7; - csync; - - /* - * Save these registers, as they are only valid in exception context - * (where we are now - as soon as we defer to IRQ5, they can change) - * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3, - * but they are not very interesting, so don't save them - */ - - p4.l = lo(DCPLB_FAULT_ADDR); - p4.h = hi(DCPLB_FAULT_ADDR); - r7 = [p4]; - [p5 + PDA_DCPLB] = r7; - - p4.l = lo(ICPLB_FAULT_ADDR); - p4.h = hi(ICPLB_FAULT_ADDR); - r6 = [p4]; - [p5 + PDA_ICPLB] = r6; - - r6 = retx; - [p5 + PDA_RETX] = r6; - - r6 = SEQSTAT; - [p5 + PDA_SEQSTAT] = r6; - - /* Save the state of single stepping */ - r6 = SYSCFG; - [p5 + PDA_SYSCFG] = r6; - /* Clear it while we handle the exception in IRQ5 mode */ - BITCLR(r6, SYSCFG_SSSTEP_P); - SYSCFG = r6; - - /* Save the current IMASK, since we change in order to jump to level 5 */ - cli r6; - [p5 + PDA_EXIMASK] = r6; - - p4.l = lo(SAFE_USER_INSTRUCTION); - p4.h = hi(SAFE_USER_INSTRUCTION); - retx = p4; - - /* Disable all interrupts, but make sure level 5 is enabled so - * we can switch to that level. - */ - r6 = 0x3f; - sti r6; - - /* In case interrupts are disabled IPEND[4] (global interrupt disable bit) - * clear it (re-enabling interrupts again) by the special sequence of pushing - * RETI onto the stack. This way we can lower ourselves to IVG5 even if the - * exception was taken after the interrupt handler was called but before it - * got a chance to enable global interrupts itself. - */ - [--sp] = reti; - sp += 4; - - raise 5; - jump.s _bfin_return_from_exception; -ENDPROC(_ex_trap_c) - -/* We just realized we got an exception, while we were processing a different - * exception. This is a unrecoverable event, so crash. - * Note: this cannot be ENTRY() as we jump here with "if cc jump" ... - */ -ENTRY(_double_fault) - /* Turn caches & protection off, to ensure we don't get any more - * double exceptions - */ - - P4.L = LO(IMEM_CONTROL); - P4.H = HI(IMEM_CONTROL); - - R5 = [P4]; /* Control Register*/ - BITCLR(R5,ENICPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - P4.L = LO(DMEM_CONTROL); - P4.H = HI(DMEM_CONTROL); - R5 = [P4]; - BITCLR(R5,ENDCPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - /* Fix up the stack */ - (R7:6,P5:4) = [sp++]; - ASTAT = [sp++]; - SP = EX_SCRATCH_REG; - - /* We should be out of the exception stack, and back down into - * kernel or user space stack - */ - SAVE_ALL_SYS - - /* The dumping functions expect the return address in the RETI - * slot. */ - r6 = retx; - [sp + PT_PC] = r6; - - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - SP += -12; - pseudo_long_call _double_fault_c, p5; - SP += 12; -.L_double_fault_panic: - JUMP .L_double_fault_panic - -ENDPROC(_double_fault) - -ENTRY(_exception_to_level5) - SAVE_ALL_SYS - - GET_PDA(p5, r7); /* Fetch current PDA */ - r6 = [p5 + PDA_RETX]; - [sp + PT_PC] = r6; - - r6 = [p5 + PDA_SYSCFG]; - [sp + PT_SYSCFG] = r6; - - r6 = [p5 + PDA_SEQSTAT]; /* Read back seqstat */ - [sp + PT_SEQSTAT] = r6; - - /* Restore the hardware error vector. */ - r7.h = _evt_ivhw; - r7.l = _evt_ivhw; - p4.l = lo(EVT5); - p4.h = hi(EVT5); - [p4] = r7; - csync; - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* Now that we have the hardware error vector programmed properly - * we can re-enable interrupts (IPEND[4]), so if the _trap_c causes - * another hardware error, we can catch it (self-nesting). - */ - [--sp] = reti; - sp += 4; -#endif - - r7 = [p5 + PDA_EXIPEND] /* Read the IPEND from the Exception state */ - [sp + PT_IPEND] = r7; /* Store IPEND onto the stack */ - - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - SP += -12; - pseudo_long_call _trap_c, p4; - SP += 12; - - /* If interrupts were off during the exception (IPEND[4] = 1), turn them off - * before we return. - */ - CC = BITTST(r7, EVT_IRPTEN_P) - if !CC jump 1f; - /* this will load a random value into the reti register - but that is OK, - * since we do restore it to the correct value in the 'RESTORE_ALL_SYS' macro - */ - sp += -4; - reti = [sp++]; -1: - /* restore the interrupt mask (IMASK) */ - r6 = [p5 + PDA_EXIMASK]; - sti r6; - - call _ret_from_exception; - RESTORE_ALL_SYS - rti; -ENDPROC(_exception_to_level5) - -ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ - /* Since the kernel stack can be anywhere, it's not guaranteed to be - * covered by a CPLB. Switch to an exception stack; use RETN as a - * scratch register (for want of a better option). - */ - EX_SCRATCH_REG = sp; - GET_PDA_SAFE(sp); - sp = [sp + PDA_EXSTACK]; - /* Try to deal with syscalls quickly. */ - [--sp] = ASTAT; - [--sp] = (R7:6,P5:4); - - ANOMALY_283_315_WORKAROUND(p5, r7) - -#ifdef CONFIG_EXACT_HWERR - /* Make sure all pending read/writes complete. This will ensure any - * accesses which could cause hardware errors completes, and signal - * the the hardware before we do something silly, like crash the - * kernel. We don't need to work around anomaly 05000312, since - * we are already atomic - */ - ssync; -#endif - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* - * Save these registers, as they are only valid in exception context - * (where we are now - as soon as we defer to IRQ5, they can change) - * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3, - * but they are not very interesting, so don't save them - */ - - GET_PDA(p5, r7); - p4.l = lo(DCPLB_FAULT_ADDR); - p4.h = hi(DCPLB_FAULT_ADDR); - r7 = [p4]; - [p5 + PDA_DF_DCPLB] = r7; - - p4.l = lo(ICPLB_FAULT_ADDR); - p4.h = hi(ICPLB_FAULT_ADDR); - r7 = [p4]; - [p5 + PDA_DF_ICPLB] = r7; - - r7 = retx; - [p5 + PDA_DF_RETX] = r7; - - r7 = SEQSTAT; /* reason code is in bit 5:0 */ - [p5 + PDA_DF_SEQSTAT] = r7; -#else - r7 = SEQSTAT; /* reason code is in bit 5:0 */ -#endif - r6.l = lo(SEQSTAT_EXCAUSE); - r6.h = hi(SEQSTAT_EXCAUSE); - r7 = r7 & r6; - p5.h = _ex_table; - p5.l = _ex_table; - p4 = r7; - p5 = p5 + (p4 << 2); - p4 = [p5]; - jump (p4); - -.Lbadsys: - r7 = -ENOSYS; /* signextending enough */ - [sp + PT_R0] = r7; /* return value from system call */ - jump .Lsyscall_really_exit; -ENDPROC(_trap) - -ENTRY(_system_call) - /* Store IPEND */ - p2.l = lo(IPEND); - p2.h = hi(IPEND); - csync; - r0 = [p2]; - [sp + PT_IPEND] = r0; - - /* Store RETS for now */ - r0 = rets; - [sp + PT_RESERVED] = r0; - /* Set the stack for the current process */ - r7 = sp; - r6.l = lo(ALIGN_PAGE_MASK); - r6.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r6; /* thread_info */ - p2 = r7; - p2 = [p2]; - - [p2+(TASK_THREAD+THREAD_KSP)] = sp; -#ifdef CONFIG_IPIPE - r0 = sp; - SP += -12; - pseudo_long_call ___ipipe_syscall_root, p0; - SP += 12; - cc = r0 == 1; - if cc jump .Lsyscall_really_exit; - cc = r0 == -1; - if cc jump .Lresume_userspace; - r3 = [sp + PT_R3]; - r4 = [sp + PT_R4]; - p0 = [sp + PT_ORIG_P0]; -#endif /* CONFIG_IPIPE */ - - /* are we tracing syscalls?*/ - r7 = sp; - r6.l = lo(ALIGN_PAGE_MASK); - r6.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r6; - p2 = r7; - r7 = [p2+TI_FLAGS]; - CC = BITTST(r7,TIF_SYSCALL_TRACE); - if CC JUMP _sys_trace; - CC = BITTST(r7,TIF_SINGLESTEP); - if CC JUMP _sys_trace; - - /* Make sure the system call # is valid */ - p4 = __NR_syscall; - /* System call number is passed in P0 */ - cc = p4 <= p0; - if cc jump .Lbadsys; - - /* Execute the appropriate system call */ - - p4 = p0; - p5.l = _sys_call_table; - p5.h = _sys_call_table; - p5 = p5 + (p4 << 2); - r0 = [sp + PT_R0]; - r1 = [sp + PT_R1]; - r2 = [sp + PT_R2]; - p5 = [p5]; - - [--sp] = r5; - [--sp] = r4; - [--sp] = r3; - SP += -12; - call (p5); - SP += 24; - [sp + PT_R0] = r0; - -.Lresume_userspace: - r7 = sp; - r4.l = lo(ALIGN_PAGE_MASK); - r4.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r4; /* thread_info->flags */ - p5 = r7; -.Lresume_userspace_1: - /* Disable interrupts. */ - [--sp] = reti; - reti = [sp++]; - - r7 = [p5 + TI_FLAGS]; - r4.l = lo(_TIF_WORK_MASK); - r4.h = hi(_TIF_WORK_MASK); - r7 = r7 & r4; - -.Lsyscall_resched: -#ifdef CONFIG_IPIPE - cc = BITTST(r7, TIF_IRQ_SYNC); - if !cc jump .Lsyscall_no_irqsync; - /* - * Clear IPEND[4] manually to undo what resume_userspace_1 just did; - * we need this so that high priority domain interrupts may still - * preempt the current domain while the pipeline log is being played - * back. - */ - [--sp] = reti; - SP += 4; /* don't merge with next insn to keep the pattern obvious */ - SP += -12; - pseudo_long_call ___ipipe_sync_root, p4; - SP += 12; - jump .Lresume_userspace_1; -.Lsyscall_no_irqsync: -#endif - cc = BITTST(r7, TIF_NEED_RESCHED); - if !cc jump .Lsyscall_sigpending; - - /* Reenable interrupts. */ - [--sp] = reti; - sp += 4; - - SP += -12; - pseudo_long_call _schedule, p4; - SP += 12; - - jump .Lresume_userspace_1; - -.Lsyscall_sigpending: - cc = BITTST(r7, TIF_SIGPENDING); - if cc jump .Lsyscall_do_signals; - cc = BITTST(r7, TIF_NOTIFY_RESUME); - if !cc jump .Lsyscall_really_exit; -.Lsyscall_do_signals: - /* Reenable interrupts. */ - [--sp] = reti; - sp += 4; - - r0 = sp; - SP += -12; - pseudo_long_call _do_notify_resume, p5; - SP += 12; - -.Lsyscall_really_exit: - r5 = [sp + PT_RESERVED]; - rets = r5; - rts; -ENDPROC(_system_call) - -/* Do not mark as ENTRY() to avoid error in assembler ... - * this symbol need not be global anyways, so ... - */ -_sys_trace: - r0 = sp; - pseudo_long_call _syscall_trace_enter, p5; - - /* Make sure the system call # is valid */ - p4 = [SP + PT_P0]; - p3 = __NR_syscall; - cc = p3 <= p4; - r0 = -ENOSYS; - if cc jump .Lsys_trace_badsys; - - /* Execute the appropriate system call */ - p5.l = _sys_call_table; - p5.h = _sys_call_table; - p5 = p5 + (p4 << 2); - r0 = [sp + PT_R0]; - r1 = [sp + PT_R1]; - r2 = [sp + PT_R2]; - r3 = [sp + PT_R3]; - r4 = [sp + PT_R4]; - r5 = [sp + PT_R5]; - p5 = [p5]; - - [--sp] = r5; - [--sp] = r4; - [--sp] = r3; - SP += -12; - call (p5); - SP += 24; -.Lsys_trace_badsys: - [sp + PT_R0] = r0; - - r0 = sp; - pseudo_long_call _syscall_trace_leave, p5; - jump .Lresume_userspace; -ENDPROC(_sys_trace) - -ENTRY(_resume) - /* - * Beware - when entering resume, prev (the current task) is - * in r0, next (the new task) is in r1. - */ - p0 = r0; - p1 = r1; - [--sp] = rets; - [--sp] = fp; - [--sp] = (r7:4, p5:3); - - /* save usp */ - p2 = usp; - [p0+(TASK_THREAD+THREAD_USP)] = p2; - - /* save current kernel stack pointer */ - [p0+(TASK_THREAD+THREAD_KSP)] = sp; - - /* save program counter */ - r1.l = _new_old_task; - r1.h = _new_old_task; - [p0+(TASK_THREAD+THREAD_PC)] = r1; - - /* restore the kernel stack pointer */ - sp = [p1+(TASK_THREAD+THREAD_KSP)]; - - /* restore user stack pointer */ - p0 = [p1+(TASK_THREAD+THREAD_USP)]; - usp = p0; - - /* restore pc */ - p0 = [p1+(TASK_THREAD+THREAD_PC)]; - jump (p0); - - /* - * Following code actually lands up in a new (old) task. - */ - -_new_old_task: - (r7:4, p5:3) = [sp++]; - fp = [sp++]; - rets = [sp++]; - - /* - * When we come out of resume, r0 carries "old" task, because we are - * in "new" task. - */ - rts; -ENDPROC(_resume) - -ENTRY(_ret_from_exception) -#ifdef CONFIG_IPIPE - p2.l = _ipipe_percpu_domain; - p2.h = _ipipe_percpu_domain; - r0.l = _ipipe_root; - r0.h = _ipipe_root; - r2 = [p2]; - cc = r0 == r2; - if !cc jump 4f; /* not on behalf of the root domain, get out */ -#endif /* CONFIG_IPIPE */ - p2.l = lo(IPEND); - p2.h = hi(IPEND); - - csync; - r0 = [p2]; - [sp + PT_IPEND] = r0; - -1: - r2 = LO(~0x37) (Z); - r0 = r2 & r0; - cc = r0 == 0; - if !cc jump 4f; /* if not return to user mode, get out */ - - /* Make sure any pending system call or deferred exception - * return in ILAT for this process to get executed, otherwise - * in case context switch happens, system call of - * first process (i.e in ILAT) will be carried - * forward to the switched process - */ - - p2.l = lo(ILAT); - p2.h = hi(ILAT); - r0 = [p2]; - r1 = (EVT_IVG14 | EVT_IVG15) (z); - r0 = r0 & r1; - cc = r0 == 0; - if !cc jump 5f; - - /* Set the stack for the current process */ - r7 = sp; - r4.l = lo(ALIGN_PAGE_MASK); - r4.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r4; /* thread_info->flags */ - p5 = r7; - r7 = [p5 + TI_FLAGS]; - r4.l = lo(_TIF_WORK_MASK); - r4.h = hi(_TIF_WORK_MASK); - r7 = r7 & r4; - cc = r7 == 0; - if cc jump 4f; - - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _schedule_and_signal; - p1.h = _schedule_and_signal; - [p0] = p1; - csync; - raise 15; /* raise evt15 to do signal or reschedule */ -4: - r0 = syscfg; - bitclr(r0, SYSCFG_SSSTEP_P); /* Turn off single step */ - syscfg = r0; -5: - rts; -ENDPROC(_ret_from_exception) - -#if defined(CONFIG_PREEMPT) - -ENTRY(_up_to_irq14) -#if ANOMALY_05000281 || ANOMALY_05000461 - r0.l = lo(SAFE_USER_INSTRUCTION); - r0.h = hi(SAFE_USER_INSTRUCTION); - reti = r0; -#endif - -#ifdef CONFIG_DEBUG_HWERR - /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#else - /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#endif - sti r0; - - p0.l = lo(EVT14); - p0.h = hi(EVT14); - p1.l = _evt_up_evt14; - p1.h = _evt_up_evt14; - [p0] = p1; - csync; - - raise 14; -1: - jump 1b; -ENDPROC(_up_to_irq14) - -ENTRY(_evt_up_evt14) -#ifdef CONFIG_DEBUG_HWERR - r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); - sti r0; -#else - cli r0; -#endif -#ifdef CONFIG_TRACE_IRQFLAGS - [--sp] = rets; - sp += -12; - call _trace_hardirqs_off; - sp += 12; - rets = [sp++]; -#endif - [--sp] = RETI; - SP += 4; - - /* restore normal evt14 */ - p0.l = lo(EVT14); - p0.h = hi(EVT14); - p1.l = _evt_evt14; - p1.h = _evt_evt14; - [p0] = p1; - csync; - - rts; -ENDPROC(_evt_up_evt14) - -#endif - -#ifdef CONFIG_IPIPE - -_resume_kernel_from_int: - r1 = LO(~0x8000) (Z); - r1 = r0 & r1; - r0 = 1; - r0 = r1 - r0; - r2 = r1 & r0; - cc = r2 == 0; - /* Sync the root stage only from the outer interrupt level. */ - if !cc jump .Lnosync; - r0.l = ___ipipe_sync_root; - r0.h = ___ipipe_sync_root; - [--sp] = reti; - [--sp] = rets; - [--sp] = ( r7:4, p5:3 ); - SP += -12; - call ___ipipe_call_irqtail - SP += 12; - ( r7:4, p5:3 ) = [sp++]; - rets = [sp++]; - reti = [sp++]; -.Lnosync: - rts -#elif defined(CONFIG_PREEMPT) - -_resume_kernel_from_int: - /* check preempt_count */ - r7 = sp; - r4.l = lo(ALIGN_PAGE_MASK); - r4.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r4; - p5 = r7; - r7 = [p5 + TI_PREEMPT]; - cc = r7 == 0x0; - if !cc jump .Lreturn_to_kernel; -.Lneed_schedule: - r7 = [p5 + TI_FLAGS]; - r4.l = lo(_TIF_WORK_MASK); - r4.h = hi(_TIF_WORK_MASK); - r7 = r7 & r4; - cc = BITTST(r7, TIF_NEED_RESCHED); - if !cc jump .Lreturn_to_kernel; - /* - * let schedule done at level 15, otherwise sheduled process will run - * at high level and block low level interrupt - */ - r6 = reti; /* save reti */ - r5.l = .Lkernel_schedule; - r5.h = .Lkernel_schedule; - reti = r5; - rti; -.Lkernel_schedule: - [--sp] = rets; - sp += -12; - pseudo_long_call _preempt_schedule_irq, p4; - sp += 12; - rets = [sp++]; - - [--sp] = rets; - sp += -12; - /* up to irq14 so that reti after restore_all can return to irq15(kernel) */ - pseudo_long_call _up_to_irq14, p4; - sp += 12; - rets = [sp++]; - - reti = r6; /* restore reti so that origin process can return to interrupted point */ - - jump .Lneed_schedule; -#else - -#define _resume_kernel_from_int .Lreturn_to_kernel -#endif - -ENTRY(_return_from_int) - /* If someone else already raised IRQ 15, do nothing. */ - csync; - p2.l = lo(ILAT); - p2.h = hi(ILAT); - r0 = [p2]; - cc = bittst (r0, EVT_IVG15_P); - if cc jump .Lreturn_to_kernel; - - /* if not return to user mode, get out */ - p2.l = lo(IPEND); - p2.h = hi(IPEND); - r0 = [p2]; - r1 = 0x17(Z); - r2 = ~r1; - r2.h = 0; - r0 = r2 & r0; - r1 = 1; - r1 = r0 - r1; - r2 = r0 & r1; - cc = r2 == 0; - if !cc jump _resume_kernel_from_int; - - /* Lower the interrupt level to 15. */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _schedule_and_signal_from_int; - p1.h = _schedule_and_signal_from_int; - [p0] = p1; - csync; -#if ANOMALY_05000281 || ANOMALY_05000461 - r0.l = lo(SAFE_USER_INSTRUCTION); - r0.h = hi(SAFE_USER_INSTRUCTION); - reti = r0; -#endif - r0 = 0x801f (z); - STI r0; - raise 15; /* raise evt15 to do signal or reschedule */ - rti; -.Lreturn_to_kernel: - rts; -ENDPROC(_return_from_int) - -ENTRY(_lower_to_irq14) -#if ANOMALY_05000281 || ANOMALY_05000461 - r0.l = lo(SAFE_USER_INSTRUCTION); - r0.h = hi(SAFE_USER_INSTRUCTION); - reti = r0; -#endif - -#ifdef CONFIG_DEBUG_HWERR - /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#else - /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#endif - sti r0; - raise 14; - rti; -ENDPROC(_lower_to_irq14) - -ENTRY(_evt_evt14) -#ifdef CONFIG_DEBUG_HWERR - r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); - sti r0; -#else - cli r0; -#endif -#ifdef CONFIG_TRACE_IRQFLAGS - [--sp] = rets; - sp += -12; - call _trace_hardirqs_off; - sp += 12; - rets = [sp++]; -#endif - [--sp] = RETI; - SP += 4; - rts; -ENDPROC(_evt_evt14) - -ENTRY(_schedule_and_signal_from_int) - /* To end up here, vector 15 was changed - so we have to change it - * back. - */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _evt_system_call; - p1.h = _evt_system_call; - [p0] = p1; - csync; - - /* Set orig_p0 to -1 to indicate this isn't the end of a syscall. */ - r0 = -1 (x); - [sp + PT_ORIG_P0] = r0; - - p1 = rets; - [sp + PT_RESERVED] = p1; - -#ifdef CONFIG_TRACE_IRQFLAGS - /* trace_hardirqs_on() checks if all irqs are disabled. But here IRQ 15 - * is turned on, so disable all irqs. */ - cli r0; - sp += -12; - call _trace_hardirqs_on; - sp += 12; -#endif -#ifdef CONFIG_SMP - GET_PDA(p0, r0); /* Fetch current PDA (can't migrate to other CPU here) */ - r0 = [p0 + PDA_IRQFLAGS]; -#else - p0.l = _bfin_irq_flags; - p0.h = _bfin_irq_flags; - r0 = [p0]; -#endif - sti r0; - - /* finish the userspace "atomic" functions for it */ - r1.l = lo(FIXED_CODE_END); - r1.h = hi(FIXED_CODE_END); - r2 = [sp + PT_PC]; - cc = r1 <= r2; - if cc jump .Lresume_userspace (bp); - - r0 = sp; - sp += -12; - - pseudo_long_call _finish_atomic_sections, p5; - sp += 12; - jump.s .Lresume_userspace; -ENDPROC(_schedule_and_signal_from_int) - -ENTRY(_schedule_and_signal) - SAVE_CONTEXT_SYSCALL - /* To end up here, vector 15 was changed - so we have to change it - * back. - */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _evt_system_call; - p1.h = _evt_system_call; - [p0] = p1; - csync; - p0.l = 1f; - p0.h = 1f; - [sp + PT_RESERVED] = P0; - call .Lresume_userspace; -1: - RESTORE_CONTEXT - rti; -ENDPROC(_schedule_and_signal) - -/* We handle this 100% in exception space - to reduce overhead - * Only potiential problem is if the software buffer gets swapped out of the - * CPLB table - then double fault. - so we don't let this happen in other places - */ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND -ENTRY(_ex_trace_buff_full) - [--sp] = P3; - [--sp] = P2; - [--sp] = LC0; - [--sp] = LT0; - [--sp] = LB0; - P5.L = _trace_buff_offset; - P5.H = _trace_buff_offset; - P3 = [P5]; /* trace_buff_offset */ - P5.L = lo(TBUFSTAT); - P5.H = hi(TBUFSTAT); - R7 = [P5]; - R7 <<= 1; /* double, since we need to read twice */ - LC0 = R7; - R7 <<= 2; /* need to shift over again, - * to get the number of bytes */ - P5.L = lo(TBUF); - P5.H = hi(TBUF); - R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1; - - P2 = R7; - P3 = P3 + P2; - R7 = P3; - R7 = R7 & R6; - P3 = R7; - P2.L = _trace_buff_offset; - P2.H = _trace_buff_offset; - [P2] = P3; - - P2.L = _software_trace_buff; - P2.H = _software_trace_buff; - - LSETUP (.Lstart, .Lend) LC0; -.Lstart: - R7 = [P5]; /* read TBUF */ - P4 = P3 + P2; - [P4] = R7; - P3 += -4; - R7 = P3; - R7 = R7 & R6; -.Lend: - P3 = R7; - - LB0 = [sp++]; - LT0 = [sp++]; - LC0 = [sp++]; - P2 = [sp++]; - P3 = [sp++]; - jump _bfin_return_from_exception; -ENDPROC(_ex_trace_buff_full) - -#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4 -.data -#else -.section .l1.data.B -#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */ -ENTRY(_trace_buff_offset) - .long 0; -ALIGN -ENTRY(_software_trace_buff) - .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256); - .long 0 - .endr -#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */ - -#ifdef CONFIG_EARLY_PRINTK -__INIT -ENTRY(_early_trap) - SAVE_ALL_SYS - trace_buffer_stop(p0,r0); - - ANOMALY_283_315_WORKAROUND(p4, r5) - - /* Turn caches off, to ensure we don't get double exceptions */ - - P4.L = LO(IMEM_CONTROL); - P4.H = HI(IMEM_CONTROL); - - R5 = [P4]; /* Control Register*/ - BITCLR(R5,ENICPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - P4.L = LO(DMEM_CONTROL); - P4.H = HI(DMEM_CONTROL); - R5 = [P4]; - BITCLR(R5,ENDCPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - r1 = RETX; - - SP += -12; - call _early_trap_c; - SP += 12; -ENDPROC(_early_trap) -__FINIT -#endif /* CONFIG_EARLY_PRINTK */ - -/* - * Put these in the kernel data section - that should always be covered by - * a CPLB. This is needed to ensure we don't get double fault conditions - */ - -#ifdef CONFIG_SYSCALL_TAB_L1 -.section .l1.data -#else -.data -#endif - -ENTRY(_ex_table) - /* entry for each EXCAUSE[5:0] - * This table must be in sync with the table in ./kernel/traps.c - * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined - */ - .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */ - .long _ex_trap_c /* 0x01 - User Defined - Software breakpoint */ -#ifdef CONFIG_KGDB - .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection - and break signal trap */ -#else - .long _ex_replaceable /* 0x02 - User Defined */ -#endif - .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */ - .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */ - .long _ex_replaceable /* 0x05 - User Defined */ - .long _ex_replaceable /* 0x06 - User Defined */ - .long _ex_replaceable /* 0x07 - User Defined */ - .long _ex_replaceable /* 0x08 - User Defined */ - .long _ex_replaceable /* 0x09 - User Defined */ - .long _ex_replaceable /* 0x0A - User Defined */ - .long _ex_replaceable /* 0x0B - User Defined */ - .long _ex_replaceable /* 0x0C - User Defined */ - .long _ex_replaceable /* 0x0D - User Defined */ - .long _ex_replaceable /* 0x0E - User Defined */ - .long _ex_replaceable /* 0x0F - User Defined */ - .long _ex_single_step /* 0x10 - HW Single step */ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */ -#else - .long _ex_trap_c /* 0x11 - Trace Buffer Full */ -#endif - .long _ex_trap_c /* 0x12 - Reserved */ - .long _ex_trap_c /* 0x13 - Reserved */ - .long _ex_trap_c /* 0x14 - Reserved */ - .long _ex_trap_c /* 0x15 - Reserved */ - .long _ex_trap_c /* 0x16 - Reserved */ - .long _ex_trap_c /* 0x17 - Reserved */ - .long _ex_trap_c /* 0x18 - Reserved */ - .long _ex_trap_c /* 0x19 - Reserved */ - .long _ex_trap_c /* 0x1A - Reserved */ - .long _ex_trap_c /* 0x1B - Reserved */ - .long _ex_trap_c /* 0x1C - Reserved */ - .long _ex_trap_c /* 0x1D - Reserved */ - .long _ex_trap_c /* 0x1E - Reserved */ - .long _ex_trap_c /* 0x1F - Reserved */ - .long _ex_trap_c /* 0x20 - Reserved */ - .long _ex_trap_c /* 0x21 - Undefined Instruction */ - .long _ex_trap_c /* 0x22 - Illegal Instruction Combination */ - .long _ex_dviol /* 0x23 - Data CPLB Protection Violation */ - .long _ex_trap_c /* 0x24 - Data access misaligned */ - .long _ex_trap_c /* 0x25 - Unrecoverable Event */ - .long _ex_dmiss /* 0x26 - Data CPLB Miss */ - .long _ex_dmult /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero */ - .long _ex_trap_c /* 0x28 - Emulation Watchpoint */ - .long _ex_trap_c /* 0x29 - Instruction fetch access error (535 only) */ - .long _ex_trap_c /* 0x2A - Instruction fetch misaligned */ - .long _ex_trap_c /* 0x2B - Instruction CPLB protection Violation */ - .long _ex_icplb_miss /* 0x2C - Instruction CPLB miss */ - .long _ex_trap_c /* 0x2D - Instruction CPLB Multiple Hits */ - .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */ - .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */ - .long _ex_trap_c /* 0x2F - Reserved */ - .long _ex_trap_c /* 0x30 - Reserved */ - .long _ex_trap_c /* 0x31 - Reserved */ - .long _ex_trap_c /* 0x32 - Reserved */ - .long _ex_trap_c /* 0x33 - Reserved */ - .long _ex_trap_c /* 0x34 - Reserved */ - .long _ex_trap_c /* 0x35 - Reserved */ - .long _ex_trap_c /* 0x36 - Reserved */ - .long _ex_trap_c /* 0x37 - Reserved */ - .long _ex_trap_c /* 0x38 - Reserved */ - .long _ex_trap_c /* 0x39 - Reserved */ - .long _ex_trap_c /* 0x3A - Reserved */ - .long _ex_trap_c /* 0x3B - Reserved */ - .long _ex_trap_c /* 0x3C - Reserved */ - .long _ex_trap_c /* 0x3D - Reserved */ - .long _ex_trap_c /* 0x3E - Reserved */ - .long _ex_trap_c /* 0x3F - Reserved */ -END(_ex_table) - -ENTRY(_sys_call_table) - .long _sys_restart_syscall /* 0 */ - .long _sys_exit - .long _sys_ni_syscall /* fork */ - .long _sys_read - .long _sys_write - .long _sys_open /* 5 */ - .long _sys_close - .long _sys_ni_syscall /* old waitpid */ - .long _sys_creat - .long _sys_link - .long _sys_unlink /* 10 */ - .long _sys_execve - .long _sys_chdir - .long _sys_time - .long _sys_mknod - .long _sys_chmod /* 15 */ - .long _sys_chown /* chown16 */ - .long _sys_ni_syscall /* old break syscall holder */ - .long _sys_ni_syscall /* old stat */ - .long _sys_lseek - .long _sys_getpid /* 20 */ - .long _sys_mount - .long _sys_ni_syscall /* old umount */ - .long _sys_setuid - .long _sys_getuid - .long _sys_stime /* 25 */ - .long _sys_ptrace - .long _sys_alarm - .long _sys_ni_syscall /* old fstat */ - .long _sys_pause - .long _sys_ni_syscall /* old utime */ /* 30 */ - .long _sys_ni_syscall /* old stty syscall holder */ - .long _sys_ni_syscall /* old gtty syscall holder */ - .long _sys_access - .long _sys_nice - .long _sys_ni_syscall /* 35 */ /* old ftime syscall holder */ - .long _sys_sync - .long _sys_kill - .long _sys_rename - .long _sys_mkdir - .long _sys_rmdir /* 40 */ - .long _sys_dup - .long _sys_pipe - .long _sys_times - .long _sys_ni_syscall /* old prof syscall holder */ - .long _sys_brk /* 45 */ - .long _sys_setgid - .long _sys_getgid - .long _sys_ni_syscall /* old sys_signal */ - .long _sys_geteuid /* geteuid16 */ - .long _sys_getegid /* getegid16 */ /* 50 */ - .long _sys_acct - .long _sys_umount /* recycled never used phys() */ - .long _sys_ni_syscall /* old lock syscall holder */ - .long _sys_ioctl - .long _sys_fcntl /* 55 */ - .long _sys_ni_syscall /* old mpx syscall holder */ - .long _sys_setpgid - .long _sys_ni_syscall /* old ulimit syscall holder */ - .long _sys_ni_syscall /* old old uname */ - .long _sys_umask /* 60 */ - .long _sys_chroot - .long _sys_ustat - .long _sys_dup2 - .long _sys_getppid - .long _sys_getpgrp /* 65 */ - .long _sys_setsid - .long _sys_ni_syscall /* old sys_sigaction */ - .long _sys_sgetmask - .long _sys_ssetmask - .long _sys_setreuid /* setreuid16 */ /* 70 */ - .long _sys_setregid /* setregid16 */ - .long _sys_ni_syscall /* old sys_sigsuspend */ - .long _sys_ni_syscall /* old sys_sigpending */ - .long _sys_sethostname - .long _sys_setrlimit /* 75 */ - .long _sys_ni_syscall /* old getrlimit */ - .long _sys_getrusage - .long _sys_gettimeofday - .long _sys_settimeofday - .long _sys_getgroups /* getgroups16 */ /* 80 */ - .long _sys_setgroups /* setgroups16 */ - .long _sys_ni_syscall /* old_select */ - .long _sys_symlink - .long _sys_ni_syscall /* old lstat */ - .long _sys_readlink /* 85 */ - .long _sys_uselib - .long _sys_ni_syscall /* sys_swapon */ - .long _sys_reboot - .long _sys_ni_syscall /* old_readdir */ - .long _sys_ni_syscall /* sys_mmap */ /* 90 */ - .long _sys_munmap - .long _sys_truncate - .long _sys_ftruncate - .long _sys_fchmod - .long _sys_fchown /* fchown16 */ /* 95 */ - .long _sys_getpriority - .long _sys_setpriority - .long _sys_ni_syscall /* old profil syscall holder */ - .long _sys_statfs - .long _sys_fstatfs /* 100 */ - .long _sys_ni_syscall - .long _sys_ni_syscall /* old sys_socketcall */ - .long _sys_syslog - .long _sys_setitimer - .long _sys_getitimer /* 105 */ - .long _sys_newstat - .long _sys_newlstat - .long _sys_newfstat - .long _sys_ni_syscall /* old uname */ - .long _sys_ni_syscall /* iopl for i386 */ /* 110 */ - .long _sys_vhangup - .long _sys_ni_syscall /* obsolete idle() syscall */ - .long _sys_ni_syscall /* vm86old for i386 */ - .long _sys_wait4 - .long _sys_ni_syscall /* 115 */ /* sys_swapoff */ - .long _sys_sysinfo - .long _sys_ni_syscall /* old sys_ipc */ - .long _sys_fsync - .long _sys_ni_syscall /* old sys_sigreturn */ - .long _bfin_clone /* 120 */ - .long _sys_setdomainname - .long _sys_newuname - .long _sys_ni_syscall /* old sys_modify_ldt */ - .long _sys_adjtimex - .long _sys_mprotect /* 125 */ - .long _sys_ni_syscall /* old sys_sigprocmask */ - .long _sys_ni_syscall /* old "creat_module" */ - .long _sys_init_module - .long _sys_delete_module - .long _sys_ni_syscall /* 130: old "get_kernel_syms" */ - .long _sys_quotactl - .long _sys_getpgid - .long _sys_fchdir - .long _sys_bdflush - .long _sys_ni_syscall /* 135 */ /* sys_sysfs */ - .long _sys_personality - .long _sys_ni_syscall /* for afs_syscall */ - .long _sys_setfsuid /* setfsuid16 */ - .long _sys_setfsgid /* setfsgid16 */ - .long _sys_llseek /* 140 */ - .long _sys_getdents - .long _sys_ni_syscall /* sys_select */ - .long _sys_flock - .long _sys_msync - .long _sys_readv /* 145 */ - .long _sys_writev - .long _sys_getsid - .long _sys_fdatasync - .long _sys_sysctl - .long _sys_mlock /* 150 */ - .long _sys_munlock - .long _sys_mlockall - .long _sys_munlockall - .long _sys_sched_setparam - .long _sys_sched_getparam /* 155 */ - .long _sys_sched_setscheduler - .long _sys_sched_getscheduler - .long _sys_sched_yield - .long _sys_sched_get_priority_max - .long _sys_sched_get_priority_min /* 160 */ - .long _sys_sched_rr_get_interval - .long _sys_nanosleep - .long _sys_mremap - .long _sys_setresuid /* setresuid16 */ - .long _sys_getresuid /* getresuid16 */ /* 165 */ - .long _sys_ni_syscall /* for vm86 */ - .long _sys_ni_syscall /* old "query_module" */ - .long _sys_ni_syscall /* sys_poll */ - .long _sys_ni_syscall /* old nfsservctl */ - .long _sys_setresgid /* setresgid16 */ /* 170 */ - .long _sys_getresgid /* getresgid16 */ - .long _sys_prctl - .long _sys_rt_sigreturn - .long _sys_rt_sigaction - .long _sys_rt_sigprocmask /* 175 */ - .long _sys_rt_sigpending - .long _sys_rt_sigtimedwait - .long _sys_rt_sigqueueinfo - .long _sys_rt_sigsuspend - .long _sys_pread64 /* 180 */ - .long _sys_pwrite64 - .long _sys_lchown /* lchown16 */ - .long _sys_getcwd - .long _sys_capget - .long _sys_capset /* 185 */ - .long _sys_sigaltstack - .long _sys_sendfile - .long _sys_ni_syscall /* streams1 */ - .long _sys_ni_syscall /* streams2 */ - .long _sys_vfork /* 190 */ - .long _sys_getrlimit - .long _sys_mmap_pgoff - .long _sys_truncate64 - .long _sys_ftruncate64 - .long _sys_stat64 /* 195 */ - .long _sys_lstat64 - .long _sys_fstat64 - .long _sys_chown - .long _sys_getuid - .long _sys_getgid /* 200 */ - .long _sys_geteuid - .long _sys_getegid - .long _sys_setreuid - .long _sys_setregid - .long _sys_getgroups /* 205 */ - .long _sys_setgroups - .long _sys_fchown - .long _sys_setresuid - .long _sys_getresuid - .long _sys_setresgid /* 210 */ - .long _sys_getresgid - .long _sys_lchown - .long _sys_setuid - .long _sys_setgid - .long _sys_setfsuid /* 215 */ - .long _sys_setfsgid - .long _sys_pivot_root - .long _sys_mincore - .long _sys_madvise - .long _sys_getdents64 /* 220 */ - .long _sys_fcntl64 - .long _sys_ni_syscall /* reserved for TUX */ - .long _sys_ni_syscall - .long _sys_gettid - .long _sys_readahead /* 225 */ - .long _sys_setxattr - .long _sys_lsetxattr - .long _sys_fsetxattr - .long _sys_getxattr - .long _sys_lgetxattr /* 230 */ - .long _sys_fgetxattr - .long _sys_listxattr - .long _sys_llistxattr - .long _sys_flistxattr - .long _sys_removexattr /* 235 */ - .long _sys_lremovexattr - .long _sys_fremovexattr - .long _sys_tkill - .long _sys_sendfile64 - .long _sys_futex /* 240 */ - .long _sys_sched_setaffinity - .long _sys_sched_getaffinity - .long _sys_ni_syscall /* sys_set_thread_area */ - .long _sys_ni_syscall /* sys_get_thread_area */ - .long _sys_io_setup /* 245 */ - .long _sys_io_destroy - .long _sys_io_getevents - .long _sys_io_submit - .long _sys_io_cancel - .long _sys_ni_syscall /* 250 */ /* sys_alloc_hugepages */ - .long _sys_ni_syscall /* sys_freec_hugepages */ - .long _sys_exit_group - .long _sys_lookup_dcookie - .long _sys_bfin_spinlock - .long _sys_epoll_create /* 255 */ - .long _sys_epoll_ctl - .long _sys_epoll_wait - .long _sys_ni_syscall /* remap_file_pages */ - .long _sys_set_tid_address - .long _sys_timer_create /* 260 */ - .long _sys_timer_settime - .long _sys_timer_gettime - .long _sys_timer_getoverrun - .long _sys_timer_delete - .long _sys_clock_settime /* 265 */ - .long _sys_clock_gettime - .long _sys_clock_getres - .long _sys_clock_nanosleep - .long _sys_statfs64 - .long _sys_fstatfs64 /* 270 */ - .long _sys_tgkill - .long _sys_utimes - .long _sys_fadvise64_64 - .long _sys_ni_syscall /* vserver */ - .long _sys_mbind /* 275 */ - .long _sys_ni_syscall /* get_mempolicy */ - .long _sys_ni_syscall /* set_mempolicy */ - .long _sys_mq_open - .long _sys_mq_unlink - .long _sys_mq_timedsend /* 280 */ - .long _sys_mq_timedreceive - .long _sys_mq_notify - .long _sys_mq_getsetattr - .long _sys_ni_syscall /* kexec_load */ - .long _sys_waitid /* 285 */ - .long _sys_add_key - .long _sys_request_key - .long _sys_keyctl - .long _sys_ioprio_set - .long _sys_ioprio_get /* 290 */ - .long _sys_inotify_init - .long _sys_inotify_add_watch - .long _sys_inotify_rm_watch - .long _sys_ni_syscall /* migrate_pages */ - .long _sys_openat /* 295 */ - .long _sys_mkdirat - .long _sys_mknodat - .long _sys_fchownat - .long _sys_futimesat - .long _sys_fstatat64 /* 300 */ - .long _sys_unlinkat - .long _sys_renameat - .long _sys_linkat - .long _sys_symlinkat - .long _sys_readlinkat /* 305 */ - .long _sys_fchmodat - .long _sys_faccessat - .long _sys_pselect6 - .long _sys_ppoll - .long _sys_unshare /* 310 */ - .long _sys_sram_alloc - .long _sys_sram_free - .long _sys_dma_memcpy - .long _sys_accept - .long _sys_bind /* 315 */ - .long _sys_connect - .long _sys_getpeername - .long _sys_getsockname - .long _sys_getsockopt - .long _sys_listen /* 320 */ - .long _sys_recv - .long _sys_recvfrom - .long _sys_recvmsg - .long _sys_send - .long _sys_sendmsg /* 325 */ - .long _sys_sendto - .long _sys_setsockopt - .long _sys_shutdown - .long _sys_socket - .long _sys_socketpair /* 330 */ - .long _sys_semctl - .long _sys_semget - .long _sys_semop - .long _sys_msgctl - .long _sys_msgget /* 335 */ - .long _sys_msgrcv - .long _sys_msgsnd - .long _sys_shmat - .long _sys_shmctl - .long _sys_shmdt /* 340 */ - .long _sys_shmget - .long _sys_splice - .long _sys_sync_file_range - .long _sys_tee - .long _sys_vmsplice /* 345 */ - .long _sys_epoll_pwait - .long _sys_utimensat - .long _sys_signalfd - .long _sys_timerfd_create - .long _sys_eventfd /* 350 */ - .long _sys_pread64 - .long _sys_pwrite64 - .long _sys_fadvise64 - .long _sys_set_robust_list - .long _sys_get_robust_list /* 355 */ - .long _sys_fallocate - .long _sys_semtimedop - .long _sys_timerfd_settime - .long _sys_timerfd_gettime - .long _sys_signalfd4 /* 360 */ - .long _sys_eventfd2 - .long _sys_epoll_create1 - .long _sys_dup3 - .long _sys_pipe2 - .long _sys_inotify_init1 /* 365 */ - .long _sys_preadv - .long _sys_pwritev - .long _sys_rt_tgsigqueueinfo - .long _sys_perf_event_open - .long _sys_recvmmsg /* 370 */ - .long _sys_fanotify_init - .long _sys_fanotify_mark - .long _sys_prlimit64 - .long _sys_cacheflush - .long _sys_name_to_handle_at /* 375 */ - .long _sys_open_by_handle_at - .long _sys_clock_adjtime - .long _sys_syncfs - .long _sys_setns - .long _sys_sendmmsg /* 380 */ - .long _sys_process_vm_readv - .long _sys_process_vm_writev - .long _sys_kcmp - .long _sys_finit_module - .long _sys_sched_setattr /* 385 */ - .long _sys_sched_getattr - .long _sys_renameat2 - .long _sys_seccomp - .long _sys_getrandom - .long _sys_memfd_create /* 390 */ - .long _sys_bpf - .long _sys_execveat - - .rept NR_syscalls-(.-_sys_call_table)/4 - .long _sys_ni_syscall - .endr -END(_sys_call_table) diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S deleted file mode 100644 index 31515f0146f9..000000000000 --- a/arch/blackfin/mach-common/head.S +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Common Blackfin startup code - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include - -__INIT - -ENTRY(__init_clear_bss) - r2 = r2 - r1; - cc = r2 == 0; - if cc jump .L_bss_done; - r2 >>= 2; - p1 = r1; - p2 = r2; - lsetup (1f, 1f) lc0 = p2; -1: [p1++] = r0; -.L_bss_done: - rts; -ENDPROC(__init_clear_bss) - -ENTRY(__start) - /* R0: argument of command line string, passed from uboot, save it */ - R7 = R0; - - /* Enable Cycle Counter and Nesting Of Interrupts */ -#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES - R0 = SYSCFG_SNEN; -#else - R0 = SYSCFG_SNEN | SYSCFG_CCEN; -#endif - SYSCFG = R0; - - /* Optimization register tricks: keep a base value in the - * reserved P registers so we use the load/store with an - * offset syntax. R0 = [P5 + ]; - * P5 - core MMR base - * R6 - 0 - */ - r6 = 0; - p5.l = 0; - p5.h = hi(COREMMR_BASE); - - /* Zero out registers required by Blackfin ABI */ - - /* Disable circular buffers */ - L0 = r6; - L1 = r6; - L2 = r6; - L3 = r6; - - /* Disable hardware loops in case we were started by 'go' */ - LC0 = r6; - LC1 = r6; - - /* - * Clear ITEST_COMMAND and DTEST_COMMAND registers, - * Leaving these as non-zero can confuse the emulator - */ - [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6; - [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6; - CSYNC; - - trace_buffer_init(p0,r0); - - /* Turn off the icache */ - r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)]; - BITCLR (r1, ENICPLB_P); - [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1; - SSYNC; - - /* Turn off the dcache */ - r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)]; - BITCLR (r1, ENDCPLB_P); - [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1; - SSYNC; - - /* in case of double faults, save a few things */ - p1.l = _initial_pda; - p1.h = _initial_pda; - r4 = RETX; -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* Only save these if we are storing them, - * This happens here, since L1 gets clobbered - * below - */ - GET_PDA(p0, r0); - r0 = [p0 + PDA_DF_RETX]; - r1 = [p0 + PDA_DF_DCPLB]; - r2 = [p0 + PDA_DF_ICPLB]; - r3 = [p0 + PDA_DF_SEQSTAT]; - [p1 + PDA_INIT_DF_RETX] = r0; - [p1 + PDA_INIT_DF_DCPLB] = r1; - [p1 + PDA_INIT_DF_ICPLB] = r2; - [p1 + PDA_INIT_DF_SEQSTAT] = r3; -#endif - [p1 + PDA_INIT_RETX] = r4; - - /* Initialize stack pointer */ - sp.l = _init_thread_union + THREAD_SIZE; - sp.h = _init_thread_union + THREAD_SIZE; - fp = sp; - usp = sp; - -#ifdef CONFIG_EARLY_PRINTK - call _init_early_exception_vectors; - r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); - sti r0; -#endif - - r0 = r6; - /* Zero out all of the fun bss regions */ -#if L1_DATA_A_LENGTH > 0 - r1.l = __sbss_l1; - r1.h = __sbss_l1; - r2.l = __ebss_l1; - r2.h = __ebss_l1; - call __init_clear_bss -#endif -#if L1_DATA_B_LENGTH > 0 - r1.l = __sbss_b_l1; - r1.h = __sbss_b_l1; - r2.l = __ebss_b_l1; - r2.h = __ebss_b_l1; - call __init_clear_bss -#endif -#if L2_LENGTH > 0 - r1.l = __sbss_l2; - r1.h = __sbss_l2; - r2.l = __ebss_l2; - r2.h = __ebss_l2; - call __init_clear_bss -#endif - r1.l = ___bss_start; - r1.h = ___bss_start; - r2.l = ___bss_stop; - r2.h = ___bss_stop; - call __init_clear_bss - - /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ - call _bfin_relocate_l1_mem; - -#ifdef CONFIG_ROMKERNEL - call _bfin_relocate_xip_data; -#endif - -#ifdef CONFIG_BFIN_KERNEL_CLOCK - /* Only use on-chip scratch space for stack when absolutely required - * to avoid Anomaly 05000227 ... we know the init_clocks() func only - * uses L1 text and stack space and no other memory region. - */ -# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) - sp.l = lo(KERNEL_CLOCK_STACK); - sp.h = hi(KERNEL_CLOCK_STACK); - call _init_clocks; - sp = usp; /* usp hasn't been touched, so restore from there */ -#endif - - /* This section keeps the processor in supervisor mode - * during kernel boot. Switches to user mode at end of boot. - * See page 3-9 of Hardware Reference manual for documentation. - */ - - /* EVT15 = _real_start */ - - p1.l = _real_start; - p1.h = _real_start; - [p5 + (EVT15 - COREMMR_BASE)] = p1; - csync; - -#ifdef CONFIG_EARLY_PRINTK - r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z); -#else - r0 = EVT_IVG15 (z); -#endif - sti r0; - - raise 15; -#ifdef CONFIG_EARLY_PRINTK - p0.l = _early_trap; - p0.h = _early_trap; -#else - p0.l = .LWAIT_HERE; - p0.h = .LWAIT_HERE; -#endif - reti = p0; -#if ANOMALY_05000281 - nop; nop; nop; -#endif - rti; - -.LWAIT_HERE: - jump .LWAIT_HERE; -ENDPROC(__start) - -/* A little BF561 glue ... */ -#ifndef WDOG_CTL -# define WDOG_CTL WDOGA_CTL -#endif - -ENTRY(_real_start) - /* Enable nested interrupts */ - [--sp] = reti; - /* watchdog off for now */ - p0.l = lo(WDOG_CTL); - p0.h = hi(WDOG_CTL); - r0 = 0xAD6(z); - w[p0] = r0; - ssync; - /* Pass the u-boot arguments to the global value command line */ - R0 = R7; - call _cmdline_init; - - sp += -12 + 4; /* +4 is for reti loading above */ - call _init_pda - sp += 12; - jump.l _start_kernel; -ENDPROC(_real_start) - -__FINIT diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S deleted file mode 100644 index 469ce7282dc8..000000000000 --- a/arch/blackfin/mach-common/interrupt.S +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Interrupt Entries - * - * Copyright 2005-2009 Analog Devices Inc. - * D. Jeff Dionne - * Kenneth Albanowski - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -.extern _ret_from_exception - -#ifdef CONFIG_I_ENTRY_L1 -.section .l1.text -#else -.text -#endif - -.align 4 /* just in case */ - -/* Common interrupt entry code. First we do CLI, then push - * RETI, to keep interrupts disabled, but to allow this state to be changed - * by local_bh_enable. - * R0 contains the interrupt number, while R1 may contain the value of IPEND, - * or garbage if IPEND won't be needed by the ISR. */ -__common_int_entry: - [--sp] = fp; - [--sp] = usp; - - [--sp] = i0; - [--sp] = i1; - [--sp] = i2; - [--sp] = i3; - - [--sp] = m0; - [--sp] = m1; - [--sp] = m2; - [--sp] = m3; - - [--sp] = l0; - [--sp] = l1; - [--sp] = l2; - [--sp] = l3; - - [--sp] = b0; - [--sp] = b1; - [--sp] = b2; - [--sp] = b3; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = a1.x; - [--sp] = a1.w; - - [--sp] = LC0; - [--sp] = LC1; - [--sp] = LT0; - [--sp] = LT1; - [--sp] = LB0; - [--sp] = LB1; - - [--sp] = ASTAT; - - [--sp] = r0; /* Skip reserved */ - [--sp] = RETS; - r2 = RETI; - [--sp] = r2; - [--sp] = RETX; - [--sp] = RETN; - [--sp] = RETE; - [--sp] = SEQSTAT; - [--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */ - - /* Switch to other method of keeping interrupts disabled. */ -#ifdef CONFIG_DEBUG_HWERR - r1 = 0x3f; - sti r1; -#else - cli r1; -#endif -#ifdef CONFIG_TRACE_IRQFLAGS - [--sp] = r0; - sp += -12; - call _trace_hardirqs_off; - sp += 12; - r0 = [sp++]; -#endif - [--sp] = RETI; /* orig_pc */ - /* Clear all L registers. */ - r1 = 0 (x); - l0 = r1; - l1 = r1; - l2 = r1; - l3 = r1; -#ifdef CONFIG_FRAME_POINTER - fp = 0; -#endif - - ANOMALY_283_315_WORKAROUND(p5, r7) - - r1 = sp; - SP += -12; -#ifdef CONFIG_IPIPE - call ___ipipe_grab_irq - SP += 12; - cc = r0 == 0; - if cc jump .Lcommon_restore_context; -#else /* CONFIG_IPIPE */ - -#ifdef CONFIG_PREEMPT - r7 = sp; - r4.l = lo(ALIGN_PAGE_MASK); - r4.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r4; - p5 = r7; - r7 = [p5 + TI_PREEMPT]; /* get preempt count */ - r7 += 1; /* increment it */ - [p5 + TI_PREEMPT] = r7; -#endif - pseudo_long_call _do_irq, p2; - -#ifdef CONFIG_PREEMPT - r7 += -1; - [p5 + TI_PREEMPT] = r7; /* restore preempt count */ -#endif - - SP += 12; -#endif /* CONFIG_IPIPE */ - pseudo_long_call _return_from_int, p2; -.Lcommon_restore_context: - RESTORE_CONTEXT - rti; - -/* interrupt routine for ivhw - 5 */ -ENTRY(_evt_ivhw) - /* In case a single action kicks off multiple memory transactions, (like - * a cache line fetch, - this can cause multiple hardware errors, let's - * catch them all. First - make sure all the actions are complete, and - * the core sees the hardware errors. - */ - SSYNC; - SSYNC; - - SAVE_ALL_SYS -#ifdef CONFIG_FRAME_POINTER - fp = 0; -#endif - - ANOMALY_283_315_WORKAROUND(p5, r7) - - /* Handle all stacked hardware errors - * To make sure we don't hang forever, only do it 10 times - */ - R0 = 0; - R2 = 10; -1: - P0.L = LO(ILAT); - P0.H = HI(ILAT); - R1 = [P0]; - CC = BITTST(R1, EVT_IVHW_P); - IF ! CC JUMP 2f; - /* OK a hardware error is pending - clear it */ - R1 = EVT_IVHW_P; - [P0] = R1; - R0 += 1; - CC = R1 == R2; - if CC JUMP 2f; - JUMP 1b; -2: - # We are going to dump something out, so make sure we print IPEND properly - p2.l = lo(IPEND); - p2.h = hi(IPEND); - r0 = [p2]; - [sp + PT_IPEND] = r0; - - /* set the EXCAUSE to HWERR for trap_c */ - r0 = [sp + PT_SEQSTAT]; - R1.L = LO(VEC_HWERR); - R1.H = HI(VEC_HWERR); - R0 = R0 | R1; - [sp + PT_SEQSTAT] = R0; - - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - SP += -12; - pseudo_long_call _trap_c, p5; - SP += 12; - -#ifdef EBIU_ERRMST - /* make sure EBIU_ERRMST is clear */ - p0.l = LO(EBIU_ERRMST); - p0.h = HI(EBIU_ERRMST); - r0.l = (CORE_ERROR | CORE_MERROR); - w[p0] = r0.l; -#endif - - pseudo_long_call _ret_from_exception, p2; - -.Lcommon_restore_all_sys: - RESTORE_ALL_SYS - rti; -ENDPROC(_evt_ivhw) - -/* Interrupt routine for evt2 (NMI). - * For inner circle type details, please see: - * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi - */ -ENTRY(_evt_nmi) -#ifndef CONFIG_NMI_WATCHDOG -.weak _evt_nmi -#else - /* Not take account of CPLBs, this handler will not return */ - SAVE_ALL_SYS - r0 = sp; - r1 = retn; - [sp + PT_PC] = r1; - trace_buffer_save(p4,r5); - - ANOMALY_283_315_WORKAROUND(p4, r5) - - SP += -12; - call _do_nmi; - SP += 12; -1: - jump 1b; -#endif - rtn; -ENDPROC(_evt_nmi) - -/* interrupt routine for core timer - 6 */ -ENTRY(_evt_timer) - TIMER_INTERRUPT_ENTRY(EVT_IVTMR_P) - -/* interrupt routine for evt7 - 7 */ -ENTRY(_evt_evt7) - INTERRUPT_ENTRY(EVT_IVG7_P) -ENTRY(_evt_evt8) - INTERRUPT_ENTRY(EVT_IVG8_P) -ENTRY(_evt_evt9) - INTERRUPT_ENTRY(EVT_IVG9_P) -ENTRY(_evt_evt10) - INTERRUPT_ENTRY(EVT_IVG10_P) -ENTRY(_evt_evt11) - INTERRUPT_ENTRY(EVT_IVG11_P) -ENTRY(_evt_evt12) - INTERRUPT_ENTRY(EVT_IVG12_P) -ENTRY(_evt_evt13) - INTERRUPT_ENTRY(EVT_IVG13_P) - - - /* interrupt routine for system_call - 15 */ -ENTRY(_evt_system_call) - SAVE_CONTEXT_SYSCALL -#ifdef CONFIG_FRAME_POINTER - fp = 0; -#endif - pseudo_long_call _system_call, p2; - jump .Lcommon_restore_context; -ENDPROC(_evt_system_call) - -#ifdef CONFIG_IPIPE -/* - * __ipipe_call_irqtail: lowers the current priority level to EVT15 - * before running a user-defined routine, then raises the priority - * level to EVT14 to prepare the caller for a normal interrupt - * return through RTI. - * - * We currently use this feature in two occasions: - * - * - before branching to __ipipe_irq_tail_hook as requested by a high - * priority domain after the pipeline delivered an interrupt, - * e.g. such as Xenomai, in order to start its rescheduling - * procedure, since we may not switch tasks when IRQ levels are - * nested on the Blackfin, so we have to fake an interrupt return - * so that we may reschedule immediately. - * - * - before branching to __ipipe_sync_root(), in order to play any interrupt - * pending for the root domain (i.e. the Linux kernel). This lowers - * the core priority level enough so that Linux IRQ handlers may - * never delay interrupts handled by high priority domains; we defer - * those handlers until this point instead. This is a substitute - * to using a threaded interrupt model for the Linux kernel. - * - * r0: address of user-defined routine - * context: caller must have preempted EVT15, hw interrupts must be off. - */ -ENTRY(___ipipe_call_irqtail) - p0 = r0; - r0.l = 1f; - r0.h = 1f; - reti = r0; - rti; -1: - [--sp] = rets; - [--sp] = ( r7:4, p5:3 ); - sp += -12; - call (p0); - sp += 12; - ( r7:4, p5:3 ) = [sp++]; - rets = [sp++]; - -#ifdef CONFIG_DEBUG_HWERR - /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IVHW | \ - EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#else - /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | \ - EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#endif - sti r0; - raise 14; /* Branches to _evt_evt14 */ -2: - jump 2b; /* Likely paranoid. */ -ENDPROC(___ipipe_call_irqtail) - -#endif /* CONFIG_IPIPE */ diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c deleted file mode 100644 index e81a5b7dabdc..000000000000 --- a/arch/blackfin/mach-common/ints-priority.c +++ /dev/null @@ -1,1366 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2004-2009 Analog Devices Inc. - * 2003 Bas Vermeulen - * 2002 Arcturus Networks Inc. MaTed - * 2000-2001 Lineo, Inc. D. Jefff Dionne - * 1999 D. Jeff Dionne - * 1996 Roman Zippel - * - * Licensed under the GPL-2 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_IPIPE -#include -#endif -#include -#include -#include -#include -#include -#include - -/* - * NOTES: - * - we have separated the physical Hardware interrupt from the - * levels that the LINUX kernel sees (see the description in irq.h) - * - - */ - -#ifndef CONFIG_SMP -/* Initialize this to an actual value to force it into the .data - * section so that we know it is properly initialized at entry into - * the kernel but before bss is initialized to zero (which is where - * it would live otherwise). The 0x1f magic represents the IRQs we - * cannot actually mask out in hardware. - */ -unsigned long bfin_irq_flags = 0x1f; -EXPORT_SYMBOL(bfin_irq_flags); -#endif - -#ifdef CONFIG_PM -unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ -unsigned vr_wakeup; -#endif - -#ifndef SEC_GCTL -static struct ivgx { - /* irq number for request_irq, available in mach-bf5xx/irq.h */ - unsigned int irqno; - /* corresponding bit in the SIC_ISR register */ - unsigned int isrflag; -} ivg_table[NR_PERI_INTS]; - -static struct ivg_slice { - /* position of first irq in ivg_table for given ivg */ - struct ivgx *ifirst; - struct ivgx *istop; -} ivg7_13[IVG13 - IVG7 + 1]; - - -/* - * Search SIC_IAR and fill tables with the irqvalues - * and their positions in the SIC_ISR register. - */ -static void __init search_IAR(void) -{ - unsigned ivg, irq_pos = 0; - for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { - int irqN; - - ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; - - for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { - int irqn; - u32 iar = - bfin_read32((unsigned long *)SIC_IAR0 + -#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ - defined(CONFIG_BF538) || defined(CONFIG_BF539) - ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) -#else - (irqN >> 3) -#endif - ); - for (irqn = irqN; irqn < irqN + 4; ++irqn) { - int iar_shift = (irqn & 7) * 4; - if (ivg == (0xf & (iar >> iar_shift))) { - ivg_table[irq_pos].irqno = IVG7 + irqn; - ivg_table[irq_pos].isrflag = 1 << (irqn % 32); - ivg7_13[ivg].istop++; - irq_pos++; - } - } - } - } -} -#endif - -/* - * This is for core internal IRQs - */ -void bfin_ack_noop(struct irq_data *d) -{ - /* Dummy function. */ -} - -static void bfin_core_mask_irq(struct irq_data *d) -{ - bfin_irq_flags &= ~(1 << d->irq); - if (!hard_irqs_disabled()) - hard_local_irq_enable(); -} - -static void bfin_core_unmask_irq(struct irq_data *d) -{ - bfin_irq_flags |= 1 << d->irq; - /* - * If interrupts are enabled, IMASK must contain the same value - * as bfin_irq_flags. Make sure that invariant holds. If interrupts - * are currently disabled we need not do anything; one of the - * callers will take care of setting IMASK to the proper value - * when reenabling interrupts. - * local_irq_enable just does "STI bfin_irq_flags", so it's exactly - * what we need. - */ - if (!hard_irqs_disabled()) - hard_local_irq_enable(); - return; -} - -#ifndef SEC_GCTL -void bfin_internal_mask_irq(unsigned int irq) -{ - unsigned long flags = hard_local_irq_save(); -#ifdef SIC_IMASK0 - unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; - unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; - bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & - ~(1 << mask_bit)); -# if defined(CONFIG_SMP) || defined(CONFIG_ICC) - bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & - ~(1 << mask_bit)); -# endif -#else - bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & - ~(1 << BFIN_SYSIRQ(irq))); -#endif /* end of SIC_IMASK0 */ - hard_local_irq_restore(flags); -} - -static void bfin_internal_mask_irq_chip(struct irq_data *d) -{ - bfin_internal_mask_irq(d->irq); -} - -#ifdef CONFIG_SMP -void bfin_internal_unmask_irq_affinity(unsigned int irq, - const struct cpumask *affinity) -#else -void bfin_internal_unmask_irq(unsigned int irq) -#endif -{ - unsigned long flags = hard_local_irq_save(); - -#ifdef SIC_IMASK0 - unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; - unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; -# ifdef CONFIG_SMP - if (cpumask_test_cpu(0, affinity)) -# endif - bfin_write_SIC_IMASK(mask_bank, - bfin_read_SIC_IMASK(mask_bank) | - (1 << mask_bit)); -# ifdef CONFIG_SMP - if (cpumask_test_cpu(1, affinity)) - bfin_write_SICB_IMASK(mask_bank, - bfin_read_SICB_IMASK(mask_bank) | - (1 << mask_bit)); -# endif -#else - bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | - (1 << BFIN_SYSIRQ(irq))); -#endif - hard_local_irq_restore(flags); -} - -#ifdef CONFIG_SMP -static void bfin_internal_unmask_irq_chip(struct irq_data *d) -{ - bfin_internal_unmask_irq_affinity(d->irq, - irq_data_get_affinity_mask(d)); -} - -static int bfin_internal_set_affinity(struct irq_data *d, - const struct cpumask *mask, bool force) -{ - bfin_internal_mask_irq(d->irq); - bfin_internal_unmask_irq_affinity(d->irq, mask); - - return 0; -} -#else -static void bfin_internal_unmask_irq_chip(struct irq_data *d) -{ - bfin_internal_unmask_irq(d->irq); -} -#endif - -#if defined(CONFIG_PM) -int bfin_internal_set_wake(unsigned int irq, unsigned int state) -{ - u32 bank, bit, wakeup = 0; - unsigned long flags; - bank = BFIN_SYSIRQ(irq) / 32; - bit = BFIN_SYSIRQ(irq) % 32; - - switch (irq) { -#ifdef IRQ_RTC - case IRQ_RTC: - wakeup |= WAKE; - break; -#endif -#ifdef IRQ_CAN0_RX - case IRQ_CAN0_RX: - wakeup |= CANWE; - break; -#endif -#ifdef IRQ_CAN1_RX - case IRQ_CAN1_RX: - wakeup |= CANWE; - break; -#endif -#ifdef IRQ_USB_INT0 - case IRQ_USB_INT0: - wakeup |= USBWE; - break; -#endif -#ifdef CONFIG_BF54x - case IRQ_CNT: - wakeup |= ROTWE; - break; -#endif - default: - break; - } - - flags = hard_local_irq_save(); - - if (state) { - bfin_sic_iwr[bank] |= (1 << bit); - vr_wakeup |= wakeup; - - } else { - bfin_sic_iwr[bank] &= ~(1 << bit); - vr_wakeup &= ~wakeup; - } - - hard_local_irq_restore(flags); - - return 0; -} - -static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) -{ - return bfin_internal_set_wake(d->irq, state); -} -#else -inline int bfin_internal_set_wake(unsigned int irq, unsigned int state) -{ - return 0; -} -# define bfin_internal_set_wake_chip NULL -#endif - -#else /* SEC_GCTL */ -static void bfin_sec_preflow_handler(struct irq_data *d) -{ - unsigned long flags = hard_local_irq_save(); - unsigned int sid = BFIN_SYSIRQ(d->irq); - - bfin_write_SEC_SCI(0, SEC_CSID, sid); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_mask_ack_irq(struct irq_data *d) -{ - unsigned long flags = hard_local_irq_save(); - unsigned int sid = BFIN_SYSIRQ(d->irq); - - bfin_write_SEC_SCI(0, SEC_CSID, sid); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_unmask_irq(struct irq_data *d) -{ - unsigned long flags = hard_local_irq_save(); - unsigned int sid = BFIN_SYSIRQ(d->irq); - - bfin_write32(SEC_END, sid); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_enable_ssi(unsigned int sid) -{ - unsigned long flags = hard_local_irq_save(); - uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); - - reg_sctl |= SEC_SCTL_SRC_EN; - bfin_write_SEC_SCTL(sid, reg_sctl); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_disable_ssi(unsigned int sid) -{ - unsigned long flags = hard_local_irq_save(); - uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); - - reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN); - bfin_write_SEC_SCTL(sid, reg_sctl); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid) -{ - unsigned long flags = hard_local_irq_save(); - uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); - - reg_sctl &= ((uint32_t)~SEC_SCTL_CTG); - bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG)); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_enable_sci(unsigned int sid) -{ - unsigned long flags = hard_local_irq_save(); - uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); - - if (sid == BFIN_SYSIRQ(IRQ_WATCH0)) - reg_sctl |= SEC_SCTL_FAULT_EN; - else - reg_sctl |= SEC_SCTL_INT_EN; - bfin_write_SEC_SCTL(sid, reg_sctl); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_disable_sci(unsigned int sid) -{ - unsigned long flags = hard_local_irq_save(); - uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); - - reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN); - bfin_write_SEC_SCTL(sid, reg_sctl); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_enable(struct irq_data *d) -{ - unsigned long flags = hard_local_irq_save(); - unsigned int sid = BFIN_SYSIRQ(d->irq); - - bfin_sec_enable_sci(sid); - bfin_sec_enable_ssi(sid); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_disable(struct irq_data *d) -{ - unsigned long flags = hard_local_irq_save(); - unsigned int sid = BFIN_SYSIRQ(d->irq); - - bfin_sec_disable_sci(sid); - bfin_sec_disable_ssi(sid); - - hard_local_irq_restore(flags); -} - -static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority) -{ - unsigned long flags = hard_local_irq_save(); - uint32_t reg_sctl; - int i; - - bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels); - - for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) { - reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO; - reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET; - bfin_write_SEC_SCTL(i, reg_sctl); - } - - hard_local_irq_restore(flags); -} - -void bfin_sec_raise_irq(unsigned int irq) -{ - unsigned long flags = hard_local_irq_save(); - unsigned int sid = BFIN_SYSIRQ(irq); - - bfin_write32(SEC_RAISE, sid); - - hard_local_irq_restore(flags); -} - -static void init_software_driven_irq(void) -{ - bfin_sec_set_ssi_coreid(34, 0); - bfin_sec_set_ssi_coreid(35, 1); - - bfin_sec_enable_sci(35); - bfin_sec_enable_ssi(35); - bfin_sec_set_ssi_coreid(36, 0); - bfin_sec_set_ssi_coreid(37, 1); - bfin_sec_enable_sci(37); - bfin_sec_enable_ssi(37); -} - -void handle_sec_sfi_fault(uint32_t gstat) -{ - -} - -void handle_sec_sci_fault(uint32_t gstat) -{ - uint32_t core_id; - uint32_t cstat; - - core_id = gstat & SEC_GSTAT_SCI; - cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT); - if (cstat & SEC_CSTAT_ERR) { - switch (cstat & SEC_CSTAT_ERRC) { - case SEC_CSTAT_ACKERR: - printk(KERN_DEBUG "sec ack err\n"); - break; - default: - printk(KERN_DEBUG "sec sci unknown err\n"); - } - } - -} - -void handle_sec_ssi_fault(uint32_t gstat) -{ - uint32_t sid; - uint32_t sstat; - - sid = gstat & SEC_GSTAT_SID; - sstat = bfin_read_SEC_SSTAT(sid); - -} - -void handle_sec_fault(uint32_t sec_gstat) -{ - if (sec_gstat & SEC_GSTAT_ERR) { - - switch (sec_gstat & SEC_GSTAT_ERRC) { - case 0: - handle_sec_sfi_fault(sec_gstat); - break; - case SEC_GSTAT_SCIERR: - handle_sec_sci_fault(sec_gstat); - break; - case SEC_GSTAT_SSIERR: - handle_sec_ssi_fault(sec_gstat); - break; - } - - - } -} - -static struct irqaction bfin_fault_irq = { - .name = "Blackfin fault", -}; - -static irqreturn_t bfin_fault_routine(int irq, void *data) -{ - struct pt_regs *fp = get_irq_regs(); - - switch (irq) { - case IRQ_C0_DBL_FAULT: - double_fault_c(fp); - break; - case IRQ_C0_HW_ERR: - dump_bfin_process(fp); - dump_bfin_mem(fp); - show_regs(fp); - printk(KERN_NOTICE "Kernel Stack\n"); - show_stack(current, NULL); - print_modules(); - panic("Core 0 hardware error"); - break; - case IRQ_C0_NMI_L1_PARITY_ERR: - panic("Core 0 NMI L1 parity error"); - break; - case IRQ_SEC_ERR: - pr_err("SEC error\n"); - handle_sec_fault(bfin_read32(SEC_GSTAT)); - break; - default: - panic("Unknown fault %d", irq); - } - - return IRQ_HANDLED; -} -#endif /* SEC_GCTL */ - -static struct irq_chip bfin_core_irqchip = { - .name = "CORE", - .irq_mask = bfin_core_mask_irq, - .irq_unmask = bfin_core_unmask_irq, -}; - -#ifndef SEC_GCTL -static struct irq_chip bfin_internal_irqchip = { - .name = "INTN", - .irq_mask = bfin_internal_mask_irq_chip, - .irq_unmask = bfin_internal_unmask_irq_chip, - .irq_disable = bfin_internal_mask_irq_chip, - .irq_enable = bfin_internal_unmask_irq_chip, -#ifdef CONFIG_SMP - .irq_set_affinity = bfin_internal_set_affinity, -#endif - .irq_set_wake = bfin_internal_set_wake_chip, -}; -#else -static struct irq_chip bfin_sec_irqchip = { - .name = "SEC", - .irq_mask_ack = bfin_sec_mask_ack_irq, - .irq_mask = bfin_sec_mask_ack_irq, - .irq_unmask = bfin_sec_unmask_irq, - .irq_eoi = bfin_sec_unmask_irq, - .irq_disable = bfin_sec_disable, - .irq_enable = bfin_sec_enable, -}; -#endif - -void bfin_handle_irq(unsigned irq) -{ -#ifdef CONFIG_IPIPE - struct pt_regs regs; /* Contents not used. */ - ipipe_trace_irq_entry(irq); - __ipipe_handle_irq(irq, ®s); - ipipe_trace_irq_exit(irq); -#else /* !CONFIG_IPIPE */ - generic_handle_irq(irq); -#endif /* !CONFIG_IPIPE */ -} - -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) -static int mac_stat_int_mask; - -static void bfin_mac_status_ack_irq(unsigned int irq) -{ - switch (irq) { - case IRQ_MAC_MMCINT: - bfin_write_EMAC_MMC_TIRQS( - bfin_read_EMAC_MMC_TIRQE() & - bfin_read_EMAC_MMC_TIRQS()); - bfin_write_EMAC_MMC_RIRQS( - bfin_read_EMAC_MMC_RIRQE() & - bfin_read_EMAC_MMC_RIRQS()); - break; - case IRQ_MAC_RXFSINT: - bfin_write_EMAC_RX_STKY( - bfin_read_EMAC_RX_IRQE() & - bfin_read_EMAC_RX_STKY()); - break; - case IRQ_MAC_TXFSINT: - bfin_write_EMAC_TX_STKY( - bfin_read_EMAC_TX_IRQE() & - bfin_read_EMAC_TX_STKY()); - break; - case IRQ_MAC_WAKEDET: - bfin_write_EMAC_WKUP_CTL( - bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS); - break; - default: - /* These bits are W1C */ - bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT)); - break; - } -} - -static void bfin_mac_status_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq; - - mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); -#ifdef BF537_FAMILY - switch (irq) { - case IRQ_MAC_PHYINT: - bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); - break; - default: - break; - } -#else - if (!mac_stat_int_mask) - bfin_internal_mask_irq(IRQ_MAC_ERROR); -#endif - bfin_mac_status_ack_irq(irq); -} - -static void bfin_mac_status_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq; - -#ifdef BF537_FAMILY - switch (irq) { - case IRQ_MAC_PHYINT: - bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); - break; - default: - break; - } -#else - if (!mac_stat_int_mask) - bfin_internal_unmask_irq(IRQ_MAC_ERROR); -#endif - mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT); -} - -#ifdef CONFIG_PM -int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) -{ -#ifdef BF537_FAMILY - return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); -#else - return bfin_internal_set_wake(IRQ_MAC_ERROR, state); -#endif -} -#else -# define bfin_mac_status_set_wake NULL -#endif - -static struct irq_chip bfin_mac_status_irqchip = { - .name = "MACST", - .irq_mask = bfin_mac_status_mask_irq, - .irq_unmask = bfin_mac_status_unmask_irq, - .irq_set_wake = bfin_mac_status_set_wake, -}; - -void bfin_demux_mac_status_irq(struct irq_desc *inta_desc) -{ - int i, irq = 0; - u32 status = bfin_read_EMAC_SYSTAT(); - - for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) - if (status & (1L << i)) { - irq = IRQ_MAC_PHYINT + i; - break; - } - - if (irq) { - if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) { - bfin_handle_irq(irq); - } else { - bfin_mac_status_ack_irq(irq); - pr_debug("IRQ %d:" - " MASKED MAC ERROR INTERRUPT ASSERTED\n", - irq); - } - } else - printk(KERN_ERR - "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" - " INTERRUPT ASSERTED BUT NO SOURCE FOUND" - "(EMAC_SYSTAT=0x%X)\n", - __func__, __FILE__, __LINE__, status); -} -#endif - -static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle) -{ -#ifdef CONFIG_IPIPE - handle = handle_level_irq; -#endif - irq_set_handler_locked(d, handle); -} - -#ifdef CONFIG_GPIO_ADI - -static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); - -static void bfin_gpio_ack_irq(struct irq_data *d) -{ - /* AFAIK ack_irq in case mask_ack is provided - * get's only called for edge sense irqs - */ - set_gpio_data(irq_to_gpio(d->irq), 0); -} - -static void bfin_gpio_mask_ack_irq(struct irq_data *d) -{ - unsigned int irq = d->irq; - u32 gpionr = irq_to_gpio(irq); - - if (!irqd_is_level_type(d)) - set_gpio_data(gpionr, 0); - - set_gpio_maska(gpionr, 0); -} - -static void bfin_gpio_mask_irq(struct irq_data *d) -{ - set_gpio_maska(irq_to_gpio(d->irq), 0); -} - -static void bfin_gpio_unmask_irq(struct irq_data *d) -{ - set_gpio_maska(irq_to_gpio(d->irq), 1); -} - -static unsigned int bfin_gpio_irq_startup(struct irq_data *d) -{ - u32 gpionr = irq_to_gpio(d->irq); - - if (__test_and_set_bit(gpionr, gpio_enabled)) - bfin_gpio_irq_prepare(gpionr); - - bfin_gpio_unmask_irq(d); - - return 0; -} - -static void bfin_gpio_irq_shutdown(struct irq_data *d) -{ - u32 gpionr = irq_to_gpio(d->irq); - - bfin_gpio_mask_irq(d); - __clear_bit(gpionr, gpio_enabled); - bfin_gpio_irq_free(gpionr); -} - -static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) -{ - unsigned int irq = d->irq; - int ret; - char buf[16]; - u32 gpionr = irq_to_gpio(irq); - - if (type == IRQ_TYPE_PROBE) { - /* only probe unenabled GPIO interrupt lines */ - if (test_bit(gpionr, gpio_enabled)) - return 0; - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - } - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | - IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - - snprintf(buf, 16, "gpio-irq%d", irq); - ret = bfin_gpio_irq_request(gpionr, buf); - if (ret) - return ret; - - if (__test_and_set_bit(gpionr, gpio_enabled)) - bfin_gpio_irq_prepare(gpionr); - - } else { - __clear_bit(gpionr, gpio_enabled); - return 0; - } - - set_gpio_inen(gpionr, 0); - set_gpio_dir(gpionr, 0); - - if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - set_gpio_both(gpionr, 1); - else - set_gpio_both(gpionr, 0); - - if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) - set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ - else - set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - set_gpio_edge(gpionr, 1); - set_gpio_inen(gpionr, 1); - set_gpio_data(gpionr, 0); - - } else { - set_gpio_edge(gpionr, 0); - set_gpio_inen(gpionr, 1); - } - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - bfin_set_irq_handler(d, handle_edge_irq); - else - bfin_set_irq_handler(d, handle_level_irq); - - return 0; -} - -static void bfin_demux_gpio_block(unsigned int irq) -{ - unsigned int gpio, mask; - - gpio = irq_to_gpio(irq); - mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); - - while (mask) { - if (mask & 1) - bfin_handle_irq(irq); - irq++; - mask >>= 1; - } -} - -void bfin_demux_gpio_irq(struct irq_desc *desc) -{ - unsigned int inta_irq = irq_desc_get_irq(desc); - unsigned int irq; - - switch (inta_irq) { -#if defined(BF537_FAMILY) - case IRQ_PF_INTA_PG_INTA: - bfin_demux_gpio_block(IRQ_PF0); - irq = IRQ_PG0; - break; - case IRQ_PH_INTA_MAC_RX: - irq = IRQ_PH0; - break; -#elif defined(BF533_FAMILY) - case IRQ_PROG_INTA: - irq = IRQ_PF0; - break; -#elif defined(BF538_FAMILY) - case IRQ_PORTF_INTA: - irq = IRQ_PF0; - break; -#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) - case IRQ_PORTF_INTA: - irq = IRQ_PF0; - break; - case IRQ_PORTG_INTA: - irq = IRQ_PG0; - break; - case IRQ_PORTH_INTA: - irq = IRQ_PH0; - break; -#elif defined(CONFIG_BF561) - case IRQ_PROG0_INTA: - irq = IRQ_PF0; - break; - case IRQ_PROG1_INTA: - irq = IRQ_PF16; - break; - case IRQ_PROG2_INTA: - irq = IRQ_PF32; - break; -#endif - default: - BUG(); - return; - } - - bfin_demux_gpio_block(irq); -} - -#ifdef CONFIG_PM - -static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) -{ - return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); -} - -#else - -# define bfin_gpio_set_wake NULL - -#endif - -static struct irq_chip bfin_gpio_irqchip = { - .name = "GPIO", - .irq_ack = bfin_gpio_ack_irq, - .irq_mask = bfin_gpio_mask_irq, - .irq_mask_ack = bfin_gpio_mask_ack_irq, - .irq_unmask = bfin_gpio_unmask_irq, - .irq_disable = bfin_gpio_mask_irq, - .irq_enable = bfin_gpio_unmask_irq, - .irq_set_type = bfin_gpio_irq_type, - .irq_startup = bfin_gpio_irq_startup, - .irq_shutdown = bfin_gpio_irq_shutdown, - .irq_set_wake = bfin_gpio_set_wake, -}; - -#endif - -#ifdef CONFIG_PM - -#ifdef SEC_GCTL -static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS]; - -static int sec_suspend(void) -{ - u32 bank; - - for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) - save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0)); - return 0; -} - -static void sec_resume(void) -{ - u32 bank; - - bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); - udelay(100); - bfin_write_SEC_GCTL(SEC_GCTL_EN); - bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); - - for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) - bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]); -} - -static struct syscore_ops sec_pm_syscore_ops = { - .suspend = sec_suspend, - .resume = sec_resume, -}; -#endif - -#endif - -void init_exception_vectors(void) -{ - /* cannot program in software: - * evt0 - emulation (jtag) - * evt1 - reset - */ - bfin_write_EVT2(evt_nmi); - bfin_write_EVT3(trap); - bfin_write_EVT5(evt_ivhw); - bfin_write_EVT6(evt_timer); - bfin_write_EVT7(evt_evt7); - bfin_write_EVT8(evt_evt8); - bfin_write_EVT9(evt_evt9); - bfin_write_EVT10(evt_evt10); - bfin_write_EVT11(evt_evt11); - bfin_write_EVT12(evt_evt12); - bfin_write_EVT13(evt_evt13); - bfin_write_EVT14(evt_evt14); - bfin_write_EVT15(evt_system_call); - CSYNC(); -} - -#ifndef SEC_GCTL -/* - * This function should be called during kernel startup to initialize - * the BFin IRQ handling routines. - */ - -int __init init_arch_irq(void) -{ - int irq; - unsigned long ilat = 0; - - /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ -#ifdef SIC_IMASK0 - bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); - bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); -# ifdef SIC_IMASK2 - bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); -# endif -# if defined(CONFIG_SMP) || defined(CONFIG_ICC) - bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); - bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); -# endif -#else - bfin_write_SIC_IMASK(SIC_UNMASK_ALL); -#endif - - local_irq_disable(); - - for (irq = 0; irq <= SYS_IRQS; irq++) { - if (irq <= IRQ_CORETMR) - irq_set_chip(irq, &bfin_core_irqchip); - else - irq_set_chip(irq, &bfin_internal_irqchip); - - switch (irq) { -#if !BFIN_GPIO_PINT -#if defined(BF537_FAMILY) - case IRQ_PH_INTA_MAC_RX: - case IRQ_PF_INTA_PG_INTA: -#elif defined(BF533_FAMILY) - case IRQ_PROG_INTA: -#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) - case IRQ_PORTF_INTA: - case IRQ_PORTG_INTA: - case IRQ_PORTH_INTA: -#elif defined(CONFIG_BF561) - case IRQ_PROG0_INTA: - case IRQ_PROG1_INTA: - case IRQ_PROG2_INTA: -#elif defined(BF538_FAMILY) - case IRQ_PORTF_INTA: -#endif - irq_set_chained_handler(irq, bfin_demux_gpio_irq); - break; -#endif -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) - case IRQ_MAC_ERROR: - irq_set_chained_handler(irq, - bfin_demux_mac_status_irq); - break; -#endif -#if defined(CONFIG_SMP) || defined(CONFIG_ICC) - case IRQ_SUPPLE_0: - case IRQ_SUPPLE_1: - irq_set_handler(irq, handle_percpu_irq); - break; -#endif - -#ifdef CONFIG_TICKSOURCE_CORETMR - case IRQ_CORETMR: -# ifdef CONFIG_SMP - irq_set_handler(irq, handle_percpu_irq); -# else - irq_set_handler(irq, handle_simple_irq); -# endif - break; -#endif - -#ifdef CONFIG_TICKSOURCE_GPTMR0 - case IRQ_TIMER0: - irq_set_handler(irq, handle_simple_irq); - break; -#endif - - default: -#ifdef CONFIG_IPIPE - irq_set_handler(irq, handle_level_irq); -#else - irq_set_handler(irq, handle_simple_irq); -#endif - break; - } - } - - init_mach_irq(); - -#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) - for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) - irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, - handle_level_irq); -#endif - /* if configured as edge, then will be changed to do_edge_IRQ */ -#ifdef CONFIG_GPIO_ADI - for (irq = GPIO_IRQ_BASE; - irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) - irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, - handle_level_irq); -#endif - bfin_write_IMASK(0); - CSYNC(); - ilat = bfin_read_ILAT(); - CSYNC(); - bfin_write_ILAT(ilat); - CSYNC(); - - printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); - /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, - * local_irq_enable() - */ - program_IAR(); - /* Therefore it's better to setup IARs before interrupts enabled */ - search_IAR(); - - /* Enable interrupts IVG7-15 */ - bfin_irq_flags |= IMASK_IVG15 | - IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | - IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; - - - /* This implicitly covers ANOMALY_05000171 - * Boot-ROM code modifies SICA_IWRx wakeup registers - */ -#ifdef SIC_IWR0 - bfin_write_SIC_IWR0(IWR_DISABLE_ALL); -# ifdef SIC_IWR1 - /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which - * will screw up the bootrom as it relies on MDMA0/1 waking it - * up from IDLE instructions. See this report for more info: - * http://blackfin.uclinux.org/gf/tracker/4323 - */ - if (ANOMALY_05000435) - bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); - else - bfin_write_SIC_IWR1(IWR_DISABLE_ALL); -# endif -# ifdef SIC_IWR2 - bfin_write_SIC_IWR2(IWR_DISABLE_ALL); -# endif -#else - bfin_write_SIC_IWR(IWR_DISABLE_ALL); -#endif - return 0; -} - -#ifdef CONFIG_DO_IRQ_L1 -__attribute__((l1_text)) -#endif -static int vec_to_irq(int vec) -{ - struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; - struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; - unsigned long sic_status[3]; - if (likely(vec == EVT_IVTMR_P)) - return IRQ_CORETMR; -#ifdef SIC_ISR - sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); -#else - if (smp_processor_id()) { -# ifdef SICB_ISR0 - /* This will be optimized out in UP mode. */ - sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); - sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); -# endif - } else { - sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); - sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); - } -#endif -#ifdef SIC_ISR2 - sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); -#endif - - for (;; ivg++) { - if (ivg >= ivg_stop) - return -1; -#ifdef SIC_ISR - if (sic_status[0] & ivg->isrflag) -#else - if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) -#endif - return ivg->irqno; - } -} - -#else /* SEC_GCTL */ - -/* - * This function should be called during kernel startup to initialize - * the BFin IRQ handling routines. - */ - -int __init init_arch_irq(void) -{ - int irq; - unsigned long ilat = 0; - - bfin_write_SEC_GCTL(SEC_GCTL_RESET); - - local_irq_disable(); - - for (irq = 0; irq <= SYS_IRQS; irq++) { - if (irq <= IRQ_CORETMR) { - irq_set_chip_and_handler(irq, &bfin_core_irqchip, - handle_simple_irq); -#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP) - if (irq == IRQ_CORETMR) - irq_set_handler(irq, handle_percpu_irq); -#endif - } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { - irq_set_chip_and_handler(irq, &bfin_sec_irqchip, - handle_percpu_irq); - } else { - irq_set_chip(irq, &bfin_sec_irqchip); - irq_set_handler(irq, handle_fasteoi_irq); - __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); - } - } - - bfin_write_IMASK(0); - CSYNC(); - ilat = bfin_read_ILAT(); - CSYNC(); - bfin_write_ILAT(ilat); - CSYNC(); - - printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); - - bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); - - /* Enable interrupts IVG7-15 */ - bfin_irq_flags |= IMASK_IVG15 | - IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | - IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; - - - bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); - bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0)); - bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0)); - bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); - udelay(100); - bfin_write_SEC_GCTL(SEC_GCTL_EN); - bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); - bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); - - init_software_driven_irq(); - -#ifdef CONFIG_PM - register_syscore_ops(&sec_pm_syscore_ops); -#endif - - bfin_fault_irq.handler = bfin_fault_routine; -#ifdef CONFIG_L1_PARITY_CHECK - setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq); -#endif - setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq); - setup_irq(IRQ_SEC_ERR, &bfin_fault_irq); - - return 0; -} - -#ifdef CONFIG_DO_IRQ_L1 -__attribute__((l1_text)) -#endif -static int vec_to_irq(int vec) -{ - if (likely(vec == EVT_IVTMR_P)) - return IRQ_CORETMR; - - return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); -} -#endif /* SEC_GCTL */ - -#ifdef CONFIG_DO_IRQ_L1 -__attribute__((l1_text)) -#endif -void do_irq(int vec, struct pt_regs *fp) -{ - int irq = vec_to_irq(vec); - if (irq == -1) - return; - asm_do_IRQ(irq, fp); -} - -#ifdef CONFIG_IPIPE - -int __ipipe_get_irq_priority(unsigned irq) -{ - int ient, prio; - - if (irq <= IRQ_CORETMR) - return irq; - -#ifdef SEC_GCTL - if (irq >= BFIN_IRQ(0)) - return IVG11; -#else - for (ient = 0; ient < NR_PERI_INTS; ient++) { - struct ivgx *ivg = ivg_table + ient; - if (ivg->irqno == irq) { - for (prio = 0; prio <= IVG13-IVG7; prio++) { - if (ivg7_13[prio].ifirst <= ivg && - ivg7_13[prio].istop > ivg) - return IVG7 + prio; - } - } - } -#endif - - return IVG15; -} - -/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ -#ifdef CONFIG_DO_IRQ_L1 -__attribute__((l1_text)) -#endif -asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) -{ - struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); - struct ipipe_domain *this_domain = __ipipe_current_domain; - int irq, s = 0; - - irq = vec_to_irq(vec); - if (irq == -1) - return 0; - - if (irq == IRQ_SYSTMR) { -#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) - bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ -#endif - /* This is basically what we need from the register frame. */ - __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend); - __this_cpu_write(__ipipe_tick_regs.pc, regs->pc); - if (this_domain != ipipe_root_domain) - __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10); - else - __this_cpu_or(__ipipe_tick_regs.ipend, 0x10); - } - - /* - * We don't want Linux interrupt handlers to run at the - * current core priority level (i.e. < EVT15), since this - * might delay other interrupts handled by a high priority - * domain. Here is what we do instead: - * - * - we raise the SYNCDEFER bit to prevent - * __ipipe_handle_irq() to sync the pipeline for the root - * stage for the incoming interrupt. Upon return, that IRQ is - * pending in the interrupt log. - * - * - we raise the TIF_IRQ_SYNC bit for the current thread, so - * that _schedule_and_signal_from_int will eventually sync the - * pipeline from EVT15. - */ - if (this_domain == ipipe_root_domain) { - s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); - barrier(); - } - - ipipe_trace_irq_entry(irq); - __ipipe_handle_irq(irq, regs); - ipipe_trace_irq_exit(irq); - - if (user_mode(regs) && - !ipipe_test_foreign_stack() && - (current->ipipe_flags & PF_EVTRET) != 0) { - /* - * Testing for user_regs() does NOT fully eliminate - * foreign stack contexts, because of the forged - * interrupt returns we do through - * __ipipe_call_irqtail. In that case, we might have - * preempted a foreign stack context in a high - * priority domain, with a single interrupt level now - * pending after the irqtail unwinding is done. In - * which case user_mode() is now true, and the event - * gets dispatched spuriously. - */ - current->ipipe_flags &= ~PF_EVTRET; - __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs); - } - - if (this_domain == ipipe_root_domain) { - set_thread_flag(TIF_IRQ_SYNC); - if (!s) { - __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status); - return !test_bit(IPIPE_STALL_FLAG, &p->status); - } - } - - return 0; -} - -#endif /* CONFIG_IPIPE */ diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c deleted file mode 100644 index f57b5fe5355e..000000000000 --- a/arch/blackfin/mach-common/pm.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Blackfin power management - * - * Copyright 2006-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 - * based on arm/mach-omap/pm.c - * Copyright 2001, Cliff Brake and others - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_BF60x -struct bfin_cpu_pm_fns *bfin_cpu_pm; -#endif - -void bfin_pm_suspend_standby_enter(void) -{ -#if !BFIN_GPIO_PINT - bfin_pm_standby_setup(); -#endif - -#ifdef CONFIG_BF60x - bfin_cpu_pm->enter(PM_SUSPEND_STANDBY); -#else -# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER - sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); -# else - sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); -# endif -#endif - -#if !BFIN_GPIO_PINT - bfin_pm_standby_restore(); -#endif - -#ifndef CONFIG_BF60x -#ifdef SIC_IWR0 - bfin_write_SIC_IWR0(IWR_DISABLE_ALL); -# ifdef SIC_IWR1 - /* BF52x system reset does not properly reset SIC_IWR1 which - * will screw up the bootrom as it relies on MDMA0/1 waking it - * up from IDLE instructions. See this report for more info: - * http://blackfin.uclinux.org/gf/tracker/4323 - */ - if (ANOMALY_05000435) - bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); - else - bfin_write_SIC_IWR1(IWR_DISABLE_ALL); -# endif -# ifdef SIC_IWR2 - bfin_write_SIC_IWR2(IWR_DISABLE_ALL); -# endif -#else - bfin_write_SIC_IWR(IWR_DISABLE_ALL); -#endif - -#endif -} - -int bf53x_suspend_l1_mem(unsigned char *memptr) -{ - dma_memcpy_nocache(memptr, (const void *) L1_CODE_START, - L1_CODE_LENGTH); - dma_memcpy_nocache(memptr + L1_CODE_LENGTH, - (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH); - dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, - (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH); - memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH + - L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START, - L1_SCRATCH_LENGTH); - - return 0; -} - -int bf53x_resume_l1_mem(unsigned char *memptr) -{ - dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH); - dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH, - L1_DATA_A_LENGTH); - dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH + - L1_DATA_A_LENGTH, L1_DATA_B_LENGTH); - memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH + - L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH); - - return 0; -} - -#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) -# ifdef CONFIG_BF60x -__attribute__((l1_text)) -# endif -static void flushinv_all_dcache(void) -{ - register u32 way, bank, subbank, set; - register u32 status, addr; - u32 dmem_ctl = bfin_read_DMEM_CONTROL(); - - for (bank = 0; bank < 2; ++bank) { - if (!(dmem_ctl & (1 << (DMC1_P - bank)))) - continue; - - for (way = 0; way < 2; ++way) - for (subbank = 0; subbank < 4; ++subbank) - for (set = 0; set < 64; ++set) { - - bfin_write_DTEST_COMMAND( - way << 26 | - bank << 23 | - subbank << 16 | - set << 5 - ); - CSYNC(); - status = bfin_read_DTEST_DATA0(); - - /* only worry about valid/dirty entries */ - if ((status & 0x3) != 0x3) - continue; - - - /* construct the address using the tag */ - addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5); - - /* flush it */ - __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr)); - } - } -} -#endif - -int bfin_pm_suspend_mem_enter(void) -{ - int ret; -#ifndef CONFIG_BF60x - int wakeup; -#endif - - unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH - + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH, - GFP_ATOMIC); - - if (memptr == NULL) { - panic("bf53x_suspend_l1_mem malloc failed"); - return -ENOMEM; - } - -#ifndef CONFIG_BF60x - wakeup = bfin_read_VR_CTL() & ~FREQ; - wakeup |= SCKELOW; - -#ifdef CONFIG_PM_BFIN_WAKE_PH6 - wakeup |= PHYWE; -#endif -#ifdef CONFIG_PM_BFIN_WAKE_GP - wakeup |= GPWE; -#endif -#endif - - ret = blackfin_dma_suspend(); - - if (ret) { - kfree(memptr); - return ret; - } - -#ifdef CONFIG_GPIO_ADI - bfin_gpio_pm_hibernate_suspend(); -#endif - -#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) - flushinv_all_dcache(); - udelay(1); -#endif - _disable_dcplb(); - _disable_icplb(); - bf53x_suspend_l1_mem(memptr); - -#ifndef CONFIG_BF60x - do_hibernate(wakeup | vr_wakeup); /* See you later! */ -#else - bfin_cpu_pm->enter(PM_SUSPEND_MEM); -#endif - - bf53x_resume_l1_mem(memptr); - - _enable_icplb(); - _enable_dcplb(); - -#ifdef CONFIG_GPIO_ADI - bfin_gpio_pm_hibernate_restore(); -#endif - blackfin_dma_resume(); - - kfree(memptr); - - return 0; -} - -/* - * bfin_pm_valid - Tell the PM core that we only support the standby sleep - * state - * @state: suspend state we're checking. - * - */ -static int bfin_pm_valid(suspend_state_t state) -{ - return (state == PM_SUSPEND_STANDBY -#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561)) - /* - * On BF533/2/1: - * If we enter Hibernate the SCKE Pin is driven Low, - * so that the SDRAM enters Self Refresh Mode. - * However when the reset sequence that follows hibernate - * state is executed, SCKE is driven High, taking the - * SDRAM out of Self Refresh. - * - * If you reconfigure and access the SDRAM "very quickly", - * you are likely to avoid errors, otherwise the SDRAM - * start losing its contents. - * An external HW workaround is possible using logic gates. - */ - || state == PM_SUSPEND_MEM -#endif - ); -} - -/* - * bfin_pm_enter - Actually enter a sleep state. - * @state: State we're entering. - * - */ -static int bfin_pm_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_STANDBY: - bfin_pm_suspend_standby_enter(); - break; - case PM_SUSPEND_MEM: - bfin_pm_suspend_mem_enter(); - break; - default: - return -EINVAL; - } - - return 0; -} - -#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH -void bfin_pm_end(void) -{ - u32 cycle, cycle2; - u64 usec64; - u32 usec; - - __asm__ __volatile__ ( - "1: %0 = CYCLES2\n" - "%1 = CYCLES\n" - "%2 = CYCLES2\n" - "CC = %2 == %0\n" - "if ! CC jump 1b\n" - : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC" - ); - - usec64 = ((u64)cycle2 << 32) + cycle; - do_div(usec64, get_cclk() / USEC_PER_SEC); - usec = usec64; - if (usec == 0) - usec = 1; - - pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n", - usec / USEC_PER_MSEC, usec % USEC_PER_MSEC); -} -#endif - -static const struct platform_suspend_ops bfin_pm_ops = { - .enter = bfin_pm_enter, - .valid = bfin_pm_valid, -#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH - .end = bfin_pm_end, -#endif -}; - -static int __init bfin_pm_init(void) -{ - suspend_set_ops(&bfin_pm_ops); - return 0; -} - -__initcall(bfin_pm_init); diff --git a/arch/blackfin/mach-common/scb-init.c b/arch/blackfin/mach-common/scb-init.c deleted file mode 100644 index 8923398db66f..000000000000 --- a/arch/blackfin/mach-common/scb-init.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority - * - * Copyright 2012 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -__attribute__((l1_text)) -inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots, - unsigned char *scb_mi_prio) -{ - unsigned int i; - - for (i = 0; i < slots; ++i) - bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]); -} - -__attribute__((l1_text)) -inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots, - unsigned char *scb_mi_prio) -{ - unsigned int i; - - for (i = 0; i < slots; ++i) { - bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i); - scb_mi_prio[i] = bfin_read32(scb_mi_arbw); - } -} - -__attribute__((l1_text)) -void init_scb(void) -{ - unsigned int i, j; - unsigned char scb_tmp_prio[32]; - - pr_info("Init System Crossbar\n"); - for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) { - - scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio); - - pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr); - scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio); - for (j = 0; j < scb_data[i].scb_mi_slots; ++j) - pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]); - } - -} diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c deleted file mode 100644 index b32ddab7966c..000000000000 --- a/arch/blackfin/mach-common/smp.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited) - * - * Copyright 2007-2009 Analog Devices Inc. - * Philippe Gerum - * - * Licensed under the GPL-2. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Anomaly notes: - * 05000120 - we always define corelock as 32-bit integer in L2 - */ -struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); - -#ifdef CONFIG_ICACHE_FLUSH_L1 -unsigned long blackfin_iflush_l1_entry[NR_CPUS]; -#endif - -struct blackfin_initial_pda initial_pda_coreb; - -enum ipi_message_type { - BFIN_IPI_NONE, - BFIN_IPI_TIMER, - BFIN_IPI_RESCHEDULE, - BFIN_IPI_CALL_FUNC, - BFIN_IPI_CPU_STOP, -}; - -struct blackfin_flush_data { - unsigned long start; - unsigned long end; -}; - -void *secondary_stack; - -static struct blackfin_flush_data smp_flush_data; - -static DEFINE_SPINLOCK(stop_lock); - -/* A magic number - stress test shows this is safe for common cases */ -#define BFIN_IPI_MSGQ_LEN 5 - -/* Simple FIFO buffer, overflow leads to panic */ -struct ipi_data { - atomic_t count; - atomic_t bits; -}; - -static DEFINE_PER_CPU(struct ipi_data, bfin_ipi); - -static void ipi_cpu_stop(unsigned int cpu) -{ - spin_lock(&stop_lock); - printk(KERN_CRIT "CPU%u: stopping\n", cpu); - dump_stack(); - spin_unlock(&stop_lock); - - set_cpu_online(cpu, false); - - local_irq_disable(); - - while (1) - SSYNC(); -} - -static void ipi_flush_icache(void *info) -{ - struct blackfin_flush_data *fdata = info; - - /* Invalidate the memory holding the bounds of the flushed region. */ - blackfin_dcache_invalidate_range((unsigned long)fdata, - (unsigned long)fdata + sizeof(*fdata)); - - /* Make sure all write buffers in the data side of the core - * are flushed before trying to invalidate the icache. This - * needs to be after the data flush and before the icache - * flush so that the SSYNC does the right thing in preventing - * the instruction prefetcher from hitting things in cached - * memory at the wrong time -- it runs much further ahead than - * the pipeline. - */ - SSYNC(); - - /* ipi_flaush_icache is invoked by generic flush_icache_range, - * so call blackfin arch icache flush directly here. - */ - blackfin_icache_flush_range(fdata->start, fdata->end); -} - -/* Use IRQ_SUPPLE_0 to request reschedule. - * When returning from interrupt to user space, - * there is chance to reschedule */ -static irqreturn_t ipi_handler_int0(int irq, void *dev_instance) -{ - unsigned int cpu = smp_processor_id(); - - platform_clear_ipi(cpu, IRQ_SUPPLE_0); - return IRQ_HANDLED; -} - -DECLARE_PER_CPU(struct clock_event_device, coretmr_events); -void ipi_timer(void) -{ - int cpu = smp_processor_id(); - struct clock_event_device *evt = &per_cpu(coretmr_events, cpu); - evt->event_handler(evt); -} - -static irqreturn_t ipi_handler_int1(int irq, void *dev_instance) -{ - struct ipi_data *bfin_ipi_data; - unsigned int cpu = smp_processor_id(); - unsigned long pending; - unsigned long msg; - - platform_clear_ipi(cpu, IRQ_SUPPLE_1); - - smp_rmb(); - bfin_ipi_data = this_cpu_ptr(&bfin_ipi); - while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) { - msg = 0; - do { - msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1); - switch (msg) { - case BFIN_IPI_TIMER: - ipi_timer(); - break; - case BFIN_IPI_RESCHEDULE: - scheduler_ipi(); - break; - case BFIN_IPI_CALL_FUNC: - generic_smp_call_function_interrupt(); - break; - case BFIN_IPI_CPU_STOP: - ipi_cpu_stop(cpu); - break; - default: - goto out; - } - atomic_dec(&bfin_ipi_data->count); - } while (msg < BITS_PER_LONG); - - } -out: - return IRQ_HANDLED; -} - -static void bfin_ipi_init(void) -{ - unsigned int cpu; - struct ipi_data *bfin_ipi_data; - for_each_possible_cpu(cpu) { - bfin_ipi_data = &per_cpu(bfin_ipi, cpu); - atomic_set(&bfin_ipi_data->bits, 0); - atomic_set(&bfin_ipi_data->count, 0); - } -} - -void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg) -{ - unsigned int cpu; - struct ipi_data *bfin_ipi_data; - unsigned long flags; - - local_irq_save(flags); - for_each_cpu(cpu, cpumask) { - bfin_ipi_data = &per_cpu(bfin_ipi, cpu); - atomic_or((1 << msg), &bfin_ipi_data->bits); - atomic_inc(&bfin_ipi_data->count); - } - local_irq_restore(flags); - smp_wmb(); - for_each_cpu(cpu, cpumask) - platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1); -} - -void arch_send_call_function_single_ipi(int cpu) -{ - send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC); -} - -void arch_send_call_function_ipi_mask(const struct cpumask *mask) -{ - send_ipi(mask, BFIN_IPI_CALL_FUNC); -} - -void smp_send_reschedule(int cpu) -{ - send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE); - - return; -} - -void smp_send_msg(const struct cpumask *mask, unsigned long type) -{ - send_ipi(mask, type); -} - -void smp_timer_broadcast(const struct cpumask *mask) -{ - smp_send_msg(mask, BFIN_IPI_TIMER); -} - -void smp_send_stop(void) -{ - cpumask_t callmap; - - preempt_disable(); - cpumask_copy(&callmap, cpu_online_mask); - cpumask_clear_cpu(smp_processor_id(), &callmap); - if (!cpumask_empty(&callmap)) - send_ipi(&callmap, BFIN_IPI_CPU_STOP); - - preempt_enable(); - - return; -} - -int __cpu_up(unsigned int cpu, struct task_struct *idle) -{ - int ret; - - secondary_stack = task_stack_page(idle) + THREAD_SIZE; - - ret = platform_boot_secondary(cpu, idle); - - secondary_stack = NULL; - - return ret; -} - -static void setup_secondary(unsigned int cpu) -{ - unsigned long ilat; - - bfin_write_IMASK(0); - CSYNC(); - ilat = bfin_read_ILAT(); - CSYNC(); - bfin_write_ILAT(ilat); - CSYNC(); - - /* Enable interrupt levels IVG7-15. IARs have been already - * programmed by the boot CPU. */ - bfin_irq_flags |= IMASK_IVG15 | - IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | - IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; -} - -void secondary_start_kernel(void) -{ - unsigned int cpu = smp_processor_id(); - struct mm_struct *mm = &init_mm; - - if (_bfin_swrst & SWRST_DBL_FAULT_B) { - printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n"); -#ifdef CONFIG_DEBUG_DOUBLEFAULT - printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n", - initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE, - initial_pda_coreb.retx_doublefault); - printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", - initial_pda_coreb.dcplb_doublefault_addr); - printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", - initial_pda_coreb.icplb_doublefault_addr); -#endif - printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", - initial_pda_coreb.retx); - } - - /* - * We want the D-cache to be enabled early, in case the atomic - * support code emulates cache coherence (see - * __ARCH_SYNC_CORE_DCACHE). - */ - init_exception_vectors(); - - local_irq_disable(); - - /* Attach the new idle task to the global mm. */ - mmget(mm); - mmgrab(mm); - current->active_mm = mm; - - preempt_disable(); - - setup_secondary(cpu); - - platform_secondary_init(cpu); - /* setup local core timer */ - bfin_local_timer_setup(); - - local_irq_enable(); - - bfin_setup_caches(cpu); - - notify_cpu_starting(cpu); - /* - * Calibrate loops per jiffy value. - * IRQs need to be enabled here - D-cache can be invalidated - * in timer irq handler, so core B can read correct jiffies. - */ - calibrate_delay(); - - /* We are done with local CPU inits, unblock the boot CPU. */ - set_cpu_online(cpu, true); - cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); -} - -void __init smp_prepare_boot_cpu(void) -{ -} - -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - platform_prepare_cpus(max_cpus); - bfin_ipi_init(); - platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0); - platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1); -} - -void __init smp_cpus_done(unsigned int max_cpus) -{ - unsigned long bogosum = 0; - unsigned int cpu; - - for_each_online_cpu(cpu) - bogosum += loops_per_jiffy; - - printk(KERN_INFO "SMP: Total of %d processors activated " - "(%lu.%02lu BogoMIPS).\n", - num_online_cpus(), - bogosum / (500000/HZ), - (bogosum / (5000/HZ)) % 100); -} - -void smp_icache_flush_range_others(unsigned long start, unsigned long end) -{ - smp_flush_data.start = start; - smp_flush_data.end = end; - - preempt_disable(); - if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) - printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); - preempt_enable(); -} -EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); - -#ifdef __ARCH_SYNC_CORE_ICACHE -unsigned long icache_invld_count[NR_CPUS]; -void resync_core_icache(void) -{ - unsigned int cpu = get_cpu(); - blackfin_invalidate_entire_icache(); - icache_invld_count[cpu]++; - put_cpu(); -} -EXPORT_SYMBOL(resync_core_icache); -#endif - -#ifdef __ARCH_SYNC_CORE_DCACHE -unsigned long dcache_invld_count[NR_CPUS]; -unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); - -void resync_core_dcache(void) -{ - unsigned int cpu = get_cpu(); - blackfin_invalidate_entire_dcache(); - dcache_invld_count[cpu]++; - put_cpu(); -} -EXPORT_SYMBOL(resync_core_dcache); -#endif - -#ifdef CONFIG_HOTPLUG_CPU -int __cpu_disable(void) -{ - unsigned int cpu = smp_processor_id(); - - if (cpu == 0) - return -EPERM; - - set_cpu_online(cpu, false); - return 0; -} - -int __cpu_die(unsigned int cpu) -{ - return cpu_wait_death(cpu, 5); -} - -void cpu_die(void) -{ - (void)cpu_report_death(); - - atomic_dec(&init_mm.mm_users); - atomic_dec(&init_mm.mm_count); - - local_irq_disable(); - platform_cpu_die(); -} -#endif diff --git a/arch/blackfin/mm/Makefile b/arch/blackfin/mm/Makefile deleted file mode 100644 index 4c011b1f661f..000000000000 --- a/arch/blackfin/mm/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mm/Makefile -# - -obj-y := sram-alloc.o isram-driver.o init.o maccess.o diff --git a/arch/blackfin/mm/blackfin_sram.h b/arch/blackfin/mm/blackfin_sram.h deleted file mode 100644 index fb0b1599cfb7..000000000000 --- a/arch/blackfin/mm/blackfin_sram.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Local prototypes meant for internal use only - * - * Copyright 2006-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BLACKFIN_SRAM_H__ -#define __BLACKFIN_SRAM_H__ - -extern void *l1sram_alloc(size_t); - -#endif diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c deleted file mode 100644 index b59cd7c3261a..000000000000 --- a/arch/blackfin/mm/init.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "blackfin_sram.h" - -/* - * ZERO_PAGE is a special page that is used for zero-initialized data and COW. - * Let the bss do its zero-init magic so we don't have to do it ourselves. - */ -char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE))); -EXPORT_SYMBOL(empty_zero_page); - -#ifndef CONFIG_EXCEPTION_L1_SCRATCH -#if defined CONFIG_SYSCALL_TAB_L1 -__attribute__((l1_data)) -#endif -static unsigned long exception_stack[NR_CPUS][1024]; -#endif - -struct blackfin_pda cpu_pda[NR_CPUS]; -EXPORT_SYMBOL(cpu_pda); - -/* - * paging_init() continues the virtual memory environment setup which - * was begun by the code in arch/head.S. - * The parameters are pointers to where to stick the starting and ending - * addresses of available kernel virtual memory. - */ -void __init paging_init(void) -{ - /* - * make sure start_mem is page aligned, otherwise bootmem and - * page_alloc get different views of the world - */ - unsigned long end_mem = memory_end & PAGE_MASK; - - unsigned long zones_size[MAX_NR_ZONES] = { - [0] = 0, - [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT, - [ZONE_NORMAL] = 0, -#ifdef CONFIG_HIGHMEM - [ZONE_HIGHMEM] = 0, -#endif - }; - - /* Set up SFC/DFC registers (user data space) */ - set_fs(KERNEL_DS); - - pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n", - PAGE_ALIGN(memory_start), end_mem); - free_area_init_node(0, zones_size, - CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL); -} - -asmlinkage void __init init_pda(void) -{ - unsigned int cpu = raw_smp_processor_id(); - - early_shadow_stamp(); - - /* Initialize the PDA fields holding references to other parts - of the memory. The content of such memory is still - undefined at the time of the call, we are only setting up - valid pointers to it. */ - memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu])); - -#ifdef CONFIG_EXCEPTION_L1_SCRATCH - cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \ - L1_SCRATCH_LENGTH); -#else - cpu_pda[cpu].ex_stack = exception_stack[cpu + 1]; -#endif - -#ifdef CONFIG_SMP - cpu_pda[cpu].imask = 0x1f; -#endif -} - -void __init mem_init(void) -{ - char buf[64]; - - high_memory = (void *)(memory_end & PAGE_MASK); - max_mapnr = MAP_NR(high_memory); - printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", max_mapnr); - - /* This will put all low memory onto the freelists. */ - free_all_bootmem(); - - snprintf(buf, sizeof(buf) - 1, "%uK DMA", DMA_UNCACHED_REGION >> 10); - mem_init_print_info(buf); -} - -#ifdef CONFIG_BLK_DEV_INITRD -void __init free_initrd_mem(unsigned long start, unsigned long end) -{ -#ifndef CONFIG_MPU - free_reserved_area((void *)start, (void *)end, -1, "initrd"); -#endif -} -#endif - -void __ref free_initmem(void) -{ -#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU - free_initmem_default(-1); - if (memory_start == (unsigned long)(&__init_end)) - memory_start = (unsigned long)(&__init_begin); -#endif -} diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c deleted file mode 100644 index aaa1e64b753b..000000000000 --- a/arch/blackfin/mm/isram-driver.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Instruction SRAM accessor functions for the Blackfin - * - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#define pr_fmt(fmt) "isram: " fmt - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* - * IMPORTANT WARNING ABOUT THESE FUNCTIONS - * - * The emulator will not function correctly if a write command is left in - * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by - * the emulator. To avoid such problems, ensure that both ITEST_COMMAND - * and DTEST_COMMAND are zero when exiting these functions. - */ - - -/* - * On the Blackfin, L1 instruction sram (which operates at core speeds) can not - * be accessed by a normal core load, so we need to go through a few hoops to - * read/write it. - * To try to make it easier - we export a memcpy interface, where either src or - * dest can be in this special L1 memory area. - * The low level read/write functions should not be exposed to the rest of the - * kernel, since they operate on 64-bit data, and need specific address alignment - */ - -static DEFINE_SPINLOCK(dtest_lock); - -/* Takes a void pointer */ -#define IADDR2DTEST(x) \ - ({ unsigned long __addr = (unsigned long)(x); \ - ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \ - (1 << 24) | /* instruction access = 1 */ \ - ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \ - ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \ - (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \ - (1 << 2); /* data array = 1 */ \ - }) - -/* Takes a pointer, and returns the offset (in bits) which things should be shifted */ -#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8) - -/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */ -#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7) - -static void isram_write(const void *addr, uint64_t data) -{ - uint32_t cmd; - unsigned long flags; - - if (unlikely(addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH))) - return; - - cmd = IADDR2DTEST(addr) | 2; /* write */ - - /* - * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND - * While in exception context - atomicity is guaranteed or double fault - */ - spin_lock_irqsave(&dtest_lock, flags); - - bfin_write_DTEST_DATA0(data & 0xFFFFFFFF); - bfin_write_DTEST_DATA1(data >> 32); - - /* use the builtin, since interrupts are already turned off */ - __builtin_bfin_csync(); - bfin_write_DTEST_COMMAND(cmd); - __builtin_bfin_csync(); - - bfin_write_DTEST_COMMAND(0); - __builtin_bfin_csync(); - - spin_unlock_irqrestore(&dtest_lock, flags); -} - -static uint64_t isram_read(const void *addr) -{ - uint32_t cmd; - unsigned long flags; - uint64_t ret; - - if (unlikely(addr > (void *)(L1_CODE_START + L1_CODE_LENGTH))) - return 0; - - cmd = IADDR2DTEST(addr) | 0; /* read */ - - /* - * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND - * While in exception context - atomicity is guaranteed or double fault - */ - spin_lock_irqsave(&dtest_lock, flags); - /* use the builtin, since interrupts are already turned off */ - __builtin_bfin_csync(); - bfin_write_DTEST_COMMAND(cmd); - __builtin_bfin_csync(); - ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32); - - bfin_write_DTEST_COMMAND(0); - __builtin_bfin_csync(); - spin_unlock_irqrestore(&dtest_lock, flags); - - return ret; -} - -static bool isram_check_addr(const void *addr, size_t n) -{ - if ((addr >= (void *)L1_CODE_START) && - (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) { - if (unlikely((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH))) { - show_stack(NULL, NULL); - pr_err("copy involving %p length (%zu) too long\n", addr, n); - } - return true; - } - return false; -} - -/* - * The isram_memcpy() function copies n bytes from memory area src to memory area dest. - * The isram_memcpy() function returns a pointer to dest. - * Either dest or src can be in L1 instruction sram. - */ -void *isram_memcpy(void *dest, const void *src, size_t n) -{ - uint64_t data_in = 0, data_out = 0; - size_t count; - bool dest_in_l1, src_in_l1, need_data, put_data; - unsigned char byte, *src_byte, *dest_byte; - - src_byte = (unsigned char *)src; - dest_byte = (unsigned char *)dest; - - dest_in_l1 = isram_check_addr(dest, n); - src_in_l1 = isram_check_addr(src, n); - - need_data = true; - put_data = true; - for (count = 0; count < n; count++) { - if (src_in_l1) { - if (need_data) { - data_in = isram_read(src + count); - need_data = false; - } - - if (ADDR2LAST(src + count)) - need_data = true; - - byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff); - - } else { - /* src is in L2 or L3 - so just dereference*/ - byte = src_byte[count]; - } - - if (dest_in_l1) { - if (put_data) { - data_out = isram_read(dest + count); - put_data = false; - } - - data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count)); - data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count)); - - if (ADDR2LAST(dest + count)) { - put_data = true; - isram_write(dest + count, data_out); - } - } else { - /* dest in L2 or L3 - so just dereference */ - dest_byte[count] = byte; - } - } - - /* make sure we dump the last byte if necessary */ - if (dest_in_l1 && !put_data) - isram_write(dest + count, data_out); - - return dest; -} -EXPORT_SYMBOL(isram_memcpy); - -#ifdef CONFIG_BFIN_ISRAM_SELF_TEST - -static int test_len = 0x20000; - -static __init void hex_dump(unsigned char *buf, int len) -{ - while (len--) - pr_cont("%02x", *buf++); -} - -static __init int isram_read_test(char *sdram, void *l1inst) -{ - int i, ret = 0; - uint64_t data1, data2; - - pr_info("INFO: running isram_read tests\n"); - - /* setup some different data to play with */ - for (i = 0; i < test_len; ++i) - sdram[i] = i % 255; - dma_memcpy(l1inst, sdram, test_len); - - /* make sure we can read the L1 inst */ - for (i = 0; i < test_len; i += sizeof(uint64_t)) { - data1 = isram_read(l1inst + i); - memcpy(&data2, sdram + i, sizeof(data2)); - if (data1 != data2) { - pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n", - l1inst + i, data1, data2); - ++ret; - } - } - - return ret; -} - -static __init int isram_write_test(char *sdram, void *l1inst) -{ - int i, ret = 0; - uint64_t data1, data2; - - pr_info("INFO: running isram_write tests\n"); - - /* setup some different data to play with */ - memset(sdram, 0, test_len * 2); - dma_memcpy(l1inst, sdram, test_len); - for (i = 0; i < test_len; ++i) - sdram[i] = i % 255; - - /* make sure we can write the L1 inst */ - for (i = 0; i < test_len; i += sizeof(uint64_t)) { - memcpy(&data1, sdram + i, sizeof(data1)); - isram_write(l1inst + i, data1); - data2 = isram_read(l1inst + i); - if (data1 != data2) { - pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n", - l1inst + i, data1, data2); - ++ret; - } - } - - dma_memcpy(sdram + test_len, l1inst, test_len); - if (memcmp(sdram, sdram + test_len, test_len)) { - pr_err("FAIL: isram_write() did not work properly\n"); - ++ret; - } - - return ret; -} - -static __init int -_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy, - void *(*fmemcpy)(void *, const void *, size_t)) -{ - memset(sdram, pattern, test_len); - fmemcpy(l1inst, sdram, test_len); - fmemcpy(sdram + test_len, l1inst, test_len); - if (memcmp(sdram, sdram + test_len, test_len)) { - pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n", - smemcpy, l1inst, sdram, test_len, pattern); - return 1; - } - return 0; -} -#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d) - -static __init int isram_memcpy_test(char *sdram, void *l1inst) -{ - int i, j, thisret, ret = 0; - - /* check broad isram_memcpy() */ - pr_info("INFO: running broad isram_memcpy tests\n"); - for (i = 0xf; i >= 0; --i) - ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy); - - /* check read of small, unaligned, and hardware 64bit limits */ - pr_info("INFO: running isram_memcpy (read) tests\n"); - - /* setup some different data to play with */ - for (i = 0; i < test_len; ++i) - sdram[i] = i % 255; - dma_memcpy(l1inst, sdram, test_len); - - thisret = 0; - for (i = 0; i < test_len - 32; ++i) { - unsigned char cmp[32]; - for (j = 1; j <= 32; ++j) { - memset(cmp, 0, sizeof(cmp)); - isram_memcpy(cmp, l1inst + i, j); - if (memcmp(cmp, sdram + i, j)) { - pr_err("FAIL: %p:", l1inst + 1); - hex_dump(cmp, j); - pr_cont(" SDRAM:"); - hex_dump(sdram + i, j); - pr_cont("\n"); - if (++thisret > 20) { - pr_err("FAIL: skipping remaining series\n"); - i = test_len; - break; - } - } - } - } - ret += thisret; - - /* check write of small, unaligned, and hardware 64bit limits */ - pr_info("INFO: running isram_memcpy (write) tests\n"); - - memset(sdram + test_len, 0, test_len); - dma_memcpy(l1inst, sdram + test_len, test_len); - - thisret = 0; - for (i = 0; i < test_len - 32; ++i) { - unsigned char cmp[32]; - for (j = 1; j <= 32; ++j) { - isram_memcpy(l1inst + i, sdram + i, j); - dma_memcpy(cmp, l1inst + i, j); - if (memcmp(cmp, sdram + i, j)) { - pr_err("FAIL: %p:", l1inst + i); - hex_dump(cmp, j); - pr_cont(" SDRAM:"); - hex_dump(sdram + i, j); - pr_cont("\n"); - if (++thisret > 20) { - pr_err("FAIL: skipping remaining series\n"); - i = test_len; - break; - } - } - } - } - ret += thisret; - - return ret; -} - -static __init int isram_test_init(void) -{ - int ret; - char *sdram; - void *l1inst; - - /* Try to test as much of L1SRAM as possible */ - while (test_len) { - test_len >>= 1; - l1inst = l1_inst_sram_alloc(test_len); - if (l1inst) - break; - } - if (!l1inst) { - pr_warning("SKIP: could not allocate L1 inst\n"); - return 0; - } - pr_info("INFO: testing %#x bytes (%p - %p)\n", - test_len, l1inst, l1inst + test_len); - - sdram = kmalloc(test_len * 2, GFP_KERNEL); - if (!sdram) { - sram_free(l1inst); - pr_warning("SKIP: could not allocate sdram\n"); - return 0; - } - - /* sanity check initial L1 inst state */ - ret = 1; - pr_info("INFO: running initial dma_memcpy checks %p\n", sdram); - if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy)) - goto abort; - if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy)) - goto abort; - - ret = 0; - ret += isram_read_test(sdram, l1inst); - ret += isram_write_test(sdram, l1inst); - ret += isram_memcpy_test(sdram, l1inst); - - abort: - sram_free(l1inst); - kfree(sdram); - - if (ret) - return -EIO; - - pr_info("PASS: all tests worked !\n"); - return 0; -} -late_initcall(isram_test_init); - -static __exit void isram_test_exit(void) -{ - /* stub to allow unloading */ -} -module_exit(isram_test_exit); - -#endif diff --git a/arch/blackfin/mm/maccess.c b/arch/blackfin/mm/maccess.c deleted file mode 100644 index e2532114c5fd..000000000000 --- a/arch/blackfin/mm/maccess.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * safe read and write memory routines callable while atomic - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -static int validate_memory_access_address(unsigned long addr, int size) -{ - if (size < 0 || addr == 0) - return -EFAULT; - return bfin_mem_access_type(addr, size); -} - -long probe_kernel_read(void *dst, const void *src, size_t size) -{ - unsigned long lsrc = (unsigned long)src; - int mem_type; - - mem_type = validate_memory_access_address(lsrc, size); - if (mem_type < 0) - return mem_type; - - if (lsrc >= SYSMMR_BASE) { - if (size == 2 && lsrc % 2 == 0) { - u16 mmr = bfin_read16(src); - memcpy(dst, &mmr, sizeof(mmr)); - return 0; - } else if (size == 4 && lsrc % 4 == 0) { - u32 mmr = bfin_read32(src); - memcpy(dst, &mmr, sizeof(mmr)); - return 0; - } - } else { - switch (mem_type) { - case BFIN_MEM_ACCESS_CORE: - case BFIN_MEM_ACCESS_CORE_ONLY: - return __probe_kernel_read(dst, src, size); - /* XXX: should support IDMA here with SMP */ - case BFIN_MEM_ACCESS_DMA: - if (dma_memcpy(dst, src, size)) - return 0; - break; - case BFIN_MEM_ACCESS_ITEST: - if (isram_memcpy(dst, src, size)) - return 0; - break; - } - } - - return -EFAULT; -} - -long probe_kernel_write(void *dst, const void *src, size_t size) -{ - unsigned long ldst = (unsigned long)dst; - int mem_type; - - mem_type = validate_memory_access_address(ldst, size); - if (mem_type < 0) - return mem_type; - - if (ldst >= SYSMMR_BASE) { - if (size == 2 && ldst % 2 == 0) { - u16 mmr; - memcpy(&mmr, src, sizeof(mmr)); - bfin_write16(dst, mmr); - return 0; - } else if (size == 4 && ldst % 4 == 0) { - u32 mmr; - memcpy(&mmr, src, sizeof(mmr)); - bfin_write32(dst, mmr); - return 0; - } - } else { - switch (mem_type) { - case BFIN_MEM_ACCESS_CORE: - case BFIN_MEM_ACCESS_CORE_ONLY: - return __probe_kernel_write(dst, src, size); - /* XXX: should support IDMA here with SMP */ - case BFIN_MEM_ACCESS_DMA: - if (dma_memcpy(dst, src, size)) - return 0; - break; - case BFIN_MEM_ACCESS_ITEST: - if (isram_memcpy(dst, src, size)) - return 0; - break; - } - } - - return -EFAULT; -} diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c deleted file mode 100644 index d2a96c2c02a3..000000000000 --- a/arch/blackfin/mm/sram-alloc.c +++ /dev/null @@ -1,899 +0,0 @@ -/* - * SRAM allocator for Blackfin on-chip memory - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "blackfin_sram.h" - -/* the data structure for L1 scratchpad and DATA SRAM */ -struct sram_piece { - void *paddr; - int size; - pid_t pid; - struct sram_piece *next; -}; - -static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1sram_lock); -static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head); -static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head); - -#if L1_DATA_A_LENGTH != 0 -static DEFINE_PER_CPU(struct sram_piece, free_l1_data_A_sram_head); -static DEFINE_PER_CPU(struct sram_piece, used_l1_data_A_sram_head); -#endif - -#if L1_DATA_B_LENGTH != 0 -static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head); -static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head); -#endif - -#if L1_DATA_A_LENGTH || L1_DATA_B_LENGTH -static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_data_sram_lock); -#endif - -#if L1_CODE_LENGTH != 0 -static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_inst_sram_lock); -static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head); -static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head); -#endif - -#if L2_LENGTH != 0 -static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp; -static struct sram_piece free_l2_sram_head, used_l2_sram_head; -#endif - -static struct kmem_cache *sram_piece_cache; - -/* L1 Scratchpad SRAM initialization function */ -static void __init l1sram_init(void) -{ - unsigned int cpu; - unsigned long reserve; - -#ifdef CONFIG_SMP - reserve = 0; -#else - reserve = sizeof(struct l1_scratch_task_info); -#endif - - for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { - per_cpu(free_l1_ssram_head, cpu).next = - kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); - if (!per_cpu(free_l1_ssram_head, cpu).next) { - printk(KERN_INFO "Fail to initialize Scratchpad data SRAM.\n"); - return; - } - - per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu) + reserve; - per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH - reserve; - per_cpu(free_l1_ssram_head, cpu).next->pid = 0; - per_cpu(free_l1_ssram_head, cpu).next->next = NULL; - - per_cpu(used_l1_ssram_head, cpu).next = NULL; - - /* mutex initialize */ - spin_lock_init(&per_cpu(l1sram_lock, cpu)); - printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n", - L1_SCRATCH_LENGTH >> 10); - } -} - -static void __init l1_data_sram_init(void) -{ -#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0 - unsigned int cpu; -#endif -#if L1_DATA_A_LENGTH != 0 - for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { - per_cpu(free_l1_data_A_sram_head, cpu).next = - kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); - if (!per_cpu(free_l1_data_A_sram_head, cpu).next) { - printk(KERN_INFO "Fail to initialize L1 Data A SRAM.\n"); - return; - } - - per_cpu(free_l1_data_A_sram_head, cpu).next->paddr = - (void *)get_l1_data_a_start_cpu(cpu) + (_ebss_l1 - _sdata_l1); - per_cpu(free_l1_data_A_sram_head, cpu).next->size = - L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1); - per_cpu(free_l1_data_A_sram_head, cpu).next->pid = 0; - per_cpu(free_l1_data_A_sram_head, cpu).next->next = NULL; - - per_cpu(used_l1_data_A_sram_head, cpu).next = NULL; - - printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n", - L1_DATA_A_LENGTH >> 10, - per_cpu(free_l1_data_A_sram_head, cpu).next->size >> 10); - } -#endif -#if L1_DATA_B_LENGTH != 0 - for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { - per_cpu(free_l1_data_B_sram_head, cpu).next = - kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); - if (!per_cpu(free_l1_data_B_sram_head, cpu).next) { - printk(KERN_INFO "Fail to initialize L1 Data B SRAM.\n"); - return; - } - - per_cpu(free_l1_data_B_sram_head, cpu).next->paddr = - (void *)get_l1_data_b_start_cpu(cpu) + (_ebss_b_l1 - _sdata_b_l1); - per_cpu(free_l1_data_B_sram_head, cpu).next->size = - L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1); - per_cpu(free_l1_data_B_sram_head, cpu).next->pid = 0; - per_cpu(free_l1_data_B_sram_head, cpu).next->next = NULL; - - per_cpu(used_l1_data_B_sram_head, cpu).next = NULL; - - printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n", - L1_DATA_B_LENGTH >> 10, - per_cpu(free_l1_data_B_sram_head, cpu).next->size >> 10); - /* mutex initialize */ - } -#endif - -#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0 - for (cpu = 0; cpu < num_possible_cpus(); ++cpu) - spin_lock_init(&per_cpu(l1_data_sram_lock, cpu)); -#endif -} - -static void __init l1_inst_sram_init(void) -{ -#if L1_CODE_LENGTH != 0 - unsigned int cpu; - for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { - per_cpu(free_l1_inst_sram_head, cpu).next = - kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); - if (!per_cpu(free_l1_inst_sram_head, cpu).next) { - printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n"); - return; - } - - per_cpu(free_l1_inst_sram_head, cpu).next->paddr = - (void *)get_l1_code_start_cpu(cpu) + (_etext_l1 - _stext_l1); - per_cpu(free_l1_inst_sram_head, cpu).next->size = - L1_CODE_LENGTH - (_etext_l1 - _stext_l1); - per_cpu(free_l1_inst_sram_head, cpu).next->pid = 0; - per_cpu(free_l1_inst_sram_head, cpu).next->next = NULL; - - per_cpu(used_l1_inst_sram_head, cpu).next = NULL; - - printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n", - L1_CODE_LENGTH >> 10, - per_cpu(free_l1_inst_sram_head, cpu).next->size >> 10); - - /* mutex initialize */ - spin_lock_init(&per_cpu(l1_inst_sram_lock, cpu)); - } -#endif -} - -#ifdef __ADSPBF60x__ -static irqreturn_t l2_ecc_err(int irq, void *dev_id) -{ - int status; - - printk(KERN_ERR "L2 ecc error happened\n"); - status = bfin_read32(L2CTL0_STAT); - if (status & 0x1) - printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n", - bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0)); - if (status & 0x2) - printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n", - bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1)); - - status = status >> 8; - if (status) - printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n", - status, bfin_read32(L2CTL0_ERRADDR0 + status)); - - panic("L2 Ecc error"); - return IRQ_HANDLED; -} -#endif - -static void __init l2_sram_init(void) -{ -#if L2_LENGTH != 0 - -#ifdef __ADSPBF60x__ - int ret; - - ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err", - NULL); - if (unlikely(ret < 0)) { - printk(KERN_INFO "Fail to request l2 ecc error interrupt"); - return; - } -#endif - - free_l2_sram_head.next = - kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); - if (!free_l2_sram_head.next) { - printk(KERN_INFO "Fail to initialize L2 SRAM.\n"); - return; - } - - free_l2_sram_head.next->paddr = - (void *)L2_START + (_ebss_l2 - _stext_l2); - free_l2_sram_head.next->size = - L2_LENGTH - (_ebss_l2 - _stext_l2); - free_l2_sram_head.next->pid = 0; - free_l2_sram_head.next->next = NULL; - - used_l2_sram_head.next = NULL; - - printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n", - L2_LENGTH >> 10, - free_l2_sram_head.next->size >> 10); - - /* mutex initialize */ - spin_lock_init(&l2_sram_lock); -#endif -} - -static int __init bfin_sram_init(void) -{ - sram_piece_cache = kmem_cache_create("sram_piece_cache", - sizeof(struct sram_piece), - 0, SLAB_PANIC, NULL); - - l1sram_init(); - l1_data_sram_init(); - l1_inst_sram_init(); - l2_sram_init(); - - return 0; -} -pure_initcall(bfin_sram_init); - -/* SRAM allocate function */ -static void *_sram_alloc(size_t size, struct sram_piece *pfree_head, - struct sram_piece *pused_head) -{ - struct sram_piece *pslot, *plast, *pavail; - - if (size <= 0 || !pfree_head || !pused_head) - return NULL; - - /* Align the size */ - size = (size + 3) & ~3; - - pslot = pfree_head->next; - plast = pfree_head; - - /* search an available piece slot */ - while (pslot != NULL && size > pslot->size) { - plast = pslot; - pslot = pslot->next; - } - - if (!pslot) - return NULL; - - if (pslot->size == size) { - plast->next = pslot->next; - pavail = pslot; - } else { - /* use atomic so our L1 allocator can be used atomically */ - pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC); - - if (!pavail) - return NULL; - - pavail->paddr = pslot->paddr; - pavail->size = size; - pslot->paddr += size; - pslot->size -= size; - } - - pavail->pid = current->pid; - - pslot = pused_head->next; - plast = pused_head; - - /* insert new piece into used piece list !!! */ - while (pslot != NULL && pavail->paddr < pslot->paddr) { - plast = pslot; - pslot = pslot->next; - } - - pavail->next = pslot; - plast->next = pavail; - - return pavail->paddr; -} - -/* Allocate the largest available block. */ -static void *_sram_alloc_max(struct sram_piece *pfree_head, - struct sram_piece *pused_head, - unsigned long *psize) -{ - struct sram_piece *pslot, *pmax; - - if (!pfree_head || !pused_head) - return NULL; - - pmax = pslot = pfree_head->next; - - /* search an available piece slot */ - while (pslot != NULL) { - if (pslot->size > pmax->size) - pmax = pslot; - pslot = pslot->next; - } - - if (!pmax) - return NULL; - - *psize = pmax->size; - - return _sram_alloc(*psize, pfree_head, pused_head); -} - -/* SRAM free function */ -static int _sram_free(const void *addr, - struct sram_piece *pfree_head, - struct sram_piece *pused_head) -{ - struct sram_piece *pslot, *plast, *pavail; - - if (!pfree_head || !pused_head) - return -1; - - /* search the relevant memory slot */ - pslot = pused_head->next; - plast = pused_head; - - /* search an available piece slot */ - while (pslot != NULL && pslot->paddr != addr) { - plast = pslot; - pslot = pslot->next; - } - - if (!pslot) - return -1; - - plast->next = pslot->next; - pavail = pslot; - pavail->pid = 0; - - /* insert free pieces back to the free list */ - pslot = pfree_head->next; - plast = pfree_head; - - while (pslot != NULL && addr > pslot->paddr) { - plast = pslot; - pslot = pslot->next; - } - - if (plast != pfree_head && plast->paddr + plast->size == pavail->paddr) { - plast->size += pavail->size; - kmem_cache_free(sram_piece_cache, pavail); - } else { - pavail->next = plast->next; - plast->next = pavail; - plast = pavail; - } - - if (pslot && plast->paddr + plast->size == pslot->paddr) { - plast->size += pslot->size; - plast->next = pslot->next; - kmem_cache_free(sram_piece_cache, pslot); - } - - return 0; -} - -int sram_free(const void *addr) -{ - -#if L1_CODE_LENGTH != 0 - if (addr >= (void *)get_l1_code_start() - && addr < (void *)(get_l1_code_start() + L1_CODE_LENGTH)) - return l1_inst_sram_free(addr); - else -#endif -#if L1_DATA_A_LENGTH != 0 - if (addr >= (void *)get_l1_data_a_start() - && addr < (void *)(get_l1_data_a_start() + L1_DATA_A_LENGTH)) - return l1_data_A_sram_free(addr); - else -#endif -#if L1_DATA_B_LENGTH != 0 - if (addr >= (void *)get_l1_data_b_start() - && addr < (void *)(get_l1_data_b_start() + L1_DATA_B_LENGTH)) - return l1_data_B_sram_free(addr); - else -#endif -#if L2_LENGTH != 0 - if (addr >= (void *)L2_START - && addr < (void *)(L2_START + L2_LENGTH)) - return l2_sram_free(addr); - else -#endif - return -1; -} -EXPORT_SYMBOL(sram_free); - -void *l1_data_A_sram_alloc(size_t size) -{ -#if L1_DATA_A_LENGTH != 0 - unsigned long flags; - void *addr; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); - - addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu), - &per_cpu(used_l1_data_A_sram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); - - pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n", - (long unsigned int)addr, size); - - return addr; -#else - return NULL; -#endif -} -EXPORT_SYMBOL(l1_data_A_sram_alloc); - -int l1_data_A_sram_free(const void *addr) -{ -#if L1_DATA_A_LENGTH != 0 - unsigned long flags; - int ret; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); - - ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu), - &per_cpu(used_l1_data_A_sram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); - - return ret; -#else - return -1; -#endif -} -EXPORT_SYMBOL(l1_data_A_sram_free); - -void *l1_data_B_sram_alloc(size_t size) -{ -#if L1_DATA_B_LENGTH != 0 - unsigned long flags; - void *addr; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); - - addr = _sram_alloc(size, &per_cpu(free_l1_data_B_sram_head, cpu), - &per_cpu(used_l1_data_B_sram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); - - pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n", - (long unsigned int)addr, size); - - return addr; -#else - return NULL; -#endif -} -EXPORT_SYMBOL(l1_data_B_sram_alloc); - -int l1_data_B_sram_free(const void *addr) -{ -#if L1_DATA_B_LENGTH != 0 - unsigned long flags; - int ret; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); - - ret = _sram_free(addr, &per_cpu(free_l1_data_B_sram_head, cpu), - &per_cpu(used_l1_data_B_sram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); - - return ret; -#else - return -1; -#endif -} -EXPORT_SYMBOL(l1_data_B_sram_free); - -void *l1_data_sram_alloc(size_t size) -{ - void *addr = l1_data_A_sram_alloc(size); - - if (!addr) - addr = l1_data_B_sram_alloc(size); - - return addr; -} -EXPORT_SYMBOL(l1_data_sram_alloc); - -void *l1_data_sram_zalloc(size_t size) -{ - void *addr = l1_data_sram_alloc(size); - - if (addr) - memset(addr, 0x00, size); - - return addr; -} -EXPORT_SYMBOL(l1_data_sram_zalloc); - -int l1_data_sram_free(const void *addr) -{ - int ret; - ret = l1_data_A_sram_free(addr); - if (ret == -1) - ret = l1_data_B_sram_free(addr); - return ret; -} -EXPORT_SYMBOL(l1_data_sram_free); - -void *l1_inst_sram_alloc(size_t size) -{ -#if L1_CODE_LENGTH != 0 - unsigned long flags; - void *addr; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags); - - addr = _sram_alloc(size, &per_cpu(free_l1_inst_sram_head, cpu), - &per_cpu(used_l1_inst_sram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags); - - pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n", - (long unsigned int)addr, size); - - return addr; -#else - return NULL; -#endif -} -EXPORT_SYMBOL(l1_inst_sram_alloc); - -int l1_inst_sram_free(const void *addr) -{ -#if L1_CODE_LENGTH != 0 - unsigned long flags; - int ret; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags); - - ret = _sram_free(addr, &per_cpu(free_l1_inst_sram_head, cpu), - &per_cpu(used_l1_inst_sram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags); - - return ret; -#else - return -1; -#endif -} -EXPORT_SYMBOL(l1_inst_sram_free); - -/* L1 Scratchpad memory allocate function */ -void *l1sram_alloc(size_t size) -{ - unsigned long flags; - void *addr; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags); - - addr = _sram_alloc(size, &per_cpu(free_l1_ssram_head, cpu), - &per_cpu(used_l1_ssram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags); - - return addr; -} - -/* L1 Scratchpad memory allocate function */ -void *l1sram_alloc_max(size_t *psize) -{ - unsigned long flags; - void *addr; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags); - - addr = _sram_alloc_max(&per_cpu(free_l1_ssram_head, cpu), - &per_cpu(used_l1_ssram_head, cpu), psize); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags); - - return addr; -} - -/* L1 Scratchpad memory free function */ -int l1sram_free(const void *addr) -{ - unsigned long flags; - int ret; - unsigned int cpu; - - cpu = smp_processor_id(); - /* add mutex operation */ - spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags); - - ret = _sram_free(addr, &per_cpu(free_l1_ssram_head, cpu), - &per_cpu(used_l1_ssram_head, cpu)); - - /* add mutex operation */ - spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags); - - return ret; -} - -void *l2_sram_alloc(size_t size) -{ -#if L2_LENGTH != 0 - unsigned long flags; - void *addr; - - /* add mutex operation */ - spin_lock_irqsave(&l2_sram_lock, flags); - - addr = _sram_alloc(size, &free_l2_sram_head, - &used_l2_sram_head); - - /* add mutex operation */ - spin_unlock_irqrestore(&l2_sram_lock, flags); - - pr_debug("Allocated address in l2_sram_alloc is 0x%lx+0x%lx\n", - (long unsigned int)addr, size); - - return addr; -#else - return NULL; -#endif -} -EXPORT_SYMBOL(l2_sram_alloc); - -void *l2_sram_zalloc(size_t size) -{ - void *addr = l2_sram_alloc(size); - - if (addr) - memset(addr, 0x00, size); - - return addr; -} -EXPORT_SYMBOL(l2_sram_zalloc); - -int l2_sram_free(const void *addr) -{ -#if L2_LENGTH != 0 - unsigned long flags; - int ret; - - /* add mutex operation */ - spin_lock_irqsave(&l2_sram_lock, flags); - - ret = _sram_free(addr, &free_l2_sram_head, - &used_l2_sram_head); - - /* add mutex operation */ - spin_unlock_irqrestore(&l2_sram_lock, flags); - - return ret; -#else - return -1; -#endif -} -EXPORT_SYMBOL(l2_sram_free); - -int sram_free_with_lsl(const void *addr) -{ - struct sram_list_struct *lsl, **tmp; - struct mm_struct *mm = current->mm; - int ret = -1; - - for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next) - if ((*tmp)->addr == addr) { - lsl = *tmp; - ret = sram_free(addr); - *tmp = lsl->next; - kfree(lsl); - break; - } - - return ret; -} -EXPORT_SYMBOL(sram_free_with_lsl); - -/* Allocate memory and keep in L1 SRAM List (lsl) so that the resources are - * tracked. These are designed for userspace so that when a process exits, - * we can safely reap their resources. - */ -void *sram_alloc_with_lsl(size_t size, unsigned long flags) -{ - void *addr = NULL; - struct sram_list_struct *lsl = NULL; - struct mm_struct *mm = current->mm; - - lsl = kzalloc(sizeof(struct sram_list_struct), GFP_KERNEL); - if (!lsl) - return NULL; - - if (flags & L1_INST_SRAM) - addr = l1_inst_sram_alloc(size); - - if (addr == NULL && (flags & L1_DATA_A_SRAM)) - addr = l1_data_A_sram_alloc(size); - - if (addr == NULL && (flags & L1_DATA_B_SRAM)) - addr = l1_data_B_sram_alloc(size); - - if (addr == NULL && (flags & L2_SRAM)) - addr = l2_sram_alloc(size); - - if (addr == NULL) { - kfree(lsl); - return NULL; - } - lsl->addr = addr; - lsl->length = size; - lsl->next = mm->context.sram_list; - mm->context.sram_list = lsl; - return addr; -} -EXPORT_SYMBOL(sram_alloc_with_lsl); - -#ifdef CONFIG_PROC_FS -/* Once we get a real allocator, we'll throw all of this away. - * Until then, we need some sort of visibility into the L1 alloc. - */ -/* Need to keep line of output the same. Currently, that is 44 bytes - * (including newline). - */ -static int _sram_proc_show(struct seq_file *m, const char *desc, - struct sram_piece *pfree_head, - struct sram_piece *pused_head) -{ - struct sram_piece *pslot; - - if (!pfree_head || !pused_head) - return -1; - - seq_printf(m, "--- SRAM %-14s Size PID State \n", desc); - - /* search the relevant memory slot */ - pslot = pused_head->next; - - while (pslot != NULL) { - seq_printf(m, "%p-%p %10i %5i %-10s\n", - pslot->paddr, pslot->paddr + pslot->size, - pslot->size, pslot->pid, "ALLOCATED"); - - pslot = pslot->next; - } - - pslot = pfree_head->next; - - while (pslot != NULL) { - seq_printf(m, "%p-%p %10i %5i %-10s\n", - pslot->paddr, pslot->paddr + pslot->size, - pslot->size, pslot->pid, "FREE"); - - pslot = pslot->next; - } - - return 0; -} -static int sram_proc_show(struct seq_file *m, void *v) -{ - unsigned int cpu; - - for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { - if (_sram_proc_show(m, "Scratchpad", - &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu))) - goto not_done; -#if L1_DATA_A_LENGTH != 0 - if (_sram_proc_show(m, "L1 Data A", - &per_cpu(free_l1_data_A_sram_head, cpu), - &per_cpu(used_l1_data_A_sram_head, cpu))) - goto not_done; -#endif -#if L1_DATA_B_LENGTH != 0 - if (_sram_proc_show(m, "L1 Data B", - &per_cpu(free_l1_data_B_sram_head, cpu), - &per_cpu(used_l1_data_B_sram_head, cpu))) - goto not_done; -#endif -#if L1_CODE_LENGTH != 0 - if (_sram_proc_show(m, "L1 Instruction", - &per_cpu(free_l1_inst_sram_head, cpu), - &per_cpu(used_l1_inst_sram_head, cpu))) - goto not_done; -#endif - } -#if L2_LENGTH != 0 - if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head)) - goto not_done; -#endif - not_done: - return 0; -} - -static int sram_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, sram_proc_show, NULL); -} - -static const struct file_operations sram_proc_ops = { - .open = sram_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init sram_proc_init(void) -{ - struct proc_dir_entry *ptr; - - ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops); - if (!ptr) { - printk(KERN_WARNING "unable to create /proc/sram\n"); - return -1; - } - return 0; -} -late_initcall(sram_proc_init); -#endif diff --git a/arch/blackfin/oprofile/Makefile b/arch/blackfin/oprofile/Makefile deleted file mode 100644 index e89e1c9f3496..000000000000 --- a/arch/blackfin/oprofile/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/oprofile/Makefile -# - -obj-$(CONFIG_OPROFILE) += oprofile.o - -DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \ - oprof.o cpu_buffer.o buffer_sync.o \ - event_buffer.o oprofile_files.o \ - oprofilefs.o oprofile_stats.o \ - timer_int.o ) - -oprofile-y := $(DRIVER_OBJS) bfin_oprofile.o diff --git a/arch/blackfin/oprofile/bfin_oprofile.c b/arch/blackfin/oprofile/bfin_oprofile.c deleted file mode 100644 index c3b9713b23f8..000000000000 --- a/arch/blackfin/oprofile/bfin_oprofile.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * bfin_oprofile.c - Blackfin oprofile code - * - * Copyright 2004-2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include -#include - -int __init oprofile_arch_init(struct oprofile_operations *ops) -{ - return -1; -} - -void oprofile_arch_exit(void) -{ -} diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 5b211fe295f0..8796ba387152 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -29,7 +29,6 @@ enum cpuhp_state { CPUHP_PERF_PREPARE, CPUHP_PERF_X86_PREPARE, CPUHP_PERF_X86_AMD_UNCORE_PREP, - CPUHP_PERF_BFIN, CPUHP_PERF_POWER, CPUHP_PERF_SUPERH, CPUHP_X86_HPET_DEAD, diff --git a/samples/Kconfig b/samples/Kconfig index c332a3b9de05..f524f551718e 100644 --- a/samples/Kconfig +++ b/samples/Kconfig @@ -98,12 +98,6 @@ config SAMPLE_SECCOMP Build samples of seccomp filters using various methods of BPF filter construction. -config SAMPLE_BLACKFIN_GPTIMERS - tristate "Build blackfin gptimers sample code -- loadable modules only" - depends on BLACKFIN && BFIN_GPTIMERS && m - help - Build samples of blackfin gptimers sample module. - config SAMPLE_VFIO_MDEV_MTTY tristate "Build VFIO mtty example mediated device sample code -- loadable modules only" depends on VFIO_MDEV_DEVICE && m diff --git a/samples/Makefile b/samples/Makefile index db54e766ddb1..70cf3758dcf2 100644 --- a/samples/Makefile +++ b/samples/Makefile @@ -2,5 +2,5 @@ obj-$(CONFIG_SAMPLES) += kobject/ kprobes/ trace_events/ livepatch/ \ hw_breakpoint/ kfifo/ kdb/ hidraw/ rpmsg/ seccomp/ \ - configfs/ connector/ v4l/ trace_printk/ blackfin/ \ + configfs/ connector/ v4l/ trace_printk/ \ vfio-mdev/ statx/ diff --git a/samples/blackfin/Makefile b/samples/blackfin/Makefile deleted file mode 100644 index 89b86cfd83a2..000000000000 --- a/samples/blackfin/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_SAMPLE_BLACKFIN_GPTIMERS) += gptimers-example.o diff --git a/samples/blackfin/gptimers-example.c b/samples/blackfin/gptimers-example.c deleted file mode 100644 index 283eba993d9d..000000000000 --- a/samples/blackfin/gptimers-example.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Simple gptimers example - * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:gptimers - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include - -/* ... random driver includes ... */ - -#define DRIVER_NAME "gptimer_example" - -#ifdef IRQ_TIMER5 -#define SAMPLE_IRQ_TIMER IRQ_TIMER5 -#else -#define SAMPLE_IRQ_TIMER IRQ_TIMER2 -#endif - -struct gptimer_data { - uint32_t period, width; -}; -static struct gptimer_data data; - -/* ... random driver state ... */ - -static irqreturn_t gptimer_example_irq(int irq, void *dev_id) -{ - struct gptimer_data *data = dev_id; - - /* make sure it was our timer which caused the interrupt */ - if (!get_gptimer_intr(TIMER5_id)) - return IRQ_NONE; - - /* read the width/period values that were captured for the waveform */ - data->width = get_gptimer_pwidth(TIMER5_id); - data->period = get_gptimer_period(TIMER5_id); - - /* acknowledge the interrupt */ - clear_gptimer_intr(TIMER5_id); - - /* tell the upper layers we took care of things */ - return IRQ_HANDLED; -} - -/* ... random driver code ... */ - -static int __init gptimer_example_init(void) -{ - int ret; - - /* grab the peripheral pins */ - ret = peripheral_request(P_TMR5, DRIVER_NAME); - if (ret) { - printk(KERN_NOTICE DRIVER_NAME ": peripheral request failed\n"); - return ret; - } - - /* grab the IRQ for the timer */ - ret = request_irq(SAMPLE_IRQ_TIMER, gptimer_example_irq, - IRQF_SHARED, DRIVER_NAME, &data); - if (ret) { - printk(KERN_NOTICE DRIVER_NAME ": IRQ request failed\n"); - peripheral_free(P_TMR5); - return ret; - } - - /* setup the timer and enable it */ - set_gptimer_config(TIMER5_id, - WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA); - enable_gptimers(TIMER5bit); - - return 0; -} -module_init(gptimer_example_init); - -static void __exit gptimer_example_exit(void) -{ - disable_gptimers(TIMER5bit); - free_irq(SAMPLE_IRQ_TIMER, &data); - peripheral_free(P_TMR5); -} -module_exit(gptimer_example_exit); - -MODULE_LICENSE("BSD"); diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 3d4040322ae1..949842e8c97e 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2969,20 +2969,6 @@ sub process { "adding a line without newline at end of file\n" . $herecurr); } -# Blackfin: use hi/lo macros - if ($realfile =~ m@arch/blackfin/.*\.S$@) { - if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("LO_MACRO", - "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); - } - if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("HI_MACRO", - "use the HI() macro, not (... >> 16)\n" . $herevet); - } - } - # check we are in a valid source file C or perl if not then ignore this hunk next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/); @@ -3269,18 +3255,6 @@ sub process { "CVS style keyword markers, these will _not_ be updated\n". $herecurr); } -# Blackfin: don't use __builtin_bfin_[cs]sync - if ($line =~ /__builtin_bfin_csync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("CSYNC", - "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); - } - if ($line =~ /__builtin_bfin_ssync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("SSYNC", - "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); - } - # check for old HOTPLUG __dev section markings if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { WARN("HOTPLUG_SECTION", -- cgit v1.2.3 From 79375ea3ec527f746d5beae8c8f6e8a58740d4a8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 23:14:56 +0100 Subject: mm: remove obsolete alloc_remap() Tile was the only remaining architecture to implement alloc_remap(), and since that is being removed, there is no point in keeping this function. Removing all callers simplifies the mem_map handling. Reviewed-by: Pavel Tatashin Signed-off-by: Arnd Bergmann --- include/linux/bootmem.h | 9 --------- mm/page_alloc.c | 5 +---- mm/sparse.c | 15 --------------- 3 files changed, 1 insertion(+), 28 deletions(-) (limited to 'include/linux') diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h index a53063e9d7d8..7942a96b1a9d 100644 --- a/include/linux/bootmem.h +++ b/include/linux/bootmem.h @@ -364,15 +364,6 @@ static inline void __init memblock_free_late( } #endif /* defined(CONFIG_HAVE_MEMBLOCK) && defined(CONFIG_NO_BOOTMEM) */ -#ifdef CONFIG_HAVE_ARCH_ALLOC_REMAP -extern void *alloc_remap(int nid, unsigned long size); -#else -static inline void *alloc_remap(int nid, unsigned long size) -{ - return NULL; -} -#endif /* CONFIG_HAVE_ARCH_ALLOC_REMAP */ - extern void *alloc_large_system_hash(const char *tablename, unsigned long bucketsize, unsigned long numentries, diff --git a/mm/page_alloc.c b/mm/page_alloc.c index cb416723538f..484e21062228 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -6199,10 +6199,7 @@ static void __ref alloc_node_mem_map(struct pglist_data *pgdat) end = pgdat_end_pfn(pgdat); end = ALIGN(end, MAX_ORDER_NR_PAGES); size = (end - start) * sizeof(struct page); - map = alloc_remap(pgdat->node_id, size); - if (!map) - map = memblock_virt_alloc_node_nopanic(size, - pgdat->node_id); + map = memblock_virt_alloc_node_nopanic(size, pgdat->node_id); pgdat->node_mem_map = map + offset; } pr_debug("%s: node %d, pgdat %08lx, node_mem_map %08lx\n", diff --git a/mm/sparse.c b/mm/sparse.c index 7af5e7a92528..65bb52599f90 100644 --- a/mm/sparse.c +++ b/mm/sparse.c @@ -427,10 +427,6 @@ struct page __init *sparse_mem_map_populate(unsigned long pnum, int nid, struct page *map; unsigned long size; - map = alloc_remap(nid, sizeof(struct page) * PAGES_PER_SECTION); - if (map) - return map; - size = PAGE_ALIGN(sizeof(struct page) * PAGES_PER_SECTION); map = memblock_virt_alloc_try_nid(size, PAGE_SIZE, __pa(MAX_DMA_ADDRESS), @@ -446,17 +442,6 @@ void __init sparse_mem_maps_populate_node(struct page **map_map, unsigned long pnum; unsigned long size = sizeof(struct page) * PAGES_PER_SECTION; - map = alloc_remap(nodeid, size * map_count); - if (map) { - for (pnum = pnum_begin; pnum < pnum_end; pnum++) { - if (!present_section_nr(pnum)) - continue; - map_map[pnum] = map; - map += size; - } - return; - } - size = PAGE_ALIGN(size); map = memblock_virt_alloc_try_nid_raw(size * map_count, PAGE_SIZE, __pa(MAX_DMA_ADDRESS), -- cgit v1.2.3 From cbe7128c4b92e2004984f477fd38dfa81662f02e Mon Sep 17 00:00:00 2001 From: Toshiaki Makita Date: Tue, 13 Mar 2018 14:51:28 +0900 Subject: vlan: Fix out of order vlan headers with reorder header off With reorder header off, received packets are untagged in skb_vlan_untag() called from within __netif_receive_skb_core(), and later the tag will be inserted back in vlan_do_receive(). This caused out of order vlan headers when we create a vlan device on top of another vlan device, because vlan_do_receive() inserts a tag as the outermost vlan tag. E.g. the outer tag is first removed in skb_vlan_untag() and inserted back in vlan_do_receive(), then the inner tag is next removed and inserted back as the outermost tag. This patch fixes the behaviour by inserting the inner tag at the right position. Signed-off-by: Toshiaki Makita Signed-off-by: David S. Miller --- include/linux/if_vlan.h | 66 ++++++++++++++++++++++++++++++++++++++++--------- net/8021q/vlan_core.c | 4 +-- 2 files changed, 57 insertions(+), 13 deletions(-) (limited to 'include/linux') diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index 5e6a2d4dc366..c4a1cff9c768 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -300,30 +300,34 @@ static inline bool vlan_hw_offload_capable(netdev_features_t features, } /** - * __vlan_insert_tag - regular VLAN tag inserting + * __vlan_insert_inner_tag - inner VLAN tag inserting * @skb: skbuff to tag * @vlan_proto: VLAN encapsulation protocol * @vlan_tci: VLAN TCI to insert + * @mac_len: MAC header length including outer vlan headers * - * Inserts the VLAN tag into @skb as part of the payload + * Inserts the VLAN tag into @skb as part of the payload at offset mac_len * Returns error if skb_cow_head failes. * * Does not change skb->protocol so this function can be used during receive. */ -static inline int __vlan_insert_tag(struct sk_buff *skb, - __be16 vlan_proto, u16 vlan_tci) +static inline int __vlan_insert_inner_tag(struct sk_buff *skb, + __be16 vlan_proto, u16 vlan_tci, + unsigned int mac_len) { struct vlan_ethhdr *veth; if (skb_cow_head(skb, VLAN_HLEN) < 0) return -ENOMEM; - veth = skb_push(skb, VLAN_HLEN); + skb_push(skb, VLAN_HLEN); - /* Move the mac addresses to the beginning of the new header. */ - memmove(skb->data, skb->data + VLAN_HLEN, 2 * ETH_ALEN); + /* Move the mac header sans proto to the beginning of the new header. */ + memmove(skb->data, skb->data + VLAN_HLEN, mac_len - ETH_TLEN); skb->mac_header -= VLAN_HLEN; + veth = (struct vlan_ethhdr *)(skb->data + mac_len - ETH_HLEN); + /* first, the ethernet type */ veth->h_vlan_proto = vlan_proto; @@ -334,12 +338,30 @@ static inline int __vlan_insert_tag(struct sk_buff *skb, } /** - * vlan_insert_tag - regular VLAN tag inserting + * __vlan_insert_tag - regular VLAN tag inserting * @skb: skbuff to tag * @vlan_proto: VLAN encapsulation protocol * @vlan_tci: VLAN TCI to insert * * Inserts the VLAN tag into @skb as part of the payload + * Returns error if skb_cow_head failes. + * + * Does not change skb->protocol so this function can be used during receive. + */ +static inline int __vlan_insert_tag(struct sk_buff *skb, + __be16 vlan_proto, u16 vlan_tci) +{ + return __vlan_insert_inner_tag(skb, vlan_proto, vlan_tci, ETH_HLEN); +} + +/** + * vlan_insert_inner_tag - inner VLAN tag inserting + * @skb: skbuff to tag + * @vlan_proto: VLAN encapsulation protocol + * @vlan_tci: VLAN TCI to insert + * @mac_len: MAC header length including outer vlan headers + * + * Inserts the VLAN tag into @skb as part of the payload at offset mac_len * Returns a VLAN tagged skb. If a new skb is created, @skb is freed. * * Following the skb_unshare() example, in case of error, the calling function @@ -347,12 +369,14 @@ static inline int __vlan_insert_tag(struct sk_buff *skb, * * Does not change skb->protocol so this function can be used during receive. */ -static inline struct sk_buff *vlan_insert_tag(struct sk_buff *skb, - __be16 vlan_proto, u16 vlan_tci) +static inline struct sk_buff *vlan_insert_inner_tag(struct sk_buff *skb, + __be16 vlan_proto, + u16 vlan_tci, + unsigned int mac_len) { int err; - err = __vlan_insert_tag(skb, vlan_proto, vlan_tci); + err = __vlan_insert_inner_tag(skb, vlan_proto, vlan_tci, mac_len); if (err) { dev_kfree_skb_any(skb); return NULL; @@ -360,6 +384,26 @@ static inline struct sk_buff *vlan_insert_tag(struct sk_buff *skb, return skb; } +/** + * vlan_insert_tag - regular VLAN tag inserting + * @skb: skbuff to tag + * @vlan_proto: VLAN encapsulation protocol + * @vlan_tci: VLAN TCI to insert + * + * Inserts the VLAN tag into @skb as part of the payload + * Returns a VLAN tagged skb. If a new skb is created, @skb is freed. + * + * Following the skb_unshare() example, in case of error, the calling function + * doesn't have to worry about freeing the original skb. + * + * Does not change skb->protocol so this function can be used during receive. + */ +static inline struct sk_buff *vlan_insert_tag(struct sk_buff *skb, + __be16 vlan_proto, u16 vlan_tci) +{ + return vlan_insert_inner_tag(skb, vlan_proto, vlan_tci, ETH_HLEN); +} + /** * vlan_insert_tag_set_proto - regular VLAN tag inserting * @skb: skbuff to tag diff --git a/net/8021q/vlan_core.c b/net/8021q/vlan_core.c index 64aa9f755e1d..45c9bf5ff3a0 100644 --- a/net/8021q/vlan_core.c +++ b/net/8021q/vlan_core.c @@ -48,8 +48,8 @@ bool vlan_do_receive(struct sk_buff **skbp) * original position later */ skb_push(skb, offset); - skb = *skbp = vlan_insert_tag(skb, skb->vlan_proto, - skb->vlan_tci); + skb = *skbp = vlan_insert_inner_tag(skb, skb->vlan_proto, + skb->vlan_tci, skb->mac_len); if (!skb) return false; skb_pull(skb, offset + VLAN_HLEN); -- cgit v1.2.3 From 79ffdfc6522ae33d8a33e971070c08ee5f27439b Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Wed, 14 Mar 2018 22:17:20 +0300 Subject: net: Add rtnl_lock_killable() rtnl_lock() is widely used mutex in kernel. Some of kernel code does memory allocations under it. In case of memory deficit this may invoke OOM killer, but the problem is a killed task can't exit if it's waiting for the mutex. This may be a reason of deadlock and panic. This patch adds a new primitive, which responds on SIGKILL, and it allows to use it in the places, where we don't want to sleep forever. Signed-off-by: Kirill Tkhai Signed-off-by: David S. Miller --- include/linux/rtnetlink.h | 1 + net/core/rtnetlink.c | 6 ++++++ 2 files changed, 7 insertions(+) (limited to 'include/linux') diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 3573b4bf2fdf..562a175c35a9 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -33,6 +33,7 @@ extern void rtnl_lock(void); extern void rtnl_unlock(void); extern int rtnl_trylock(void); extern int rtnl_is_locked(void); +extern int rtnl_lock_killable(void); extern wait_queue_head_t netdev_unregistering_wq; extern struct rw_semaphore net_sem; diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 67f375cfb982..87079eaa871b 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -75,6 +75,12 @@ void rtnl_lock(void) } EXPORT_SYMBOL(rtnl_lock); +int rtnl_lock_killable(void) +{ + return mutex_lock_killable(&rtnl_mutex); +} +EXPORT_SYMBOL(rtnl_lock_killable); + static struct sk_buff *defer_kfree_skb_list; void rtnl_kfree_skbs(struct sk_buff *head, struct sk_buff *tail) { -- cgit v1.2.3 From 4c6994806f708559c2812b73501406e21ae5dcd0 Mon Sep 17 00:00:00 2001 From: Joseph Qi Date: Fri, 16 Mar 2018 14:51:27 +0800 Subject: blk-throttle: fix race between blkcg_bio_issue_check() and cgroup_rmdir() We've triggered a WARNING in blk_throtl_bio() when throttling writeback io, which complains blkg->refcnt is already 0 when calling blkg_get(), and then kernel crashes with invalid page request. After investigating this issue, we've found it is caused by a race between blkcg_bio_issue_check() and cgroup_rmdir(), which is described below: writeback kworker cgroup_rmdir cgroup_destroy_locked kill_css css_killed_ref_fn css_killed_work_fn offline_css blkcg_css_offline blkcg_bio_issue_check rcu_read_lock blkg_lookup spin_trylock(q->queue_lock) blkg_destroy spin_unlock(q->queue_lock) blk_throtl_bio spin_lock_irq(q->queue_lock) ... spin_unlock_irq(q->queue_lock) rcu_read_unlock Since rcu can only prevent blkg from releasing when it is being used, the blkg->refcnt can be decreased to 0 during blkg_destroy() and schedule blkg release. Then trying to blkg_get() in blk_throtl_bio() will complains the WARNING. And then the corresponding blkg_put() will schedule blkg release again, which result in double free. This race is introduced by commit ae1188963611 ("blkcg: consolidate blkg creation in blkcg_bio_issue_check()"). Before this commit, it will lookup first and then try to lookup/create again with queue_lock. Since revive this logic is a bit drastic, so fix it by only offlining pd during blkcg_css_offline(), and move the rest destruction (especially blkg_put()) into blkcg_css_free(), which should be the right way as discussed. Fixes: ae1188963611 ("blkcg: consolidate blkg creation in blkcg_bio_issue_check()") Reported-by: Jiufei Xue Signed-off-by: Joseph Qi Acked-by: Tejun Heo Signed-off-by: Jens Axboe --- block/blk-cgroup.c | 78 ++++++++++++++++++++++++++++++++++++---------- include/linux/blk-cgroup.h | 1 + 2 files changed, 63 insertions(+), 16 deletions(-) (limited to 'include/linux') diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c index c2033a232a44..1c16694ae145 100644 --- a/block/blk-cgroup.c +++ b/block/blk-cgroup.c @@ -307,11 +307,28 @@ struct blkcg_gq *blkg_lookup_create(struct blkcg *blkcg, } } +static void blkg_pd_offline(struct blkcg_gq *blkg) +{ + int i; + + lockdep_assert_held(blkg->q->queue_lock); + lockdep_assert_held(&blkg->blkcg->lock); + + for (i = 0; i < BLKCG_MAX_POLS; i++) { + struct blkcg_policy *pol = blkcg_policy[i]; + + if (blkg->pd[i] && !blkg->pd[i]->offline && + pol->pd_offline_fn) { + pol->pd_offline_fn(blkg->pd[i]); + blkg->pd[i]->offline = true; + } + } +} + static void blkg_destroy(struct blkcg_gq *blkg) { struct blkcg *blkcg = blkg->blkcg; struct blkcg_gq *parent = blkg->parent; - int i; lockdep_assert_held(blkg->q->queue_lock); lockdep_assert_held(&blkcg->lock); @@ -320,13 +337,6 @@ static void blkg_destroy(struct blkcg_gq *blkg) WARN_ON_ONCE(list_empty(&blkg->q_node)); WARN_ON_ONCE(hlist_unhashed(&blkg->blkcg_node)); - for (i = 0; i < BLKCG_MAX_POLS; i++) { - struct blkcg_policy *pol = blkcg_policy[i]; - - if (blkg->pd[i] && pol->pd_offline_fn) - pol->pd_offline_fn(blkg->pd[i]); - } - if (parent) { blkg_rwstat_add_aux(&parent->stat_bytes, &blkg->stat_bytes); blkg_rwstat_add_aux(&parent->stat_ios, &blkg->stat_ios); @@ -369,6 +379,7 @@ static void blkg_destroy_all(struct request_queue *q) struct blkcg *blkcg = blkg->blkcg; spin_lock(&blkcg->lock); + blkg_pd_offline(blkg); blkg_destroy(blkg); spin_unlock(&blkcg->lock); } @@ -995,25 +1006,25 @@ static struct cftype blkcg_legacy_files[] = { * @css: css of interest * * This function is called when @css is about to go away and responsible - * for shooting down all blkgs associated with @css. blkgs should be - * removed while holding both q and blkcg locks. As blkcg lock is nested - * inside q lock, this function performs reverse double lock dancing. + * for offlining all blkgs pd and killing all wbs associated with @css. + * blkgs pd offline should be done while holding both q and blkcg locks. + * As blkcg lock is nested inside q lock, this function performs reverse + * double lock dancing. * * This is the blkcg counterpart of ioc_release_fn(). */ static void blkcg_css_offline(struct cgroup_subsys_state *css) { struct blkcg *blkcg = css_to_blkcg(css); + struct blkcg_gq *blkg; spin_lock_irq(&blkcg->lock); - while (!hlist_empty(&blkcg->blkg_list)) { - struct blkcg_gq *blkg = hlist_entry(blkcg->blkg_list.first, - struct blkcg_gq, blkcg_node); + hlist_for_each_entry(blkg, &blkcg->blkg_list, blkcg_node) { struct request_queue *q = blkg->q; if (spin_trylock(q->queue_lock)) { - blkg_destroy(blkg); + blkg_pd_offline(blkg); spin_unlock(q->queue_lock); } else { spin_unlock_irq(&blkcg->lock); @@ -1027,11 +1038,43 @@ static void blkcg_css_offline(struct cgroup_subsys_state *css) wb_blkcg_offline(blkcg); } +/** + * blkcg_destroy_all_blkgs - destroy all blkgs associated with a blkcg + * @blkcg: blkcg of interest + * + * This function is called when blkcg css is about to free and responsible for + * destroying all blkgs associated with @blkcg. + * blkgs should be removed while holding both q and blkcg locks. As blkcg lock + * is nested inside q lock, this function performs reverse double lock dancing. + */ +static void blkcg_destroy_all_blkgs(struct blkcg *blkcg) +{ + spin_lock_irq(&blkcg->lock); + while (!hlist_empty(&blkcg->blkg_list)) { + struct blkcg_gq *blkg = hlist_entry(blkcg->blkg_list.first, + struct blkcg_gq, + blkcg_node); + struct request_queue *q = blkg->q; + + if (spin_trylock(q->queue_lock)) { + blkg_destroy(blkg); + spin_unlock(q->queue_lock); + } else { + spin_unlock_irq(&blkcg->lock); + cpu_relax(); + spin_lock_irq(&blkcg->lock); + } + } + spin_unlock_irq(&blkcg->lock); +} + static void blkcg_css_free(struct cgroup_subsys_state *css) { struct blkcg *blkcg = css_to_blkcg(css); int i; + blkcg_destroy_all_blkgs(blkcg); + mutex_lock(&blkcg_pol_mutex); list_del(&blkcg->all_blkcgs_node); @@ -1371,8 +1414,11 @@ void blkcg_deactivate_policy(struct request_queue *q, spin_lock(&blkg->blkcg->lock); if (blkg->pd[pol->plid]) { - if (pol->pd_offline_fn) + if (!blkg->pd[pol->plid]->offline && + pol->pd_offline_fn) { pol->pd_offline_fn(blkg->pd[pol->plid]); + blkg->pd[pol->plid]->offline = true; + } pol->pd_free_fn(blkg->pd[pol->plid]); blkg->pd[pol->plid] = NULL; } diff --git a/include/linux/blk-cgroup.h b/include/linux/blk-cgroup.h index 69bea82ebeb1..6c666fd7de3c 100644 --- a/include/linux/blk-cgroup.h +++ b/include/linux/blk-cgroup.h @@ -88,6 +88,7 @@ struct blkg_policy_data { /* the blkg and policy id this per-policy data belongs to */ struct blkcg_gq *blkg; int plid; + bool offline; }; /* -- cgit v1.2.3 From f29ab49b5388b2f829cf99859bc5f8ad8ec4d06a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 16 Mar 2018 14:25:40 +0100 Subject: dma-mapping: Convert NO_DMA get_dma_ops() into a real dummy If NO_DMA=y, get_dma_ops() returns a reference to the non-existing symbol bad_dma_ops, thus causing a link failure if it is ever used. Make get_dma_ops() return NULL instead, to avoid the link failure. This allows to improve compile-testing, and limits the need to keep on sprinkling dependencies on HAS_DMA all over the place. Signed-off-by: Geert Uytterhoeven Reviewed-by: Mark Brown Acked-by: Robin Murphy Signed-off-by: Christoph Hellwig --- include/linux/dma-mapping.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index eb9eab4ecd6d..5ea7eec83c0f 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -212,14 +212,14 @@ static inline void set_dma_ops(struct device *dev, } #else /* - * Define the dma api to allow compilation but not linking of - * dma dependent code. Code that depends on the dma-mapping - * API needs to set 'depends on HAS_DMA' in its Kconfig + * Define the dma api to allow compilation of dma dependent code. + * Code that depends on the dma-mapping API needs to set 'depends on HAS_DMA' + * in its Kconfig, unless it already depends on || COMPILE_TEST, + * where guarantuees the availability of the dma-mapping API. */ -extern const struct dma_map_ops bad_dma_ops; static inline const struct dma_map_ops *get_dma_ops(struct device *dev) { - return &bad_dma_ops; + return NULL; } #endif -- cgit v1.2.3 From ab642e952f80c66c5592f0e2c35588843a813df8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 16 Mar 2018 14:25:41 +0100 Subject: dma-coherent: Add NO_DMA dummies for managed DMA API Add dummies for dmam_{alloc,free}_coherent(), to allow compile-testing if NO_DMA=y. This prevents the following from showing up later: ERROR: "dmam_alloc_coherent" [drivers/net/ethernet/arc/arc_emac.ko] undefined! ERROR: "dmam_free_coherent" [drivers/net/ethernet/apm/xgene/xgene-enet.ko] undefined! ERROR: "dmam_alloc_coherent" [drivers/net/ethernet/apm/xgene/xgene-enet.ko] undefined! ERROR: "dmam_alloc_coherent" [drivers/mtd/nand/hisi504_nand.ko] undefined! ERROR: "dmam_alloc_coherent" [drivers/mmc/host/dw_mmc.ko] undefined! Signed-off-by: Geert Uytterhoeven Reviewed-by: Mark Brown Acked-by: Robin Murphy Signed-off-by: Christoph Hellwig --- include/linux/dma-mapping.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/linux') diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 5ea7eec83c0f..94f41846b933 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -776,10 +776,19 @@ static inline void dma_deconfigure(struct device *dev) {} /* * Managed DMA API */ +#ifdef CONFIG_HAS_DMA extern void *dmam_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp); extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle); +#else /* !CONFIG_HAS_DMA */ +static inline void *dmam_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp) +{ return NULL; } +static inline void dmam_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) { } +#endif /* !CONFIG_HAS_DMA */ + extern void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs); -- cgit v1.2.3 From c1ce6c2beea38171a57c56e55875318cef9a2ad5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 16 Mar 2018 14:25:43 +0100 Subject: mm: Add NO_DMA dummies for DMA pool API Add dummies for dma{,m}_pool_{create,destroy,alloc,free}(), to allow compile-testing if NO_DMA=y. This prevents the following from showing up later: ERROR: "dma_pool_destroy" [drivers/usb/mtu3/mtu3.ko] undefined! ERROR: "dma_pool_free" [drivers/usb/mtu3/mtu3.ko] undefined! ERROR: "dma_pool_alloc" [drivers/usb/mtu3/mtu3.ko] undefined! ERROR: "dma_pool_create" [drivers/usb/mtu3/mtu3.ko] undefined! ERROR: "dma_pool_destroy" [drivers/scsi/hisi_sas/hisi_sas_main.ko] undefined! ERROR: "dma_pool_free" [drivers/scsi/hisi_sas/hisi_sas_main.ko] undefined! ERROR: "dma_pool_alloc" [drivers/scsi/hisi_sas/hisi_sas_main.ko] undefined! ERROR: "dma_pool_create" [drivers/scsi/hisi_sas/hisi_sas_main.ko] undefined! ERROR: "dma_pool_alloc" [drivers/mailbox/bcm-pdc-mailbox.ko] undefined! ERROR: "dma_pool_free" [drivers/mailbox/bcm-pdc-mailbox.ko] undefined! ERROR: "dma_pool_create" [drivers/mailbox/bcm-pdc-mailbox.ko] undefined! ERROR: "dma_pool_destroy" [drivers/mailbox/bcm-pdc-mailbox.ko] undefined! Signed-off-by: Geert Uytterhoeven Reviewed-by: Mark Brown Acked-by: Robin Murphy Signed-off-by: Christoph Hellwig --- include/linux/dmapool.h | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/include/linux/dmapool.h b/include/linux/dmapool.h index 53ba737505df..f632ecfb4238 100644 --- a/include/linux/dmapool.h +++ b/include/linux/dmapool.h @@ -16,6 +16,8 @@ struct device; +#ifdef CONFIG_HAS_DMA + struct dma_pool *dma_pool_create(const char *name, struct device *dev, size_t size, size_t align, size_t allocation); @@ -23,13 +25,6 @@ void dma_pool_destroy(struct dma_pool *pool); void *dma_pool_alloc(struct dma_pool *pool, gfp_t mem_flags, dma_addr_t *handle); - -static inline void *dma_pool_zalloc(struct dma_pool *pool, gfp_t mem_flags, - dma_addr_t *handle) -{ - return dma_pool_alloc(pool, mem_flags | __GFP_ZERO, handle); -} - void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t addr); /* @@ -39,5 +34,26 @@ struct dma_pool *dmam_pool_create(const char *name, struct device *dev, size_t size, size_t align, size_t allocation); void dmam_pool_destroy(struct dma_pool *pool); +#else /* !CONFIG_HAS_DMA */ +static inline struct dma_pool *dma_pool_create(const char *name, + struct device *dev, size_t size, size_t align, size_t allocation) +{ return NULL; } +static inline void dma_pool_destroy(struct dma_pool *pool) { } +static inline void *dma_pool_alloc(struct dma_pool *pool, gfp_t mem_flags, + dma_addr_t *handle) { return NULL; } +static inline void dma_pool_free(struct dma_pool *pool, void *vaddr, + dma_addr_t addr) { } +static inline struct dma_pool *dmam_pool_create(const char *name, + struct device *dev, size_t size, size_t align, size_t allocation) +{ return NULL; } +static inline void dmam_pool_destroy(struct dma_pool *pool) { } +#endif /* !CONFIG_HAS_DMA */ + +static inline void *dma_pool_zalloc(struct dma_pool *pool, gfp_t mem_flags, + dma_addr_t *handle) +{ + return dma_pool_alloc(pool, mem_flags | __GFP_ZERO, handle); +} + #endif -- cgit v1.2.3 From 1f674e16f9ce6eb20ee2e81ae7514737376874de Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 16 Mar 2018 14:25:42 +0100 Subject: usb: gadget: Add NO_DMA dummies for DMA mapping API Add dummies for usb_gadget_{,un}map_request{,_by_dev}(), to allow compile-testing if NO_DMA=y. This prevents the following from showing up later: ERROR: "usb_gadget_unmap_request_by_dev" [drivers/usb/renesas_usbhs/renesas_usbhs.ko] undefined! ERROR: "usb_gadget_map_request_by_dev" [drivers/usb/renesas_usbhs/renesas_usbhs.ko] undefined! ERROR: "usb_gadget_map_request" [drivers/usb/mtu3/mtu3.ko] undefined! ERROR: "usb_gadget_unmap_request" [drivers/usb/mtu3/mtu3.ko] undefined! ERROR: "usb_gadget_map_request" [drivers/usb/gadget/udc/renesas_usb3.ko] undefined! ERROR: "usb_gadget_unmap_request" [drivers/usb/gadget/udc/renesas_usb3.ko] undefined! Signed-off-by: Geert Uytterhoeven Reviewed-by: Mark Brown Acked-by: Felipe Balbi Acked-by: Greg Kroah-Hartman Acked-by: Robin Murphy Signed-off-by: Christoph Hellwig --- include/linux/usb/gadget.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/linux') diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 66a5cff7ee14..b68e7f9b210b 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -805,6 +805,7 @@ int usb_otg_descriptor_init(struct usb_gadget *gadget, /* utility to simplify map/unmap of usb_requests to/from DMA */ +#ifdef CONFIG_HAS_DMA extern int usb_gadget_map_request_by_dev(struct device *dev, struct usb_request *req, int is_in); extern int usb_gadget_map_request(struct usb_gadget *gadget, @@ -814,6 +815,17 @@ extern void usb_gadget_unmap_request_by_dev(struct device *dev, struct usb_request *req, int is_in); extern void usb_gadget_unmap_request(struct usb_gadget *gadget, struct usb_request *req, int is_in); +#else /* !CONFIG_HAS_DMA */ +static inline int usb_gadget_map_request_by_dev(struct device *dev, + struct usb_request *req, int is_in) { return -ENOSYS; } +static inline int usb_gadget_map_request(struct usb_gadget *gadget, + struct usb_request *req, int is_in) { return -ENOSYS; } + +static inline void usb_gadget_unmap_request_by_dev(struct device *dev, + struct usb_request *req, int is_in) { } +static inline void usb_gadget_unmap_request(struct usb_gadget *gadget, + struct usb_request *req, int is_in) { } +#endif /* !CONFIG_HAS_DMA */ /*-------------------------------------------------------------------------*/ -- cgit v1.2.3 From edb39592a5877bd91b2e6ee15194268f35b04892 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 15 Mar 2018 17:36:56 +0100 Subject: perf: Fix sibling iteration Mark noticed that the change to sibling_list changed some iteration semantics; because previously we used group_list as list entry, sibling events would always have an empty sibling_list. But because we now use sibling_list for both list head and list entry, siblings will report as having siblings. Fix this with a custom for_each_sibling_event() iterator. Fixes: 8343aae66167 ("perf/core: Remove perf_event::group_entry") Reported-by: Mark Rutland Suggested-by: Mark Rutland Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Thomas Gleixner Cc: vincent.weaver@maine.edu Cc: alexander.shishkin@linux.intel.com Cc: torvalds@linux-foundation.org Cc: alexey.budankov@linux.intel.com Cc: valery.cherepennikov@intel.com Cc: eranian@google.com Cc: acme@redhat.com Cc: linux-tip-commits@vger.kernel.org Cc: davidcc@google.com Cc: kan.liang@intel.com Cc: Dmitry.Prohorov@intel.com Cc: jolsa@redhat.com Link: https://lkml.kernel.org/r/20180315170129.GX4043@hirez.programming.kicks-ass.net --- arch/alpha/kernel/perf_event.c | 2 +- arch/arm/mach-imx/mmdc.c | 2 +- arch/arm/mm/cache-l2x0-pmu.c | 2 +- arch/mips/kernel/perf_event_mipsxx.c | 2 +- arch/powerpc/perf/core-book3s.c | 2 +- arch/powerpc/perf/core-fsl-emb.c | 2 +- arch/sparc/kernel/perf_event.c | 2 +- arch/x86/events/core.c | 2 +- arch/x86/events/intel/uncore.c | 2 +- drivers/bus/arm-cci.c | 2 +- drivers/bus/arm-ccn.c | 4 ++-- drivers/perf/arm_dsu_pmu.c | 2 +- drivers/perf/arm_pmu.c | 2 +- drivers/perf/hisilicon/hisi_uncore_pmu.c | 2 +- drivers/perf/qcom_l2_pmu.c | 7 +++---- drivers/perf/qcom_l3_pmu.c | 2 +- drivers/perf/xgene_pmu.c | 4 ++-- include/linux/perf_event.h | 4 ++++ kernel/events/core.c | 34 +++++++++++++++----------------- 19 files changed, 41 insertions(+), 40 deletions(-) (limited to 'include/linux') diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 435864c24479..5613aa378a83 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -351,7 +351,7 @@ static int collect_events(struct perf_event *group, int max_count, evtype[n] = group->hw.event_base; current_idx[n++] = PMC_NO_INDEX; } - list_for_each_entry(pe, &group->sibling_list, sibling_list) { + for_each_sibling_event(pe, group) { if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) return -1; diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 27a9ca20933e..04b3bf71de94 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -269,7 +269,7 @@ static bool mmdc_pmu_group_is_valid(struct perf_event *event) return false; } - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, leader) { if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) return false; } diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c index 3a89ea4c2b57..afe5b4c7b164 100644 --- a/arch/arm/mm/cache-l2x0-pmu.c +++ b/arch/arm/mm/cache-l2x0-pmu.c @@ -293,7 +293,7 @@ static bool l2x0_pmu_group_is_valid(struct perf_event *event) else if (!is_software_event(leader)) return false; - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, leader) { if (sibling->pmu == pmu) num_hw++; else if (!is_software_event(sibling)) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 46097ff3208b..ee73550f0b9a 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -711,7 +711,7 @@ static int validate_group(struct perf_event *event) if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) return -EINVAL; - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, leader) { if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) return -EINVAL; } diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 7c1f66050433..f8908ea4ea73 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -1426,7 +1426,7 @@ static int collect_events(struct perf_event *group, int max_count, flags[n] = group->hw.event_base; events[n++] = group->hw.config; } - list_for_each_entry(event, &group->sibling_list, sibling_list) { + for_each_sibling_event(event, group) { if (event->pmu->task_ctx_nr == perf_hw_context && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c index 94c2e63662c6..85f1d18e5fd3 100644 --- a/arch/powerpc/perf/core-fsl-emb.c +++ b/arch/powerpc/perf/core-fsl-emb.c @@ -277,7 +277,7 @@ static int collect_events(struct perf_event *group, int max_count, ctrs[n] = group; n++; } - list_for_each_entry(event, &group->sibling_list, sibling_list) { + for_each_sibling_event(event, group) { if (!is_software_event(event) && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index a0a86d369119..d3149baaa33c 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1342,7 +1342,7 @@ static int collect_events(struct perf_event *group, int max_count, events[n] = group->hw.event_base; current_idx[n++] = PIC_NO_INDEX; } - list_for_each_entry(event, &group->sibling_list, sibling_list) { + for_each_sibling_event(event, group) { if (!is_software_event(event) && event->state != PERF_EVENT_STATE_OFF) { if (n >= max_count) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 77a4125b6b1f..bfc8f43909c1 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -990,7 +990,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, if (!dogrp) return n; - list_for_each_entry(event, &leader->sibling_list, sibling_list) { + for_each_sibling_event(event, leader) { if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF) continue; diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 9e374cd22ad2..a7956fc7ca1d 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -354,7 +354,7 @@ uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, if (!dogrp) return n; - list_for_each_entry(event, &leader->sibling_list, sibling_list) { + for_each_sibling_event(event, leader) { if (!is_box_event(box, event) || event->state <= PERF_EVENT_STATE_OFF) continue; diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index c98435bdb64f..c4c0c8560cce 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -1311,7 +1311,7 @@ validate_group(struct perf_event *event) if (!validate_event(event->pmu, &fake_pmu, leader)) return -EINVAL; - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, leader) { if (!validate_event(event->pmu, &fake_pmu, sibling)) return -EINVAL; } diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index 1c310a4be000..65b7e4042ece 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -846,11 +846,11 @@ static int arm_ccn_pmu_event_init(struct perf_event *event) !is_software_event(event->group_leader)) return -EINVAL; - list_for_each_entry(sibling, &event->group_leader->sibling_list, - sibling_list) + for_each_sibling_event(sibling, event->group_leader) { if (sibling->pmu != event->pmu && !is_software_event(sibling)) return -EINVAL; + } return 0; } diff --git a/drivers/perf/arm_dsu_pmu.c b/drivers/perf/arm_dsu_pmu.c index 660680d78147..660cb8ac886a 100644 --- a/drivers/perf/arm_dsu_pmu.c +++ b/drivers/perf/arm_dsu_pmu.c @@ -536,7 +536,7 @@ static bool dsu_pmu_validate_group(struct perf_event *event) memset(fake_hw.used_mask, 0, sizeof(fake_hw.used_mask)); if (!dsu_pmu_validate_event(event->pmu, &fake_hw, leader)) return false; - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, leader) { if (!dsu_pmu_validate_event(event->pmu, &fake_hw, sibling)) return false; } diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 628d7a7b9526..344e2083e941 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -311,7 +311,7 @@ validate_group(struct perf_event *event) if (!validate_event(event->pmu, &fake_pmu, leader)) return -EINVAL; - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, leader) { if (!validate_event(event->pmu, &fake_pmu, sibling)) return -EINVAL; } diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c index e3356087fd76..44df61397a38 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -82,7 +82,7 @@ static bool hisi_validate_event_group(struct perf_event *event) counters++; } - list_for_each_entry(sibling, &event->group_leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, event->group_leader) { if (is_software_event(sibling)) continue; if (sibling->pmu != event->pmu) diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c index 5e535a718965..842135cf35a3 100644 --- a/drivers/perf/qcom_l2_pmu.c +++ b/drivers/perf/qcom_l2_pmu.c @@ -534,14 +534,14 @@ static int l2_cache_event_init(struct perf_event *event) return -EINVAL; } - list_for_each_entry(sibling, &event->group_leader->sibling_list, - sibling_list) + for_each_sibling_event(sibling, event->group_leader) { if (sibling->pmu != event->pmu && !is_software_event(sibling)) { dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, "Can't create mixed PMU group\n"); return -EINVAL; } + } cluster = get_cluster_pmu(l2cache_pmu, event->cpu); if (!cluster) { @@ -571,8 +571,7 @@ static int l2_cache_event_init(struct perf_event *event) return -EINVAL; } - list_for_each_entry(sibling, &event->group_leader->sibling_list, - sibling_list) { + for_each_sibling_event(sibling, event->group_leader) { if ((sibling != event) && !is_software_event(sibling) && (L2_EVT_GROUP(sibling->attr.config) == diff --git a/drivers/perf/qcom_l3_pmu.c b/drivers/perf/qcom_l3_pmu.c index 5dedf4b1a552..2dc63d61f2ea 100644 --- a/drivers/perf/qcom_l3_pmu.c +++ b/drivers/perf/qcom_l3_pmu.c @@ -468,7 +468,7 @@ static bool qcom_l3_cache__validate_event_group(struct perf_event *event) counters = event_num_counters(event); counters += event_num_counters(leader); - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sibling, leader) { if (is_software_event(sibling)) continue; if (sibling->pmu != event->pmu) diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c index f1f4a56cab5e..6bdb1dad805f 100644 --- a/drivers/perf/xgene_pmu.c +++ b/drivers/perf/xgene_pmu.c @@ -949,11 +949,11 @@ static int xgene_perf_event_init(struct perf_event *event) !is_software_event(event->group_leader)) return -EINVAL; - list_for_each_entry(sibling, &event->group_leader->sibling_list, - sibling_list) + for_each_sibling_event(sibling, event->group_leader) { if (sibling->pmu != event->pmu && !is_software_event(sibling)) return -EINVAL; + } return 0; } diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 2bb200e1bbea..ff39ab011376 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -536,6 +536,10 @@ struct pmu_event_list { struct list_head list; }; +#define for_each_sibling_event(sibling, event) \ + if ((event)->group_leader == (event)) \ + list_for_each_entry((sibling), &(event)->sibling_list, sibling_list) + /** * struct perf_event - performance event kernel representation: */ diff --git a/kernel/events/core.c b/kernel/events/core.c index 3b4c7792a6ac..4d7a460d6669 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -643,7 +643,7 @@ static void perf_event_update_sibling_time(struct perf_event *leader) { struct perf_event *sibling; - list_for_each_entry(sibling, &leader->sibling_list, sibling_list) + for_each_sibling_event(sibling, leader) perf_event_update_time(sibling); } @@ -1828,7 +1828,7 @@ static void perf_group_attach(struct perf_event *event) perf_event__header_size(group_leader); - list_for_each_entry(pos, &group_leader->sibling_list, sibling_list) + for_each_sibling_event(pos, group_leader) perf_event__header_size(pos); } @@ -1928,7 +1928,7 @@ static void perf_group_detach(struct perf_event *event) out: perf_event__header_size(event->group_leader); - list_for_each_entry(tmp, &event->group_leader->sibling_list, sibling_list) + for_each_sibling_event(tmp, event->group_leader) perf_event__header_size(tmp); } @@ -1951,13 +1951,13 @@ static inline int __pmu_filter_match(struct perf_event *event) */ static inline int pmu_filter_match(struct perf_event *event) { - struct perf_event *child; + struct perf_event *sibling; if (!__pmu_filter_match(event)) return 0; - list_for_each_entry(child, &event->sibling_list, sibling_list) { - if (!__pmu_filter_match(child)) + for_each_sibling_event(sibling, event) { + if (!__pmu_filter_match(sibling)) return 0; } @@ -2031,7 +2031,7 @@ group_sched_out(struct perf_event *group_event, /* * Schedule out siblings (if any): */ - list_for_each_entry(event, &group_event->sibling_list, sibling_list) + for_each_sibling_event(event, group_event) event_sched_out(event, cpuctx, ctx); perf_pmu_enable(ctx->pmu); @@ -2310,7 +2310,7 @@ group_sched_in(struct perf_event *group_event, /* * Schedule in siblings as one group (if any): */ - list_for_each_entry(event, &group_event->sibling_list, sibling_list) { + for_each_sibling_event(event, group_event) { if (event_sched_in(event, cpuctx, ctx)) { partial_group = event; goto group_error; @@ -2326,7 +2326,7 @@ group_error: * partial group before returning: * The events up to the failed event are scheduled out normally. */ - list_for_each_entry(event, &group_event->sibling_list, sibling_list) { + for_each_sibling_event(event, group_event) { if (event == partial_group) break; @@ -3863,7 +3863,7 @@ static void __perf_event_read(void *info) pmu->read(event); - list_for_each_entry(sub, &event->sibling_list, sibling_list) { + for_each_sibling_event(sub, event) { if (sub->state == PERF_EVENT_STATE_ACTIVE) { /* * Use sibling's PMU rather than @event's since @@ -4711,7 +4711,7 @@ static int __perf_read_group_add(struct perf_event *leader, if (read_format & PERF_FORMAT_ID) values[n++] = primary_event_id(leader); - list_for_each_entry(sub, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sub, leader) { values[n++] += perf_event_count(sub); if (read_format & PERF_FORMAT_ID) values[n++] = primary_event_id(sub); @@ -4905,7 +4905,7 @@ static void perf_event_for_each(struct perf_event *event, event = event->group_leader; perf_event_for_each_child(event, func); - list_for_each_entry(sibling, &event->sibling_list, sibling_list) + for_each_sibling_event(sibling, event) perf_event_for_each_child(sibling, func); } @@ -6077,7 +6077,7 @@ static void perf_output_read_group(struct perf_output_handle *handle, __output_copy(handle, values, n * sizeof(u64)); - list_for_each_entry(sub, &leader->sibling_list, sibling_list) { + for_each_sibling_event(sub, leader) { n = 0; if ((sub != event) && @@ -10662,8 +10662,7 @@ SYSCALL_DEFINE5(perf_event_open, perf_remove_from_context(group_leader, 0); put_ctx(gctx); - list_for_each_entry(sibling, &group_leader->sibling_list, - sibling_list) { + for_each_sibling_event(sibling, group_leader) { perf_remove_from_context(sibling, 0); put_ctx(gctx); } @@ -10684,8 +10683,7 @@ SYSCALL_DEFINE5(perf_event_open, * By installing siblings first we NO-OP because they're not * reachable through the group lists. */ - list_for_each_entry(sibling, &group_leader->sibling_list, - sibling_list) { + for_each_sibling_event(sibling, group_leader) { perf_event__state_init(sibling); perf_install_in_context(ctx, sibling, sibling->cpu); get_ctx(ctx); @@ -11324,7 +11322,7 @@ static int inherit_group(struct perf_event *parent_event, * case inherit_event() will create individual events, similar to what * perf_group_detach() would do anyway. */ - list_for_each_entry(sub, &parent_event->sibling_list, sibling_list) { + for_each_sibling_event(sub, parent_event) { child_ctr = inherit_event(sub, parent, parent_ctx, child, leader, child_ctx); if (IS_ERR(child_ctr)) -- cgit v1.2.3 From 6e0d4ff4580c1272f4e4860bf22841ef31fd31ba Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Tue, 23 Jan 2018 20:24:45 +0800 Subject: clk: add more __must_check for bulk APIs we need it even when !CONFIG_HAVE_CLK because it allows us to catch missing checking return values in the non-clk compile configurations too. More test coverage. Cc: Stephen Boyd Suggested-by: Stephen Boyd Signed-off-by: Dong Aisheng Signed-off-by: Stephen Boyd --- include/linux/clk.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/clk.h b/include/linux/clk.h index 4c4ef9f34db3..0dbd0885b2c2 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -209,7 +209,7 @@ static inline int clk_prepare(struct clk *clk) return 0; } -static inline int clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks) +static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks) { might_sleep(); return 0; @@ -603,8 +603,8 @@ static inline struct clk *clk_get(struct device *dev, const char *id) return NULL; } -static inline int clk_bulk_get(struct device *dev, int num_clks, - struct clk_bulk_data *clks) +static inline int __must_check clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks) { return 0; } @@ -614,8 +614,8 @@ static inline struct clk *devm_clk_get(struct device *dev, const char *id) return NULL; } -static inline int devm_clk_bulk_get(struct device *dev, int num_clks, - struct clk_bulk_data *clks) +static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks) { return 0; } @@ -645,7 +645,7 @@ static inline int clk_enable(struct clk *clk) return 0; } -static inline int clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) +static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) { return 0; } @@ -719,8 +719,8 @@ static inline void clk_disable_unprepare(struct clk *clk) clk_unprepare(clk); } -static inline int clk_bulk_prepare_enable(int num_clks, - struct clk_bulk_data *clks) +static inline int __must_check clk_bulk_prepare_enable(int num_clks, + struct clk_bulk_data *clks) { int ret; -- cgit v1.2.3 From 63189b785960c3346d1af347516b7438f7ada8ec Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Thu, 8 Mar 2018 14:22:56 +0800 Subject: f2fs: wrap all options with f2fs_sb_info.mount_opt This patch merges miscellaneous mount options into struct f2fs_mount_info, After this patch, once we add new mount option, we don't need to worry about recovery of it in remount_fs(), since we will recover the f2fs_sb_info.mount_opt including all options. Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim --- fs/f2fs/data.c | 2 +- fs/f2fs/dir.c | 2 +- fs/f2fs/f2fs.h | 64 +++++++------- fs/f2fs/file.c | 4 +- fs/f2fs/namei.c | 6 +- fs/f2fs/segment.c | 8 +- fs/f2fs/super.c | 226 +++++++++++++++++++++++------------------------- fs/f2fs/sysfs.c | 4 +- include/linux/f2fs_fs.h | 8 +- 9 files changed, 154 insertions(+), 170 deletions(-) (limited to 'include/linux') diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 6c3c9784de06..3d6ae3173f98 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -2300,7 +2300,7 @@ static ssize_t f2fs_direct_IO(struct kiocb *iocb, struct iov_iter *iter) int rw = iov_iter_rw(iter); int err; enum rw_hint hint = iocb->ki_hint; - int whint_mode = sbi->whint_mode; + int whint_mode = F2FS_OPTION(sbi).whint_mode; err = check_direct_IO(inode, iter, offset); if (err) diff --git a/fs/f2fs/dir.c b/fs/f2fs/dir.c index 87c51709bc48..3644db9177cb 100644 --- a/fs/f2fs/dir.c +++ b/fs/f2fs/dir.c @@ -704,7 +704,7 @@ void f2fs_delete_entry(struct f2fs_dir_entry *dentry, struct page *page, f2fs_update_time(F2FS_I_SB(dir), REQ_TIME); - if (F2FS_I_SB(dir)->fsync_mode == FSYNC_MODE_STRICT) + if (F2FS_OPTION(F2FS_I_SB(dir)).fsync_mode == FSYNC_MODE_STRICT) add_ino_entry(F2FS_I_SB(dir), dir->i_ino, TRANS_DIR_INO); if (f2fs_has_inline_dentry(dir)) diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 3c79b3565cb3..93822634870d 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -98,9 +98,10 @@ extern char *fault_name[FAULT_MAX]; #define F2FS_MOUNT_INLINE_XATTR_SIZE 0x00800000 #define F2FS_MOUNT_RESERVE_ROOT 0x01000000 -#define clear_opt(sbi, option) ((sbi)->mount_opt.opt &= ~F2FS_MOUNT_##option) -#define set_opt(sbi, option) ((sbi)->mount_opt.opt |= F2FS_MOUNT_##option) -#define test_opt(sbi, option) ((sbi)->mount_opt.opt & F2FS_MOUNT_##option) +#define F2FS_OPTION(sbi) ((sbi)->mount_opt) +#define clear_opt(sbi, option) (F2FS_OPTION(sbi).opt &= ~F2FS_MOUNT_##option) +#define set_opt(sbi, option) (F2FS_OPTION(sbi).opt |= F2FS_MOUNT_##option) +#define test_opt(sbi, option) (F2FS_OPTION(sbi).opt & F2FS_MOUNT_##option) #define ver_after(a, b) (typecheck(unsigned long long, a) && \ typecheck(unsigned long long, b) && \ @@ -113,7 +114,25 @@ typedef u32 block_t; /* typedef u32 nid_t; struct f2fs_mount_info { - unsigned int opt; + unsigned int opt; + int write_io_size_bits; /* Write IO size bits */ + block_t root_reserved_blocks; /* root reserved blocks */ + kuid_t s_resuid; /* reserved blocks for uid */ + kgid_t s_resgid; /* reserved blocks for gid */ + int active_logs; /* # of active logs */ + int inline_xattr_size; /* inline xattr size */ +#ifdef CONFIG_F2FS_FAULT_INJECTION + struct f2fs_fault_info fault_info; /* For fault injection */ +#endif +#ifdef CONFIG_QUOTA + /* Names of quota files with journalled quota */ + char *s_qf_names[MAXQUOTAS]; + int s_jquota_fmt; /* Format of quota to use */ +#endif + /* For which write hints are passed down to block layer */ + int whint_mode; + int alloc_mode; /* segment allocation policy */ + int fsync_mode; /* fsync policy */ }; #define F2FS_FEATURE_ENCRYPT 0x0001 @@ -1081,7 +1100,6 @@ struct f2fs_sb_info { struct f2fs_bio_info *write_io[NR_PAGE_TYPE]; /* for write bios */ struct mutex wio_mutex[NR_PAGE_TYPE - 1][NR_TEMP_TYPE]; /* bio ordering for NODE/DATA */ - int write_io_size_bits; /* Write IO size bits */ mempool_t *write_io_dummy; /* Dummy pages */ /* for checkpoint */ @@ -1131,9 +1149,7 @@ struct f2fs_sb_info { unsigned int total_node_count; /* total node block count */ unsigned int total_valid_node_count; /* valid node block count */ loff_t max_file_blocks; /* max block index of file */ - int active_logs; /* # of active logs */ int dir_level; /* directory level */ - int inline_xattr_size; /* inline xattr size */ unsigned int trigger_ssr_threshold; /* threshold to trigger ssr */ int readdir_ra; /* readahead inode in readdir */ @@ -1143,9 +1159,6 @@ struct f2fs_sb_info { block_t last_valid_block_count; /* for recovery */ block_t reserved_blocks; /* configurable reserved blocks */ block_t current_reserved_blocks; /* current reserved blocks */ - block_t root_reserved_blocks; /* root reserved blocks */ - kuid_t s_resuid; /* reserved blocks for uid */ - kgid_t s_resgid; /* reserved blocks for gid */ unsigned int nquota_files; /* # of quota sysfile */ @@ -1230,25 +1243,6 @@ struct f2fs_sb_info { /* Precomputed FS UUID checksum for seeding other checksums */ __u32 s_chksum_seed; - - /* For fault injection */ -#ifdef CONFIG_F2FS_FAULT_INJECTION - struct f2fs_fault_info fault_info; -#endif - -#ifdef CONFIG_QUOTA - /* Names of quota files with journalled quota */ - char *s_qf_names[MAXQUOTAS]; - int s_jquota_fmt; /* Format of quota to use */ -#endif - /* For which write hints are passed down to block layer */ - int whint_mode; - - /* segment allocation policy */ - int alloc_mode; - - /* fsync policy */ - int fsync_mode; }; #ifdef CONFIG_F2FS_FAULT_INJECTION @@ -1258,7 +1252,7 @@ struct f2fs_sb_info { __func__, __builtin_return_address(0)) static inline bool time_to_inject(struct f2fs_sb_info *sbi, int type) { - struct f2fs_fault_info *ffi = &sbi->fault_info; + struct f2fs_fault_info *ffi = &F2FS_OPTION(sbi).fault_info; if (!ffi->inject_rate) return false; @@ -1615,10 +1609,10 @@ static inline bool __allow_reserved_blocks(struct f2fs_sb_info *sbi, return false; if (IS_NOQUOTA(inode)) return true; - if (uid_eq(sbi->s_resuid, current_fsuid())) + if (uid_eq(F2FS_OPTION(sbi).s_resuid, current_fsuid())) return true; - if (!gid_eq(sbi->s_resgid, GLOBAL_ROOT_GID) && - in_group_p(sbi->s_resgid)) + if (!gid_eq(F2FS_OPTION(sbi).s_resgid, GLOBAL_ROOT_GID) && + in_group_p(F2FS_OPTION(sbi).s_resgid)) return true; if (capable(CAP_SYS_RESOURCE)) return true; @@ -1656,7 +1650,7 @@ static inline int inc_valid_block_count(struct f2fs_sb_info *sbi, sbi->current_reserved_blocks; if (!__allow_reserved_blocks(sbi, inode)) - avail_user_block_count -= sbi->root_reserved_blocks; + avail_user_block_count -= F2FS_OPTION(sbi).root_reserved_blocks; if (unlikely(sbi->total_valid_block_count > avail_user_block_count)) { diff = sbi->total_valid_block_count - avail_user_block_count; @@ -1863,7 +1857,7 @@ static inline int inc_valid_node_count(struct f2fs_sb_info *sbi, sbi->current_reserved_blocks + 1; if (!__allow_reserved_blocks(sbi, inode)) - valid_block_count += sbi->root_reserved_blocks; + valid_block_count += F2FS_OPTION(sbi).root_reserved_blocks; if (unlikely(valid_block_count > sbi->user_block_count)) { spin_unlock(&sbi->stat_lock); diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index 99fa207fc310..3072837744b9 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -163,9 +163,9 @@ static inline enum cp_reason_type need_do_checkpoint(struct inode *inode) cp_reason = CP_NODE_NEED_CP; else if (test_opt(sbi, FASTBOOT)) cp_reason = CP_FASTBOOT_MODE; - else if (sbi->active_logs == 2) + else if (F2FS_OPTION(sbi).active_logs == 2) cp_reason = CP_SPEC_LOG_NUM; - else if (sbi->fsync_mode == FSYNC_MODE_STRICT && + else if (F2FS_OPTION(sbi).fsync_mode == FSYNC_MODE_STRICT && need_dentry_mark(sbi, inode->i_ino) && exist_written_data(sbi, F2FS_I(inode)->i_pino, TRANS_DIR_INO)) cp_reason = CP_RECOVER_DIR; diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index e9bb3a3a8b0a..f4ae46282eef 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -97,7 +97,7 @@ static struct inode *f2fs_new_inode(struct inode *dir, umode_t mode) if (f2fs_sb_has_flexible_inline_xattr(sbi->sb)) { f2fs_bug_on(sbi, !f2fs_has_extra_attr(inode)); if (f2fs_has_inline_xattr(inode)) - xattr_size = sbi->inline_xattr_size; + xattr_size = F2FS_OPTION(sbi).inline_xattr_size; /* Otherwise, will be 0 */ } else if (f2fs_has_inline_xattr(inode) || f2fs_has_inline_dentry(inode)) { @@ -970,7 +970,7 @@ static int f2fs_rename(struct inode *old_dir, struct dentry *old_dentry, f2fs_put_page(old_dir_page, 0); f2fs_i_links_write(old_dir, false); } - if (sbi->fsync_mode == FSYNC_MODE_STRICT) + if (F2FS_OPTION(sbi).fsync_mode == FSYNC_MODE_STRICT) add_ino_entry(sbi, new_dir->i_ino, TRANS_DIR_INO); f2fs_unlock_op(sbi); @@ -1121,7 +1121,7 @@ static int f2fs_cross_rename(struct inode *old_dir, struct dentry *old_dentry, } f2fs_mark_inode_dirty_sync(new_dir, false); - if (sbi->fsync_mode == FSYNC_MODE_STRICT) { + if (F2FS_OPTION(sbi).fsync_mode == FSYNC_MODE_STRICT) { add_ino_entry(sbi, old_dir->i_ino, TRANS_DIR_INO); add_ino_entry(sbi, new_dir->i_ino, TRANS_DIR_INO); } diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index 570e02d89cbc..637980d04503 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -2171,7 +2171,7 @@ static unsigned int __get_next_segno(struct f2fs_sb_info *sbi, int type) return SIT_I(sbi)->last_victim[ALLOC_NEXT]; /* find segments from 0 to reuse freed segments */ - if (sbi->alloc_mode == ALLOC_MODE_REUSE) + if (F2FS_OPTION(sbi).alloc_mode == ALLOC_MODE_REUSE) return 0; return CURSEG_I(sbi, type)->segno; @@ -2524,7 +2524,7 @@ int rw_hint_to_seg_type(enum rw_hint hint) enum rw_hint io_type_to_rw_hint(struct f2fs_sb_info *sbi, enum page_type type, enum temp_type temp) { - if (sbi->whint_mode == WHINT_MODE_USER) { + if (F2FS_OPTION(sbi).whint_mode == WHINT_MODE_USER) { if (type == DATA) { if (temp == WARM) return WRITE_LIFE_NOT_SET; @@ -2535,7 +2535,7 @@ enum rw_hint io_type_to_rw_hint(struct f2fs_sb_info *sbi, } else { return WRITE_LIFE_NOT_SET; } - } else if (sbi->whint_mode == WHINT_MODE_FS) { + } else if (F2FS_OPTION(sbi).whint_mode == WHINT_MODE_FS) { if (type == DATA) { if (temp == WARM) return WRITE_LIFE_LONG; @@ -2603,7 +2603,7 @@ static int __get_segment_type(struct f2fs_io_info *fio) { int type = 0; - switch (fio->sbi->active_logs) { + switch (F2FS_OPTION(fio->sbi).active_logs) { case 2: type = __get_segment_type_2(fio); break; diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index 2516dfa26a98..419eaacf3366 100644 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -60,7 +60,7 @@ char *fault_name[FAULT_MAX] = { static void f2fs_build_fault_attr(struct f2fs_sb_info *sbi, unsigned int rate) { - struct f2fs_fault_info *ffi = &sbi->fault_info; + struct f2fs_fault_info *ffi = &F2FS_OPTION(sbi).fault_info; if (rate) { atomic_set(&ffi->inject_ops, 0); @@ -208,21 +208,24 @@ static inline void limit_reserve_root(struct f2fs_sb_info *sbi) block_t limit = (sbi->user_block_count << 1) / 1000; /* limit is 0.2% */ - if (test_opt(sbi, RESERVE_ROOT) && sbi->root_reserved_blocks > limit) { - sbi->root_reserved_blocks = limit; + if (test_opt(sbi, RESERVE_ROOT) && + F2FS_OPTION(sbi).root_reserved_blocks > limit) { + F2FS_OPTION(sbi).root_reserved_blocks = limit; f2fs_msg(sbi->sb, KERN_INFO, "Reduce reserved blocks for root = %u", - sbi->root_reserved_blocks); + F2FS_OPTION(sbi).root_reserved_blocks); } if (!test_opt(sbi, RESERVE_ROOT) && - (!uid_eq(sbi->s_resuid, + (!uid_eq(F2FS_OPTION(sbi).s_resuid, make_kuid(&init_user_ns, F2FS_DEF_RESUID)) || - !gid_eq(sbi->s_resgid, + !gid_eq(F2FS_OPTION(sbi).s_resgid, make_kgid(&init_user_ns, F2FS_DEF_RESGID)))) f2fs_msg(sbi->sb, KERN_INFO, "Ignore s_resuid=%u, s_resgid=%u w/o reserve_root", - from_kuid_munged(&init_user_ns, sbi->s_resuid), - from_kgid_munged(&init_user_ns, sbi->s_resgid)); + from_kuid_munged(&init_user_ns, + F2FS_OPTION(sbi).s_resuid), + from_kgid_munged(&init_user_ns, + F2FS_OPTION(sbi).s_resgid)); } static void init_once(void *foo) @@ -242,7 +245,7 @@ static int f2fs_set_qf_name(struct super_block *sb, int qtype, char *qname; int ret = -EINVAL; - if (sb_any_quota_loaded(sb) && !sbi->s_qf_names[qtype]) { + if (sb_any_quota_loaded(sb) && !F2FS_OPTION(sbi).s_qf_names[qtype]) { f2fs_msg(sb, KERN_ERR, "Cannot change journaled " "quota options when quota turned on"); @@ -260,8 +263,8 @@ static int f2fs_set_qf_name(struct super_block *sb, int qtype, "Not enough memory for storing quotafile name"); return -EINVAL; } - if (sbi->s_qf_names[qtype]) { - if (strcmp(sbi->s_qf_names[qtype], qname) == 0) + if (F2FS_OPTION(sbi).s_qf_names[qtype]) { + if (strcmp(F2FS_OPTION(sbi).s_qf_names[qtype], qname) == 0) ret = 0; else f2fs_msg(sb, KERN_ERR, @@ -274,7 +277,7 @@ static int f2fs_set_qf_name(struct super_block *sb, int qtype, "quotafile must be on filesystem root"); goto errout; } - sbi->s_qf_names[qtype] = qname; + F2FS_OPTION(sbi).s_qf_names[qtype] = qname; set_opt(sbi, QUOTA); return 0; errout: @@ -286,13 +289,13 @@ static int f2fs_clear_qf_name(struct super_block *sb, int qtype) { struct f2fs_sb_info *sbi = F2FS_SB(sb); - if (sb_any_quota_loaded(sb) && sbi->s_qf_names[qtype]) { + if (sb_any_quota_loaded(sb) && F2FS_OPTION(sbi).s_qf_names[qtype]) { f2fs_msg(sb, KERN_ERR, "Cannot change journaled quota options" " when quota turned on"); return -EINVAL; } - kfree(sbi->s_qf_names[qtype]); - sbi->s_qf_names[qtype] = NULL; + kfree(F2FS_OPTION(sbi).s_qf_names[qtype]); + F2FS_OPTION(sbi).s_qf_names[qtype] = NULL; return 0; } @@ -308,15 +311,19 @@ static int f2fs_check_quota_options(struct f2fs_sb_info *sbi) "Cannot enable project quota enforcement."); return -1; } - if (sbi->s_qf_names[USRQUOTA] || sbi->s_qf_names[GRPQUOTA] || - sbi->s_qf_names[PRJQUOTA]) { - if (test_opt(sbi, USRQUOTA) && sbi->s_qf_names[USRQUOTA]) + if (F2FS_OPTION(sbi).s_qf_names[USRQUOTA] || + F2FS_OPTION(sbi).s_qf_names[GRPQUOTA] || + F2FS_OPTION(sbi).s_qf_names[PRJQUOTA]) { + if (test_opt(sbi, USRQUOTA) && + F2FS_OPTION(sbi).s_qf_names[USRQUOTA]) clear_opt(sbi, USRQUOTA); - if (test_opt(sbi, GRPQUOTA) && sbi->s_qf_names[GRPQUOTA]) + if (test_opt(sbi, GRPQUOTA) && + F2FS_OPTION(sbi).s_qf_names[GRPQUOTA]) clear_opt(sbi, GRPQUOTA); - if (test_opt(sbi, PRJQUOTA) && sbi->s_qf_names[PRJQUOTA]) + if (test_opt(sbi, PRJQUOTA) && + F2FS_OPTION(sbi).s_qf_names[PRJQUOTA]) clear_opt(sbi, PRJQUOTA); if (test_opt(sbi, GRPQUOTA) || test_opt(sbi, USRQUOTA) || @@ -326,17 +333,17 @@ static int f2fs_check_quota_options(struct f2fs_sb_info *sbi) return -1; } - if (!sbi->s_jquota_fmt) { + if (!F2FS_OPTION(sbi).s_jquota_fmt) { f2fs_msg(sbi->sb, KERN_ERR, "journaled quota format " "not specified"); return -1; } } - if (f2fs_sb_has_quota_ino(sbi->sb) && sbi->s_jquota_fmt) { + if (f2fs_sb_has_quota_ino(sbi->sb) && F2FS_OPTION(sbi).s_jquota_fmt) { f2fs_msg(sbi->sb, KERN_INFO, "QUOTA feature is enabled, so ignore jquota_fmt"); - sbi->s_jquota_fmt = 0; + F2FS_OPTION(sbi).s_jquota_fmt = 0; } if (f2fs_sb_has_quota_ino(sbi->sb) && f2fs_readonly(sbi->sb)) { f2fs_msg(sbi->sb, KERN_INFO, @@ -446,7 +453,7 @@ static int parse_options(struct super_block *sb, char *options) if (args->from && match_int(args, &arg)) return -EINVAL; set_opt(sbi, INLINE_XATTR_SIZE); - sbi->inline_xattr_size = arg; + F2FS_OPTION(sbi).inline_xattr_size = arg; break; #else case Opt_user_xattr: @@ -486,7 +493,7 @@ static int parse_options(struct super_block *sb, char *options) return -EINVAL; if (arg != 2 && arg != 4 && arg != NR_CURSEG_TYPE) return -EINVAL; - sbi->active_logs = arg; + F2FS_OPTION(sbi).active_logs = arg; break; case Opt_disable_ext_identify: set_opt(sbi, DISABLE_EXT_IDENTIFY); @@ -530,9 +537,9 @@ static int parse_options(struct super_block *sb, char *options) if (test_opt(sbi, RESERVE_ROOT)) { f2fs_msg(sb, KERN_INFO, "Preserve previous reserve_root=%u", - sbi->root_reserved_blocks); + F2FS_OPTION(sbi).root_reserved_blocks); } else { - sbi->root_reserved_blocks = arg; + F2FS_OPTION(sbi).root_reserved_blocks = arg; set_opt(sbi, RESERVE_ROOT); } break; @@ -545,7 +552,7 @@ static int parse_options(struct super_block *sb, char *options) "Invalid uid value %d", arg); return -EINVAL; } - sbi->s_resuid = uid; + F2FS_OPTION(sbi).s_resuid = uid; break; case Opt_resgid: if (args->from && match_int(args, &arg)) @@ -556,7 +563,7 @@ static int parse_options(struct super_block *sb, char *options) "Invalid gid value %d", arg); return -EINVAL; } - sbi->s_resgid = gid; + F2FS_OPTION(sbi).s_resgid = gid; break; case Opt_mode: name = match_strdup(&args[0]); @@ -591,7 +598,7 @@ static int parse_options(struct super_block *sb, char *options) 1 << arg, BIO_MAX_PAGES); return -EINVAL; } - sbi->write_io_size_bits = arg; + F2FS_OPTION(sbi).write_io_size_bits = arg; break; case Opt_fault_injection: if (args->from && match_int(args, &arg)) @@ -652,13 +659,13 @@ static int parse_options(struct super_block *sb, char *options) return ret; break; case Opt_jqfmt_vfsold: - sbi->s_jquota_fmt = QFMT_VFS_OLD; + F2FS_OPTION(sbi).s_jquota_fmt = QFMT_VFS_OLD; break; case Opt_jqfmt_vfsv0: - sbi->s_jquota_fmt = QFMT_VFS_V0; + F2FS_OPTION(sbi).s_jquota_fmt = QFMT_VFS_V0; break; case Opt_jqfmt_vfsv1: - sbi->s_jquota_fmt = QFMT_VFS_V1; + F2FS_OPTION(sbi).s_jquota_fmt = QFMT_VFS_V1; break; case Opt_noquota: clear_opt(sbi, QUOTA); @@ -691,13 +698,13 @@ static int parse_options(struct super_block *sb, char *options) return -ENOMEM; if (strlen(name) == 10 && !strncmp(name, "user-based", 10)) { - sbi->whint_mode = WHINT_MODE_USER; + F2FS_OPTION(sbi).whint_mode = WHINT_MODE_USER; } else if (strlen(name) == 3 && !strncmp(name, "off", 3)) { - sbi->whint_mode = WHINT_MODE_OFF; + F2FS_OPTION(sbi).whint_mode = WHINT_MODE_OFF; } else if (strlen(name) == 8 && !strncmp(name, "fs-based", 8)) { - sbi->whint_mode = WHINT_MODE_FS; + F2FS_OPTION(sbi).whint_mode = WHINT_MODE_FS; } else { kfree(name); return -EINVAL; @@ -711,10 +718,10 @@ static int parse_options(struct super_block *sb, char *options) if (strlen(name) == 7 && !strncmp(name, "default", 7)) { - sbi->alloc_mode = ALLOC_MODE_DEFAULT; + F2FS_OPTION(sbi).alloc_mode = ALLOC_MODE_DEFAULT; } else if (strlen(name) == 5 && !strncmp(name, "reuse", 5)) { - sbi->alloc_mode = ALLOC_MODE_REUSE; + F2FS_OPTION(sbi).alloc_mode = ALLOC_MODE_REUSE; } else { kfree(name); return -EINVAL; @@ -727,10 +734,10 @@ static int parse_options(struct super_block *sb, char *options) return -ENOMEM; if (strlen(name) == 5 && !strncmp(name, "posix", 5)) { - sbi->fsync_mode = FSYNC_MODE_POSIX; + F2FS_OPTION(sbi).fsync_mode = FSYNC_MODE_POSIX; } else if (strlen(name) == 6 && !strncmp(name, "strict", 6)) { - sbi->fsync_mode = FSYNC_MODE_STRICT; + F2FS_OPTION(sbi).fsync_mode = FSYNC_MODE_STRICT; } else { kfree(name); return -EINVAL; @@ -770,8 +777,9 @@ static int parse_options(struct super_block *sb, char *options) "set with inline_xattr option"); return -EINVAL; } - if (!sbi->inline_xattr_size || - sbi->inline_xattr_size >= DEF_ADDRS_PER_INODE - + if (!F2FS_OPTION(sbi).inline_xattr_size || + F2FS_OPTION(sbi).inline_xattr_size >= + DEF_ADDRS_PER_INODE - F2FS_TOTAL_EXTRA_ATTR_SIZE - DEF_INLINE_RESERVED_SIZE - DEF_MIN_INLINE_SIZE) { @@ -784,8 +792,8 @@ static int parse_options(struct super_block *sb, char *options) /* Not pass down write hints if the number of active logs is lesser * than NR_CURSEG_TYPE. */ - if (sbi->active_logs != NR_CURSEG_TYPE) - sbi->whint_mode = WHINT_MODE_OFF; + if (F2FS_OPTION(sbi).active_logs != NR_CURSEG_TYPE) + F2FS_OPTION(sbi).whint_mode = WHINT_MODE_OFF; return 0; } @@ -1027,7 +1035,7 @@ static void f2fs_put_super(struct super_block *sb) mempool_destroy(sbi->write_io_dummy); #ifdef CONFIG_QUOTA for (i = 0; i < MAXQUOTAS; i++) - kfree(sbi->s_qf_names[i]); + kfree(F2FS_OPTION(sbi).s_qf_names[i]); #endif destroy_percpu_info(sbi); for (i = 0; i < NR_PAGE_TYPE; i++) @@ -1141,8 +1149,9 @@ static int f2fs_statfs(struct dentry *dentry, struct kstatfs *buf) buf->f_blocks = total_count - start_count; buf->f_bfree = user_block_count - valid_user_blocks(sbi) - sbi->current_reserved_blocks; - if (buf->f_bfree > sbi->root_reserved_blocks) - buf->f_bavail = buf->f_bfree - sbi->root_reserved_blocks; + if (buf->f_bfree > F2FS_OPTION(sbi).root_reserved_blocks) + buf->f_bavail = buf->f_bfree - + F2FS_OPTION(sbi).root_reserved_blocks; else buf->f_bavail = 0; @@ -1177,10 +1186,10 @@ static inline void f2fs_show_quota_options(struct seq_file *seq, #ifdef CONFIG_QUOTA struct f2fs_sb_info *sbi = F2FS_SB(sb); - if (sbi->s_jquota_fmt) { + if (F2FS_OPTION(sbi).s_jquota_fmt) { char *fmtname = ""; - switch (sbi->s_jquota_fmt) { + switch (F2FS_OPTION(sbi).s_jquota_fmt) { case QFMT_VFS_OLD: fmtname = "vfsold"; break; @@ -1194,14 +1203,17 @@ static inline void f2fs_show_quota_options(struct seq_file *seq, seq_printf(seq, ",jqfmt=%s", fmtname); } - if (sbi->s_qf_names[USRQUOTA]) - seq_show_option(seq, "usrjquota", sbi->s_qf_names[USRQUOTA]); + if (F2FS_OPTION(sbi).s_qf_names[USRQUOTA]) + seq_show_option(seq, "usrjquota", + F2FS_OPTION(sbi).s_qf_names[USRQUOTA]); - if (sbi->s_qf_names[GRPQUOTA]) - seq_show_option(seq, "grpjquota", sbi->s_qf_names[GRPQUOTA]); + if (F2FS_OPTION(sbi).s_qf_names[GRPQUOTA]) + seq_show_option(seq, "grpjquota", + F2FS_OPTION(sbi).s_qf_names[GRPQUOTA]); - if (sbi->s_qf_names[PRJQUOTA]) - seq_show_option(seq, "prjjquota", sbi->s_qf_names[PRJQUOTA]); + if (F2FS_OPTION(sbi).s_qf_names[PRJQUOTA]) + seq_show_option(seq, "prjjquota", + F2FS_OPTION(sbi).s_qf_names[PRJQUOTA]); #endif } @@ -1236,7 +1248,7 @@ static int f2fs_show_options(struct seq_file *seq, struct dentry *root) seq_puts(seq, ",noinline_xattr"); if (test_opt(sbi, INLINE_XATTR_SIZE)) seq_printf(seq, ",inline_xattr_size=%u", - sbi->inline_xattr_size); + F2FS_OPTION(sbi).inline_xattr_size); #endif #ifdef CONFIG_F2FS_FS_POSIX_ACL if (test_opt(sbi, POSIX_ACL)) @@ -1272,18 +1284,20 @@ static int f2fs_show_options(struct seq_file *seq, struct dentry *root) seq_puts(seq, "adaptive"); else if (test_opt(sbi, LFS)) seq_puts(seq, "lfs"); - seq_printf(seq, ",active_logs=%u", sbi->active_logs); + seq_printf(seq, ",active_logs=%u", F2FS_OPTION(sbi).active_logs); if (test_opt(sbi, RESERVE_ROOT)) seq_printf(seq, ",reserve_root=%u,resuid=%u,resgid=%u", - sbi->root_reserved_blocks, - from_kuid_munged(&init_user_ns, sbi->s_resuid), - from_kgid_munged(&init_user_ns, sbi->s_resgid)); + F2FS_OPTION(sbi).root_reserved_blocks, + from_kuid_munged(&init_user_ns, + F2FS_OPTION(sbi).s_resuid), + from_kgid_munged(&init_user_ns, + F2FS_OPTION(sbi).s_resgid)); if (F2FS_IO_SIZE_BITS(sbi)) seq_printf(seq, ",io_size=%uKB", F2FS_IO_SIZE_KB(sbi)); #ifdef CONFIG_F2FS_FAULT_INJECTION if (test_opt(sbi, FAULT_INJECTION)) seq_printf(seq, ",fault_injection=%u", - sbi->fault_info.inject_rate); + F2FS_OPTION(sbi).fault_info.inject_rate); #endif #ifdef CONFIG_QUOTA if (test_opt(sbi, QUOTA)) @@ -1296,19 +1310,19 @@ static int f2fs_show_options(struct seq_file *seq, struct dentry *root) seq_puts(seq, ",prjquota"); #endif f2fs_show_quota_options(seq, sbi->sb); - if (sbi->whint_mode == WHINT_MODE_USER) + if (F2FS_OPTION(sbi).whint_mode == WHINT_MODE_USER) seq_printf(seq, ",whint_mode=%s", "user-based"); - else if (sbi->whint_mode == WHINT_MODE_FS) + else if (F2FS_OPTION(sbi).whint_mode == WHINT_MODE_FS) seq_printf(seq, ",whint_mode=%s", "fs-based"); - if (sbi->alloc_mode == ALLOC_MODE_DEFAULT) + if (F2FS_OPTION(sbi).alloc_mode == ALLOC_MODE_DEFAULT) seq_printf(seq, ",alloc_mode=%s", "default"); - else if (sbi->alloc_mode == ALLOC_MODE_REUSE) + else if (F2FS_OPTION(sbi).alloc_mode == ALLOC_MODE_REUSE) seq_printf(seq, ",alloc_mode=%s", "reuse"); - if (sbi->fsync_mode == FSYNC_MODE_POSIX) + if (F2FS_OPTION(sbi).fsync_mode == FSYNC_MODE_POSIX) seq_printf(seq, ",fsync_mode=%s", "posix"); - else if (sbi->fsync_mode == FSYNC_MODE_STRICT) + else if (F2FS_OPTION(sbi).fsync_mode == FSYNC_MODE_STRICT) seq_printf(seq, ",fsync_mode=%s", "strict"); return 0; } @@ -1316,11 +1330,11 @@ static int f2fs_show_options(struct seq_file *seq, struct dentry *root) static void default_options(struct f2fs_sb_info *sbi) { /* init some FS parameters */ - sbi->active_logs = NR_CURSEG_TYPE; - sbi->inline_xattr_size = DEFAULT_INLINE_XATTR_ADDRS; - sbi->whint_mode = WHINT_MODE_OFF; - sbi->alloc_mode = ALLOC_MODE_DEFAULT; - sbi->fsync_mode = FSYNC_MODE_POSIX; + F2FS_OPTION(sbi).active_logs = NR_CURSEG_TYPE; + F2FS_OPTION(sbi).inline_xattr_size = DEFAULT_INLINE_XATTR_ADDRS; + F2FS_OPTION(sbi).whint_mode = WHINT_MODE_OFF; + F2FS_OPTION(sbi).alloc_mode = ALLOC_MODE_DEFAULT; + F2FS_OPTION(sbi).fsync_mode = FSYNC_MODE_POSIX; sbi->readdir_ra = 1; set_opt(sbi, BG_GC); @@ -1358,24 +1372,11 @@ static int f2fs_remount(struct super_block *sb, int *flags, char *data) struct f2fs_sb_info *sbi = F2FS_SB(sb); struct f2fs_mount_info org_mount_opt; unsigned long old_sb_flags; - int err, active_logs; + int err; bool need_restart_gc = false; bool need_stop_gc = false; bool no_extent_cache = !test_opt(sbi, EXTENT_CACHE); - int old_whint_mode = sbi->whint_mode; - int old_alloc_mode = sbi->alloc_mode; - int old_fsync_mode = sbi->fsync_mode; - int old_inline_xattr_size = sbi->inline_xattr_size; - block_t old_root_reserved_blocks = sbi->root_reserved_blocks; - kuid_t old_resuid = sbi->s_resuid; - kgid_t old_resgid = sbi->s_resgid; - int old_write_io_size_bits = sbi->write_io_size_bits; -#ifdef CONFIG_F2FS_FAULT_INJECTION - struct f2fs_fault_info ffi = sbi->fault_info; -#endif #ifdef CONFIG_QUOTA - int s_jquota_fmt; - char *s_qf_names[MAXQUOTAS]; int i, j; #endif @@ -1385,21 +1386,21 @@ static int f2fs_remount(struct super_block *sb, int *flags, char *data) */ org_mount_opt = sbi->mount_opt; old_sb_flags = sb->s_flags; - active_logs = sbi->active_logs; #ifdef CONFIG_QUOTA - s_jquota_fmt = sbi->s_jquota_fmt; + org_mount_opt.s_jquota_fmt = F2FS_OPTION(sbi).s_jquota_fmt; for (i = 0; i < MAXQUOTAS; i++) { - if (sbi->s_qf_names[i]) { - s_qf_names[i] = kstrdup(sbi->s_qf_names[i], - GFP_KERNEL); - if (!s_qf_names[i]) { + if (F2FS_OPTION(sbi).s_qf_names[i]) { + org_mount_opt.s_qf_names[i] = + kstrdup(F2FS_OPTION(sbi).s_qf_names[i], + GFP_KERNEL); + if (!org_mount_opt.s_qf_names[i]) { for (j = 0; j < i; j++) - kfree(s_qf_names[j]); + kfree(org_mount_opt.s_qf_names[j]); return -ENOMEM; } } else { - s_qf_names[i] = NULL; + org_mount_opt.s_qf_names[i] = NULL; } } #endif @@ -1469,7 +1470,8 @@ static int f2fs_remount(struct super_block *sb, int *flags, char *data) need_stop_gc = true; } - if (*flags & SB_RDONLY || sbi->whint_mode != old_whint_mode) { + if (*flags & SB_RDONLY || + F2FS_OPTION(sbi).whint_mode != org_mount_opt.whint_mode) { writeback_inodes_sb(sb, WB_REASON_SYNC); sync_inodes_sb(sb); @@ -1495,7 +1497,7 @@ skip: #ifdef CONFIG_QUOTA /* Release old quota file names */ for (i = 0; i < MAXQUOTAS; i++) - kfree(s_qf_names[i]); + kfree(org_mount_opt.s_qf_names[i]); #endif /* Update the POSIXACL Flag */ sb->s_flags = (sb->s_flags & ~SB_POSIXACL) | @@ -1513,26 +1515,14 @@ restore_gc: } restore_opts: #ifdef CONFIG_QUOTA - sbi->s_jquota_fmt = s_jquota_fmt; + F2FS_OPTION(sbi).s_jquota_fmt = org_mount_opt.s_jquota_fmt; for (i = 0; i < MAXQUOTAS; i++) { - kfree(sbi->s_qf_names[i]); - sbi->s_qf_names[i] = s_qf_names[i]; + kfree(F2FS_OPTION(sbi).s_qf_names[i]); + F2FS_OPTION(sbi).s_qf_names[i] = org_mount_opt.s_qf_names[i]; } #endif - sbi->write_io_size_bits = old_write_io_size_bits; - sbi->s_resgid = old_resgid; - sbi->s_resuid = old_resuid; - sbi->root_reserved_blocks = old_root_reserved_blocks; - sbi->inline_xattr_size = old_inline_xattr_size; - sbi->alloc_mode = old_alloc_mode; - sbi->fsync_mode = old_fsync_mode; - sbi->whint_mode = old_whint_mode; sbi->mount_opt = org_mount_opt; - sbi->active_logs = active_logs; sb->s_flags = old_sb_flags; -#ifdef CONFIG_F2FS_FAULT_INJECTION - sbi->fault_info = ffi; -#endif return err; } @@ -1654,8 +1644,8 @@ static qsize_t *f2fs_get_reserved_space(struct inode *inode) static int f2fs_quota_on_mount(struct f2fs_sb_info *sbi, int type) { - return dquot_quota_on_mount(sbi->sb, sbi->s_qf_names[type], - sbi->s_jquota_fmt, type); + return dquot_quota_on_mount(sbi->sb, F2FS_OPTION(sbi).s_qf_names[type], + F2FS_OPTION(sbi).s_jquota_fmt, type); } int f2fs_enable_quota_files(struct f2fs_sb_info *sbi, bool rdonly) @@ -1674,7 +1664,7 @@ int f2fs_enable_quota_files(struct f2fs_sb_info *sbi, bool rdonly) } for (i = 0; i < MAXQUOTAS; i++) { - if (sbi->s_qf_names[i]) { + if (F2FS_OPTION(sbi).s_qf_names[i]) { err = f2fs_quota_on_mount(sbi, i); if (!err) { enabled = 1; @@ -2558,7 +2548,7 @@ static void f2fs_tuning_parameters(struct f2fs_sb_info *sbi) /* adjust parameters according to the volume size */ if (sm_i->main_segments <= SMALL_VOLUME_SEGMENTS) { - sbi->alloc_mode = ALLOC_MODE_REUSE; + F2FS_OPTION(sbi).alloc_mode = ALLOC_MODE_REUSE; sm_i->dcc_info->discard_granularity = 1; sm_i->ipu_policy = 1 << F2FS_IPU_FORCE; } @@ -2611,8 +2601,8 @@ try_onemore: sb->s_fs_info = sbi; sbi->raw_super = raw_super; - sbi->s_resuid = make_kuid(&init_user_ns, F2FS_DEF_RESUID); - sbi->s_resgid = make_kgid(&init_user_ns, F2FS_DEF_RESGID); + F2FS_OPTION(sbi).s_resuid = make_kuid(&init_user_ns, F2FS_DEF_RESUID); + F2FS_OPTION(sbi).s_resgid = make_kgid(&init_user_ns, F2FS_DEF_RESGID); /* precompute checksum seed for metadata */ if (f2fs_sb_has_inode_chksum(sb)) @@ -2970,7 +2960,7 @@ free_bio_info: free_options: #ifdef CONFIG_QUOTA for (i = 0; i < MAXQUOTAS; i++) - kfree(sbi->s_qf_names[i]); + kfree(F2FS_OPTION(sbi).s_qf_names[i]); #endif kfree(options); free_sb_buf: diff --git a/fs/f2fs/sysfs.c b/fs/f2fs/sysfs.c index 23a2d8d66c43..7d983ad19da4 100644 --- a/fs/f2fs/sysfs.c +++ b/fs/f2fs/sysfs.c @@ -58,7 +58,7 @@ static unsigned char *__struct_ptr(struct f2fs_sb_info *sbi, int struct_type) #ifdef CONFIG_F2FS_FAULT_INJECTION else if (struct_type == FAULT_INFO_RATE || struct_type == FAULT_INFO_TYPE) - return (unsigned char *)&sbi->fault_info; + return (unsigned char *)&F2FS_OPTION(sbi).fault_info; #endif return NULL; } @@ -222,7 +222,7 @@ out: if (a->struct_type == RESERVED_BLOCKS) { spin_lock(&sbi->stat_lock); if (t > (unsigned long)(sbi->user_block_count - - sbi->root_reserved_blocks)) { + F2FS_OPTION(sbi).root_reserved_blocks)) { spin_unlock(&sbi->stat_lock); return -EINVAL; } diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index b06ab1f04ff6..124787e8db58 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -39,10 +39,10 @@ #define F2FS_MAX_QUOTAS 3 -#define F2FS_IO_SIZE(sbi) (1 << (sbi)->write_io_size_bits) /* Blocks */ -#define F2FS_IO_SIZE_KB(sbi) (1 << ((sbi)->write_io_size_bits + 2)) /* KB */ -#define F2FS_IO_SIZE_BYTES(sbi) (1 << ((sbi)->write_io_size_bits + 12)) /* B */ -#define F2FS_IO_SIZE_BITS(sbi) ((sbi)->write_io_size_bits) /* power of 2 */ +#define F2FS_IO_SIZE(sbi) (1 << F2FS_OPTION(sbi).write_io_size_bits) /* Blocks */ +#define F2FS_IO_SIZE_KB(sbi) (1 << (F2FS_OPTION(sbi).write_io_size_bits + 2)) /* KB */ +#define F2FS_IO_SIZE_BYTES(sbi) (1 << (F2FS_OPTION(sbi).write_io_size_bits + 12)) /* B */ +#define F2FS_IO_SIZE_BITS(sbi) (F2FS_OPTION(sbi).write_io_size_bits) /* power of 2 */ #define F2FS_IO_SIZE_MASK(sbi) (F2FS_IO_SIZE(sbi) - 1) /* This flag is used by node and meta inodes, and by recovery */ -- cgit v1.2.3 From bb1105e479fbb8b0edc6f35affec71b75e31c8c0 Mon Sep 17 00:00:00 2001 From: Jaegeuk Kim Date: Fri, 9 Mar 2018 17:42:28 -0800 Subject: f2fs: align memory boundary for bitops For example, in arm64, free_nid_bitmap should be aligned to word size in order to use bit operations. Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim --- fs/f2fs/f2fs.h | 2 +- fs/f2fs/node.c | 20 +++++++++++++++++--- include/linux/f2fs_fs.h | 4 ++++ 3 files changed, 22 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 88f2b420de27..641b4b98d373 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -766,7 +766,7 @@ struct f2fs_nm_info { unsigned int nid_cnt[MAX_NID_STATE]; /* the number of free node id */ spinlock_t nid_list_lock; /* protect nid lists ops */ struct mutex build_lock; /* lock for build free nids */ - unsigned char (*free_nid_bitmap)[NAT_ENTRY_BITMAP_SIZE]; + unsigned char **free_nid_bitmap; unsigned char *nat_block_bitmap; unsigned short *free_nid_count; /* free nid count of NAT block */ diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index b86e2b15b619..f7886b46478d 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -2708,12 +2708,20 @@ static int init_node_manager(struct f2fs_sb_info *sbi) static int init_free_nid_cache(struct f2fs_sb_info *sbi) { struct f2fs_nm_info *nm_i = NM_I(sbi); + int i; - nm_i->free_nid_bitmap = f2fs_kvzalloc(sbi, nm_i->nat_blocks * - NAT_ENTRY_BITMAP_SIZE, GFP_KERNEL); + nm_i->free_nid_bitmap = f2fs_kzalloc(sbi, nm_i->nat_blocks * + sizeof(unsigned char *), GFP_KERNEL); if (!nm_i->free_nid_bitmap) return -ENOMEM; + for (i = 0; i < nm_i->nat_blocks; i++) { + nm_i->free_nid_bitmap[i] = f2fs_kvzalloc(sbi, + NAT_ENTRY_BITMAP_SIZE_ALIGNED, GFP_KERNEL); + if (!nm_i->free_nid_bitmap) + return -ENOMEM; + } + nm_i->nat_block_bitmap = f2fs_kvzalloc(sbi, nm_i->nat_blocks / 8, GFP_KERNEL); if (!nm_i->nat_block_bitmap) @@ -2804,7 +2812,13 @@ void destroy_node_manager(struct f2fs_sb_info *sbi) up_write(&nm_i->nat_tree_lock); kvfree(nm_i->nat_block_bitmap); - kvfree(nm_i->free_nid_bitmap); + if (nm_i->free_nid_bitmap) { + int i; + + for (i = 0; i < nm_i->nat_blocks; i++) + kvfree(nm_i->free_nid_bitmap[i]); + kfree(nm_i->free_nid_bitmap); + } kvfree(nm_i->free_nid_count); kfree(nm_i->nat_bitmap); diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index 124787e8db58..aa5db8b5521a 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -305,6 +305,10 @@ struct f2fs_node { */ #define NAT_ENTRY_PER_BLOCK (PAGE_SIZE / sizeof(struct f2fs_nat_entry)) #define NAT_ENTRY_BITMAP_SIZE ((NAT_ENTRY_PER_BLOCK + 7) / 8) +#define NAT_ENTRY_BITMAP_SIZE_ALIGNED \ + ((NAT_ENTRY_BITMAP_SIZE + BITS_PER_LONG - 1) / \ + BITS_PER_LONG * BITS_PER_LONG) + struct f2fs_nat_entry { __u8 version; /* latest version of cached nat entry */ -- cgit v1.2.3 From 71db049e7355f31604e2c04b6cabb71d02bd487d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 17 Feb 2018 14:58:40 +0100 Subject: rtc: Add RTC range Add a way for drivers to inform the core of the supported date/time range. The core can then check whether the date/time or alarm is in the range before calling ->set_time, ->set_mmss or ->set_alarm. It returns -ERANGE when the time is out of range. Signed-off-by: Alexandre Belloni --- Documentation/ABI/testing/sysfs-class-rtc | 8 ++++++++ drivers/rtc/interface.c | 14 ++++++++++++++ drivers/rtc/rtc-sysfs.c | 12 ++++++++++++ include/linux/rtc.h | 3 +++ 4 files changed, 37 insertions(+) (limited to 'include/linux') diff --git a/Documentation/ABI/testing/sysfs-class-rtc b/Documentation/ABI/testing/sysfs-class-rtc index 792a38300336..95984289a4ee 100644 --- a/Documentation/ABI/testing/sysfs-class-rtc +++ b/Documentation/ABI/testing/sysfs-class-rtc @@ -43,6 +43,14 @@ Contact: linux-rtc@vger.kernel.org Description: (RO) The name of the RTC corresponding to this sysfs directory +What: /sys/class/rtc/rtcX/range +Date: January 2018 +KernelVersion: 4.16 +Contact: linux-rtc@vger.kernel.org +Description: + Valid time range for the RTC, as seconds from epoch, formatted + as [min, max] + What: /sys/class/rtc/rtcX/since_epoch Date: March 2006 KernelVersion: 2.6.17 diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c index 7e253be19ba7..c068daebeec2 100644 --- a/drivers/rtc/interface.c +++ b/drivers/rtc/interface.c @@ -70,6 +70,13 @@ int rtc_set_time(struct rtc_device *rtc, struct rtc_time *tm) if (err != 0) return err; + if (rtc->range_min != rtc->range_max) { + time64_t time = rtc_tm_to_time64(tm); + + if (time < rtc->range_min || time > rtc->range_max) + return -ERANGE; + } + err = mutex_lock_interruptible(&rtc->ops_lock); if (err) return err; @@ -374,6 +381,13 @@ int rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) if (err != 0) return err; + if (rtc->range_min != rtc->range_max) { + time64_t time = rtc_tm_to_time64(&alarm->time); + + if (time < rtc->range_min || time > rtc->range_max) + return -ERANGE; + } + err = mutex_lock_interruptible(&rtc->ops_lock); if (err) return err; diff --git a/drivers/rtc/rtc-sysfs.c b/drivers/rtc/rtc-sysfs.c index 92ff2edb86a6..454da38c6012 100644 --- a/drivers/rtc/rtc-sysfs.c +++ b/drivers/rtc/rtc-sysfs.c @@ -248,6 +248,14 @@ offset_store(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RW(offset); +static ssize_t +range_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "[%lld,%llu]\n", to_rtc_device(dev)->range_min, + to_rtc_device(dev)->range_max); +} +static DEVICE_ATTR_RO(range); + static struct attribute *rtc_attrs[] = { &dev_attr_name.attr, &dev_attr_date.attr, @@ -257,6 +265,7 @@ static struct attribute *rtc_attrs[] = { &dev_attr_hctosys.attr, &dev_attr_wakealarm.attr, &dev_attr_offset.attr, + &dev_attr_range.attr, NULL, }; @@ -286,6 +295,9 @@ static umode_t rtc_attr_is_visible(struct kobject *kobj, } else if (attr == &dev_attr_offset.attr) { if (!rtc->ops->set_offset) mode = 0; + } else if (attr == &dev_attr_range.attr) { + if (!(rtc->range_max - rtc->range_min)) + mode = 0; } return mode; diff --git a/include/linux/rtc.h b/include/linux/rtc.h index 3b65b201169c..c78528c394e5 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -150,6 +150,9 @@ struct rtc_device { bool nvram_old_abi; struct bin_attribute *nvram; + time64_t range_min; + timeu64_t range_max; + #ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL struct work_struct uie_task; struct timer_list uie_timer; -- cgit v1.2.3 From 989515647e783221f9737ed1cf519573d26ce99b Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Mon, 8 Jan 2018 14:04:50 +0800 Subject: rtc: Add one offset seconds to expand RTC range From our investigation for all RTC drivers, 1 driver will be expired before year 2017, 7 drivers will be expired before year 2038, 23 drivers will be expired before year 2069, 72 drivers will be expired before 2100 and 104 drivers will be expired before 2106. Especially for these early expired drivers, we need to expand the RTC range to make the RTC can still work after the expired year. So we can expand the RTC range by adding one offset to the time when reading from hardware, and subtracting it when writing back. For example, if you have an RTC that can do 100 years, and currently is configured to be based in Jan 1 1970, so it can represents times from 1970 to 2069. Then if you change the start year from 1970 to 2000, which means it can represents times from 2000 to 2099. By adding or subtracting the offset produced by moving the wrap point, all times between 1970 and 1999 from RTC hardware could get interpreted as times from 2070 to 2099, but the interpretation of dates between 2000 and 2069 would not change. Signed-off-by: Baolin Wang Signed-off-by: Alexandre Belloni --- drivers/rtc/class.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/rtc/interface.c | 59 ++++++++++++++++++++++++++++++++++++++++- include/linux/rtc.h | 3 +++ 3 files changed, 131 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c index 5a5ab4fa14f9..d37588f08055 100644 --- a/drivers/rtc/class.c +++ b/drivers/rtc/class.c @@ -211,6 +211,73 @@ static int rtc_device_get_id(struct device *dev) return id; } +static void rtc_device_get_offset(struct rtc_device *rtc) +{ + time64_t range_secs; + u32 start_year; + int ret; + + /* + * If RTC driver did not implement the range of RTC hardware device, + * then we can not expand the RTC range by adding or subtracting one + * offset. + */ + if (rtc->range_min == rtc->range_max) + return; + + ret = device_property_read_u32(rtc->dev.parent, "start-year", + &start_year); + if (!ret) { + rtc->start_secs = mktime64(start_year, 1, 1, 0, 0, 0); + rtc->set_start_time = true; + } + + /* + * If user did not implement the start time for RTC driver, then no + * need to expand the RTC range. + */ + if (!rtc->set_start_time) + return; + + range_secs = rtc->range_max - rtc->range_min + 1; + + /* + * If the start_secs is larger than the maximum seconds (rtc->range_max) + * supported by RTC hardware or the maximum seconds of new expanded + * range (start_secs + rtc->range_max - rtc->range_min) is less than + * rtc->range_min, which means the minimum seconds (rtc->range_min) of + * RTC hardware will be mapped to start_secs by adding one offset, so + * the offset seconds calculation formula should be: + * rtc->offset_secs = rtc->start_secs - rtc->range_min; + * + * If the start_secs is larger than the minimum seconds (rtc->range_min) + * supported by RTC hardware, then there is one region is overlapped + * between the original RTC hardware range and the new expanded range, + * and this overlapped region do not need to be mapped into the new + * expanded range due to it is valid for RTC device. So the minimum + * seconds of RTC hardware (rtc->range_min) should be mapped to + * rtc->range_max + 1, then the offset seconds formula should be: + * rtc->offset_secs = rtc->range_max - rtc->range_min + 1; + * + * If the start_secs is less than the minimum seconds (rtc->range_min), + * which is similar to case 2. So the start_secs should be mapped to + * start_secs + rtc->range_max - rtc->range_min + 1, then the + * offset seconds formula should be: + * rtc->offset_secs = -(rtc->range_max - rtc->range_min + 1); + * + * Otherwise the offset seconds should be 0. + */ + if (rtc->start_secs > rtc->range_max || + rtc->start_secs + range_secs - 1 < rtc->range_min) + rtc->offset_secs = rtc->start_secs - rtc->range_min; + else if (rtc->start_secs > rtc->range_min) + rtc->offset_secs = range_secs; + else if (rtc->start_secs < rtc->range_min) + rtc->offset_secs = -range_secs; + else + rtc->offset_secs = 0; +} + /** * rtc_device_register - register w/ RTC class * @dev: the device to register @@ -247,6 +314,8 @@ struct rtc_device *rtc_device_register(const char *name, struct device *dev, dev_set_name(&rtc->dev, "rtc%d", id); + rtc_device_get_offset(rtc); + /* Check to see if there is an ALARM already set in hw */ err = __rtc_read_alarm(rtc, &alrm); @@ -436,6 +505,7 @@ int __rtc_register_device(struct module *owner, struct rtc_device *rtc) return -EINVAL; rtc->owner = owner; + rtc_device_get_offset(rtc); /* Check to see if there is an ALARM already set in hw */ err = __rtc_read_alarm(rtc, &alrm); diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c index 25aebc5b448d..7cbdc9228dd5 100644 --- a/drivers/rtc/interface.c +++ b/drivers/rtc/interface.c @@ -23,12 +23,61 @@ static int rtc_timer_enqueue(struct rtc_device *rtc, struct rtc_timer *timer); static void rtc_timer_remove(struct rtc_device *rtc, struct rtc_timer *timer); +static void rtc_add_offset(struct rtc_device *rtc, struct rtc_time *tm) +{ + time64_t secs; + + if (!rtc->offset_secs) + return; + + secs = rtc_tm_to_time64(tm); + + /* + * Since the reading time values from RTC device are always in the RTC + * original valid range, but we need to skip the overlapped region + * between expanded range and original range, which is no need to add + * the offset. + */ + if ((rtc->start_secs > rtc->range_min && secs >= rtc->start_secs) || + (rtc->start_secs < rtc->range_min && + secs <= (rtc->start_secs + rtc->range_max - rtc->range_min))) + return; + + rtc_time64_to_tm(secs + rtc->offset_secs, tm); +} + +static void rtc_subtract_offset(struct rtc_device *rtc, struct rtc_time *tm) +{ + time64_t secs; + + if (!rtc->offset_secs) + return; + + secs = rtc_tm_to_time64(tm); + + /* + * If the setting time values are in the valid range of RTC hardware + * device, then no need to subtract the offset when setting time to RTC + * device. Otherwise we need to subtract the offset to make the time + * values are valid for RTC hardware device. + */ + if (secs >= rtc->range_min && secs <= rtc->range_max) + return; + + rtc_time64_to_tm(secs - rtc->offset_secs, tm); +} + static int rtc_valid_range(struct rtc_device *rtc, struct rtc_time *tm) { if (rtc->range_min != rtc->range_max) { time64_t time = rtc_tm_to_time64(tm); + time64_t range_min = rtc->set_start_time ? rtc->start_secs : + rtc->range_min; + time64_t range_max = rtc->set_start_time ? + (rtc->start_secs + rtc->range_max - rtc->range_min) : + rtc->range_max; - if (time < rtc->range_min || time > rtc->range_max) + if (time < range_min || time > range_max) return -ERANGE; } @@ -51,6 +100,8 @@ static int __rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm) return err; } + rtc_add_offset(rtc, tm); + err = rtc_valid_tm(tm); if (err < 0) dev_dbg(&rtc->dev, "read_time: rtc_time isn't valid\n"); @@ -86,6 +137,8 @@ int rtc_set_time(struct rtc_device *rtc, struct rtc_time *tm) if (err) return err; + rtc_subtract_offset(rtc, tm); + err = mutex_lock_interruptible(&rtc->ops_lock); if (err) return err; @@ -355,6 +408,8 @@ static int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) err = rtc_valid_tm(&alarm->time); if (err) return err; + + rtc_subtract_offset(rtc, &alarm->time); scheduled = rtc_tm_to_time64(&alarm->time); /* Make sure we're not setting alarms in the past */ @@ -406,6 +461,8 @@ int rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) err = rtc_timer_enqueue(rtc, &rtc->aie_timer); mutex_unlock(&rtc->ops_lock); + + rtc_add_offset(rtc, &alarm->time); return err; } EXPORT_SYMBOL_GPL(rtc_set_alarm); diff --git a/include/linux/rtc.h b/include/linux/rtc.h index c78528c394e5..82a3038f16ab 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -152,6 +152,9 @@ struct rtc_device { time64_t range_min; timeu64_t range_max; + time64_t start_secs; + time64_t offset_secs; + bool set_start_time; #ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL struct work_struct uie_task; -- cgit v1.2.3 From 83bbc5ac63326433755592829caf02920b3d8dc0 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 8 Mar 2018 00:13:52 +0100 Subject: rtc: Add useful timestamp definitions Add commonly used timestamps for range definition. Signed-off-by: Alexandre Belloni --- include/linux/rtc.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux') diff --git a/include/linux/rtc.h b/include/linux/rtc.h index 82a3038f16ab..4c007f69082f 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -169,6 +169,11 @@ struct rtc_device { }; #define to_rtc_device(d) container_of(d, struct rtc_device, dev) +/* useful timestamps */ +#define RTC_TIMESTAMP_BEGIN_1900 -2208989361LL /* 1900-01-01 00:00:00 */ +#define RTC_TIMESTAMP_BEGIN_2000 946684800LL /* 2000-01-01 00:00:00 */ +#define RTC_TIMESTAMP_END_2099 4102444799LL /* 2099-12-31 23:59:59 */ + extern struct rtc_device *rtc_device_register(const char *name, struct device *dev, const struct rtc_class_ops *ops, -- cgit v1.2.3 From 4a681243cc2d2cea98c6b5e57224f3bcb08bce6c Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Sat, 10 Mar 2018 00:27:15 -0600 Subject: rtc: s5m: Move enum from rtc.h to rtc-s5m.c Move this enum to rtc-s5m.c once it is meaningless to others drivers [1]. [1] https://marc.info/?l=linux-rtc&m=152060068925948&w=2 Suggested-by: Krzysztof Kozlowski Signed-off-by: Gustavo A. R. Silva Reviewed-by: Krzysztof Kozlowski Acked-by: Lee Jones Signed-off-by: Alexandre Belloni --- drivers/rtc/rtc-s5m.c | 11 +++++++++++ include/linux/mfd/samsung/rtc.h | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include/linux') diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c index 6deae10c14ac..4c363deb79fd 100644 --- a/drivers/rtc/rtc-s5m.c +++ b/drivers/rtc/rtc-s5m.c @@ -38,6 +38,17 @@ */ #define UDR_READ_RETRY_CNT 5 +enum { + RTC_SEC = 0, + RTC_MIN, + RTC_HOUR, + RTC_WEEKDAY, + RTC_DATE, + RTC_MONTH, + RTC_YEAR1, + RTC_YEAR2, +}; + /* * Registers used by the driver which are different between chipsets. * diff --git a/include/linux/mfd/samsung/rtc.h b/include/linux/mfd/samsung/rtc.h index 48c3c5be7eb1..9ed2871ea335 100644 --- a/include/linux/mfd/samsung/rtc.h +++ b/include/linux/mfd/samsung/rtc.h @@ -141,15 +141,4 @@ enum s2mps_rtc_reg { #define WTSR_ENABLE_SHIFT 6 #define WTSR_ENABLE_MASK (1 << WTSR_ENABLE_SHIFT) -enum { - RTC_SEC = 0, - RTC_MIN, - RTC_HOUR, - RTC_WEEKDAY, - RTC_DATE, - RTC_MONTH, - RTC_YEAR1, - RTC_YEAR2, -}; - #endif /* __LINUX_MFD_SEC_RTC_H */ -- cgit v1.2.3 From 233bde21aa43516baa013ef7ac33f3427056db3e Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Wed, 14 Mar 2018 15:48:06 -0700 Subject: block: Move SECTOR_SIZE and SECTOR_SHIFT definitions into It happens often while I'm preparing a patch for a block driver that I'm wondering: is a definition of SECTOR_SIZE and/or SECTOR_SHIFT available for this driver? Do I have to introduce definitions of these constants before I can use these constants? To avoid this confusion, move the existing definitions of SECTOR_SIZE and SECTOR_SHIFT into the header file such that these become available for all block drivers. Make the SECTOR_SIZE definition in the uapi msdos_fs.h header file conditional to avoid that including that header file after causes the compiler to complain about a SECTOR_SIZE redefinition. Note: the SECTOR_SIZE / SECTOR_SHIFT / SECTOR_BITS definitions have not been removed from uapi header files nor from NAND drivers in which these constants are used for another purpose than converting block layer offsets and sizes into a number of sectors. Cc: David S. Miller Cc: Mike Snitzer Cc: Dan Williams Cc: Minchan Kim Cc: Nitin Gupta Reviewed-by: Sergey Senozhatsky Reviewed-by: Christoph Hellwig Reviewed-by: Johannes Thumshirn Reviewed-by: Martin K. Petersen Signed-off-by: Bart Van Assche Signed-off-by: Jens Axboe --- arch/xtensa/platforms/iss/simdisk.c | 1 - drivers/block/brd.c | 1 - drivers/block/null_blk.c | 2 -- drivers/block/rbd.c | 9 -------- drivers/block/zram/zram_drv.h | 1 - drivers/ide/ide-cd.c | 8 +++---- drivers/ide/ide-cd.h | 6 +----- drivers/nvdimm/nd.h | 1 - drivers/scsi/gdth.h | 3 --- include/linux/blkdev.h | 42 +++++++++++++++++++++++++++---------- include/linux/device-mapper.h | 2 -- include/linux/ide.h | 1 - include/uapi/linux/msdos_fs.h | 2 ++ 13 files changed, 38 insertions(+), 41 deletions(-) (limited to 'include/linux') diff --git a/arch/xtensa/platforms/iss/simdisk.c b/arch/xtensa/platforms/iss/simdisk.c index 1b6418407467..026211e7ab09 100644 --- a/arch/xtensa/platforms/iss/simdisk.c +++ b/arch/xtensa/platforms/iss/simdisk.c @@ -21,7 +21,6 @@ #include #define SIMDISK_MAJOR 240 -#define SECTOR_SHIFT 9 #define SIMDISK_MINORS 1 #define MAX_SIMDISK_COUNT 10 diff --git a/drivers/block/brd.c b/drivers/block/brd.c index deea78e485da..66cb0f857f64 100644 --- a/drivers/block/brd.c +++ b/drivers/block/brd.c @@ -24,7 +24,6 @@ #include -#define SECTOR_SHIFT 9 #define PAGE_SECTORS_SHIFT (PAGE_SHIFT - SECTOR_SHIFT) #define PAGE_SECTORS (1 << PAGE_SECTORS_SHIFT) diff --git a/drivers/block/null_blk.c b/drivers/block/null_blk.c index 0517613afccb..a76553293a31 100644 --- a/drivers/block/null_blk.c +++ b/drivers/block/null_blk.c @@ -16,10 +16,8 @@ #include #include -#define SECTOR_SHIFT 9 #define PAGE_SECTORS_SHIFT (PAGE_SHIFT - SECTOR_SHIFT) #define PAGE_SECTORS (1 << PAGE_SECTORS_SHIFT) -#define SECTOR_SIZE (1 << SECTOR_SHIFT) #define SECTOR_MASK (PAGE_SECTORS - 1) #define FREE_BATCH 16 diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c index 0016170cde0a..1e03b04819c8 100644 --- a/drivers/block/rbd.c +++ b/drivers/block/rbd.c @@ -50,15 +50,6 @@ #define RBD_DEBUG /* Activate rbd_assert() calls */ -/* - * The basic unit of block I/O is a sector. It is interpreted in a - * number of contexts in Linux (blk, bio, genhd), but the default is - * universally 512 bytes. These symbols are just slightly more - * meaningful than the bare numbers they represent. - */ -#define SECTOR_SHIFT 9 -#define SECTOR_SIZE (1ULL << SECTOR_SHIFT) - /* * Increment the given counter and return its updated value. * If the counter is already 0 it will not be incremented. diff --git a/drivers/block/zram/zram_drv.h b/drivers/block/zram/zram_drv.h index 31762db861e3..1e9bf65c0bfb 100644 --- a/drivers/block/zram/zram_drv.h +++ b/drivers/block/zram/zram_drv.h @@ -37,7 +37,6 @@ static const size_t max_zpage_size = PAGE_SIZE / 4 * 3; /*-- End of configurable params */ -#define SECTOR_SHIFT 9 #define SECTORS_PER_PAGE_SHIFT (PAGE_SHIFT - SECTOR_SHIFT) #define SECTORS_PER_PAGE (1 << SECTORS_PER_PAGE_SHIFT) #define ZRAM_LOGICAL_BLOCK_SHIFT 12 diff --git a/drivers/ide/ide-cd.c b/drivers/ide/ide-cd.c index 5613cc2d51fc..5a8e8e3c22cd 100644 --- a/drivers/ide/ide-cd.c +++ b/drivers/ide/ide-cd.c @@ -712,7 +712,7 @@ static ide_startstop_t cdrom_start_rw(ide_drive_t *drive, struct request *rq) struct request_queue *q = drive->queue; int write = rq_data_dir(rq) == WRITE; unsigned short sectors_per_frame = - queue_logical_block_size(q) >> SECTOR_BITS; + queue_logical_block_size(q) >> SECTOR_SHIFT; ide_debug_log(IDE_DBG_RQ, "rq->cmd[0]: 0x%x, rq->cmd_flags: 0x%x, " "secs_per_frame: %u", @@ -919,7 +919,7 @@ static int cdrom_read_capacity(ide_drive_t *drive, unsigned long *capacity, * end up being bogus. */ blocklen = be32_to_cpu(capbuf.blocklen); - blocklen = (blocklen >> SECTOR_BITS) << SECTOR_BITS; + blocklen = (blocklen >> SECTOR_SHIFT) << SECTOR_SHIFT; switch (blocklen) { case 512: case 1024: @@ -935,7 +935,7 @@ static int cdrom_read_capacity(ide_drive_t *drive, unsigned long *capacity, } *capacity = 1 + be32_to_cpu(capbuf.lba); - *sectors_per_frame = blocklen >> SECTOR_BITS; + *sectors_per_frame = blocklen >> SECTOR_SHIFT; ide_debug_log(IDE_DBG_PROBE, "cap: %lu, sectors_per_frame: %lu", *capacity, *sectors_per_frame); @@ -1012,7 +1012,7 @@ int ide_cd_read_toc(ide_drive_t *drive, struct request_sense *sense) drive->probed_capacity = toc->capacity * sectors_per_frame; blk_queue_logical_block_size(drive->queue, - sectors_per_frame << SECTOR_BITS); + sectors_per_frame << SECTOR_SHIFT); /* first read just the header, so we know how long the TOC is */ stat = cdrom_read_tocentry(drive, 0, 1, 0, (char *) &toc->hdr, diff --git a/drivers/ide/ide-cd.h b/drivers/ide/ide-cd.h index 264e822eba58..04f0f310a856 100644 --- a/drivers/ide/ide-cd.h +++ b/drivers/ide/ide-cd.h @@ -21,11 +21,7 @@ /************************************************************************/ -#define SECTOR_BITS 9 -#ifndef SECTOR_SIZE -#define SECTOR_SIZE (1 << SECTOR_BITS) -#endif -#define SECTORS_PER_FRAME (CD_FRAMESIZE >> SECTOR_BITS) +#define SECTORS_PER_FRAME (CD_FRAMESIZE >> SECTOR_SHIFT) #define SECTOR_BUFFER_SIZE (CD_FRAMESIZE * 32) /* Capabilities Page size including 8 bytes of Mode Page Header */ diff --git a/drivers/nvdimm/nd.h b/drivers/nvdimm/nd.h index 8d6375ee0fda..184e070d50a2 100644 --- a/drivers/nvdimm/nd.h +++ b/drivers/nvdimm/nd.h @@ -29,7 +29,6 @@ enum { * BTT instance */ ND_MAX_LANES = 256, - SECTOR_SHIFT = 9, INT_LBASIZE_ALIGNMENT = 64, NVDIMM_IO_ATOMIC = 1, }; diff --git a/drivers/scsi/gdth.h b/drivers/scsi/gdth.h index 95fc720c1b30..e6e5ccb1e0f3 100644 --- a/drivers/scsi/gdth.h +++ b/drivers/scsi/gdth.h @@ -178,9 +178,6 @@ #define MSG_SIZE 34 /* size of message structure */ #define MSG_REQUEST 0 /* async. event: message */ -/* cacheservice defines */ -#define SECTOR_SIZE 0x200 /* always 512 bytes per sec. */ - /* DPMEM constants */ #define DPMEM_MAGIC 0xC0FFEE11 #define IC_HEADER_BYTES 48 diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 19eaf8d89368..9af3e0f430bc 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -1021,6 +1021,19 @@ static inline struct request_queue *bdev_get_queue(struct block_device *bdev) return bdev->bd_disk->queue; /* this is never NULL */ } +/* + * The basic unit of block I/O is a sector. It is used in a number of contexts + * in Linux (blk, bio, genhd). The size of one sector is 512 = 2**9 + * bytes. Variables of type sector_t represent an offset or size that is a + * multiple of 512 bytes. Hence these two constants. + */ +#ifndef SECTOR_SHIFT +#define SECTOR_SHIFT 9 +#endif +#ifndef SECTOR_SIZE +#define SECTOR_SIZE (1 << SECTOR_SHIFT) +#endif + /* * blk_rq_pos() : the current sector * blk_rq_bytes() : bytes left in the entire request @@ -1048,12 +1061,12 @@ extern unsigned int blk_rq_err_bytes(const struct request *rq); static inline unsigned int blk_rq_sectors(const struct request *rq) { - return blk_rq_bytes(rq) >> 9; + return blk_rq_bytes(rq) >> SECTOR_SHIFT; } static inline unsigned int blk_rq_cur_sectors(const struct request *rq) { - return blk_rq_cur_bytes(rq) >> 9; + return blk_rq_cur_bytes(rq) >> SECTOR_SHIFT; } static inline unsigned int blk_rq_zone_no(struct request *rq) @@ -1083,7 +1096,8 @@ static inline unsigned int blk_queue_get_max_sectors(struct request_queue *q, int op) { if (unlikely(op == REQ_OP_DISCARD || op == REQ_OP_SECURE_ERASE)) - return min(q->limits.max_discard_sectors, UINT_MAX >> 9); + return min(q->limits.max_discard_sectors, + UINT_MAX >> SECTOR_SHIFT); if (unlikely(op == REQ_OP_WRITE_SAME)) return q->limits.max_write_same_sectors; @@ -1395,16 +1409,21 @@ extern int blkdev_issue_zeroout(struct block_device *bdev, sector_t sector, static inline int sb_issue_discard(struct super_block *sb, sector_t block, sector_t nr_blocks, gfp_t gfp_mask, unsigned long flags) { - return blkdev_issue_discard(sb->s_bdev, block << (sb->s_blocksize_bits - 9), - nr_blocks << (sb->s_blocksize_bits - 9), + return blkdev_issue_discard(sb->s_bdev, + block << (sb->s_blocksize_bits - + SECTOR_SHIFT), + nr_blocks << (sb->s_blocksize_bits - + SECTOR_SHIFT), gfp_mask, flags); } static inline int sb_issue_zeroout(struct super_block *sb, sector_t block, sector_t nr_blocks, gfp_t gfp_mask) { return blkdev_issue_zeroout(sb->s_bdev, - block << (sb->s_blocksize_bits - 9), - nr_blocks << (sb->s_blocksize_bits - 9), + block << (sb->s_blocksize_bits - + SECTOR_SHIFT), + nr_blocks << (sb->s_blocksize_bits - + SECTOR_SHIFT), gfp_mask, 0); } @@ -1511,7 +1530,8 @@ static inline int queue_alignment_offset(struct request_queue *q) static inline int queue_limit_alignment_offset(struct queue_limits *lim, sector_t sector) { unsigned int granularity = max(lim->physical_block_size, lim->io_min); - unsigned int alignment = sector_div(sector, granularity >> 9) << 9; + unsigned int alignment = sector_div(sector, granularity >> SECTOR_SHIFT) + << SECTOR_SHIFT; return (granularity + lim->alignment_offset - alignment) % granularity; } @@ -1545,8 +1565,8 @@ static inline int queue_limit_discard_alignment(struct queue_limits *lim, sector return 0; /* Why are these in bytes, not sectors? */ - alignment = lim->discard_alignment >> 9; - granularity = lim->discard_granularity >> 9; + alignment = lim->discard_alignment >> SECTOR_SHIFT; + granularity = lim->discard_granularity >> SECTOR_SHIFT; if (!granularity) return 0; @@ -1557,7 +1577,7 @@ static inline int queue_limit_discard_alignment(struct queue_limits *lim, sector offset = (granularity + alignment - offset) % granularity; /* Turn it back into bytes, gaah */ - return offset << 9; + return offset << SECTOR_SHIFT; } static inline int bdev_discard_alignment(struct block_device *bdev) diff --git a/include/linux/device-mapper.h b/include/linux/device-mapper.h index da83f64952e7..4384433b50e7 100644 --- a/include/linux/device-mapper.h +++ b/include/linux/device-mapper.h @@ -542,8 +542,6 @@ do { \ #define DMEMIT(x...) sz += ((sz >= maxlen) ? \ 0 : scnprintf(result + sz, maxlen - sz, x)) -#define SECTOR_SHIFT 9 - /* * Definitions of return values from target end_io function. */ diff --git a/include/linux/ide.h b/include/linux/ide.h index 771989d25ef8..0acfa62b1d44 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -165,7 +165,6 @@ struct ide_io_ports { */ #define PARTN_BITS 6 /* number of minor dev bits for partitions */ #define MAX_DRIVES 2 /* per interface; 2 assumed by lots of code */ -#define SECTOR_SIZE 512 /* * Timeouts for various operations: diff --git a/include/uapi/linux/msdos_fs.h b/include/uapi/linux/msdos_fs.h index a45d0754102e..fde753735aba 100644 --- a/include/uapi/linux/msdos_fs.h +++ b/include/uapi/linux/msdos_fs.h @@ -10,7 +10,9 @@ * The MS-DOS filesystem constants/structures */ +#ifndef SECTOR_SIZE #define SECTOR_SIZE 512 /* sector size (bytes) */ +#endif #define SECTOR_BITS 9 /* log2(SECTOR_SIZE) */ #define MSDOS_DPB (MSDOS_DPS) /* dir entries per block */ #define MSDOS_DPB_BITS 4 /* log2(MSDOS_DPB) */ -- cgit v1.2.3 From 9035cf9a97e429e6b5291841da81c433879f5658 Mon Sep 17 00:00:00 2001 From: Khalid Aziz Date: Wed, 21 Feb 2018 10:15:49 -0700 Subject: mm: Add address parameter to arch_validate_prot() A protection flag may not be valid across entire address space and hence arch_validate_prot() might need the address a protection bit is being set on to ensure it is a valid protection flag. For example, sparc processors support memory corruption detection (as part of ADI feature) flag on memory addresses mapped on to physical RAM but not on PFN mapped pages or addresses mapped on to devices. This patch adds address to the parameters being passed to arch_validate_prot() so protection bits can be validated in the relevant context. Signed-off-by: Khalid Aziz Cc: Khalid Aziz Reviewed-by: Anthony Yznaga Acked-by: Michael Ellerman (powerpc) Acked-by: Andrew Morton Signed-off-by: David S. Miller --- arch/powerpc/include/asm/mman.h | 4 ++-- arch/powerpc/kernel/syscalls.c | 2 +- include/linux/mman.h | 2 +- mm/mprotect.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/arch/powerpc/include/asm/mman.h b/arch/powerpc/include/asm/mman.h index 07e3f54de9e3..e3f1b5ba5d5c 100644 --- a/arch/powerpc/include/asm/mman.h +++ b/arch/powerpc/include/asm/mman.h @@ -43,7 +43,7 @@ static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags) } #define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags) -static inline bool arch_validate_prot(unsigned long prot) +static inline bool arch_validate_prot(unsigned long prot, unsigned long addr) { if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO)) return false; @@ -51,7 +51,7 @@ static inline bool arch_validate_prot(unsigned long prot) return false; return true; } -#define arch_validate_prot(prot) arch_validate_prot(prot) +#define arch_validate_prot arch_validate_prot #endif /* CONFIG_PPC64 */ #endif /* _ASM_POWERPC_MMAN_H */ diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c index a877bf8269fe..6d90ddbd2d11 100644 --- a/arch/powerpc/kernel/syscalls.c +++ b/arch/powerpc/kernel/syscalls.c @@ -48,7 +48,7 @@ static inline long do_mmap2(unsigned long addr, size_t len, { long ret = -EINVAL; - if (!arch_validate_prot(prot)) + if (!arch_validate_prot(prot, addr)) goto out; if (shift) { diff --git a/include/linux/mman.h b/include/linux/mman.h index 6a4d1caaff5c..4b08e9c9c538 100644 --- a/include/linux/mman.h +++ b/include/linux/mman.h @@ -92,7 +92,7 @@ static inline void vm_unacct_memory(long pages) * * Returns true if the prot flags are valid */ -static inline bool arch_validate_prot(unsigned long prot) +static inline bool arch_validate_prot(unsigned long prot, unsigned long addr) { return (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM)) == 0; } diff --git a/mm/mprotect.c b/mm/mprotect.c index e3309fcf586b..088ea9c08678 100644 --- a/mm/mprotect.c +++ b/mm/mprotect.c @@ -417,7 +417,7 @@ static int do_mprotect_pkey(unsigned long start, size_t len, end = start + len; if (end <= start) return -ENOMEM; - if (!arch_validate_prot(prot)) + if (!arch_validate_prot(prot, start)) return -EINVAL; reqprot = prot; -- cgit v1.2.3 From 2c2d57b5e769956fb36581e0d3cccdb5ea68038f Mon Sep 17 00:00:00 2001 From: Khalid Aziz Date: Wed, 21 Feb 2018 10:15:50 -0700 Subject: mm: Clear arch specific VM flags on protection change When protection bits are changed on a VMA, some of the architecture specific flags should be cleared as well. An examples of this are the PKEY flags on x86. This patch expands the current code that clears PKEY flags for x86, to support similar functionality for other architectures as well. Signed-off-by: Khalid Aziz Cc: Khalid Aziz Reviewed-by: Anthony Yznaga Acked-by: Andrew Morton Signed-off-by: David S. Miller --- include/linux/mm.h | 6 ++++++ mm/mprotect.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/mm.h b/include/linux/mm.h index ad06d42adb1a..ae806dbc63ee 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -287,6 +287,12 @@ extern unsigned int kobjsize(const void *objp); /* This mask is used to clear all the VMA flags used by mlock */ #define VM_LOCKED_CLEAR_MASK (~(VM_LOCKED | VM_LOCKONFAULT)) +/* Arch-specific flags to clear when updating VM flags on protection change */ +#ifndef VM_ARCH_CLEAR +# define VM_ARCH_CLEAR VM_NONE +#endif +#define VM_FLAGS_CLEAR (ARCH_VM_PKEY_FLAGS | VM_ARCH_CLEAR) + /* * mapping from the currently active vm_flags protection bits (the * low four bits) to a page protection mask.. diff --git a/mm/mprotect.c b/mm/mprotect.c index 088ea9c08678..c1d6af7455da 100644 --- a/mm/mprotect.c +++ b/mm/mprotect.c @@ -475,7 +475,7 @@ static int do_mprotect_pkey(unsigned long start, size_t len, * cleared from the VMA. */ mask_off_old_flags = VM_READ | VM_WRITE | VM_EXEC | - ARCH_VM_PKEY_FLAGS; + VM_FLAGS_CLEAR; new_vma_pkey = arch_override_mprotect_pkey(vma, prot, pkey); newflags = calc_vm_prot_bits(prot, new_vma_pkey); -- cgit v1.2.3 From a4602b62d9fdea41412ba765bbf32ecfc2b6a94c Mon Sep 17 00:00:00 2001 From: Khalid Aziz Date: Wed, 21 Feb 2018 10:15:51 -0700 Subject: mm: Allow arch code to override copy_highpage() Some architectures can support metadata for memory pages and when a page is copied, its metadata must also be copied. Sparc processors from M7 onwards support metadata for memory pages. This metadata provides tag based protection for access to memory pages. To maintain this protection, the tag data must be copied to the new page when a page is migrated across NUMA nodes. This patch allows arch specific code to override default copy_highpage() and copy metadata along with page data upon migration. Signed-off-by: Khalid Aziz Cc: Khalid Aziz Reviewed-by: Anthony Yznaga Acked-by: Andrew Morton Signed-off-by: David S. Miller --- include/linux/highmem.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux') diff --git a/include/linux/highmem.h b/include/linux/highmem.h index 776f90f3a1cd..0690679832d4 100644 --- a/include/linux/highmem.h +++ b/include/linux/highmem.h @@ -237,6 +237,8 @@ static inline void copy_user_highpage(struct page *to, struct page *from, #endif +#ifndef __HAVE_ARCH_COPY_HIGHPAGE + static inline void copy_highpage(struct page *to, struct page *from) { char *vfrom, *vto; @@ -248,4 +250,6 @@ static inline void copy_highpage(struct page *to, struct page *from) kunmap_atomic(vfrom); } +#endif + #endif /* _LINUX_HIGHMEM_H */ -- cgit v1.2.3 From 74a04967482faa7144b93dae3b2e913870dd421c Mon Sep 17 00:00:00 2001 From: Khalid Aziz Date: Fri, 23 Feb 2018 15:46:41 -0700 Subject: sparc64: Add support for ADI (Application Data Integrity) ADI is a new feature supported on SPARC M7 and newer processors to allow hardware to catch rogue accesses to memory. ADI is supported for data fetches only and not instruction fetches. An app can enable ADI on its data pages, set version tags on them and use versioned addresses to access the data pages. Upper bits of the address contain the version tag. On M7 processors, upper four bits (bits 63-60) contain the version tag. If a rogue app attempts to access ADI enabled data pages, its access is blocked and processor generates an exception. Please see Documentation/sparc/adi.txt for further details. This patch extends mprotect to enable ADI (TSTATE.mcde), enable/disable MCD (Memory Corruption Detection) on selected memory ranges, enable TTE.mcd in PTEs, return ADI parameters to userspace and save/restore ADI version tags on page swap out/in or migration. ADI is not enabled by default for any task. A task must explicitly enable ADI on a memory range and set version tag for ADI to be effective for the task. Signed-off-by: Khalid Aziz Cc: Khalid Aziz Reviewed-by: Anthony Yznaga Signed-off-by: David S. Miller --- Documentation/sparc/adi.txt | 278 +++++++++++++++++++++++++++++ arch/sparc/include/asm/mman.h | 84 ++++++++- arch/sparc/include/asm/mmu_64.h | 17 ++ arch/sparc/include/asm/mmu_context_64.h | 51 ++++++ arch/sparc/include/asm/page_64.h | 6 + arch/sparc/include/asm/pgtable_64.h | 46 +++++ arch/sparc/include/asm/thread_info_64.h | 2 +- arch/sparc/include/asm/trap_block.h | 2 + arch/sparc/include/uapi/asm/mman.h | 2 + arch/sparc/kernel/adi_64.c | 301 ++++++++++++++++++++++++++++++++ arch/sparc/kernel/etrap_64.S | 27 ++- arch/sparc/kernel/process_64.c | 25 +++ arch/sparc/kernel/rtrap_64.S | 33 +++- arch/sparc/kernel/setup_64.c | 2 + arch/sparc/kernel/urtt_fill.S | 7 +- arch/sparc/kernel/vmlinux.lds.S | 5 + arch/sparc/mm/gup.c | 37 ++++ arch/sparc/mm/hugetlbpage.c | 14 +- arch/sparc/mm/init_64.c | 69 ++++++++ arch/sparc/mm/tsb.c | 21 +++ include/linux/mm.h | 3 + mm/ksm.c | 4 + 22 files changed, 1028 insertions(+), 8 deletions(-) create mode 100644 Documentation/sparc/adi.txt (limited to 'include/linux') diff --git a/Documentation/sparc/adi.txt b/Documentation/sparc/adi.txt new file mode 100644 index 000000000000..e1aed155fb89 --- /dev/null +++ b/Documentation/sparc/adi.txt @@ -0,0 +1,278 @@ +Application Data Integrity (ADI) +================================ + +SPARC M7 processor adds the Application Data Integrity (ADI) feature. +ADI allows a task to set version tags on any subset of its address +space. Once ADI is enabled and version tags are set for ranges of +address space of a task, the processor will compare the tag in pointers +to memory in these ranges to the version set by the application +previously. Access to memory is granted only if the tag in given pointer +matches the tag set by the application. In case of mismatch, processor +raises an exception. + +Following steps must be taken by a task to enable ADI fully: + +1. Set the user mode PSTATE.mcde bit. This acts as master switch for + the task's entire address space to enable/disable ADI for the task. + +2. Set TTE.mcd bit on any TLB entries that correspond to the range of + addresses ADI is being enabled on. MMU checks the version tag only + on the pages that have TTE.mcd bit set. + +3. Set the version tag for virtual addresses using stxa instruction + and one of the MCD specific ASIs. Each stxa instruction sets the + given tag for one ADI block size number of bytes. This step must + be repeated for entire page to set tags for entire page. + +ADI block size for the platform is provided by the hypervisor to kernel +in machine description tables. Hypervisor also provides the number of +top bits in the virtual address that specify the version tag. Once +version tag has been set for a memory location, the tag is stored in the +physical memory and the same tag must be present in the ADI version tag +bits of the virtual address being presented to the MMU. For example on +SPARC M7 processor, MMU uses bits 63-60 for version tags and ADI block +size is same as cacheline size which is 64 bytes. A task that sets ADI +version to, say 10, on a range of memory, must access that memory using +virtual addresses that contain 0xa in bits 63-60. + +ADI is enabled on a set of pages using mprotect() with PROT_ADI flag. +When ADI is enabled on a set of pages by a task for the first time, +kernel sets the PSTATE.mcde bit fot the task. Version tags for memory +addresses are set with an stxa instruction on the addresses using +ASI_MCD_PRIMARY or ASI_MCD_ST_BLKINIT_PRIMARY. ADI block size is +provided by the hypervisor to the kernel. Kernel returns the value of +ADI block size to userspace using auxiliary vector along with other ADI +info. Following auxiliary vectors are provided by the kernel: + + AT_ADI_BLKSZ ADI block size. This is the granularity and + alignment, in bytes, of ADI versioning. + AT_ADI_NBITS Number of ADI version bits in the VA + + +IMPORTANT NOTES: + +- Version tag values of 0x0 and 0xf are reserved. These values match any + tag in virtual address and never generate a mismatch exception. + +- Version tags are set on virtual addresses from userspace even though + tags are stored in physical memory. Tags are set on a physical page + after it has been allocated to a task and a pte has been created for + it. + +- When a task frees a memory page it had set version tags on, the page + goes back to free page pool. When this page is re-allocated to a task, + kernel clears the page using block initialization ASI which clears the + version tags as well for the page. If a page allocated to a task is + freed and allocated back to the same task, old version tags set by the + task on that page will no longer be present. + +- ADI tag mismatches are not detected for non-faulting loads. + +- Kernel does not set any tags for user pages and it is entirely a + task's responsibility to set any version tags. Kernel does ensure the + version tags are preserved if a page is swapped out to the disk and + swapped back in. It also preserves that version tags if a page is + migrated. + +- ADI works for any size pages. A userspace task need not be aware of + page size when using ADI. It can simply select a virtual address + range, enable ADI on the range using mprotect() and set version tags + for the entire range. mprotect() ensures range is aligned to page size + and is a multiple of page size. + +- ADI tags can only be set on writable memory. For example, ADI tags can + not be set on read-only mappings. + + + +ADI related traps +----------------- + +With ADI enabled, following new traps may occur: + +Disrupting memory corruption + + When a store accesses a memory localtion that has TTE.mcd=1, + the task is running with ADI enabled (PSTATE.mcde=1), and the ADI + tag in the address used (bits 63:60) does not match the tag set on + the corresponding cacheline, a memory corruption trap occurs. By + default, it is a disrupting trap and is sent to the hypervisor + first. Hypervisor creates a sun4v error report and sends a + resumable error (TT=0x7e) trap to the kernel. The kernel sends + a SIGSEGV to the task that resulted in this trap with the following + info: + + siginfo.si_signo = SIGSEGV; + siginfo.errno = 0; + siginfo.si_code = SEGV_ADIDERR; + siginfo.si_addr = addr; /* PC where first mismatch occurred */ + siginfo.si_trapno = 0; + + +Precise memory corruption + + When a store accesses a memory location that has TTE.mcd=1, + the task is running with ADI enabled (PSTATE.mcde=1), and the ADI + tag in the address used (bits 63:60) does not match the tag set on + the corresponding cacheline, a memory corruption trap occurs. If + MCD precise exception is enabled (MCDPERR=1), a precise + exception is sent to the kernel with TT=0x1a. The kernel sends + a SIGSEGV to the task that resulted in this trap with the following + info: + + siginfo.si_signo = SIGSEGV; + siginfo.errno = 0; + siginfo.si_code = SEGV_ADIPERR; + siginfo.si_addr = addr; /* address that caused trap */ + siginfo.si_trapno = 0; + + NOTE: ADI tag mismatch on a load always results in precise trap. + + +MCD disabled + + When a task has not enabled ADI and attempts to set ADI version + on a memory address, processor sends an MCD disabled trap. This + trap is handled by hypervisor first and the hypervisor vectors this + trap through to the kernel as Data Access Exception trap with + fault type set to 0xa (invalid ASI). When this occurs, the kernel + sends the task SIGSEGV signal with following info: + + siginfo.si_signo = SIGSEGV; + siginfo.errno = 0; + siginfo.si_code = SEGV_ACCADI; + siginfo.si_addr = addr; /* address that caused trap */ + siginfo.si_trapno = 0; + + +Sample program to use ADI +------------------------- + +Following sample program is meant to illustrate how to use the ADI +functionality. + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef AT_ADI_BLKSZ +#define AT_ADI_BLKSZ 48 +#endif +#ifndef AT_ADI_NBITS +#define AT_ADI_NBITS 49 +#endif + +#ifndef PROT_ADI +#define PROT_ADI 0x10 +#endif + +#define BUFFER_SIZE 32*1024*1024UL + +main(int argc, char* argv[], char* envp[]) +{ + unsigned long i, mcde, adi_blksz, adi_nbits; + char *shmaddr, *tmp_addr, *end, *veraddr, *clraddr; + int shmid, version; + Elf64_auxv_t *auxv; + + adi_blksz = 0; + + while(*envp++ != NULL); + for (auxv = (Elf64_auxv_t *)envp; auxv->a_type != AT_NULL; auxv++) { + switch (auxv->a_type) { + case AT_ADI_BLKSZ: + adi_blksz = auxv->a_un.a_val; + break; + case AT_ADI_NBITS: + adi_nbits = auxv->a_un.a_val; + break; + } + } + if (adi_blksz == 0) { + fprintf(stderr, "Oops! ADI is not supported\n"); + exit(1); + } + + printf("ADI capabilities:\n"); + printf("\tBlock size = %ld\n", adi_blksz); + printf("\tNumber of bits = %ld\n", adi_nbits); + + if ((shmid = shmget(2, BUFFER_SIZE, + IPC_CREAT | SHM_R | SHM_W)) < 0) { + perror("shmget failed"); + exit(1); + } + + shmaddr = shmat(shmid, NULL, 0); + if (shmaddr == (char *)-1) { + perror("shm attach failed"); + shmctl(shmid, IPC_RMID, NULL); + exit(1); + } + + if (mprotect(shmaddr, BUFFER_SIZE, PROT_READ|PROT_WRITE|PROT_ADI)) { + perror("mprotect failed"); + goto err_out; + } + + /* Set the ADI version tag on the shm segment + */ + version = 10; + tmp_addr = shmaddr; + end = shmaddr + BUFFER_SIZE; + while (tmp_addr < end) { + asm volatile( + "stxa %1, [%0]0x90\n\t" + : + : "r" (tmp_addr), "r" (version)); + tmp_addr += adi_blksz; + } + asm volatile("membar #Sync\n\t"); + + /* Create a versioned address from the normal address by placing + * version tag in the upper adi_nbits bits + */ + tmp_addr = (void *) ((unsigned long)shmaddr << adi_nbits); + tmp_addr = (void *) ((unsigned long)tmp_addr >> adi_nbits); + veraddr = (void *) (((unsigned long)version << (64-adi_nbits)) + | (unsigned long)tmp_addr); + + printf("Starting the writes:\n"); + for (i = 0; i < BUFFER_SIZE; i++) { + veraddr[i] = (char)(i); + if (!(i % (1024 * 1024))) + printf("."); + } + printf("\n"); + + printf("Verifying data..."); + fflush(stdout); + for (i = 0; i < BUFFER_SIZE; i++) + if (veraddr[i] != (char)i) + printf("\nIndex %lu mismatched\n", i); + printf("Done.\n"); + + /* Disable ADI and clean up + */ + if (mprotect(shmaddr, BUFFER_SIZE, PROT_READ|PROT_WRITE)) { + perror("mprotect failed"); + goto err_out; + } + + if (shmdt((const void *)shmaddr) != 0) + perror("Detach failure"); + shmctl(shmid, IPC_RMID, NULL); + + exit(0); + +err_out: + if (shmdt((const void *)shmaddr) != 0) + perror("Detach failure"); + shmctl(shmid, IPC_RMID, NULL); + exit(1); +} diff --git a/arch/sparc/include/asm/mman.h b/arch/sparc/include/asm/mman.h index 7e9472143f9b..f94532f25db1 100644 --- a/arch/sparc/include/asm/mman.h +++ b/arch/sparc/include/asm/mman.h @@ -7,5 +7,87 @@ #ifndef __ASSEMBLY__ #define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len) int sparc_mmap_check(unsigned long addr, unsigned long len); -#endif + +#ifdef CONFIG_SPARC64 +#include + +static inline void ipi_set_tstate_mcde(void *arg) +{ + struct mm_struct *mm = arg; + + /* Set TSTATE_MCDE for the task using address map that ADI has been + * enabled on if the task is running. If not, it will be set + * automatically at the next context switch + */ + if (current->mm == mm) { + struct pt_regs *regs; + + regs = task_pt_regs(current); + regs->tstate |= TSTATE_MCDE; + } +} + +#define arch_calc_vm_prot_bits(prot, pkey) sparc_calc_vm_prot_bits(prot) +static inline unsigned long sparc_calc_vm_prot_bits(unsigned long prot) +{ + if (adi_capable() && (prot & PROT_ADI)) { + struct pt_regs *regs; + + if (!current->mm->context.adi) { + regs = task_pt_regs(current); + regs->tstate |= TSTATE_MCDE; + current->mm->context.adi = true; + on_each_cpu_mask(mm_cpumask(current->mm), + ipi_set_tstate_mcde, current->mm, 0); + } + return VM_SPARC_ADI; + } else { + return 0; + } +} + +#define arch_vm_get_page_prot(vm_flags) sparc_vm_get_page_prot(vm_flags) +static inline pgprot_t sparc_vm_get_page_prot(unsigned long vm_flags) +{ + return (vm_flags & VM_SPARC_ADI) ? __pgprot(_PAGE_MCD_4V) : __pgprot(0); +} + +#define arch_validate_prot(prot, addr) sparc_validate_prot(prot, addr) +static inline int sparc_validate_prot(unsigned long prot, unsigned long addr) +{ + if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_ADI)) + return 0; + if (prot & PROT_ADI) { + if (!adi_capable()) + return 0; + + if (addr) { + struct vm_area_struct *vma; + + vma = find_vma(current->mm, addr); + if (vma) { + /* ADI can not be enabled on PFN + * mapped pages + */ + if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP)) + return 0; + + /* Mergeable pages can become unmergeable + * if ADI is enabled on them even if they + * have identical data on them. This can be + * because ADI enabled pages with identical + * data may still not have identical ADI + * tags on them. Disallow ADI on mergeable + * pages. + */ + if (vma->vm_flags & VM_MERGEABLE) + return 0; + } + } + } + return 1; +} +#endif /* CONFIG_SPARC64 */ + +#endif /* __ASSEMBLY__ */ #endif /* __SPARC_MMAN_H__ */ diff --git a/arch/sparc/include/asm/mmu_64.h b/arch/sparc/include/asm/mmu_64.h index ad4fb93508ba..7e2704c770e9 100644 --- a/arch/sparc/include/asm/mmu_64.h +++ b/arch/sparc/include/asm/mmu_64.h @@ -90,6 +90,20 @@ struct tsb_config { #define MM_NUM_TSBS 1 #endif +/* ADI tags are stored when a page is swapped out and the storage for + * tags is allocated dynamically. There is a tag storage descriptor + * associated with each set of tag storage pages. Tag storage descriptors + * are allocated dynamically. Since kernel will allocate a full page for + * each tag storage descriptor, we can store up to + * PAGE_SIZE/sizeof(tag storage descriptor) descriptors on that page. + */ +typedef struct { + unsigned long start; /* Start address for this tag storage */ + unsigned long end; /* Last address for tag storage */ + unsigned char *tags; /* Where the tags are */ + unsigned long tag_users; /* number of references to descriptor */ +} tag_storage_desc_t; + typedef struct { spinlock_t lock; unsigned long sparc64_ctx_val; @@ -98,6 +112,9 @@ typedef struct { struct tsb_config tsb_block[MM_NUM_TSBS]; struct hv_tsb_descr tsb_descr[MM_NUM_TSBS]; void *vdso; + bool adi; + tag_storage_desc_t *tag_store; + spinlock_t tag_lock; } mm_context_t; #endif /* !__ASSEMBLY__ */ diff --git a/arch/sparc/include/asm/mmu_context_64.h b/arch/sparc/include/asm/mmu_context_64.h index b361702ef52a..312fcee8df2b 100644 --- a/arch/sparc/include/asm/mmu_context_64.h +++ b/arch/sparc/include/asm/mmu_context_64.h @@ -9,8 +9,10 @@ #include #include #include +#include #include +#include #include #include @@ -136,6 +138,55 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str #define deactivate_mm(tsk,mm) do { } while (0) #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, NULL) + +#define __HAVE_ARCH_START_CONTEXT_SWITCH +static inline void arch_start_context_switch(struct task_struct *prev) +{ + /* Save the current state of MCDPER register for the process + * we are switching from + */ + if (adi_capable()) { + register unsigned long tmp_mcdper; + + __asm__ __volatile__( + ".word 0x83438000\n\t" /* rd %mcdper, %g1 */ + "mov %%g1, %0\n\t" + : "=r" (tmp_mcdper) + : + : "g1"); + if (tmp_mcdper) + set_tsk_thread_flag(prev, TIF_MCDPER); + else + clear_tsk_thread_flag(prev, TIF_MCDPER); + } +} + +#define finish_arch_post_lock_switch finish_arch_post_lock_switch +static inline void finish_arch_post_lock_switch(void) +{ + /* Restore the state of MCDPER register for the new process + * just switched to. + */ + if (adi_capable()) { + register unsigned long tmp_mcdper; + + tmp_mcdper = test_thread_flag(TIF_MCDPER); + __asm__ __volatile__( + "mov %0, %%g1\n\t" + ".word 0x9d800001\n\t" /* wr %g0, %g1, %mcdper" */ + ".word 0xaf902001\n\t" /* wrpr %g0, 1, %pmcdper */ + : + : "ir" (tmp_mcdper) + : "g1"); + if (current && current->mm && current->mm->context.adi) { + struct pt_regs *regs; + + regs = task_pt_regs(current); + regs->tstate |= TSTATE_MCDE; + } + } +} + #endif /* !(__ASSEMBLY__) */ #endif /* !(__SPARC64_MMU_CONTEXT_H) */ diff --git a/arch/sparc/include/asm/page_64.h b/arch/sparc/include/asm/page_64.h index c28379b1b0fc..e80f2d5bf62f 100644 --- a/arch/sparc/include/asm/page_64.h +++ b/arch/sparc/include/asm/page_64.h @@ -48,6 +48,12 @@ struct page; void clear_user_page(void *addr, unsigned long vaddr, struct page *page); #define copy_page(X,Y) memcpy((void *)(X), (void *)(Y), PAGE_SIZE) void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *topage); +#define __HAVE_ARCH_COPY_USER_HIGHPAGE +struct vm_area_struct; +void copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr, struct vm_area_struct *vma); +#define __HAVE_ARCH_COPY_HIGHPAGE +void copy_highpage(struct page *to, struct page *from); /* Unlike sparc32, sparc64's parameter passing API is more * sane in that structures which as small enough are passed diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h index 619332a44402..44d6ac47e035 100644 --- a/arch/sparc/include/asm/pgtable_64.h +++ b/arch/sparc/include/asm/pgtable_64.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -606,6 +607,18 @@ static inline pte_t pte_mkspecial(pte_t pte) return pte; } +static inline pte_t pte_mkmcd(pte_t pte) +{ + pte_val(pte) |= _PAGE_MCD_4V; + return pte; +} + +static inline pte_t pte_mknotmcd(pte_t pte) +{ + pte_val(pte) &= ~_PAGE_MCD_4V; + return pte; +} + static inline unsigned long pte_young(pte_t pte) { unsigned long mask; @@ -1048,6 +1061,39 @@ int page_in_phys_avail(unsigned long paddr); int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, unsigned long, pgprot_t); +void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma, + unsigned long addr, pte_t pte); + +int adi_save_tags(struct mm_struct *mm, struct vm_area_struct *vma, + unsigned long addr, pte_t oldpte); + +#define __HAVE_ARCH_DO_SWAP_PAGE +static inline void arch_do_swap_page(struct mm_struct *mm, + struct vm_area_struct *vma, + unsigned long addr, + pte_t pte, pte_t oldpte) +{ + /* If this is a new page being mapped in, there can be no + * ADI tags stored away for this page. Skip looking for + * stored tags + */ + if (pte_none(oldpte)) + return; + + if (adi_state.enabled && (pte_val(pte) & _PAGE_MCD_4V)) + adi_restore_tags(mm, vma, addr, pte); +} + +#define __HAVE_ARCH_UNMAP_ONE +static inline int arch_unmap_one(struct mm_struct *mm, + struct vm_area_struct *vma, + unsigned long addr, pte_t oldpte) +{ + if (adi_state.enabled && (pte_val(oldpte) & _PAGE_MCD_4V)) + return adi_save_tags(mm, vma, addr, oldpte); + return 0; +} + static inline int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot) diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h index f7e7b0baec9f..7fb676360928 100644 --- a/arch/sparc/include/asm/thread_info_64.h +++ b/arch/sparc/include/asm/thread_info_64.h @@ -188,7 +188,7 @@ register struct thread_info *current_thread_info_reg asm("g6"); * in using in assembly, else we can't use the mask as * an immediate value in instructions such as andcc. */ -/* flag bit 12 is available */ +#define TIF_MCDPER 12 /* Precise MCD exception */ #define TIF_MEMDIE 13 /* is terminating due to OOM killer */ #define TIF_POLLING_NRFLAG 14 diff --git a/arch/sparc/include/asm/trap_block.h b/arch/sparc/include/asm/trap_block.h index 6a4c8652ad67..0f6d0c4f6683 100644 --- a/arch/sparc/include/asm/trap_block.h +++ b/arch/sparc/include/asm/trap_block.h @@ -76,6 +76,8 @@ extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch, __sun4v_1insn_patch_end; extern struct sun4v_1insn_patch_entry __fast_win_ctrl_1insn_patch, __fast_win_ctrl_1insn_patch_end; +extern struct sun4v_1insn_patch_entry __sun_m7_1insn_patch, + __sun_m7_1insn_patch_end; struct sun4v_2insn_patch_entry { unsigned int addr; diff --git a/arch/sparc/include/uapi/asm/mman.h b/arch/sparc/include/uapi/asm/mman.h index 715a2c927e79..f6f99ec65bb3 100644 --- a/arch/sparc/include/uapi/asm/mman.h +++ b/arch/sparc/include/uapi/asm/mman.h @@ -6,6 +6,8 @@ /* SunOS'ified... */ +#define PROT_ADI 0x10 /* ADI enabled */ + #define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */ #define MAP_NORESERVE 0x40 /* don't reserve swap pages */ #define MAP_INHERIT 0x80 /* SunOS doesn't do this, but... */ diff --git a/arch/sparc/kernel/adi_64.c b/arch/sparc/kernel/adi_64.c index 8fb72585d9f1..d0a2ac975b42 100644 --- a/arch/sparc/kernel/adi_64.c +++ b/arch/sparc/kernel/adi_64.c @@ -8,10 +8,24 @@ * This work is licensed under the terms of the GNU GPL, version 2. */ #include +#include +#include #include #include +#include +#include + +/* Each page of storage for ADI tags can accommodate tags for 128 + * pages. When ADI enabled pages are being swapped out, it would be + * prudent to allocate at least enough tag storage space to accommodate + * SWAPFILE_CLUSTER number of pages. Allocate enough tag storage to + * store tags for four SWAPFILE_CLUSTER pages to reduce need for + * further allocations for same vma. + */ +#define TAG_STORAGE_PAGES 8 struct adi_config adi_state; +EXPORT_SYMBOL(adi_state); /* mdesc_adi_init() : Parse machine description provided by the * hypervisor to detect ADI capabilities @@ -84,6 +98,19 @@ void __init mdesc_adi_init(void) goto adi_not_found; adi_state.caps.ue_on_adi = *val; + /* Some of the code to support swapping ADI tags is written + * assumption that two ADI tags can fit inside one byte. If + * this assumption is broken by a future architecture change, + * that code will have to be revisited. If that were to happen, + * disable ADI support so we do not get unpredictable results + * with programs trying to use ADI and their pages getting + * swapped out + */ + if (adi_state.caps.nbits > 4) { + pr_warn("WARNING: ADI tag size >4 on this platform. Disabling AADI support\n"); + adi_state.enabled = false; + } + mdesc_release(hp); return; @@ -94,3 +121,277 @@ adi_not_found: if (hp) mdesc_release(hp); } + +tag_storage_desc_t *find_tag_store(struct mm_struct *mm, + struct vm_area_struct *vma, + unsigned long addr) +{ + tag_storage_desc_t *tag_desc = NULL; + unsigned long i, max_desc, flags; + + /* Check if this vma already has tag storage descriptor + * allocated for it. + */ + max_desc = PAGE_SIZE/sizeof(tag_storage_desc_t); + if (mm->context.tag_store) { + tag_desc = mm->context.tag_store; + spin_lock_irqsave(&mm->context.tag_lock, flags); + for (i = 0; i < max_desc; i++) { + if ((addr >= tag_desc->start) && + ((addr + PAGE_SIZE - 1) <= tag_desc->end)) + break; + tag_desc++; + } + spin_unlock_irqrestore(&mm->context.tag_lock, flags); + + /* If no matching entries were found, this must be a + * freshly allocated page + */ + if (i >= max_desc) + tag_desc = NULL; + } + + return tag_desc; +} + +tag_storage_desc_t *alloc_tag_store(struct mm_struct *mm, + struct vm_area_struct *vma, + unsigned long addr) +{ + unsigned char *tags; + unsigned long i, size, max_desc, flags; + tag_storage_desc_t *tag_desc, *open_desc; + unsigned long end_addr, hole_start, hole_end; + + max_desc = PAGE_SIZE/sizeof(tag_storage_desc_t); + open_desc = NULL; + hole_start = 0; + hole_end = ULONG_MAX; + end_addr = addr + PAGE_SIZE - 1; + + /* Check if this vma already has tag storage descriptor + * allocated for it. + */ + spin_lock_irqsave(&mm->context.tag_lock, flags); + if (mm->context.tag_store) { + tag_desc = mm->context.tag_store; + + /* Look for a matching entry for this address. While doing + * that, look for the first open slot as well and find + * the hole in already allocated range where this request + * will fit in. + */ + for (i = 0; i < max_desc; i++) { + if (tag_desc->tag_users == 0) { + if (open_desc == NULL) + open_desc = tag_desc; + } else { + if ((addr >= tag_desc->start) && + (tag_desc->end >= (addr + PAGE_SIZE - 1))) { + tag_desc->tag_users++; + goto out; + } + } + if ((tag_desc->start > end_addr) && + (tag_desc->start < hole_end)) + hole_end = tag_desc->start; + if ((tag_desc->end < addr) && + (tag_desc->end > hole_start)) + hole_start = tag_desc->end; + tag_desc++; + } + + } else { + size = sizeof(tag_storage_desc_t)*max_desc; + mm->context.tag_store = kzalloc(size, GFP_NOWAIT|__GFP_NOWARN); + if (mm->context.tag_store == NULL) { + tag_desc = NULL; + goto out; + } + tag_desc = mm->context.tag_store; + for (i = 0; i < max_desc; i++, tag_desc++) + tag_desc->tag_users = 0; + open_desc = mm->context.tag_store; + i = 0; + } + + /* Check if we ran out of tag storage descriptors */ + if (open_desc == NULL) { + tag_desc = NULL; + goto out; + } + + /* Mark this tag descriptor slot in use and then initialize it */ + tag_desc = open_desc; + tag_desc->tag_users = 1; + + /* Tag storage has not been allocated for this vma and space + * is available in tag storage descriptor. Since this page is + * being swapped out, there is high probability subsequent pages + * in the VMA will be swapped out as well. Allocate pages to + * store tags for as many pages in this vma as possible but not + * more than TAG_STORAGE_PAGES. Each byte in tag space holds + * two ADI tags since each ADI tag is 4 bits. Each ADI tag + * covers adi_blksize() worth of addresses. Check if the hole is + * big enough to accommodate full address range for using + * TAG_STORAGE_PAGES number of tag pages. + */ + size = TAG_STORAGE_PAGES * PAGE_SIZE; + end_addr = addr + (size*2*adi_blksize()) - 1; + /* Check for overflow. If overflow occurs, allocate only one page */ + if (end_addr < addr) { + size = PAGE_SIZE; + end_addr = addr + (size*2*adi_blksize()) - 1; + /* If overflow happens with the minimum tag storage + * allocation as well, adjust ending address for this + * tag storage. + */ + if (end_addr < addr) + end_addr = ULONG_MAX; + } + if (hole_end < end_addr) { + /* Available hole is too small on the upper end of + * address. Can we expand the range towards the lower + * address and maximize use of this slot? + */ + unsigned long tmp_addr; + + end_addr = hole_end - 1; + tmp_addr = end_addr - (size*2*adi_blksize()) + 1; + /* Check for underflow. If underflow occurs, allocate + * only one page for storing ADI tags + */ + if (tmp_addr > addr) { + size = PAGE_SIZE; + tmp_addr = end_addr - (size*2*adi_blksize()) - 1; + /* If underflow happens with the minimum tag storage + * allocation as well, adjust starting address for + * this tag storage. + */ + if (tmp_addr > addr) + tmp_addr = 0; + } + if (tmp_addr < hole_start) { + /* Available hole is restricted on lower address + * end as well + */ + tmp_addr = hole_start + 1; + } + addr = tmp_addr; + size = (end_addr + 1 - addr)/(2*adi_blksize()); + size = (size + (PAGE_SIZE-adi_blksize()))/PAGE_SIZE; + size = size * PAGE_SIZE; + } + tags = kzalloc(size, GFP_NOWAIT|__GFP_NOWARN); + if (tags == NULL) { + tag_desc->tag_users = 0; + tag_desc = NULL; + goto out; + } + tag_desc->start = addr; + tag_desc->tags = tags; + tag_desc->end = end_addr; + +out: + spin_unlock_irqrestore(&mm->context.tag_lock, flags); + return tag_desc; +} + +void del_tag_store(tag_storage_desc_t *tag_desc, struct mm_struct *mm) +{ + unsigned long flags; + unsigned char *tags = NULL; + + spin_lock_irqsave(&mm->context.tag_lock, flags); + tag_desc->tag_users--; + if (tag_desc->tag_users == 0) { + tag_desc->start = tag_desc->end = 0; + /* Do not free up the tag storage space allocated + * by the first descriptor. This is persistent + * emergency tag storage space for the task. + */ + if (tag_desc != mm->context.tag_store) { + tags = tag_desc->tags; + tag_desc->tags = NULL; + } + } + spin_unlock_irqrestore(&mm->context.tag_lock, flags); + kfree(tags); +} + +#define tag_start(addr, tag_desc) \ + ((tag_desc)->tags + ((addr - (tag_desc)->start)/(2*adi_blksize()))) + +/* Retrieve any saved ADI tags for the page being swapped back in and + * restore these tags to the newly allocated physical page. + */ +void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma, + unsigned long addr, pte_t pte) +{ + unsigned char *tag; + tag_storage_desc_t *tag_desc; + unsigned long paddr, tmp, version1, version2; + + /* Check if the swapped out page has an ADI version + * saved. If yes, restore version tag to the newly + * allocated page. + */ + tag_desc = find_tag_store(mm, vma, addr); + if (tag_desc == NULL) + return; + + tag = tag_start(addr, tag_desc); + paddr = pte_val(pte) & _PAGE_PADDR_4V; + for (tmp = paddr; tmp < (paddr+PAGE_SIZE); tmp += adi_blksize()) { + version1 = (*tag) >> 4; + version2 = (*tag) & 0x0f; + *tag++ = 0; + asm volatile("stxa %0, [%1] %2\n\t" + : + : "r" (version1), "r" (tmp), + "i" (ASI_MCD_REAL)); + tmp += adi_blksize(); + asm volatile("stxa %0, [%1] %2\n\t" + : + : "r" (version2), "r" (tmp), + "i" (ASI_MCD_REAL)); + } + asm volatile("membar #Sync\n\t"); + + /* Check and mark this tag space for release later if + * the swapped in page was the last user of tag space + */ + del_tag_store(tag_desc, mm); +} + +/* A page is about to be swapped out. Save any ADI tags associated with + * this physical page so they can be restored later when the page is swapped + * back in. + */ +int adi_save_tags(struct mm_struct *mm, struct vm_area_struct *vma, + unsigned long addr, pte_t oldpte) +{ + unsigned char *tag; + tag_storage_desc_t *tag_desc; + unsigned long version1, version2, paddr, tmp; + + tag_desc = alloc_tag_store(mm, vma, addr); + if (tag_desc == NULL) + return -1; + + tag = tag_start(addr, tag_desc); + paddr = pte_val(oldpte) & _PAGE_PADDR_4V; + for (tmp = paddr; tmp < (paddr+PAGE_SIZE); tmp += adi_blksize()) { + asm volatile("ldxa [%1] %2, %0\n\t" + : "=r" (version1) + : "r" (tmp), "i" (ASI_MCD_REAL)); + tmp += adi_blksize(); + asm volatile("ldxa [%1] %2, %0\n\t" + : "=r" (version2) + : "r" (tmp), "i" (ASI_MCD_REAL)); + *tag = (version1 << 4) | version2; + tag++; + } + + return 0; +} diff --git a/arch/sparc/kernel/etrap_64.S b/arch/sparc/kernel/etrap_64.S index 5c77a2e0e991..08cc41f64725 100644 --- a/arch/sparc/kernel/etrap_64.S +++ b/arch/sparc/kernel/etrap_64.S @@ -151,7 +151,32 @@ etrap_save: save %g2, -STACK_BIAS, %sp stx %g6, [%sp + PTREGS_OFF + PT_V9_G6] stx %g7, [%sp + PTREGS_OFF + PT_V9_G7] or %l7, %l0, %l7 - sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0 +661: sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0 + /* If userspace is using ADI, it could potentially pass + * a pointer with version tag embedded in it. To maintain + * the ADI security, we must enable PSTATE.mcde. Userspace + * would have already set TTE.mcd in an earlier call to + * kernel and set the version tag for the address being + * dereferenced. Setting PSTATE.mcde would ensure any + * access to userspace data through a system call honors + * ADI and does not allow a rogue app to bypass ADI by + * using system calls. Setting PSTATE.mcde only affects + * accesses to virtual addresses that have TTE.mcd set. + * Set PMCDPER to ensure any exceptions caused by ADI + * version tag mismatch are exposed before system call + * returns to userspace. Setting PMCDPER affects only + * writes to virtual addresses that have TTE.mcd set and + * have a version tag set as well. + */ + .section .sun_m7_1insn_patch, "ax" + .word 661b + sethi %hi(TSTATE_TSO | TSTATE_PEF | TSTATE_MCDE), %l0 + .previous +661: nop + .section .sun_m7_1insn_patch, "ax" + .word 661b + .word 0xaf902001 /* wrpr %g0, 1, %pmcdper */ + .previous or %l7, %l0, %l7 wrpr %l2, %tnpc wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c index 318efd784a0b..454a8af28f13 100644 --- a/arch/sparc/kernel/process_64.c +++ b/arch/sparc/kernel/process_64.c @@ -670,6 +670,31 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, return 0; } +/* TIF_MCDPER in thread info flags for current task is updated lazily upon + * a context switch. Update this flag in current task's thread flags + * before dup so the dup'd task will inherit the current TIF_MCDPER flag. + */ +int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) +{ + if (adi_capable()) { + register unsigned long tmp_mcdper; + + __asm__ __volatile__( + ".word 0x83438000\n\t" /* rd %mcdper, %g1 */ + "mov %%g1, %0\n\t" + : "=r" (tmp_mcdper) + : + : "g1"); + if (tmp_mcdper) + set_thread_flag(TIF_MCDPER); + else + clear_thread_flag(TIF_MCDPER); + } + + *dst = *src; + return 0; +} + typedef struct { union { unsigned int pr_regs[32]; diff --git a/arch/sparc/kernel/rtrap_64.S b/arch/sparc/kernel/rtrap_64.S index 0b21042ab181..f6528884a2c8 100644 --- a/arch/sparc/kernel/rtrap_64.S +++ b/arch/sparc/kernel/rtrap_64.S @@ -25,13 +25,31 @@ .align 32 __handle_preemption: call SCHEDULE_USER - wrpr %g0, RTRAP_PSTATE, %pstate +661: wrpr %g0, RTRAP_PSTATE, %pstate + /* If userspace is using ADI, it could potentially pass + * a pointer with version tag embedded in it. To maintain + * the ADI security, we must re-enable PSTATE.mcde before + * we continue execution in the kernel for another thread. + */ + .section .sun_m7_1insn_patch, "ax" + .word 661b + wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate + .previous ba,pt %xcc, __handle_preemption_continue wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate __handle_user_windows: call fault_in_user_windows - wrpr %g0, RTRAP_PSTATE, %pstate +661: wrpr %g0, RTRAP_PSTATE, %pstate + /* If userspace is using ADI, it could potentially pass + * a pointer with version tag embedded in it. To maintain + * the ADI security, we must re-enable PSTATE.mcde before + * we continue execution in the kernel for another thread. + */ + .section .sun_m7_1insn_patch, "ax" + .word 661b + wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate + .previous ba,pt %xcc, __handle_preemption_continue wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate @@ -48,7 +66,16 @@ __handle_signal: add %sp, PTREGS_OFF, %o0 mov %l0, %o2 call do_notify_resume - wrpr %g0, RTRAP_PSTATE, %pstate +661: wrpr %g0, RTRAP_PSTATE, %pstate + /* If userspace is using ADI, it could potentially pass + * a pointer with version tag embedded in it. To maintain + * the ADI security, we must re-enable PSTATE.mcde before + * we continue execution in the kernel for another thread. + */ + .section .sun_m7_1insn_patch, "ax" + .word 661b + wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate + .previous wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate /* Signal delivery can modify pt_regs tstate, so we must diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c index 34f7a533a74f..7944b3ca216a 100644 --- a/arch/sparc/kernel/setup_64.c +++ b/arch/sparc/kernel/setup_64.c @@ -294,6 +294,8 @@ static void __init sun4v_patch(void) case SUN4V_CHIP_SPARC_M7: case SUN4V_CHIP_SPARC_M8: case SUN4V_CHIP_SPARC_SN: + sun4v_patch_1insn_range(&__sun_m7_1insn_patch, + &__sun_m7_1insn_patch_end); sun_m7_patch_2insn_range(&__sun_m7_2insn_patch, &__sun_m7_2insn_patch_end); break; diff --git a/arch/sparc/kernel/urtt_fill.S b/arch/sparc/kernel/urtt_fill.S index 44183aa59168..e4cee7be5cd0 100644 --- a/arch/sparc/kernel/urtt_fill.S +++ b/arch/sparc/kernel/urtt_fill.S @@ -50,7 +50,12 @@ user_rtt_fill_fixup_common: SET_GL(0) .previous - wrpr %g0, RTRAP_PSTATE, %pstate +661: wrpr %g0, RTRAP_PSTATE, %pstate + .section .sun_m7_1insn_patch, "ax" + .word 661b + /* Re-enable PSTATE.mcde to maintain ADI security */ + wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate + .previous mov %l1, %g6 ldx [%g6 + TI_TASK], %g4 diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S index 5a2344574f39..61afd787bd0c 100644 --- a/arch/sparc/kernel/vmlinux.lds.S +++ b/arch/sparc/kernel/vmlinux.lds.S @@ -145,6 +145,11 @@ SECTIONS *(.pause_3insn_patch) __pause_3insn_patch_end = .; } + .sun_m7_1insn_patch : { + __sun_m7_1insn_patch = .; + *(.sun_m7_1insn_patch) + __sun_m7_1insn_patch_end = .; + } .sun_m7_2insn_patch : { __sun_m7_2insn_patch = .; *(.sun_m7_2insn_patch) diff --git a/arch/sparc/mm/gup.c b/arch/sparc/mm/gup.c index 5335ba3c850e..357b6047653a 100644 --- a/arch/sparc/mm/gup.c +++ b/arch/sparc/mm/gup.c @@ -12,6 +12,7 @@ #include #include #include +#include /* * The performance critical leaf functions are made noinline otherwise gcc @@ -201,6 +202,24 @@ int __get_user_pages_fast(unsigned long start, int nr_pages, int write, pgd_t *pgdp; int nr = 0; +#ifdef CONFIG_SPARC64 + if (adi_capable()) { + long addr = start; + + /* If userspace has passed a versioned address, kernel + * will not find it in the VMAs since it does not store + * the version tags in the list of VMAs. Storing version + * tags in list of VMAs is impractical since they can be + * changed any time from userspace without dropping into + * kernel. Any address search in VMAs will be done with + * non-versioned addresses. Ensure the ADI version bits + * are dropped here by sign extending the last bit before + * ADI bits. IOMMU does not implement version tags. + */ + addr = (addr << (long)adi_nbits()) >> (long)adi_nbits(); + start = addr; + } +#endif start &= PAGE_MASK; addr = start; len = (unsigned long) nr_pages << PAGE_SHIFT; @@ -231,6 +250,24 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, pgd_t *pgdp; int nr = 0; +#ifdef CONFIG_SPARC64 + if (adi_capable()) { + long addr = start; + + /* If userspace has passed a versioned address, kernel + * will not find it in the VMAs since it does not store + * the version tags in the list of VMAs. Storing version + * tags in list of VMAs is impractical since they can be + * changed any time from userspace without dropping into + * kernel. Any address search in VMAs will be done with + * non-versioned addresses. Ensure the ADI version bits + * are dropped here by sign extending the last bit before + * ADI bits. IOMMU does not implements version tags, + */ + addr = (addr << (long)adi_nbits()) >> (long)adi_nbits(); + start = addr; + } +#endif start &= PAGE_MASK; addr = start; len = (unsigned long) nr_pages << PAGE_SHIFT; diff --git a/arch/sparc/mm/hugetlbpage.c b/arch/sparc/mm/hugetlbpage.c index 0112d6942288..f78793a06bbd 100644 --- a/arch/sparc/mm/hugetlbpage.c +++ b/arch/sparc/mm/hugetlbpage.c @@ -182,8 +182,20 @@ pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, struct page *page, int writeable) { unsigned int shift = huge_page_shift(hstate_vma(vma)); + pte_t pte; - return hugepage_shift_to_tte(entry, shift); + pte = hugepage_shift_to_tte(entry, shift); + +#ifdef CONFIG_SPARC64 + /* If this vma has ADI enabled on it, turn on TTE.mcd + */ + if (vma->vm_flags & VM_SPARC_ADI) + return pte_mkmcd(pte); + else + return pte_mknotmcd(pte); +#else + return pte; +#endif } static unsigned int sun4v_huge_tte_to_shift(pte_t entry) diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 995f9490334d..cb9ebac6663f 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -3160,3 +3160,72 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) do_flush_tlb_kernel_range(start, end); } } + +void copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr, struct vm_area_struct *vma) +{ + char *vfrom, *vto; + + vfrom = kmap_atomic(from); + vto = kmap_atomic(to); + copy_user_page(vto, vfrom, vaddr, to); + kunmap_atomic(vto); + kunmap_atomic(vfrom); + + /* If this page has ADI enabled, copy over any ADI tags + * as well + */ + if (vma->vm_flags & VM_SPARC_ADI) { + unsigned long pfrom, pto, i, adi_tag; + + pfrom = page_to_phys(from); + pto = page_to_phys(to); + + for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { + asm volatile("ldxa [%1] %2, %0\n\t" + : "=r" (adi_tag) + : "r" (i), "i" (ASI_MCD_REAL)); + asm volatile("stxa %0, [%1] %2\n\t" + : + : "r" (adi_tag), "r" (pto), + "i" (ASI_MCD_REAL)); + pto += adi_blksize(); + } + asm volatile("membar #Sync\n\t"); + } +} +EXPORT_SYMBOL(copy_user_highpage); + +void copy_highpage(struct page *to, struct page *from) +{ + char *vfrom, *vto; + + vfrom = kmap_atomic(from); + vto = kmap_atomic(to); + copy_page(vto, vfrom); + kunmap_atomic(vto); + kunmap_atomic(vfrom); + + /* If this platform is ADI enabled, copy any ADI tags + * as well + */ + if (adi_capable()) { + unsigned long pfrom, pto, i, adi_tag; + + pfrom = page_to_phys(from); + pto = page_to_phys(to); + + for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { + asm volatile("ldxa [%1] %2, %0\n\t" + : "=r" (adi_tag) + : "r" (i), "i" (ASI_MCD_REAL)); + asm volatile("stxa %0, [%1] %2\n\t" + : + : "r" (adi_tag), "r" (pto), + "i" (ASI_MCD_REAL)); + pto += adi_blksize(); + } + asm volatile("membar #Sync\n\t"); + } +} +EXPORT_SYMBOL(copy_highpage); diff --git a/arch/sparc/mm/tsb.c b/arch/sparc/mm/tsb.c index 75a04c1a2383..f5edc28aa3a5 100644 --- a/arch/sparc/mm/tsb.c +++ b/arch/sparc/mm/tsb.c @@ -546,6 +546,9 @@ int init_new_context(struct task_struct *tsk, struct mm_struct *mm) mm->context.sparc64_ctx_val = 0UL; + mm->context.tag_store = NULL; + spin_lock_init(&mm->context.tag_lock); + #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) /* We reset them to zero because the fork() page copying * will re-increment the counters as the parent PTEs are @@ -611,4 +614,22 @@ void destroy_context(struct mm_struct *mm) } spin_unlock_irqrestore(&ctx_alloc_lock, flags); + + /* If ADI tag storage was allocated for this task, free it */ + if (mm->context.tag_store) { + tag_storage_desc_t *tag_desc; + unsigned long max_desc; + unsigned char *tags; + + tag_desc = mm->context.tag_store; + max_desc = PAGE_SIZE/sizeof(tag_storage_desc_t); + for (i = 0; i < max_desc; i++) { + tags = tag_desc->tags; + tag_desc->tags = NULL; + kfree(tags); + tag_desc++; + } + kfree(mm->context.tag_store); + mm->context.tag_store = NULL; + } } diff --git a/include/linux/mm.h b/include/linux/mm.h index ae806dbc63ee..32fe6919a11b 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -245,6 +245,9 @@ extern unsigned int kobjsize(const void *objp); # define VM_GROWSUP VM_ARCH_1 #elif defined(CONFIG_IA64) # define VM_GROWSUP VM_ARCH_1 +#elif defined(CONFIG_SPARC64) +# define VM_SPARC_ADI VM_ARCH_1 /* Uses ADI tag for access control */ +# define VM_ARCH_CLEAR VM_SPARC_ADI #elif !defined(CONFIG_MMU) # define VM_MAPPED_COPY VM_ARCH_1 /* T if mapped copy of data (nommu mmap) */ #endif diff --git a/mm/ksm.c b/mm/ksm.c index 293721f5da70..adb5f991da8e 100644 --- a/mm/ksm.c +++ b/mm/ksm.c @@ -2369,6 +2369,10 @@ int ksm_madvise(struct vm_area_struct *vma, unsigned long start, if (*vm_flags & VM_SAO) return 0; #endif +#ifdef VM_SPARC_ADI + if (*vm_flags & VM_SPARC_ADI) + return 0; +#endif if (!test_bit(MMF_VM_MERGEABLE, &mm->flags)) { err = __ksm_enter(mm); -- cgit v1.2.3 From f63109f0cb40bca848eef9bf096dfdb7def5e20d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 4 Mar 2018 23:37:22 +0100 Subject: gpio: htc-gpio: Include the right header This driver is a pure GPIO driver and should only include . Drop the include of from the platform data header as well, it serves no purpose. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-htc-egpio.c | 1 + include/linux/platform_data/gpio-htc-egpio.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/gpio/gpio-htc-egpio.c b/drivers/gpio/gpio-htc-egpio.c index 271356effb2e..516383934945 100644 --- a/drivers/gpio/gpio-htc-egpio.c +++ b/drivers/gpio/gpio-htc-egpio.c @@ -18,6 +18,7 @@ #include #include #include +#include struct egpio_chip { int reg_start; diff --git a/include/linux/platform_data/gpio-htc-egpio.h b/include/linux/platform_data/gpio-htc-egpio.h index b7baf1e42c55..9a3e78082883 100644 --- a/include/linux/platform_data/gpio-htc-egpio.h +++ b/include/linux/platform_data/gpio-htc-egpio.h @@ -6,8 +6,6 @@ #ifndef __HTC_EGPIO_H__ #define __HTC_EGPIO_H__ -#include - /* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */ #define HTC_EGPIO_OUTPUT (~0) #define HTC_EGPIO_INPUT 0 -- cgit v1.2.3 From 1c94984396dc7bc40b4f6899674eaa41f29a4f6e Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Thu, 1 Mar 2018 00:19:21 +0100 Subject: vfs: make sure struct filename->iname is word-aligned I noticed that offsetof(struct filename, iname) is actually 28 on 64 bit platforms, so we always pass an unaligned pointer to strncpy_from_user. This is mostly a problem for those 64 bit platforms without HAVE_EFFICIENT_UNALIGNED_ACCESS, but even on x86_64, unaligned accesses carry a penalty. A user-space microbenchmark doing nothing but strncpy_from_user from the same (aligned) source string runs about 5% faster when the destination is aligned. That number increases to 20% when the string is long enough (~32 bytes) that we cross a cache line boundary - that's for example the case for about half the files a "git status" in a kernel tree ends up stat'ing. This won't make any real-life workloads 5%, or even 1%, faster, but path lookup is common enough that cutting even a few cycles should be worthwhile. So ensure we always pass an aligned destination pointer to strncpy_from_user. Instead of explicit padding, simply swap the refcnt and aname members, as suggested by Al Viro. Signed-off-by: Rasmus Villemoes Signed-off-by: Al Viro --- fs/namei.c | 2 ++ include/linux/fs.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/fs/namei.c b/fs/namei.c index 921ae32dbc80..5a66e7ca5d60 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -39,6 +39,7 @@ #include #include #include +#include #include "internal.h" #include "mount.h" @@ -130,6 +131,7 @@ getname_flags(const char __user *filename, int flags, int *empty) struct filename *result; char *kname; int len; + BUILD_BUG_ON(offsetof(struct filename, iname) % sizeof(long) != 0); result = audit_reusename(filename); if (result) diff --git a/include/linux/fs.h b/include/linux/fs.h index 2a815560fda0..d7b2caadb292 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2380,8 +2380,8 @@ struct audit_names; struct filename { const char *name; /* pointer to actual string */ const __user char *uptr; /* original userland pointer */ - struct audit_names *aname; int refcnt; + struct audit_names *aname; const char iname[]; }; -- cgit v1.2.3 From 08fdc8a0138afaf324296a342f32ad26ec465e43 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 3 Oct 2017 18:17:41 +0200 Subject: buffer.c: call thaw_super during emergency thaw There are 2 distinct freezing mechanisms - one operates on block devices and another one directly on super blocks. Both end up with the same result, but thaw of only one of these does not thaw the other. In particular fsfreeze --freeze uses the ioctl variant going to the super block. Since prior to this patch emergency thaw was not doing a relevant thaw, filesystems frozen with this method remained unaffected. The patch is a hack which adds blind unfreezing. In order to keep the super block write-locked the whole time the code is shuffled around and the newly introduced __iterate_supers is employed. Signed-off-by: Mateusz Guzik Signed-off-by: Al Viro --- fs/buffer.c | 25 +------------------------ fs/super.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- include/linux/fs.h | 6 ++++++ 3 files changed, 49 insertions(+), 26 deletions(-) (limited to 'include/linux') diff --git a/fs/buffer.c b/fs/buffer.c index 170df856bdb9..37ea00b265d0 100644 --- a/fs/buffer.c +++ b/fs/buffer.c @@ -523,35 +523,12 @@ repeat: return err; } -static void do_thaw_one(struct super_block *sb, void *unused) +void emergency_thaw_bdev(struct super_block *sb) { while (sb->s_bdev && !thaw_bdev(sb->s_bdev, sb)) printk(KERN_WARNING "Emergency Thaw on %pg\n", sb->s_bdev); } -static void do_thaw_all(struct work_struct *work) -{ - iterate_supers(do_thaw_one, NULL); - kfree(work); - printk(KERN_WARNING "Emergency Thaw complete\n"); -} - -/** - * emergency_thaw_all -- forcibly thaw every frozen filesystem - * - * Used for emergency unfreeze of all filesystems via SysRq - */ -void emergency_thaw_all(void) -{ - struct work_struct *work; - - work = kmalloc(sizeof(*work), GFP_ATOMIC); - if (work) { - INIT_WORK(work, do_thaw_all); - schedule_work(work); - } -} - /** * sync_mapping_buffers - write out & wait upon a mapping's "associated" buffers * @mapping: the mapping which wants those buffers written diff --git a/fs/super.c b/fs/super.c index fd9c02f543eb..83c5c8a60f5f 100644 --- a/fs/super.c +++ b/fs/super.c @@ -36,6 +36,7 @@ #include #include "internal.h" +static int thaw_super_locked(struct super_block *sb); static LIST_HEAD(super_blocks); static DEFINE_SPINLOCK(sb_lock); @@ -934,6 +935,40 @@ void emergency_remount(void) } } +static void do_thaw_all_callback(struct super_block *sb) +{ + down_write(&sb->s_umount); + if (sb->s_root && sb->s_flags & MS_BORN) { + emergency_thaw_bdev(sb); + thaw_super_locked(sb); + } else { + up_write(&sb->s_umount); + } +} + +static void do_thaw_all(struct work_struct *work) +{ + __iterate_supers(do_thaw_all_callback); + kfree(work); + printk(KERN_WARNING "Emergency Thaw complete\n"); +} + +/** + * emergency_thaw_all -- forcibly thaw every frozen filesystem + * + * Used for emergency unfreeze of all filesystems via SysRq + */ +void emergency_thaw_all(void) +{ + struct work_struct *work; + + work = kmalloc(sizeof(*work), GFP_ATOMIC); + if (work) { + INIT_WORK(work, do_thaw_all); + schedule_work(work); + } +} + /* * Unnamed block devices are dummy devices used by virtual * filesystems which don't use real block-devices. -- jrs @@ -1503,11 +1538,10 @@ EXPORT_SYMBOL(freeze_super); * * Unlocks the filesystem and marks it writeable again after freeze_super(). */ -int thaw_super(struct super_block *sb) +static int thaw_super_locked(struct super_block *sb) { int error; - down_write(&sb->s_umount); if (sb->s_writers.frozen != SB_FREEZE_COMPLETE) { up_write(&sb->s_umount); return -EINVAL; @@ -1538,4 +1572,10 @@ out: deactivate_locked_super(sb); return 0; } + +int thaw_super(struct super_block *sb) +{ + down_write(&sb->s_umount); + return thaw_super_locked(sb); +} EXPORT_SYMBOL(thaw_super); diff --git a/include/linux/fs.h b/include/linux/fs.h index 339e73742e73..b864fcb3b5aa 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2428,6 +2428,7 @@ extern int sync_blockdev(struct block_device *bdev); extern void kill_bdev(struct block_device *); extern struct super_block *freeze_bdev(struct block_device *); extern void emergency_thaw_all(void); +extern void emergency_thaw_bdev(struct super_block *sb); extern int thaw_bdev(struct block_device *bdev, struct super_block *sb); extern int fsync_bdev(struct block_device *); @@ -2453,6 +2454,11 @@ static inline int thaw_bdev(struct block_device *bdev, struct super_block *sb) return 0; } +static inline int emergency_thaw_bdev(struct super_block *sb) +{ + return 0; +} + static inline void iterate_bdevs(void (*f)(struct block_device *, void *), void *arg) { } -- cgit v1.2.3 From a84d1169164b274f13b97a23ff235c000efe3b49 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 15 Mar 2018 17:12:40 +0100 Subject: y2038: Introduce struct __kernel_old_timeval Dealing with 'struct timeval' users in the y2038 series is a bit tricky: We have two definitions of timeval that are visible to user space, one comes from glibc (or some other C library), the other comes from linux/time.h. The kernel copy is what we want to be used for a number of structures defined by the kernel itself, e.g. elf_prstatus (used it core dumps), sysinfo and rusage (used in system calls). These generally tend to be used for passing time intervals rather than absolute (epoch-based) times, so they do not suffer from the y2038 overflow. Some of them could be changed to use 64-bit timestamps by creating new system calls, others like the core files cannot easily be changed. An application using these interfaces likely also uses gettimeofday() or other interfaces that use absolute times, and pass 'struct timeval' pointers directly into kernel interfaces, so glibc must redefine their timeval based on a 64-bit time_t when they introduce their y2038-safe interfaces. The only reasonable way forward I see is to remove the 'timeval' definion from the kernel's uapi headers, and change the interfaces that we do not want to (or cannot) duplicate for 64-bit times to use a new __kernel_old_timeval definition instead. This type should be avoided for all new interfaces (those can use 64-bit nanoseconds, or the 64-bit version of timespec instead), and should be used with great care when converting existing interfaces from timeval, to be sure they don't suffer from the y2038 overflow, and only with consensus for the particular user that using __kernel_old_timeval is better than moving to a 64-bit based interface. The structure name is intentionally chosen to not conflict with user space types, and to be ugly enough to discourage its use. Note that ioctl based interfaces that pass a bare 'timeval' pointer cannot change to '__kernel_old_timeval' because the user space source code refers to 'timeval' instead, and we don't want to modify the user space sources if possible. However, any application that relies on a structure to contain an embedded 'timeval' (e.g. by passing a pointer to the member into a function call that expects a timeval pointer) is broken when that structure gets converted to __kernel_old_timeval. I don't see any way around that, and we have to rely on the compiler to produce a warning or compile failure that will alert users when they recompile their sources against a new libc. Signed-off-by: Arnd Bergmann Signed-off-by: Thomas Gleixner Cc: Stephen Boyd Cc: John Stultz Cc: Al Viro Link: https://lkml.kernel.org/r/20180315161739.576085-1-arnd@arndb.de --- include/linux/time32.h | 1 + include/uapi/linux/time.h | 12 ++++++++++++ kernel/time/time.c | 12 ++++++++++++ 3 files changed, 25 insertions(+) (limited to 'include/linux') diff --git a/include/linux/time32.h b/include/linux/time32.h index 65b1de25198d..d2bcd4377b56 100644 --- a/include/linux/time32.h +++ b/include/linux/time32.h @@ -217,5 +217,6 @@ static inline s64 timeval_to_ns(const struct timeval *tv) * Returns the timeval representation of the nsec parameter. */ extern struct timeval ns_to_timeval(const s64 nsec); +extern struct __kernel_old_timeval ns_to_kernel_old_timeval(s64 nsec); #endif diff --git a/include/uapi/linux/time.h b/include/uapi/linux/time.h index 61a187df8da2..16a296612ba4 100644 --- a/include/uapi/linux/time.h +++ b/include/uapi/linux/time.h @@ -42,6 +42,18 @@ struct itimerval { struct timeval it_value; /* current value */ }; +/* + * legacy timeval structure, only embedded in structures that + * traditionally used 'timeval' to pass time intervals (not absolute + * times). Do not add new users. If user space fails to compile + * here, this is probably because it is not y2038 safe and needs to + * be changed to use another interface. + */ +struct __kernel_old_timeval { + __kernel_long_t tv_sec; + __kernel_long_t tv_usec; +}; + /* * The IDs of the various system clocks (for POSIX.1b interval timers): */ diff --git a/kernel/time/time.c b/kernel/time/time.c index bd4e6c7dd689..3044d48ebe56 100644 --- a/kernel/time/time.c +++ b/kernel/time/time.c @@ -488,6 +488,18 @@ struct timeval ns_to_timeval(const s64 nsec) } EXPORT_SYMBOL(ns_to_timeval); +struct __kernel_old_timeval ns_to_kernel_old_timeval(const s64 nsec) +{ + struct timespec64 ts = ns_to_timespec64(nsec); + struct __kernel_old_timeval tv; + + tv.tv_sec = ts.tv_sec; + tv.tv_usec = (suseconds_t)ts.tv_nsec / 1000; + + return tv; +} +EXPORT_SYMBOL(ns_to_kernel_old_timeval); + /** * set_normalized_timespec - set timespec sec and nsec parts and normalize * -- cgit v1.2.3 From e5878732a521dd31ea6377875e49adc424503e5b Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Mon, 19 Mar 2018 10:02:18 +0800 Subject: ahci: imx: add the imx6qp ahci sata support - Regarding to imx6q ahci sata, imx6qp ahci sata has the reset mechanism. Add the imx6qp ahci sata support in this commit. - Use the specific reset callback for imx53 sata, and use the default ahci_ops.softreset for the others. Signed-off-by: Richard Zhu Signed-off-by: Tejun Heo --- Documentation/devicetree/bindings/ata/imx-sata.txt | 1 + drivers/ata/ahci_imx.c | 36 +++++++++++++++++++--- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 2 ++ 3 files changed, 35 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt index a3d14719e478..781f88751762 100644 --- a/Documentation/devicetree/bindings/ata/imx-sata.txt +++ b/Documentation/devicetree/bindings/ata/imx-sata.txt @@ -7,6 +7,7 @@ Required properties: - compatible : should be one of the following: - "fsl,imx53-ahci" for i.MX53 SATA controller - "fsl,imx6q-ahci" for i.MX6Q SATA controller + - "fsl,imx6qp-ahci" for i.MX6QP SATA controller - interrupts : interrupt mapping for SATA IRQ - reg : registers mapping - clocks : list of clock specifiers, must contain an entry for each diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index a58bcc069c54..577458fe4aa9 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -58,6 +58,7 @@ enum { enum ahci_imx_type { AHCI_IMX53, AHCI_IMX6Q, + AHCI_IMX6QP, }; struct imx_ahci_priv { @@ -188,11 +189,26 @@ static int imx_phy_reg_read(u16 *val, void __iomem *mmio) static int imx_sata_phy_reset(struct ahci_host_priv *hpriv) { + struct imx_ahci_priv *imxpriv = hpriv->plat_data; void __iomem *mmio = hpriv->mmio; int timeout = 10; u16 val; int ret; + if (imxpriv->type == AHCI_IMX6QP) { + /* 6qp adds the sata reset mechanism, use it for 6qp sata */ + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_PD, 0); + + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_RST, 0); + udelay(50); + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_RST, + IMX6Q_GPR5_SATA_SW_RST); + return 0; + } + /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */ ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio); if (ret) @@ -408,7 +424,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) if (ret < 0) goto disable_regulator; - if (imxpriv->type == AHCI_IMX6Q) { + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { /* * set PHY Paremeters, two steps to configure the GPR13, * one write for rest of parameters, mask of first write @@ -459,10 +475,21 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv) if (imxpriv->no_device) return; - if (imxpriv->type == AHCI_IMX6Q) { + switch (imxpriv->type) { + case AHCI_IMX6QP: + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_PD, + IMX6Q_GPR5_SATA_SW_PD); regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, IMX6Q_GPR13_SATA_MPLL_CLK_EN, !IMX6Q_GPR13_SATA_MPLL_CLK_EN); + break; + + case AHCI_IMX6Q: + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, + IMX6Q_GPR13_SATA_MPLL_CLK_EN, + !IMX6Q_GPR13_SATA_MPLL_CLK_EN); + break; } clk_disable_unprepare(imxpriv->sata_ref_clk); @@ -513,7 +540,7 @@ static int ahci_imx_softreset(struct ata_link *link, unsigned int *class, if (imxpriv->type == AHCI_IMX53) ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline); - else if (imxpriv->type == AHCI_IMX6Q) + else ret = ahci_ops.softreset(link, class, deadline); return ret; @@ -536,6 +563,7 @@ static const struct ata_port_info ahci_imx_port_info = { static const struct of_device_id imx_ahci_of_match[] = { { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 }, { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q }, + { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP }, {}, }; MODULE_DEVICE_TABLE(of, imx_ahci_of_match); @@ -743,7 +771,7 @@ static int imx_ahci_probe(struct platform_device *pdev) return PTR_ERR(imxpriv->ahb_clk); } - if (imxpriv->type == AHCI_IMX6Q) { + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { u32 reg_value; imxpriv->gpr = syscon_regmap_lookup_by_compatible( diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c8e0164c5423..e06f5f79eaef 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -243,6 +243,8 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_SATA_SW_PD BIT(10) +#define IMX6Q_GPR5_SATA_SW_RST BIT(11) #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) -- cgit v1.2.3 From b3a5d111994450909158929560906f2c1c6c1d85 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Wed, 14 Mar 2018 12:45:12 -0700 Subject: percpu_ref: Update doc to dissuade users from depending on internal RCU grace periods percpu_ref internally uses sched-RCU to implement the percpu -> atomic mode switching and the documentation suggested that this could be depended upon. This doesn't seem like a good idea. * percpu_ref uses sched-RCU which has different grace periods regular RCU. Users may combine percpu_ref with regular RCU usage and incorrectly believe that regular RCU grace periods are performed by percpu_ref. This can lead to, for example, use-after-free due to premature freeing. * percpu_ref has a grace period when switching from percpu to atomic mode. It doesn't have one between the last put and release. This distinction is subtle and can lead to surprising bugs. * percpu_ref allows starting in and switching to atomic mode manually for debugging and other purposes. This means that there may not be any grace periods from kill to release. This patch makes it clear that the grace periods are percpu_ref's internal implementation detail and can't be depended upon by the users. Signed-off-by: Tejun Heo Cc: Kent Overstreet Cc: Linus Torvalds Signed-off-by: Tejun Heo --- include/linux/percpu-refcount.h | 18 ++++++++++++------ lib/percpu-refcount.c | 2 ++ 2 files changed, 14 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/percpu-refcount.h b/include/linux/percpu-refcount.h index 864d167a1073..009cdf3d65b6 100644 --- a/include/linux/percpu-refcount.h +++ b/include/linux/percpu-refcount.h @@ -30,10 +30,14 @@ * calls io_destroy() or the process exits. * * In the aio code, kill_ioctx() is called when we wish to destroy a kioctx; it - * calls percpu_ref_kill(), then hlist_del_rcu() and synchronize_rcu() to remove - * the kioctx from the proccess's list of kioctxs - after that, there can't be - * any new users of the kioctx (from lookup_ioctx()) and it's then safe to drop - * the initial ref with percpu_ref_put(). + * removes the kioctx from the proccess's table of kioctxs and kills percpu_ref. + * After that, there can't be any new users of the kioctx (from lookup_ioctx()) + * and it's then safe to drop the initial ref with percpu_ref_put(). + * + * Note that the free path, free_ioctx(), needs to go through explicit call_rcu() + * to synchronize with RCU protected lookup_ioctx(). percpu_ref operations don't + * imply RCU grace periods of any kind and if a user wants to combine percpu_ref + * with RCU protection, it must be done explicitly. * * Code that does a two stage shutdown like this often needs some kind of * explicit synchronization to ensure the initial refcount can only be dropped @@ -113,8 +117,10 @@ void percpu_ref_reinit(struct percpu_ref *ref); * Must be used to drop the initial ref on a percpu refcount; must be called * precisely once before shutdown. * - * Puts @ref in non percpu mode, then does a call_rcu() before gathering up the - * percpu counters and dropping the initial ref. + * Switches @ref into atomic mode before gathering up the percpu counters + * and dropping the initial ref. + * + * There are no implied RCU grace periods between kill and release. */ static inline void percpu_ref_kill(struct percpu_ref *ref) { diff --git a/lib/percpu-refcount.c b/lib/percpu-refcount.c index 30e7dd88148b..9f96fa7bc000 100644 --- a/lib/percpu-refcount.c +++ b/lib/percpu-refcount.c @@ -322,6 +322,8 @@ EXPORT_SYMBOL_GPL(percpu_ref_switch_to_percpu); * This function normally doesn't block and can be called from any context * but it may block if @confirm_kill is specified and @ref is in the * process of switching to atomic mode by percpu_ref_switch_to_atomic(). + * + * There are no implied RCU grace periods between kill and release. */ void percpu_ref_kill_and_confirm(struct percpu_ref *ref, percpu_ref_func_t *confirm_kill) -- cgit v1.2.3 From 05f0fe6b74dbd7690a4cbd61810948b7d575576a Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Wed, 14 Mar 2018 12:45:13 -0700 Subject: RCU, workqueue: Implement rcu_work There are cases where RCU callback needs to be bounced to a sleepable context. This is currently done by the RCU callback queueing a work item, which can be cumbersome to write and confusing to read. This patch introduces rcu_work, a workqueue work variant which gets executed after a RCU grace period, and converts the open coded bouncing in fs/aio and kernel/cgroup. v3: Dropped queue_rcu_work_on(). Documented rcu grace period behavior after queue_rcu_work(). v2: Use rcu_barrier() instead of synchronize_rcu() to wait for completion of previously queued rcu callback as per Paul. Signed-off-by: Tejun Heo Acked-by: "Paul E. McKenney" Cc: Linus Torvalds --- include/linux/workqueue.h | 23 ++++++++++++++++++++ kernel/workqueue.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) (limited to 'include/linux') diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h index bc0cda180c8b..d026f8f818cc 100644 --- a/include/linux/workqueue.h +++ b/include/linux/workqueue.h @@ -13,6 +13,7 @@ #include #include #include +#include struct workqueue_struct; @@ -120,6 +121,14 @@ struct delayed_work { int cpu; }; +struct rcu_work { + struct work_struct work; + struct rcu_head rcu; + + /* target workqueue ->rcu uses to queue ->work */ + struct workqueue_struct *wq; +}; + /** * struct workqueue_attrs - A struct for workqueue attributes. * @@ -151,6 +160,11 @@ static inline struct delayed_work *to_delayed_work(struct work_struct *work) return container_of(work, struct delayed_work, work); } +static inline struct rcu_work *to_rcu_work(struct work_struct *work) +{ + return container_of(work, struct rcu_work, work); +} + struct execute_work { struct work_struct work; }; @@ -266,6 +280,12 @@ static inline unsigned int work_static(struct work_struct *work) { return 0; } #define INIT_DEFERRABLE_WORK_ONSTACK(_work, _func) \ __INIT_DELAYED_WORK_ONSTACK(_work, _func, TIMER_DEFERRABLE) +#define INIT_RCU_WORK(_work, _func) \ + INIT_WORK(&(_work)->work, (_func)) + +#define INIT_RCU_WORK_ONSTACK(_work, _func) \ + INIT_WORK_ONSTACK(&(_work)->work, (_func)) + /** * work_pending - Find out whether a work item is currently pending * @work: The work item in question @@ -447,6 +467,7 @@ extern bool queue_delayed_work_on(int cpu, struct workqueue_struct *wq, struct delayed_work *work, unsigned long delay); extern bool mod_delayed_work_on(int cpu, struct workqueue_struct *wq, struct delayed_work *dwork, unsigned long delay); +extern bool queue_rcu_work(struct workqueue_struct *wq, struct rcu_work *rwork); extern void flush_workqueue(struct workqueue_struct *wq); extern void drain_workqueue(struct workqueue_struct *wq); @@ -463,6 +484,8 @@ extern bool flush_delayed_work(struct delayed_work *dwork); extern bool cancel_delayed_work(struct delayed_work *dwork); extern bool cancel_delayed_work_sync(struct delayed_work *dwork); +extern bool flush_rcu_work(struct rcu_work *rwork); + extern void workqueue_set_max_active(struct workqueue_struct *wq, int max_active); extern struct work_struct *current_work(void); diff --git a/kernel/workqueue.c b/kernel/workqueue.c index bb9a519cbf50..7df85fa9f651 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -1604,6 +1604,40 @@ bool mod_delayed_work_on(int cpu, struct workqueue_struct *wq, } EXPORT_SYMBOL_GPL(mod_delayed_work_on); +static void rcu_work_rcufn(struct rcu_head *rcu) +{ + struct rcu_work *rwork = container_of(rcu, struct rcu_work, rcu); + + /* read the comment in __queue_work() */ + local_irq_disable(); + __queue_work(WORK_CPU_UNBOUND, rwork->wq, &rwork->work); + local_irq_enable(); +} + +/** + * queue_rcu_work - queue work after a RCU grace period + * @wq: workqueue to use + * @rwork: work to queue + * + * Return: %false if @rwork was already pending, %true otherwise. Note + * that a full RCU grace period is guaranteed only after a %true return. + * While @rwork is guarnateed to be executed after a %false return, the + * execution may happen before a full RCU grace period has passed. + */ +bool queue_rcu_work(struct workqueue_struct *wq, struct rcu_work *rwork) +{ + struct work_struct *work = &rwork->work; + + if (!test_and_set_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(work))) { + rwork->wq = wq; + call_rcu(&rwork->rcu, rcu_work_rcufn); + return true; + } + + return false; +} +EXPORT_SYMBOL(queue_rcu_work); + /** * worker_enter_idle - enter idle state * @worker: worker which is entering idle state @@ -3001,6 +3035,26 @@ bool flush_delayed_work(struct delayed_work *dwork) } EXPORT_SYMBOL(flush_delayed_work); +/** + * flush_rcu_work - wait for a rwork to finish executing the last queueing + * @rwork: the rcu work to flush + * + * Return: + * %true if flush_rcu_work() waited for the work to finish execution, + * %false if it was already idle. + */ +bool flush_rcu_work(struct rcu_work *rwork) +{ + if (test_bit(WORK_STRUCT_PENDING_BIT, work_data_bits(&rwork->work))) { + rcu_barrier(); + flush_work(&rwork->work); + return true; + } else { + return flush_work(&rwork->work); + } +} +EXPORT_SYMBOL(flush_rcu_work); + static bool __cancel_work(struct work_struct *work, bool is_dwork) { unsigned long flags; -- cgit v1.2.3 From 8f36aaec9c929f2864196b0799203491f6a67dc6 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Wed, 14 Mar 2018 12:45:14 -0700 Subject: cgroup: Use rcu_work instead of explicit rcu and work item Workqueue now has rcu_work. Use it instead of open-coding rcu -> work item bouncing. Signed-off-by: Tejun Heo --- include/linux/cgroup-defs.h | 2 +- kernel/cgroup/cgroup.c | 21 +++++++-------------- 2 files changed, 8 insertions(+), 15 deletions(-) (limited to 'include/linux') diff --git a/include/linux/cgroup-defs.h b/include/linux/cgroup-defs.h index 9f242b876fde..92d7640632ef 100644 --- a/include/linux/cgroup-defs.h +++ b/include/linux/cgroup-defs.h @@ -151,8 +151,8 @@ struct cgroup_subsys_state { atomic_t online_cnt; /* percpu_ref killing and RCU release */ - struct rcu_head rcu_head; struct work_struct destroy_work; + struct rcu_work destroy_rwork; /* * PI: the parent css. Placed here for cache proximity to following diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 8cda3bc3ae22..4c5d4ca0d4e4 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -4514,10 +4514,10 @@ static struct cftype cgroup_base_files[] = { * and thus involve punting to css->destroy_work adding two additional * steps to the already complex sequence. */ -static void css_free_work_fn(struct work_struct *work) +static void css_free_rwork_fn(struct work_struct *work) { - struct cgroup_subsys_state *css = - container_of(work, struct cgroup_subsys_state, destroy_work); + struct cgroup_subsys_state *css = container_of(to_rcu_work(work), + struct cgroup_subsys_state, destroy_rwork); struct cgroup_subsys *ss = css->ss; struct cgroup *cgrp = css->cgroup; @@ -4563,15 +4563,6 @@ static void css_free_work_fn(struct work_struct *work) } } -static void css_free_rcu_fn(struct rcu_head *rcu_head) -{ - struct cgroup_subsys_state *css = - container_of(rcu_head, struct cgroup_subsys_state, rcu_head); - - INIT_WORK(&css->destroy_work, css_free_work_fn); - queue_work(cgroup_destroy_wq, &css->destroy_work); -} - static void css_release_work_fn(struct work_struct *work) { struct cgroup_subsys_state *css = @@ -4621,7 +4612,8 @@ static void css_release_work_fn(struct work_struct *work) mutex_unlock(&cgroup_mutex); - call_rcu(&css->rcu_head, css_free_rcu_fn); + INIT_RCU_WORK(&css->destroy_rwork, css_free_rwork_fn); + queue_rcu_work(cgroup_destroy_wq, &css->destroy_rwork); } static void css_release(struct percpu_ref *ref) @@ -4755,7 +4747,8 @@ static struct cgroup_subsys_state *css_create(struct cgroup *cgrp, err_list_del: list_del_rcu(&css->sibling); err_free_css: - call_rcu(&css->rcu_head, css_free_rcu_fn); + INIT_RCU_WORK(&css->destroy_rwork, css_free_rwork_fn); + queue_rcu_work(cgroup_destroy_wq, &css->destroy_rwork); return ERR_PTR(err); } -- cgit v1.2.3 From 05d3ac978ed25b753bfe34fe76c50c31ee506a82 Mon Sep 17 00:00:00 2001 From: Bodong Wang Date: Mon, 19 Mar 2018 15:10:29 +0200 Subject: net/mlx5: Packet pacing enhancement Add two new parameters: max_burst_sz and typical_pkt_size (both in bytes) to rate limit configurations. max_burst_sz: The device will schedule bursts of packets for an SQ connected to this rate, smaller than or equal to this value. Value 0x0 indicates packet bursts will be limited to the device defaults. This field should be used if bursts of packets must be strictly kept under a certain value. typical_pkt_size: When the rate limit is intended for a stream of similar packets, stating the typical packet size can improve the accuracy of the rate limiter. The expected packet size will be the same for all SQs associated with the same rate limit index. Ethernet driver is updated according to this change, but these two parameters will be kept as 0 due to lacking of proper way to get the configurations from user space which requires to change ndo_set_tx_maxrate interface. Signed-off-by: Bodong Wang Reviewed-by: Daniel Jurgens Reviewed-by: Yishai Hadas Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 19 ++++--- drivers/net/ethernet/mellanox/mlx5/core/rl.c | 63 +++++++++++++++-------- include/linux/mlx5/driver.h | 15 ++++-- include/linux/mlx5/mlx5_ifc.h | 12 ++++- 4 files changed, 76 insertions(+), 33 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 47bab842c5ee..2ee4ffbddd5f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1195,10 +1195,13 @@ static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) { struct mlx5e_channel *c = sq->channel; struct mlx5_core_dev *mdev = c->mdev; + struct mlx5_rate_limit rl = {0}; mlx5e_destroy_sq(mdev, sq->sqn); - if (sq->rate_limit) - mlx5_rl_remove_rate(mdev, sq->rate_limit); + if (sq->rate_limit) { + rl.rate = sq->rate_limit; + mlx5_rl_remove_rate(mdev, &rl); + } mlx5e_free_txqsq_descs(sq); mlx5e_free_txqsq(sq); } @@ -1528,6 +1531,7 @@ static int mlx5e_set_sq_maxrate(struct net_device *dev, struct mlx5e_priv *priv = netdev_priv(dev); struct mlx5_core_dev *mdev = priv->mdev; struct mlx5e_modify_sq_param msp = {0}; + struct mlx5_rate_limit rl = {0}; u16 rl_index = 0; int err; @@ -1535,14 +1539,17 @@ static int mlx5e_set_sq_maxrate(struct net_device *dev, /* nothing to do */ return 0; - if (sq->rate_limit) + if (sq->rate_limit) { + rl.rate = sq->rate_limit; /* remove current rl index to free space to next ones */ - mlx5_rl_remove_rate(mdev, sq->rate_limit); + mlx5_rl_remove_rate(mdev, &rl); + } sq->rate_limit = 0; if (rate) { - err = mlx5_rl_add_rate(mdev, rate, &rl_index); + rl.rate = rate; + err = mlx5_rl_add_rate(mdev, &rl_index, &rl); if (err) { netdev_err(dev, "Failed configuring rate %u: %d\n", rate, err); @@ -1560,7 +1567,7 @@ static int mlx5e_set_sq_maxrate(struct net_device *dev, rate, err); /* remove the rate from the table */ if (rate) - mlx5_rl_remove_rate(mdev, rate); + mlx5_rl_remove_rate(mdev, &rl); return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c index d3c33e9eea72..bc86dffdc43c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c @@ -107,16 +107,16 @@ int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, * If the table is full, return NULL */ static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table, - u32 rate) + struct mlx5_rate_limit *rl) { struct mlx5_rl_entry *ret_entry = NULL; bool empty_found = false; int i; for (i = 0; i < table->max_size; i++) { - if (table->rl_entry[i].rate == rate) + if (mlx5_rl_are_equal(&table->rl_entry[i].rl, rl)) return &table->rl_entry[i]; - if (!empty_found && !table->rl_entry[i].rate) { + if (!empty_found && !table->rl_entry[i].rl.rate) { empty_found = true; ret_entry = &table->rl_entry[i]; } @@ -126,7 +126,8 @@ static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table, } static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev, - u32 rate, u16 index) + u16 index, + struct mlx5_rate_limit *rl) { u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0}; u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0}; @@ -134,7 +135,9 @@ static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev, MLX5_SET(set_pp_rate_limit_in, in, opcode, MLX5_CMD_OP_SET_PP_RATE_LIMIT); MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, index); - MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rate); + MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rl->rate); + MLX5_SET(set_pp_rate_limit_in, in, burst_upper_bound, rl->max_burst_sz); + MLX5_SET(set_pp_rate_limit_in, in, typical_packet_size, rl->typical_pkt_sz); return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } @@ -146,7 +149,17 @@ bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate) } EXPORT_SYMBOL(mlx5_rl_is_in_range); -int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index) +bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, + struct mlx5_rate_limit *rl_1) +{ + return ((rl_0->rate == rl_1->rate) && + (rl_0->max_burst_sz == rl_1->max_burst_sz) && + (rl_0->typical_pkt_sz == rl_1->typical_pkt_sz)); +} +EXPORT_SYMBOL(mlx5_rl_are_equal); + +int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, + struct mlx5_rate_limit *rl) { struct mlx5_rl_table *table = &dev->priv.rl_table; struct mlx5_rl_entry *entry; @@ -154,14 +167,14 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index) mutex_lock(&table->rl_lock); - if (!rate || !mlx5_rl_is_in_range(dev, rate)) { + if (!rl->rate || !mlx5_rl_is_in_range(dev, rl->rate)) { mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n", - rate, table->min_rate, table->max_rate); + rl->rate, table->min_rate, table->max_rate); err = -EINVAL; goto out; } - entry = find_rl_entry(table, rate); + entry = find_rl_entry(table, rl); if (!entry) { mlx5_core_err(dev, "Max number of %u rates reached\n", table->max_size); @@ -173,13 +186,15 @@ int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index) entry->refcount++; } else { /* new rate limit */ - err = mlx5_set_pp_rate_limit_cmd(dev, rate, entry->index); + err = mlx5_set_pp_rate_limit_cmd(dev, entry->index, rl); if (err) { - mlx5_core_err(dev, "Failed configuring rate: %u (%d)\n", - rate, err); + mlx5_core_err(dev, "Failed configuring rate limit(err %d): \ + rate %u, max_burst_sz %u, typical_pkt_sz %u\n", + err, rl->rate, rl->max_burst_sz, + rl->typical_pkt_sz); goto out; } - entry->rate = rate; + entry->rl = *rl; entry->refcount = 1; } *index = entry->index; @@ -190,27 +205,30 @@ out: } EXPORT_SYMBOL(mlx5_rl_add_rate); -void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate) +void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl) { struct mlx5_rl_table *table = &dev->priv.rl_table; struct mlx5_rl_entry *entry = NULL; + struct mlx5_rate_limit reset_rl = {0}; /* 0 is a reserved value for unlimited rate */ - if (rate == 0) + if (rl->rate == 0) return; mutex_lock(&table->rl_lock); - entry = find_rl_entry(table, rate); + entry = find_rl_entry(table, rl); if (!entry || !entry->refcount) { - mlx5_core_warn(dev, "Rate %u is not configured\n", rate); + mlx5_core_warn(dev, "Rate %u, max_burst_sz %u typical_pkt_sz %u \ + are not configured\n", + rl->rate, rl->max_burst_sz, rl->typical_pkt_sz); goto out; } entry->refcount--; if (!entry->refcount) { /* need to remove rate */ - mlx5_set_pp_rate_limit_cmd(dev, 0, entry->index); - entry->rate = 0; + mlx5_set_pp_rate_limit_cmd(dev, entry->index, &reset_rl); + entry->rl = reset_rl; } out: @@ -257,13 +275,14 @@ int mlx5_init_rl_table(struct mlx5_core_dev *dev) void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev) { struct mlx5_rl_table *table = &dev->priv.rl_table; + struct mlx5_rate_limit rl = {0}; int i; /* Clear all configured rates */ for (i = 0; i < table->max_size; i++) - if (table->rl_entry[i].rate) - mlx5_set_pp_rate_limit_cmd(dev, 0, - table->rl_entry[i].index); + if (table->rl_entry[i].rl.rate) + mlx5_set_pp_rate_limit_cmd(dev, table->rl_entry[i].index, + &rl); kfree(dev->priv.rl_table.rl_entry); } diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index cded85ab6fe4..767d193c269a 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -591,8 +591,14 @@ struct mlx5_eswitch; struct mlx5_lag; struct mlx5_pagefault; +struct mlx5_rate_limit { + u32 rate; + u32 max_burst_sz; + u16 typical_pkt_sz; +}; + struct mlx5_rl_entry { - u32 rate; + struct mlx5_rate_limit rl; u16 index; u16 refcount; }; @@ -1107,9 +1113,12 @@ int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, int mlx5_init_rl_table(struct mlx5_core_dev *dev); void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); -int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); -void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); +int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, + struct mlx5_rate_limit *rl); +void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); +bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, + struct mlx5_rate_limit *rl_1); int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, bool map_wc, bool fast_path); void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 14ad84afe8ba..c63bbdc35503 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -571,7 +571,10 @@ struct mlx5_ifc_qos_cap_bits { u8 esw_scheduling[0x1]; u8 esw_bw_share[0x1]; u8 esw_rate_limit[0x1]; - u8 reserved_at_4[0x1c]; + u8 reserved_at_4[0x1]; + u8 packet_pacing_burst_bound[0x1]; + u8 packet_pacing_typical_size[0x1]; + u8 reserved_at_7[0x19]; u8 reserved_at_20[0x20]; @@ -7313,7 +7316,12 @@ struct mlx5_ifc_set_pp_rate_limit_in_bits { u8 rate_limit[0x20]; - u8 reserved_at_a0[0x160]; + u8 burst_upper_bound[0x20]; + + u8 reserved_at_c0[0x10]; + u8 typical_packet_size[0x10]; + + u8 reserved_at_e0[0x120]; }; struct mlx5_ifc_access_register_out_bits { -- cgit v1.2.3 From 33c4c8a588e6cccf3832b84b7792f02153e0ccda Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Mon, 12 Mar 2018 10:41:18 +0100 Subject: PCI: Add Altera vendor ID Add the Altera PCI Vendor id to pci_ids.h and remove the private definitions from xillybus_pcie.c and altera-cvp.c. Signed-off-by: Johannes Thumshirn Signed-off-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko Acked-by: Eli Billauer Acked-by: Bjorn Helgaas Cc: Anatolij Gustschin --- drivers/char/xillybus/xillybus_pcie.c | 1 - drivers/fpga/altera-cvp.c | 2 -- include/linux/pci_ids.h | 2 ++ 3 files changed, 2 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/char/xillybus/xillybus_pcie.c b/drivers/char/xillybus/xillybus_pcie.c index dff2d1538164..05e5324f60bd 100644 --- a/drivers/char/xillybus/xillybus_pcie.c +++ b/drivers/char/xillybus/xillybus_pcie.c @@ -24,7 +24,6 @@ MODULE_LICENSE("GPL v2"); #define PCI_DEVICE_ID_XILLYBUS 0xebeb -#define PCI_VENDOR_ID_ALTERA 0x1172 #define PCI_VENDOR_ID_ACTEL 0x11aa #define PCI_VENDOR_ID_LATTICE 0x1204 diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 00e73d28077c..77b04e4b3254 100644 --- a/drivers/fpga/altera-cvp.c +++ b/drivers/fpga/altera-cvp.c @@ -384,8 +384,6 @@ static int altera_cvp_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id); static void altera_cvp_remove(struct pci_dev *pdev); -#define PCI_VENDOR_ID_ALTERA 0x1172 - static struct pci_device_id altera_cvp_id_tbl[] = { { PCI_VDEVICE(ALTERA, PCI_ANY_ID) }, { } diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a6b30667a331..6a96a70fb462 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -1561,6 +1561,8 @@ #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408 +#define PCI_VENDOR_ID_ALTERA 0x1172 + #define PCI_VENDOR_ID_SBE 0x1176 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302 -- cgit v1.2.3 From 312fc2b4c82e96a48cb2d0da2bd4816eb253c499 Mon Sep 17 00:00:00 2001 From: John Fastabend Date: Sun, 18 Mar 2018 12:57:00 -0700 Subject: net: do_tcp_sendpages flag to avoid SKBTX_SHARED_FRAG When calling do_tcp_sendpages() from in kernel and we know the data has no references from user side we can omit SKBTX_SHARED_FRAG flag. This patch adds an internal flag, NO_SKBTX_SHARED_FRAG that can be used to omit setting SKBTX_SHARED_FRAG. The flag is not exposed to userspace because the sendpage call from the splice logic masks out all bits except MSG_MORE. Signed-off-by: John Fastabend Acked-by: David S. Miller Signed-off-by: Daniel Borkmann --- include/linux/socket.h | 1 + net/ipv4/tcp.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/socket.h b/include/linux/socket.h index 1ce1f768a58c..60e01482a9c4 100644 --- a/include/linux/socket.h +++ b/include/linux/socket.h @@ -287,6 +287,7 @@ struct ucred { #define MSG_SENDPAGE_NOTLAST 0x20000 /* sendpage() internal : not the last page */ #define MSG_BATCH 0x40000 /* sendmmsg(): more messages coming */ #define MSG_EOF MSG_FIN +#define MSG_NO_SHARED_FRAGS 0x80000 /* sendpage() internal : page frags are not shared */ #define MSG_ZEROCOPY 0x4000000 /* Use user data in kernel path */ #define MSG_FASTOPEN 0x20000000 /* Send data in TCP SYN */ diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index fb350f740f69..f90ec24c2cc8 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -994,7 +994,9 @@ new_segment: get_page(page); skb_fill_page_desc(skb, i, page, offset, copy); } - skb_shinfo(skb)->tx_flags |= SKBTX_SHARED_FRAG; + + if (!(flags & MSG_NO_SHARED_FRAGS)) + skb_shinfo(skb)->tx_flags |= SKBTX_SHARED_FRAG; skb->len += copy; skb->data_len += copy; -- cgit v1.2.3 From 4f738adba30a7cfc006f605707e7aee847ffefa0 Mon Sep 17 00:00:00 2001 From: John Fastabend Date: Sun, 18 Mar 2018 12:57:10 -0700 Subject: bpf: create tcp_bpf_ulp allowing BPF to monitor socket TX/RX data This implements a BPF ULP layer to allow policy enforcement and monitoring at the socket layer. In order to support this a new program type BPF_PROG_TYPE_SK_MSG is used to run the policy at the sendmsg/sendpage hook. To attach the policy to sockets a sockmap is used with a new program attach type BPF_SK_MSG_VERDICT. Similar to previous sockmap usages when a sock is added to a sockmap, via a map update, if the map contains a BPF_SK_MSG_VERDICT program type attached then the BPF ULP layer is created on the socket and the attached BPF_PROG_TYPE_SK_MSG program is run for every msg in sendmsg case and page/offset in sendpage case. BPF_PROG_TYPE_SK_MSG Semantics/API: BPF_PROG_TYPE_SK_MSG supports only two return codes SK_PASS and SK_DROP. Returning SK_DROP free's the copied data in the sendmsg case and in the sendpage case leaves the data untouched. Both cases return -EACESS to the user. Returning SK_PASS will allow the msg to be sent. In the sendmsg case data is copied into kernel space buffers before running the BPF program. The kernel space buffers are stored in a scatterlist object where each element is a kernel memory buffer. Some effort is made to coalesce data from the sendmsg call here. For example a sendmsg call with many one byte iov entries will likely be pushed into a single entry. The BPF program is run with data pointers (start/end) pointing to the first sg element. In the sendpage case data is not copied. We opt not to copy the data by default here, because the BPF infrastructure does not know what bytes will be needed nor when they will be needed. So copying all bytes may be wasteful. Because of this the initial start/end data pointers are (0,0). Meaning no data can be read or written. This avoids reading data that may be modified by the user. A new helper is added later in this series if reading and writing the data is needed. The helper call will do a copy by default so that the page is exclusively owned by the BPF call. The verdict from the BPF_PROG_TYPE_SK_MSG applies to the entire msg in the sendmsg() case and the entire page/offset in the sendpage case. This avoids ambiguity on how to handle mixed return codes in the sendmsg case. Again a helper is added later in the series if a verdict needs to apply to multiple system calls and/or only a subpart of the currently being processed message. The helper msg_redirect_map() can be used to select the socket to send the data on. This is used similar to existing redirect use cases. This allows policy to redirect msgs. Pseudo code simple example: The basic logic to attach a program to a socket is as follows, // load the programs bpf_prog_load(SOCKMAP_TCP_MSG_PROG, BPF_PROG_TYPE_SK_MSG, &obj, &msg_prog); // lookup the sockmap bpf_map_msg = bpf_object__find_map_by_name(obj, "my_sock_map"); // get fd for sockmap map_fd_msg = bpf_map__fd(bpf_map_msg); // attach program to sockmap bpf_prog_attach(msg_prog, map_fd_msg, BPF_SK_MSG_VERDICT, 0); Adding sockets to the map is done in the normal way, // Add a socket 'fd' to sockmap at location 'i' bpf_map_update_elem(map_fd_msg, &i, fd, BPF_ANY); After the above any socket attached to "my_sock_map", in this case 'fd', will run the BPF msg verdict program (msg_prog) on every sendmsg and sendpage system call. For a complete example see BPF selftests or sockmap samples. Implementation notes: It seemed the simplest, to me at least, to use a refcnt to ensure psock is not lost across the sendmsg copy into the sg, the bpf program running on the data in sg_data, and the final pass to the TCP stack. Some performance testing may show a better method to do this and avoid the refcnt cost, but for now use the simpler method. Another item that will come after basic support is in place is supporting MSG_MORE flag. At the moment we call sendpages even if the MSG_MORE flag is set. An enhancement would be to collect the pages into a larger scatterlist and pass down the stack. Notice that bpf_tcp_sendmsg() could support this with some additional state saved across sendmsg calls. I built the code to support this without having to do refactoring work. Other features TBD include ZEROCOPY and the TCP_RECV_QUEUE/TCP_NO_QUEUE support. This will follow initial series shortly. Future work could improve size limits on the scatterlist rings used here. Currently, we use MAX_SKB_FRAGS simply because this was being used already in the TLS case. Future work could extend the kernel sk APIs to tune this depending on workload. This is a trade-off between memory usage and throughput performance. Signed-off-by: John Fastabend Acked-by: David S. Miller Acked-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/bpf.h | 1 + include/linux/bpf_types.h | 1 + include/linux/filter.h | 17 ++ include/uapi/linux/bpf.h | 22 +- kernel/bpf/sockmap.c | 712 +++++++++++++++++++++++++++++++++++++++++++++- kernel/bpf/syscall.c | 14 +- kernel/bpf/verifier.c | 5 +- net/core/filter.c | 106 +++++++ 8 files changed, 857 insertions(+), 21 deletions(-) (limited to 'include/linux') diff --git a/include/linux/bpf.h b/include/linux/bpf.h index 66df387106de..819229c80eca 100644 --- a/include/linux/bpf.h +++ b/include/linux/bpf.h @@ -21,6 +21,7 @@ struct bpf_verifier_env; struct perf_event; struct bpf_prog; struct bpf_map; +struct sock; /* map is generic key/value storage optionally accesible by eBPF programs */ struct bpf_map_ops { diff --git a/include/linux/bpf_types.h b/include/linux/bpf_types.h index 19b8349a3809..5e2e8a49fb21 100644 --- a/include/linux/bpf_types.h +++ b/include/linux/bpf_types.h @@ -13,6 +13,7 @@ BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_OUT, lwt_inout) BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_XMIT, lwt_xmit) BPF_PROG_TYPE(BPF_PROG_TYPE_SOCK_OPS, sock_ops) BPF_PROG_TYPE(BPF_PROG_TYPE_SK_SKB, sk_skb) +BPF_PROG_TYPE(BPF_PROG_TYPE_SK_MSG, sk_msg) #endif #ifdef CONFIG_BPF_EVENTS BPF_PROG_TYPE(BPF_PROG_TYPE_KPROBE, kprobe) diff --git a/include/linux/filter.h b/include/linux/filter.h index fdb691b520c0..109d05ccea9a 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -507,6 +507,22 @@ struct xdp_buff { struct xdp_rxq_info *rxq; }; +struct sk_msg_buff { + void *data; + void *data_end; + __u32 apply_bytes; + __u32 cork_bytes; + int sg_copybreak; + int sg_start; + int sg_curr; + int sg_end; + struct scatterlist sg_data[MAX_SKB_FRAGS]; + bool sg_copy[MAX_SKB_FRAGS]; + __u32 key; + __u32 flags; + struct bpf_map *map; +}; + /* Compute the linear packet data range [data, data_end) which * will be accessed by various program types (cls_bpf, act_bpf, * lwt, ...). Subsystems allowing direct data access must (!) @@ -771,6 +787,7 @@ xdp_data_meta_unsupported(const struct xdp_buff *xdp) void bpf_warn_invalid_xdp_action(u32 act); struct sock *do_sk_redirect_map(struct sk_buff *skb); +struct sock *do_msg_redirect_map(struct sk_msg_buff *md); #ifdef CONFIG_BPF_JIT extern int bpf_jit_enable; diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 1e15d1724d89..ef529539abde 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -133,6 +133,7 @@ enum bpf_prog_type { BPF_PROG_TYPE_SOCK_OPS, BPF_PROG_TYPE_SK_SKB, BPF_PROG_TYPE_CGROUP_DEVICE, + BPF_PROG_TYPE_SK_MSG, }; enum bpf_attach_type { @@ -143,6 +144,7 @@ enum bpf_attach_type { BPF_SK_SKB_STREAM_PARSER, BPF_SK_SKB_STREAM_VERDICT, BPF_CGROUP_DEVICE, + BPF_SK_MSG_VERDICT, __MAX_BPF_ATTACH_TYPE }; @@ -718,6 +720,15 @@ union bpf_attr { * int bpf_override_return(pt_regs, rc) * @pt_regs: pointer to struct pt_regs * @rc: the return value to set + * + * int bpf_msg_redirect_map(map, key, flags) + * Redirect msg to a sock in map using key as a lookup key for the + * sock in map. + * @map: pointer to sockmap + * @key: key to lookup sock in map + * @flags: reserved for future use + * Return: SK_PASS + * */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -779,7 +790,8 @@ union bpf_attr { FN(perf_prog_read_value), \ FN(getsockopt), \ FN(override_return), \ - FN(sock_ops_cb_flags_set), + FN(sock_ops_cb_flags_set), \ + FN(msg_redirect_map), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call @@ -942,6 +954,14 @@ enum sk_action { SK_PASS, }; +/* user accessible metadata for SK_MSG packet hook, new fields must + * be added to the end of this structure + */ +struct sk_msg_md { + void *data; + void *data_end; +}; + #define BPF_TAG_SIZE 8 struct bpf_prog_info { diff --git a/kernel/bpf/sockmap.c b/kernel/bpf/sockmap.c index 051b224270e3..69c5bccabd22 100644 --- a/kernel/bpf/sockmap.c +++ b/kernel/bpf/sockmap.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -47,6 +48,7 @@ struct bpf_stab { struct bpf_map map; struct sock **sock_map; + struct bpf_prog *bpf_tx_msg; struct bpf_prog *bpf_parse; struct bpf_prog *bpf_verdict; }; @@ -73,7 +75,16 @@ struct smap_psock { int save_off; struct sk_buff *save_skb; + /* datapath variables for tx_msg ULP */ + struct sock *sk_redir; + int apply_bytes; + int cork_bytes; + int sg_size; + int eval; + struct sk_msg_buff *cork; + struct strparser strp; + struct bpf_prog *bpf_tx_msg; struct bpf_prog *bpf_parse; struct bpf_prog *bpf_verdict; struct list_head maps; @@ -91,6 +102,11 @@ struct smap_psock { void (*save_write_space)(struct sock *sk); }; +static void smap_release_sock(struct smap_psock *psock, struct sock *sock); +static int bpf_tcp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size); +static int bpf_tcp_sendpage(struct sock *sk, struct page *page, + int offset, size_t size, int flags); + static inline struct smap_psock *smap_psock_sk(const struct sock *sk) { return rcu_dereference_sk_user_data(sk); @@ -115,27 +131,41 @@ static int bpf_tcp_init(struct sock *sk) psock->save_close = sk->sk_prot->close; psock->sk_proto = sk->sk_prot; + + if (psock->bpf_tx_msg) { + tcp_bpf_proto.sendmsg = bpf_tcp_sendmsg; + tcp_bpf_proto.sendpage = bpf_tcp_sendpage; + } + sk->sk_prot = &tcp_bpf_proto; rcu_read_unlock(); return 0; } +static void smap_release_sock(struct smap_psock *psock, struct sock *sock); +static int free_start_sg(struct sock *sk, struct sk_msg_buff *md); + static void bpf_tcp_release(struct sock *sk) { struct smap_psock *psock; rcu_read_lock(); psock = smap_psock_sk(sk); + if (unlikely(!psock)) + goto out; - if (likely(psock)) { - sk->sk_prot = psock->sk_proto; - psock->sk_proto = NULL; + if (psock->cork) { + free_start_sg(psock->sock, psock->cork); + kfree(psock->cork); + psock->cork = NULL; } + + sk->sk_prot = psock->sk_proto; + psock->sk_proto = NULL; +out: rcu_read_unlock(); } -static void smap_release_sock(struct smap_psock *psock, struct sock *sock); - static void bpf_tcp_close(struct sock *sk, long timeout) { void (*close_fun)(struct sock *sk, long timeout); @@ -174,6 +204,7 @@ enum __sk_action { __SK_DROP = 0, __SK_PASS, __SK_REDIRECT, + __SK_NONE, }; static struct tcp_ulp_ops bpf_tcp_ulp_ops __read_mostly = { @@ -185,10 +216,621 @@ static struct tcp_ulp_ops bpf_tcp_ulp_ops __read_mostly = { .release = bpf_tcp_release, }; +static int memcopy_from_iter(struct sock *sk, + struct sk_msg_buff *md, + struct iov_iter *from, int bytes) +{ + struct scatterlist *sg = md->sg_data; + int i = md->sg_curr, rc = -ENOSPC; + + do { + int copy; + char *to; + + if (md->sg_copybreak >= sg[i].length) { + md->sg_copybreak = 0; + + if (++i == MAX_SKB_FRAGS) + i = 0; + + if (i == md->sg_end) + break; + } + + copy = sg[i].length - md->sg_copybreak; + to = sg_virt(&sg[i]) + md->sg_copybreak; + md->sg_copybreak += copy; + + if (sk->sk_route_caps & NETIF_F_NOCACHE_COPY) + rc = copy_from_iter_nocache(to, copy, from); + else + rc = copy_from_iter(to, copy, from); + + if (rc != copy) { + rc = -EFAULT; + goto out; + } + + bytes -= copy; + if (!bytes) + break; + + md->sg_copybreak = 0; + if (++i == MAX_SKB_FRAGS) + i = 0; + } while (i != md->sg_end); +out: + md->sg_curr = i; + return rc; +} + +static int bpf_tcp_push(struct sock *sk, int apply_bytes, + struct sk_msg_buff *md, + int flags, bool uncharge) +{ + bool apply = apply_bytes; + struct scatterlist *sg; + int offset, ret = 0; + struct page *p; + size_t size; + + while (1) { + sg = md->sg_data + md->sg_start; + size = (apply && apply_bytes < sg->length) ? + apply_bytes : sg->length; + offset = sg->offset; + + tcp_rate_check_app_limited(sk); + p = sg_page(sg); +retry: + ret = do_tcp_sendpages(sk, p, offset, size, flags); + if (ret != size) { + if (ret > 0) { + if (apply) + apply_bytes -= ret; + size -= ret; + offset += ret; + if (uncharge) + sk_mem_uncharge(sk, ret); + goto retry; + } + + sg->length = size; + sg->offset = offset; + return ret; + } + + if (apply) + apply_bytes -= ret; + sg->offset += ret; + sg->length -= ret; + if (uncharge) + sk_mem_uncharge(sk, ret); + + if (!sg->length) { + put_page(p); + md->sg_start++; + if (md->sg_start == MAX_SKB_FRAGS) + md->sg_start = 0; + memset(sg, 0, sizeof(*sg)); + + if (md->sg_start == md->sg_end) + break; + } + + if (apply && !apply_bytes) + break; + } + return 0; +} + +static inline void bpf_compute_data_pointers_sg(struct sk_msg_buff *md) +{ + struct scatterlist *sg = md->sg_data + md->sg_start; + + if (md->sg_copy[md->sg_start]) { + md->data = md->data_end = 0; + } else { + md->data = sg_virt(sg); + md->data_end = md->data + sg->length; + } +} + +static void return_mem_sg(struct sock *sk, int bytes, struct sk_msg_buff *md) +{ + struct scatterlist *sg = md->sg_data; + int i = md->sg_start; + + do { + int uncharge = (bytes < sg[i].length) ? bytes : sg[i].length; + + sk_mem_uncharge(sk, uncharge); + bytes -= uncharge; + if (!bytes) + break; + i++; + if (i == MAX_SKB_FRAGS) + i = 0; + } while (i != md->sg_end); +} + +static void free_bytes_sg(struct sock *sk, int bytes, struct sk_msg_buff *md) +{ + struct scatterlist *sg = md->sg_data; + int i = md->sg_start, free; + + while (bytes && sg[i].length) { + free = sg[i].length; + if (bytes < free) { + sg[i].length -= bytes; + sg[i].offset += bytes; + sk_mem_uncharge(sk, bytes); + break; + } + + sk_mem_uncharge(sk, sg[i].length); + put_page(sg_page(&sg[i])); + bytes -= sg[i].length; + sg[i].length = 0; + sg[i].page_link = 0; + sg[i].offset = 0; + i++; + + if (i == MAX_SKB_FRAGS) + i = 0; + } +} + +static int free_sg(struct sock *sk, int start, struct sk_msg_buff *md) +{ + struct scatterlist *sg = md->sg_data; + int i = start, free = 0; + + while (sg[i].length) { + free += sg[i].length; + sk_mem_uncharge(sk, sg[i].length); + put_page(sg_page(&sg[i])); + sg[i].length = 0; + sg[i].page_link = 0; + sg[i].offset = 0; + i++; + + if (i == MAX_SKB_FRAGS) + i = 0; + } + + return free; +} + +static int free_start_sg(struct sock *sk, struct sk_msg_buff *md) +{ + int free = free_sg(sk, md->sg_start, md); + + md->sg_start = md->sg_end; + return free; +} + +static int free_curr_sg(struct sock *sk, struct sk_msg_buff *md) +{ + return free_sg(sk, md->sg_curr, md); +} + +static int bpf_map_msg_verdict(int _rc, struct sk_msg_buff *md) +{ + return ((_rc == SK_PASS) ? + (md->map ? __SK_REDIRECT : __SK_PASS) : + __SK_DROP); +} + +static unsigned int smap_do_tx_msg(struct sock *sk, + struct smap_psock *psock, + struct sk_msg_buff *md) +{ + struct bpf_prog *prog; + unsigned int rc, _rc; + + preempt_disable(); + rcu_read_lock(); + + /* If the policy was removed mid-send then default to 'accept' */ + prog = READ_ONCE(psock->bpf_tx_msg); + if (unlikely(!prog)) { + _rc = SK_PASS; + goto verdict; + } + + bpf_compute_data_pointers_sg(md); + rc = (*prog->bpf_func)(md, prog->insnsi); + psock->apply_bytes = md->apply_bytes; + + /* Moving return codes from UAPI namespace into internal namespace */ + _rc = bpf_map_msg_verdict(rc, md); + + /* The psock has a refcount on the sock but not on the map and because + * we need to drop rcu read lock here its possible the map could be + * removed between here and when we need it to execute the sock + * redirect. So do the map lookup now for future use. + */ + if (_rc == __SK_REDIRECT) { + if (psock->sk_redir) + sock_put(psock->sk_redir); + psock->sk_redir = do_msg_redirect_map(md); + if (!psock->sk_redir) { + _rc = __SK_DROP; + goto verdict; + } + sock_hold(psock->sk_redir); + } +verdict: + rcu_read_unlock(); + preempt_enable(); + + return _rc; +} + +static int bpf_tcp_sendmsg_do_redirect(struct sock *sk, int send, + struct sk_msg_buff *md, + int flags) +{ + struct smap_psock *psock; + struct scatterlist *sg; + int i, err, free = 0; + + sg = md->sg_data; + + rcu_read_lock(); + psock = smap_psock_sk(sk); + if (unlikely(!psock)) + goto out_rcu; + + if (!refcount_inc_not_zero(&psock->refcnt)) + goto out_rcu; + + rcu_read_unlock(); + lock_sock(sk); + err = bpf_tcp_push(sk, send, md, flags, false); + release_sock(sk); + smap_release_sock(psock, sk); + if (unlikely(err)) + goto out; + return 0; +out_rcu: + rcu_read_unlock(); +out: + i = md->sg_start; + while (sg[i].length) { + free += sg[i].length; + put_page(sg_page(&sg[i])); + sg[i].length = 0; + i++; + if (i == MAX_SKB_FRAGS) + i = 0; + } + return free; +} + +static inline void bpf_md_init(struct smap_psock *psock) +{ + if (!psock->apply_bytes) { + psock->eval = __SK_NONE; + if (psock->sk_redir) { + sock_put(psock->sk_redir); + psock->sk_redir = NULL; + } + } +} + +static void apply_bytes_dec(struct smap_psock *psock, int i) +{ + if (psock->apply_bytes) { + if (psock->apply_bytes < i) + psock->apply_bytes = 0; + else + psock->apply_bytes -= i; + } +} + +static int bpf_exec_tx_verdict(struct smap_psock *psock, + struct sk_msg_buff *m, + struct sock *sk, + int *copied, int flags) +{ + bool cork = false, enospc = (m->sg_start == m->sg_end); + struct sock *redir; + int err = 0; + int send; + +more_data: + if (psock->eval == __SK_NONE) + psock->eval = smap_do_tx_msg(sk, psock, m); + + if (m->cork_bytes && + m->cork_bytes > psock->sg_size && !enospc) { + psock->cork_bytes = m->cork_bytes - psock->sg_size; + if (!psock->cork) { + psock->cork = kcalloc(1, + sizeof(struct sk_msg_buff), + GFP_ATOMIC | __GFP_NOWARN); + + if (!psock->cork) { + err = -ENOMEM; + goto out_err; + } + } + memcpy(psock->cork, m, sizeof(*m)); + goto out_err; + } + + send = psock->sg_size; + if (psock->apply_bytes && psock->apply_bytes < send) + send = psock->apply_bytes; + + switch (psock->eval) { + case __SK_PASS: + err = bpf_tcp_push(sk, send, m, flags, true); + if (unlikely(err)) { + *copied -= free_start_sg(sk, m); + break; + } + + apply_bytes_dec(psock, send); + psock->sg_size -= send; + break; + case __SK_REDIRECT: + redir = psock->sk_redir; + apply_bytes_dec(psock, send); + + if (psock->cork) { + cork = true; + psock->cork = NULL; + } + + return_mem_sg(sk, send, m); + release_sock(sk); + + err = bpf_tcp_sendmsg_do_redirect(redir, send, m, flags); + lock_sock(sk); + + if (cork) { + free_start_sg(sk, m); + kfree(m); + m = NULL; + } + if (unlikely(err)) + *copied -= err; + else + psock->sg_size -= send; + break; + case __SK_DROP: + default: + free_bytes_sg(sk, send, m); + apply_bytes_dec(psock, send); + *copied -= send; + psock->sg_size -= send; + err = -EACCES; + break; + } + + if (likely(!err)) { + bpf_md_init(psock); + if (m && + m->sg_data[m->sg_start].page_link && + m->sg_data[m->sg_start].length) + goto more_data; + } + +out_err: + return err; +} + +static int bpf_tcp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) +{ + int flags = msg->msg_flags | MSG_NO_SHARED_FRAGS; + struct sk_msg_buff md = {0}; + unsigned int sg_copy = 0; + struct smap_psock *psock; + int copied = 0, err = 0; + struct scatterlist *sg; + long timeo; + + /* Its possible a sock event or user removed the psock _but_ the ops + * have not been reprogrammed yet so we get here. In this case fallback + * to tcp_sendmsg. Note this only works because we _only_ ever allow + * a single ULP there is no hierarchy here. + */ + rcu_read_lock(); + psock = smap_psock_sk(sk); + if (unlikely(!psock)) { + rcu_read_unlock(); + return tcp_sendmsg(sk, msg, size); + } + + /* Increment the psock refcnt to ensure its not released while sending a + * message. Required because sk lookup and bpf programs are used in + * separate rcu critical sections. Its OK if we lose the map entry + * but we can't lose the sock reference. + */ + if (!refcount_inc_not_zero(&psock->refcnt)) { + rcu_read_unlock(); + return tcp_sendmsg(sk, msg, size); + } + + sg = md.sg_data; + sg_init_table(sg, MAX_SKB_FRAGS); + rcu_read_unlock(); + + lock_sock(sk); + timeo = sock_sndtimeo(sk, msg->msg_flags & MSG_DONTWAIT); + + while (msg_data_left(msg)) { + struct sk_msg_buff *m; + bool enospc = false; + int copy; + + if (sk->sk_err) { + err = sk->sk_err; + goto out_err; + } + + copy = msg_data_left(msg); + if (!sk_stream_memory_free(sk)) + goto wait_for_sndbuf; + + m = psock->cork_bytes ? psock->cork : &md; + m->sg_curr = m->sg_copybreak ? m->sg_curr : m->sg_end; + err = sk_alloc_sg(sk, copy, m->sg_data, + m->sg_start, &m->sg_end, &sg_copy, + m->sg_end - 1); + if (err) { + if (err != -ENOSPC) + goto wait_for_memory; + enospc = true; + copy = sg_copy; + } + + err = memcopy_from_iter(sk, m, &msg->msg_iter, copy); + if (err < 0) { + free_curr_sg(sk, m); + goto out_err; + } + + psock->sg_size += copy; + copied += copy; + sg_copy = 0; + + /* When bytes are being corked skip running BPF program and + * applying verdict unless there is no more buffer space. In + * the ENOSPC case simply run BPF prorgram with currently + * accumulated data. We don't have much choice at this point + * we could try extending the page frags or chaining complex + * frags but even in these cases _eventually_ we will hit an + * OOM scenario. More complex recovery schemes may be + * implemented in the future, but BPF programs must handle + * the case where apply_cork requests are not honored. The + * canonical method to verify this is to check data length. + */ + if (psock->cork_bytes) { + if (copy > psock->cork_bytes) + psock->cork_bytes = 0; + else + psock->cork_bytes -= copy; + + if (psock->cork_bytes && !enospc) + goto out_cork; + + /* All cork bytes accounted for re-run filter */ + psock->eval = __SK_NONE; + psock->cork_bytes = 0; + } + + err = bpf_exec_tx_verdict(psock, m, sk, &copied, flags); + if (unlikely(err < 0)) + goto out_err; + continue; +wait_for_sndbuf: + set_bit(SOCK_NOSPACE, &sk->sk_socket->flags); +wait_for_memory: + err = sk_stream_wait_memory(sk, &timeo); + if (err) + goto out_err; + } +out_err: + if (err < 0) + err = sk_stream_error(sk, msg->msg_flags, err); +out_cork: + release_sock(sk); + smap_release_sock(psock, sk); + return copied ? copied : err; +} + +static int bpf_tcp_sendpage(struct sock *sk, struct page *page, + int offset, size_t size, int flags) +{ + struct sk_msg_buff md = {0}, *m = NULL; + int err = 0, copied = 0; + struct smap_psock *psock; + struct scatterlist *sg; + bool enospc = false; + + rcu_read_lock(); + psock = smap_psock_sk(sk); + if (unlikely(!psock)) + goto accept; + + if (!refcount_inc_not_zero(&psock->refcnt)) + goto accept; + rcu_read_unlock(); + + lock_sock(sk); + + if (psock->cork_bytes) + m = psock->cork; + else + m = &md; + + /* Catch case where ring is full and sendpage is stalled. */ + if (unlikely(m->sg_end == m->sg_start && + m->sg_data[m->sg_end].length)) + goto out_err; + + psock->sg_size += size; + sg = &m->sg_data[m->sg_end]; + sg_set_page(sg, page, size, offset); + get_page(page); + m->sg_copy[m->sg_end] = true; + sk_mem_charge(sk, size); + m->sg_end++; + copied = size; + + if (m->sg_end == MAX_SKB_FRAGS) + m->sg_end = 0; + + if (m->sg_end == m->sg_start) + enospc = true; + + if (psock->cork_bytes) { + if (size > psock->cork_bytes) + psock->cork_bytes = 0; + else + psock->cork_bytes -= size; + + if (psock->cork_bytes && !enospc) + goto out_err; + + /* All cork bytes accounted for re-run filter */ + psock->eval = __SK_NONE; + psock->cork_bytes = 0; + } + + err = bpf_exec_tx_verdict(psock, m, sk, &copied, flags); +out_err: + release_sock(sk); + smap_release_sock(psock, sk); + return copied ? copied : err; +accept: + rcu_read_unlock(); + return tcp_sendpage(sk, page, offset, size, flags); +} + +static void bpf_tcp_msg_add(struct smap_psock *psock, + struct sock *sk, + struct bpf_prog *tx_msg) +{ + struct bpf_prog *orig_tx_msg; + + orig_tx_msg = xchg(&psock->bpf_tx_msg, tx_msg); + if (orig_tx_msg) + bpf_prog_put(orig_tx_msg); +} + static int bpf_tcp_ulp_register(void) { tcp_bpf_proto = tcp_prot; tcp_bpf_proto.close = bpf_tcp_close; + /* Once BPF TX ULP is registered it is never unregistered. It + * will be in the ULP list for the lifetime of the system. Doing + * duplicate registers is not a problem. + */ return tcp_register_ulp(&bpf_tcp_ulp_ops); } @@ -412,7 +1054,6 @@ static int smap_parse_func_strparser(struct strparser *strp, return rc; } - static int smap_read_sock_done(struct strparser *strp, int err) { return err; @@ -482,12 +1123,22 @@ static void smap_gc_work(struct work_struct *w) bpf_prog_put(psock->bpf_parse); if (psock->bpf_verdict) bpf_prog_put(psock->bpf_verdict); + if (psock->bpf_tx_msg) + bpf_prog_put(psock->bpf_tx_msg); + + if (psock->cork) { + free_start_sg(psock->sock, psock->cork); + kfree(psock->cork); + } list_for_each_entry_safe(e, tmp, &psock->maps, list) { list_del(&e->list); kfree(e); } + if (psock->sk_redir) + sock_put(psock->sk_redir); + sock_put(psock->sock); kfree(psock); } @@ -503,6 +1154,7 @@ static struct smap_psock *smap_init_psock(struct sock *sock, if (!psock) return ERR_PTR(-ENOMEM); + psock->eval = __SK_NONE; psock->sock = sock; skb_queue_head_init(&psock->rxqueue); INIT_WORK(&psock->tx_work, smap_tx_work); @@ -711,10 +1363,11 @@ static int sock_map_ctx_update_elem(struct bpf_sock_ops_kern *skops, { struct bpf_stab *stab = container_of(map, struct bpf_stab, map); struct smap_psock_map_entry *e = NULL; - struct bpf_prog *verdict, *parse; + struct bpf_prog *verdict, *parse, *tx_msg; struct sock *osock, *sock; struct smap_psock *psock; u32 i = *(u32 *)key; + bool new = false; int err; if (unlikely(flags > BPF_EXIST)) @@ -737,6 +1390,7 @@ static int sock_map_ctx_update_elem(struct bpf_sock_ops_kern *skops, */ verdict = READ_ONCE(stab->bpf_verdict); parse = READ_ONCE(stab->bpf_parse); + tx_msg = READ_ONCE(stab->bpf_tx_msg); if (parse && verdict) { /* bpf prog refcnt may be zero if a concurrent attach operation @@ -755,6 +1409,17 @@ static int sock_map_ctx_update_elem(struct bpf_sock_ops_kern *skops, } } + if (tx_msg) { + tx_msg = bpf_prog_inc_not_zero(stab->bpf_tx_msg); + if (IS_ERR(tx_msg)) { + if (verdict) + bpf_prog_put(verdict); + if (parse) + bpf_prog_put(parse); + return PTR_ERR(tx_msg); + } + } + write_lock_bh(&sock->sk_callback_lock); psock = smap_psock_sk(sock); @@ -769,7 +1434,14 @@ static int sock_map_ctx_update_elem(struct bpf_sock_ops_kern *skops, err = -EBUSY; goto out_progs; } - refcount_inc(&psock->refcnt); + if (READ_ONCE(psock->bpf_tx_msg) && tx_msg) { + err = -EBUSY; + goto out_progs; + } + if (!refcount_inc_not_zero(&psock->refcnt)) { + err = -EAGAIN; + goto out_progs; + } } else { psock = smap_init_psock(sock, stab); if (IS_ERR(psock)) { @@ -777,11 +1449,8 @@ static int sock_map_ctx_update_elem(struct bpf_sock_ops_kern *skops, goto out_progs; } - err = tcp_set_ulp_id(sock, TCP_ULP_BPF); - if (err) - goto out_progs; - set_bit(SMAP_TX_RUNNING, &psock->state); + new = true; } e = kzalloc(sizeof(*e), GFP_ATOMIC | __GFP_NOWARN); @@ -794,6 +1463,14 @@ static int sock_map_ctx_update_elem(struct bpf_sock_ops_kern *skops, /* 3. At this point we have a reference to a valid psock that is * running. Attach any BPF programs needed. */ + if (tx_msg) + bpf_tcp_msg_add(psock, sock, tx_msg); + if (new) { + err = tcp_set_ulp_id(sock, TCP_ULP_BPF); + if (err) + goto out_free; + } + if (parse && verdict && !psock->strp_enabled) { err = smap_init_sock(psock, sock); if (err) @@ -815,8 +1492,6 @@ static int sock_map_ctx_update_elem(struct bpf_sock_ops_kern *skops, struct smap_psock *opsock = smap_psock_sk(osock); write_lock_bh(&osock->sk_callback_lock); - if (osock != sock && parse) - smap_stop_sock(opsock, osock); smap_list_remove(opsock, &stab->sock_map[i]); smap_release_sock(opsock, osock); write_unlock_bh(&osock->sk_callback_lock); @@ -829,6 +1504,8 @@ out_progs: bpf_prog_put(verdict); if (parse) bpf_prog_put(parse); + if (tx_msg) + bpf_prog_put(tx_msg); write_unlock_bh(&sock->sk_callback_lock); kfree(e); return err; @@ -843,6 +1520,9 @@ int sock_map_prog(struct bpf_map *map, struct bpf_prog *prog, u32 type) return -EINVAL; switch (type) { + case BPF_SK_MSG_VERDICT: + orig = xchg(&stab->bpf_tx_msg, prog); + break; case BPF_SK_SKB_STREAM_PARSER: orig = xchg(&stab->bpf_parse, prog); break; @@ -904,6 +1584,10 @@ static void sock_map_release(struct bpf_map *map, struct file *map_file) orig = xchg(&stab->bpf_verdict, NULL); if (orig) bpf_prog_put(orig); + + orig = xchg(&stab->bpf_tx_msg, NULL); + if (orig) + bpf_prog_put(orig); } const struct bpf_map_ops sock_map_ops = { diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c index e24aa3241387..3aeb4ea2a93a 100644 --- a/kernel/bpf/syscall.c +++ b/kernel/bpf/syscall.c @@ -1315,7 +1315,8 @@ static int bpf_obj_get(const union bpf_attr *attr) #define BPF_PROG_ATTACH_LAST_FIELD attach_flags -static int sockmap_get_from_fd(const union bpf_attr *attr, bool attach) +static int sockmap_get_from_fd(const union bpf_attr *attr, + int type, bool attach) { struct bpf_prog *prog = NULL; int ufd = attr->target_fd; @@ -1329,8 +1330,7 @@ static int sockmap_get_from_fd(const union bpf_attr *attr, bool attach) return PTR_ERR(map); if (attach) { - prog = bpf_prog_get_type(attr->attach_bpf_fd, - BPF_PROG_TYPE_SK_SKB); + prog = bpf_prog_get_type(attr->attach_bpf_fd, type); if (IS_ERR(prog)) { fdput(f); return PTR_ERR(prog); @@ -1382,9 +1382,11 @@ static int bpf_prog_attach(const union bpf_attr *attr) case BPF_CGROUP_DEVICE: ptype = BPF_PROG_TYPE_CGROUP_DEVICE; break; + case BPF_SK_MSG_VERDICT: + return sockmap_get_from_fd(attr, BPF_PROG_TYPE_SK_MSG, true); case BPF_SK_SKB_STREAM_PARSER: case BPF_SK_SKB_STREAM_VERDICT: - return sockmap_get_from_fd(attr, true); + return sockmap_get_from_fd(attr, BPF_PROG_TYPE_SK_SKB, true); default: return -EINVAL; } @@ -1437,9 +1439,11 @@ static int bpf_prog_detach(const union bpf_attr *attr) case BPF_CGROUP_DEVICE: ptype = BPF_PROG_TYPE_CGROUP_DEVICE; break; + case BPF_SK_MSG_VERDICT: + return sockmap_get_from_fd(attr, BPF_PROG_TYPE_SK_MSG, false); case BPF_SK_SKB_STREAM_PARSER: case BPF_SK_SKB_STREAM_VERDICT: - return sockmap_get_from_fd(attr, false); + return sockmap_get_from_fd(attr, BPF_PROG_TYPE_SK_SKB, false); default: return -EINVAL; } diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index eb79a34359c0..e9f7c20691c1 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -1248,6 +1248,7 @@ static bool may_access_direct_pkt_data(struct bpf_verifier_env *env, case BPF_PROG_TYPE_XDP: case BPF_PROG_TYPE_LWT_XMIT: case BPF_PROG_TYPE_SK_SKB: + case BPF_PROG_TYPE_SK_MSG: if (meta) return meta->pkt_access; @@ -2071,7 +2072,8 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, case BPF_MAP_TYPE_SOCKMAP: if (func_id != BPF_FUNC_sk_redirect_map && func_id != BPF_FUNC_sock_map_update && - func_id != BPF_FUNC_map_delete_elem) + func_id != BPF_FUNC_map_delete_elem && + func_id != BPF_FUNC_msg_redirect_map) goto error; break; default: @@ -2109,6 +2111,7 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, goto error; break; case BPF_FUNC_sk_redirect_map: + case BPF_FUNC_msg_redirect_map: if (map->map_type != BPF_MAP_TYPE_SOCKMAP) goto error; break; diff --git a/net/core/filter.c b/net/core/filter.c index 33edfa8372fd..2b6c47597eab 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -1890,6 +1890,44 @@ static const struct bpf_func_proto bpf_sk_redirect_map_proto = { .arg4_type = ARG_ANYTHING, }; +BPF_CALL_4(bpf_msg_redirect_map, struct sk_msg_buff *, msg, + struct bpf_map *, map, u32, key, u64, flags) +{ + /* If user passes invalid input drop the packet. */ + if (unlikely(flags)) + return SK_DROP; + + msg->key = key; + msg->flags = flags; + msg->map = map; + + return SK_PASS; +} + +struct sock *do_msg_redirect_map(struct sk_msg_buff *msg) +{ + struct sock *sk = NULL; + + if (msg->map) { + sk = __sock_map_lookup_elem(msg->map, msg->key); + + msg->key = 0; + msg->map = NULL; + } + + return sk; +} + +static const struct bpf_func_proto bpf_msg_redirect_map_proto = { + .func = bpf_msg_redirect_map, + .gpl_only = false, + .ret_type = RET_INTEGER, + .arg1_type = ARG_PTR_TO_CTX, + .arg2_type = ARG_CONST_MAP_PTR, + .arg3_type = ARG_ANYTHING, + .arg4_type = ARG_ANYTHING, +}; + BPF_CALL_1(bpf_get_cgroup_classid, const struct sk_buff *, skb) { return task_get_classid(skb); @@ -3591,6 +3629,16 @@ static const struct bpf_func_proto * } } +static const struct bpf_func_proto *sk_msg_func_proto(enum bpf_func_id func_id) +{ + switch (func_id) { + case BPF_FUNC_msg_redirect_map: + return &bpf_msg_redirect_map_proto; + default: + return bpf_base_func_proto(func_id); + } +} + static const struct bpf_func_proto *sk_skb_func_proto(enum bpf_func_id func_id) { switch (func_id) { @@ -3980,6 +4028,32 @@ static bool sk_skb_is_valid_access(int off, int size, return bpf_skb_is_valid_access(off, size, type, info); } +static bool sk_msg_is_valid_access(int off, int size, + enum bpf_access_type type, + struct bpf_insn_access_aux *info) +{ + if (type == BPF_WRITE) + return false; + + switch (off) { + case offsetof(struct sk_msg_md, data): + info->reg_type = PTR_TO_PACKET; + break; + case offsetof(struct sk_msg_md, data_end): + info->reg_type = PTR_TO_PACKET_END; + break; + } + + if (off < 0 || off >= sizeof(struct sk_msg_md)) + return false; + if (off % size != 0) + return false; + if (size != sizeof(__u64)) + return false; + + return true; +} + static u32 bpf_convert_ctx_access(enum bpf_access_type type, const struct bpf_insn *si, struct bpf_insn *insn_buf, @@ -4778,6 +4852,29 @@ static u32 sk_skb_convert_ctx_access(enum bpf_access_type type, return insn - insn_buf; } +static u32 sk_msg_convert_ctx_access(enum bpf_access_type type, + const struct bpf_insn *si, + struct bpf_insn *insn_buf, + struct bpf_prog *prog, u32 *target_size) +{ + struct bpf_insn *insn = insn_buf; + + switch (si->off) { + case offsetof(struct sk_msg_md, data): + *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_msg_buff, data), + si->dst_reg, si->src_reg, + offsetof(struct sk_msg_buff, data)); + break; + case offsetof(struct sk_msg_md, data_end): + *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_msg_buff, data_end), + si->dst_reg, si->src_reg, + offsetof(struct sk_msg_buff, data_end)); + break; + } + + return insn - insn_buf; +} + const struct bpf_verifier_ops sk_filter_verifier_ops = { .get_func_proto = sk_filter_func_proto, .is_valid_access = sk_filter_is_valid_access, @@ -4868,6 +4965,15 @@ const struct bpf_verifier_ops sk_skb_verifier_ops = { const struct bpf_prog_ops sk_skb_prog_ops = { }; +const struct bpf_verifier_ops sk_msg_verifier_ops = { + .get_func_proto = sk_msg_func_proto, + .is_valid_access = sk_msg_is_valid_access, + .convert_ctx_access = sk_msg_convert_ctx_access, +}; + +const struct bpf_prog_ops sk_msg_prog_ops = { +}; + int sk_detach_filter(struct sock *sk) { int ret = -ENOENT; -- cgit v1.2.3 From 751ba79cc552c146595cd439b21c4ff8998c3b69 Mon Sep 17 00:00:00 2001 From: Matt Brown Date: Fri, 4 Aug 2017 13:42:32 +1000 Subject: lib/raid6/altivec: Add vpermxor implementation for raid6 Q syndrome This patch uses the vpermxor instruction to optimise the raid6 Q syndrome. This instruction was made available with POWER8, ISA version 2.07. It allows for both vperm and vxor instructions to be done in a single instruction. This has been tested for correctness on a ppc64le vm with a basic RAID6 setup containing 5 drives. The performance benchmarks are from the raid6test in the /lib/raid6/test directory. These results are from an IBM Firestone machine with ppc64le architecture. The benchmark results show a 35% speed increase over the best existing algorithm for powerpc (altivec). The raid6test has also been run on a big-endian ppc64 vm to ensure it also works for big-endian architectures. Performance benchmarks: raid6: altivecx4 gen() 18773 MB/s raid6: altivecx8 gen() 19438 MB/s raid6: vpermxor4 gen() 25112 MB/s raid6: vpermxor8 gen() 26279 MB/s Signed-off-by: Matt Brown Reviewed-by: Daniel Axtens [mpe: Add VPERMXOR macro so we can build with old binutils] Signed-off-by: Michael Ellerman --- arch/powerpc/include/asm/ppc-opcode.h | 6 ++ include/linux/raid/pq.h | 4 ++ lib/raid6/.gitignore | 1 + lib/raid6/Makefile | 27 ++++++++- lib/raid6/algos.c | 4 ++ lib/raid6/test/Makefile | 17 +++++- lib/raid6/vpermxor.uc | 105 ++++++++++++++++++++++++++++++++++ 7 files changed, 161 insertions(+), 3 deletions(-) create mode 100644 lib/raid6/vpermxor.uc (limited to 'include/linux') diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index f1083bcf449c..7370da18035e 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -271,6 +271,7 @@ #define PPC_INST_TLBSRX_DOT 0x7c0006a5 #define PPC_INST_VPMSUMW 0x10000488 #define PPC_INST_VPMSUMD 0x100004c8 +#define PPC_INST_VPERMXOR 0x1000002d #define PPC_INST_XXLOR 0xf0000490 #define PPC_INST_XXSWAPD 0xf0000250 #define PPC_INST_XVCPSGNDP 0xf0000780 @@ -517,6 +518,11 @@ #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \ VSX_XX3((t), (a), (b)))) +#define VPERMXOR(vrt, vra, vrb, vrc) \ + stringify_in_c(.long (PPC_INST_VPERMXOR | \ + ___PPC_RT(vrt) | ___PPC_RA(vra) | \ + ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6))) + #define PPC_NAP stringify_in_c(.long PPC_INST_NAP) #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) #define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE) diff --git a/include/linux/raid/pq.h b/include/linux/raid/pq.h index 583cdd3d49ca..fd2e02461e41 100644 --- a/include/linux/raid/pq.h +++ b/include/linux/raid/pq.h @@ -107,6 +107,10 @@ extern const struct raid6_calls raid6_avx512x2; extern const struct raid6_calls raid6_avx512x4; extern const struct raid6_calls raid6_tilegx8; extern const struct raid6_calls raid6_s390vx8; +extern const struct raid6_calls raid6_vpermxor1; +extern const struct raid6_calls raid6_vpermxor2; +extern const struct raid6_calls raid6_vpermxor4; +extern const struct raid6_calls raid6_vpermxor8; struct raid6_recov_calls { void (*data2)(int, size_t, int, int, void **); diff --git a/lib/raid6/.gitignore b/lib/raid6/.gitignore index f01b1cb04f91..3de0d8921286 100644 --- a/lib/raid6/.gitignore +++ b/lib/raid6/.gitignore @@ -4,3 +4,4 @@ int*.c tables.c neon?.c s390vx?.c +vpermxor*.c diff --git a/lib/raid6/Makefile b/lib/raid6/Makefile index 4add700ddfe3..21f59443e99e 100644 --- a/lib/raid6/Makefile +++ b/lib/raid6/Makefile @@ -5,7 +5,8 @@ raid6_pq-y += algos.o recov.o tables.o int1.o int2.o int4.o \ int8.o int16.o int32.o raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o avx512.o recov_avx512.o -raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o +raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o \ + vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o raid6_pq-$(CONFIG_KERNEL_MODE_NEON) += neon.o neon1.o neon2.o neon4.o neon8.o recov_neon.o recov_neon_inner.o raid6_pq-$(CONFIG_TILEGX) += tilegx8.o raid6_pq-$(CONFIG_S390) += s390vx8.o recov_s390xc.o @@ -91,6 +92,30 @@ $(obj)/altivec8.c: UNROLL := 8 $(obj)/altivec8.c: $(src)/altivec.uc $(src)/unroll.awk FORCE $(call if_changed,unroll) +CFLAGS_vpermxor1.o += $(altivec_flags) +targets += vpermxor1.c +$(obj)/vpermxor1.c: UNROLL := 1 +$(obj)/vpermxor1.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE + $(call if_changed,unroll) + +CFLAGS_vpermxor2.o += $(altivec_flags) +targets += vpermxor2.c +$(obj)/vpermxor2.c: UNROLL := 2 +$(obj)/vpermxor2.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE + $(call if_changed,unroll) + +CFLAGS_vpermxor4.o += $(altivec_flags) +targets += vpermxor4.c +$(obj)/vpermxor4.c: UNROLL := 4 +$(obj)/vpermxor4.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE + $(call if_changed,unroll) + +CFLAGS_vpermxor8.o += $(altivec_flags) +targets += vpermxor8.c +$(obj)/vpermxor8.c: UNROLL := 8 +$(obj)/vpermxor8.c: $(src)/vpermxor.uc $(src)/unroll.awk FORCE + $(call if_changed,unroll) + CFLAGS_neon1.o += $(NEON_FLAGS) targets += neon1.c $(obj)/neon1.c: UNROLL := 1 diff --git a/lib/raid6/algos.c b/lib/raid6/algos.c index 476994723258..b2e681018145 100644 --- a/lib/raid6/algos.c +++ b/lib/raid6/algos.c @@ -74,6 +74,10 @@ const struct raid6_calls * const raid6_algos[] = { &raid6_altivec2, &raid6_altivec4, &raid6_altivec8, + &raid6_vpermxor1, + &raid6_vpermxor2, + &raid6_vpermxor4, + &raid6_vpermxor8, #endif #if defined(CONFIG_TILEGX) &raid6_tilegx8, diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile index be1010bdc435..ef6d0e00f189 100644 --- a/lib/raid6/test/Makefile +++ b/lib/raid6/test/Makefile @@ -48,7 +48,8 @@ else gcc -c -x c - >&/dev/null && \ rm ./-.o && echo yes) ifeq ($(HAS_ALTIVEC),yes) - OBJS += altivec1.o altivec2.o altivec4.o altivec8.o + OBJS += altivec1.o altivec2.o altivec4.o altivec8.o \ + vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o endif endif ifeq ($(ARCH),tilegx) @@ -98,6 +99,18 @@ altivec4.c: altivec.uc ../unroll.awk altivec8.c: altivec.uc ../unroll.awk $(AWK) ../unroll.awk -vN=8 < altivec.uc > $@ +vpermxor1.c: vpermxor.uc ../unroll.awk + $(AWK) ../unroll.awk -vN=1 < vpermxor.uc > $@ + +vpermxor2.c: vpermxor.uc ../unroll.awk + $(AWK) ../unroll.awk -vN=2 < vpermxor.uc > $@ + +vpermxor4.c: vpermxor.uc ../unroll.awk + $(AWK) ../unroll.awk -vN=4 < vpermxor.uc > $@ + +vpermxor8.c: vpermxor.uc ../unroll.awk + $(AWK) ../unroll.awk -vN=8 < vpermxor.uc > $@ + int1.c: int.uc ../unroll.awk $(AWK) ../unroll.awk -vN=1 < int.uc > $@ @@ -123,7 +136,7 @@ tables.c: mktables ./mktables > tables.c clean: - rm -f *.o *.a mktables mktables.c *.uc int*.c altivec*.c neon*.c tables.c raid6test + rm -f *.o *.a mktables mktables.c *.uc int*.c altivec*.c vpermxor*.c neon*.c tables.c raid6test rm -f tilegx*.c spotless: clean diff --git a/lib/raid6/vpermxor.uc b/lib/raid6/vpermxor.uc new file mode 100644 index 000000000000..10475dc423c1 --- /dev/null +++ b/lib/raid6/vpermxor.uc @@ -0,0 +1,105 @@ +/* + * Copyright 2017, Matt Brown, IBM Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * vpermxor$#.c + * + * Based on H. Peter Anvin's paper - The mathematics of RAID-6 + * + * $#-way unrolled portable integer math RAID-6 instruction set + * This file is postprocessed using unroll.awk + * + * vpermxor$#.c makes use of the vpermxor instruction to optimise the RAID6 Q + * syndrome calculations. + * This can be run on systems which have both Altivec and vpermxor instruction. + * + * This instruction was introduced in POWER8 - ISA v2.07. + */ + +#include +#ifdef CONFIG_ALTIVEC + +#include +#ifdef __KERNEL__ +#include +#include +#include +#endif + +typedef vector unsigned char unative_t; +#define NSIZE sizeof(unative_t) + +static const vector unsigned char gf_low = {0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, + 0x12, 0x10, 0x0e, 0x0c, 0x0a, 0x08, + 0x06, 0x04, 0x02,0x00}; +static const vector unsigned char gf_high = {0xfd, 0xdd, 0xbd, 0x9d, 0x7d, 0x5d, + 0x3d, 0x1d, 0xe0, 0xc0, 0xa0, 0x80, + 0x60, 0x40, 0x20, 0x00}; + +static void noinline raid6_vpermxor$#_gen_syndrome_real(int disks, size_t bytes, + void **ptrs) +{ + u8 **dptr = (u8 **)ptrs; + u8 *p, *q; + int d, z, z0; + unative_t wp$$, wq$$, wd$$; + + z0 = disks - 3; /* Highest data disk */ + p = dptr[z0+1]; /* XOR parity */ + q = dptr[z0+2]; /* RS syndrome */ + + for (d = 0; d < bytes; d += NSIZE*$#) { + wp$$ = wq$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; + + for (z = z0-1; z>=0; z--) { + wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE]; + /* P syndrome */ + wp$$ = vec_xor(wp$$, wd$$); + + /* Q syndrome */ + asm(VPERMXOR(%0,%1,%2,%3):"=v"(wq$$):"v"(gf_high), "v"(gf_low), "v"(wq$$)); + wq$$ = vec_xor(wq$$, wd$$); + } + *(unative_t *)&p[d+NSIZE*$$] = wp$$; + *(unative_t *)&q[d+NSIZE*$$] = wq$$; + } +} + +static void raid6_vpermxor$#_gen_syndrome(int disks, size_t bytes, void **ptrs) +{ + preempt_disable(); + enable_kernel_altivec(); + + raid6_vpermxor$#_gen_syndrome_real(disks, bytes, ptrs); + + disable_kernel_altivec(); + preempt_enable(); +} + +int raid6_have_altivec_vpermxor(void); +#if $# == 1 +int raid6_have_altivec_vpermxor(void) +{ + /* Check if arch has both altivec and the vpermxor instructions */ +# ifdef __KERNEL__ + return (cpu_has_feature(CPU_FTR_ALTIVEC_COMP) && + cpu_has_feature(CPU_FTR_ARCH_207S)); +# else + return 1; +#endif + +} +#endif + +const struct raid6_calls raid6_vpermxor$# = { + raid6_vpermxor$#_gen_syndrome, + NULL, + raid6_have_altivec_vpermxor, + "vpermxor$#", + 0 +}; +#endif -- cgit v1.2.3 From 7f65ea42eb00bc902f1c37a71e984e4f4064cfa9 Mon Sep 17 00:00:00 2001 From: Patrick Bellasi Date: Fri, 9 Mar 2018 09:52:42 +0000 Subject: sched/fair: Add util_est on top of PELT The util_avg signal computed by PELT is too variable for some use-cases. For example, a big task waking up after a long sleep period will have its utilization almost completely decayed. This introduces some latency before schedutil will be able to pick the best frequency to run a task. The same issue can affect task placement. Indeed, since the task utilization is already decayed at wakeup, when the task is enqueued in a CPU, this can result in a CPU running a big task as being temporarily represented as being almost empty. This leads to a race condition where other tasks can be potentially allocated on a CPU which just started to run a big task which slept for a relatively long period. Moreover, the PELT utilization of a task can be updated every [ms], thus making it a continuously changing value for certain longer running tasks. This means that the instantaneous PELT utilization of a RUNNING task is not really meaningful to properly support scheduler decisions. For all these reasons, a more stable signal can do a better job of representing the expected/estimated utilization of a task/cfs_rq. Such a signal can be easily created on top of PELT by still using it as an estimator which produces values to be aggregated on meaningful events. This patch adds a simple implementation of util_est, a new signal built on top of PELT's util_avg where: util_est(task) = max(task::util_avg, f(task::util_avg@dequeue)) This allows to remember how big a task has been reported by PELT in its previous activations via f(task::util_avg@dequeue), which is the new _task_util_est(struct task_struct*) function added by this patch. If a task should change its behavior and it runs longer in a new activation, after a certain time its util_est will just track the original PELT signal (i.e. task::util_avg). The estimated utilization of cfs_rq is defined only for root ones. That's because the only sensible consumer of this signal are the scheduler and schedutil when looking for the overall CPU utilization due to FAIR tasks. For this reason, the estimated utilization of a root cfs_rq is simply defined as: util_est(cfs_rq) = max(cfs_rq::util_avg, cfs_rq::util_est::enqueued) where: cfs_rq::util_est::enqueued = sum(_task_util_est(task)) for each RUNNABLE task on that root cfs_rq It's worth noting that the estimated utilization is tracked only for objects of interests, specifically: - Tasks: to better support tasks placement decisions - root cfs_rqs: to better support both tasks placement decisions as well as frequencies selection Signed-off-by: Patrick Bellasi Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Dietmar Eggemann Cc: Joel Fernandes Cc: Juri Lelli Cc: Linus Torvalds Cc: Morten Rasmussen Cc: Paul Turner Cc: Rafael J . Wysocki Cc: Steve Muckle Cc: Thomas Gleixner Cc: Todd Kjos Cc: Vincent Guittot Cc: Viresh Kumar Link: http://lkml.kernel.org/r/20180309095245.11071-2-patrick.bellasi@arm.com Signed-off-by: Ingo Molnar --- include/linux/sched.h | 29 ++++++++++++ kernel/sched/debug.c | 4 ++ kernel/sched/fair.c | 122 +++++++++++++++++++++++++++++++++++++++++++++--- kernel/sched/features.h | 5 ++ 4 files changed, 154 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sched.h b/include/linux/sched.h index 21b1168da951..f228c6033832 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -274,6 +274,34 @@ struct load_weight { u32 inv_weight; }; +/** + * struct util_est - Estimation utilization of FAIR tasks + * @enqueued: instantaneous estimated utilization of a task/cpu + * @ewma: the Exponential Weighted Moving Average (EWMA) + * utilization of a task + * + * Support data structure to track an Exponential Weighted Moving Average + * (EWMA) of a FAIR task's utilization. New samples are added to the moving + * average each time a task completes an activation. Sample's weight is chosen + * so that the EWMA will be relatively insensitive to transient changes to the + * task's workload. + * + * The enqueued attribute has a slightly different meaning for tasks and cpus: + * - task: the task's util_avg at last task dequeue time + * - cfs_rq: the sum of util_est.enqueued for each RUNNABLE task on that CPU + * Thus, the util_est.enqueued of a task represents the contribution on the + * estimated utilization of the CPU where that task is currently enqueued. + * + * Only for tasks we track a moving average of the past instantaneous + * estimated utilization. This allows to absorb sporadic drops in utilization + * of an otherwise almost periodic task. + */ +struct util_est { + unsigned int enqueued; + unsigned int ewma; +#define UTIL_EST_WEIGHT_SHIFT 2 +}; + /* * The load_avg/util_avg accumulates an infinite geometric series * (see __update_load_avg() in kernel/sched/fair.c). @@ -335,6 +363,7 @@ struct sched_avg { unsigned long load_avg; unsigned long runnable_load_avg; unsigned long util_avg; + struct util_est util_est; }; struct sched_statistics { diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c index 644d9a464380..332303be4beb 100644 --- a/kernel/sched/debug.c +++ b/kernel/sched/debug.c @@ -541,6 +541,8 @@ void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) cfs_rq->avg.runnable_load_avg); SEQ_printf(m, " .%-30s: %lu\n", "util_avg", cfs_rq->avg.util_avg); + SEQ_printf(m, " .%-30s: %u\n", "util_est_enqueued", + cfs_rq->avg.util_est.enqueued); SEQ_printf(m, " .%-30s: %ld\n", "removed.load_avg", cfs_rq->removed.load_avg); SEQ_printf(m, " .%-30s: %ld\n", "removed.util_avg", @@ -989,6 +991,8 @@ void proc_sched_show_task(struct task_struct *p, struct pid_namespace *ns, P(se.avg.runnable_load_avg); P(se.avg.util_avg); P(se.avg.last_update_time); + P(se.avg.util_est.ewma); + P(se.avg.util_est.enqueued); #endif P(policy); P(prio); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 3582117e1580..22b59a7facd2 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -3873,6 +3873,113 @@ static inline unsigned long cfs_rq_load_avg(struct cfs_rq *cfs_rq) static int idle_balance(struct rq *this_rq, struct rq_flags *rf); +static inline unsigned long task_util(struct task_struct *p) +{ + return READ_ONCE(p->se.avg.util_avg); +} + +static inline unsigned long _task_util_est(struct task_struct *p) +{ + struct util_est ue = READ_ONCE(p->se.avg.util_est); + + return max(ue.ewma, ue.enqueued); +} + +static inline unsigned long task_util_est(struct task_struct *p) +{ + return max(task_util(p), _task_util_est(p)); +} + +static inline void util_est_enqueue(struct cfs_rq *cfs_rq, + struct task_struct *p) +{ + unsigned int enqueued; + + if (!sched_feat(UTIL_EST)) + return; + + /* Update root cfs_rq's estimated utilization */ + enqueued = cfs_rq->avg.util_est.enqueued; + enqueued += _task_util_est(p); + WRITE_ONCE(cfs_rq->avg.util_est.enqueued, enqueued); +} + +/* + * Check if a (signed) value is within a specified (unsigned) margin, + * based on the observation that: + * + * abs(x) < y := (unsigned)(x + y - 1) < (2 * y - 1) + * + * NOTE: this only works when value + maring < INT_MAX. + */ +static inline bool within_margin(int value, int margin) +{ + return ((unsigned int)(value + margin - 1) < (2 * margin - 1)); +} + +static void +util_est_dequeue(struct cfs_rq *cfs_rq, struct task_struct *p, bool task_sleep) +{ + long last_ewma_diff; + struct util_est ue; + + if (!sched_feat(UTIL_EST)) + return; + + /* + * Update root cfs_rq's estimated utilization + * + * If *p is the last task then the root cfs_rq's estimated utilization + * of a CPU is 0 by definition. + */ + ue.enqueued = 0; + if (cfs_rq->nr_running) { + ue.enqueued = cfs_rq->avg.util_est.enqueued; + ue.enqueued -= min_t(unsigned int, ue.enqueued, + _task_util_est(p)); + } + WRITE_ONCE(cfs_rq->avg.util_est.enqueued, ue.enqueued); + + /* + * Skip update of task's estimated utilization when the task has not + * yet completed an activation, e.g. being migrated. + */ + if (!task_sleep) + return; + + /* + * Skip update of task's estimated utilization when its EWMA is + * already ~1% close to its last activation value. + */ + ue = p->se.avg.util_est; + ue.enqueued = task_util(p); + last_ewma_diff = ue.enqueued - ue.ewma; + if (within_margin(last_ewma_diff, (SCHED_CAPACITY_SCALE / 100))) + return; + + /* + * Update Task's estimated utilization + * + * When *p completes an activation we can consolidate another sample + * of the task size. This is done by storing the current PELT value + * as ue.enqueued and by using this value to update the Exponential + * Weighted Moving Average (EWMA): + * + * ewma(t) = w * task_util(p) + (1-w) * ewma(t-1) + * = w * task_util(p) + ewma(t-1) - w * ewma(t-1) + * = w * (task_util(p) - ewma(t-1)) + ewma(t-1) + * = w * ( last_ewma_diff ) + ewma(t-1) + * = w * (last_ewma_diff + ewma(t-1) / w) + * + * Where 'w' is the weight of new samples, which is configured to be + * 0.25, thus making w=1/4 ( >>= UTIL_EST_WEIGHT_SHIFT) + */ + ue.ewma <<= UTIL_EST_WEIGHT_SHIFT; + ue.ewma += last_ewma_diff; + ue.ewma >>= UTIL_EST_WEIGHT_SHIFT; + WRITE_ONCE(p->se.avg.util_est, ue); +} + #else /* CONFIG_SMP */ static inline int @@ -3902,6 +4009,13 @@ static inline int idle_balance(struct rq *rq, struct rq_flags *rf) return 0; } +static inline void +util_est_enqueue(struct cfs_rq *cfs_rq, struct task_struct *p) {} + +static inline void +util_est_dequeue(struct cfs_rq *cfs_rq, struct task_struct *p, + bool task_sleep) {} + #endif /* CONFIG_SMP */ static void check_spread(struct cfs_rq *cfs_rq, struct sched_entity *se) @@ -5249,6 +5363,7 @@ enqueue_task_fair(struct rq *rq, struct task_struct *p, int flags) if (!se) add_nr_running(rq, 1); + util_est_enqueue(&rq->cfs, p); hrtick_update(rq); } @@ -5308,6 +5423,7 @@ static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags) if (!se) sub_nr_running(rq, 1); + util_est_dequeue(&rq->cfs, p, task_sleep); hrtick_update(rq); } @@ -5835,7 +5951,6 @@ static int wake_affine(struct sched_domain *sd, struct task_struct *p, return target; } -static inline unsigned long task_util(struct task_struct *p); static unsigned long cpu_util_wake(int cpu, struct task_struct *p); static unsigned long capacity_spare_wake(int cpu, struct task_struct *p) @@ -6351,11 +6466,6 @@ static unsigned long cpu_util(int cpu) return (util >= capacity) ? capacity : util; } -static inline unsigned long task_util(struct task_struct *p) -{ - return p->se.avg.util_avg; -} - /* * cpu_util_wake: Compute CPU utilization with any contributions from * the waking task p removed. diff --git a/kernel/sched/features.h b/kernel/sched/features.h index 9552fd5854bf..c459a4b61544 100644 --- a/kernel/sched/features.h +++ b/kernel/sched/features.h @@ -85,3 +85,8 @@ SCHED_FEAT(ATTACH_AGE_LOAD, true) SCHED_FEAT(WA_IDLE, true) SCHED_FEAT(WA_WEIGHT, true) SCHED_FEAT(WA_BIAS, true) + +/* + * UtilEstimation. Use estimated CPU utilization. + */ +SCHED_FEAT(UTIL_EST, false) -- cgit v1.2.3 From 6b2bb7265f0b62605e8caee3613449ed0db270b9 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 15 Mar 2018 11:40:33 +0100 Subject: sched/wait: Introduce wait_var_event() As a replacement for the wait_on_atomic_t() API provide the wait_var_event() API. The wait_var_event() API is based on the very same hashed-waitqueue idea, but doesn't care about the type (atomic_t) or the specific condition (atomic_read() == 0). IOW. it's much more widely applicable/flexible. It shares all the benefits/disadvantages of a hashed-waitqueue approach with the existing wait_on_atomic_t/wait_on_bit() APIs. The API is modeled after the existing wait_event() API, but instead of taking a wait_queue_head, it takes an address. This addresses is hashed to obtain a wait_queue_head from the bit_wait_table. Similar to the wait_event() API, it takes a condition expression as second argument and will wait until this expression becomes true. The following are (mostly) identical replacements: wait_on_atomic_t(&my_atomic, atomic_t_wait, TASK_UNINTERRUPTIBLE); wake_up_atomic_t(&my_atomic); wait_var_event(&my_atomic, !atomic_read(&my_atomic)); wake_up_var(&my_atomic); The only difference is that wake_up_var() is an unconditional wakeup and doesn't check the previously hard-coded (atomic_read() == 0) condition here. This is of little concequence, since most callers are already conditional on atomic_dec_and_test() and the ones that are not, are trivial to make so. Tested-by: Dan Williams Signed-off-by: Peter Zijlstra (Intel) Cc: David Howells Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/wait_bit.h | 70 ++++++++++++++++++++++++++++++++++++++++++++++++ kernel/sched/wait_bit.c | 48 +++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) (limited to 'include/linux') diff --git a/include/linux/wait_bit.h b/include/linux/wait_bit.h index 61b39eaf7cad..3fcdb75d69cf 100644 --- a/include/linux/wait_bit.h +++ b/include/linux/wait_bit.h @@ -262,4 +262,74 @@ int wait_on_atomic_t(atomic_t *val, wait_atomic_t_action_f action, unsigned mode return out_of_line_wait_on_atomic_t(val, action, mode); } +extern void init_wait_var_entry(struct wait_bit_queue_entry *wbq_entry, void *var, int flags); +extern void wake_up_var(void *var); +extern wait_queue_head_t *__var_waitqueue(void *p); + +#define ___wait_var_event(var, condition, state, exclusive, ret, cmd) \ +({ \ + __label__ __out; \ + struct wait_queue_head *__wq_head = __var_waitqueue(var); \ + struct wait_bit_queue_entry __wbq_entry; \ + long __ret = ret; /* explicit shadow */ \ + \ + init_wait_var_entry(&__wbq_entry, var, \ + exclusive ? WQ_FLAG_EXCLUSIVE : 0); \ + for (;;) { \ + long __int = prepare_to_wait_event(__wq_head, \ + &__wbq_entry.wq_entry, \ + state); \ + if (condition) \ + break; \ + \ + if (___wait_is_interruptible(state) && __int) { \ + __ret = __int; \ + goto __out; \ + } \ + \ + cmd; \ + } \ + finish_wait(__wq_head, &__wbq_entry.wq_entry); \ +__out: __ret; \ +}) + +#define __wait_var_event(var, condition) \ + ___wait_var_event(var, condition, TASK_UNINTERRUPTIBLE, 0, 0, \ + schedule()) + +#define wait_var_event(var, condition) \ +do { \ + might_sleep(); \ + if (condition) \ + break; \ + __wait_var_event(var, condition); \ +} while (0) + +#define __wait_var_event_killable(var, condition) \ + ___wait_var_event(var, condition, TASK_KILLABLE, 0, 0, \ + schedule()) + +#define wait_var_event_killable(var, condition) \ +({ \ + int __ret = 0; \ + might_sleep(); \ + if (!(condition)) \ + __ret = __wait_var_event_killable(var, condition); \ + __ret; \ +}) + +#define __wait_var_event_timeout(var, condition, timeout) \ + ___wait_var_event(var, ___wait_cond_timeout(condition), \ + TASK_UNINTERRUPTIBLE, 0, timeout, \ + __ret = schedule_timeout(__ret)) + +#define wait_var_event_timeout(var, condition, timeout) \ +({ \ + long __ret = timeout; \ + might_sleep(); \ + if (!___wait_cond_timeout(condition)) \ + __ret = __wait_var_event_timeout(var, condition, timeout); \ + __ret; \ +}) + #endif /* _LINUX_WAIT_BIT_H */ diff --git a/kernel/sched/wait_bit.c b/kernel/sched/wait_bit.c index 4239c78f5cd3..ed84ab245a05 100644 --- a/kernel/sched/wait_bit.c +++ b/kernel/sched/wait_bit.c @@ -149,6 +149,54 @@ void wake_up_bit(void *word, int bit) } EXPORT_SYMBOL(wake_up_bit); +wait_queue_head_t *__var_waitqueue(void *p) +{ + if (BITS_PER_LONG == 64) { + unsigned long q = (unsigned long)p; + + return bit_waitqueue((void *)(q & ~1), q & 1); + } + return bit_waitqueue(p, 0); +} +EXPORT_SYMBOL(__var_waitqueue); + +static int +var_wake_function(struct wait_queue_entry *wq_entry, unsigned int mode, + int sync, void *arg) +{ + struct wait_bit_key *key = arg; + struct wait_bit_queue_entry *wbq_entry = + container_of(wq_entry, struct wait_bit_queue_entry, wq_entry); + + if (wbq_entry->key.flags != key->flags || + wbq_entry->key.bit_nr != key->bit_nr) + return 0; + + return autoremove_wake_function(wq_entry, mode, sync, key); +} + +void init_wait_var_entry(struct wait_bit_queue_entry *wbq_entry, void *var, int flags) +{ + *wbq_entry = (struct wait_bit_queue_entry){ + .key = { + .flags = (var), + .bit_nr = -1, + }, + .wq_entry = { + .private = current, + .func = var_wake_function, + .entry = LIST_HEAD_INIT(wbq_entry->wq_entry.entry), + }, + }; +} +EXPORT_SYMBOL(init_wait_var_entry); + +void wake_up_var(void *var) +{ + __wake_up_bit(__var_waitqueue(var), var, -1); +} +EXPORT_SYMBOL(wake_up_var); + /* * Manipulate the atomic_t address to produce a better bit waitqueue table hash * index (we're keying off bit -1, but that would produce a horrible hash -- cgit v1.2.3 From dc5d4afbb0bf7b7746ff5e56e1a5688ad7f29b32 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 15 Mar 2018 11:43:43 +0100 Subject: sched/wait, fs/fscache: Convert wait_on_atomic_t() usage to the new wait_var_event() API The old wait_on_atomic_t() is going to get removed, use the more flexible wait_var_event() API instead. No change in functionality. Signed-off-by: Peter Zijlstra (Intel) Cc: David Howells Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- fs/fscache/cookie.c | 7 ++++--- include/linux/fscache-cache.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/fs/fscache/cookie.c b/fs/fscache/cookie.c index ff84258132bb..d705125665f0 100644 --- a/fs/fscache/cookie.c +++ b/fs/fscache/cookie.c @@ -557,9 +557,10 @@ void __fscache_disable_cookie(struct fscache_cookie *cookie, bool invalidate) * n_active reaches 0). This makes sure outstanding reads and writes * have completed. */ - if (!atomic_dec_and_test(&cookie->n_active)) - wait_on_atomic_t(&cookie->n_active, atomic_t_wait, - TASK_UNINTERRUPTIBLE); + if (!atomic_dec_and_test(&cookie->n_active)) { + wait_var_event(&cookie->n_active, + !atomic_read(&cookie->n_active)); + } /* Make sure any pending writes are cancelled. */ if (cookie->def->type != FSCACHE_COOKIE_TYPE_INDEX) diff --git a/include/linux/fscache-cache.h b/include/linux/fscache-cache.h index 4c467ef50159..3b03e29e2f1a 100644 --- a/include/linux/fscache-cache.h +++ b/include/linux/fscache-cache.h @@ -496,7 +496,7 @@ static inline bool __fscache_unuse_cookie(struct fscache_cookie *cookie) static inline void __fscache_wake_unused_cookie(struct fscache_cookie *cookie) { - wake_up_atomic_t(&cookie->n_active); + wake_up_var(&cookie->n_active); } /** -- cgit v1.2.3 From 9b8cce52c4b5c08297900bfdcafc6b08d9bc4a27 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 15 Mar 2018 11:46:30 +0100 Subject: sched/wait: Remove the wait_on_atomic_t() API There are no users left (everyone got converted to wait_var_event()), remove it. Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Mike Galbraith Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- include/linux/wait_bit.h | 27 ------------- kernel/sched/wait_bit.c | 101 ----------------------------------------------- 2 files changed, 128 deletions(-) (limited to 'include/linux') diff --git a/include/linux/wait_bit.h b/include/linux/wait_bit.h index 3fcdb75d69cf..9318b2166439 100644 --- a/include/linux/wait_bit.h +++ b/include/linux/wait_bit.h @@ -10,7 +10,6 @@ struct wait_bit_key { void *flags; int bit_nr; -#define WAIT_ATOMIC_T_BIT_NR -1 unsigned long timeout; }; @@ -22,21 +21,15 @@ struct wait_bit_queue_entry { #define __WAIT_BIT_KEY_INITIALIZER(word, bit) \ { .flags = word, .bit_nr = bit, } -#define __WAIT_ATOMIC_T_KEY_INITIALIZER(p) \ - { .flags = p, .bit_nr = WAIT_ATOMIC_T_BIT_NR, } - typedef int wait_bit_action_f(struct wait_bit_key *key, int mode); -typedef int wait_atomic_t_action_f(atomic_t *counter, unsigned int mode); void __wake_up_bit(struct wait_queue_head *wq_head, void *word, int bit); int __wait_on_bit(struct wait_queue_head *wq_head, struct wait_bit_queue_entry *wbq_entry, wait_bit_action_f *action, unsigned int mode); int __wait_on_bit_lock(struct wait_queue_head *wq_head, struct wait_bit_queue_entry *wbq_entry, wait_bit_action_f *action, unsigned int mode); void wake_up_bit(void *word, int bit); -void wake_up_atomic_t(atomic_t *p); int out_of_line_wait_on_bit(void *word, int, wait_bit_action_f *action, unsigned int mode); int out_of_line_wait_on_bit_timeout(void *word, int, wait_bit_action_f *action, unsigned int mode, unsigned long timeout); int out_of_line_wait_on_bit_lock(void *word, int, wait_bit_action_f *action, unsigned int mode); -int out_of_line_wait_on_atomic_t(atomic_t *p, wait_atomic_t_action_f action, unsigned int mode); struct wait_queue_head *bit_waitqueue(void *word, int bit); extern void __init wait_bit_init(void); @@ -57,7 +50,6 @@ extern int bit_wait(struct wait_bit_key *key, int mode); extern int bit_wait_io(struct wait_bit_key *key, int mode); extern int bit_wait_timeout(struct wait_bit_key *key, int mode); extern int bit_wait_io_timeout(struct wait_bit_key *key, int mode); -extern int atomic_t_wait(atomic_t *counter, unsigned int mode); /** * wait_on_bit - wait for a bit to be cleared @@ -243,25 +235,6 @@ wait_on_bit_lock_action(unsigned long *word, int bit, wait_bit_action_f *action, return out_of_line_wait_on_bit_lock(word, bit, action, mode); } -/** - * wait_on_atomic_t - Wait for an atomic_t to become 0 - * @val: The atomic value being waited on, a kernel virtual address - * @action: the function used to sleep, which may take special actions - * @mode: the task state to sleep in - * - * Wait for an atomic_t to become 0. We abuse the bit-wait waitqueue table for - * the purpose of getting a waitqueue, but we set the key to a bit number - * outside of the target 'word'. - */ -static inline -int wait_on_atomic_t(atomic_t *val, wait_atomic_t_action_f action, unsigned mode) -{ - might_sleep(); - if (atomic_read(val) == 0) - return 0; - return out_of_line_wait_on_atomic_t(val, action, mode); -} - extern void init_wait_var_entry(struct wait_bit_queue_entry *wbq_entry, void *var, int flags); extern void wake_up_var(void *var); extern wait_queue_head_t *__var_waitqueue(void *p); diff --git a/kernel/sched/wait_bit.c b/kernel/sched/wait_bit.c index ed84ab245a05..60a84f5a6cb4 100644 --- a/kernel/sched/wait_bit.c +++ b/kernel/sched/wait_bit.c @@ -197,107 +197,6 @@ void wake_up_var(void *var) } EXPORT_SYMBOL(wake_up_var); -/* - * Manipulate the atomic_t address to produce a better bit waitqueue table hash - * index (we're keying off bit -1, but that would produce a horrible hash - * value). - */ -static inline wait_queue_head_t *atomic_t_waitqueue(atomic_t *p) -{ - if (BITS_PER_LONG == 64) { - unsigned long q = (unsigned long)p; - - return bit_waitqueue((void *)(q & ~1), q & 1); - } - return bit_waitqueue(p, 0); -} - -static int wake_atomic_t_function(struct wait_queue_entry *wq_entry, unsigned mode, int sync, - void *arg) -{ - struct wait_bit_key *key = arg; - struct wait_bit_queue_entry *wait_bit = container_of(wq_entry, struct wait_bit_queue_entry, wq_entry); - atomic_t *val = key->flags; - - if (wait_bit->key.flags != key->flags || - wait_bit->key.bit_nr != key->bit_nr || - atomic_read(val) != 0) - return 0; - - return autoremove_wake_function(wq_entry, mode, sync, key); -} - -/* - * To allow interruptible waiting and asynchronous (i.e. nonblocking) waiting, - * the actions of __wait_on_atomic_t() are permitted return codes. Nonzero - * return codes halt waiting and return. - */ -static __sched -int __wait_on_atomic_t(struct wait_queue_head *wq_head, struct wait_bit_queue_entry *wbq_entry, - wait_atomic_t_action_f action, unsigned int mode) -{ - atomic_t *val; - int ret = 0; - - do { - prepare_to_wait(wq_head, &wbq_entry->wq_entry, mode); - val = wbq_entry->key.flags; - if (atomic_read(val) == 0) - break; - ret = (*action)(val, mode); - } while (!ret && atomic_read(val) != 0); - finish_wait(wq_head, &wbq_entry->wq_entry); - - return ret; -} - -#define DEFINE_WAIT_ATOMIC_T(name, p) \ - struct wait_bit_queue_entry name = { \ - .key = __WAIT_ATOMIC_T_KEY_INITIALIZER(p), \ - .wq_entry = { \ - .private = current, \ - .func = wake_atomic_t_function, \ - .entry = \ - LIST_HEAD_INIT((name).wq_entry.entry), \ - }, \ - } - -__sched int out_of_line_wait_on_atomic_t(atomic_t *p, - wait_atomic_t_action_f action, - unsigned int mode) -{ - struct wait_queue_head *wq_head = atomic_t_waitqueue(p); - DEFINE_WAIT_ATOMIC_T(wq_entry, p); - - return __wait_on_atomic_t(wq_head, &wq_entry, action, mode); -} -EXPORT_SYMBOL(out_of_line_wait_on_atomic_t); - -__sched int atomic_t_wait(atomic_t *counter, unsigned int mode) -{ - schedule(); - if (signal_pending_state(mode, current)) - return -EINTR; - - return 0; -} -EXPORT_SYMBOL(atomic_t_wait); - -/** - * wake_up_atomic_t - Wake up a waiter on a atomic_t - * @p: The atomic_t being waited on, a kernel virtual address - * - * Wake up anyone waiting for the atomic_t to go to zero. - * - * Abuse the bit-waker function and its waitqueue hash table set (the atomic_t - * check is done by the waiter's wake function, not the by the waker itself). - */ -void wake_up_atomic_t(atomic_t *p) -{ - __wake_up_bit(atomic_t_waitqueue(p), p, WAIT_ATOMIC_T_BIT_NR); -} -EXPORT_SYMBOL(wake_up_atomic_t); - __sched int bit_wait(struct wait_bit_key *word, int mode) { schedule(); -- cgit v1.2.3 From 578ae447e7e5d78c90ac40a06406c1741f79ba96 Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Mon, 19 Mar 2018 13:18:57 -0500 Subject: jump_label: Disable jump labels in __exit code With the following commit: 333522447063 ("jump_label: Explicitly disable jump labels in __init code") ... we explicitly disabled jump labels in __init code, so they could be detected and not warned about in the following commit: dc1dd184c2f0 ("jump_label: Warn on failed jump_label patching attempt") In-kernel __exit code has the same issue. It's never used, so it's freed along with the rest of initmem. But jump label entries in __exit code aren't explicitly disabled, so we get the following warning when enabling pr_debug() in __exit code: can't patch jump_label at dmi_sysfs_exit+0x0/0x2d WARNING: CPU: 0 PID: 22572 at kernel/jump_label.c:376 __jump_label_update+0x9d/0xb0 Fix the warning by disabling all jump labels in initmem (which includes both __init and __exit code). Reported-and-tested-by: Li Wang Signed-off-by: Josh Poimboeuf Cc: Borislav Petkov Cc: Jason Baron Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: dc1dd184c2f0 ("jump_label: Warn on failed jump_label patching attempt") Link: http://lkml.kernel.org/r/7121e6e595374f06616c505b6e690e275c0054d1.1521483452.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar --- include/linux/jump_label.h | 4 ++-- init/main.c | 2 +- kernel/jump_label.c | 7 ++++--- 3 files changed, 7 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/jump_label.h b/include/linux/jump_label.h index 2168cc6b8b30..b46b541c67c4 100644 --- a/include/linux/jump_label.h +++ b/include/linux/jump_label.h @@ -151,7 +151,7 @@ extern struct jump_entry __start___jump_table[]; extern struct jump_entry __stop___jump_table[]; extern void jump_label_init(void); -extern void jump_label_invalidate_init(void); +extern void jump_label_invalidate_initmem(void); extern void jump_label_lock(void); extern void jump_label_unlock(void); extern void arch_jump_label_transform(struct jump_entry *entry, @@ -199,7 +199,7 @@ static __always_inline void jump_label_init(void) static_key_initialized = true; } -static inline void jump_label_invalidate_init(void) {} +static inline void jump_label_invalidate_initmem(void) {} static __always_inline bool static_key_false(struct static_key *key) { diff --git a/init/main.c b/init/main.c index 969eaf140ef0..21efbf6ace93 100644 --- a/init/main.c +++ b/init/main.c @@ -1001,7 +1001,7 @@ static int __ref kernel_init(void *unused) /* need to finish all async __init code before freeing the memory */ async_synchronize_full(); ftrace_free_init_mem(); - jump_label_invalidate_init(); + jump_label_invalidate_initmem(); free_initmem(); mark_readonly(); system_state = SYSTEM_RUNNING; diff --git a/kernel/jump_label.c b/kernel/jump_label.c index e7214093dcd1..01ebdf1f9f40 100644 --- a/kernel/jump_label.c +++ b/kernel/jump_label.c @@ -16,6 +16,7 @@ #include #include #include +#include #ifdef HAVE_JUMP_LABEL @@ -421,15 +422,15 @@ void __init jump_label_init(void) cpus_read_unlock(); } -/* Disable any jump label entries in __init code */ -void __init jump_label_invalidate_init(void) +/* Disable any jump label entries in __init/__exit code */ +void __init jump_label_invalidate_initmem(void) { struct jump_entry *iter_start = __start___jump_table; struct jump_entry *iter_stop = __stop___jump_table; struct jump_entry *iter; for (iter = iter_start; iter < iter_stop; iter++) { - if (init_kernel_text(iter->code)) + if (init_section_contains((void *)(unsigned long)iter->code, 1)) iter->code = 0; } } -- cgit v1.2.3 From b958758e686aebe84672acc8871aca87d04f13a3 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Mar 2018 14:47:19 +0100 Subject: mtd: rawnand: rename SET/GET FEATURES related functions SET/GET FEATURES are flagged ONFI-compliant because of their name. This is not accurate as non-ONFI NAND chips support it and use it. Rename the hooks and helpers to remove the "onfi" prefix. Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c | 4 +-- drivers/mtd/nand/raw/cafe_nand.c | 4 +-- drivers/mtd/nand/raw/docg4.c | 4 +-- drivers/mtd/nand/raw/fsl_elbc_nand.c | 4 +-- drivers/mtd/nand/raw/fsl_ifc_nand.c | 4 +-- drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c | 8 ++--- drivers/mtd/nand/raw/hisi504_nand.c | 4 +-- drivers/mtd/nand/raw/mpc5121_nfc.c | 4 +-- drivers/mtd/nand/raw/mxc_nand.c | 14 ++++---- drivers/mtd/nand/raw/nand_base.c | 42 +++++++++++------------- drivers/mtd/nand/raw/nand_micron.c | 16 ++++----- drivers/mtd/nand/raw/qcom_nandc.c | 4 +-- drivers/mtd/nand/raw/sh_flctl.c | 4 +-- drivers/staging/mt29f_spinand/mt29f_spinand.c | 4 +-- include/linux/mtd/rawnand.h | 17 +++++----- 15 files changed, 66 insertions(+), 71 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c index 54bac5b73f0a..60874de430eb 100644 --- a/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c +++ b/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c @@ -392,8 +392,8 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte; b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf; b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf; - b47n->nand_chip.onfi_set_features = nand_onfi_get_set_features_notsupp; - b47n->nand_chip.onfi_get_features = nand_onfi_get_set_features_notsupp; + b47n->nand_chip.set_features = nand_get_set_features_notsupp; + b47n->nand_chip.get_features = nand_get_set_features_notsupp; nand_chip->chip_delay = 50; b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH; diff --git a/drivers/mtd/nand/raw/cafe_nand.c b/drivers/mtd/nand/raw/cafe_nand.c index 37cfae2761d4..3c1b6a3786b2 100644 --- a/drivers/mtd/nand/raw/cafe_nand.c +++ b/drivers/mtd/nand/raw/cafe_nand.c @@ -645,8 +645,8 @@ static int cafe_nand_probe(struct pci_dev *pdev, cafe->nand.read_buf = cafe_read_buf; cafe->nand.write_buf = cafe_write_buf; cafe->nand.select_chip = cafe_select_chip; - cafe->nand.onfi_set_features = nand_onfi_get_set_features_notsupp; - cafe->nand.onfi_get_features = nand_onfi_get_set_features_notsupp; + cafe->nand.set_features = nand_get_set_features_notsupp; + cafe->nand.get_features = nand_get_set_features_notsupp; cafe->nand.chip_delay = 0; diff --git a/drivers/mtd/nand/raw/docg4.c b/drivers/mtd/nand/raw/docg4.c index 72f1327c4430..1314aa99b9ab 100644 --- a/drivers/mtd/nand/raw/docg4.c +++ b/drivers/mtd/nand/raw/docg4.c @@ -1269,8 +1269,8 @@ static void __init init_mtd_structs(struct mtd_info *mtd) nand->read_buf = docg4_read_buf; nand->write_buf = docg4_write_buf16; nand->erase = docg4_erase_block; - nand->onfi_set_features = nand_onfi_get_set_features_notsupp; - nand->onfi_get_features = nand_onfi_get_set_features_notsupp; + nand->set_features = nand_get_set_features_notsupp; + nand->get_features = nand_get_set_features_notsupp; nand->ecc.read_page = docg4_read_page; nand->ecc.write_page = docg4_write_page; nand->ecc.read_page_raw = docg4_read_page_raw; diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index 84f7d6a94be7..d28df991c73c 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -775,8 +775,8 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) chip->select_chip = fsl_elbc_select_chip; chip->cmdfunc = fsl_elbc_cmdfunc; chip->waitfunc = fsl_elbc_wait; - chip->onfi_set_features = nand_onfi_get_set_features_notsupp; - chip->onfi_get_features = nand_onfi_get_set_features_notsupp; + chip->set_features = nand_get_set_features_notsupp; + chip->get_features = nand_get_set_features_notsupp; chip->bbt_td = &bbt_main_descr; chip->bbt_md = &bbt_mirror_descr; diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index 4f0bbc8a803d..7ca678f05ae3 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -838,8 +838,8 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) chip->select_chip = fsl_ifc_select_chip; chip->cmdfunc = fsl_ifc_cmdfunc; chip->waitfunc = fsl_ifc_wait; - chip->onfi_set_features = nand_onfi_get_set_features_notsupp; - chip->onfi_get_features = nand_onfi_get_set_features_notsupp; + chip->set_features = nand_get_set_features_notsupp; + chip->get_features = nand_get_set_features_notsupp; chip->bbt_td = &bbt_main_descr; chip->bbt_md = &bbt_mirror_descr; diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c index 97787246af41..f78d907ca61e 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c @@ -934,15 +934,15 @@ static int enable_edo_mode(struct gpmi_nand_data *this, int mode) /* [1] send SET FEATURE command to NAND */ feature[0] = mode; - ret = nand->onfi_set_features(mtd, nand, - ONFI_FEATURE_ADDR_TIMING_MODE, feature); + ret = nand->set_features(mtd, nand, + ONFI_FEATURE_ADDR_TIMING_MODE, feature); if (ret) goto err_out; /* [2] send GET FEATURE command to double-check the timing mode */ memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN); - ret = nand->onfi_get_features(mtd, nand, - ONFI_FEATURE_ADDR_TIMING_MODE, feature); + ret = nand->get_features(mtd, nand, + ONFI_FEATURE_ADDR_TIMING_MODE, feature); if (ret || feature[0] != mode) goto err_out; diff --git a/drivers/mtd/nand/raw/hisi504_nand.c b/drivers/mtd/nand/raw/hisi504_nand.c index cb862793ab6d..27558a67fa41 100644 --- a/drivers/mtd/nand/raw/hisi504_nand.c +++ b/drivers/mtd/nand/raw/hisi504_nand.c @@ -762,8 +762,8 @@ static int hisi_nfc_probe(struct platform_device *pdev) chip->write_buf = hisi_nfc_write_buf; chip->read_buf = hisi_nfc_read_buf; chip->chip_delay = HINFC504_CHIP_DELAY; - chip->onfi_set_features = nand_onfi_get_set_features_notsupp; - chip->onfi_get_features = nand_onfi_get_set_features_notsupp; + chip->set_features = nand_get_set_features_notsupp; + chip->get_features = nand_get_set_features_notsupp; hisi_nfc_host_init(host); diff --git a/drivers/mtd/nand/raw/mpc5121_nfc.c b/drivers/mtd/nand/raw/mpc5121_nfc.c index 913b9d1225c6..6d1740d54e0d 100644 --- a/drivers/mtd/nand/raw/mpc5121_nfc.c +++ b/drivers/mtd/nand/raw/mpc5121_nfc.c @@ -707,8 +707,8 @@ static int mpc5121_nfc_probe(struct platform_device *op) chip->read_buf = mpc5121_nfc_read_buf; chip->write_buf = mpc5121_nfc_write_buf; chip->select_chip = mpc5121_nfc_select_chip; - chip->onfi_set_features = nand_onfi_get_set_features_notsupp; - chip->onfi_get_features = nand_onfi_get_set_features_notsupp; + chip->set_features = nand_get_set_features_notsupp; + chip->get_features = nand_get_set_features_notsupp; chip->bbt_options = NAND_BBT_USE_FLASH; chip->ecc.mode = NAND_ECC_SOFT; chip->ecc.algo = NAND_ECC_HAMMING; diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 87b5ee66e501..61501654e708 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1421,9 +1421,8 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, } } -static int mxc_nand_onfi_set_features(struct mtd_info *mtd, - struct nand_chip *chip, int addr, - u8 *subfeature_param) +static int mxc_nand_set_features(struct mtd_info *mtd, struct nand_chip *chip, + int addr, u8 *subfeature_param) { struct nand_chip *nand_chip = mtd_to_nand(mtd); struct mxc_nand_host *host = nand_get_controller_data(nand_chip); @@ -1447,9 +1446,8 @@ static int mxc_nand_onfi_set_features(struct mtd_info *mtd, return 0; } -static int mxc_nand_onfi_get_features(struct mtd_info *mtd, - struct nand_chip *chip, int addr, - u8 *subfeature_param) +static int mxc_nand_get_features(struct mtd_info *mtd, struct nand_chip *chip, + int addr, u8 *subfeature_param) { struct nand_chip *nand_chip = mtd_to_nand(mtd); struct mxc_nand_host *host = nand_get_controller_data(nand_chip); @@ -1752,8 +1750,8 @@ static int mxcnd_probe(struct platform_device *pdev) this->read_word = mxc_nand_read_word; this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; - this->onfi_set_features = mxc_nand_onfi_set_features; - this->onfi_get_features = mxc_nand_onfi_get_features; + this->set_features = mxc_nand_set_features; + this->get_features = mxc_nand_get_features; host->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(host->clk)) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index d1d5e2281860..802cd9ed44a1 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -349,7 +349,7 @@ static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) * 8-bits of the data bus. During address transfers, the host shall * set the upper 8-bits of the data bus to 00h. * - * One user of the write_byte callback is nand_onfi_set_features. The + * One user of the write_byte callback is nand_set_features. The * four parameters are specified to be written to I/O[7:0], but this is * neither an address nor a command transfer. Let's assume a 0 on the * upper I/O lines is OK. @@ -1231,9 +1231,9 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) chip->onfi_timing_mode_default, }; - ret = chip->onfi_set_features(mtd, chip, - ONFI_FEATURE_ADDR_TIMING_MODE, - tmode_param); + ret = chip->set_features(mtd, chip, + ONFI_FEATURE_ADDR_TIMING_MODE, + tmode_param); if (ret) goto err; } @@ -4769,15 +4769,15 @@ static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len) } /** - * nand_default_onfi_set_features- [REPLACEABLE] set features for ONFI nand + * nand_default_set_features- [REPLACEABLE] set NAND chip features * @mtd: MTD device structure * @chip: nand chip info structure * @addr: feature address. * @subfeature_param: the subfeature parameters, a four bytes array. */ -static int nand_default_onfi_set_features(struct mtd_info *mtd, - struct nand_chip *chip, int addr, - uint8_t *subfeature_param) +static int nand_default_set_features(struct mtd_info *mtd, + struct nand_chip *chip, int addr, + uint8_t *subfeature_param) { if (!chip->onfi_version || !(le16_to_cpu(chip->onfi_params.opt_cmd) @@ -4788,15 +4788,15 @@ static int nand_default_onfi_set_features(struct mtd_info *mtd, } /** - * nand_default_onfi_get_features- [REPLACEABLE] get features for ONFI nand + * nand_default_get_features- [REPLACEABLE] get NAND chip features * @mtd: MTD device structure * @chip: nand chip info structure * @addr: feature address. * @subfeature_param: the subfeature parameters, a four bytes array. */ -static int nand_default_onfi_get_features(struct mtd_info *mtd, - struct nand_chip *chip, int addr, - uint8_t *subfeature_param) +static int nand_default_get_features(struct mtd_info *mtd, + struct nand_chip *chip, int addr, + uint8_t *subfeature_param) { if (!chip->onfi_version || !(le16_to_cpu(chip->onfi_params.opt_cmd) @@ -4807,8 +4807,7 @@ static int nand_default_onfi_get_features(struct mtd_info *mtd, } /** - * nand_onfi_get_set_features_notsupp - set/get features stub returning - * -ENOTSUPP + * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP * @mtd: MTD device structure * @chip: nand chip info structure * @addr: feature address. @@ -4817,13 +4816,12 @@ static int nand_default_onfi_get_features(struct mtd_info *mtd, * Should be used by NAND controller drivers that do not support the SET/GET * FEATURES operations. */ -int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, - struct nand_chip *chip, int addr, - u8 *subfeature_param) +int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip, + int addr, u8 *subfeature_param) { return -ENOTSUPP; } -EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp); +EXPORT_SYMBOL(nand_get_set_features_notsupp); /** * nand_suspend - [MTD Interface] Suspend the NAND flash @@ -4880,10 +4878,10 @@ static void nand_set_defaults(struct nand_chip *chip) chip->select_chip = nand_select_chip; /* set for ONFI nand */ - if (!chip->onfi_set_features) - chip->onfi_set_features = nand_default_onfi_set_features; - if (!chip->onfi_get_features) - chip->onfi_get_features = nand_default_onfi_get_features; + if (!chip->set_features) + chip->set_features = nand_default_set_features; + if (!chip->get_features) + chip->get_features = nand_default_get_features; /* If called twice, pointers that depend on busw may need to be reset */ if (!chip->read_byte || chip->read_byte == nand_read_byte) diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c index 02e109ae73f1..ab3e3a1a5212 100644 --- a/drivers/mtd/nand/raw/nand_micron.c +++ b/drivers/mtd/nand/raw/nand_micron.c @@ -48,8 +48,8 @@ static int micron_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) struct nand_chip *chip = mtd_to_nand(mtd); u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; - return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, - feature); + return chip->set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, + feature); } /* @@ -108,8 +108,8 @@ static int micron_nand_on_die_ecc_setup(struct nand_chip *chip, bool enable) if (enable) feature[0] |= ONFI_FEATURE_ON_DIE_ECC_EN; - return chip->onfi_set_features(nand_to_mtd(chip), chip, - ONFI_FEATURE_ON_DIE_ECC, feature); + return chip->set_features(nand_to_mtd(chip), chip, + ONFI_FEATURE_ON_DIE_ECC, feature); } static int @@ -219,8 +219,8 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip) if (ret) return MICRON_ON_DIE_UNSUPPORTED; - chip->onfi_get_features(nand_to_mtd(chip), chip, - ONFI_FEATURE_ON_DIE_ECC, feature); + chip->get_features(nand_to_mtd(chip), chip, + ONFI_FEATURE_ON_DIE_ECC, feature); if ((feature[0] & ONFI_FEATURE_ON_DIE_ECC_EN) == 0) return MICRON_ON_DIE_UNSUPPORTED; @@ -228,8 +228,8 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip) if (ret) return MICRON_ON_DIE_UNSUPPORTED; - chip->onfi_get_features(nand_to_mtd(chip), chip, - ONFI_FEATURE_ON_DIE_ECC, feature); + chip->get_features(nand_to_mtd(chip), chip, + ONFI_FEATURE_ON_DIE_ECC, feature); if (feature[0] & ONFI_FEATURE_ON_DIE_ECC_EN) return MICRON_ON_DIE_MANDATORY; diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 563b759ffca6..b554fb6e609c 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2651,8 +2651,8 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc, chip->read_byte = qcom_nandc_read_byte; chip->read_buf = qcom_nandc_read_buf; chip->write_buf = qcom_nandc_write_buf; - chip->onfi_set_features = nand_onfi_get_set_features_notsupp; - chip->onfi_get_features = nand_onfi_get_set_features_notsupp; + chip->set_features = nand_get_set_features_notsupp; + chip->get_features = nand_get_set_features_notsupp; /* * the bad block marker is readable only when we read the last codeword diff --git a/drivers/mtd/nand/raw/sh_flctl.c b/drivers/mtd/nand/raw/sh_flctl.c index a60d43adff3c..7a740d583866 100644 --- a/drivers/mtd/nand/raw/sh_flctl.c +++ b/drivers/mtd/nand/raw/sh_flctl.c @@ -1180,8 +1180,8 @@ static int flctl_probe(struct platform_device *pdev) nand->read_buf = flctl_read_buf; nand->select_chip = flctl_select_chip; nand->cmdfunc = flctl_cmdfunc; - nand->onfi_set_features = nand_onfi_get_set_features_notsupp; - nand->onfi_get_features = nand_onfi_get_set_features_notsupp; + nand->set_features = nand_get_set_features_notsupp; + nand->get_features = nand_get_set_features_notsupp; if (pdata->flcmncr_val & SEL_16BIT) nand->options |= NAND_BUSWIDTH_16; diff --git a/drivers/staging/mt29f_spinand/mt29f_spinand.c b/drivers/staging/mt29f_spinand/mt29f_spinand.c index 264ad362d858..6819dd2c1117 100644 --- a/drivers/staging/mt29f_spinand/mt29f_spinand.c +++ b/drivers/staging/mt29f_spinand/mt29f_spinand.c @@ -918,8 +918,8 @@ static int spinand_probe(struct spi_device *spi_nand) chip->waitfunc = spinand_wait; chip->options |= NAND_CACHEPRG; chip->select_chip = spinand_select_chip; - chip->onfi_set_features = nand_onfi_get_set_features_notsupp; - chip->onfi_get_features = nand_onfi_get_set_features_notsupp; + chip->set_features = nand_get_set_features_notsupp; + chip->get_features = nand_get_set_features_notsupp; mtd = nand_to_mtd(chip); diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 56c5570aadbe..fb2e288ef8b1 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1170,8 +1170,8 @@ int nand_op_parser_exec_op(struct nand_chip *chip, * @blocks_per_die: [INTERN] The number of PEBs in a die * @data_interface: [INTERN] NAND interface timing information * @read_retries: [INTERN] the number of read retry modes supported - * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand - * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand + * @set_features: [REPLACEABLE] set the NAND chip features + * @get_features: [REPLACEABLE] get the NAND chip features * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this * means the configuration should not be applied but @@ -1212,10 +1212,10 @@ struct nand_chip { bool check_only); int (*erase)(struct mtd_info *mtd, int page); int (*scan_bbt)(struct mtd_info *mtd); - int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, - int feature_addr, uint8_t *subfeature_para); - int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, - int feature_addr, uint8_t *subfeature_para); + int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip, + int feature_addr, uint8_t *subfeature_para); + int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip, + int feature_addr, uint8_t *subfeature_para); int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, const struct nand_data_interface *conf); @@ -1630,9 +1630,8 @@ int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page); /* Stub used by drivers that do not support GET/SET FEATURES operations */ -int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, - struct nand_chip *chip, int addr, - u8 *subfeature_param); +int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip, + int addr, u8 *subfeature_param); /* Default read_page_raw implementation */ int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, -- cgit v1.2.3 From 97baea1e6b74c73973fa0922252f880ab15450ea Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Mar 2018 14:47:20 +0100 Subject: mtd: rawnand: use wrappers to call onfi GET/SET_FEATURES Prepare the fact that some features managed by GET/SET_FEATURES could be overloaded by vendor code. To handle this logic, use new wrappers instead of directly call the ->get/set_features() hooks. Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c | 6 +-- drivers/mtd/nand/raw/nand_base.c | 89 ++++++++++++++++++++----------- drivers/mtd/nand/raw/nand_micron.c | 18 ++++--- include/linux/mtd/rawnand.h | 3 ++ 4 files changed, 74 insertions(+), 42 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c index f78d907ca61e..039f2795617f 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c @@ -934,15 +934,13 @@ static int enable_edo_mode(struct gpmi_nand_data *this, int mode) /* [1] send SET FEATURE command to NAND */ feature[0] = mode; - ret = nand->set_features(mtd, nand, - ONFI_FEATURE_ADDR_TIMING_MODE, feature); + ret = nand_set_features(nand, ONFI_FEATURE_ADDR_TIMING_MODE, feature); if (ret) goto err_out; /* [2] send GET FEATURE command to double-check the timing mode */ memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN); - ret = nand->get_features(mtd, nand, - ONFI_FEATURE_ADDR_TIMING_MODE, feature); + ret = nand_get_features(nand, ONFI_FEATURE_ADDR_TIMING_MODE, feature); if (ret || feature[0] != mode) goto err_out; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 802cd9ed44a1..d344dcb12620 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -1160,6 +1160,55 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) return status; } +static bool nand_supports_set_get_features(struct nand_chip *chip) +{ + return (chip->onfi_version && + (le16_to_cpu(chip->onfi_params.opt_cmd) & + ONFI_OPT_CMD_SET_GET_FEATURES)); +} + +/** + * nand_get_features - wrapper to perform a GET_FEATURE + * @chip: NAND chip info structure + * @addr: feature address + * @subfeature_param: the subfeature parameters, a four bytes array + * + * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the + * operation cannot be handled. + */ +int nand_get_features(struct nand_chip *chip, int addr, + u8 *subfeature_param) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + if (!nand_supports_set_get_features(chip)) + return -ENOTSUPP; + + return chip->get_features(mtd, chip, addr, subfeature_param); +} +EXPORT_SYMBOL_GPL(nand_get_features); + +/** + * nand_set_features - wrapper to perform a SET_FEATURE + * @chip: NAND chip info structure + * @addr: feature address + * @subfeature_param: the subfeature parameters, a four bytes array + * + * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the + * operation cannot be handled. + */ +int nand_set_features(struct nand_chip *chip, int addr, + u8 *subfeature_param) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + if (!nand_supports_set_get_features(chip)) + return -ENOTSUPP; + + return chip->set_features(mtd, chip, addr, subfeature_param); +} +EXPORT_SYMBOL_GPL(nand_set_features); + /** * nand_reset_data_interface - Reset data interface and timings * @chip: The NAND chip @@ -1215,32 +1264,22 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) { struct mtd_info *mtd = nand_to_mtd(chip); + u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { + chip->onfi_timing_mode_default, + }; int ret; if (!chip->setup_data_interface) return 0; - /* - * Ensure the timing mode has been changed on the chip side - * before changing timings on the controller side. - */ - if (chip->onfi_version && - (le16_to_cpu(chip->onfi_params.opt_cmd) & - ONFI_OPT_CMD_SET_GET_FEATURES)) { - u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { - chip->onfi_timing_mode_default, - }; - - ret = chip->set_features(mtd, chip, - ONFI_FEATURE_ADDR_TIMING_MODE, - tmode_param); - if (ret) - goto err; - } + /* Change the mode on the chip side */ + ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, + tmode_param); + if (ret) + return ret; - ret = chip->setup_data_interface(mtd, chipnr, &chip->data_interface); -err: - return ret; + /* Change the mode on the controller side */ + return chip->setup_data_interface(mtd, chipnr, &chip->data_interface); } /** @@ -4779,11 +4818,6 @@ static int nand_default_set_features(struct mtd_info *mtd, struct nand_chip *chip, int addr, uint8_t *subfeature_param) { - if (!chip->onfi_version || - !(le16_to_cpu(chip->onfi_params.opt_cmd) - & ONFI_OPT_CMD_SET_GET_FEATURES)) - return -EINVAL; - return nand_set_features_op(chip, addr, subfeature_param); } @@ -4798,11 +4832,6 @@ static int nand_default_get_features(struct mtd_info *mtd, struct nand_chip *chip, int addr, uint8_t *subfeature_param) { - if (!chip->onfi_version || - !(le16_to_cpu(chip->onfi_params.opt_cmd) - & ONFI_OPT_CMD_SET_GET_FEATURES)) - return -EINVAL; - return nand_get_features_op(chip, addr, subfeature_param); } diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c index ab3e3a1a5212..b825656f6284 100644 --- a/drivers/mtd/nand/raw/nand_micron.c +++ b/drivers/mtd/nand/raw/nand_micron.c @@ -48,8 +48,7 @@ static int micron_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) struct nand_chip *chip = mtd_to_nand(mtd); u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; - return chip->set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, - feature); + return nand_set_features(chip, ONFI_FEATURE_ADDR_READ_RETRY, feature); } /* @@ -108,8 +107,7 @@ static int micron_nand_on_die_ecc_setup(struct nand_chip *chip, bool enable) if (enable) feature[0] |= ONFI_FEATURE_ON_DIE_ECC_EN; - return chip->set_features(nand_to_mtd(chip), chip, - ONFI_FEATURE_ON_DIE_ECC, feature); + return nand_set_features(chip, ONFI_FEATURE_ON_DIE_ECC, feature); } static int @@ -219,8 +217,10 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip) if (ret) return MICRON_ON_DIE_UNSUPPORTED; - chip->get_features(nand_to_mtd(chip), chip, - ONFI_FEATURE_ON_DIE_ECC, feature); + ret = nand_get_features(chip, ONFI_FEATURE_ON_DIE_ECC, feature); + if (ret < 0) + return ret; + if ((feature[0] & ONFI_FEATURE_ON_DIE_ECC_EN) == 0) return MICRON_ON_DIE_UNSUPPORTED; @@ -228,8 +228,10 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip) if (ret) return MICRON_ON_DIE_UNSUPPORTED; - chip->get_features(nand_to_mtd(chip), chip, - ONFI_FEATURE_ON_DIE_ECC, feature); + ret = nand_get_features(chip, ONFI_FEATURE_ON_DIE_ECC, feature); + if (ret < 0) + return ret; + if (feature[0] & ONFI_FEATURE_ON_DIE_ECC_EN) return MICRON_ON_DIE_MANDATORY; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index fb2e288ef8b1..3cc2a3435b20 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1629,6 +1629,9 @@ int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page); +/* Wrapper to use in order for controllers/vendors to GET/SET FEATURES */ +int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param); +int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param); /* Stub used by drivers that do not support GET/SET FEATURES operations */ int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip, int addr, u8 *subfeature_param); -- cgit v1.2.3 From b7fa07460b0f0e9fbe6d9319a0864c145bd59bcb Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 19 Mar 2018 11:38:22 +0100 Subject: set_memory.h: Provide set_memory_{en,de}crypted() stubs ... to make these APIs more universally available. Tested-by: Tom Lendacky Signed-off-by: Christoph Hellwig Reviewed-by: Thomas Gleixner Reviewed-by: Konrad Rzeszutek Wilk Reviewed-by: Tom Lendacky Cc: David Woodhouse Cc: Joerg Roedel Cc: Jon Mason Cc: Linus Torvalds Cc: Muli Ben-Yehuda Cc: Peter Zijlstra Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/20180319103826.12853-11-hch@lst.de Signed-off-by: Ingo Molnar --- include/linux/set_memory.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/linux') diff --git a/include/linux/set_memory.h b/include/linux/set_memory.h index e5140648f638..da5178216da5 100644 --- a/include/linux/set_memory.h +++ b/include/linux/set_memory.h @@ -17,4 +17,16 @@ static inline int set_memory_x(unsigned long addr, int numpages) { return 0; } static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } #endif +#ifndef CONFIG_ARCH_HAS_MEM_ENCRYPT +static inline int set_memory_encrypted(unsigned long addr, int numpages) +{ + return 0; +} + +static inline int set_memory_decrypted(unsigned long addr, int numpages) +{ + return 0; +} +#endif /* CONFIG_ARCH_HAS_MEM_ENCRYPT */ + #endif /* _LINUX_SET_MEMORY_H_ */ -- cgit v1.2.3 From b6e05477c10c12e36141558fc14f04b00ea634d4 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 19 Mar 2018 11:38:24 +0100 Subject: dma/direct: Handle the memory encryption bit in common code Give the basic phys_to_dma() and dma_to_phys() helpers a __-prefix and add the memory encryption mask to the non-prefixed versions. Use the __-prefixed versions directly instead of clearing the mask again in various places. Tested-by: Tom Lendacky Signed-off-by: Christoph Hellwig Reviewed-by: Thomas Gleixner Cc: David Woodhouse Cc: Joerg Roedel Cc: Jon Mason Cc: Konrad Rzeszutek Wilk Cc: Linus Torvalds Cc: Muli Ben-Yehuda Cc: Peter Zijlstra Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/20180319103826.12853-13-hch@lst.de Signed-off-by: Ingo Molnar --- arch/arm/include/asm/dma-direct.h | 4 ++-- arch/mips/cavium-octeon/dma-octeon.c | 10 ++++----- .../include/asm/mach-cavium-octeon/dma-coherence.h | 4 ++-- .../include/asm/mach-loongson64/dma-coherence.h | 10 ++++----- arch/mips/loongson64/common/dma-swiotlb.c | 4 ++-- arch/powerpc/include/asm/dma-direct.h | 4 ++-- arch/x86/Kconfig | 2 +- arch/x86/include/asm/dma-direct.h | 25 ++-------------------- arch/x86/mm/mem_encrypt.c | 2 +- arch/x86/pci/sta2x11-fixup.c | 6 +++--- include/linux/dma-direct.h | 21 ++++++++++++++++-- lib/swiotlb.c | 25 ++++++++-------------- 12 files changed, 53 insertions(+), 64 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/include/asm/dma-direct.h b/arch/arm/include/asm/dma-direct.h index 5b0a8a421894..b67e5fc1fe43 100644 --- a/arch/arm/include/asm/dma-direct.h +++ b/arch/arm/include/asm/dma-direct.h @@ -2,13 +2,13 @@ #ifndef ASM_ARM_DMA_DIRECT_H #define ASM_ARM_DMA_DIRECT_H 1 -static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) { unsigned int offset = paddr & ~PAGE_MASK; return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset; } -static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr) +static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dev_addr) { unsigned int offset = dev_addr & ~PAGE_MASK; return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset; diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index c7bb8a407041..7b335ab21697 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -10,7 +10,7 @@ * IP32 changes by Ilya. * Copyright (C) 2010 Cavium Networks, Inc. */ -#include +#include #include #include #include @@ -182,7 +182,7 @@ struct octeon_dma_map_ops { phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); }; -dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) { struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev), struct octeon_dma_map_ops, @@ -190,9 +190,9 @@ dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) return ops->phys_to_dma(dev, paddr); } -EXPORT_SYMBOL(phys_to_dma); +EXPORT_SYMBOL(__phys_to_dma); -phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr) { struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev), struct octeon_dma_map_ops, @@ -200,7 +200,7 @@ phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) return ops->dma_to_phys(dev, daddr); } -EXPORT_SYMBOL(dma_to_phys); +EXPORT_SYMBOL(__dma_to_phys); static struct octeon_dma_map_ops octeon_linear_dma_map_ops = { .dma_map_ops = { diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h index 138edf6b5b48..6eb1ee548b11 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -69,8 +69,8 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) return addr + size - 1 <= *dev->dma_mask; } -dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); -phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr); +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr); struct dma_map_ops; extern const struct dma_map_ops *octeon_pci_dma_map_ops; diff --git a/arch/mips/include/asm/mach-loongson64/dma-coherence.h b/arch/mips/include/asm/mach-loongson64/dma-coherence.h index b1b575f5c6c1..64fc44dec0a8 100644 --- a/arch/mips/include/asm/mach-loongson64/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson64/dma-coherence.h @@ -25,13 +25,13 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) return addr + size - 1 <= *dev->dma_mask; } -extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); -extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); +extern dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr); +extern phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr); static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) { #ifdef CONFIG_CPU_LOONGSON3 - return phys_to_dma(dev, virt_to_phys(addr)); + return __phys_to_dma(dev, virt_to_phys(addr)); #else return virt_to_phys(addr) | 0x80000000; #endif @@ -41,7 +41,7 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) { #ifdef CONFIG_CPU_LOONGSON3 - return phys_to_dma(dev, page_to_phys(page)); + return __phys_to_dma(dev, page_to_phys(page)); #else return page_to_phys(page) | 0x80000000; #endif @@ -51,7 +51,7 @@ static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { #if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT) - return dma_to_phys(dev, dma_addr); + return __dma_to_phys(dev, dma_addr); #elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); #else diff --git a/arch/mips/loongson64/common/dma-swiotlb.c b/arch/mips/loongson64/common/dma-swiotlb.c index 7bbcf89475f3..6a739f8ae110 100644 --- a/arch/mips/loongson64/common/dma-swiotlb.c +++ b/arch/mips/loongson64/common/dma-swiotlb.c @@ -63,7 +63,7 @@ static int loongson_dma_supported(struct device *dev, u64 mask) return swiotlb_dma_supported(dev, mask); } -dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) { long nid; #ifdef CONFIG_PHYS48_TO_HT40 @@ -75,7 +75,7 @@ dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) return paddr; } -phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr) { long nid; #ifdef CONFIG_PHYS48_TO_HT40 diff --git a/arch/powerpc/include/asm/dma-direct.h b/arch/powerpc/include/asm/dma-direct.h index a5b59c765426..7702875aabb7 100644 --- a/arch/powerpc/include/asm/dma-direct.h +++ b/arch/powerpc/include/asm/dma-direct.h @@ -17,12 +17,12 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) return addr + size - 1 <= *dev->dma_mask; } -static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) { return paddr + get_dma_offset(dev); } -static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr) { return daddr - get_dma_offset(dev); } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7dc347217d3a..5b4899de076f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -54,7 +54,6 @@ config X86 select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_KCOV if X86_64 - select ARCH_HAS_PHYS_TO_DMA select ARCH_HAS_MEMBARRIER_SYNC_CORE select ARCH_HAS_PMEM_API if X86_64 select ARCH_HAS_REFCOUNT @@ -692,6 +691,7 @@ config X86_SUPPORTS_MEMORY_FAILURE config STA2X11 bool "STA2X11 Companion Chip Support" depends on X86_32_NON_STANDARD && PCI + select ARCH_HAS_PHYS_TO_DMA select X86_DEV_DMA_OPS select X86_DMA_REMAP select SWIOTLB diff --git a/arch/x86/include/asm/dma-direct.h b/arch/x86/include/asm/dma-direct.h index 1295bc622ebe..1a19251eaac9 100644 --- a/arch/x86/include/asm/dma-direct.h +++ b/arch/x86/include/asm/dma-direct.h @@ -2,29 +2,8 @@ #ifndef ASM_X86_DMA_DIRECT_H #define ASM_X86_DMA_DIRECT_H 1 -#include - -#ifdef CONFIG_X86_DMA_REMAP /* Platform code defines bridge-specific code */ bool dma_capable(struct device *dev, dma_addr_t addr, size_t size); -dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); -phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); -#else -static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) -{ - if (!dev->dma_mask) - return 0; - - return addr + size - 1 <= *dev->dma_mask; -} - -static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) -{ - return __sme_set(paddr); -} +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr); +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr); -static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) -{ - return __sme_clr(daddr); -} -#endif /* CONFIG_X86_DMA_REMAP */ #endif /* ASM_X86_DMA_DIRECT_H */ diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index d243e8d80d89..1b396422d26f 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -211,7 +211,7 @@ static void *sev_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, * Since we will be clearing the encryption bit, check the * mask with it already cleared. */ - addr = __sme_clr(phys_to_dma(dev, page_to_phys(page))); + addr = __phys_to_dma(dev, page_to_phys(page)); if ((addr + size) > dev->coherent_dma_mask) { __free_pages(page, get_order(size)); } else { diff --git a/arch/x86/pci/sta2x11-fixup.c b/arch/x86/pci/sta2x11-fixup.c index eac58e03f43c..7a5bafb76d77 100644 --- a/arch/x86/pci/sta2x11-fixup.c +++ b/arch/x86/pci/sta2x11-fixup.c @@ -207,11 +207,11 @@ bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) } /** - * phys_to_dma - Return the DMA AMBA address used for this STA2x11 device + * __phys_to_dma - Return the DMA AMBA address used for this STA2x11 device * @dev: device for a PCI device * @paddr: Physical address */ -dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) { if (!dev->archdata.is_sta2x11) return paddr; @@ -223,7 +223,7 @@ dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) * @dev: device for a PCI device * @daddr: STA2x11 AMBA DMA address */ -phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr) { if (!dev->archdata.is_sta2x11) return daddr; diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h index bcdb1a3e4b1f..53ad6a47f513 100644 --- a/include/linux/dma-direct.h +++ b/include/linux/dma-direct.h @@ -3,18 +3,19 @@ #define _LINUX_DMA_DIRECT_H 1 #include +#include #ifdef CONFIG_ARCH_HAS_PHYS_TO_DMA #include #else -static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) { dma_addr_t dev_addr = (dma_addr_t)paddr; return dev_addr - ((dma_addr_t)dev->dma_pfn_offset << PAGE_SHIFT); } -static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr) +static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dev_addr) { phys_addr_t paddr = (phys_addr_t)dev_addr; @@ -30,6 +31,22 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) } #endif /* !CONFIG_ARCH_HAS_PHYS_TO_DMA */ +/* + * If memory encryption is supported, phys_to_dma will set the memory encryption + * bit in the DMA address, and dma_to_phys will clear it. The raw __phys_to_dma + * and __dma_to_phys versions should only be used on non-encrypted memory for + * special occasions like DMA coherent buffers. + */ +static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + return __sme_set(__phys_to_dma(dev, paddr)); +} + +static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) +{ + return __sme_clr(__dma_to_phys(dev, daddr)); +} + #ifdef CONFIG_ARCH_HAS_DMA_MARK_CLEAN void dma_mark_clean(void *addr, size_t size); #else diff --git a/lib/swiotlb.c b/lib/swiotlb.c index 005d1d87bb2e..8b06b4485e65 100644 --- a/lib/swiotlb.c +++ b/lib/swiotlb.c @@ -157,13 +157,6 @@ unsigned long swiotlb_size_or_default(void) return size ? size : (IO_TLB_DEFAULT_SIZE); } -/* For swiotlb, clear memory encryption mask from dma addresses */ -static dma_addr_t swiotlb_phys_to_dma(struct device *hwdev, - phys_addr_t address) -{ - return __sme_clr(phys_to_dma(hwdev, address)); -} - /* Note that this doesn't work with highmem page */ static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, volatile void *address) @@ -622,7 +615,7 @@ map_single(struct device *hwdev, phys_addr_t phys, size_t size, return SWIOTLB_MAP_ERROR; } - start_dma_addr = swiotlb_phys_to_dma(hwdev, io_tlb_start); + start_dma_addr = __phys_to_dma(hwdev, io_tlb_start); return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, dir, attrs); } @@ -726,12 +719,12 @@ swiotlb_alloc_buffer(struct device *dev, size_t size, dma_addr_t *dma_handle, goto out_warn; phys_addr = swiotlb_tbl_map_single(dev, - swiotlb_phys_to_dma(dev, io_tlb_start), + __phys_to_dma(dev, io_tlb_start), 0, size, DMA_FROM_DEVICE, 0); if (phys_addr == SWIOTLB_MAP_ERROR) goto out_warn; - *dma_handle = swiotlb_phys_to_dma(dev, phys_addr); + *dma_handle = __phys_to_dma(dev, phys_addr); if (dma_coherent_ok(dev, *dma_handle, size)) goto out_unmap; @@ -867,10 +860,10 @@ dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, map = map_single(dev, phys, size, dir, attrs); if (map == SWIOTLB_MAP_ERROR) { swiotlb_full(dev, size, dir, 1); - return swiotlb_phys_to_dma(dev, io_tlb_overflow_buffer); + return __phys_to_dma(dev, io_tlb_overflow_buffer); } - dev_addr = swiotlb_phys_to_dma(dev, map); + dev_addr = __phys_to_dma(dev, map); /* Ensure that the address returned is DMA'ble */ if (dma_capable(dev, dev_addr, size)) @@ -879,7 +872,7 @@ dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, attrs |= DMA_ATTR_SKIP_CPU_SYNC; swiotlb_tbl_unmap_single(dev, map, size, dir, attrs); - return swiotlb_phys_to_dma(dev, io_tlb_overflow_buffer); + return __phys_to_dma(dev, io_tlb_overflow_buffer); } /* @@ -1009,7 +1002,7 @@ swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, sg_dma_len(sgl) = 0; return 0; } - sg->dma_address = swiotlb_phys_to_dma(hwdev, map); + sg->dma_address = __phys_to_dma(hwdev, map); } else sg->dma_address = dev_addr; sg_dma_len(sg) = sg->length; @@ -1073,7 +1066,7 @@ swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, int swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) { - return (dma_addr == swiotlb_phys_to_dma(hwdev, io_tlb_overflow_buffer)); + return (dma_addr == __phys_to_dma(hwdev, io_tlb_overflow_buffer)); } /* @@ -1085,7 +1078,7 @@ swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) int swiotlb_dma_supported(struct device *hwdev, u64 mask) { - return swiotlb_phys_to_dma(hwdev, io_tlb_end - 1) <= mask; + return __phys_to_dma(hwdev, io_tlb_end - 1) <= mask; } #ifdef CONFIG_DMA_DIRECT_OPS -- cgit v1.2.3 From 16e73adbca76fd18733278cb688b0ddb4cad162c Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 19 Mar 2018 11:38:26 +0100 Subject: dma/swiotlb: Remove swiotlb_{alloc,free}_coherent() Unused now that everyone uses swiotlb_{alloc,free}(). Tested-by: Tom Lendacky Signed-off-by: Christoph Hellwig Reviewed-by: Thomas Gleixner Cc: David Woodhouse Cc: Joerg Roedel Cc: Jon Mason Cc: Konrad Rzeszutek Wilk Cc: Linus Torvalds Cc: Muli Ben-Yehuda Cc: Peter Zijlstra Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/20180319103826.12853-15-hch@lst.de Signed-off-by: Ingo Molnar --- include/linux/swiotlb.h | 8 -------- lib/swiotlb.c | 38 -------------------------------------- 2 files changed, 46 deletions(-) (limited to 'include/linux') diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h index 5b1f2a00491c..965be92c33b5 100644 --- a/include/linux/swiotlb.h +++ b/include/linux/swiotlb.h @@ -72,14 +72,6 @@ void *swiotlb_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle, void swiotlb_free(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_addr, unsigned long attrs); -extern void -*swiotlb_alloc_coherent(struct device *hwdev, size_t size, - dma_addr_t *dma_handle, gfp_t flags); - -extern void -swiotlb_free_coherent(struct device *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle); - extern dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction dir, diff --git a/lib/swiotlb.c b/lib/swiotlb.c index 8b06b4485e65..15954b86f09e 100644 --- a/lib/swiotlb.c +++ b/lib/swiotlb.c @@ -157,13 +157,6 @@ unsigned long swiotlb_size_or_default(void) return size ? size : (IO_TLB_DEFAULT_SIZE); } -/* Note that this doesn't work with highmem page */ -static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, - volatile void *address) -{ - return phys_to_dma(hwdev, virt_to_phys(address)); -} - static bool no_iotlb_memory; void swiotlb_print_info(void) @@ -752,28 +745,6 @@ out_warn: return NULL; } -void * -swiotlb_alloc_coherent(struct device *hwdev, size_t size, - dma_addr_t *dma_handle, gfp_t flags) -{ - int order = get_order(size); - unsigned long attrs = (flags & __GFP_NOWARN) ? DMA_ATTR_NO_WARN : 0; - void *ret; - - ret = (void *)__get_free_pages(flags, order); - if (ret) { - *dma_handle = swiotlb_virt_to_bus(hwdev, ret); - if (dma_coherent_ok(hwdev, *dma_handle, size)) { - memset(ret, 0, size); - return ret; - } - free_pages((unsigned long)ret, order); - } - - return swiotlb_alloc_buffer(hwdev, size, dma_handle, attrs); -} -EXPORT_SYMBOL(swiotlb_alloc_coherent); - static bool swiotlb_free_buffer(struct device *dev, size_t size, dma_addr_t dma_addr) { @@ -793,15 +764,6 @@ static bool swiotlb_free_buffer(struct device *dev, size_t size, return true; } -void -swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, - dma_addr_t dev_addr) -{ - if (!swiotlb_free_buffer(hwdev, size, dev_addr)) - free_pages((unsigned long)vaddr, get_order(size)); -} -EXPORT_SYMBOL(swiotlb_free_coherent); - static void swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir, int do_panic) -- cgit v1.2.3 From f4531b2b1929806d2bec1a2f19805031d8bc0806 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Mar 2018 14:47:26 +0100 Subject: mtd: rawnand: prepare the removal of ONFI/JEDEC parameter pages The NAND chip parameter page is statically allocated within the nand_chip structure, which reserves a lot of space. Even not ONFI nor JEDEC chips have it embedded. Also, only a few parameters are actually read from the parameter page after the detection. To prepare to the removal of such huge structure, a small NAND parameter structure is allocated statically and contains only very few members that are generic to all chips and actually used elsewhere in the code. Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- drivers/mtd/nand/raw/nand_base.c | 39 +++++++++++++++++---------------------- include/linux/mtd/rawnand.h | 13 +++++++++++++ 2 files changed, 30 insertions(+), 22 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 4099d8a1e25e..0f1f45526c7f 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -1162,9 +1162,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) static bool nand_supports_set_get_features(struct nand_chip *chip) { - return (chip->onfi_version && - (le16_to_cpu(chip->onfi_params.opt_cmd) & - ONFI_OPT_CMD_SET_GET_FEATURES)); + return chip->parameters.supports_set_get_features; } /** @@ -5145,8 +5143,8 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) sanitize_string(p->manufacturer, sizeof(p->manufacturer)); sanitize_string(p->model, sizeof(p->model)); - if (!mtd->name) - mtd->name = p->model; + strncpy(chip->parameters.model, p->model, + sizeof(chip->parameters.model) - 1); mtd->writesize = le32_to_cpu(p->byte_per_page); @@ -5193,6 +5191,10 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) pr_warn("Could not retrieve ONFI ECC requirements\n"); } + /* Save some parameters from the parameter page for future use */ + if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_SET_GET_FEATURES) + chip->parameters.supports_set_get_features = true; + return 1; } @@ -5245,8 +5247,8 @@ static int nand_flash_detect_jedec(struct nand_chip *chip) sanitize_string(p->manufacturer, sizeof(p->manufacturer)); sanitize_string(p->model, sizeof(p->model)); - if (!mtd->name) - mtd->name = p->model; + strncpy(chip->parameters.model, p->model, + sizeof(chip->parameters.model) - 1); mtd->writesize = le32_to_cpu(p->byte_per_page); @@ -5433,8 +5435,8 @@ static bool find_full_id_nand(struct nand_chip *chip, chip->onfi_timing_mode_default = type->onfi_timing_mode_default; - if (!mtd->name) - mtd->name = type->name; + strncpy(chip->parameters.model, type->name, + sizeof(chip->parameters.model) - 1); return true; } @@ -5587,8 +5589,8 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) if (!type->name) return -ENODEV; - if (!mtd->name) - mtd->name = type->name; + strncpy(chip->parameters.model, type->name, + sizeof(chip->parameters.model) - 1); chip->chipsize = (uint64_t)type->chipsize << 20; @@ -5601,6 +5603,8 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) chip->options |= type->options; ident_done: + if (!mtd->name) + mtd->name = chip->parameters.model; if (chip->options & NAND_BUSWIDTH_AUTO) { WARN_ON(busw & NAND_BUSWIDTH_16); @@ -5647,17 +5651,8 @@ ident_done: pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", maf_id, dev_id); - - if (chip->onfi_version) - pr_info("%s %s\n", nand_manufacturer_name(manufacturer), - chip->onfi_params.model); - else if (chip->jedec_version) - pr_info("%s %s\n", nand_manufacturer_name(manufacturer), - chip->jedec_params.model); - else - pr_info("%s %s\n", nand_manufacturer_name(manufacturer), - type->name); - + pr_info("%s %s\n", nand_manufacturer_name(manufacturer), + chip->parameters.model); pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 3cc2a3435b20..a24591411d78 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -429,6 +429,16 @@ struct nand_jedec_params { __le16 crc; } __packed; +/** + * struct nand_parameters - NAND generic parameters from the parameter page + * @model: Model name + * @supports_set_get_features: The NAND chip supports setting/getting features + */ +struct nand_parameters { + char model[100]; + bool supports_set_get_features; +}; + /* The maximum expected count of bytes in the NAND ID sequence */ #define NAND_MAX_ID_LEN 8 @@ -1165,6 +1175,8 @@ int nand_op_parser_exec_op(struct nand_chip *chip, * supported, 0 otherwise. * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is * supported, 0 otherwise. + * @parameters: [INTERN] holds generic parameters under an easily + * readable form. * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a * this nand device will encounter their life times. * @blocks_per_die: [INTERN] The number of PEBs in a die @@ -1249,6 +1261,7 @@ struct nand_chip { struct nand_onfi_params onfi_params; struct nand_jedec_params jedec_params; }; + struct nand_parameters parameters; u16 max_bb_per_die; u32 blocks_per_die; -- cgit v1.2.3 From a97421c7532d382ab560ca153bdf9450f97c7e41 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Mar 2018 14:47:27 +0100 Subject: mtd: rawnand: prepare the removal of the ONFI parameter page The NAND chip parameter page is statically allocated within the nand_chip structure, which reserves a lot of space. Even not ONFI nor JEDEC chips have it embedded. Also, only a few parameters are actually read from the parameter page after the detection. ONFI-related parameters that will be used outside from the identification function are stored in a separate onfi_parameters structure embedded in nand_parameters, this small structure that already hold generic parameters. For now, the onfi_parameters structure is allocated statically. However, after some deep rework in the NAND framework, it will be possible to do dynamic allocations from the NAND identification phase, and this strcuture will then be dynamically allocated when needed. Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c | 2 +- drivers/mtd/nand/raw/nand_base.c | 30 +++++++++++++------- drivers/mtd/nand/raw/nand_micron.c | 19 ++++++------- drivers/mtd/nand/raw/nand_timings.c | 12 ++++---- include/linux/mtd/rawnand.h | 47 +++++++++++++++++++------------ 5 files changed, 64 insertions(+), 46 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c index 039f2795617f..f3cc38372d79 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c @@ -971,7 +971,7 @@ int gpmi_extra_init(struct gpmi_nand_data *this) struct nand_chip *chip = &this->nand; /* Enable the asynchronous EDO feature. */ - if (GPMI_IS_MX6(this) && chip->onfi_version) { + if (GPMI_IS_MX6(this) && chip->parameters.onfi.version) { int mode = onfi_get_async_timing_mode(chip); /* We only support the timing mode 4 and mode 5. */ diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 0f1f45526c7f..789c11e0925e 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -5126,17 +5126,17 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) /* Check version */ val = le16_to_cpu(p->revision); if (val & (1 << 5)) - chip->onfi_version = 23; + chip->parameters.onfi.version = 23; else if (val & (1 << 4)) - chip->onfi_version = 22; + chip->parameters.onfi.version = 22; else if (val & (1 << 3)) - chip->onfi_version = 21; + chip->parameters.onfi.version = 21; else if (val & (1 << 2)) - chip->onfi_version = 20; + chip->parameters.onfi.version = 20; else if (val & (1 << 1)) - chip->onfi_version = 10; + chip->parameters.onfi.version = 10; - if (!chip->onfi_version) { + if (!chip->parameters.onfi.version) { pr_info("unsupported ONFI version: %d\n", val); return 0; } @@ -5166,14 +5166,14 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun); chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun); - if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) + if (le16_to_cpu(p->features) & ONFI_FEATURE_16_BIT_BUS) chip->options |= NAND_BUSWIDTH_16; if (p->ecc_bits != 0xff) { chip->ecc_strength_ds = p->ecc_bits; chip->ecc_step_ds = 512; - } else if (chip->onfi_version >= 21 && - (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { + } else if (chip->parameters.onfi.version >= 21 && + (le16_to_cpu(p->features) & ONFI_FEATURE_EXT_PARAM_PAGE)) { /* * The nand_flash_detect_ext_param_page() uses the @@ -5194,6 +5194,16 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) /* Save some parameters from the parameter page for future use */ if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_SET_GET_FEATURES) chip->parameters.supports_set_get_features = true; + chip->parameters.onfi.tPROG = le16_to_cpu(p->t_prog); + chip->parameters.onfi.tBERS = le16_to_cpu(p->t_bers); + chip->parameters.onfi.tR = le16_to_cpu(p->t_r); + chip->parameters.onfi.tCCS = le16_to_cpu(p->t_ccs); + chip->parameters.onfi.async_timing_mode = + le16_to_cpu(p->async_timing_mode); + chip->parameters.onfi.vendor_revision = + le16_to_cpu(p->vendor_revision); + memcpy(chip->parameters.onfi.vendor, p->vendor, + sizeof(p->vendor)); return 1; } @@ -5575,7 +5585,7 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) } } - chip->onfi_version = 0; + chip->parameters.onfi.version = 0; if (!type->name || !type->pagesize) { /* Check if the chip is ONFI compliant */ if (nand_flash_detect_onfi(chip)) diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c index b825656f6284..c5974d8313e7 100644 --- a/drivers/mtd/nand/raw/nand_micron.c +++ b/drivers/mtd/nand/raw/nand_micron.c @@ -56,17 +56,14 @@ static int micron_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) */ static int micron_nand_onfi_init(struct nand_chip *chip) { - struct nand_onfi_params *p = &chip->onfi_params; - struct nand_onfi_vendor_micron *micron = (void *)p->vendor; + struct nand_parameters *p = &chip->parameters; + struct nand_onfi_vendor_micron *micron = (void *)p->onfi.vendor; - if (!chip->onfi_version) - return 0; - - if (le16_to_cpu(p->vendor_revision) < 1) - return 0; + if (chip->parameters.onfi.version && p->onfi.vendor_revision) { + chip->read_retries = micron->read_retry_options; + chip->setup_read_retry = micron_nand_setup_read_retry; + } - chip->read_retries = micron->read_retry_options; - chip->setup_read_retry = micron_nand_setup_read_retry; return 0; } @@ -207,7 +204,7 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip) u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = { 0, }; int ret; - if (chip->onfi_version == 0) + if (!chip->parameters.onfi.version) return MICRON_ON_DIE_UNSUPPORTED; if (chip->bits_per_cell != 1) @@ -239,7 +236,7 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip) * Some Micron NANDs have an on-die ECC of 4/512, some other * 8/512. We only support the former. */ - if (chip->onfi_params.ecc_bits != 4) + if (chip->ecc_strength_ds != 4) return MICRON_ON_DIE_UNSUPPORTED; return MICRON_ON_DIE_SUPPORTED; diff --git a/drivers/mtd/nand/raw/nand_timings.c b/drivers/mtd/nand/raw/nand_timings.c index 9400d039ddbd..7c4e4a371bbc 100644 --- a/drivers/mtd/nand/raw/nand_timings.c +++ b/drivers/mtd/nand/raw/nand_timings.c @@ -306,17 +306,17 @@ int onfi_fill_data_interface(struct nand_chip *chip, * tR, tPROG, tCCS, ... * These information are part of the ONFI parameter page. */ - if (chip->onfi_version) { - struct nand_onfi_params *params = &chip->onfi_params; + if (chip->parameters.onfi.version) { + struct nand_parameters *params = &chip->parameters; struct nand_sdr_timings *timings = &iface->timings.sdr; /* microseconds -> picoseconds */ - timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog); - timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers); - timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r); + timings->tPROG_max = 1000000ULL * params->onfi.tPROG; + timings->tBERS_max = 1000000ULL * params->onfi.tBERS; + timings->tR_max = 1000000ULL * params->onfi.tR; /* nanoseconds -> picoseconds */ - timings->tCCS_min = 1000UL * le16_to_cpu(params->t_ccs); + timings->tCCS_min = 1000UL * params->onfi.tCCS; } return 0; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index a24591411d78..7b5afa6ef5a9 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -429,14 +429,41 @@ struct nand_jedec_params { __le16 crc; } __packed; +/** + * struct onfi_params - ONFI specific parameters that will be reused + * @version: ONFI version (BCD encoded), 0 if ONFI is not supported + * @tPROG: Page program time + * @tBERS: Block erase time + * @tR: Page read time + * @tCCS: Change column setup time + * @async_timing_mode: Supported asynchronous timing mode + * @vendor_revision: Vendor specific revision number + * @vendor: Vendor specific data + */ +struct onfi_params { + int version; + u16 tPROG; + u16 tBERS; + u16 tR; + u16 tCCS; + u16 async_timing_mode; + u16 vendor_revision; + u8 vendor[88]; +}; + /** * struct nand_parameters - NAND generic parameters from the parameter page * @model: Model name * @supports_set_get_features: The NAND chip supports setting/getting features + * @onfi: ONFI specific parameters */ struct nand_parameters { + /* Generic parameters */ char model[100]; bool supports_set_get_features; + + /* ONFI parameters */ + struct onfi_params onfi; }; /* The maximum expected count of bytes in the NAND ID sequence */ @@ -1167,8 +1194,6 @@ int nand_op_parser_exec_op(struct nand_chip *chip, * currently in data_buf. * @subpagesize: [INTERN] holds the subpagesize * @id: [INTERN] holds NAND ID - * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), - * non 0 if ONFI supported. * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), * non 0 if JEDEC supported. * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is @@ -1255,7 +1280,6 @@ struct nand_chip { int badblockbits; struct nand_id id; - int onfi_version; int jedec_version; union { struct nand_onfi_params onfi_params; @@ -1548,26 +1572,13 @@ struct platform_nand_data { struct platform_nand_ctrl ctrl; }; -/* return the supported features. */ -static inline int onfi_feature(struct nand_chip *chip) -{ - return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; -} - /* return the supported asynchronous timing mode. */ static inline int onfi_get_async_timing_mode(struct nand_chip *chip) { - if (!chip->onfi_version) + if (!chip->parameters.onfi.version) return ONFI_TIMING_MODE_UNKNOWN; - return le16_to_cpu(chip->onfi_params.async_timing_mode); -} -/* return the supported synchronous timing mode. */ -static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) -{ - if (!chip->onfi_version) - return ONFI_TIMING_MODE_UNKNOWN; - return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); + return chip->parameters.onfi.async_timing_mode; } int onfi_fill_data_interface(struct nand_chip *chip, -- cgit v1.2.3 From 789157e41a0694e70bf80bceecd79438c3de98d6 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Mar 2018 14:47:28 +0100 Subject: mtd: rawnand: allow vendors to declare (un)supported features If SET/GET_FEATURES is available (from the parameter page), use a bitmap to declare what feature is actually supported. Initialize the bitmap in the core to support timing changes (only feature used by the core), also add support for Micron specific features used in Micron initialization code (in the init routine). Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- drivers/mtd/nand/raw/nand_base.c | 26 +++++++++++++++++++------- drivers/mtd/nand/raw/nand_micron.c | 4 ++++ include/linux/mtd/rawnand.h | 8 +++++++- 3 files changed, 30 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 789c11e0925e..0bd9f22973e9 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -1160,9 +1160,16 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) return status; } -static bool nand_supports_set_get_features(struct nand_chip *chip) +static bool nand_supports_get_features(struct nand_chip *chip, int addr) { - return chip->parameters.supports_set_get_features; + return (chip->parameters.supports_set_get_features && + test_bit(addr, chip->parameters.get_feature_list)); +} + +static bool nand_supports_set_features(struct nand_chip *chip, int addr) +{ + return (chip->parameters.supports_set_get_features && + test_bit(addr, chip->parameters.set_feature_list)); } /** @@ -1179,7 +1186,7 @@ int nand_get_features(struct nand_chip *chip, int addr, { struct mtd_info *mtd = nand_to_mtd(chip); - if (!nand_supports_set_get_features(chip)) + if (!nand_supports_get_features(chip, addr)) return -ENOTSUPP; return chip->get_features(mtd, chip, addr, subfeature_param); @@ -1200,7 +1207,7 @@ int nand_set_features(struct nand_chip *chip, int addr, { struct mtd_info *mtd = nand_to_mtd(chip); - if (!nand_supports_set_get_features(chip)) + if (!nand_supports_set_features(chip, addr)) return -ENOTSUPP; return chip->set_features(mtd, chip, addr, subfeature_param); @@ -1271,7 +1278,7 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) return 0; /* Change the mode on the chip side (if supported by the NAND chip) */ - if (nand_supports_set_get_features(chip)) { + if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) { chip->select_chip(mtd, chipnr); ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, tmode_param); @@ -1286,7 +1293,7 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) return ret; /* Check the mode has been accepted by the chip, if supported */ - if (!nand_supports_set_get_features(chip)) + if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) return 0; memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN); @@ -5192,8 +5199,13 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) } /* Save some parameters from the parameter page for future use */ - if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_SET_GET_FEATURES) + if (le16_to_cpu(p->opt_cmd) & ONFI_OPT_CMD_SET_GET_FEATURES) { chip->parameters.supports_set_get_features = true; + bitmap_set(chip->parameters.get_feature_list, + ONFI_FEATURE_ADDR_TIMING_MODE, 1); + bitmap_set(chip->parameters.set_feature_list, + ONFI_FEATURE_ADDR_TIMING_MODE, 1); + } chip->parameters.onfi.tPROG = le16_to_cpu(p->t_prog); chip->parameters.onfi.tBERS = le16_to_cpu(p->t_bers); chip->parameters.onfi.tR = le16_to_cpu(p->t_r); diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c index c5974d8313e7..0af45b134c0c 100644 --- a/drivers/mtd/nand/raw/nand_micron.c +++ b/drivers/mtd/nand/raw/nand_micron.c @@ -64,6 +64,10 @@ static int micron_nand_onfi_init(struct nand_chip *chip) chip->setup_read_retry = micron_nand_setup_read_retry; } + if (p->supports_set_get_features) { + set_bit(ONFI_FEATURE_ADDR_READ_RETRY, p->set_feature_list); + set_bit(ONFI_FEATURE_ADDR_READ_RETRY, p->get_feature_list); + } return 0; } diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 7b5afa6ef5a9..d9f417719d36 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -21,6 +21,7 @@ #include #include #include +#include struct mtd_info; struct nand_flash_dev; @@ -235,7 +236,8 @@ struct nand_chip; #define ONFI_TIMING_MODE_5 (1 << 5) #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) -/* ONFI feature address */ +/* ONFI feature number/address */ +#define ONFI_FEATURE_NUMBER 256 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 /* Vendor-specific feature address (Micron) */ @@ -455,12 +457,16 @@ struct onfi_params { * struct nand_parameters - NAND generic parameters from the parameter page * @model: Model name * @supports_set_get_features: The NAND chip supports setting/getting features + * @set_feature_list: Bitmap of features that can be set + * @get_feature_list: Bitmap of features that can be get * @onfi: ONFI specific parameters */ struct nand_parameters { /* Generic parameters */ char model[100]; bool supports_set_get_features; + DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); + DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); /* ONFI parameters */ struct onfi_params onfi; -- cgit v1.2.3 From 480139d9229e3be0530bc548da208b5f49b1ab90 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Mar 2018 14:47:30 +0100 Subject: mtd: rawnand: get rid of the JEDEC parameter page in nand_chip The NAND chip parameter page is statically allocated within the nand_chip structure, which reserves a lot of space. Even not ONFI nor JEDEC chips have it embedded. Also, only a few parameters are actually read from the parameter page after the detection. Now that there is a small nand_parameters structure that can held generic parameters, remove the JEDEC page from the nand_chip structure by just allocating it during the identification phase and removing it right after. Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- drivers/mtd/nand/raw/nand_base.c | 41 +++++++++++++++++++++++++++------------- include/linux/mtd/rawnand.h | 17 +---------------- 2 files changed, 29 insertions(+), 29 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 0bd9f22973e9..79348165e4a3 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -5226,8 +5226,9 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) static int nand_flash_detect_jedec(struct nand_chip *chip) { struct mtd_info *mtd = nand_to_mtd(chip); - struct nand_jedec_params *p = &chip->jedec_params; + struct nand_jedec_params *p; struct jedec_ecc_info *ecc; + int jedec_version = 0; char id[5]; int i, val, ret; @@ -5236,14 +5237,23 @@ static int nand_flash_detect_jedec(struct nand_chip *chip) if (ret || strncmp(id, "JEDEC", sizeof(id))) return 0; + /* JEDEC chip: allocate a buffer to hold its parameter page */ + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + ret = nand_read_param_page_op(chip, 0x40, NULL, 0); - if (ret) - return 0; + if (ret) { + ret = 0; + goto free_jedec_param_page; + } for (i = 0; i < 3; i++) { ret = nand_read_data_op(chip, p, sizeof(*p), true); - if (ret) - return 0; + if (ret) { + ret = 0; + goto free_jedec_param_page; + } if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == le16_to_cpu(p->crc)) @@ -5252,19 +5262,19 @@ static int nand_flash_detect_jedec(struct nand_chip *chip) if (i == 3) { pr_err("Could not find valid JEDEC parameter page; aborting\n"); - return 0; + goto free_jedec_param_page; } /* Check version */ val = le16_to_cpu(p->revision); if (val & (1 << 2)) - chip->jedec_version = 10; + jedec_version = 10; else if (val & (1 << 1)) - chip->jedec_version = 1; /* vendor specific version */ + jedec_version = 1; /* vendor specific version */ - if (!chip->jedec_version) { + if (!jedec_version) { pr_info("unsupported JEDEC version: %d\n", val); - return 0; + goto free_jedec_param_page; } sanitize_string(p->manufacturer, sizeof(p->manufacturer)); @@ -5285,7 +5295,7 @@ static int nand_flash_detect_jedec(struct nand_chip *chip) chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; chip->bits_per_cell = p->bits_per_cell; - if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) + if (le16_to_cpu(p->features) & JEDEC_FEATURE_16_BIT_BUS) chip->options |= NAND_BUSWIDTH_16; /* ECC info */ @@ -5298,7 +5308,9 @@ static int nand_flash_detect_jedec(struct nand_chip *chip) pr_warn("Invalid codeword size\n"); } - return 1; +free_jedec_param_page: + kfree(p); + return ret; } /* @@ -5604,7 +5616,10 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) goto ident_done; /* Check if the chip is JEDEC compliant */ - if (nand_flash_detect_jedec(chip)) + ret = nand_flash_detect_jedec(chip); + if (ret < 0) + return ret; + else if (ret) goto ident_done; } diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d9f417719d36..cf82a959b0f3 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1200,12 +1200,8 @@ int nand_op_parser_exec_op(struct nand_chip *chip, * currently in data_buf. * @subpagesize: [INTERN] holds the subpagesize * @id: [INTERN] holds NAND ID - * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), - * non 0 if JEDEC supported. * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is * supported, 0 otherwise. - * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is - * supported, 0 otherwise. * @parameters: [INTERN] holds generic parameters under an easily * readable form. * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a @@ -1286,11 +1282,7 @@ struct nand_chip { int badblockbits; struct nand_id id; - int jedec_version; - union { - struct nand_onfi_params onfi_params; - struct nand_jedec_params jedec_params; - }; + struct nand_onfi_params onfi_params; struct nand_parameters parameters; u16 max_bb_per_die; u32 blocks_per_die; @@ -1621,13 +1613,6 @@ static inline int nand_opcode_8bits(unsigned int command) return 0; } -/* return the supported JEDEC features. */ -static inline int jedec_feature(struct nand_chip *chip) -{ - return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) - : 0; -} - /* get timing characteristics from ONFI timing mode. */ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); -- cgit v1.2.3 From bd0b64340c2d66c0fe1aa99b0b23159d7e0c21f2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Mar 2018 14:47:31 +0100 Subject: mtd: rawnand: get rid of the ONFI parameter page in nand_chip The NAND chip parameter page is statically allocated within the nand_chip structure, which reserves a lot of space. Even not ONFI nor JEDEC chips have it embedded. Also, only a few parameters are actually read from the parameter page after the detection. Now that there is a small nand_parameters structure that hold all needed ONFI parameters, remove the ONFI page from the nand_chip structure by just allocating it during the identification phase and removing it right after. Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- drivers/mtd/nand/raw/nand_base.c | 34 +++++++++++++++++++++++++--------- include/linux/mtd/rawnand.h | 3 --- 2 files changed, 25 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 79348165e4a3..d0b993fcf3a5 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -5101,7 +5101,7 @@ ext_out: static int nand_flash_detect_onfi(struct nand_chip *chip) { struct mtd_info *mtd = nand_to_mtd(chip); - struct nand_onfi_params *p = &chip->onfi_params; + struct nand_onfi_params *p; char id[4]; int i, ret, val; @@ -5110,14 +5110,23 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) if (ret || strncmp(id, "ONFI", 4)) return 0; + /* ONFI chip: allocate a buffer to hold its parameter page */ + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + ret = nand_read_param_page_op(chip, 0, NULL, 0); - if (ret) - return 0; + if (ret) { + ret = 0; + goto free_onfi_param_page; + } for (i = 0; i < 3; i++) { ret = nand_read_data_op(chip, p, sizeof(*p), true); - if (ret) - return 0; + if (ret) { + ret = 0; + goto free_onfi_param_page; + } if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == le16_to_cpu(p->crc)) { @@ -5127,7 +5136,7 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) if (i == 3) { pr_err("Could not find valid ONFI parameter page; aborting\n"); - return 0; + goto free_onfi_param_page; } /* Check version */ @@ -5145,7 +5154,9 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) if (!chip->parameters.onfi.version) { pr_info("unsupported ONFI version: %d\n", val); - return 0; + goto free_onfi_param_page; + } else { + ret = 1; } sanitize_string(p->manufacturer, sizeof(p->manufacturer)); @@ -5217,7 +5228,9 @@ static int nand_flash_detect_onfi(struct nand_chip *chip) memcpy(chip->parameters.onfi.vendor, p->vendor, sizeof(p->vendor)); - return 1; +free_onfi_param_page: + kfree(p); + return ret; } /* @@ -5612,7 +5625,10 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) chip->parameters.onfi.version = 0; if (!type->name || !type->pagesize) { /* Check if the chip is ONFI compliant */ - if (nand_flash_detect_onfi(chip)) + ret = nand_flash_detect_onfi(chip); + if (ret < 0) + return ret; + else if (ret) goto ident_done; /* Check if the chip is JEDEC compliant */ diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index cf82a959b0f3..5dad59b31244 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1200,8 +1200,6 @@ int nand_op_parser_exec_op(struct nand_chip *chip, * currently in data_buf. * @subpagesize: [INTERN] holds the subpagesize * @id: [INTERN] holds NAND ID - * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is - * supported, 0 otherwise. * @parameters: [INTERN] holds generic parameters under an easily * readable form. * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a @@ -1282,7 +1280,6 @@ struct nand_chip { int badblockbits; struct nand_id id; - struct nand_onfi_params onfi_params; struct nand_parameters parameters; u16 max_bb_per_die; u32 blocks_per_die; -- cgit v1.2.3 From 04dfac09068766550e3173aac88ff70d70958050 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 14 Mar 2018 15:53:10 +0200 Subject: ARM: omap2+: control: add support for auxiliary control module instances Control module can have multiple instances in a system, each with separate address space and features. Add base support for these auxiliary instances, with support for syscon and clock mappings under them. Signed-off-by: Tero Kristo Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/control.c | 15 +++++++++++---- include/linux/clk/ti.h | 1 + 2 files changed, 12 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index bd8089ff929f..632adb2b7d03 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -623,6 +623,7 @@ void __init omap3_ctrl_init(void) struct control_init_data { int index; + void __iomem *mem; s16 offset; }; @@ -660,15 +661,21 @@ int __init omap2_control_base_init(void) struct device_node *np; const struct of_device_id *match; struct control_init_data *data; + void __iomem *mem; for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { data = (struct control_init_data *)match->data; - omap2_ctrl_base = of_iomap(np, 0); - if (!omap2_ctrl_base) + mem = of_iomap(np, 0); + if (!mem) return -ENOMEM; - omap2_ctrl_offset = data->offset; + if (data->index == TI_CLKM_CTRL) { + omap2_ctrl_base = mem; + omap2_ctrl_offset = data->offset; + } + + data->mem = mem; } return 0; @@ -713,7 +720,7 @@ int __init omap_control_init(void) } else { /* No scm_conf found, direct access */ ret = omap2_clk_provider_init(np, data->index, NULL, - omap2_ctrl_base); + data->mem); if (ret) return ret; } diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index d18da839b810..7e3bceee3489 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -203,6 +203,7 @@ enum { TI_CLKM_PRM, TI_CLKM_SCRM, TI_CLKM_CTRL, + TI_CLKM_CTRL_AUX, TI_CLKM_PLLSS, CLK_MAX_MEMMAPS }; -- cgit v1.2.3 From 2d172691515961cad2abb4bf1b15d187bf2106cf Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 15 Mar 2018 21:52:18 -0500 Subject: clk: davinci: New driver for davinci PLL clocks This adds a new driver for mach-davinci PLL clocks. This is porting the code from arch/arm/mach-davinci/clock.c to the common clock framework. Additionally, it adds device tree support for these clocks. The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent compile errors until the clock code in arch/arm/mach-davinci is removed. Note: although there are similar clocks for TI Keystone we are not able to share the code for a few reasons. The keystone clocks are device tree only and use legacy one-node-per-clock bindings. Also the register layouts are a bit different, which would add even more if/else mess to the keystone clocks. And the keystone PLL driver doesn't support setting clock rates. Signed-off-by: David Lechner Signed-off-by: Stephen Boyd --- MAINTAINERS | 7 + drivers/clk/Makefile | 1 + drivers/clk/davinci/Makefile | 5 + drivers/clk/davinci/pll.c | 888 ++++++++++++++++++++++++++ drivers/clk/davinci/pll.h | 120 ++++ include/linux/platform_data/clk-davinci-pll.h | 21 + 6 files changed, 1042 insertions(+) create mode 100644 drivers/clk/davinci/Makefile create mode 100644 drivers/clk/davinci/pll.c create mode 100644 drivers/clk/davinci/pll.h create mode 100644 include/linux/platform_data/clk-davinci-pll.h (limited to 'include/linux') diff --git a/MAINTAINERS b/MAINTAINERS index 3bdc260e36b7..e6b9f169a243 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13792,6 +13792,13 @@ F: arch/arm/mach-davinci/ F: drivers/i2c/busses/i2c-davinci.c F: arch/arm/boot/dts/da850* +TI DAVINCI SERIES CLOCK DRIVER +M: David Lechner +R: Sekhar Nori +S: Maintained +F: Documentation/devicetree/bindings/clock/ti/davinci/ +F: drivers/clk/davinci/ + TI DAVINCI SERIES GPIO DRIVER M: Keerthy L: linux-gpio@vger.kernel.org diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71ec41e6364f..07ac0fdb71a9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ obj-$(CONFIG_H8300) += h8300/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile new file mode 100644 index 000000000000..d9673bd321e0 --- /dev/null +++ b/drivers/clk/davinci/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +ifeq ($(CONFIG_COMMON_CLK), y) +obj-y += pll.o +endif diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c new file mode 100644 index 000000000000..bfa5b7e52d3d --- /dev/null +++ b/drivers/clk/davinci/pll.c @@ -0,0 +1,888 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLL clock driver for TI Davinci SoCs + * + * Copyright (C) 2018 David Lechner + * + * Based on arch/arm/mach-davinci/clock.c + * Copyright (C) 2006-2007 Texas Instruments. + * Copyright (C) 2008-2009 Deep Root Systems, LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pll.h" + +#define MAX_NAME_SIZE 20 +#define OSCIN_CLK_NAME "oscin" + +#define REVID 0x000 +#define PLLCTL 0x100 +#define OCSEL 0x104 +#define PLLSECCTL 0x108 +#define PLLM 0x110 +#define PREDIV 0x114 +#define PLLDIV1 0x118 +#define PLLDIV2 0x11c +#define PLLDIV3 0x120 +#define OSCDIV 0x124 +#define POSTDIV 0x128 +#define BPDIV 0x12c +#define PLLCMD 0x138 +#define PLLSTAT 0x13c +#define ALNCTL 0x140 +#define DCHANGE 0x144 +#define CKEN 0x148 +#define CKSTAT 0x14c +#define SYSTAT 0x150 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16c +#define PLLDIV8 0x170 +#define PLLDIV9 0x174 + +#define PLLCTL_PLLEN BIT(0) +#define PLLCTL_PLLPWRDN BIT(1) +#define PLLCTL_PLLRST BIT(3) +#define PLLCTL_PLLDIS BIT(4) +#define PLLCTL_PLLENSRC BIT(5) +#define PLLCTL_CLKMODE BIT(8) + +/* shared by most *DIV registers */ +#define DIV_RATIO_SHIFT 0 +#define DIV_RATIO_WIDTH 5 +#define DIV_ENABLE_SHIFT 15 + +#define PLLCMD_GOSET BIT(0) +#define PLLSTAT_GOSTAT BIT(0) + +#define CKEN_OBSCLK_SHIFT 1 +#define CKEN_AUXEN_SHIFT 0 + +/* + * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN + * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us + * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input + * is ~25MHz. Units are micro seconds. + */ +#define PLL_BYPASS_TIME 1 + +/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ +#define PLL_RESET_TIME 1 + +/* + * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 + * Units are micro seconds. + */ +#define PLL_LOCK_TIME 20 + +/** + * struct davinci_pll_clk - Main PLL clock (aka PLLOUT) + * @hw: clk_hw for the pll + * @base: Base memory address + * @pllm_min: The minimum allowable PLLM[PLLM] value + * @pllm_max: The maxiumum allowable PLLM[PLLM] value + * @pllm_mask: Bitmask for PLLM[PLLM] value + */ +struct davinci_pll_clk { + struct clk_hw hw; + void __iomem *base; + u32 pllm_min; + u32 pllm_max; + u32 pllm_mask; +}; + +#define to_davinci_pll_clk(_hw) \ + container_of((_hw), struct davinci_pll_clk, hw) + +static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + unsigned long rate = parent_rate; + u32 mult; + + mult = readl(pll->base + PLLM) & pll->pllm_mask; + rate *= mult + 1; + + return rate; +} + +static int davinci_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + struct clk_hw *parent = req->best_parent_hw; + unsigned long parent_rate = req->best_parent_rate; + unsigned long rate = req->rate; + unsigned long best_rate, r; + u32 mult; + + /* there is a limited range of valid outputs (see datasheet) */ + if (rate < req->min_rate) + return -EINVAL; + + rate = min(rate, req->max_rate); + mult = rate / parent_rate; + best_rate = parent_rate * mult; + + /* easy case when there is no PREDIV */ + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { + if (best_rate < req->min_rate) + return -EINVAL; + + if (mult < pll->pllm_min || mult > pll->pllm_max) + return -EINVAL; + + req->rate = best_rate; + + return 0; + } + + /* see if the PREDIV clock can help us */ + best_rate = 0; + + for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { + parent_rate = clk_hw_round_rate(parent, rate / mult); + r = parent_rate * mult; + if (r < req->min_rate) + continue; + if (r > rate || r > req->max_rate) + break; + if (r > best_rate) { + best_rate = r; + req->rate = best_rate; + req->best_parent_rate = parent_rate; + if (best_rate == rate) + break; + } + } + + return 0; +} + +static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + u32 mult; + + mult = rate / parent_rate; + writel(mult - 1, pll->base + PLLM); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry); +#else +#define davinci_pll_debug_init NULL +#endif + +static const struct clk_ops davinci_pll_ops = { + .recalc_rate = davinci_pll_recalc_rate, + .determine_rate = davinci_pll_determine_rate, + .set_rate = davinci_pll_set_rate, + .debug_init = davinci_pll_debug_init, +}; + +/* PLLM works differently on DM365 */ +static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + unsigned long rate = parent_rate; + u32 mult; + + mult = readl(pll->base + PLLM) & pll->pllm_mask; + rate *= mult * 2; + + return rate; +} + +static const struct clk_ops dm365_pll_ops = { + .recalc_rate = dm365_pll_recalc_rate, + .debug_init = davinci_pll_debug_init, +}; + +/** + * davinci_pll_div_register - common *DIV clock implementation + * @name: the clock name + * @parent_name: the parent clock name + * @reg: the *DIV register + * @fixed: if true, the divider is a fixed value + * @flags: bitmap of CLK_* flags from clock-provider.h + */ +static struct clk *davinci_pll_div_register(struct device *dev, + const char *name, + const char *parent_name, + void __iomem *reg, + bool fixed, u32 flags) +{ + const char * const *parent_names = parent_name ? &parent_name : NULL; + int num_parents = parent_name ? 1 : 0; + const struct clk_ops *divider_ops = &clk_divider_ops; + struct clk_gate *gate; + struct clk_divider *divider; + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = reg; + gate->bit_idx = DIV_ENABLE_SHIFT; + + divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + divider->reg = reg; + divider->shift = DIV_RATIO_SHIFT; + divider->width = DIV_RATIO_WIDTH; + + if (fixed) { + divider->flags |= CLK_DIVIDER_READ_ONLY; + divider_ops = &clk_divider_ro_ops; + } + + return clk_register_composite(dev, name, parent_names, num_parents, + NULL, NULL, ÷r->hw, divider_ops, + &gate->hw, &clk_gate_ops, flags); +} + +struct davinci_pllen_clk { + struct clk_hw hw; + void __iomem *base; +}; + +#define to_davinci_pllen_clk(_hw) \ + container_of((_hw), struct davinci_pllen_clk, hw) + +static const struct clk_ops davinci_pllen_ops = { + /* this clocks just uses the clock notification feature */ +}; + +/* + * The PLL has to be switched into bypass mode while we are chaning the rate, + * so we do that on the PLLEN clock since it is the end of the line. This will + * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are + * changed and will switch back to the PLL after the changes have been made. + */ +static int davinci_pllen_rate_change(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(cnd->clk); + struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); + u32 ctrl; + + ctrl = readl(pll->base + PLLCTL); + + if (flags == PRE_RATE_CHANGE) { + /* Switch the PLL to bypass mode */ + ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); + writel(ctrl, pll->base + PLLCTL); + + udelay(PLL_BYPASS_TIME); + + /* Reset and enable PLL */ + ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); + writel(ctrl, pll->base + PLLCTL); + } else { + udelay(PLL_RESET_TIME); + + /* Bring PLL out of reset */ + ctrl |= PLLCTL_PLLRST; + writel(ctrl, pll->base + PLLCTL); + + udelay(PLL_LOCK_TIME); + + /* Remove PLL from bypass mode */ + ctrl |= PLLCTL_PLLEN; + writel(ctrl, pll->base + PLLCTL); + } + + return NOTIFY_OK; +} + +static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev) +{ + struct davinci_pll_platform_data *pdata = dev_get_platdata(dev); + + /* + * Platform data is optional, so allocate a new struct if one was not + * provided. For device tree, this will always be the case. + */ + if (!pdata) + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return NULL; + + /* for device tree, we need to fill in the struct */ + if (dev->of_node) + pdata->cfgchip = + syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); + + return pdata; +} + +static struct notifier_block davinci_pllen_notifier = { + .notifier_call = davinci_pllen_rate_change, +}; + +/** + * davinci_pll_clk_register - Register a PLL clock + * @info: The device-specific clock info + * @parent_name: The parent clock name + * @base: The PLL's memory region + * + * This creates a series of clocks that represent the PLL. + * + * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN + * + * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL) + * - PREDIV and POSTDIV are optional (depends on the PLL controller) + * - PLL is the PLL output (aka PLLOUT) + * - PLLEN is the bypass multiplexer + * + * Returns: The PLLOUT clock or a negative error code. + */ +struct clk *davinci_pll_clk_register(struct device *dev, + const struct davinci_pll_clk_info *info, + const char *parent_name, + void __iomem *base) +{ + struct davinci_pll_platform_data *pdata; + char prediv_name[MAX_NAME_SIZE]; + char pllout_name[MAX_NAME_SIZE]; + char postdiv_name[MAX_NAME_SIZE]; + char pllen_name[MAX_NAME_SIZE]; + struct clk_init_data init; + struct davinci_pll_clk *pllout; + struct davinci_pllen_clk *pllen; + struct clk *pllout_clk, *clk; + + pdata = davinci_pll_get_pdata(dev); + if (!pdata) + return ERR_PTR(-ENOMEM); + + if (info->flags & PLL_HAS_CLKMODE) { + /* + * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL. + * We register a clock named "oscin" that serves as the internal + * "input clock" domain shared by both PLLs (if there are 2) + * and will be the parent clock to the AUXCLK, SYSCLKBP and + * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean + * a number of different things. In this driver we use it to + * mean the signal after the PLLCTL[CLKMODE] switch. + */ + clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME, + parent_name, 0, 1, 1); + if (IS_ERR(clk)) + return clk; + + parent_name = OSCIN_CLK_NAME; + } + + if (info->flags & PLL_HAS_PREDIV) { + bool fixed = info->flags & PLL_PREDIV_FIXED_DIV; + u32 flags = 0; + + snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name); + + if (info->flags & PLL_PREDIV_ALWAYS_ENABLED) + flags |= CLK_IS_CRITICAL; + + /* Some? DM355 chips don't correctly report the PREDIV value */ + if (info->flags & PLL_PREDIV_FIXED8) + clk = clk_register_fixed_factor(dev, prediv_name, + parent_name, flags, 1, 8); + else + clk = davinci_pll_div_register(dev, prediv_name, + parent_name, base + PREDIV, fixed, flags); + if (IS_ERR(clk)) + return clk; + + parent_name = prediv_name; + } + + /* Unlock writing to PLL registers */ + if (info->unlock_reg) { + if (IS_ERR_OR_NULL(pdata->cfgchip)) + dev_warn(dev, "Failed to get CFGCHIP (%ld)\n", + PTR_ERR(pdata->cfgchip)); + else + regmap_write_bits(pdata->cfgchip, info->unlock_reg, + info->unlock_mask, 0); + } + + pllout = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL); + if (!pllout) + return ERR_PTR(-ENOMEM); + + snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name); + + init.name = pllout_name; + if (info->flags & PLL_PLLM_2X) + init.ops = &dm365_pll_ops; + else + init.ops = &davinci_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = 0; + + if (info->flags & PLL_HAS_PREDIV) + init.flags |= CLK_SET_RATE_PARENT; + + pllout->hw.init = &init; + pllout->base = base; + pllout->pllm_mask = info->pllm_mask; + pllout->pllm_min = info->pllm_min; + pllout->pllm_max = info->pllm_max; + + pllout_clk = devm_clk_register(dev, &pllout->hw); + if (IS_ERR(pllout_clk)) + return pllout_clk; + + clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate, + info->pllout_max_rate); + + parent_name = pllout_name; + + if (info->flags & PLL_HAS_POSTDIV) { + bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV; + u32 flags = CLK_SET_RATE_PARENT; + + snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name); + + if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED) + flags |= CLK_IS_CRITICAL; + + clk = davinci_pll_div_register(dev, postdiv_name, parent_name, + base + POSTDIV, fixed, flags); + if (IS_ERR(clk)) + return clk; + + parent_name = postdiv_name; + } + + pllen = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL); + if (!pllen) + return ERR_PTR(-ENOMEM); + + snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name); + + init.name = pllen_name; + init.ops = &davinci_pllen_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; + + pllen->hw.init = &init; + pllen->base = base; + + clk = devm_clk_register(dev, &pllen->hw); + if (IS_ERR(clk)) + return clk; + + clk_notifier_register(clk, &davinci_pllen_notifier); + + return pllout_clk; +} + +/** + * davinci_pll_auxclk_register - Register bypass clock (AUXCLK) + * @name: The clock name + * @base: The PLL memory region + */ +struct clk *davinci_pll_auxclk_register(struct device *dev, + const char *name, + void __iomem *base) +{ + return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN, + CKEN_AUXEN_SHIFT, 0, NULL); +} + +/** + * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP) + * @name: The clock name + * @base: The PLL memory region + */ +struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, + const char *name, + void __iomem *base) +{ + return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV, + DIV_RATIO_SHIFT, DIV_RATIO_WIDTH, + CLK_DIVIDER_READ_ONLY, NULL); +} + +/** + * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK) + * @info: The clock info + * @base: The PLL memory region + */ +struct clk * +davinci_pll_obsclk_register(struct device *dev, + const struct davinci_pll_obsclk_info *info, + void __iomem *base) +{ + struct clk_mux *mux; + struct clk_gate *gate; + struct clk_divider *divider; + u32 oscdiv; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + mux->reg = base + OCSEL; + mux->table = info->table; + mux->mask = info->ocsrc_mask; + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = base + CKEN; + gate->bit_idx = CKEN_OBSCLK_SHIFT; + + divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + divider->reg = base + OSCDIV; + divider->shift = DIV_RATIO_SHIFT; + divider->width = DIV_RATIO_WIDTH; + + /* make sure divider is enabled just in case bootloader disabled it */ + oscdiv = readl(base + OSCDIV); + oscdiv |= BIT(DIV_ENABLE_SHIFT); + writel(oscdiv, base + OSCDIV); + + return clk_register_composite(dev, info->name, info->parent_names, + info->num_parents, + &mux->hw, &clk_mux_ops, + ÷r->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, 0); +} + +/* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */ +static int davinci_pll_sysclk_rate_change(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk)); + struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); + u32 pllcmd, pllstat; + + switch (flags) { + case POST_RATE_CHANGE: + /* apply the changes */ + pllcmd = readl(pll->base + PLLCMD); + pllcmd |= PLLCMD_GOSET; + writel(pllcmd, pll->base + PLLCMD); + /* fallthrough */ + case PRE_RATE_CHANGE: + /* Wait until for outstanding changes to take effect */ + do { + pllstat = readl(pll->base + PLLSTAT); + } while (pllstat & PLLSTAT_GOSTAT); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block davinci_pll_sysclk_notifier = { + .notifier_call = davinci_pll_sysclk_rate_change, +}; + +/** + * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn) + * @info: The clock info + * @base: The PLL memory region + */ +struct clk * +davinci_pll_sysclk_register(struct device *dev, + const struct davinci_pll_sysclk_info *info, + void __iomem *base) +{ + const struct clk_ops *divider_ops = &clk_divider_ops; + struct clk_gate *gate; + struct clk_divider *divider; + struct clk *clk; + u32 reg; + u32 flags = 0; + + /* PLLDIVn registers are not entirely consecutive */ + if (info->id < 4) + reg = PLLDIV1 + 4 * (info->id - 1); + else + reg = PLLDIV4 + 4 * (info->id - 4); + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = base + reg; + gate->bit_idx = DIV_ENABLE_SHIFT; + + divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + divider->reg = base + reg; + divider->shift = DIV_RATIO_SHIFT; + divider->width = info->ratio_width; + divider->flags = 0; + + if (info->flags & SYSCLK_FIXED_DIV) { + divider->flags |= CLK_DIVIDER_READ_ONLY; + divider_ops = &clk_divider_ro_ops; + } + + /* Only the ARM clock can change the parent PLL rate */ + if (info->flags & SYSCLK_ARM_RATE) + flags |= CLK_SET_RATE_PARENT; + + if (info->flags & SYSCLK_ALWAYS_ENABLED) + flags |= CLK_IS_CRITICAL; + + clk = clk_register_composite(dev, info->name, &info->parent_name, 1, + NULL, NULL, ÷r->hw, divider_ops, + &gate->hw, &clk_gate_ops, flags); + if (IS_ERR(clk)) + return clk; + + clk_notifier_register(clk, &davinci_pll_sysclk_notifier); + + return clk; +} + +int of_davinci_pll_init(struct device *dev, + const struct davinci_pll_clk_info *info, + const struct davinci_pll_obsclk_info *obsclk_info, + const struct davinci_pll_sysclk_info **div_info, + u8 max_sysclk_id, + void __iomem *base) +{ + struct device_node *node = dev->of_node; + struct device_node *child; + const char *parent_name; + struct clk *clk; + + if (info->flags & PLL_HAS_CLKMODE) + parent_name = of_clk_get_parent_name(node, 0); + else + parent_name = OSCIN_CLK_NAME; + + clk = davinci_pll_clk_register(dev, info, parent_name, base); + if (IS_ERR(clk)) { + dev_err(dev, "failed to register %s\n", info->name); + return PTR_ERR(clk); + } + + child = of_get_child_by_name(node, "pllout"); + if (of_device_is_available(child)) + of_clk_add_provider(child, of_clk_src_simple_get, clk); + of_node_put(child); + + child = of_get_child_by_name(node, "sysclk"); + if (of_device_is_available(child)) { + struct clk_onecell_data *clk_data; + struct clk **clks; + int n_clks = max_sysclk_id + 1; + int i; + + clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clks = devm_kmalloc_array(dev, n_clks, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + + clk_data->clks = clks; + clk_data->clk_num = n_clks; + + for (i = 0; i < n_clks; i++) + clks[i] = ERR_PTR(-ENOENT); + + for (; *div_info; div_info++) { + clk = davinci_pll_sysclk_register(dev, *div_info, base); + if (IS_ERR(clk)) + dev_warn(dev, "failed to register %s (%ld)\n", + (*div_info)->name, PTR_ERR(clk)); + else + clks[(*div_info)->id] = clk; + } + of_clk_add_provider(child, of_clk_src_onecell_get, clk_data); + } + of_node_put(child); + + child = of_get_child_by_name(node, "auxclk"); + if (of_device_is_available(child)) { + char child_name[MAX_NAME_SIZE]; + + snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name); + + clk = davinci_pll_auxclk_register(dev, child_name, base); + if (IS_ERR(clk)) + dev_warn(dev, "failed to register %s (%ld)\n", + child_name, PTR_ERR(clk)); + else + of_clk_add_provider(child, of_clk_src_simple_get, clk); + } + of_node_put(child); + + child = of_get_child_by_name(node, "obsclk"); + if (of_device_is_available(child)) { + if (obsclk_info) + clk = davinci_pll_obsclk_register(dev, obsclk_info, base); + else + clk = ERR_PTR(-EINVAL); + + if (IS_ERR(clk)) + dev_warn(dev, "failed to register obsclk (%ld)\n", + PTR_ERR(clk)); + else + of_clk_add_provider(child, of_clk_src_simple_get, clk); + } + of_node_put(child); + + return 0; +} + +static const struct of_device_id davinci_pll_of_match[] = { + { } +}; + +static const struct platform_device_id davinci_pll_id_table[] = { + { } +}; + +typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base); + +static int davinci_pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id; + davinci_pll_init pll_init = NULL; + struct resource *res; + void __iomem *base; + + of_id = of_match_device(davinci_pll_of_match, dev); + if (of_id) + pll_init = of_id->data; + else if (pdev->id_entry) + pll_init = (void *)pdev->id_entry->driver_data; + + if (!pll_init) { + dev_err(dev, "unable to find driver data\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + dev_err(dev, "ioremap failed\n"); + return PTR_ERR(base); + } + + return pll_init(dev, base); +} + +static struct platform_driver davinci_pll_driver = { + .probe = davinci_pll_probe, + .driver = { + .name = "davinci-pll-clk", + .of_match_table = davinci_pll_of_match, + }, + .id_table = davinci_pll_id_table, +}; + +static int __init davinci_pll_driver_init(void) +{ + return platform_driver_register(&davinci_pll_driver); +} + +/* has to be postcore_initcall because PSC devices depend on PLL parent clocks */ +postcore_initcall(davinci_pll_driver_init); + +#ifdef CONFIG_DEBUG_FS +#include + +#define DEBUG_REG(n) \ +{ \ + .name = #n, \ + .offset = n, \ +} + +static const struct debugfs_reg32 davinci_pll_regs[] = { + DEBUG_REG(REVID), + DEBUG_REG(PLLCTL), + DEBUG_REG(OCSEL), + DEBUG_REG(PLLSECCTL), + DEBUG_REG(PLLM), + DEBUG_REG(PREDIV), + DEBUG_REG(PLLDIV1), + DEBUG_REG(PLLDIV2), + DEBUG_REG(PLLDIV3), + DEBUG_REG(OSCDIV), + DEBUG_REG(POSTDIV), + DEBUG_REG(BPDIV), + DEBUG_REG(PLLCMD), + DEBUG_REG(PLLSTAT), + DEBUG_REG(ALNCTL), + DEBUG_REG(DCHANGE), + DEBUG_REG(CKEN), + DEBUG_REG(CKSTAT), + DEBUG_REG(SYSTAT), + DEBUG_REG(PLLDIV4), + DEBUG_REG(PLLDIV5), + DEBUG_REG(PLLDIV6), + DEBUG_REG(PLLDIV7), + DEBUG_REG(PLLDIV8), + DEBUG_REG(PLLDIV9), +}; + +static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + struct debugfs_regset32 *regset; + struct dentry *d; + + regset = kzalloc(sizeof(*regset), GFP_KERNEL); + if (!regset) + return -ENOMEM; + + regset->regs = davinci_pll_regs; + regset->nregs = ARRAY_SIZE(davinci_pll_regs); + regset->base = pll->base; + + d = debugfs_create_regset32("registers", 0400, dentry, regset); + if (IS_ERR(d)) { + kfree(regset); + return PTR_ERR(d); + } + + return 0; +} +#endif diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h new file mode 100644 index 000000000000..52103aeeceec --- /dev/null +++ b/drivers/clk/davinci/pll.h @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock driver for TI Davinci PSC controllers + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __CLK_DAVINCI_PLL_H___ +#define __CLK_DAVINCI_PLL_H___ + +#include +#include +#include +#include + +#define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */ +#define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */ +#define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */ +#define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */ +#define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */ +#define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */ +#define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */ +#define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */ +#define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */ +#define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */ + +/** davinci_pll_clk_info - controller-specific PLL info + * @name: The name of the PLL + * @unlock_reg: Option CFGCHIP register for unlocking PLL + * @unlock_mask: Bitmask used with @unlock_reg + * @pllm_mask: Bitmask for PLLM[PLLM] value + * @pllm_min: Minimum allowable value for PLLM[PLLM] + * @pllm_max: Maximum allowable value for PLLM[PLLM] + * @pllout_min_rate: Minimum allowable rate for PLLOUT + * @pllout_max_rate: Maximum allowable rate for PLLOUT + * @flags: Bitmap of PLL_* flags. + */ +struct davinci_pll_clk_info { + const char *name; + u32 unlock_reg; + u32 unlock_mask; + u32 pllm_mask; + u32 pllm_min; + u32 pllm_max; + unsigned long pllout_min_rate; + unsigned long pllout_max_rate; + u32 flags; +}; + +#define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */ +#define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */ +#define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */ + +/** davinci_pll_sysclk_info - SYSCLKn-specific info + * @name: The name of the clock + * @parent_name: The name of the parent clock + * @id: "n" in "SYSCLKn" + * @ratio_width: Width (in bits) of RATIO in PLLDIVn register + * @flags: Bitmap of SYSCLK_* flags. + */ +struct davinci_pll_sysclk_info { + const char *name; + const char *parent_name; + u32 id; + u32 ratio_width; + u32 flags; +}; + +#define SYSCLK(i, n, p, w, f) \ +static const struct davinci_pll_sysclk_info n = { \ + .name = #n, \ + .parent_name = #p, \ + .id = (i), \ + .ratio_width = (w), \ + .flags = (f), \ +} + +/** davinci_pll_obsclk_info - OBSCLK-specific info + * @name: The name of the clock + * @parent_names: Array of names of the parent clocks + * @num_parents: Length of @parent_names + * @table: Array of values to write to OCSEL[OCSRC] cooresponding to + * @parent_names + * @ocsrc_mask: Bitmask for OCSEL[OCSRC] + */ +struct davinci_pll_obsclk_info { + const char *name; + const char * const *parent_names; + u8 num_parents; + u32 *table; + u32 ocsrc_mask; +}; + +struct clk *davinci_pll_clk_register(struct device *dev, + const struct davinci_pll_clk_info *info, + const char *parent_name, + void __iomem *base); +struct clk *davinci_pll_auxclk_register(struct device *dev, + const char *name, + void __iomem *base); +struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, + const char *name, + void __iomem *base); +struct clk * +davinci_pll_obsclk_register(struct device *dev, + const struct davinci_pll_obsclk_info *info, + void __iomem *base); +struct clk * +davinci_pll_sysclk_register(struct device *dev, + const struct davinci_pll_sysclk_info *info, + void __iomem *base); + +int of_davinci_pll_init(struct device *dev, + const struct davinci_pll_clk_info *info, + const struct davinci_pll_obsclk_info *obsclk_info, + const struct davinci_pll_sysclk_info **div_info, + u8 max_sysclk_id, + void __iomem *base); + +#endif /* __CLK_DAVINCI_PLL_H___ */ diff --git a/include/linux/platform_data/clk-davinci-pll.h b/include/linux/platform_data/clk-davinci-pll.h new file mode 100644 index 000000000000..e55dab1d578b --- /dev/null +++ b/include/linux/platform_data/clk-davinci-pll.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLL clock driver for TI Davinci SoCs + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ +#define __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ + +#include + +/** + * davinci_pll_platform_data + * @cfgchip: CFGCHIP syscon regmap + */ +struct davinci_pll_platform_data { + struct regmap *cfgchip; +}; + +#endif /* __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ */ -- cgit v1.2.3 From 1e88a8d64f221208801bb279ee7452df0b6d609f Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 15 Mar 2018 21:52:34 -0500 Subject: clk: davinci: New driver for TI DA8XX CFGCHIP clocks This adds a new driver for the gate and multiplexer clocks in the CFGCHIPn syscon registers on TI DA8XX-type SoCs. Signed-off-by: David Lechner Signed-off-by: Stephen Boyd --- drivers/clk/davinci/Makefile | 2 + drivers/clk/davinci/da8xx-cfgchip.c | 439 ++++++++++++++++++++++++ include/linux/platform_data/clk-da8xx-cfgchip.h | 21 ++ 3 files changed, 462 insertions(+) create mode 100644 drivers/clk/davinci/da8xx-cfgchip.c create mode 100644 include/linux/platform_data/clk-da8xx-cfgchip.h (limited to 'include/linux') diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile index 6c388d44162d..11178b79b483 100644 --- a/drivers/clk/davinci/Makefile +++ b/drivers/clk/davinci/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 ifeq ($(CONFIG_COMMON_CLK), y) +obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o + obj-y += pll.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o diff --git a/drivers/clk/davinci/da8xx-cfgchip.c b/drivers/clk/davinci/da8xx-cfgchip.c new file mode 100644 index 000000000000..880a77ace273 --- /dev/null +++ b/drivers/clk/davinci/da8xx-cfgchip.c @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP + * + * Copyright (C) 2018 David Lechner + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* --- Gate clocks --- */ + +#define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1) + +struct da8xx_cfgchip_gate_clk_info { + const char *name; + u32 cfgchip; + u32 bit; + u32 flags; +}; + +struct da8xx_cfgchip_gate_clk { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; +}; + +#define to_da8xx_cfgchip_gate_clk(_hw) \ + container_of((_hw), struct da8xx_cfgchip_gate_clk, hw) + +static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw) +{ + struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); + + return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); +} + +static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw) +{ + struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); + + regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); +} + +static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw) +{ + struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); + unsigned int val; + + regmap_read(clk->regmap, clk->reg, &val); + + return !!(val & clk->mask); +} + +static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* this clock divides by 4.5 */ + return parent_rate * 2 / 9; +} + +static const struct clk_ops da8xx_cfgchip_gate_clk_ops = { + .enable = da8xx_cfgchip_gate_clk_enable, + .disable = da8xx_cfgchip_gate_clk_disable, + .is_enabled = da8xx_cfgchip_gate_clk_is_enabled, +}; + +static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = { + .enable = da8xx_cfgchip_gate_clk_enable, + .disable = da8xx_cfgchip_gate_clk_disable, + .is_enabled = da8xx_cfgchip_gate_clk_is_enabled, + .recalc_rate = da8xx_cfgchip_div4p5_recalc_rate, +}; + +static struct da8xx_cfgchip_gate_clk * __init +da8xx_cfgchip_gate_clk_register(struct device *dev, + const struct da8xx_cfgchip_gate_clk_info *info, + struct regmap *regmap) +{ + struct clk *parent; + const char *parent_name; + struct da8xx_cfgchip_gate_clk *gate; + struct clk_init_data init; + int ret; + + parent = devm_clk_get(dev, NULL); + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name = __clk_get_name(parent); + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = info->name; + if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5) + init.ops = &da8xx_cfgchip_div4p5_clk_ops; + else + init.ops = &da8xx_cfgchip_gate_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = 0; + + gate->hw.init = &init; + gate->regmap = regmap; + gate->reg = info->cfgchip; + gate->mask = info->bit; + + ret = devm_clk_hw_register(dev, &gate->hw); + if (ret < 0) + return ERR_PTR(ret); + + return gate; +} + +static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = { + .name = "ehrpwm_tbclk", + .cfgchip = CFGCHIP(1), + .bit = CFGCHIP1_TBCLKSYNC, +}; + +static int __init da8xx_cfgchip_register_tbclk(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_gate_clk *gate; + + gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info, + regmap); + if (IS_ERR(gate)) + return PTR_ERR(gate); + + clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0"); + clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1"); + + return 0; +} + +static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = { + .name = "div4.5", + .cfgchip = CFGCHIP(3), + .bit = CFGCHIP3_DIV45PENA, + .flags = DA8XX_GATE_CLOCK_IS_DIV4P5, +}; + +static int __init da8xx_cfgchip_register_div4p5(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_gate_clk *gate; + + gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap); + if (IS_ERR(gate)) + return PTR_ERR(gate); + + return 0; +} + +static int __init +of_da8xx_cfgchip_gate_clk_init(struct device *dev, + const struct da8xx_cfgchip_gate_clk_info *info, + struct regmap *regmap) +{ + struct da8xx_cfgchip_gate_clk *gate; + + gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap); + if (IS_ERR(gate)) + return PTR_ERR(gate); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate); +} + +static int __init of_da8xx_tbclksync_init(struct device *dev, + struct regmap *regmap) +{ + return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap); +} + +static int __init of_da8xx_div4p5ena_init(struct device *dev, + struct regmap *regmap) +{ + return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap); +} + +/* --- MUX clocks --- */ + +struct da8xx_cfgchip_mux_clk_info { + const char *name; + const char *parent0; + const char *parent1; + u32 cfgchip; + u32 bit; +}; + +struct da8xx_cfgchip_mux_clk { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; +}; + +#define to_da8xx_cfgchip_mux_clk(_hw) \ + container_of((_hw), struct da8xx_cfgchip_mux_clk, hw) + +static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw); + unsigned int val = index ? clk->mask : 0; + + return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); +} + +static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw) +{ + struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw); + unsigned int val; + + regmap_read(clk->regmap, clk->reg, &val); + + return (val & clk->mask) ? 1 : 0; +} + +static const struct clk_ops da8xx_cfgchip_mux_clk_ops = { + .set_parent = da8xx_cfgchip_mux_clk_set_parent, + .get_parent = da8xx_cfgchip_mux_clk_get_parent, +}; + +static struct da8xx_cfgchip_mux_clk * __init +da8xx_cfgchip_mux_clk_register(struct device *dev, + const struct da8xx_cfgchip_mux_clk_info *info, + struct regmap *regmap) +{ + const char * const parent_names[] = { info->parent0, info->parent1 }; + struct da8xx_cfgchip_mux_clk *mux; + struct clk_init_data init; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + init.name = info->name; + init.ops = &da8xx_cfgchip_mux_clk_ops; + init.parent_names = parent_names; + init.num_parents = 2; + init.flags = 0; + + mux->hw.init = &init; + mux->regmap = regmap; + mux->reg = info->cfgchip; + mux->mask = info->bit; + + ret = devm_clk_hw_register(dev, &mux->hw); + if (ret < 0) + return ERR_PTR(ret); + + return mux; +} + +static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = { + .name = "async1", + .parent0 = "pll0_sysclk3", + .parent1 = "div4.5", + .cfgchip = CFGCHIP(3), + .bit = CFGCHIP3_EMA_CLKSRC, +}; + +static int __init da8xx_cfgchip_register_async1(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_mux_clk *mux; + + mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0"); + + return 0; +} + +static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = { + .name = "async3", + .parent0 = "pll0_sysclk2", + .parent1 = "pll1_sysclk2", + .cfgchip = CFGCHIP(3), + .bit = CFGCHIP3_ASYNC3_CLKSRC, +}; + +static int __init da850_cfgchip_register_async3(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_mux_clk *mux; + struct clk_hw *parent; + + mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1"); + + /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */ + parent = clk_hw_get_parent_by_index(&mux->hw, 1); + if (parent) + clk_set_parent(mux->hw.clk, parent->clk); + else + dev_warn(dev, "Failed to find async3 parent clock\n"); + + return 0; +} + +static int __init +of_da8xx_cfgchip_init_mux_clock(struct device *dev, + const struct da8xx_cfgchip_mux_clk_info *info, + struct regmap *regmap) +{ + struct da8xx_cfgchip_mux_clk *mux; + + mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw); +} + +static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap) +{ + return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap); +} + +static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap) +{ + return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap); +} + +/* --- platform device --- */ + +static const struct of_device_id da8xx_cfgchip_of_match[] = { + { + .compatible = "ti,da830-tbclksync", + .data = of_da8xx_tbclksync_init, + }, + { + .compatible = "ti,da830-div4p5ena", + .data = of_da8xx_div4p5ena_init, + }, + { + .compatible = "ti,da850-async1-clksrc", + .data = of_da850_async1_init, + }, + { + .compatible = "ti,da850-async3-clksrc", + .data = of_da850_async3_init, + }, + { } +}; + +static const struct platform_device_id da8xx_cfgchip_id_table[] = { + { + .name = "da830-tbclksync", + .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk, + }, + { + .name = "da830-div4p5ena", + .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5, + }, + { + .name = "da850-async1-clksrc", + .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1, + }, + { + .name = "da850-async3-clksrc", + .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3, + }, + { } +}; + +typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap); + +static int da8xx_cfgchip_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data; + const struct of_device_id *of_id; + da8xx_cfgchip_init clk_init = NULL; + struct regmap *regmap = NULL; + + of_id = of_match_device(da8xx_cfgchip_of_match, dev); + if (of_id) { + struct device_node *parent; + + clk_init = of_id->data; + parent = of_get_parent(dev->of_node); + regmap = syscon_node_to_regmap(parent); + of_node_put(parent); + } else if (pdev->id_entry && pdata) { + clk_init = (void *)pdev->id_entry->driver_data; + regmap = pdata->cfgchip; + } + + if (!clk_init) { + dev_err(dev, "unable to find driver data\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(regmap)) { + dev_err(dev, "no regmap for CFGCHIP syscon\n"); + return regmap ? PTR_ERR(regmap) : -ENOENT; + } + + return clk_init(dev, regmap); +} + +static struct platform_driver da8xx_cfgchip_driver = { + .probe = da8xx_cfgchip_probe, + .driver = { + .name = "da8xx-cfgchip-clk", + .of_match_table = da8xx_cfgchip_of_match, + }, + .id_table = da8xx_cfgchip_id_table, +}; + +static int __init da8xx_cfgchip_driver_init(void) +{ + return platform_driver_register(&da8xx_cfgchip_driver); +} + +/* has to be postcore_initcall because PSC devices depend on the async3 clock */ +postcore_initcall(da8xx_cfgchip_driver_init); diff --git a/include/linux/platform_data/clk-da8xx-cfgchip.h b/include/linux/platform_data/clk-da8xx-cfgchip.h new file mode 100644 index 000000000000..de0f77d38669 --- /dev/null +++ b/include/linux/platform_data/clk-da8xx-cfgchip.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-da8xx-cfgchip - TI DaVinci DA8xx CFGCHIP clock driver + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ +#define __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ + +#include + +/** + * da8xx_cfgchip_clk_platform_data + * @cfgchip: CFGCHIP syscon regmap + */ +struct da8xx_cfgchip_clk_platform_data { + struct regmap *cfgchip; +}; + +#endif /* __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ */ -- cgit v1.2.3 From 97cc3264508f33783ba21573204d7e0bf5b197e7 Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Tue, 20 Mar 2018 17:05:15 -0400 Subject: svcrdma: Consult max_qp_init_rd_atom when accepting connections The target needs to return the lesser of the client's Inbound RDMA Read Queue Depth (IRD), provided in the connection parameters, and the local device's Outbound RDMA Read Queue Depth (ORD). The latter limit is max_qp_init_rd_atom, not max_qp_rd_atom. The svcrdma_ord value caps the ORD value for iWARP transports, which do not exchange ORD/IRD values at connection time. Since no other Linux kernel RDMA-enabled storage target sees fit to provide this cap, I'm removing it here too. initiator_depth is a u8, so ensure the computed ORD value does not overflow that field. Signed-off-by: Chuck Lever Signed-off-by: J. Bruce Fields --- include/linux/sunrpc/svc_rdma.h | 3 --- net/sunrpc/xprtrdma/svc_rdma.c | 4 ++-- net/sunrpc/xprtrdma/svc_rdma_transport.c | 22 +++++++++------------- 3 files changed, 11 insertions(+), 18 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sunrpc/svc_rdma.h b/include/linux/sunrpc/svc_rdma.h index 4b731b046bcd..7337e1221590 100644 --- a/include/linux/sunrpc/svc_rdma.h +++ b/include/linux/sunrpc/svc_rdma.h @@ -132,9 +132,6 @@ struct svcxprt_rdma { #define RDMAXPRT_CONN_PENDING 3 #define RPCRDMA_LISTEN_BACKLOG 10 -/* The default ORD value is based on two outstanding full-size writes with a - * page size of 4k, or 32k * 2 ops / 4k = 16 outstanding RDMA_READ. */ -#define RPCRDMA_ORD (64/4) #define RPCRDMA_MAX_REQUESTS 32 /* Typical ULP usage of BC requests is NFSv4.1 backchannel. Our diff --git a/net/sunrpc/xprtrdma/svc_rdma.c b/net/sunrpc/xprtrdma/svc_rdma.c index a4a8f6989ee7..dd8a431dc2ae 100644 --- a/net/sunrpc/xprtrdma/svc_rdma.c +++ b/net/sunrpc/xprtrdma/svc_rdma.c @@ -51,9 +51,9 @@ #define RPCDBG_FACILITY RPCDBG_SVCXPRT /* RPC/RDMA parameters */ -unsigned int svcrdma_ord = RPCRDMA_ORD; +unsigned int svcrdma_ord = 16; /* historical default */ static unsigned int min_ord = 1; -static unsigned int max_ord = 4096; +static unsigned int max_ord = 255; unsigned int svcrdma_max_requests = RPCRDMA_MAX_REQUESTS; unsigned int svcrdma_max_bc_requests = RPCRDMA_MAX_BC_REQUESTS; static unsigned int min_max_requests = 4; diff --git a/net/sunrpc/xprtrdma/svc_rdma_transport.c b/net/sunrpc/xprtrdma/svc_rdma_transport.c index 135ae175ca8e..7b2f4d3a2543 100644 --- a/net/sunrpc/xprtrdma/svc_rdma_transport.c +++ b/net/sunrpc/xprtrdma/svc_rdma_transport.c @@ -762,13 +762,6 @@ static struct svc_xprt *svc_rdma_accept(struct svc_xprt *xprt) if (!svc_rdma_prealloc_ctxts(newxprt)) goto errout; - /* - * Limit ORD based on client limit, local device limit, and - * configured svcrdma limit. - */ - newxprt->sc_ord = min_t(size_t, dev->attrs.max_qp_rd_atom, newxprt->sc_ord); - newxprt->sc_ord = min_t(size_t, svcrdma_ord, newxprt->sc_ord); - newxprt->sc_pd = ib_alloc_pd(dev, 0); if (IS_ERR(newxprt->sc_pd)) { dprintk("svcrdma: error creating PD for connect request\n"); @@ -843,15 +836,18 @@ static struct svc_xprt *svc_rdma_accept(struct svc_xprt *xprt) set_bit(RDMAXPRT_CONN_PENDING, &newxprt->sc_flags); memset(&conn_param, 0, sizeof conn_param); conn_param.responder_resources = 0; - conn_param.initiator_depth = newxprt->sc_ord; + conn_param.initiator_depth = min_t(int, newxprt->sc_ord, + dev->attrs.max_qp_init_rd_atom); + if (!conn_param.initiator_depth) { + dprintk("svcrdma: invalid ORD setting\n"); + ret = -EINVAL; + goto errout; + } conn_param.private_data = &pmsg; conn_param.private_data_len = sizeof(pmsg); ret = rdma_accept(newxprt->sc_cm_id, &conn_param); - if (ret) { - dprintk("svcrdma: failed to accept new connection, ret=%d\n", - ret); + if (ret) goto errout; - } dprintk("svcrdma: new connection %p accepted:\n", newxprt); sap = (struct sockaddr *)&newxprt->sc_cm_id->route.addr.src_addr; @@ -862,7 +858,7 @@ static struct svc_xprt *svc_rdma_accept(struct svc_xprt *xprt) dprintk(" sq_depth : %d\n", newxprt->sc_sq_depth); dprintk(" rdma_rw_ctxs : %d\n", ctxts); dprintk(" max_requests : %d\n", newxprt->sc_max_requests); - dprintk(" ord : %d\n", newxprt->sc_ord); + dprintk(" ord : %d\n", conn_param.initiator_depth); return &newxprt->sc_xprt; -- cgit v1.2.3 From 66afdedf269cf485efb5affb30c34e1f37705445 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 12 Feb 2018 09:53:12 +0100 Subject: extcon: gpio: Localize platform data Nothing in the entire kernel #includes so move the platform data declaration inside of the driver. Signed-off-by: Linus Walleij Signed-off-by: Chanwoo Choi --- drivers/extcon/extcon-gpio.c | 22 +++++++++++++++++- include/linux/extcon/extcon-gpio.h | 47 -------------------------------------- 2 files changed, 21 insertions(+), 48 deletions(-) delete mode 100644 include/linux/extcon/extcon-gpio.h (limited to 'include/linux') diff --git a/drivers/extcon/extcon-gpio.c b/drivers/extcon/extcon-gpio.c index ab770adcca7e..5f88f36cc54e 100644 --- a/drivers/extcon/extcon-gpio.c +++ b/drivers/extcon/extcon-gpio.c @@ -18,7 +18,6 @@ */ #include -#include #include #include #include @@ -29,6 +28,27 @@ #include #include +/** + * struct gpio_extcon_pdata - A simple GPIO-controlled extcon device. + * @extcon_id: The unique id of specific external connector. + * @gpio: Corresponding GPIO. + * @gpio_active_low: Boolean describing whether gpio active state is 1 or 0 + * If true, low state of gpio means active. + * If false, high state of gpio means active. + * @debounce: Debounce time for GPIO IRQ in ms. + * @irq_flags: IRQ Flags (e.g., IRQF_TRIGGER_LOW). + * @check_on_resume: Boolean describing whether to check the state of gpio + * while resuming from sleep. + */ +struct gpio_extcon_pdata { + unsigned int extcon_id; + unsigned gpio; + bool gpio_active_low; + unsigned long debounce; + unsigned long irq_flags; + bool check_on_resume; +}; + struct gpio_extcon_data { struct extcon_dev *edev; int irq; diff --git a/include/linux/extcon/extcon-gpio.h b/include/linux/extcon/extcon-gpio.h deleted file mode 100644 index 7cacafb78b09..000000000000 --- a/include/linux/extcon/extcon-gpio.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Single-state GPIO extcon driver based on extcon class - * - * Copyright (C) 2012 Samsung Electronics - * Author: MyungJoo Ham - * - * based on switch class driver - * Copyright (C) 2008 Google, Inc. - * Author: Mike Lockwood - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __EXTCON_GPIO_H__ -#define __EXTCON_GPIO_H__ __FILE__ - -#include - -/** - * struct gpio_extcon_pdata - A simple GPIO-controlled extcon device. - * @extcon_id: The unique id of specific external connector. - * @gpio: Corresponding GPIO. - * @gpio_active_low: Boolean describing whether gpio active state is 1 or 0 - * If true, low state of gpio means active. - * If false, high state of gpio means active. - * @debounce: Debounce time for GPIO IRQ in ms. - * @irq_flags: IRQ Flags (e.g., IRQF_TRIGGER_LOW). - * @check_on_resume: Boolean describing whether to check the state of gpio - * while resuming from sleep. - */ -struct gpio_extcon_pdata { - unsigned int extcon_id; - unsigned gpio; - bool gpio_active_low; - unsigned long debounce; - unsigned long irq_flags; - - bool check_on_resume; -}; - -#endif /* __EXTCON_GPIO_H__ */ -- cgit v1.2.3 From e7bfb3fdbde3bfeeeb64e2d73ac6babe59519c9e Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 12 Feb 2018 22:03:11 +0100 Subject: mtd: Stop updating erase_info->state and calling mtd_erase_callback() MTD users are no longer checking erase_info->state to determine if the erase operation failed or succeeded. Moreover, mtd_erase_callback() is now a NOP. We can safely get rid of all mtd_erase_callback() calls and all erase_info->state assignments. While at it, get rid of the erase_info->state field, all MTD_ERASE_XXX definitions and the mtd_erase_callback() function. Signed-off-by: Boris Brezillon Reviewed-by: Richard Weinberger Reviewed-by: Miquel Raynal Acked-by: Bert Kenward --- Changes in v2: - Address a few coding style issues (reported by Miquel) - Remove comments that are no longer valid (reported by Miquel) --- drivers/mtd/chips/cfi_cmdset_0001.c | 16 ++-------------- drivers/mtd/chips/cfi_cmdset_0002.c | 26 +++----------------------- drivers/mtd/chips/cfi_cmdset_0020.c | 3 --- drivers/mtd/chips/map_ram.c | 2 -- drivers/mtd/devices/bcm47xxsflash.c | 9 +-------- drivers/mtd/devices/block2mtd.c | 7 +------ drivers/mtd/devices/docg3.c | 16 ++-------------- drivers/mtd/devices/lart.c | 6 ------ drivers/mtd/devices/mtd_dataflash.c | 4 ---- drivers/mtd/devices/mtdram.c | 3 +-- drivers/mtd/devices/phram.c | 7 ------- drivers/mtd/devices/pmc551.c | 2 -- drivers/mtd/devices/powernv_flash.c | 12 ++---------- drivers/mtd/devices/slram.c | 7 +------ drivers/mtd/devices/spear_smi.c | 3 --- drivers/mtd/devices/sst25l.c | 3 --- drivers/mtd/devices/st_spi_fsm.c | 4 ---- drivers/mtd/lpddr/lpddr2_nvm.c | 10 ++-------- drivers/mtd/lpddr/lpddr_cmds.c | 2 -- drivers/mtd/mtdconcat.c | 1 - drivers/mtd/mtdcore.c | 6 ++---- drivers/mtd/mtdpart.c | 5 ----- drivers/mtd/nand/nand_base.c | 16 ++++------------ drivers/mtd/onenand/onenand_base.c | 17 ----------------- drivers/mtd/spi-nor/spi-nor.c | 3 --- drivers/mtd/ubi/gluebi.c | 3 --- drivers/net/ethernet/sfc/falcon/mtd.c | 11 +---------- drivers/net/ethernet/sfc/mtd.c | 11 +---------- drivers/staging/goldfish/goldfish_nand.c | 3 --- include/linux/mtd/mtd.h | 9 --------- 30 files changed, 23 insertions(+), 204 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c index 5e1b68cbcd0a..d4c07b85f18e 100644 --- a/drivers/mtd/chips/cfi_cmdset_0001.c +++ b/drivers/mtd/chips/cfi_cmdset_0001.c @@ -1993,20 +1993,8 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, static int cfi_intelext_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) { - unsigned long ofs, len; - int ret; - - ofs = instr->addr; - len = instr->len; - - ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL); - if (ret) - return ret; - - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - - return 0; + return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr, + instr->len, NULL); } static void cfi_intelext_sync (struct mtd_info *mtd) diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c index 56aa6b75213d..668e2cbc155b 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c @@ -2415,20 +2415,8 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) { - unsigned long ofs, len; - int ret; - - ofs = instr->addr; - len = instr->len; - - ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL); - if (ret) - return ret; - - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - - return 0; + return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr, + instr->len, NULL); } @@ -2436,7 +2424,6 @@ static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) { struct map_info *map = mtd->priv; struct cfi_private *cfi = map->fldrv_priv; - int ret = 0; if (instr->addr != 0) return -EINVAL; @@ -2444,14 +2431,7 @@ static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) if (instr->len != mtd->size) return -EINVAL; - ret = do_erase_chip(map, &cfi->chips[0]); - if (ret) - return ret; - - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - - return 0; + return do_erase_chip(map, &cfi->chips[0]); } static int do_atmel_lock(struct map_info *map, struct flchip *chip, diff --git a/drivers/mtd/chips/cfi_cmdset_0020.c b/drivers/mtd/chips/cfi_cmdset_0020.c index 7d342965f392..7b7658a05036 100644 --- a/drivers/mtd/chips/cfi_cmdset_0020.c +++ b/drivers/mtd/chips/cfi_cmdset_0020.c @@ -965,9 +965,6 @@ static int cfi_staa_erase_varsize(struct mtd_info *mtd, } } - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - return 0; } diff --git a/drivers/mtd/chips/map_ram.c b/drivers/mtd/chips/map_ram.c index 1cd0fff0e940..c37fce926864 100644 --- a/drivers/mtd/chips/map_ram.c +++ b/drivers/mtd/chips/map_ram.c @@ -131,8 +131,6 @@ static int mapram_erase (struct mtd_info *mtd, struct erase_info *instr) allff = map_word_ff(map); for (i=0; ilen; i += map_bankwidth(map)) map_write(map, allff, instr->addr + i); - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); return 0; } diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c index 6b84947cfbea..9baa81b8780c 100644 --- a/drivers/mtd/devices/bcm47xxsflash.c +++ b/drivers/mtd/devices/bcm47xxsflash.c @@ -68,7 +68,6 @@ static int bcm47xxsflash_poll(struct bcm47xxsflash *b47s, int timeout) static int bcm47xxsflash_erase(struct mtd_info *mtd, struct erase_info *erase) { struct bcm47xxsflash *b47s = mtd->priv; - int err; switch (b47s->type) { case BCM47XXSFLASH_TYPE_ST: @@ -89,13 +88,7 @@ static int bcm47xxsflash_erase(struct mtd_info *mtd, struct erase_info *erase) break; } - err = bcm47xxsflash_poll(b47s, HZ); - if (err) - erase->state = MTD_ERASE_FAILED; - else - erase->state = MTD_ERASE_DONE; - - return err; + return bcm47xxsflash_poll(b47s, HZ); } static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len, diff --git a/drivers/mtd/devices/block2mtd.c b/drivers/mtd/devices/block2mtd.c index bb0734600a07..c9e424993e37 100644 --- a/drivers/mtd/devices/block2mtd.c +++ b/drivers/mtd/devices/block2mtd.c @@ -88,17 +88,12 @@ static int block2mtd_erase(struct mtd_info *mtd, struct erase_info *instr) size_t len = instr->len; int err; - instr->state = MTD_ERASING; mutex_lock(&dev->write_mutex); err = _block2mtd_erase(dev, from, len); mutex_unlock(&dev->write_mutex); - if (err) { + if (err) pr_err("erase failed err = %d\n", err); - instr->state = MTD_ERASE_FAILED; - } else - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); return err; } diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c index a85af236b44d..c594fe5eac08 100644 --- a/drivers/mtd/devices/docg3.c +++ b/drivers/mtd/devices/docg3.c @@ -1191,39 +1191,27 @@ static int doc_erase(struct mtd_info *mtd, struct erase_info *info) { struct docg3 *docg3 = mtd->priv; uint64_t len; - int block0, block1, page, ret, ofs = 0; + int block0, block1, page, ret = 0, ofs = 0; doc_dbg("doc_erase(from=%lld, len=%lld\n", info->addr, info->len); - info->state = MTD_ERASE_PENDING; calc_block_sector(info->addr + info->len, &block0, &block1, &page, &ofs, docg3->reliable); - ret = -EINVAL; if (info->addr + info->len > mtd->size || page || ofs) - goto reset_err; + return -EINVAL; - ret = 0; calc_block_sector(info->addr, &block0, &block1, &page, &ofs, docg3->reliable); mutex_lock(&docg3->cascade->lock); doc_set_device_id(docg3, docg3->device_id); doc_set_reliable_mode(docg3); for (len = info->len; !ret && len > 0; len -= mtd->erasesize) { - info->state = MTD_ERASING; ret = doc_erase_block(docg3, block0, block1); block0 += 2; block1 += 2; } mutex_unlock(&docg3->cascade->lock); - if (ret) - goto reset_err; - - info->state = MTD_ERASE_DONE; - return 0; - -reset_err: - info->state = MTD_ERASE_FAILED; return ret; } diff --git a/drivers/mtd/devices/lart.c b/drivers/mtd/devices/lart.c index 555b94406e0b..f67b653c17d7 100644 --- a/drivers/mtd/devices/lart.c +++ b/drivers/mtd/devices/lart.c @@ -414,10 +414,7 @@ static int flash_erase (struct mtd_info *mtd,struct erase_info *instr) while (len) { if (!erase_block (addr)) - { - instr->state = MTD_ERASE_FAILED; return (-EIO); - } addr += mtd->eraseregions[i].erasesize; len -= mtd->eraseregions[i].erasesize; @@ -425,9 +422,6 @@ static int flash_erase (struct mtd_info *mtd,struct erase_info *instr) if (addr == mtd->eraseregions[i].offset + (mtd->eraseregions[i].erasesize * mtd->eraseregions[i].numblocks)) i++; } - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - return (0); } diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c index 5dc8bd042cc5..aaaeaae01e1d 100644 --- a/drivers/mtd/devices/mtd_dataflash.c +++ b/drivers/mtd/devices/mtd_dataflash.c @@ -220,10 +220,6 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) } mutex_unlock(&priv->lock); - /* Inform MTD subsystem that erase is complete */ - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - return 0; } diff --git a/drivers/mtd/devices/mtdram.c b/drivers/mtd/devices/mtdram.c index 0bf4aeaf0cb8..46238796145f 100644 --- a/drivers/mtd/devices/mtdram.c +++ b/drivers/mtd/devices/mtdram.c @@ -60,8 +60,7 @@ static int ram_erase(struct mtd_info *mtd, struct erase_info *instr) if (check_offs_len(mtd, instr->addr, instr->len)) return -EINVAL; memset((char *)mtd->priv + instr->addr, 0xff, instr->len); - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); + return 0; } diff --git a/drivers/mtd/devices/phram.c b/drivers/mtd/devices/phram.c index 7287696a21f9..9ee04b5f9311 100644 --- a/drivers/mtd/devices/phram.c +++ b/drivers/mtd/devices/phram.c @@ -39,13 +39,6 @@ static int phram_erase(struct mtd_info *mtd, struct erase_info *instr) memset(start + instr->addr, 0xff, instr->len); - /* - * This'll catch a few races. Free the thing before returning :) - * I don't feel at all ashamed. This kind of thing is possible anyway - * with flash, but unlikely. - */ - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); return 0; } diff --git a/drivers/mtd/devices/pmc551.c b/drivers/mtd/devices/pmc551.c index cadea0620cd0..5d842cbca3de 100644 --- a/drivers/mtd/devices/pmc551.c +++ b/drivers/mtd/devices/pmc551.c @@ -184,12 +184,10 @@ static int pmc551_erase(struct mtd_info *mtd, struct erase_info *instr) } out: - instr->state = MTD_ERASE_DONE; #ifdef CONFIG_MTD_PMC551_DEBUG printk(KERN_DEBUG "pmc551_erase() done\n"); #endif - mtd_erase_callback(instr); return 0; } diff --git a/drivers/mtd/devices/powernv_flash.c b/drivers/mtd/devices/powernv_flash.c index 26f9feaa5d17..c1312b141ae0 100644 --- a/drivers/mtd/devices/powernv_flash.c +++ b/drivers/mtd/devices/powernv_flash.c @@ -175,19 +175,11 @@ static int powernv_flash_erase(struct mtd_info *mtd, struct erase_info *erase) { int rc; - erase->state = MTD_ERASING; - - /* todo: register our own notifier to do a true async implementation */ rc = powernv_flash_async_op(mtd, FLASH_OP_ERASE, erase->addr, erase->len, NULL, NULL); - - if (rc) { + if (rc) erase->fail_addr = erase->addr; - erase->state = MTD_ERASE_FAILED; - } else { - erase->state = MTD_ERASE_DONE; - } - mtd_erase_callback(erase); + return rc; } diff --git a/drivers/mtd/devices/slram.c b/drivers/mtd/devices/slram.c index 0ec85f316d24..10183ee4e12b 100644 --- a/drivers/mtd/devices/slram.c +++ b/drivers/mtd/devices/slram.c @@ -84,12 +84,7 @@ static int slram_erase(struct mtd_info *mtd, struct erase_info *instr) slram_priv_t *priv = mtd->priv; memset(priv->start + instr->addr, 0xff, instr->len); - /* This'll catch a few races. Free the thing before returning :) - * I don't feel at all ashamed. This kind of thing is possible anyway - * with flash, but unlikely. - */ - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); + return(0); } diff --git a/drivers/mtd/devices/spear_smi.c b/drivers/mtd/devices/spear_smi.c index ddf478976013..986f81d2f93e 100644 --- a/drivers/mtd/devices/spear_smi.c +++ b/drivers/mtd/devices/spear_smi.c @@ -518,7 +518,6 @@ static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info) /* preparing the command for flash */ ret = spear_smi_erase_sector(dev, bank, command, 4); if (ret) { - e_info->state = MTD_ERASE_FAILED; mutex_unlock(&flash->lock); return ret; } @@ -527,8 +526,6 @@ static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info) } mutex_unlock(&flash->lock); - e_info->state = MTD_ERASE_DONE; - mtd_erase_callback(e_info); return 0; } diff --git a/drivers/mtd/devices/sst25l.c b/drivers/mtd/devices/sst25l.c index 5b84d71efb36..1897f33fe3e7 100644 --- a/drivers/mtd/devices/sst25l.c +++ b/drivers/mtd/devices/sst25l.c @@ -195,7 +195,6 @@ static int sst25l_erase(struct mtd_info *mtd, struct erase_info *instr) err = sst25l_erase_sector(flash, addr); if (err) { mutex_unlock(&flash->lock); - instr->state = MTD_ERASE_FAILED; dev_err(&flash->spi->dev, "Erase failed\n"); return err; } @@ -205,8 +204,6 @@ static int sst25l_erase(struct mtd_info *mtd, struct erase_info *instr) mutex_unlock(&flash->lock); - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); return 0; } diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index a33f5fd6818c..55d4a77f3b7f 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -1825,13 +1825,9 @@ static int stfsm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) mutex_unlock(&fsm->lock); - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - return 0; out1: - instr->state = MTD_ERASE_FAILED; mutex_unlock(&fsm->lock); return ret; diff --git a/drivers/mtd/lpddr/lpddr2_nvm.c b/drivers/mtd/lpddr/lpddr2_nvm.c index 2342277c9bcb..5d73db2a496d 100644 --- a/drivers/mtd/lpddr/lpddr2_nvm.c +++ b/drivers/mtd/lpddr/lpddr2_nvm.c @@ -380,14 +380,8 @@ out: */ static int lpddr2_nvm_erase(struct mtd_info *mtd, struct erase_info *instr) { - int ret = lpddr2_nvm_do_block_op(mtd, instr->addr, instr->len, - LPDDR2_NVM_ERASE); - if (!ret) { - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - } - - return ret; + return lpddr2_nvm_do_block_op(mtd, instr->addr, instr->len, + LPDDR2_NVM_ERASE); } /* diff --git a/drivers/mtd/lpddr/lpddr_cmds.c b/drivers/mtd/lpddr/lpddr_cmds.c index 018c75faadb3..5c5ba3c7c79d 100644 --- a/drivers/mtd/lpddr/lpddr_cmds.c +++ b/drivers/mtd/lpddr/lpddr_cmds.c @@ -693,8 +693,6 @@ static int lpddr_erase(struct mtd_info *mtd, struct erase_info *instr) ofs += size; len -= size; } - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); return 0; } diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c index 93c47e56d9d8..6b86d1a73cf2 100644 --- a/drivers/mtd/mtdconcat.c +++ b/drivers/mtd/mtdconcat.c @@ -446,7 +446,6 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr) erase->addr = 0; offset += subdev->size; } - instr->state = erase->state; kfree(erase); return err; diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index f92ad02959eb..f25d65ea7149 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -961,11 +961,9 @@ int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) if (!(mtd->flags & MTD_WRITEABLE)) return -EROFS; - if (!instr->len) { - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); + if (!instr->len) return 0; - } + ledtrig_mtd_activity(); return mtd->_erase(mtd, instr); } diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 1c07a6f0dfe5..85fea8ea3423 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -212,11 +212,6 @@ static int part_erase(struct mtd_info *mtd, struct erase_info *instr) return ret; } -void mtd_erase_callback(struct erase_info *instr) -{ -} -EXPORT_SYMBOL_GPL(mtd_erase_callback); - static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) { struct mtd_part *part = mtd_to_part(mtd); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 16c8bc06975d..87b72bf626ae 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -4604,22 +4604,20 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, if (nand_check_wp(mtd)) { pr_debug("%s: device is write protected!\n", __func__); - instr->state = MTD_ERASE_FAILED; + ret = -EIO; goto erase_exit; } /* Loop through the pages */ len = instr->len; - instr->state = MTD_ERASING; - while (len) { /* Check if we have a bad block, we do not erase bad blocks! */ if (nand_block_checkbad(mtd, ((loff_t) page) << chip->page_shift, allowbbt)) { pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", __func__, page); - instr->state = MTD_ERASE_FAILED; + ret = -EIO; goto erase_exit; } @@ -4637,7 +4635,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, if (status) { pr_debug("%s: failed erase, page 0x%08x\n", __func__, page); - instr->state = MTD_ERASE_FAILED; + ret = -EIO; instr->fail_addr = ((loff_t)page << chip->page_shift); goto erase_exit; @@ -4654,20 +4652,14 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, chip->select_chip(mtd, chipnr); } } - instr->state = MTD_ERASE_DONE; + ret = 0; erase_exit: - ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; - /* Deselect and wake up anyone waiting on the device */ chip->select_chip(mtd, -1); nand_release_device(mtd); - /* Do call back function */ - if (!ret) - mtd_erase_callback(instr); - /* Return more or less happy */ return ret; } diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 979f4031f23c..8d19b78777b5 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -2143,7 +2143,6 @@ static int onenand_multiblock_erase_verify(struct mtd_info *mtd, if (ret) { printk(KERN_ERR "%s: Failed verify, block %d\n", __func__, onenand_block(this, addr)); - instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; return -1; } @@ -2172,8 +2171,6 @@ static int onenand_multiblock_erase(struct mtd_info *mtd, int ret = 0; int bdry_block = 0; - instr->state = MTD_ERASING; - if (ONENAND_IS_DDP(this)) { loff_t bdry_addr = this->chipsize >> 1; if (addr < bdry_addr && (addr + len) > bdry_addr) @@ -2187,7 +2184,6 @@ static int onenand_multiblock_erase(struct mtd_info *mtd, printk(KERN_WARNING "%s: attempt to erase a bad block " "at addr 0x%012llx\n", __func__, (unsigned long long) addr); - instr->state = MTD_ERASE_FAILED; return -EIO; } len -= block_size; @@ -2227,7 +2223,6 @@ static int onenand_multiblock_erase(struct mtd_info *mtd, printk(KERN_ERR "%s: Failed multiblock erase, " "block %d\n", __func__, onenand_block(this, addr)); - instr->state = MTD_ERASE_FAILED; instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; return -EIO; } @@ -2247,7 +2242,6 @@ static int onenand_multiblock_erase(struct mtd_info *mtd, if (ret) { printk(KERN_ERR "%s: Failed erase, block %d\n", __func__, onenand_block(this, addr)); - instr->state = MTD_ERASE_FAILED; instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; return -EIO; } @@ -2259,7 +2253,6 @@ static int onenand_multiblock_erase(struct mtd_info *mtd, /* verify */ verify_instr.len = eb_count * block_size; if (onenand_multiblock_erase_verify(mtd, &verify_instr)) { - instr->state = verify_instr.state; instr->fail_addr = verify_instr.fail_addr; return -EIO; } @@ -2294,8 +2287,6 @@ static int onenand_block_by_block_erase(struct mtd_info *mtd, region_end = region->offset + region->erasesize * region->numblocks; } - instr->state = MTD_ERASING; - /* Loop through the blocks */ while (len) { cond_resched(); @@ -2305,7 +2296,6 @@ static int onenand_block_by_block_erase(struct mtd_info *mtd, printk(KERN_WARNING "%s: attempt to erase a bad block " "at addr 0x%012llx\n", __func__, (unsigned long long) addr); - instr->state = MTD_ERASE_FAILED; return -EIO; } @@ -2318,7 +2308,6 @@ static int onenand_block_by_block_erase(struct mtd_info *mtd, if (ret) { printk(KERN_ERR "%s: Failed erase, block %d\n", __func__, onenand_block(this, addr)); - instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; return -EIO; } @@ -2407,12 +2396,6 @@ static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) /* Deselect and wake up anyone waiting on the device */ onenand_release_device(mtd); - /* Do call back function */ - if (!ret) { - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - } - return ret; } diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d445a4d3b770..5bfa36e95f35 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -560,9 +560,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) erase_err: spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); - instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; - mtd_erase_callback(instr); - return ret; } diff --git a/drivers/mtd/ubi/gluebi.c b/drivers/mtd/ubi/gluebi.c index 1cb287ec32ad..6b655a53113b 100644 --- a/drivers/mtd/ubi/gluebi.c +++ b/drivers/mtd/ubi/gluebi.c @@ -272,12 +272,9 @@ static int gluebi_erase(struct mtd_info *mtd, struct erase_info *instr) if (err) goto out_err; - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); return 0; out_err: - instr->state = MTD_ERASE_FAILED; instr->fail_addr = (long long)lnum * mtd->erasesize; return err; } diff --git a/drivers/net/ethernet/sfc/falcon/mtd.c b/drivers/net/ethernet/sfc/falcon/mtd.c index cde593cb1052..2d67e4621a3d 100644 --- a/drivers/net/ethernet/sfc/falcon/mtd.c +++ b/drivers/net/ethernet/sfc/falcon/mtd.c @@ -24,17 +24,8 @@ static int ef4_mtd_erase(struct mtd_info *mtd, struct erase_info *erase) { struct ef4_nic *efx = mtd->priv; - int rc; - rc = efx->type->mtd_erase(mtd, erase->addr, erase->len); - if (rc == 0) { - erase->state = MTD_ERASE_DONE; - } else { - erase->state = MTD_ERASE_FAILED; - erase->fail_addr = MTD_FAIL_ADDR_UNKNOWN; - } - mtd_erase_callback(erase); - return rc; + return efx->type->mtd_erase(mtd, erase->addr, erase->len); } static void ef4_mtd_sync(struct mtd_info *mtd) diff --git a/drivers/net/ethernet/sfc/mtd.c b/drivers/net/ethernet/sfc/mtd.c index a77a8bd2dd70..4ac30b6e5dab 100644 --- a/drivers/net/ethernet/sfc/mtd.c +++ b/drivers/net/ethernet/sfc/mtd.c @@ -24,17 +24,8 @@ static int efx_mtd_erase(struct mtd_info *mtd, struct erase_info *erase) { struct efx_nic *efx = mtd->priv; - int rc; - rc = efx->type->mtd_erase(mtd, erase->addr, erase->len); - if (rc == 0) { - erase->state = MTD_ERASE_DONE; - } else { - erase->state = MTD_ERASE_FAILED; - erase->fail_addr = MTD_FAIL_ADDR_UNKNOWN; - } - mtd_erase_callback(erase); - return rc; + return efx->type->mtd_erase(mtd, erase->addr, erase->len); } static void efx_mtd_sync(struct mtd_info *mtd) diff --git a/drivers/staging/goldfish/goldfish_nand.c b/drivers/staging/goldfish/goldfish_nand.c index 52cc1363993e..f5e002ecba75 100644 --- a/drivers/staging/goldfish/goldfish_nand.c +++ b/drivers/staging/goldfish/goldfish_nand.c @@ -119,9 +119,6 @@ static int goldfish_nand_erase(struct mtd_info *mtd, struct erase_info *instr) return -EIO; } - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); - return 0; invalid_arg: diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 4cbb7f555244..a86c4fa93115 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -30,12 +30,6 @@ #include -#define MTD_ERASE_PENDING 0x01 -#define MTD_ERASING 0x02 -#define MTD_ERASE_SUSPEND 0x04 -#define MTD_ERASE_DONE 0x08 -#define MTD_ERASE_FAILED 0x10 - #define MTD_FAIL_ADDR_UNKNOWN -1LL struct mtd_info; @@ -49,7 +43,6 @@ struct erase_info { uint64_t addr; uint64_t len; uint64_t fail_addr; - u_char state; }; struct mtd_erase_region_info { @@ -589,8 +582,6 @@ extern void register_mtd_user (struct mtd_notifier *new); extern int unregister_mtd_user (struct mtd_notifier *old); void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size); -void mtd_erase_callback(struct erase_info *instr); - static inline int mtd_is_bitflip(int err) { return err == -EUCLEAN; } -- cgit v1.2.3 From 6b00c35138b404be98b85f4a703be594cbed501c Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Thu, 22 Mar 2018 01:08:10 +0530 Subject: mtd: nand: fsl_ifc: Read ECCSTAT0 and ECCSTAT1 registers for IFC 2.0 Due to missing information in Hardware manual, current implementation doesn't read ECCSTAT0 and ECCSTAT1 registers for IFC 2.0. Add support to read ECCSTAT0 and ECCSTAT1 registers during ecccheck for IFC 2.0. Fixes: 656441478ed5 ("mtd: nand: ifc: Fix location of eccstat registers for IFC V1.0") Cc: stable@vger.kernel.org # v3.18+ Signed-off-by: Jagdish Gediya Reviewed-by: Prabhakar Kushwaha Signed-off-by: Boris Brezillon --- drivers/mtd/nand/fsl_ifc_nand.c | 6 +----- include/linux/fsl_ifc.h | 6 +----- 2 files changed, 2 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index fae01b04abc7..5a9c2f0020c2 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -227,11 +227,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd) int sector_end = sector_start + chip->ecc.steps - 1; __be32 *eccstat_regs; - if (ctrl->version >= FSL_IFC_VERSION_2_0_0) - eccstat_regs = ifc->ifc_nand.v2_nand_eccstat; - else - eccstat_regs = ifc->ifc_nand.v1_nand_eccstat; - + eccstat_regs = ifc->ifc_nand.nand_eccstat; eccstat = ifc_in32(&eccstat_regs[sector_start / 4]); for (i = sector_start; i <= sector_end; i++) { diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h index c332f0a45607..3fdfede2f0f3 100644 --- a/include/linux/fsl_ifc.h +++ b/include/linux/fsl_ifc.h @@ -734,11 +734,7 @@ struct fsl_ifc_nand { u32 res19[0x10]; __be32 nand_fsr; u32 res20; - /* The V1 nand_eccstat is actually 4 words that overlaps the - * V2 nand_eccstat. - */ - __be32 v1_nand_eccstat[2]; - __be32 v2_nand_eccstat[6]; + __be32 nand_eccstat[8]; u32 res21[0x1c]; __be32 nanndcr; u32 res22[0x2]; -- cgit v1.2.3 From 9a2fe9b801f585baccf8352d82839dcd54b300cf Mon Sep 17 00:00:00 2001 From: Ruslan Bilovol Date: Wed, 21 Mar 2018 02:03:59 +0200 Subject: ALSA: usb: initial USB Audio Device Class 3.0 support Recently released USB Audio Class 3.0 specification introduces many significant changes comparing to previous versions, like - new Power Domains, support for LPM/L1 - new Cluster descriptor - changed layout of all class-specific descriptors - new High Capability descriptors - New class-specific String descriptors - new and removed units - additional sources for interrupts - removed Type II Audio Data Formats - ... and many other things (check spec) It also provides backward compatibility through multiple configurations, as well as requires mandatory support for BADD (Basic Audio Device Definition) on each ADC3.0 compliant device This patch adds initial support of UAC3 specification that is enough for Generic I/O Profile (BAOF, BAIF) device support from BADD document. Signed-off-by: Ruslan Bilovol Reviewed-by: Greg Kroah-Hartman Signed-off-by: Takashi Iwai --- include/linux/usb/audio-v2.h | 4 +- include/linux/usb/audio-v3.h | 395 +++++++++++++++++++++++++++++++++++++++++ include/uapi/linux/usb/audio.h | 1 + sound/usb/card.c | 7 +- sound/usb/card.h | 2 +- sound/usb/clock.c | 228 +++++++++++++++++++++--- sound/usb/clock.h | 4 +- sound/usb/format.c | 91 ++++++++-- sound/usb/format.h | 6 +- sound/usb/mixer.c | 337 +++++++++++++++++++++++------------ sound/usb/stream.c | 365 +++++++++++++++++++++++++++++++++---- 11 files changed, 1246 insertions(+), 194 deletions(-) create mode 100644 include/linux/usb/audio-v3.h (limited to 'include/linux') diff --git a/include/linux/usb/audio-v2.h b/include/linux/usb/audio-v2.h index 3119d0ace7aa..2db83a191e78 100644 --- a/include/linux/usb/audio-v2.h +++ b/include/linux/usb/audio-v2.h @@ -34,12 +34,12 @@ * */ -static inline bool uac2_control_is_readable(u32 bmControls, u8 control) +static inline bool uac_v2v3_control_is_readable(u32 bmControls, u8 control) { return (bmControls >> (control * 2)) & 0x1; } -static inline bool uac2_control_is_writeable(u32 bmControls, u8 control) +static inline bool uac_v2v3_control_is_writeable(u32 bmControls, u8 control) { return (bmControls >> (control * 2)) & 0x2; } diff --git a/include/linux/usb/audio-v3.h b/include/linux/usb/audio-v3.h new file mode 100644 index 000000000000..a8959aaba0ae --- /dev/null +++ b/include/linux/usb/audio-v3.h @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 Ruslan Bilovol + * + * This file holds USB constants and structures defined + * by the USB DEVICE CLASS DEFINITION FOR AUDIO DEVICES Release 3.0. + */ + +#ifndef __LINUX_USB_AUDIO_V3_H +#define __LINUX_USB_AUDIO_V3_H + +#include + +/* + * v1.0, v2.0 and v3.0 of this standard have many things in common. For the rest + * of the definitions, please refer to audio.h and audio-v2.h + */ + +/* All High Capability descriptors have these 2 fields at the beginning */ +struct uac3_hc_descriptor_header { + __le16 wLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __le16 wDescriptorID; +} __attribute__ ((packed)); + +/* 4.3.1 CLUSTER DESCRIPTOR HEADER */ +struct uac3_cluster_header_descriptor { + __le16 wLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __le16 wDescriptorID; + __u8 bNrChannels; +} __attribute__ ((packed)); + +/* 4.3.2.1 SEGMENTS */ +struct uac3_cluster_segment_descriptor { + __le16 wLength; + __u8 bSegmentType; + /* __u8[0]; segment-specific data */ +} __attribute__ ((packed)); + +/* 4.3.2.1.1 END SEGMENT */ +struct uac3_cluster_end_segment_descriptor { + __le16 wLength; + __u8 bSegmentType; /* Constant END_SEGMENT */ +} __attribute__ ((packed)); + +/* 4.3.2.1.3.1 INFORMATION SEGMENT */ +struct uac3_cluster_information_segment_descriptor { + __le16 wLength; + __u8 bSegmentType; + __u8 bChPurpose; + __u8 bChRelationship; + __u8 bChGroupID; +} __attribute__ ((packed)); + +/* 4.5.2 CLASS-SPECIFIC AC INTERFACE DESCRIPTOR */ +struct uac3_ac_header_descriptor { + __u8 bLength; /* 10 */ + __u8 bDescriptorType; /* CS_INTERFACE descriptor type */ + __u8 bDescriptorSubtype; /* HEADER descriptor subtype */ + __u8 bCategory; + + /* includes Clock Source, Unit, Terminal, and Power Domain desc. */ + __le16 wTotalLength; + + __le32 bmControls; +} __attribute__ ((packed)); + +/* 4.5.2.1 INPUT TERMINAL DESCRIPTOR */ +struct uac3_input_terminal_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bTerminalID; + __le16 wTerminalType; + __u8 bAssocTerminal; + __u8 bCSourceID; + __le32 bmControls; + __le16 wClusterDescrID; + __le16 wExTerminalDescrID; + __le16 wConnectorsDescrID; + __le16 wTerminalDescrStr; +} __attribute__((packed)); + +/* 4.5.2.2 OUTPUT TERMINAL DESCRIPTOR */ +struct uac3_output_terminal_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bTerminalID; + __le16 wTerminalType; + __u8 bAssocTerminal; + __u8 bSourceID; + __u8 bCSourceID; + __le32 bmControls; + __le16 wExTerminalDescrID; + __le16 wConnectorsDescrID; + __le16 wTerminalDescrStr; +} __attribute__((packed)); + +/* 4.5.2.7 FEATURE UNIT DESCRIPTOR */ +struct uac3_feature_unit_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bUnitID; + __u8 bSourceID; + /* bmaControls is actually u32, + * but u8 is needed for the hybrid parser */ + __u8 bmaControls[0]; /* variable length */ + /* wFeatureDescrStr omitted */ +} __attribute__((packed)); + +#define UAC3_DT_FEATURE_UNIT_SIZE(ch) (7 + ((ch) + 1) * 4) + +/* As above, but more useful for defining your own descriptors */ +#define DECLARE_UAC3_FEATURE_UNIT_DESCRIPTOR(ch) \ +struct uac3_feature_unit_descriptor_##ch { \ + __u8 bLength; \ + __u8 bDescriptorType; \ + __u8 bDescriptorSubtype; \ + __u8 bUnitID; \ + __u8 bSourceID; \ + __le32 bmaControls[ch + 1]; \ + __le16 wFeatureDescrStr; \ +} __attribute__ ((packed)) + +/* 4.5.2.12 CLOCK SOURCE DESCRIPTOR */ +struct uac3_clock_source_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bClockID; + __u8 bmAttributes; + __le32 bmControls; + __u8 bReferenceTerminal; + __le16 wClockSourceStr; +} __attribute__((packed)); + +/* bmAttribute fields */ +#define UAC3_CLOCK_SOURCE_TYPE_EXT 0x0 +#define UAC3_CLOCK_SOURCE_TYPE_INT 0x1 +#define UAC3_CLOCK_SOURCE_ASYNC (0 << 2) +#define UAC3_CLOCK_SOURCE_SYNCED_TO_SOF (1 << 1) + +/* 4.5.2.13 CLOCK SELECTOR DESCRIPTOR */ +struct uac3_clock_selector_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bClockID; + __u8 bNrInPins; + __u8 baCSourceID[]; + /* bmControls and wCSelectorDescrStr omitted */ +} __attribute__((packed)); + +/* 4.5.2.14 CLOCK MULTIPLIER DESCRIPTOR */ +struct uac3_clock_multiplier_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bClockID; + __u8 bCSourceID; + __le32 bmControls; + __le16 wCMultiplierDescrStr; +} __attribute__((packed)); + +/* 4.5.2.15 POWER DOMAIN DESCRIPTOR */ +struct uac3_power_domain_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bPowerDomainID; + __le16 waRecoveryTime1; + __le16 waRecoveryTime2; + __u8 bNrEntities; + __u8 baEntityID[]; + /* wPDomainDescrStr omitted */ +} __attribute__((packed)); + +/* As above, but more useful for defining your own descriptors */ +#define DECLARE_UAC3_POWER_DOMAIN_DESCRIPTOR(n) \ +struct uac3_power_domain_descriptor_##n { \ + __u8 bLength; \ + __u8 bDescriptorType; \ + __u8 bDescriptorSubtype; \ + __u8 bPowerDomainID; \ + __le16 waRecoveryTime1; \ + __le16 waRecoveryTime2; \ + __u8 bNrEntities; \ + __u8 baEntityID[n]; \ + __le16 wPDomainDescrStr; \ +} __attribute__ ((packed)) + +/* 4.7.2 CLASS-SPECIFIC AS INTERFACE DESCRIPTOR */ +struct uac3_as_header_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __u8 bTerminalLink; + __le32 bmControls; + __le16 wClusterDescrID; + __le64 bmFormats; + __u8 bSubslotSize; + __u8 bBitResolution; + __le16 bmAuxProtocols; + __u8 bControlSize; +} __attribute__((packed)); + +#define UAC3_FORMAT_TYPE_I_RAW_DATA (1 << 6) + +/* 4.8.1.2 CLASS-SPECIFIC AS ISOCHRONOUS AUDIO DATA ENDPOINT DESCRIPTOR */ +struct uac3_iso_endpoint_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubtype; + __le32 bmControls; + __u8 bLockDelayUnits; + __le16 wLockDelay; +} __attribute__((packed)); + +/* 6.1 INTERRUPT DATA MESSAGE */ +struct uac3_interrupt_data_msg { + __u8 bInfo; + __u8 bSourceType; + __le16 wValue; + __le16 wIndex; +} __attribute__((packed)); + +/* A.2 AUDIO AUDIO FUNCTION SUBCLASS CODES */ +#define UAC3_FUNCTION_SUBCLASS_UNDEFINED 0x00 +#define UAC3_FUNCTION_SUBCLASS_FULL_ADC_3_0 0x01 +/* BADD profiles */ +#define UAC3_FUNCTION_SUBCLASS_GENERIC_IO 0x20 +#define UAC3_FUNCTION_SUBCLASS_HEADPHONE 0x21 +#define UAC3_FUNCTION_SUBCLASS_SPEAKER 0x22 +#define UAC3_FUNCTION_SUBCLASS_MICROPHONE 0x23 +#define UAC3_FUNCTION_SUBCLASS_HEADSET 0x24 +#define UAC3_FUNCTION_SUBCLASS_HEADSET_ADAPTER 0x25 +#define UAC3_FUNCTION_SUBCLASS_SPEAKERPHONE 0x26 + +/* A.7 AUDIO FUNCTION CATEGORY CODES */ +#define UAC3_FUNCTION_SUBCLASS_UNDEFINED 0x00 +#define UAC3_FUNCTION_DESKTOP_SPEAKER 0x01 +#define UAC3_FUNCTION_HOME_THEATER 0x02 +#define UAC3_FUNCTION_MICROPHONE 0x03 +#define UAC3_FUNCTION_HEADSET 0x04 +#define UAC3_FUNCTION_TELEPHONE 0x05 +#define UAC3_FUNCTION_CONVERTER 0x06 +#define UAC3_FUNCTION_SOUND_RECORDER 0x07 +#define UAC3_FUNCTION_IO_BOX 0x08 +#define UAC3_FUNCTION_MUSICAL_INSTRUMENT 0x09 +#define UAC3_FUNCTION_PRO_AUDIO 0x0a +#define UAC3_FUNCTION_AUDIO_VIDEO 0x0b +#define UAC3_FUNCTION_CONTROL_PANEL 0x0c +#define UAC3_FUNCTION_HEADPHONE 0x0d +#define UAC3_FUNCTION_GENERIC_SPEAKER 0x0e +#define UAC3_FUNCTION_HEADSET_ADAPTER 0x0f +#define UAC3_FUNCTION_SPEAKERPHONE 0x10 +#define UAC3_FUNCTION_OTHER 0xff + +/* A.8 AUDIO CLASS-SPECIFIC DESCRIPTOR TYPES */ +#define UAC3_CS_UNDEFINED 0x20 +#define UAC3_CS_DEVICE 0x21 +#define UAC3_CS_CONFIGURATION 0x22 +#define UAC3_CS_STRING 0x23 +#define UAC3_CS_INTERFACE 0x24 +#define UAC3_CS_ENDPOINT 0x25 +#define UAC3_CS_CLUSTER 0x26 + +/* A.10 CLUSTER DESCRIPTOR SEGMENT TYPES */ +#define UAC3_SEGMENT_UNDEFINED 0x00 +#define UAC3_CLUSTER_DESCRIPTION 0x01 +#define UAC3_CLUSTER_VENDOR_DEFINED 0x1F +#define UAC3_CHANNEL_INFORMATION 0x20 +#define UAC3_CHANNEL_AMBISONIC 0x21 +#define UAC3_CHANNEL_DESCRIPTION 0x22 +#define UAC3_CHANNEL_VENDOR_DEFINED 0xFE +#define UAC3_END_SEGMENT 0xFF + +/* A.11 CHANNEL PURPOSE DEFINITIONS */ +#define UAC3_PURPOSE_UNDEFINED 0x00 +#define UAC3_PURPOSE_GENERIC_AUDIO 0x01 +#define UAC3_PURPOSE_VOICE 0x02 +#define UAC3_PURPOSE_SPEECH 0x03 +#define UAC3_PURPOSE_AMBIENT 0x04 +#define UAC3_PURPOSE_REFERENCE 0x05 +#define UAC3_PURPOSE_ULTRASONIC 0x06 +#define UAC3_PURPOSE_VIBROKINETIC 0x07 +#define UAC3_PURPOSE_NON_AUDIO 0xFF + +/* A.12 CHANNEL RELATIONSHIP DEFINITIONS */ +#define UAC3_CH_RELATIONSHIP_UNDEFINED 0x00 +#define UAC3_CH_MONO 0x01 +#define UAC3_CH_LEFT 0x02 +#define UAC3_CH_RIGHT 0x03 +#define UAC3_CH_ARRAY 0x04 +#define UAC3_CH_PATTERN_X 0x20 +#define UAC3_CH_PATTERN_Y 0x21 +#define UAC3_CH_PATTERN_A 0x22 +#define UAC3_CH_PATTERN_B 0x23 +#define UAC3_CH_PATTERN_M 0x24 +#define UAC3_CH_PATTERN_S 0x25 +#define UAC3_CH_FRONT_LEFT 0x80 +#define UAC3_CH_FRONT_RIGHT 0x81 +#define UAC3_CH_FRONT_CENTER 0x82 +#define UAC3_CH_FRONT_LEFT_OF_CENTER 0x83 +#define UAC3_CH_FRONT_RIGHT_OF_CENTER 0x84 +#define UAC3_CH_FRONT_WIDE_LEFT 0x85 +#define UAC3_CH_FRONT_WIDE_RIGHT 0x86 +#define UAC3_CH_SIDE_LEFT 0x87 +#define UAC3_CH_SIDE_RIGHT 0x88 +#define UAC3_CH_SURROUND_ARRAY_LEFT 0x89 +#define UAC3_CH_SURROUND_ARRAY_RIGHT 0x8A +#define UAC3_CH_BACK_LEFT 0x8B +#define UAC3_CH_BACK_RIGHT 0x8C +#define UAC3_CH_BACK_CENTER 0x8D +#define UAC3_CH_BACK_LEFT_OF_CENTER 0x8E +#define UAC3_CH_BACK_RIGHT_OF_CENTER 0x8F +#define UAC3_CH_BACK_WIDE_LEFT 0x90 +#define UAC3_CH_BACK_WIDE_RIGHT 0x91 +#define UAC3_CH_TOP_CENTER 0x92 +#define UAC3_CH_TOP_FRONT_LEFT 0x93 +#define UAC3_CH_TOP_FRONT_RIGHT 0x94 +#define UAC3_CH_TOP_FRONT_CENTER 0x95 +#define UAC3_CH_TOP_FRONT_LOC 0x96 +#define UAC3_CH_TOP_FRONT_ROC 0x97 +#define UAC3_CH_TOP_FRONT_WIDE_LEFT 0x98 +#define UAC3_CH_TOP_FRONT_WIDE_RIGHT 0x99 +#define UAC3_CH_TOP_SIDE_LEFT 0x9A +#define UAC3_CH_TOP_SIDE_RIGHT 0x9B +#define UAC3_CH_TOP_SURR_ARRAY_LEFT 0x9C +#define UAC3_CH_TOP_SURR_ARRAY_RIGHT 0x9D +#define UAC3_CH_TOP_BACK_LEFT 0x9E +#define UAC3_CH_TOP_BACK_RIGHT 0x9F +#define UAC3_CH_TOP_BACK_CENTER 0xA0 +#define UAC3_CH_TOP_BACK_LOC 0xA1 +#define UAC3_CH_TOP_BACK_ROC 0xA2 +#define UAC3_CH_TOP_BACK_WIDE_LEFT 0xA3 +#define UAC3_CH_TOP_BACK_WIDE_RIGHT 0xA4 +#define UAC3_CH_BOTTOM_CENTER 0xA5 +#define UAC3_CH_BOTTOM_FRONT_LEFT 0xA6 +#define UAC3_CH_BOTTOM_FRONT_RIGHT 0xA7 +#define UAC3_CH_BOTTOM_FRONT_CENTER 0xA8 +#define UAC3_CH_BOTTOM_FRONT_LOC 0xA9 +#define UAC3_CH_BOTTOM_FRONT_ROC 0xAA +#define UAC3_CH_BOTTOM_FRONT_WIDE_LEFT 0xAB +#define UAC3_CH_BOTTOM_FRONT_WIDE_RIGHT 0xAC +#define UAC3_CH_BOTTOM_SIDE_LEFT 0xAD +#define UAC3_CH_BOTTOM_SIDE_RIGHT 0xAE +#define UAC3_CH_BOTTOM_SURR_ARRAY_LEFT 0xAF +#define UAC3_CH_BOTTOM_SURR_ARRAY_RIGHT 0xB0 +#define UAC3_CH_BOTTOM_BACK_LEFT 0xB1 +#define UAC3_CH_BOTTOM_BACK_RIGHT 0xB2 +#define UAC3_CH_BOTTOM_BACK_CENTER 0xB3 +#define UAC3_CH_BOTTOM_BACK_LOC 0xB4 +#define UAC3_CH_BOTTOM_BACK_ROC 0xB5 +#define UAC3_CH_BOTTOM_BACK_WIDE_LEFT 0xB6 +#define UAC3_CH_BOTTOM_BACK_WIDE_RIGHT 0xB7 +#define UAC3_CH_LOW_FREQUENCY_EFFECTS 0xB8 +#define UAC3_CH_LFE_LEFT 0xB9 +#define UAC3_CH_LFE_RIGHT 0xBA +#define UAC3_CH_HEADPHONE_LEFT 0xBB +#define UAC3_CH_HEADPHONE_RIGHT 0xBC + +/* A.15 AUDIO CLASS-SPECIFIC AC INTERFACE DESCRIPTOR SUBTYPES */ +/* see audio.h for the rest, which is identical to v1 */ +#define UAC3_EXTENDED_TERMINAL 0x04 +#define UAC3_MIXER_UNIT 0x05 +#define UAC3_SELECTOR_UNIT 0x06 +#define UAC3_FEATURE_UNIT 0x07 +#define UAC3_EFFECT_UNIT 0x08 +#define UAC3_PROCESSING_UNIT 0x09 +#define UAC3_EXTENSION_UNIT 0x0a +#define UAC3_CLOCK_SOURCE 0x0b +#define UAC3_CLOCK_SELECTOR 0x0c +#define UAC3_CLOCK_MULTIPLIER 0x0d +#define UAC3_SAMPLE_RATE_CONVERTER 0x0e +#define UAC3_CONNECTORS 0x0f +#define UAC3_POWER_DOMAIN 0x10 + +/* A.22 AUDIO CLASS-SPECIFIC REQUEST CODES */ +/* see audio-v2.h for the rest, which is identical to v2 */ +#define UAC3_CS_REQ_INTEN 0x04 +#define UAC3_CS_REQ_STRING 0x05 +#define UAC3_CS_REQ_HIGH_CAPABILITY_DESCRIPTOR 0x06 + +/* A.23.1 AUDIOCONTROL INTERFACE CONTROL SELECTORS */ +#define UAC3_AC_CONTROL_UNDEFINED 0x00 +#define UAC3_AC_ACTIVE_INTERFACE_CONTROL 0x01 +#define UAC3_AC_POWER_DOMAIN_CONTROL 0x02 + +#endif /* __LINUX_USB_AUDIO_V3_H */ diff --git a/include/uapi/linux/usb/audio.h b/include/uapi/linux/usb/audio.h index da3315ed1bcd..3a78e7145689 100644 --- a/include/uapi/linux/usb/audio.h +++ b/include/uapi/linux/usb/audio.h @@ -27,6 +27,7 @@ /* bInterfaceProtocol values to denote the version of the standard used */ #define UAC_VERSION_1 0x00 #define UAC_VERSION_2 0x20 +#define UAC_VERSION_3 0x30 /* A.2 Audio Interface Subclass Codes */ #define USB_SUBCLASS_AUDIOCONTROL 0x01 diff --git a/sound/usb/card.c b/sound/usb/card.c index 8018d56cfecc..4a1c6bb3dfa0 100644 --- a/sound/usb/card.c +++ b/sound/usb/card.c @@ -7,6 +7,7 @@ * Alan Cox (alan@lxorguk.ukuu.org.uk) * Thomas Sailer (sailer@ife.ee.ethz.ch) * + * Audio Class 3.0 support by Ruslan Bilovol * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,6 +45,7 @@ #include #include #include +#include #include #include @@ -281,7 +283,8 @@ static int snd_usb_create_streams(struct snd_usb_audio *chip, int ctrlif) break; } - case UAC_VERSION_2: { + case UAC_VERSION_2: + case UAC_VERSION_3: { struct usb_interface_assoc_descriptor *assoc = usb_ifnum_to_if(dev, ctrlif)->intf_assoc; @@ -301,7 +304,7 @@ static int snd_usb_create_streams(struct snd_usb_audio *chip, int ctrlif) } if (!assoc) { - dev_err(&dev->dev, "Audio class v2 interfaces need an interface association\n"); + dev_err(&dev->dev, "Audio class v2/v3 interfaces need an interface association\n"); return -EINVAL; } diff --git a/sound/usb/card.h b/sound/usb/card.h index ed87cc83eb47..1406292d50ec 100644 --- a/sound/usb/card.h +++ b/sound/usb/card.h @@ -22,7 +22,7 @@ struct audioformat { unsigned char endpoint; /* endpoint */ unsigned char ep_attr; /* endpoint attributes */ unsigned char datainterval; /* log_2 of data packet interval */ - unsigned char protocol; /* UAC_VERSION_1/2 */ + unsigned char protocol; /* UAC_VERSION_1/2/3 */ unsigned int maxpacksize; /* max. packet size */ unsigned int rates; /* rate bitmasks */ unsigned int rate_min, rate_max; /* min/max rates */ diff --git a/sound/usb/clock.c b/sound/usb/clock.c index eb3396ffba4c..25de7fe285d9 100644 --- a/sound/usb/clock.c +++ b/sound/usb/clock.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -50,6 +51,22 @@ static struct uac_clock_source_descriptor * return NULL; } +static struct uac3_clock_source_descriptor * + snd_usb_find_clock_source_v3(struct usb_host_interface *ctrl_iface, + int clock_id) +{ + struct uac3_clock_source_descriptor *cs = NULL; + + while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, + ctrl_iface->extralen, + cs, UAC3_CLOCK_SOURCE))) { + if (cs->bClockID == clock_id) + return cs; + } + + return NULL; +} + static struct uac_clock_selector_descriptor * snd_usb_find_clock_selector(struct usb_host_interface *ctrl_iface, int clock_id) @@ -69,6 +86,22 @@ static struct uac_clock_selector_descriptor * return NULL; } +static struct uac3_clock_selector_descriptor * + snd_usb_find_clock_selector_v3(struct usb_host_interface *ctrl_iface, + int clock_id) +{ + struct uac3_clock_selector_descriptor *cs = NULL; + + while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, + ctrl_iface->extralen, + cs, UAC3_CLOCK_SELECTOR))) { + if (cs->bClockID == clock_id) + return cs; + } + + return NULL; +} + static struct uac_clock_multiplier_descriptor * snd_usb_find_clock_multiplier(struct usb_host_interface *ctrl_iface, int clock_id) @@ -85,6 +118,22 @@ static struct uac_clock_multiplier_descriptor * return NULL; } +static struct uac3_clock_multiplier_descriptor * + snd_usb_find_clock_multiplier_v3(struct usb_host_interface *ctrl_iface, + int clock_id) +{ + struct uac3_clock_multiplier_descriptor *cs = NULL; + + while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, + ctrl_iface->extralen, + cs, UAC3_CLOCK_MULTIPLIER))) { + if (cs->bClockID == clock_id) + return cs; + } + + return NULL; +} + static int uac_clock_selector_get_val(struct snd_usb_audio *chip, int selector_id) { unsigned char buf; @@ -138,19 +187,33 @@ static int uac_clock_selector_set_val(struct snd_usb_audio *chip, int selector_i return ret; } -static bool uac_clock_source_is_valid(struct snd_usb_audio *chip, int source_id) +static bool uac_clock_source_is_valid(struct snd_usb_audio *chip, + int protocol, + int source_id) { int err; unsigned char data; struct usb_device *dev = chip->dev; - struct uac_clock_source_descriptor *cs_desc = - snd_usb_find_clock_source(chip->ctrl_intf, source_id); - - if (!cs_desc) - return 0; + u32 bmControls; + + if (protocol == UAC_VERSION_3) { + struct uac3_clock_source_descriptor *cs_desc = + snd_usb_find_clock_source_v3(chip->ctrl_intf, source_id); + + if (!cs_desc) + return 0; + bmControls = le32_to_cpu(cs_desc->bmControls); + } else { /* UAC_VERSION_1/2 */ + struct uac_clock_source_descriptor *cs_desc = + snd_usb_find_clock_source(chip->ctrl_intf, source_id); + + if (!cs_desc) + return 0; + bmControls = cs_desc->bmControls; + } /* If a clock source can't tell us whether it's valid, we assume it is */ - if (!uac2_control_is_readable(cs_desc->bmControls, + if (!uac_v2v3_control_is_readable(bmControls, UAC2_CS_CONTROL_CLOCK_VALID - 1)) return 1; @@ -170,9 +233,8 @@ static bool uac_clock_source_is_valid(struct snd_usb_audio *chip, int source_id) return !!data; } -static int __uac_clock_find_source(struct snd_usb_audio *chip, - int entity_id, unsigned long *visited, - bool validate) +static int __uac_clock_find_source(struct snd_usb_audio *chip, int entity_id, + unsigned long *visited, bool validate) { struct uac_clock_source_descriptor *source; struct uac_clock_selector_descriptor *selector; @@ -191,7 +253,8 @@ static int __uac_clock_find_source(struct snd_usb_audio *chip, source = snd_usb_find_clock_source(chip->ctrl_intf, entity_id); if (source) { entity_id = source->bClockID; - if (validate && !uac_clock_source_is_valid(chip, entity_id)) { + if (validate && !uac_clock_source_is_valid(chip, UAC_VERSION_2, + entity_id)) { usb_audio_err(chip, "clock source %d is not valid, cannot use\n", entity_id); @@ -260,6 +323,97 @@ static int __uac_clock_find_source(struct snd_usb_audio *chip, return -EINVAL; } +static int __uac3_clock_find_source(struct snd_usb_audio *chip, int entity_id, + unsigned long *visited, bool validate) +{ + struct uac3_clock_source_descriptor *source; + struct uac3_clock_selector_descriptor *selector; + struct uac3_clock_multiplier_descriptor *multiplier; + + entity_id &= 0xff; + + if (test_and_set_bit(entity_id, visited)) { + usb_audio_warn(chip, + "%s(): recursive clock topology detected, id %d.\n", + __func__, entity_id); + return -EINVAL; + } + + /* first, see if the ID we're looking for is a clock source already */ + source = snd_usb_find_clock_source_v3(chip->ctrl_intf, entity_id); + if (source) { + entity_id = source->bClockID; + if (validate && !uac_clock_source_is_valid(chip, UAC_VERSION_3, + entity_id)) { + usb_audio_err(chip, + "clock source %d is not valid, cannot use\n", + entity_id); + return -ENXIO; + } + return entity_id; + } + + selector = snd_usb_find_clock_selector_v3(chip->ctrl_intf, entity_id); + if (selector) { + int ret, i, cur; + + /* the entity ID we are looking for is a selector. + * find out what it currently selects */ + ret = uac_clock_selector_get_val(chip, selector->bClockID); + if (ret < 0) + return ret; + + /* Selector values are one-based */ + + if (ret > selector->bNrInPins || ret < 1) { + usb_audio_err(chip, + "%s(): selector reported illegal value, id %d, ret %d\n", + __func__, selector->bClockID, ret); + + return -EINVAL; + } + + cur = ret; + ret = __uac3_clock_find_source(chip, selector->baCSourceID[ret - 1], + visited, validate); + if (!validate || ret > 0 || !chip->autoclock) + return ret; + + /* The current clock source is invalid, try others. */ + for (i = 1; i <= selector->bNrInPins; i++) { + int err; + + if (i == cur) + continue; + + ret = __uac3_clock_find_source(chip, selector->baCSourceID[i - 1], + visited, true); + if (ret < 0) + continue; + + err = uac_clock_selector_set_val(chip, entity_id, i); + if (err < 0) + continue; + + usb_audio_info(chip, + "found and selected valid clock source %d\n", + ret); + return ret; + } + + return -ENXIO; + } + + /* FIXME: multipliers only act as pass-thru element for now */ + multiplier = snd_usb_find_clock_multiplier_v3(chip->ctrl_intf, + entity_id); + if (multiplier) + return __uac3_clock_find_source(chip, multiplier->bCSourceID, + visited, validate); + + return -EINVAL; +} + /* * For all kinds of sample rate settings and other device queries, * the clock source (end-leaf) must be used. However, clock selectors, @@ -271,12 +425,22 @@ static int __uac_clock_find_source(struct snd_usb_audio *chip, * * Returns the clock source UnitID (>=0) on success, or an error. */ -int snd_usb_clock_find_source(struct snd_usb_audio *chip, int entity_id, - bool validate) +int snd_usb_clock_find_source(struct snd_usb_audio *chip, int protocol, + int entity_id, bool validate) { DECLARE_BITMAP(visited, 256); memset(visited, 0, sizeof(visited)); - return __uac_clock_find_source(chip, entity_id, visited, validate); + + switch (protocol) { + case UAC_VERSION_2: + return __uac_clock_find_source(chip, entity_id, visited, + validate); + case UAC_VERSION_3: + return __uac3_clock_find_source(chip, entity_id, visited, + validate); + default: + return -EINVAL; + } } static int set_sample_rate_v1(struct snd_usb_audio *chip, int iface, @@ -335,7 +499,7 @@ static int set_sample_rate_v1(struct snd_usb_audio *chip, int iface, return 0; } -static int get_sample_rate_v2(struct snd_usb_audio *chip, int iface, +static int get_sample_rate_v2v3(struct snd_usb_audio *chip, int iface, int altsetting, int clock) { struct usb_device *dev = chip->dev; @@ -348,7 +512,7 @@ static int get_sample_rate_v2(struct snd_usb_audio *chip, int iface, snd_usb_ctrl_intf(chip) | (clock << 8), &data, sizeof(data)); if (err < 0) { - dev_warn(&dev->dev, "%d:%d: cannot get freq (v2): err %d\n", + dev_warn(&dev->dev, "%d:%d: cannot get freq (v2/v3): err %d\n", iface, altsetting, err); return 0; } @@ -356,7 +520,7 @@ static int get_sample_rate_v2(struct snd_usb_audio *chip, int iface, return le32_to_cpu(data); } -static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface, +static int set_sample_rate_v2v3(struct snd_usb_audio *chip, int iface, struct usb_host_interface *alts, struct audioformat *fmt, int rate) { @@ -365,18 +529,30 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface, int err, cur_rate, prev_rate; int clock; bool writeable; - struct uac_clock_source_descriptor *cs_desc; + u32 bmControls; - clock = snd_usb_clock_find_source(chip, fmt->clock, true); + clock = snd_usb_clock_find_source(chip, fmt->protocol, + fmt->clock, true); if (clock < 0) return clock; - prev_rate = get_sample_rate_v2(chip, iface, fmt->altsetting, clock); + prev_rate = get_sample_rate_v2v3(chip, iface, fmt->altsetting, clock); if (prev_rate == rate) return 0; - cs_desc = snd_usb_find_clock_source(chip->ctrl_intf, clock); - writeable = uac2_control_is_writeable(cs_desc->bmControls, UAC2_CS_CONTROL_SAM_FREQ - 1); + if (fmt->protocol == UAC_VERSION_3) { + struct uac3_clock_source_descriptor *cs_desc; + + cs_desc = snd_usb_find_clock_source_v3(chip->ctrl_intf, clock); + bmControls = le32_to_cpu(cs_desc->bmControls); + } else { + struct uac_clock_source_descriptor *cs_desc; + + cs_desc = snd_usb_find_clock_source(chip->ctrl_intf, clock); + bmControls = cs_desc->bmControls; + } + + writeable = uac_v2v3_control_is_writeable(bmControls, UAC2_CS_CONTROL_SAM_FREQ - 1); if (writeable) { data = cpu_to_le32(rate); err = snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), UAC2_CS_CUR, @@ -386,12 +562,13 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface, &data, sizeof(data)); if (err < 0) { usb_audio_err(chip, - "%d:%d: cannot set freq %d (v2): err %d\n", + "%d:%d: cannot set freq %d (v2/v3): err %d\n", iface, fmt->altsetting, rate, err); return err; } - cur_rate = get_sample_rate_v2(chip, iface, fmt->altsetting, clock); + cur_rate = get_sample_rate_v2v3(chip, iface, + fmt->altsetting, clock); } else { cur_rate = prev_rate; } @@ -430,7 +607,8 @@ int snd_usb_init_sample_rate(struct snd_usb_audio *chip, int iface, return set_sample_rate_v1(chip, iface, alts, fmt, rate); case UAC_VERSION_2: - return set_sample_rate_v2(chip, iface, alts, fmt, rate); + case UAC_VERSION_3: + return set_sample_rate_v2v3(chip, iface, alts, fmt, rate); } } diff --git a/sound/usb/clock.h b/sound/usb/clock.h index 87557cae1a0b..076e31b79ee0 100644 --- a/sound/usb/clock.h +++ b/sound/usb/clock.h @@ -6,7 +6,7 @@ int snd_usb_init_sample_rate(struct snd_usb_audio *chip, int iface, struct usb_host_interface *alts, struct audioformat *fmt, int rate); -int snd_usb_clock_find_source(struct snd_usb_audio *chip, int entity_id, - bool validate); +int snd_usb_clock_find_source(struct snd_usb_audio *chip, int protocol, + int entity_id, bool validate); #endif /* __USBAUDIO_CLOCK_H */ diff --git a/sound/usb/format.c b/sound/usb/format.c index 2c44386e5569..edbe67eeddfa 100644 --- a/sound/usb/format.c +++ b/sound/usb/format.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -39,11 +40,11 @@ * @dev: usb device * @fp: audioformat record * @format: the format tag (wFormatTag) - * @fmt: the format type descriptor + * @fmt: the format type descriptor (v1/v2) or AudioStreaming descriptor (v3) */ static u64 parse_audio_format_i_type(struct snd_usb_audio *chip, struct audioformat *fp, - unsigned int format, void *_fmt) + u64 format, void *_fmt) { int sample_width, sample_bytes; u64 pcm_formats = 0; @@ -69,6 +70,18 @@ static u64 parse_audio_format_i_type(struct snd_usb_audio *chip, format <<= 1; break; } + case UAC_VERSION_3: { + struct uac3_as_header_descriptor *as = _fmt; + + sample_width = as->bBitResolution; + sample_bytes = as->bSubslotSize; + + if (format & UAC3_FORMAT_TYPE_I_RAW_DATA) + pcm_formats |= SNDRV_PCM_FMTBIT_SPECIAL; + + format <<= 1; + break; + } } if ((pcm_formats == 0) && @@ -137,7 +150,7 @@ static u64 parse_audio_format_i_type(struct snd_usb_audio *chip, } if (format & ~0x3f) { usb_audio_info(chip, - "%u:%d : unsupported format bits %#x\n", + "%u:%d : unsupported format bits %#llx\n", fp->iface, fp->altsetting, format); } @@ -281,15 +294,16 @@ static int parse_uac2_sample_rate_range(struct snd_usb_audio *chip, /* * parse the format descriptor and stores the possible sample rates - * on the audioformat table (audio class v2). + * on the audioformat table (audio class v2 and v3). */ -static int parse_audio_format_rates_v2(struct snd_usb_audio *chip, +static int parse_audio_format_rates_v2v3(struct snd_usb_audio *chip, struct audioformat *fp) { struct usb_device *dev = chip->dev; unsigned char tmp[2], *data; int nr_triplets, data_size, ret = 0; - int clock = snd_usb_clock_find_source(chip, fp->clock, false); + int clock = snd_usb_clock_find_source(chip, fp->protocol, + fp->clock, false); if (clock < 0) { dev_err(&dev->dev, @@ -368,13 +382,30 @@ err: * parse the format type I and III descriptors */ static int parse_audio_format_i(struct snd_usb_audio *chip, - struct audioformat *fp, unsigned int format, - struct uac_format_type_i_continuous_descriptor *fmt) + struct audioformat *fp, u64 format, + void *_fmt) { snd_pcm_format_t pcm_format; + unsigned int fmt_type; int ret; - if (fmt->bFormatType == UAC_FORMAT_TYPE_III) { + switch (fp->protocol) { + default: + case UAC_VERSION_1: + case UAC_VERSION_2: { + struct uac_format_type_i_continuous_descriptor *fmt = _fmt; + + fmt_type = fmt->bFormatType; + break; + } + case UAC_VERSION_3: { + /* fp->fmt_type is already set in this case */ + fmt_type = fp->fmt_type; + break; + } + } + + if (fmt_type == UAC_FORMAT_TYPE_III) { /* FIXME: the format type is really IECxxx * but we give normal PCM format to get the existing * apps working... @@ -393,7 +424,7 @@ static int parse_audio_format_i(struct snd_usb_audio *chip, } fp->formats = pcm_format_to_bits(pcm_format); } else { - fp->formats = parse_audio_format_i_type(chip, fp, format, fmt); + fp->formats = parse_audio_format_i_type(chip, fp, format, _fmt); if (!fp->formats) return -EINVAL; } @@ -405,15 +436,20 @@ static int parse_audio_format_i(struct snd_usb_audio *chip, */ switch (fp->protocol) { default: - case UAC_VERSION_1: + case UAC_VERSION_1: { + struct uac_format_type_i_continuous_descriptor *fmt = _fmt; + fp->channels = fmt->bNrChannels; ret = parse_audio_format_rates_v1(chip, fp, (unsigned char *) fmt, 7); break; + } case UAC_VERSION_2: + case UAC_VERSION_3: { /* fp->channels is already set in this case */ - ret = parse_audio_format_rates_v2(chip, fp); + ret = parse_audio_format_rates_v2v3(chip, fp); break; } + } if (fp->channels < 1) { usb_audio_err(chip, @@ -430,7 +466,7 @@ static int parse_audio_format_i(struct snd_usb_audio *chip, */ static int parse_audio_format_ii(struct snd_usb_audio *chip, struct audioformat *fp, - int format, void *_fmt) + u64 format, void *_fmt) { int brate, framesize, ret; @@ -445,7 +481,7 @@ static int parse_audio_format_ii(struct snd_usb_audio *chip, break; default: usb_audio_info(chip, - "%u:%d : unknown format tag %#x is detected. processed as MPEG.\n", + "%u:%d : unknown format tag %#llx is detected. processed as MPEG.\n", fp->iface, fp->altsetting, format); fp->formats = SNDRV_PCM_FMTBIT_MPEG; break; @@ -470,7 +506,7 @@ static int parse_audio_format_ii(struct snd_usb_audio *chip, framesize = le16_to_cpu(fmt->wSamplesPerFrame); usb_audio_info(chip, "found format II with max.bitrate = %d, frame size=%d\n", brate, framesize); fp->frame_size = framesize; - ret = parse_audio_format_rates_v2(chip, fp); + ret = parse_audio_format_rates_v2v3(chip, fp); break; } } @@ -479,7 +515,7 @@ static int parse_audio_format_ii(struct snd_usb_audio *chip, } int snd_usb_parse_audio_format(struct snd_usb_audio *chip, - struct audioformat *fp, unsigned int format, + struct audioformat *fp, u64 format, struct uac_format_type_i_continuous_descriptor *fmt, int stream) { @@ -520,3 +556,26 @@ int snd_usb_parse_audio_format(struct snd_usb_audio *chip, return 0; } +int snd_usb_parse_audio_format_v3(struct snd_usb_audio *chip, + struct audioformat *fp, + struct uac3_as_header_descriptor *as, + int stream) +{ + u64 format = le64_to_cpu(as->bmFormats); + int err; + + /* + * Type I format bits are D0..D6 + * This test works because type IV is not supported + */ + if (format & 0x7f) + fp->fmt_type = UAC_FORMAT_TYPE_I; + else + fp->fmt_type = UAC_FORMAT_TYPE_III; + + err = parse_audio_format_i(chip, fp, format, as); + if (err < 0) + return err; + + return 0; +} diff --git a/sound/usb/format.h b/sound/usb/format.h index 8c3ff9ce0824..e70171892f32 100644 --- a/sound/usb/format.h +++ b/sound/usb/format.h @@ -3,8 +3,12 @@ #define __USBAUDIO_FORMAT_H int snd_usb_parse_audio_format(struct snd_usb_audio *chip, - struct audioformat *fp, unsigned int format, + struct audioformat *fp, u64 format, struct uac_format_type_i_continuous_descriptor *fmt, int stream); +int snd_usb_parse_audio_format_v3(struct snd_usb_audio *chip, + struct audioformat *fp, + struct uac3_as_header_descriptor *as, + int stream); #endif /* __USBAUDIO_FORMAT_H */ diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index 06b22624ab7a..1c02f7373eda 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include @@ -189,7 +190,7 @@ static void *find_audio_control_unit(struct mixer_build *state, USB_DT_CS_INTERFACE)) != NULL) { if (hdr->bLength >= 4 && hdr->bDescriptorSubtype >= UAC_INPUT_TERMINAL && - hdr->bDescriptorSubtype <= UAC2_SAMPLE_RATE_CONVERTER && + hdr->bDescriptorSubtype <= UAC3_SAMPLE_RATE_CONVERTER && hdr->bUnitID == unit) return hdr; } @@ -468,9 +469,10 @@ int snd_usb_mixer_set_ctl_value(struct usb_mixer_elem_info *cval, validx += cval->idx_off; + if (cval->head.mixer->protocol == UAC_VERSION_1) { val_len = cval->val_type >= USB_MIXER_S16 ? 2 : 1; - } else { /* UAC_VERSION_2 */ + } else { /* UAC_VERSION_2/3 */ val_len = uac2_ctl_value_size(cval->val_type); /* FIXME */ @@ -723,6 +725,7 @@ static int get_term_name(struct mixer_build *state, struct usb_audio_term *iterm static int check_input_term(struct mixer_build *state, int id, struct usb_audio_term *term) { + int protocol = state->mixer->protocol; int err; void *p1; @@ -730,16 +733,104 @@ static int check_input_term(struct mixer_build *state, int id, while ((p1 = find_audio_control_unit(state, id)) != NULL) { unsigned char *hdr = p1; term->id = id; - switch (hdr[2]) { - case UAC_INPUT_TERMINAL: - if (state->mixer->protocol == UAC_VERSION_1) { - struct uac_input_terminal_descriptor *d = p1; - term->type = le16_to_cpu(d->wTerminalType); - term->channels = d->bNrChannels; - term->chconfig = le16_to_cpu(d->wChannelConfig); - term->name = d->iTerminal; - } else { /* UAC_VERSION_2 */ - struct uac2_input_terminal_descriptor *d = p1; + + if (protocol == UAC_VERSION_1 || protocol == UAC_VERSION_2) { + switch (hdr[2]) { + case UAC_INPUT_TERMINAL: + if (protocol == UAC_VERSION_1) { + struct uac_input_terminal_descriptor *d = p1; + + term->type = le16_to_cpu(d->wTerminalType); + term->channels = d->bNrChannels; + term->chconfig = le16_to_cpu(d->wChannelConfig); + term->name = d->iTerminal; + } else { /* UAC_VERSION_2 */ + struct uac2_input_terminal_descriptor *d = p1; + + /* call recursively to verify that the + * referenced clock entity is valid */ + err = check_input_term(state, d->bCSourceID, term); + if (err < 0) + return err; + + /* save input term properties after recursion, + * to ensure they are not overriden by the + * recursion calls */ + term->id = id; + term->type = le16_to_cpu(d->wTerminalType); + term->channels = d->bNrChannels; + term->chconfig = le32_to_cpu(d->bmChannelConfig); + term->name = d->iTerminal; + } + return 0; + case UAC_FEATURE_UNIT: { + /* the header is the same for v1 and v2 */ + struct uac_feature_unit_descriptor *d = p1; + + id = d->bSourceID; + break; /* continue to parse */ + } + case UAC_MIXER_UNIT: { + struct uac_mixer_unit_descriptor *d = p1; + + term->type = d->bDescriptorSubtype << 16; /* virtual type */ + term->channels = uac_mixer_unit_bNrChannels(d); + term->chconfig = uac_mixer_unit_wChannelConfig(d, protocol); + term->name = uac_mixer_unit_iMixer(d); + return 0; + } + case UAC_SELECTOR_UNIT: + case UAC2_CLOCK_SELECTOR: { + struct uac_selector_unit_descriptor *d = p1; + /* call recursively to retrieve the channel info */ + err = check_input_term(state, d->baSourceID[0], term); + if (err < 0) + return err; + term->type = d->bDescriptorSubtype << 16; /* virtual type */ + term->id = id; + term->name = uac_selector_unit_iSelector(d); + return 0; + } + case UAC1_PROCESSING_UNIT: + case UAC1_EXTENSION_UNIT: + /* UAC2_PROCESSING_UNIT_V2 */ + /* UAC2_EFFECT_UNIT */ + case UAC2_EXTENSION_UNIT_V2: { + struct uac_processing_unit_descriptor *d = p1; + + if (protocol == UAC_VERSION_2 && + hdr[2] == UAC2_EFFECT_UNIT) { + /* UAC2/UAC1 unit IDs overlap here in an + * uncompatible way. Ignore this unit for now. + */ + return 0; + } + + if (d->bNrInPins) { + id = d->baSourceID[0]; + break; /* continue to parse */ + } + term->type = d->bDescriptorSubtype << 16; /* virtual type */ + term->channels = uac_processing_unit_bNrChannels(d); + term->chconfig = uac_processing_unit_wChannelConfig(d, protocol); + term->name = uac_processing_unit_iProcessing(d, protocol); + return 0; + } + case UAC2_CLOCK_SOURCE: { + struct uac_clock_source_descriptor *d = p1; + + term->type = d->bDescriptorSubtype << 16; /* virtual type */ + term->id = id; + term->name = d->iClockSource; + return 0; + } + default: + return -ENODEV; + } + } else { /* UAC_VERSION_3 */ + switch (hdr[2]) { + case UAC_INPUT_TERMINAL: { + struct uac3_input_terminal_descriptor *d = p1; /* call recursively to verify that the * referenced clock entity is valid */ @@ -752,71 +843,31 @@ static int check_input_term(struct mixer_build *state, int id, * recursion calls */ term->id = id; term->type = le16_to_cpu(d->wTerminalType); - term->channels = d->bNrChannels; - term->chconfig = le32_to_cpu(d->bmChannelConfig); - term->name = d->iTerminal; - } - return 0; - case UAC_FEATURE_UNIT: { - /* the header is the same for v1 and v2 */ - struct uac_feature_unit_descriptor *d = p1; - id = d->bSourceID; - break; /* continue to parse */ - } - case UAC_MIXER_UNIT: { - struct uac_mixer_unit_descriptor *d = p1; - term->type = d->bDescriptorSubtype << 16; /* virtual type */ - term->channels = uac_mixer_unit_bNrChannels(d); - term->chconfig = uac_mixer_unit_wChannelConfig(d, state->mixer->protocol); - term->name = uac_mixer_unit_iMixer(d); - return 0; - } - case UAC_SELECTOR_UNIT: - case UAC2_CLOCK_SELECTOR: { - struct uac_selector_unit_descriptor *d = p1; - /* call recursively to retrieve the channel info */ - err = check_input_term(state, d->baSourceID[0], term); - if (err < 0) - return err; - term->type = d->bDescriptorSubtype << 16; /* virtual type */ - term->id = id; - term->name = uac_selector_unit_iSelector(d); - return 0; - } - case UAC1_PROCESSING_UNIT: - case UAC1_EXTENSION_UNIT: - /* UAC2_PROCESSING_UNIT_V2 */ - /* UAC2_EFFECT_UNIT */ - case UAC2_EXTENSION_UNIT_V2: { - struct uac_processing_unit_descriptor *d = p1; - - if (state->mixer->protocol == UAC_VERSION_2 && - hdr[2] == UAC2_EFFECT_UNIT) { - /* UAC2/UAC1 unit IDs overlap here in an - * uncompatible way. Ignore this unit for now. - */ + + /* REVISIT: UAC3 IT doesn't have channels/cfg */ + term->channels = 0; + term->chconfig = 0; + + term->name = le16_to_cpu(d->wTerminalDescrStr); return 0; } + case UAC3_FEATURE_UNIT: { + struct uac3_feature_unit_descriptor *d = p1; - if (d->bNrInPins) { - id = d->baSourceID[0]; + id = d->bSourceID; break; /* continue to parse */ } - term->type = d->bDescriptorSubtype << 16; /* virtual type */ - term->channels = uac_processing_unit_bNrChannels(d); - term->chconfig = uac_processing_unit_wChannelConfig(d, state->mixer->protocol); - term->name = uac_processing_unit_iProcessing(d, state->mixer->protocol); - return 0; - } - case UAC2_CLOCK_SOURCE: { - struct uac_clock_source_descriptor *d = p1; - term->type = d->bDescriptorSubtype << 16; /* virtual type */ - term->id = id; - term->name = d->iClockSource; - return 0; - } - default: - return -ENODEV; + case UAC3_CLOCK_SOURCE: { + struct uac3_clock_source_descriptor *d = p1; + + term->type = d->bDescriptorSubtype << 16; /* virtual type */ + term->id = id; + term->name = le16_to_cpu(d->wClockSourceStr); + return 0; + } + default: + return -ENODEV; + } } } return -ENODEV; @@ -1423,7 +1474,7 @@ static int parse_clock_source_unit(struct mixer_build *state, int unitid, * The only property of this unit we are interested in is the * clock source validity. If that isn't readable, just bail out. */ - if (!uac2_control_is_readable(hdr->bmControls, + if (!uac_v2v3_control_is_readable(hdr->bmControls, ilog2(UAC2_CS_CONTROL_CLOCK_VALID))) return 0; @@ -1439,7 +1490,7 @@ static int parse_clock_source_unit(struct mixer_build *state, int unitid, cval->val_type = USB_MIXER_BOOLEAN; cval->control = UAC2_CS_CONTROL_CLOCK_VALID; - if (uac2_control_is_writeable(hdr->bmControls, + if (uac_v2v3_control_is_writeable(hdr->bmControls, ilog2(UAC2_CS_CONTROL_CLOCK_VALID))) kctl = snd_ctl_new1(&usb_feature_unit_ctl, cval); else { @@ -1502,7 +1553,7 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, unitid); return -EINVAL; } - } else { + } else if (state->mixer->protocol == UAC_VERSION_2) { struct uac2_feature_unit_descriptor *ftr = _ftr; if (hdr->bLength < 6) { usb_audio_err(state->chip, @@ -1519,6 +1570,24 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, unitid); return -EINVAL; } + } else { /* UAC_VERSION_3 */ + struct uac3_feature_unit_descriptor *ftr = _ftr; + + if (hdr->bLength < 7) { + usb_audio_err(state->chip, + "unit %u: invalid UAC3_FEATURE_UNIT descriptor\n", + unitid); + return -EINVAL; + } + csize = 4; + channels = (ftr->bLength - 7) / 4 - 1; + bmaControls = ftr->bmaControls; + if (hdr->bLength < 7 + csize) { + usb_audio_err(state->chip, + "unit %u: invalid UAC3_FEATURE_UNIT descriptor\n", + unitid); + return -EINVAL; + } } /* parse the source unit */ @@ -1577,7 +1646,7 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, build_feature_ctl(state, _ftr, 0, i, &iterm, unitid, 0); } - } else { /* UAC_VERSION_2 */ + } else { /* UAC_VERSION_2/3 */ for (i = 0; i < ARRAY_SIZE(audio_feature_info); i++) { unsigned int ch_bits = 0; unsigned int ch_read_only = 0; @@ -1587,9 +1656,9 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, mask = snd_usb_combine_bytes(bmaControls + csize * (j+1), csize); - if (uac2_control_is_readable(mask, i)) { + if (uac_v2v3_control_is_readable(mask, i)) { ch_bits |= (1 << j); - if (!uac2_control_is_writeable(mask, i)) + if (!uac_v2v3_control_is_writeable(mask, i)) ch_read_only |= (1 << j); } } @@ -1610,9 +1679,9 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, if (ch_bits & 1) build_feature_ctl(state, _ftr, ch_bits, i, &iterm, unitid, ch_read_only); - if (uac2_control_is_readable(master_bits, i)) + if (uac_v2v3_control_is_readable(master_bits, i)) build_feature_ctl(state, _ftr, 0, i, &iterm, unitid, - !uac2_control_is_writeable(master_bits, i)); + !uac_v2v3_control_is_writeable(master_bits, i)); } } @@ -2220,6 +2289,7 @@ static int parse_audio_selector_unit(struct mixer_build *state, int unitid, static int parse_audio_unit(struct mixer_build *state, int unitid) { unsigned char *p1; + int protocol = state->mixer->protocol; if (test_and_set_bit(unitid, state->unitbitmap)) return 0; /* the unit already visited */ @@ -2230,36 +2300,61 @@ static int parse_audio_unit(struct mixer_build *state, int unitid) return -EINVAL; } - switch (p1[2]) { - case UAC_INPUT_TERMINAL: - return 0; /* NOP */ - case UAC_MIXER_UNIT: - return parse_audio_mixer_unit(state, unitid, p1); - case UAC2_CLOCK_SOURCE: - return parse_clock_source_unit(state, unitid, p1); - case UAC_SELECTOR_UNIT: - case UAC2_CLOCK_SELECTOR: - return parse_audio_selector_unit(state, unitid, p1); - case UAC_FEATURE_UNIT: - return parse_audio_feature_unit(state, unitid, p1); - case UAC1_PROCESSING_UNIT: - /* UAC2_EFFECT_UNIT has the same value */ - if (state->mixer->protocol == UAC_VERSION_1) - return parse_audio_processing_unit(state, unitid, p1); - else - return 0; /* FIXME - effect units not implemented yet */ - case UAC1_EXTENSION_UNIT: - /* UAC2_PROCESSING_UNIT_V2 has the same value */ - if (state->mixer->protocol == UAC_VERSION_1) + if (protocol == UAC_VERSION_1 || protocol == UAC_VERSION_2) { + switch (p1[2]) { + case UAC_INPUT_TERMINAL: + return 0; /* NOP */ + case UAC_MIXER_UNIT: + return parse_audio_mixer_unit(state, unitid, p1); + case UAC2_CLOCK_SOURCE: + return parse_clock_source_unit(state, unitid, p1); + case UAC_SELECTOR_UNIT: + case UAC2_CLOCK_SELECTOR: + return parse_audio_selector_unit(state, unitid, p1); + case UAC_FEATURE_UNIT: + return parse_audio_feature_unit(state, unitid, p1); + case UAC1_PROCESSING_UNIT: + /* UAC2_EFFECT_UNIT has the same value */ + if (protocol == UAC_VERSION_1) + return parse_audio_processing_unit(state, unitid, p1); + else + return 0; /* FIXME - effect units not implemented yet */ + case UAC1_EXTENSION_UNIT: + /* UAC2_PROCESSING_UNIT_V2 has the same value */ + if (protocol == UAC_VERSION_1) + return parse_audio_extension_unit(state, unitid, p1); + else /* UAC_VERSION_2 */ + return parse_audio_processing_unit(state, unitid, p1); + case UAC2_EXTENSION_UNIT_V2: return parse_audio_extension_unit(state, unitid, p1); - else /* UAC_VERSION_2 */ + default: + usb_audio_err(state->chip, + "unit %u: unexpected type 0x%02x\n", unitid, p1[2]); + return -EINVAL; + } + } else { /* UAC_VERSION_3 */ + switch (p1[2]) { + case UAC_INPUT_TERMINAL: + return 0; /* NOP */ + case UAC3_MIXER_UNIT: + return parse_audio_mixer_unit(state, unitid, p1); + case UAC3_CLOCK_SOURCE: + return parse_clock_source_unit(state, unitid, p1); + case UAC3_CLOCK_SELECTOR: + return parse_audio_selector_unit(state, unitid, p1); + case UAC3_FEATURE_UNIT: + return parse_audio_feature_unit(state, unitid, p1); + case UAC3_EFFECT_UNIT: + return 0; /* FIXME - effect units not implemented yet */ + case UAC3_PROCESSING_UNIT: return parse_audio_processing_unit(state, unitid, p1); - case UAC2_EXTENSION_UNIT_V2: - return parse_audio_extension_unit(state, unitid, p1); - default: - usb_audio_err(state->chip, - "unit %u: unexpected type 0x%02x\n", unitid, p1[2]); - return -EINVAL; + case UAC3_EXTENSION_UNIT: + return parse_audio_extension_unit(state, unitid, p1); + default: + usb_audio_err(state->chip, + "unit %u: unexpected type 0x%02x\n", unitid, p1[2]); + return -EINVAL; + } } } @@ -2330,7 +2425,7 @@ static int snd_usb_mixer_controls(struct usb_mixer_interface *mixer) err = parse_audio_unit(&state, desc->bSourceID); if (err < 0 && err != -EINVAL) return err; - } else { /* UAC_VERSION_2 */ + } else if (mixer->protocol == UAC_VERSION_2) { struct uac2_output_terminal_descriptor *desc = p; if (desc->bLength < sizeof(*desc)) @@ -2351,6 +2446,27 @@ static int snd_usb_mixer_controls(struct usb_mixer_interface *mixer) err = parse_audio_unit(&state, desc->bCSourceID); if (err < 0 && err != -EINVAL) return err; + } else { /* UAC_VERSION_3 */ + struct uac3_output_terminal_descriptor *desc = p; + + if (desc->bLength < sizeof(*desc)) + continue; /* invalid descriptor? */ + /* mark terminal ID as visited */ + set_bit(desc->bTerminalID, state.unitbitmap); + state.oterm.id = desc->bTerminalID; + state.oterm.type = le16_to_cpu(desc->wTerminalType); + state.oterm.name = le16_to_cpu(desc->wTerminalDescrStr); + err = parse_audio_unit(&state, desc->bSourceID); + if (err < 0 && err != -EINVAL) + return err; + + /* + * For UAC3, use the same approach to also add the + * clock selectors + */ + err = parse_audio_unit(&state, desc->bCSourceID); + if (err < 0 && err != -EINVAL) + return err; } } @@ -2597,6 +2713,9 @@ int snd_usb_create_mixer(struct snd_usb_audio *chip, int ctrlif, case UAC_VERSION_2: mixer->protocol = UAC_VERSION_2; break; + case UAC_VERSION_3: + mixer->protocol = UAC_VERSION_3; + break; } if ((err = snd_usb_mixer_controls(mixer)) < 0 || diff --git a/sound/usb/stream.c b/sound/usb/stream.c index dbbe854745ab..6a8f5843334e 100644 --- a/sound/usb/stream.c +++ b/sound/usb/stream.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -311,6 +312,153 @@ static struct snd_pcm_chmap_elem *convert_chmap(int channels, unsigned int bits, return chmap; } +/* UAC3 device stores channels information in Cluster Descriptors */ +static struct +snd_pcm_chmap_elem *convert_chmap_v3(struct uac3_cluster_header_descriptor + *cluster) +{ + unsigned int channels = cluster->bNrChannels; + struct snd_pcm_chmap_elem *chmap; + void *p = cluster; + int len, c; + + if (channels > ARRAY_SIZE(chmap->map)) + return NULL; + + chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); + if (!chmap) + return NULL; + + len = le16_to_cpu(cluster->wLength); + c = 0; + p += sizeof(struct uac3_cluster_header_descriptor); + + while (((p - (void *)cluster) < len) && (c < channels)) { + struct uac3_cluster_segment_descriptor *cs_desc = p; + u16 cs_len; + u8 cs_type; + + cs_len = le16_to_cpu(cs_desc->wLength); + cs_type = cs_desc->bSegmentType; + + if (cs_type == UAC3_CHANNEL_INFORMATION) { + struct uac3_cluster_information_segment_descriptor *is = p; + unsigned char map; + + /* + * TODO: this conversion is not complete, update it + * after adding UAC3 values to asound.h + */ + switch (is->bChPurpose) { + case UAC3_CH_MONO: + map = SNDRV_CHMAP_MONO; + break; + case UAC3_CH_LEFT: + case UAC3_CH_FRONT_LEFT: + case UAC3_CH_HEADPHONE_LEFT: + map = SNDRV_CHMAP_FL; + break; + case UAC3_CH_RIGHT: + case UAC3_CH_FRONT_RIGHT: + case UAC3_CH_HEADPHONE_RIGHT: + map = SNDRV_CHMAP_FR; + break; + case UAC3_CH_FRONT_CENTER: + map = SNDRV_CHMAP_FC; + break; + case UAC3_CH_FRONT_LEFT_OF_CENTER: + map = SNDRV_CHMAP_FLC; + break; + case UAC3_CH_FRONT_RIGHT_OF_CENTER: + map = SNDRV_CHMAP_FRC; + break; + case UAC3_CH_SIDE_LEFT: + map = SNDRV_CHMAP_SL; + break; + case UAC3_CH_SIDE_RIGHT: + map = SNDRV_CHMAP_SR; + break; + case UAC3_CH_BACK_LEFT: + map = SNDRV_CHMAP_RL; + break; + case UAC3_CH_BACK_RIGHT: + map = SNDRV_CHMAP_RR; + break; + case UAC3_CH_BACK_CENTER: + map = SNDRV_CHMAP_RC; + break; + case UAC3_CH_BACK_LEFT_OF_CENTER: + map = SNDRV_CHMAP_RLC; + break; + case UAC3_CH_BACK_RIGHT_OF_CENTER: + map = SNDRV_CHMAP_RRC; + break; + case UAC3_CH_TOP_CENTER: + map = SNDRV_CHMAP_TC; + break; + case UAC3_CH_TOP_FRONT_LEFT: + map = SNDRV_CHMAP_TFL; + break; + case UAC3_CH_TOP_FRONT_RIGHT: + map = SNDRV_CHMAP_TFR; + break; + case UAC3_CH_TOP_FRONT_CENTER: + map = SNDRV_CHMAP_TFC; + break; + case UAC3_CH_TOP_FRONT_LOC: + map = SNDRV_CHMAP_TFLC; + break; + case UAC3_CH_TOP_FRONT_ROC: + map = SNDRV_CHMAP_TFRC; + break; + case UAC3_CH_TOP_SIDE_LEFT: + map = SNDRV_CHMAP_TSL; + break; + case UAC3_CH_TOP_SIDE_RIGHT: + map = SNDRV_CHMAP_TSR; + break; + case UAC3_CH_TOP_BACK_LEFT: + map = SNDRV_CHMAP_TRL; + break; + case UAC3_CH_TOP_BACK_RIGHT: + map = SNDRV_CHMAP_TRR; + break; + case UAC3_CH_TOP_BACK_CENTER: + map = SNDRV_CHMAP_TRC; + break; + case UAC3_CH_BOTTOM_CENTER: + map = SNDRV_CHMAP_BC; + break; + case UAC3_CH_LOW_FREQUENCY_EFFECTS: + map = SNDRV_CHMAP_LFE; + break; + case UAC3_CH_LFE_LEFT: + map = SNDRV_CHMAP_LLFE; + break; + case UAC3_CH_LFE_RIGHT: + map = SNDRV_CHMAP_RLFE; + break; + case UAC3_CH_RELATIONSHIP_UNDEFINED: + default: + map = SNDRV_CHMAP_UNKNOWN; + break; + } + chmap->map[c++] = map; + } + p += cs_len; + } + + if (channels < c) + pr_err("%s: channel number mismatch\n", __func__); + + chmap->channels = channels; + + for (; c < channels; c++) + chmap->map[c] = SNDRV_CHMAP_UNKNOWN; + + return chmap; +} + /* * add this endpoint to the chip instance. * if a stream with the same endpoint already exists, append to it. @@ -461,10 +609,11 @@ snd_usb_find_input_terminal_descriptor(struct usb_host_interface *ctrl_iface, return NULL; } -static struct uac2_output_terminal_descriptor * - snd_usb_find_output_terminal_descriptor(struct usb_host_interface *ctrl_iface, - int terminal_id) +static void * +snd_usb_find_output_terminal_descriptor(struct usb_host_interface *ctrl_iface, + int terminal_id) { + /* OK to use with both UAC2 and UAC3 */ struct uac2_output_terminal_descriptor *term = NULL; while ((term = snd_usb_find_csint_desc(ctrl_iface->extra, @@ -484,10 +633,12 @@ int snd_usb_parse_audio_interface(struct snd_usb_audio *chip, int iface_no) struct usb_host_interface *alts; struct usb_interface_descriptor *altsd; int i, altno, err, stream; - unsigned int format = 0, num_channels = 0; + u64 format = 0; + unsigned int num_channels = 0; struct audioformat *fp = NULL; int num, protocol, clock = 0; - struct uac_format_type_i_continuous_descriptor *fmt; + struct uac_format_type_i_continuous_descriptor *fmt = NULL; + struct snd_pcm_chmap_elem *chmap_v3 = NULL; unsigned int chconfig; dev = chip->dev; @@ -624,38 +775,158 @@ int snd_usb_parse_audio_interface(struct snd_usb_audio *chip, int iface_no) iface_no, altno, as->bTerminalLink); continue; } - } - /* get format type */ - fmt = snd_usb_find_csint_desc(alts->extra, alts->extralen, NULL, UAC_FORMAT_TYPE); - if (!fmt) { + case UAC_VERSION_3: { + struct uac3_input_terminal_descriptor *input_term; + struct uac3_output_terminal_descriptor *output_term; + struct uac3_as_header_descriptor *as; + struct uac3_cluster_header_descriptor *cluster; + struct uac3_hc_descriptor_header hc_header; + u16 cluster_id, wLength; + + as = snd_usb_find_csint_desc(alts->extra, + alts->extralen, + NULL, UAC_AS_GENERAL); + + if (!as) { + dev_err(&dev->dev, + "%u:%d : UAC_AS_GENERAL descriptor not found\n", + iface_no, altno); + continue; + } + + if (as->bLength < sizeof(*as)) { + dev_err(&dev->dev, + "%u:%d : invalid UAC_AS_GENERAL desc\n", + iface_no, altno); + continue; + } + + cluster_id = le16_to_cpu(as->wClusterDescrID); + if (!cluster_id) { + dev_err(&dev->dev, + "%u:%d : no cluster descriptor\n", + iface_no, altno); + continue; + } + + /* + * Get number of channels and channel map through + * High Capability Cluster Descriptor + * + * First step: get High Capability header and + * read size of Cluster Descriptor + */ + err = snd_usb_ctl_msg(chip->dev, + usb_rcvctrlpipe(chip->dev, 0), + UAC3_CS_REQ_HIGH_CAPABILITY_DESCRIPTOR, + USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_IN, + cluster_id, + snd_usb_ctrl_intf(chip), + &hc_header, sizeof(hc_header)); + if (err < 0) + return err; + else if (err != sizeof(hc_header)) { + dev_err(&dev->dev, + "%u:%d : can't get High Capability descriptor\n", + iface_no, altno); + return -EIO; + } + + /* + * Second step: allocate needed amount of memory + * and request Cluster Descriptor + */ + wLength = le16_to_cpu(hc_header.wLength); + cluster = kzalloc(wLength, GFP_KERNEL); + if (!cluster) + return -ENOMEM; + err = snd_usb_ctl_msg(chip->dev, + usb_rcvctrlpipe(chip->dev, 0), + UAC3_CS_REQ_HIGH_CAPABILITY_DESCRIPTOR, + USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_IN, + cluster_id, + snd_usb_ctrl_intf(chip), + cluster, wLength); + if (err < 0) { + kfree(cluster); + return err; + } else if (err != wLength) { + dev_err(&dev->dev, + "%u:%d : can't get Cluster Descriptor\n", + iface_no, altno); + kfree(cluster); + return -EIO; + } + + num_channels = cluster->bNrChannels; + chmap_v3 = convert_chmap_v3(cluster); + + kfree(cluster); + + format = le64_to_cpu(as->bmFormats); + + /* lookup the terminal associated to this interface + * to extract the clock */ + input_term = snd_usb_find_input_terminal_descriptor( + chip->ctrl_intf, + as->bTerminalLink); + + if (input_term) { + clock = input_term->bCSourceID; + break; + } + + output_term = snd_usb_find_output_terminal_descriptor(chip->ctrl_intf, + as->bTerminalLink); + if (output_term) { + clock = output_term->bCSourceID; + break; + } + dev_err(&dev->dev, - "%u:%d : no UAC_FORMAT_TYPE desc\n", - iface_no, altno); + "%u:%d : bogus bTerminalLink %d\n", + iface_no, altno, as->bTerminalLink); continue; } - if (((protocol == UAC_VERSION_1) && (fmt->bLength < 8)) || - ((protocol == UAC_VERSION_2) && (fmt->bLength < 6))) { - dev_err(&dev->dev, - "%u:%d : invalid UAC_FORMAT_TYPE desc\n", - iface_no, altno); - continue; } - /* - * Blue Microphones workaround: The last altsetting is identical - * with the previous one, except for a larger packet size, but - * is actually a mislabeled two-channel setting; ignore it. - */ - if (fmt->bNrChannels == 1 && - fmt->bSubframeSize == 2 && - altno == 2 && num == 3 && - fp && fp->altsetting == 1 && fp->channels == 1 && - fp->formats == SNDRV_PCM_FMTBIT_S16_LE && - protocol == UAC_VERSION_1 && - le16_to_cpu(get_endpoint(alts, 0)->wMaxPacketSize) == + if (protocol == UAC_VERSION_1 || protocol == UAC_VERSION_2) { + /* get format type */ + fmt = snd_usb_find_csint_desc(alts->extra, + alts->extralen, + NULL, UAC_FORMAT_TYPE); + if (!fmt) { + dev_err(&dev->dev, + "%u:%d : no UAC_FORMAT_TYPE desc\n", + iface_no, altno); + continue; + } + if (((protocol == UAC_VERSION_1) && (fmt->bLength < 8)) + || ((protocol == UAC_VERSION_2) && + (fmt->bLength < 6))) { + dev_err(&dev->dev, + "%u:%d : invalid UAC_FORMAT_TYPE desc\n", + iface_no, altno); + continue; + } + + /* + * Blue Microphones workaround: The last altsetting is + * identical with the previous one, except for a larger + * packet size, but is actually a mislabeled two-channel + * setting; ignore it. + */ + if (fmt->bNrChannels == 1 && + fmt->bSubframeSize == 2 && + altno == 2 && num == 3 && + fp && fp->altsetting == 1 && fp->channels == 1 && + fp->formats == SNDRV_PCM_FMTBIT_S16_LE && + protocol == UAC_VERSION_1 && + le16_to_cpu(get_endpoint(alts, 0)->wMaxPacketSize) == fp->maxpacksize * 2) - continue; + continue; + } fp = kzalloc(sizeof(*fp), GFP_KERNEL); if (!fp) @@ -681,17 +952,39 @@ int snd_usb_parse_audio_interface(struct snd_usb_audio *chip, int iface_no) snd_usb_audioformat_attributes_quirk(chip, fp, stream); /* ok, let's parse further... */ - if (snd_usb_parse_audio_format(chip, fp, format, fmt, stream) < 0) { - kfree(fp->rate_table); - kfree(fp); - fp = NULL; - continue; + if (protocol == UAC_VERSION_1 || protocol == UAC_VERSION_2) { + if (snd_usb_parse_audio_format(chip, fp, format, + fmt, stream) < 0) { + kfree(fp->rate_table); + kfree(fp); + fp = NULL; + continue; + } + } else { + struct uac3_as_header_descriptor *as; + + as = snd_usb_find_csint_desc(alts->extra, + alts->extralen, + NULL, UAC_AS_GENERAL); + + if (snd_usb_parse_audio_format_v3(chip, fp, as, + stream) < 0) { + kfree(fp->rate_table); + kfree(fp); + fp = NULL; + continue; + } } /* Create chmap */ if (fp->channels != num_channels) chconfig = 0; - fp->chmap = convert_chmap(fp->channels, chconfig, protocol); + + if (protocol == UAC_VERSION_3) + fp->chmap = chmap_v3; + else + fp->chmap = convert_chmap(fp->channels, chconfig, + protocol); dev_dbg(&dev->dev, "%u:%d: add audio endpoint %#x\n", iface_no, altno, fp->endpoint); err = snd_usb_add_audio_stream(chip, stream, fp); -- cgit v1.2.3 From 94b9d9b7a14cbb1640868d53b27f403ed2e5b4a9 Mon Sep 17 00:00:00 2001 From: Richard Guy Briggs Date: Wed, 21 Mar 2018 04:42:20 -0400 Subject: audit: remove path param from link denied function In commit 45b578fe4c3cade6f4ca1fc934ce199afd857edc ("audit: link denied should not directly generate PATH record") the need for the struct path *link parameter was removed. Remove the now useless struct path argument. Signed-off-by: Richard Guy Briggs Signed-off-by: Paul Moore --- fs/namei.c | 4 ++-- include/linux/audit.h | 6 ++---- kernel/audit.c | 3 +-- 3 files changed, 5 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/fs/namei.c b/fs/namei.c index 9cc91fb7f156..e3682bb72cb5 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -945,7 +945,7 @@ static inline int may_follow_link(struct nameidata *nd) if (nd->flags & LOOKUP_RCU) return -ECHILD; - audit_log_link_denied("follow_link", &nd->stack[0].link); + audit_log_link_denied("follow_link"); return -EACCES; } @@ -1011,7 +1011,7 @@ static int may_linkat(struct path *link) if (safe_hardlink_source(inode) || inode_owner_or_capable(inode)) return 0; - audit_log_link_denied("linkat", link); + audit_log_link_denied("linkat"); return -EPERM; } diff --git a/include/linux/audit.h b/include/linux/audit.h index af410d9fbf2d..75d5b031e802 100644 --- a/include/linux/audit.h +++ b/include/linux/audit.h @@ -146,8 +146,7 @@ extern void audit_log_d_path(struct audit_buffer *ab, const struct path *path); extern void audit_log_key(struct audit_buffer *ab, char *key); -extern void audit_log_link_denied(const char *operation, - const struct path *link); +extern void audit_log_link_denied(const char *operation); extern void audit_log_lost(const char *message); extern int audit_log_task_context(struct audit_buffer *ab); @@ -194,8 +193,7 @@ static inline void audit_log_d_path(struct audit_buffer *ab, { } static inline void audit_log_key(struct audit_buffer *ab, char *key) { } -static inline void audit_log_link_denied(const char *string, - const struct path *link) +static inline void audit_log_link_denied(const char *string) { } static inline int audit_log_task_context(struct audit_buffer *ab) { diff --git a/kernel/audit.c b/kernel/audit.c index 3f2f143edadf..e8bf8d78ac4a 100644 --- a/kernel/audit.c +++ b/kernel/audit.c @@ -2308,9 +2308,8 @@ EXPORT_SYMBOL(audit_log_task_info); /** * audit_log_link_denied - report a link restriction denial * @operation: specific link operation - * @link: the path that triggered the restriction */ -void audit_log_link_denied(const char *operation, const struct path *link) +void audit_log_link_denied(const char *operation) { struct audit_buffer *ab; -- cgit v1.2.3 From 1acfb9b7ee0b1881bb8e875b6757976e48293ec4 Mon Sep 17 00:00:00 2001 From: Jay Fang Date: Mon, 12 Mar 2018 17:13:32 +0800 Subject: PCI: Add decoding for 16 GT/s link speed PCIe 4.0 defines the 16.0 GT/s link speed. Links can run at that speed without any Linux changes, but previously their sysfs "max_link_speed" and "current_link_speed" files contained "Unknown speed", not the expected "16.0 GT/s". Add decoding for the new 16 GT/s link speed. Signed-off-by: Jay Fang [bhelgaas: add PCI_EXP_LNKCAP2_SLS_16_0GB] Signed-off-by: Bjorn Helgaas Reviewed-by: Dongdong Liu --- drivers/pci/pci-sysfs.c | 6 ++++++ drivers/pci/probe.c | 2 +- drivers/pci/slot.c | 1 + include/linux/pci.h | 1 + include/uapi/linux/pci_regs.h | 7 +++++-- 5 files changed, 14 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index eb6bee8724cc..7dc5be545d18 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -168,6 +168,9 @@ static ssize_t max_link_speed_show(struct device *dev, return -EINVAL; switch (linkcap & PCI_EXP_LNKCAP_SLS) { + case PCI_EXP_LNKCAP_SLS_16_0GB: + speed = "16 GT/s"; + break; case PCI_EXP_LNKCAP_SLS_8_0GB: speed = "8 GT/s"; break; @@ -213,6 +216,9 @@ static ssize_t current_link_speed_show(struct device *dev, return -EINVAL; switch (linkstat & PCI_EXP_LNKSTA_CLS) { + case PCI_EXP_LNKSTA_CLS_16_0GB: + speed = "16 GT/s"; + break; case PCI_EXP_LNKSTA_CLS_8_0GB: speed = "8 GT/s"; break; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index ef5377438a1e..86bf045f3d59 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -592,7 +592,7 @@ const unsigned char pcie_link_speed[] = { PCIE_SPEED_2_5GT, /* 1 */ PCIE_SPEED_5_0GT, /* 2 */ PCIE_SPEED_8_0GT, /* 3 */ - PCI_SPEED_UNKNOWN, /* 4 */ + PCIE_SPEED_16_0GT, /* 4 */ PCI_SPEED_UNKNOWN, /* 5 */ PCI_SPEED_UNKNOWN, /* 6 */ PCI_SPEED_UNKNOWN, /* 7 */ diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index d10f556dc03e..191893e19d5c 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -76,6 +76,7 @@ static const char *pci_bus_speed_strings[] = { "2.5 GT/s PCIe", /* 0x14 */ "5.0 GT/s PCIe", /* 0x15 */ "8.0 GT/s PCIe", /* 0x16 */ + "16.0 GT/s PCIe", /* 0x17 */ }; static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf) diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1beda008..8043a5937ad0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -256,6 +256,7 @@ enum pci_bus_speed { PCIE_SPEED_2_5GT = 0x14, PCIE_SPEED_5_0GT = 0x15, PCIE_SPEED_8_0GT = 0x16, + PCIE_SPEED_16_0GT = 0x17, PCI_SPEED_UNKNOWN = 0xff, }; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 0c79eac5e9b8..103ba797a8f3 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -520,6 +520,7 @@ #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ +#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ @@ -547,6 +548,7 @@ #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ +#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ @@ -648,8 +650,9 @@ #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */ #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ -#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */ -#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */ +#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ +#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ +#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ -- cgit v1.2.3 From 031e3601869c815582ca1d49d1ff73de58e446b0 Mon Sep 17 00:00:00 2001 From: Zhichang Yuan Date: Thu, 15 Mar 2018 02:15:50 +0800 Subject: lib: Add generic PIO mapping method 41f8bba7f555 ("of/pci: Add pci_register_io_range() and pci_pio_to_address()") added support for PCI I/O space mapped into CPU physical memory space. With that support, the I/O ranges configured for PCI/PCIe hosts on some architectures can be mapped to logical PIO and converted easily between CPU address and the corresponding logical PIO. Based on this, PCI I/O port space can be accessed via in/out accessors that use memory read/write. But on some platforms, there are bus hosts that access I/O port space with host-local I/O port addresses rather than memory addresses. Add a more generic I/O mapping method to support those devices. With this patch, both the CPU addresses and the host-local port can be mapped into the logical PIO space with different logical/fake PIOs. After this, all the I/O accesses to either PCI MMIO devices or host-local I/O peripherals can be unified into the existing I/O accessors defined in asm-generic/io.h and be redirected to the right device-specific hooks based on the input logical PIO. Tested-by: dann frazier Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: John Garry [bhelgaas: remove -EFAULT return from logic_pio_register_range() per https://lkml.kernel.org/r/20180403143909.GA21171@ulmo, fix NULL pointer checking per https://lkml.kernel.org/r/20180403211505.GA29612@embeddedor.com] Signed-off-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko --- include/asm-generic/io.h | 2 + include/linux/logic_pio.h | 123 ++++++++++++++++++++ lib/Kconfig | 16 +++ lib/Makefile | 2 + lib/logic_pio.c | 280 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 423 insertions(+) create mode 100644 include/linux/logic_pio.h create mode 100644 lib/logic_pio.c (limited to 'include/linux') diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b4531e3b2120..b7996a79d64b 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -351,6 +351,8 @@ static inline void writesq(volatile void __iomem *addr, const void *buffer, #define IO_SPACE_LIMIT 0xffff #endif +#include + /* * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be * implemented on hardware that needs an additional delay for I/O accesses to diff --git a/include/linux/logic_pio.h b/include/linux/logic_pio.h new file mode 100644 index 000000000000..cbd9d8495690 --- /dev/null +++ b/include/linux/logic_pio.h @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 HiSilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + */ + +#ifndef __LINUX_LOGIC_PIO_H +#define __LINUX_LOGIC_PIO_H + +#include + +enum { + LOGIC_PIO_INDIRECT, /* Indirect IO flag */ + LOGIC_PIO_CPU_MMIO, /* Memory-mapped IO flag */ +}; + +struct logic_pio_hwaddr { + struct list_head list; + struct fwnode_handle *fwnode; + resource_size_t hw_start; + resource_size_t io_start; + resource_size_t size; /* range size populated */ + unsigned long flags; + + void *hostdata; + const struct logic_pio_host_ops *ops; +}; + +struct logic_pio_host_ops { + u32 (*in)(void *hostdata, unsigned long addr, size_t dwidth); + void (*out)(void *hostdata, unsigned long addr, u32 val, + size_t dwidth); + u32 (*ins)(void *hostdata, unsigned long addr, void *buffer, + size_t dwidth, unsigned int count); + void (*outs)(void *hostdata, unsigned long addr, const void *buffer, + size_t dwidth, unsigned int count); +}; + +#ifdef CONFIG_INDIRECT_PIO +u8 logic_inb(unsigned long addr); +void logic_outb(u8 value, unsigned long addr); +void logic_outw(u16 value, unsigned long addr); +void logic_outl(u32 value, unsigned long addr); +u16 logic_inw(unsigned long addr); +u32 logic_inl(unsigned long addr); +void logic_outb(u8 value, unsigned long addr); +void logic_outw(u16 value, unsigned long addr); +void logic_outl(u32 value, unsigned long addr); +void logic_insb(unsigned long addr, void *buffer, unsigned int count); +void logic_insl(unsigned long addr, void *buffer, unsigned int count); +void logic_insw(unsigned long addr, void *buffer, unsigned int count); +void logic_outsb(unsigned long addr, const void *buffer, unsigned int count); +void logic_outsw(unsigned long addr, const void *buffer, unsigned int count); +void logic_outsl(unsigned long addr, const void *buffer, unsigned int count); + +#ifndef inb +#define inb logic_inb +#endif + +#ifndef inw +#define inw logic_inw +#endif + +#ifndef inl +#define inl logic_inl +#endif + +#ifndef outb +#define outb logic_outb +#endif + +#ifndef outw +#define outw logic_outw +#endif + +#ifndef outl +#define outl logic_outl +#endif + +#ifndef insb +#define insb logic_insb +#endif + +#ifndef insw +#define insw logic_insw +#endif + +#ifndef insl +#define insl logic_insl +#endif + +#ifndef outsb +#define outsb logic_outsb +#endif + +#ifndef outsw +#define outsw logic_outsw +#endif + +#ifndef outsl +#define outsl logic_outsl +#endif + +/* + * We reserve 0x4000 bytes for Indirect IO as so far this library is only + * used by the HiSilicon LPC Host. If needed, we can reserve a wider IO + * area by redefining the macro below. + */ +#define PIO_INDIRECT_SIZE 0x4000 +#define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - PIO_INDIRECT_SIZE) +#else +#define MMIO_UPPER_LIMIT IO_SPACE_LIMIT +#endif /* CONFIG_INDIRECT_PIO */ + +struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode); +unsigned long logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, + resource_size_t hw_addr, resource_size_t size); +int logic_pio_register_range(struct logic_pio_hwaddr *newrange); +resource_size_t logic_pio_to_hwaddr(unsigned long pio); +unsigned long logic_pio_trans_cpuaddr(resource_size_t hw_addr); + +#endif /* __LINUX_LOGIC_PIO_H */ diff --git a/lib/Kconfig b/lib/Kconfig index e96089499371..5fe577673b98 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -55,6 +55,22 @@ config ARCH_USE_CMPXCHG_LOCKREF config ARCH_HAS_FAST_MULTIPLIER bool +config INDIRECT_PIO + bool "Access I/O in non-MMIO mode" + depends on ARM64 + help + On some platforms where no separate I/O space exists, there are I/O + hosts which can not be accessed in MMIO mode. Using the logical PIO + mechanism, the host-local I/O resource can be mapped into system + logic PIO space shared with MMIO hosts, such as PCI/PCIe, then the + system can access the I/O devices with the mapped-logic PIO through + I/O accessors. + + This way has relatively little I/O performance cost. Please make + sure your devices really need this configure item enabled. + + When in doubt, say N. + config CRC_CCITT tristate "CRC-CCITT functions" help diff --git a/lib/Makefile b/lib/Makefile index a90d4fcd748f..4a9eacda3c8b 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -81,6 +81,8 @@ obj-$(CONFIG_HAS_IOMEM) += iomap_copy.o devres.o obj-$(CONFIG_CHECK_SIGNATURE) += check_signature.o obj-$(CONFIG_DEBUG_LOCKING_API_SELFTESTS) += locking-selftest.o +obj-y += logic_pio.o + obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o obj-$(CONFIG_BTREE) += btree.o diff --git a/lib/logic_pio.c b/lib/logic_pio.c new file mode 100644 index 000000000000..feea48fd1a0d --- /dev/null +++ b/lib/logic_pio.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 HiSilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + */ + +#define pr_fmt(fmt) "LOGIC PIO: " fmt + +#include +#include +#include +#include +#include +#include +#include + +/* The unique hardware address list */ +static LIST_HEAD(io_range_list); +static DEFINE_MUTEX(io_range_mutex); + +/* Consider a kernel general helper for this */ +#define in_range(b, first, len) ((b) >= (first) && (b) < (first) + (len)) + +/** + * logic_pio_register_range - register logical PIO range for a host + * @new_range: pointer to the IO range to be registered. + * + * Returns 0 on success, the error code in case of failure. + * + * Register a new IO range node in the IO range list. + */ +int logic_pio_register_range(struct logic_pio_hwaddr *new_range) +{ + struct logic_pio_hwaddr *range; + resource_size_t start; + resource_size_t end; + resource_size_t mmio_sz = 0; + resource_size_t iio_sz = MMIO_UPPER_LIMIT; + int ret = 0; + + if (!new_range || !new_range->fwnode || !new_range->size) + return -EINVAL; + + start = new_range->hw_start; + end = new_range->hw_start + new_range->size; + + mutex_lock(&io_range_mutex); + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->fwnode == new_range->fwnode) { + /* range already there */ + goto end_register; + } + if (range->flags == LOGIC_PIO_CPU_MMIO && + new_range->flags == LOGIC_PIO_CPU_MMIO) { + /* for MMIO ranges we need to check for overlap */ + if (start >= range->hw_start + range->size || + end < range->hw_start) { + mmio_sz += range->size; + } else { + ret = -EFAULT; + goto end_register; + } + } else if (range->flags == LOGIC_PIO_INDIRECT && + new_range->flags == LOGIC_PIO_INDIRECT) { + iio_sz += range->size; + } + } + + /* range not registered yet, check for available space */ + if (new_range->flags == LOGIC_PIO_CPU_MMIO) { + if (mmio_sz + new_range->size - 1 > MMIO_UPPER_LIMIT) { + /* if it's too big check if 64K space can be reserved */ + if (mmio_sz + SZ_64K - 1 > MMIO_UPPER_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->size = SZ_64K; + pr_warn("Requested IO range too big, new size set to 64K\n"); + } + new_range->io_start = mmio_sz; + } else if (new_range->flags == LOGIC_PIO_INDIRECT) { + if (iio_sz + new_range->size - 1 > IO_SPACE_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->io_start = iio_sz; + } else { + /* invalid flag */ + ret = -EINVAL; + goto end_register; + } + + list_add_tail_rcu(&new_range->list, &io_range_list); + +end_register: + mutex_unlock(&io_range_mutex); + return ret; +} + +/** + * find_io_range_by_fwnode - find logical PIO range for given FW node + * @fwnode: FW node handle associated with logical PIO range + * + * Returns pointer to node on success, NULL otherwise. + * + * Traverse the io_range_list to find the registered node for @fwnode. + */ +struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->fwnode == fwnode) + return range; + } + return NULL; +} + +/* Return a registered range given an input PIO token */ +static struct logic_pio_hwaddr *find_io_range(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (in_range(pio, range->io_start, range->size)) + return range; + } + pr_err("PIO entry token %lx invalid\n", pio); + return NULL; +} + +/** + * logic_pio_to_hwaddr - translate logical PIO to HW address + * @pio: logical PIO value + * + * Returns HW address if valid, ~0 otherwise. + * + * Translate the input logical PIO to the corresponding hardware address. + * The input PIO should be unique in the whole logical PIO space. + */ +resource_size_t logic_pio_to_hwaddr(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + + range = find_io_range(pio); + if (range) + return range->hw_start + pio - range->io_start; + + return (resource_size_t)~0; +} + +/** + * logic_pio_trans_hwaddr - translate HW address to logical PIO + * @fwnode: FW node reference for the host + * @addr: Host-relative HW address + * @size: size to translate + * + * Returns Logical PIO value if successful, ~0UL otherwise + */ +unsigned long logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, + resource_size_t addr, resource_size_t size) +{ + struct logic_pio_hwaddr *range; + + range = find_io_range_by_fwnode(fwnode); + if (!range || range->flags == LOGIC_PIO_CPU_MMIO) { + pr_err("IO range not found or invalid\n"); + return ~0UL; + } + if (range->size < size) { + pr_err("resource size %pa cannot fit in IO range size %pa\n", + &size, &range->size); + return ~0UL; + } + return addr - range->hw_start + range->io_start; +} + +unsigned long logic_pio_trans_cpuaddr(resource_size_t addr) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->flags != LOGIC_PIO_CPU_MMIO) + continue; + if (in_range(addr, range->hw_start, range->size)) + return addr - range->hw_start + range->io_start; + } + pr_err("addr %llx not registered in io_range_list\n", + (unsigned long long) addr); + return ~0UL; +} + +#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE) +#define BUILD_LOGIC_IO(bw, type) \ +type logic_in##bw(unsigned long addr) \ +{ \ + type ret = (type)~0; \ + \ + if (addr < MMIO_UPPER_LIMIT) { \ + ret = read##bw(PCI_IOBASE + addr); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + ret = entry->ops->in(entry->hostdata, \ + addr, sizeof(type)); \ + else \ + WARN_ON_ONCE(1); \ + } \ + return ret; \ +} \ + \ +void logic_out##bw(type value, unsigned long addr) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + write##bw(value, PCI_IOBASE + addr); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->out(entry->hostdata, \ + addr, value, sizeof(type)); \ + else \ + WARN_ON_ONCE(1); \ + } \ +} \ + \ +void logic_ins##bw(unsigned long addr, void *buffer, \ + unsigned int count) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + reads##bw(PCI_IOBASE + addr, buffer, count); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->ins(entry->hostdata, \ + addr, buffer, sizeof(type), count); \ + else \ + WARN_ON_ONCE(1); \ + } \ + \ +} \ + \ +void logic_outs##bw(unsigned long addr, const void *buffer, \ + unsigned int count) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + writes##bw(PCI_IOBASE + addr, buffer, count); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->outs(entry->hostdata, \ + addr, buffer, sizeof(type), count); \ + else \ + WARN_ON_ONCE(1); \ + } \ +} + +BUILD_LOGIC_IO(b, u8) +EXPORT_SYMBOL(logic_inb); +EXPORT_SYMBOL(logic_insb); +EXPORT_SYMBOL(logic_outb); +EXPORT_SYMBOL(logic_outsb); + +BUILD_LOGIC_IO(w, u16) +EXPORT_SYMBOL(logic_inw); +EXPORT_SYMBOL(logic_insw); +EXPORT_SYMBOL(logic_outw); +EXPORT_SYMBOL(logic_outsw); + +BUILD_LOGIC_IO(l, u32) +EXPORT_SYMBOL(logic_inl); +EXPORT_SYMBOL(logic_insl); +EXPORT_SYMBOL(logic_outl); +EXPORT_SYMBOL(logic_outsl); + +#endif /* CONFIG_INDIRECT_PIO && PCI_IOBASE */ -- cgit v1.2.3 From 6e2fb22103b99c26ae30a46512abe75526d8e4c9 Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Wed, 21 Mar 2018 12:42:25 -0400 Subject: block: use 32-bit blk_status_t on Alpha Early alpha processors cannot write a single byte or word; they read 8 bytes, modify the value in registers and write back 8 bytes. The type blk_status_t is defined as one byte, it is often written asynchronously by I/O completion routines, this asynchronous modification can corrupt content of nearby bytes if these nearby bytes can be written simultaneously by another CPU. - one example of such corruption is the structure dm_io where "blk_status_t status" is written by an asynchronous completion routine and "atomic_t io_count" is modified synchronously - another example is the structure dm_buffer where "unsigned hold_count" is modified synchronously from process context and "blk_status_t write_error" is modified asynchronously from bio completion routine This patch fixes the bug by changing the type blk_status_t to 32 bits if we are on Alpha and if we are compiling for a processor that doesn't have the byte-word-extension. Signed-off-by: Mikulas Patocka Cc: stable@vger.kernel.org # 4.13+ Signed-off-by: Jens Axboe --- include/linux/blk_types.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux') diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h index bf18b95ed92d..17b18b91ebac 100644 --- a/include/linux/blk_types.h +++ b/include/linux/blk_types.h @@ -20,8 +20,13 @@ typedef void (bio_end_io_t) (struct bio *); /* * Block error status values. See block/blk-core:blk_errors for the details. + * Alpha cannot write a byte atomically, so we need to use 32-bit value. */ +#if defined(CONFIG_ALPHA) && !defined(__alpha_bwx__) +typedef u32 __bitwise blk_status_t; +#else typedef u8 __bitwise blk_status_t; +#endif #define BLK_STS_OK 0 #define BLK_STS_NOTSUPP ((__force blk_status_t)1) #define BLK_STS_TIMEOUT ((__force blk_status_t)2) -- cgit v1.2.3 From f2d9b66d84f3ff5ea3aff111e6a403e04fa8bf37 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Tue, 20 Mar 2018 15:57:02 +0300 Subject: drivers: base: Unified device connection lookup Several frameworks - clk, gpio, phy, pmw, etc. - maintain lookup tables for describing connections and provide custom API for handling them. This introduces a single generic lookup table and API for the connections. The motivation for this commit is centralizing the connection lookup, but the goal is to ultimately extract the connection descriptions also from firmware by using the fwnode_graph_* functions and other mechanisms that are available. Reviewed-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- Documentation/driver-api/device_connection.rst | 43 ++++++++ drivers/base/Makefile | 3 +- drivers/base/devcon.c | 136 +++++++++++++++++++++++++ include/linux/device.h | 22 ++++ 4 files changed, 203 insertions(+), 1 deletion(-) create mode 100644 Documentation/driver-api/device_connection.rst create mode 100644 drivers/base/devcon.c (limited to 'include/linux') diff --git a/Documentation/driver-api/device_connection.rst b/Documentation/driver-api/device_connection.rst new file mode 100644 index 000000000000..affbc5566ab0 --- /dev/null +++ b/Documentation/driver-api/device_connection.rst @@ -0,0 +1,43 @@ +================== +Device connections +================== + +Introduction +------------ + +Devices often have connections to other devices that are outside of the direct +child/parent relationship. A serial or network communication controller, which +could be a PCI device, may need to be able to get a reference to its PHY +component, which could be attached for example to the I2C bus. Some device +drivers need to be able to control the clocks or the GPIOs for their devices, +and so on. + +Device connections are generic descriptions of any type of connection between +two separate devices. + +Device connections alone do not create a dependency between the two devices. +They are only descriptions which are not tied to either of the devices directly. +A dependency between the two devices exists only if one of the two endpoint +devices requests a reference to the other. The descriptions themselves can be +defined in firmware (not yet supported) or they can be built-in. + +Usage +----- + +Device connections should exist before device ``->probe`` callback is called for +either endpoint device in the description. If the connections are defined in +firmware, this is not a problem. It should be considered if the connection +descriptions are "built-in", and need to be added separately. + +The connection description consists of the names of the two devices with the +connection, i.e. the endpoints, and unique identifier for the connection which +is needed if there are multiple connections between the two devices. + +After a description exists, the devices in it can request reference to the other +endpoint device, or they can request the description itself. + +API +--- + +.. kernel-doc:: drivers/base/devcon.c + : functions: device_connection_find_match device_connection_find device_connection_add device_connection_remove diff --git a/drivers/base/Makefile b/drivers/base/Makefile index e32a52490051..12a7f64d35a9 100644 --- a/drivers/base/Makefile +++ b/drivers/base/Makefile @@ -5,7 +5,8 @@ obj-y := component.o core.o bus.o dd.o syscore.o \ driver.o class.o platform.o \ cpu.o firmware.o init.o map.o devres.o \ attribute_container.o transport_class.o \ - topology.o container.o property.o cacheinfo.o + topology.o container.o property.o cacheinfo.o \ + devcon.o obj-$(CONFIG_DEVTMPFS) += devtmpfs.o obj-$(CONFIG_DMA_CMA) += dma-contiguous.o obj-y += power/ diff --git a/drivers/base/devcon.c b/drivers/base/devcon.c new file mode 100644 index 000000000000..d427e806cd73 --- /dev/null +++ b/drivers/base/devcon.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Device connections + * + * Copyright (C) 2018 Intel Corporation + * Author: Heikki Krogerus + */ + +#include + +static DEFINE_MUTEX(devcon_lock); +static LIST_HEAD(devcon_list); + +/** + * device_connection_find_match - Find physical connection to a device + * @dev: Device with the connection + * @con_id: Identifier for the connection + * @data: Data for the match function + * @match: Function to check and convert the connection description + * + * Find a connection with unique identifier @con_id between @dev and another + * device. @match will be used to convert the connection description to data the + * caller is expecting to be returned. + */ +void *device_connection_find_match(struct device *dev, const char *con_id, + void *data, + void *(*match)(struct device_connection *con, + int ep, void *data)) +{ + const char *devname = dev_name(dev); + struct device_connection *con; + void *ret = NULL; + int ep; + + if (!match) + return NULL; + + mutex_lock(&devcon_lock); + + list_for_each_entry(con, &devcon_list, list) { + ep = match_string(con->endpoint, 2, devname); + if (ep < 0) + continue; + + if (con_id && strcmp(con->id, con_id)) + continue; + + ret = match(con, !ep, data); + if (ret) + break; + } + + mutex_unlock(&devcon_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(device_connection_find_match); + +extern struct bus_type platform_bus_type; +extern struct bus_type pci_bus_type; +extern struct bus_type i2c_bus_type; +extern struct bus_type spi_bus_type; + +static struct bus_type *generic_match_buses[] = { + &platform_bus_type, +#ifdef CONFIG_PCI + &pci_bus_type, +#endif +#ifdef CONFIG_I2C + &i2c_bus_type, +#endif +#ifdef CONFIG_SPI_MASTER + &spi_bus_type, +#endif + NULL, +}; + +/* This tries to find the device from the most common bus types by name. */ +static void *generic_match(struct device_connection *con, int ep, void *data) +{ + struct bus_type *bus; + struct device *dev; + + for (bus = generic_match_buses[0]; bus; bus++) { + dev = bus_find_device_by_name(bus, NULL, con->endpoint[ep]); + if (dev) + return dev; + } + + /* + * We only get called if a connection was found, tell the caller to + * wait for the other device to show up. + */ + return ERR_PTR(-EPROBE_DEFER); +} + +/** + * device_connection_find - Find two devices connected together + * @dev: Device with the connection + * @con_id: Identifier for the connection + * + * Find a connection with unique identifier @con_id between @dev and + * another device. On success returns handle to the device that is connected + * to @dev, with the reference count for the found device incremented. Returns + * NULL if no matching connection was found, or ERR_PTR(-EPROBE_DEFER) when a + * connection was found but the other device has not been enumerated yet. + */ +struct device *device_connection_find(struct device *dev, const char *con_id) +{ + return device_connection_find_match(dev, con_id, NULL, generic_match); +} +EXPORT_SYMBOL_GPL(device_connection_find); + +/** + * device_connection_add - Register a connection description + * @con: The connection description to be registered + */ +void device_connection_add(struct device_connection *con) +{ + mutex_lock(&devcon_lock); + list_add_tail(&con->list, &devcon_list); + mutex_unlock(&devcon_lock); +} +EXPORT_SYMBOL_GPL(device_connection_add); + +/** + * device_connections_remove - Unregister connection description + * @con: The connection description to be unregistered + */ +void device_connection_remove(struct device_connection *con) +{ + mutex_lock(&devcon_lock); + list_del(&con->list); + mutex_unlock(&devcon_lock); +} +EXPORT_SYMBOL_GPL(device_connection_remove); diff --git a/include/linux/device.h b/include/linux/device.h index b093405ed525..204ff64279fd 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -729,6 +729,28 @@ struct device_dma_parameters { unsigned long segment_boundary_mask; }; +/** + * struct device_connection - Device Connection Descriptor + * @endpoint: The names of the two devices connected together + * @id: Unique identifier for the connection + * @list: List head, private, for internal use only + */ +struct device_connection { + const char *endpoint[2]; + const char *id; + struct list_head list; +}; + +void *device_connection_find_match(struct device *dev, const char *con_id, + void *data, + void *(*match)(struct device_connection *con, + int ep, void *data)); + +struct device *device_connection_find(struct device *dev, const char *con_id); + +void device_connection_add(struct device_connection *con); +void device_connection_remove(struct device_connection *con); + /** * enum device_link_state - Device link states. * @DL_STATE_NONE: The presence of the drivers is not being tracked. -- cgit v1.2.3 From bdecb33af34f79cbfbb656661210f77c8b8b5b5f Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Tue, 20 Mar 2018 15:57:03 +0300 Subject: usb: typec: API for controlling USB Type-C Multiplexers USB Type-C connectors consist of various muxes and switches that route the pins on the connector to the right locations. The USB Type-C drivers need to be able to control the muxes, as they are the ones that know things like the cable plug orientation, and the current mode that was negotiated with the partner. This introduces a small API for registering and controlling cable plug orientation switches, and separate small API for registering and controlling pin multiplexer/demultiplexer switches that are needed with Accessory/Alternate Modes. Reviewed-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- Documentation/driver-api/usb/typec.rst | 73 +- drivers/usb/typec/Makefile | 1 + drivers/usb/typec/class.c | 1435 ++++++++++++++++++++++++++++++++ drivers/usb/typec/mux.c | 191 +++++ drivers/usb/typec/typec.c | 1365 ------------------------------ include/linux/usb/typec.h | 14 + include/linux/usb/typec_mux.h | 55 ++ 7 files changed, 1758 insertions(+), 1376 deletions(-) create mode 100644 drivers/usb/typec/class.c create mode 100644 drivers/usb/typec/mux.c delete mode 100644 drivers/usb/typec/typec.c create mode 100644 include/linux/usb/typec_mux.h (limited to 'include/linux') diff --git a/Documentation/driver-api/usb/typec.rst b/Documentation/driver-api/usb/typec.rst index 8a7249f2ff04..feb31946490b 100644 --- a/Documentation/driver-api/usb/typec.rst +++ b/Documentation/driver-api/usb/typec.rst @@ -61,7 +61,7 @@ Registering the ports The port drivers will describe every Type-C port they control with struct typec_capability data structure, and register them with the following API: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_register_port typec_unregister_port When registering the ports, the prefer_role member in struct typec_capability @@ -80,7 +80,7 @@ typec_partner_desc. The class copies the details of the partner during registration. The class offers the following API for registering/unregistering partners. -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_register_partner typec_unregister_partner The class will provide a handle to struct typec_partner if the registration was @@ -92,7 +92,7 @@ should include handle to struct usb_pd_identity instance. The class will then create a sysfs directory for the identity under the partner device. The result of Discover Identity command can then be reported with the following API: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_partner_set_identity Registering Cables @@ -113,7 +113,7 @@ typec_cable_desc and about a plug in struct typec_plug_desc. The class copies the details during registration. The class offers the following API for registering/unregistering cables and their plugs: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_register_cable typec_unregister_cable typec_register_plug typec_unregister_plug The class will provide a handle to struct typec_cable and struct typec_plug if @@ -125,7 +125,7 @@ include handle to struct usb_pd_identity instance. The class will then create a sysfs directory for the identity under the cable device. The result of Discover Identity command can then be reported with the following API: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_cable_set_identity Notifications @@ -135,7 +135,7 @@ When the partner has executed a role change, or when the default roles change during connection of a partner or cable, the port driver must use the following APIs to report it to the class: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_set_data_role typec_set_pwr_role typec_set_vconn_role typec_set_pwr_opmode Alternate Modes @@ -150,7 +150,7 @@ and struct typec_altmode_desc which is a container for all the supported modes. Ports that support Alternate Modes need to register each SVID they support with the following API: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_port_register_altmode If a partner or cable plug provides a list of SVIDs as response to USB Power @@ -159,12 +159,12 @@ registered. API for the partners: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_partner_register_altmode API for the Cable Plugs: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_plug_register_altmode So ports, partners and cable plugs will register the alternate modes with their @@ -172,11 +172,62 @@ own functions, but the registration will always return a handle to struct typec_altmode on success, or NULL. The unregistration will happen with the same function: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_unregister_altmode If a partner or cable plug enters or exits a mode, the port driver needs to notify the class with the following API: -.. kernel-doc:: drivers/usb/typec/typec.c +.. kernel-doc:: drivers/usb/typec/class.c :functions: typec_altmode_update_active + +Multiplexer/DeMultiplexer Switches +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +USB Type-C connectors may have one or more mux/demux switches behind them. Since +the plugs can be inserted right-side-up or upside-down, a switch is needed to +route the correct data pairs from the connector to the USB controllers. If +Alternate or Accessory Modes are supported, another switch is needed that can +route the pins on the connector to some other component besides USB. USB Type-C +Connector Class supplies an API for registering those switches. + +.. kernel-doc:: drivers/usb/typec/mux.c + :functions: typec_switch_register typec_switch_unregister typec_mux_register typec_mux_unregister + +In most cases the same physical mux will handle both the orientation and mode. +However, as the port drivers will be responsible for the orientation, and the +alternate mode drivers for the mode, the two are always separated into their +own logical components: "mux" for the mode and "switch" for the orientation. + +When a port is registered, USB Type-C Connector Class requests both the mux and +the switch for the port. The drivers can then use the following API for +controlling them: + +.. kernel-doc:: drivers/usb/typec/class.c + :functions: typec_set_orientation typec_set_mode + +If the connector is dual-role capable, there may also be a switch for the data +role. USB Type-C Connector Class does not supply separate API for them. The +port drivers can use USB Role Class API with those. + +Illustration of the muxes behind a connector that supports an alternate mode: + + ------------------------ + | Connector | + ------------------------ + | | + ------------------------ + \ Orientation / + -------------------- + | + -------------------- + / Mode \ + ------------------------ + / \ + ------------------------ -------------------- + | Alt Mode | / USB Role \ + ------------------------ ------------------------ + / \ + ------------------------ ------------------------ + | USB Host | | USB Device | + ------------------------ ------------------------ diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile index bb3138a6eaac..56b2e9516ec1 100644 --- a/drivers/usb/typec/Makefile +++ b/drivers/usb/typec/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_TYPEC) += typec.o +typec-y := class.o mux.o obj-$(CONFIG_TYPEC_TCPM) += tcpm.o obj-y += fusb302/ obj-$(CONFIG_TYPEC_WCOVE) += typec_wcove.o diff --git a/drivers/usb/typec/class.c b/drivers/usb/typec/class.c new file mode 100644 index 000000000000..2620a694704f --- /dev/null +++ b/drivers/usb/typec/class.c @@ -0,0 +1,1435 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * USB Type-C Connector Class + * + * Copyright (C) 2017, Intel Corporation + * Author: Heikki Krogerus + */ + +#include +#include +#include +#include +#include +#include + +struct typec_mode { + int index; + u32 vdo; + char *desc; + enum typec_port_type roles; + + struct typec_altmode *alt_mode; + + unsigned int active:1; + + char group_name[6]; + struct attribute_group group; + struct attribute *attrs[5]; + struct device_attribute vdo_attr; + struct device_attribute desc_attr; + struct device_attribute active_attr; + struct device_attribute roles_attr; +}; + +struct typec_altmode { + struct device dev; + u16 svid; + int n_modes; + struct typec_mode modes[ALTMODE_MAX_MODES]; + const struct attribute_group *mode_groups[ALTMODE_MAX_MODES]; +}; + +struct typec_plug { + struct device dev; + enum typec_plug_index index; +}; + +struct typec_cable { + struct device dev; + enum typec_plug_type type; + struct usb_pd_identity *identity; + unsigned int active:1; +}; + +struct typec_partner { + struct device dev; + unsigned int usb_pd:1; + struct usb_pd_identity *identity; + enum typec_accessory accessory; +}; + +struct typec_port { + unsigned int id; + struct device dev; + + int prefer_role; + enum typec_data_role data_role; + enum typec_role pwr_role; + enum typec_role vconn_role; + enum typec_pwr_opmode pwr_opmode; + enum typec_port_type port_type; + struct mutex port_type_lock; + + enum typec_orientation orientation; + struct typec_switch *sw; + struct typec_mux *mux; + + const struct typec_capability *cap; +}; + +#define to_typec_port(_dev_) container_of(_dev_, struct typec_port, dev) +#define to_typec_plug(_dev_) container_of(_dev_, struct typec_plug, dev) +#define to_typec_cable(_dev_) container_of(_dev_, struct typec_cable, dev) +#define to_typec_partner(_dev_) container_of(_dev_, struct typec_partner, dev) +#define to_altmode(_dev_) container_of(_dev_, struct typec_altmode, dev) + +static const struct device_type typec_partner_dev_type; +static const struct device_type typec_cable_dev_type; +static const struct device_type typec_plug_dev_type; +static const struct device_type typec_port_dev_type; + +#define is_typec_partner(_dev_) (_dev_->type == &typec_partner_dev_type) +#define is_typec_cable(_dev_) (_dev_->type == &typec_cable_dev_type) +#define is_typec_plug(_dev_) (_dev_->type == &typec_plug_dev_type) +#define is_typec_port(_dev_) (_dev_->type == &typec_port_dev_type) + +static DEFINE_IDA(typec_index_ida); +static struct class *typec_class; + +/* ------------------------------------------------------------------------- */ +/* Common attributes */ + +static const char * const typec_accessory_modes[] = { + [TYPEC_ACCESSORY_NONE] = "none", + [TYPEC_ACCESSORY_AUDIO] = "analog_audio", + [TYPEC_ACCESSORY_DEBUG] = "debug", +}; + +static struct usb_pd_identity *get_pd_identity(struct device *dev) +{ + if (is_typec_partner(dev)) { + struct typec_partner *partner = to_typec_partner(dev); + + return partner->identity; + } else if (is_typec_cable(dev)) { + struct typec_cable *cable = to_typec_cable(dev); + + return cable->identity; + } + return NULL; +} + +static ssize_t id_header_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct usb_pd_identity *id = get_pd_identity(dev); + + return sprintf(buf, "0x%08x\n", id->id_header); +} +static DEVICE_ATTR_RO(id_header); + +static ssize_t cert_stat_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct usb_pd_identity *id = get_pd_identity(dev); + + return sprintf(buf, "0x%08x\n", id->cert_stat); +} +static DEVICE_ATTR_RO(cert_stat); + +static ssize_t product_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct usb_pd_identity *id = get_pd_identity(dev); + + return sprintf(buf, "0x%08x\n", id->product); +} +static DEVICE_ATTR_RO(product); + +static struct attribute *usb_pd_id_attrs[] = { + &dev_attr_id_header.attr, + &dev_attr_cert_stat.attr, + &dev_attr_product.attr, + NULL +}; + +static const struct attribute_group usb_pd_id_group = { + .name = "identity", + .attrs = usb_pd_id_attrs, +}; + +static const struct attribute_group *usb_pd_id_groups[] = { + &usb_pd_id_group, + NULL, +}; + +static void typec_report_identity(struct device *dev) +{ + sysfs_notify(&dev->kobj, "identity", "id_header"); + sysfs_notify(&dev->kobj, "identity", "cert_stat"); + sysfs_notify(&dev->kobj, "identity", "product"); +} + +/* ------------------------------------------------------------------------- */ +/* Alternate Modes */ + +/** + * typec_altmode_update_active - Report Enter/Exit mode + * @alt: Handle to the alternate mode + * @mode: Mode index + * @active: True when the mode has been entered + * + * If a partner or cable plug executes Enter/Exit Mode command successfully, the + * drivers use this routine to report the updated state of the mode. + */ +void typec_altmode_update_active(struct typec_altmode *alt, int mode, + bool active) +{ + struct typec_mode *m = &alt->modes[mode]; + char dir[6]; + + if (m->active == active) + return; + + m->active = active; + snprintf(dir, sizeof(dir), "mode%d", mode); + sysfs_notify(&alt->dev.kobj, dir, "active"); + kobject_uevent(&alt->dev.kobj, KOBJ_CHANGE); +} +EXPORT_SYMBOL_GPL(typec_altmode_update_active); + +/** + * typec_altmode2port - Alternate Mode to USB Type-C port + * @alt: The Alternate Mode + * + * Returns handle to the port that a cable plug or partner with @alt is + * connected to. + */ +struct typec_port *typec_altmode2port(struct typec_altmode *alt) +{ + if (is_typec_plug(alt->dev.parent)) + return to_typec_port(alt->dev.parent->parent->parent); + if (is_typec_partner(alt->dev.parent)) + return to_typec_port(alt->dev.parent->parent); + if (is_typec_port(alt->dev.parent)) + return to_typec_port(alt->dev.parent); + + return NULL; +} +EXPORT_SYMBOL_GPL(typec_altmode2port); + +static ssize_t +typec_altmode_vdo_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct typec_mode *mode = container_of(attr, struct typec_mode, + vdo_attr); + + return sprintf(buf, "0x%08x\n", mode->vdo); +} + +static ssize_t +typec_altmode_desc_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct typec_mode *mode = container_of(attr, struct typec_mode, + desc_attr); + + return sprintf(buf, "%s\n", mode->desc ? mode->desc : ""); +} + +static ssize_t +typec_altmode_active_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct typec_mode *mode = container_of(attr, struct typec_mode, + active_attr); + + return sprintf(buf, "%s\n", mode->active ? "yes" : "no"); +} + +static ssize_t +typec_altmode_active_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct typec_mode *mode = container_of(attr, struct typec_mode, + active_attr); + struct typec_port *port = typec_altmode2port(mode->alt_mode); + bool activate; + int ret; + + if (!port->cap->activate_mode) + return -EOPNOTSUPP; + + ret = kstrtobool(buf, &activate); + if (ret) + return ret; + + ret = port->cap->activate_mode(port->cap, mode->index, activate); + if (ret) + return ret; + + return size; +} + +static ssize_t +typec_altmode_roles_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct typec_mode *mode = container_of(attr, struct typec_mode, + roles_attr); + ssize_t ret; + + switch (mode->roles) { + case TYPEC_PORT_DFP: + ret = sprintf(buf, "source\n"); + break; + case TYPEC_PORT_UFP: + ret = sprintf(buf, "sink\n"); + break; + case TYPEC_PORT_DRP: + default: + ret = sprintf(buf, "source sink\n"); + break; + } + return ret; +} + +static void typec_init_modes(struct typec_altmode *alt, + const struct typec_mode_desc *desc, bool is_port) +{ + int i; + + for (i = 0; i < alt->n_modes; i++, desc++) { + struct typec_mode *mode = &alt->modes[i]; + + /* Not considering the human readable description critical */ + mode->desc = kstrdup(desc->desc, GFP_KERNEL); + if (desc->desc && !mode->desc) + dev_err(&alt->dev, "failed to copy mode%d desc\n", i); + + mode->alt_mode = alt; + mode->vdo = desc->vdo; + mode->roles = desc->roles; + mode->index = desc->index; + sprintf(mode->group_name, "mode%d", desc->index); + + sysfs_attr_init(&mode->vdo_attr.attr); + mode->vdo_attr.attr.name = "vdo"; + mode->vdo_attr.attr.mode = 0444; + mode->vdo_attr.show = typec_altmode_vdo_show; + + sysfs_attr_init(&mode->desc_attr.attr); + mode->desc_attr.attr.name = "description"; + mode->desc_attr.attr.mode = 0444; + mode->desc_attr.show = typec_altmode_desc_show; + + sysfs_attr_init(&mode->active_attr.attr); + mode->active_attr.attr.name = "active"; + mode->active_attr.attr.mode = 0644; + mode->active_attr.show = typec_altmode_active_show; + mode->active_attr.store = typec_altmode_active_store; + + mode->attrs[0] = &mode->vdo_attr.attr; + mode->attrs[1] = &mode->desc_attr.attr; + mode->attrs[2] = &mode->active_attr.attr; + + /* With ports, list the roles that the mode is supported with */ + if (is_port) { + sysfs_attr_init(&mode->roles_attr.attr); + mode->roles_attr.attr.name = "supported_roles"; + mode->roles_attr.attr.mode = 0444; + mode->roles_attr.show = typec_altmode_roles_show; + + mode->attrs[3] = &mode->roles_attr.attr; + } + + mode->group.attrs = mode->attrs; + mode->group.name = mode->group_name; + + alt->mode_groups[i] = &mode->group; + } +} + +static ssize_t svid_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct typec_altmode *alt = to_altmode(dev); + + return sprintf(buf, "%04x\n", alt->svid); +} +static DEVICE_ATTR_RO(svid); + +static struct attribute *typec_altmode_attrs[] = { + &dev_attr_svid.attr, + NULL +}; +ATTRIBUTE_GROUPS(typec_altmode); + +static void typec_altmode_release(struct device *dev) +{ + struct typec_altmode *alt = to_altmode(dev); + int i; + + for (i = 0; i < alt->n_modes; i++) + kfree(alt->modes[i].desc); + kfree(alt); +} + +static const struct device_type typec_altmode_dev_type = { + .name = "typec_alternate_mode", + .groups = typec_altmode_groups, + .release = typec_altmode_release, +}; + +static struct typec_altmode * +typec_register_altmode(struct device *parent, + const struct typec_altmode_desc *desc) +{ + struct typec_altmode *alt; + int ret; + + alt = kzalloc(sizeof(*alt), GFP_KERNEL); + if (!alt) + return ERR_PTR(-ENOMEM); + + alt->svid = desc->svid; + alt->n_modes = desc->n_modes; + typec_init_modes(alt, desc->modes, is_typec_port(parent)); + + alt->dev.parent = parent; + alt->dev.groups = alt->mode_groups; + alt->dev.type = &typec_altmode_dev_type; + dev_set_name(&alt->dev, "svid-%04x", alt->svid); + + ret = device_register(&alt->dev); + if (ret) { + dev_err(parent, "failed to register alternate mode (%d)\n", + ret); + put_device(&alt->dev); + return ERR_PTR(ret); + } + + return alt; +} + +/** + * typec_unregister_altmode - Unregister Alternate Mode + * @alt: The alternate mode to be unregistered + * + * Unregister device created with typec_partner_register_altmode(), + * typec_plug_register_altmode() or typec_port_register_altmode(). + */ +void typec_unregister_altmode(struct typec_altmode *alt) +{ + if (!IS_ERR_OR_NULL(alt)) + device_unregister(&alt->dev); +} +EXPORT_SYMBOL_GPL(typec_unregister_altmode); + +/* ------------------------------------------------------------------------- */ +/* Type-C Partners */ + +static ssize_t accessory_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct typec_partner *p = to_typec_partner(dev); + + return sprintf(buf, "%s\n", typec_accessory_modes[p->accessory]); +} +static DEVICE_ATTR_RO(accessory_mode); + +static ssize_t supports_usb_power_delivery_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct typec_partner *p = to_typec_partner(dev); + + return sprintf(buf, "%s\n", p->usb_pd ? "yes" : "no"); +} +static DEVICE_ATTR_RO(supports_usb_power_delivery); + +static struct attribute *typec_partner_attrs[] = { + &dev_attr_accessory_mode.attr, + &dev_attr_supports_usb_power_delivery.attr, + NULL +}; +ATTRIBUTE_GROUPS(typec_partner); + +static void typec_partner_release(struct device *dev) +{ + struct typec_partner *partner = to_typec_partner(dev); + + kfree(partner); +} + +static const struct device_type typec_partner_dev_type = { + .name = "typec_partner", + .groups = typec_partner_groups, + .release = typec_partner_release, +}; + +/** + * typec_partner_set_identity - Report result from Discover Identity command + * @partner: The partner updated identity values + * + * This routine is used to report that the result of Discover Identity USB power + * delivery command has become available. + */ +int typec_partner_set_identity(struct typec_partner *partner) +{ + if (!partner->identity) + return -EINVAL; + + typec_report_identity(&partner->dev); + return 0; +} +EXPORT_SYMBOL_GPL(typec_partner_set_identity); + +/** + * typec_partner_register_altmode - Register USB Type-C Partner Alternate Mode + * @partner: USB Type-C Partner that supports the alternate mode + * @desc: Description of the alternate mode + * + * This routine is used to register each alternate mode individually that + * @partner has listed in response to Discover SVIDs command. The modes for a + * SVID listed in response to Discover Modes command need to be listed in an + * array in @desc. + * + * Returns handle to the alternate mode on success or NULL on failure. + */ +struct typec_altmode * +typec_partner_register_altmode(struct typec_partner *partner, + const struct typec_altmode_desc *desc) +{ + return typec_register_altmode(&partner->dev, desc); +} +EXPORT_SYMBOL_GPL(typec_partner_register_altmode); + +/** + * typec_register_partner - Register a USB Type-C Partner + * @port: The USB Type-C Port the partner is connected to + * @desc: Description of the partner + * + * Registers a device for USB Type-C Partner described in @desc. + * + * Returns handle to the partner on success or ERR_PTR on failure. + */ +struct typec_partner *typec_register_partner(struct typec_port *port, + struct typec_partner_desc *desc) +{ + struct typec_partner *partner; + int ret; + + partner = kzalloc(sizeof(*partner), GFP_KERNEL); + if (!partner) + return ERR_PTR(-ENOMEM); + + partner->usb_pd = desc->usb_pd; + partner->accessory = desc->accessory; + + if (desc->identity) { + /* + * Creating directory for the identity only if the driver is + * able to provide data to it. + */ + partner->dev.groups = usb_pd_id_groups; + partner->identity = desc->identity; + } + + partner->dev.class = typec_class; + partner->dev.parent = &port->dev; + partner->dev.type = &typec_partner_dev_type; + dev_set_name(&partner->dev, "%s-partner", dev_name(&port->dev)); + + ret = device_register(&partner->dev); + if (ret) { + dev_err(&port->dev, "failed to register partner (%d)\n", ret); + put_device(&partner->dev); + return ERR_PTR(ret); + } + + return partner; +} +EXPORT_SYMBOL_GPL(typec_register_partner); + +/** + * typec_unregister_partner - Unregister a USB Type-C Partner + * @partner: The partner to be unregistered + * + * Unregister device created with typec_register_partner(). + */ +void typec_unregister_partner(struct typec_partner *partner) +{ + if (!IS_ERR_OR_NULL(partner)) + device_unregister(&partner->dev); +} +EXPORT_SYMBOL_GPL(typec_unregister_partner); + +/* ------------------------------------------------------------------------- */ +/* Type-C Cable Plugs */ + +static void typec_plug_release(struct device *dev) +{ + struct typec_plug *plug = to_typec_plug(dev); + + kfree(plug); +} + +static const struct device_type typec_plug_dev_type = { + .name = "typec_plug", + .release = typec_plug_release, +}; + +/** + * typec_plug_register_altmode - Register USB Type-C Cable Plug Alternate Mode + * @plug: USB Type-C Cable Plug that supports the alternate mode + * @desc: Description of the alternate mode + * + * This routine is used to register each alternate mode individually that @plug + * has listed in response to Discover SVIDs command. The modes for a SVID that + * the plug lists in response to Discover Modes command need to be listed in an + * array in @desc. + * + * Returns handle to the alternate mode on success or ERR_PTR on failure. + */ +struct typec_altmode * +typec_plug_register_altmode(struct typec_plug *plug, + const struct typec_altmode_desc *desc) +{ + return typec_register_altmode(&plug->dev, desc); +} +EXPORT_SYMBOL_GPL(typec_plug_register_altmode); + +/** + * typec_register_plug - Register a USB Type-C Cable Plug + * @cable: USB Type-C Cable with the plug + * @desc: Description of the cable plug + * + * Registers a device for USB Type-C Cable Plug described in @desc. A USB Type-C + * Cable Plug represents a plug with electronics in it that can response to USB + * Power Delivery SOP Prime or SOP Double Prime packages. + * + * Returns handle to the cable plug on success or ERR_PTR on failure. + */ +struct typec_plug *typec_register_plug(struct typec_cable *cable, + struct typec_plug_desc *desc) +{ + struct typec_plug *plug; + char name[8]; + int ret; + + plug = kzalloc(sizeof(*plug), GFP_KERNEL); + if (!plug) + return ERR_PTR(-ENOMEM); + + sprintf(name, "plug%d", desc->index); + + plug->index = desc->index; + plug->dev.class = typec_class; + plug->dev.parent = &cable->dev; + plug->dev.type = &typec_plug_dev_type; + dev_set_name(&plug->dev, "%s-%s", dev_name(cable->dev.parent), name); + + ret = device_register(&plug->dev); + if (ret) { + dev_err(&cable->dev, "failed to register plug (%d)\n", ret); + put_device(&plug->dev); + return ERR_PTR(ret); + } + + return plug; +} +EXPORT_SYMBOL_GPL(typec_register_plug); + +/** + * typec_unregister_plug - Unregister a USB Type-C Cable Plug + * @plug: The cable plug to be unregistered + * + * Unregister device created with typec_register_plug(). + */ +void typec_unregister_plug(struct typec_plug *plug) +{ + if (!IS_ERR_OR_NULL(plug)) + device_unregister(&plug->dev); +} +EXPORT_SYMBOL_GPL(typec_unregister_plug); + +/* Type-C Cables */ + +static ssize_t +type_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct typec_cable *cable = to_typec_cable(dev); + + return sprintf(buf, "%s\n", cable->active ? "active" : "passive"); +} +static DEVICE_ATTR_RO(type); + +static const char * const typec_plug_types[] = { + [USB_PLUG_NONE] = "unknown", + [USB_PLUG_TYPE_A] = "type-a", + [USB_PLUG_TYPE_B] = "type-b", + [USB_PLUG_TYPE_C] = "type-c", + [USB_PLUG_CAPTIVE] = "captive", +}; + +static ssize_t plug_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct typec_cable *cable = to_typec_cable(dev); + + return sprintf(buf, "%s\n", typec_plug_types[cable->type]); +} +static DEVICE_ATTR_RO(plug_type); + +static struct attribute *typec_cable_attrs[] = { + &dev_attr_type.attr, + &dev_attr_plug_type.attr, + NULL +}; +ATTRIBUTE_GROUPS(typec_cable); + +static void typec_cable_release(struct device *dev) +{ + struct typec_cable *cable = to_typec_cable(dev); + + kfree(cable); +} + +static const struct device_type typec_cable_dev_type = { + .name = "typec_cable", + .groups = typec_cable_groups, + .release = typec_cable_release, +}; + +/** + * typec_cable_set_identity - Report result from Discover Identity command + * @cable: The cable updated identity values + * + * This routine is used to report that the result of Discover Identity USB power + * delivery command has become available. + */ +int typec_cable_set_identity(struct typec_cable *cable) +{ + if (!cable->identity) + return -EINVAL; + + typec_report_identity(&cable->dev); + return 0; +} +EXPORT_SYMBOL_GPL(typec_cable_set_identity); + +/** + * typec_register_cable - Register a USB Type-C Cable + * @port: The USB Type-C Port the cable is connected to + * @desc: Description of the cable + * + * Registers a device for USB Type-C Cable described in @desc. The cable will be + * parent for the optional cable plug devises. + * + * Returns handle to the cable on success or ERR_PTR on failure. + */ +struct typec_cable *typec_register_cable(struct typec_port *port, + struct typec_cable_desc *desc) +{ + struct typec_cable *cable; + int ret; + + cable = kzalloc(sizeof(*cable), GFP_KERNEL); + if (!cable) + return ERR_PTR(-ENOMEM); + + cable->type = desc->type; + cable->active = desc->active; + + if (desc->identity) { + /* + * Creating directory for the identity only if the driver is + * able to provide data to it. + */ + cable->dev.groups = usb_pd_id_groups; + cable->identity = desc->identity; + } + + cable->dev.class = typec_class; + cable->dev.parent = &port->dev; + cable->dev.type = &typec_cable_dev_type; + dev_set_name(&cable->dev, "%s-cable", dev_name(&port->dev)); + + ret = device_register(&cable->dev); + if (ret) { + dev_err(&port->dev, "failed to register cable (%d)\n", ret); + put_device(&cable->dev); + return ERR_PTR(ret); + } + + return cable; +} +EXPORT_SYMBOL_GPL(typec_register_cable); + +/** + * typec_unregister_cable - Unregister a USB Type-C Cable + * @cable: The cable to be unregistered + * + * Unregister device created with typec_register_cable(). + */ +void typec_unregister_cable(struct typec_cable *cable) +{ + if (!IS_ERR_OR_NULL(cable)) + device_unregister(&cable->dev); +} +EXPORT_SYMBOL_GPL(typec_unregister_cable); + +/* ------------------------------------------------------------------------- */ +/* USB Type-C ports */ + +static const char * const typec_roles[] = { + [TYPEC_SINK] = "sink", + [TYPEC_SOURCE] = "source", +}; + +static const char * const typec_data_roles[] = { + [TYPEC_DEVICE] = "device", + [TYPEC_HOST] = "host", +}; + +static const char * const typec_port_types[] = { + [TYPEC_PORT_DFP] = "source", + [TYPEC_PORT_UFP] = "sink", + [TYPEC_PORT_DRP] = "dual", +}; + +static const char * const typec_port_types_drp[] = { + [TYPEC_PORT_DFP] = "dual [source] sink", + [TYPEC_PORT_UFP] = "dual source [sink]", + [TYPEC_PORT_DRP] = "[dual] source sink", +}; + +static ssize_t +preferred_role_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct typec_port *port = to_typec_port(dev); + int role; + int ret; + + if (port->cap->type != TYPEC_PORT_DRP) { + dev_dbg(dev, "Preferred role only supported with DRP ports\n"); + return -EOPNOTSUPP; + } + + if (!port->cap->try_role) { + dev_dbg(dev, "Setting preferred role not supported\n"); + return -EOPNOTSUPP; + } + + role = sysfs_match_string(typec_roles, buf); + if (role < 0) { + if (sysfs_streq(buf, "none")) + role = TYPEC_NO_PREFERRED_ROLE; + else + return -EINVAL; + } + + ret = port->cap->try_role(port->cap, role); + if (ret) + return ret; + + port->prefer_role = role; + return size; +} + +static ssize_t +preferred_role_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct typec_port *port = to_typec_port(dev); + + if (port->cap->type != TYPEC_PORT_DRP) + return 0; + + if (port->prefer_role < 0) + return 0; + + return sprintf(buf, "%s\n", typec_roles[port->prefer_role]); +} +static DEVICE_ATTR_RW(preferred_role); + +static ssize_t data_role_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct typec_port *port = to_typec_port(dev); + int ret; + + if (!port->cap->dr_set) { + dev_dbg(dev, "data role swapping not supported\n"); + return -EOPNOTSUPP; + } + + ret = sysfs_match_string(typec_data_roles, buf); + if (ret < 0) + return ret; + + mutex_lock(&port->port_type_lock); + if (port->port_type != TYPEC_PORT_DRP) { + dev_dbg(dev, "port type fixed at \"%s\"", + typec_port_types[port->port_type]); + ret = -EOPNOTSUPP; + goto unlock_and_ret; + } + + ret = port->cap->dr_set(port->cap, ret); + if (ret) + goto unlock_and_ret; + + ret = size; +unlock_and_ret: + mutex_unlock(&port->port_type_lock); + return ret; +} + +static ssize_t data_role_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct typec_port *port = to_typec_port(dev); + + if (port->cap->type == TYPEC_PORT_DRP) + return sprintf(buf, "%s\n", port->data_role == TYPEC_HOST ? + "[host] device" : "host [device]"); + + return sprintf(buf, "[%s]\n", typec_data_roles[port->data_role]); +} +static DEVICE_ATTR_RW(data_role); + +static ssize_t power_role_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct typec_port *port = to_typec_port(dev); + int ret; + + if (!port->cap->pd_revision) { + dev_dbg(dev, "USB Power Delivery not supported\n"); + return -EOPNOTSUPP; + } + + if (!port->cap->pr_set) { + dev_dbg(dev, "power role swapping not supported\n"); + return -EOPNOTSUPP; + } + + if (port->pwr_opmode != TYPEC_PWR_MODE_PD) { + dev_dbg(dev, "partner unable to swap power role\n"); + return -EIO; + } + + ret = sysfs_match_string(typec_roles, buf); + if (ret < 0) + return ret; + + mutex_lock(&port->port_type_lock); + if (port->port_type != TYPEC_PORT_DRP) { + dev_dbg(dev, "port type fixed at \"%s\"", + typec_port_types[port->port_type]); + ret = -EOPNOTSUPP; + goto unlock_and_ret; + } + + ret = port->cap->pr_set(port->cap, ret); + if (ret) + goto unlock_and_ret; + + ret = size; +unlock_and_ret: + mutex_unlock(&port->port_type_lock); + return ret; +} + +static ssize_t power_role_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct typec_port *port = to_typec_port(dev); + + if (port->cap->type == TYPEC_PORT_DRP) + return sprintf(buf, "%s\n", port->pwr_role == TYPEC_SOURCE ? + "[source] sink" : "source [sink]"); + + return sprintf(buf, "[%s]\n", typec_roles[port->pwr_role]); +} +static DEVICE_ATTR_RW(power_role); + +static ssize_t +port_type_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct typec_port *port = to_typec_port(dev); + int ret; + enum typec_port_type type; + + if (!port->cap->port_type_set || port->cap->type != TYPEC_PORT_DRP) { + dev_dbg(dev, "changing port type not supported\n"); + return -EOPNOTSUPP; + } + + ret = sysfs_match_string(typec_port_types, buf); + if (ret < 0) + return ret; + + type = ret; + mutex_lock(&port->port_type_lock); + + if (port->port_type == type) { + ret = size; + goto unlock_and_ret; + } + + ret = port->cap->port_type_set(port->cap, type); + if (ret) + goto unlock_and_ret; + + port->port_type = type; + ret = size; + +unlock_and_ret: + mutex_unlock(&port->port_type_lock); + return ret; +} + +static ssize_t +port_type_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct typec_port *port = to_typec_port(dev); + + if (port->cap->type == TYPEC_PORT_DRP) + return sprintf(buf, "%s\n", + typec_port_types_drp[port->port_type]); + + return sprintf(buf, "[%s]\n", typec_port_types[port->cap->type]); +} +static DEVICE_ATTR_RW(port_type); + +static const char * const typec_pwr_opmodes[] = { + [TYPEC_PWR_MODE_USB] = "default", + [TYPEC_PWR_MODE_1_5A] = "1.5A", + [TYPEC_PWR_MODE_3_0A] = "3.0A", + [TYPEC_PWR_MODE_PD] = "usb_power_delivery", +}; + +static ssize_t power_operation_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct typec_port *port = to_typec_port(dev); + + return sprintf(buf, "%s\n", typec_pwr_opmodes[port->pwr_opmode]); +} +static DEVICE_ATTR_RO(power_operation_mode); + +static ssize_t vconn_source_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct typec_port *port = to_typec_port(dev); + bool source; + int ret; + + if (!port->cap->pd_revision) { + dev_dbg(dev, "VCONN swap depends on USB Power Delivery\n"); + return -EOPNOTSUPP; + } + + if (!port->cap->vconn_set) { + dev_dbg(dev, "VCONN swapping not supported\n"); + return -EOPNOTSUPP; + } + + ret = kstrtobool(buf, &source); + if (ret) + return ret; + + ret = port->cap->vconn_set(port->cap, (enum typec_role)source); + if (ret) + return ret; + + return size; +} + +static ssize_t vconn_source_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct typec_port *port = to_typec_port(dev); + + return sprintf(buf, "%s\n", + port->vconn_role == TYPEC_SOURCE ? "yes" : "no"); +} +static DEVICE_ATTR_RW(vconn_source); + +static ssize_t supported_accessory_modes_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct typec_port *port = to_typec_port(dev); + ssize_t ret = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(port->cap->accessory); i++) { + if (port->cap->accessory[i]) + ret += sprintf(buf + ret, "%s ", + typec_accessory_modes[port->cap->accessory[i]]); + } + + if (!ret) + return sprintf(buf, "none\n"); + + buf[ret - 1] = '\n'; + + return ret; +} +static DEVICE_ATTR_RO(supported_accessory_modes); + +static ssize_t usb_typec_revision_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct typec_port *port = to_typec_port(dev); + u16 rev = port->cap->revision; + + return sprintf(buf, "%d.%d\n", (rev >> 8) & 0xff, (rev >> 4) & 0xf); +} +static DEVICE_ATTR_RO(usb_typec_revision); + +static ssize_t usb_power_delivery_revision_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct typec_port *p = to_typec_port(dev); + + return sprintf(buf, "%d\n", (p->cap->pd_revision >> 8) & 0xff); +} +static DEVICE_ATTR_RO(usb_power_delivery_revision); + +static struct attribute *typec_attrs[] = { + &dev_attr_data_role.attr, + &dev_attr_power_operation_mode.attr, + &dev_attr_power_role.attr, + &dev_attr_preferred_role.attr, + &dev_attr_supported_accessory_modes.attr, + &dev_attr_usb_power_delivery_revision.attr, + &dev_attr_usb_typec_revision.attr, + &dev_attr_vconn_source.attr, + &dev_attr_port_type.attr, + NULL, +}; +ATTRIBUTE_GROUPS(typec); + +static int typec_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + int ret; + + ret = add_uevent_var(env, "TYPEC_PORT=%s", dev_name(dev)); + if (ret) + dev_err(dev, "failed to add uevent TYPEC_PORT\n"); + + return ret; +} + +static void typec_release(struct device *dev) +{ + struct typec_port *port = to_typec_port(dev); + + ida_simple_remove(&typec_index_ida, port->id); + typec_switch_put(port->sw); + typec_mux_put(port->mux); + kfree(port); +} + +static const struct device_type typec_port_dev_type = { + .name = "typec_port", + .groups = typec_groups, + .uevent = typec_uevent, + .release = typec_release, +}; + +/* --------------------------------------- */ +/* Driver callbacks to report role updates */ + +/** + * typec_set_data_role - Report data role change + * @port: The USB Type-C Port where the role was changed + * @role: The new data role + * + * This routine is used by the port drivers to report data role changes. + */ +void typec_set_data_role(struct typec_port *port, enum typec_data_role role) +{ + if (port->data_role == role) + return; + + port->data_role = role; + sysfs_notify(&port->dev.kobj, NULL, "data_role"); + kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); +} +EXPORT_SYMBOL_GPL(typec_set_data_role); + +/** + * typec_set_pwr_role - Report power role change + * @port: The USB Type-C Port where the role was changed + * @role: The new data role + * + * This routine is used by the port drivers to report power role changes. + */ +void typec_set_pwr_role(struct typec_port *port, enum typec_role role) +{ + if (port->pwr_role == role) + return; + + port->pwr_role = role; + sysfs_notify(&port->dev.kobj, NULL, "power_role"); + kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); +} +EXPORT_SYMBOL_GPL(typec_set_pwr_role); + +/** + * typec_set_pwr_role - Report VCONN source change + * @port: The USB Type-C Port which VCONN role changed + * @role: Source when @port is sourcing VCONN, or Sink when it's not + * + * This routine is used by the port drivers to report if the VCONN source is + * changes. + */ +void typec_set_vconn_role(struct typec_port *port, enum typec_role role) +{ + if (port->vconn_role == role) + return; + + port->vconn_role = role; + sysfs_notify(&port->dev.kobj, NULL, "vconn_source"); + kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); +} +EXPORT_SYMBOL_GPL(typec_set_vconn_role); + +static int partner_match(struct device *dev, void *data) +{ + return is_typec_partner(dev); +} + +/** + * typec_set_pwr_opmode - Report changed power operation mode + * @port: The USB Type-C Port where the mode was changed + * @opmode: New power operation mode + * + * This routine is used by the port drivers to report changed power operation + * mode in @port. The modes are USB (default), 1.5A, 3.0A as defined in USB + * Type-C specification, and "USB Power Delivery" when the power levels are + * negotiated with methods defined in USB Power Delivery specification. + */ +void typec_set_pwr_opmode(struct typec_port *port, + enum typec_pwr_opmode opmode) +{ + struct device *partner_dev; + + if (port->pwr_opmode == opmode) + return; + + port->pwr_opmode = opmode; + sysfs_notify(&port->dev.kobj, NULL, "power_operation_mode"); + kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); + + partner_dev = device_find_child(&port->dev, NULL, partner_match); + if (partner_dev) { + struct typec_partner *partner = to_typec_partner(partner_dev); + + if (opmode == TYPEC_PWR_MODE_PD && !partner->usb_pd) { + partner->usb_pd = 1; + sysfs_notify(&partner_dev->kobj, NULL, + "supports_usb_power_delivery"); + } + put_device(partner_dev); + } +} +EXPORT_SYMBOL_GPL(typec_set_pwr_opmode); + +/* ------------------------------------------ */ +/* API for Multiplexer/DeMultiplexer Switches */ + +/** + * typec_set_orientation - Set USB Type-C cable plug orientation + * @port: USB Type-C Port + * @orientation: USB Type-C cable plug orientation + * + * Set cable plug orientation for @port. + */ +int typec_set_orientation(struct typec_port *port, + enum typec_orientation orientation) +{ + int ret; + + if (port->sw) { + ret = port->sw->set(port->sw, orientation); + if (ret) + return ret; + } + + port->orientation = orientation; + + return 0; +} +EXPORT_SYMBOL_GPL(typec_set_orientation); + +/** + * typec_set_mode - Set mode of operation for USB Type-C connector + * @port: USB Type-C port for the connector + * @mode: Operation mode for the connector + * + * Set mode @mode for @port. This function will configure the muxes needed to + * enter @mode. + */ +int typec_set_mode(struct typec_port *port, int mode) +{ + return port->mux ? port->mux->set(port->mux, mode) : 0; +} +EXPORT_SYMBOL_GPL(typec_set_mode); + +/* --------------------------------------- */ + +/** + * typec_port_register_altmode - Register USB Type-C Port Alternate Mode + * @port: USB Type-C Port that supports the alternate mode + * @desc: Description of the alternate mode + * + * This routine is used to register an alternate mode that @port is capable of + * supporting. + * + * Returns handle to the alternate mode on success or ERR_PTR on failure. + */ +struct typec_altmode * +typec_port_register_altmode(struct typec_port *port, + const struct typec_altmode_desc *desc) +{ + return typec_register_altmode(&port->dev, desc); +} +EXPORT_SYMBOL_GPL(typec_port_register_altmode); + +/** + * typec_register_port - Register a USB Type-C Port + * @parent: Parent device + * @cap: Description of the port + * + * Registers a device for USB Type-C Port described in @cap. + * + * Returns handle to the port on success or ERR_PTR on failure. + */ +struct typec_port *typec_register_port(struct device *parent, + const struct typec_capability *cap) +{ + struct typec_port *port; + int role; + int ret; + int id; + + port = kzalloc(sizeof(*port), GFP_KERNEL); + if (!port) + return ERR_PTR(-ENOMEM); + + id = ida_simple_get(&typec_index_ida, 0, 0, GFP_KERNEL); + if (id < 0) { + kfree(port); + return ERR_PTR(id); + } + + port->sw = typec_switch_get(cap->fwnode ? &port->dev : parent); + if (IS_ERR(port->sw)) { + ret = PTR_ERR(port->sw); + goto err_switch; + } + + port->mux = typec_mux_get(cap->fwnode ? &port->dev : parent); + if (IS_ERR(port->mux)) { + ret = PTR_ERR(port->mux); + goto err_mux; + } + + if (cap->type == TYPEC_PORT_DFP) + role = TYPEC_SOURCE; + else if (cap->type == TYPEC_PORT_UFP) + role = TYPEC_SINK; + else + role = cap->prefer_role; + + if (role == TYPEC_SOURCE) { + port->data_role = TYPEC_HOST; + port->pwr_role = TYPEC_SOURCE; + port->vconn_role = TYPEC_SOURCE; + } else { + port->data_role = TYPEC_DEVICE; + port->pwr_role = TYPEC_SINK; + port->vconn_role = TYPEC_SINK; + } + + port->id = id; + port->cap = cap; + port->port_type = cap->type; + mutex_init(&port->port_type_lock); + port->prefer_role = cap->prefer_role; + + port->dev.class = typec_class; + port->dev.parent = parent; + port->dev.fwnode = cap->fwnode; + port->dev.type = &typec_port_dev_type; + dev_set_name(&port->dev, "port%d", id); + + ret = device_register(&port->dev); + if (ret) { + dev_err(parent, "failed to register port (%d)\n", ret); + put_device(&port->dev); + return ERR_PTR(ret); + } + + return port; + +err_mux: + typec_switch_put(port->sw); + +err_switch: + ida_simple_remove(&typec_index_ida, port->id); + kfree(port); + + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(typec_register_port); + +/** + * typec_unregister_port - Unregister a USB Type-C Port + * @port: The port to be unregistered + * + * Unregister device created with typec_register_port(). + */ +void typec_unregister_port(struct typec_port *port) +{ + if (!IS_ERR_OR_NULL(port)) + device_unregister(&port->dev); +} +EXPORT_SYMBOL_GPL(typec_unregister_port); + +static int __init typec_init(void) +{ + typec_class = class_create(THIS_MODULE, "typec"); + return PTR_ERR_OR_ZERO(typec_class); +} +subsys_initcall(typec_init); + +static void __exit typec_exit(void) +{ + class_destroy(typec_class); + ida_destroy(&typec_index_ida); +} +module_exit(typec_exit); + +MODULE_AUTHOR("Heikki Krogerus "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("USB Type-C Connector Class"); diff --git a/drivers/usb/typec/mux.c b/drivers/usb/typec/mux.c new file mode 100644 index 000000000000..f89093bd7185 --- /dev/null +++ b/drivers/usb/typec/mux.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * USB Type-C Multiplexer/DeMultiplexer Switch support + * + * Copyright (C) 2018 Intel Corporation + * Author: Heikki Krogerus + * Hans de Goede + */ + +#include +#include +#include +#include + +static DEFINE_MUTEX(switch_lock); +static DEFINE_MUTEX(mux_lock); +static LIST_HEAD(switch_list); +static LIST_HEAD(mux_list); + +static void *typec_switch_match(struct device_connection *con, int ep, + void *data) +{ + struct typec_switch *sw; + + list_for_each_entry(sw, &switch_list, entry) + if (!strcmp(con->endpoint[ep], dev_name(sw->dev))) + return sw; + + /* + * We only get called if a connection was found, tell the caller to + * wait for the switch to show up. + */ + return ERR_PTR(-EPROBE_DEFER); +} + +/** + * typec_switch_get - Find USB Type-C orientation switch + * @dev: The caller device + * + * Finds a switch linked with @dev. Returns a reference to the switch on + * success, NULL if no matching connection was found, or + * ERR_PTR(-EPROBE_DEFER) when a connection was found but the switch + * has not been enumerated yet. + */ +struct typec_switch *typec_switch_get(struct device *dev) +{ + struct typec_switch *sw; + + mutex_lock(&switch_lock); + sw = device_connection_find_match(dev, "typec-switch", NULL, + typec_switch_match); + if (!IS_ERR_OR_NULL(sw)) + get_device(sw->dev); + mutex_unlock(&switch_lock); + + return sw; +} +EXPORT_SYMBOL_GPL(typec_switch_get); + +/** + * typec_put_switch - Release USB Type-C orientation switch + * @sw: USB Type-C orientation switch + * + * Decrement reference count for @sw. + */ +void typec_switch_put(struct typec_switch *sw) +{ + if (!IS_ERR_OR_NULL(sw)) + put_device(sw->dev); +} +EXPORT_SYMBOL_GPL(typec_switch_put); + +/** + * typec_switch_register - Register USB Type-C orientation switch + * @sw: USB Type-C orientation switch + * + * This function registers a switch that can be used for routing the correct + * data pairs depending on the cable plug orientation from the USB Type-C + * connector to the USB controllers. USB Type-C plugs can be inserted + * right-side-up or upside-down. + */ +int typec_switch_register(struct typec_switch *sw) +{ + mutex_lock(&switch_lock); + list_add_tail(&sw->entry, &switch_list); + mutex_unlock(&switch_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(typec_switch_register); + +/** + * typec_switch_unregister - Unregister USB Type-C orientation switch + * @sw: USB Type-C orientation switch + * + * Unregister switch that was registered with typec_switch_register(). + */ +void typec_switch_unregister(struct typec_switch *sw) +{ + mutex_lock(&switch_lock); + list_del(&sw->entry); + mutex_unlock(&switch_lock); +} +EXPORT_SYMBOL_GPL(typec_switch_unregister); + +/* ------------------------------------------------------------------------- */ + +static void *typec_mux_match(struct device_connection *con, int ep, void *data) +{ + struct typec_mux *mux; + + list_for_each_entry(mux, &mux_list, entry) + if (!strcmp(con->endpoint[ep], dev_name(mux->dev))) + return mux; + + /* + * We only get called if a connection was found, tell the caller to + * wait for the switch to show up. + */ + return ERR_PTR(-EPROBE_DEFER); +} + +/** + * typec_mux_get - Find USB Type-C Multiplexer + * @dev: The caller device + * + * Finds a mux linked to the caller. This function is primarily meant for the + * Type-C drivers. Returns a reference to the mux on success, NULL if no + * matching connection was found, or ERR_PTR(-EPROBE_DEFER) when a connection + * was found but the mux has not been enumerated yet. + */ +struct typec_mux *typec_mux_get(struct device *dev) +{ + struct typec_mux *mux; + + mutex_lock(&mux_lock); + mux = device_connection_find_match(dev, "typec-mux", NULL, + typec_mux_match); + if (!IS_ERR_OR_NULL(mux)) + get_device(mux->dev); + mutex_unlock(&mux_lock); + + return mux; +} +EXPORT_SYMBOL_GPL(typec_mux_get); + +/** + * typec_mux_put - Release handle to a Multiplexer + * @mux: USB Type-C Connector Multiplexer/DeMultiplexer + * + * Decrements reference count for @mux. + */ +void typec_mux_put(struct typec_mux *mux) +{ + if (!IS_ERR_OR_NULL(mux)) + put_device(mux->dev); +} +EXPORT_SYMBOL_GPL(typec_mux_put); + +/** + * typec_mux_register - Register Multiplexer routing USB Type-C pins + * @mux: USB Type-C Connector Multiplexer/DeMultiplexer + * + * USB Type-C connectors can be used for alternate modes of operation besides + * USB when Accessory/Alternate Modes are supported. With some of those modes, + * the pins on the connector need to be reconfigured. This function registers + * multiplexer switches routing the pins on the connector. + */ +int typec_mux_register(struct typec_mux *mux) +{ + mutex_lock(&mux_lock); + list_add_tail(&mux->entry, &mux_list); + mutex_unlock(&mux_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(typec_mux_register); + +/** + * typec_mux_unregister - Unregister Multiplexer Switch + * @sw: USB Type-C Connector Multiplexer/DeMultiplexer + * + * Unregister mux that was registered with typec_mux_register(). + */ +void typec_mux_unregister(struct typec_mux *mux) +{ + mutex_lock(&mux_lock); + list_del(&mux->entry); + mutex_unlock(&mux_lock); +} +EXPORT_SYMBOL_GPL(typec_mux_unregister); diff --git a/drivers/usb/typec/typec.c b/drivers/usb/typec/typec.c deleted file mode 100644 index dc28ad868d93..000000000000 --- a/drivers/usb/typec/typec.c +++ /dev/null @@ -1,1365 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * USB Type-C Connector Class - * - * Copyright (C) 2017, Intel Corporation - * Author: Heikki Krogerus - */ - -#include -#include -#include -#include -#include - -struct typec_mode { - int index; - u32 vdo; - char *desc; - enum typec_port_type roles; - - struct typec_altmode *alt_mode; - - unsigned int active:1; - - char group_name[6]; - struct attribute_group group; - struct attribute *attrs[5]; - struct device_attribute vdo_attr; - struct device_attribute desc_attr; - struct device_attribute active_attr; - struct device_attribute roles_attr; -}; - -struct typec_altmode { - struct device dev; - u16 svid; - int n_modes; - struct typec_mode modes[ALTMODE_MAX_MODES]; - const struct attribute_group *mode_groups[ALTMODE_MAX_MODES]; -}; - -struct typec_plug { - struct device dev; - enum typec_plug_index index; -}; - -struct typec_cable { - struct device dev; - enum typec_plug_type type; - struct usb_pd_identity *identity; - unsigned int active:1; -}; - -struct typec_partner { - struct device dev; - unsigned int usb_pd:1; - struct usb_pd_identity *identity; - enum typec_accessory accessory; -}; - -struct typec_port { - unsigned int id; - struct device dev; - - int prefer_role; - enum typec_data_role data_role; - enum typec_role pwr_role; - enum typec_role vconn_role; - enum typec_pwr_opmode pwr_opmode; - enum typec_port_type port_type; - struct mutex port_type_lock; - - const struct typec_capability *cap; -}; - -#define to_typec_port(_dev_) container_of(_dev_, struct typec_port, dev) -#define to_typec_plug(_dev_) container_of(_dev_, struct typec_plug, dev) -#define to_typec_cable(_dev_) container_of(_dev_, struct typec_cable, dev) -#define to_typec_partner(_dev_) container_of(_dev_, struct typec_partner, dev) -#define to_altmode(_dev_) container_of(_dev_, struct typec_altmode, dev) - -static const struct device_type typec_partner_dev_type; -static const struct device_type typec_cable_dev_type; -static const struct device_type typec_plug_dev_type; -static const struct device_type typec_port_dev_type; - -#define is_typec_partner(_dev_) (_dev_->type == &typec_partner_dev_type) -#define is_typec_cable(_dev_) (_dev_->type == &typec_cable_dev_type) -#define is_typec_plug(_dev_) (_dev_->type == &typec_plug_dev_type) -#define is_typec_port(_dev_) (_dev_->type == &typec_port_dev_type) - -static DEFINE_IDA(typec_index_ida); -static struct class *typec_class; - -/* Common attributes */ - -static const char * const typec_accessory_modes[] = { - [TYPEC_ACCESSORY_NONE] = "none", - [TYPEC_ACCESSORY_AUDIO] = "analog_audio", - [TYPEC_ACCESSORY_DEBUG] = "debug", -}; - -static struct usb_pd_identity *get_pd_identity(struct device *dev) -{ - if (is_typec_partner(dev)) { - struct typec_partner *partner = to_typec_partner(dev); - - return partner->identity; - } else if (is_typec_cable(dev)) { - struct typec_cable *cable = to_typec_cable(dev); - - return cable->identity; - } - return NULL; -} - -static ssize_t id_header_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct usb_pd_identity *id = get_pd_identity(dev); - - return sprintf(buf, "0x%08x\n", id->id_header); -} -static DEVICE_ATTR_RO(id_header); - -static ssize_t cert_stat_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct usb_pd_identity *id = get_pd_identity(dev); - - return sprintf(buf, "0x%08x\n", id->cert_stat); -} -static DEVICE_ATTR_RO(cert_stat); - -static ssize_t product_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct usb_pd_identity *id = get_pd_identity(dev); - - return sprintf(buf, "0x%08x\n", id->product); -} -static DEVICE_ATTR_RO(product); - -static struct attribute *usb_pd_id_attrs[] = { - &dev_attr_id_header.attr, - &dev_attr_cert_stat.attr, - &dev_attr_product.attr, - NULL -}; - -static const struct attribute_group usb_pd_id_group = { - .name = "identity", - .attrs = usb_pd_id_attrs, -}; - -static const struct attribute_group *usb_pd_id_groups[] = { - &usb_pd_id_group, - NULL, -}; - -static void typec_report_identity(struct device *dev) -{ - sysfs_notify(&dev->kobj, "identity", "id_header"); - sysfs_notify(&dev->kobj, "identity", "cert_stat"); - sysfs_notify(&dev->kobj, "identity", "product"); -} - -/* ------------------------------------------------------------------------- */ -/* Alternate Modes */ - -/** - * typec_altmode_update_active - Report Enter/Exit mode - * @alt: Handle to the alternate mode - * @mode: Mode index - * @active: True when the mode has been entered - * - * If a partner or cable plug executes Enter/Exit Mode command successfully, the - * drivers use this routine to report the updated state of the mode. - */ -void typec_altmode_update_active(struct typec_altmode *alt, int mode, - bool active) -{ - struct typec_mode *m = &alt->modes[mode]; - char dir[6]; - - if (m->active == active) - return; - - m->active = active; - snprintf(dir, sizeof(dir), "mode%d", mode); - sysfs_notify(&alt->dev.kobj, dir, "active"); - kobject_uevent(&alt->dev.kobj, KOBJ_CHANGE); -} -EXPORT_SYMBOL_GPL(typec_altmode_update_active); - -/** - * typec_altmode2port - Alternate Mode to USB Type-C port - * @alt: The Alternate Mode - * - * Returns handle to the port that a cable plug or partner with @alt is - * connected to. - */ -struct typec_port *typec_altmode2port(struct typec_altmode *alt) -{ - if (is_typec_plug(alt->dev.parent)) - return to_typec_port(alt->dev.parent->parent->parent); - if (is_typec_partner(alt->dev.parent)) - return to_typec_port(alt->dev.parent->parent); - if (is_typec_port(alt->dev.parent)) - return to_typec_port(alt->dev.parent); - - return NULL; -} -EXPORT_SYMBOL_GPL(typec_altmode2port); - -static ssize_t -typec_altmode_vdo_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct typec_mode *mode = container_of(attr, struct typec_mode, - vdo_attr); - - return sprintf(buf, "0x%08x\n", mode->vdo); -} - -static ssize_t -typec_altmode_desc_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct typec_mode *mode = container_of(attr, struct typec_mode, - desc_attr); - - return sprintf(buf, "%s\n", mode->desc ? mode->desc : ""); -} - -static ssize_t -typec_altmode_active_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct typec_mode *mode = container_of(attr, struct typec_mode, - active_attr); - - return sprintf(buf, "%s\n", mode->active ? "yes" : "no"); -} - -static ssize_t -typec_altmode_active_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t size) -{ - struct typec_mode *mode = container_of(attr, struct typec_mode, - active_attr); - struct typec_port *port = typec_altmode2port(mode->alt_mode); - bool activate; - int ret; - - if (!port->cap->activate_mode) - return -EOPNOTSUPP; - - ret = kstrtobool(buf, &activate); - if (ret) - return ret; - - ret = port->cap->activate_mode(port->cap, mode->index, activate); - if (ret) - return ret; - - return size; -} - -static ssize_t -typec_altmode_roles_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct typec_mode *mode = container_of(attr, struct typec_mode, - roles_attr); - ssize_t ret; - - switch (mode->roles) { - case TYPEC_PORT_DFP: - ret = sprintf(buf, "source\n"); - break; - case TYPEC_PORT_UFP: - ret = sprintf(buf, "sink\n"); - break; - case TYPEC_PORT_DRP: - default: - ret = sprintf(buf, "source sink\n"); - break; - } - return ret; -} - -static void typec_init_modes(struct typec_altmode *alt, - const struct typec_mode_desc *desc, bool is_port) -{ - int i; - - for (i = 0; i < alt->n_modes; i++, desc++) { - struct typec_mode *mode = &alt->modes[i]; - - /* Not considering the human readable description critical */ - mode->desc = kstrdup(desc->desc, GFP_KERNEL); - if (desc->desc && !mode->desc) - dev_err(&alt->dev, "failed to copy mode%d desc\n", i); - - mode->alt_mode = alt; - mode->vdo = desc->vdo; - mode->roles = desc->roles; - mode->index = desc->index; - sprintf(mode->group_name, "mode%d", desc->index); - - sysfs_attr_init(&mode->vdo_attr.attr); - mode->vdo_attr.attr.name = "vdo"; - mode->vdo_attr.attr.mode = 0444; - mode->vdo_attr.show = typec_altmode_vdo_show; - - sysfs_attr_init(&mode->desc_attr.attr); - mode->desc_attr.attr.name = "description"; - mode->desc_attr.attr.mode = 0444; - mode->desc_attr.show = typec_altmode_desc_show; - - sysfs_attr_init(&mode->active_attr.attr); - mode->active_attr.attr.name = "active"; - mode->active_attr.attr.mode = 0644; - mode->active_attr.show = typec_altmode_active_show; - mode->active_attr.store = typec_altmode_active_store; - - mode->attrs[0] = &mode->vdo_attr.attr; - mode->attrs[1] = &mode->desc_attr.attr; - mode->attrs[2] = &mode->active_attr.attr; - - /* With ports, list the roles that the mode is supported with */ - if (is_port) { - sysfs_attr_init(&mode->roles_attr.attr); - mode->roles_attr.attr.name = "supported_roles"; - mode->roles_attr.attr.mode = 0444; - mode->roles_attr.show = typec_altmode_roles_show; - - mode->attrs[3] = &mode->roles_attr.attr; - } - - mode->group.attrs = mode->attrs; - mode->group.name = mode->group_name; - - alt->mode_groups[i] = &mode->group; - } -} - -static ssize_t svid_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct typec_altmode *alt = to_altmode(dev); - - return sprintf(buf, "%04x\n", alt->svid); -} -static DEVICE_ATTR_RO(svid); - -static struct attribute *typec_altmode_attrs[] = { - &dev_attr_svid.attr, - NULL -}; -ATTRIBUTE_GROUPS(typec_altmode); - -static void typec_altmode_release(struct device *dev) -{ - struct typec_altmode *alt = to_altmode(dev); - int i; - - for (i = 0; i < alt->n_modes; i++) - kfree(alt->modes[i].desc); - kfree(alt); -} - -static const struct device_type typec_altmode_dev_type = { - .name = "typec_alternate_mode", - .groups = typec_altmode_groups, - .release = typec_altmode_release, -}; - -static struct typec_altmode * -typec_register_altmode(struct device *parent, - const struct typec_altmode_desc *desc) -{ - struct typec_altmode *alt; - int ret; - - alt = kzalloc(sizeof(*alt), GFP_KERNEL); - if (!alt) - return ERR_PTR(-ENOMEM); - - alt->svid = desc->svid; - alt->n_modes = desc->n_modes; - typec_init_modes(alt, desc->modes, is_typec_port(parent)); - - alt->dev.parent = parent; - alt->dev.groups = alt->mode_groups; - alt->dev.type = &typec_altmode_dev_type; - dev_set_name(&alt->dev, "svid-%04x", alt->svid); - - ret = device_register(&alt->dev); - if (ret) { - dev_err(parent, "failed to register alternate mode (%d)\n", - ret); - put_device(&alt->dev); - return ERR_PTR(ret); - } - - return alt; -} - -/** - * typec_unregister_altmode - Unregister Alternate Mode - * @alt: The alternate mode to be unregistered - * - * Unregister device created with typec_partner_register_altmode(), - * typec_plug_register_altmode() or typec_port_register_altmode(). - */ -void typec_unregister_altmode(struct typec_altmode *alt) -{ - if (!IS_ERR_OR_NULL(alt)) - device_unregister(&alt->dev); -} -EXPORT_SYMBOL_GPL(typec_unregister_altmode); - -/* ------------------------------------------------------------------------- */ -/* Type-C Partners */ - -static ssize_t accessory_mode_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct typec_partner *p = to_typec_partner(dev); - - return sprintf(buf, "%s\n", typec_accessory_modes[p->accessory]); -} -static DEVICE_ATTR_RO(accessory_mode); - -static ssize_t supports_usb_power_delivery_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct typec_partner *p = to_typec_partner(dev); - - return sprintf(buf, "%s\n", p->usb_pd ? "yes" : "no"); -} -static DEVICE_ATTR_RO(supports_usb_power_delivery); - -static struct attribute *typec_partner_attrs[] = { - &dev_attr_accessory_mode.attr, - &dev_attr_supports_usb_power_delivery.attr, - NULL -}; -ATTRIBUTE_GROUPS(typec_partner); - -static void typec_partner_release(struct device *dev) -{ - struct typec_partner *partner = to_typec_partner(dev); - - kfree(partner); -} - -static const struct device_type typec_partner_dev_type = { - .name = "typec_partner", - .groups = typec_partner_groups, - .release = typec_partner_release, -}; - -/** - * typec_partner_set_identity - Report result from Discover Identity command - * @partner: The partner updated identity values - * - * This routine is used to report that the result of Discover Identity USB power - * delivery command has become available. - */ -int typec_partner_set_identity(struct typec_partner *partner) -{ - if (!partner->identity) - return -EINVAL; - - typec_report_identity(&partner->dev); - return 0; -} -EXPORT_SYMBOL_GPL(typec_partner_set_identity); - -/** - * typec_partner_register_altmode - Register USB Type-C Partner Alternate Mode - * @partner: USB Type-C Partner that supports the alternate mode - * @desc: Description of the alternate mode - * - * This routine is used to register each alternate mode individually that - * @partner has listed in response to Discover SVIDs command. The modes for a - * SVID listed in response to Discover Modes command need to be listed in an - * array in @desc. - * - * Returns handle to the alternate mode on success or NULL on failure. - */ -struct typec_altmode * -typec_partner_register_altmode(struct typec_partner *partner, - const struct typec_altmode_desc *desc) -{ - return typec_register_altmode(&partner->dev, desc); -} -EXPORT_SYMBOL_GPL(typec_partner_register_altmode); - -/** - * typec_register_partner - Register a USB Type-C Partner - * @port: The USB Type-C Port the partner is connected to - * @desc: Description of the partner - * - * Registers a device for USB Type-C Partner described in @desc. - * - * Returns handle to the partner on success or ERR_PTR on failure. - */ -struct typec_partner *typec_register_partner(struct typec_port *port, - struct typec_partner_desc *desc) -{ - struct typec_partner *partner; - int ret; - - partner = kzalloc(sizeof(*partner), GFP_KERNEL); - if (!partner) - return ERR_PTR(-ENOMEM); - - partner->usb_pd = desc->usb_pd; - partner->accessory = desc->accessory; - - if (desc->identity) { - /* - * Creating directory for the identity only if the driver is - * able to provide data to it. - */ - partner->dev.groups = usb_pd_id_groups; - partner->identity = desc->identity; - } - - partner->dev.class = typec_class; - partner->dev.parent = &port->dev; - partner->dev.type = &typec_partner_dev_type; - dev_set_name(&partner->dev, "%s-partner", dev_name(&port->dev)); - - ret = device_register(&partner->dev); - if (ret) { - dev_err(&port->dev, "failed to register partner (%d)\n", ret); - put_device(&partner->dev); - return ERR_PTR(ret); - } - - return partner; -} -EXPORT_SYMBOL_GPL(typec_register_partner); - -/** - * typec_unregister_partner - Unregister a USB Type-C Partner - * @partner: The partner to be unregistered - * - * Unregister device created with typec_register_partner(). - */ -void typec_unregister_partner(struct typec_partner *partner) -{ - if (!IS_ERR_OR_NULL(partner)) - device_unregister(&partner->dev); -} -EXPORT_SYMBOL_GPL(typec_unregister_partner); - -/* ------------------------------------------------------------------------- */ -/* Type-C Cable Plugs */ - -static void typec_plug_release(struct device *dev) -{ - struct typec_plug *plug = to_typec_plug(dev); - - kfree(plug); -} - -static const struct device_type typec_plug_dev_type = { - .name = "typec_plug", - .release = typec_plug_release, -}; - -/** - * typec_plug_register_altmode - Register USB Type-C Cable Plug Alternate Mode - * @plug: USB Type-C Cable Plug that supports the alternate mode - * @desc: Description of the alternate mode - * - * This routine is used to register each alternate mode individually that @plug - * has listed in response to Discover SVIDs command. The modes for a SVID that - * the plug lists in response to Discover Modes command need to be listed in an - * array in @desc. - * - * Returns handle to the alternate mode on success or ERR_PTR on failure. - */ -struct typec_altmode * -typec_plug_register_altmode(struct typec_plug *plug, - const struct typec_altmode_desc *desc) -{ - return typec_register_altmode(&plug->dev, desc); -} -EXPORT_SYMBOL_GPL(typec_plug_register_altmode); - -/** - * typec_register_plug - Register a USB Type-C Cable Plug - * @cable: USB Type-C Cable with the plug - * @desc: Description of the cable plug - * - * Registers a device for USB Type-C Cable Plug described in @desc. A USB Type-C - * Cable Plug represents a plug with electronics in it that can response to USB - * Power Delivery SOP Prime or SOP Double Prime packages. - * - * Returns handle to the cable plug on success or ERR_PTR on failure. - */ -struct typec_plug *typec_register_plug(struct typec_cable *cable, - struct typec_plug_desc *desc) -{ - struct typec_plug *plug; - char name[8]; - int ret; - - plug = kzalloc(sizeof(*plug), GFP_KERNEL); - if (!plug) - return ERR_PTR(-ENOMEM); - - sprintf(name, "plug%d", desc->index); - - plug->index = desc->index; - plug->dev.class = typec_class; - plug->dev.parent = &cable->dev; - plug->dev.type = &typec_plug_dev_type; - dev_set_name(&plug->dev, "%s-%s", dev_name(cable->dev.parent), name); - - ret = device_register(&plug->dev); - if (ret) { - dev_err(&cable->dev, "failed to register plug (%d)\n", ret); - put_device(&plug->dev); - return ERR_PTR(ret); - } - - return plug; -} -EXPORT_SYMBOL_GPL(typec_register_plug); - -/** - * typec_unregister_plug - Unregister a USB Type-C Cable Plug - * @plug: The cable plug to be unregistered - * - * Unregister device created with typec_register_plug(). - */ -void typec_unregister_plug(struct typec_plug *plug) -{ - if (!IS_ERR_OR_NULL(plug)) - device_unregister(&plug->dev); -} -EXPORT_SYMBOL_GPL(typec_unregister_plug); - -/* Type-C Cables */ - -static ssize_t -type_show(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct typec_cable *cable = to_typec_cable(dev); - - return sprintf(buf, "%s\n", cable->active ? "active" : "passive"); -} -static DEVICE_ATTR_RO(type); - -static const char * const typec_plug_types[] = { - [USB_PLUG_NONE] = "unknown", - [USB_PLUG_TYPE_A] = "type-a", - [USB_PLUG_TYPE_B] = "type-b", - [USB_PLUG_TYPE_C] = "type-c", - [USB_PLUG_CAPTIVE] = "captive", -}; - -static ssize_t plug_type_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct typec_cable *cable = to_typec_cable(dev); - - return sprintf(buf, "%s\n", typec_plug_types[cable->type]); -} -static DEVICE_ATTR_RO(plug_type); - -static struct attribute *typec_cable_attrs[] = { - &dev_attr_type.attr, - &dev_attr_plug_type.attr, - NULL -}; -ATTRIBUTE_GROUPS(typec_cable); - -static void typec_cable_release(struct device *dev) -{ - struct typec_cable *cable = to_typec_cable(dev); - - kfree(cable); -} - -static const struct device_type typec_cable_dev_type = { - .name = "typec_cable", - .groups = typec_cable_groups, - .release = typec_cable_release, -}; - -/** - * typec_cable_set_identity - Report result from Discover Identity command - * @cable: The cable updated identity values - * - * This routine is used to report that the result of Discover Identity USB power - * delivery command has become available. - */ -int typec_cable_set_identity(struct typec_cable *cable) -{ - if (!cable->identity) - return -EINVAL; - - typec_report_identity(&cable->dev); - return 0; -} -EXPORT_SYMBOL_GPL(typec_cable_set_identity); - -/** - * typec_register_cable - Register a USB Type-C Cable - * @port: The USB Type-C Port the cable is connected to - * @desc: Description of the cable - * - * Registers a device for USB Type-C Cable described in @desc. The cable will be - * parent for the optional cable plug devises. - * - * Returns handle to the cable on success or ERR_PTR on failure. - */ -struct typec_cable *typec_register_cable(struct typec_port *port, - struct typec_cable_desc *desc) -{ - struct typec_cable *cable; - int ret; - - cable = kzalloc(sizeof(*cable), GFP_KERNEL); - if (!cable) - return ERR_PTR(-ENOMEM); - - cable->type = desc->type; - cable->active = desc->active; - - if (desc->identity) { - /* - * Creating directory for the identity only if the driver is - * able to provide data to it. - */ - cable->dev.groups = usb_pd_id_groups; - cable->identity = desc->identity; - } - - cable->dev.class = typec_class; - cable->dev.parent = &port->dev; - cable->dev.type = &typec_cable_dev_type; - dev_set_name(&cable->dev, "%s-cable", dev_name(&port->dev)); - - ret = device_register(&cable->dev); - if (ret) { - dev_err(&port->dev, "failed to register cable (%d)\n", ret); - put_device(&cable->dev); - return ERR_PTR(ret); - } - - return cable; -} -EXPORT_SYMBOL_GPL(typec_register_cable); - -/** - * typec_unregister_cable - Unregister a USB Type-C Cable - * @cable: The cable to be unregistered - * - * Unregister device created with typec_register_cable(). - */ -void typec_unregister_cable(struct typec_cable *cable) -{ - if (!IS_ERR_OR_NULL(cable)) - device_unregister(&cable->dev); -} -EXPORT_SYMBOL_GPL(typec_unregister_cable); - -/* ------------------------------------------------------------------------- */ -/* USB Type-C ports */ - -static const char * const typec_roles[] = { - [TYPEC_SINK] = "sink", - [TYPEC_SOURCE] = "source", -}; - -static const char * const typec_data_roles[] = { - [TYPEC_DEVICE] = "device", - [TYPEC_HOST] = "host", -}; - -static const char * const typec_port_types[] = { - [TYPEC_PORT_DFP] = "source", - [TYPEC_PORT_UFP] = "sink", - [TYPEC_PORT_DRP] = "dual", -}; - -static const char * const typec_port_types_drp[] = { - [TYPEC_PORT_DFP] = "dual [source] sink", - [TYPEC_PORT_UFP] = "dual source [sink]", - [TYPEC_PORT_DRP] = "[dual] source sink", -}; - -static ssize_t -preferred_role_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t size) -{ - struct typec_port *port = to_typec_port(dev); - int role; - int ret; - - if (port->cap->type != TYPEC_PORT_DRP) { - dev_dbg(dev, "Preferred role only supported with DRP ports\n"); - return -EOPNOTSUPP; - } - - if (!port->cap->try_role) { - dev_dbg(dev, "Setting preferred role not supported\n"); - return -EOPNOTSUPP; - } - - role = sysfs_match_string(typec_roles, buf); - if (role < 0) { - if (sysfs_streq(buf, "none")) - role = TYPEC_NO_PREFERRED_ROLE; - else - return -EINVAL; - } - - ret = port->cap->try_role(port->cap, role); - if (ret) - return ret; - - port->prefer_role = role; - return size; -} - -static ssize_t -preferred_role_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct typec_port *port = to_typec_port(dev); - - if (port->cap->type != TYPEC_PORT_DRP) - return 0; - - if (port->prefer_role < 0) - return 0; - - return sprintf(buf, "%s\n", typec_roles[port->prefer_role]); -} -static DEVICE_ATTR_RW(preferred_role); - -static ssize_t data_role_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - struct typec_port *port = to_typec_port(dev); - int ret; - - if (!port->cap->dr_set) { - dev_dbg(dev, "data role swapping not supported\n"); - return -EOPNOTSUPP; - } - - ret = sysfs_match_string(typec_data_roles, buf); - if (ret < 0) - return ret; - - mutex_lock(&port->port_type_lock); - if (port->port_type != TYPEC_PORT_DRP) { - dev_dbg(dev, "port type fixed at \"%s\"", - typec_port_types[port->port_type]); - ret = -EOPNOTSUPP; - goto unlock_and_ret; - } - - ret = port->cap->dr_set(port->cap, ret); - if (ret) - goto unlock_and_ret; - - ret = size; -unlock_and_ret: - mutex_unlock(&port->port_type_lock); - return ret; -} - -static ssize_t data_role_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct typec_port *port = to_typec_port(dev); - - if (port->cap->type == TYPEC_PORT_DRP) - return sprintf(buf, "%s\n", port->data_role == TYPEC_HOST ? - "[host] device" : "host [device]"); - - return sprintf(buf, "[%s]\n", typec_data_roles[port->data_role]); -} -static DEVICE_ATTR_RW(data_role); - -static ssize_t power_role_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - struct typec_port *port = to_typec_port(dev); - int ret; - - if (!port->cap->pd_revision) { - dev_dbg(dev, "USB Power Delivery not supported\n"); - return -EOPNOTSUPP; - } - - if (!port->cap->pr_set) { - dev_dbg(dev, "power role swapping not supported\n"); - return -EOPNOTSUPP; - } - - if (port->pwr_opmode != TYPEC_PWR_MODE_PD) { - dev_dbg(dev, "partner unable to swap power role\n"); - return -EIO; - } - - ret = sysfs_match_string(typec_roles, buf); - if (ret < 0) - return ret; - - mutex_lock(&port->port_type_lock); - if (port->port_type != TYPEC_PORT_DRP) { - dev_dbg(dev, "port type fixed at \"%s\"", - typec_port_types[port->port_type]); - ret = -EOPNOTSUPP; - goto unlock_and_ret; - } - - ret = port->cap->pr_set(port->cap, ret); - if (ret) - goto unlock_and_ret; - - ret = size; -unlock_and_ret: - mutex_unlock(&port->port_type_lock); - return ret; -} - -static ssize_t power_role_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct typec_port *port = to_typec_port(dev); - - if (port->cap->type == TYPEC_PORT_DRP) - return sprintf(buf, "%s\n", port->pwr_role == TYPEC_SOURCE ? - "[source] sink" : "source [sink]"); - - return sprintf(buf, "[%s]\n", typec_roles[port->pwr_role]); -} -static DEVICE_ATTR_RW(power_role); - -static ssize_t -port_type_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t size) -{ - struct typec_port *port = to_typec_port(dev); - int ret; - enum typec_port_type type; - - if (!port->cap->port_type_set || port->cap->type != TYPEC_PORT_DRP) { - dev_dbg(dev, "changing port type not supported\n"); - return -EOPNOTSUPP; - } - - ret = sysfs_match_string(typec_port_types, buf); - if (ret < 0) - return ret; - - type = ret; - mutex_lock(&port->port_type_lock); - - if (port->port_type == type) { - ret = size; - goto unlock_and_ret; - } - - ret = port->cap->port_type_set(port->cap, type); - if (ret) - goto unlock_and_ret; - - port->port_type = type; - ret = size; - -unlock_and_ret: - mutex_unlock(&port->port_type_lock); - return ret; -} - -static ssize_t -port_type_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct typec_port *port = to_typec_port(dev); - - if (port->cap->type == TYPEC_PORT_DRP) - return sprintf(buf, "%s\n", - typec_port_types_drp[port->port_type]); - - return sprintf(buf, "[%s]\n", typec_port_types[port->cap->type]); -} -static DEVICE_ATTR_RW(port_type); - -static const char * const typec_pwr_opmodes[] = { - [TYPEC_PWR_MODE_USB] = "default", - [TYPEC_PWR_MODE_1_5A] = "1.5A", - [TYPEC_PWR_MODE_3_0A] = "3.0A", - [TYPEC_PWR_MODE_PD] = "usb_power_delivery", -}; - -static ssize_t power_operation_mode_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct typec_port *port = to_typec_port(dev); - - return sprintf(buf, "%s\n", typec_pwr_opmodes[port->pwr_opmode]); -} -static DEVICE_ATTR_RO(power_operation_mode); - -static ssize_t vconn_source_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - struct typec_port *port = to_typec_port(dev); - bool source; - int ret; - - if (!port->cap->pd_revision) { - dev_dbg(dev, "VCONN swap depends on USB Power Delivery\n"); - return -EOPNOTSUPP; - } - - if (!port->cap->vconn_set) { - dev_dbg(dev, "VCONN swapping not supported\n"); - return -EOPNOTSUPP; - } - - ret = kstrtobool(buf, &source); - if (ret) - return ret; - - ret = port->cap->vconn_set(port->cap, (enum typec_role)source); - if (ret) - return ret; - - return size; -} - -static ssize_t vconn_source_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct typec_port *port = to_typec_port(dev); - - return sprintf(buf, "%s\n", - port->vconn_role == TYPEC_SOURCE ? "yes" : "no"); -} -static DEVICE_ATTR_RW(vconn_source); - -static ssize_t supported_accessory_modes_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct typec_port *port = to_typec_port(dev); - ssize_t ret = 0; - int i; - - for (i = 0; i < ARRAY_SIZE(port->cap->accessory); i++) { - if (port->cap->accessory[i]) - ret += sprintf(buf + ret, "%s ", - typec_accessory_modes[port->cap->accessory[i]]); - } - - if (!ret) - return sprintf(buf, "none\n"); - - buf[ret - 1] = '\n'; - - return ret; -} -static DEVICE_ATTR_RO(supported_accessory_modes); - -static ssize_t usb_typec_revision_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct typec_port *port = to_typec_port(dev); - u16 rev = port->cap->revision; - - return sprintf(buf, "%d.%d\n", (rev >> 8) & 0xff, (rev >> 4) & 0xf); -} -static DEVICE_ATTR_RO(usb_typec_revision); - -static ssize_t usb_power_delivery_revision_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct typec_port *p = to_typec_port(dev); - - return sprintf(buf, "%d\n", (p->cap->pd_revision >> 8) & 0xff); -} -static DEVICE_ATTR_RO(usb_power_delivery_revision); - -static struct attribute *typec_attrs[] = { - &dev_attr_data_role.attr, - &dev_attr_power_operation_mode.attr, - &dev_attr_power_role.attr, - &dev_attr_preferred_role.attr, - &dev_attr_supported_accessory_modes.attr, - &dev_attr_usb_power_delivery_revision.attr, - &dev_attr_usb_typec_revision.attr, - &dev_attr_vconn_source.attr, - &dev_attr_port_type.attr, - NULL, -}; -ATTRIBUTE_GROUPS(typec); - -static int typec_uevent(struct device *dev, struct kobj_uevent_env *env) -{ - int ret; - - ret = add_uevent_var(env, "TYPEC_PORT=%s", dev_name(dev)); - if (ret) - dev_err(dev, "failed to add uevent TYPEC_PORT\n"); - - return ret; -} - -static void typec_release(struct device *dev) -{ - struct typec_port *port = to_typec_port(dev); - - ida_simple_remove(&typec_index_ida, port->id); - kfree(port); -} - -static const struct device_type typec_port_dev_type = { - .name = "typec_port", - .groups = typec_groups, - .uevent = typec_uevent, - .release = typec_release, -}; - -/* --------------------------------------- */ -/* Driver callbacks to report role updates */ - -/** - * typec_set_data_role - Report data role change - * @port: The USB Type-C Port where the role was changed - * @role: The new data role - * - * This routine is used by the port drivers to report data role changes. - */ -void typec_set_data_role(struct typec_port *port, enum typec_data_role role) -{ - if (port->data_role == role) - return; - - port->data_role = role; - sysfs_notify(&port->dev.kobj, NULL, "data_role"); - kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); -} -EXPORT_SYMBOL_GPL(typec_set_data_role); - -/** - * typec_set_pwr_role - Report power role change - * @port: The USB Type-C Port where the role was changed - * @role: The new data role - * - * This routine is used by the port drivers to report power role changes. - */ -void typec_set_pwr_role(struct typec_port *port, enum typec_role role) -{ - if (port->pwr_role == role) - return; - - port->pwr_role = role; - sysfs_notify(&port->dev.kobj, NULL, "power_role"); - kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); -} -EXPORT_SYMBOL_GPL(typec_set_pwr_role); - -/** - * typec_set_pwr_role - Report VCONN source change - * @port: The USB Type-C Port which VCONN role changed - * @role: Source when @port is sourcing VCONN, or Sink when it's not - * - * This routine is used by the port drivers to report if the VCONN source is - * changes. - */ -void typec_set_vconn_role(struct typec_port *port, enum typec_role role) -{ - if (port->vconn_role == role) - return; - - port->vconn_role = role; - sysfs_notify(&port->dev.kobj, NULL, "vconn_source"); - kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); -} -EXPORT_SYMBOL_GPL(typec_set_vconn_role); - -static int partner_match(struct device *dev, void *data) -{ - return is_typec_partner(dev); -} - -/** - * typec_set_pwr_opmode - Report changed power operation mode - * @port: The USB Type-C Port where the mode was changed - * @opmode: New power operation mode - * - * This routine is used by the port drivers to report changed power operation - * mode in @port. The modes are USB (default), 1.5A, 3.0A as defined in USB - * Type-C specification, and "USB Power Delivery" when the power levels are - * negotiated with methods defined in USB Power Delivery specification. - */ -void typec_set_pwr_opmode(struct typec_port *port, - enum typec_pwr_opmode opmode) -{ - struct device *partner_dev; - - if (port->pwr_opmode == opmode) - return; - - port->pwr_opmode = opmode; - sysfs_notify(&port->dev.kobj, NULL, "power_operation_mode"); - kobject_uevent(&port->dev.kobj, KOBJ_CHANGE); - - partner_dev = device_find_child(&port->dev, NULL, partner_match); - if (partner_dev) { - struct typec_partner *partner = to_typec_partner(partner_dev); - - if (opmode == TYPEC_PWR_MODE_PD && !partner->usb_pd) { - partner->usb_pd = 1; - sysfs_notify(&partner_dev->kobj, NULL, - "supports_usb_power_delivery"); - } - put_device(partner_dev); - } -} -EXPORT_SYMBOL_GPL(typec_set_pwr_opmode); - -/* --------------------------------------- */ - -/** - * typec_port_register_altmode - Register USB Type-C Port Alternate Mode - * @port: USB Type-C Port that supports the alternate mode - * @desc: Description of the alternate mode - * - * This routine is used to register an alternate mode that @port is capable of - * supporting. - * - * Returns handle to the alternate mode on success or ERR_PTR on failure. - */ -struct typec_altmode * -typec_port_register_altmode(struct typec_port *port, - const struct typec_altmode_desc *desc) -{ - return typec_register_altmode(&port->dev, desc); -} -EXPORT_SYMBOL_GPL(typec_port_register_altmode); - -/** - * typec_register_port - Register a USB Type-C Port - * @parent: Parent device - * @cap: Description of the port - * - * Registers a device for USB Type-C Port described in @cap. - * - * Returns handle to the port on success or ERR_PTR on failure. - */ -struct typec_port *typec_register_port(struct device *parent, - const struct typec_capability *cap) -{ - struct typec_port *port; - int role; - int ret; - int id; - - port = kzalloc(sizeof(*port), GFP_KERNEL); - if (!port) - return ERR_PTR(-ENOMEM); - - id = ida_simple_get(&typec_index_ida, 0, 0, GFP_KERNEL); - if (id < 0) { - kfree(port); - return ERR_PTR(id); - } - - if (cap->type == TYPEC_PORT_DFP) - role = TYPEC_SOURCE; - else if (cap->type == TYPEC_PORT_UFP) - role = TYPEC_SINK; - else - role = cap->prefer_role; - - if (role == TYPEC_SOURCE) { - port->data_role = TYPEC_HOST; - port->pwr_role = TYPEC_SOURCE; - port->vconn_role = TYPEC_SOURCE; - } else { - port->data_role = TYPEC_DEVICE; - port->pwr_role = TYPEC_SINK; - port->vconn_role = TYPEC_SINK; - } - - port->id = id; - port->cap = cap; - port->port_type = cap->type; - mutex_init(&port->port_type_lock); - port->prefer_role = cap->prefer_role; - - port->dev.class = typec_class; - port->dev.parent = parent; - port->dev.fwnode = cap->fwnode; - port->dev.type = &typec_port_dev_type; - dev_set_name(&port->dev, "port%d", id); - - ret = device_register(&port->dev); - if (ret) { - dev_err(parent, "failed to register port (%d)\n", ret); - put_device(&port->dev); - return ERR_PTR(ret); - } - - return port; -} -EXPORT_SYMBOL_GPL(typec_register_port); - -/** - * typec_unregister_port - Unregister a USB Type-C Port - * @port: The port to be unregistered - * - * Unregister device created with typec_register_port(). - */ -void typec_unregister_port(struct typec_port *port) -{ - if (!IS_ERR_OR_NULL(port)) - device_unregister(&port->dev); -} -EXPORT_SYMBOL_GPL(typec_unregister_port); - -static int __init typec_init(void) -{ - typec_class = class_create(THIS_MODULE, "typec"); - return PTR_ERR_OR_ZERO(typec_class); -} -subsys_initcall(typec_init); - -static void __exit typec_exit(void) -{ - class_destroy(typec_class); - ida_destroy(&typec_index_ida); -} -module_exit(typec_exit); - -MODULE_AUTHOR("Heikki Krogerus "); -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("USB Type-C Connector Class"); diff --git a/include/linux/usb/typec.h b/include/linux/usb/typec.h index 0d44ce6af08f..2408e5c2ed91 100644 --- a/include/linux/usb/typec.h +++ b/include/linux/usb/typec.h @@ -60,6 +60,12 @@ enum typec_accessory { #define TYPEC_MAX_ACCESSORY 3 +enum typec_orientation { + TYPEC_ORIENTATION_NONE, + TYPEC_ORIENTATION_NORMAL, + TYPEC_ORIENTATION_REVERSE, +}; + /* * struct usb_pd_identity - USB Power Delivery identity data * @id_header: ID Header VDO @@ -185,6 +191,8 @@ struct typec_partner_desc { * @pd_revision: USB Power Delivery Specification revision if supported * @prefer_role: Initial role preference * @accessory: Supported Accessory Modes + * @sw: Cable plug orientation switch + * @mux: Multiplexer switch for Alternate/Accessory Modes * @fwnode: Optional fwnode of the port * @try_role: Set data role preference for DRP port * @dr_set: Set Data Role @@ -202,6 +210,8 @@ struct typec_capability { int prefer_role; enum typec_accessory accessory[TYPEC_MAX_ACCESSORY]; + struct typec_switch *sw; + struct typec_mux *mux; struct fwnode_handle *fwnode; int (*try_role)(const struct typec_capability *, @@ -245,4 +255,8 @@ void typec_set_pwr_role(struct typec_port *port, enum typec_role role); void typec_set_vconn_role(struct typec_port *port, enum typec_role role); void typec_set_pwr_opmode(struct typec_port *port, enum typec_pwr_opmode mode); +int typec_set_orientation(struct typec_port *port, + enum typec_orientation orientation); +int typec_set_mode(struct typec_port *port, int mode); + #endif /* __LINUX_USB_TYPEC_H */ diff --git a/include/linux/usb/typec_mux.h b/include/linux/usb/typec_mux.h new file mode 100644 index 000000000000..12c1b057834b --- /dev/null +++ b/include/linux/usb/typec_mux.h @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __USB_TYPEC_MUX +#define __USB_TYPEC_MUX + +#include +#include + +struct device; + +/** + * struct typec_switch - USB Type-C cable orientation switch + * @dev: Switch device + * @entry: List entry + * @set: Callback to the driver for setting the orientation + * + * USB Type-C pin flipper switch routing the correct data pairs from the + * connector to the USB controller depending on the orientation of the cable + * plug. + */ +struct typec_switch { + struct device *dev; + struct list_head entry; + + int (*set)(struct typec_switch *sw, enum typec_orientation orientation); +}; + +/** + * struct typec_switch - USB Type-C connector pin mux + * @dev: Mux device + * @entry: List entry + * @set: Callback to the driver for setting the state of the mux + * + * Pin Multiplexer/DeMultiplexer switch routing the USB Type-C connector pins to + * different components depending on the requested mode of operation. Used with + * Accessory/Alternate modes. + */ +struct typec_mux { + struct device *dev; + struct list_head entry; + + int (*set)(struct typec_mux *mux, int state); +}; + +struct typec_switch *typec_switch_get(struct device *dev); +void typec_switch_put(struct typec_switch *sw); +int typec_switch_register(struct typec_switch *sw); +void typec_switch_unregister(struct typec_switch *sw); + +struct typec_mux *typec_mux_get(struct device *dev); +void typec_mux_put(struct typec_mux *mux); +int typec_mux_register(struct typec_mux *mux); +void typec_mux_unregister(struct typec_mux *mux); + +#endif /* __USB_TYPEC_MUX */ -- cgit v1.2.3 From fde0aa6c175a4d8aa19e82b86ae0f9278bc8563b Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Tue, 20 Mar 2018 15:57:04 +0300 Subject: usb: common: Small class for USB role switches USB role switch is a device that can be used to choose the data role for USB connector. With dual-role capable USB controllers, the controller itself will be the switch, but on some platforms the USB host and device controllers are separate IPs and there is a mux between them and the connector. On those platforms the mux driver will need to register the switch. With USB Type-C connectors, the host-to-device relationship is negotiated over the Configuration Channel (CC). That means the USB Type-C drivers need to be in control of the role switch. The class provides a simple API for the USB Type-C drivers for the control. For other types of USB connectors (mainly microAB) the class provides user space control via sysfs attribute file that can be used to request role swapping from the switch. Reviewed-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-class-usb_role | 21 ++ drivers/usb/Kconfig | 3 + drivers/usb/common/Makefile | 1 + drivers/usb/common/roles.c | 305 +++++++++++++++++++++++++ include/linux/usb/role.h | 53 +++++ 5 files changed, 383 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-class-usb_role create mode 100644 drivers/usb/common/roles.c create mode 100644 include/linux/usb/role.h (limited to 'include/linux') diff --git a/Documentation/ABI/testing/sysfs-class-usb_role b/Documentation/ABI/testing/sysfs-class-usb_role new file mode 100644 index 000000000000..3b810a425a52 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-usb_role @@ -0,0 +1,21 @@ +What: /sys/class/usb_role/ +Date: Jan 2018 +Contact: Heikki Krogerus +Description: + Place in sysfs for USB Role Switches. USB Role Switch is a + device that can select the data role (host or device) for USB + port. + +What: /sys/class/usb_role//role +Date: Jan 2018 +Contact: Heikki Krogerus +Description: + The current role of the switch. This attribute can be used for + requesting role swapping with non-USB Type-C ports. With USB + Type-C ports, the ABI defined for USB Type-C connector class + must be used. + + Valid values: + - none + - host + - device diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 148f3ee70286..f278958e04ca 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -203,4 +203,7 @@ config USB_ULPI_BUS To compile this driver as a module, choose M here: the module will be called ulpi. +config USB_ROLE_SWITCH + tristate + endif # USB_SUPPORT diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile index 0a7c45e85481..fb4d5ef4165c 100644 --- a/drivers/usb/common/Makefile +++ b/drivers/usb/common/Makefile @@ -9,3 +9,4 @@ usb-common-$(CONFIG_USB_LED_TRIG) += led.o obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o obj-$(CONFIG_USB_ULPI_BUS) += ulpi.o +obj-$(CONFIG_USB_ROLE_SWITCH) += roles.o diff --git a/drivers/usb/common/roles.c b/drivers/usb/common/roles.c new file mode 100644 index 000000000000..15cc76e22123 --- /dev/null +++ b/drivers/usb/common/roles.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * USB Role Switch Support + * + * Copyright (C) 2018 Intel Corporation + * Author: Heikki Krogerus + * Hans de Goede + */ + +#include +#include +#include +#include +#include + +static struct class *role_class; + +struct usb_role_switch { + struct device dev; + struct mutex lock; /* device lock*/ + enum usb_role role; + + /* From descriptor */ + struct device *usb2_port; + struct device *usb3_port; + struct device *udc; + usb_role_switch_set_t set; + usb_role_switch_get_t get; + bool allow_userspace_control; +}; + +#define to_role_switch(d) container_of(d, struct usb_role_switch, dev) + +/** + * usb_role_switch_set_role - Set USB role for a switch + * @sw: USB role switch + * @role: USB role to be switched to + * + * Set USB role @role for @sw. + */ +int usb_role_switch_set_role(struct usb_role_switch *sw, enum usb_role role) +{ + int ret; + + if (IS_ERR_OR_NULL(sw)) + return 0; + + mutex_lock(&sw->lock); + + ret = sw->set(sw->dev.parent, role); + if (!ret) + sw->role = role; + + mutex_unlock(&sw->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(usb_role_switch_set_role); + +/** + * usb_role_switch_get_role - Get the USB role for a switch + * @sw: USB role switch + * + * Depending on the role-switch-driver this function returns either a cached + * value of the last set role, or reads back the actual value from the hardware. + */ +enum usb_role usb_role_switch_get_role(struct usb_role_switch *sw) +{ + enum usb_role role; + + if (IS_ERR_OR_NULL(sw)) + return USB_ROLE_NONE; + + mutex_lock(&sw->lock); + + if (sw->get) + role = sw->get(sw->dev.parent); + else + role = sw->role; + + mutex_unlock(&sw->lock); + + return role; +} +EXPORT_SYMBOL_GPL(usb_role_switch_get_role); + +static int __switch_match(struct device *dev, const void *name) +{ + return !strcmp((const char *)name, dev_name(dev)); +} + +static void *usb_role_switch_match(struct device_connection *con, int ep, + void *data) +{ + struct device *dev; + + dev = class_find_device(role_class, NULL, con->endpoint[ep], + __switch_match); + + return dev ? to_role_switch(dev) : ERR_PTR(-EPROBE_DEFER); +} + +/** + * usb_role_switch_get - Find USB role switch linked with the caller + * @dev: The caller device + * + * Finds and returns role switch linked with @dev. The reference count for the + * found switch is incremented. + */ +struct usb_role_switch *usb_role_switch_get(struct device *dev) +{ + return device_connection_find_match(dev, "usb-role-switch", NULL, + usb_role_switch_match); +} +EXPORT_SYMBOL_GPL(usb_role_switch_get); + +/** + * usb_role_switch_put - Release handle to a switch + * @sw: USB Role Switch + * + * Decrement reference count for @sw. + */ +void usb_role_switch_put(struct usb_role_switch *sw) +{ + if (!IS_ERR_OR_NULL(sw)) + put_device(&sw->dev); +} +EXPORT_SYMBOL_GPL(usb_role_switch_put); + +static umode_t +usb_role_switch_is_visible(struct kobject *kobj, struct attribute *attr, int n) +{ + struct device *dev = container_of(kobj, typeof(*dev), kobj); + struct usb_role_switch *sw = to_role_switch(dev); + + if (sw->allow_userspace_control) + return attr->mode; + + return 0; +} + +static const char * const usb_roles[] = { + [USB_ROLE_NONE] = "none", + [USB_ROLE_HOST] = "host", + [USB_ROLE_DEVICE] = "device", +}; + +static ssize_t +role_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct usb_role_switch *sw = to_role_switch(dev); + enum usb_role role = usb_role_switch_get_role(sw); + + return sprintf(buf, "%s\n", usb_roles[role]); +} + +static ssize_t role_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct usb_role_switch *sw = to_role_switch(dev); + int ret; + + ret = sysfs_match_string(usb_roles, buf); + if (ret < 0) { + bool res; + + /* Extra check if the user wants to disable the switch */ + ret = kstrtobool(buf, &res); + if (ret || res) + return -EINVAL; + } + + ret = usb_role_switch_set_role(sw, ret); + if (ret) + return ret; + + return size; +} +static DEVICE_ATTR_RW(role); + +static struct attribute *usb_role_switch_attrs[] = { + &dev_attr_role.attr, + NULL, +}; + +static const struct attribute_group usb_role_switch_group = { + .is_visible = usb_role_switch_is_visible, + .attrs = usb_role_switch_attrs, +}; + +static const struct attribute_group *usb_role_switch_groups[] = { + &usb_role_switch_group, + NULL, +}; + +static int +usb_role_switch_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + int ret; + + ret = add_uevent_var(env, "USB_ROLE_SWITCH=%s", dev_name(dev)); + if (ret) + dev_err(dev, "failed to add uevent USB_ROLE_SWITCH\n"); + + return ret; +} + +static void usb_role_switch_release(struct device *dev) +{ + struct usb_role_switch *sw = to_role_switch(dev); + + kfree(sw); +} + +static const struct device_type usb_role_dev_type = { + .name = "usb_role_switch", + .groups = usb_role_switch_groups, + .uevent = usb_role_switch_uevent, + .release = usb_role_switch_release, +}; + +/** + * usb_role_switch_register - Register USB Role Switch + * @parent: Parent device for the switch + * @desc: Description of the switch + * + * USB Role Switch is a device capable or choosing the role for USB connector. + * On platforms where the USB controller is dual-role capable, the controller + * driver will need to register the switch. On platforms where the USB host and + * USB device controllers behind the connector are separate, there will be a + * mux, and the driver for that mux will need to register the switch. + * + * Returns handle to a new role switch or ERR_PTR. The content of @desc is + * copied. + */ +struct usb_role_switch * +usb_role_switch_register(struct device *parent, + const struct usb_role_switch_desc *desc) +{ + struct usb_role_switch *sw; + int ret; + + if (!desc || !desc->set) + return ERR_PTR(-EINVAL); + + sw = kzalloc(sizeof(*sw), GFP_KERNEL); + if (!sw) + return ERR_PTR(-ENOMEM); + + mutex_init(&sw->lock); + + sw->allow_userspace_control = desc->allow_userspace_control; + sw->usb2_port = desc->usb2_port; + sw->usb3_port = desc->usb3_port; + sw->udc = desc->udc; + sw->set = desc->set; + sw->get = desc->get; + + sw->dev.parent = parent; + sw->dev.class = role_class; + sw->dev.type = &usb_role_dev_type; + dev_set_name(&sw->dev, "%s-role-switch", dev_name(parent)); + + ret = device_register(&sw->dev); + if (ret) { + put_device(&sw->dev); + return ERR_PTR(ret); + } + + /* TODO: Symlinks for the host port and the device controller. */ + + return sw; +} +EXPORT_SYMBOL_GPL(usb_role_switch_register); + +/** + * usb_role_switch_unregister - Unregsiter USB Role Switch + * @sw: USB Role Switch + * + * Unregister switch that was registered with usb_role_switch_register(). + */ +void usb_role_switch_unregister(struct usb_role_switch *sw) +{ + if (!IS_ERR_OR_NULL(sw)) + device_unregister(&sw->dev); +} +EXPORT_SYMBOL_GPL(usb_role_switch_unregister); + +static int __init usb_roles_init(void) +{ + role_class = class_create(THIS_MODULE, "usb_role"); + return PTR_ERR_OR_ZERO(role_class); +} +subsys_initcall(usb_roles_init); + +static void __exit usb_roles_exit(void) +{ + class_destroy(role_class); +} +module_exit(usb_roles_exit); + +MODULE_AUTHOR("Heikki Krogerus "); +MODULE_AUTHOR("Hans de Goede "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("USB Role Class"); diff --git a/include/linux/usb/role.h b/include/linux/usb/role.h new file mode 100644 index 000000000000..edc51be4a77c --- /dev/null +++ b/include/linux/usb/role.h @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __LINUX_USB_ROLE_H +#define __LINUX_USB_ROLE_H + +#include + +struct usb_role_switch; + +enum usb_role { + USB_ROLE_NONE, + USB_ROLE_HOST, + USB_ROLE_DEVICE, +}; + +typedef int (*usb_role_switch_set_t)(struct device *dev, enum usb_role role); +typedef enum usb_role (*usb_role_switch_get_t)(struct device *dev); + +/** + * struct usb_role_switch_desc - USB Role Switch Descriptor + * @usb2_port: Optional reference to the host controller port device (USB2) + * @usb3_port: Optional reference to the host controller port device (USB3) + * @udc: Optional reference to the peripheral controller device + * @set: Callback for setting the role + * @get: Callback for getting the role (optional) + * @allow_userspace_control: If true userspace may change the role through sysfs + * + * @usb2_port and @usb3_port will point to the USB host port and @udc to the USB + * device controller behind the USB connector with the role switch. If + * @usb2_port, @usb3_port and @udc are included in the description, the + * reference count for them should be incremented by the caller of + * usb_role_switch_register() before registering the switch. + */ +struct usb_role_switch_desc { + struct device *usb2_port; + struct device *usb3_port; + struct device *udc; + usb_role_switch_set_t set; + usb_role_switch_get_t get; + bool allow_userspace_control; +}; + +int usb_role_switch_set_role(struct usb_role_switch *sw, enum usb_role role); +enum usb_role usb_role_switch_get_role(struct usb_role_switch *sw); +struct usb_role_switch *usb_role_switch_get(struct device *dev); +void usb_role_switch_put(struct usb_role_switch *sw); + +struct usb_role_switch * +usb_role_switch_register(struct device *parent, + const struct usb_role_switch_desc *desc); +void usb_role_switch_unregister(struct usb_role_switch *sw); + +#endif /* __LINUX_USB_ROLE_H */ -- cgit v1.2.3 From ceeb162500c3480b660a47d509db7955a7913271 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Tue, 20 Mar 2018 15:57:05 +0300 Subject: usb: typec: Separate the definitions for data and power roles USB Type-C specification v1.2 separated the power and data roles more clearly. Dual-Role-Data term was introduced, and the meaning of DRP was changed from "Dual-Role-Port" to "Dual-Role-Power". In order to allow the port drivers to describe the capabilities of the ports more clearly according to the newest specifications, introducing separate definitions for the data roles. Reviewed-by: Guenter Roeck Signed-off-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- drivers/usb/typec/class.c | 56 ++++++++++++++++++++++--------------- drivers/usb/typec/fusb302/fusb302.c | 1 + drivers/usb/typec/tcpm.c | 9 +++--- drivers/usb/typec/tps6598x.c | 26 +++++++++++------ drivers/usb/typec/typec_wcove.c | 1 + drivers/usb/typec/ucsi/ucsi.c | 13 +++++++-- include/linux/usb/tcpm.h | 1 + include/linux/usb/typec.h | 14 ++++++++-- 8 files changed, 80 insertions(+), 41 deletions(-) (limited to 'include/linux') diff --git a/drivers/usb/typec/class.c b/drivers/usb/typec/class.c index 2620a694704f..53df10df2f9d 100644 --- a/drivers/usb/typec/class.c +++ b/drivers/usb/typec/class.c @@ -282,10 +282,10 @@ typec_altmode_roles_show(struct device *dev, struct device_attribute *attr, ssize_t ret; switch (mode->roles) { - case TYPEC_PORT_DFP: + case TYPEC_PORT_SRC: ret = sprintf(buf, "source\n"); break; - case TYPEC_PORT_UFP: + case TYPEC_PORT_SNK: ret = sprintf(buf, "sink\n"); break; case TYPEC_PORT_DRP: @@ -797,14 +797,14 @@ static const char * const typec_data_roles[] = { }; static const char * const typec_port_types[] = { - [TYPEC_PORT_DFP] = "source", - [TYPEC_PORT_UFP] = "sink", + [TYPEC_PORT_SRC] = "source", + [TYPEC_PORT_SNK] = "sink", [TYPEC_PORT_DRP] = "dual", }; static const char * const typec_port_types_drp[] = { - [TYPEC_PORT_DFP] = "dual [source] sink", - [TYPEC_PORT_UFP] = "dual source [sink]", + [TYPEC_PORT_SRC] = "dual [source] sink", + [TYPEC_PORT_SNK] = "dual source [sink]", [TYPEC_PORT_DRP] = "[dual] source sink", }; @@ -875,9 +875,7 @@ static ssize_t data_role_store(struct device *dev, return ret; mutex_lock(&port->port_type_lock); - if (port->port_type != TYPEC_PORT_DRP) { - dev_dbg(dev, "port type fixed at \"%s\"", - typec_port_types[port->port_type]); + if (port->cap->data != TYPEC_PORT_DRD) { ret = -EOPNOTSUPP; goto unlock_and_ret; } @@ -897,7 +895,7 @@ static ssize_t data_role_show(struct device *dev, { struct typec_port *port = to_typec_port(dev); - if (port->cap->type == TYPEC_PORT_DRP) + if (port->cap->data == TYPEC_PORT_DRD) return sprintf(buf, "%s\n", port->data_role == TYPEC_HOST ? "[host] device" : "host [device]"); @@ -1328,7 +1326,6 @@ struct typec_port *typec_register_port(struct device *parent, const struct typec_capability *cap) { struct typec_port *port; - int role; int ret; int id; @@ -1354,21 +1351,36 @@ struct typec_port *typec_register_port(struct device *parent, goto err_mux; } - if (cap->type == TYPEC_PORT_DFP) - role = TYPEC_SOURCE; - else if (cap->type == TYPEC_PORT_UFP) - role = TYPEC_SINK; - else - role = cap->prefer_role; - - if (role == TYPEC_SOURCE) { - port->data_role = TYPEC_HOST; + switch (cap->type) { + case TYPEC_PORT_SRC: port->pwr_role = TYPEC_SOURCE; port->vconn_role = TYPEC_SOURCE; - } else { - port->data_role = TYPEC_DEVICE; + break; + case TYPEC_PORT_SNK: port->pwr_role = TYPEC_SINK; port->vconn_role = TYPEC_SINK; + break; + case TYPEC_PORT_DRP: + if (cap->prefer_role != TYPEC_NO_PREFERRED_ROLE) + port->pwr_role = cap->prefer_role; + else + port->pwr_role = TYPEC_SINK; + break; + } + + switch (cap->data) { + case TYPEC_PORT_DFP: + port->data_role = TYPEC_HOST; + break; + case TYPEC_PORT_UFP: + port->data_role = TYPEC_DEVICE; + break; + case TYPEC_PORT_DRD: + if (cap->prefer_role == TYPEC_SOURCE) + port->data_role = TYPEC_HOST; + else + port->data_role = TYPEC_DEVICE; + break; } port->id = id; diff --git a/drivers/usb/typec/fusb302/fusb302.c b/drivers/usb/typec/fusb302/fusb302.c index 06794c06330f..82bf7c0ed53c 100644 --- a/drivers/usb/typec/fusb302/fusb302.c +++ b/drivers/usb/typec/fusb302/fusb302.c @@ -1219,6 +1219,7 @@ static const struct tcpc_config fusb302_tcpc_config = { .max_snk_mw = 15000, .operating_snk_mw = 2500, .type = TYPEC_PORT_DRP, + .data = TYPEC_PORT_DRD, .default_role = TYPEC_SINK, .alt_modes = NULL, }; diff --git a/drivers/usb/typec/tcpm.c b/drivers/usb/typec/tcpm.c index 4c0fc5493d58..62e710bb6367 100644 --- a/drivers/usb/typec/tcpm.c +++ b/drivers/usb/typec/tcpm.c @@ -345,7 +345,7 @@ static enum tcpm_state tcpm_default_state(struct tcpm_port *port) else if (port->tcpc->config->default_role == TYPEC_SINK) return SNK_UNATTACHED; /* Fall through to return SRC_UNATTACHED */ - } else if (port->port_type == TYPEC_PORT_UFP) { + } else if (port->port_type == TYPEC_PORT_SNK) { return SNK_UNATTACHED; } return SRC_UNATTACHED; @@ -2179,7 +2179,7 @@ static inline enum tcpm_state unattached_state(struct tcpm_port *port) return SRC_UNATTACHED; else return SNK_UNATTACHED; - } else if (port->port_type == TYPEC_PORT_DFP) { + } else if (port->port_type == TYPEC_PORT_SRC) { return SRC_UNATTACHED; } @@ -3469,11 +3469,11 @@ static int tcpm_port_type_set(const struct typec_capability *cap, if (!port->connected) { tcpm_set_state(port, PORT_RESET, 0); - } else if (type == TYPEC_PORT_UFP) { + } else if (type == TYPEC_PORT_SNK) { if (!(port->pwr_role == TYPEC_SINK && port->data_role == TYPEC_DEVICE)) tcpm_set_state(port, PORT_RESET, 0); - } else if (type == TYPEC_PORT_DFP) { + } else if (type == TYPEC_PORT_SRC) { if (!(port->pwr_role == TYPEC_SOURCE && port->data_role == TYPEC_HOST)) tcpm_set_state(port, PORT_RESET, 0); @@ -3641,6 +3641,7 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) port->typec_caps.prefer_role = tcpc->config->default_role; port->typec_caps.type = tcpc->config->type; + port->typec_caps.data = tcpc->config->data; port->typec_caps.revision = 0x0120; /* Type-C spec release 1.2 */ port->typec_caps.pd_revision = 0x0200; /* USB-PD spec release 2.0 */ port->typec_caps.dr_set = tcpm_dr_set; diff --git a/drivers/usb/typec/tps6598x.c b/drivers/usb/typec/tps6598x.c index 37a15c14a6c6..8b8406867c02 100644 --- a/drivers/usb/typec/tps6598x.c +++ b/drivers/usb/typec/tps6598x.c @@ -393,31 +393,39 @@ static int tps6598x_probe(struct i2c_client *client) if (ret < 0) return ret; + tps->typec_cap.revision = USB_TYPEC_REV_1_2; + tps->typec_cap.pd_revision = 0x200; + tps->typec_cap.prefer_role = TYPEC_NO_PREFERRED_ROLE; + tps->typec_cap.pr_set = tps6598x_pr_set; + tps->typec_cap.dr_set = tps6598x_dr_set; + switch (TPS_SYSCONF_PORTINFO(conf)) { case TPS_PORTINFO_SINK_ACCESSORY: case TPS_PORTINFO_SINK: - tps->typec_cap.type = TYPEC_PORT_UFP; + tps->typec_cap.type = TYPEC_PORT_SNK; + tps->typec_cap.data = TYPEC_PORT_UFP; break; case TPS_PORTINFO_DRP_UFP_DRD: case TPS_PORTINFO_DRP_DFP_DRD: - tps->typec_cap.dr_set = tps6598x_dr_set; - /* fall through */ + tps->typec_cap.type = TYPEC_PORT_DRP; + tps->typec_cap.data = TYPEC_PORT_DRD; + break; case TPS_PORTINFO_DRP_UFP: + tps->typec_cap.type = TYPEC_PORT_DRP; + tps->typec_cap.data = TYPEC_PORT_UFP; + break; case TPS_PORTINFO_DRP_DFP: - tps->typec_cap.pr_set = tps6598x_pr_set; tps->typec_cap.type = TYPEC_PORT_DRP; + tps->typec_cap.data = TYPEC_PORT_DFP; break; case TPS_PORTINFO_SOURCE: - tps->typec_cap.type = TYPEC_PORT_DFP; + tps->typec_cap.type = TYPEC_PORT_SRC; + tps->typec_cap.data = TYPEC_PORT_DFP; break; default: return -ENODEV; } - tps->typec_cap.revision = USB_TYPEC_REV_1_2; - tps->typec_cap.pd_revision = 0x200; - tps->typec_cap.prefer_role = TYPEC_NO_PREFERRED_ROLE; - tps->port = typec_register_port(&client->dev, &tps->typec_cap); if (IS_ERR(tps->port)) return PTR_ERR(tps->port); diff --git a/drivers/usb/typec/typec_wcove.c b/drivers/usb/typec/typec_wcove.c index 2e990e0d917d..19cca7f1b2c5 100644 --- a/drivers/usb/typec/typec_wcove.c +++ b/drivers/usb/typec/typec_wcove.c @@ -572,6 +572,7 @@ static struct tcpc_config wcove_typec_config = { .operating_snk_mw = 15000, .type = TYPEC_PORT_DRP, + .data = TYPEC_PORT_DRD, .default_role = TYPEC_SINK, }; diff --git a/drivers/usb/typec/ucsi/ucsi.c b/drivers/usb/typec/ucsi/ucsi.c index 69d544cfcd45..bf0977fbd100 100644 --- a/drivers/usb/typec/ucsi/ucsi.c +++ b/drivers/usb/typec/ucsi/ucsi.c @@ -592,11 +592,18 @@ static int ucsi_register_port(struct ucsi *ucsi, int index) return ret; if (con->cap.op_mode & UCSI_CONCAP_OPMODE_DRP) - cap->type = TYPEC_PORT_DRP; + cap->data = TYPEC_PORT_DRD; else if (con->cap.op_mode & UCSI_CONCAP_OPMODE_DFP) - cap->type = TYPEC_PORT_DFP; + cap->data = TYPEC_PORT_DFP; else if (con->cap.op_mode & UCSI_CONCAP_OPMODE_UFP) - cap->type = TYPEC_PORT_UFP; + cap->data = TYPEC_PORT_UFP; + + if (con->cap.provider && con->cap.consumer) + cap->type = TYPEC_PORT_DRP; + else if (con->cap.provider) + cap->type = TYPEC_PORT_SRC; + else if (con->cap.consumer) + cap->type = TYPEC_PORT_SNK; cap->revision = ucsi->cap.typec_version; cap->pd_revision = ucsi->cap.pd_version; diff --git a/include/linux/usb/tcpm.h b/include/linux/usb/tcpm.h index ca1c0b57f03f..5a5e1d8c5b65 100644 --- a/include/linux/usb/tcpm.h +++ b/include/linux/usb/tcpm.h @@ -91,6 +91,7 @@ struct tcpc_config { unsigned int operating_snk_mw; enum typec_port_type type; + enum typec_port_data data; enum typec_role default_role; bool try_role_hw; /* try.{src,snk} implemented in hardware */ diff --git a/include/linux/usb/typec.h b/include/linux/usb/typec.h index 2408e5c2ed91..672b39bb0adc 100644 --- a/include/linux/usb/typec.h +++ b/include/linux/usb/typec.h @@ -22,9 +22,15 @@ struct typec_port; struct fwnode_handle; enum typec_port_type { + TYPEC_PORT_SRC, + TYPEC_PORT_SNK, + TYPEC_PORT_DRP, +}; + +enum typec_port_data { TYPEC_PORT_DFP, TYPEC_PORT_UFP, - TYPEC_PORT_DRP, + TYPEC_PORT_DRD, }; enum typec_plug_type { @@ -186,10 +192,11 @@ struct typec_partner_desc { /* * struct typec_capability - USB Type-C Port Capabilities - * @role: DFP (Host-only), UFP (Device-only) or DRP (Dual Role) + * @type: Supported power role of the port + * @data: Supported data role of the port * @revision: USB Type-C Specification release. Binary coded decimal * @pd_revision: USB Power Delivery Specification revision if supported - * @prefer_role: Initial role preference + * @prefer_role: Initial role preference (DRP ports). * @accessory: Supported Accessory Modes * @sw: Cable plug orientation switch * @mux: Multiplexer switch for Alternate/Accessory Modes @@ -205,6 +212,7 @@ struct typec_partner_desc { */ struct typec_capability { enum typec_port_type type; + enum typec_port_data data; u16 revision; /* 0120H = "1.2" */ u16 pd_revision; /* 0300H = "3.0" */ int prefer_role; -- cgit v1.2.3 From c6962c29729cc64177f56a466766daa7de9f87ac Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 20 Mar 2018 15:57:06 +0300 Subject: usb: typec: tcpm: Set USB role switch to device mode when configured as such Setting the mux to MUX_NONE and the switch to USB_SWITCH_DISCONNECT when the data-role is device is not correct. Plenty of devices support operating as USB device through a (separate) USB device controller. We really need 2 different versions of USB_SWITCH_CONNECT, USB_SWITCH_CONNECT_HOST and USB_SWITCH_DEVICE. Rather then modifying the tcpc_usb_switch enum for this, simply remove it and switch to the usb_role enum which provides exactly this, this will save use needing to convert betweent the 2 enums when calling an usb-role-switch driver later. Besides switching to the usb_role type, this commit also actually sets the mux to TYPEC_MUX_USB and the switch to USB_ROLE_DEVICE instead of setting both to none when the data-role is device. This commit also makes tcpm_reset_port() call tcpm_mux_set(port, TYPEC_MUX_NONE, USB_ROLE_NONE) so that the mux and switch do _not_ stay in their last mode after a detach. Signed-off-by: Hans de Goede Reviewed-by: Guenter Roeck Reviewed-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- drivers/usb/typec/tcpm.c | 22 +++++++++++----------- include/linux/usb/tcpm.h | 8 ++------ 2 files changed, 13 insertions(+), 17 deletions(-) (limited to 'include/linux') diff --git a/drivers/usb/typec/tcpm.c b/drivers/usb/typec/tcpm.c index 62e710bb6367..2519b0d17f1f 100644 --- a/drivers/usb/typec/tcpm.c +++ b/drivers/usb/typec/tcpm.c @@ -604,15 +604,15 @@ void tcpm_pd_transmit_complete(struct tcpm_port *port, EXPORT_SYMBOL_GPL(tcpm_pd_transmit_complete); static int tcpm_mux_set(struct tcpm_port *port, enum tcpc_mux_mode mode, - enum tcpc_usb_switch config) + enum usb_role usb_role) { int ret = 0; - tcpm_log(port, "Requesting mux mode %d, config %d, polarity %d", - mode, config, port->polarity); + tcpm_log(port, "Requesting mux mode %d, usb-role %d, polarity %d", + mode, usb_role, port->polarity); if (port->tcpc->mux) - ret = port->tcpc->mux->set(port->tcpc->mux, mode, config, + ret = port->tcpc->mux->set(port->tcpc->mux, mode, usb_role, port->polarity); return ret; @@ -728,14 +728,15 @@ static int tcpm_set_attached_state(struct tcpm_port *port, bool attached) static int tcpm_set_roles(struct tcpm_port *port, bool attached, enum typec_role role, enum typec_data_role data) { + enum usb_role usb_role; int ret; if (data == TYPEC_HOST) - ret = tcpm_mux_set(port, TYPEC_MUX_USB, - TCPC_USB_SWITCH_CONNECT); + usb_role = USB_ROLE_HOST; else - ret = tcpm_mux_set(port, TYPEC_MUX_NONE, - TCPC_USB_SWITCH_DISCONNECT); + usb_role = USB_ROLE_DEVICE; + + ret = tcpm_mux_set(port, TYPEC_MUX_USB, usb_role); if (ret < 0) return ret; @@ -2028,7 +2029,7 @@ out_disable_vconn: out_disable_pd: port->tcpc->set_pd_rx(port->tcpc, false); out_disable_mux: - tcpm_mux_set(port, TYPEC_MUX_NONE, TCPC_USB_SWITCH_DISCONNECT); + tcpm_mux_set(port, TYPEC_MUX_NONE, USB_ROLE_NONE); return ret; } @@ -2072,6 +2073,7 @@ static void tcpm_reset_port(struct tcpm_port *port) tcpm_init_vconn(port); tcpm_set_current_limit(port, 0, 0); tcpm_set_polarity(port, TYPEC_POLARITY_CC1); + tcpm_mux_set(port, TYPEC_MUX_NONE, USB_ROLE_NONE); tcpm_set_attached_state(port, false); port->try_src_count = 0; port->try_snk_count = 0; @@ -2122,8 +2124,6 @@ static int tcpm_snk_attach(struct tcpm_port *port) static void tcpm_snk_detach(struct tcpm_port *port) { tcpm_detach(port); - - /* XXX: (Dis)connect SuperSpeed mux? */ } static int tcpm_acc_attach(struct tcpm_port *port) diff --git a/include/linux/usb/tcpm.h b/include/linux/usb/tcpm.h index 5a5e1d8c5b65..3e8bdaa5085a 100644 --- a/include/linux/usb/tcpm.h +++ b/include/linux/usb/tcpm.h @@ -16,6 +16,7 @@ #define __LINUX_USB_TCPM_H #include +#include #include #include "pd.h" @@ -98,11 +99,6 @@ struct tcpc_config { const struct typec_altmode_desc *alt_modes; }; -enum tcpc_usb_switch { - TCPC_USB_SWITCH_CONNECT, - TCPC_USB_SWITCH_DISCONNECT, -}; - /* Mux state attributes */ #define TCPC_MUX_USB_ENABLED BIT(0) /* USB enabled */ #define TCPC_MUX_DP_ENABLED BIT(1) /* DP enabled */ @@ -119,7 +115,7 @@ enum tcpc_mux_mode { struct tcpc_mux_dev { int (*set)(struct tcpc_mux_dev *dev, enum tcpc_mux_mode mux_mode, - enum tcpc_usb_switch usb_config, + enum usb_role usb_role, enum typec_cc_polarity polarity); bool dfp_only; void *priv_data; -- cgit v1.2.3 From 2000016c94b4f724cb5851486b9f9a94e8da32fc Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 20 Mar 2018 15:57:07 +0300 Subject: usb: typec: tcpm: Use new Type-C switch/mux and usb-role-switch functions Remove the unused (not implemented anywhere) tcpc_mux_dev abstraction and replace it with calling the new typec_set_orientation, usb_role_switch_set and typec_set_mode functions. Signed-off-by: Hans de Goede Reviewed-by: Guenter Roeck Reviewed-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Signed-off-by: Greg Kroah-Hartman --- drivers/usb/typec/Kconfig | 1 + drivers/usb/typec/fusb302/fusb302.c | 1 - drivers/usb/typec/tcpm.c | 46 ++++++++++++++++++++++++++++--------- include/linux/usb/tcpm.h | 10 -------- 4 files changed, 36 insertions(+), 22 deletions(-) (limited to 'include/linux') diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig index bcb2744c5977..a2a0684e7c82 100644 --- a/drivers/usb/typec/Kconfig +++ b/drivers/usb/typec/Kconfig @@ -48,6 +48,7 @@ if TYPEC config TYPEC_TCPM tristate "USB Type-C Port Controller Manager" depends on USB + select USB_ROLE_SWITCH help The Type-C Port Controller Manager provides a USB PD and USB Type-C state machine for use with Type-C Port Controllers. diff --git a/drivers/usb/typec/fusb302/fusb302.c b/drivers/usb/typec/fusb302/fusb302.c index 82bf7c0ed53c..703617129067 100644 --- a/drivers/usb/typec/fusb302/fusb302.c +++ b/drivers/usb/typec/fusb302/fusb302.c @@ -1239,7 +1239,6 @@ static void init_tcpc_dev(struct tcpc_dev *fusb302_tcpc_dev) fusb302_tcpc_dev->set_roles = tcpm_set_roles; fusb302_tcpc_dev->start_drp_toggling = tcpm_start_drp_toggling; fusb302_tcpc_dev->pd_transmit = tcpm_pd_transmit; - fusb302_tcpc_dev->mux = NULL; } static const char * const cc_polarity_name[] = { diff --git a/drivers/usb/typec/tcpm.c b/drivers/usb/typec/tcpm.c index 2519b0d17f1f..677d12138dbd 100644 --- a/drivers/usb/typec/tcpm.c +++ b/drivers/usb/typec/tcpm.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -176,6 +177,7 @@ struct tcpm_port { struct typec_port *typec_port; struct tcpc_dev *tcpc; + struct usb_role_switch *role_sw; enum typec_role vconn_role; enum typec_role pwr_role; @@ -604,18 +606,25 @@ void tcpm_pd_transmit_complete(struct tcpm_port *port, EXPORT_SYMBOL_GPL(tcpm_pd_transmit_complete); static int tcpm_mux_set(struct tcpm_port *port, enum tcpc_mux_mode mode, - enum usb_role usb_role) + enum usb_role usb_role, + enum typec_orientation orientation) { - int ret = 0; + int ret; - tcpm_log(port, "Requesting mux mode %d, usb-role %d, polarity %d", - mode, usb_role, port->polarity); + tcpm_log(port, "Requesting mux mode %d, usb-role %d, orientation %d", + mode, usb_role, orientation); - if (port->tcpc->mux) - ret = port->tcpc->mux->set(port->tcpc->mux, mode, usb_role, - port->polarity); + ret = typec_set_orientation(port->typec_port, orientation); + if (ret) + return ret; - return ret; + if (port->role_sw) { + ret = usb_role_switch_set_role(port->role_sw, usb_role); + if (ret) + return ret; + } + + return typec_set_mode(port->typec_port, mode); } static int tcpm_set_polarity(struct tcpm_port *port, @@ -728,15 +737,21 @@ static int tcpm_set_attached_state(struct tcpm_port *port, bool attached) static int tcpm_set_roles(struct tcpm_port *port, bool attached, enum typec_role role, enum typec_data_role data) { + enum typec_orientation orientation; enum usb_role usb_role; int ret; + if (port->polarity == TYPEC_POLARITY_CC1) + orientation = TYPEC_ORIENTATION_NORMAL; + else + orientation = TYPEC_ORIENTATION_REVERSE; + if (data == TYPEC_HOST) usb_role = USB_ROLE_HOST; else usb_role = USB_ROLE_DEVICE; - ret = tcpm_mux_set(port, TYPEC_MUX_USB, usb_role); + ret = tcpm_mux_set(port, TYPEC_MUX_USB, usb_role, orientation); if (ret < 0) return ret; @@ -2029,7 +2044,8 @@ out_disable_vconn: out_disable_pd: port->tcpc->set_pd_rx(port->tcpc, false); out_disable_mux: - tcpm_mux_set(port, TYPEC_MUX_NONE, USB_ROLE_NONE); + tcpm_mux_set(port, TYPEC_MUX_NONE, USB_ROLE_NONE, + TYPEC_ORIENTATION_NONE); return ret; } @@ -2073,7 +2089,8 @@ static void tcpm_reset_port(struct tcpm_port *port) tcpm_init_vconn(port); tcpm_set_current_limit(port, 0, 0); tcpm_set_polarity(port, TYPEC_POLARITY_CC1); - tcpm_mux_set(port, TYPEC_MUX_NONE, USB_ROLE_NONE); + tcpm_mux_set(port, TYPEC_MUX_NONE, USB_ROLE_NONE, + TYPEC_ORIENTATION_NONE); tcpm_set_attached_state(port, false); port->try_src_count = 0; port->try_snk_count = 0; @@ -3653,6 +3670,12 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) port->partner_desc.identity = &port->partner_ident; port->port_type = tcpc->config->type; + port->role_sw = usb_role_switch_get(port->dev); + if (IS_ERR(port->role_sw)) { + err = PTR_ERR(port->role_sw); + goto out_destroy_wq; + } + port->typec_port = typec_register_port(port->dev, &port->typec_caps); if (IS_ERR(port->typec_port)) { err = PTR_ERR(port->typec_port); @@ -3688,6 +3711,7 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) return port; out_destroy_wq: + usb_role_switch_put(port->role_sw); destroy_workqueue(port->wq); return ERR_PTR(err); } diff --git a/include/linux/usb/tcpm.h b/include/linux/usb/tcpm.h index 3e8bdaa5085a..f0d839daeaea 100644 --- a/include/linux/usb/tcpm.h +++ b/include/linux/usb/tcpm.h @@ -16,7 +16,6 @@ #define __LINUX_USB_TCPM_H #include -#include #include #include "pd.h" @@ -113,14 +112,6 @@ enum tcpc_mux_mode { TCPC_MUX_DP_ENABLED, }; -struct tcpc_mux_dev { - int (*set)(struct tcpc_mux_dev *dev, enum tcpc_mux_mode mux_mode, - enum usb_role usb_role, - enum typec_cc_polarity polarity); - bool dfp_only; - void *priv_data; -}; - /** * struct tcpc_dev - Port configuration and callback functions * @config: Pointer to port configuration @@ -172,7 +163,6 @@ struct tcpc_dev { int (*try_role)(struct tcpc_dev *dev, int role); int (*pd_transmit)(struct tcpc_dev *dev, enum tcpm_transmit_type type, const struct pd_message *msg); - struct tcpc_mux_dev *mux; }; struct tcpm_port; -- cgit v1.2.3 From 5df7af85ecd88e8b5f1f31d6456c3cf38a8bbdda Mon Sep 17 00:00:00 2001 From: Kevin Hao Date: Tue, 20 Mar 2018 09:44:52 +0800 Subject: net: phy: Add general dummy stubs for MMD register access For some phy devices, even though they don't support the MMD extended register access, it does have some side effect if we are trying to read/write the MMD registers via indirect method. So introduce general dummy stubs for MMD register access which these devices can use to avoid such side effect. Fixes: b6b5e8a69118 ("gianfar: Disable EEE autoneg by default") Signed-off-by: Kevin Hao Signed-off-by: David S. Miller --- drivers/net/phy/phy_device.c | 17 +++++++++++++++++ include/linux/phy.h | 4 ++++ 2 files changed, 21 insertions(+) (limited to 'include/linux') diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index fe16f5894092..74664a6c0cdc 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1673,6 +1673,23 @@ int genphy_config_init(struct phy_device *phydev) } EXPORT_SYMBOL(genphy_config_init); +/* This is used for the phy device which doesn't support the MMD extended + * register access, but it does have side effect when we are trying to access + * the MMD register via indirect method. + */ +int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, u16 regnum) +{ + return -EOPNOTSUPP; +} +EXPORT_SYMBOL(genphy_read_mmd_unsupported); + +int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, + u16 regnum, u16 val) +{ + return -EOPNOTSUPP; +} +EXPORT_SYMBOL(genphy_write_mmd_unsupported); + int genphy_suspend(struct phy_device *phydev) { return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); diff --git a/include/linux/phy.h b/include/linux/phy.h index b260fb336b25..7c4c2379e010 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -984,6 +984,10 @@ static inline int genphy_no_soft_reset(struct phy_device *phydev) { return 0; } +int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, + u16 regnum); +int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, + u16 regnum, u16 val); /* Clause 45 PHY */ int genphy_c45_restart_aneg(struct phy_device *phydev); -- cgit v1.2.3 From 5d42c96e1cf98bdfea18e7d32e5f6cf75aac93b9 Mon Sep 17 00:00:00 2001 From: "Luis R. Rodriguez" Date: Wed, 21 Mar 2018 15:34:29 -0700 Subject: firmware: add firmware_request_cache() to help with cache on reboot Some devices have an optimization in place to enable the firmware to be retaineed during a system reboot, so after reboot the device can skip requesting and loading the firmware. This can save up to 1s in load time. The mt7601u 802.11 device happens to be such a device. When these devices retain the firmware on a reboot and then suspend they can miss looking for the firmware on resume. To help with this we need a way to cache the firmware when such an optimization has taken place. Signed-off-by: Luis R. Rodriguez Signed-off-by: Greg Kroah-Hartman --- .../driver-api/firmware/request_firmware.rst | 14 +++++++++++++ drivers/base/firmware_loader/main.c | 24 ++++++++++++++++++++++ include/linux/firmware.h | 3 +++ 3 files changed, 41 insertions(+) (limited to 'include/linux') diff --git a/Documentation/driver-api/firmware/request_firmware.rst b/Documentation/driver-api/firmware/request_firmware.rst index cc0aea880824..cf4516dfbf96 100644 --- a/Documentation/driver-api/firmware/request_firmware.rst +++ b/Documentation/driver-api/firmware/request_firmware.rst @@ -44,6 +44,20 @@ request_firmware_nowait .. kernel-doc:: drivers/base/firmware_class.c :functions: request_firmware_nowait +Special optimizations on reboot +=============================== + +Some devices have an optimization in place to enable the firmware to be +retained during system reboot. When such optimizations are used the driver +author must ensure the firmware is still available on resume from suspend, +this can be done with firmware_request_cache() insted of requesting for the +firmare to be loaded. + +firmware_request_cache() +----------------------- +.. kernel-doc:: drivers/base/firmware_class.c + :functions: firmware_request_cache + request firmware API expected driver use ======================================== diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c index 2913bb0e5e7b..eb34089e4299 100644 --- a/drivers/base/firmware_loader/main.c +++ b/drivers/base/firmware_loader/main.c @@ -656,6 +656,30 @@ int request_firmware_direct(const struct firmware **firmware_p, } EXPORT_SYMBOL_GPL(request_firmware_direct); +/** + * firmware_request_cache: - cache firmware for suspend so resume can use it + * @name: name of firmware file + * @device: device for which firmware should be cached for + * + * There are some devices with an optimization that enables the device to not + * require loading firmware on system reboot. This optimization may still + * require the firmware present on resume from suspend. This routine can be + * used to ensure the firmware is present on resume from suspend in these + * situations. This helper is not compatible with drivers which use + * request_firmware_into_buf() or request_firmware_nowait() with no uevent set. + **/ +int firmware_request_cache(struct device *device, const char *name) +{ + int ret; + + mutex_lock(&fw_lock); + ret = fw_add_devm_name(device, name); + mutex_unlock(&fw_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(firmware_request_cache); + /** * request_firmware_into_buf - load firmware into a previously allocated buffer * @firmware_p: pointer to firmware image diff --git a/include/linux/firmware.h b/include/linux/firmware.h index d4508080348d..41050417cafb 100644 --- a/include/linux/firmware.h +++ b/include/linux/firmware.h @@ -85,4 +85,7 @@ static inline int request_firmware_into_buf(const struct firmware **firmware_p, } #endif + +int firmware_request_cache(struct device *device, const char *name); + #endif -- cgit v1.2.3 From f59f1caf72ba00d519c793c3deb32cd3be32edc2 Mon Sep 17 00:00:00 2001 From: Daniel Vacek Date: Thu, 22 Mar 2018 16:17:38 -0700 Subject: Revert "mm: page_alloc: skip over regions of invalid pfns where possible" This reverts commit b92df1de5d28 ("mm: page_alloc: skip over regions of invalid pfns where possible"). The commit is meant to be a boot init speed up skipping the loop in memmap_init_zone() for invalid pfns. But given some specific memory mapping on x86_64 (or more generally theoretically anywhere but on arm with CONFIG_HAVE_ARCH_PFN_VALID) the implementation also skips valid pfns which is plain wrong and causes 'kernel BUG at mm/page_alloc.c:1389!' crash> log | grep -e BUG -e RIP -e Call.Trace -e move_freepages_block -e rmqueue -e freelist -A1 kernel BUG at mm/page_alloc.c:1389! invalid opcode: 0000 [#1] SMP -- RIP: 0010: move_freepages+0x15e/0x160 -- Call Trace: move_freepages_block+0x73/0x80 __rmqueue+0x263/0x460 get_page_from_freelist+0x7e1/0x9e0 __alloc_pages_nodemask+0x176/0x420 -- crash> page_init_bug -v | grep RAM 1000 - 9bfff System RAM (620.00 KiB) 100000 - 430bffff System RAM ( 1.05 GiB = 1071.75 MiB = 1097472.00 KiB) 4b0c8000 - 4bf9cfff System RAM ( 14.83 MiB = 15188.00 KiB) 4bfac000 - 646b1fff System RAM (391.02 MiB = 400408.00 KiB) 7b788000 - 7b7fffff System RAM (480.00 KiB) 100000000 - 67fffffff System RAM ( 22.00 GiB) crash> page_init_bug | head -6 7b788000 - 7b7fffff System RAM (480.00 KiB) 1fffff00000000 0 1 DMA32 4096 1048575 505736 505344 505855 0 0 0 DMA 1 4095 1fffff00000400 0 1 DMA32 4096 1048575 BUG, zones differ! crash> kmem -p 77fff000 78000000 7b5ff000 7b600000 7b787000 7b788000 PAGE PHYSICAL MAPPING INDEX CNT FLAGS ffffea0001e00000 78000000 0 0 0 0 ffffea0001ed7fc0 7b5ff000 0 0 0 0 ffffea0001ed8000 7b600000 0 0 0 0 <<<< ffffea0001ede1c0 7b787000 0 0 0 0 ffffea0001ede200 7b788000 0 0 1 1fffff00000000 Link: http://lkml.kernel.org/r/20180316143855.29838-1-neelx@redhat.com Fixes: b92df1de5d28 ("mm: page_alloc: skip over regions of invalid pfns where possible") Signed-off-by: Daniel Vacek Acked-by: Ard Biesheuvel Acked-by: Michal Hocko Reviewed-by: Andrew Morton Cc: Vlastimil Babka Cc: Mel Gorman Cc: Pavel Tatashin Cc: Paul Burton Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/linux/memblock.h | 1 - mm/memblock.c | 28 ---------------------------- mm/page_alloc.c | 11 +---------- 3 files changed, 1 insertion(+), 39 deletions(-) (limited to 'include/linux') diff --git a/include/linux/memblock.h b/include/linux/memblock.h index 8be5077efb5f..f92ea7783652 100644 --- a/include/linux/memblock.h +++ b/include/linux/memblock.h @@ -187,7 +187,6 @@ int memblock_search_pfn_nid(unsigned long pfn, unsigned long *start_pfn, unsigned long *end_pfn); void __next_mem_pfn_range(int *idx, int nid, unsigned long *out_start_pfn, unsigned long *out_end_pfn, int *out_nid); -unsigned long memblock_next_valid_pfn(unsigned long pfn, unsigned long max_pfn); /** * for_each_mem_pfn_range - early memory pfn range iterator diff --git a/mm/memblock.c b/mm/memblock.c index b6ba6b7adadc..48376bd33274 100644 --- a/mm/memblock.c +++ b/mm/memblock.c @@ -1101,34 +1101,6 @@ void __init_memblock __next_mem_pfn_range(int *idx, int nid, *out_nid = r->nid; } -unsigned long __init_memblock memblock_next_valid_pfn(unsigned long pfn, - unsigned long max_pfn) -{ - struct memblock_type *type = &memblock.memory; - unsigned int right = type->cnt; - unsigned int mid, left = 0; - phys_addr_t addr = PFN_PHYS(++pfn); - - do { - mid = (right + left) / 2; - - if (addr < type->regions[mid].base) - right = mid; - else if (addr >= (type->regions[mid].base + - type->regions[mid].size)) - left = mid + 1; - else { - /* addr is within the region, so pfn is valid */ - return pfn; - } - } while (left < right); - - if (right == type->cnt) - return -1UL; - else - return PHYS_PFN(type->regions[right].base); -} - /** * memblock_set_node - set node ID on memblock regions * @base: base of area to set node ID for diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 010dee0f089e..1741dd23e7c1 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -5356,17 +5356,8 @@ void __meminit memmap_init_zone(unsigned long size, int nid, unsigned long zone, if (context != MEMMAP_EARLY) goto not_early; - if (!early_pfn_valid(pfn)) { -#ifdef CONFIG_HAVE_MEMBLOCK_NODE_MAP - /* - * Skip to the pfn preceding the next valid one (or - * end_pfn), such that we hit a valid pfn (or end_pfn) - * on our next iteration of the loop. - */ - pfn = memblock_next_valid_pfn(pfn, end_pfn) - 1; -#endif + if (!early_pfn_valid(pfn)) continue; - } if (!early_pfn_in_nid(pfn, nid)) continue; if (!update_defer_init(pgdat, pfn, end_pfn, &nr_initialised)) -- cgit v1.2.3 From aefad9593ec5ad4aae5346253a8b646364cd7317 Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 22 Mar 2018 20:52:43 -0500 Subject: sem/security: Pass kern_ipc_perm not sem_array into the sem security hooks All of the implementations of security hooks that take sem_array only access sem_perm the struct kern_ipc_perm member. This means the dependencies of the sem security hooks can be simplified by passing the kern_ipc_perm member of sem_array. Making this change will allow struct sem and struct sem_array to become private to ipc/sem.c. Signed-off-by: "Eric W. Biederman" --- include/linux/lsm_hooks.h | 10 +++++----- include/linux/security.h | 21 ++++++++++----------- ipc/sem.c | 19 ++++++++----------- security/security.c | 10 +++++----- security/selinux/hooks.c | 28 ++++++++++++++-------------- security/smack/smack_lsm.c | 22 +++++++++++----------- 6 files changed, 53 insertions(+), 57 deletions(-) (limited to 'include/linux') diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index 7161d8e7ee79..e4a94863a88c 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -1592,11 +1592,11 @@ union security_list_options { int (*shm_shmat)(struct shmid_kernel *shp, char __user *shmaddr, int shmflg); - int (*sem_alloc_security)(struct sem_array *sma); - void (*sem_free_security)(struct sem_array *sma); - int (*sem_associate)(struct sem_array *sma, int semflg); - int (*sem_semctl)(struct sem_array *sma, int cmd); - int (*sem_semop)(struct sem_array *sma, struct sembuf *sops, + int (*sem_alloc_security)(struct kern_ipc_perm *sma); + void (*sem_free_security)(struct kern_ipc_perm *sma); + int (*sem_associate)(struct kern_ipc_perm *sma, int semflg); + int (*sem_semctl)(struct kern_ipc_perm *sma, int cmd); + int (*sem_semop)(struct kern_ipc_perm *sma, struct sembuf *sops, unsigned nsops, int alter); int (*netlink_send)(struct sock *sk, struct sk_buff *skb); diff --git a/include/linux/security.h b/include/linux/security.h index 73f1ef625d40..fa7adac4b99a 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -36,7 +36,6 @@ struct linux_binprm; struct cred; struct rlimit; struct siginfo; -struct sem_array; struct sembuf; struct kern_ipc_perm; struct audit_context; @@ -368,11 +367,11 @@ void security_shm_free(struct shmid_kernel *shp); int security_shm_associate(struct shmid_kernel *shp, int shmflg); int security_shm_shmctl(struct shmid_kernel *shp, int cmd); int security_shm_shmat(struct shmid_kernel *shp, char __user *shmaddr, int shmflg); -int security_sem_alloc(struct sem_array *sma); -void security_sem_free(struct sem_array *sma); -int security_sem_associate(struct sem_array *sma, int semflg); -int security_sem_semctl(struct sem_array *sma, int cmd); -int security_sem_semop(struct sem_array *sma, struct sembuf *sops, +int security_sem_alloc(struct kern_ipc_perm *sma); +void security_sem_free(struct kern_ipc_perm *sma); +int security_sem_associate(struct kern_ipc_perm *sma, int semflg); +int security_sem_semctl(struct kern_ipc_perm *sma, int cmd); +int security_sem_semop(struct kern_ipc_perm *sma, struct sembuf *sops, unsigned nsops, int alter); void security_d_instantiate(struct dentry *dentry, struct inode *inode); int security_getprocattr(struct task_struct *p, char *name, char **value); @@ -1103,25 +1102,25 @@ static inline int security_shm_shmat(struct shmid_kernel *shp, return 0; } -static inline int security_sem_alloc(struct sem_array *sma) +static inline int security_sem_alloc(struct kern_ipc_perm *sma) { return 0; } -static inline void security_sem_free(struct sem_array *sma) +static inline void security_sem_free(struct kern_ipc_perm *sma) { } -static inline int security_sem_associate(struct sem_array *sma, int semflg) +static inline int security_sem_associate(struct kern_ipc_perm *sma, int semflg) { return 0; } -static inline int security_sem_semctl(struct sem_array *sma, int cmd) +static inline int security_sem_semctl(struct kern_ipc_perm *sma, int cmd) { return 0; } -static inline int security_sem_semop(struct sem_array *sma, +static inline int security_sem_semop(struct kern_ipc_perm *sma, struct sembuf *sops, unsigned nsops, int alter) { diff --git a/ipc/sem.c b/ipc/sem.c index a4af04979fd2..01f5c63670ae 100644 --- a/ipc/sem.c +++ b/ipc/sem.c @@ -265,7 +265,7 @@ static void sem_rcu_free(struct rcu_head *head) struct kern_ipc_perm *p = container_of(head, struct kern_ipc_perm, rcu); struct sem_array *sma = container_of(p, struct sem_array, sem_perm); - security_sem_free(sma); + security_sem_free(&sma->sem_perm); kvfree(sma); } @@ -495,7 +495,7 @@ static int newary(struct ipc_namespace *ns, struct ipc_params *params) sma->sem_perm.key = key; sma->sem_perm.security = NULL; - retval = security_sem_alloc(sma); + retval = security_sem_alloc(&sma->sem_perm); if (retval) { kvfree(sma); return retval; @@ -535,10 +535,7 @@ static int newary(struct ipc_namespace *ns, struct ipc_params *params) */ static inline int sem_security(struct kern_ipc_perm *ipcp, int semflg) { - struct sem_array *sma; - - sma = container_of(ipcp, struct sem_array, sem_perm); - return security_sem_associate(sma, semflg); + return security_sem_associate(ipcp, semflg); } /* @@ -1209,7 +1206,7 @@ static int semctl_stat(struct ipc_namespace *ns, int semid, if (ipcperms(ns, &sma->sem_perm, S_IRUGO)) goto out_unlock; - err = security_sem_semctl(sma, cmd); + err = security_sem_semctl(&sma->sem_perm, cmd); if (err) goto out_unlock; @@ -1300,7 +1297,7 @@ static int semctl_setval(struct ipc_namespace *ns, int semid, int semnum, return -EACCES; } - err = security_sem_semctl(sma, SETVAL); + err = security_sem_semctl(&sma->sem_perm, SETVAL); if (err) { rcu_read_unlock(); return -EACCES; @@ -1354,7 +1351,7 @@ static int semctl_main(struct ipc_namespace *ns, int semid, int semnum, if (ipcperms(ns, &sma->sem_perm, cmd == SETALL ? S_IWUGO : S_IRUGO)) goto out_rcu_wakeup; - err = security_sem_semctl(sma, cmd); + err = security_sem_semctl(&sma->sem_perm, cmd); if (err) goto out_rcu_wakeup; @@ -1545,7 +1542,7 @@ static int semctl_down(struct ipc_namespace *ns, int semid, sma = container_of(ipcp, struct sem_array, sem_perm); - err = security_sem_semctl(sma, cmd); + err = security_sem_semctl(&sma->sem_perm, cmd); if (err) goto out_unlock1; @@ -1962,7 +1959,7 @@ static long do_semtimedop(int semid, struct sembuf __user *tsops, goto out_free; } - error = security_sem_semop(sma, sops, nsops, alter); + error = security_sem_semop(&sma->sem_perm, sops, nsops, alter); if (error) { rcu_read_unlock(); goto out_free; diff --git a/security/security.c b/security/security.c index 1cd8526cb0b7..d3b9aeb6b73b 100644 --- a/security/security.c +++ b/security/security.c @@ -1220,27 +1220,27 @@ int security_shm_shmat(struct shmid_kernel *shp, char __user *shmaddr, int shmfl return call_int_hook(shm_shmat, 0, shp, shmaddr, shmflg); } -int security_sem_alloc(struct sem_array *sma) +int security_sem_alloc(struct kern_ipc_perm *sma) { return call_int_hook(sem_alloc_security, 0, sma); } -void security_sem_free(struct sem_array *sma) +void security_sem_free(struct kern_ipc_perm *sma) { call_void_hook(sem_free_security, sma); } -int security_sem_associate(struct sem_array *sma, int semflg) +int security_sem_associate(struct kern_ipc_perm *sma, int semflg) { return call_int_hook(sem_associate, 0, sma, semflg); } -int security_sem_semctl(struct sem_array *sma, int cmd) +int security_sem_semctl(struct kern_ipc_perm *sma, int cmd) { return call_int_hook(sem_semctl, 0, sma, cmd); } -int security_sem_semop(struct sem_array *sma, struct sembuf *sops, +int security_sem_semop(struct kern_ipc_perm *sma, struct sembuf *sops, unsigned nsops, int alter) { return call_int_hook(sem_semop, 0, sma, sops, nsops, alter); diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 8644d864e3c1..cce994e9fc0a 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -5767,53 +5767,53 @@ static int selinux_shm_shmat(struct shmid_kernel *shp, } /* Semaphore security operations */ -static int selinux_sem_alloc_security(struct sem_array *sma) +static int selinux_sem_alloc_security(struct kern_ipc_perm *sma) { struct ipc_security_struct *isec; struct common_audit_data ad; u32 sid = current_sid(); int rc; - rc = ipc_alloc_security(&sma->sem_perm, SECCLASS_SEM); + rc = ipc_alloc_security(sma, SECCLASS_SEM); if (rc) return rc; - isec = sma->sem_perm.security; + isec = sma->security; ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = sma->sem_perm.key; + ad.u.ipc_id = sma->key; rc = avc_has_perm(sid, isec->sid, SECCLASS_SEM, SEM__CREATE, &ad); if (rc) { - ipc_free_security(&sma->sem_perm); + ipc_free_security(sma); return rc; } return 0; } -static void selinux_sem_free_security(struct sem_array *sma) +static void selinux_sem_free_security(struct kern_ipc_perm *sma) { - ipc_free_security(&sma->sem_perm); + ipc_free_security(sma); } -static int selinux_sem_associate(struct sem_array *sma, int semflg) +static int selinux_sem_associate(struct kern_ipc_perm *sma, int semflg) { struct ipc_security_struct *isec; struct common_audit_data ad; u32 sid = current_sid(); - isec = sma->sem_perm.security; + isec = sma->security; ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = sma->sem_perm.key; + ad.u.ipc_id = sma->key; return avc_has_perm(sid, isec->sid, SECCLASS_SEM, SEM__ASSOCIATE, &ad); } /* Note, at this point, sma is locked down */ -static int selinux_sem_semctl(struct sem_array *sma, int cmd) +static int selinux_sem_semctl(struct kern_ipc_perm *sma, int cmd) { int err; u32 perms; @@ -5851,11 +5851,11 @@ static int selinux_sem_semctl(struct sem_array *sma, int cmd) return 0; } - err = ipc_has_perm(&sma->sem_perm, perms); + err = ipc_has_perm(sma, perms); return err; } -static int selinux_sem_semop(struct sem_array *sma, +static int selinux_sem_semop(struct kern_ipc_perm *sma, struct sembuf *sops, unsigned nsops, int alter) { u32 perms; @@ -5865,7 +5865,7 @@ static int selinux_sem_semop(struct sem_array *sma, else perms = SEM__READ; - return ipc_has_perm(&sma->sem_perm, perms); + return ipc_has_perm(sma, perms); } static int selinux_ipc_permission(struct kern_ipc_perm *ipcp, short flag) diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index 03fdecba93bb..0402b8c1aec1 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -3077,9 +3077,9 @@ static int smack_shm_shmat(struct shmid_kernel *shp, char __user *shmaddr, * * Returns a pointer to the smack value */ -static struct smack_known *smack_of_sem(struct sem_array *sma) +static struct smack_known *smack_of_sem(struct kern_ipc_perm *sma) { - return (struct smack_known *)sma->sem_perm.security; + return (struct smack_known *)sma->security; } /** @@ -3088,9 +3088,9 @@ static struct smack_known *smack_of_sem(struct sem_array *sma) * * Returns 0 */ -static int smack_sem_alloc_security(struct sem_array *sma) +static int smack_sem_alloc_security(struct kern_ipc_perm *sma) { - struct kern_ipc_perm *isp = &sma->sem_perm; + struct kern_ipc_perm *isp = sma; struct smack_known *skp = smk_of_current(); isp->security = skp; @@ -3103,9 +3103,9 @@ static int smack_sem_alloc_security(struct sem_array *sma) * * Clears the blob pointer */ -static void smack_sem_free_security(struct sem_array *sma) +static void smack_sem_free_security(struct kern_ipc_perm *sma) { - struct kern_ipc_perm *isp = &sma->sem_perm; + struct kern_ipc_perm *isp = sma; isp->security = NULL; } @@ -3117,7 +3117,7 @@ static void smack_sem_free_security(struct sem_array *sma) * * Returns 0 if current has the requested access, error code otherwise */ -static int smk_curacc_sem(struct sem_array *sma, int access) +static int smk_curacc_sem(struct kern_ipc_perm *sma, int access) { struct smack_known *ssp = smack_of_sem(sma); struct smk_audit_info ad; @@ -3125,7 +3125,7 @@ static int smk_curacc_sem(struct sem_array *sma, int access) #ifdef CONFIG_AUDIT smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_IPC); - ad.a.u.ipc_id = sma->sem_perm.id; + ad.a.u.ipc_id = sma->id; #endif rc = smk_curacc(ssp, access, &ad); rc = smk_bu_current("sem", ssp, access, rc); @@ -3139,7 +3139,7 @@ static int smk_curacc_sem(struct sem_array *sma, int access) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_sem_associate(struct sem_array *sma, int semflg) +static int smack_sem_associate(struct kern_ipc_perm *sma, int semflg) { int may; @@ -3154,7 +3154,7 @@ static int smack_sem_associate(struct sem_array *sma, int semflg) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_sem_semctl(struct sem_array *sma, int cmd) +static int smack_sem_semctl(struct kern_ipc_perm *sma, int cmd) { int may; @@ -3198,7 +3198,7 @@ static int smack_sem_semctl(struct sem_array *sma, int cmd) * * Returns 0 if access is allowed, error code otherwise */ -static int smack_sem_semop(struct sem_array *sma, struct sembuf *sops, +static int smack_sem_semop(struct kern_ipc_perm *sma, struct sembuf *sops, unsigned nsops, int alter) { return smk_curacc_sem(sma, MAY_READWRITE); -- cgit v1.2.3 From 7191adff2a5566efb139c79ea03eda3d0520d44a Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 22 Mar 2018 21:08:27 -0500 Subject: shm/security: Pass kern_ipc_perm not shmid_kernel into the shm security hooks All of the implementations of security hooks that take shmid_kernel only access shm_perm the struct kern_ipc_perm member. This means the dependencies of the shm security hooks can be simplified by passing the kern_ipc_perm member of shmid_kernel.. Making this change will allow struct shmid_kernel to become private to ipc/shm.c. Signed-off-by: "Eric W. Biederman" --- include/linux/lsm_hooks.h | 10 +++++----- include/linux/security.h | 21 ++++++++++----------- ipc/shm.c | 17 +++++++---------- security/security.c | 10 +++++----- security/selinux/hooks.c | 28 ++++++++++++++-------------- security/smack/smack_lsm.c | 22 +++++++++++----------- 6 files changed, 52 insertions(+), 56 deletions(-) (limited to 'include/linux') diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index e4a94863a88c..cac7a8082c43 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -1585,11 +1585,11 @@ union security_list_options { struct task_struct *target, long type, int mode); - int (*shm_alloc_security)(struct shmid_kernel *shp); - void (*shm_free_security)(struct shmid_kernel *shp); - int (*shm_associate)(struct shmid_kernel *shp, int shmflg); - int (*shm_shmctl)(struct shmid_kernel *shp, int cmd); - int (*shm_shmat)(struct shmid_kernel *shp, char __user *shmaddr, + int (*shm_alloc_security)(struct kern_ipc_perm *shp); + void (*shm_free_security)(struct kern_ipc_perm *shp); + int (*shm_associate)(struct kern_ipc_perm *shp, int shmflg); + int (*shm_shmctl)(struct kern_ipc_perm *shp, int cmd); + int (*shm_shmat)(struct kern_ipc_perm *shp, char __user *shmaddr, int shmflg); int (*sem_alloc_security)(struct kern_ipc_perm *sma); diff --git a/include/linux/security.h b/include/linux/security.h index fa7adac4b99a..f390755808ea 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -49,7 +49,6 @@ struct qstr; struct iattr; struct fown_struct; struct file_operations; -struct shmid_kernel; struct msg_msg; struct msg_queue; struct xattr; @@ -362,11 +361,11 @@ int security_msg_queue_msgsnd(struct msg_queue *msq, struct msg_msg *msg, int msqflg); int security_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, struct task_struct *target, long type, int mode); -int security_shm_alloc(struct shmid_kernel *shp); -void security_shm_free(struct shmid_kernel *shp); -int security_shm_associate(struct shmid_kernel *shp, int shmflg); -int security_shm_shmctl(struct shmid_kernel *shp, int cmd); -int security_shm_shmat(struct shmid_kernel *shp, char __user *shmaddr, int shmflg); +int security_shm_alloc(struct kern_ipc_perm *shp); +void security_shm_free(struct kern_ipc_perm *shp); +int security_shm_associate(struct kern_ipc_perm *shp, int shmflg); +int security_shm_shmctl(struct kern_ipc_perm *shp, int cmd); +int security_shm_shmat(struct kern_ipc_perm *shp, char __user *shmaddr, int shmflg); int security_sem_alloc(struct kern_ipc_perm *sma); void security_sem_free(struct kern_ipc_perm *sma); int security_sem_associate(struct kern_ipc_perm *sma, int semflg); @@ -1077,26 +1076,26 @@ static inline int security_msg_queue_msgrcv(struct msg_queue *msq, return 0; } -static inline int security_shm_alloc(struct shmid_kernel *shp) +static inline int security_shm_alloc(struct kern_ipc_perm *shp) { return 0; } -static inline void security_shm_free(struct shmid_kernel *shp) +static inline void security_shm_free(struct kern_ipc_perm *shp) { } -static inline int security_shm_associate(struct shmid_kernel *shp, +static inline int security_shm_associate(struct kern_ipc_perm *shp, int shmflg) { return 0; } -static inline int security_shm_shmctl(struct shmid_kernel *shp, int cmd) +static inline int security_shm_shmctl(struct kern_ipc_perm *shp, int cmd) { return 0; } -static inline int security_shm_shmat(struct shmid_kernel *shp, +static inline int security_shm_shmat(struct kern_ipc_perm *shp, char __user *shmaddr, int shmflg) { return 0; diff --git a/ipc/shm.c b/ipc/shm.c index 4643865e9171..387a786e7be1 100644 --- a/ipc/shm.c +++ b/ipc/shm.c @@ -181,7 +181,7 @@ static void shm_rcu_free(struct rcu_head *head) rcu); struct shmid_kernel *shp = container_of(ptr, struct shmid_kernel, shm_perm); - security_shm_free(shp); + security_shm_free(&shp->shm_perm); kvfree(shp); } @@ -554,7 +554,7 @@ static int newseg(struct ipc_namespace *ns, struct ipc_params *params) shp->mlock_user = NULL; shp->shm_perm.security = NULL; - error = security_shm_alloc(shp); + error = security_shm_alloc(&shp->shm_perm); if (error) { kvfree(shp); return error; @@ -635,10 +635,7 @@ no_file: */ static inline int shm_security(struct kern_ipc_perm *ipcp, int shmflg) { - struct shmid_kernel *shp; - - shp = container_of(ipcp, struct shmid_kernel, shm_perm); - return security_shm_associate(shp, shmflg); + return security_shm_associate(ipcp, shmflg); } /* @@ -835,7 +832,7 @@ static int shmctl_down(struct ipc_namespace *ns, int shmid, int cmd, shp = container_of(ipcp, struct shmid_kernel, shm_perm); - err = security_shm_shmctl(shp, cmd); + err = security_shm_shmctl(&shp->shm_perm, cmd); if (err) goto out_unlock1; @@ -934,7 +931,7 @@ static int shmctl_stat(struct ipc_namespace *ns, int shmid, if (ipcperms(ns, &shp->shm_perm, S_IRUGO)) goto out_unlock; - err = security_shm_shmctl(shp, cmd); + err = security_shm_shmctl(&shp->shm_perm, cmd); if (err) goto out_unlock; @@ -978,7 +975,7 @@ static int shmctl_do_lock(struct ipc_namespace *ns, int shmid, int cmd) } audit_ipc_obj(&(shp->shm_perm)); - err = security_shm_shmctl(shp, cmd); + err = security_shm_shmctl(&shp->shm_perm, cmd); if (err) goto out_unlock1; @@ -1348,7 +1345,7 @@ long do_shmat(int shmid, char __user *shmaddr, int shmflg, if (ipcperms(ns, &shp->shm_perm, acc_mode)) goto out_unlock; - err = security_shm_shmat(shp, shmaddr, shmflg); + err = security_shm_shmat(&shp->shm_perm, shmaddr, shmflg); if (err) goto out_unlock; diff --git a/security/security.c b/security/security.c index d3b9aeb6b73b..77b69bd6f234 100644 --- a/security/security.c +++ b/security/security.c @@ -1195,27 +1195,27 @@ int security_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, return call_int_hook(msg_queue_msgrcv, 0, msq, msg, target, type, mode); } -int security_shm_alloc(struct shmid_kernel *shp) +int security_shm_alloc(struct kern_ipc_perm *shp) { return call_int_hook(shm_alloc_security, 0, shp); } -void security_shm_free(struct shmid_kernel *shp) +void security_shm_free(struct kern_ipc_perm *shp) { call_void_hook(shm_free_security, shp); } -int security_shm_associate(struct shmid_kernel *shp, int shmflg) +int security_shm_associate(struct kern_ipc_perm *shp, int shmflg) { return call_int_hook(shm_associate, 0, shp, shmflg); } -int security_shm_shmctl(struct shmid_kernel *shp, int cmd) +int security_shm_shmctl(struct kern_ipc_perm *shp, int cmd) { return call_int_hook(shm_shmctl, 0, shp, cmd); } -int security_shm_shmat(struct shmid_kernel *shp, char __user *shmaddr, int shmflg) +int security_shm_shmat(struct kern_ipc_perm *shp, char __user *shmaddr, int shmflg) { return call_int_hook(shm_shmat, 0, shp, shmaddr, shmflg); } diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index cce994e9fc0a..14f9e6c08273 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -5674,53 +5674,53 @@ static int selinux_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, } /* Shared Memory security operations */ -static int selinux_shm_alloc_security(struct shmid_kernel *shp) +static int selinux_shm_alloc_security(struct kern_ipc_perm *shp) { struct ipc_security_struct *isec; struct common_audit_data ad; u32 sid = current_sid(); int rc; - rc = ipc_alloc_security(&shp->shm_perm, SECCLASS_SHM); + rc = ipc_alloc_security(shp, SECCLASS_SHM); if (rc) return rc; - isec = shp->shm_perm.security; + isec = shp->security; ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = shp->shm_perm.key; + ad.u.ipc_id = shp->key; rc = avc_has_perm(sid, isec->sid, SECCLASS_SHM, SHM__CREATE, &ad); if (rc) { - ipc_free_security(&shp->shm_perm); + ipc_free_security(shp); return rc; } return 0; } -static void selinux_shm_free_security(struct shmid_kernel *shp) +static void selinux_shm_free_security(struct kern_ipc_perm *shp) { - ipc_free_security(&shp->shm_perm); + ipc_free_security(shp); } -static int selinux_shm_associate(struct shmid_kernel *shp, int shmflg) +static int selinux_shm_associate(struct kern_ipc_perm *shp, int shmflg) { struct ipc_security_struct *isec; struct common_audit_data ad; u32 sid = current_sid(); - isec = shp->shm_perm.security; + isec = shp->security; ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = shp->shm_perm.key; + ad.u.ipc_id = shp->key; return avc_has_perm(sid, isec->sid, SECCLASS_SHM, SHM__ASSOCIATE, &ad); } /* Note, at this point, shp is locked down */ -static int selinux_shm_shmctl(struct shmid_kernel *shp, int cmd) +static int selinux_shm_shmctl(struct kern_ipc_perm *shp, int cmd) { int perms; int err; @@ -5749,11 +5749,11 @@ static int selinux_shm_shmctl(struct shmid_kernel *shp, int cmd) return 0; } - err = ipc_has_perm(&shp->shm_perm, perms); + err = ipc_has_perm(shp, perms); return err; } -static int selinux_shm_shmat(struct shmid_kernel *shp, +static int selinux_shm_shmat(struct kern_ipc_perm *shp, char __user *shmaddr, int shmflg) { u32 perms; @@ -5763,7 +5763,7 @@ static int selinux_shm_shmat(struct shmid_kernel *shp, else perms = SHM__READ | SHM__WRITE; - return ipc_has_perm(&shp->shm_perm, perms); + return ipc_has_perm(shp, perms); } /* Semaphore security operations */ diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index 0402b8c1aec1..a3398c7f32c9 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -2950,9 +2950,9 @@ static void smack_msg_msg_free_security(struct msg_msg *msg) * * Returns a pointer to the smack value */ -static struct smack_known *smack_of_shm(struct shmid_kernel *shp) +static struct smack_known *smack_of_shm(struct kern_ipc_perm *shp) { - return (struct smack_known *)shp->shm_perm.security; + return (struct smack_known *)shp->security; } /** @@ -2961,9 +2961,9 @@ static struct smack_known *smack_of_shm(struct shmid_kernel *shp) * * Returns 0 */ -static int smack_shm_alloc_security(struct shmid_kernel *shp) +static int smack_shm_alloc_security(struct kern_ipc_perm *shp) { - struct kern_ipc_perm *isp = &shp->shm_perm; + struct kern_ipc_perm *isp = shp; struct smack_known *skp = smk_of_current(); isp->security = skp; @@ -2976,9 +2976,9 @@ static int smack_shm_alloc_security(struct shmid_kernel *shp) * * Clears the blob pointer */ -static void smack_shm_free_security(struct shmid_kernel *shp) +static void smack_shm_free_security(struct kern_ipc_perm *shp) { - struct kern_ipc_perm *isp = &shp->shm_perm; + struct kern_ipc_perm *isp = shp; isp->security = NULL; } @@ -2990,7 +2990,7 @@ static void smack_shm_free_security(struct shmid_kernel *shp) * * Returns 0 if current has the requested access, error code otherwise */ -static int smk_curacc_shm(struct shmid_kernel *shp, int access) +static int smk_curacc_shm(struct kern_ipc_perm *shp, int access) { struct smack_known *ssp = smack_of_shm(shp); struct smk_audit_info ad; @@ -2998,7 +2998,7 @@ static int smk_curacc_shm(struct shmid_kernel *shp, int access) #ifdef CONFIG_AUDIT smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_IPC); - ad.a.u.ipc_id = shp->shm_perm.id; + ad.a.u.ipc_id = shp->id; #endif rc = smk_curacc(ssp, access, &ad); rc = smk_bu_current("shm", ssp, access, rc); @@ -3012,7 +3012,7 @@ static int smk_curacc_shm(struct shmid_kernel *shp, int access) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_shm_associate(struct shmid_kernel *shp, int shmflg) +static int smack_shm_associate(struct kern_ipc_perm *shp, int shmflg) { int may; @@ -3027,7 +3027,7 @@ static int smack_shm_associate(struct shmid_kernel *shp, int shmflg) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_shm_shmctl(struct shmid_kernel *shp, int cmd) +static int smack_shm_shmctl(struct kern_ipc_perm *shp, int cmd) { int may; @@ -3062,7 +3062,7 @@ static int smack_shm_shmctl(struct shmid_kernel *shp, int cmd) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_shm_shmat(struct shmid_kernel *shp, char __user *shmaddr, +static int smack_shm_shmat(struct kern_ipc_perm *shp, char __user *shmaddr, int shmflg) { int may; -- cgit v1.2.3 From d8c6e8543294428426578d74dc7aaf121e762d58 Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 22 Mar 2018 21:22:26 -0500 Subject: msg/security: Pass kern_ipc_perm not msg_queue into the msg_queue security hooks All of the implementations of security hooks that take msg_queue only access q_perm the struct kern_ipc_perm member. This means the dependencies of the msg_queue security hooks can be simplified by passing the kern_ipc_perm member of msg_queue. Making this change will allow struct msg_queue to become private to ipc/msg.c. Signed-off-by: "Eric W. Biederman" --- include/linux/lsm_hooks.h | 12 ++++++------ include/linux/security.h | 25 ++++++++++++------------- ipc/msg.c | 18 ++++++++---------- security/security.c | 12 ++++++------ security/selinux/hooks.c | 36 ++++++++++++++++++------------------ security/smack/smack_lsm.c | 24 ++++++++++++------------ 6 files changed, 62 insertions(+), 65 deletions(-) (limited to 'include/linux') diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index cac7a8082c43..bde167fa2c51 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -1575,13 +1575,13 @@ union security_list_options { int (*msg_msg_alloc_security)(struct msg_msg *msg); void (*msg_msg_free_security)(struct msg_msg *msg); - int (*msg_queue_alloc_security)(struct msg_queue *msq); - void (*msg_queue_free_security)(struct msg_queue *msq); - int (*msg_queue_associate)(struct msg_queue *msq, int msqflg); - int (*msg_queue_msgctl)(struct msg_queue *msq, int cmd); - int (*msg_queue_msgsnd)(struct msg_queue *msq, struct msg_msg *msg, + int (*msg_queue_alloc_security)(struct kern_ipc_perm *msq); + void (*msg_queue_free_security)(struct kern_ipc_perm *msq); + int (*msg_queue_associate)(struct kern_ipc_perm *msq, int msqflg); + int (*msg_queue_msgctl)(struct kern_ipc_perm *msq, int cmd); + int (*msg_queue_msgsnd)(struct kern_ipc_perm *msq, struct msg_msg *msg, int msqflg); - int (*msg_queue_msgrcv)(struct msg_queue *msq, struct msg_msg *msg, + int (*msg_queue_msgrcv)(struct kern_ipc_perm *msq, struct msg_msg *msg, struct task_struct *target, long type, int mode); diff --git a/include/linux/security.h b/include/linux/security.h index f390755808ea..128e1e4a5346 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -50,7 +50,6 @@ struct iattr; struct fown_struct; struct file_operations; struct msg_msg; -struct msg_queue; struct xattr; struct xfrm_sec_ctx; struct mm_struct; @@ -353,13 +352,13 @@ int security_ipc_permission(struct kern_ipc_perm *ipcp, short flag); void security_ipc_getsecid(struct kern_ipc_perm *ipcp, u32 *secid); int security_msg_msg_alloc(struct msg_msg *msg); void security_msg_msg_free(struct msg_msg *msg); -int security_msg_queue_alloc(struct msg_queue *msq); -void security_msg_queue_free(struct msg_queue *msq); -int security_msg_queue_associate(struct msg_queue *msq, int msqflg); -int security_msg_queue_msgctl(struct msg_queue *msq, int cmd); -int security_msg_queue_msgsnd(struct msg_queue *msq, +int security_msg_queue_alloc(struct kern_ipc_perm *msq); +void security_msg_queue_free(struct kern_ipc_perm *msq); +int security_msg_queue_associate(struct kern_ipc_perm *msq, int msqflg); +int security_msg_queue_msgctl(struct kern_ipc_perm *msq, int cmd); +int security_msg_queue_msgsnd(struct kern_ipc_perm *msq, struct msg_msg *msg, int msqflg); -int security_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, +int security_msg_queue_msgrcv(struct kern_ipc_perm *msq, struct msg_msg *msg, struct task_struct *target, long type, int mode); int security_shm_alloc(struct kern_ipc_perm *shp); void security_shm_free(struct kern_ipc_perm *shp); @@ -1043,32 +1042,32 @@ static inline int security_msg_msg_alloc(struct msg_msg *msg) static inline void security_msg_msg_free(struct msg_msg *msg) { } -static inline int security_msg_queue_alloc(struct msg_queue *msq) +static inline int security_msg_queue_alloc(struct kern_ipc_perm *msq) { return 0; } -static inline void security_msg_queue_free(struct msg_queue *msq) +static inline void security_msg_queue_free(struct kern_ipc_perm *msq) { } -static inline int security_msg_queue_associate(struct msg_queue *msq, +static inline int security_msg_queue_associate(struct kern_ipc_perm *msq, int msqflg) { return 0; } -static inline int security_msg_queue_msgctl(struct msg_queue *msq, int cmd) +static inline int security_msg_queue_msgctl(struct kern_ipc_perm *msq, int cmd) { return 0; } -static inline int security_msg_queue_msgsnd(struct msg_queue *msq, +static inline int security_msg_queue_msgsnd(struct kern_ipc_perm *msq, struct msg_msg *msg, int msqflg) { return 0; } -static inline int security_msg_queue_msgrcv(struct msg_queue *msq, +static inline int security_msg_queue_msgrcv(struct kern_ipc_perm *msq, struct msg_msg *msg, struct task_struct *target, long type, int mode) diff --git a/ipc/msg.c b/ipc/msg.c index 0dcc6699dc53..cdfab0825fce 100644 --- a/ipc/msg.c +++ b/ipc/msg.c @@ -101,7 +101,7 @@ static void msg_rcu_free(struct rcu_head *head) struct kern_ipc_perm *p = container_of(head, struct kern_ipc_perm, rcu); struct msg_queue *msq = container_of(p, struct msg_queue, q_perm); - security_msg_queue_free(msq); + security_msg_queue_free(&msq->q_perm); kvfree(msq); } @@ -127,7 +127,7 @@ static int newque(struct ipc_namespace *ns, struct ipc_params *params) msq->q_perm.key = key; msq->q_perm.security = NULL; - retval = security_msg_queue_alloc(msq); + retval = security_msg_queue_alloc(&msq->q_perm); if (retval) { kvfree(msq); return retval; @@ -258,9 +258,7 @@ static void freeque(struct ipc_namespace *ns, struct kern_ipc_perm *ipcp) */ static inline int msg_security(struct kern_ipc_perm *ipcp, int msgflg) { - struct msg_queue *msq = container_of(ipcp, struct msg_queue, q_perm); - - return security_msg_queue_associate(msq, msgflg); + return security_msg_queue_associate(ipcp, msgflg); } SYSCALL_DEFINE2(msgget, key_t, key, int, msgflg) @@ -380,7 +378,7 @@ static int msgctl_down(struct ipc_namespace *ns, int msqid, int cmd, msq = container_of(ipcp, struct msg_queue, q_perm); - err = security_msg_queue_msgctl(msq, cmd); + err = security_msg_queue_msgctl(&msq->q_perm, cmd); if (err) goto out_unlock1; @@ -502,7 +500,7 @@ static int msgctl_stat(struct ipc_namespace *ns, int msqid, if (ipcperms(ns, &msq->q_perm, S_IRUGO)) goto out_unlock; - err = security_msg_queue_msgctl(msq, cmd); + err = security_msg_queue_msgctl(&msq->q_perm, cmd); if (err) goto out_unlock; @@ -718,7 +716,7 @@ static inline int pipelined_send(struct msg_queue *msq, struct msg_msg *msg, list_for_each_entry_safe(msr, t, &msq->q_receivers, r_list) { if (testmsg(msg, msr->r_msgtype, msr->r_mode) && - !security_msg_queue_msgrcv(msq, msg, msr->r_tsk, + !security_msg_queue_msgrcv(&msq->q_perm, msg, msr->r_tsk, msr->r_msgtype, msr->r_mode)) { list_del(&msr->r_list); @@ -784,7 +782,7 @@ static long do_msgsnd(int msqid, long mtype, void __user *mtext, goto out_unlock0; } - err = security_msg_queue_msgsnd(msq, msg, msgflg); + err = security_msg_queue_msgsnd(&msq->q_perm, msg, msgflg); if (err) goto out_unlock0; @@ -960,7 +958,7 @@ static struct msg_msg *find_msg(struct msg_queue *msq, long *msgtyp, int mode) list_for_each_entry(msg, &msq->q_messages, m_list) { if (testmsg(msg, *msgtyp, mode) && - !security_msg_queue_msgrcv(msq, msg, current, + !security_msg_queue_msgrcv(&msq->q_perm, msg, current, *msgtyp, mode)) { if (mode == SEARCH_LESSEQUAL && msg->m_type != 1) { *msgtyp = msg->m_type - 1; diff --git a/security/security.c b/security/security.c index 77b69bd6f234..02d734e69955 100644 --- a/security/security.c +++ b/security/security.c @@ -1163,33 +1163,33 @@ void security_msg_msg_free(struct msg_msg *msg) call_void_hook(msg_msg_free_security, msg); } -int security_msg_queue_alloc(struct msg_queue *msq) +int security_msg_queue_alloc(struct kern_ipc_perm *msq) { return call_int_hook(msg_queue_alloc_security, 0, msq); } -void security_msg_queue_free(struct msg_queue *msq) +void security_msg_queue_free(struct kern_ipc_perm *msq) { call_void_hook(msg_queue_free_security, msq); } -int security_msg_queue_associate(struct msg_queue *msq, int msqflg) +int security_msg_queue_associate(struct kern_ipc_perm *msq, int msqflg) { return call_int_hook(msg_queue_associate, 0, msq, msqflg); } -int security_msg_queue_msgctl(struct msg_queue *msq, int cmd) +int security_msg_queue_msgctl(struct kern_ipc_perm *msq, int cmd) { return call_int_hook(msg_queue_msgctl, 0, msq, cmd); } -int security_msg_queue_msgsnd(struct msg_queue *msq, +int security_msg_queue_msgsnd(struct kern_ipc_perm *msq, struct msg_msg *msg, int msqflg) { return call_int_hook(msg_queue_msgsnd, 0, msq, msg, msqflg); } -int security_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, +int security_msg_queue_msgrcv(struct kern_ipc_perm *msq, struct msg_msg *msg, struct task_struct *target, long type, int mode) { return call_int_hook(msg_queue_msgrcv, 0, msq, msg, target, type, mode); diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 14f9e6c08273..925e546b5a87 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -5532,52 +5532,52 @@ static void selinux_msg_msg_free_security(struct msg_msg *msg) } /* message queue security operations */ -static int selinux_msg_queue_alloc_security(struct msg_queue *msq) +static int selinux_msg_queue_alloc_security(struct kern_ipc_perm *msq) { struct ipc_security_struct *isec; struct common_audit_data ad; u32 sid = current_sid(); int rc; - rc = ipc_alloc_security(&msq->q_perm, SECCLASS_MSGQ); + rc = ipc_alloc_security(msq, SECCLASS_MSGQ); if (rc) return rc; - isec = msq->q_perm.security; + isec = msq->security; ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = msq->q_perm.key; + ad.u.ipc_id = msq->key; rc = avc_has_perm(sid, isec->sid, SECCLASS_MSGQ, MSGQ__CREATE, &ad); if (rc) { - ipc_free_security(&msq->q_perm); + ipc_free_security(msq); return rc; } return 0; } -static void selinux_msg_queue_free_security(struct msg_queue *msq) +static void selinux_msg_queue_free_security(struct kern_ipc_perm *msq) { - ipc_free_security(&msq->q_perm); + ipc_free_security(msq); } -static int selinux_msg_queue_associate(struct msg_queue *msq, int msqflg) +static int selinux_msg_queue_associate(struct kern_ipc_perm *msq, int msqflg) { struct ipc_security_struct *isec; struct common_audit_data ad; u32 sid = current_sid(); - isec = msq->q_perm.security; + isec = msq->security; ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = msq->q_perm.key; + ad.u.ipc_id = msq->key; return avc_has_perm(sid, isec->sid, SECCLASS_MSGQ, MSGQ__ASSOCIATE, &ad); } -static int selinux_msg_queue_msgctl(struct msg_queue *msq, int cmd) +static int selinux_msg_queue_msgctl(struct kern_ipc_perm *msq, int cmd) { int err; int perms; @@ -5602,11 +5602,11 @@ static int selinux_msg_queue_msgctl(struct msg_queue *msq, int cmd) return 0; } - err = ipc_has_perm(&msq->q_perm, perms); + err = ipc_has_perm(msq, perms); return err; } -static int selinux_msg_queue_msgsnd(struct msg_queue *msq, struct msg_msg *msg, int msqflg) +static int selinux_msg_queue_msgsnd(struct kern_ipc_perm *msq, struct msg_msg *msg, int msqflg) { struct ipc_security_struct *isec; struct msg_security_struct *msec; @@ -5614,7 +5614,7 @@ static int selinux_msg_queue_msgsnd(struct msg_queue *msq, struct msg_msg *msg, u32 sid = current_sid(); int rc; - isec = msq->q_perm.security; + isec = msq->security; msec = msg->security; /* @@ -5632,7 +5632,7 @@ static int selinux_msg_queue_msgsnd(struct msg_queue *msq, struct msg_msg *msg, } ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = msq->q_perm.key; + ad.u.ipc_id = msq->key; /* Can this process write to the queue? */ rc = avc_has_perm(sid, isec->sid, SECCLASS_MSGQ, @@ -5649,7 +5649,7 @@ static int selinux_msg_queue_msgsnd(struct msg_queue *msq, struct msg_msg *msg, return rc; } -static int selinux_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, +static int selinux_msg_queue_msgrcv(struct kern_ipc_perm *msq, struct msg_msg *msg, struct task_struct *target, long type, int mode) { @@ -5659,11 +5659,11 @@ static int selinux_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, u32 sid = task_sid(target); int rc; - isec = msq->q_perm.security; + isec = msq->security; msec = msg->security; ad.type = LSM_AUDIT_DATA_IPC; - ad.u.ipc_id = msq->q_perm.key; + ad.u.ipc_id = msq->key; rc = avc_has_perm(sid, isec->sid, SECCLASS_MSGQ, MSGQ__READ, &ad); diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index a3398c7f32c9..d960c2ea8d79 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -3210,9 +3210,9 @@ static int smack_sem_semop(struct kern_ipc_perm *sma, struct sembuf *sops, * * Returns 0 */ -static int smack_msg_queue_alloc_security(struct msg_queue *msq) +static int smack_msg_queue_alloc_security(struct kern_ipc_perm *msq) { - struct kern_ipc_perm *kisp = &msq->q_perm; + struct kern_ipc_perm *kisp = msq; struct smack_known *skp = smk_of_current(); kisp->security = skp; @@ -3225,9 +3225,9 @@ static int smack_msg_queue_alloc_security(struct msg_queue *msq) * * Clears the blob pointer */ -static void smack_msg_queue_free_security(struct msg_queue *msq) +static void smack_msg_queue_free_security(struct kern_ipc_perm *msq) { - struct kern_ipc_perm *kisp = &msq->q_perm; + struct kern_ipc_perm *kisp = msq; kisp->security = NULL; } @@ -3238,9 +3238,9 @@ static void smack_msg_queue_free_security(struct msg_queue *msq) * * Returns a pointer to the smack label entry */ -static struct smack_known *smack_of_msq(struct msg_queue *msq) +static struct smack_known *smack_of_msq(struct kern_ipc_perm *msq) { - return (struct smack_known *)msq->q_perm.security; + return (struct smack_known *)msq->security; } /** @@ -3250,7 +3250,7 @@ static struct smack_known *smack_of_msq(struct msg_queue *msq) * * return 0 if current has access, error otherwise */ -static int smk_curacc_msq(struct msg_queue *msq, int access) +static int smk_curacc_msq(struct kern_ipc_perm *msq, int access) { struct smack_known *msp = smack_of_msq(msq); struct smk_audit_info ad; @@ -3258,7 +3258,7 @@ static int smk_curacc_msq(struct msg_queue *msq, int access) #ifdef CONFIG_AUDIT smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_IPC); - ad.a.u.ipc_id = msq->q_perm.id; + ad.a.u.ipc_id = msq->id; #endif rc = smk_curacc(msp, access, &ad); rc = smk_bu_current("msq", msp, access, rc); @@ -3272,7 +3272,7 @@ static int smk_curacc_msq(struct msg_queue *msq, int access) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_msg_queue_associate(struct msg_queue *msq, int msqflg) +static int smack_msg_queue_associate(struct kern_ipc_perm *msq, int msqflg) { int may; @@ -3287,7 +3287,7 @@ static int smack_msg_queue_associate(struct msg_queue *msq, int msqflg) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_msg_queue_msgctl(struct msg_queue *msq, int cmd) +static int smack_msg_queue_msgctl(struct kern_ipc_perm *msq, int cmd) { int may; @@ -3321,7 +3321,7 @@ static int smack_msg_queue_msgctl(struct msg_queue *msq, int cmd) * * Returns 0 if current has the requested access, error code otherwise */ -static int smack_msg_queue_msgsnd(struct msg_queue *msq, struct msg_msg *msg, +static int smack_msg_queue_msgsnd(struct kern_ipc_perm *msq, struct msg_msg *msg, int msqflg) { int may; @@ -3340,7 +3340,7 @@ static int smack_msg_queue_msgsnd(struct msg_queue *msq, struct msg_msg *msg, * * Returns 0 if current has read and write access, error code otherwise */ -static int smack_msg_queue_msgrcv(struct msg_queue *msq, struct msg_msg *msg, +static int smack_msg_queue_msgrcv(struct kern_ipc_perm *msq, struct msg_msg *msg, struct task_struct *target, long type, int mode) { return smk_curacc_msq(msq, MAY_READWRITE); -- cgit v1.2.3 From 1a5c1349d105df5196ad9025e271b02a4dc05aee Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 22 Mar 2018 21:30:56 -0500 Subject: sem: Move struct sem and struct sem_array into ipc/sem.c All of the users are now in ipc/sem.c so make the definitions local to that file to make code maintenance easier. AKA to prevent rebuilding the entire kernel when one of these files is changed. Signed-off-by: "Eric W. Biederman" --- include/linux/sem.h | 40 +--------------------------------------- ipc/sem.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 39 deletions(-) (limited to 'include/linux') diff --git a/include/linux/sem.h b/include/linux/sem.h index 9badd322dcee..5608a500c43e 100644 --- a/include/linux/sem.h +++ b/include/linux/sem.h @@ -2,48 +2,10 @@ #ifndef _LINUX_SEM_H #define _LINUX_SEM_H -#include -#include -#include -#include #include struct task_struct; - -/* One semaphore structure for each semaphore in the system. */ -struct sem { - int semval; /* current value */ - /* - * PID of the process that last modified the semaphore. For - * Linux, specifically these are: - * - semop - * - semctl, via SETVAL and SETALL. - * - at task exit when performing undo adjustments (see exit_sem). - */ - int sempid; - spinlock_t lock; /* spinlock for fine-grained semtimedop */ - struct list_head pending_alter; /* pending single-sop operations */ - /* that alter the semaphore */ - struct list_head pending_const; /* pending single-sop operations */ - /* that do not alter the semaphore*/ - time_t sem_otime; /* candidate for sem_otime */ -} ____cacheline_aligned_in_smp; - -/* One sem_array data structure for each set of semaphores in the system. */ -struct sem_array { - struct kern_ipc_perm sem_perm; /* permissions .. see ipc.h */ - time64_t sem_ctime; /* create/last semctl() time */ - struct list_head pending_alter; /* pending operations */ - /* that alter the array */ - struct list_head pending_const; /* pending complex operations */ - /* that do not alter semvals */ - struct list_head list_id; /* undo requests on this array */ - int sem_nsems; /* no. of semaphores in array */ - int complex_count; /* pending complex operations */ - unsigned int use_global_lock;/* >0: global lock required */ - - struct sem sems[]; -} __randomize_layout; +struct sem_undo_list; #ifdef CONFIG_SYSVIPC diff --git a/ipc/sem.c b/ipc/sem.c index 01f5c63670ae..d661c491b0a5 100644 --- a/ipc/sem.c +++ b/ipc/sem.c @@ -88,6 +88,40 @@ #include #include "util.h" +/* One semaphore structure for each semaphore in the system. */ +struct sem { + int semval; /* current value */ + /* + * PID of the process that last modified the semaphore. For + * Linux, specifically these are: + * - semop + * - semctl, via SETVAL and SETALL. + * - at task exit when performing undo adjustments (see exit_sem). + */ + int sempid; + spinlock_t lock; /* spinlock for fine-grained semtimedop */ + struct list_head pending_alter; /* pending single-sop operations */ + /* that alter the semaphore */ + struct list_head pending_const; /* pending single-sop operations */ + /* that do not alter the semaphore*/ + time_t sem_otime; /* candidate for sem_otime */ +} ____cacheline_aligned_in_smp; + +/* One sem_array data structure for each set of semaphores in the system. */ +struct sem_array { + struct kern_ipc_perm sem_perm; /* permissions .. see ipc.h */ + time64_t sem_ctime; /* create/last semctl() time */ + struct list_head pending_alter; /* pending operations */ + /* that alter the array */ + struct list_head pending_const; /* pending complex operations */ + /* that do not alter semvals */ + struct list_head list_id; /* undo requests on this array */ + int sem_nsems; /* no. of semaphores in array */ + int complex_count; /* pending complex operations */ + unsigned int use_global_lock;/* >0: global lock required */ + + struct sem sems[]; +} __randomize_layout; /* One queue for each sleeping process in the system. */ struct sem_queue { -- cgit v1.2.3 From aaeab02ddcc830e31c33cdb72a3c117b2d499ae2 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 23 Mar 2018 13:44:06 +1100 Subject: usb/gadget: Add an EP dispose() callback for EP lifetime tracking Some UDC may want to allocate endpoints dynamically, either because the HW supports an arbitrary large number or because (like the Aspeed BMC SoCs), the pool of HW endpoints is shared between multiple gadgets. The allocation side can be done rather easily using the existing match_ep() UDC hook. However we have no good place to "free" them. This implements a "simple" variant of this, which calls an EP dispose callback on all EPs associated with a gadget when the composite device gets unbound. This is required by my upcoming Aspeed vHub driver. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Felipe Balbi --- drivers/usb/gadget/composite.c | 16 ++++++++++++++++ include/linux/usb/gadget.h | 1 + 2 files changed, 17 insertions(+) (limited to 'include/linux') diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 1924e20f6e8c..63a7cb87514a 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -2142,6 +2142,7 @@ end: void composite_dev_cleanup(struct usb_composite_dev *cdev) { struct usb_gadget_string_container *uc, *tmp; + struct usb_ep *ep, *tmp_ep; list_for_each_entry_safe(uc, tmp, &cdev->gstrings, list) { list_del(&uc->list); @@ -2163,6 +2164,21 @@ void composite_dev_cleanup(struct usb_composite_dev *cdev) } cdev->next_string_id = 0; device_remove_file(&cdev->gadget->dev, &dev_attr_suspended); + + /* + * Some UDC backends have a dynamic EP allocation scheme. + * + * In that case, the dispose() callback is used to notify the + * backend that the EPs are no longer in use. + * + * Note: The UDC backend can remove the EP from the ep_list as + * a result, so we need to use the _safe list iterator. + */ + list_for_each_entry_safe(ep, tmp_ep, + &cdev->gadget->ep_list, ep_list) { + if (ep->ops->dispose) + ep->ops->dispose(ep); + } } static int composite_bind(struct usb_gadget *gadget, diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 66a5cff7ee14..e3424234b23a 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -129,6 +129,7 @@ struct usb_ep_ops { int (*enable) (struct usb_ep *ep, const struct usb_endpoint_descriptor *desc); int (*disable) (struct usb_ep *ep); + void (*dispose) (struct usb_ep *ep); struct usb_request *(*alloc_request) (struct usb_ep *ep, gfp_t gfp_flags); -- cgit v1.2.3 From 888d867df4417deffc33927e6fc2c6925736fe92 Mon Sep 17 00:00:00 2001 From: Tomas Winkler Date: Mon, 5 Mar 2018 13:34:49 +0200 Subject: tpm: cmd_ready command can be issued only after granting locality The correct sequence is to first request locality and only after that perform cmd_ready handshake, otherwise the hardware will drop the subsequent message as from the device point of view the cmd_ready handshake wasn't performed. Symmetrically locality has to be relinquished only after going idle handshake has completed, this requires that go_idle has to poll for the completion and as well locality relinquish has to poll for completion so it is not overridden in back to back commands flow. Two wrapper functions are added (request_locality relinquish_locality) to simplify the error handling. The issue is only visible on devices that support multiple localities. Fixes: 877c57d0d0ca ("tpm_crb: request and relinquish locality 0") Signed-off-by: Tomas Winkler Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-interface.c | 54 +++++++++++++++----- drivers/char/tpm/tpm_crb.c | 108 +++++++++++++++++++++++++++------------ drivers/char/tpm/tpm_tis_core.c | 4 +- include/linux/tpm.h | 2 +- 4 files changed, 120 insertions(+), 48 deletions(-) (limited to 'include/linux') diff --git a/drivers/char/tpm/tpm-interface.c b/drivers/char/tpm/tpm-interface.c index 9e80a953d693..d27a7fb7b830 100644 --- a/drivers/char/tpm/tpm-interface.c +++ b/drivers/char/tpm/tpm-interface.c @@ -369,6 +369,36 @@ err_len: return -EINVAL; } +static int tpm_request_locality(struct tpm_chip *chip) +{ + int rc; + + if (!chip->ops->request_locality) + return 0; + + rc = chip->ops->request_locality(chip, 0); + if (rc < 0) + return rc; + + chip->locality = rc; + + return 0; +} + +static void tpm_relinquish_locality(struct tpm_chip *chip) +{ + int rc; + + if (!chip->ops->relinquish_locality) + return; + + rc = chip->ops->relinquish_locality(chip, chip->locality); + if (rc) + dev_err(&chip->dev, "%s: : error %d\n", __func__, rc); + + chip->locality = -1; +} + /** * tmp_transmit - Internal kernel interface to transmit TPM commands. * @@ -422,8 +452,6 @@ ssize_t tpm_transmit(struct tpm_chip *chip, struct tpm_space *space, if (!(flags & TPM_TRANSMIT_UNLOCKED)) mutex_lock(&chip->tpm_mutex); - if (chip->dev.parent) - pm_runtime_get_sync(chip->dev.parent); if (chip->ops->clk_enable != NULL) chip->ops->clk_enable(chip, true); @@ -431,14 +459,15 @@ ssize_t tpm_transmit(struct tpm_chip *chip, struct tpm_space *space, /* Store the decision as chip->locality will be changed. */ need_locality = chip->locality == -1; - if (!(flags & TPM_TRANSMIT_RAW) && - need_locality && chip->ops->request_locality) { - rc = chip->ops->request_locality(chip, 0); + if (!(flags & TPM_TRANSMIT_RAW) && need_locality) { + rc = tpm_request_locality(chip); if (rc < 0) goto out_no_locality; - chip->locality = rc; } + if (chip->dev.parent) + pm_runtime_get_sync(chip->dev.parent); + rc = tpm2_prepare_space(chip, space, ordinal, buf); if (rc) goto out; @@ -499,17 +528,16 @@ out_recv: rc = tpm2_commit_space(chip, space, ordinal, buf, &len); out: - if (need_locality && chip->ops->relinquish_locality) { - chip->ops->relinquish_locality(chip, chip->locality); - chip->locality = -1; - } + if (chip->dev.parent) + pm_runtime_put_sync(chip->dev.parent); + + if (need_locality) + tpm_relinquish_locality(chip); + out_no_locality: if (chip->ops->clk_enable != NULL) chip->ops->clk_enable(chip, false); - if (chip->dev.parent) - pm_runtime_put_sync(chip->dev.parent); - if (!(flags & TPM_TRANSMIT_UNLOCKED)) mutex_unlock(&chip->tpm_mutex); return rc ? rc : len; diff --git a/drivers/char/tpm/tpm_crb.c b/drivers/char/tpm/tpm_crb.c index 7b3c2a8aa9de..497edd9848cd 100644 --- a/drivers/char/tpm/tpm_crb.c +++ b/drivers/char/tpm/tpm_crb.c @@ -112,6 +112,25 @@ struct tpm2_crb_smc { u32 smc_func_id; }; +static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value, + unsigned long timeout) +{ + ktime_t start; + ktime_t stop; + + start = ktime_get(); + stop = ktime_add(start, ms_to_ktime(timeout)); + + do { + if ((ioread32(reg) & mask) == value) + return true; + + usleep_range(50, 100); + } while (ktime_before(ktime_get(), stop)); + + return ((ioread32(reg) & mask) == value); +} + /** * crb_go_idle - request tpm crb device to go the idle state * @@ -128,7 +147,7 @@ struct tpm2_crb_smc { * * Return: 0 always */ -static int __maybe_unused crb_go_idle(struct device *dev, struct crb_priv *priv) +static int crb_go_idle(struct device *dev, struct crb_priv *priv) { if ((priv->sm == ACPI_TPM2_START_METHOD) || (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD) || @@ -136,30 +155,17 @@ static int __maybe_unused crb_go_idle(struct device *dev, struct crb_priv *priv) return 0; iowrite32(CRB_CTRL_REQ_GO_IDLE, &priv->regs_t->ctrl_req); - /* we don't really care when this settles */ + if (!crb_wait_for_reg_32(&priv->regs_t->ctrl_req, + CRB_CTRL_REQ_GO_IDLE/* mask */, + 0, /* value */ + TPM2_TIMEOUT_C)) { + dev_warn(dev, "goIdle timed out\n"); + return -ETIME; + } return 0; } -static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value, - unsigned long timeout) -{ - ktime_t start; - ktime_t stop; - - start = ktime_get(); - stop = ktime_add(start, ms_to_ktime(timeout)); - - do { - if ((ioread32(reg) & mask) == value) - return true; - - usleep_range(50, 100); - } while (ktime_before(ktime_get(), stop)); - - return false; -} - /** * crb_cmd_ready - request tpm crb device to enter ready state * @@ -175,8 +181,7 @@ static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value, * * Return: 0 on success -ETIME on timeout; */ -static int __maybe_unused crb_cmd_ready(struct device *dev, - struct crb_priv *priv) +static int crb_cmd_ready(struct device *dev, struct crb_priv *priv) { if ((priv->sm == ACPI_TPM2_START_METHOD) || (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD) || @@ -195,11 +200,11 @@ static int __maybe_unused crb_cmd_ready(struct device *dev, return 0; } -static int crb_request_locality(struct tpm_chip *chip, int loc) +static int __crb_request_locality(struct device *dev, + struct crb_priv *priv, int loc) { - struct crb_priv *priv = dev_get_drvdata(&chip->dev); u32 value = CRB_LOC_STATE_LOC_ASSIGNED | - CRB_LOC_STATE_TPM_REG_VALID_STS; + CRB_LOC_STATE_TPM_REG_VALID_STS; if (!priv->regs_h) return 0; @@ -207,21 +212,45 @@ static int crb_request_locality(struct tpm_chip *chip, int loc) iowrite32(CRB_LOC_CTRL_REQUEST_ACCESS, &priv->regs_h->loc_ctrl); if (!crb_wait_for_reg_32(&priv->regs_h->loc_state, value, value, TPM2_TIMEOUT_C)) { - dev_warn(&chip->dev, "TPM_LOC_STATE_x.requestAccess timed out\n"); + dev_warn(dev, "TPM_LOC_STATE_x.requestAccess timed out\n"); return -ETIME; } return 0; } -static void crb_relinquish_locality(struct tpm_chip *chip, int loc) +static int crb_request_locality(struct tpm_chip *chip, int loc) { struct crb_priv *priv = dev_get_drvdata(&chip->dev); + return __crb_request_locality(&chip->dev, priv, loc); +} + +static int __crb_relinquish_locality(struct device *dev, + struct crb_priv *priv, int loc) +{ + u32 mask = CRB_LOC_STATE_LOC_ASSIGNED | + CRB_LOC_STATE_TPM_REG_VALID_STS; + u32 value = CRB_LOC_STATE_TPM_REG_VALID_STS; + if (!priv->regs_h) - return; + return 0; iowrite32(CRB_LOC_CTRL_RELINQUISH, &priv->regs_h->loc_ctrl); + if (!crb_wait_for_reg_32(&priv->regs_h->loc_state, mask, value, + TPM2_TIMEOUT_C)) { + dev_warn(dev, "TPM_LOC_STATE_x.requestAccess timed out\n"); + return -ETIME; + } + + return 0; +} + +static int crb_relinquish_locality(struct tpm_chip *chip, int loc) +{ + struct crb_priv *priv = dev_get_drvdata(&chip->dev); + + return __crb_relinquish_locality(&chip->dev, priv, loc); } static u8 crb_status(struct tpm_chip *chip) @@ -475,6 +504,10 @@ static int crb_map_io(struct acpi_device *device, struct crb_priv *priv, dev_warn(dev, FW_BUG "Bad ACPI memory layout"); } + ret = __crb_request_locality(dev, priv, 0); + if (ret) + return ret; + priv->regs_t = crb_map_res(dev, priv, &io_res, buf->control_address, sizeof(struct crb_regs_tail)); if (IS_ERR(priv->regs_t)) @@ -531,6 +564,8 @@ out: crb_go_idle(dev, priv); + __crb_relinquish_locality(dev, priv, 0); + return ret; } @@ -588,10 +623,14 @@ static int crb_acpi_add(struct acpi_device *device) chip->acpi_dev_handle = device->handle; chip->flags = TPM_CHIP_FLAG_TPM2; - rc = crb_cmd_ready(dev, priv); + rc = __crb_request_locality(dev, priv, 0); if (rc) return rc; + rc = crb_cmd_ready(dev, priv); + if (rc) + goto out; + pm_runtime_get_noresume(dev); pm_runtime_set_active(dev); pm_runtime_enable(dev); @@ -601,12 +640,15 @@ static int crb_acpi_add(struct acpi_device *device) crb_go_idle(dev, priv); pm_runtime_put_noidle(dev); pm_runtime_disable(dev); - return rc; + goto out; } - pm_runtime_put(dev); + pm_runtime_put_sync(dev); - return 0; +out: + __crb_relinquish_locality(dev, priv, 0); + + return rc; } static int crb_acpi_remove(struct acpi_device *device) diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c index da074e3db19b..5a1f47b43947 100644 --- a/drivers/char/tpm/tpm_tis_core.c +++ b/drivers/char/tpm/tpm_tis_core.c @@ -143,11 +143,13 @@ static bool check_locality(struct tpm_chip *chip, int l) return false; } -static void release_locality(struct tpm_chip *chip, int l) +static int release_locality(struct tpm_chip *chip, int l) { struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev); tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_ACTIVE_LOCALITY); + + return 0; } static int request_locality(struct tpm_chip *chip, int l) diff --git a/include/linux/tpm.h b/include/linux/tpm.h index bcdd3790e94d..06639fb6ab85 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -44,7 +44,7 @@ struct tpm_class_ops { bool (*update_timeouts)(struct tpm_chip *chip, unsigned long *timeout_cap); int (*request_locality)(struct tpm_chip *chip, int loc); - void (*relinquish_locality)(struct tpm_chip *chip, int loc); + int (*relinquish_locality)(struct tpm_chip *chip, int loc); void (*clk_enable)(struct tpm_chip *chip, bool value); }; -- cgit v1.2.3 From 6eb486b66a3094cdcd68dc39c9df3a29d6a51dd5 Mon Sep 17 00:00:00 2001 From: Shanker Donthineni Date: Wed, 21 Mar 2018 20:58:49 -0500 Subject: irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling Booting with GICR_CTLR.EnableLPI=1 is usually a bad idea, and may result in subtle memory corruption. Detecting this is thus pretty important. On detecting that LPIs are still enabled, we taint the kernel (because we're not sure of anything anymore), and try to disable LPIs. This can fail, as implementations are allowed to implement GICR_CTLR.EnableLPI as a one-way enable, meaning the redistributors cannot be reprogrammed with new tables. Should this happen, we fail probing the redistributor and warn the user that things are pretty dire. Signed-off-by: Shanker Donthineni [maz: reworded changelog, minor comment and message changes] Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 74 ++++++++++++++++++++++++++++++-------- include/linux/irqchip/arm-gic-v3.h | 1 + 2 files changed, 61 insertions(+), 14 deletions(-) (limited to 'include/linux') diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 2c9006726450..cb952c073d77 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1879,16 +1879,6 @@ static void its_cpu_init_lpis(void) gic_data_rdist()->pend_page = pend_page; } - /* Disable LPIs */ - val = readl_relaxed(rbase + GICR_CTLR); - val &= ~GICR_CTLR_ENABLE_LPIS; - writel_relaxed(val, rbase + GICR_CTLR); - - /* - * Make sure any change to the table is observable by the GIC. - */ - dsb(sy); - /* set PROPBASE */ val = (page_to_phys(gic_rdists->prop_page) | GICR_PROPBASER_InnerShareable | @@ -3403,13 +3393,69 @@ static bool gic_rdists_supports_plpis(void) return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); } +static int redist_disable_lpis(void) +{ + void __iomem *rbase = gic_data_rdist_rd_base(); + u64 timeout = USEC_PER_SEC; + u64 val; + + if (!gic_rdists_supports_plpis()) { + pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); + return -ENXIO; + } + + val = readl_relaxed(rbase + GICR_CTLR); + if (!(val & GICR_CTLR_ENABLE_LPIS)) + return 0; + + pr_warn("CPU%d: Booted with LPIs enabled, memory probably corrupted\n", + smp_processor_id()); + add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); + + /* Disable LPIs */ + val &= ~GICR_CTLR_ENABLE_LPIS; + writel_relaxed(val, rbase + GICR_CTLR); + + /* Make sure any change to GICR_CTLR is observable by the GIC */ + dsb(sy); + + /* + * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs + * from 1 to 0 before programming GICR_PEND{PROP}BASER registers. + * Error out if we time out waiting for RWP to clear. + */ + while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) { + if (!timeout) { + pr_err("CPU%d: Timeout while disabling LPIs\n", + smp_processor_id()); + return -ETIMEDOUT; + } + udelay(1); + timeout--; + } + + /* + * After it has been written to 1, it is IMPLEMENTATION + * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be + * cleared to 0. Error out if clearing the bit failed. + */ + if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) { + pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id()); + return -EBUSY; + } + + return 0; +} + int its_cpu_init(void) { if (!list_empty(&its_nodes)) { - if (!gic_rdists_supports_plpis()) { - pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); - return -ENXIO; - } + int ret; + + ret = redist_disable_lpis(); + if (ret) + return ret; + its_cpu_init_lpis(); its_cpu_init_collections(); } diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 9aacea2aa938..5988473e4abf 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -106,6 +106,7 @@ #define GICR_PIDR2 GICD_PIDR2 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) +#define GICR_CTLR_RWP (1UL << 3) #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) -- cgit v1.2.3 From 21e9b3e931f78497b19b1f8f3d59d19412c1a28f Mon Sep 17 00:00:00 2001 From: Andrew Chant Date: Thu, 22 Mar 2018 14:39:55 -0700 Subject: ALSA: usb-audio: fix uac control query argument This patch fixes code readability and should have no functional change. Correct uac control query functions to account for the 1-based indexing of USB Audio Class control identifiers. The function parameter, u8 control, should be the constant defined in audio-v2.h to identify the control to be checked for readability or writeability. This patch fixes all callers that had adjusted, and makes explicit the mapping between audio_feature_info[] array index and the associated control identifier. Signed-off-by: Andrew Chant Signed-off-by: Takashi Iwai --- include/linux/usb/audio-v2.h | 4 +-- sound/usb/clock.c | 5 ++-- sound/usb/mixer.c | 69 +++++++++++++++++++++++++++----------------- 3 files changed, 48 insertions(+), 30 deletions(-) (limited to 'include/linux') diff --git a/include/linux/usb/audio-v2.h b/include/linux/usb/audio-v2.h index 2db83a191e78..aaafecf073ff 100644 --- a/include/linux/usb/audio-v2.h +++ b/include/linux/usb/audio-v2.h @@ -36,12 +36,12 @@ static inline bool uac_v2v3_control_is_readable(u32 bmControls, u8 control) { - return (bmControls >> (control * 2)) & 0x1; + return (bmControls >> ((control - 1) * 2)) & 0x1; } static inline bool uac_v2v3_control_is_writeable(u32 bmControls, u8 control) { - return (bmControls >> (control * 2)) & 0x2; + return (bmControls >> ((control - 1) * 2)) & 0x2; } /* 4.7.2 Class-Specific AC Interface Descriptor */ diff --git a/sound/usb/clock.c b/sound/usb/clock.c index 25de7fe285d9..ab39ccb974c6 100644 --- a/sound/usb/clock.c +++ b/sound/usb/clock.c @@ -214,7 +214,7 @@ static bool uac_clock_source_is_valid(struct snd_usb_audio *chip, /* If a clock source can't tell us whether it's valid, we assume it is */ if (!uac_v2v3_control_is_readable(bmControls, - UAC2_CS_CONTROL_CLOCK_VALID - 1)) + UAC2_CS_CONTROL_CLOCK_VALID)) return 1; err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR, @@ -552,7 +552,8 @@ static int set_sample_rate_v2v3(struct snd_usb_audio *chip, int iface, bmControls = cs_desc->bmControls; } - writeable = uac_v2v3_control_is_writeable(bmControls, UAC2_CS_CONTROL_SAM_FREQ - 1); + writeable = uac_v2v3_control_is_writeable(bmControls, + UAC2_CS_CONTROL_SAM_FREQ); if (writeable) { data = cpu_to_le32(rate); err = snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), UAC2_CS_CUR, diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index 1c02f7373eda..3075ac50a391 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -879,26 +879,27 @@ static int check_input_term(struct mixer_build *state, int id, /* feature unit control information */ struct usb_feature_control_info { + int control; const char *name; int type; /* data type for uac1 */ int type_uac2; /* data type for uac2 if different from uac1, else -1 */ }; static struct usb_feature_control_info audio_feature_info[] = { - { "Mute", USB_MIXER_INV_BOOLEAN, -1 }, - { "Volume", USB_MIXER_S16, -1 }, - { "Tone Control - Bass", USB_MIXER_S8, -1 }, - { "Tone Control - Mid", USB_MIXER_S8, -1 }, - { "Tone Control - Treble", USB_MIXER_S8, -1 }, - { "Graphic Equalizer", USB_MIXER_S8, -1 }, /* FIXME: not implemeted yet */ - { "Auto Gain Control", USB_MIXER_BOOLEAN, -1 }, - { "Delay Control", USB_MIXER_U16, USB_MIXER_U32 }, - { "Bass Boost", USB_MIXER_BOOLEAN, -1 }, - { "Loudness", USB_MIXER_BOOLEAN, -1 }, + { UAC_FU_MUTE, "Mute", USB_MIXER_INV_BOOLEAN, -1 }, + { UAC_FU_VOLUME, "Volume", USB_MIXER_S16, -1 }, + { UAC_FU_BASS, "Tone Control - Bass", USB_MIXER_S8, -1 }, + { UAC_FU_MID, "Tone Control - Mid", USB_MIXER_S8, -1 }, + { UAC_FU_TREBLE, "Tone Control - Treble", USB_MIXER_S8, -1 }, + { UAC_FU_GRAPHIC_EQUALIZER, "Graphic Equalizer", USB_MIXER_S8, -1 }, /* FIXME: not implemented yet */ + { UAC_FU_AUTOMATIC_GAIN, "Auto Gain Control", USB_MIXER_BOOLEAN, -1 }, + { UAC_FU_DELAY, "Delay Control", USB_MIXER_U16, USB_MIXER_U32 }, + { UAC_FU_BASS_BOOST, "Bass Boost", USB_MIXER_BOOLEAN, -1 }, + { UAC_FU_LOUDNESS, "Loudness", USB_MIXER_BOOLEAN, -1 }, /* UAC2 specific */ - { "Input Gain Control", USB_MIXER_S16, -1 }, - { "Input Gain Pad Control", USB_MIXER_S16, -1 }, - { "Phase Inverter Control", USB_MIXER_BOOLEAN, -1 }, + { UAC2_FU_INPUT_GAIN, "Input Gain Control", USB_MIXER_S16, -1 }, + { UAC2_FU_INPUT_GAIN_PAD, "Input Gain Pad Control", USB_MIXER_S16, -1 }, + { UAC2_FU_PHASE_INVERTER, "Phase Inverter Control", USB_MIXER_BOOLEAN, -1 }, }; /* private_free callback */ @@ -1293,6 +1294,17 @@ static void check_no_speaker_on_headset(struct snd_kcontrol *kctl, strlcpy(kctl->id.name, "Headphone", sizeof(kctl->id.name)); } +static struct usb_feature_control_info *get_feature_control_info(int control) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(audio_feature_info); ++i) { + if (audio_feature_info[i].control == control) + return &audio_feature_info[i]; + } + return NULL; +} + static void build_feature_ctl(struct mixer_build *state, void *raw_desc, unsigned int ctl_mask, int control, struct usb_audio_term *iterm, int unitid, @@ -1308,8 +1320,6 @@ static void build_feature_ctl(struct mixer_build *state, void *raw_desc, const struct usbmix_name_map *map; unsigned int range; - control++; /* change from zero-based to 1-based value */ - if (control == UAC_FU_GRAPHIC_EQUALIZER) { /* FIXME: not supported yet */ return; @@ -1325,7 +1335,10 @@ static void build_feature_ctl(struct mixer_build *state, void *raw_desc, snd_usb_mixer_elem_init_std(&cval->head, state->mixer, unitid); cval->control = control; cval->cmask = ctl_mask; - ctl_info = &audio_feature_info[control-1]; + + ctl_info = get_feature_control_info(control); + if (!ctl_info) + return; if (state->mixer->protocol == UAC_VERSION_1) cval->val_type = ctl_info->type; else /* UAC_VERSION_2 */ @@ -1475,7 +1488,7 @@ static int parse_clock_source_unit(struct mixer_build *state, int unitid, * clock source validity. If that isn't readable, just bail out. */ if (!uac_v2v3_control_is_readable(hdr->bmControls, - ilog2(UAC2_CS_CONTROL_CLOCK_VALID))) + UAC2_CS_CONTROL_CLOCK_VALID)) return 0; cval = kzalloc(sizeof(*cval), GFP_KERNEL); @@ -1491,7 +1504,7 @@ static int parse_clock_source_unit(struct mixer_build *state, int unitid, cval->control = UAC2_CS_CONTROL_CLOCK_VALID; if (uac_v2v3_control_is_writeable(hdr->bmControls, - ilog2(UAC2_CS_CONTROL_CLOCK_VALID))) + UAC2_CS_CONTROL_CLOCK_VALID)) kctl = snd_ctl_new1(&usb_feature_unit_ctl, cval); else { cval->master_readonly = 1; @@ -1625,6 +1638,8 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, /* check all control types */ for (i = 0; i < 10; i++) { unsigned int ch_bits = 0; + int control = audio_feature_info[i].control; + for (j = 0; j < channels; j++) { unsigned int mask; @@ -1640,25 +1655,26 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, * (for ease of programming). */ if (ch_bits & 1) - build_feature_ctl(state, _ftr, ch_bits, i, + build_feature_ctl(state, _ftr, ch_bits, control, &iterm, unitid, 0); if (master_bits & (1 << i)) - build_feature_ctl(state, _ftr, 0, i, &iterm, - unitid, 0); + build_feature_ctl(state, _ftr, 0, control, + &iterm, unitid, 0); } } else { /* UAC_VERSION_2/3 */ for (i = 0; i < ARRAY_SIZE(audio_feature_info); i++) { unsigned int ch_bits = 0; unsigned int ch_read_only = 0; + int control = audio_feature_info[i].control; for (j = 0; j < channels; j++) { unsigned int mask; mask = snd_usb_combine_bytes(bmaControls + csize * (j+1), csize); - if (uac_v2v3_control_is_readable(mask, i)) { + if (uac_v2v3_control_is_readable(mask, control)) { ch_bits |= (1 << j); - if (!uac_v2v3_control_is_writeable(mask, i)) + if (!uac_v2v3_control_is_writeable(mask, control)) ch_read_only |= (1 << j); } } @@ -1677,11 +1693,12 @@ static int parse_audio_feature_unit(struct mixer_build *state, int unitid, * (for ease of programming). */ if (ch_bits & 1) - build_feature_ctl(state, _ftr, ch_bits, i, + build_feature_ctl(state, _ftr, ch_bits, control, &iterm, unitid, ch_read_only); - if (uac_v2v3_control_is_readable(master_bits, i)) + if (uac_v2v3_control_is_readable(master_bits, control)) build_feature_ctl(state, _ftr, 0, i, &iterm, unitid, - !uac_v2v3_control_is_writeable(master_bits, i)); + !uac_v2v3_control_is_writeable(master_bits, + control)); } } -- cgit v1.2.3 From 3ec30113264a7bcd389f51d1738e42da0f41bb5a Mon Sep 17 00:00:00 2001 From: Matthew Garrett Date: Mon, 8 Jan 2018 13:36:19 -0800 Subject: security: Add a cred_getsecid hook For IMA purposes, we want to be able to obtain the prepared secid in the bprm structure before the credentials are committed. Add a cred_getsecid hook that makes this possible. Signed-off-by: Matthew Garrett Acked-by: Paul Moore Cc: Paul Moore Cc: Stephen Smalley Cc: Casey Schaufler Signed-off-by: Mimi Zohar --- include/linux/lsm_hooks.h | 6 ++++++ include/linux/security.h | 1 + security/security.c | 7 +++++++ security/selinux/hooks.c | 6 ++++++ security/smack/smack_lsm.c | 18 ++++++++++++++++++ 5 files changed, 38 insertions(+) (limited to 'include/linux') diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index e0ac011d07a5..bbc6a1240b2e 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -554,6 +554,10 @@ * @new points to the new credentials. * @old points to the original credentials. * Transfer data from original creds to new creds + * @cred_getsecid: + * Retrieve the security identifier of the cred structure @c + * @c contains the credentials, secid will be placed into @secid. + * In case of failure, @secid will be set to zero. * @kernel_act_as: * Set the credentials for a kernel service to act as (subjective context). * @new points to the credentials to be modified. @@ -1542,6 +1546,7 @@ union security_list_options { int (*cred_prepare)(struct cred *new, const struct cred *old, gfp_t gfp); void (*cred_transfer)(struct cred *new, const struct cred *old); + void (*cred_getsecid)(const struct cred *c, u32 *secid); int (*kernel_act_as)(struct cred *new, u32 secid); int (*kernel_create_files_as)(struct cred *new, struct inode *inode); int (*kernel_module_request)(char *kmod_name); @@ -1825,6 +1830,7 @@ struct security_hook_heads { struct list_head cred_free; struct list_head cred_prepare; struct list_head cred_transfer; + struct list_head cred_getsecid; struct list_head kernel_act_as; struct list_head kernel_create_files_as; struct list_head kernel_read_file; diff --git a/include/linux/security.h b/include/linux/security.h index 3f5fd988ee87..116b8717a98c 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -324,6 +324,7 @@ int security_cred_alloc_blank(struct cred *cred, gfp_t gfp); void security_cred_free(struct cred *cred); int security_prepare_creds(struct cred *new, const struct cred *old, gfp_t gfp); void security_transfer_creds(struct cred *new, const struct cred *old); +void security_cred_getsecid(const struct cred *c, u32 *secid); int security_kernel_act_as(struct cred *new, u32 secid); int security_kernel_create_files_as(struct cred *new, struct inode *inode); int security_kernel_module_request(char *kmod_name); diff --git a/security/security.c b/security/security.c index 14c291910d25..957e8bee3554 100644 --- a/security/security.c +++ b/security/security.c @@ -1005,6 +1005,13 @@ void security_transfer_creds(struct cred *new, const struct cred *old) call_void_hook(cred_transfer, new, old); } +void security_cred_getsecid(const struct cred *c, u32 *secid) +{ + *secid = 0; + call_void_hook(cred_getsecid, c, secid); +} +EXPORT_SYMBOL(security_cred_getsecid); + int security_kernel_act_as(struct cred *new, u32 secid) { return call_int_hook(kernel_act_as, 0, new, secid); diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 8abd542c6b7c..b7d4473edbde 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -3844,6 +3844,11 @@ static void selinux_cred_transfer(struct cred *new, const struct cred *old) *tsec = *old_tsec; } +static void selinux_cred_getsecid(const struct cred *c, u32 *secid) +{ + *secid = cred_sid(c); +} + /* * set the security data for a kernel service * - all the creation contexts are set to unlabelled @@ -6482,6 +6487,7 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(cred_free, selinux_cred_free), LSM_HOOK_INIT(cred_prepare, selinux_cred_prepare), LSM_HOOK_INIT(cred_transfer, selinux_cred_transfer), + LSM_HOOK_INIT(cred_getsecid, selinux_cred_getsecid), LSM_HOOK_INIT(kernel_act_as, selinux_kernel_act_as), LSM_HOOK_INIT(kernel_create_files_as, selinux_kernel_create_files_as), LSM_HOOK_INIT(kernel_module_request, selinux_kernel_module_request), diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index feada2665322..ed20d36c1149 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -2049,6 +2049,23 @@ static void smack_cred_transfer(struct cred *new, const struct cred *old) /* cbs copy rule list */ } +/** + * smack_cred_getsecid - get the secid corresponding to a creds structure + * @c: the object creds + * @secid: where to put the result + * + * Sets the secid to contain a u32 version of the smack label. + */ +static void smack_cred_getsecid(const struct cred *c, u32 *secid) +{ + struct smack_known *skp; + + rcu_read_lock(); + skp = smk_of_task(c->security); + *secid = skp->smk_secid; + rcu_read_unlock(); +} + /** * smack_kernel_act_as - Set the subjective context in a set of credentials * @new: points to the set of credentials to be modified. @@ -4733,6 +4750,7 @@ static struct security_hook_list smack_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(cred_free, smack_cred_free), LSM_HOOK_INIT(cred_prepare, smack_cred_prepare), LSM_HOOK_INIT(cred_transfer, smack_cred_transfer), + LSM_HOOK_INIT(cred_getsecid, smack_cred_getsecid), LSM_HOOK_INIT(kernel_act_as, smack_kernel_act_as), LSM_HOOK_INIT(kernel_create_files_as, smack_kernel_create_files_as), LSM_HOOK_INIT(task_setpgid, smack_task_setpgid), -- cgit v1.2.3 From 57b56ac6fecb05c3192586e4892572dd13d972de Mon Sep 17 00:00:00 2001 From: Mimi Zohar Date: Wed, 21 Feb 2018 11:33:37 -0500 Subject: ima: fail file signature verification on non-init mounted filesystems FUSE can be mounted by unprivileged users either today with fusermount installed with setuid, or soon with the upcoming patches to allow FUSE mounts in a non-init user namespace. This patch addresses the new unprivileged non-init mounted filesystems, which are untrusted, by failing the signature verification. This patch defines two new flags SB_I_IMA_UNVERIFIABLE_SIGNATURE and SB_I_UNTRUSTED_MOUNTER. Signed-off-by: Mimi Zohar Cc: Miklos Szeredi Cc: Seth Forshee Cc: Dongsu Park Cc: Alban Crequy Acked-by: Serge Hallyn Acked-by: "Eric W. Biederman" --- include/linux/fs.h | 2 ++ security/integrity/ima/ima_appraise.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/fs.h b/include/linux/fs.h index c6baf767619e..d9e60824c374 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1321,6 +1321,8 @@ extern int send_sigurg(struct fown_struct *fown); /* sb->s_iflags to limit user namespace mounts */ #define SB_I_USERNS_VISIBLE 0x00000010 /* fstype already mounted */ +#define SB_I_IMA_UNVERIFIABLE_SIGNATURE 0x00000020 +#define SB_I_UNTRUSTED_MOUNTER 0x00000040 /* Possible states of 'frozen' field */ enum { diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c index 1b177461f20e..4bafb397ee91 100644 --- a/security/integrity/ima/ima_appraise.c +++ b/security/integrity/ima/ima_appraise.c @@ -302,7 +302,19 @@ int ima_appraise_measurement(enum ima_hooks func, } out: - if (status != INTEGRITY_PASS) { + /* + * File signatures on some filesystems can not be properly verified. + * On these filesytems, that are mounted by an untrusted mounter, + * fail the file signature verification. + */ + if ((inode->i_sb->s_iflags & + (SB_I_IMA_UNVERIFIABLE_SIGNATURE | SB_I_UNTRUSTED_MOUNTER)) == + (SB_I_IMA_UNVERIFIABLE_SIGNATURE | SB_I_UNTRUSTED_MOUNTER)) { + status = INTEGRITY_FAIL; + cause = "unverifiable-signature"; + integrity_audit_msg(AUDIT_INTEGRITY_DATA, inode, filename, + op, cause, rc, 0); + } else if (status != INTEGRITY_PASS) { if ((ima_appraise & IMA_APPRAISE_FIX) && (!xattr_value || xattr_value->type != EVM_IMA_XATTR_DIGSIG)) { @@ -319,6 +331,7 @@ out: } else { ima_cache_flags(iint, func); } + ima_set_cache_status(iint, func, status); return status; } -- cgit v1.2.3 From 1c6ef16d38091a1820e98df25900b5977e404bbd Mon Sep 17 00:00:00 2001 From: Benjamin Tissoires Date: Tue, 20 Mar 2018 12:04:47 +0100 Subject: HID: use BIT macro instead of plain integers for flags This can lead to some hairy situation with the developer losing a day or two realizing that 4 should be after 2, not 3. Signed-off-by: Benjamin Tissoires Reviewed-by: Dmitry Torokhov Acked-by: Peter Hutterer -- include/linux/hid.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) Signed-off-by: Jiri Kosina --- include/linux/hid.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/hid.h b/include/linux/hid.h index 091a81cf330f..d104f2ebc809 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -26,6 +26,7 @@ #define __HID_H +#include #include #include #include @@ -494,13 +495,13 @@ struct hid_output_fifo { char *raw_report; }; -#define HID_CLAIMED_INPUT 1 -#define HID_CLAIMED_HIDDEV 2 -#define HID_CLAIMED_HIDRAW 4 -#define HID_CLAIMED_DRIVER 8 +#define HID_CLAIMED_INPUT BIT(0) +#define HID_CLAIMED_HIDDEV BIT(1) +#define HID_CLAIMED_HIDRAW BIT(2) +#define HID_CLAIMED_DRIVER BIT(3) -#define HID_STAT_ADDED 1 -#define HID_STAT_PARSED 2 +#define HID_STAT_ADDED BIT(0) +#define HID_STAT_PARSED BIT(1) struct hid_input { struct list_head list; -- cgit v1.2.3 From c30e5989d6926c5c1c77c87ed1e54f506e095d74 Mon Sep 17 00:00:00 2001 From: Benjamin Tissoires Date: Tue, 20 Mar 2018 12:04:48 +0100 Subject: HID: use BIT() macro for quirks too This should prevent future mess ups fortunately. Signed-off-by: Benjamin Tissoires Acked-by: Peter Hutterer -- include/linux/hid.h | 52 ++++++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) Signed-off-by: Jiri Kosina --- include/linux/hid.h | 52 ++++++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) (limited to 'include/linux') diff --git a/include/linux/hid.h b/include/linux/hid.h index d104f2ebc809..bc92005e5f08 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -311,13 +311,13 @@ struct hid_item { * HID connect requests */ -#define HID_CONNECT_HIDINPUT 0x01 -#define HID_CONNECT_HIDINPUT_FORCE 0x02 -#define HID_CONNECT_HIDRAW 0x04 -#define HID_CONNECT_HIDDEV 0x08 -#define HID_CONNECT_HIDDEV_FORCE 0x10 -#define HID_CONNECT_FF 0x20 -#define HID_CONNECT_DRIVER 0x40 +#define HID_CONNECT_HIDINPUT BIT(0) +#define HID_CONNECT_HIDINPUT_FORCE BIT(1) +#define HID_CONNECT_HIDRAW BIT(2) +#define HID_CONNECT_HIDDEV BIT(3) +#define HID_CONNECT_HIDDEV_FORCE BIT(4) +#define HID_CONNECT_FF BIT(5) +#define HID_CONNECT_DRIVER BIT(6) #define HID_CONNECT_DEFAULT (HID_CONNECT_HIDINPUT|HID_CONNECT_HIDRAW| \ HID_CONNECT_HIDDEV|HID_CONNECT_FF) @@ -330,25 +330,25 @@ struct hid_item { */ #define MAX_USBHID_BOOT_QUIRKS 4 -#define HID_QUIRK_INVERT 0x00000001 -#define HID_QUIRK_NOTOUCH 0x00000002 -#define HID_QUIRK_IGNORE 0x00000004 -#define HID_QUIRK_NOGET 0x00000008 -#define HID_QUIRK_HIDDEV_FORCE 0x00000010 -#define HID_QUIRK_BADPAD 0x00000020 -#define HID_QUIRK_MULTI_INPUT 0x00000040 -#define HID_QUIRK_HIDINPUT_FORCE 0x00000080 -#define HID_QUIRK_NO_EMPTY_INPUT 0x00000100 -/* 0x00000200 reserved for backward compatibility, was NO_INIT_INPUT_REPORTS */ -#define HID_QUIRK_ALWAYS_POLL 0x00000400 -#define HID_QUIRK_SKIP_OUTPUT_REPORTS 0x00010000 -#define HID_QUIRK_SKIP_OUTPUT_REPORT_ID 0x00020000 -#define HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP 0x00040000 -#define HID_QUIRK_HAVE_SPECIAL_DRIVER 0x00080000 -#define HID_QUIRK_FULLSPEED_INTERVAL 0x10000000 -#define HID_QUIRK_NO_INIT_REPORTS 0x20000000 -#define HID_QUIRK_NO_IGNORE 0x40000000 -#define HID_QUIRK_NO_INPUT_SYNC 0x80000000 +#define HID_QUIRK_INVERT BIT(0) +#define HID_QUIRK_NOTOUCH BIT(1) +#define HID_QUIRK_IGNORE BIT(2) +#define HID_QUIRK_NOGET BIT(3) +#define HID_QUIRK_HIDDEV_FORCE BIT(4) +#define HID_QUIRK_BADPAD BIT(5) +#define HID_QUIRK_MULTI_INPUT BIT(6) +#define HID_QUIRK_HIDINPUT_FORCE BIT(7) +#define HID_QUIRK_NO_EMPTY_INPUT BIT(8) +/* BIT(9) reserved for backward compatibility, was NO_INIT_INPUT_REPORTS */ +#define HID_QUIRK_ALWAYS_POLL BIT(10) +#define HID_QUIRK_SKIP_OUTPUT_REPORTS BIT(16) +#define HID_QUIRK_SKIP_OUTPUT_REPORT_ID BIT(17) +#define HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP BIT(18) +#define HID_QUIRK_HAVE_SPECIAL_DRIVER BIT(19) +#define HID_QUIRK_FULLSPEED_INTERVAL BIT(28) +#define HID_QUIRK_NO_INIT_REPORTS BIT(29) +#define HID_QUIRK_NO_IGNORE BIT(30) +#define HID_QUIRK_NO_INPUT_SYNC BIT(31) /* * HID device groups -- cgit v1.2.3 From 39335d1cbb8fb3260ac5f18fbcc45beb690e5ebd Mon Sep 17 00:00:00 2001 From: Benjamin Tissoires Date: Tue, 20 Mar 2018 12:04:49 +0100 Subject: HID: core: remove the need for HID_QUIRK_NO_EMPTY_INPUT There is no real point of registering an empty input node. This should be default, but given some drivers need the blank input node to set it up during input_configured, we need to postpone the check for hidinput_has_been_populated(). Signed-off-by: Benjamin Tissoires Acked-by: Peter Hutterer Signed-off-by: Jiri Kosina --- drivers/hid/hid-asus.c | 3 +-- drivers/hid/hid-input.c | 10 +++++----- drivers/hid/hid-multitouch.c | 1 - drivers/hid/hid-uclogic.c | 1 - include/linux/hid.h | 2 +- 5 files changed, 7 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/drivers/hid/hid-asus.c b/drivers/hid/hid-asus.c index 88b9703318e4..cc738ebf93ac 100644 --- a/drivers/hid/hid-asus.c +++ b/drivers/hid/hid-asus.c @@ -644,8 +644,7 @@ static int asus_probe(struct hid_device *hdev, const struct hid_device_id *id) * All functionality is on a single HID interface and for * userspace the touchpad must be a separate input_dev. */ - hdev->quirks |= HID_QUIRK_MULTI_INPUT | - HID_QUIRK_NO_EMPTY_INPUT; + hdev->quirks |= HID_QUIRK_MULTI_INPUT; drvdata->tp = &asus_t100chi_tp; } diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c index 04d01b57d94c..b237b5590227 100644 --- a/drivers/hid/hid-input.c +++ b/drivers/hid/hid-input.c @@ -1656,16 +1656,16 @@ int hidinput_connect(struct hid_device *hid, unsigned int force) } list_for_each_entry_safe(hidinput, next, &hid->inputs, list) { - if ((hid->quirks & HID_QUIRK_NO_EMPTY_INPUT) && - !hidinput_has_been_populated(hidinput)) { + if (drv->input_configured && + drv->input_configured(hid, hidinput)) + goto out_unwind; + + if (!hidinput_has_been_populated(hidinput)) { /* no need to register an input device not populated */ hidinput_cleanup_hidinput(hid, hidinput); continue; } - if (drv->input_configured && - drv->input_configured(hid, hidinput)) - goto out_unwind; if (input_register_device(hidinput->input)) goto out_unwind; hidinput->registered = true; diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c index bc724e6b75c9..c4d89830cd1f 100644 --- a/drivers/hid/hid-multitouch.c +++ b/drivers/hid/hid-multitouch.c @@ -1469,7 +1469,6 @@ static int mt_probe(struct hid_device *hdev, const struct hid_device_id *id) * device. */ hdev->quirks |= HID_QUIRK_MULTI_INPUT; - hdev->quirks |= HID_QUIRK_NO_EMPTY_INPUT; /* * Some multitouch screens do not like to be polled for input diff --git a/drivers/hid/hid-uclogic.c b/drivers/hid/hid-uclogic.c index e3e6e5c893cc..56b196d60041 100644 --- a/drivers/hid/hid-uclogic.c +++ b/drivers/hid/hid-uclogic.c @@ -946,7 +946,6 @@ static int uclogic_probe(struct hid_device *hdev, * than the pen, so use QUIRK_MULTI_INPUT for all tablets. */ hdev->quirks |= HID_QUIRK_MULTI_INPUT; - hdev->quirks |= HID_QUIRK_NO_EMPTY_INPUT; /* Allocate and assign driver data */ drvdata = devm_kzalloc(&hdev->dev, sizeof(*drvdata), GFP_KERNEL); diff --git a/include/linux/hid.h b/include/linux/hid.h index bc92005e5f08..b0db16fa7093 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -338,7 +338,7 @@ struct hid_item { #define HID_QUIRK_BADPAD BIT(5) #define HID_QUIRK_MULTI_INPUT BIT(6) #define HID_QUIRK_HIDINPUT_FORCE BIT(7) -#define HID_QUIRK_NO_EMPTY_INPUT BIT(8) +/* BIT(8) reserved for backward compatibility, was HID_QUIRK_NO_EMPTY_INPUT */ /* BIT(9) reserved for backward compatibility, was NO_INIT_INPUT_REPORTS */ #define HID_QUIRK_ALWAYS_POLL BIT(10) #define HID_QUIRK_SKIP_OUTPUT_REPORTS BIT(16) -- cgit v1.2.3 From 5b04cedeca188874d3267bc210ec10c337635ddd Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Thu, 15 Mar 2018 12:05:31 -0500 Subject: bus: fsl-mc: change mc_command in fsl_mc_command The "struct mc_command" is a very generic name for a global kernel structure. Change its name in "struct fsl_mc_command". Signed-off-by: Ioana Ciornei Signed-off-by: Greg Kroah-Hartman --- drivers/bus/fsl-mc/dpbp.c | 12 ++--- drivers/bus/fsl-mc/dpcon.c | 14 +++--- drivers/bus/fsl-mc/dpmcp.c | 6 +-- drivers/bus/fsl-mc/dprc.c | 28 +++++------ drivers/bus/fsl-mc/fsl-mc-bus.c | 2 +- drivers/bus/fsl-mc/mc-sys.c | 20 ++++---- drivers/staging/fsl-dpaa2/ethernet/dpni.c | 84 +++++++++++++++---------------- drivers/staging/fsl-dpaa2/ethsw/dpsw.c | 64 +++++++++++------------ drivers/staging/fsl-mc/bus/dpio/dpio.c | 12 ++--- include/linux/fsl/mc.h | 10 ++-- 10 files changed, 126 insertions(+), 126 deletions(-) (limited to 'include/linux') diff --git a/drivers/bus/fsl-mc/dpbp.c b/drivers/bus/fsl-mc/dpbp.c index 0aeacc5bf461..17e3c5d2f22e 100644 --- a/drivers/bus/fsl-mc/dpbp.c +++ b/drivers/bus/fsl-mc/dpbp.c @@ -31,7 +31,7 @@ int dpbp_open(struct fsl_mc_io *mc_io, int dpbp_id, u16 *token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpbp_cmd_open *cmd_params; int err; @@ -68,7 +68,7 @@ int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags, @@ -91,7 +91,7 @@ int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags, @@ -114,7 +114,7 @@ int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE, @@ -137,7 +137,7 @@ int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET, @@ -163,7 +163,7 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io, u16 token, struct dpbp_attr *attr) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpbp_rsp_get_attributes *rsp_params; int err; diff --git a/drivers/bus/fsl-mc/dpcon.c b/drivers/bus/fsl-mc/dpcon.c index a1ba819449d5..760555d7946e 100644 --- a/drivers/bus/fsl-mc/dpcon.c +++ b/drivers/bus/fsl-mc/dpcon.c @@ -31,7 +31,7 @@ int dpcon_open(struct fsl_mc_io *mc_io, int dpcon_id, u16 *token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpcon_cmd_open *dpcon_cmd; int err; @@ -69,7 +69,7 @@ int dpcon_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE, @@ -93,7 +93,7 @@ int dpcon_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE, @@ -117,7 +117,7 @@ int dpcon_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE, @@ -141,7 +141,7 @@ int dpcon_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET, @@ -166,7 +166,7 @@ int dpcon_get_attributes(struct fsl_mc_io *mc_io, u16 token, struct dpcon_attr *attr) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpcon_rsp_get_attr *dpcon_rsp; int err; @@ -204,7 +204,7 @@ int dpcon_set_notification(struct fsl_mc_io *mc_io, u16 token, struct dpcon_notification_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpcon_cmd_set_notification *dpcon_cmd; /* prepare command */ diff --git a/drivers/bus/fsl-mc/dpmcp.c b/drivers/bus/fsl-mc/dpmcp.c index 8d997b0f6ba3..5fbd0dbde24a 100644 --- a/drivers/bus/fsl-mc/dpmcp.c +++ b/drivers/bus/fsl-mc/dpmcp.c @@ -30,7 +30,7 @@ int dpmcp_open(struct fsl_mc_io *mc_io, int dpmcp_id, u16 *token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpmcp_cmd_open *cmd_params; int err; @@ -66,7 +66,7 @@ int dpmcp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CLOSE, @@ -88,7 +88,7 @@ int dpmcp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPMCP_CMDID_RESET, diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c index 5c23e8d4ddb3..1c3f62182266 100644 --- a/drivers/bus/fsl-mc/dprc.c +++ b/drivers/bus/fsl-mc/dprc.c @@ -24,7 +24,7 @@ int dprc_open(struct fsl_mc_io *mc_io, int container_id, u16 *token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_open *cmd_params; int err; @@ -61,7 +61,7 @@ int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags, @@ -88,7 +88,7 @@ int dprc_set_irq(struct fsl_mc_io *mc_io, u8 irq_index, struct dprc_irq_cfg *irq_cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_set_irq *cmd_params; /* prepare command */ @@ -126,7 +126,7 @@ int dprc_set_irq_enable(struct fsl_mc_io *mc_io, u8 irq_index, u8 en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_set_irq_enable *cmd_params; /* prepare command */ @@ -162,7 +162,7 @@ int dprc_set_irq_mask(struct fsl_mc_io *mc_io, u8 irq_index, u32 mask) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_set_irq_mask *cmd_params; /* prepare command */ @@ -194,7 +194,7 @@ int dprc_get_irq_status(struct fsl_mc_io *mc_io, u8 irq_index, u32 *status) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_get_irq_status *cmd_params; struct dprc_rsp_get_irq_status *rsp_params; int err; @@ -236,7 +236,7 @@ int dprc_clear_irq_status(struct fsl_mc_io *mc_io, u8 irq_index, u32 status) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_clear_irq_status *cmd_params; /* prepare command */ @@ -264,7 +264,7 @@ int dprc_get_attributes(struct fsl_mc_io *mc_io, u16 token, struct dprc_attributes *attr) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_rsp_get_attributes *rsp_params; int err; @@ -302,7 +302,7 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, u16 token, int *obj_count) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_rsp_get_obj_count *rsp_params; int err; @@ -344,7 +344,7 @@ int dprc_get_obj(struct fsl_mc_io *mc_io, int obj_index, struct fsl_mc_obj_desc *obj_desc) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_get_obj *cmd_params; struct dprc_rsp_get_obj *rsp_params; int err; @@ -399,7 +399,7 @@ int dprc_set_obj_irq(struct fsl_mc_io *mc_io, u8 irq_index, struct dprc_irq_cfg *irq_cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_set_obj_irq *cmd_params; /* prepare command */ @@ -440,7 +440,7 @@ int dprc_get_obj_region(struct fsl_mc_io *mc_io, u8 region_index, struct dprc_region_desc *region_desc) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dprc_cmd_get_obj_region *cmd_params; struct dprc_rsp_get_obj_region *rsp_params; int err; @@ -482,7 +482,7 @@ int dprc_get_api_version(struct fsl_mc_io *mc_io, u16 *major_ver, u16 *minor_ver) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; int err; /* prepare command */ @@ -512,7 +512,7 @@ int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; int err; /* prepare command */ diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 1b333c43aae9..5d8266c6571f 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -314,7 +314,7 @@ static int mc_get_version(struct fsl_mc_io *mc_io, u32 cmd_flags, struct mc_version *mc_ver_info) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpmng_rsp_get_version *rsp_params; int err; diff --git a/drivers/bus/fsl-mc/mc-sys.c b/drivers/bus/fsl-mc/mc-sys.c index bd03f1524ecb..3221a7fbaf0a 100644 --- a/drivers/bus/fsl-mc/mc-sys.c +++ b/drivers/bus/fsl-mc/mc-sys.c @@ -28,14 +28,14 @@ #define MC_CMD_COMPLETION_POLLING_MIN_SLEEP_USECS 10 #define MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS 500 -static enum mc_cmd_status mc_cmd_hdr_read_status(struct mc_command *cmd) +static enum mc_cmd_status mc_cmd_hdr_read_status(struct fsl_mc_command *cmd) { struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; return (enum mc_cmd_status)hdr->status; } -static u16 mc_cmd_hdr_read_cmdid(struct mc_command *cmd) +static u16 mc_cmd_hdr_read_cmdid(struct fsl_mc_command *cmd) { struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; u16 cmd_id = le16_to_cpu(hdr->cmd_id); @@ -94,8 +94,8 @@ static const char *mc_status_to_string(enum mc_cmd_status status) * @portal: pointer to an MC portal * @cmd: pointer to a filled command */ -static inline void mc_write_command(struct mc_command __iomem *portal, - struct mc_command *cmd) +static inline void mc_write_command(struct fsl_mc_command __iomem *portal, + struct fsl_mc_command *cmd) { int i; @@ -121,9 +121,9 @@ static inline void mc_write_command(struct mc_command __iomem *portal, * * Returns MC_CMD_STATUS_OK on Success; Error code otherwise. */ -static inline enum mc_cmd_status mc_read_response(struct mc_command __iomem * - portal, - struct mc_command *resp) +static inline enum mc_cmd_status mc_read_response(struct fsl_mc_command __iomem + *portal, + struct fsl_mc_command *resp) { int i; enum mc_cmd_status status; @@ -156,7 +156,7 @@ static inline enum mc_cmd_status mc_read_response(struct mc_command __iomem * * @mc_status: MC command completion status */ static int mc_polling_wait_preemptible(struct fsl_mc_io *mc_io, - struct mc_command *cmd, + struct fsl_mc_command *cmd, enum mc_cmd_status *mc_status) { enum mc_cmd_status status; @@ -202,7 +202,7 @@ static int mc_polling_wait_preemptible(struct fsl_mc_io *mc_io, * @mc_status: MC command completion status */ static int mc_polling_wait_atomic(struct fsl_mc_io *mc_io, - struct mc_command *cmd, + struct fsl_mc_command *cmd, enum mc_cmd_status *mc_status) { enum mc_cmd_status status; @@ -241,7 +241,7 @@ static int mc_polling_wait_atomic(struct fsl_mc_io *mc_io, * * Returns '0' on Success; Error code otherwise. */ -int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd) +int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd) { int error; enum mc_cmd_status status; diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpni.c b/drivers/staging/fsl-dpaa2/ethernet/dpni.c index b16ff5c2f8c1..1a721c95a67a 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpni.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c @@ -122,7 +122,7 @@ int dpni_open(struct fsl_mc_io *mc_io, int dpni_id, u16 *token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_open *cmd_params; int err; @@ -160,7 +160,7 @@ int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE, @@ -188,7 +188,7 @@ int dpni_set_pools(struct fsl_mc_io *mc_io, u16 token, const struct dpni_pools_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_pools *cmd_params; int i; @@ -222,7 +222,7 @@ int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE, @@ -245,7 +245,7 @@ int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE, @@ -270,7 +270,7 @@ int dpni_is_enabled(struct fsl_mc_io *mc_io, u16 token, int *en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_is_enabled *rsp_params; int err; @@ -303,7 +303,7 @@ int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET, @@ -335,7 +335,7 @@ int dpni_set_irq_enable(struct fsl_mc_io *mc_io, u8 irq_index, u8 en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_irq_enable *cmd_params; /* prepare command */ @@ -366,7 +366,7 @@ int dpni_get_irq_enable(struct fsl_mc_io *mc_io, u8 irq_index, u8 *en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_irq_enable *cmd_params; struct dpni_rsp_get_irq_enable *rsp_params; @@ -413,7 +413,7 @@ int dpni_set_irq_mask(struct fsl_mc_io *mc_io, u8 irq_index, u32 mask) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_irq_mask *cmd_params; /* prepare command */ @@ -447,7 +447,7 @@ int dpni_get_irq_mask(struct fsl_mc_io *mc_io, u8 irq_index, u32 *mask) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_irq_mask *cmd_params; struct dpni_rsp_get_irq_mask *rsp_params; int err; @@ -489,7 +489,7 @@ int dpni_get_irq_status(struct fsl_mc_io *mc_io, u8 irq_index, u32 *status) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_irq_status *cmd_params; struct dpni_rsp_get_irq_status *rsp_params; int err; @@ -532,7 +532,7 @@ int dpni_clear_irq_status(struct fsl_mc_io *mc_io, u8 irq_index, u32 status) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_clear_irq_status *cmd_params; /* prepare command */ @@ -561,7 +561,7 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, u16 token, struct dpni_attr *attr) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_attr *rsp_params; int err; @@ -609,7 +609,7 @@ int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, u16 token, struct dpni_error_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_errors_behavior *cmd_params; /* prepare command */ @@ -641,7 +641,7 @@ int dpni_get_buffer_layout(struct fsl_mc_io *mc_io, enum dpni_queue_type qtype, struct dpni_buffer_layout *layout) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_buffer_layout *cmd_params; struct dpni_rsp_get_buffer_layout *rsp_params; int err; @@ -689,7 +689,7 @@ int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, enum dpni_queue_type qtype, const struct dpni_buffer_layout *layout) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_buffer_layout *cmd_params; /* prepare command */ @@ -731,7 +731,7 @@ int dpni_set_offload(struct fsl_mc_io *mc_io, enum dpni_offload type, u32 config) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_offload *cmd_params; cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_OFFLOAD, @@ -750,7 +750,7 @@ int dpni_get_offload(struct fsl_mc_io *mc_io, enum dpni_offload type, u32 *config) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_offload *cmd_params; struct dpni_rsp_get_offload *rsp_params; int err; @@ -792,7 +792,7 @@ int dpni_get_qdid(struct fsl_mc_io *mc_io, enum dpni_queue_type qtype, u16 *qdid) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_qdid *cmd_params; struct dpni_rsp_get_qdid *rsp_params; int err; @@ -830,7 +830,7 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u16 token, u16 *data_offset) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_tx_data_offset *rsp_params; int err; @@ -865,7 +865,7 @@ int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u16 token, const struct dpni_link_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_link_cfg *cmd_params; /* prepare command */ @@ -894,7 +894,7 @@ int dpni_get_link_state(struct fsl_mc_io *mc_io, u16 token, struct dpni_link_state *state) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_link_state *rsp_params; int err; @@ -933,7 +933,7 @@ int dpni_set_max_frame_length(struct fsl_mc_io *mc_io, u16 token, u16 max_frame_length) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_max_frame_length *cmd_params; /* prepare command */ @@ -963,7 +963,7 @@ int dpni_get_max_frame_length(struct fsl_mc_io *mc_io, u16 token, u16 *max_frame_length) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_max_frame_length *rsp_params; int err; @@ -998,7 +998,7 @@ int dpni_set_multicast_promisc(struct fsl_mc_io *mc_io, u16 token, int en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_multicast_promisc *cmd_params; /* prepare command */ @@ -1026,7 +1026,7 @@ int dpni_get_multicast_promisc(struct fsl_mc_io *mc_io, u16 token, int *en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_multicast_promisc *rsp_params; int err; @@ -1061,7 +1061,7 @@ int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io, u16 token, int en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_unicast_promisc *cmd_params; /* prepare command */ @@ -1089,7 +1089,7 @@ int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io, u16 token, int *en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_unicast_promisc *rsp_params; int err; @@ -1124,7 +1124,7 @@ int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, u16 token, const u8 mac_addr[6]) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_primary_mac_addr *cmd_params; int i; @@ -1154,7 +1154,7 @@ int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, u16 token, u8 mac_addr[6]) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_primary_mac_addr *rsp_params; int i, err; @@ -1193,7 +1193,7 @@ int dpni_get_port_mac_addr(struct fsl_mc_io *mc_io, u16 token, u8 mac_addr[6]) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_rsp_get_port_mac_addr *rsp_params; int i, err; @@ -1229,7 +1229,7 @@ int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u16 token, const u8 mac_addr[6]) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_add_mac_addr *cmd_params; int i; @@ -1259,7 +1259,7 @@ int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, u16 token, const u8 mac_addr[6]) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_remove_mac_addr *cmd_params; int i; @@ -1293,7 +1293,7 @@ int dpni_clear_mac_filters(struct fsl_mc_io *mc_io, int unicast, int multicast) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_clear_mac_filters *cmd_params; /* prepare command */ @@ -1327,7 +1327,7 @@ int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io, u8 tc_id, const struct dpni_rx_tc_dist_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_rx_tc_dist *cmd_params; /* prepare command */ @@ -1371,7 +1371,7 @@ int dpni_set_queue(struct fsl_mc_io *mc_io, u8 options, const struct dpni_queue *queue) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_queue *cmd_params; /* prepare command */ @@ -1419,7 +1419,7 @@ int dpni_get_queue(struct fsl_mc_io *mc_io, struct dpni_queue *queue, struct dpni_queue_id *qid) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_queue *cmd_params; struct dpni_rsp_get_queue *rsp_params; int err; @@ -1473,7 +1473,7 @@ int dpni_get_statistics(struct fsl_mc_io *mc_io, u8 page, union dpni_statistics *stat) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_statistics *cmd_params; struct dpni_rsp_get_statistics *rsp_params; int i, err; @@ -1522,7 +1522,7 @@ int dpni_set_taildrop(struct fsl_mc_io *mc_io, u8 index, struct dpni_taildrop *taildrop) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_set_taildrop *cmd_params; /* prepare command */ @@ -1566,7 +1566,7 @@ int dpni_get_taildrop(struct fsl_mc_io *mc_io, u8 index, struct dpni_taildrop *taildrop) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpni_cmd_get_taildrop *cmd_params; struct dpni_rsp_get_taildrop *rsp_params; int err; @@ -1610,7 +1610,7 @@ int dpni_get_api_version(struct fsl_mc_io *mc_io, u16 *minor_ver) { struct dpni_rsp_get_api_version *rsp_params; - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; int err; cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION, diff --git a/drivers/staging/fsl-dpaa2/ethsw/dpsw.c b/drivers/staging/fsl-dpaa2/ethsw/dpsw.c index aefa52ff5818..9b9bc604b461 100644 --- a/drivers/staging/fsl-dpaa2/ethsw/dpsw.c +++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw.c @@ -43,7 +43,7 @@ int dpsw_open(struct fsl_mc_io *mc_io, int dpsw_id, u16 *token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_open *cmd_params; int err; @@ -80,7 +80,7 @@ int dpsw_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLOSE, @@ -103,7 +103,7 @@ int dpsw_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ENABLE, @@ -126,7 +126,7 @@ int dpsw_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPSW_CMDID_DISABLE, @@ -149,7 +149,7 @@ int dpsw_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPSW_CMDID_RESET, @@ -181,7 +181,7 @@ int dpsw_set_irq_enable(struct fsl_mc_io *mc_io, u8 irq_index, u8 en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_set_irq_enable *cmd_params; /* prepare command */ @@ -218,7 +218,7 @@ int dpsw_set_irq_mask(struct fsl_mc_io *mc_io, u8 irq_index, u32 mask) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_set_irq_mask *cmd_params; /* prepare command */ @@ -251,7 +251,7 @@ int dpsw_get_irq_status(struct fsl_mc_io *mc_io, u8 irq_index, u32 *status) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_get_irq_status *cmd_params; struct dpsw_rsp_get_irq_status *rsp_params; int err; @@ -294,7 +294,7 @@ int dpsw_clear_irq_status(struct fsl_mc_io *mc_io, u8 irq_index, u32 status) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_clear_irq_status *cmd_params; /* prepare command */ @@ -323,7 +323,7 @@ int dpsw_get_attributes(struct fsl_mc_io *mc_io, u16 token, struct dpsw_attr *attr) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_rsp_get_attr *rsp_params; int err; @@ -373,7 +373,7 @@ int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io, u16 if_id, struct dpsw_link_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_set_link_cfg *cmd_params; /* prepare command */ @@ -405,7 +405,7 @@ int dpsw_if_get_link_state(struct fsl_mc_io *mc_io, u16 if_id, struct dpsw_link_state *state) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_get_link_state *cmd_params; struct dpsw_rsp_if_get_link_state *rsp_params; int err; @@ -447,7 +447,7 @@ int dpsw_if_set_flooding(struct fsl_mc_io *mc_io, u16 if_id, u8 en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_set_flooding *cmd_params; /* prepare command */ @@ -478,7 +478,7 @@ int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io, u16 if_id, u8 en) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_set_broadcast *cmd_params; /* prepare command */ @@ -509,7 +509,7 @@ int dpsw_if_set_tci(struct fsl_mc_io *mc_io, u16 if_id, const struct dpsw_tci_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_set_tci *cmd_params; u16 tmp_conf = 0; @@ -547,7 +547,7 @@ int dpsw_if_set_stp(struct fsl_mc_io *mc_io, u16 if_id, const struct dpsw_stp_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_set_stp *cmd_params; /* prepare command */ @@ -581,7 +581,7 @@ int dpsw_if_get_counter(struct fsl_mc_io *mc_io, enum dpsw_counter type, u64 *counter) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_get_counter *cmd_params; struct dpsw_rsp_if_get_counter *rsp_params; int err; @@ -620,7 +620,7 @@ int dpsw_if_enable(struct fsl_mc_io *mc_io, u16 token, u16 if_id) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if *cmd_params; /* prepare command */ @@ -648,7 +648,7 @@ int dpsw_if_disable(struct fsl_mc_io *mc_io, u16 token, u16 if_id) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if *cmd_params; /* prepare command */ @@ -678,7 +678,7 @@ int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io, u16 if_id, u16 frame_length) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_if_set_max_frame_length *cmd_params; /* prepare command */ @@ -716,7 +716,7 @@ int dpsw_vlan_add(struct fsl_mc_io *mc_io, u16 vlan_id, const struct dpsw_vlan_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_vlan_add *cmd_params; /* prepare command */ @@ -752,7 +752,7 @@ int dpsw_vlan_add_if(struct fsl_mc_io *mc_io, u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_vlan_manage_if *cmd_params; /* prepare command */ @@ -790,7 +790,7 @@ int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io, u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_vlan_manage_if *cmd_params; /* prepare command */ @@ -824,7 +824,7 @@ int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io, u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_vlan_manage_if *cmd_params; /* prepare command */ @@ -860,7 +860,7 @@ int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io, u16 vlan_id, const struct dpsw_vlan_if_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_vlan_manage_if *cmd_params; /* prepare command */ @@ -889,7 +889,7 @@ int dpsw_vlan_remove(struct fsl_mc_io *mc_io, u16 token, u16 vlan_id) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_vlan_remove *cmd_params; /* prepare command */ @@ -919,7 +919,7 @@ int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io, u16 fdb_id, const struct dpsw_fdb_unicast_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_fdb_unicast_op *cmd_params; int i; @@ -954,7 +954,7 @@ int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io, u16 fdb_id, const struct dpsw_fdb_unicast_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_fdb_unicast_op *cmd_params; int i; @@ -996,7 +996,7 @@ int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io, u16 fdb_id, const struct dpsw_fdb_multicast_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_fdb_multicast_op *cmd_params; int i; @@ -1038,7 +1038,7 @@ int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io, u16 fdb_id, const struct dpsw_fdb_multicast_cfg *cfg) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_fdb_multicast_op *cmd_params; int i; @@ -1074,7 +1074,7 @@ int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io, u16 fdb_id, enum dpsw_fdb_learning_mode mode) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_cmd_fdb_set_learning_mode *cmd_params; /* prepare command */ @@ -1103,7 +1103,7 @@ int dpsw_get_api_version(struct fsl_mc_io *mc_io, u16 *major_ver, u16 *minor_ver) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpsw_rsp_get_api_version *rsp_params; int err; diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio.c b/drivers/staging/fsl-mc/bus/dpio/dpio.c index 3175057e0265..ff37c80e11a0 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio.c +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c @@ -37,7 +37,7 @@ int dpio_open(struct fsl_mc_io *mc_io, int dpio_id, u16 *token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpio_cmd_open *dpio_cmd; int err; @@ -70,7 +70,7 @@ int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE, @@ -92,7 +92,7 @@ int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE, @@ -114,7 +114,7 @@ int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE, @@ -138,7 +138,7 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io, u16 token, struct dpio_attr *attr) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; struct dpio_rsp_get_attr *dpio_rsp; int err; @@ -180,7 +180,7 @@ int dpio_get_api_version(struct fsl_mc_io *mc_io, u16 *major_ver, u16 *minor_ver) { - struct mc_command cmd = { 0 }; + struct fsl_mc_command cmd = { 0 }; int err; /* prepare command */ diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h index cfb1fbf3a882..f27cb14088a4 100644 --- a/include/linux/fsl/mc.h +++ b/include/linux/fsl/mc.h @@ -209,7 +209,7 @@ struct mc_cmd_header { __le16 cmd_id; }; -struct mc_command { +struct fsl_mc_command { u64 header; u64 params[MC_CMD_NUM_OF_PARAMS]; }; @@ -256,7 +256,7 @@ static inline u64 mc_encode_cmd_header(u16 cmd_id, return header; } -static inline u16 mc_cmd_hdr_read_token(struct mc_command *cmd) +static inline u16 mc_cmd_hdr_read_token(struct fsl_mc_command *cmd) { struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; u16 token = le16_to_cpu(hdr->token); @@ -273,7 +273,7 @@ struct mc_rsp_api_ver { __le16 minor_ver; }; -static inline u32 mc_cmd_read_object_id(struct mc_command *cmd) +static inline u32 mc_cmd_read_object_id(struct fsl_mc_command *cmd) { struct mc_rsp_create *rsp_params; @@ -281,7 +281,7 @@ static inline u32 mc_cmd_read_object_id(struct mc_command *cmd) return le32_to_cpu(rsp_params->object_id); } -static inline void mc_cmd_read_api_version(struct mc_command *cmd, +static inline void mc_cmd_read_api_version(struct fsl_mc_command *cmd, u16 *major_ver, u16 *minor_ver) { @@ -342,7 +342,7 @@ struct fsl_mc_io { }; }; -int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); +int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd); #ifdef CONFIG_FSL_MC_BUS #define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type) -- cgit v1.2.3 From 0063ec4459dcf1583c7aa84ada0f7125450d9245 Mon Sep 17 00:00:00 2001 From: Gary R Hook Date: Wed, 14 Mar 2018 17:15:52 -0500 Subject: crypto: doc - Document remaining members in struct crypto_alg Add missing comments for union members ablkcipher, blkcipher, cipher, and compress. This silences complaints when building the htmldocs. Fixes: 0d7f488f0305a (crypto: doc - cipher data structures) Signed-off-by: Gary R Hook Signed-off-by: Herbert Xu --- include/linux/crypto.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/linux') diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 7e6e84cf6383..6eb06101089f 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -435,6 +435,14 @@ struct compress_alg { * @cra_exit: Deinitialize the cryptographic transformation object. This is a * counterpart to @cra_init, used to remove various changes set in * @cra_init. + * @cra_u.ablkcipher: Union member which contains an asynchronous block cipher + * definition. See @struct @ablkcipher_alg. + * @cra_u.blkcipher: Union member which contains a synchronous block cipher + * definition See @struct @blkcipher_alg. + * @cra_u.cipher: Union member which contains a single-block symmetric cipher + * definition. See @struct @cipher_alg. + * @cra_u.compress: Union member which contains a (de)compression algorithm. + * See @struct @compress_alg. * @cra_module: Owner of this transformation implementation. Set to THIS_MODULE * @cra_list: internally used * @cra_users: internally used -- cgit v1.2.3 From d726f6b1997528354e1053accbb6223981e81802 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Tue, 13 Feb 2018 22:09:34 +0000 Subject: platform/x86: mlx-platform: Add deffered bus functionality mlx-platform activates i2c-mux-reg, which creates buses needed by mlxreg-hotplug. If the mlxreg-hotplug probe runs before the i2c-mux-reg probe completes, it may attempt to connect a device to an adapter number that has not been created yet, and fail. Make mlx-platform driver record the highest bus number in mlxreg-hotplug platform data and defer mlxreg-hotplug probe until all the buses are created. Signed-off-by: Vadim Pasternak [dvhart: rewrite commit message more concisely] Signed-off-by: Darren Hart (VMware) --- drivers/platform/mellanox/mlxreg-hotplug.c | 7 +++++++ drivers/platform/x86/mlx-platform.c | 10 ++++++++++ include/linux/platform_data/mlxreg.h | 2 ++ 3 files changed, 19 insertions(+) (limited to 'include/linux') diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c index 313cf8ad77bf..fe4910bc0f96 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -550,6 +550,7 @@ static int mlxreg_hotplug_probe(struct platform_device *pdev) { struct mlxreg_core_hotplug_platform_data *pdata; struct mlxreg_hotplug_priv_data *priv; + struct i2c_adapter *deferred_adap; int err; pdata = dev_get_platdata(&pdev->dev); @@ -558,6 +559,12 @@ static int mlxreg_hotplug_probe(struct platform_device *pdev) return -EINVAL; } + /* Defer probing if the necessary adapter is not configured yet. */ + deferred_adap = i2c_get_adapter(pdata->deferred_nr); + if (!deferred_adap) + return -EPROBE_DEFER; + i2c_put_adapter(deferred_adap); + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 71b452a89a6e..67f3c6d36988 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -697,6 +697,8 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_default_channels[i]); } mlxplat_hotplug = &mlxplat_mlxcpld_default_data; + mlxplat_hotplug->deferred_nr = + mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -711,6 +713,8 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -725,6 +729,8 @@ static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -739,6 +745,8 @@ static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; + mlxplat_hotplug->deferred_nr = + mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -753,6 +761,8 @@ static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index fcdc707eab99..262910967476 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -129,6 +129,7 @@ struct mlxreg_core_platform_data { * @mask: top aggregation interrupt common mask; * @cell_low: location of low aggregation interrupt register; * @mask_low: low aggregation interrupt common mask; + * @deferred_nr: I2C adapter number must be exist prior probing execution; */ struct mlxreg_core_hotplug_platform_data { struct mlxreg_core_item *items; @@ -139,6 +140,7 @@ struct mlxreg_core_hotplug_platform_data { u32 mask; u32 cell_low; u32 mask_low; + int deferred_nr; }; #endif /* __LINUX_PLATFORM_DATA_MLXREG_H */ -- cgit v1.2.3 From ef0f62264b2a9e6fc73476ed22ade1ff1f3ad7f3 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Tue, 13 Feb 2018 22:09:36 +0000 Subject: platform/x86: mlx-platform: Add physical bus number auto detection mlx-platform does not provide a bus number to i2c-mlxcpld, assuming it is always one. On some x86 systems, other i2c drivers may probe before i2c-mlxcpld, causing bus one to be busy. Make mlx-platform determine which adapter number is free prior to activating i2c-mlxpld, adjusting the mux base numbers accordingly. Update the mlxreg-hotplug pdata similarly. This adds an explicit mlx-platform build dependency on I2C, update the Kconfig accordingly. Add the missing REGMAP dependency while we're at it. Signed-off-by: Vadim Pasternak [dvhart: Rewrite commit message more concisely] [dvhart: Add build dependencies] Signed-off-by: Darren Hart (VMware) --- drivers/platform/mellanox/mlxreg-hotplug.c | 12 ++++--- drivers/platform/x86/Kconfig | 1 + drivers/platform/x86/mlx-platform.c | 53 ++++++++++++++++++++++++++++-- include/linux/platform_data/mlxreg.h | 2 ++ 4 files changed, 62 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c index c1e1c4f254ce..ea9e7f4479ca 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -96,6 +96,8 @@ struct mlxreg_hotplug_priv_data { static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, struct mlxreg_core_data *data) { + struct mlxreg_core_hotplug_platform_data *pdata; + /* * Return if adapter number is negative. It could be in case hotplug * event is not associated with hotplug device. @@ -103,10 +105,12 @@ static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, if (data->hpdev.nr < 0) return 0; - data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr); + pdata = dev_get_platdata(&priv->pdev->dev); + data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr + + pdata->shift_nr); if (!data->hpdev.adapter) { dev_err(priv->dev, "Failed to get adapter for bus %d\n", - data->hpdev.nr); + data->hpdev.nr + pdata->shift_nr); return -EFAULT; } @@ -114,8 +118,8 @@ static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, data->hpdev.brdinfo); if (!data->hpdev.client) { dev_err(priv->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", - data->hpdev.brdinfo->type, data->hpdev.nr, - data->hpdev.brdinfo->addr); + data->hpdev.brdinfo->type, data->hpdev.nr + + pdata->shift_nr, data->hpdev.brdinfo->addr); i2c_put_adapter(data->hpdev.adapter); data->hpdev.adapter = NULL; diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index 1868aab0282a..b528e44ad8ae 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1175,6 +1175,7 @@ config INTEL_TELEMETRY config MLX_PLATFORM tristate "Mellanox Technologies platform support" + depends on I2C && REGMAP ---help--- This option enables system support for the Mellanox Technologies platform. The Mellanox systems provide data center networking diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 67f3c6d36988..7a0bd24c1ae2 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -85,6 +85,12 @@ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0) +/* Default I2C parent bus number */ +#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 + +/* Maximum number of possible physical buses equipped on system */ +#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 + /* Number of channels in group */ #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 @@ -843,10 +849,48 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); +static int mlxplat_mlxcpld_verify_bus_topology(int *nr) +{ + struct i2c_adapter *search_adap; + int shift, i; + + /* Scan adapters from expected id to verify it is free. */ + *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; + for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < + MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; i++) { + search_adap = i2c_get_adapter(i); + if (search_adap) { + i2c_put_adapter(search_adap); + continue; + } + + /* Return if expected parent adapter is free. */ + if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) + return 0; + break; + } + + /* Return with error if free id for adapter is not found. */ + if (i == MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM) + return -ENODEV; + + /* Shift adapter ids, since expected parent adapter is not free. */ + *nr = i; + for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) { + shift = *nr - mlxplat_mux_data[i].parent; + mlxplat_mux_data[i].parent = *nr; + mlxplat_mux_data[i].base_nr += shift; + if (shift > 0) + mlxplat_hotplug->shift_nr = shift; + } + + return 0; +} + static int __init mlxplat_init(void) { struct mlxplat_priv *priv; - int i, err; + int i, nr, err; if (!dmi_check_system(mlxplat_dmi_table)) return -ENODEV; @@ -866,7 +910,12 @@ static int __init mlxplat_init(void) } platform_set_drvdata(mlxplat_dev, priv); - priv->pdev_i2c = platform_device_register_simple("i2c_mlxcpld", -1, + err = mlxplat_mlxcpld_verify_bus_topology(&nr); + if (nr < 0) + goto fail_alloc; + + nr = (nr == MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM) ? -1 : nr; + priv->pdev_i2c = platform_device_register_simple("i2c_mlxcpld", nr, NULL, 0); if (IS_ERR(priv->pdev_i2c)) { err = PTR_ERR(priv->pdev_i2c); diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 262910967476..2744cff1b297 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -130,6 +130,7 @@ struct mlxreg_core_platform_data { * @cell_low: location of low aggregation interrupt register; * @mask_low: low aggregation interrupt common mask; * @deferred_nr: I2C adapter number must be exist prior probing execution; + * @shift_nr: I2C adapter numbers must be incremented by this value; */ struct mlxreg_core_hotplug_platform_data { struct mlxreg_core_item *items; @@ -141,6 +142,7 @@ struct mlxreg_core_hotplug_platform_data { u32 cell_low; u32 mask_low; int deferred_nr; + int shift_nr; }; #endif /* __LINUX_PLATFORM_DATA_MLXREG_H */ -- cgit v1.2.3 From eb49778c8c6cbe075cf90d741ccf16f674a8db4e Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 5 Jul 2017 22:13:58 +1200 Subject: i2c: pca-platform: drop gpio from platform data Now that the i2c-pca-plaform driver is using the device managed API for gpios there is no need for the reset gpio to be specified via i2c_pca9564_pf_platform_data. Signed-off-by: Chris Packham Signed-off-by: Wolfram Sang --- arch/blackfin/mach-bf561/boards/acvilon.c | 1 - arch/sh/boards/board-sh7785lcr.c | 1 - include/linux/i2c-pca-platform.h | 3 --- 3 files changed, 5 deletions(-) (limited to 'include/linux') diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c index 696cc9d7820a..9dd612220211 100644 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ b/arch/blackfin/mach-bf561/boards/acvilon.c @@ -112,7 +112,6 @@ static struct resource bfin_i2c_pca_resources[] = { }; struct i2c_pca9564_pf_platform_data pca9564_platform_data = { - .gpio = -1, .i2c_clock_speed = 330000, .timeout = HZ, }; diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index caec1ebffb09..d7d232dea33e 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -253,7 +253,6 @@ static struct gpiod_lookup_table i2c_gpio_table = { }; static struct i2c_pca9564_pf_platform_data i2c_platform_data = { - .gpio = 0, .i2c_clock_speed = I2C_PCA_CON_330kHz, .timeout = HZ, }; diff --git a/include/linux/i2c-pca-platform.h b/include/linux/i2c-pca-platform.h index 0e5f7c77d1d8..c37329432a8e 100644 --- a/include/linux/i2c-pca-platform.h +++ b/include/linux/i2c-pca-platform.h @@ -3,9 +3,6 @@ #define I2C_PCA9564_PLATFORM_H struct i2c_pca9564_pf_platform_data { - int gpio; /* pin to reset chip. driver will work when - * not supplied (negative value), but it - * cannot exit some error conditions then */ int i2c_clock_speed; /* values are defined in linux/i2c-algo-pca.h */ int timeout; /* timeout in jiffies */ }; -- cgit v1.2.3 From a2e102cd3cdd8b7a14e08716510707b15802073f Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 22 Mar 2018 21:34:44 -0500 Subject: shm: Move struct shmid_kernel into ipc/shm.c All of the users are now in ipc/shm.c so make the definition local to that file to make code maintenance easier. AKA to prevent rebuilding the entire kernel when struct shmid_kernel changes. Signed-off-by: "Eric W. Biederman" --- include/linux/shm.h | 22 ---------------------- ipc/shm.c | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 22 deletions(-) (limited to 'include/linux') diff --git a/include/linux/shm.h b/include/linux/shm.h index 2bbafacfbfc9..3a8eae3ca33c 100644 --- a/include/linux/shm.h +++ b/include/linux/shm.h @@ -7,28 +7,6 @@ #include #include -struct shmid_kernel /* private to the kernel */ -{ - struct kern_ipc_perm shm_perm; - struct file *shm_file; - unsigned long shm_nattch; - unsigned long shm_segsz; - time64_t shm_atim; - time64_t shm_dtim; - time64_t shm_ctim; - pid_t shm_cprid; - pid_t shm_lprid; - struct user_struct *mlock_user; - - /* The task created the shm object. NULL if the task is dead. */ - struct task_struct *shm_creator; - struct list_head shm_clist; /* list by creator */ -} __randomize_layout; - -/* shm_mode upper byte flags */ -#define SHM_DEST 01000 /* segment will be destroyed on last detach */ -#define SHM_LOCKED 02000 /* segment will not be swapped */ - #ifdef CONFIG_SYSVIPC struct sysv_shm { struct list_head shm_clist; diff --git a/ipc/shm.c b/ipc/shm.c index 387a786e7be1..0565669ebe5c 100644 --- a/ipc/shm.c +++ b/ipc/shm.c @@ -48,6 +48,28 @@ #include "util.h" +struct shmid_kernel /* private to the kernel */ +{ + struct kern_ipc_perm shm_perm; + struct file *shm_file; + unsigned long shm_nattch; + unsigned long shm_segsz; + time64_t shm_atim; + time64_t shm_dtim; + time64_t shm_ctim; + pid_t shm_cprid; + pid_t shm_lprid; + struct user_struct *mlock_user; + + /* The task created the shm object. NULL if the task is dead. */ + struct task_struct *shm_creator; + struct list_head shm_clist; /* list by creator */ +} __randomize_layout; + +/* shm_mode upper byte flags */ +#define SHM_DEST 01000 /* segment will be destroyed on last detach */ +#define SHM_LOCKED 02000 /* segment will not be swapped */ + struct shm_file_data { int id; struct ipc_namespace *ns; -- cgit v1.2.3 From 34b56df922b10ac2876f268c522951785bf333fd Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 22 Mar 2018 21:37:34 -0500 Subject: msg: Move struct msg_queue into ipc/msg.c All of the users are now in ipc/msg.c so make the definition local to that file to make code maintenance easier. AKA to prevent rebuilding the entire kernel when struct msg_queue changes. Signed-off-by: "Eric W. Biederman" --- include/linux/msg.h | 18 ------------------ ipc/msg.c | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 18 deletions(-) (limited to 'include/linux') diff --git a/include/linux/msg.h b/include/linux/msg.h index 0a7eefeee0d1..9a972a296b95 100644 --- a/include/linux/msg.h +++ b/include/linux/msg.h @@ -3,7 +3,6 @@ #define _LINUX_MSG_H #include -#include #include /* one msg_msg structure for each message */ @@ -16,21 +15,4 @@ struct msg_msg { /* the actual message follows immediately */ }; -/* one msq_queue structure for each present queue on the system */ -struct msg_queue { - struct kern_ipc_perm q_perm; - time64_t q_stime; /* last msgsnd time */ - time64_t q_rtime; /* last msgrcv time */ - time64_t q_ctime; /* last change time */ - unsigned long q_cbytes; /* current number of bytes on queue */ - unsigned long q_qnum; /* number of messages in queue */ - unsigned long q_qbytes; /* max number of bytes on queue */ - pid_t q_lspid; /* pid of last msgsnd */ - pid_t q_lrpid; /* last receive pid */ - - struct list_head q_messages; - struct list_head q_receivers; - struct list_head q_senders; -} __randomize_layout; - #endif /* _LINUX_MSG_H */ diff --git a/ipc/msg.c b/ipc/msg.c index cdfab0825fce..af5a963306c4 100644 --- a/ipc/msg.c +++ b/ipc/msg.c @@ -43,6 +43,23 @@ #include #include "util.h" +/* one msq_queue structure for each present queue on the system */ +struct msg_queue { + struct kern_ipc_perm q_perm; + time64_t q_stime; /* last msgsnd time */ + time64_t q_rtime; /* last msgrcv time */ + time64_t q_ctime; /* last change time */ + unsigned long q_cbytes; /* current number of bytes on queue */ + unsigned long q_qnum; /* number of messages in queue */ + unsigned long q_qbytes; /* max number of bytes on queue */ + pid_t q_lspid; /* pid of last msgsnd */ + pid_t q_lrpid; /* last receive pid */ + + struct list_head q_messages; + struct list_head q_receivers; + struct list_head q_senders; +} __randomize_layout; + /* one msg_receiver structure for each sleeping receiver */ struct msg_receiver { struct list_head r_list; -- cgit v1.2.3 From f83a396d06d499029fe6d32e326605a2b5ca4eff Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 22 Mar 2018 21:45:50 -0500 Subject: ipc: Move IPCMNI from include/ipc.h into ipc/util.h The definition IPCMNI is only used in ipc/util.h and ipc/util.c. So there is no reason to keep it in a header file that the whole kernel can see. Move it into util.h to simplify future maintenance. Signed-off-by: "Eric W. Biederman" --- include/linux/ipc.h | 2 -- ipc/util.h | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/ipc.h b/include/linux/ipc.h index 821b2f260992..6cc2df7f7ac9 100644 --- a/include/linux/ipc.h +++ b/include/linux/ipc.h @@ -8,8 +8,6 @@ #include #include -#define IPCMNI 32768 /* <= MAX_INT limit for ipc arrays (including sysctl changes) */ - /* used by in-kernel data structures */ struct kern_ipc_perm { spinlock_t lock; diff --git a/ipc/util.h b/ipc/util.h index 89b8ec176fc4..959c10eb9cc1 100644 --- a/ipc/util.h +++ b/ipc/util.h @@ -15,6 +15,7 @@ #include #include +#define IPCMNI 32768 /* <= MAX_INT limit for ipc arrays (including sysctl changes) */ #define SEQ_MULTIPLIER (IPCMNI) int sem_init(void); -- cgit v1.2.3 From 819671ff849b07b9831b91de879ddc5da4b333d4 Mon Sep 17 00:00:00 2001 From: Dominik Brodowski Date: Sun, 11 Mar 2018 11:34:25 +0100 Subject: syscalls: define and explain goal to not call syscalls in the kernel The syscall entry points to the kernel defined by SYSCALL_DEFINEx() and COMPAT_SYSCALL_DEFINEx() should only be called from userspace through kernel entry points, but not from the kernel itself. This will allow cleanups and optimizations to the entry paths *and* to the parts of the kernel code which currently need to pretend to be userspace in order to make use of syscalls. Signed-off-by: Dominik Brodowski --- Documentation/process/adding-syscalls.rst | 32 +++++++++++++++++++++++++++++++ include/linux/syscalls.h | 7 +++++++ 2 files changed, 39 insertions(+) (limited to 'include/linux') diff --git a/Documentation/process/adding-syscalls.rst b/Documentation/process/adding-syscalls.rst index 8cc25a06f353..556613744556 100644 --- a/Documentation/process/adding-syscalls.rst +++ b/Documentation/process/adding-syscalls.rst @@ -487,6 +487,38 @@ patchset, for the convenience of reviewers. The man page should be cc'ed to linux-man@vger.kernel.org For more details, see https://www.kernel.org/doc/man-pages/patches.html + +Do not call System Calls in the Kernel +-------------------------------------- + +System calls are, as stated above, interaction points between userspace and +the kernel. Therefore, system call functions such as ``sys_xyzzy()`` or +``compat_sys_xyzzy()`` should only be called from userspace via the syscall +table, but not from elsewhere in the kernel. If the syscall functionality is +useful to be used within the kernel, needs to be shared between an old and a +new syscall, or needs to be shared between a syscall and its compatibility +variant, it should be implemented by means of a "helper" function (such as +``kern_xyzzy()``). This kernel function may then be called within the +syscall stub (``sys_xyzzy()``), the compatibility syscall stub +(``compat_sys_xyzzy()``), and/or other kernel code. + +At least on 64-bit x86, it will be a hard requirement from v4.17 onwards to not +call system call functions in the kernel. It uses a different calling +convention for system calls where ``struct pt_regs`` is decoded on-the-fly in a +syscall wrapper which then hands processing over to the actual syscall function. +This means that only those parameters which are actually needed for a specific +syscall are passed on during syscall entry, instead of filling in six CPU +registers with random user space content all the time (which may cause serious +trouble down the call chain). + +Moreover, rules on how data may be accessed may differ between kernel data and +user data. This is another reason why calling ``sys_xyzzy()`` is generally a +bad idea. + +Exceptions to this rule are only allowed in architecture-specific overrides, +architecture-specific compatibility wrappers, or other code in arch/. + + References and Sources ---------------------- diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index a78186d826d7..0526286a0314 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -941,4 +941,11 @@ asmlinkage long sys_pkey_free(int pkey); asmlinkage long sys_statx(int dfd, const char __user *path, unsigned flags, unsigned mask, struct statx __user *buffer); + +/* + * Kernel code should not call syscalls (i.e., sys_xyzyyz()) directly. + * Instead, use one of the functions which work equivalently, such as + * the ksys_xyzyyz() functions prototyped below. + */ + #endif -- cgit v1.2.3 From b9193c1b61ddb97da4713155b0d580e41fb544ac Mon Sep 17 00:00:00 2001 From: Martin KaFai Lau Date: Sat, 24 Mar 2018 11:44:22 -0700 Subject: bpf: Rename bpf_verifer_log bpf_verifer_log => bpf_verifier_log Signed-off-by: Martin KaFai Lau Acked-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/bpf_verifier.h | 6 +++--- kernel/bpf/verifier.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h index 6b66cd1aa0b9..c30668414b22 100644 --- a/include/linux/bpf_verifier.h +++ b/include/linux/bpf_verifier.h @@ -153,7 +153,7 @@ struct bpf_insn_aux_data { #define BPF_VERIFIER_TMP_LOG_SIZE 1024 -struct bpf_verifer_log { +struct bpf_verifier_log { u32 level; char kbuf[BPF_VERIFIER_TMP_LOG_SIZE]; char __user *ubuf; @@ -161,7 +161,7 @@ struct bpf_verifer_log { u32 len_total; }; -static inline bool bpf_verifier_log_full(const struct bpf_verifer_log *log) +static inline bool bpf_verifier_log_full(const struct bpf_verifier_log *log) { return log->len_used >= log->len_total - 1; } @@ -185,7 +185,7 @@ struct bpf_verifier_env { bool allow_ptr_leaks; bool seen_direct_write; struct bpf_insn_aux_data *insn_aux_data; /* array of per-insn state */ - struct bpf_verifer_log log; + struct bpf_verifier_log log; u32 subprog_starts[BPF_MAX_SUBPROGS]; /* computes the stack depth of each bpf function */ u16 subprog_stack_depth[BPF_MAX_SUBPROGS + 1]; diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index e93a6e48641b..1e84e02ff733 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -171,7 +171,7 @@ static DEFINE_MUTEX(bpf_verifier_lock); static void log_write(struct bpf_verifier_env *env, const char *fmt, va_list args) { - struct bpf_verifer_log *log = &env->log; + struct bpf_verifier_log *log = &env->log; unsigned int n; if (!log->level || !log->ubuf || bpf_verifier_log_full(log)) @@ -5611,7 +5611,7 @@ static void free_states(struct bpf_verifier_env *env) int bpf_check(struct bpf_prog **prog, union bpf_attr *attr) { struct bpf_verifier_env *env; - struct bpf_verifer_log *log; + struct bpf_verifier_log *log; int ret = -EINVAL; /* no program is valid */ -- cgit v1.2.3 From 77d2e05abd45886dcad2b632c738cf46b9f7c19e Mon Sep 17 00:00:00 2001 From: Martin KaFai Lau Date: Sat, 24 Mar 2018 11:44:23 -0700 Subject: bpf: Add bpf_verifier_vlog() and bpf_verifier_log_needed() The BTF (BPF Type Format) verifier needs to reuse the current BPF verifier log. Hence, it requires the following changes: (1) Expose log_write() in verifier.c for other users. Its name is renamed to bpf_verifier_vlog(). (2) The BTF verifier also needs to check 'log->level && log->ubuf && !bpf_verifier_log_full(log);' independently outside of the current log_write(). It is because the BTF verifier will do one-check before making multiple calls to btf_verifier_vlog to log the details of a type. Hence, this check is also re-factored to a new function bpf_verifier_log_needed(). Since it is re-factored, we can check it before va_start() in the current bpf_verifier_log_write() and verbose(). Signed-off-by: Martin KaFai Lau Acked-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/bpf_verifier.h | 7 +++++++ kernel/bpf/verifier.c | 19 +++++++++++-------- 2 files changed, 18 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h index c30668414b22..7e61c395fddf 100644 --- a/include/linux/bpf_verifier.h +++ b/include/linux/bpf_verifier.h @@ -166,6 +166,11 @@ static inline bool bpf_verifier_log_full(const struct bpf_verifier_log *log) return log->len_used >= log->len_total - 1; } +static inline bool bpf_verifier_log_needed(const struct bpf_verifier_log *log) +{ + return log->level && log->ubuf && !bpf_verifier_log_full(log); +} + #define BPF_MAX_SUBPROGS 256 /* single container for all structs @@ -192,6 +197,8 @@ struct bpf_verifier_env { u32 subprog_cnt; }; +void bpf_verifier_vlog(struct bpf_verifier_log *log, const char *fmt, + va_list args); __printf(2, 3) void bpf_verifier_log_write(struct bpf_verifier_env *env, const char *fmt, ...); diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index 1e84e02ff733..8acd2207e412 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -168,15 +168,11 @@ struct bpf_call_arg_meta { static DEFINE_MUTEX(bpf_verifier_lock); -static void log_write(struct bpf_verifier_env *env, const char *fmt, - va_list args) +void bpf_verifier_vlog(struct bpf_verifier_log *log, const char *fmt, + va_list args) { - struct bpf_verifier_log *log = &env->log; unsigned int n; - if (!log->level || !log->ubuf || bpf_verifier_log_full(log)) - return; - n = vscnprintf(log->kbuf, BPF_VERIFIER_TMP_LOG_SIZE, fmt, args); WARN_ONCE(n >= BPF_VERIFIER_TMP_LOG_SIZE - 1, @@ -200,18 +196,25 @@ __printf(2, 3) void bpf_verifier_log_write(struct bpf_verifier_env *env, { va_list args; + if (!bpf_verifier_log_needed(&env->log)) + return; + va_start(args, fmt); - log_write(env, fmt, args); + bpf_verifier_vlog(&env->log, fmt, args); va_end(args); } EXPORT_SYMBOL_GPL(bpf_verifier_log_write); __printf(2, 3) static void verbose(void *private_data, const char *fmt, ...) { + struct bpf_verifier_env *env = private_data; va_list args; + if (!bpf_verifier_log_needed(&env->log)) + return; + va_start(args, fmt); - log_write(private_data, fmt, args); + bpf_verifier_vlog(&env->log, fmt, args); va_end(args); } -- cgit v1.2.3 From b91ed9d8082c394dda63f94f935219cd0a565938 Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Fri, 16 Mar 2018 19:13:02 +0530 Subject: quota: Kill an unused extern entry form quota.h Kill an unused extern entry from quota.h which is leftover of below patch. [f32764bd2: quota: Convert quota statistics to generic percpu_counter] Signed-off-by: Ritesh Harjani Signed-off-by: Jan Kara --- include/linux/quota.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/quota.h b/include/linux/quota.h index 5ac9de4fcd6f..ca9772c8e48b 100644 --- a/include/linux/quota.h +++ b/include/linux/quota.h @@ -267,7 +267,6 @@ struct dqstats { struct percpu_counter counter[_DQST_DQSTAT_LAST]; }; -extern struct dqstats *dqstats_pcpu; extern struct dqstats dqstats; static inline void dqstats_inc(unsigned int type) -- cgit v1.2.3 From df91f56adce1fc131e05368a0ad0ea72afd9a79a Mon Sep 17 00:00:00 2001 From: Nikolay Borisov Date: Mon, 8 Jan 2018 11:45:04 +0200 Subject: libcrc32c: Add crc32c_impl function This function returns a string with the currently in-use implementation of the crc32c algorithm, i.e crc32c-generic (for unoptimised, generic implementation) or crc32c-intel for the sse optimised version. This will be used by btrfs. Signed-off-by: Nikolay Borisov Acked-by: Herbert Xu [ use crypto_shash_driver_name as suggested by Herbert ] Signed-off-by: David Sterba --- include/linux/crc32c.h | 1 + lib/libcrc32c.c | 6 ++++++ 2 files changed, 7 insertions(+) (limited to 'include/linux') diff --git a/include/linux/crc32c.h b/include/linux/crc32c.h index 357ae4611a45..bd21af828ff6 100644 --- a/include/linux/crc32c.h +++ b/include/linux/crc32c.h @@ -5,6 +5,7 @@ #include extern u32 crc32c(u32 crc, const void *address, unsigned int length); +extern const char *crc32c_impl(void); /* This macro exists for backwards-compatibility. */ #define crc32c_le crc32c diff --git a/lib/libcrc32c.c b/lib/libcrc32c.c index 9f79547d1b97..f0a2934605bf 100644 --- a/lib/libcrc32c.c +++ b/lib/libcrc32c.c @@ -71,6 +71,12 @@ static void __exit libcrc32c_mod_fini(void) crypto_free_shash(tfm); } +const char *crc32c_impl(void) +{ + return crypto_shash_driver_name(tfm); +} +EXPORT_SYMBOL(crc32c_impl); + module_init(libcrc32c_mod_init); module_exit(libcrc32c_mod_fini); -- cgit v1.2.3 From a687a5337063af99ebd0eebaa6f4b4cf2e07c21b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 7 Mar 2018 23:30:54 +0100 Subject: treewide: simplify Kconfig dependencies for removed archs A lot of Kconfig symbols have architecture specific dependencies. In those cases that depend on architectures we have already removed, they can be omitted. Acked-by: Kalle Valo Acked-by: Alexandre Belloni Signed-off-by: Arnd Bergmann --- block/bounce.c | 2 +- drivers/ide/Kconfig | 2 +- drivers/ide/ide-generic.c | 12 +----------- drivers/input/joystick/analog.c | 2 +- drivers/isdn/hisax/Kconfig | 10 +++++----- drivers/net/ethernet/davicom/Kconfig | 2 +- drivers/net/ethernet/smsc/Kconfig | 6 +++--- drivers/net/wireless/cisco/Kconfig | 2 +- drivers/pwm/Kconfig | 2 +- drivers/rtc/Kconfig | 2 +- drivers/spi/Kconfig | 4 ++-- drivers/usb/musb/Kconfig | 2 +- drivers/video/console/Kconfig | 3 +-- drivers/watchdog/Kconfig | 6 ------ drivers/watchdog/Makefile | 6 ------ fs/Kconfig.binfmt | 5 ++--- fs/minix/Kconfig | 2 +- include/linux/ide.h | 7 +------ init/Kconfig | 5 ++--- lib/Kconfig.debug | 13 +++++-------- lib/test_user_copy.c | 2 -- mm/Kconfig | 7 ------- mm/percpu.c | 4 ---- 23 files changed, 31 insertions(+), 77 deletions(-) (limited to 'include/linux') diff --git a/block/bounce.c b/block/bounce.c index 6a3e68292273..dd0b93f2a871 100644 --- a/block/bounce.c +++ b/block/bounce.c @@ -31,7 +31,7 @@ static struct bio_set *bounce_bio_set, *bounce_bio_split; static mempool_t *page_pool, *isa_page_pool; -#if defined(CONFIG_HIGHMEM) || defined(CONFIG_NEED_BOUNCE_POOL) +#if defined(CONFIG_HIGHMEM) static __init int init_emergency_pool(void) { #if defined(CONFIG_HIGHMEM) && !defined(CONFIG_MEMORY_HOTPLUG) diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index cf1fb3fb5d26..901b8833847f 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -200,7 +200,7 @@ comment "IDE chipset support/bugfixes" config IDE_GENERIC tristate "generic/default IDE chipset support" - depends on ALPHA || X86 || IA64 || M32R || MIPS || ARCH_RPC + depends on ALPHA || X86 || IA64 || MIPS || ARCH_RPC default ARM && ARCH_RPC help This is the generic IDE driver. This driver attaches to the diff --git a/drivers/ide/ide-generic.c b/drivers/ide/ide-generic.c index 54d7c4685d23..80c0d69b83ac 100644 --- a/drivers/ide/ide-generic.c +++ b/drivers/ide/ide-generic.c @@ -13,13 +13,10 @@ #include #include -/* FIXME: convert arm and m32r to use ide_platform host driver */ +/* FIXME: convert arm to use ide_platform host driver */ #ifdef CONFIG_ARM #include #endif -#ifdef CONFIG_M32R -#include -#endif #define DRV_NAME "ide_generic" @@ -35,13 +32,6 @@ static const struct ide_port_info ide_generic_port_info = { #ifdef CONFIG_ARM static const u16 legacy_bases[] = { 0x1f0 }; static const int legacy_irqs[] = { IRQ_HARDDISK }; -#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) || \ - defined(CONFIG_PLAT_OPSPUT) -static const u16 legacy_bases[] = { 0x1f0 }; -static const int legacy_irqs[] = { PLD_IRQ_CFIREQ }; -#elif defined(CONFIG_PLAT_MAPPI3) -static const u16 legacy_bases[] = { 0x1f0, 0x170 }; -static const int legacy_irqs[] = { PLD_IRQ_CFIREQ, PLD_IRQ_IDEIREQ }; #elif defined(CONFIG_ALPHA) static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168 }; static const int legacy_irqs[] = { 14, 15, 11, 10 }; diff --git a/drivers/input/joystick/analog.c b/drivers/input/joystick/analog.c index be1b4921f22a..eefac7978f93 100644 --- a/drivers/input/joystick/analog.c +++ b/drivers/input/joystick/analog.c @@ -163,7 +163,7 @@ static unsigned int get_time_pit(void) #define GET_TIME(x) do { x = (unsigned int)rdtsc(); } while (0) #define DELTA(x,y) ((y)-(x)) #define TIME_NAME "TSC" -#elif defined(__alpha__) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) || defined(CONFIG_TILE) +#elif defined(__alpha__) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) #define GET_TIME(x) do { x = get_cycles(); } while (0) #define DELTA(x,y) ((y)-(x)) #define TIME_NAME "get_cycles" diff --git a/drivers/isdn/hisax/Kconfig b/drivers/isdn/hisax/Kconfig index eb83d94ab4fe..38cfc8baae19 100644 --- a/drivers/isdn/hisax/Kconfig +++ b/drivers/isdn/hisax/Kconfig @@ -109,7 +109,7 @@ config HISAX_16_3 config HISAX_TELESPCI bool "Teles PCI" - depends on PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN))) + depends on PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || (XTENSA && !CPU_LITTLE_ENDIAN))) help This enables HiSax support for the Teles PCI. See on how to configure it. @@ -237,7 +237,7 @@ config HISAX_MIC config HISAX_NETJET bool "NETjet card" - depends on PCI && (BROKEN || !(PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN) || MICROBLAZE)) + depends on PCI && (BROKEN || !(PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || (XTENSA && !CPU_LITTLE_ENDIAN) || MICROBLAZE)) depends on VIRT_TO_BUS help This enables HiSax support for the NetJet from Traverse @@ -249,7 +249,7 @@ config HISAX_NETJET config HISAX_NETJET_U bool "NETspider U card" - depends on PCI && (BROKEN || !(PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN) || MICROBLAZE)) + depends on PCI && (BROKEN || !(PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || (XTENSA && !CPU_LITTLE_ENDIAN) || MICROBLAZE)) depends on VIRT_TO_BUS help This enables HiSax support for the Netspider U interface ISDN card @@ -318,7 +318,7 @@ config HISAX_GAZEL config HISAX_HFC_PCI bool "HFC PCI-Bus cards" - depends on PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN))) + depends on PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || (XTENSA && !CPU_LITTLE_ENDIAN))) help This enables HiSax support for the HFC-S PCI 2BDS0 based cards. @@ -343,7 +343,7 @@ config HISAX_HFC_SX config HISAX_ENTERNOW_PCI bool "Formula-n enter:now PCI card" - depends on HISAX_NETJET && PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || FRV || (XTENSA && !CPU_LITTLE_ENDIAN))) + depends on HISAX_NETJET && PCI && (BROKEN || !(SPARC || PPC || PARISC || M68K || (MIPS && !CPU_LITTLE_ENDIAN) || (XTENSA && !CPU_LITTLE_ENDIAN))) help This enables HiSax support for the Formula-n enter:now PCI ISDN card. diff --git a/drivers/net/ethernet/davicom/Kconfig b/drivers/net/ethernet/davicom/Kconfig index 7ec2d74f94d3..680a6d983f37 100644 --- a/drivers/net/ethernet/davicom/Kconfig +++ b/drivers/net/ethernet/davicom/Kconfig @@ -4,7 +4,7 @@ config DM9000 tristate "DM9000 support" - depends on ARM || BLACKFIN || MIPS || COLDFIRE || NIOS2 + depends on ARM || MIPS || COLDFIRE || NIOS2 select CRC32 select MII ---help--- diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig index 948603e9b905..3da0c573d2ab 100644 --- a/drivers/net/ethernet/smsc/Kconfig +++ b/drivers/net/ethernet/smsc/Kconfig @@ -5,8 +5,8 @@ config NET_VENDOR_SMSC bool "SMC (SMSC)/Western Digital devices" default y - depends on ARM || ARM64 || ATARI_ETHERNAT || BLACKFIN || COLDFIRE || \ - ISA || M32R || MAC || MIPS || NIOS2 || PCI || \ + depends on ARM || ARM64 || ATARI_ETHERNAT || COLDFIRE || \ + ISA || MAC || MIPS || NIOS2 || PCI || \ PCMCIA || SUPERH || XTENSA || H8300 ---help--- If you have a network (Ethernet) card belonging to this class, say Y. @@ -37,7 +37,7 @@ config SMC91X select CRC32 select MII depends on !OF || GPIOLIB - depends on ARM || ARM64 || ATARI_ETHERNAT || BLACKFIN || COLDFIRE || \ + depends on ARM || ARM64 || ATARI_ETHERNAT || COLDFIRE || \ M32R || MIPS || NIOS2 || SUPERH || XTENSA || H8300 ---help--- This is a driver for SMC's 91x series of Ethernet chipsets, diff --git a/drivers/net/wireless/cisco/Kconfig b/drivers/net/wireless/cisco/Kconfig index b22567dff893..8ed0b154bb33 100644 --- a/drivers/net/wireless/cisco/Kconfig +++ b/drivers/net/wireless/cisco/Kconfig @@ -33,7 +33,7 @@ config AIRO config AIRO_CS tristate "Cisco/Aironet 34X/35X/4500/4800 PCMCIA cards" - depends on CFG80211 && PCMCIA && (BROKEN || !M32R) + depends on CFG80211 && PCMCIA select WIRELESS_EXT select WEXT_SPY select WEXT_PRIV diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 763ee50ea57d..f16aad3bf5d6 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -43,7 +43,7 @@ config PWM_AB8500 config PWM_ATMEL tristate "Atmel PWM support" - depends on ARCH_AT91 || AVR32 + depends on ARCH_AT91 help Generic PWM framework driver for Atmel SoC. diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index be5a3dc99c11..46af10ac45fc 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -868,7 +868,7 @@ comment "Platform RTC drivers" config RTC_DRV_CMOS tristate "PC-style 'CMOS'" - depends on X86 || ARM || M32R || PPC || MIPS || SPARC64 + depends on X86 || ARM || PPC || MIPS || SPARC64 default y if X86 select RTC_MC146818_LIB help diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 603783976b81..103c13fcefa0 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -72,10 +72,10 @@ config SPI_ARMADA_3700 config SPI_ATMEL tristate "Atmel SPI Controller" depends on HAS_DMA - depends on (ARCH_AT91 || AVR32 || COMPILE_TEST) + depends on ARCH_AT91 || COMPILE_TEST help This selects a driver for the Atmel SPI Controller, present on - many AT32 (AVR32) and AT91 (ARM) chips. + many AT91 ARM chips. config SPI_AU1550 tristate "Au1550/Au1200/Au1300 SPI Controller" diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig index 5506a9c03c1f..e757afc1cfd0 100644 --- a/drivers/usb/musb/Kconfig +++ b/drivers/usb/musb/Kconfig @@ -87,7 +87,7 @@ config USB_MUSB_DA8XX config USB_MUSB_TUSB6010 tristate "TUSB6010" depends on HAS_IOMEM - depends on (ARCH_OMAP2PLUS || COMPILE_TEST) && !BLACKFIN + depends on ARCH_OMAP2PLUS || COMPILE_TEST depends on NOP_USB_XCEIV = USB_MUSB_HDRC # both built-in or both modules config USB_MUSB_OMAP2PLUS diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index 005ed87c8216..a9e398c144f8 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig @@ -6,8 +6,7 @@ menu "Console display driver support" config VGA_CONSOLE bool "VGA text console" if EXPERT || !X86 - depends on !4xx && !PPC_8xx && !SPARC && !M68K && !PARISC && !FRV && \ - !SUPERH && !BLACKFIN && !AVR32 && !CRIS && \ + depends on !4xx && !PPC_8xx && !SPARC && !M68K && !PARISC && !SUPERH && \ (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) && \ !ARM64 && !ARC && !MICROBLAZE && !OPENRISC default y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e19679348d1..79020ce95de2 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -828,10 +828,6 @@ config BFIN_WDT To compile this driver as a module, choose M here: the module will be called bfin_wdt. -# CRIS Architecture - -# FRV Architecture - # X86 (i386 + ia64 + x86_64) Architecture config ACQUIRE_WDT @@ -1431,8 +1427,6 @@ config NIC7018_WDT To compile this driver as a module, choose M here: the module will be called nic7018_wdt. -# M32R Architecture - # M68K Architecture config M54xx_WATCHDOG diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0474d38aa854..1f9a0235f22c 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -94,10 +94,6 @@ obj-$(CONFIG_SPRD_WATCHDOG) += sprd_wdt.o # BLACKFIN Architecture obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o -# CRIS Architecture - -# FRV Architecture - # X86 (i386 + ia64 + x86_64) Architecture obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o @@ -146,8 +142,6 @@ obj-$(CONFIG_INTEL_MEI_WDT) += mei_wdt.o obj-$(CONFIG_NI903X_WDT) += ni903x_wdt.o obj-$(CONFIG_NIC7018_WDT) += nic7018_wdt.o -# M32R Architecture - # M68K Architecture obj-$(CONFIG_M54xx_WATCHDOG) += m54xx_wdt.o diff --git a/fs/Kconfig.binfmt b/fs/Kconfig.binfmt index 58c2bbd385ad..57a27c42b5ac 100644 --- a/fs/Kconfig.binfmt +++ b/fs/Kconfig.binfmt @@ -1,6 +1,6 @@ config BINFMT_ELF bool "Kernel support for ELF binaries" - depends on MMU && (BROKEN || !FRV) + depends on MMU select ELFCORE default y ---help--- @@ -35,7 +35,7 @@ config ARCH_BINFMT_ELF_STATE config BINFMT_ELF_FDPIC bool "Kernel support for FDPIC ELF binaries" default y if !BINFMT_ELF - depends on (ARM || FRV || BLACKFIN || (SUPERH32 && !MMU) || C6X) + depends on (ARM || (SUPERH32 && !MMU) || C6X) select ELFCORE help ELF FDPIC binaries are based on ELF, but allow the individual load @@ -90,7 +90,6 @@ config BINFMT_SCRIPT config BINFMT_FLAT bool "Kernel support for flat binaries" depends on !MMU || ARM || M68K - depends on !FRV || BROKEN help Support uClinux FLAT format binaries. diff --git a/fs/minix/Kconfig b/fs/minix/Kconfig index f2a0cfcef11d..bcd53a79156f 100644 --- a/fs/minix/Kconfig +++ b/fs/minix/Kconfig @@ -18,7 +18,7 @@ config MINIX_FS config MINIX_FS_NATIVE_ENDIAN def_bool MINIX_FS - depends on M32R || MICROBLAZE || MIPS || S390 || SUPERH || SPARC || XTENSA || (M68K && !MMU) + depends on MICROBLAZE || MIPS || S390 || SUPERH || SPARC || XTENSA || (M68K && !MMU) config MINIX_FS_BIG_ENDIAN_16BIT_INDEXED def_bool MINIX_FS diff --git a/include/linux/ide.h b/include/linux/ide.h index 20d42c0d9fb6..1d6f16110eae 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -25,15 +25,10 @@ #include #include -#if defined(CONFIG_CRIS) || defined(CONFIG_FRV) -# define SUPPORT_VLB_SYNC 0 -#else -# define SUPPORT_VLB_SYNC 1 -#endif - /* * Probably not wise to fiddle with these */ +#define SUPPORT_VLB_SYNC 1 #define IDE_DEFAULT_MAX_FAILURES 1 #define ERROR_MAX 8 /* Max read/write errors per sector */ #define ERROR_RESET 3 /* Reset controller every 4th retry */ diff --git a/init/Kconfig b/init/Kconfig index a14bcc9724a2..2852692d7c9c 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -998,7 +998,6 @@ config RELAY config BLK_DEV_INITRD bool "Initial RAM filesystem and RAM disk (initramfs/initrd) support" - depends on BROKEN || !FRV help The initial RAM filesystem is a ramfs which is loaded by the boot loader (loadlin or lilo) and that is mounted as root @@ -1108,7 +1107,7 @@ config MULTIUSER config SGETMASK_SYSCALL bool "sgetmask/ssetmask syscalls support" if EXPERT - def_bool PARISC || BLACKFIN || M68K || PPC || MIPS || X86 || SPARC || CRIS || MICROBLAZE || SUPERH + def_bool PARISC || M68K || PPC || MIPS || X86 || SPARC || MICROBLAZE || SUPERH ---help--- sys_sgetmask and sys_ssetmask are obsolete system calls no longer supported in libc but still enabled by default in some @@ -1370,7 +1369,7 @@ config KALLSYMS_ABSOLUTE_PERCPU config KALLSYMS_BASE_RELATIVE bool depends on KALLSYMS - default !IA64 && !(TILE && 64BIT) + default !IA64 help Instead of emitting them as absolute values in the native word size, emit the symbol references in the kallsyms table as 32-bit entries, diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 41ac9d294245..6927c6d8d185 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -165,7 +165,7 @@ config DEBUG_INFO_REDUCED config DEBUG_INFO_SPLIT bool "Produce split debuginfo in .dwo files" - depends on DEBUG_INFO && !FRV + depends on DEBUG_INFO help Generate debug info into separate .dwo files. This significantly reduces the build directory size for builds with DEBUG_INFO, @@ -354,10 +354,7 @@ config ARCH_WANT_FRAME_POINTERS config FRAME_POINTER bool "Compile the kernel with frame pointers" - depends on DEBUG_KERNEL && \ - (CRIS || M68K || FRV || UML || \ - SUPERH || BLACKFIN) || \ - ARCH_WANT_FRAME_POINTERS + depends on DEBUG_KERNEL && (M68K || UML || SUPERH) || ARCH_WANT_FRAME_POINTERS default y if (DEBUG_INFO && UML) || ARCH_WANT_FRAME_POINTERS help If you say Y here the resulting kernel image will be slightly @@ -1138,7 +1135,7 @@ config LOCKDEP bool depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT select STACKTRACE - select FRAME_POINTER if !MIPS && !PPC && !ARM_UNWIND && !S390 && !MICROBLAZE && !ARC && !SCORE && !X86 + select FRAME_POINTER if !MIPS && !PPC && !ARM_UNWIND && !S390 && !MICROBLAZE && !ARC && !X86 select KALLSYMS select KALLSYMS_ALL @@ -1571,7 +1568,7 @@ config FAULT_INJECTION_STACKTRACE_FILTER depends on FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT depends on !X86_64 select STACKTRACE - select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND && !ARC && !SCORE && !X86 + select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND && !ARC && !X86 help Provide stacktrace filter for fault-injection capabilities @@ -1969,7 +1966,7 @@ config STRICT_DEVMEM bool "Filter access to /dev/mem" depends on MMU && DEVMEM depends on ARCH_HAS_DEVMEM_IS_ALLOWED - default y if TILE || PPC || X86 || ARM64 + default y if PPC || X86 || ARM64 ---help--- If this option is disabled, you allow userspace (root) access to all of memory, including kernel and userspace memory. Accidental diff --git a/lib/test_user_copy.c b/lib/test_user_copy.c index a6556f3364d1..e161f0498f42 100644 --- a/lib/test_user_copy.c +++ b/lib/test_user_copy.c @@ -31,8 +31,6 @@ * their capability at compile-time, we just have to opt-out certain archs. */ #if BITS_PER_LONG == 64 || (!(defined(CONFIG_ARM) && !defined(MMU)) && \ - !defined(CONFIG_BLACKFIN) && \ - !defined(CONFIG_M32R) && \ !defined(CONFIG_M68K) && \ !defined(CONFIG_MICROBLAZE) && \ !defined(CONFIG_NIOS2) && \ diff --git a/mm/Kconfig b/mm/Kconfig index abefa573bcd8..d5004d82a1d6 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -278,13 +278,6 @@ config BOUNCE by default when ZONE_DMA or HIGHMEM is selected, but you may say n to override this. -# On the 'tile' arch, USB OHCI needs the bounce pool since tilegx will often -# have more than 4GB of memory, but we don't currently use the IOTLB to present -# a 32-bit address to OHCI. So we need to use a bounce pool instead. -config NEED_BOUNCE_POOL - bool - default y if TILE && USB_OHCI_HCD - config NR_QUICK int depends on QUICKLIST diff --git a/mm/percpu.c b/mm/percpu.c index 50e7fdf84055..79e3549cab0f 100644 --- a/mm/percpu.c +++ b/mm/percpu.c @@ -2719,11 +2719,7 @@ void __init setup_per_cpu_areas(void) if (pcpu_setup_first_chunk(ai, fc) < 0) panic("Failed to initialize percpu areas."); -#ifdef CONFIG_CRIS -#warning "the CRIS architecture has physical and virtual addresses confused" -#else pcpu_free_alloc_info(ai); -#endif } #endif /* CONFIG_SMP */ -- cgit v1.2.3 From 768a032d0e73f962ec13cd05b722d9744d2cf903 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 18:21:04 +0100 Subject: net: adi: remove blackfin ethernet drivers The blackfin architecture is getting removed, so the bfin_mac driver is now obsolete. Acked-by: Dominik Brodowski Acked-by: Aaron Wu Signed-off-by: Arnd Bergmann --- drivers/net/ethernet/Kconfig | 1 - drivers/net/ethernet/Makefile | 1 - drivers/net/ethernet/adi/Kconfig | 66 -- drivers/net/ethernet/adi/Makefile | 5 - drivers/net/ethernet/adi/bfin_mac.c | 1881 ----------------------------------- drivers/net/ethernet/adi/bfin_mac.h | 104 -- include/linux/bfin_mac.h | 30 - 7 files changed, 2088 deletions(-) delete mode 100644 drivers/net/ethernet/adi/Kconfig delete mode 100644 drivers/net/ethernet/adi/Makefile delete mode 100644 drivers/net/ethernet/adi/bfin_mac.c delete mode 100644 drivers/net/ethernet/adi/bfin_mac.h delete mode 100644 include/linux/bfin_mac.h (limited to 'include/linux') diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index 92be1ad3df59..074d760a568b 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -34,7 +34,6 @@ source "drivers/net/ethernet/arc/Kconfig" source "drivers/net/ethernet/atheros/Kconfig" source "drivers/net/ethernet/aurora/Kconfig" source "drivers/net/ethernet/cadence/Kconfig" -source "drivers/net/ethernet/adi/Kconfig" source "drivers/net/ethernet/broadcom/Kconfig" source "drivers/net/ethernet/brocade/Kconfig" source "drivers/net/ethernet/calxeda/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index edef6069dd4b..135dae67d671 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_NET_VENDOR_ARC) += arc/ obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/ obj-$(CONFIG_NET_VENDOR_AURORA) += aurora/ obj-$(CONFIG_NET_CADENCE) += cadence/ -obj-$(CONFIG_NET_BFIN) += adi/ obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/ obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/ obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/ diff --git a/drivers/net/ethernet/adi/Kconfig b/drivers/net/ethernet/adi/Kconfig deleted file mode 100644 index 98cc8f535021..000000000000 --- a/drivers/net/ethernet/adi/Kconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# Blackfin device configuration -# - -config NET_BFIN - bool "Blackfin devices" - depends on BF516 || BF518 || BF526 || BF527 || BF536 || BF537 - ---help--- - If you have a network (Ethernet) card belonging to this class, say Y. - - If unsure, say Y. - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the remaining Blackfin card questions. If you say Y, you will be - asked for your specific card in the following questions. - -if NET_BFIN - -config BFIN_MAC - tristate "Blackfin on-chip MAC support" - depends on (BF516 || BF518 || BF526 || BF527 || BF536 || BF537) - select CRC32 - select MII - select PHYLIB - select BFIN_MAC_USE_L1 if DMA_UNCACHED_NONE - ---help--- - This is the driver for Blackfin on-chip mac device. Say Y if you want - it compiled into the kernel. This driver is also available as a - module ( = code which can be inserted in and removed from the running - kernel whenever you want). The module will be called bfin_mac. - -config BFIN_MAC_USE_L1 - bool "Use L1 memory for rx/tx packets" - depends on BFIN_MAC && (BF527 || BF537) - default y - ---help--- - To get maximum network performance, you should use L1 memory as rx/tx - buffers. Say N here if you want to reserve L1 memory for other uses. - -config BFIN_TX_DESC_NUM - int "Number of transmit buffer packets" - depends on BFIN_MAC - range 6 10 if BFIN_MAC_USE_L1 - range 10 100 - default "10" - ---help--- - Set the number of buffer packets used in driver. - -config BFIN_RX_DESC_NUM - int "Number of receive buffer packets" - depends on BFIN_MAC - range 20 64 - default "20" - ---help--- - Set the number of buffer packets used in driver. - -config BFIN_MAC_USE_HWSTAMP - bool "Use IEEE 1588 hwstamp" - depends on BFIN_MAC && BF518 - imply PTP_1588_CLOCK - default y - ---help--- - To support the IEEE 1588 Precision Time Protocol (PTP), select y here - -endif # NET_BFIN diff --git a/drivers/net/ethernet/adi/Makefile b/drivers/net/ethernet/adi/Makefile deleted file mode 100644 index b1fbe195d0e8..000000000000 --- a/drivers/net/ethernet/adi/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Blackfin device drivers. -# - -obj-$(CONFIG_BFIN_MAC) += bfin_mac.o diff --git a/drivers/net/ethernet/adi/bfin_mac.c b/drivers/net/ethernet/adi/bfin_mac.c deleted file mode 100644 index 7120f2b9c6ef..000000000000 --- a/drivers/net/ethernet/adi/bfin_mac.c +++ /dev/null @@ -1,1881 +0,0 @@ -/* - * Blackfin On-Chip MAC Driver - * - * Copyright 2004-2010 Analog Devices Inc. - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Licensed under the GPL-2 or later. - */ - -#define DRV_VERSION "1.1" -#define DRV_DESC "Blackfin on-chip Ethernet MAC driver" - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "bfin_mac.h" - -MODULE_AUTHOR("Bryan Wu, Luke Yang"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION(DRV_DESC); -MODULE_ALIAS("platform:bfin_mac"); - -#if defined(CONFIG_BFIN_MAC_USE_L1) -# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num) -# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr) -#else -# define bfin_mac_alloc(dma_handle, size, num) \ - dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL) -# define bfin_mac_free(dma_handle, ptr, num) \ - dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle) -#endif - -#define PKT_BUF_SZ 1580 - -#define MAX_TIMEOUT_CNT 500 - -/* pointers to maintain transmit list */ -static struct net_dma_desc_tx *tx_list_head; -static struct net_dma_desc_tx *tx_list_tail; -static struct net_dma_desc_rx *rx_list_head; -static struct net_dma_desc_rx *rx_list_tail; -static struct net_dma_desc_rx *current_rx_ptr; -static struct net_dma_desc_tx *current_tx_ptr; -static struct net_dma_desc_tx *tx_desc; -static struct net_dma_desc_rx *rx_desc; - -static void desc_list_free(void) -{ - struct net_dma_desc_rx *r; - struct net_dma_desc_tx *t; - int i; -#if !defined(CONFIG_BFIN_MAC_USE_L1) - dma_addr_t dma_handle = 0; -#endif - - if (tx_desc) { - t = tx_list_head; - for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { - if (t) { - if (t->skb) { - dev_kfree_skb(t->skb); - t->skb = NULL; - } - t = t->next; - } - } - bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM); - } - - if (rx_desc) { - r = rx_list_head; - for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { - if (r) { - if (r->skb) { - dev_kfree_skb(r->skb); - r->skb = NULL; - } - r = r->next; - } - } - bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM); - } -} - -static int desc_list_init(struct net_device *dev) -{ - int i; - struct sk_buff *new_skb; -#if !defined(CONFIG_BFIN_MAC_USE_L1) - /* - * This dma_handle is useless in Blackfin dma_alloc_coherent(). - * The real dma handler is the return value of dma_alloc_coherent(). - */ - dma_addr_t dma_handle; -#endif - - tx_desc = bfin_mac_alloc(&dma_handle, - sizeof(struct net_dma_desc_tx), - CONFIG_BFIN_TX_DESC_NUM); - if (tx_desc == NULL) - goto init_error; - - rx_desc = bfin_mac_alloc(&dma_handle, - sizeof(struct net_dma_desc_rx), - CONFIG_BFIN_RX_DESC_NUM); - if (rx_desc == NULL) - goto init_error; - - /* init tx_list */ - tx_list_head = tx_list_tail = tx_desc; - - for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { - struct net_dma_desc_tx *t = tx_desc + i; - struct dma_descriptor *a = &(t->desc_a); - struct dma_descriptor *b = &(t->desc_b); - - /* - * disable DMA - * read from memory WNR = 0 - * wordsize is 32 bits - * 6 half words is desc size - * large desc flow - */ - a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; - a->start_addr = (unsigned long)t->packet; - a->x_count = 0; - a->next_dma_desc = b; - - /* - * enabled DMA - * write to memory WNR = 1 - * wordsize is 32 bits - * disable interrupt - * 6 half words is desc size - * large desc flow - */ - b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; - b->start_addr = (unsigned long)(&(t->status)); - b->x_count = 0; - - t->skb = NULL; - tx_list_tail->desc_b.next_dma_desc = a; - tx_list_tail->next = t; - tx_list_tail = t; - } - tx_list_tail->next = tx_list_head; /* tx_list is a circle */ - tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); - current_tx_ptr = tx_list_head; - - /* init rx_list */ - rx_list_head = rx_list_tail = rx_desc; - - for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { - struct net_dma_desc_rx *r = rx_desc + i; - struct dma_descriptor *a = &(r->desc_a); - struct dma_descriptor *b = &(r->desc_b); - - /* allocate a new skb for next time receive */ - new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); - if (!new_skb) - goto init_error; - - skb_reserve(new_skb, NET_IP_ALIGN); - /* Invalidate the data cache of skb->data range when it is write back - * cache. It will prevent overwriting the new data from DMA - */ - blackfin_dcache_invalidate_range((unsigned long)new_skb->head, - (unsigned long)new_skb->end); - r->skb = new_skb; - - /* - * enabled DMA - * write to memory WNR = 1 - * wordsize is 32 bits - * disable interrupt - * 6 half words is desc size - * large desc flow - */ - a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; - /* since RXDWA is enabled */ - a->start_addr = (unsigned long)new_skb->data - 2; - a->x_count = 0; - a->next_dma_desc = b; - - /* - * enabled DMA - * write to memory WNR = 1 - * wordsize is 32 bits - * enable interrupt - * 6 half words is desc size - * large desc flow - */ - b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | - NDSIZE_6 | DMAFLOW_LARGE; - b->start_addr = (unsigned long)(&(r->status)); - b->x_count = 0; - - rx_list_tail->desc_b.next_dma_desc = a; - rx_list_tail->next = r; - rx_list_tail = r; - } - rx_list_tail->next = rx_list_head; /* rx_list is a circle */ - rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); - current_rx_ptr = rx_list_head; - - return 0; - -init_error: - desc_list_free(); - pr_err("kmalloc failed\n"); - return -ENOMEM; -} - - -/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ - -/* - * MII operations - */ -/* Wait until the previous MDC/MDIO transaction has completed */ -static int bfin_mdio_poll(void) -{ - int timeout_cnt = MAX_TIMEOUT_CNT; - - /* poll the STABUSY bit */ - while ((bfin_read_EMAC_STAADD()) & STABUSY) { - udelay(1); - if (timeout_cnt-- < 0) { - pr_err("wait MDC/MDIO transaction to complete timeout\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - -/* Read an off-chip register in a PHY through the MDC/MDIO port */ -static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) -{ - int ret; - - ret = bfin_mdio_poll(); - if (ret) - return ret; - - /* read mode */ - bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | - SET_REGAD((u16) regnum) | - STABUSY); - - ret = bfin_mdio_poll(); - if (ret) - return ret; - - return (int) bfin_read_EMAC_STADAT(); -} - -/* Write an off-chip register in a PHY through the MDC/MDIO port */ -static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, - u16 value) -{ - int ret; - - ret = bfin_mdio_poll(); - if (ret) - return ret; - - bfin_write_EMAC_STADAT((u32) value); - - /* write mode */ - bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | - SET_REGAD((u16) regnum) | - STAOP | - STABUSY); - - return bfin_mdio_poll(); -} - -static void bfin_mac_adjust_link(struct net_device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - unsigned long flags; - int new_state = 0; - - spin_lock_irqsave(&lp->lock, flags); - if (phydev->link) { - /* Now we make sure that we can be in full duplex mode. - * If not, we operate in half-duplex mode. */ - if (phydev->duplex != lp->old_duplex) { - u32 opmode = bfin_read_EMAC_OPMODE(); - new_state = 1; - - if (phydev->duplex) - opmode |= FDMODE; - else - opmode &= ~(FDMODE); - - bfin_write_EMAC_OPMODE(opmode); - lp->old_duplex = phydev->duplex; - } - - if (phydev->speed != lp->old_speed) { - if (phydev->interface == PHY_INTERFACE_MODE_RMII) { - u32 opmode = bfin_read_EMAC_OPMODE(); - switch (phydev->speed) { - case 10: - opmode |= RMII_10; - break; - case 100: - opmode &= ~RMII_10; - break; - default: - netdev_warn(dev, - "Ack! Speed (%d) is not 10/100!\n", - phydev->speed); - break; - } - bfin_write_EMAC_OPMODE(opmode); - } - - new_state = 1; - lp->old_speed = phydev->speed; - } - - if (!lp->old_link) { - new_state = 1; - lp->old_link = 1; - } - } else if (lp->old_link) { - new_state = 1; - lp->old_link = 0; - lp->old_speed = 0; - lp->old_duplex = -1; - } - - if (new_state) { - u32 opmode = bfin_read_EMAC_OPMODE(); - phy_print_status(phydev); - pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); - } - - spin_unlock_irqrestore(&lp->lock, flags); -} - -/* MDC = 2.5 MHz */ -#define MDC_CLK 2500000 - -static int mii_probe(struct net_device *dev, int phy_mode) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - struct phy_device *phydev; - unsigned short sysctl; - u32 sclk, mdc_div; - - /* Enable PHY output early */ - if (!(bfin_read_VR_CTL() & CLKBUFOE)) - bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); - - sclk = get_sclk(); - mdc_div = ((sclk / MDC_CLK) / 2) - 1; - - sysctl = bfin_read_EMAC_SYSCTL(); - sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); - bfin_write_EMAC_SYSCTL(sysctl); - - phydev = phy_find_first(lp->mii_bus); - if (!phydev) { - netdev_err(dev, "no phy device found\n"); - return -ENODEV; - } - - if (phy_mode != PHY_INTERFACE_MODE_RMII && - phy_mode != PHY_INTERFACE_MODE_MII) { - netdev_err(dev, "invalid phy interface mode\n"); - return -EINVAL; - } - - phydev = phy_connect(dev, phydev_name(phydev), - &bfin_mac_adjust_link, phy_mode); - - if (IS_ERR(phydev)) { - netdev_err(dev, "could not attach PHY\n"); - return PTR_ERR(phydev); - } - - /* mask with MAC supported features */ - phydev->supported &= (SUPPORTED_10baseT_Half - | SUPPORTED_10baseT_Full - | SUPPORTED_100baseT_Half - | SUPPORTED_100baseT_Full - | SUPPORTED_Autoneg - | SUPPORTED_Pause | SUPPORTED_Asym_Pause - | SUPPORTED_MII - | SUPPORTED_TP); - - phydev->advertising = phydev->supported; - - lp->old_link = 0; - lp->old_speed = 0; - lp->old_duplex = -1; - - phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", - MDC_CLK, mdc_div, sclk / 1000000); - - return 0; -} - -/* - * Ethtool support - */ - -/* - * interrupt routine for magic packet wakeup - */ -static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id) -{ - return IRQ_HANDLED; -} - -static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, - struct ethtool_drvinfo *info) -{ - strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); - strlcpy(info->version, DRV_VERSION, sizeof(info->version)); - strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); - strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); -} - -static void bfin_mac_ethtool_getwol(struct net_device *dev, - struct ethtool_wolinfo *wolinfo) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - - wolinfo->supported = WAKE_MAGIC; - wolinfo->wolopts = lp->wol; -} - -static int bfin_mac_ethtool_setwol(struct net_device *dev, - struct ethtool_wolinfo *wolinfo) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - int rc; - - if (wolinfo->wolopts & (WAKE_MAGICSECURE | - WAKE_UCAST | - WAKE_MCAST | - WAKE_BCAST | - WAKE_ARP)) - return -EOPNOTSUPP; - - lp->wol = wolinfo->wolopts; - - if (lp->wol && !lp->irq_wake_requested) { - /* register wake irq handler */ - rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt, - 0, "EMAC_WAKE", dev); - if (rc) - return rc; - lp->irq_wake_requested = true; - } - - if (!lp->wol && lp->irq_wake_requested) { - free_irq(IRQ_MAC_WAKEDET, dev); - lp->irq_wake_requested = false; - } - - /* Make sure the PHY driver doesn't suspend */ - device_init_wakeup(&dev->dev, lp->wol); - - return 0; -} - -#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP -static int bfin_mac_ethtool_get_ts_info(struct net_device *dev, - struct ethtool_ts_info *info) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - - info->so_timestamping = - SOF_TIMESTAMPING_TX_HARDWARE | - SOF_TIMESTAMPING_RX_HARDWARE | - SOF_TIMESTAMPING_RAW_HARDWARE; - info->phc_index = lp->phc_index; - info->tx_types = - (1 << HWTSTAMP_TX_OFF) | - (1 << HWTSTAMP_TX_ON); - info->rx_filters = - (1 << HWTSTAMP_FILTER_NONE) | - (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | - (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | - (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); - return 0; -} -#endif - -static const struct ethtool_ops bfin_mac_ethtool_ops = { - .get_link = ethtool_op_get_link, - .get_drvinfo = bfin_mac_ethtool_getdrvinfo, - .get_wol = bfin_mac_ethtool_getwol, - .set_wol = bfin_mac_ethtool_setwol, -#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP - .get_ts_info = bfin_mac_ethtool_get_ts_info, -#endif - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, -}; - -/**************************************************************************/ -static void setup_system_regs(struct net_device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - int i; - unsigned short sysctl; - - /* - * Odd word alignment for Receive Frame DMA word - * Configure checksum support and rcve frame word alignment - */ - sysctl = bfin_read_EMAC_SYSCTL(); - /* - * check if interrupt is requested for any PHY, - * enable PHY interrupt only if needed - */ - for (i = 0; i < PHY_MAX_ADDR; ++i) - if (lp->mii_bus->irq[i] != PHY_POLL) - break; - if (i < PHY_MAX_ADDR) - sysctl |= PHYIE; - sysctl |= RXDWA; -#if defined(BFIN_MAC_CSUM_OFFLOAD) - sysctl |= RXCKS; -#else - sysctl &= ~RXCKS; -#endif - bfin_write_EMAC_SYSCTL(sysctl); - - bfin_write_EMAC_MMC_CTL(RSTC | CROLL); - - /* Set vlan regs to let 1522 bytes long packets pass through */ - bfin_write_EMAC_VLAN1(lp->vlan1_mask); - bfin_write_EMAC_VLAN2(lp->vlan2_mask); - - /* Initialize the TX DMA channel registers */ - bfin_write_DMA2_X_COUNT(0); - bfin_write_DMA2_X_MODIFY(4); - bfin_write_DMA2_Y_COUNT(0); - bfin_write_DMA2_Y_MODIFY(0); - - /* Initialize the RX DMA channel registers */ - bfin_write_DMA1_X_COUNT(0); - bfin_write_DMA1_X_MODIFY(4); - bfin_write_DMA1_Y_COUNT(0); - bfin_write_DMA1_Y_MODIFY(0); -} - -static void setup_mac_addr(u8 *mac_addr) -{ - u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); - u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); - - /* this depends on a little-endian machine */ - bfin_write_EMAC_ADDRLO(addr_low); - bfin_write_EMAC_ADDRHI(addr_hi); -} - -static int bfin_mac_set_mac_address(struct net_device *dev, void *p) -{ - struct sockaddr *addr = p; - if (netif_running(dev)) - return -EBUSY; - memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); - setup_mac_addr(dev->dev_addr); - return 0; -} - -#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP -#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE) - -static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result) -{ - u32 ipn = 1000000000UL / input_clk; - u32 ppn = 1; - unsigned int shift = 0; - - while (ppn <= ipn) { - ppn <<= 1; - shift++; - } - *shift_result = shift; - return 1000000000UL / ppn; -} - -static int bfin_mac_hwtstamp_set(struct net_device *netdev, - struct ifreq *ifr) -{ - struct hwtstamp_config config; - struct bfin_mac_local *lp = netdev_priv(netdev); - u16 ptpctl; - u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff; - - if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) - return -EFAULT; - - pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n", - __func__, config.flags, config.tx_type, config.rx_filter); - - /* reserved for future extensions */ - if (config.flags) - return -EINVAL; - - if ((config.tx_type != HWTSTAMP_TX_OFF) && - (config.tx_type != HWTSTAMP_TX_ON)) - return -ERANGE; - - ptpctl = bfin_read_EMAC_PTP_CTL(); - - switch (config.rx_filter) { - case HWTSTAMP_FILTER_NONE: - /* - * Dont allow any timestamping - */ - ptpfv3 = 0xFFFFFFFF; - bfin_write_EMAC_PTP_FV3(ptpfv3); - break; - case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: - case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: - case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: - /* - * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL) - * to enable all the field matches. - */ - ptpctl &= ~0x1F00; - bfin_write_EMAC_PTP_CTL(ptpctl); - /* - * Keep the default values of the EMAC_PTP_FOFF register. - */ - ptpfoff = 0x4A24170C; - bfin_write_EMAC_PTP_FOFF(ptpfoff); - /* - * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 - * registers. - */ - ptpfv1 = 0x11040800; - bfin_write_EMAC_PTP_FV1(ptpfv1); - ptpfv2 = 0x0140013F; - bfin_write_EMAC_PTP_FV2(ptpfv2); - /* - * The default value (0xFFFC) allows the timestamping of both - * received Sync messages and Delay_Req messages. - */ - ptpfv3 = 0xFFFFFFFC; - bfin_write_EMAC_PTP_FV3(ptpfv3); - - config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; - break; - case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: - case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: - case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: - /* Clear all five comparison mask bits (bits[12:8]) in the - * EMAC_PTP_CTL register to enable all the field matches. - */ - ptpctl &= ~0x1F00; - bfin_write_EMAC_PTP_CTL(ptpctl); - /* - * Keep the default values of the EMAC_PTP_FOFF register, except set - * the PTPCOF field to 0x2A. - */ - ptpfoff = 0x2A24170C; - bfin_write_EMAC_PTP_FOFF(ptpfoff); - /* - * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 - * registers. - */ - ptpfv1 = 0x11040800; - bfin_write_EMAC_PTP_FV1(ptpfv1); - ptpfv2 = 0x0140013F; - bfin_write_EMAC_PTP_FV2(ptpfv2); - /* - * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set - * the value to 0xFFF0. - */ - ptpfv3 = 0xFFFFFFF0; - bfin_write_EMAC_PTP_FV3(ptpfv3); - - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; - break; - case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: - case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: - case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: - /* - * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the - * EFTM and PTPCM field comparison. - */ - ptpctl &= ~0x1100; - bfin_write_EMAC_PTP_CTL(ptpctl); - /* - * Keep the default values of all the fields of the EMAC_PTP_FOFF - * register, except set the PTPCOF field to 0x0E. - */ - ptpfoff = 0x0E24170C; - bfin_write_EMAC_PTP_FOFF(ptpfoff); - /* - * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which - * corresponds to PTP messages on the MAC layer. - */ - ptpfv1 = 0x110488F7; - bfin_write_EMAC_PTP_FV1(ptpfv1); - ptpfv2 = 0x0140013F; - bfin_write_EMAC_PTP_FV2(ptpfv2); - /* - * To allow the timestamping of Pdelay_Req and Pdelay_Resp - * messages, set the value to 0xFFF0. - */ - ptpfv3 = 0xFFFFFFF0; - bfin_write_EMAC_PTP_FV3(ptpfv3); - - config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; - break; - default: - return -ERANGE; - } - - if (config.tx_type == HWTSTAMP_TX_OFF && - bfin_mac_hwtstamp_is_none(config.rx_filter)) { - ptpctl &= ~PTP_EN; - bfin_write_EMAC_PTP_CTL(ptpctl); - - SSYNC(); - } else { - ptpctl |= PTP_EN; - bfin_write_EMAC_PTP_CTL(ptpctl); - - /* - * clear any existing timestamp - */ - bfin_read_EMAC_PTP_RXSNAPLO(); - bfin_read_EMAC_PTP_RXSNAPHI(); - - bfin_read_EMAC_PTP_TXSNAPLO(); - bfin_read_EMAC_PTP_TXSNAPHI(); - - SSYNC(); - } - - lp->stamp_cfg = config; - return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? - -EFAULT : 0; -} - -static int bfin_mac_hwtstamp_get(struct net_device *netdev, - struct ifreq *ifr) -{ - struct bfin_mac_local *lp = netdev_priv(netdev); - - return copy_to_user(ifr->ifr_data, &lp->stamp_cfg, - sizeof(lp->stamp_cfg)) ? - -EFAULT : 0; -} - -static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) -{ - struct bfin_mac_local *lp = netdev_priv(netdev); - - if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { - int timeout_cnt = MAX_TIMEOUT_CNT; - - /* When doing time stamping, keep the connection to the socket - * a while longer - */ - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - - /* - * The timestamping is done at the EMAC module's MII/RMII interface - * when the module sees the Start of Frame of an event message packet. This - * interface is the closest possible place to the physical Ethernet transmission - * medium, providing the best timing accuracy. - */ - while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt)) - udelay(1); - if (timeout_cnt == 0) - netdev_err(netdev, "timestamp the TX packet failed\n"); - else { - struct skb_shared_hwtstamps shhwtstamps; - u64 ns; - u64 regval; - - regval = bfin_read_EMAC_PTP_TXSNAPLO(); - regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32; - memset(&shhwtstamps, 0, sizeof(shhwtstamps)); - ns = regval << lp->shift; - shhwtstamps.hwtstamp = ns_to_ktime(ns); - skb_tstamp_tx(skb, &shhwtstamps); - } - } -} - -static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) -{ - struct bfin_mac_local *lp = netdev_priv(netdev); - u32 valid; - u64 regval, ns; - struct skb_shared_hwtstamps *shhwtstamps; - - if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter)) - return; - - valid = bfin_read_EMAC_PTP_ISTAT() & RXEL; - if (!valid) - return; - - shhwtstamps = skb_hwtstamps(skb); - - regval = bfin_read_EMAC_PTP_RXSNAPLO(); - regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32; - ns = regval << lp->shift; - memset(shhwtstamps, 0, sizeof(*shhwtstamps)); - shhwtstamps->hwtstamp = ns_to_ktime(ns); -} - -static void bfin_mac_hwtstamp_init(struct net_device *netdev) -{ - struct bfin_mac_local *lp = netdev_priv(netdev); - u64 addend, ppb; - u32 input_clk, phc_clk; - - /* Initialize hardware timer */ - input_clk = get_sclk(); - phc_clk = bfin_select_phc_clock(input_clk, &lp->shift); - addend = phc_clk * (1ULL << 32); - do_div(addend, input_clk); - bfin_write_EMAC_PTP_ADDEND((u32)addend); - - lp->addend = addend; - ppb = 1000000000ULL * input_clk; - do_div(ppb, phc_clk); - lp->max_ppb = ppb - 1000000000ULL - 1ULL; - - /* Initialize hwstamp config */ - lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE; - lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF; -} - -static u64 bfin_ptp_time_read(struct bfin_mac_local *lp) -{ - u64 ns; - u32 lo, hi; - - lo = bfin_read_EMAC_PTP_TIMELO(); - hi = bfin_read_EMAC_PTP_TIMEHI(); - - ns = ((u64) hi) << 32; - ns |= lo; - ns <<= lp->shift; - - return ns; -} - -static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns) -{ - u32 hi, lo; - - ns >>= lp->shift; - hi = ns >> 32; - lo = ns & 0xffffffff; - - bfin_write_EMAC_PTP_TIMELO(lo); - bfin_write_EMAC_PTP_TIMEHI(hi); -} - -/* PTP Hardware Clock operations */ - -static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) -{ - u64 adj; - u32 diff, addend; - int neg_adj = 0; - struct bfin_mac_local *lp = - container_of(ptp, struct bfin_mac_local, caps); - - if (ppb < 0) { - neg_adj = 1; - ppb = -ppb; - } - addend = lp->addend; - adj = addend; - adj *= ppb; - diff = div_u64(adj, 1000000000ULL); - - addend = neg_adj ? addend - diff : addend + diff; - - bfin_write_EMAC_PTP_ADDEND(addend); - - return 0; -} - -static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) -{ - s64 now; - unsigned long flags; - struct bfin_mac_local *lp = - container_of(ptp, struct bfin_mac_local, caps); - - spin_lock_irqsave(&lp->phc_lock, flags); - - now = bfin_ptp_time_read(lp); - now += delta; - bfin_ptp_time_write(lp, now); - - spin_unlock_irqrestore(&lp->phc_lock, flags); - - return 0; -} - -static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) -{ - u64 ns; - unsigned long flags; - struct bfin_mac_local *lp = - container_of(ptp, struct bfin_mac_local, caps); - - spin_lock_irqsave(&lp->phc_lock, flags); - - ns = bfin_ptp_time_read(lp); - - spin_unlock_irqrestore(&lp->phc_lock, flags); - - *ts = ns_to_timespec64(ns); - - return 0; -} - -static int bfin_ptp_settime(struct ptp_clock_info *ptp, - const struct timespec64 *ts) -{ - u64 ns; - unsigned long flags; - struct bfin_mac_local *lp = - container_of(ptp, struct bfin_mac_local, caps); - - ns = timespec64_to_ns(ts); - - spin_lock_irqsave(&lp->phc_lock, flags); - - bfin_ptp_time_write(lp, ns); - - spin_unlock_irqrestore(&lp->phc_lock, flags); - - return 0; -} - -static int bfin_ptp_enable(struct ptp_clock_info *ptp, - struct ptp_clock_request *rq, int on) -{ - return -EOPNOTSUPP; -} - -static const struct ptp_clock_info bfin_ptp_caps = { - .owner = THIS_MODULE, - .name = "BF518 clock", - .max_adj = 0, - .n_alarm = 0, - .n_ext_ts = 0, - .n_per_out = 0, - .n_pins = 0, - .pps = 0, - .adjfreq = bfin_ptp_adjfreq, - .adjtime = bfin_ptp_adjtime, - .gettime64 = bfin_ptp_gettime, - .settime64 = bfin_ptp_settime, - .enable = bfin_ptp_enable, -}; - -static int bfin_phc_init(struct net_device *netdev, struct device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(netdev); - - lp->caps = bfin_ptp_caps; - lp->caps.max_adj = lp->max_ppb; - lp->clock = ptp_clock_register(&lp->caps, dev); - if (IS_ERR(lp->clock)) - return PTR_ERR(lp->clock); - - lp->phc_index = ptp_clock_index(lp->clock); - spin_lock_init(&lp->phc_lock); - - return 0; -} - -static void bfin_phc_release(struct bfin_mac_local *lp) -{ - ptp_clock_unregister(lp->clock); -} - -#else -# define bfin_mac_hwtstamp_is_none(cfg) 0 -# define bfin_mac_hwtstamp_init(dev) -# define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP) -# define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP) -# define bfin_rx_hwtstamp(dev, skb) -# define bfin_tx_hwtstamp(dev, skb) -# define bfin_phc_init(netdev, dev) 0 -# define bfin_phc_release(lp) -#endif - -static inline void _tx_reclaim_skb(void) -{ - do { - tx_list_head->desc_a.config &= ~DMAEN; - tx_list_head->status.status_word = 0; - if (tx_list_head->skb) { - dev_consume_skb_any(tx_list_head->skb); - tx_list_head->skb = NULL; - } - tx_list_head = tx_list_head->next; - - } while (tx_list_head->status.status_word != 0); -} - -static void tx_reclaim_skb(struct bfin_mac_local *lp) -{ - int timeout_cnt = MAX_TIMEOUT_CNT; - - if (tx_list_head->status.status_word != 0) - _tx_reclaim_skb(); - - if (current_tx_ptr->next == tx_list_head) { - while (tx_list_head->status.status_word == 0) { - /* slow down polling to avoid too many queue stop. */ - udelay(10); - /* reclaim skb if DMA is not running. */ - if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) - break; - if (timeout_cnt-- < 0) - break; - } - - if (timeout_cnt >= 0) - _tx_reclaim_skb(); - else - netif_stop_queue(lp->ndev); - } - - if (current_tx_ptr->next != tx_list_head && - netif_queue_stopped(lp->ndev)) - netif_wake_queue(lp->ndev); - - if (tx_list_head != current_tx_ptr) { - /* shorten the timer interval if tx queue is stopped */ - if (netif_queue_stopped(lp->ndev)) - lp->tx_reclaim_timer.expires = - jiffies + (TX_RECLAIM_JIFFIES >> 4); - else - lp->tx_reclaim_timer.expires = - jiffies + TX_RECLAIM_JIFFIES; - - mod_timer(&lp->tx_reclaim_timer, - lp->tx_reclaim_timer.expires); - } - - return; -} - -static void tx_reclaim_skb_timeout(struct timer_list *t) -{ - struct bfin_mac_local *lp = from_timer(lp, t, tx_reclaim_timer); - - tx_reclaim_skb(lp); -} - -static int bfin_mac_hard_start_xmit(struct sk_buff *skb, - struct net_device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - u16 *data; - u32 data_align = (unsigned long)(skb->data) & 0x3; - - current_tx_ptr->skb = skb; - - if (data_align == 0x2) { - /* move skb->data to current_tx_ptr payload */ - data = (u16 *)(skb->data) - 1; - *data = (u16)(skb->len); - /* - * When transmitting an Ethernet packet, the PTP_TSYNC module requires - * a DMA_Length_Word field associated with the packet. The lower 12 bits - * of this field are the length of the packet payload in bytes and the higher - * 4 bits are the timestamping enable field. - */ - if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) - *data |= 0x1000; - - current_tx_ptr->desc_a.start_addr = (u32)data; - /* this is important! */ - blackfin_dcache_flush_range((u32)data, - (u32)((u8 *)data + skb->len + 4)); - } else { - *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len); - /* enable timestamping for the sent packet */ - if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) - *((u16 *)(current_tx_ptr->packet)) |= 0x1000; - memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data, - skb->len); - current_tx_ptr->desc_a.start_addr = - (u32)current_tx_ptr->packet; - blackfin_dcache_flush_range( - (u32)current_tx_ptr->packet, - (u32)(current_tx_ptr->packet + skb->len + 2)); - } - - /* make sure the internal data buffers in the core are drained - * so that the DMA descriptors are completely written when the - * DMA engine goes to fetch them below - */ - SSYNC(); - - /* always clear status buffer before start tx dma */ - current_tx_ptr->status.status_word = 0; - - /* enable this packet's dma */ - current_tx_ptr->desc_a.config |= DMAEN; - - /* tx dma is running, just return */ - if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN) - goto out; - - /* tx dma is not running */ - bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); - /* dma enabled, read from memory, size is 6 */ - bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); - /* Turn on the EMAC tx */ - bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); - -out: - bfin_tx_hwtstamp(dev, skb); - - current_tx_ptr = current_tx_ptr->next; - dev->stats.tx_packets++; - dev->stats.tx_bytes += (skb->len); - - tx_reclaim_skb(lp); - - return NETDEV_TX_OK; -} - -#define IP_HEADER_OFF 0 -#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \ - RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE) - -static void bfin_mac_rx(struct bfin_mac_local *lp) -{ - struct net_device *dev = lp->ndev; - struct sk_buff *skb, *new_skb; - unsigned short len; -#if defined(BFIN_MAC_CSUM_OFFLOAD) - unsigned int i; - unsigned char fcs[ETH_FCS_LEN + 1]; -#endif - - /* check if frame status word reports an error condition - * we which case we simply drop the packet - */ - if (current_rx_ptr->status.status_word & RX_ERROR_MASK) { - netdev_notice(dev, "rx: receive error - packet dropped\n"); - dev->stats.rx_dropped++; - goto out; - } - - /* allocate a new skb for next time receive */ - skb = current_rx_ptr->skb; - - new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); - if (!new_skb) { - dev->stats.rx_dropped++; - goto out; - } - /* reserve 2 bytes for RXDWA padding */ - skb_reserve(new_skb, NET_IP_ALIGN); - /* Invalidate the data cache of skb->data range when it is write back - * cache. It will prevent overwriting the new data from DMA - */ - blackfin_dcache_invalidate_range((unsigned long)new_skb->head, - (unsigned long)new_skb->end); - - current_rx_ptr->skb = new_skb; - current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; - - len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN); - /* Deduce Ethernet FCS length from Ethernet payload length */ - len -= ETH_FCS_LEN; - skb_put(skb, len); - - skb->protocol = eth_type_trans(skb, dev); - - bfin_rx_hwtstamp(dev, skb); - -#if defined(BFIN_MAC_CSUM_OFFLOAD) - /* Checksum offloading only works for IPv4 packets with the standard IP header - * length of 20 bytes, because the blackfin MAC checksum calculation is - * based on that assumption. We must NOT use the calculated checksum if our - * IP version or header break that assumption. - */ - if (skb->data[IP_HEADER_OFF] == 0x45) { - skb->csum = current_rx_ptr->status.ip_payload_csum; - /* - * Deduce Ethernet FCS from hardware generated IP payload checksum. - * IP checksum is based on 16-bit one's complement algorithm. - * To deduce a value from checksum is equal to add its inversion. - * If the IP payload len is odd, the inversed FCS should also - * begin from odd address and leave first byte zero. - */ - if (skb->len % 2) { - fcs[0] = 0; - for (i = 0; i < ETH_FCS_LEN; i++) - fcs[i + 1] = ~skb->data[skb->len + i]; - skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum); - } else { - for (i = 0; i < ETH_FCS_LEN; i++) - fcs[i] = ~skb->data[skb->len + i]; - skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum); - } - skb->ip_summed = CHECKSUM_COMPLETE; - } -#endif - - napi_gro_receive(&lp->napi, skb); - - dev->stats.rx_packets++; - dev->stats.rx_bytes += len; -out: - current_rx_ptr->status.status_word = 0x00000000; - current_rx_ptr = current_rx_ptr->next; -} - -static int bfin_mac_poll(struct napi_struct *napi, int budget) -{ - int i = 0; - struct bfin_mac_local *lp = container_of(napi, - struct bfin_mac_local, - napi); - - while (current_rx_ptr->status.status_word != 0 && i < budget) { - bfin_mac_rx(lp); - i++; - } - - if (i < budget) { - napi_complete_done(napi, i); - if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags)) - enable_irq(IRQ_MAC_RX); - } - - return i; -} - -/* interrupt routine to handle rx and error signal */ -static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) -{ - struct bfin_mac_local *lp = netdev_priv(dev_id); - u32 status; - - status = bfin_read_DMA1_IRQ_STATUS(); - - bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR); - if (status & DMA_DONE) { - disable_irq_nosync(IRQ_MAC_RX); - set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags); - napi_schedule(&lp->napi); - } - - return IRQ_HANDLED; -} - -#ifdef CONFIG_NET_POLL_CONTROLLER -static void bfin_mac_poll_controller(struct net_device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - - bfin_mac_interrupt(IRQ_MAC_RX, dev); - tx_reclaim_skb(lp); -} -#endif /* CONFIG_NET_POLL_CONTROLLER */ - -static void bfin_mac_disable(void) -{ - unsigned int opmode; - - opmode = bfin_read_EMAC_OPMODE(); - opmode &= (~RE); - opmode &= (~TE); - /* Turn off the EMAC */ - bfin_write_EMAC_OPMODE(opmode); -} - -/* - * Enable Interrupts, Receive, and Transmit - */ -static int bfin_mac_enable(struct phy_device *phydev) -{ - int ret; - u32 opmode; - - pr_debug("%s\n", __func__); - - /* Set RX DMA */ - bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); - bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); - - /* Wait MII done */ - ret = bfin_mdio_poll(); - if (ret) - return ret; - - /* We enable only RX here */ - /* ASTP : Enable Automatic Pad Stripping - PR : Promiscuous Mode for test - PSF : Receive frames with total length less than 64 bytes. - FDMODE : Full Duplex Mode - LB : Internal Loopback for test - RE : Receiver Enable */ - opmode = bfin_read_EMAC_OPMODE(); - if (opmode & FDMODE) - opmode |= PSF; - else - opmode |= DRO | DC | PSF; - opmode |= RE; - - if (phydev->interface == PHY_INTERFACE_MODE_RMII) { - opmode |= RMII; /* For Now only 100MBit are supported */ -#if defined(CONFIG_BF537) || defined(CONFIG_BF536) - if (__SILICON_REVISION__ < 3) { - /* - * This isn't publicly documented (fun times!), but in - * silicon <=0.2, the RX and TX pins are clocked together. - * So in order to recv, we must enable the transmit side - * as well. This will cause a spurious TX interrupt too, - * but we can easily consume that. - */ - opmode |= TE; - } -#endif - } - - /* Turn on the EMAC rx */ - bfin_write_EMAC_OPMODE(opmode); - - return 0; -} - -/* Our watchdog timed out. Called by the networking layer */ -static void bfin_mac_timeout(struct net_device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - - pr_debug("%s: %s\n", dev->name, __func__); - - bfin_mac_disable(); - - del_timer(&lp->tx_reclaim_timer); - - /* reset tx queue and free skb */ - while (tx_list_head != current_tx_ptr) { - tx_list_head->desc_a.config &= ~DMAEN; - tx_list_head->status.status_word = 0; - if (tx_list_head->skb) { - dev_kfree_skb(tx_list_head->skb); - tx_list_head->skb = NULL; - } - tx_list_head = tx_list_head->next; - } - - if (netif_queue_stopped(dev)) - netif_wake_queue(dev); - - bfin_mac_enable(dev->phydev); - - /* We can accept TX packets again */ - netif_trans_update(dev); /* prevent tx timeout */ -} - -static void bfin_mac_multicast_hash(struct net_device *dev) -{ - u32 emac_hashhi, emac_hashlo; - struct netdev_hw_addr *ha; - u32 crc; - - emac_hashhi = emac_hashlo = 0; - - netdev_for_each_mc_addr(ha, dev) { - crc = ether_crc(ETH_ALEN, ha->addr); - crc >>= 26; - - if (crc & 0x20) - emac_hashhi |= 1 << (crc & 0x1f); - else - emac_hashlo |= 1 << (crc & 0x1f); - } - - bfin_write_EMAC_HASHHI(emac_hashhi); - bfin_write_EMAC_HASHLO(emac_hashlo); -} - -/* - * This routine will, depending on the values passed to it, - * either make it accept multicast packets, go into - * promiscuous mode (for TCPDUMP and cousins) or accept - * a select set of multicast packets - */ -static void bfin_mac_set_multicast_list(struct net_device *dev) -{ - u32 sysctl; - - if (dev->flags & IFF_PROMISC) { - netdev_info(dev, "set promisc mode\n"); - sysctl = bfin_read_EMAC_OPMODE(); - sysctl |= PR; - bfin_write_EMAC_OPMODE(sysctl); - } else if (dev->flags & IFF_ALLMULTI) { - /* accept all multicast */ - sysctl = bfin_read_EMAC_OPMODE(); - sysctl |= PAM; - bfin_write_EMAC_OPMODE(sysctl); - } else if (!netdev_mc_empty(dev)) { - /* set up multicast hash table */ - sysctl = bfin_read_EMAC_OPMODE(); - sysctl |= HM; - bfin_write_EMAC_OPMODE(sysctl); - bfin_mac_multicast_hash(dev); - } else { - /* clear promisc or multicast mode */ - sysctl = bfin_read_EMAC_OPMODE(); - sysctl &= ~(RAF | PAM); - bfin_write_EMAC_OPMODE(sysctl); - } -} - -static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) -{ - if (!netif_running(netdev)) - return -EINVAL; - - switch (cmd) { - case SIOCSHWTSTAMP: - return bfin_mac_hwtstamp_set(netdev, ifr); - case SIOCGHWTSTAMP: - return bfin_mac_hwtstamp_get(netdev, ifr); - default: - if (netdev->phydev) - return phy_mii_ioctl(netdev->phydev, ifr, cmd); - else - return -EOPNOTSUPP; - } -} - -/* - * this puts the device in an inactive state - */ -static void bfin_mac_shutdown(struct net_device *dev) -{ - /* Turn off the EMAC */ - bfin_write_EMAC_OPMODE(0x00000000); - /* Turn off the EMAC RX DMA */ - bfin_write_DMA1_CONFIG(0x0000); - bfin_write_DMA2_CONFIG(0x0000); -} - -/* - * Open and Initialize the interface - * - * Set up everything, reset the card, etc.. - */ -static int bfin_mac_open(struct net_device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - int ret; - pr_debug("%s: %s\n", dev->name, __func__); - - /* - * Check that the address is valid. If its not, refuse - * to bring the device up. The user must specify an - * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx - */ - if (!is_valid_ether_addr(dev->dev_addr)) { - netdev_warn(dev, "no valid ethernet hw addr\n"); - return -EINVAL; - } - - /* initial rx and tx list */ - ret = desc_list_init(dev); - if (ret) - return ret; - - phy_start(dev->phydev); - setup_system_regs(dev); - setup_mac_addr(dev->dev_addr); - - bfin_mac_disable(); - ret = bfin_mac_enable(dev->phydev); - if (ret) - return ret; - pr_debug("hardware init finished\n"); - - napi_enable(&lp->napi); - netif_start_queue(dev); - netif_carrier_on(dev); - - return 0; -} - -/* - * this makes the board clean up everything that it can - * and not talk to the outside world. Caused by - * an 'ifconfig ethX down' - */ -static int bfin_mac_close(struct net_device *dev) -{ - struct bfin_mac_local *lp = netdev_priv(dev); - pr_debug("%s: %s\n", dev->name, __func__); - - netif_stop_queue(dev); - napi_disable(&lp->napi); - netif_carrier_off(dev); - - phy_stop(dev->phydev); - phy_write(dev->phydev, MII_BMCR, BMCR_PDOWN); - - /* clear everything */ - bfin_mac_shutdown(dev); - - /* free the rx/tx buffers */ - desc_list_free(); - - return 0; -} - -static const struct net_device_ops bfin_mac_netdev_ops = { - .ndo_open = bfin_mac_open, - .ndo_stop = bfin_mac_close, - .ndo_start_xmit = bfin_mac_hard_start_xmit, - .ndo_set_mac_address = bfin_mac_set_mac_address, - .ndo_tx_timeout = bfin_mac_timeout, - .ndo_set_rx_mode = bfin_mac_set_multicast_list, - .ndo_do_ioctl = bfin_mac_ioctl, - .ndo_validate_addr = eth_validate_addr, -#ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = bfin_mac_poll_controller, -#endif -}; - -static int bfin_mac_probe(struct platform_device *pdev) -{ - struct net_device *ndev; - struct bfin_mac_local *lp; - struct platform_device *pd; - struct bfin_mii_bus_platform_data *mii_bus_data; - int rc; - - ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); - if (!ndev) - return -ENOMEM; - - SET_NETDEV_DEV(ndev, &pdev->dev); - platform_set_drvdata(pdev, ndev); - lp = netdev_priv(ndev); - lp->ndev = ndev; - - /* Grab the MAC address in the MAC */ - *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); - *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); - - /* probe mac */ - /*todo: how to probe? which is revision_register */ - bfin_write_EMAC_ADDRLO(0x12345678); - if (bfin_read_EMAC_ADDRLO() != 0x12345678) { - dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); - rc = -ENODEV; - goto out_err_probe_mac; - } - - - /* - * Is it valid? (Did bootloader initialize it?) - * Grab the MAC from the board somehow - * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c - */ - if (!is_valid_ether_addr(ndev->dev_addr)) { - if (bfin_get_ether_addr(ndev->dev_addr) || - !is_valid_ether_addr(ndev->dev_addr)) { - /* Still not valid, get a random one */ - netdev_warn(ndev, "Setting Ethernet MAC to a random one\n"); - eth_hw_addr_random(ndev); - } - } - - setup_mac_addr(ndev->dev_addr); - - if (!dev_get_platdata(&pdev->dev)) { - dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n"); - rc = -ENODEV; - goto out_err_probe_mac; - } - pd = dev_get_platdata(&pdev->dev); - lp->mii_bus = platform_get_drvdata(pd); - if (!lp->mii_bus) { - dev_err(&pdev->dev, "Cannot get mii_bus!\n"); - rc = -ENODEV; - goto out_err_probe_mac; - } - lp->mii_bus->priv = ndev; - mii_bus_data = dev_get_platdata(&pd->dev); - - rc = mii_probe(ndev, mii_bus_data->phy_mode); - if (rc) { - dev_err(&pdev->dev, "MII Probe failed!\n"); - goto out_err_mii_probe; - } - - lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask; - lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask; - - ndev->netdev_ops = &bfin_mac_netdev_ops; - ndev->ethtool_ops = &bfin_mac_ethtool_ops; - - timer_setup(&lp->tx_reclaim_timer, tx_reclaim_skb_timeout, 0); - - lp->flags = 0; - netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM); - - spin_lock_init(&lp->lock); - - /* now, enable interrupts */ - /* register irq handler */ - rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, - 0, "EMAC_RX", ndev); - if (rc) { - dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); - rc = -EBUSY; - goto out_err_request_irq; - } - - rc = register_netdev(ndev); - if (rc) { - dev_err(&pdev->dev, "Cannot register net device!\n"); - goto out_err_reg_ndev; - } - - bfin_mac_hwtstamp_init(ndev); - rc = bfin_phc_init(ndev, &pdev->dev); - if (rc) { - dev_err(&pdev->dev, "Cannot register PHC device!\n"); - goto out_err_phc; - } - - /* now, print out the card info, in a short format.. */ - netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); - - return 0; - -out_err_phc: -out_err_reg_ndev: - free_irq(IRQ_MAC_RX, ndev); -out_err_request_irq: - netif_napi_del(&lp->napi); -out_err_mii_probe: - mdiobus_unregister(lp->mii_bus); - mdiobus_free(lp->mii_bus); -out_err_probe_mac: - free_netdev(ndev); - - return rc; -} - -static int bfin_mac_remove(struct platform_device *pdev) -{ - struct net_device *ndev = platform_get_drvdata(pdev); - struct bfin_mac_local *lp = netdev_priv(ndev); - - bfin_phc_release(lp); - - lp->mii_bus->priv = NULL; - - unregister_netdev(ndev); - - netif_napi_del(&lp->napi); - - free_irq(IRQ_MAC_RX, ndev); - - free_netdev(ndev); - - return 0; -} - -#ifdef CONFIG_PM -static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) -{ - struct net_device *net_dev = platform_get_drvdata(pdev); - struct bfin_mac_local *lp = netdev_priv(net_dev); - - if (lp->wol) { - bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE); - bfin_write_EMAC_WKUP_CTL(MPKE); - enable_irq_wake(IRQ_MAC_WAKEDET); - } else { - if (netif_running(net_dev)) - bfin_mac_close(net_dev); - } - - return 0; -} - -static int bfin_mac_resume(struct platform_device *pdev) -{ - struct net_device *net_dev = platform_get_drvdata(pdev); - struct bfin_mac_local *lp = netdev_priv(net_dev); - - if (lp->wol) { - bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); - bfin_write_EMAC_WKUP_CTL(0); - disable_irq_wake(IRQ_MAC_WAKEDET); - } else { - if (netif_running(net_dev)) - bfin_mac_open(net_dev); - } - - return 0; -} -#else -#define bfin_mac_suspend NULL -#define bfin_mac_resume NULL -#endif /* CONFIG_PM */ - -static int bfin_mii_bus_probe(struct platform_device *pdev) -{ - struct mii_bus *miibus; - struct bfin_mii_bus_platform_data *mii_bus_pd; - const unsigned short *pin_req; - int rc, i; - - mii_bus_pd = dev_get_platdata(&pdev->dev); - if (!mii_bus_pd) { - dev_err(&pdev->dev, "No peripherals in platform data!\n"); - return -EINVAL; - } - - /* - * We are setting up a network card, - * so set the GPIO pins to Ethernet mode - */ - pin_req = mii_bus_pd->mac_peripherals; - rc = peripheral_request_list(pin_req, KBUILD_MODNAME); - if (rc) { - dev_err(&pdev->dev, "Requesting peripherals failed!\n"); - return rc; - } - - rc = -ENOMEM; - miibus = mdiobus_alloc(); - if (miibus == NULL) - goto out_err_alloc; - miibus->read = bfin_mdiobus_read; - miibus->write = bfin_mdiobus_write; - - miibus->parent = &pdev->dev; - miibus->name = "bfin_mii_bus"; - miibus->phy_mask = mii_bus_pd->phy_mask; - - snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x", - pdev->name, pdev->id); - - rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR); - if (rc != mii_bus_pd->phydev_number) - dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n", - mii_bus_pd->phydev_number); - for (i = 0; i < rc; ++i) { - unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr; - if (phyaddr < PHY_MAX_ADDR) - miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq; - else - dev_err(&pdev->dev, - "Invalid PHY address %i for phydev %i\n", - phyaddr, i); - } - - rc = mdiobus_register(miibus); - if (rc) { - dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); - goto out_err_irq_alloc; - } - - platform_set_drvdata(pdev, miibus); - return 0; - -out_err_irq_alloc: - mdiobus_free(miibus); -out_err_alloc: - peripheral_free_list(pin_req); - - return rc; -} - -static int bfin_mii_bus_remove(struct platform_device *pdev) -{ - struct mii_bus *miibus = platform_get_drvdata(pdev); - struct bfin_mii_bus_platform_data *mii_bus_pd = - dev_get_platdata(&pdev->dev); - - mdiobus_unregister(miibus); - mdiobus_free(miibus); - peripheral_free_list(mii_bus_pd->mac_peripherals); - - return 0; -} - -static struct platform_driver bfin_mii_bus_driver = { - .probe = bfin_mii_bus_probe, - .remove = bfin_mii_bus_remove, - .driver = { - .name = "bfin_mii_bus", - }, -}; - -static struct platform_driver bfin_mac_driver = { - .probe = bfin_mac_probe, - .remove = bfin_mac_remove, - .resume = bfin_mac_resume, - .suspend = bfin_mac_suspend, - .driver = { - .name = KBUILD_MODNAME, - }, -}; - -static struct platform_driver * const drivers[] = { - &bfin_mii_bus_driver, - &bfin_mac_driver, -}; - -static int __init bfin_mac_init(void) -{ - return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); -} - -module_init(bfin_mac_init); - -static void __exit bfin_mac_cleanup(void) -{ - platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); -} - -module_exit(bfin_mac_cleanup); - diff --git a/drivers/net/ethernet/adi/bfin_mac.h b/drivers/net/ethernet/adi/bfin_mac.h deleted file mode 100644 index 4ad5b9be3f84..000000000000 --- a/drivers/net/ethernet/adi/bfin_mac.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Blackfin On-Chip MAC Driver - * - * Copyright 2004-2007 Analog Devices Inc. - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Licensed under the GPL-2 or later. - */ -#ifndef _BFIN_MAC_H_ -#define _BFIN_MAC_H_ - -#include -#include -#include -#include -#include - -/* - * Disable hardware checksum for bug #5600 if writeback cache is - * enabled. Otherwize, corrupted RX packet will be sent up stack - * without error mark. - */ -#ifndef CONFIG_BFIN_EXTMEM_WRITEBACK -#define BFIN_MAC_CSUM_OFFLOAD -#endif - -#define TX_RECLAIM_JIFFIES (HZ / 5) -#define BFIN_MAC_RX_IRQ_DISABLED 1 - -struct dma_descriptor { - struct dma_descriptor *next_dma_desc; - unsigned long start_addr; - unsigned short config; - unsigned short x_count; -}; - -struct status_area_rx { -#if defined(BFIN_MAC_CSUM_OFFLOAD) - unsigned short ip_hdr_csum; /* ip header checksum */ - /* ip payload(udp or tcp or others) checksum */ - unsigned short ip_payload_csum; -#endif - unsigned long status_word; /* the frame status word */ -}; - -struct status_area_tx { - unsigned long status_word; /* the frame status word */ -}; - -/* use two descriptors for a packet */ -struct net_dma_desc_rx { - struct net_dma_desc_rx *next; - struct sk_buff *skb; - struct dma_descriptor desc_a; - struct dma_descriptor desc_b; - struct status_area_rx status; -}; - -/* use two descriptors for a packet */ -struct net_dma_desc_tx { - struct net_dma_desc_tx *next; - struct sk_buff *skb; - struct dma_descriptor desc_a; - struct dma_descriptor desc_b; - unsigned char packet[1560]; - struct status_area_tx status; -}; - -struct bfin_mac_local { - spinlock_t lock; - - int wol; /* Wake On Lan */ - int irq_wake_requested; - struct timer_list tx_reclaim_timer; - struct net_device *ndev; - struct napi_struct napi; - unsigned long flags; - - /* Data for EMAC_VLAN1 regs */ - u16 vlan1_mask, vlan2_mask; - - /* MII and PHY stuffs */ - int old_link; /* used by bf537_adjust_link */ - int old_speed; - int old_duplex; - - struct mii_bus *mii_bus; - -#if defined(CONFIG_BFIN_MAC_USE_HWSTAMP) - u32 addend; - unsigned int shift; - s32 max_ppb; - struct hwtstamp_config stamp_cfg; - struct ptp_clock_info caps; - struct ptp_clock *clock; - int phc_index; - spinlock_t phc_lock; /* protects time lo/hi registers */ -#endif -}; - -int bfin_get_ether_addr(char *addr); - -#endif diff --git a/include/linux/bfin_mac.h b/include/linux/bfin_mac.h deleted file mode 100644 index a69554ef8476..000000000000 --- a/include/linux/bfin_mac.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Blackfin On-Chip MAC Driver - * - * Copyright 2004-2010 Analog Devices Inc. - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _LINUX_BFIN_MAC_H_ -#define _LINUX_BFIN_MAC_H_ - -#include - -struct bfin_phydev_platform_data { - unsigned short addr; - int irq; -}; - -struct bfin_mii_bus_platform_data { - int phydev_number; - struct bfin_phydev_platform_data *phydev_data; - const unsigned short *mac_peripherals; - int phy_mode; - unsigned int phy_mask; - unsigned short vlan1_mask, vlan2_mask; -}; - -#endif -- cgit v1.2.3 From 889ce12b1650b3c388634451872638a08faf6d6b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 16:05:23 +0100 Subject: raid: remove tile specific raid6 implementation The Tile architecture is getting removed, so we no longer need this either. Acked-by: Ard Biesheuvel Signed-off-by: Arnd Bergmann --- include/linux/raid/pq.h | 1 - lib/raid6/Makefile | 6 ---- lib/raid6/algos.c | 3 -- lib/raid6/test/Makefile | 7 ---- lib/raid6/tilegx.uc | 87 ------------------------------------------------- 5 files changed, 104 deletions(-) delete mode 100644 lib/raid6/tilegx.uc (limited to 'include/linux') diff --git a/include/linux/raid/pq.h b/include/linux/raid/pq.h index 583cdd3d49ca..a366cc314479 100644 --- a/include/linux/raid/pq.h +++ b/include/linux/raid/pq.h @@ -105,7 +105,6 @@ extern const struct raid6_calls raid6_avx2x4; extern const struct raid6_calls raid6_avx512x1; extern const struct raid6_calls raid6_avx512x2; extern const struct raid6_calls raid6_avx512x4; -extern const struct raid6_calls raid6_tilegx8; extern const struct raid6_calls raid6_s390vx8; struct raid6_recov_calls { diff --git a/lib/raid6/Makefile b/lib/raid6/Makefile index 4add700ddfe3..44d6b46df051 100644 --- a/lib/raid6/Makefile +++ b/lib/raid6/Makefile @@ -7,7 +7,6 @@ raid6_pq-y += algos.o recov.o tables.o int1.o int2.o int4.o \ raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o avx512.o recov_avx512.o raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o raid6_pq-$(CONFIG_KERNEL_MODE_NEON) += neon.o neon1.o neon2.o neon4.o neon8.o recov_neon.o recov_neon_inner.o -raid6_pq-$(CONFIG_TILEGX) += tilegx8.o raid6_pq-$(CONFIG_S390) += s390vx8.o recov_s390xc.o hostprogs-y += mktables @@ -115,11 +114,6 @@ $(obj)/neon8.c: UNROLL := 8 $(obj)/neon8.c: $(src)/neon.uc $(src)/unroll.awk FORCE $(call if_changed,unroll) -targets += tilegx8.c -$(obj)/tilegx8.c: UNROLL := 8 -$(obj)/tilegx8.c: $(src)/tilegx.uc $(src)/unroll.awk FORCE - $(call if_changed,unroll) - targets += s390vx8.c $(obj)/s390vx8.c: UNROLL := 8 $(obj)/s390vx8.c: $(src)/s390vx.uc $(src)/unroll.awk FORCE diff --git a/lib/raid6/algos.c b/lib/raid6/algos.c index 476994723258..c65aa80d67ed 100644 --- a/lib/raid6/algos.c +++ b/lib/raid6/algos.c @@ -75,9 +75,6 @@ const struct raid6_calls * const raid6_algos[] = { &raid6_altivec4, &raid6_altivec8, #endif -#if defined(CONFIG_TILEGX) - &raid6_tilegx8, -#endif #if defined(CONFIG_S390) &raid6_s390vx8, #endif diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile index be1010bdc435..fabc477b1417 100644 --- a/lib/raid6/test/Makefile +++ b/lib/raid6/test/Makefile @@ -51,9 +51,6 @@ else OBJS += altivec1.o altivec2.o altivec4.o altivec8.o endif endif -ifeq ($(ARCH),tilegx) -OBJS += tilegx8.o -endif .c.o: $(CC) $(CFLAGS) -c -o $@ $< @@ -116,15 +113,11 @@ int16.c: int.uc ../unroll.awk int32.c: int.uc ../unroll.awk $(AWK) ../unroll.awk -vN=32 < int.uc > $@ -tilegx8.c: tilegx.uc ../unroll.awk - $(AWK) ../unroll.awk -vN=8 < tilegx.uc > $@ - tables.c: mktables ./mktables > tables.c clean: rm -f *.o *.a mktables mktables.c *.uc int*.c altivec*.c neon*.c tables.c raid6test - rm -f tilegx*.c spotless: clean rm -f *~ diff --git a/lib/raid6/tilegx.uc b/lib/raid6/tilegx.uc deleted file mode 100644 index 2dd291a11264..000000000000 --- a/lib/raid6/tilegx.uc +++ /dev/null @@ -1,87 +0,0 @@ -/* -*- linux-c -*- ------------------------------------------------------- * - * - * Copyright 2002 H. Peter Anvin - All Rights Reserved - * Copyright 2012 Tilera Corporation - All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, Inc., 53 Temple Place Ste 330, - * Boston MA 02111-1307, USA; either version 2 of the License, or - * (at your option) any later version; incorporated herein by reference. - * - * ----------------------------------------------------------------------- */ - -/* - * tilegx$#.c - * - * $#-way unrolled TILE-Gx SIMD for RAID-6 math. - * - * This file is postprocessed using unroll.awk. - * - */ - -#include - -/* Create 8 byte copies of constant byte */ -# define NBYTES(x) (__insn_v1addi(0, x)) -# define NSIZE 8 - -/* - * The SHLBYTE() operation shifts each byte left by 1, *not* - * rolling over into the next byte - */ -static inline __attribute_const__ u64 SHLBYTE(u64 v) -{ - /* Vector One Byte Shift Left Immediate. */ - return __insn_v1shli(v, 1); -} - -/* - * The MASK() operation returns 0xFF in any byte for which the high - * bit is 1, 0x00 for any byte for which the high bit is 0. - */ -static inline __attribute_const__ u64 MASK(u64 v) -{ - /* Vector One Byte Shift Right Signed Immediate. */ - return __insn_v1shrsi(v, 7); -} - - -void raid6_tilegx$#_gen_syndrome(int disks, size_t bytes, void **ptrs) -{ - u8 **dptr = (u8 **)ptrs; - u64 *p, *q; - int d, z, z0; - - u64 wd$$, wq$$, wp$$, w1$$, w2$$; - u64 x1d = NBYTES(0x1d); - u64 * z0ptr; - - z0 = disks - 3; /* Highest data disk */ - p = (u64 *)dptr[z0+1]; /* XOR parity */ - q = (u64 *)dptr[z0+2]; /* RS syndrome */ - - z0ptr = (u64 *)&dptr[z0][0]; - for ( d = 0 ; d < bytes ; d += NSIZE*$# ) { - wq$$ = wp$$ = *z0ptr++; - for ( z = z0-1 ; z >= 0 ; z-- ) { - wd$$ = *(u64 *)&dptr[z][d+$$*NSIZE]; - wp$$ = wp$$ ^ wd$$; - w2$$ = MASK(wq$$); - w1$$ = SHLBYTE(wq$$); - w2$$ = w2$$ & x1d; - w1$$ = w1$$ ^ w2$$; - wq$$ = w1$$ ^ wd$$; - } - *p++ = wp$$; - *q++ = wq$$; - } -} - -const struct raid6_calls raid6_tilegx$# = { - raid6_tilegx$#_gen_syndrome, - NULL, /* XOR not yet implemented */ - NULL, - "tilegx$#", - 0 -}; -- cgit v1.2.3 From 8cbfbae85085bdd0bdafc085b1ed14abe0349573 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 16:32:20 +0100 Subject: video/logo: remove obsolete logo files The blackfin and m32r architectures are getting removed, so it's time to clean up the logos as well. Acked-by: Bartlomiej Zolnierkiewicz Signed-off-by: Arnd Bergmann --- drivers/video/logo/Kconfig | 15 - drivers/video/logo/Makefile | 3 - drivers/video/logo/logo.c | 12 - drivers/video/logo/logo_blackfin_clut224.ppm | 1127 ---------------------- drivers/video/logo/logo_blackfin_vga16.ppm | 1127 ---------------------- drivers/video/logo/logo_m32r_clut224.ppm | 1292 -------------------------- include/linux/linux_logo.h | 3 - 7 files changed, 3579 deletions(-) delete mode 100644 drivers/video/logo/logo_blackfin_clut224.ppm delete mode 100644 drivers/video/logo/logo_blackfin_vga16.ppm delete mode 100644 drivers/video/logo/logo_m32r_clut224.ppm (limited to 'include/linux') diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig index 0037104d66ac..d1f6196c8b9a 100644 --- a/drivers/video/logo/Kconfig +++ b/drivers/video/logo/Kconfig @@ -27,16 +27,6 @@ config LOGO_LINUX_CLUT224 bool "Standard 224-color Linux logo" default y -config LOGO_BLACKFIN_VGA16 - bool "16-colour Blackfin Processor Linux logo" - depends on BLACKFIN - default y - -config LOGO_BLACKFIN_CLUT224 - bool "224-colour Blackfin Processor Linux logo" - depends on BLACKFIN - default y - config LOGO_DEC_CLUT224 bool "224-color Digital Equipment Corporation Linux logo" depends on MACH_DECSTATION || ALPHA @@ -77,9 +67,4 @@ config LOGO_SUPERH_CLUT224 depends on SUPERH default y -config LOGO_M32R_CLUT224 - bool "224-color M32R Linux logo" - depends on M32R - default y - endif # LOGO diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile index 6194373ee424..228a89b9bdd1 100644 --- a/drivers/video/logo/Makefile +++ b/drivers/video/logo/Makefile @@ -5,8 +5,6 @@ obj-$(CONFIG_LOGO) += logo.o obj-$(CONFIG_LOGO_LINUX_MONO) += logo_linux_mono.o obj-$(CONFIG_LOGO_LINUX_VGA16) += logo_linux_vga16.o obj-$(CONFIG_LOGO_LINUX_CLUT224) += logo_linux_clut224.o -obj-$(CONFIG_LOGO_BLACKFIN_CLUT224) += logo_blackfin_clut224.o -obj-$(CONFIG_LOGO_BLACKFIN_VGA16) += logo_blackfin_vga16.o obj-$(CONFIG_LOGO_DEC_CLUT224) += logo_dec_clut224.o obj-$(CONFIG_LOGO_MAC_CLUT224) += logo_mac_clut224.o obj-$(CONFIG_LOGO_PARISC_CLUT224) += logo_parisc_clut224.o @@ -15,7 +13,6 @@ obj-$(CONFIG_LOGO_SUN_CLUT224) += logo_sun_clut224.o obj-$(CONFIG_LOGO_SUPERH_MONO) += logo_superh_mono.o obj-$(CONFIG_LOGO_SUPERH_VGA16) += logo_superh_vga16.o obj-$(CONFIG_LOGO_SUPERH_CLUT224) += logo_superh_clut224.o -obj-$(CONFIG_LOGO_M32R_CLUT224) += logo_m32r_clut224.o obj-$(CONFIG_SPU_BASE) += logo_spe_clut224.o diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c index 4d50bfd13e7c..36aa050f9a21 100644 --- a/drivers/video/logo/logo.c +++ b/drivers/video/logo/logo.c @@ -63,10 +63,6 @@ const struct linux_logo * __ref fb_find_logo(int depth) /* Generic Linux logo */ logo = &logo_linux_vga16; #endif -#ifdef CONFIG_LOGO_BLACKFIN_VGA16 - /* Blackfin processor logo */ - logo = &logo_blackfin_vga16; -#endif #ifdef CONFIG_LOGO_SUPERH_VGA16 /* SuperH Linux logo */ logo = &logo_superh_vga16; @@ -78,10 +74,6 @@ const struct linux_logo * __ref fb_find_logo(int depth) /* Generic Linux logo */ logo = &logo_linux_clut224; #endif -#ifdef CONFIG_LOGO_BLACKFIN_CLUT224 - /* Blackfin Linux logo */ - logo = &logo_blackfin_clut224; -#endif #ifdef CONFIG_LOGO_DEC_CLUT224 /* DEC Linux logo on MIPS/MIPS64 or ALPHA */ logo = &logo_dec_clut224; @@ -106,10 +98,6 @@ const struct linux_logo * __ref fb_find_logo(int depth) #ifdef CONFIG_LOGO_SUPERH_CLUT224 /* SuperH Linux logo */ logo = &logo_superh_clut224; -#endif -#ifdef CONFIG_LOGO_M32R_CLUT224 - /* M32R Linux logo */ - logo = &logo_m32r_clut224; #endif } return logo; diff --git a/drivers/video/logo/logo_blackfin_clut224.ppm b/drivers/video/logo/logo_blackfin_clut224.ppm deleted file mode 100644 index dc9a50a14477..000000000000 --- a/drivers/video/logo/logo_blackfin_clut224.ppm +++ /dev/null @@ -1,1127 +0,0 @@ -P3 -# This was generated by the GIMP & Netpbm tools -# gimp linux_bf.svg (create 80x80 save as linux_bf.ppm) -# pnmquant 224 linux_bf.ppm | pnmnoraw > logo_blackfin_clut224.ppm -# -80 80 -255 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1 1 1 3 3 3 4 6 6 6 6 6 4 6 6 3 3 3 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 2 2 2 10 10 10 26 26 27 -44 44 45 66 66 66 78 81 81 78 81 81 75 75 76 60 60 60 -39 39 39 20 20 20 6 6 6 1 1 1 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 2 2 2 14 14 14 47 47 47 84 84 84 75 75 76 -47 47 47 12 12 12 0 0 0 0 0 0 0 0 0 20 20 20 -53 54 54 81 81 82 74 74 74 31 31 31 6 6 6 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4 4 4 34 34 35 84 84 84 60 60 60 4 4 4 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 17 18 18 75 75 76 66 66 66 17 18 18 -1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 -42 42 43 84 84 84 8 8 8 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 3 3 36 40 40 10 16 16 0 0 0 31 31 31 84 84 84 -29 29 30 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 26 27 27 -84 84 84 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -15 19 19 114 115 115 110 114 114 44 46 46 0 0 0 12 12 12 -90 87 86 24 24 24 1 1 1 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 75 75 76 -14 14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30 40 40 133 133 133 129 130 130 78 85 85 23 31 30 0 0 0 -19 19 19 78 81 81 13 13 13 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 26 27 27 81 81 82 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -36 40 40 89 90 91 55 63 63 23 31 30 4 6 6 0 0 0 -0 0 0 60 60 60 47 47 47 2 2 2 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 2 2 2 53 54 54 34 34 35 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4 10 10 7 9 9 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 1 1 1 84 84 84 13 13 13 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 4 6 6 78 81 81 2 2 2 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 65 64 64 36 36 36 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 10 11 11 81 81 82 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 12 12 12 67 70 70 4 4 4 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 16 16 16 81 81 82 0 0 0 -0 0 0 0 0 0 4 10 10 44 50 50 18 21 21 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 1 1 78 85 85 120 121 122 7 9 9 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 82 82 81 12 12 12 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 19 19 19 81 81 82 0 0 0 -0 0 0 2 2 2 8 8 8 55 63 63 108 110 110 52 58 58 -0 0 0 0 0 0 0 0 0 0 0 0 42 42 43 129 130 130 -140 142 143 114 115 115 110 114 114 129 130 130 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 75 75 76 24 24 24 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 19 19 19 74 74 74 0 0 0 -4 6 6 167 168 167 196 196 197 196 196 197 61 65 66 78 85 85 -0 0 0 0 0 0 0 0 0 118 118 118 202 202 203 219 219 219 -219 219 219 214 214 215 187 187 188 78 85 85 29 33 34 0 0 0 -0 0 0 0 0 0 0 0 0 60 60 60 39 39 39 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 19 19 19 72 71 71 0 0 0 -185 185 184 244 245 245 250 251 252 251 251 252 247 248 249 36 36 36 -0 0 0 0 0 0 13 13 13 243 243 241 252 252 252 253 253 253 -253 253 253 252 252 252 247 247 246 193 193 194 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 42 42 43 50 51 51 1 1 1 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 19 19 19 78 81 81 0 0 0 -247 247 246 193 193 194 95 97 97 193 193 194 255 255 255 237 237 238 -0 0 0 0 0 0 202 202 203 255 255 255 247 247 246 108 107 107 -82 85 86 167 168 167 255 255 255 248 248 249 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 34 34 35 56 56 56 2 2 2 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 19 19 19 78 81 81 0 0 0 -250 250 251 50 51 51 153 154 155 150 151 151 244 245 245 244 245 245 -44 50 50 84 89 89 153 154 155 255 255 255 140 142 143 0 0 0 -149 149 150 156 155 156 237 237 238 254 254 254 67 70 70 0 0 0 -0 0 0 0 0 0 0 0 0 39 39 39 47 47 47 1 1 1 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 19 19 19 81 81 82 0 0 0 -248 248 249 34 34 35 72 71 71 165 165 165 202 202 203 244 245 245 -10 16 16 82 85 86 89 90 91 255 255 255 95 97 97 0 0 0 -0 0 0 53 54 54 177 177 174 255 255 255 127 127 126 0 0 0 -0 0 0 0 0 0 0 0 0 39 39 39 36 36 36 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 14 14 14 78 81 81 0 0 0 -243 243 243 89 90 91 0 0 0 36 40 40 201 147 55 241 205 27 -241 205 27 241 205 27 241 205 27 238 192 33 108 110 110 0 0 0 -0 0 0 0 0 0 191 190 190 254 254 254 34 34 35 0 0 0 -0 0 0 0 0 0 0 0 0 42 42 43 42 42 43 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 10 10 10 75 75 76 0 0 0 -202 202 203 218 217 217 21 19 17 230 165 41 199 129 48 213 157 40 -244 212 23 243 206 27 180 121 62 243 206 27 244 209 25 226 179 40 -15 10 7 103 103 103 254 254 254 251 251 252 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 17 18 18 58 58 58 2 2 2 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 9 9 9 84 84 84 0 0 0 -0 0 0 226 226 219 213 157 40 244 209 25 245 211 23 245 211 23 -245 214 38 245 214 38 245 211 23 245 211 23 245 211 23 244 212 23 -244 212 23 241 205 27 226 179 40 196 196 197 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 74 74 74 4 6 6 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 7 7 7 84 84 84 0 0 0 -54 42 32 213 157 40 243 206 27 245 211 23 245 211 23 245 211 23 -245 215 41 245 214 35 245 211 23 245 211 23 245 214 35 245 215 41 -245 214 35 245 211 23 245 211 23 238 204 29 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 81 81 82 12 12 12 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 4 6 6 74 74 74 0 0 0 -201 147 55 241 205 27 245 211 23 245 211 23 245 211 23 245 213 29 -245 214 38 245 211 23 245 211 23 245 214 35 245 215 41 245 215 41 -245 213 29 142 83 36 142 83 36 244 209 25 1 1 1 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 74 74 74 25 25 26 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 4 4 4 72 71 71 6 6 6 -213 157 40 244 209 25 245 211 23 245 211 23 245 211 23 245 213 29 -244 212 23 245 211 23 245 214 35 245 215 41 245 215 41 245 213 29 -142 83 36 142 83 36 238 192 33 241 205 27 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 44 44 44 49 50 50 -2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 3 3 3 65 64 64 17 18 18 -199 129 48 199 129 48 245 211 23 245 211 23 245 211 23 245 211 23 -245 211 23 244 212 23 245 214 38 245 214 38 142 83 36 142 83 36 -142 83 36 245 211 23 244 210 23 230 165 41 0 0 0 0 0 0 -78 81 81 114 115 115 73 79 79 0 0 0 3 3 3 81 81 82 -9 9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 1 1 1 49 50 50 29 29 30 -90 87 86 199 129 48 173 101 51 173 101 51 245 211 23 245 211 23 -245 211 23 230 165 41 142 83 36 142 83 36 142 83 36 245 211 23 -244 210 23 241 205 27 230 165 41 175 173 165 3 3 3 0 0 0 -44 46 46 118 118 118 118 118 118 108 110 110 0 0 0 75 75 76 -28 28 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 1 1 1 52 53 53 26 26 27 -118 118 118 175 173 165 199 129 48 173 101 51 173 101 51 173 101 51 -173 101 51 142 83 36 173 101 51 245 211 23 244 209 25 238 204 29 -213 157 40 214 196 166 227 227 227 214 214 215 120 121 122 0 0 0 -0 0 0 108 110 110 118 118 118 118 118 118 0 0 0 23 23 23 -66 66 66 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 7 7 7 75 75 76 4 4 4 -127 127 126 205 205 205 181 181 181 199 129 48 226 179 40 244 209 25 -244 209 25 244 209 25 243 206 27 238 192 33 213 157 40 187 166 103 -234 234 234 248 248 249 251 252 252 248 248 249 214 214 215 0 0 0 -0 0 0 0 0 0 103 103 103 100 103 103 0 0 0 0 0 0 -78 81 81 24 24 24 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 26 27 27 82 82 81 0 0 0 -146 146 147 234 234 234 222 221 221 178 178 179 180 121 62 213 157 40 -213 157 40 213 157 40 201 147 55 180 121 62 219 219 219 243 243 241 -253 253 253 255 255 255 255 255 255 255 255 255 250 250 251 120 121 122 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 20 20 72 71 71 8 8 8 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 10 10 10 75 75 76 22 22 22 0 0 0 -205 205 205 253 253 253 247 248 249 212 211 212 178 178 179 161 161 162 -165 165 165 181 181 181 205 205 205 227 227 227 244 245 245 254 254 254 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 239 239 240 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 67 70 70 39 39 39 2 2 2 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 4 4 4 50 51 51 60 60 60 0 0 0 16 16 16 -249 250 251 255 255 255 255 255 255 240 240 240 209 210 210 193 193 194 -200 200 197 212 211 212 231 231 231 246 247 248 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 253 253 253 -153 154 155 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 3 3 3 84 84 84 20 20 20 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2 2 2 33 33 34 81 81 82 0 0 0 0 0 0 231 231 231 -255 255 255 255 255 255 255 255 255 253 253 253 234 234 234 222 221 221 -227 227 227 237 237 238 250 250 251 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -240 240 240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 26 27 27 72 71 71 8 8 8 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 -21 21 22 84 84 84 7 7 7 0 0 0 150 151 151 252 252 252 -255 255 255 255 255 255 255 255 255 255 255 255 252 252 252 244 245 245 -246 247 248 253 253 253 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -251 251 252 9 9 9 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 65 64 64 47 47 47 3 3 3 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 12 12 -75 75 76 26 26 27 0 0 0 1 1 1 239 239 240 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 202 202 203 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 84 84 84 28 28 29 -1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 4 4 4 55 55 55 -60 60 60 0 0 0 0 0 0 95 97 97 248 248 249 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 244 245 245 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 14 14 14 82 82 81 -15 15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 1 1 1 29 29 30 84 84 84 -0 0 0 0 0 0 0 0 0 156 155 156 247 247 246 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 247 247 246 240 240 240 232 232 233 232 232 233 -243 243 243 253 253 253 53 54 54 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 44 44 -60 60 60 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 10 10 10 81 81 82 14 14 14 -0 0 0 0 0 0 6 6 6 150 151 151 214 214 215 250 251 252 -255 255 255 255 255 255 255 255 255 246 247 248 218 217 217 214 214 215 -218 217 217 244 245 245 255 255 255 255 255 255 255 255 255 250 248 249 -232 232 233 214 214 215 196 196 197 182 183 184 181 181 181 181 181 181 -187 187 188 240 240 240 232 232 233 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -78 81 81 34 34 35 1 1 1 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 1 1 1 39 39 39 74 74 74 0 0 0 -0 0 0 0 0 0 60 60 60 161 161 162 200 200 197 229 229 230 -251 251 252 255 255 255 255 255 255 255 255 255 243 243 241 214 214 215 -248 248 249 255 255 255 255 255 255 255 255 255 255 255 255 254 254 254 -239 239 240 214 214 215 193 193 194 182 183 184 178 178 179 176 177 177 -176 177 177 182 183 184 248 248 249 14 14 14 0 0 0 61 65 66 -10 16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 10 10 84 84 84 13 13 13 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 10 11 11 82 82 81 7 7 7 0 0 0 -0 0 0 0 0 0 165 165 165 229 229 230 249 250 251 254 254 254 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 253 253 253 240 240 240 227 227 227 205 205 205 -181 181 181 176 177 177 191 190 190 227 227 227 0 0 0 44 50 50 -84 89 89 61 65 66 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 58 58 58 49 50 50 3 3 3 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 1 1 1 36 36 36 66 66 66 0 0 0 29 33 34 -0 3 3 26 27 27 234 234 234 254 254 254 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -254 254 254 253 253 254 252 253 253 253 253 254 253 254 254 253 254 254 -254 254 254 255 255 255 255 255 255 255 255 255 255 255 255 251 251 252 -227 227 227 187 187 188 176 177 177 222 221 221 13 13 13 0 0 0 -12 15 14 73 79 79 36 40 40 0 0 0 0 0 0 0 0 0 -0 0 0 1 1 1 90 87 86 17 18 18 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 7 7 7 78 81 81 12 12 12 23 31 30 52 58 58 -0 0 0 209 210 210 253 253 253 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 254 254 254 -251 251 252 150 151 151 103 103 103 129 130 130 196 196 197 250 250 251 -252 252 253 254 254 254 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 240 240 240 193 193 194 196 196 197 229 229 230 0 0 0 -0 0 0 4 10 10 30 40 40 0 3 3 0 0 0 0 0 0 -0 0 0 0 0 0 47 47 47 53 54 54 3 3 3 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 23 23 23 81 81 82 0 0 0 52 58 58 36 40 40 -42 42 43 250 250 251 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 254 254 254 -227 227 227 7 7 7 7 7 7 7 7 7 7 7 7 44 44 45 -156 155 156 249 250 251 253 253 253 254 254 254 255 255 255 255 255 255 -255 255 255 255 255 255 247 247 246 222 221 221 239 239 240 0 0 0 -30 40 40 44 50 50 23 31 30 29 33 34 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 90 87 86 16 16 16 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2 2 2 50 51 51 42 42 43 29 33 34 52 58 58 0 0 0 -232 232 233 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 254 254 254 -250 251 252 44 44 44 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 56 56 56 209 210 210 252 252 253 254 254 254 255 255 255 -255 255 255 255 255 255 255 255 255 254 253 253 249 250 251 146 146 147 -36 40 40 44 50 50 36 40 40 67 70 70 61 65 66 0 0 0 -0 0 0 0 0 0 0 0 0 55 55 55 44 44 45 1 1 1 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 10 10 81 81 82 1 1 1 52 58 58 44 50 50 52 53 53 -251 251 252 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 254 254 254 -253 253 253 187 187 188 8 8 8 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 19 19 19 178 178 179 252 252 253 254 254 254 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 237 237 238 -10 16 16 30 40 40 0 3 3 23 31 30 84 89 89 0 0 0 -0 0 0 0 0 0 0 0 0 3 3 3 81 81 82 9 9 9 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -29 29 30 72 71 71 10 16 16 52 58 58 0 0 0 222 221 221 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -254 254 254 251 251 252 95 97 97 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 10 10 10 161 161 162 251 252 252 -254 254 254 255 255 255 255 255 255 255 255 255 255 255 255 248 248 249 -0 0 0 0 0 0 0 0 0 0 0 0 84 89 89 0 3 3 -0 0 0 0 0 0 0 0 0 0 0 0 74 74 74 26 27 27 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 4 4 -65 64 64 20 20 20 20 25 25 30 40 40 0 0 0 247 247 246 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 253 253 254 222 221 221 9 9 9 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 149 149 150 -252 252 253 254 254 254 255 255 255 255 255 255 255 255 255 252 252 252 -0 0 0 0 0 0 0 0 0 0 0 0 73 79 79 12 15 14 -0 0 0 0 0 0 0 0 0 0 0 0 36 36 36 58 58 58 -3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 20 -74 74 74 0 0 0 4 10 10 4 10 10 36 36 36 252 252 252 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 227 227 227 253 253 253 255 255 255 -255 255 255 254 254 254 250 251 252 65 64 64 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 -146 146 147 251 252 252 254 254 254 255 255 255 255 255 255 253 254 254 -0 0 0 0 0 0 0 0 0 0 0 0 52 58 58 10 16 16 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 82 81 -9 9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 4 6 6 65 64 64 -25 25 25 0 3 3 30 40 40 0 0 0 187 187 188 254 254 254 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 193 193 194 253 252 252 255 255 255 -255 255 255 255 255 255 252 253 253 129 130 130 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -8 8 8 149 149 150 252 252 253 254 254 254 255 255 255 254 254 254 -52 53 53 0 0 0 0 0 0 0 0 0 20 25 25 2 5 4 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 81 82 -20 20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 26 26 27 81 81 82 -0 0 0 18 21 21 73 79 79 0 0 0 237 237 238 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 182 183 184 255 255 255 255 255 255 -255 255 255 255 255 255 253 253 253 176 177 177 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 8 8 8 153 154 155 251 252 252 254 254 254 255 255 255 -150 151 151 0 0 0 0 0 0 0 0 0 20 25 25 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65 64 64 -33 33 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 6 6 6 67 70 70 20 20 20 -0 0 0 23 31 30 82 85 86 0 0 0 247 247 246 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 182 183 184 255 255 255 255 255 255 -255 255 255 255 255 255 253 254 254 214 214 215 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 8 8 8 156 155 156 252 252 253 254 254 254 -167 168 167 0 0 0 0 0 0 0 0 0 67 70 70 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 47 47 -44 44 44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 21 21 22 75 75 76 0 0 0 -0 0 0 29 33 34 84 89 89 0 0 0 248 248 249 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 248 248 249 181 181 181 255 255 255 255 255 255 -255 255 255 255 255 255 254 254 254 240 240 240 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 8 8 8 161 161 162 251 252 252 -185 185 184 4 4 4 0 0 0 10 11 11 100 103 103 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 36 36 -55 55 55 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 33 33 34 50 51 51 0 0 0 -0 0 0 9 11 11 82 85 86 10 16 16 248 248 249 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 245 244 245 179 180 181 255 255 255 255 255 255 -255 255 255 255 255 255 254 254 254 251 252 252 20 20 20 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 10 10 10 161 161 162 -205 205 205 17 18 18 0 0 0 95 97 97 78 81 81 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 36 36 -53 54 54 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 31 31 31 58 58 58 0 0 0 -0 0 0 0 0 0 67 70 70 78 81 81 248 248 249 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 234 234 234 179 180 181 255 255 255 255 255 255 -255 255 255 255 255 255 254 254 254 251 252 252 23 23 23 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -10 11 11 84 84 84 161 161 162 209 210 210 229 229 230 237 237 238 -202 202 203 26 26 27 9 11 11 44 50 50 0 0 0 4 6 6 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52 53 53 -39 39 39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 23 23 23 78 81 81 213 157 40 -243 206 27 243 206 27 54 42 32 73 79 79 222 221 221 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 238 238 236 178 178 179 255 255 255 255 255 255 -255 255 255 255 255 255 254 254 254 251 252 253 36 36 36 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 84 84 84 -222 221 221 251 252 252 252 253 253 253 253 253 253 254 254 252 252 253 -146 146 147 140 142 143 156 155 156 110 114 114 26 27 27 82 85 86 -84 89 89 95 97 97 36 40 40 0 0 0 0 0 0 74 74 74 -23 23 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 14 14 14 -24 24 24 26 26 27 26 26 27 26 26 27 25 25 26 21 21 22 -7 7 7 0 0 0 1 1 1 34 34 35 238 192 33 244 210 23 -244 212 23 244 212 23 244 210 23 88 79 47 200 200 197 254 254 254 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 244 245 245 179 180 181 255 255 255 255 255 255 -255 255 255 255 255 255 254 254 254 252 252 253 36 36 36 7 7 7 -7 7 7 7 7 7 7 7 7 8 8 8 149 149 150 251 251 252 -252 252 253 253 253 253 253 253 253 250 248 249 239 223 156 239 223 156 -120 121 122 182 183 184 176 177 177 120 121 122 33 33 34 3 3 3 -0 0 0 67 70 70 146 146 147 20 25 25 1 1 1 82 82 81 -9 9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 19 19 19 89 90 91 -146 146 147 150 151 151 150 151 151 150 151 151 150 151 151 129 130 130 -58 58 58 6 6 6 14 14 14 201 147 55 245 211 23 245 213 29 -245 214 35 245 215 41 245 213 29 244 210 23 142 83 36 232 232 233 -254 254 254 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 185 185 184 255 255 255 255 255 255 -255 255 255 255 255 255 254 254 254 251 252 252 50 51 51 7 7 7 -7 7 7 7 7 7 7 7 7 146 146 147 251 252 252 252 253 253 -251 252 253 239 239 240 171 168 154 129 130 130 137 136 134 175 173 165 -221 218 200 65 64 64 22 22 22 186 186 187 114 115 115 26 26 27 -2 2 2 0 0 0 61 65 66 31 33 27 238 192 33 108 96 91 -9 9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 2 2 2 52 53 53 178 178 179 -21 21 22 7 7 7 7 7 7 7 7 7 7 7 7 118 118 118 -137 136 134 36 36 36 65 64 64 243 206 27 244 212 23 245 215 41 -245 215 41 245 215 41 245 215 41 244 209 25 244 209 25 1 1 1 -219 219 219 253 253 253 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 214 214 215 255 255 255 255 255 255 -255 255 255 255 255 255 254 254 254 252 252 253 50 51 51 7 7 7 -7 7 7 7 7 7 84 84 84 250 251 252 252 253 253 251 251 252 -167 168 167 22 22 22 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 34 34 35 187 187 188 103 103 103 -29 29 30 3 3 3 7 9 9 238 204 29 245 215 41 245 214 35 -28 28 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 7 7 7 90 87 86 178 178 179 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 16 16 16 -193 193 194 133 133 133 187 166 103 245 218 76 245 218 76 245 216 51 -245 216 51 245 218 76 246 224 96 245 218 76 245 218 76 245 218 76 -25 25 25 186 186 187 252 252 252 254 254 254 254 254 254 253 254 254 -254 254 254 254 254 254 254 254 254 246 247 248 254 254 254 253 254 254 -254 254 254 254 254 254 253 254 254 251 252 252 36 36 36 7 7 7 -7 7 7 20 20 20 229 229 230 253 253 253 252 253 253 178 178 179 -10 10 10 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 42 42 43 196 196 197 -118 118 118 33 33 34 238 204 29 245 215 41 245 215 41 245 215 41 -49 50 50 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 17 18 18 120 121 122 137 136 134 -7 7 7 7 7 7 34 34 35 20 20 20 7 7 7 7 7 7 -202 202 203 209 206 202 193 187 162 193 187 162 248 234 156 245 218 76 -245 218 76 248 234 156 193 187 162 193 187 162 193 187 162 214 196 166 -240 219 129 95 97 97 196 196 197 186 186 187 187 187 188 196 196 197 -252 252 253 251 252 253 212 211 212 187 187 188 196 196 197 251 252 252 -218 217 217 187 187 188 191 190 190 250 251 252 24 24 24 7 7 7 -7 7 7 110 114 114 252 252 253 253 254 254 250 251 252 89 90 91 -89 90 91 129 130 130 127 127 126 44 44 44 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 49 50 50 -202 202 203 214 196 166 245 216 51 245 214 38 245 214 35 245 214 38 -58 58 58 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 31 31 31 156 155 156 82 82 81 -7 7 7 10 10 10 237 237 238 66 66 66 7 7 7 25 25 25 -247 248 249 81 81 82 7 7 7 31 31 31 247 237 174 245 218 76 -246 226 108 200 200 197 7 7 7 7 7 7 7 7 7 137 136 134 -247 237 174 193 193 194 72 71 71 7 7 7 7 7 7 8 8 8 -196 196 197 250 251 252 67 70 70 7 7 7 84 84 84 244 245 245 -47 47 47 7 7 7 118 118 118 249 250 251 12 12 12 7 7 7 -9 9 9 218 217 217 253 253 253 254 254 254 252 253 253 251 251 252 -249 250 251 237 237 238 95 97 97 9 9 9 15 15 15 95 97 97 -47 47 47 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -66 66 66 240 230 197 246 226 108 245 214 38 245 211 23 244 212 23 -65 64 64 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 2 2 2 52 53 53 185 185 184 25 25 25 -7 7 7 60 60 60 240 240 240 14 14 14 7 7 7 84 84 84 -247 248 249 23 23 23 7 7 7 94 91 88 248 234 156 245 218 76 -248 234 156 127 127 126 7 7 7 7 7 7 7 7 7 167 168 167 -251 248 240 65 64 64 7 7 7 7 7 7 7 7 7 7 7 7 -84 84 84 243 243 243 15 15 15 7 7 7 140 142 143 146 146 147 -7 7 7 33 33 34 237 237 238 243 243 243 21 21 22 120 121 122 -218 217 217 252 252 253 254 254 254 253 253 254 252 253 253 251 252 252 -247 248 249 72 71 71 7 7 7 58 58 58 222 221 221 248 248 249 -75 75 76 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 82 82 81 246 239 193 246 226 108 245 216 51 245 214 38 -238 192 33 21 21 22 1 1 1 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 8 8 8 90 87 86 182 183 184 7 7 7 -7 7 7 120 121 122 187 187 188 7 7 7 7 7 7 146 146 147 -205 205 205 7 7 7 7 7 7 153 153 148 240 219 129 246 224 96 -246 239 193 39 39 39 60 60 60 108 110 110 7 7 7 202 202 203 -227 227 227 7 7 7 7 7 7 205 205 205 89 90 91 7 7 7 -120 121 122 193 193 194 7 7 7 7 7 7 186 186 187 25 25 25 -7 7 7 167 168 167 251 251 252 243 243 243 214 214 215 250 251 252 -251 252 253 254 254 254 253 253 253 219 219 219 140 140 139 140 140 139 -118 118 118 7 7 7 52 53 53 237 237 238 247 247 246 176 177 177 -8 8 8 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 95 97 97 246 239 193 246 226 108 245 216 51 -245 214 38 201 147 55 31 31 31 103 103 103 103 103 103 72 71 71 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 17 18 18 127 127 126 140 140 139 7 7 7 -7 7 7 17 18 18 17 18 18 7 7 7 95 97 97 244 245 245 -146 146 147 7 7 7 7 7 7 200 200 197 246 226 108 240 219 129 -194 194 184 7 7 7 140 140 139 89 90 91 7 7 7 232 232 233 -165 165 165 7 7 7 31 31 31 249 250 251 39 39 39 7 7 7 -176 177 177 133 133 133 7 7 7 22 22 22 108 110 110 7 7 7 -72 71 71 251 252 252 252 253 253 250 251 252 247 248 249 205 205 205 -251 252 253 254 254 254 252 252 253 84 84 84 7 7 7 7 7 7 -7 7 7 7 7 7 140 142 143 247 248 249 140 140 139 14 14 14 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 16 16 16 -14 14 14 7 7 7 7 7 7 114 115 115 246 239 193 246 224 96 -245 216 51 245 216 51 243 235 220 176 177 177 185 185 184 229 229 230 -47 47 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 31 31 31 156 155 156 90 87 86 7 7 7 -7 7 7 7 7 7 7 7 7 31 31 31 243 243 241 247 247 246 -84 84 84 7 7 7 26 27 27 246 239 193 246 226 108 248 234 156 -108 110 110 7 7 7 212 211 212 44 44 44 22 22 22 249 250 251 -108 107 107 7 7 7 89 90 91 238 238 236 114 115 115 118 118 118 -231 231 231 75 75 76 7 7 7 34 34 35 10 11 11 12 12 12 -214 214 215 253 253 253 253 253 253 200 200 197 31 31 31 103 103 103 -252 252 253 252 253 253 218 217 217 9 9 9 7 7 7 7 7 7 -7 7 7 7 7 7 25 25 25 39 39 39 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 103 103 103 234 234 234 -181 181 181 7 7 7 7 7 7 7 7 7 133 133 133 247 237 174 -246 224 96 246 226 108 185 185 184 177 177 174 153 154 155 181 181 181 -140 140 139 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 1 1 1 49 50 50 186 186 187 28 28 28 7 7 7 -12 12 12 22 22 22 7 7 7 7 7 7 108 107 107 247 247 246 -25 25 25 7 7 7 90 87 86 247 237 174 246 226 108 246 239 193 -28 28 28 44 44 44 237 237 238 9 9 9 53 54 54 249 250 251 -49 50 50 7 7 7 153 153 148 249 241 199 214 196 166 185 185 184 -229 229 230 19 19 19 7 7 7 7 7 7 7 7 7 103 103 103 -251 252 253 254 254 254 253 253 253 150 151 151 7 7 7 187 187 188 -252 252 253 251 251 252 103 103 103 7 7 7 7 7 7 7 7 7 -7 7 7 23 23 23 17 18 18 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 12 12 12 153 153 148 246 239 193 249 241 199 -161 161 162 9 9 9 84 84 84 108 110 110 25 25 25 153 153 148 -247 237 174 246 224 96 218 217 217 165 165 165 182 183 184 193 193 194 -114 115 115 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 4 4 4 74 74 74 181 181 181 7 7 7 7 7 7 -110 114 114 200 200 197 7 7 7 7 7 7 60 60 60 209 210 210 -7 7 7 7 7 7 146 146 147 248 234 156 248 234 156 177 177 174 -7 7 7 118 118 118 193 193 194 7 7 7 84 84 84 232 232 233 -8 8 8 7 7 7 209 210 210 221 218 200 193 187 162 219 219 219 -200 200 197 7 7 7 7 7 7 7 7 7 7 7 7 95 97 97 -251 252 252 254 254 254 252 253 253 118 118 118 29 29 30 247 248 249 -252 252 253 227 227 227 16 16 16 7 7 7 7 7 7 7 7 7 -100 103 103 218 217 217 219 218 214 7 7 7 7 7 7 7 7 7 -7 7 7 21 21 22 185 185 184 246 239 193 248 234 156 240 230 197 -60 60 60 194 194 184 246 239 193 249 241 199 137 136 134 10 10 10 -171 168 154 248 234 156 248 234 156 226 226 219 209 210 210 249 241 199 -28 28 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 13 13 13 108 110 110 146 146 147 7 7 7 7 7 7 -167 168 167 140 140 139 7 7 7 7 7 7 120 121 122 146 146 147 -7 7 7 7 7 7 194 194 184 240 219 129 247 237 174 95 97 97 -7 7 7 95 97 97 90 87 86 7 7 7 118 118 118 176 177 177 -7 7 7 28 28 28 248 248 249 44 44 45 7 7 7 167 168 167 -140 140 139 7 7 7 36 36 36 74 74 74 7 7 7 65 64 64 -251 252 253 254 254 254 251 252 252 81 81 82 108 110 110 251 252 252 -251 251 252 127 127 126 7 7 7 7 7 7 8 8 8 140 140 139 -181 181 181 140 140 139 221 218 200 7 7 7 7 7 7 7 7 7 -34 34 35 209 210 210 231 231 231 246 239 193 247 237 174 194 194 184 -227 227 227 249 241 199 240 219 129 248 234 156 153 153 148 7 7 7 -13 13 13 185 185 184 248 234 156 245 218 76 245 216 51 245 214 38 -31 31 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 31 31 31 153 154 155 89 90 91 7 7 7 8 8 8 -232 232 233 82 82 81 7 7 7 7 7 7 179 180 181 89 90 91 -7 7 7 24 24 24 243 235 220 248 234 156 240 230 197 20 20 20 -7 7 7 7 7 7 7 7 7 7 7 7 149 149 150 118 118 118 -7 7 7 90 87 86 229 229 230 7 7 7 7 7 7 229 229 230 -82 82 81 7 7 7 95 97 97 100 103 103 7 7 7 34 34 35 -251 252 252 253 253 254 251 251 252 47 47 47 193 193 194 251 252 252 -239 239 240 23 23 23 7 7 7 13 13 13 165 165 165 234 234 234 -149 149 150 146 114 101 200 200 197 7 7 7 7 7 7 52 53 53 -227 227 227 167 168 167 16 16 16 214 196 166 248 234 156 243 235 220 -219 219 219 156 155 156 247 237 174 246 239 193 75 75 76 7 7 7 -60 60 60 227 227 227 243 235 220 240 219 129 245 218 76 245 213 29 -16 16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -1 1 1 49 50 50 185 185 184 33 33 34 7 7 7 10 11 11 -56 56 56 16 16 16 7 7 7 10 10 10 237 237 238 26 27 27 -7 7 7 55 55 55 185 185 184 221 218 200 167 168 167 7 7 7 -20 20 20 39 39 39 10 11 11 7 7 7 181 181 181 58 58 58 -7 7 7 103 103 103 133 133 133 7 7 7 44 44 44 247 248 249 -24 24 24 7 7 7 156 155 156 129 130 130 7 7 7 9 9 9 -244 245 245 252 253 253 237 237 238 34 34 35 248 248 249 251 251 252 -161 161 162 7 7 7 24 24 24 187 187 188 212 211 212 67 70 70 -187 187 188 173 170 143 209 206 202 10 10 10 95 97 97 237 237 238 -129 130 130 8 8 8 89 90 91 246 239 193 247 237 174 177 177 174 -17 18 18 137 136 134 249 241 199 219 218 214 10 10 10 95 97 97 -243 243 243 150 151 151 31 31 31 221 218 200 240 219 129 53 54 54 -3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -4 4 4 72 71 71 182 183 184 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 12 12 12 161 161 162 209 210 210 7 7 7 -7 7 7 7 7 7 7 7 7 187 187 188 82 82 81 7 7 7 -146 146 147 247 248 249 17 18 18 7 7 7 212 211 212 47 47 47 -7 7 7 7 7 7 7 7 7 8 8 8 146 146 147 205 205 205 -7 7 7 7 7 7 214 214 215 156 155 156 7 7 7 7 7 7 -218 217 217 251 252 252 186 186 187 110 114 114 249 250 251 248 248 249 -75 75 76 34 34 35 205 205 205 129 130 130 16 16 16 7 7 7 -156 155 156 214 196 166 240 230 197 243 243 241 227 227 227 74 74 74 -7 7 7 29 29 30 226 226 219 249 241 199 175 173 165 14 14 14 -9 9 9 221 218 200 246 239 193 153 153 148 146 146 147 246 247 248 -110 114 114 7 7 7 7 7 7 42 42 43 193 193 194 95 97 97 -19 19 19 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -6 6 6 84 84 84 140 142 143 7 7 7 7 7 7 7 7 7 -7 7 7 20 20 20 177 177 174 249 241 199 149 149 150 7 7 7 -7 7 7 7 7 7 10 11 11 226 226 219 13 13 13 8 8 8 -219 218 214 219 218 214 7 7 7 8 8 8 238 238 236 200 200 197 -13 13 13 7 7 7 13 13 13 161 161 162 243 235 220 146 146 147 -7 7 7 29 29 30 232 232 233 176 177 177 7 7 7 7 7 7 -182 183 184 237 237 238 129 130 130 167 168 167 176 177 177 202 202 203 -10 11 11 95 97 97 44 44 45 7 7 7 7 7 7 7 7 7 -75 75 76 226 226 219 243 235 220 156 155 156 24 24 24 7 7 7 -7 7 7 176 177 177 247 247 246 200 200 197 17 18 18 7 7 7 -49 50 50 246 239 193 248 234 156 251 248 240 239 239 240 84 84 84 -7 7 7 7 7 7 7 7 7 7 7 7 60 60 60 187 187 188 -84 84 84 14 14 14 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -4 4 4 53 54 54 137 136 134 156 155 156 161 161 162 161 161 162 -167 168 167 239 223 156 240 219 129 246 226 108 239 223 156 239 223 156 -239 223 156 239 223 156 214 196 166 239 223 156 193 187 162 193 187 162 -248 234 156 239 223 156 193 187 162 193 187 162 248 234 156 248 234 156 -214 196 166 193 187 162 214 196 166 248 234 156 240 219 129 214 196 166 -193 187 162 193 187 162 171 168 154 146 146 147 137 136 134 137 136 134 -161 161 162 209 210 210 65 64 64 202 202 203 179 180 181 140 140 139 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 60 60 60 39 39 39 7 7 7 7 7 7 7 7 7 -66 66 66 249 250 251 202 202 203 16 16 16 7 7 7 7 7 7 -23 23 23 243 235 220 246 239 193 226 226 219 52 53 53 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 75 75 76 -176 177 177 66 66 66 9 9 9 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 10 10 10 28 28 29 34 34 35 36 36 36 36 36 36 -44 44 45 146 114 101 241 207 50 241 207 50 241 207 50 241 211 63 -241 211 63 241 211 63 241 211 63 241 211 63 241 211 63 245 216 51 -245 216 51 245 216 51 241 211 63 241 211 63 245 216 51 241 211 63 -245 218 76 245 218 76 245 216 51 245 215 41 245 214 38 241 207 50 -241 211 63 201 147 55 88 79 47 29 29 30 34 34 35 42 42 43 -103 103 103 191 190 190 75 75 76 196 196 197 200 200 197 65 64 64 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -90 87 86 146 146 147 19 19 19 7 7 7 7 7 7 7 7 7 -7 7 7 90 87 86 140 140 139 31 31 31 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -103 103 103 161 161 162 53 54 54 7 7 7 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 12 12 12 50 51 51 146 114 101 180 121 62 199 129 48 -201 147 55 213 157 40 213 157 40 230 165 41 226 179 40 226 179 40 -238 192 33 241 205 27 244 209 25 244 210 23 244 212 23 245 211 23 -245 211 23 245 211 23 245 211 23 244 209 25 238 204 29 226 179 40 -213 157 40 199 129 48 54 42 32 0 0 0 4 6 6 44 44 45 -150 151 151 129 130 130 137 136 134 205 205 205 202 202 203 8 8 8 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 129 130 130 146 146 147 47 47 47 4 4 4 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 2 2 2 12 12 12 28 28 29 49 50 50 -74 74 74 108 96 91 180 121 62 180 121 62 199 129 48 201 147 55 -213 157 40 230 165 41 226 179 40 238 192 33 241 205 27 241 205 27 -243 206 27 243 206 27 241 205 27 238 204 29 226 179 40 213 157 40 -199 129 48 199 129 48 21 19 17 65 64 64 103 103 103 167 168 167 -202 202 203 24 24 24 193 193 194 229 229 230 140 140 139 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 8 8 8 156 155 156 133 133 133 36 36 36 3 3 3 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 -4 4 4 10 11 11 21 21 22 39 39 39 60 60 60 108 96 91 -180 121 62 199 129 48 199 129 48 213 157 40 230 165 41 226 179 40 -226 179 40 226 179 40 226 179 40 226 179 40 213 157 40 199 129 48 -180 121 62 99 91 79 72 71 71 56 56 56 129 130 130 167 168 167 -21 21 22 17 18 18 231 231 231 229 229 230 52 53 53 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 13 13 13 176 177 177 120 121 122 33 33 34 -2 2 2 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 8 8 8 -21 21 22 47 47 47 99 91 79 180 121 62 199 129 48 199 129 48 -201 147 55 213 157 40 213 157 40 201 147 55 199 129 48 180 121 62 -99 91 79 26 26 27 9 9 9 60 60 60 186 186 187 31 31 31 -7 7 7 60 60 60 243 243 243 209 210 210 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 -7 7 7 7 7 7 7 7 7 26 27 27 193 193 194 108 110 110 -22 22 22 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 1 1 1 8 8 8 24 24 24 58 58 58 108 96 91 -180 121 62 180 121 62 180 121 62 180 121 62 180 121 62 72 71 71 -15 15 15 0 0 0 4 6 6 75 75 76 156 155 156 24 24 24 -24 24 24 108 107 107 232 232 233 137 136 134 24 24 24 24 24 24 -24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 -24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 -24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 -24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 -24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 -24 24 24 24 24 24 24 24 24 24 24 24 58 58 58 176 177 177 -60 60 60 3 3 3 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 12 12 12 -26 27 27 44 44 44 55 55 55 50 51 51 29 29 30 8 8 8 -0 0 0 0 0 0 3 3 3 47 47 47 127 127 126 150 151 151 -150 151 151 140 142 143 129 130 130 140 142 143 150 151 151 150 151 151 -150 151 151 150 151 151 150 151 151 150 151 151 150 151 151 150 151 151 -150 151 151 150 151 151 153 154 155 161 161 162 165 165 165 167 168 167 -177 177 174 167 168 167 161 161 162 156 155 156 150 151 151 150 151 151 -150 151 151 150 151 151 150 151 151 150 151 151 150 151 151 150 151 151 -150 151 151 150 151 151 150 151 151 150 151 151 150 151 151 150 151 151 -150 151 151 150 151 151 150 151 151 150 151 151 149 149 150 127 127 126 -44 44 45 2 2 2 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 2 2 2 1 1 1 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 7 7 7 21 21 22 25 25 26 -25 25 26 24 24 24 20 20 20 23 23 24 25 25 26 26 26 27 -26 26 27 26 26 27 26 26 27 26 26 27 26 26 27 26 26 27 -26 26 27 26 26 27 26 26 27 26 26 27 26 26 27 26 27 27 -28 28 29 26 27 27 26 26 27 26 26 27 26 26 27 26 26 27 -26 26 27 26 26 27 26 26 27 26 26 27 26 26 27 26 26 27 -26 26 27 26 26 27 26 26 27 26 26 27 26 26 27 26 26 27 -26 26 27 26 26 27 26 26 27 26 26 27 25 25 26 21 21 22 -7 7 7 0 0 0 diff --git a/drivers/video/logo/logo_blackfin_vga16.ppm b/drivers/video/logo/logo_blackfin_vga16.ppm deleted file mode 100644 index 1352b02a9d93..000000000000 --- a/drivers/video/logo/logo_blackfin_vga16.ppm +++ /dev/null @@ -1,1127 +0,0 @@ -P3 -# This was generated by the GIMP & Netpbm tools -# gimp linux_bf.svg (create 80x80 save as linux_bf.ppm) -# ppmquant -mapfile clut_vga16.ppm linux_bf.ppm | pnmnoraw > logo_blackfin_vga16.ppm -# -80 80 -255 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 -170 170 170 85 85 85 85 85 85 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 170 170 170 170 170 170 170 170 170 85 85 85 85 85 85 -0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 255 255 255 -255 255 255 255 255 255 170 170 170 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 -0 0 0 0 0 0 0 0 0 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -255 255 255 170 170 170 85 85 85 170 170 170 255 255 255 255 255 255 -0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 85 85 85 -85 85 85 170 170 170 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -255 255 255 85 85 85 170 170 170 170 170 170 255 255 255 255 255 255 -85 85 85 85 85 85 170 170 170 255 255 255 170 170 170 0 0 0 -170 170 170 170 170 170 255 255 255 255 255 255 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -255 255 255 0 0 0 85 85 85 170 170 170 170 170 170 255 255 255 -0 0 0 85 85 85 85 85 85 255 255 255 85 85 85 0 0 0 -0 0 0 85 85 85 170 170 170 255 255 255 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -255 255 255 85 85 85 0 0 0 0 0 0 255 85 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 85 85 85 0 0 0 -0 0 0 0 0 0 170 170 170 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -170 170 170 255 255 255 0 0 0 255 85 85 170 85 0 170 85 0 -255 255 85 255 255 85 170 85 0 255 255 85 255 255 85 255 255 85 -0 0 0 85 85 85 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 255 255 255 255 85 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 255 85 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -170 85 0 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 170 85 0 85 85 85 255 255 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -255 85 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -170 85 0 85 85 85 255 255 85 255 255 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -170 85 0 170 85 0 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 170 85 0 170 85 0 -170 85 0 255 255 85 255 255 85 255 85 85 0 0 0 0 0 0 -85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -85 85 85 170 85 0 170 85 0 170 85 0 255 255 85 255 255 85 -255 255 85 255 85 85 170 85 0 170 85 0 170 85 0 255 255 85 -255 255 85 255 255 85 255 85 85 170 170 170 0 0 0 0 0 0 -85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -85 85 85 170 170 170 170 85 0 170 85 0 170 85 0 170 85 0 -170 85 0 170 85 0 170 85 0 255 255 85 255 255 85 255 255 85 -255 85 85 170 170 170 255 255 255 255 255 255 85 85 85 0 0 0 -0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -170 170 170 170 170 170 170 170 170 170 85 0 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 85 85 170 170 170 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 -0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -170 170 170 255 255 255 255 255 255 170 170 170 170 85 0 255 85 85 -255 85 85 255 85 85 255 85 85 255 85 85 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -170 170 170 255 255 255 255 255 255 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 -255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170 -170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 170 170 170 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -85 85 85 0 0 0 0 0 0 85 85 85 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 255 255 255 255 255 255 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 85 85 85 170 170 170 170 170 170 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 255 255 255 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 -170 170 170 170 170 170 170 170 170 255 255 255 0 0 0 85 85 85 -85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 170 170 170 170 170 170 255 255 255 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 -0 0 0 170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 170 170 170 85 85 85 170 170 170 170 170 170 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 170 170 170 170 170 170 255 255 255 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 -0 0 0 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 -0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 85 85 85 0 0 0 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 255 255 255 -170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 -170 170 170 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 -170 170 170 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 -170 170 170 0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 -0 0 0 0 0 0 85 85 85 85 85 85 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 170 170 170 255 255 255 255 255 255 -170 170 170 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 -255 255 85 255 255 85 0 0 0 85 85 85 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -170 170 170 170 170 170 170 170 170 85 85 85 0 0 0 85 85 85 -85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 85 85 85 170 170 170 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 85 170 170 170 -85 85 85 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -85 85 85 0 0 0 0 0 0 170 85 0 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 170 85 0 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 -255 255 255 255 255 255 170 170 170 170 170 170 170 170 170 170 170 170 -255 255 255 85 85 85 0 0 0 170 170 170 85 85 85 0 0 0 -0 0 0 0 0 0 85 85 85 0 0 0 255 255 85 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -170 170 170 0 0 0 85 85 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 0 0 0 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 85 85 85 0 0 0 -0 0 0 0 0 0 85 85 85 255 255 255 255 255 255 255 255 255 -170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 0 0 0 0 0 0 255 255 85 255 255 85 255 255 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -170 170 170 170 170 170 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -0 0 0 170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 -0 0 0 0 0 0 255 255 255 255 255 255 255 255 255 170 170 170 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 -85 85 85 0 0 0 255 255 85 255 255 85 255 255 85 255 255 85 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -170 170 170 170 170 170 170 170 170 170 170 170 255 255 85 255 255 85 -255 255 85 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 -255 255 85 85 85 85 170 170 170 170 170 170 170 170 170 170 170 170 -255 255 255 255 255 255 170 170 170 170 170 170 170 170 170 255 255 255 -255 255 255 170 170 170 170 170 170 255 255 255 0 0 0 0 0 0 -0 0 0 85 85 85 255 255 255 255 255 255 255 255 255 85 85 85 -85 85 85 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -170 170 170 170 170 170 255 255 85 255 255 85 255 255 85 255 255 85 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 0 0 0 255 255 255 85 85 85 0 0 0 0 0 0 -255 255 255 85 85 85 0 0 0 0 0 0 255 255 255 255 255 85 -255 255 85 170 170 170 0 0 0 0 0 0 0 0 0 170 170 170 -255 255 255 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 -170 170 170 255 255 255 85 85 85 0 0 0 85 85 85 255 255 255 -85 85 85 0 0 0 85 85 85 255 255 255 0 0 0 0 0 0 -0 0 0 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 85 85 85 0 0 0 0 0 0 85 85 85 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 255 255 255 255 255 85 255 255 85 255 255 85 255 255 85 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 -0 0 0 85 85 85 255 255 255 0 0 0 0 0 0 85 85 85 -255 255 255 0 0 0 0 0 0 85 85 85 255 255 85 255 255 85 -255 255 85 85 85 85 0 0 0 0 0 0 0 0 0 170 170 170 -255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 255 255 255 0 0 0 0 0 0 170 170 170 170 170 170 -0 0 0 0 0 0 255 255 255 255 255 255 0 0 0 85 85 85 -255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 85 85 85 0 0 0 85 85 85 255 255 255 255 255 255 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 255 255 255 255 255 85 255 255 85 255 255 85 -255 255 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 -0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 170 170 170 -170 170 170 0 0 0 0 0 0 170 170 170 255 255 85 255 255 85 -255 255 255 0 0 0 85 85 85 85 85 85 0 0 0 170 170 170 -255 255 255 0 0 0 0 0 0 170 170 170 85 85 85 0 0 0 -85 85 85 170 170 170 0 0 0 0 0 0 170 170 170 0 0 0 -0 0 0 170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 -255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170 -85 85 85 0 0 0 85 85 85 255 255 255 255 255 255 170 170 170 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 255 255 255 255 255 85 255 255 85 -255 255 85 170 85 0 0 0 0 85 85 85 85 85 85 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 255 255 255 -170 170 170 0 0 0 0 0 0 170 170 170 255 255 85 255 255 85 -170 170 170 0 0 0 170 170 170 85 85 85 0 0 0 255 255 255 -170 170 170 0 0 0 0 0 0 255 255 255 0 0 0 0 0 0 -170 170 170 170 170 170 0 0 0 0 0 0 85 85 85 0 0 0 -85 85 85 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 -255 255 255 255 255 255 255 255 255 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 170 170 170 255 255 255 170 170 170 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 255 255 255 255 255 85 -255 255 85 255 255 85 255 255 255 170 170 170 170 170 170 255 255 255 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 255 255 255 255 255 255 -85 85 85 0 0 0 0 0 0 255 255 255 255 255 85 255 255 85 -85 85 85 0 0 0 255 255 255 85 85 85 0 0 0 255 255 255 -85 85 85 0 0 0 85 85 85 255 255 255 85 85 85 85 85 85 -255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -255 255 255 255 255 255 255 255 255 170 170 170 0 0 0 85 85 85 -255 255 255 255 255 255 255 255 255 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 255 255 255 -170 170 170 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 -255 255 85 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 255 255 255 -0 0 0 0 0 0 85 85 85 255 255 85 255 255 85 255 255 255 -0 0 0 85 85 85 255 255 255 0 0 0 85 85 85 255 255 255 -85 85 85 0 0 0 170 170 170 255 255 255 170 170 170 170 170 170 -255 255 255 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -255 255 255 255 255 255 255 255 255 170 170 170 0 0 0 170 170 170 -255 255 255 255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 255 255 255 -170 170 170 0 0 0 85 85 85 85 85 85 0 0 0 170 170 170 -255 255 85 255 255 85 255 255 255 170 170 170 170 170 170 170 170 170 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 -85 85 85 170 170 170 0 0 0 0 0 0 85 85 85 170 170 170 -0 0 0 0 0 0 170 170 170 255 255 85 255 255 85 170 170 170 -0 0 0 85 85 85 170 170 170 0 0 0 85 85 85 255 255 255 -0 0 0 0 0 0 170 170 170 170 170 170 170 170 170 255 255 255 -170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -255 255 255 255 255 255 255 255 255 85 85 85 0 0 0 255 255 255 -255 255 255 255 255 255 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 255 255 255 255 255 255 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 170 170 170 255 255 255 255 255 85 255 255 255 -85 85 85 170 170 170 255 255 255 255 255 255 170 170 170 0 0 0 -170 170 170 255 255 85 255 255 85 255 255 255 170 170 170 255 255 255 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 -170 170 170 170 170 170 0 0 0 0 0 0 85 85 85 170 170 170 -0 0 0 0 0 0 170 170 170 255 255 85 255 255 255 85 85 85 -0 0 0 85 85 85 85 85 85 0 0 0 85 85 85 170 170 170 -0 0 0 0 0 0 255 255 255 85 85 85 0 0 0 170 170 170 -170 170 170 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 -255 255 255 255 255 255 255 255 255 85 85 85 85 85 85 255 255 255 -255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 170 170 170 -170 170 170 170 170 170 255 255 255 0 0 0 0 0 0 0 0 0 -0 0 0 170 170 170 255 255 255 255 255 255 255 255 85 170 170 170 -255 255 255 255 255 255 255 255 85 255 255 85 170 170 170 0 0 0 -0 0 0 170 170 170 255 255 85 255 255 85 255 255 85 255 255 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 170 170 170 85 85 85 0 0 0 0 0 0 -255 255 255 85 85 85 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 0 0 0 255 255 255 255 255 85 255 255 255 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 85 85 85 255 255 255 0 0 0 0 0 0 255 255 255 -85 85 85 0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 -255 255 255 255 255 255 255 255 255 85 85 85 170 170 170 255 255 255 -255 255 255 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 -170 170 170 85 85 85 170 170 170 0 0 0 0 0 0 85 85 85 -255 255 255 170 170 170 0 0 0 170 170 170 255 255 85 255 255 255 -255 255 255 170 170 170 255 255 255 255 255 255 85 85 85 0 0 0 -85 85 85 255 255 255 255 255 255 255 255 85 255 255 85 255 255 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 -85 85 85 0 0 0 0 0 0 0 0 0 255 255 255 0 0 0 -0 0 0 85 85 85 170 170 170 255 255 255 170 170 170 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 85 85 85 170 170 170 0 0 0 85 85 85 255 255 255 -0 0 0 0 0 0 170 170 170 170 170 170 0 0 0 0 0 0 -255 255 255 255 255 255 255 255 255 0 0 0 255 255 255 255 255 255 -170 170 170 0 0 0 0 0 0 170 170 170 255 255 255 85 85 85 -170 170 170 170 170 170 170 170 170 0 0 0 85 85 85 255 255 255 -170 170 170 0 0 0 85 85 85 255 255 255 255 255 85 170 170 170 -0 0 0 170 170 170 255 255 255 255 255 255 0 0 0 85 85 85 -255 255 255 170 170 170 0 0 0 170 170 170 255 255 85 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 170 170 170 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 0 0 0 -170 170 170 255 255 255 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170 -0 0 0 0 0 0 255 255 255 170 170 170 0 0 0 0 0 0 -255 255 255 255 255 255 170 170 170 85 85 85 255 255 255 255 255 255 -85 85 85 0 0 0 170 170 170 170 170 170 0 0 0 0 0 0 -170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 85 85 85 -0 0 0 0 0 0 255 255 255 255 255 255 170 170 170 0 0 0 -0 0 0 170 170 170 255 255 255 170 170 170 170 170 170 255 255 255 -85 85 85 0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 170 170 170 255 255 255 170 170 170 0 0 0 -0 0 0 0 0 0 0 0 0 255 255 255 0 0 0 0 0 0 -255 255 255 255 255 255 0 0 0 0 0 0 255 255 255 170 170 170 -0 0 0 0 0 0 0 0 0 170 170 170 255 255 255 170 170 170 -0 0 0 0 0 0 255 255 255 170 170 170 0 0 0 0 0 0 -170 170 170 255 255 255 170 170 170 170 170 170 170 170 170 170 170 170 -0 0 0 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 -85 85 85 255 255 255 255 255 255 170 170 170 0 0 0 0 0 0 -0 0 0 170 170 170 255 255 255 170 170 170 0 0 0 0 0 0 -85 85 85 255 255 255 255 255 85 255 255 255 255 255 255 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 -85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 255 255 85 255 255 85 255 255 85 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -255 255 85 170 170 170 170 170 170 170 170 170 255 255 85 255 255 85 -170 170 170 170 170 170 170 170 170 255 255 85 255 255 85 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 85 85 85 170 170 170 170 170 170 170 170 170 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 -0 0 0 255 255 255 255 255 255 255 255 255 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 85 85 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 85 85 85 85 85 0 0 0 0 0 0 0 0 0 -85 85 85 170 170 170 85 85 85 170 170 170 170 170 170 85 85 85 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85 85 85 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 85 85 85 85 85 85 170 85 0 170 85 0 -170 85 0 255 85 85 255 85 85 255 85 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 85 85 170 85 0 85 85 85 0 0 0 0 0 0 85 85 85 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 -85 85 85 85 85 85 170 85 0 170 85 0 170 85 0 170 85 0 -255 85 85 255 85 85 255 255 85 255 255 85 255 255 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 85 85 -170 85 0 170 85 0 0 0 0 85 85 85 85 85 85 170 170 170 -170 170 170 0 0 0 170 170 170 255 255 255 170 170 170 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 170 170 170 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 -170 85 0 170 85 0 170 85 0 255 85 85 255 85 85 255 255 85 -255 255 85 255 255 85 255 255 85 255 255 85 255 85 85 170 85 0 -170 85 0 85 85 85 85 85 85 85 85 85 170 170 170 170 170 170 -0 0 0 0 0 0 255 255 255 255 255 255 85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 0 0 0 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 85 85 85 170 85 0 170 85 0 170 85 0 -170 85 0 255 85 85 255 85 85 255 85 85 170 85 0 170 85 0 -85 85 85 0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 -0 0 0 85 85 85 255 255 255 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 85 85 85 -0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 -170 85 0 170 85 0 170 85 0 170 85 0 170 85 0 85 85 85 -0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 0 0 0 -0 0 0 85 85 85 255 255 255 170 170 170 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 -85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 -170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 85 85 85 -85 85 85 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 diff --git a/drivers/video/logo/logo_m32r_clut224.ppm b/drivers/video/logo/logo_m32r_clut224.ppm deleted file mode 100644 index 8b2983c5a0bd..000000000000 --- a/drivers/video/logo/logo_m32r_clut224.ppm +++ /dev/null @@ -1,1292 +0,0 @@ -P3 -# CREATOR: The GIMP's PNM Filter Version 1.0 -# -# Note: how to convert ppm to pnm(ascii). -# $ convert -posterize 224 m32r.ppm - | pnm2asc -f5 >logo_m32r_clut224.ppm -# -# convert - imagemagick: /usr/bin/convert -# pnm2asc - pnm to ascii-pnm format converter -# http://www.is.aist.go.jp/etlcdb/util/p2a.htm#English - -80 80 -255 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 43 43 43 75 75 75 27 27 27 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 59 59 59 123 123 123 67 67 67 27 27 27 - 2 2 3 2 2 3 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 10 6 3 59 59 59 80 80 80 43 43 43 27 27 27 - 2 2 3 2 2 3 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 19 19 19 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 2 2 3 10 6 3 10 6 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 10 6 3 11 11 11 11 11 11 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 2 2 3 2 2 3 27 27 27 10 6 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 19 19 19 2 2 3 2 2 3 51 51 51 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 123 123 123 196 196 196 115 115 115 2 2 3 - 2 2 3 2 2 3 2 2 3 75 75 75 141 141 140 - 172 172 172 196 196 196 190 189 188 2 2 3 11 11 11 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 27 27 27 164 164 164 228 228 228 221 221 220 10 6 3 - 2 2 3 2 2 3 2 2 3 172 172 172 245 245 245 - 254 254 252 254 254 252 221 221 220 35 35 35 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 164 164 164 228 228 228 35 35 35 236 236 236 236 236 236 - 2 2 3 11 11 11 2 2 3 254 254 252 245 245 245 - 2 2 3 75 75 75 245 245 245 245 245 245 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 212 212 212 2 2 3 51 51 51 11 11 11 245 245 245 - 27 27 27 80 80 80 10 6 3 254 254 252 2 2 3 - 2 2 3 91 91 91 19 19 19 254 254 252 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 196 196 196 10 6 3 2 2 3 11 11 11 107 107 107 - 49 35 5 57 42 11 31 22 3 236 236 236 2 2 3 - 2 2 3 2 2 3 2 2 3 254 254 252 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 107 107 107 221 221 220 2 2 3 64 43 7 194 148 10 - 236 188 10 225 180 10 170 126 10 236 188 10 94 86 67 - 2 2 3 2 2 3 204 204 204 236 236 236 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 228 228 228 182 126 10 218 164 9 236 188 10 - 236 188 10 237 204 14 236 205 40 246 214 48 246 214 48 - 245 189 11 209 156 9 196 196 196 11 11 11 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 165 114 10 207 148 7 229 172 9 236 180 10 - 236 196 11 237 204 14 242 218 43 246 218 75 246 218 19 - 246 213 13 246 218 19 244 205 11 218 164 9 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 164 109 5 192 133 7 224 165 9 236 180 10 236 188 10 - 236 196 11 241 212 42 246 218 75 246 218 19 246 218 19 - 246 218 19 236 196 11 150 114 10 229 172 9 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 165 114 10 201 142 7 229 172 9 242 182 11 236 188 10 - 237 204 14 245 213 67 246 218 19 246 213 13 246 213 13 - 154 119 10 207 148 7 218 164 9 216 156 8 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 120 78 3 225 180 10 245 189 11 236 205 40 - 241 212 42 241 212 17 237 204 14 148 107 9 182 126 10 - 216 156 8 218 164 9 207 148 7 82 70 43 2 2 3 - 2 2 3 123 123 123 35 35 35 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 10 6 3 180 180 180 156 102 5 135 88 5 142 106 7 - 126 98 11 165 114 10 185 132 9 207 148 7 215 150 13 - 199 140 8 188 148 71 196 196 196 190 189 188 2 2 3 - 2 2 3 11 11 11 132 132 132 75 75 75 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 10 6 3 190 189 188 190 189 188 151 97 5 192 133 7 - 207 148 7 206 142 8 199 140 8 180 121 7 180 132 31 - 190 189 188 190 189 188 212 212 212 212 212 212 107 107 107 - 2 2 3 2 2 3 99 99 99 51 51 51 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 190 189 188 190 189 188 190 189 188 136 95 7 - 151 97 5 151 97 5 151 97 5 183 156 91 190 189 188 - 190 189 188 228 228 228 254 254 252 254 254 252 221 221 220 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 10 6 3 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 2 2 3 - 75 75 75 245 245 245 196 196 196 190 189 188 190 189 188 - 190 189 188 196 196 196 190 189 188 190 189 188 204 204 204 - 236 236 236 254 254 252 254 254 252 254 254 252 254 254 252 - 35 35 35 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 2 2 3 27 27 27 2 2 3 - 245 245 245 254 254 252 245 245 245 190 189 188 190 189 188 - 190 189 188 190 189 188 190 189 188 212 212 212 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 10 6 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 2 2 3 2 2 3 132 132 132 - 254 254 252 254 254 252 254 254 252 236 236 236 196 196 196 - 190 189 188 204 204 204 245 245 245 245 245 245 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 80 80 80 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 2 2 3 2 2 3 2 2 3 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 245 245 245 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 2 2 3 2 2 3 2 2 3 212 212 212 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 2 2 3 2 2 3 204 204 204 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 245 245 245 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 245 245 245 236 236 236 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 2 2 3 - 2 2 3 2 2 3 11 11 11 164 164 164 212 212 212 - 236 236 236 245 245 245 254 254 252 236 236 236 221 221 220 - 221 221 220 228 228 228 245 245 245 245 245 245 245 245 245 - 236 236 236 221 221 220 212 212 212 204 204 204 204 204 204 - 196 196 196 204 204 204 59 59 59 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 2 2 3 - 2 2 3 2 2 3 27 27 27 172 172 172 212 212 212 - 236 236 236 254 254 252 254 254 252 254 254 252 228 228 228 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 245 245 245 221 221 220 204 204 204 196 196 196 - 196 196 196 196 196 196 228 228 228 19 19 19 2 2 3 - 80 80 80 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 2 2 3 2 2 3 2 2 3 - 11 11 11 2 2 3 164 164 164 236 236 236 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 236 236 236 212 212 212 196 196 196 245 245 245 2 2 3 - 2 2 3 11 11 11 51 51 51 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 2 2 3 2 2 3 86 86 83 - 2 2 3 27 27 27 236 236 236 254 254 252 254 254 252 - 245 245 245 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 212 212 212 196 196 196 91 91 91 - 2 2 3 2 2 3 2 2 3 11 11 11 2 2 3 - 2 2 3 2 2 3 2 2 3 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 2 2 3 2 2 3 2 2 3 - 2 2 3 245 245 245 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 245 245 245 254 254 252 254 254 252 254 254 252 - 254 254 252 245 245 245 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 221 221 220 245 245 245 - 2 2 3 11 11 11 43 43 43 19 19 19 10 6 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 2 2 3 80 80 80 2 2 3 - 2 2 3 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 245 245 245 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 43 43 43 27 27 27 80 80 80 19 19 19 80 80 80 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 2 2 3 2 2 3 2 2 3 2 2 3 - 245 245 245 254 254 252 254 254 252 17 11 233 254 254 252 - 254 254 252 254 254 252 254 254 252 236 236 236 17 11 233 - 17 11 233 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 11 11 11 11 11 11 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 2 2 3 67 67 67 2 2 3 19 19 19 - 254 254 252 254 254 252 245 245 245 17 11 233 245 245 245 - 254 254 252 254 254 252 17 11 233 228 228 228 17 11 233 - 17 11 233 17 11 233 17 11 233 254 254 252 17 11 233 - 17 11 233 254 254 252 254 254 252 17 11 233 17 11 233 - 17 11 233 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 2 2 3 2 2 3 2 2 3 2 2 3 - 11 11 11 2 2 3 2 2 3 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 2 2 3 10 6 3 11 11 11 2 2 3 228 228 228 - 254 254 252 254 254 252 254 254 252 17 11 233 254 254 252 - 254 254 252 17 11 233 17 11 233 17 11 233 245 245 245 - 254 254 252 254 254 252 17 11 233 17 11 233 17 11 233 - 17 11 233 17 11 233 254 254 252 17 11 233 17 11 233 - 17 11 233 17 11 233 254 254 252 254 254 252 254 254 252 - 254 254 252 2 2 3 2 2 3 2 2 3 2 2 3 - 27 27 27 2 2 3 2 2 3 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 2 2 3 2 2 3 2 2 3 2 2 3 254 254 252 - 254 254 252 254 254 252 254 254 252 17 11 233 17 11 233 - 17 11 233 17 11 233 17 11 233 17 11 233 254 254 252 - 17 11 233 17 11 233 17 11 233 254 254 252 254 254 252 - 17 11 233 17 11 233 254 254 252 17 11 233 17 11 233 - 254 254 252 17 11 233 254 254 252 254 254 252 254 254 252 - 254 254 252 2 2 3 2 2 3 2 2 3 2 2 3 - 11 11 11 2 2 3 2 2 3 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 19 19 19 2 2 3 2 2 3 254 254 252 - 254 254 252 254 254 252 17 11 233 245 245 245 17 11 233 - 17 11 233 245 245 245 254 254 252 17 11 233 254 254 252 - 17 11 233 17 11 233 17 11 233 254 254 252 254 254 252 - 17 11 233 17 11 233 254 254 252 17 11 233 17 11 233 - 17 11 233 17 11 233 254 254 252 254 254 252 254 254 252 - 254 254 252 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 2 2 3 - 2 2 3 19 19 19 2 2 3 19 19 19 254 254 252 - 254 254 252 245 245 245 17 11 233 254 254 252 17 11 233 - 17 11 233 254 254 252 254 254 252 17 11 233 254 254 252 - 254 254 252 254 254 252 17 11 233 17 11 233 254 254 252 - 17 11 233 17 11 233 254 254 252 17 11 233 17 11 233 - 17 11 233 17 11 233 17 11 233 254 254 252 254 254 252 - 254 254 252 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 2 2 3 - 2 2 3 43 43 43 2 2 3 43 43 43 254 254 252 - 245 245 245 254 254 252 17 11 233 254 254 252 17 11 233 - 254 254 252 254 254 252 254 254 252 17 11 233 17 11 233 - 17 11 233 17 11 233 17 11 233 254 254 252 17 11 233 - 17 11 233 17 11 233 17 11 233 17 11 233 17 11 233 - 245 245 245 254 254 252 17 11 233 254 254 252 254 254 252 - 245 245 245 2 2 3 2 2 3 2 2 3 11 11 11 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 2 2 3 - 2 2 3 75 75 75 2 2 3 99 99 99 254 254 252 - 254 254 252 254 254 252 17 11 233 254 254 252 254 254 252 - 254 254 252 254 254 252 245 245 245 228 228 228 254 254 252 - 254 254 252 17 11 233 245 245 245 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 17 11 233 17 11 233 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 2 2 3 2 2 3 2 2 3 75 75 75 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 2 2 3 - 2 2 3 2 2 3 11 11 11 107 107 107 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 245 245 245 254 254 252 245 245 245 236 236 236 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 2 2 3 2 2 3 11 11 11 19 19 19 - 11 11 11 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 2 2 3 11 11 11 - 140 102 3 11 11 11 10 6 3 67 67 67 254 254 252 - 245 245 245 245 245 245 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 245 245 245 228 228 228 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 245 245 245 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 2 2 3 43 43 43 2 2 3 2 2 3 - 2 2 3 11 11 11 67 67 67 11 11 11 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 185 132 9 242 182 11 - 245 189 11 245 189 11 49 35 5 2 2 3 228 228 228 - 254 254 252 254 254 252 254 254 252 245 245 245 254 254 252 - 254 254 252 254 254 252 254 254 252 228 228 228 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 245 238 222 232 189 94 - 226 186 99 43 43 43 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 59 59 59 2 2 3 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 216 156 8 236 180 22 - 245 189 11 245 189 11 245 189 11 49 35 5 11 11 11 - 212 212 212 245 245 245 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 245 245 245 228 228 228 254 254 252 - 245 245 245 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 245 245 245 254 254 252 254 254 252 229 172 9 246 218 19 - 246 218 19 41 27 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 19 19 19 27 27 27 196 154 14 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 199 140 8 229 172 9 242 182 11 - 245 189 11 245 189 11 245 189 11 244 196 10 2 2 3 - 2 2 3 115 115 115 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 245 245 245 228 228 228 254 254 252 - 254 254 252 245 245 245 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 224 165 9 245 189 11 - 236 196 11 19 19 19 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 11 11 11 236 196 11 - 244 205 11 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 182 126 10 209 156 9 215 150 13 - 193 140 10 207 148 24 216 156 8 242 182 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 209 156 9 - 2 2 3 2 2 3 43 43 43 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 236 236 236 216 156 8 245 189 11 - 229 172 9 64 43 7 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 207 148 7 236 188 10 - 245 189 11 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 180 121 7 216 156 8 242 182 11 236 180 10 - 229 172 9 242 182 11 242 182 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 237 204 14 - 170 126 10 2 2 3 2 2 3 11 11 11 236 236 236 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 204 204 204 196 196 196 216 156 8 236 180 10 - 224 165 9 182 126 10 73 48 6 2 2 3 2 2 3 - 2 2 3 41 27 3 199 140 8 229 172 9 236 180 10 - 245 189 11 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 185 132 9 229 172 9 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 226 188 11 2 2 3 2 2 3 2 2 3 11 11 11 - 245 245 245 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 245 245 245 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 196 196 196 196 196 196 215 150 13 236 180 10 - 229 172 9 201 142 7 185 132 9 180 121 7 173 120 10 - 180 121 7 192 133 7 229 172 9 242 182 11 245 189 11 - 245 189 11 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 180 126 47 224 165 9 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 236 188 10 193 140 10 2 2 3 2 2 3 2 2 3 - 2 2 3 212 212 212 254 254 252 245 245 245 245 245 245 - 254 254 252 254 254 252 254 254 252 245 245 245 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 204 204 204 196 196 196 199 140 8 229 172 9 - 236 180 10 218 164 9 215 150 13 207 148 7 207 148 7 - 216 156 8 229 172 9 245 189 11 245 189 11 245 189 11 - 245 189 11 242 182 11 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 185 132 9 216 156 8 242 182 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 236 196 11 19 19 19 2 2 3 2 2 3 - 2 2 3 11 11 11 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 245 245 245 254 254 252 254 254 252 - 245 245 245 221 221 220 196 196 196 185 132 9 229 172 9 - 242 182 11 229 172 9 224 165 9 218 164 9 224 165 9 - 229 172 9 236 180 10 245 189 11 245 189 11 245 189 11 - 245 189 11 236 180 22 242 182 11 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 236 180 22 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 236 188 10 225 180 10 2 2 3 2 2 3 - 2 2 3 11 11 11 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 221 221 220 19 19 19 185 132 9 224 165 9 - 245 189 11 245 189 11 242 182 11 236 180 10 236 180 10 - 242 182 11 242 182 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 196 154 14 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 207 148 7 236 180 22 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 242 182 11 - 245 189 11 245 189 11 237 204 14 135 88 5 2 2 3 - 27 27 27 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 245 245 245 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 67 67 67 19 13 3 185 132 9 229 172 9 - 242 182 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 236 180 22 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 245 189 11 242 182 11 - 242 182 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 236 188 10 226 188 11 104 83 48 - 254 254 252 254 254 252 254 254 252 254 254 252 245 245 245 - 254 254 252 254 254 252 245 245 245 254 254 252 245 245 245 - 254 254 252 245 245 245 254 254 252 254 254 252 254 254 252 - 2 2 3 2 2 3 56 38 5 185 132 9 229 172 9 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 242 182 11 - 229 172 9 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 182 126 10 215 150 13 242 182 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 242 182 11 245 189 11 236 196 11 216 156 8 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 245 245 245 2 2 3 - 2 2 3 2 2 3 75 54 3 182 126 10 229 172 9 - 242 182 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 229 172 9 - 207 148 24 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 192 133 7 229 172 9 242 182 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 242 182 11 225 180 10 224 165 9 - 107 69 5 245 245 245 254 254 252 254 254 252 254 254 252 - 254 254 252 254 254 252 254 254 252 254 254 252 254 254 252 - 254 254 252 236 236 236 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 91 67 9 182 126 10 229 172 9 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 242 182 11 242 182 11 216 156 8 180 126 47 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 206 142 8 224 165 9 245 189 11 242 182 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 242 182 11 - 245 189 11 245 189 11 242 182 11 242 182 11 216 156 8 - 156 102 5 19 13 3 43 43 43 196 196 196 254 254 252 - 245 245 245 254 254 252 254 254 252 204 204 204 51 51 51 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 95 62 5 185 132 9 229 172 9 - 242 182 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 242 182 11 245 189 11 245 189 11 - 236 180 22 216 156 8 206 142 8 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 192 133 7 215 150 13 229 172 9 229 172 9 - 236 180 10 236 180 22 242 182 11 242 182 11 245 189 11 - 245 189 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 245 189 11 245 189 11 229 172 9 216 156 8 - 156 102 5 83 54 6 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 115 73 3 185 132 9 229 172 9 - 242 182 11 245 189 11 245 189 11 245 189 11 245 189 11 - 245 189 11 242 182 11 229 172 9 229 172 9 216 156 8 - 180 121 7 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 180 121 7 182 126 10 192 133 7 199 140 8 - 207 148 7 215 150 13 216 156 8 224 165 9 229 172 9 - 236 180 22 245 189 11 242 182 11 245 189 11 242 182 11 - 245 189 11 245 189 11 242 182 11 229 172 9 199 140 8 - 151 97 5 101 67 7 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 115 73 3 180 121 7 216 156 8 - 236 180 22 242 182 11 245 189 11 245 189 11 242 182 11 - 236 180 10 224 165 9 215 150 13 206 142 8 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 156 102 5 164 109 5 172 114 5 180 121 7 180 121 7 - 192 133 7 201 142 7 216 156 8 224 165 9 236 180 22 - 245 189 11 242 182 11 229 172 9 201 142 7 172 114 5 - 125 83 5 83 54 6 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 2 2 3 2 2 3 2 2 3 - 2 2 3 2 2 3 91 58 5 156 102 5 192 133 7 - 216 156 8 229 172 9 236 180 10 236 180 10 229 172 9 - 215 150 13 199 140 8 164 109 5 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 120 78 3 132 82 3 - 151 97 5 157 106 7 180 121 7 185 132 9 193 140 10 - 207 148 7 207 148 7 192 133 7 172 114 5 132 82 3 - 101 67 7 41 27 3 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 73 48 6 143 90 3 180 121 7 - 192 133 7 207 148 7 207 148 7 201 142 7 185 132 9 - 173 120 10 136 95 7 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 91 58 5 125 83 5 135 88 5 - 144 95 7 151 97 5 132 82 3 115 73 3 95 62 5 - 64 43 7 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 64 43 7 91 58 5 151 97 5 - 157 106 7 172 114 5 172 114 5 164 109 5 151 97 5 - 85 59 6 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 73 48 6 - 91 58 5 95 62 5 95 62 5 91 58 5 56 38 5 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 83 54 6 - 107 69 5 132 82 3 125 83 5 101 67 7 71 47 31 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 - 215 150 13 215 150 13 215 150 13 215 150 13 215 150 13 diff --git a/include/linux/linux_logo.h b/include/linux/linux_logo.h index 5e3581d76c7f..d4d5b93efe84 100644 --- a/include/linux/linux_logo.h +++ b/include/linux/linux_logo.h @@ -36,8 +36,6 @@ struct linux_logo { extern const struct linux_logo logo_linux_mono; extern const struct linux_logo logo_linux_vga16; extern const struct linux_logo logo_linux_clut224; -extern const struct linux_logo logo_blackfin_vga16; -extern const struct linux_logo logo_blackfin_clut224; extern const struct linux_logo logo_dec_clut224; extern const struct linux_logo logo_mac_clut224; extern const struct linux_logo logo_parisc_clut224; @@ -46,7 +44,6 @@ extern const struct linux_logo logo_sun_clut224; extern const struct linux_logo logo_superh_mono; extern const struct linux_logo logo_superh_vga16; extern const struct linux_logo logo_superh_clut224; -extern const struct linux_logo logo_m32r_clut224; extern const struct linux_logo logo_spe_clut224; extern const struct linux_logo *fb_find_logo(int depth); -- cgit v1.2.3 From e3ed8b436bc32102ac2995940bc3a63c09755b63 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 17:02:41 +0100 Subject: fbdev: remove blackfin drivers The blackfin architecture is getting removed, this removes the associated fbdev drivers as well. Acked-by: Bartlomiej Zolnierkiewicz Acked-by: Aaron Wu Signed-off-by: Arnd Bergmann --- drivers/video/fbdev/Kconfig | 103 ---- drivers/video/fbdev/Makefile | 5 - drivers/video/fbdev/bf537-lq035.c | 891 --------------------------------- drivers/video/fbdev/bf54x-lq043fb.c | 764 ---------------------------- drivers/video/fbdev/bfin-lq035q1-fb.c | 864 -------------------------------- drivers/video/fbdev/bfin-t350mcqb-fb.c | 669 ------------------------- drivers/video/fbdev/bfin_adv7393fb.c | 828 ------------------------------ drivers/video/fbdev/bfin_adv7393fb.h | 319 ------------ include/linux/fb.h | 3 +- 9 files changed, 1 insertion(+), 4445 deletions(-) delete mode 100644 drivers/video/fbdev/bf537-lq035.c delete mode 100644 drivers/video/fbdev/bf54x-lq043fb.c delete mode 100644 drivers/video/fbdev/bfin-lq035q1-fb.c delete mode 100644 drivers/video/fbdev/bfin-t350mcqb-fb.c delete mode 100644 drivers/video/fbdev/bfin_adv7393fb.c delete mode 100644 drivers/video/fbdev/bfin_adv7393fb.h (limited to 'include/linux') diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 11e699f1062b..399573742487 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -580,109 +580,6 @@ config FB_VGA16 To compile this driver as a module, choose M here: the module will be called vga16fb. -config FB_BF54X_LQ043 - tristate "SHARP LQ043 TFT LCD (BF548 EZKIT)" - depends on FB && (BF54x) && !BF542 - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the framebuffer device driver for a SHARP LQ043T1DG01 TFT LCD - -config FB_BFIN_T350MCQB - tristate "Varitronix COG-T350MCQB TFT LCD display (BF527 EZKIT)" - depends on FB && BLACKFIN - select BFIN_GPTIMERS - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the framebuffer device driver for a Varitronix VL-PS-COG-T350MCQB-01 display TFT LCD - This display is a QVGA 320x240 24-bit RGB display interfaced by an 8-bit wide PPI - It uses PPI[0..7] PPI_FS1, PPI_FS2 and PPI_CLK. - -config FB_BFIN_LQ035Q1 - tristate "SHARP LQ035Q1DH02 TFT LCD" - depends on FB && BLACKFIN && SPI - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - select BFIN_GPTIMERS - help - This is the framebuffer device driver for a SHARP LQ035Q1DH02 TFT display found on - the Blackfin Landscape LCD EZ-Extender Card. - This display is a QVGA 320x240 18-bit RGB display interfaced by an 16-bit wide PPI - It uses PPI[0..15] PPI_FS1, PPI_FS2 and PPI_CLK. - - To compile this driver as a module, choose M here: the - module will be called bfin-lq035q1-fb. - -config FB_BF537_LQ035 - tristate "SHARP LQ035 TFT LCD (BF537 STAMP)" - depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - select BFIN_GPTIMERS - help - This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD - attached to a BF537. - - To compile this driver as a module, choose M here: the - module will be called bf537-lq035. - -config FB_BFIN_7393 - tristate "Blackfin ADV7393 Video encoder" - depends on FB && BLACKFIN - select I2C - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - This is the framebuffer device for a ADV7393 video encoder - attached to a Blackfin on the PPI port. - If your Blackfin board has a ADV7393 select Y. - - To compile this driver as a module, choose M here: the - module will be called bfin_adv7393fb. - -choice - prompt "Video mode support" - depends on FB_BFIN_7393 - default NTSC - -config NTSC - bool 'NTSC 720x480' - -config PAL - bool 'PAL 720x576' - -config NTSC_640x480 - bool 'NTSC 640x480 (Experimental)' - -config PAL_640x480 - bool 'PAL 640x480 (Experimental)' - -config NTSC_YCBCR - bool 'NTSC 720x480 YCbCR input' - -config PAL_YCBCR - bool 'PAL 720x576 YCbCR input' - -endchoice - -choice - prompt "Size of ADV7393 frame buffer memory Single/Double Size" - depends on (FB_BFIN_7393) - default ADV7393_1XMEM - -config ADV7393_1XMEM - bool 'Single' - -config ADV7393_2XMEM - bool 'Double' -endchoice - config FB_STI tristate "HP STI frame buffer device support" depends on FB && PARISC diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile index 115961e0721b..55282a21b500 100644 --- a/drivers/video/fbdev/Makefile +++ b/drivers/video/fbdev/Makefile @@ -136,11 +136,6 @@ obj-$(CONFIG_FB_VESA) += vesafb.o obj-$(CONFIG_FB_EFI) += efifb.o obj-$(CONFIG_FB_VGA16) += vga16fb.o obj-$(CONFIG_FB_OF) += offb.o -obj-$(CONFIG_FB_BF537_LQ035) += bf537-lq035.o -obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o -obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o -obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o -obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o obj-$(CONFIG_FB_MX3) += mx3fb.o obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o obj-$(CONFIG_FB_MXS) += mxsfb.o diff --git a/drivers/video/fbdev/bf537-lq035.c b/drivers/video/fbdev/bf537-lq035.c deleted file mode 100644 index ef29fb425122..000000000000 --- a/drivers/video/fbdev/bf537-lq035.c +++ /dev/null @@ -1,891 +0,0 @@ -/* - * Analog Devices Blackfin(BF537 STAMP) + SHARP TFT LCD. - * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:tft-lcd - * - * Copyright 2006-2010 Analog Devices Inc. - * Licensed under the GPL-2. - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define NO_BL 1 - -#define MAX_BRIGHENESS 95 -#define MIN_BRIGHENESS 5 -#define NBR_PALETTE 256 - -static const unsigned short ppi_pins[] = { - P_PPI0_CLK, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, 0 -}; - -static unsigned char *fb_buffer; /* RGB Buffer */ -static unsigned long *dma_desc_table; -static int t_conf_done, lq035_open_cnt; -static DEFINE_SPINLOCK(bfin_lq035_lock); - -static int landscape; -module_param(landscape, int, 0); -MODULE_PARM_DESC(landscape, - "LANDSCAPE use 320x240 instead of Native 240x320 Resolution"); - -static int bgr; -module_param(bgr, int, 0); -MODULE_PARM_DESC(bgr, - "BGR use 16-bit BGR-565 instead of RGB-565"); - -static int nocursor = 1; -module_param(nocursor, int, 0644); -MODULE_PARM_DESC(nocursor, "cursor enable/disable"); - -static unsigned long current_brightness; /* backlight */ - -/* AD5280 vcomm */ -static unsigned char vcomm_value = 150; -static struct i2c_client *ad5280_client; - -static void set_vcomm(void) -{ - int nr; - - if (!ad5280_client) - return; - - nr = i2c_smbus_write_byte_data(ad5280_client, 0x00, vcomm_value); - if (nr) - pr_err("i2c_smbus_write_byte_data fail: %d\n", nr); -} - -static int ad5280_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - int ret; - if (!i2c_check_functionality(client->adapter, - I2C_FUNC_SMBUS_BYTE_DATA)) { - dev_err(&client->dev, "SMBUS Byte Data not Supported\n"); - return -EIO; - } - - ret = i2c_smbus_write_byte_data(client, 0x00, vcomm_value); - if (ret) { - dev_err(&client->dev, "write fail: %d\n", ret); - return ret; - } - - ad5280_client = client; - - return 0; -} - -static int ad5280_remove(struct i2c_client *client) -{ - ad5280_client = NULL; - return 0; -} - -static const struct i2c_device_id ad5280_id[] = { - {"bf537-lq035-ad5280", 0}, - {} -}; - -MODULE_DEVICE_TABLE(i2c, ad5280_id); - -static struct i2c_driver ad5280_driver = { - .driver = { - .name = "bf537-lq035-ad5280", - }, - .probe = ad5280_probe, - .remove = ad5280_remove, - .id_table = ad5280_id, -}; - -#ifdef CONFIG_PNAV10 -#define MOD GPIO_PH13 - -#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER0_CONFIG -#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER0_WIDTH -#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER0_PERIOD -#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER0_COUNTER -#define TIMDIS_LP TIMDIS0 -#define TIMEN_LP TIMEN0 - -#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG -#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH -#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD -#define TIMDIS_SPS TIMDIS1 -#define TIMEN_SPS TIMEN1 - -#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER5_CONFIG -#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER5_WIDTH -#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER5_PERIOD -#define TIMDIS_SP TIMDIS5 -#define TIMEN_SP TIMEN5 - -#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER2_CONFIG -#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER2_WIDTH -#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER2_PERIOD -#define TIMDIS_PS_CLS TIMDIS2 -#define TIMEN_PS_CLS TIMEN2 - -#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER3_CONFIG -#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER3_WIDTH -#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER3_PERIOD -#define TIMDIS_REV TIMDIS3 -#define TIMEN_REV TIMEN3 -#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER3_COUNTER - -#define FREQ_PPI_CLK (5*1024*1024) /* PPI_CLK 5MHz */ - -#define TIMERS {P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR5, 0} - -#else - -#define UD GPIO_PF13 /* Up / Down */ -#define MOD GPIO_PF10 -#define LBR GPIO_PF14 /* Left Right */ - -#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER6_CONFIG -#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER6_WIDTH -#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER6_PERIOD -#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER6_COUNTER -#define TIMDIS_LP TIMDIS6 -#define TIMEN_LP TIMEN6 - -#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG -#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH -#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD -#define TIMDIS_SPS TIMDIS1 -#define TIMEN_SPS TIMEN1 - -#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER0_CONFIG -#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER0_WIDTH -#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER0_PERIOD -#define TIMDIS_SP TIMDIS0 -#define TIMEN_SP TIMEN0 - -#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER7_CONFIG -#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER7_WIDTH -#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER7_PERIOD -#define TIMDIS_PS_CLS TIMDIS7 -#define TIMEN_PS_CLS TIMEN7 - -#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER5_CONFIG -#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER5_WIDTH -#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER5_PERIOD -#define TIMDIS_REV TIMDIS5 -#define TIMEN_REV TIMEN5 -#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER5_COUNTER - -#define FREQ_PPI_CLK (6*1000*1000) /* PPI_CLK 6MHz */ -#define TIMERS {P_TMR0, P_TMR1, P_TMR5, P_TMR6, P_TMR7, 0} - -#endif - -#define LCD_X_RES 240 /* Horizontal Resolution */ -#define LCD_Y_RES 320 /* Vertical Resolution */ - -#define LCD_BBP 16 /* Bit Per Pixel */ - -/* the LCD and the DMA start counting differently; - * since one starts at 0 and the other starts at 1, - * we have a difference of 1 between START_LINES - * and U_LINES. - */ -#define START_LINES 8 /* lines for field flyback or field blanking signal */ -#define U_LINES 9 /* number of undisplayed blanking lines */ - -#define FRAMES_PER_SEC (60) - -#define DCLKS_PER_FRAME (FREQ_PPI_CLK/FRAMES_PER_SEC) -#define DCLKS_PER_LINE (DCLKS_PER_FRAME/(LCD_Y_RES+U_LINES)) - -#define PPI_CONFIG_VALUE (PORT_DIR|XFR_TYPE|DLEN_16|POLS) -#define PPI_DELAY_VALUE (0) -#define TIMER_CONFIG (PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL) - -#define ACTIVE_VIDEO_MEM_OFFSET (LCD_X_RES*START_LINES*(LCD_BBP/8)) -#define ACTIVE_VIDEO_MEM_SIZE (LCD_Y_RES*LCD_X_RES*(LCD_BBP/8)) -#define TOTAL_VIDEO_MEM_SIZE ((LCD_Y_RES+U_LINES)*LCD_X_RES*(LCD_BBP/8)) -#define TOTAL_DMA_DESC_SIZE (2 * sizeof(u32) * (LCD_Y_RES + U_LINES)) - -static void start_timers(void) /* CHECK with HW */ -{ - unsigned long flags; - - local_irq_save(flags); - - bfin_write_TIMER_ENABLE(TIMEN_REV); - SSYNC(); - - while (bfin_read_TIMER_REV_COUNTER() <= 11) - continue; - bfin_write_TIMER_ENABLE(TIMEN_LP); - SSYNC(); - - while (bfin_read_TIMER_LP_COUNTER() < 3) - continue; - bfin_write_TIMER_ENABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS); - SSYNC(); - t_conf_done = 1; - local_irq_restore(flags); -} - -static void config_timers(void) -{ - /* Stop timers */ - bfin_write_TIMER_DISABLE(TIMDIS_SP|TIMDIS_SPS|TIMDIS_REV| - TIMDIS_LP|TIMDIS_PS_CLS); - SSYNC(); - - /* LP, timer 6 */ - bfin_write_TIMER_LP_CONFIG(TIMER_CONFIG|PULSE_HI); - bfin_write_TIMER_LP_WIDTH(1); - - bfin_write_TIMER_LP_PERIOD(DCLKS_PER_LINE); - SSYNC(); - - /* SPS, timer 1 */ - bfin_write_TIMER_SPS_CONFIG(TIMER_CONFIG|PULSE_HI); - bfin_write_TIMER_SPS_WIDTH(DCLKS_PER_LINE*2); - bfin_write_TIMER_SPS_PERIOD((DCLKS_PER_LINE * (LCD_Y_RES+U_LINES))); - SSYNC(); - - /* SP, timer 0 */ - bfin_write_TIMER_SP_CONFIG(TIMER_CONFIG|PULSE_HI); - bfin_write_TIMER_SP_WIDTH(1); - bfin_write_TIMER_SP_PERIOD(DCLKS_PER_LINE); - SSYNC(); - - /* PS & CLS, timer 7 */ - bfin_write_TIMER_PS_CLS_CONFIG(TIMER_CONFIG); - bfin_write_TIMER_PS_CLS_WIDTH(LCD_X_RES + START_LINES); - bfin_write_TIMER_PS_CLS_PERIOD(DCLKS_PER_LINE); - - SSYNC(); - -#ifdef NO_BL - /* REV, timer 5 */ - bfin_write_TIMER_REV_CONFIG(TIMER_CONFIG|PULSE_HI); - - bfin_write_TIMER_REV_WIDTH(DCLKS_PER_LINE); - bfin_write_TIMER_REV_PERIOD(DCLKS_PER_LINE*2); - - SSYNC(); -#endif -} - -static void config_ppi(void) -{ - bfin_write_PPI_DELAY(PPI_DELAY_VALUE); - bfin_write_PPI_COUNT(LCD_X_RES-1); - /* 0x10 -> PORT_CFG -> 2 or 3 frame syncs */ - bfin_write_PPI_CONTROL((PPI_CONFIG_VALUE|0x10) & (~POLS)); -} - -static int config_dma(void) -{ - u32 i; - - if (landscape) { - - for (i = 0; i < U_LINES; ++i) { - /* blanking lines point to first line of fb_buffer */ - dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2]; - dma_desc_table[2*i+1] = (unsigned long)fb_buffer; - } - - for (i = U_LINES; i < U_LINES + LCD_Y_RES; ++i) { - /* visible lines */ - dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2]; - dma_desc_table[2*i+1] = (unsigned long)fb_buffer + - (LCD_Y_RES+U_LINES-1-i)*2; - } - - /* last descriptor points to first */ - dma_desc_table[2*(LCD_Y_RES+U_LINES-1)] = (unsigned long)&dma_desc_table[0]; - - set_dma_x_count(CH_PPI, LCD_X_RES); - set_dma_x_modify(CH_PPI, LCD_Y_RES * (LCD_BBP / 8)); - set_dma_y_count(CH_PPI, 0); - set_dma_y_modify(CH_PPI, 0); - set_dma_next_desc_addr(CH_PPI, (void *)dma_desc_table[0]); - set_dma_config(CH_PPI, DMAFLOW_LARGE | NDSIZE_4 | WDSIZE_16); - - } else { - - set_dma_config(CH_PPI, set_bfin_dma_config(DIR_READ, - DMA_FLOW_AUTO, - INTR_DISABLE, - DIMENSION_2D, - DATA_SIZE_16, - DMA_NOSYNC_KEEP_DMA_BUF)); - set_dma_x_count(CH_PPI, LCD_X_RES); - set_dma_x_modify(CH_PPI, LCD_BBP / 8); - set_dma_y_count(CH_PPI, LCD_Y_RES+U_LINES); - set_dma_y_modify(CH_PPI, LCD_BBP / 8); - set_dma_start_addr(CH_PPI, (unsigned long) fb_buffer); - } - - return 0; -} - -static int request_ports(void) -{ - u16 tmr_req[] = TIMERS; - - /* - UD: PF13 - MOD: PF10 - LBR: PF14 - PPI_CLK: PF15 - */ - - if (peripheral_request_list(ppi_pins, KBUILD_MODNAME)) { - pr_err("requesting PPI peripheral failed\n"); - return -EBUSY; - } - - if (peripheral_request_list(tmr_req, KBUILD_MODNAME)) { - peripheral_free_list(ppi_pins); - pr_err("requesting timer peripheral failed\n"); - return -EBUSY; - } - -#if (defined(UD) && defined(LBR)) - if (gpio_request_one(UD, GPIOF_OUT_INIT_LOW, KBUILD_MODNAME)) { - pr_err("requesting GPIO %d failed\n", UD); - return -EBUSY; - } - - if (gpio_request_one(LBR, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) { - pr_err("requesting GPIO %d failed\n", LBR); - gpio_free(UD); - return -EBUSY; - } -#endif - - if (gpio_request_one(MOD, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) { - pr_err("requesting GPIO %d failed\n", MOD); -#if (defined(UD) && defined(LBR)) - gpio_free(LBR); - gpio_free(UD); -#endif - return -EBUSY; - } - - SSYNC(); - return 0; -} - -static void free_ports(void) -{ - u16 tmr_req[] = TIMERS; - - peripheral_free_list(ppi_pins); - peripheral_free_list(tmr_req); - -#if defined(UD) && defined(LBR) - gpio_free(LBR); - gpio_free(UD); -#endif - gpio_free(MOD); -} - -static struct fb_info bfin_lq035_fb; - -static struct fb_var_screeninfo bfin_lq035_fb_defined = { - .bits_per_pixel = LCD_BBP, - .activate = FB_ACTIVATE_TEST, - .xres = LCD_X_RES, /*default portrait mode RGB*/ - .yres = LCD_Y_RES, - .xres_virtual = LCD_X_RES, - .yres_virtual = LCD_Y_RES, - .height = -1, - .width = -1, - .left_margin = 0, - .right_margin = 0, - .upper_margin = 0, - .lower_margin = 0, - .red = {11, 5, 0}, - .green = {5, 6, 0}, - .blue = {0, 5, 0}, - .transp = {0, 0, 0}, -}; - -static struct fb_fix_screeninfo bfin_lq035_fb_fix = { - .id = KBUILD_MODNAME, - .smem_len = ACTIVE_VIDEO_MEM_SIZE, - .type = FB_TYPE_PACKED_PIXELS, - .visual = FB_VISUAL_TRUECOLOR, - .xpanstep = 0, - .ypanstep = 0, - .line_length = LCD_X_RES*(LCD_BBP/8), - .accel = FB_ACCEL_NONE, -}; - - -static int bfin_lq035_fb_open(struct fb_info *info, int user) -{ - unsigned long flags; - - spin_lock_irqsave(&bfin_lq035_lock, flags); - lq035_open_cnt++; - spin_unlock_irqrestore(&bfin_lq035_lock, flags); - - if (lq035_open_cnt <= 1) { - bfin_write_PPI_CONTROL(0); - SSYNC(); - - set_vcomm(); - config_dma(); - config_ppi(); - - /* start dma */ - enable_dma(CH_PPI); - SSYNC(); - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); - SSYNC(); - - if (!t_conf_done) { - config_timers(); - start_timers(); - } - /* gpio_set_value(MOD,1); */ - } - - return 0; -} - -static int bfin_lq035_fb_release(struct fb_info *info, int user) -{ - unsigned long flags; - - spin_lock_irqsave(&bfin_lq035_lock, flags); - lq035_open_cnt--; - spin_unlock_irqrestore(&bfin_lq035_lock, flags); - - - if (lq035_open_cnt <= 0) { - - bfin_write_PPI_CONTROL(0); - SSYNC(); - - disable_dma(CH_PPI); - } - - return 0; -} - - -static int bfin_lq035_fb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - switch (var->bits_per_pixel) { - case 16:/* DIRECTCOLOUR, 64k */ - var->red.offset = info->var.red.offset; - var->green.offset = info->var.green.offset; - var->blue.offset = info->var.blue.offset; - var->red.length = info->var.red.length; - var->green.length = info->var.green.length; - var->blue.length = info->var.blue.length; - var->transp.offset = 0; - var->transp.length = 0; - var->transp.msb_right = 0; - var->red.msb_right = 0; - var->green.msb_right = 0; - var->blue.msb_right = 0; - break; - default: - pr_debug("%s: depth not supported: %u BPP\n", __func__, - var->bits_per_pixel); - return -EINVAL; - } - - if (info->var.xres != var->xres || - info->var.yres != var->yres || - info->var.xres_virtual != var->xres_virtual || - info->var.yres_virtual != var->yres_virtual) { - pr_debug("%s: Resolution not supported: X%u x Y%u\n", - __func__, var->xres, var->yres); - return -EINVAL; - } - - /* - * Memory limit - */ - - if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { - pr_debug("%s: Memory Limit requested yres_virtual = %u\n", - __func__, var->yres_virtual); - return -ENOMEM; - } - - return 0; -} - -static int bfin_lq035_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - if (nocursor) - return 0; - else - return -EINVAL; /* just to force soft_cursor() call */ -} - -static int bfin_lq035_fb_setcolreg(u_int regno, u_int red, u_int green, - u_int blue, u_int transp, - struct fb_info *info) -{ - if (regno >= NBR_PALETTE) - return -EINVAL; - - if (info->var.grayscale) - /* grayscale = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; - - if (info->fix.visual == FB_VISUAL_TRUECOLOR) { - - u32 value; - /* Place color in the pseudopalette */ - if (regno > 16) - return -EINVAL; - - red >>= (16 - info->var.red.length); - green >>= (16 - info->var.green.length); - blue >>= (16 - info->var.blue.length); - - value = (red << info->var.red.offset) | - (green << info->var.green.offset)| - (blue << info->var.blue.offset); - value &= 0xFFFF; - - ((u32 *) (info->pseudo_palette))[regno] = value; - - } - - return 0; -} - -static struct fb_ops bfin_lq035_fb_ops = { - .owner = THIS_MODULE, - .fb_open = bfin_lq035_fb_open, - .fb_release = bfin_lq035_fb_release, - .fb_check_var = bfin_lq035_fb_check_var, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, - .fb_cursor = bfin_lq035_fb_cursor, - .fb_setcolreg = bfin_lq035_fb_setcolreg, -}; - -static int bl_get_brightness(struct backlight_device *bd) -{ - return current_brightness; -} - -static const struct backlight_ops bfin_lq035fb_bl_ops = { - .get_brightness = bl_get_brightness, -}; - -static struct backlight_device *bl_dev; - -static int bfin_lcd_get_power(struct lcd_device *dev) -{ - return 0; -} - -static int bfin_lcd_set_power(struct lcd_device *dev, int power) -{ - return 0; -} - -static int bfin_lcd_get_contrast(struct lcd_device *dev) -{ - return (int)vcomm_value; -} - -static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast) -{ - if (contrast > 255) - contrast = 255; - if (contrast < 0) - contrast = 0; - - vcomm_value = (unsigned char)contrast; - set_vcomm(); - return 0; -} - -static int bfin_lcd_check_fb(struct lcd_device *lcd, struct fb_info *fi) -{ - if (!fi || (fi == &bfin_lq035_fb)) - return 1; - return 0; -} - -static struct lcd_ops bfin_lcd_ops = { - .get_power = bfin_lcd_get_power, - .set_power = bfin_lcd_set_power, - .get_contrast = bfin_lcd_get_contrast, - .set_contrast = bfin_lcd_set_contrast, - .check_fb = bfin_lcd_check_fb, -}; - -static struct lcd_device *lcd_dev; - -static int bfin_lq035_probe(struct platform_device *pdev) -{ - struct backlight_properties props; - dma_addr_t dma_handle; - int ret; - - if (request_dma(CH_PPI, KBUILD_MODNAME)) { - pr_err("couldn't request PPI DMA\n"); - return -EFAULT; - } - - if (request_ports()) { - pr_err("couldn't request gpio port\n"); - ret = -EFAULT; - goto out_ports; - } - - fb_buffer = dma_alloc_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, - &dma_handle, GFP_KERNEL); - if (fb_buffer == NULL) { - pr_err("couldn't allocate dma buffer\n"); - ret = -ENOMEM; - goto out_dma_coherent; - } - - if (L1_DATA_A_LENGTH) - dma_desc_table = l1_data_sram_zalloc(TOTAL_DMA_DESC_SIZE); - else - dma_desc_table = dma_alloc_coherent(NULL, TOTAL_DMA_DESC_SIZE, - &dma_handle, 0); - - if (dma_desc_table == NULL) { - pr_err("couldn't allocate dma descriptor\n"); - ret = -ENOMEM; - goto out_table; - } - - bfin_lq035_fb.screen_base = (void *)fb_buffer; - bfin_lq035_fb_fix.smem_start = (int)fb_buffer; - if (landscape) { - bfin_lq035_fb_defined.xres = LCD_Y_RES; - bfin_lq035_fb_defined.yres = LCD_X_RES; - bfin_lq035_fb_defined.xres_virtual = LCD_Y_RES; - bfin_lq035_fb_defined.yres_virtual = LCD_X_RES; - - bfin_lq035_fb_fix.line_length = LCD_Y_RES*(LCD_BBP/8); - } else { - bfin_lq035_fb.screen_base += ACTIVE_VIDEO_MEM_OFFSET; - bfin_lq035_fb_fix.smem_start += ACTIVE_VIDEO_MEM_OFFSET; - } - - bfin_lq035_fb_defined.green.msb_right = 0; - bfin_lq035_fb_defined.red.msb_right = 0; - bfin_lq035_fb_defined.blue.msb_right = 0; - bfin_lq035_fb_defined.green.offset = 5; - bfin_lq035_fb_defined.green.length = 6; - bfin_lq035_fb_defined.red.length = 5; - bfin_lq035_fb_defined.blue.length = 5; - - if (bgr) { - bfin_lq035_fb_defined.red.offset = 0; - bfin_lq035_fb_defined.blue.offset = 11; - } else { - bfin_lq035_fb_defined.red.offset = 11; - bfin_lq035_fb_defined.blue.offset = 0; - } - - bfin_lq035_fb.fbops = &bfin_lq035_fb_ops; - bfin_lq035_fb.var = bfin_lq035_fb_defined; - - bfin_lq035_fb.fix = bfin_lq035_fb_fix; - bfin_lq035_fb.flags = FBINFO_DEFAULT; - - - bfin_lq035_fb.pseudo_palette = devm_kzalloc(&pdev->dev, - sizeof(u32) * 16, - GFP_KERNEL); - if (bfin_lq035_fb.pseudo_palette == NULL) { - pr_err("failed to allocate pseudo_palette\n"); - ret = -ENOMEM; - goto out_table; - } - - if (fb_alloc_cmap(&bfin_lq035_fb.cmap, NBR_PALETTE, 0) < 0) { - pr_err("failed to allocate colormap (%d entries)\n", - NBR_PALETTE); - ret = -EFAULT; - goto out_table; - } - - if (register_framebuffer(&bfin_lq035_fb) < 0) { - pr_err("unable to register framebuffer\n"); - ret = -EINVAL; - goto out_reg; - } - - i2c_add_driver(&ad5280_driver); - - memset(&props, 0, sizeof(props)); - props.type = BACKLIGHT_RAW; - props.max_brightness = MAX_BRIGHENESS; - bl_dev = backlight_device_register("bf537-bl", NULL, NULL, - &bfin_lq035fb_bl_ops, &props); - - lcd_dev = lcd_device_register(KBUILD_MODNAME, &pdev->dev, NULL, - &bfin_lcd_ops); - if (IS_ERR(lcd_dev)) { - pr_err("unable to register lcd\n"); - ret = PTR_ERR(lcd_dev); - goto out_lcd; - } - lcd_dev->props.max_contrast = 255, - - pr_info("initialized"); - - return 0; -out_lcd: - unregister_framebuffer(&bfin_lq035_fb); -out_reg: - fb_dealloc_cmap(&bfin_lq035_fb.cmap); -out_table: - dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0); - fb_buffer = NULL; -out_dma_coherent: - free_ports(); -out_ports: - free_dma(CH_PPI); - return ret; -} - -static int bfin_lq035_remove(struct platform_device *pdev) -{ - if (fb_buffer != NULL) - dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0); - - if (L1_DATA_A_LENGTH) - l1_data_sram_free(dma_desc_table); - else - dma_free_coherent(NULL, TOTAL_DMA_DESC_SIZE, NULL, 0); - - bfin_write_TIMER_DISABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS| - TIMEN_LP|TIMEN_REV); - t_conf_done = 0; - - free_dma(CH_PPI); - - - fb_dealloc_cmap(&bfin_lq035_fb.cmap); - - - lcd_device_unregister(lcd_dev); - backlight_device_unregister(bl_dev); - - unregister_framebuffer(&bfin_lq035_fb); - i2c_del_driver(&ad5280_driver); - - free_ports(); - - pr_info("unregistered LCD driver\n"); - - return 0; -} - -#ifdef CONFIG_PM -static int bfin_lq035_suspend(struct platform_device *pdev, pm_message_t state) -{ - if (lq035_open_cnt > 0) { - bfin_write_PPI_CONTROL(0); - SSYNC(); - disable_dma(CH_PPI); - } - - return 0; -} - -static int bfin_lq035_resume(struct platform_device *pdev) -{ - if (lq035_open_cnt > 0) { - bfin_write_PPI_CONTROL(0); - SSYNC(); - - config_dma(); - config_ppi(); - - enable_dma(CH_PPI); - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); - SSYNC(); - - config_timers(); - start_timers(); - } else { - t_conf_done = 0; - } - - return 0; -} -#else -# define bfin_lq035_suspend NULL -# define bfin_lq035_resume NULL -#endif - -static struct platform_driver bfin_lq035_driver = { - .probe = bfin_lq035_probe, - .remove = bfin_lq035_remove, - .suspend = bfin_lq035_suspend, - .resume = bfin_lq035_resume, - .driver = { - .name = KBUILD_MODNAME, - }, -}; - -static int __init bfin_lq035_driver_init(void) -{ - request_module("i2c-bfin-twi"); - return platform_driver_register(&bfin_lq035_driver); -} -module_init(bfin_lq035_driver_init); - -static void __exit bfin_lq035_driver_cleanup(void) -{ - platform_driver_unregister(&bfin_lq035_driver); -} -module_exit(bfin_lq035_driver_cleanup); - -MODULE_DESCRIPTION("SHARP LQ035Q7DB03 TFT LCD Driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/bf54x-lq043fb.c b/drivers/video/fbdev/bf54x-lq043fb.c deleted file mode 100644 index 8f1f97c75619..000000000000 --- a/drivers/video/fbdev/bf54x-lq043fb.c +++ /dev/null @@ -1,764 +0,0 @@ -/* - * File: drivers/video/bf54x-lq043.c - * Based on: - * Author: Michael Hennerich - * - * Created: - * Description: ADSP-BF54x Framebuffer driver - * - * - * Modified: - * Copyright 2007-2008 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#define NO_BL_SUPPORT - -#define DRIVER_NAME "bf54x-lq043" -static char driver_name[] = DRIVER_NAME; - -#define BFIN_LCD_NBR_PALETTE_ENTRIES 256 - -#define EPPI0_18 {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, \ - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, \ - P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, 0} - -#define EPPI0_24 {P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, 0} - -struct bfin_bf54xfb_info { - struct fb_info *fb; - struct device *dev; - - struct bfin_bf54xfb_mach_info *mach_info; - - unsigned char *fb_buffer; /* RGB Buffer */ - - dma_addr_t dma_handle; - int lq043_open_cnt; - int irq; - spinlock_t lock; /* lock */ -}; - -static int nocursor; -module_param(nocursor, int, 0644); -MODULE_PARM_DESC(nocursor, "cursor enable/disable"); - -static int outp_rgb666; -module_param(outp_rgb666, int, 0); -MODULE_PARM_DESC(outp_rgb666, "Output 18-bit RGB666"); - -#define LCD_X_RES 480 /*Horizontal Resolution */ -#define LCD_Y_RES 272 /* Vertical Resolution */ - -#define LCD_BPP 24 /* Bit Per Pixel */ -#define DMA_BUS_SIZE 32 - -/* -- Horizontal synchronizing -- - * - * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet - * (LCY-W-06602A Page 9 of 22) - * - * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz - * - * Period TH - 525 - Clock - * Pulse width THp - 41 - Clock - * Horizontal period THd - 480 - Clock - * Back porch THb - 2 - Clock - * Front porch THf - 2 - Clock - * - * -- Vertical synchronizing -- - * Period TV - 286 - Line - * Pulse width TVp - 10 - Line - * Vertical period TVd - 272 - Line - * Back porch TVb - 2 - Line - * Front porch TVf - 2 - Line - */ - -#define LCD_CLK (8*1000*1000) /* 8MHz */ - -/* # active data to transfer after Horizontal Delay clock */ -#define EPPI_HCOUNT LCD_X_RES - -/* # active lines to transfer after Vertical Delay clock */ -#define EPPI_VCOUNT LCD_Y_RES - -/* Samples per Line = 480 (active data) + 45 (padding) */ -#define EPPI_LINE 525 - -/* Lines per Frame = 272 (active data) + 14 (padding) */ -#define EPPI_FRAME 286 - -/* FS1 (Hsync) Width (Typical)*/ -#define EPPI_FS1W_HBL 41 - -/* FS1 (Hsync) Period (Typical) */ -#define EPPI_FS1P_AVPL EPPI_LINE - -/* Horizontal Delay clock after assertion of Hsync (Typical) */ -#define EPPI_HDELAY 43 - -/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */ -#define EPPI_FS2W_LVB (EPPI_LINE * 10) - - /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */ -#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME) - -/* Vertical Delay after assertion of Vsync (2 Lines) */ -#define EPPI_VDELAY 12 - -#define EPPI_CLIP 0xFF00FF00 - -/* EPPI Control register configuration value for RGB out - * - EPPI as Output - * GP 2 frame sync mode, - * Internal Clock generation disabled, Internal FS generation enabled, - * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge, - * FS1 & FS2 are active high, - * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) - * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled - * Swapping Enabled, - * One (DMA) Channel Mode, - * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output - * Regular watermark - when FIFO is 100% full, - * Urgent watermark - when FIFO is 75% full - */ - -#define EPPI_CONTROL (0x20136E2E | SWAPEN) - -static inline u16 get_eppi_clkdiv(u32 target_ppi_clk) -{ - u32 sclk = get_sclk(); - - /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */ - - return (((sclk / target_ppi_clk) / 2) - 1); -} - -static void config_ppi(struct bfin_bf54xfb_info *fbi) -{ - - u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK); - - bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL); - bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL); - bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB); - bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF); - bfin_write_EPPI0_CLIP(EPPI_CLIP); - - bfin_write_EPPI0_FRAME(EPPI_FRAME); - bfin_write_EPPI0_LINE(EPPI_LINE); - - bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT); - bfin_write_EPPI0_HDELAY(EPPI_HDELAY); - bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT); - bfin_write_EPPI0_VDELAY(EPPI_VDELAY); - - bfin_write_EPPI0_CLKDIV(eppi_clkdiv); - -/* - * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) - * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output - */ - if (outp_rgb666) - bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 | - RGB_FMT_EN); - else - bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) & - ~RGB_FMT_EN); - - -} - -static int config_dma(struct bfin_bf54xfb_info *fbi) -{ - - set_dma_config(CH_EPPI0, - set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, - INTR_DISABLE, DIMENSION_2D, - DATA_SIZE_32, - DMA_NOSYNC_KEEP_DMA_BUF)); - set_dma_x_count(CH_EPPI0, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); - set_dma_x_modify(CH_EPPI0, DMA_BUS_SIZE / 8); - set_dma_y_count(CH_EPPI0, LCD_Y_RES); - set_dma_y_modify(CH_EPPI0, DMA_BUS_SIZE / 8); - set_dma_start_addr(CH_EPPI0, (unsigned long)fbi->fb_buffer); - - return 0; -} - -static int request_ports(struct bfin_bf54xfb_info *fbi) -{ - - u16 eppi_req_18[] = EPPI0_18; - u16 disp = fbi->mach_info->disp; - - if (gpio_request_one(disp, GPIOF_OUT_INIT_HIGH, DRIVER_NAME)) { - printk(KERN_ERR "Requesting GPIO %d failed\n", disp); - return -EFAULT; - } - - if (peripheral_request_list(eppi_req_18, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals failed\n"); - gpio_free(disp); - return -EFAULT; - } - - if (!outp_rgb666) { - - u16 eppi_req_24[] = EPPI0_24; - - if (peripheral_request_list(eppi_req_24, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals failed\n"); - peripheral_free_list(eppi_req_18); - gpio_free(disp); - return -EFAULT; - } - } - - return 0; -} - -static void free_ports(struct bfin_bf54xfb_info *fbi) -{ - - u16 eppi_req_18[] = EPPI0_18; - - gpio_free(fbi->mach_info->disp); - - peripheral_free_list(eppi_req_18); - - if (!outp_rgb666) { - u16 eppi_req_24[] = EPPI0_24; - peripheral_free_list(eppi_req_24); - } -} - -static int bfin_bf54x_fb_open(struct fb_info *info, int user) -{ - struct bfin_bf54xfb_info *fbi = info->par; - - spin_lock(&fbi->lock); - fbi->lq043_open_cnt++; - - if (fbi->lq043_open_cnt <= 1) { - - bfin_write_EPPI0_CONTROL(0); - SSYNC(); - - config_dma(fbi); - config_ppi(fbi); - - /* start dma */ - enable_dma(CH_EPPI0); - bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN); - } - - spin_unlock(&fbi->lock); - - return 0; -} - -static int bfin_bf54x_fb_release(struct fb_info *info, int user) -{ - struct bfin_bf54xfb_info *fbi = info->par; - - spin_lock(&fbi->lock); - - fbi->lq043_open_cnt--; - - if (fbi->lq043_open_cnt <= 0) { - - bfin_write_EPPI0_CONTROL(0); - SSYNC(); - disable_dma(CH_EPPI0); - } - - spin_unlock(&fbi->lock); - - return 0; -} - -static int bfin_bf54x_fb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - - switch (var->bits_per_pixel) { - case 24:/* TRUECOLOUR, 16m */ - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = var->green.length = var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - var->transp.msb_right = 0; - var->red.msb_right = 0; - var->green.msb_right = 0; - var->blue.msb_right = 0; - break; - default: - pr_debug("%s: depth not supported: %u BPP\n", __func__, - var->bits_per_pixel); - return -EINVAL; - } - - if (info->var.xres != var->xres || info->var.yres != var->yres || - info->var.xres_virtual != var->xres_virtual || - info->var.yres_virtual != var->yres_virtual) { - pr_debug("%s: Resolution not supported: X%u x Y%u \n", - __func__, var->xres, var->yres); - return -EINVAL; - } - - /* - * Memory limit - */ - - if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { - pr_debug("%s: Memory Limit requested yres_virtual = %u\n", - __func__, var->yres_virtual); - return -ENOMEM; - } - - return 0; -} - -int bfin_bf54x_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - if (nocursor) - return 0; - else - return -EINVAL; /* just to force soft_cursor() call */ -} - -static int bfin_bf54x_fb_setcolreg(u_int regno, u_int red, u_int green, - u_int blue, u_int transp, - struct fb_info *info) -{ - if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES) - return -EINVAL; - - if (info->var.grayscale) { - /* grayscale = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; - } - - if (info->fix.visual == FB_VISUAL_TRUECOLOR) { - - u32 value; - /* Place color in the pseudopalette */ - if (regno > 16) - return -EINVAL; - - red >>= (16 - info->var.red.length); - green >>= (16 - info->var.green.length); - blue >>= (16 - info->var.blue.length); - - value = (red << info->var.red.offset) | - (green << info->var.green.offset) | - (blue << info->var.blue.offset); - value &= 0xFFFFFF; - - ((u32 *) (info->pseudo_palette))[regno] = value; - - } - - return 0; -} - -static struct fb_ops bfin_bf54x_fb_ops = { - .owner = THIS_MODULE, - .fb_open = bfin_bf54x_fb_open, - .fb_release = bfin_bf54x_fb_release, - .fb_check_var = bfin_bf54x_fb_check_var, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, - .fb_cursor = bfin_bf54x_fb_cursor, - .fb_setcolreg = bfin_bf54x_fb_setcolreg, -}; - -#ifndef NO_BL_SUPPORT -static int bl_get_brightness(struct backlight_device *bd) -{ - return 0; -} - -static const struct backlight_ops bfin_lq043fb_bl_ops = { - .get_brightness = bl_get_brightness, -}; - -static struct backlight_device *bl_dev; - -static int bfin_lcd_get_power(struct lcd_device *dev) -{ - return 0; -} - -static int bfin_lcd_set_power(struct lcd_device *dev, int power) -{ - return 0; -} - -static int bfin_lcd_get_contrast(struct lcd_device *dev) -{ - return 0; -} - -static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast) -{ - - return 0; -} - -static int bfin_lcd_check_fb(struct lcd_device *dev, struct fb_info *fi) -{ - if (!fi || (fi == &bfin_bf54x_fb)) - return 1; - return 0; -} - -static struct lcd_ops bfin_lcd_ops = { - .get_power = bfin_lcd_get_power, - .set_power = bfin_lcd_set_power, - .get_contrast = bfin_lcd_get_contrast, - .set_contrast = bfin_lcd_set_contrast, - .check_fb = bfin_lcd_check_fb, -}; - -static struct lcd_device *lcd_dev; -#endif - -static irqreturn_t bfin_bf54x_irq_error(int irq, void *dev_id) -{ - /*struct bfin_bf54xfb_info *info = dev_id;*/ - - u16 status = bfin_read_EPPI0_STATUS(); - - bfin_write_EPPI0_STATUS(0xFFFF); - - if (status) { - bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN); - disable_dma(CH_EPPI0); - - /* start dma */ - enable_dma(CH_EPPI0); - bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN); - bfin_write_EPPI0_STATUS(0xFFFF); - } - - return IRQ_HANDLED; -} - -static int bfin_bf54x_probe(struct platform_device *pdev) -{ -#ifndef NO_BL_SUPPORT - struct backlight_properties props; -#endif - struct bfin_bf54xfb_info *info; - struct fb_info *fbinfo; - int ret; - - printk(KERN_INFO DRIVER_NAME ": FrameBuffer initializing...\n"); - - if (request_dma(CH_EPPI0, "CH_EPPI0") < 0) { - printk(KERN_ERR DRIVER_NAME - ": couldn't request CH_EPPI0 DMA\n"); - ret = -EFAULT; - goto out1; - } - - fbinfo = - framebuffer_alloc(sizeof(struct bfin_bf54xfb_info), &pdev->dev); - if (!fbinfo) { - ret = -ENOMEM; - goto out2; - } - - info = fbinfo->par; - info->fb = fbinfo; - info->dev = &pdev->dev; - spin_lock_init(&info->lock); - - platform_set_drvdata(pdev, fbinfo); - - strcpy(fbinfo->fix.id, driver_name); - - info->mach_info = pdev->dev.platform_data; - - if (info->mach_info == NULL) { - dev_err(&pdev->dev, - "no platform data for lcd, cannot attach\n"); - ret = -EINVAL; - goto out3; - } - - fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; - fbinfo->fix.type_aux = 0; - fbinfo->fix.xpanstep = 0; - fbinfo->fix.ypanstep = 0; - fbinfo->fix.ywrapstep = 0; - fbinfo->fix.accel = FB_ACCEL_NONE; - fbinfo->fix.visual = FB_VISUAL_TRUECOLOR; - - fbinfo->var.nonstd = 0; - fbinfo->var.activate = FB_ACTIVATE_NOW; - fbinfo->var.height = info->mach_info->height; - fbinfo->var.width = info->mach_info->width; - fbinfo->var.accel_flags = 0; - fbinfo->var.vmode = FB_VMODE_NONINTERLACED; - - fbinfo->fbops = &bfin_bf54x_fb_ops; - fbinfo->flags = FBINFO_FLAG_DEFAULT; - - fbinfo->var.xres = info->mach_info->xres.defval; - fbinfo->var.xres_virtual = info->mach_info->xres.defval; - fbinfo->var.yres = info->mach_info->yres.defval; - fbinfo->var.yres_virtual = info->mach_info->yres.defval; - fbinfo->var.bits_per_pixel = info->mach_info->bpp.defval; - - fbinfo->var.upper_margin = 0; - fbinfo->var.lower_margin = 0; - fbinfo->var.vsync_len = 0; - - fbinfo->var.left_margin = 0; - fbinfo->var.right_margin = 0; - fbinfo->var.hsync_len = 0; - - fbinfo->var.red.offset = 16; - fbinfo->var.green.offset = 8; - fbinfo->var.blue.offset = 0; - fbinfo->var.transp.offset = 0; - fbinfo->var.red.length = 8; - fbinfo->var.green.length = 8; - fbinfo->var.blue.length = 8; - fbinfo->var.transp.length = 0; - fbinfo->fix.smem_len = info->mach_info->xres.max * - info->mach_info->yres.max * info->mach_info->bpp.max / 8; - - fbinfo->fix.line_length = fbinfo->var.xres_virtual * - fbinfo->var.bits_per_pixel / 8; - - info->fb_buffer = - dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle, - GFP_KERNEL); - - if (NULL == info->fb_buffer) { - printk(KERN_ERR DRIVER_NAME - ": couldn't allocate dma buffer.\n"); - ret = -ENOMEM; - goto out3; - } - - fbinfo->screen_base = (void *)info->fb_buffer; - fbinfo->fix.smem_start = (int)info->fb_buffer; - - fbinfo->fbops = &bfin_bf54x_fb_ops; - - fbinfo->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16, - GFP_KERNEL); - if (!fbinfo->pseudo_palette) { - printk(KERN_ERR DRIVER_NAME - "Fail to allocate pseudo_palette\n"); - - ret = -ENOMEM; - goto out4; - } - - if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) - < 0) { - printk(KERN_ERR DRIVER_NAME - "Fail to allocate colormap (%d entries)\n", - BFIN_LCD_NBR_PALETTE_ENTRIES); - ret = -EFAULT; - goto out4; - } - - if (request_ports(info)) { - printk(KERN_ERR DRIVER_NAME ": couldn't request gpio port.\n"); - ret = -EFAULT; - goto out6; - } - - info->irq = platform_get_irq(pdev, 0); - if (info->irq < 0) { - ret = -EINVAL; - goto out7; - } - - if (request_irq(info->irq, bfin_bf54x_irq_error, 0, - "PPI ERROR", info) < 0) { - printk(KERN_ERR DRIVER_NAME - ": unable to request PPI ERROR IRQ\n"); - ret = -EFAULT; - goto out7; - } - - if (register_framebuffer(fbinfo) < 0) { - printk(KERN_ERR DRIVER_NAME - ": unable to register framebuffer.\n"); - ret = -EINVAL; - goto out8; - } -#ifndef NO_BL_SUPPORT - memset(&props, 0, sizeof(struct backlight_properties)); - props.type = BACKLIGHT_RAW; - props.max_brightness = 255; - bl_dev = backlight_device_register("bf54x-bl", NULL, NULL, - &bfin_lq043fb_bl_ops, &props); - if (IS_ERR(bl_dev)) { - printk(KERN_ERR DRIVER_NAME - ": unable to register backlight.\n"); - ret = -EINVAL; - unregister_framebuffer(fbinfo); - goto out8; - } - - lcd_dev = lcd_device_register(DRIVER_NAME, &pdev->dev, NULL, &bfin_lcd_ops); - lcd_dev->props.max_contrast = 255, printk(KERN_INFO "Done.\n"); -#endif - - return 0; - -out8: - free_irq(info->irq, info); -out7: - free_ports(info); -out6: - fb_dealloc_cmap(&fbinfo->cmap); -out4: - dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, - info->dma_handle); -out3: - framebuffer_release(fbinfo); -out2: - free_dma(CH_EPPI0); -out1: - - return ret; -} - -static int bfin_bf54x_remove(struct platform_device *pdev) -{ - - struct fb_info *fbinfo = platform_get_drvdata(pdev); - struct bfin_bf54xfb_info *info = fbinfo->par; - - free_dma(CH_EPPI0); - free_irq(info->irq, info); - - if (info->fb_buffer != NULL) - dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, - info->dma_handle); - - fb_dealloc_cmap(&fbinfo->cmap); - -#ifndef NO_BL_SUPPORT - lcd_device_unregister(lcd_dev); - backlight_device_unregister(bl_dev); -#endif - - unregister_framebuffer(fbinfo); - - free_ports(info); - - printk(KERN_INFO DRIVER_NAME ": Unregister LCD driver.\n"); - - return 0; -} - -#ifdef CONFIG_PM -static int bfin_bf54x_suspend(struct platform_device *pdev, pm_message_t state) -{ - bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN); - disable_dma(CH_EPPI0); - bfin_write_EPPI0_STATUS(0xFFFF); - - return 0; -} - -static int bfin_bf54x_resume(struct platform_device *pdev) -{ - struct fb_info *fbinfo = platform_get_drvdata(pdev); - struct bfin_bf54xfb_info *info = fbinfo->par; - - if (info->lq043_open_cnt) { - - bfin_write_EPPI0_CONTROL(0); - SSYNC(); - - config_dma(info); - config_ppi(info); - - /* start dma */ - enable_dma(CH_EPPI0); - bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN); - } - - return 0; -} -#else -#define bfin_bf54x_suspend NULL -#define bfin_bf54x_resume NULL -#endif - -static struct platform_driver bfin_bf54x_driver = { - .probe = bfin_bf54x_probe, - .remove = bfin_bf54x_remove, - .suspend = bfin_bf54x_suspend, - .resume = bfin_bf54x_resume, - .driver = { - .name = DRIVER_NAME, - }, -}; -module_platform_driver(bfin_bf54x_driver); - -MODULE_DESCRIPTION("Blackfin BF54x TFT LCD Driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/bfin-lq035q1-fb.c b/drivers/video/fbdev/bfin-lq035q1-fb.c deleted file mode 100644 index b459354ad940..000000000000 --- a/drivers/video/fbdev/bfin-lq035q1-fb.c +++ /dev/null @@ -1,864 +0,0 @@ -/* - * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02 - * - * Copyright 2008-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#define DRIVER_NAME "bfin-lq035q1" -#define pr_fmt(fmt) DRIVER_NAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#if defined(BF533_FAMILY) || defined(BF538_FAMILY) -#define TIMER_HSYNC_id TIMER1_id -#define TIMER_HSYNCbit TIMER1bit -#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN1 -#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1 -#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF1 - -#define TIMER_VSYNC_id TIMER2_id -#define TIMER_VSYNCbit TIMER2bit -#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN2 -#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL2 -#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF2 -#else -#define TIMER_HSYNC_id TIMER0_id -#define TIMER_HSYNCbit TIMER0bit -#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN0 -#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL0 -#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF0 - -#define TIMER_VSYNC_id TIMER1_id -#define TIMER_VSYNCbit TIMER1bit -#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN1 -#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1 -#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF1 -#endif - -#define LCD_X_RES 320 /* Horizontal Resolution */ -#define LCD_Y_RES 240 /* Vertical Resolution */ -#define DMA_BUS_SIZE 16 -#define U_LINE 4 /* Blanking Lines */ - - -/* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD) - * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165 - */ - - -#define BFIN_LCD_NBR_PALETTE_ENTRIES 256 - -#define PPI_TX_MODE 0x2 -#define PPI_XFER_TYPE_11 0xC -#define PPI_PORT_CFG_01 0x10 -#define PPI_POLS_1 0x8000 - -#define LQ035_INDEX 0x74 -#define LQ035_DATA 0x76 - -#define LQ035_DRIVER_OUTPUT_CTL 0x1 -#define LQ035_SHUT_CTL 0x11 - -#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV) -#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK) - -#define LQ035_SHUT (1 << 0) /* Shutdown */ -#define LQ035_ON (0 << 0) /* Shutdown */ - -struct bfin_lq035q1fb_info { - struct fb_info *fb; - struct device *dev; - struct spi_driver spidrv; - struct bfin_lq035q1fb_disp_info *disp_info; - unsigned char *fb_buffer; /* RGB Buffer */ - dma_addr_t dma_handle; - int lq035_open_cnt; - int irq; - spinlock_t lock; /* lock */ - u32 pseudo_pal[16]; - - u32 lcd_bpp; - u32 h_actpix; - u32 h_period; - u32 h_pulse; - u32 h_start; - u32 v_lines; - u32 v_pulse; - u32 v_period; -}; - -static int nocursor; -module_param(nocursor, int, 0644); -MODULE_PARM_DESC(nocursor, "cursor enable/disable"); - -struct spi_control { - unsigned short mode; -}; - -static int lq035q1_control(struct spi_device *spi, unsigned char reg, unsigned short value) -{ - int ret; - u8 regs[3] = { LQ035_INDEX, 0, 0 }; - u8 dat[3] = { LQ035_DATA, 0, 0 }; - - if (!spi) - return -ENODEV; - - regs[2] = reg; - dat[1] = value >> 8; - dat[2] = value & 0xFF; - - ret = spi_write(spi, regs, ARRAY_SIZE(regs)); - ret |= spi_write(spi, dat, ARRAY_SIZE(dat)); - return ret; -} - -static int lq035q1_spidev_probe(struct spi_device *spi) -{ - int ret; - struct spi_control *ctl; - struct bfin_lq035q1fb_info *info = container_of(spi->dev.driver, - struct bfin_lq035q1fb_info, - spidrv.driver); - - ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); - - if (!ctl) - return -ENOMEM; - - ctl->mode = (info->disp_info->mode & - LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT; - - ret = lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON); - ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode); - if (ret) { - kfree(ctl); - return ret; - } - - spi_set_drvdata(spi, ctl); - - return 0; -} - -static int lq035q1_spidev_remove(struct spi_device *spi) -{ - return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); -} - -#ifdef CONFIG_PM_SLEEP -static int lq035q1_spidev_suspend(struct device *dev) -{ - struct spi_device *spi = to_spi_device(dev); - - return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); -} - -static int lq035q1_spidev_resume(struct device *dev) -{ - struct spi_device *spi = to_spi_device(dev); - struct spi_control *ctl = spi_get_drvdata(spi); - int ret; - - ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode); - if (ret) - return ret; - - return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON); -} - -static SIMPLE_DEV_PM_OPS(lq035q1_spidev_pm_ops, lq035q1_spidev_suspend, - lq035q1_spidev_resume); -#define LQ035Q1_SPIDEV_PM_OPS (&lq035q1_spidev_pm_ops) - -#else -#define LQ035Q1_SPIDEV_PM_OPS NULL -#endif - -/* Power down all displays on reboot, poweroff or halt */ -static void lq035q1_spidev_shutdown(struct spi_device *spi) -{ - lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); -} - -static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg) -{ - if (info->disp_info->use_bl) - gpio_set_value(info->disp_info->gpio_bl, arg); - - return 0; -} - -static int bfin_lq035q1_calc_timing(struct bfin_lq035q1fb_info *fbi) -{ - unsigned long clocks_per_pix, cpld_pipeline_delay_cor; - - /* - * Interface 16/18-bit TFT over an 8-bit wide PPI using a small - * Programmable Logic Device (CPLD) - * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165 - */ - - switch (fbi->disp_info->ppi_mode) { - case USE_RGB565_16_BIT_PPI: - fbi->lcd_bpp = 16; - clocks_per_pix = 1; - cpld_pipeline_delay_cor = 0; - break; - case USE_RGB565_8_BIT_PPI: - fbi->lcd_bpp = 16; - clocks_per_pix = 2; - cpld_pipeline_delay_cor = 3; - break; - case USE_RGB888_8_BIT_PPI: - fbi->lcd_bpp = 24; - clocks_per_pix = 3; - cpld_pipeline_delay_cor = 5; - break; - default: - return -EINVAL; - } - - /* - * HS and VS timing parameters (all in number of PPI clk ticks) - */ - - fbi->h_actpix = (LCD_X_RES * clocks_per_pix); /* active horizontal pixel */ - fbi->h_period = (336 * clocks_per_pix); /* HS period */ - fbi->h_pulse = (2 * clocks_per_pix); /* HS pulse width */ - fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */ - - fbi->v_lines = (LCD_Y_RES + U_LINE); /* total vertical lines */ - fbi->v_pulse = (2 * clocks_per_pix); /* VS pulse width (1-5 H_PERIODs) */ - fbi->v_period = (fbi->h_period * fbi->v_lines); /* VS period */ - - return 0; -} - -static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi) -{ - unsigned ppi_pmode; - - if (fbi->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI) - ppi_pmode = DLEN_16; - else - ppi_pmode = (DLEN_8 | PACK_EN); - - bfin_write_PPI_DELAY(fbi->h_start); - bfin_write_PPI_COUNT(fbi->h_actpix - 1); - bfin_write_PPI_FRAME(fbi->v_lines); - - bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */ - PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ - PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ - ppi_pmode | /* 8/16 bit data length / PACK_EN? */ - PPI_POLS_1); /* faling edge syncs POLS */ -} - -static inline void bfin_lq035q1_disable_ppi(void) -{ - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); -} - -static inline void bfin_lq035q1_enable_ppi(void) -{ - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); -} - -static void bfin_lq035q1_start_timers(void) -{ - enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit); -} - -static void bfin_lq035q1_stop_timers(void) -{ - disable_gptimers(TIMER_HSYNCbit | TIMER_VSYNCbit); - - set_gptimer_status(0, TIMER_HSYNC_STATUS_TRUN | TIMER_VSYNC_STATUS_TRUN | - TIMER_HSYNC_STATUS_TIMIL | TIMER_VSYNC_STATUS_TIMIL | - TIMER_HSYNC_STATUS_TOVF | TIMER_VSYNC_STATUS_TOVF); - -} - -static void bfin_lq035q1_init_timers(struct bfin_lq035q1fb_info *fbi) -{ - - bfin_lq035q1_stop_timers(); - - set_gptimer_period(TIMER_HSYNC_id, fbi->h_period); - set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse); - set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | - TIMER_TIN_SEL | TIMER_CLK_SEL| - TIMER_EMU_RUN); - - set_gptimer_period(TIMER_VSYNC_id, fbi->v_period); - set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse); - set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | - TIMER_TIN_SEL | TIMER_CLK_SEL | - TIMER_EMU_RUN); - -} - -static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi) -{ - - - set_dma_config(CH_PPI, - set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, - INTR_DISABLE, DIMENSION_2D, - DATA_SIZE_16, - DMA_NOSYNC_KEEP_DMA_BUF)); - set_dma_x_count(CH_PPI, (LCD_X_RES * fbi->lcd_bpp) / DMA_BUS_SIZE); - set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8); - set_dma_y_count(CH_PPI, fbi->v_lines); - - set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8); - set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer); - -} - -static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, - P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, - P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, - P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, - P_PPI0_D15, 0}; - -static const u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, - P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, - P_PPI0_D6, P_PPI0_D7, 0}; - -static inline void bfin_lq035q1_free_ports(unsigned ppi16) -{ - if (ppi16) - peripheral_free_list(ppi0_req_16); - else - peripheral_free_list(ppi0_req_8); - - if (ANOMALY_05000400) - gpio_free(P_IDENT(P_PPI0_FS3)); -} - -static int bfin_lq035q1_request_ports(struct platform_device *pdev, - unsigned ppi16) -{ - int ret; - /* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode: - * Drive PPI_FS3 Low - */ - if (ANOMALY_05000400) { - int ret = gpio_request_one(P_IDENT(P_PPI0_FS3), - GPIOF_OUT_INIT_LOW, "PPI_FS3"); - if (ret) - return ret; - } - - if (ppi16) - ret = peripheral_request_list(ppi0_req_16, DRIVER_NAME); - else - ret = peripheral_request_list(ppi0_req_8, DRIVER_NAME); - - if (ret) { - dev_err(&pdev->dev, "requesting peripherals failed\n"); - return -EFAULT; - } - - return 0; -} - -static int bfin_lq035q1_fb_open(struct fb_info *info, int user) -{ - struct bfin_lq035q1fb_info *fbi = info->par; - - spin_lock(&fbi->lock); - fbi->lq035_open_cnt++; - - if (fbi->lq035_open_cnt <= 1) { - - bfin_lq035q1_disable_ppi(); - SSYNC(); - - bfin_lq035q1_config_dma(fbi); - bfin_lq035q1_config_ppi(fbi); - bfin_lq035q1_init_timers(fbi); - - /* start dma */ - enable_dma(CH_PPI); - bfin_lq035q1_enable_ppi(); - bfin_lq035q1_start_timers(); - lq035q1_backlight(fbi, 1); - } - - spin_unlock(&fbi->lock); - - return 0; -} - -static int bfin_lq035q1_fb_release(struct fb_info *info, int user) -{ - struct bfin_lq035q1fb_info *fbi = info->par; - - spin_lock(&fbi->lock); - - fbi->lq035_open_cnt--; - - if (fbi->lq035_open_cnt <= 0) { - lq035q1_backlight(fbi, 0); - bfin_lq035q1_disable_ppi(); - SSYNC(); - disable_dma(CH_PPI); - bfin_lq035q1_stop_timers(); - } - - spin_unlock(&fbi->lock); - - return 0; -} - -static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct bfin_lq035q1fb_info *fbi = info->par; - - if (var->bits_per_pixel == fbi->lcd_bpp) { - var->red.offset = info->var.red.offset; - var->green.offset = info->var.green.offset; - var->blue.offset = info->var.blue.offset; - var->red.length = info->var.red.length; - var->green.length = info->var.green.length; - var->blue.length = info->var.blue.length; - var->transp.offset = 0; - var->transp.length = 0; - var->transp.msb_right = 0; - var->red.msb_right = 0; - var->green.msb_right = 0; - var->blue.msb_right = 0; - } else { - pr_debug("%s: depth not supported: %u BPP\n", __func__, - var->bits_per_pixel); - return -EINVAL; - } - - if (info->var.xres != var->xres || info->var.yres != var->yres || - info->var.xres_virtual != var->xres_virtual || - info->var.yres_virtual != var->yres_virtual) { - pr_debug("%s: Resolution not supported: X%u x Y%u \n", - __func__, var->xres, var->yres); - return -EINVAL; - } - - /* - * Memory limit - */ - - if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { - pr_debug("%s: Memory Limit requested yres_virtual = %u\n", - __func__, var->yres_virtual); - return -ENOMEM; - } - - - return 0; -} - -int bfin_lq035q1_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - if (nocursor) - return 0; - else - return -EINVAL; /* just to force soft_cursor() call */ -} - -static int bfin_lq035q1_fb_setcolreg(u_int regno, u_int red, u_int green, - u_int blue, u_int transp, - struct fb_info *info) -{ - if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES) - return -EINVAL; - - if (info->var.grayscale) { - /* grayscale = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; - } - - if (info->fix.visual == FB_VISUAL_TRUECOLOR) { - - u32 value; - /* Place color in the pseudopalette */ - if (regno > 16) - return -EINVAL; - - red >>= (16 - info->var.red.length); - green >>= (16 - info->var.green.length); - blue >>= (16 - info->var.blue.length); - - value = (red << info->var.red.offset) | - (green << info->var.green.offset) | - (blue << info->var.blue.offset); - value &= 0xFFFFFF; - - ((u32 *) (info->pseudo_palette))[regno] = value; - - } - - return 0; -} - -static struct fb_ops bfin_lq035q1_fb_ops = { - .owner = THIS_MODULE, - .fb_open = bfin_lq035q1_fb_open, - .fb_release = bfin_lq035q1_fb_release, - .fb_check_var = bfin_lq035q1_fb_check_var, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, - .fb_cursor = bfin_lq035q1_fb_cursor, - .fb_setcolreg = bfin_lq035q1_fb_setcolreg, -}; - -static irqreturn_t bfin_lq035q1_irq_error(int irq, void *dev_id) -{ - /*struct bfin_lq035q1fb_info *info = (struct bfin_lq035q1fb_info *)dev_id;*/ - - u16 status = bfin_read_PPI_STATUS(); - bfin_write_PPI_STATUS(-1); - - if (status) { - bfin_lq035q1_disable_ppi(); - disable_dma(CH_PPI); - - /* start dma */ - enable_dma(CH_PPI); - bfin_lq035q1_enable_ppi(); - bfin_write_PPI_STATUS(-1); - } - - return IRQ_HANDLED; -} - -static int bfin_lq035q1_probe(struct platform_device *pdev) -{ - struct bfin_lq035q1fb_info *info; - struct fb_info *fbinfo; - u32 active_video_mem_offset; - int ret; - - ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI"); - if (ret < 0) { - dev_err(&pdev->dev, "PPI DMA unavailable\n"); - goto out1; - } - - fbinfo = framebuffer_alloc(sizeof(*info), &pdev->dev); - if (!fbinfo) { - ret = -ENOMEM; - goto out2; - } - - info = fbinfo->par; - info->fb = fbinfo; - info->dev = &pdev->dev; - spin_lock_init(&info->lock); - - info->disp_info = pdev->dev.platform_data; - - platform_set_drvdata(pdev, fbinfo); - - ret = bfin_lq035q1_calc_timing(info); - if (ret < 0) { - dev_err(&pdev->dev, "Failed PPI Mode\n"); - goto out3; - } - - strcpy(fbinfo->fix.id, DRIVER_NAME); - - fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; - fbinfo->fix.type_aux = 0; - fbinfo->fix.xpanstep = 0; - fbinfo->fix.ypanstep = 0; - fbinfo->fix.ywrapstep = 0; - fbinfo->fix.accel = FB_ACCEL_NONE; - fbinfo->fix.visual = FB_VISUAL_TRUECOLOR; - - fbinfo->var.nonstd = 0; - fbinfo->var.activate = FB_ACTIVATE_NOW; - fbinfo->var.height = -1; - fbinfo->var.width = -1; - fbinfo->var.accel_flags = 0; - fbinfo->var.vmode = FB_VMODE_NONINTERLACED; - - fbinfo->var.xres = LCD_X_RES; - fbinfo->var.xres_virtual = LCD_X_RES; - fbinfo->var.yres = LCD_Y_RES; - fbinfo->var.yres_virtual = LCD_Y_RES; - fbinfo->var.bits_per_pixel = info->lcd_bpp; - - if (info->disp_info->mode & LQ035_BGR) { - if (info->lcd_bpp == 24) { - fbinfo->var.red.offset = 0; - fbinfo->var.green.offset = 8; - fbinfo->var.blue.offset = 16; - } else { - fbinfo->var.red.offset = 0; - fbinfo->var.green.offset = 5; - fbinfo->var.blue.offset = 11; - } - } else { - if (info->lcd_bpp == 24) { - fbinfo->var.red.offset = 16; - fbinfo->var.green.offset = 8; - fbinfo->var.blue.offset = 0; - } else { - fbinfo->var.red.offset = 11; - fbinfo->var.green.offset = 5; - fbinfo->var.blue.offset = 0; - } - } - - fbinfo->var.transp.offset = 0; - - if (info->lcd_bpp == 24) { - fbinfo->var.red.length = 8; - fbinfo->var.green.length = 8; - fbinfo->var.blue.length = 8; - } else { - fbinfo->var.red.length = 5; - fbinfo->var.green.length = 6; - fbinfo->var.blue.length = 5; - } - - fbinfo->var.transp.length = 0; - - active_video_mem_offset = ((U_LINE / 2) * LCD_X_RES * (info->lcd_bpp / 8)); - - fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * info->lcd_bpp / 8 - + active_video_mem_offset; - - fbinfo->fix.line_length = fbinfo->var.xres_virtual * - fbinfo->var.bits_per_pixel / 8; - - - fbinfo->fbops = &bfin_lq035q1_fb_ops; - fbinfo->flags = FBINFO_FLAG_DEFAULT; - - info->fb_buffer = - dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle, - GFP_KERNEL); - - if (NULL == info->fb_buffer) { - dev_err(&pdev->dev, "couldn't allocate dma buffer\n"); - ret = -ENOMEM; - goto out3; - } - - fbinfo->screen_base = (void *)info->fb_buffer + active_video_mem_offset; - fbinfo->fix.smem_start = (int)info->fb_buffer + active_video_mem_offset; - - fbinfo->fbops = &bfin_lq035q1_fb_ops; - - fbinfo->pseudo_palette = &info->pseudo_pal; - - ret = fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0); - if (ret < 0) { - dev_err(&pdev->dev, "failed to allocate colormap (%d entries)\n", - BFIN_LCD_NBR_PALETTE_ENTRIES); - goto out4; - } - - ret = bfin_lq035q1_request_ports(pdev, - info->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI); - if (ret) { - dev_err(&pdev->dev, "couldn't request gpio port\n"); - goto out6; - } - - info->irq = platform_get_irq(pdev, 0); - if (info->irq < 0) { - ret = -EINVAL; - goto out7; - } - - ret = request_irq(info->irq, bfin_lq035q1_irq_error, 0, - DRIVER_NAME" PPI ERROR", info); - if (ret < 0) { - dev_err(&pdev->dev, "unable to request PPI ERROR IRQ\n"); - goto out7; - } - - info->spidrv.driver.name = DRIVER_NAME"-spi"; - info->spidrv.probe = lq035q1_spidev_probe; - info->spidrv.remove = lq035q1_spidev_remove; - info->spidrv.shutdown = lq035q1_spidev_shutdown; - info->spidrv.driver.pm = LQ035Q1_SPIDEV_PM_OPS; - - ret = spi_register_driver(&info->spidrv); - if (ret < 0) { - dev_err(&pdev->dev, "couldn't register SPI Interface\n"); - goto out8; - } - - if (info->disp_info->use_bl) { - ret = gpio_request_one(info->disp_info->gpio_bl, - GPIOF_OUT_INIT_LOW, "LQ035 Backlight"); - - if (ret) { - dev_err(&pdev->dev, "failed to request GPIO %d\n", - info->disp_info->gpio_bl); - goto out9; - } - } - - ret = register_framebuffer(fbinfo); - if (ret < 0) { - dev_err(&pdev->dev, "unable to register framebuffer\n"); - goto out10; - } - - dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n", - LCD_X_RES, LCD_Y_RES, info->lcd_bpp); - - return 0; - - out10: - if (info->disp_info->use_bl) - gpio_free(info->disp_info->gpio_bl); - out9: - spi_unregister_driver(&info->spidrv); - out8: - free_irq(info->irq, info); - out7: - bfin_lq035q1_free_ports(info->disp_info->ppi_mode == - USE_RGB565_16_BIT_PPI); - out6: - fb_dealloc_cmap(&fbinfo->cmap); - out4: - dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, - info->dma_handle); - out3: - framebuffer_release(fbinfo); - out2: - free_dma(CH_PPI); - out1: - - return ret; -} - -static int bfin_lq035q1_remove(struct platform_device *pdev) -{ - struct fb_info *fbinfo = platform_get_drvdata(pdev); - struct bfin_lq035q1fb_info *info = fbinfo->par; - - if (info->disp_info->use_bl) - gpio_free(info->disp_info->gpio_bl); - - spi_unregister_driver(&info->spidrv); - - unregister_framebuffer(fbinfo); - - free_dma(CH_PPI); - free_irq(info->irq, info); - - if (info->fb_buffer != NULL) - dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, - info->dma_handle); - - fb_dealloc_cmap(&fbinfo->cmap); - - bfin_lq035q1_free_ports(info->disp_info->ppi_mode == - USE_RGB565_16_BIT_PPI); - - framebuffer_release(fbinfo); - - dev_info(&pdev->dev, "unregistered LCD driver\n"); - - return 0; -} - -#ifdef CONFIG_PM -static int bfin_lq035q1_suspend(struct device *dev) -{ - struct fb_info *fbinfo = dev_get_drvdata(dev); - struct bfin_lq035q1fb_info *info = fbinfo->par; - - if (info->lq035_open_cnt) { - lq035q1_backlight(info, 0); - bfin_lq035q1_disable_ppi(); - SSYNC(); - disable_dma(CH_PPI); - bfin_lq035q1_stop_timers(); - bfin_write_PPI_STATUS(-1); - } - - return 0; -} - -static int bfin_lq035q1_resume(struct device *dev) -{ - struct fb_info *fbinfo = dev_get_drvdata(dev); - struct bfin_lq035q1fb_info *info = fbinfo->par; - - if (info->lq035_open_cnt) { - bfin_lq035q1_disable_ppi(); - SSYNC(); - - bfin_lq035q1_config_dma(info); - bfin_lq035q1_config_ppi(info); - bfin_lq035q1_init_timers(info); - - /* start dma */ - enable_dma(CH_PPI); - bfin_lq035q1_enable_ppi(); - bfin_lq035q1_start_timers(); - lq035q1_backlight(info, 1); - } - - return 0; -} - -static const struct dev_pm_ops bfin_lq035q1_dev_pm_ops = { - .suspend = bfin_lq035q1_suspend, - .resume = bfin_lq035q1_resume, -}; -#endif - -static struct platform_driver bfin_lq035q1_driver = { - .probe = bfin_lq035q1_probe, - .remove = bfin_lq035q1_remove, - .driver = { - .name = DRIVER_NAME, -#ifdef CONFIG_PM - .pm = &bfin_lq035q1_dev_pm_ops, -#endif - }, -}; - -module_platform_driver(bfin_lq035q1_driver); - -MODULE_DESCRIPTION("Blackfin TFT LCD Driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/bfin-t350mcqb-fb.c b/drivers/video/fbdev/bfin-t350mcqb-fb.c deleted file mode 100644 index e5ee4d9677f7..000000000000 --- a/drivers/video/fbdev/bfin-t350mcqb-fb.c +++ /dev/null @@ -1,669 +0,0 @@ -/* - * File: drivers/video/bfin-t350mcqb-fb.c - * Based on: - * Author: Michael Hennerich - * - * Created: - * Description: Blackfin LCD Framebuffer driver - * - * - * Modified: - * Copyright 2004-2007 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define NO_BL_SUPPORT - -#define LCD_X_RES 320 /* Horizontal Resolution */ -#define LCD_Y_RES 240 /* Vertical Resolution */ -#define LCD_BPP 24 /* Bit Per Pixel */ - -#define DMA_BUS_SIZE 16 -#define LCD_CLK (12*1000*1000) /* 12MHz */ - -#define CLOCKS_PER_PIX 3 - - /* - * HS and VS timing parameters (all in number of PPI clk ticks) - */ - -#define U_LINE 1 /* Blanking Lines */ - -#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */ -#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */ -#define H_PULSE 90 /* HS pulse width */ -#define H_START 204 /* first valid pixel */ - -#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */ -#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */ -#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */ - -#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX) - -#define BFIN_LCD_NBR_PALETTE_ENTRIES 256 - -#define DRIVER_NAME "bfin-t350mcqb" -static char driver_name[] = DRIVER_NAME; - -struct bfin_t350mcqbfb_info { - struct fb_info *fb; - struct device *dev; - unsigned char *fb_buffer; /* RGB Buffer */ - dma_addr_t dma_handle; - int lq043_open_cnt; - int irq; - spinlock_t lock; /* lock */ - u32 pseudo_pal[16]; -}; - -static int nocursor; -module_param(nocursor, int, 0644); -MODULE_PARM_DESC(nocursor, "cursor enable/disable"); - -#define PPI_TX_MODE 0x2 -#define PPI_XFER_TYPE_11 0xC -#define PPI_PORT_CFG_01 0x10 -#define PPI_PACK_EN 0x80 -#define PPI_POLS_1 0x8000 - -static void bfin_t350mcqb_config_ppi(struct bfin_t350mcqbfb_info *fbi) -{ - bfin_write_PPI_DELAY(H_START); - bfin_write_PPI_COUNT(H_ACTPIX-1); - bfin_write_PPI_FRAME(V_LINES); - - bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */ - PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ - PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ - PPI_PACK_EN | /* packing enabled PACK_EN */ - PPI_POLS_1); /* faling edge syncs POLS */ -} - -static inline void bfin_t350mcqb_disable_ppi(void) -{ - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); -} - -static inline void bfin_t350mcqb_enable_ppi(void) -{ - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); -} - -static void bfin_t350mcqb_start_timers(void) -{ - unsigned long flags; - - local_irq_save(flags); - enable_gptimers(TIMER1bit); - enable_gptimers(TIMER0bit); - local_irq_restore(flags); -} - -static void bfin_t350mcqb_stop_timers(void) -{ - disable_gptimers(TIMER0bit | TIMER1bit); - - set_gptimer_status(0, TIMER_STATUS_TRUN0 | TIMER_STATUS_TRUN1 | - TIMER_STATUS_TIMIL0 | TIMER_STATUS_TIMIL1 | - TIMER_STATUS_TOVF0 | TIMER_STATUS_TOVF1); - -} - -static void bfin_t350mcqb_init_timers(void) -{ - - bfin_t350mcqb_stop_timers(); - - set_gptimer_period(TIMER0_id, H_PERIOD); - set_gptimer_pwidth(TIMER0_id, H_PULSE); - set_gptimer_config(TIMER0_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | - TIMER_TIN_SEL | TIMER_CLK_SEL| - TIMER_EMU_RUN); - - set_gptimer_period(TIMER1_id, V_PERIOD); - set_gptimer_pwidth(TIMER1_id, V_PULSE); - set_gptimer_config(TIMER1_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | - TIMER_TIN_SEL | TIMER_CLK_SEL | - TIMER_EMU_RUN); - -} - -static void bfin_t350mcqb_config_dma(struct bfin_t350mcqbfb_info *fbi) -{ - - set_dma_config(CH_PPI, - set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, - INTR_DISABLE, DIMENSION_2D, - DATA_SIZE_16, - DMA_NOSYNC_KEEP_DMA_BUF)); - set_dma_x_count(CH_PPI, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); - set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8); - set_dma_y_count(CH_PPI, V_LINES); - - set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8); - set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer); - -} - -static u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, - P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, - P_PPI0_D6, P_PPI0_D7, 0}; - -static int bfin_t350mcqb_request_ports(int action) -{ - if (action) { - if (peripheral_request_list(ppi0_req_8, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals failed\n"); - return -EFAULT; - } - } else - peripheral_free_list(ppi0_req_8); - - return 0; -} - -static int bfin_t350mcqb_fb_open(struct fb_info *info, int user) -{ - struct bfin_t350mcqbfb_info *fbi = info->par; - - spin_lock(&fbi->lock); - fbi->lq043_open_cnt++; - - if (fbi->lq043_open_cnt <= 1) { - - bfin_t350mcqb_disable_ppi(); - SSYNC(); - - bfin_t350mcqb_config_dma(fbi); - bfin_t350mcqb_config_ppi(fbi); - bfin_t350mcqb_init_timers(); - - /* start dma */ - enable_dma(CH_PPI); - bfin_t350mcqb_enable_ppi(); - bfin_t350mcqb_start_timers(); - } - - spin_unlock(&fbi->lock); - - return 0; -} - -static int bfin_t350mcqb_fb_release(struct fb_info *info, int user) -{ - struct bfin_t350mcqbfb_info *fbi = info->par; - - spin_lock(&fbi->lock); - - fbi->lq043_open_cnt--; - - if (fbi->lq043_open_cnt <= 0) { - bfin_t350mcqb_disable_ppi(); - SSYNC(); - disable_dma(CH_PPI); - bfin_t350mcqb_stop_timers(); - } - - spin_unlock(&fbi->lock); - - return 0; -} - -static int bfin_t350mcqb_fb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - - switch (var->bits_per_pixel) { - case 24:/* TRUECOLOUR, 16m */ - var->red.offset = 0; - var->green.offset = 8; - var->blue.offset = 16; - var->red.length = var->green.length = var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - var->transp.msb_right = 0; - var->red.msb_right = 0; - var->green.msb_right = 0; - var->blue.msb_right = 0; - break; - default: - pr_debug("%s: depth not supported: %u BPP\n", __func__, - var->bits_per_pixel); - return -EINVAL; - } - - if (info->var.xres != var->xres || info->var.yres != var->yres || - info->var.xres_virtual != var->xres_virtual || - info->var.yres_virtual != var->yres_virtual) { - pr_debug("%s: Resolution not supported: X%u x Y%u \n", - __func__, var->xres, var->yres); - return -EINVAL; - } - - /* - * Memory limit - */ - - if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { - pr_debug("%s: Memory Limit requested yres_virtual = %u\n", - __func__, var->yres_virtual); - return -ENOMEM; - } - - return 0; -} - -int bfin_t350mcqb_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - if (nocursor) - return 0; - else - return -EINVAL; /* just to force soft_cursor() call */ -} - -static int bfin_t350mcqb_fb_setcolreg(u_int regno, u_int red, u_int green, - u_int blue, u_int transp, - struct fb_info *info) -{ - if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES) - return -EINVAL; - - if (info->var.grayscale) { - /* grayscale = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; - } - - if (info->fix.visual == FB_VISUAL_TRUECOLOR) { - - u32 value; - /* Place color in the pseudopalette */ - if (regno > 16) - return -EINVAL; - - red >>= (16 - info->var.red.length); - green >>= (16 - info->var.green.length); - blue >>= (16 - info->var.blue.length); - - value = (red << info->var.red.offset) | - (green << info->var.green.offset) | - (blue << info->var.blue.offset); - value &= 0xFFFFFF; - - ((u32 *) (info->pseudo_palette))[regno] = value; - - } - - return 0; -} - -static struct fb_ops bfin_t350mcqb_fb_ops = { - .owner = THIS_MODULE, - .fb_open = bfin_t350mcqb_fb_open, - .fb_release = bfin_t350mcqb_fb_release, - .fb_check_var = bfin_t350mcqb_fb_check_var, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, - .fb_cursor = bfin_t350mcqb_fb_cursor, - .fb_setcolreg = bfin_t350mcqb_fb_setcolreg, -}; - -#ifndef NO_BL_SUPPORT -static int bl_get_brightness(struct backlight_device *bd) -{ - return 0; -} - -static const struct backlight_ops bfin_lq043fb_bl_ops = { - .get_brightness = bl_get_brightness, -}; - -static struct backlight_device *bl_dev; - -static int bfin_lcd_get_power(struct lcd_device *dev) -{ - return 0; -} - -static int bfin_lcd_set_power(struct lcd_device *dev, int power) -{ - return 0; -} - -static int bfin_lcd_get_contrast(struct lcd_device *dev) -{ - return 0; -} - -static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast) -{ - - return 0; -} - -static int bfin_lcd_check_fb(struct lcd_device *dev, struct fb_info *fi) -{ - if (!fi || (fi == &bfin_t350mcqb_fb)) - return 1; - return 0; -} - -static struct lcd_ops bfin_lcd_ops = { - .get_power = bfin_lcd_get_power, - .set_power = bfin_lcd_set_power, - .get_contrast = bfin_lcd_get_contrast, - .set_contrast = bfin_lcd_set_contrast, - .check_fb = bfin_lcd_check_fb, -}; - -static struct lcd_device *lcd_dev; -#endif - -static irqreturn_t bfin_t350mcqb_irq_error(int irq, void *dev_id) -{ - /*struct bfin_t350mcqbfb_info *info = (struct bfin_t350mcqbfb_info *)dev_id;*/ - - u16 status = bfin_read_PPI_STATUS(); - bfin_write_PPI_STATUS(0xFFFF); - - if (status) { - bfin_t350mcqb_disable_ppi(); - disable_dma(CH_PPI); - - /* start dma */ - enable_dma(CH_PPI); - bfin_t350mcqb_enable_ppi(); - bfin_write_PPI_STATUS(0xFFFF); - } - - return IRQ_HANDLED; -} - -static int bfin_t350mcqb_probe(struct platform_device *pdev) -{ -#ifndef NO_BL_SUPPORT - struct backlight_properties props; -#endif - struct bfin_t350mcqbfb_info *info; - struct fb_info *fbinfo; - int ret; - - printk(KERN_INFO DRIVER_NAME ": %dx%d %d-bit RGB FrameBuffer initializing...\n", - LCD_X_RES, LCD_Y_RES, LCD_BPP); - - if (request_dma(CH_PPI, "CH_PPI") < 0) { - printk(KERN_ERR DRIVER_NAME - ": couldn't request CH_PPI DMA\n"); - ret = -EFAULT; - goto out1; - } - - fbinfo = - framebuffer_alloc(sizeof(struct bfin_t350mcqbfb_info), &pdev->dev); - if (!fbinfo) { - ret = -ENOMEM; - goto out2; - } - - info = fbinfo->par; - info->fb = fbinfo; - info->dev = &pdev->dev; - spin_lock_init(&info->lock); - - platform_set_drvdata(pdev, fbinfo); - - strcpy(fbinfo->fix.id, driver_name); - - fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; - fbinfo->fix.type_aux = 0; - fbinfo->fix.xpanstep = 0; - fbinfo->fix.ypanstep = 0; - fbinfo->fix.ywrapstep = 0; - fbinfo->fix.accel = FB_ACCEL_NONE; - fbinfo->fix.visual = FB_VISUAL_TRUECOLOR; - - fbinfo->var.nonstd = 0; - fbinfo->var.activate = FB_ACTIVATE_NOW; - fbinfo->var.height = 53; - fbinfo->var.width = 70; - fbinfo->var.accel_flags = 0; - fbinfo->var.vmode = FB_VMODE_NONINTERLACED; - - fbinfo->var.xres = LCD_X_RES; - fbinfo->var.xres_virtual = LCD_X_RES; - fbinfo->var.yres = LCD_Y_RES; - fbinfo->var.yres_virtual = LCD_Y_RES; - fbinfo->var.bits_per_pixel = LCD_BPP; - - fbinfo->var.red.offset = 0; - fbinfo->var.green.offset = 8; - fbinfo->var.blue.offset = 16; - fbinfo->var.transp.offset = 0; - fbinfo->var.red.length = 8; - fbinfo->var.green.length = 8; - fbinfo->var.blue.length = 8; - fbinfo->var.transp.length = 0; - fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * LCD_BPP / 8; - - fbinfo->fix.line_length = fbinfo->var.xres_virtual * - fbinfo->var.bits_per_pixel / 8; - - - fbinfo->fbops = &bfin_t350mcqb_fb_ops; - fbinfo->flags = FBINFO_FLAG_DEFAULT; - - info->fb_buffer = dma_alloc_coherent(NULL, fbinfo->fix.smem_len + - ACTIVE_VIDEO_MEM_OFFSET, - &info->dma_handle, GFP_KERNEL); - - if (NULL == info->fb_buffer) { - printk(KERN_ERR DRIVER_NAME - ": couldn't allocate dma buffer.\n"); - ret = -ENOMEM; - goto out3; - } - - fbinfo->screen_base = (void *)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET; - fbinfo->fix.smem_start = (int)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET; - - fbinfo->fbops = &bfin_t350mcqb_fb_ops; - - fbinfo->pseudo_palette = &info->pseudo_pal; - - if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) - < 0) { - printk(KERN_ERR DRIVER_NAME - "Fail to allocate colormap (%d entries)\n", - BFIN_LCD_NBR_PALETTE_ENTRIES); - ret = -EFAULT; - goto out4; - } - - if (bfin_t350mcqb_request_ports(1)) { - printk(KERN_ERR DRIVER_NAME ": couldn't request gpio port.\n"); - ret = -EFAULT; - goto out6; - } - - info->irq = platform_get_irq(pdev, 0); - if (info->irq < 0) { - ret = -EINVAL; - goto out7; - } - - ret = request_irq(info->irq, bfin_t350mcqb_irq_error, 0, - "PPI ERROR", info); - if (ret < 0) { - printk(KERN_ERR DRIVER_NAME - ": unable to request PPI ERROR IRQ\n"); - goto out7; - } - - if (register_framebuffer(fbinfo) < 0) { - printk(KERN_ERR DRIVER_NAME - ": unable to register framebuffer.\n"); - ret = -EINVAL; - goto out8; - } -#ifndef NO_BL_SUPPORT - memset(&props, 0, sizeof(struct backlight_properties)); - props.type = BACKLIGHT_RAW; - props.max_brightness = 255; - bl_dev = backlight_device_register("bf52x-bl", NULL, NULL, - &bfin_lq043fb_bl_ops, &props); - if (IS_ERR(bl_dev)) { - printk(KERN_ERR DRIVER_NAME - ": unable to register backlight.\n"); - ret = -EINVAL; - unregister_framebuffer(fbinfo); - goto out8; - } - - lcd_dev = lcd_device_register(DRIVER_NAME, NULL, &bfin_lcd_ops); - lcd_dev->props.max_contrast = 255, printk(KERN_INFO "Done.\n"); -#endif - - return 0; - -out8: - free_irq(info->irq, info); -out7: - bfin_t350mcqb_request_ports(0); -out6: - fb_dealloc_cmap(&fbinfo->cmap); -out4: - dma_free_coherent(NULL, fbinfo->fix.smem_len + ACTIVE_VIDEO_MEM_OFFSET, - info->fb_buffer, info->dma_handle); -out3: - framebuffer_release(fbinfo); -out2: - free_dma(CH_PPI); -out1: - - return ret; -} - -static int bfin_t350mcqb_remove(struct platform_device *pdev) -{ - - struct fb_info *fbinfo = platform_get_drvdata(pdev); - struct bfin_t350mcqbfb_info *info = fbinfo->par; - - unregister_framebuffer(fbinfo); - - free_dma(CH_PPI); - free_irq(info->irq, info); - - if (info->fb_buffer != NULL) - dma_free_coherent(NULL, fbinfo->fix.smem_len + - ACTIVE_VIDEO_MEM_OFFSET, info->fb_buffer, - info->dma_handle); - - fb_dealloc_cmap(&fbinfo->cmap); - -#ifndef NO_BL_SUPPORT - lcd_device_unregister(lcd_dev); - backlight_device_unregister(bl_dev); -#endif - - bfin_t350mcqb_request_ports(0); - - framebuffer_release(fbinfo); - - printk(KERN_INFO DRIVER_NAME ": Unregister LCD driver.\n"); - - return 0; -} - -#ifdef CONFIG_PM -static int bfin_t350mcqb_suspend(struct platform_device *pdev, pm_message_t state) -{ - struct fb_info *fbinfo = platform_get_drvdata(pdev); - struct bfin_t350mcqbfb_info *fbi = fbinfo->par; - - if (fbi->lq043_open_cnt) { - bfin_t350mcqb_disable_ppi(); - disable_dma(CH_PPI); - bfin_t350mcqb_stop_timers(); - bfin_write_PPI_STATUS(-1); - } - - - return 0; -} - -static int bfin_t350mcqb_resume(struct platform_device *pdev) -{ - struct fb_info *fbinfo = platform_get_drvdata(pdev); - struct bfin_t350mcqbfb_info *fbi = fbinfo->par; - - if (fbi->lq043_open_cnt) { - bfin_t350mcqb_config_dma(fbi); - bfin_t350mcqb_config_ppi(fbi); - bfin_t350mcqb_init_timers(); - - /* start dma */ - enable_dma(CH_PPI); - bfin_t350mcqb_enable_ppi(); - bfin_t350mcqb_start_timers(); - } - - return 0; -} -#else -#define bfin_t350mcqb_suspend NULL -#define bfin_t350mcqb_resume NULL -#endif - -static struct platform_driver bfin_t350mcqb_driver = { - .probe = bfin_t350mcqb_probe, - .remove = bfin_t350mcqb_remove, - .suspend = bfin_t350mcqb_suspend, - .resume = bfin_t350mcqb_resume, - .driver = { - .name = DRIVER_NAME, - }, -}; -module_platform_driver(bfin_t350mcqb_driver); - -MODULE_DESCRIPTION("Blackfin TFT LCD Driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/bfin_adv7393fb.c b/drivers/video/fbdev/bfin_adv7393fb.c deleted file mode 100644 index 542ffaddc6ab..000000000000 --- a/drivers/video/fbdev/bfin_adv7393fb.c +++ /dev/null @@ -1,828 +0,0 @@ -/* - * Frame buffer driver for ADV7393/2 video encoder - * - * Copyright 2006-2009 Analog Devices Inc. - * Licensed under the GPL-2 or late. - */ - -/* - * TODO: Remove Globals - * TODO: Code Cleanup - */ - -#define DRIVER_NAME "bfin-adv7393" - -#define pr_fmt(fmt) DRIVER_NAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "bfin_adv7393fb.h" - -static int mode = VMODE; -static int mem = VMEM; -static int nocursor = 1; - -static const unsigned short ppi_pins[] = { - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - 0 -}; - -/* - * card parameters - */ - -static struct bfin_adv7393_fb_par { - /* structure holding blackfin / adv7393 parameters when - screen is blanked */ - struct { - u8 Mode; /* ntsc/pal/? */ - } vga_state; - atomic_t ref_count; -} bfin_par; - -/* --------------------------------------------------------------------- */ - -static struct fb_var_screeninfo bfin_adv7393_fb_defined = { - .xres = 720, - .yres = 480, - .xres_virtual = 720, - .yres_virtual = 480, - .bits_per_pixel = 16, - .activate = FB_ACTIVATE_TEST, - .height = -1, - .width = -1, - .left_margin = 0, - .right_margin = 0, - .upper_margin = 0, - .lower_margin = 0, - .vmode = FB_VMODE_INTERLACED, - .red = {11, 5, 0}, - .green = {5, 6, 0}, - .blue = {0, 5, 0}, - .transp = {0, 0, 0}, -}; - -static struct fb_fix_screeninfo bfin_adv7393_fb_fix = { - .id = "BFIN ADV7393", - .smem_len = 720 * 480 * 2, - .type = FB_TYPE_PACKED_PIXELS, - .visual = FB_VISUAL_TRUECOLOR, - .xpanstep = 0, - .ypanstep = 0, - .line_length = 720 * 2, - .accel = FB_ACCEL_NONE -}; - -static struct fb_ops bfin_adv7393_fb_ops = { - .owner = THIS_MODULE, - .fb_open = bfin_adv7393_fb_open, - .fb_release = bfin_adv7393_fb_release, - .fb_check_var = bfin_adv7393_fb_check_var, - .fb_pan_display = bfin_adv7393_fb_pan_display, - .fb_blank = bfin_adv7393_fb_blank, - .fb_fillrect = cfb_fillrect, - .fb_copyarea = cfb_copyarea, - .fb_imageblit = cfb_imageblit, - .fb_cursor = bfin_adv7393_fb_cursor, - .fb_setcolreg = bfin_adv7393_fb_setcolreg, -}; - -static int dma_desc_list(struct adv7393fb_device *fbdev, u16 arg) -{ - if (arg == BUILD) { /* Build */ - fbdev->vb1 = l1_data_sram_zalloc(sizeof(struct dmasg)); - if (fbdev->vb1 == NULL) - goto error; - - fbdev->av1 = l1_data_sram_zalloc(sizeof(struct dmasg)); - if (fbdev->av1 == NULL) - goto error; - - fbdev->vb2 = l1_data_sram_zalloc(sizeof(struct dmasg)); - if (fbdev->vb2 == NULL) - goto error; - - fbdev->av2 = l1_data_sram_zalloc(sizeof(struct dmasg)); - if (fbdev->av2 == NULL) - goto error; - - /* Build linked DMA descriptor list */ - fbdev->vb1->next_desc_addr = fbdev->av1; - fbdev->av1->next_desc_addr = fbdev->vb2; - fbdev->vb2->next_desc_addr = fbdev->av2; - fbdev->av2->next_desc_addr = fbdev->vb1; - - /* Save list head */ - fbdev->descriptor_list_head = fbdev->av2; - - /* Vertical Blanking Field 1 */ - fbdev->vb1->start_addr = VB_DUMMY_MEMORY_SOURCE; - fbdev->vb1->cfg = DMA_CFG_VAL; - - fbdev->vb1->x_count = - fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank; - - fbdev->vb1->x_modify = 0; - fbdev->vb1->y_count = fbdev->modes[mode].vb1_lines; - fbdev->vb1->y_modify = 0; - - /* Active Video Field 1 */ - - fbdev->av1->start_addr = (unsigned long)fbdev->fb_mem; - fbdev->av1->cfg = DMA_CFG_VAL; - fbdev->av1->x_count = - fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank; - fbdev->av1->x_modify = fbdev->modes[mode].bpp / 8; - fbdev->av1->y_count = fbdev->modes[mode].a_lines; - fbdev->av1->y_modify = - (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank + - 1) * (fbdev->modes[mode].bpp / 8); - - /* Vertical Blanking Field 2 */ - - fbdev->vb2->start_addr = VB_DUMMY_MEMORY_SOURCE; - fbdev->vb2->cfg = DMA_CFG_VAL; - fbdev->vb2->x_count = - fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank; - - fbdev->vb2->x_modify = 0; - fbdev->vb2->y_count = fbdev->modes[mode].vb2_lines; - fbdev->vb2->y_modify = 0; - - /* Active Video Field 2 */ - - fbdev->av2->start_addr = - (unsigned long)fbdev->fb_mem + fbdev->line_len; - - fbdev->av2->cfg = DMA_CFG_VAL; - - fbdev->av2->x_count = - fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank; - - fbdev->av2->x_modify = (fbdev->modes[mode].bpp / 8); - fbdev->av2->y_count = fbdev->modes[mode].a_lines; - - fbdev->av2->y_modify = - (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank + - 1) * (fbdev->modes[mode].bpp / 8); - - return 1; - } - -error: - l1_data_sram_free(fbdev->vb1); - l1_data_sram_free(fbdev->av1); - l1_data_sram_free(fbdev->vb2); - l1_data_sram_free(fbdev->av2); - - return 0; -} - -static int bfin_config_dma(struct adv7393fb_device *fbdev) -{ - BUG_ON(!(fbdev->fb_mem)); - - set_dma_x_count(CH_PPI, fbdev->descriptor_list_head->x_count); - set_dma_x_modify(CH_PPI, fbdev->descriptor_list_head->x_modify); - set_dma_y_count(CH_PPI, fbdev->descriptor_list_head->y_count); - set_dma_y_modify(CH_PPI, fbdev->descriptor_list_head->y_modify); - set_dma_start_addr(CH_PPI, fbdev->descriptor_list_head->start_addr); - set_dma_next_desc_addr(CH_PPI, - fbdev->descriptor_list_head->next_desc_addr); - set_dma_config(CH_PPI, fbdev->descriptor_list_head->cfg); - - return 1; -} - -static void bfin_disable_dma(void) -{ - bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN); -} - -static void bfin_config_ppi(struct adv7393fb_device *fbdev) -{ - if (ANOMALY_05000183) { - bfin_write_TIMER2_CONFIG(WDTH_CAP); - bfin_write_TIMER_ENABLE(TIMEN2); - } - - bfin_write_PPI_CONTROL(0x381E); - bfin_write_PPI_FRAME(fbdev->modes[mode].tot_lines); - bfin_write_PPI_COUNT(fbdev->modes[mode].xres + - fbdev->modes[mode].boeft_blank - 1); - bfin_write_PPI_DELAY(fbdev->modes[mode].aoeft_blank - 1); -} - -static void bfin_enable_ppi(void) -{ - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); -} - -static void bfin_disable_ppi(void) -{ - bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); -} - -static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value) -{ - return i2c_smbus_write_byte_data(client, reg, value); -} - -static inline int adv7393_read(struct i2c_client *client, u8 reg) -{ - return i2c_smbus_read_byte_data(client, reg); -} - -static int -adv7393_write_block(struct i2c_client *client, - const u8 *data, unsigned int len) -{ - int ret = -1; - u8 reg; - - while (len >= 2) { - reg = *data++; - ret = adv7393_write(client, reg, *data++); - if (ret < 0) - break; - len -= 2; - } - - return ret; -} - -static int adv7393_mode(struct i2c_client *client, u16 mode) -{ - switch (mode) { - case POWER_ON: /* ADV7393 Sleep mode OFF */ - adv7393_write(client, 0x00, 0x1E); - break; - case POWER_DOWN: /* ADV7393 Sleep mode ON */ - adv7393_write(client, 0x00, 0x1F); - break; - case BLANK_OFF: /* Pixel Data Valid */ - adv7393_write(client, 0x82, 0xCB); - break; - case BLANK_ON: /* Pixel Data Invalid */ - adv7393_write(client, 0x82, 0x8B); - break; - default: - return -EINVAL; - break; - } - return 0; -} - -static irqreturn_t ppi_irq_error(int irq, void *dev_id) -{ - - struct adv7393fb_device *fbdev = (struct adv7393fb_device *)dev_id; - - u16 status = bfin_read_PPI_STATUS(); - - pr_debug("%s: PPI Status = 0x%X\n", __func__, status); - - if (status) { - bfin_disable_dma(); /* TODO: Check Sequence */ - bfin_disable_ppi(); - bfin_clear_PPI_STATUS(); - bfin_config_dma(fbdev); - bfin_enable_ppi(); - } - - return IRQ_HANDLED; - -} - -static int proc_output(char *buf) -{ - char *p = buf; - - p += sprintf(p, - "Usage:\n" - "echo 0x[REG][Value] > adv7393\n" - "example: echo 0x1234 >adv7393\n" - "writes 0x34 into Register 0x12\n"); - - return p - buf; -} - -static ssize_t -adv7393_read_proc(struct file *file, char __user *buf, - size_t size, loff_t *ppos) -{ - static const char message[] = "Usage:\n" - "echo 0x[REG][Value] > adv7393\n" - "example: echo 0x1234 >adv7393\n" - "writes 0x34 into Register 0x12\n"; - return simple_read_from_buffer(buf, size, ppos, message, - sizeof(message)); -} - -static ssize_t -adv7393_write_proc(struct file *file, const char __user * buffer, - size_t count, loff_t *ppos) -{ - struct adv7393fb_device *fbdev = PDE_DATA(file_inode(file)); - unsigned int val; - int ret; - - ret = kstrtouint_from_user(buffer, count, 0, &val); - if (ret) - return -EFAULT; - - adv7393_write(fbdev->client, val >> 8, val & 0xff); - - return count; -} - -static const struct file_operations fops = { - .read = adv7393_read_proc, - .write = adv7393_write_proc, - .llseek = default_llseek, -}; - -static int bfin_adv7393_fb_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - int ret = 0; - struct proc_dir_entry *entry; - - struct adv7393fb_device *fbdev = NULL; - - if (mem > 2) { - dev_err(&client->dev, "mem out of allowed range [1;2]\n"); - return -EINVAL; - } - - if (mode >= ARRAY_SIZE(known_modes)) { - dev_err(&client->dev, "mode %d: not supported", mode); - return -EFAULT; - } - - fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL); - if (!fbdev) { - dev_err(&client->dev, "failed to allocate device private record"); - return -ENOMEM; - } - - i2c_set_clientdata(client, fbdev); - - fbdev->modes = known_modes; - fbdev->client = client; - - fbdev->fb_len = - mem * fbdev->modes[mode].xres * fbdev->modes[mode].xres * - (fbdev->modes[mode].bpp / 8); - - fbdev->line_len = - fbdev->modes[mode].xres * (fbdev->modes[mode].bpp / 8); - - /* Workaround "PPI Does Not Start Properly In Specific Mode" */ - if (ANOMALY_05000400) { - ret = gpio_request_one(P_IDENT(P_PPI0_FS3), GPIOF_OUT_INIT_LOW, - "PPI0_FS3"); - if (ret) { - dev_err(&client->dev, "PPI0_FS3 GPIO request failed\n"); - ret = -EBUSY; - goto free_fbdev; - } - } - - if (peripheral_request_list(ppi_pins, DRIVER_NAME)) { - dev_err(&client->dev, "requesting PPI peripheral failed\n"); - ret = -EFAULT; - goto free_gpio; - } - - fbdev->fb_mem = - dma_alloc_coherent(NULL, fbdev->fb_len, &fbdev->dma_handle, - GFP_KERNEL); - - if (NULL == fbdev->fb_mem) { - dev_err(&client->dev, "couldn't allocate dma buffer (%d bytes)\n", - (u32) fbdev->fb_len); - ret = -ENOMEM; - goto free_ppi_pins; - } - - fbdev->info.screen_base = (void *)fbdev->fb_mem; - bfin_adv7393_fb_fix.smem_start = (int)fbdev->fb_mem; - - bfin_adv7393_fb_fix.smem_len = fbdev->fb_len; - bfin_adv7393_fb_fix.line_length = fbdev->line_len; - - if (mem > 1) - bfin_adv7393_fb_fix.ypanstep = 1; - - bfin_adv7393_fb_defined.red.length = 5; - bfin_adv7393_fb_defined.green.length = 6; - bfin_adv7393_fb_defined.blue.length = 5; - - bfin_adv7393_fb_defined.xres = fbdev->modes[mode].xres; - bfin_adv7393_fb_defined.yres = fbdev->modes[mode].yres; - bfin_adv7393_fb_defined.xres_virtual = fbdev->modes[mode].xres; - bfin_adv7393_fb_defined.yres_virtual = mem * fbdev->modes[mode].yres; - bfin_adv7393_fb_defined.bits_per_pixel = fbdev->modes[mode].bpp; - - fbdev->info.fbops = &bfin_adv7393_fb_ops; - fbdev->info.var = bfin_adv7393_fb_defined; - fbdev->info.fix = bfin_adv7393_fb_fix; - fbdev->info.par = &bfin_par; - fbdev->info.flags = FBINFO_DEFAULT; - - fbdev->info.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL); - if (!fbdev->info.pseudo_palette) { - dev_err(&client->dev, "failed to allocate pseudo_palette\n"); - ret = -ENOMEM; - goto free_fb_mem; - } - - if (fb_alloc_cmap(&fbdev->info.cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) < 0) { - dev_err(&client->dev, "failed to allocate colormap (%d entries)\n", - BFIN_LCD_NBR_PALETTE_ENTRIES); - ret = -EFAULT; - goto free_palette; - } - - if (request_dma(CH_PPI, "BF5xx_PPI_DMA") < 0) { - dev_err(&client->dev, "unable to request PPI DMA\n"); - ret = -EFAULT; - goto free_cmap; - } - - if (request_irq(IRQ_PPI_ERROR, ppi_irq_error, 0, - "PPI ERROR", fbdev) < 0) { - dev_err(&client->dev, "unable to request PPI ERROR IRQ\n"); - ret = -EFAULT; - goto free_ch_ppi; - } - - fbdev->open = 0; - - ret = adv7393_write_block(client, fbdev->modes[mode].adv7393_i2c_initd, - fbdev->modes[mode].adv7393_i2c_initd_len); - - if (ret) { - dev_err(&client->dev, "i2c attach: init error\n"); - goto free_irq_ppi; - } - - - if (register_framebuffer(&fbdev->info) < 0) { - dev_err(&client->dev, "unable to register framebuffer\n"); - ret = -EFAULT; - goto free_irq_ppi; - } - - dev_info(&client->dev, "fb%d: %s frame buffer device\n", - fbdev->info.node, fbdev->info.fix.id); - dev_info(&client->dev, "fb memory address : 0x%p\n", fbdev->fb_mem); - - entry = proc_create_data("driver/adv7393", 0, NULL, &fops, fbdev); - if (!entry) { - dev_err(&client->dev, "unable to create /proc entry\n"); - ret = -EFAULT; - goto free_fb; - } - return 0; - -free_fb: - unregister_framebuffer(&fbdev->info); -free_irq_ppi: - free_irq(IRQ_PPI_ERROR, fbdev); -free_ch_ppi: - free_dma(CH_PPI); -free_cmap: - fb_dealloc_cmap(&fbdev->info.cmap); -free_palette: - kfree(fbdev->info.pseudo_palette); -free_fb_mem: - dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem, - fbdev->dma_handle); -free_ppi_pins: - peripheral_free_list(ppi_pins); -free_gpio: - if (ANOMALY_05000400) - gpio_free(P_IDENT(P_PPI0_FS3)); -free_fbdev: - kfree(fbdev); - - return ret; -} - -static int bfin_adv7393_fb_open(struct fb_info *info, int user) -{ - struct adv7393fb_device *fbdev = to_adv7393fb_device(info); - - fbdev->info.screen_base = (void *)fbdev->fb_mem; - if (!fbdev->info.screen_base) { - dev_err(&fbdev->client->dev, "unable to map device\n"); - return -ENOMEM; - } - - fbdev->open = 1; - dma_desc_list(fbdev, BUILD); - adv7393_mode(fbdev->client, BLANK_OFF); - bfin_config_ppi(fbdev); - bfin_config_dma(fbdev); - bfin_enable_ppi(); - - return 0; -} - -static int bfin_adv7393_fb_release(struct fb_info *info, int user) -{ - struct adv7393fb_device *fbdev = to_adv7393fb_device(info); - - adv7393_mode(fbdev->client, BLANK_ON); - bfin_disable_dma(); - bfin_disable_ppi(); - dma_desc_list(fbdev, DESTRUCT); - fbdev->open = 0; - return 0; -} - -static int -bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) -{ - - switch (var->bits_per_pixel) { - case 16:/* DIRECTCOLOUR, 64k */ - var->red.offset = info->var.red.offset; - var->green.offset = info->var.green.offset; - var->blue.offset = info->var.blue.offset; - var->red.length = info->var.red.length; - var->green.length = info->var.green.length; - var->blue.length = info->var.blue.length; - var->transp.offset = 0; - var->transp.length = 0; - var->transp.msb_right = 0; - var->red.msb_right = 0; - var->green.msb_right = 0; - var->blue.msb_right = 0; - break; - default: - pr_debug("%s: depth not supported: %u BPP\n", __func__, - var->bits_per_pixel); - return -EINVAL; - } - - if (info->var.xres != var->xres || - info->var.yres != var->yres || - info->var.xres_virtual != var->xres_virtual || - info->var.yres_virtual != var->yres_virtual) { - pr_debug("%s: Resolution not supported: X%u x Y%u\n", - __func__, var->xres, var->yres); - return -EINVAL; - } - - /* - * Memory limit - */ - - if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { - pr_debug("%s: Memory Limit requested yres_virtual = %u\n", - __func__, var->yres_virtual); - return -ENOMEM; - } - - return 0; -} - -static int -bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) -{ - int dy; - u32 dmaaddr; - struct adv7393fb_device *fbdev = to_adv7393fb_device(info); - - if (!var || !info) - return -EINVAL; - - if (var->xoffset - info->var.xoffset) { - /* No support for X panning for now! */ - return -EINVAL; - } - dy = var->yoffset - info->var.yoffset; - - if (dy) { - pr_debug("%s: Panning screen of %d lines\n", __func__, dy); - - dmaaddr = fbdev->av1->start_addr; - dmaaddr += (info->fix.line_length * dy); - /* TODO: Wait for current frame to finished */ - - fbdev->av1->start_addr = (unsigned long)dmaaddr; - fbdev->av2->start_addr = (unsigned long)dmaaddr + fbdev->line_len; - } - - return 0; - -} - -/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */ -static int bfin_adv7393_fb_blank(int blank, struct fb_info *info) -{ - struct adv7393fb_device *fbdev = to_adv7393fb_device(info); - - switch (blank) { - - case VESA_NO_BLANKING: - /* Turn on panel */ - adv7393_mode(fbdev->client, BLANK_OFF); - break; - - case VESA_VSYNC_SUSPEND: - case VESA_HSYNC_SUSPEND: - case VESA_POWERDOWN: - /* Turn off panel */ - adv7393_mode(fbdev->client, BLANK_ON); - break; - - default: - return -EINVAL; - break; - } - return 0; -} - -int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) -{ - if (nocursor) - return 0; - else - return -EINVAL; /* just to force soft_cursor() call */ -} - -static int bfin_adv7393_fb_setcolreg(u_int regno, u_int red, u_int green, - u_int blue, u_int transp, - struct fb_info *info) -{ - if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES) - return -EINVAL; - - if (info->var.grayscale) - /* grayscale = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; - - if (info->fix.visual == FB_VISUAL_TRUECOLOR) { - u32 value; - /* Place color in the pseudopalette */ - if (regno > 16) - return -EINVAL; - - red >>= (16 - info->var.red.length); - green >>= (16 - info->var.green.length); - blue >>= (16 - info->var.blue.length); - - value = (red << info->var.red.offset) | - (green << info->var.green.offset)| - (blue << info->var.blue.offset); - value &= 0xFFFF; - - ((u32 *) (info->pseudo_palette))[regno] = value; - } - - return 0; -} - -static int bfin_adv7393_fb_remove(struct i2c_client *client) -{ - struct adv7393fb_device *fbdev = i2c_get_clientdata(client); - - adv7393_mode(client, POWER_DOWN); - - if (fbdev->fb_mem) - dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem, fbdev->dma_handle); - free_dma(CH_PPI); - free_irq(IRQ_PPI_ERROR, fbdev); - unregister_framebuffer(&fbdev->info); - remove_proc_entry("driver/adv7393", NULL); - fb_dealloc_cmap(&fbdev->info.cmap); - kfree(fbdev->info.pseudo_palette); - - if (ANOMALY_05000400) - gpio_free(P_IDENT(P_PPI0_FS3)); /* FS3 */ - peripheral_free_list(ppi_pins); - kfree(fbdev); - - return 0; -} - -#ifdef CONFIG_PM -static int bfin_adv7393_fb_suspend(struct device *dev) -{ - struct adv7393fb_device *fbdev = dev_get_drvdata(dev); - - if (fbdev->open) { - bfin_disable_dma(); - bfin_disable_ppi(); - dma_desc_list(fbdev, DESTRUCT); - } - adv7393_mode(fbdev->client, POWER_DOWN); - - return 0; -} - -static int bfin_adv7393_fb_resume(struct device *dev) -{ - struct adv7393fb_device *fbdev = dev_get_drvdata(dev); - - adv7393_mode(fbdev->client, POWER_ON); - - if (fbdev->open) { - dma_desc_list(fbdev, BUILD); - bfin_config_ppi(fbdev); - bfin_config_dma(fbdev); - bfin_enable_ppi(); - } - - return 0; -} - -static const struct dev_pm_ops bfin_adv7393_dev_pm_ops = { - .suspend = bfin_adv7393_fb_suspend, - .resume = bfin_adv7393_fb_resume, -}; -#endif - -static const struct i2c_device_id bfin_adv7393_id[] = { - {DRIVER_NAME, 0}, - {} -}; - -MODULE_DEVICE_TABLE(i2c, bfin_adv7393_id); - -static struct i2c_driver bfin_adv7393_fb_driver = { - .driver = { - .name = DRIVER_NAME, -#ifdef CONFIG_PM - .pm = &bfin_adv7393_dev_pm_ops, -#endif - }, - .probe = bfin_adv7393_fb_probe, - .remove = bfin_adv7393_fb_remove, - .id_table = bfin_adv7393_id, -}; - -static int __init bfin_adv7393_fb_driver_init(void) -{ -#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) - request_module("i2c-bfin-twi"); -#else - request_module("i2c-gpio"); -#endif - - return i2c_add_driver(&bfin_adv7393_fb_driver); -} -module_init(bfin_adv7393_fb_driver_init); - -static void __exit bfin_adv7393_fb_driver_cleanup(void) -{ - i2c_del_driver(&bfin_adv7393_fb_driver); -} -module_exit(bfin_adv7393_fb_driver_cleanup); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("Frame buffer driver for ADV7393/2 Video Encoder"); - -module_param(mode, int, 0); -MODULE_PARM_DESC(mode, - "Video Mode (0=NTSC,1=PAL,2=NTSC 640x480,3=PAL 640x480,4=NTSC YCbCr input,5=PAL YCbCr input)"); - -module_param(mem, int, 0); -MODULE_PARM_DESC(mem, - "Size of frame buffer memory 1=Single 2=Double Size (allows y-panning / frame stacking)"); - -module_param(nocursor, int, 0644); -MODULE_PARM_DESC(nocursor, "cursor enable/disable"); diff --git a/drivers/video/fbdev/bfin_adv7393fb.h b/drivers/video/fbdev/bfin_adv7393fb.h deleted file mode 100644 index afd0380e19e1..000000000000 --- a/drivers/video/fbdev/bfin_adv7393fb.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Frame buffer driver for ADV7393/2 video encoder - * - * Copyright 2006-2009 Analog Devices Inc. - * Licensed under the GPL-2 or late. - */ - -#ifndef __BFIN_ADV7393FB_H__ -#define __BFIN_ADV7393FB_H__ - -#define BFIN_LCD_NBR_PALETTE_ENTRIES 256 - -#ifdef CONFIG_NTSC -# define VMODE 0 -#endif -#ifdef CONFIG_PAL -# define VMODE 1 -#endif -#ifdef CONFIG_NTSC_640x480 -# define VMODE 2 -#endif -#ifdef CONFIG_PAL_640x480 -# define VMODE 3 -#endif -#ifdef CONFIG_NTSC_YCBCR -# define VMODE 4 -#endif -#ifdef CONFIG_PAL_YCBCR -# define VMODE 5 -#endif - -#ifndef VMODE -# define VMODE 1 -#endif - -#ifdef CONFIG_ADV7393_2XMEM -# define VMEM 2 -#else -# define VMEM 1 -#endif - -#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534) -# define DMA_CFG_VAL 0x7935 /* Set Sync Bit */ -# define VB_DUMMY_MEMORY_SOURCE L1_DATA_B_START -#else -# define DMA_CFG_VAL 0x7915 -# define VB_DUMMY_MEMORY_SOURCE BOOT_ROM_START -#endif - -enum { - DESTRUCT, - BUILD, -}; - -enum { - POWER_ON, - POWER_DOWN, - BLANK_ON, - BLANK_OFF, -}; - -struct adv7393fb_modes { - const s8 name[25]; /* Full name */ - u16 xres; /* Active Horizonzal Pixels */ - u16 yres; /* Active Vertical Pixels */ - u16 bpp; - u16 vmode; - u16 a_lines; /* Active Lines per Field */ - u16 vb1_lines; /* Vertical Blanking Field 1 Lines */ - u16 vb2_lines; /* Vertical Blanking Field 2 Lines */ - u16 tot_lines; /* Total Lines per Frame */ - u16 boeft_blank; /* Before Odd/Even Field Transition No. of Blank Pixels */ - u16 aoeft_blank; /* After Odd/Even Field Transition No. of Blank Pixels */ - const s8 *adv7393_i2c_initd; - u16 adv7393_i2c_initd_len; -}; - -static const u8 init_NTSC_TESTPATTERN[] = { - 0x00, 0x1E, /* Power up all DACs and PLL */ - 0x01, 0x00, /* SD-Only Mode */ - 0x80, 0x10, /* SSAF Luma Filter Enabled, NTSC Mode */ - 0x82, 0xCB, /* Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS/YC output */ - 0x84, 0x40, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */ -}; - -static const u8 init_NTSC[] = { - 0x00, 0x1E, /* Power up all DACs and PLL */ - 0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */ - 0x8C, 0x1F, /* NTSC Subcarrier Frequency */ - 0x8D, 0x7C, /* NTSC Subcarrier Frequency */ - 0x8E, 0xF0, /* NTSC Subcarrier Frequency */ - 0x8F, 0x21, /* NTSC Subcarrier Frequency */ - 0x01, 0x00, /* SD-Only Mode */ - 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */ - 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */ - 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */ - 0x86, 0x82, - 0x8B, 0x11, - 0x88, 0x20, - 0x8A, 0x0d, -}; - -static const u8 init_PAL[] = { - 0x00, 0x1E, /* Power up all DACs and PLL */ - 0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */ - 0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */ - 0x8C, 0xCB, /* PAL Subcarrier Frequency */ - 0x8D, 0x8A, /* PAL Subcarrier Frequency */ - 0x8E, 0x09, /* PAL Subcarrier Frequency */ - 0x8F, 0x2A, /* PAL Subcarrier Frequency */ - 0x01, 0x00, /* SD-Only Mode */ - 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */ - 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */ - 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */ - 0x86, 0x82, - 0x8B, 0x11, - 0x88, 0x20, - 0x8A, 0x0d, -}; - -static const u8 init_NTSC_YCbCr[] = { - 0x00, 0x1E, /* Power up all DACs and PLL */ - 0x8C, 0x1F, /* NTSC Subcarrier Frequency */ - 0x8D, 0x7C, /* NTSC Subcarrier Frequency */ - 0x8E, 0xF0, /* NTSC Subcarrier Frequency */ - 0x8F, 0x21, /* NTSC Subcarrier Frequency */ - 0x01, 0x00, /* SD-Only Mode */ - 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */ - 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */ - 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */ - 0x86, 0x82, - 0x8B, 0x11, - 0x88, 0x08, - 0x8A, 0x0d, -}; - -static const u8 init_PAL_YCbCr[] = { - 0x00, 0x1E, /* Power up all DACs and PLL */ - 0x8C, 0xCB, /* PAL Subcarrier Frequency */ - 0x8D, 0x8A, /* PAL Subcarrier Frequency */ - 0x8E, 0x09, /* PAL Subcarrier Frequency */ - 0x8F, 0x2A, /* PAL Subcarrier Frequency */ - 0x01, 0x00, /* SD-Only Mode */ - 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */ - 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */ - 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */ - 0x86, 0x82, - 0x8B, 0x11, - 0x88, 0x08, - 0x8A, 0x0d, -}; - -static struct adv7393fb_modes known_modes[] = { - /* NTSC 720x480 CRT */ - { - .name = "NTSC 720x480", - .xres = 720, - .yres = 480, - .bpp = 16, - .vmode = FB_VMODE_INTERLACED, - .a_lines = 240, - .vb1_lines = 22, - .vb2_lines = 23, - .tot_lines = 525, - .boeft_blank = 16, - .aoeft_blank = 122, - .adv7393_i2c_initd = init_NTSC, - .adv7393_i2c_initd_len = sizeof(init_NTSC) - }, - /* PAL 720x480 CRT */ - { - .name = "PAL 720x576", - .xres = 720, - .yres = 576, - .bpp = 16, - .vmode = FB_VMODE_INTERLACED, - .a_lines = 288, - .vb1_lines = 24, - .vb2_lines = 25, - .tot_lines = 625, - .boeft_blank = 12, - .aoeft_blank = 132, - .adv7393_i2c_initd = init_PAL, - .adv7393_i2c_initd_len = sizeof(init_PAL) - }, - /* NTSC 640x480 CRT Experimental */ - { - .name = "NTSC 640x480", - .xres = 640, - .yres = 480, - .bpp = 16, - .vmode = FB_VMODE_INTERLACED, - .a_lines = 240, - .vb1_lines = 22, - .vb2_lines = 23, - .tot_lines = 525, - .boeft_blank = 16 + 40, - .aoeft_blank = 122 + 40, - .adv7393_i2c_initd = init_NTSC, - .adv7393_i2c_initd_len = sizeof(init_NTSC) - }, - /* PAL 640x480 CRT Experimental */ - { - .name = "PAL 640x480", - .xres = 640, - .yres = 480, - .bpp = 16, - .vmode = FB_VMODE_INTERLACED, - .a_lines = 288 - 20, - .vb1_lines = 24 + 20, - .vb2_lines = 25 + 20, - .tot_lines = 625, - .boeft_blank = 12 + 40, - .aoeft_blank = 132 + 40, - .adv7393_i2c_initd = init_PAL, - .adv7393_i2c_initd_len = sizeof(init_PAL) - }, - /* NTSC 720x480 YCbCR */ - { - .name = "NTSC 720x480 YCbCR", - .xres = 720, - .yres = 480, - .bpp = 16, - .vmode = FB_VMODE_INTERLACED, - .a_lines = 240, - .vb1_lines = 22, - .vb2_lines = 23, - .tot_lines = 525, - .boeft_blank = 16, - .aoeft_blank = 122, - .adv7393_i2c_initd = init_NTSC_YCbCr, - .adv7393_i2c_initd_len = sizeof(init_NTSC_YCbCr) - }, - /* PAL 720x480 CRT */ - { - .name = "PAL 720x576 YCbCR", - .xres = 720, - .yres = 576, - .bpp = 16, - .vmode = FB_VMODE_INTERLACED, - .a_lines = 288, - .vb1_lines = 24, - .vb2_lines = 25, - .tot_lines = 625, - .boeft_blank = 12, - .aoeft_blank = 132, - .adv7393_i2c_initd = init_PAL_YCbCr, - .adv7393_i2c_initd_len = sizeof(init_PAL_YCbCr) - } -}; - -struct adv7393fb_regs { - -}; - -struct adv7393fb_device { - struct fb_info info; /* FB driver info record */ - - struct i2c_client *client; - - struct dmasg *descriptor_list_head; - struct dmasg *vb1; - struct dmasg *av1; - struct dmasg *vb2; - struct dmasg *av2; - - dma_addr_t dma_handle; - - struct fb_info bfin_adv7393_fb; - - struct adv7393fb_modes *modes; - - struct adv7393fb_regs *regs; /* Registers memory map */ - size_t regs_len; - size_t fb_len; - size_t line_len; - u16 open; - u16 *fb_mem; /* RGB Buffer */ - -}; - -#define to_adv7393fb_device(_info) \ - (_info ? container_of(_info, struct adv7393fb_device, info) : NULL); - -static int bfin_adv7393_fb_open(struct fb_info *info, int user); -static int bfin_adv7393_fb_release(struct fb_info *info, int user); -static int bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info); - -static int bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info); - -static int bfin_adv7393_fb_blank(int blank, struct fb_info *info); - -static void bfin_config_ppi(struct adv7393fb_device *fbdev); -static int bfin_config_dma(struct adv7393fb_device *fbdev); -static void bfin_disable_dma(void); -static void bfin_enable_ppi(void); -static void bfin_disable_ppi(void); - -static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value); -static inline int adv7393_read(struct i2c_client *client, u8 reg); -static int adv7393_write_block(struct i2c_client *client, const u8 *data, - unsigned int len); - -int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor); -static int bfin_adv7393_fb_setcolreg(u_int, u_int, u_int, u_int, - u_int, struct fb_info *info); - -#endif diff --git a/include/linux/fb.h b/include/linux/fb.h index f577d3c89618..aa74a228bb92 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -571,8 +571,7 @@ static inline struct apertures_struct *alloc_apertures(unsigned int max_num) { #elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || \ defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || \ - defined(__avr32__) || defined(__bfin__) || defined(__arm__) || \ - defined(__aarch64__) + defined(__arm__) || defined(__aarch64__) #define fb_readb __raw_readb #define fb_readw __raw_readw -- cgit v1.2.3 From f59b2dc2de63652cad750efc2ad1012eb1bb342f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 18:16:31 +0100 Subject: pinctrl: remove adi2/blackfin drivers The blackfin architecture is getting removed, so these are now obsolete. Acked-by: Aaron Wu Signed-off-by: Arnd Bergmann --- drivers/pinctrl/Kconfig | 19 - drivers/pinctrl/Makefile | 3 - drivers/pinctrl/pinctrl-adi2-bf54x.c | 588 --------------- drivers/pinctrl/pinctrl-adi2-bf60x.c | 517 ------------- drivers/pinctrl/pinctrl-adi2.c | 1114 ---------------------------- drivers/pinctrl/pinctrl-adi2.h | 75 -- include/linux/platform_data/pinctrl-adi2.h | 40 - 7 files changed, 2356 deletions(-) delete mode 100644 drivers/pinctrl/pinctrl-adi2-bf54x.c delete mode 100644 drivers/pinctrl/pinctrl-adi2-bf60x.c delete mode 100644 drivers/pinctrl/pinctrl-adi2.c delete mode 100644 drivers/pinctrl/pinctrl-adi2.h delete mode 100644 include/linux/platform_data/pinctrl-adi2.h (limited to 'include/linux') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0f254b35c378..008073570a38 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -30,17 +30,6 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. -config PINCTRL_ADI2 - bool "ADI pin controller driver" - depends on (BF54x || BF60x) - depends on !GPIO_ADI - select PINMUX - select IRQ_DOMAIN - help - This is the pin controller and gpio driver for ADI BF54x, BF60x and - future processors. This option is selected automatically when specific - machine and arch are selected to build. - config PINCTRL_ARTPEC6 bool "Axis ARTPEC-6 pin controller driver" depends on MACH_ARTPEC6 @@ -77,14 +66,6 @@ config PINCTRL_AXP209 selected. Say yes to enable pinctrl and GPIO support for the AXP209 PMIC -config PINCTRL_BF54x - def_bool y if BF54x - select PINCTRL_ADI2 - -config PINCTRL_BF60x - def_bool y if BF60x - select PINCTRL_ADI2 - config PINCTRL_AT91 bool "AT91 pinctrl driver" depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d3692633e9ed..92a40bdb6273 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -8,12 +8,9 @@ obj-$(CONFIG_PINMUX) += pinmux.o obj-$(CONFIG_PINCONF) += pinconf.o obj-$(CONFIG_OF) += devicetree.o obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o -obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o -obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o -obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c deleted file mode 100644 index 008a29e92e56..000000000000 --- a/drivers/pinctrl/pinctrl-adi2-bf54x.c +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#include -#include "pinctrl-adi2.h" - -static const struct pinctrl_pin_desc adi_pads[] = { - PINCTRL_PIN(0, "PA0"), - PINCTRL_PIN(1, "PA1"), - PINCTRL_PIN(2, "PA2"), - PINCTRL_PIN(3, "PG3"), - PINCTRL_PIN(4, "PA4"), - PINCTRL_PIN(5, "PA5"), - PINCTRL_PIN(6, "PA6"), - PINCTRL_PIN(7, "PA7"), - PINCTRL_PIN(8, "PA8"), - PINCTRL_PIN(9, "PA9"), - PINCTRL_PIN(10, "PA10"), - PINCTRL_PIN(11, "PA11"), - PINCTRL_PIN(12, "PA12"), - PINCTRL_PIN(13, "PA13"), - PINCTRL_PIN(14, "PA14"), - PINCTRL_PIN(15, "PA15"), - PINCTRL_PIN(16, "PB0"), - PINCTRL_PIN(17, "PB1"), - PINCTRL_PIN(18, "PB2"), - PINCTRL_PIN(19, "PB3"), - PINCTRL_PIN(20, "PB4"), - PINCTRL_PIN(21, "PB5"), - PINCTRL_PIN(22, "PB6"), - PINCTRL_PIN(23, "PB7"), - PINCTRL_PIN(24, "PB8"), - PINCTRL_PIN(25, "PB9"), - PINCTRL_PIN(26, "PB10"), - PINCTRL_PIN(27, "PB11"), - PINCTRL_PIN(28, "PB12"), - PINCTRL_PIN(29, "PB13"), - PINCTRL_PIN(30, "PB14"), - PINCTRL_PIN(32, "PC0"), - PINCTRL_PIN(33, "PC1"), - PINCTRL_PIN(34, "PC2"), - PINCTRL_PIN(35, "PC3"), - PINCTRL_PIN(36, "PC4"), - PINCTRL_PIN(37, "PC5"), - PINCTRL_PIN(38, "PC6"), - PINCTRL_PIN(39, "PC7"), - PINCTRL_PIN(40, "PC8"), - PINCTRL_PIN(41, "PC9"), - PINCTRL_PIN(42, "PC10"), - PINCTRL_PIN(43, "PC11"), - PINCTRL_PIN(44, "PC12"), - PINCTRL_PIN(45, "PC13"), - PINCTRL_PIN(48, "PD0"), - PINCTRL_PIN(49, "PD1"), - PINCTRL_PIN(50, "PD2"), - PINCTRL_PIN(51, "PD3"), - PINCTRL_PIN(52, "PD4"), - PINCTRL_PIN(53, "PD5"), - PINCTRL_PIN(54, "PD6"), - PINCTRL_PIN(55, "PD7"), - PINCTRL_PIN(56, "PD8"), - PINCTRL_PIN(57, "PD9"), - PINCTRL_PIN(58, "PD10"), - PINCTRL_PIN(59, "PD11"), - PINCTRL_PIN(60, "PD12"), - PINCTRL_PIN(61, "PD13"), - PINCTRL_PIN(62, "PD14"), - PINCTRL_PIN(63, "PD15"), - PINCTRL_PIN(64, "PE0"), - PINCTRL_PIN(65, "PE1"), - PINCTRL_PIN(66, "PE2"), - PINCTRL_PIN(67, "PE3"), - PINCTRL_PIN(68, "PE4"), - PINCTRL_PIN(69, "PE5"), - PINCTRL_PIN(70, "PE6"), - PINCTRL_PIN(71, "PE7"), - PINCTRL_PIN(72, "PE8"), - PINCTRL_PIN(73, "PE9"), - PINCTRL_PIN(74, "PE10"), - PINCTRL_PIN(75, "PE11"), - PINCTRL_PIN(76, "PE12"), - PINCTRL_PIN(77, "PE13"), - PINCTRL_PIN(78, "PE14"), - PINCTRL_PIN(79, "PE15"), - PINCTRL_PIN(80, "PF0"), - PINCTRL_PIN(81, "PF1"), - PINCTRL_PIN(82, "PF2"), - PINCTRL_PIN(83, "PF3"), - PINCTRL_PIN(84, "PF4"), - PINCTRL_PIN(85, "PF5"), - PINCTRL_PIN(86, "PF6"), - PINCTRL_PIN(87, "PF7"), - PINCTRL_PIN(88, "PF8"), - PINCTRL_PIN(89, "PF9"), - PINCTRL_PIN(90, "PF10"), - PINCTRL_PIN(91, "PF11"), - PINCTRL_PIN(92, "PF12"), - PINCTRL_PIN(93, "PF13"), - PINCTRL_PIN(94, "PF14"), - PINCTRL_PIN(95, "PF15"), - PINCTRL_PIN(96, "PG0"), - PINCTRL_PIN(97, "PG1"), - PINCTRL_PIN(98, "PG2"), - PINCTRL_PIN(99, "PG3"), - PINCTRL_PIN(100, "PG4"), - PINCTRL_PIN(101, "PG5"), - PINCTRL_PIN(102, "PG6"), - PINCTRL_PIN(103, "PG7"), - PINCTRL_PIN(104, "PG8"), - PINCTRL_PIN(105, "PG9"), - PINCTRL_PIN(106, "PG10"), - PINCTRL_PIN(107, "PG11"), - PINCTRL_PIN(108, "PG12"), - PINCTRL_PIN(109, "PG13"), - PINCTRL_PIN(110, "PG14"), - PINCTRL_PIN(111, "PG15"), - PINCTRL_PIN(112, "PH0"), - PINCTRL_PIN(113, "PH1"), - PINCTRL_PIN(114, "PH2"), - PINCTRL_PIN(115, "PH3"), - PINCTRL_PIN(116, "PH4"), - PINCTRL_PIN(117, "PH5"), - PINCTRL_PIN(118, "PH6"), - PINCTRL_PIN(119, "PH7"), - PINCTRL_PIN(120, "PH8"), - PINCTRL_PIN(121, "PH9"), - PINCTRL_PIN(122, "PH10"), - PINCTRL_PIN(123, "PH11"), - PINCTRL_PIN(124, "PH12"), - PINCTRL_PIN(125, "PH13"), - PINCTRL_PIN(128, "PI0"), - PINCTRL_PIN(129, "PI1"), - PINCTRL_PIN(130, "PI2"), - PINCTRL_PIN(131, "PI3"), - PINCTRL_PIN(132, "PI4"), - PINCTRL_PIN(133, "PI5"), - PINCTRL_PIN(134, "PI6"), - PINCTRL_PIN(135, "PI7"), - PINCTRL_PIN(136, "PI8"), - PINCTRL_PIN(137, "PI9"), - PINCTRL_PIN(138, "PI10"), - PINCTRL_PIN(139, "PI11"), - PINCTRL_PIN(140, "PI12"), - PINCTRL_PIN(141, "PI13"), - PINCTRL_PIN(142, "PI14"), - PINCTRL_PIN(143, "PI15"), - PINCTRL_PIN(144, "PJ0"), - PINCTRL_PIN(145, "PJ1"), - PINCTRL_PIN(146, "PJ2"), - PINCTRL_PIN(147, "PJ3"), - PINCTRL_PIN(148, "PJ4"), - PINCTRL_PIN(149, "PJ5"), - PINCTRL_PIN(150, "PJ6"), - PINCTRL_PIN(151, "PJ7"), - PINCTRL_PIN(152, "PJ8"), - PINCTRL_PIN(153, "PJ9"), - PINCTRL_PIN(154, "PJ10"), - PINCTRL_PIN(155, "PJ11"), - PINCTRL_PIN(156, "PJ12"), - PINCTRL_PIN(157, "PJ13"), -}; - -static const unsigned uart0_pins[] = { - GPIO_PE7, GPIO_PE8, -}; - -static const unsigned uart1_pins[] = { - GPIO_PH0, GPIO_PH1, -}; - -static const unsigned uart1_ctsrts_pins[] = { - GPIO_PE9, GPIO_PE10, -}; - -static const unsigned uart2_pins[] = { - GPIO_PB4, GPIO_PB5, -}; - -static const unsigned uart3_pins[] = { - GPIO_PB6, GPIO_PB7, -}; - -static const unsigned uart3_ctsrts_pins[] = { - GPIO_PB2, GPIO_PB3, -}; - -static const unsigned rsi0_pins[] = { - GPIO_PC8, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, GPIO_PC13, -}; - -static const unsigned spi0_pins[] = { - GPIO_PE0, GPIO_PE1, GPIO_PE2, -}; - -static const unsigned spi1_pins[] = { - GPIO_PG8, GPIO_PG9, GPIO_PG10, -}; - -static const unsigned twi0_pins[] = { - GPIO_PE14, GPIO_PE15, -}; - -static const unsigned twi1_pins[] = { - GPIO_PB0, GPIO_PB1, -}; - -static const unsigned rotary_pins[] = { - GPIO_PH4, GPIO_PH3, GPIO_PH5, -}; - -static const unsigned can0_pins[] = { - GPIO_PG13, GPIO_PG12, -}; - -static const unsigned can1_pins[] = { - GPIO_PG14, GPIO_PG15, -}; - -static const unsigned smc0_pins[] = { - GPIO_PH8, GPIO_PH9, GPIO_PH10, GPIO_PH11, GPIO_PH12, GPIO_PH13, - GPIO_PI0, GPIO_PI1, GPIO_PI2, GPIO_PI3, GPIO_PI4, GPIO_PI5, GPIO_PI6, - GPIO_PI7, GPIO_PI8, GPIO_PI9, GPIO_PI10, GPIO_PI11, - GPIO_PI12, GPIO_PI13, GPIO_PI14, GPIO_PI15, -}; - -static const unsigned sport0_pins[] = { - GPIO_PC0, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC6, GPIO_PC7, -}; - -static const unsigned sport1_pins[] = { - GPIO_PD0, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD6, GPIO_PD7, -}; - -static const unsigned sport2_pins[] = { - GPIO_PA0, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA6, GPIO_PA7, -}; - -static const unsigned sport3_pins[] = { - GPIO_PA8, GPIO_PA10, GPIO_PA11, GPIO_PA12, GPIO_PA14, GPIO_PA15, -}; - -static const unsigned ppi0_8b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF13, GPIO_PG0, GPIO_PG1, GPIO_PG2, -}; - -static const unsigned ppi0_16b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, - GPIO_PG0, GPIO_PG1, GPIO_PG2, -}; - -static const unsigned ppi0_24b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PD0, GPIO_PD1, GPIO_PD2, - GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PG3, GPIO_PG4, - GPIO_PG0, GPIO_PG1, GPIO_PG2, -}; - -static const unsigned ppi1_8b_pins[] = { - GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6, - GPIO_PD7, GPIO_PE11, GPIO_PE12, GPIO_PE13, -}; - -static const unsigned ppi1_16b_pins[] = { - GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6, - GPIO_PD7, GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12, - GPIO_PD13, GPIO_PD14, GPIO_PD15, - GPIO_PE11, GPIO_PE12, GPIO_PE13, -}; - -static const unsigned ppi2_8b_pins[] = { - GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12, - GPIO_PD13, GPIO_PD14, GPIO_PD15, - GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3, -}; - -static const unsigned atapi_pins[] = { - GPIO_PH2, GPIO_PJ3, GPIO_PJ4, GPIO_PJ5, GPIO_PJ6, - GPIO_PJ7, GPIO_PJ8, GPIO_PJ9, GPIO_PJ10, -}; - -static const unsigned atapi_alter_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PG2, GPIO_PG3, GPIO_PG4, -}; - -static const unsigned nfc0_pins[] = { - GPIO_PJ1, GPIO_PJ2, -}; - -static const unsigned keys_4x4_pins[] = { - GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, - GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15, -}; - -static const unsigned keys_8x8_pins[] = { - GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, - GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15, - GPIO_PE0, GPIO_PE1, GPIO_PE2, GPIO_PE3, - GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, -}; - -static const unsigned short uart0_mux[] = { - P_UART0_TX, P_UART0_RX, - 0 -}; - -static const unsigned short uart1_mux[] = { - P_UART1_TX, P_UART1_RX, - 0 -}; - -static const unsigned short uart1_ctsrts_mux[] = { - P_UART1_RTS, P_UART1_CTS, - 0 -}; - -static const unsigned short uart2_mux[] = { - P_UART2_TX, P_UART2_RX, - 0 -}; - -static const unsigned short uart3_mux[] = { - P_UART3_TX, P_UART3_RX, - 0 -}; - -static const unsigned short uart3_ctsrts_mux[] = { - P_UART3_RTS, P_UART3_CTS, - 0 -}; - -static const unsigned short rsi0_mux[] = { - P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, - 0 -}; - -static const unsigned short spi0_mux[] = { - P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0 -}; - -static const unsigned short spi1_mux[] = { - P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0 -}; - -static const unsigned short twi0_mux[] = { - P_TWI0_SCL, P_TWI0_SDA, 0 -}; - -static const unsigned short twi1_mux[] = { - P_TWI1_SCL, P_TWI1_SDA, 0 -}; - -static const unsigned short rotary_mux[] = { - P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0 -}; - -static const unsigned short sport0_mux[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static const unsigned short sport1_mux[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static const unsigned short sport2_mux[] = { - P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, - P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0 -}; - -static const unsigned short sport3_mux[] = { - P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, - P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0 -}; - -static const unsigned short can0_mux[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static const unsigned short can1_mux[] = { - P_CAN1_RX, P_CAN1_TX, 0 -}; - -static const unsigned short smc0_mux[] = { - P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, - P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, - P_A22, P_A23, P_A24, P_A25, P_NOR_CLK, 0, -}; - -static const unsigned short ppi0_8b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_16b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_24b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, - P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi1_8b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi1_16b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11, - P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi2_8b_mux[] = { - P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, - P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, - P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, - 0, -}; - -static const unsigned short atapi_mux[] = { - P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1, - P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY, -}; - -static const unsigned short atapi_alter_mux[] = { - P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A, - P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, - P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A, - P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, - 0 -}; - -static const unsigned short nfc0_mux[] = { - P_NAND_CE, P_NAND_RB, - 0 -}; - -static const unsigned short keys_4x4_mux[] = { - P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0, - P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0, - 0 -}; - -static const unsigned short keys_8x8_mux[] = { - P_KEY_ROW7, P_KEY_ROW6, P_KEY_ROW5, P_KEY_ROW4, - P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0, - P_KEY_COL7, P_KEY_COL6, P_KEY_COL5, P_KEY_COL4, - P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0, - 0 -}; - -static const struct adi_pin_group adi_pin_groups[] = { - ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), - ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), - ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), - ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux), - ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux), - ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux), - ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), - ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), - ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), - ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), - ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), - ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), - ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), - ADI_PIN_GROUP("can1grp", can1_pins, can1_mux), - ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), - ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), - ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), - ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), - ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux), - ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), - ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), - ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), - ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), - ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), - ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), - ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux), - ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux), - ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux), - ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux), - ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux), -}; - -static const char * const uart0grp[] = { "uart0grp" }; -static const char * const uart1grp[] = { "uart1grp" }; -static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; -static const char * const uart2grp[] = { "uart2grp" }; -static const char * const uart3grp[] = { "uart3grp" }; -static const char * const uart3ctsrtsgrp[] = { "uart3ctsrtsgrp" }; -static const char * const rsi0grp[] = { "rsi0grp" }; -static const char * const spi0grp[] = { "spi0grp" }; -static const char * const spi1grp[] = { "spi1grp" }; -static const char * const twi0grp[] = { "twi0grp" }; -static const char * const twi1grp[] = { "twi1grp" }; -static const char * const rotarygrp[] = { "rotarygrp" }; -static const char * const can0grp[] = { "can0grp" }; -static const char * const can1grp[] = { "can1grp" }; -static const char * const smc0grp[] = { "smc0grp" }; -static const char * const sport0grp[] = { "sport0grp" }; -static const char * const sport1grp[] = { "sport1grp" }; -static const char * const sport2grp[] = { "sport2grp" }; -static const char * const sport3grp[] = { "sport3grp" }; -static const char * const ppi0grp[] = { "ppi0_8bgrp", - "ppi0_16bgrp", - "ppi0_24bgrp" }; -static const char * const ppi1grp[] = { "ppi1_8bgrp", - "ppi1_16bgrp" }; -static const char * const ppi2grp[] = { "ppi2_8bgrp" }; -static const char * const atapigrp[] = { "atapigrp" }; -static const char * const atapialtergrp[] = { "atapialtergrp" }; -static const char * const nfc0grp[] = { "nfc0grp" }; -static const char * const keysgrp[] = { "keys_4x4grp", - "keys_8x8grp" }; - -static const struct adi_pmx_func adi_pmx_functions[] = { - ADI_PMX_FUNCTION("uart0", uart0grp), - ADI_PMX_FUNCTION("uart1", uart1grp), - ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), - ADI_PMX_FUNCTION("uart2", uart2grp), - ADI_PMX_FUNCTION("uart3", uart3grp), - ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp), - ADI_PMX_FUNCTION("rsi0", rsi0grp), - ADI_PMX_FUNCTION("spi0", spi0grp), - ADI_PMX_FUNCTION("spi1", spi1grp), - ADI_PMX_FUNCTION("twi0", twi0grp), - ADI_PMX_FUNCTION("twi1", twi1grp), - ADI_PMX_FUNCTION("rotary", rotarygrp), - ADI_PMX_FUNCTION("can0", can0grp), - ADI_PMX_FUNCTION("can1", can1grp), - ADI_PMX_FUNCTION("smc0", smc0grp), - ADI_PMX_FUNCTION("sport0", sport0grp), - ADI_PMX_FUNCTION("sport1", sport1grp), - ADI_PMX_FUNCTION("sport2", sport2grp), - ADI_PMX_FUNCTION("sport3", sport3grp), - ADI_PMX_FUNCTION("ppi0", ppi0grp), - ADI_PMX_FUNCTION("ppi1", ppi1grp), - ADI_PMX_FUNCTION("ppi2", ppi2grp), - ADI_PMX_FUNCTION("atapi", atapigrp), - ADI_PMX_FUNCTION("atapi_alter", atapialtergrp), - ADI_PMX_FUNCTION("nfc0", nfc0grp), - ADI_PMX_FUNCTION("keys", keysgrp), -}; - -static const struct adi_pinctrl_soc_data adi_bf54x_soc = { - .functions = adi_pmx_functions, - .nfunctions = ARRAY_SIZE(adi_pmx_functions), - .groups = adi_pin_groups, - .ngroups = ARRAY_SIZE(adi_pin_groups), - .pins = adi_pads, - .npins = ARRAY_SIZE(adi_pads), -}; - -void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc) -{ - *soc = &adi_bf54x_soc; -} diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c deleted file mode 100644 index fcfa00821f12..000000000000 --- a/drivers/pinctrl/pinctrl-adi2-bf60x.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#include -#include "pinctrl-adi2.h" - -static const struct pinctrl_pin_desc adi_pads[] = { - PINCTRL_PIN(0, "PA0"), - PINCTRL_PIN(1, "PA1"), - PINCTRL_PIN(2, "PA2"), - PINCTRL_PIN(3, "PG3"), - PINCTRL_PIN(4, "PA4"), - PINCTRL_PIN(5, "PA5"), - PINCTRL_PIN(6, "PA6"), - PINCTRL_PIN(7, "PA7"), - PINCTRL_PIN(8, "PA8"), - PINCTRL_PIN(9, "PA9"), - PINCTRL_PIN(10, "PA10"), - PINCTRL_PIN(11, "PA11"), - PINCTRL_PIN(12, "PA12"), - PINCTRL_PIN(13, "PA13"), - PINCTRL_PIN(14, "PA14"), - PINCTRL_PIN(15, "PA15"), - PINCTRL_PIN(16, "PB0"), - PINCTRL_PIN(17, "PB1"), - PINCTRL_PIN(18, "PB2"), - PINCTRL_PIN(19, "PB3"), - PINCTRL_PIN(20, "PB4"), - PINCTRL_PIN(21, "PB5"), - PINCTRL_PIN(22, "PB6"), - PINCTRL_PIN(23, "PB7"), - PINCTRL_PIN(24, "PB8"), - PINCTRL_PIN(25, "PB9"), - PINCTRL_PIN(26, "PB10"), - PINCTRL_PIN(27, "PB11"), - PINCTRL_PIN(28, "PB12"), - PINCTRL_PIN(29, "PB13"), - PINCTRL_PIN(30, "PB14"), - PINCTRL_PIN(31, "PB15"), - PINCTRL_PIN(32, "PC0"), - PINCTRL_PIN(33, "PC1"), - PINCTRL_PIN(34, "PC2"), - PINCTRL_PIN(35, "PC3"), - PINCTRL_PIN(36, "PC4"), - PINCTRL_PIN(37, "PC5"), - PINCTRL_PIN(38, "PC6"), - PINCTRL_PIN(39, "PC7"), - PINCTRL_PIN(40, "PC8"), - PINCTRL_PIN(41, "PC9"), - PINCTRL_PIN(42, "PC10"), - PINCTRL_PIN(43, "PC11"), - PINCTRL_PIN(44, "PC12"), - PINCTRL_PIN(45, "PC13"), - PINCTRL_PIN(46, "PC14"), - PINCTRL_PIN(47, "PC15"), - PINCTRL_PIN(48, "PD0"), - PINCTRL_PIN(49, "PD1"), - PINCTRL_PIN(50, "PD2"), - PINCTRL_PIN(51, "PD3"), - PINCTRL_PIN(52, "PD4"), - PINCTRL_PIN(53, "PD5"), - PINCTRL_PIN(54, "PD6"), - PINCTRL_PIN(55, "PD7"), - PINCTRL_PIN(56, "PD8"), - PINCTRL_PIN(57, "PD9"), - PINCTRL_PIN(58, "PD10"), - PINCTRL_PIN(59, "PD11"), - PINCTRL_PIN(60, "PD12"), - PINCTRL_PIN(61, "PD13"), - PINCTRL_PIN(62, "PD14"), - PINCTRL_PIN(63, "PD15"), - PINCTRL_PIN(64, "PE0"), - PINCTRL_PIN(65, "PE1"), - PINCTRL_PIN(66, "PE2"), - PINCTRL_PIN(67, "PE3"), - PINCTRL_PIN(68, "PE4"), - PINCTRL_PIN(69, "PE5"), - PINCTRL_PIN(70, "PE6"), - PINCTRL_PIN(71, "PE7"), - PINCTRL_PIN(72, "PE8"), - PINCTRL_PIN(73, "PE9"), - PINCTRL_PIN(74, "PE10"), - PINCTRL_PIN(75, "PE11"), - PINCTRL_PIN(76, "PE12"), - PINCTRL_PIN(77, "PE13"), - PINCTRL_PIN(78, "PE14"), - PINCTRL_PIN(79, "PE15"), - PINCTRL_PIN(80, "PF0"), - PINCTRL_PIN(81, "PF1"), - PINCTRL_PIN(82, "PF2"), - PINCTRL_PIN(83, "PF3"), - PINCTRL_PIN(84, "PF4"), - PINCTRL_PIN(85, "PF5"), - PINCTRL_PIN(86, "PF6"), - PINCTRL_PIN(87, "PF7"), - PINCTRL_PIN(88, "PF8"), - PINCTRL_PIN(89, "PF9"), - PINCTRL_PIN(90, "PF10"), - PINCTRL_PIN(91, "PF11"), - PINCTRL_PIN(92, "PF12"), - PINCTRL_PIN(93, "PF13"), - PINCTRL_PIN(94, "PF14"), - PINCTRL_PIN(95, "PF15"), - PINCTRL_PIN(96, "PG0"), - PINCTRL_PIN(97, "PG1"), - PINCTRL_PIN(98, "PG2"), - PINCTRL_PIN(99, "PG3"), - PINCTRL_PIN(100, "PG4"), - PINCTRL_PIN(101, "PG5"), - PINCTRL_PIN(102, "PG6"), - PINCTRL_PIN(103, "PG7"), - PINCTRL_PIN(104, "PG8"), - PINCTRL_PIN(105, "PG9"), - PINCTRL_PIN(106, "PG10"), - PINCTRL_PIN(107, "PG11"), - PINCTRL_PIN(108, "PG12"), - PINCTRL_PIN(109, "PG13"), - PINCTRL_PIN(110, "PG14"), - PINCTRL_PIN(111, "PG15"), -}; - -static const unsigned uart0_pins[] = { - GPIO_PD7, GPIO_PD8, -}; - -static const unsigned uart0_ctsrts_pins[] = { - GPIO_PD9, GPIO_PD10, -}; - -static const unsigned uart1_pins[] = { - GPIO_PG15, GPIO_PG14, -}; - -static const unsigned uart1_ctsrts_pins[] = { - GPIO_PG10, GPIO_PG13, -}; - -static const unsigned rsi0_pins[] = { - GPIO_PG3, GPIO_PG2, GPIO_PG0, GPIO_PE15, GPIO_PG5, GPIO_PG6, -}; - -static const unsigned eth0_pins[] = { - GPIO_PC6, GPIO_PC7, GPIO_PC2, GPIO_PC0, GPIO_PC3, GPIO_PC1, - GPIO_PB13, GPIO_PD6, GPIO_PC5, GPIO_PC4, GPIO_PB14, GPIO_PB15, -}; - -static const unsigned eth1_pins[] = { - GPIO_PE10, GPIO_PE11, GPIO_PG3, GPIO_PG0, GPIO_PG2, GPIO_PE15, - GPIO_PG5, GPIO_PE12, GPIO_PE13, GPIO_PE14, GPIO_PG6, GPIO_PC9, -}; - -static const unsigned spi0_pins[] = { - GPIO_PD4, GPIO_PD2, GPIO_PD3, -}; - -static const unsigned spi1_pins[] = { - GPIO_PD5, GPIO_PD14, GPIO_PD13, -}; - -static const unsigned twi0_pins[] = { -}; - -static const unsigned twi1_pins[] = { -}; - -static const unsigned rotary_pins[] = { - GPIO_PG7, GPIO_PG11, GPIO_PG12, -}; - -static const unsigned can0_pins[] = { - GPIO_PG1, GPIO_PG4, -}; - -static const unsigned smc0_pins[] = { - GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, - GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PB2, GPIO_PA10, GPIO_PA11, - GPIO_PB3, GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB6, - GPIO_PB7, GPIO_PB8, GPIO_PB10, GPIO_PB11, GPIO_PB0, -}; - -static const unsigned sport0_pins[] = { - GPIO_PB5, GPIO_PB4, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB11, -}; - -static const unsigned sport1_pins[] = { - GPIO_PE2, GPIO_PE5, GPIO_PD15, GPIO_PE4, GPIO_PE3, GPIO_PE1, -}; - -static const unsigned sport2_pins[] = { - GPIO_PG4, GPIO_PG1, GPIO_PG9, GPIO_PG10, GPIO_PG7, GPIO_PB12, -}; - -static const unsigned ppi0_8b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF13, GPIO_PF14, GPIO_PF15, - GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9, -}; - -static const unsigned ppi0_16b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, - GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9, -}; - -static const unsigned ppi0_24b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PE0, GPIO_PE1, GPIO_PE2, - GPIO_PE3, GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, GPIO_PE8, - GPIO_PE9, GPIO_PD12, GPIO_PD15, -}; - -static const unsigned ppi1_8b_pins[] = { - GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6, - GPIO_PC7, GPIO_PC8, GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6, -}; - -static const unsigned ppi1_16b_pins[] = { - GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6, - GPIO_PC7, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, - GPIO_PC13, GPIO_PC14, GPIO_PC15, - GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6, -}; - -static const unsigned ppi2_8b_pins[] = { - GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, - GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3, -}; - -static const unsigned ppi2_16b_pins[] = { - GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, - GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, GPIO_PA12, - GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB0, GPIO_PB1, GPIO_PB2, -}; - -static const unsigned lp0_pins[] = { - GPIO_PB0, GPIO_PB1, GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, - GPIO_PA4, GPIO_PA5, GPIO_PA6, GPIO_PA7, -}; - -static const unsigned lp1_pins[] = { - GPIO_PB3, GPIO_PB2, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, - GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, -}; - -static const unsigned lp2_pins[] = { - GPIO_PE6, GPIO_PE7, GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, - GPIO_PF4, GPIO_PF5, GPIO_PF6, GPIO_PF7, -}; - -static const unsigned lp3_pins[] = { - GPIO_PE9, GPIO_PE8, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, - GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15, -}; - -static const unsigned short uart0_mux[] = { - P_UART0_TX, P_UART0_RX, - 0 -}; - -static const unsigned short uart0_ctsrts_mux[] = { - P_UART0_RTS, P_UART0_CTS, - 0 -}; - -static const unsigned short uart1_mux[] = { - P_UART1_TX, P_UART1_RX, - 0 -}; - -static const unsigned short uart1_ctsrts_mux[] = { - P_UART1_RTS, P_UART1_CTS, - 0 -}; - -static const unsigned short rsi0_mux[] = { - P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, - P_RSI_CMD, P_RSI_CLK, 0 -}; - -static const unsigned short eth0_mux[] = P_RMII0; -static const unsigned short eth1_mux[] = P_RMII1; - -static const unsigned short spi0_mux[] = { - P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0 -}; - -static const unsigned short spi1_mux[] = { - P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0 -}; - -static const unsigned short twi0_mux[] = { - P_TWI0_SCL, P_TWI0_SDA, 0 -}; - -static const unsigned short twi1_mux[] = { - P_TWI1_SCL, P_TWI1_SDA, 0 -}; - -static const unsigned short rotary_mux[] = { - P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0 -}; - -static const unsigned short sport0_mux[] = { - P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK, - P_SPORT0_BFS, P_SPORT0_BD0, 0, -}; - -static const unsigned short sport1_mux[] = { - P_SPORT1_ACLK, P_SPORT1_AFS, P_SPORT1_AD0, P_SPORT1_BCLK, - P_SPORT1_BFS, P_SPORT1_BD0, 0, -}; - -static const unsigned short sport2_mux[] = { - P_SPORT2_ACLK, P_SPORT2_AFS, P_SPORT2_AD0, P_SPORT2_BCLK, - P_SPORT2_BFS, P_SPORT2_BD0, 0, -}; - -static const unsigned short can0_mux[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static const unsigned short smc0_mux[] = { - P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, - P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, - P_A22, P_A23, P_A24, P_A25, P_NORCK, 0, -}; - -static const unsigned short ppi0_8b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_16b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_24b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, - P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi1_8b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi1_16b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11, - P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi2_8b_mux[] = { - P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, - P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, - P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, - 0, -}; - -static const unsigned short ppi2_16b_mux[] = { - P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, - P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, - P_PPI2_D8, P_PPI2_D9, P_PPI2_D10, P_PPI2_D11, - P_PPI2_D12, P_PPI2_D13, P_PPI2_D14, P_PPI2_D15, - P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, - 0, -}; - -static const unsigned short lp0_mux[] = { - P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2, - P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7, - 0 -}; - -static const unsigned short lp1_mux[] = { - P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2, - P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7, - 0 -}; - -static const unsigned short lp2_mux[] = { - P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2, - P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7, - 0 -}; - -static const unsigned short lp3_mux[] = { - P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2, - P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7, - 0 -}; - -static const struct adi_pin_group adi_pin_groups[] = { - ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), - ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins, uart0_ctsrts_mux), - ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), - ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), - ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), - ADI_PIN_GROUP("eth0grp", eth0_pins, eth0_mux), - ADI_PIN_GROUP("eth1grp", eth1_pins, eth1_mux), - ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), - ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), - ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), - ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), - ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), - ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), - ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), - ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), - ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), - ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), - ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), - ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), - ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), - ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), - ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), - ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), - ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins, ppi2_16b_mux), - ADI_PIN_GROUP("lp0grp", lp0_pins, lp0_mux), - ADI_PIN_GROUP("lp1grp", lp1_pins, lp1_mux), - ADI_PIN_GROUP("lp2grp", lp2_pins, lp2_mux), - ADI_PIN_GROUP("lp3grp", lp3_pins, lp3_mux), -}; - -static const char * const uart0grp[] = { "uart0grp" }; -static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" }; -static const char * const uart1grp[] = { "uart1grp" }; -static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; -static const char * const rsi0grp[] = { "rsi0grp" }; -static const char * const eth0grp[] = { "eth0grp" }; -static const char * const eth1grp[] = { "eth1grp" }; -static const char * const spi0grp[] = { "spi0grp" }; -static const char * const spi1grp[] = { "spi1grp" }; -static const char * const twi0grp[] = { "twi0grp" }; -static const char * const twi1grp[] = { "twi1grp" }; -static const char * const rotarygrp[] = { "rotarygrp" }; -static const char * const can0grp[] = { "can0grp" }; -static const char * const smc0grp[] = { "smc0grp" }; -static const char * const sport0grp[] = { "sport0grp" }; -static const char * const sport1grp[] = { "sport1grp" }; -static const char * const sport2grp[] = { "sport2grp" }; -static const char * const ppi0grp[] = { "ppi0_8bgrp", - "ppi0_16bgrp", - "ppi0_24bgrp" }; -static const char * const ppi1grp[] = { "ppi1_8bgrp", - "ppi1_16bgrp" }; -static const char * const ppi2grp[] = { "ppi2_8bgrp", - "ppi2_16bgrp" }; -static const char * const lp0grp[] = { "lp0grp" }; -static const char * const lp1grp[] = { "lp1grp" }; -static const char * const lp2grp[] = { "lp2grp" }; -static const char * const lp3grp[] = { "lp3grp" }; - -static const struct adi_pmx_func adi_pmx_functions[] = { - ADI_PMX_FUNCTION("uart0", uart0grp), - ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp), - ADI_PMX_FUNCTION("uart1", uart1grp), - ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), - ADI_PMX_FUNCTION("rsi0", rsi0grp), - ADI_PMX_FUNCTION("eth0", eth0grp), - ADI_PMX_FUNCTION("eth1", eth1grp), - ADI_PMX_FUNCTION("spi0", spi0grp), - ADI_PMX_FUNCTION("spi1", spi1grp), - ADI_PMX_FUNCTION("twi0", twi0grp), - ADI_PMX_FUNCTION("twi1", twi1grp), - ADI_PMX_FUNCTION("rotary", rotarygrp), - ADI_PMX_FUNCTION("can0", can0grp), - ADI_PMX_FUNCTION("smc0", smc0grp), - ADI_PMX_FUNCTION("sport0", sport0grp), - ADI_PMX_FUNCTION("sport1", sport1grp), - ADI_PMX_FUNCTION("sport2", sport2grp), - ADI_PMX_FUNCTION("ppi0", ppi0grp), - ADI_PMX_FUNCTION("ppi1", ppi1grp), - ADI_PMX_FUNCTION("ppi2", ppi2grp), - ADI_PMX_FUNCTION("lp0", lp0grp), - ADI_PMX_FUNCTION("lp1", lp1grp), - ADI_PMX_FUNCTION("lp2", lp2grp), - ADI_PMX_FUNCTION("lp3", lp3grp), -}; - -static const struct adi_pinctrl_soc_data adi_bf60x_soc = { - .functions = adi_pmx_functions, - .nfunctions = ARRAY_SIZE(adi_pmx_functions), - .groups = adi_pin_groups, - .ngroups = ARRAY_SIZE(adi_pin_groups), - .pins = adi_pads, - .npins = ARRAY_SIZE(adi_pads), -}; - -void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc) -{ - *soc = &adi_bf60x_soc; -} diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c deleted file mode 100644 index 094a451db2a2..000000000000 --- a/drivers/pinctrl/pinctrl-adi2.c +++ /dev/null @@ -1,1114 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "pinctrl-adi2.h" -#include "core.h" - -/* -According to the BF54x HRM, pint means "pin interrupt". -http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf - -ADSP-BF54x processor Blackfin processors have four SIC interrupt chan- -nels dedicated to pin interrupt purposes. These channels are managed by -four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx -block can sense to up to 32 pins. While PINT0 and PINT1 can sense the -pins of port A and port B, PINT2 and PINT3 manage all the pins from port -C to port J as shown in Figure 9-2. - -n BF54x HRM: -The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and -upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi- -plexers shown in Figure 9-3. Lower half units of eight pins can be -forwarded to either byte 0 or byte 2 of either associated PINTx block. -Upper half units can be forwarded to either byte 1 or byte 3 of the pin -interrupt blocks, without further restrictions. - -All MMR registers in the pin interrupt module are 32 bits wide. To simply the -mapping logic, this driver only maps a 16-bit gpio port to the upper or lower -16 bits of a PINTx block. You can find the Figure 9-3 on page 583. - -Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map -to one PINT device. Two in "struct gpio_pint" are used to ease the PINT -interrupt handler. - -The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ -domain pointer in domain[0]. The IRQ domain pointer of the other bank is set -to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out -the current domain pointer according to whether the interrupt request mask -is in lower 16 bits (domain[0]) or upper 16bits (domain[1]). - -A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO -port devices can be mapped to the same PINT device. - -*/ - -static LIST_HEAD(adi_pint_list); -static LIST_HEAD(adi_gpio_port_list); - -#define DRIVER_NAME "pinctrl-adi2" - -#define PINT_HI_OFFSET 16 - -/** - * struct gpio_port_saved - GPIO port registers that should be saved between - * power suspend and resume operations. - * - * @fer: PORTx_FER register - * @data: PORTx_DATA register - * @dir: PORTx_DIR register - * @inen: PORTx_INEN register - * @mux: PORTx_MUX register - */ -struct gpio_port_saved { - u16 fer; - u16 data; - u16 dir; - u16 inen; - u32 mux; -}; - -/* - * struct gpio_pint_saved - PINT registers saved in PM operations - * - * @assign: ASSIGN register - * @edge_set: EDGE_SET register - * @invert_set: INVERT_SET register - */ -struct gpio_pint_saved { - u32 assign; - u32 edge_set; - u32 invert_set; -}; - -/** - * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO - * banks can be mapped into one Pin interrupt controller. - * - * @node: All gpio_pint instances are added to a global list. - * @base: PINT device register base address - * @irq: IRQ of the PINT device, it is the parent IRQ of all - * GPIO IRQs mapping to this device. - * @domain: [0] irq domain of the gpio port, whose hardware interrupts are - * mapping to the low 16-bit of the pint registers. - * [1] irq domain of the gpio port, whose hardware interrupts are - * mapping to the high 16-bit of the pint registers. - * @regs: address pointer to the PINT device - * @map_count: No more than 2 GPIO banks can be mapped to this PINT device. - * @lock: This lock make sure the irq_chip operations to one PINT device - * for different GPIO interrrupts are atomic. - * @pint_map_port: Set up the mapping between one PINT device and - * multiple GPIO banks. - */ -struct gpio_pint { - struct list_head node; - void __iomem *base; - int irq; - struct irq_domain *domain[2]; - struct gpio_pint_regs *regs; - struct gpio_pint_saved saved_data; - int map_count; - spinlock_t lock; - - int (*pint_map_port)(struct gpio_pint *pint, bool assign, - u8 map, struct irq_domain *domain); -}; - -/** - * ADI pin controller - * - * @dev: a pointer back to containing device - * @pctl: the pinctrl device - * @soc: SoC data for this specific chip - */ -struct adi_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - const struct adi_pinctrl_soc_data *soc; -}; - -/** - * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped - * into one pin interrupt controller. - * - * @node: All gpio_port instances are added to a list. - * @base: GPIO bank device register base address - * @irq_base: base IRQ of the GPIO bank device - * @width: PIN number of the GPIO bank device - * @regs: address pointer to the GPIO bank device - * @saved_data: registers that should be saved between PM operations. - * @dev: device structure of this GPIO bank - * @pint: GPIO PINT device that this GPIO bank mapped to - * @pint_map: GIOP bank mapping code in PINT device - * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A - * GPIO bank can be mapped into either low 16 bits[0] or high 16 - * bits[1] of each PINT register. - * @lock: This lock make sure the irq_chip operations to one PINT device - * for different GPIO interrrupts are atomic. - * @chip: abstract a GPIO controller - * @domain: The irq domain owned by the GPIO port. - * @rsvmap: Reservation map array for each pin in the GPIO bank - */ -struct gpio_port { - struct list_head node; - void __iomem *base; - int irq_base; - unsigned int width; - struct gpio_port_t *regs; - struct gpio_port_saved saved_data; - struct device *dev; - - struct gpio_pint *pint; - u8 pint_map; - bool pint_assign; - - spinlock_t lock; - struct gpio_chip chip; - struct irq_domain *domain; -}; - -static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin) -{ - return pin - range->pin_base; -} - -static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq) -{ - return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq); -} - -static struct gpio_pint *find_gpio_pint(unsigned id) -{ - struct gpio_pint *pint; - int i = 0; - - list_for_each_entry(pint, &adi_pint_list, node) { - if (id == i) - return pint; - i++; - } - - return NULL; -} - -static inline void port_setup(struct gpio_port *port, unsigned offset, - bool use_for_gpio) -{ - struct gpio_port_t *regs = port->regs; - - if (use_for_gpio) - writew(readw(®s->port_fer) & ~BIT(offset), - ®s->port_fer); - else - writew(readw(®s->port_fer) | BIT(offset), ®s->port_fer); -} - -static inline void portmux_setup(struct gpio_port *port, unsigned offset, - unsigned short function) -{ - struct gpio_port_t *regs = port->regs; - u32 pmux; - - pmux = readl(®s->port_mux); - - /* The function field of each pin has 2 consecutive bits in - * the mux register. - */ - pmux &= ~(0x3 << (2 * offset)); - pmux |= (function & 0x3) << (2 * offset); - - writel(pmux, ®s->port_mux); -} - -static inline u16 get_portmux(struct gpio_port *port, unsigned offset) -{ - struct gpio_port_t *regs = port->regs; - u32 pmux = readl(®s->port_mux); - - /* The function field of each pin has 2 consecutive bits in - * the mux register. - */ - return pmux >> (2 * offset) & 0x3; -} - -static void adi_gpio_ack_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - unsigned pintbit = hwirq_to_pintbit(port, d->hwirq); - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { - if (readl(®s->invert_set) & pintbit) - writel(pintbit, ®s->invert_clear); - else - writel(pintbit, ®s->invert_set); - } - - writel(pintbit, ®s->request); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void adi_gpio_mask_ack_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - unsigned pintbit = hwirq_to_pintbit(port, d->hwirq); - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { - if (readl(®s->invert_set) & pintbit) - writel(pintbit, ®s->invert_clear); - else - writel(pintbit, ®s->invert_set); - } - - writel(pintbit, ®s->request); - writel(pintbit, ®s->mask_clear); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void adi_gpio_mask_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void adi_gpio_unmask_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static unsigned int adi_gpio_irq_startup(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs; - - if (!port) { - pr_err("GPIO IRQ %d :Not exist\n", d->irq); - /* FIXME: negative return code will be ignored */ - return -ENODEV; - } - - regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - port_setup(port, d->hwirq, true); - writew(BIT(d->hwirq), &port->regs->dir_clear); - writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static void adi_gpio_irq_shutdown(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static int adi_gpio_irq_type(struct irq_data *d, unsigned int type) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *pint_regs; - unsigned pintmask; - unsigned int irq = d->irq; - int ret = 0; - char buf[16]; - - if (!port) { - pr_err("GPIO IRQ %d :Not exist\n", d->irq); - return -ENODEV; - } - - pint_regs = port->pint->regs; - - pintmask = hwirq_to_pintbit(port, d->hwirq); - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - /* In case of interrupt autodetect, set irq type to edge sensitive. */ - if (type == IRQ_TYPE_PROBE) - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | - IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - snprintf(buf, 16, "gpio-irq%u", irq); - port_setup(port, d->hwirq, true); - } else - goto out; - - /* The GPIO interrupt is triggered only when its input value - * transfer from 0 to 1. So, invert the input value if the - * irq type is low or falling - */ - if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) - writel(pintmask, &pint_regs->invert_set); - else - writel(pintmask, &pint_regs->invert_clear); - - /* In edge sensitive case, if the input value of the requested irq - * is already 1, invert it. - */ - if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { - if (gpio_get_value(port->chip.base + d->hwirq)) - writel(pintmask, &pint_regs->invert_set); - else - writel(pintmask, &pint_regs->invert_clear); - } - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - writel(pintmask, &pint_regs->edge_set); - irq_set_handler_locked(d, handle_edge_irq); - } else { - writel(pintmask, &pint_regs->edge_clear); - irq_set_handler_locked(d, handle_level_irq); - } - -out: - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); - - return ret; -} - -#ifdef CONFIG_PM -static int adi_gpio_set_wake(struct irq_data *d, unsigned int state) -{ - struct gpio_port *port = irq_data_get_irq_chip_data(d); - - if (!port || !port->pint || port->pint->irq != d->irq) - return -EINVAL; - -#ifndef SEC_GCTL - adi_internal_set_wake(port->pint->irq, state); -#endif - - return 0; -} - -static int adi_pint_suspend(void) -{ - struct gpio_pint *pint; - - list_for_each_entry(pint, &adi_pint_list, node) { - writel(0xffffffff, &pint->regs->mask_clear); - pint->saved_data.assign = readl(&pint->regs->assign); - pint->saved_data.edge_set = readl(&pint->regs->edge_set); - pint->saved_data.invert_set = readl(&pint->regs->invert_set); - } - - return 0; -} - -static void adi_pint_resume(void) -{ - struct gpio_pint *pint; - - list_for_each_entry(pint, &adi_pint_list, node) { - writel(pint->saved_data.assign, &pint->regs->assign); - writel(pint->saved_data.edge_set, &pint->regs->edge_set); - writel(pint->saved_data.invert_set, &pint->regs->invert_set); - } -} - -static int adi_gpio_suspend(void) -{ - struct gpio_port *port; - - list_for_each_entry(port, &adi_gpio_port_list, node) { - port->saved_data.fer = readw(&port->regs->port_fer); - port->saved_data.mux = readl(&port->regs->port_mux); - port->saved_data.data = readw(&port->regs->data); - port->saved_data.inen = readw(&port->regs->inen); - port->saved_data.dir = readw(&port->regs->dir_set); - } - - return adi_pint_suspend(); -} - -static void adi_gpio_resume(void) -{ - struct gpio_port *port; - - adi_pint_resume(); - - list_for_each_entry(port, &adi_gpio_port_list, node) { - writel(port->saved_data.mux, &port->regs->port_mux); - writew(port->saved_data.fer, &port->regs->port_fer); - writew(port->saved_data.inen, &port->regs->inen); - writew(port->saved_data.data & port->saved_data.dir, - &port->regs->data_set); - writew(port->saved_data.dir, &port->regs->dir_set); - } - -} - -static struct syscore_ops gpio_pm_syscore_ops = { - .suspend = adi_gpio_suspend, - .resume = adi_gpio_resume, -}; -#else /* CONFIG_PM */ -#define adi_gpio_set_wake NULL -#endif /* CONFIG_PM */ - -#ifdef CONFIG_IRQ_PREFLOW_FASTEOI -static inline void preflow_handler(struct irq_desc *desc) -{ - if (desc->preflow_handler) - desc->preflow_handler(&desc->irq_data); -} -#else -static inline void preflow_handler(struct irq_desc *desc) { } -#endif - -static void adi_gpio_handle_pint_irq(struct irq_desc *desc) -{ - u32 request; - u32 level_mask, hwirq; - bool umask = false; - struct gpio_pint *pint = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct gpio_pint_regs *regs = pint->regs; - struct irq_domain *domain; - - preflow_handler(desc); - chained_irq_enter(chip, desc); - - request = readl(®s->request); - level_mask = readl(®s->edge_set) & request; - - hwirq = 0; - domain = pint->domain[0]; - while (request) { - /* domain pointer need to be changed only once at IRQ 16 when - * we go through IRQ requests from bit 0 to bit 31. - */ - if (hwirq == PINT_HI_OFFSET) - domain = pint->domain[1]; - - if (request & 1) { - if (level_mask & BIT(hwirq)) { - umask = true; - chained_irq_exit(chip, desc); - } - generic_handle_irq(irq_find_mapping(domain, - hwirq % PINT_HI_OFFSET)); - } - - hwirq++; - request >>= 1; - } - - if (!umask) - chained_irq_exit(chip, desc); -} - -static struct irq_chip adi_gpio_irqchip = { - .name = "GPIO", - .irq_ack = adi_gpio_ack_irq, - .irq_mask = adi_gpio_mask_irq, - .irq_mask_ack = adi_gpio_mask_ack_irq, - .irq_unmask = adi_gpio_unmask_irq, - .irq_disable = adi_gpio_mask_irq, - .irq_enable = adi_gpio_unmask_irq, - .irq_set_type = adi_gpio_irq_type, - .irq_startup = adi_gpio_irq_startup, - .irq_shutdown = adi_gpio_irq_shutdown, - .irq_set_wake = adi_gpio_set_wake, -}; - -static int adi_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->ngroups; -} - -static const char *adi_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->groups[selector].name; -} - -static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - *pins = pinctrl->soc->groups[selector].pins; - *num_pins = pinctrl->soc->groups[selector].num; - return 0; -} - -static const struct pinctrl_ops adi_pctrl_ops = { - .get_groups_count = adi_get_groups_count, - .get_group_name = adi_get_group_name, - .get_group_pins = adi_get_group_pins, -}; - -static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id, - unsigned group_id) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_port *port; - struct pinctrl_gpio_range *range; - unsigned long flags; - unsigned short *mux, pin; - - mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; - - while (*mux) { - pin = P_IDENT(*mux); - - range = pinctrl_find_gpio_range_from_pin(pctldev, pin); - if (range == NULL) /* should not happen */ - return -ENODEV; - - port = gpiochip_get_data(range->gc); - - spin_lock_irqsave(&port->lock, flags); - - portmux_setup(port, pin_to_offset(range, pin), - P_FUNCT2MUX(*mux)); - port_setup(port, pin_to_offset(range, pin), false); - mux++; - - spin_unlock_irqrestore(&port->lock, flags); - } - - return 0; -} - -static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->nfunctions; -} - -static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->functions[selector].name; -} - -static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pinctrl->soc->functions[selector].groups; - *num_groups = pinctrl->soc->functions[selector].num_groups; - return 0; -} - -static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned pin) -{ - struct gpio_port *port; - unsigned long flags; - u8 offset; - - port = gpiochip_get_data(range->gc); - offset = pin_to_offset(range, pin); - - spin_lock_irqsave(&port->lock, flags); - - port_setup(port, offset, true); - - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static const struct pinmux_ops adi_pinmux_ops = { - .set_mux = adi_pinmux_set, - .get_functions_count = adi_pinmux_get_funcs_count, - .get_function_name = adi_pinmux_get_func_name, - .get_function_groups = adi_pinmux_get_groups, - .gpio_request_enable = adi_pinmux_request_gpio, - .strict = true, -}; - - -static struct pinctrl_desc adi_pinmux_desc = { - .name = DRIVER_NAME, - .pctlops = &adi_pctrl_ops, - .pmxops = &adi_pinmux_ops, - .owner = THIS_MODULE, -}; - -static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct gpio_port *port; - unsigned long flags; - - port = gpiochip_get_data(chip); - - spin_lock_irqsave(&port->lock, flags); - - writew(BIT(offset), &port->regs->dir_clear); - writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen); - - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct gpio_port *port = gpiochip_get_data(chip); - struct gpio_port_t *regs = port->regs; - unsigned long flags; - - spin_lock_irqsave(&port->lock, flags); - - if (value) - writew(BIT(offset), ®s->data_set); - else - writew(BIT(offset), ®s->data_clear); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct gpio_port *port = gpiochip_get_data(chip); - struct gpio_port_t *regs = port->regs; - unsigned long flags; - - spin_lock_irqsave(&port->lock, flags); - - writew(readw(®s->inen) & ~BIT(offset), ®s->inen); - if (value) - writew(BIT(offset), ®s->data_set); - else - writew(BIT(offset), ®s->data_clear); - writew(BIT(offset), ®s->dir_set); - - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ - struct gpio_port *port = gpiochip_get_data(chip); - struct gpio_port_t *regs = port->regs; - unsigned long flags; - int ret; - - spin_lock_irqsave(&port->lock, flags); - - ret = !!(readw(®s->data) & BIT(offset)); - - spin_unlock_irqrestore(&port->lock, flags); - - return ret; -} - -static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct gpio_port *port = gpiochip_get_data(chip); - - if (port->irq_base >= 0) - return irq_find_mapping(port->domain, offset); - else - return irq_create_mapping(port->domain, offset); -} - -static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map, - struct irq_domain *domain) -{ - struct gpio_pint_regs *regs = pint->regs; - u32 map_mask; - - if (pint->map_count > 1) - return -EINVAL; - - pint->map_count++; - - /* The map_mask of each gpio port is a 16-bit duplicate - * of the 8-bit map. It can be set to either high 16 bits or low - * 16 bits of the pint assignment register. - */ - map_mask = (map << 8) | map; - if (assign) { - map_mask <<= PINT_HI_OFFSET; - writel((readl(®s->assign) & 0xFFFF) | map_mask, - ®s->assign); - } else - writel((readl(®s->assign) & 0xFFFF0000) | map_mask, - ®s->assign); - - pint->domain[assign] = domain; - - return 0; -} - -static int adi_gpio_pint_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct resource *res; - struct gpio_pint *pint = devm_kzalloc(dev, sizeof(*pint), GFP_KERNEL); - - if (!pint) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pint->base = devm_ioremap_resource(dev, res); - if (IS_ERR(pint->base)) - return PTR_ERR(pint->base); - - pint->regs = (struct gpio_pint_regs *)pint->base; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) { - dev_err(dev, "Invalid IRQ resource\n"); - return -ENODEV; - } - - spin_lock_init(&pint->lock); - - pint->irq = res->start; - pint->pint_map_port = adi_pint_map_port; - platform_set_drvdata(pdev, pint); - - irq_set_chained_handler_and_data(pint->irq, adi_gpio_handle_pint_irq, - pint); - - list_add_tail(&pint->node, &adi_pint_list); - - return 0; -} - -static int adi_gpio_pint_remove(struct platform_device *pdev) -{ - struct gpio_pint *pint = platform_get_drvdata(pdev); - - list_del(&pint->node); - irq_set_handler(pint->irq, handle_simple_irq); - - return 0; -} - -static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct gpio_port *port = d->host_data; - - if (!port) - return -EINVAL; - - irq_set_chip_data(irq, port); - irq_set_chip_and_handler(irq, &adi_gpio_irqchip, - handle_level_irq); - - return 0; -} - -static const struct irq_domain_ops adi_gpio_irq_domain_ops = { - .map = adi_gpio_irq_map, - .xlate = irq_domain_xlate_onecell, -}; - -static int adi_gpio_init_int(struct gpio_port *port) -{ - struct device_node *node = port->dev->of_node; - struct gpio_pint *pint = port->pint; - int ret; - - port->domain = irq_domain_add_linear(node, port->width, - &adi_gpio_irq_domain_ops, port); - if (!port->domain) { - dev_err(port->dev, "Failed to create irqdomain\n"); - return -ENOSYS; - } - - /* According to BF54x and BF60x HRM, pin interrupt devices are not - * part of the GPIO port device. in GPIO interrupt mode, the GPIO - * pins of multiple port devices can be routed into one pin interrupt - * device. The mapping can be configured by setting pint assignment - * register with the mapping value of different GPIO port. This is - * done via function pint_map_port(). - */ - ret = pint->pint_map_port(port->pint, port->pint_assign, - port->pint_map, port->domain); - if (ret) - return ret; - - if (port->irq_base >= 0) { - ret = irq_create_strict_mappings(port->domain, port->irq_base, - 0, port->width); - if (ret) { - dev_err(port->dev, "Couldn't associate to domain\n"); - return ret; - } - } - - return 0; -} - -#define DEVNAME_SIZE 16 - -static int adi_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - const struct adi_pinctrl_gpio_platform_data *pdata; - struct resource *res; - struct gpio_port *port; - char pinctrl_devname[DEVNAME_SIZE]; - static int gpio; - int ret = 0; - - pdata = dev->platform_data; - if (!pdata) - return -EINVAL; - - port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); - if (!port) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - port->base = devm_ioremap_resource(dev, res); - if (IS_ERR(port->base)) - return PTR_ERR(port->base); - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) - port->irq_base = -1; - else - port->irq_base = res->start; - - port->width = pdata->port_width; - port->dev = dev; - port->regs = (struct gpio_port_t *)port->base; - port->pint_assign = pdata->pint_assign; - port->pint_map = pdata->pint_map; - - port->pint = find_gpio_pint(pdata->pint_id); - if (port->pint) { - ret = adi_gpio_init_int(port); - if (ret) - return ret; - } - - spin_lock_init(&port->lock); - - platform_set_drvdata(pdev, port); - - port->chip.label = "adi-gpio"; - port->chip.direction_input = adi_gpio_direction_input; - port->chip.get = adi_gpio_get_value; - port->chip.direction_output = adi_gpio_direction_output; - port->chip.set = adi_gpio_set_value; - port->chip.request = gpiochip_generic_request, - port->chip.free = gpiochip_generic_free, - port->chip.to_irq = adi_gpio_to_irq; - if (pdata->port_gpio_base > 0) - port->chip.base = pdata->port_gpio_base; - else - port->chip.base = gpio; - port->chip.ngpio = port->width; - gpio = port->chip.base + port->width; - - ret = gpiochip_add_data(&port->chip, port); - if (ret) { - dev_err(&pdev->dev, "Fail to add GPIO chip.\n"); - goto out_remove_domain; - } - - /* Add gpio pin range */ - snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d", - pdata->pinctrl_id); - pinctrl_devname[DEVNAME_SIZE - 1] = 0; - ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname, - 0, pdata->port_pin_base, port->width); - if (ret) { - dev_err(&pdev->dev, "Fail to add pin range to %s.\n", - pinctrl_devname); - goto out_remove_gpiochip; - } - - list_add_tail(&port->node, &adi_gpio_port_list); - - return 0; - -out_remove_gpiochip: - gpiochip_remove(&port->chip); -out_remove_domain: - if (port->pint) - irq_domain_remove(port->domain); - - return ret; -} - -static int adi_gpio_remove(struct platform_device *pdev) -{ - struct gpio_port *port = platform_get_drvdata(pdev); - u8 offset; - - list_del(&port->node); - gpiochip_remove(&port->chip); - if (port->pint) { - for (offset = 0; offset < port->width; offset++) - irq_dispose_mapping(irq_find_mapping(port->domain, - offset)); - irq_domain_remove(port->domain); - } - - return 0; -} - -static int adi_pinctrl_probe(struct platform_device *pdev) -{ - struct adi_pinctrl *pinctrl; - - pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); - if (!pinctrl) - return -ENOMEM; - - pinctrl->dev = &pdev->dev; - - adi_pinctrl_soc_init(&pinctrl->soc); - - adi_pinmux_desc.pins = pinctrl->soc->pins; - adi_pinmux_desc.npins = pinctrl->soc->npins; - - /* Now register the pin controller and all pins it handles */ - pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &adi_pinmux_desc, - pinctrl); - if (IS_ERR(pinctrl->pctl)) { - dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n"); - return PTR_ERR(pinctrl->pctl); - } - - platform_set_drvdata(pdev, pinctrl); - - return 0; -} - -static struct platform_driver adi_pinctrl_driver = { - .probe = adi_pinctrl_probe, - .driver = { - .name = DRIVER_NAME, - }, -}; - -static struct platform_driver adi_gpio_pint_driver = { - .probe = adi_gpio_pint_probe, - .remove = adi_gpio_pint_remove, - .driver = { - .name = "adi-gpio-pint", - }, -}; - -static struct platform_driver adi_gpio_driver = { - .probe = adi_gpio_probe, - .remove = adi_gpio_remove, - .driver = { - .name = "adi-gpio", - }, -}; - -static struct platform_driver * const drivers[] = { - &adi_pinctrl_driver, - &adi_gpio_pint_driver, - &adi_gpio_driver, -}; - -static int __init adi_pinctrl_setup(void) -{ - int ret; - - ret = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); - if (ret) - return ret; - -#ifdef CONFIG_PM - register_syscore_ops(&gpio_pm_syscore_ops); -#endif - return 0; -} -arch_initcall(adi_pinctrl_setup); - -MODULE_AUTHOR("Sonic Zhang "); -MODULE_DESCRIPTION("ADI gpio2 pin control driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h deleted file mode 100644 index 3ca29738213f..000000000000 --- a/drivers/pinctrl/pinctrl-adi2.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#ifndef PINCTRL_PINCTRL_ADI2_H -#define PINCTRL_PINCTRL_ADI2_H - -#include - - /** - * struct adi_pin_group - describes a pin group - * @name: the name of this pin group - * @pins: an array of pins - * @num: the number of pins in this array - */ -struct adi_pin_group { - const char *name; - const unsigned *pins; - const unsigned num; - const unsigned short *mux; -}; - -#define ADI_PIN_GROUP(n, p, m) \ - { \ - .name = n, \ - .pins = p, \ - .num = ARRAY_SIZE(p), \ - .mux = m, \ - } - - /** - * struct adi_pmx_func - describes function mux setting of pin groups - * @name: the name of this function mux setting - * @groups: an array of pin groups - * @num_groups: the number of pin groups in this array - * @mux: the function mux setting array, end by zero - */ -struct adi_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; -}; - -#define ADI_PMX_FUNCTION(n, g) \ - { \ - .name = n, \ - .groups = g, \ - .num_groups = ARRAY_SIZE(g), \ - } - -/** - * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration - * @functions: The functions supported on this SoC. - * @nfunction: The number of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The number of entries in @groups. - * @pins: An array describing all pins the pin controller affects. - * @npins: The number of entries in @pins. - */ -struct adi_pinctrl_soc_data { - const struct adi_pmx_func *functions; - int nfunctions; - const struct adi_pin_group *groups; - int ngroups; - const struct pinctrl_pin_desc *pins; - int npins; -}; - -void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc); - -#endif /* PINCTRL_PINCTRL_ADI2_H */ diff --git a/include/linux/platform_data/pinctrl-adi2.h b/include/linux/platform_data/pinctrl-adi2.h deleted file mode 100644 index 8f91300617ec..000000000000 --- a/include/linux/platform_data/pinctrl-adi2.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - - -#ifndef PINCTRL_ADI2_H -#define PINCTRL_ADI2_H - -#include -#include - -/** - * struct adi_pinctrl_gpio_platform_data - Pinctrl gpio platform data - * for ADI GPIO2 device. - * - * @port_gpio_base: Optional global GPIO index of the GPIO bank. - * 0 means driver decides. - * @port_pin_base: Pin index of the pin controller device. - * @port_width: PIN number of the GPIO bank device - * @pint_id: GPIO PINT device id that this GPIO bank should map to. - * @pint_assign: The 32-bit GPIO PINT registers can be divided into 2 parts. A - * GPIO bank can be mapped into either low 16 bits[0] or high 16 - * bits[1] of each PINT register. - * @pint_map: GIOP bank mapping code in PINT device - */ -struct adi_pinctrl_gpio_platform_data { - unsigned int port_gpio_base; - unsigned int port_pin_base; - unsigned int port_width; - u8 pinctrl_id; - u8 pint_id; - bool pint_assign; - u8 pint_map; -}; - -#endif -- cgit v1.2.3 From c957ea5c797cfccffeee92e0af8e0e99212dd755 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 17:24:55 +0100 Subject: input: misc: remove blackfin rotary driver The blackfin architecture is getting removed, so this one is obsolete as well. Acked-by: Dmitry Torokhov Acked-by: Aaron Wu Signed-off-by: Arnd Bergmann --- drivers/input/misc/Kconfig | 9 - drivers/input/misc/Makefile | 1 - drivers/input/misc/bfin_rotary.c | 294 ------------------------------ include/linux/platform_data/bfin_rotary.h | 117 ------------ 4 files changed, 421 deletions(-) delete mode 100644 drivers/input/misc/bfin_rotary.c delete mode 100644 include/linux/platform_data/bfin_rotary.h (limited to 'include/linux') diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 62a1312a7387..e9770f5e3f77 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -655,15 +655,6 @@ config INPUT_DM355EVM To compile this driver as a module, choose M here: the module will be called dm355evm_keys. -config INPUT_BFIN_ROTARY - tristate "Blackfin Rotary support" - depends on BF54x || BF52x - help - Say Y here if you want to use the Blackfin Rotary. - - To compile this driver as a module, choose M here: the - module will be called bfin-rotary. - config INPUT_WM831X_ON tristate "WM831X ON pin" depends on MFD_WM831X diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index a8f61af865aa..eb9c6c3ec530 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_INPUT_ARIZONA_HAPTICS) += arizona-haptics.o obj-$(CONFIG_INPUT_ATI_REMOTE2) += ati_remote2.o obj-$(CONFIG_INPUT_ATLAS_BTNS) += atlas_btns.o obj-$(CONFIG_INPUT_ATMEL_CAPTOUCH) += atmel_captouch.o -obj-$(CONFIG_INPUT_BFIN_ROTARY) += bfin_rotary.o obj-$(CONFIG_INPUT_BMA150) += bma150.o obj-$(CONFIG_INPUT_CM109) += cm109.o obj-$(CONFIG_INPUT_CMA3000) += cma3000_d0x.o diff --git a/drivers/input/misc/bfin_rotary.c b/drivers/input/misc/bfin_rotary.c deleted file mode 100644 index 799ce3d2820e..000000000000 --- a/drivers/input/misc/bfin_rotary.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Rotary counter driver for Analog Devices Blackfin Processors - * - * Copyright 2008-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define CNT_CONFIG_OFF 0 /* CNT Config Offset */ -#define CNT_IMASK_OFF 4 /* CNT Interrupt Mask Offset */ -#define CNT_STATUS_OFF 8 /* CNT Status Offset */ -#define CNT_COMMAND_OFF 12 /* CNT Command Offset */ -#define CNT_DEBOUNCE_OFF 16 /* CNT Debounce Offset */ -#define CNT_COUNTER_OFF 20 /* CNT Counter Offset */ -#define CNT_MAX_OFF 24 /* CNT Maximum Count Offset */ -#define CNT_MIN_OFF 28 /* CNT Minimum Count Offset */ - -struct bfin_rot { - struct input_dev *input; - void __iomem *base; - int irq; - unsigned int up_key; - unsigned int down_key; - unsigned int button_key; - unsigned int rel_code; - - unsigned short mode; - unsigned short debounce; - - unsigned short cnt_config; - unsigned short cnt_imask; - unsigned short cnt_debounce; -}; - -static void report_key_event(struct input_dev *input, int keycode) -{ - /* simulate a press-n-release */ - input_report_key(input, keycode, 1); - input_sync(input); - input_report_key(input, keycode, 0); - input_sync(input); -} - -static void report_rotary_event(struct bfin_rot *rotary, int delta) -{ - struct input_dev *input = rotary->input; - - if (rotary->up_key) { - report_key_event(input, - delta > 0 ? rotary->up_key : rotary->down_key); - } else { - input_report_rel(input, rotary->rel_code, delta); - input_sync(input); - } -} - -static irqreturn_t bfin_rotary_isr(int irq, void *dev_id) -{ - struct bfin_rot *rotary = dev_id; - int delta; - - switch (readw(rotary->base + CNT_STATUS_OFF)) { - - case ICII: - break; - - case UCII: - case DCII: - delta = readl(rotary->base + CNT_COUNTER_OFF); - if (delta) - report_rotary_event(rotary, delta); - break; - - case CZMII: - report_key_event(rotary->input, rotary->button_key); - break; - - default: - break; - } - - writew(W1LCNT_ZERO, rotary->base + CNT_COMMAND_OFF); /* Clear COUNTER */ - writew(-1, rotary->base + CNT_STATUS_OFF); /* Clear STATUS */ - - return IRQ_HANDLED; -} - -static int bfin_rotary_open(struct input_dev *input) -{ - struct bfin_rot *rotary = input_get_drvdata(input); - unsigned short val; - - if (rotary->mode & ROT_DEBE) - writew(rotary->debounce & DPRESCALE, - rotary->base + CNT_DEBOUNCE_OFF); - - writew(rotary->mode & ~CNTE, rotary->base + CNT_CONFIG_OFF); - - val = UCIE | DCIE; - if (rotary->button_key) - val |= CZMIE; - writew(val, rotary->base + CNT_IMASK_OFF); - - writew(rotary->mode | CNTE, rotary->base + CNT_CONFIG_OFF); - - return 0; -} - -static void bfin_rotary_close(struct input_dev *input) -{ - struct bfin_rot *rotary = input_get_drvdata(input); - - writew(0, rotary->base + CNT_CONFIG_OFF); - writew(0, rotary->base + CNT_IMASK_OFF); -} - -static void bfin_rotary_free_action(void *data) -{ - peripheral_free_list(data); -} - -static int bfin_rotary_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - const struct bfin_rotary_platform_data *pdata = dev_get_platdata(dev); - struct bfin_rot *rotary; - struct resource *res; - struct input_dev *input; - int error; - - /* Basic validation */ - if ((pdata->rotary_up_key && !pdata->rotary_down_key) || - (!pdata->rotary_up_key && pdata->rotary_down_key)) { - return -EINVAL; - } - - if (pdata->pin_list) { - error = peripheral_request_list(pdata->pin_list, - dev_name(dev)); - if (error) { - dev_err(dev, "requesting peripherals failed: %d\n", - error); - return error; - } - - error = devm_add_action_or_reset(dev, bfin_rotary_free_action, - pdata->pin_list); - if (error) { - dev_err(dev, "setting cleanup action failed: %d\n", - error); - return error; - } - } - - rotary = devm_kzalloc(dev, sizeof(struct bfin_rot), GFP_KERNEL); - if (!rotary) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rotary->base = devm_ioremap_resource(dev, res); - if (IS_ERR(rotary->base)) - return PTR_ERR(rotary->base); - - input = devm_input_allocate_device(dev); - if (!input) - return -ENOMEM; - - rotary->input = input; - - rotary->up_key = pdata->rotary_up_key; - rotary->down_key = pdata->rotary_down_key; - rotary->button_key = pdata->rotary_button_key; - rotary->rel_code = pdata->rotary_rel_code; - - rotary->mode = pdata->mode; - rotary->debounce = pdata->debounce; - - input->name = pdev->name; - input->phys = "bfin-rotary/input0"; - input->dev.parent = dev; - - input_set_drvdata(input, rotary); - - input->id.bustype = BUS_HOST; - input->id.vendor = 0x0001; - input->id.product = 0x0001; - input->id.version = 0x0100; - - input->open = bfin_rotary_open; - input->close = bfin_rotary_close; - - if (rotary->up_key) { - __set_bit(EV_KEY, input->evbit); - __set_bit(rotary->up_key, input->keybit); - __set_bit(rotary->down_key, input->keybit); - } else { - __set_bit(EV_REL, input->evbit); - __set_bit(rotary->rel_code, input->relbit); - } - - if (rotary->button_key) { - __set_bit(EV_KEY, input->evbit); - __set_bit(rotary->button_key, input->keybit); - } - - /* Quiesce the device before requesting irq */ - bfin_rotary_close(input); - - rotary->irq = platform_get_irq(pdev, 0); - if (rotary->irq < 0) { - dev_err(dev, "No rotary IRQ specified\n"); - return -ENOENT; - } - - error = devm_request_irq(dev, rotary->irq, bfin_rotary_isr, - 0, dev_name(dev), rotary); - if (error) { - dev_err(dev, "unable to claim irq %d; error %d\n", - rotary->irq, error); - return error; - } - - error = input_register_device(input); - if (error) { - dev_err(dev, "unable to register input device (%d)\n", error); - return error; - } - - platform_set_drvdata(pdev, rotary); - device_init_wakeup(dev, 1); - - return 0; -} - -static int __maybe_unused bfin_rotary_suspend(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct bfin_rot *rotary = platform_get_drvdata(pdev); - - rotary->cnt_config = readw(rotary->base + CNT_CONFIG_OFF); - rotary->cnt_imask = readw(rotary->base + CNT_IMASK_OFF); - rotary->cnt_debounce = readw(rotary->base + CNT_DEBOUNCE_OFF); - - if (device_may_wakeup(&pdev->dev)) - enable_irq_wake(rotary->irq); - - return 0; -} - -static int __maybe_unused bfin_rotary_resume(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct bfin_rot *rotary = platform_get_drvdata(pdev); - - writew(rotary->cnt_debounce, rotary->base + CNT_DEBOUNCE_OFF); - writew(rotary->cnt_imask, rotary->base + CNT_IMASK_OFF); - writew(rotary->cnt_config & ~CNTE, rotary->base + CNT_CONFIG_OFF); - - if (device_may_wakeup(&pdev->dev)) - disable_irq_wake(rotary->irq); - - if (rotary->cnt_config & CNTE) - writew(rotary->cnt_config, rotary->base + CNT_CONFIG_OFF); - - return 0; -} - -static SIMPLE_DEV_PM_OPS(bfin_rotary_pm_ops, - bfin_rotary_suspend, bfin_rotary_resume); - -static struct platform_driver bfin_rotary_device_driver = { - .probe = bfin_rotary_probe, - .driver = { - .name = "bfin-rotary", - .pm = &bfin_rotary_pm_ops, - }, -}; -module_platform_driver(bfin_rotary_device_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("Rotary Counter driver for Blackfin Processors"); -MODULE_ALIAS("platform:bfin-rotary"); diff --git a/include/linux/platform_data/bfin_rotary.h b/include/linux/platform_data/bfin_rotary.h deleted file mode 100644 index 98829370fee2..000000000000 --- a/include/linux/platform_data/bfin_rotary.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * board initialization should put one of these structures into platform_data - * and place the bfin-rotary onto platform_bus named "bfin-rotary". - * - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_ROTARY_H -#define _BFIN_ROTARY_H - -/* mode bitmasks */ -#define ROT_QUAD_ENC CNTMODE_QUADENC /* quadrature/grey code encoder mode */ -#define ROT_BIN_ENC CNTMODE_BINENC /* binary encoder mode */ -#define ROT_UD_CNT CNTMODE_UDCNT /* rotary counter mode */ -#define ROT_DIR_CNT CNTMODE_DIRCNT /* direction counter mode */ - -#define ROT_DEBE DEBE /* Debounce Enable */ - -#define ROT_CDGINV CDGINV /* CDG Pin Polarity Invert */ -#define ROT_CUDINV CUDINV /* CUD Pin Polarity Invert */ -#define ROT_CZMINV CZMINV /* CZM Pin Polarity Invert */ - -struct bfin_rotary_platform_data { - /* set rotary UP KEY_### or BTN_### in case you prefer - * bfin-rotary to send EV_KEY otherwise set 0 - */ - unsigned int rotary_up_key; - /* set rotary DOWN KEY_### or BTN_### in case you prefer - * bfin-rotary to send EV_KEY otherwise set 0 - */ - unsigned int rotary_down_key; - /* set rotary BUTTON KEY_### or BTN_### */ - unsigned int rotary_button_key; - /* set rotary Relative Axis REL_### in case you prefer - * bfin-rotary to send EV_REL otherwise set 0 - */ - unsigned int rotary_rel_code; - unsigned short debounce; /* 0..17 */ - unsigned short mode; - unsigned short pm_wakeup; - unsigned short *pin_list; -}; - -/* CNT_CONFIG bitmasks */ -#define CNTE (1 << 0) /* Counter Enable */ -#define DEBE (1 << 1) /* Debounce Enable */ -#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */ -#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */ -#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */ -#define CNTMODE_SHIFT 8 -#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */ -#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */ -#define BNDMODE_SHIFT 12 -#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */ -#define INPDIS (1 << 15) /* CUG and CDG Input Disable */ - -#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */ -#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */ -#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */ -#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */ -#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */ - -#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */ -#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */ -#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */ -#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */ - -/* CNT_IMASK bitmasks */ -#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */ -#define UCIE (1 << 1) /* Up count Interrupt Enable */ -#define DCIE (1 << 2) /* Down count Interrupt Enable */ -#define MINCIE (1 << 3) /* Min Count Interrupt Enable */ -#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */ -#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */ -#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */ -#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */ -#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */ -#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */ -#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */ - -/* CNT_STATUS bitmasks */ -#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */ -#define UCII (1 << 1) /* Up count Interrupt Identifier */ -#define DCII (1 << 2) /* Down count Interrupt Identifier */ -#define MINCII (1 << 3) /* Min Count Interrupt Identifier */ -#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */ -#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */ -#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */ -#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */ -#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */ -#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */ -#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */ - -/* CNT_COMMAND bitmasks */ -#define W1LCNT 0xf /* Load Counter Register */ -#define W1LMIN 0xf0 /* Load Min Register */ -#define W1LMAX 0xf00 /* Load Max Register */ -#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */ - -#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */ -#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */ -#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */ - -#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */ -#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */ -#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */ - -#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */ -#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */ -#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */ - -/* CNT_DEBOUNCE bitmasks */ -#define DPRESCALE 0xf /* Load Counter Register */ - -#endif -- cgit v1.2.3 From 03f4c9abd73284193f70e64da1a266d393650530 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 16:10:20 +0100 Subject: usb: host: remove tilegx platform glue The tile architecture is getting removed, so the ehci and ohci platform glue drivers are no longer needed. In case of ohci, this is the last one to define a PLATFORM_DRIVER macro, so we can remove even more. Acked-by: Greg Kroah-Hartman Acked-by: Alan Stern Signed-off-by: Arnd Bergmann --- drivers/usb/host/ehci-hcd.c | 5 - drivers/usb/host/ehci-tilegx.c | 207 ----------------------------------------- drivers/usb/host/ohci-hcd.c | 18 ---- drivers/usb/host/ohci-tilegx.c | 196 -------------------------------------- include/linux/usb/tilegx.h | 35 ------- 5 files changed, 461 deletions(-) delete mode 100644 drivers/usb/host/ehci-tilegx.c delete mode 100644 drivers/usb/host/ohci-tilegx.c delete mode 100644 include/linux/usb/tilegx.h (limited to 'include/linux') diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 7f0737449df7..d927adf3afcd 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1275,11 +1275,6 @@ MODULE_LICENSE ("GPL"); #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver #endif -#ifdef CONFIG_TILE_USB -#include "ehci-tilegx.c" -#define PLATFORM_DRIVER ehci_hcd_tilegx_driver -#endif - #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP #include "ehci-pmcmsp.c" #define PLATFORM_DRIVER ehci_hcd_msp_driver diff --git a/drivers/usb/host/ehci-tilegx.c b/drivers/usb/host/ehci-tilegx.c deleted file mode 100644 index 610ed437ed2c..000000000000 --- a/drivers/usb/host/ehci-tilegx.c +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - */ - -/* - * Tilera TILE-Gx USB EHCI host controller driver. - */ - -#include -#include -#include -#include - -#include - -#include -#include - -static void tilegx_start_ehc(void) -{ -} - -static void tilegx_stop_ehc(void) -{ -} - -static int tilegx_ehci_setup(struct usb_hcd *hcd) -{ - int ret = ehci_init(hcd); - - /* - * Some drivers do: - * - * struct ehci_hcd *ehci = hcd_to_ehci(hcd); - * ehci->need_io_watchdog = 0; - * - * here, but since this is a new driver we're going to leave the - * watchdog enabled. Later we may try to turn it off and see - * whether we run into any problems. - */ - - return ret; -} - -static const struct hc_driver ehci_tilegx_hc_driver = { - .description = hcd_name, - .product_desc = "Tile-Gx EHCI", - .hcd_priv_size = sizeof(struct ehci_hcd), - - /* - * Generic hardware linkage. - */ - .irq = ehci_irq, - .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, - - /* - * Basic lifecycle operations. - */ - .reset = tilegx_ehci_setup, - .start = ehci_run, - .stop = ehci_stop, - .shutdown = ehci_shutdown, - - /* - * Managing I/O requests and associated device resources. - */ - .urb_enqueue = ehci_urb_enqueue, - .urb_dequeue = ehci_urb_dequeue, - .endpoint_disable = ehci_endpoint_disable, - .endpoint_reset = ehci_endpoint_reset, - - /* - * Scheduling support. - */ - .get_frame_number = ehci_get_frame, - - /* - * Root hub support. - */ - .hub_status_data = ehci_hub_status_data, - .hub_control = ehci_hub_control, - .bus_suspend = ehci_bus_suspend, - .bus_resume = ehci_bus_resume, - .relinquish_port = ehci_relinquish_port, - .port_handed_over = ehci_port_handed_over, - - .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -}; - -static int ehci_hcd_tilegx_drv_probe(struct platform_device *pdev) -{ - struct usb_hcd *hcd; - struct ehci_hcd *ehci; - struct tilegx_usb_platform_data *pdata = dev_get_platdata(&pdev->dev); - pte_t pte = { 0 }; - int my_cpu = smp_processor_id(); - int ret; - - if (usb_disabled()) - return -ENODEV; - - /* - * Try to initialize our GXIO context; if we can't, the device - * doesn't exist. - */ - if (gxio_usb_host_init(&pdata->usb_ctx, pdata->dev_index, 1) != 0) - return -ENXIO; - - hcd = usb_create_hcd(&ehci_tilegx_hc_driver, &pdev->dev, - dev_name(&pdev->dev)); - if (!hcd) { - ret = -ENOMEM; - goto err_hcd; - } - - /* - * We don't use rsrc_start to map in our registers, but seems like - * we ought to set it to something, so we use the register VA. - */ - hcd->rsrc_start = - (ulong) gxio_usb_host_get_reg_start(&pdata->usb_ctx); - hcd->rsrc_len = gxio_usb_host_get_reg_len(&pdata->usb_ctx); - hcd->regs = gxio_usb_host_get_reg_start(&pdata->usb_ctx); - - tilegx_start_ehc(); - - ehci = hcd_to_ehci(hcd); - ehci->caps = hcd->regs; - ehci->regs = - hcd->regs + HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); - /* cache this readonly data; minimize chip reads */ - ehci->hcs_params = readl(&ehci->caps->hcs_params); - - /* Create our IRQs and register them. */ - pdata->irq = irq_alloc_hwirq(-1); - if (!pdata->irq) { - ret = -ENXIO; - goto err_no_irq; - } - - tile_irq_activate(pdata->irq, TILE_IRQ_PERCPU); - - /* Configure interrupts. */ - ret = gxio_usb_host_cfg_interrupt(&pdata->usb_ctx, - cpu_x(my_cpu), cpu_y(my_cpu), - KERNEL_PL, pdata->irq); - if (ret) { - ret = -ENXIO; - goto err_have_irq; - } - - /* Register all of our memory. */ - pte = pte_set_home(pte, PAGE_HOME_HASH); - ret = gxio_usb_host_register_client_memory(&pdata->usb_ctx, pte, 0); - if (ret) { - ret = -ENXIO; - goto err_have_irq; - } - - ret = usb_add_hcd(hcd, pdata->irq, IRQF_SHARED); - if (ret == 0) { - platform_set_drvdata(pdev, hcd); - device_wakeup_enable(hcd->self.controller); - return ret; - } - -err_have_irq: - irq_free_hwirq(pdata->irq); -err_no_irq: - tilegx_stop_ehc(); - usb_put_hcd(hcd); -err_hcd: - gxio_usb_host_destroy(&pdata->usb_ctx); - return ret; -} - -static int ehci_hcd_tilegx_drv_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - struct tilegx_usb_platform_data *pdata = dev_get_platdata(&pdev->dev); - - usb_remove_hcd(hcd); - usb_put_hcd(hcd); - tilegx_stop_ehc(); - gxio_usb_host_destroy(&pdata->usb_ctx); - irq_free_hwirq(pdata->irq); - - return 0; -} - -static void ehci_hcd_tilegx_drv_shutdown(struct platform_device *pdev) -{ - usb_hcd_platform_shutdown(pdev); - ehci_hcd_tilegx_drv_remove(pdev); -} - -static struct platform_driver ehci_hcd_tilegx_driver = { - .probe = ehci_hcd_tilegx_drv_probe, - .remove = ehci_hcd_tilegx_drv_remove, - .shutdown = ehci_hcd_tilegx_drv_shutdown, - .driver = { - .name = "tilegx-ehci", - } -}; - -MODULE_ALIAS("platform:tilegx-ehci"); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 84f88fa411cd..199f1b7a91a3 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1244,11 +1244,6 @@ MODULE_LICENSE ("GPL"); #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver #endif -#ifdef CONFIG_TILE_USB -#include "ohci-tilegx.c" -#define PLATFORM_DRIVER ohci_hcd_tilegx_driver -#endif - static int __init ohci_hcd_mod_init(void) { int retval = 0; @@ -1273,12 +1268,6 @@ static int __init ohci_hcd_mod_init(void) goto error_ps3; #endif -#ifdef PLATFORM_DRIVER - retval = platform_driver_register(&PLATFORM_DRIVER); - if (retval < 0) - goto error_platform; -#endif - #ifdef OF_PLATFORM_DRIVER retval = platform_driver_register(&OF_PLATFORM_DRIVER); if (retval < 0) @@ -1322,10 +1311,6 @@ static int __init ohci_hcd_mod_init(void) platform_driver_unregister(&OF_PLATFORM_DRIVER); error_of_platform: #endif -#ifdef PLATFORM_DRIVER - platform_driver_unregister(&PLATFORM_DRIVER); - error_platform: -#endif #ifdef PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); error_ps3: @@ -1353,9 +1338,6 @@ static void __exit ohci_hcd_mod_exit(void) #ifdef OF_PLATFORM_DRIVER platform_driver_unregister(&OF_PLATFORM_DRIVER); #endif -#ifdef PLATFORM_DRIVER - platform_driver_unregister(&PLATFORM_DRIVER); -#endif #ifdef PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); #endif diff --git a/drivers/usb/host/ohci-tilegx.c b/drivers/usb/host/ohci-tilegx.c deleted file mode 100644 index d21ca3ce9a30..000000000000 --- a/drivers/usb/host/ohci-tilegx.c +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - */ - -/* - * Tilera TILE-Gx USB OHCI host controller driver. - */ - -#include -#include -#include -#include - -#include - -#include -#include - -static void tilegx_start_ohc(void) -{ -} - -static void tilegx_stop_ohc(void) -{ -} - -static int tilegx_ohci_start(struct usb_hcd *hcd) -{ - struct ohci_hcd *ohci = hcd_to_ohci(hcd); - int ret; - - ret = ohci_init(ohci); - if (ret < 0) - return ret; - - ret = ohci_run(ohci); - if (ret < 0) { - dev_err(hcd->self.controller, "can't start %s\n", - hcd->self.bus_name); - ohci_stop(hcd); - return ret; - } - - return 0; -} - -static const struct hc_driver ohci_tilegx_hc_driver = { - .description = hcd_name, - .product_desc = "Tile-Gx OHCI", - .hcd_priv_size = sizeof(struct ohci_hcd), - - /* - * Generic hardware linkage. - */ - .irq = ohci_irq, - .flags = HCD_MEMORY | HCD_LOCAL_MEM | HCD_USB11, - - /* - * Basic lifecycle operations. - */ - .start = tilegx_ohci_start, - .stop = ohci_stop, - .shutdown = ohci_shutdown, - - /* - * Managing I/O requests and associated device resources. - */ - .urb_enqueue = ohci_urb_enqueue, - .urb_dequeue = ohci_urb_dequeue, - .endpoint_disable = ohci_endpoint_disable, - - /* - * Scheduling support. - */ - .get_frame_number = ohci_get_frame, - - /* - * Root hub support. - */ - .hub_status_data = ohci_hub_status_data, - .hub_control = ohci_hub_control, - .start_port_reset = ohci_start_port_reset, -}; - -static int ohci_hcd_tilegx_drv_probe(struct platform_device *pdev) -{ - struct usb_hcd *hcd; - struct tilegx_usb_platform_data *pdata = dev_get_platdata(&pdev->dev); - pte_t pte = { 0 }; - int my_cpu = smp_processor_id(); - int ret; - - if (usb_disabled()) - return -ENODEV; - - /* - * Try to initialize our GXIO context; if we can't, the device - * doesn't exist. - */ - if (gxio_usb_host_init(&pdata->usb_ctx, pdata->dev_index, 0) != 0) - return -ENXIO; - - hcd = usb_create_hcd(&ohci_tilegx_hc_driver, &pdev->dev, - dev_name(&pdev->dev)); - if (!hcd) { - ret = -ENOMEM; - goto err_hcd; - } - - /* - * We don't use rsrc_start to map in our registers, but seems like - * we ought to set it to something, so we use the register VA. - */ - hcd->rsrc_start = - (ulong) gxio_usb_host_get_reg_start(&pdata->usb_ctx); - hcd->rsrc_len = gxio_usb_host_get_reg_len(&pdata->usb_ctx); - hcd->regs = gxio_usb_host_get_reg_start(&pdata->usb_ctx); - - tilegx_start_ohc(); - - /* Create our IRQs and register them. */ - pdata->irq = irq_alloc_hwirq(-1); - if (!pdata->irq) { - ret = -ENXIO; - goto err_no_irq; - } - - tile_irq_activate(pdata->irq, TILE_IRQ_PERCPU); - - /* Configure interrupts. */ - ret = gxio_usb_host_cfg_interrupt(&pdata->usb_ctx, - cpu_x(my_cpu), cpu_y(my_cpu), - KERNEL_PL, pdata->irq); - if (ret) { - ret = -ENXIO; - goto err_have_irq; - } - - /* Register all of our memory. */ - pte = pte_set_home(pte, PAGE_HOME_HASH); - ret = gxio_usb_host_register_client_memory(&pdata->usb_ctx, pte, 0); - if (ret) { - ret = -ENXIO; - goto err_have_irq; - } - - ohci_hcd_init(hcd_to_ohci(hcd)); - - ret = usb_add_hcd(hcd, pdata->irq, IRQF_SHARED); - if (ret == 0) { - platform_set_drvdata(pdev, hcd); - device_wakeup_enable(hcd->self.controller); - return ret; - } - -err_have_irq: - irq_free_hwirq(pdata->irq); -err_no_irq: - tilegx_stop_ohc(); - usb_put_hcd(hcd); -err_hcd: - gxio_usb_host_destroy(&pdata->usb_ctx); - return ret; -} - -static int ohci_hcd_tilegx_drv_remove(struct platform_device *pdev) -{ - struct usb_hcd *hcd = platform_get_drvdata(pdev); - struct tilegx_usb_platform_data *pdata = dev_get_platdata(&pdev->dev); - - usb_remove_hcd(hcd); - usb_put_hcd(hcd); - tilegx_stop_ohc(); - gxio_usb_host_destroy(&pdata->usb_ctx); - irq_free_hwirq(pdata->irq); - - return 0; -} - -static void ohci_hcd_tilegx_drv_shutdown(struct platform_device *pdev) -{ - usb_hcd_platform_shutdown(pdev); - ohci_hcd_tilegx_drv_remove(pdev); -} - -static struct platform_driver ohci_hcd_tilegx_driver = { - .probe = ohci_hcd_tilegx_drv_probe, - .remove = ohci_hcd_tilegx_drv_remove, - .shutdown = ohci_hcd_tilegx_drv_shutdown, - .driver = { - .name = "tilegx-ohci", - } -}; - -MODULE_ALIAS("platform:tilegx-ohci"); diff --git a/include/linux/usb/tilegx.h b/include/linux/usb/tilegx.h deleted file mode 100644 index 817908573fe8..000000000000 --- a/include/linux/usb/tilegx.h +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2012 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - * - * Structure to contain platform-specific data related to Tile-Gx USB - * controllers. - */ - -#ifndef _LINUX_USB_TILEGX_H -#define _LINUX_USB_TILEGX_H - -#include - -struct tilegx_usb_platform_data { - /* GXIO device index. */ - int dev_index; - - /* GXIO device context. */ - gxio_usb_host_context_t usb_ctx; - - /* Device IRQ. */ - unsigned int irq; -}; - -#endif /* _LINUX_USB_TILEGX_H */ -- cgit v1.2.3 From a9762b704f5d5e167bbc261573621782b90efbc4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 17:37:54 +0100 Subject: usb: musb: remove blackfin port The blackfin architecture is getting removed, so we can clean up all the special cases in the musb driver. Acked-by: Greg Kroah-Hartman Acked-by: Aaron Wu Acked-by: Bin Liu Cc: Stephen Rothwell [arnd: adding in fixups from Aaron and Stephen] Signed-off-by: Arnd Bergmann --- .../driver-api/usb/writing_musb_glue_layer.rst | 3 - drivers/usb/musb/Kconfig | 12 +- drivers/usb/musb/Makefile | 1 - drivers/usb/musb/blackfin.c | 623 --------------------- drivers/usb/musb/blackfin.h | 81 --- drivers/usb/musb/musb_core.c | 7 +- drivers/usb/musb/musb_core.h | 43 -- drivers/usb/musb/musb_debugfs.c | 2 - drivers/usb/musb/musb_dma.h | 11 - drivers/usb/musb/musb_gadget.c | 56 +- drivers/usb/musb/musb_host.c | 12 +- drivers/usb/musb/musb_regs.h | 182 ------ drivers/usb/musb/musbhsdma.c | 5 - drivers/usb/musb/musbhsdma.h | 64 --- include/linux/usb/musb.h | 7 - 15 files changed, 13 insertions(+), 1096 deletions(-) delete mode 100644 drivers/usb/musb/blackfin.c delete mode 100644 drivers/usb/musb/blackfin.h (limited to 'include/linux') diff --git a/Documentation/driver-api/usb/writing_musb_glue_layer.rst b/Documentation/driver-api/usb/writing_musb_glue_layer.rst index e90e8fa95600..5bf7152fd76f 100644 --- a/Documentation/driver-api/usb/writing_musb_glue_layer.rst +++ b/Documentation/driver-api/usb/writing_musb_glue_layer.rst @@ -718,6 +718,3 @@ http://www.maximintegrated.com/app-notes/index.mvp/id/1822 Texas Instruments USB Configuration Wiki Page: http://processors.wiki.ti.com/index.php/Usbgeneralpage - -Analog Devices Blackfin MUSB Configuration: -http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:musb diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig index e757afc1cfd0..ad08895e78f9 100644 --- a/drivers/usb/musb/Kconfig +++ b/drivers/usb/musb/Kconfig @@ -5,7 +5,7 @@ # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller config USB_MUSB_HDRC - tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, AW, ...)' + tristate 'Inventra Highspeed Dual Role Controller' depends on (USB || USB_GADGET) depends on HAS_IOMEM help @@ -18,9 +18,6 @@ config USB_MUSB_HDRC Texas Instruments families using this IP include DaVinci (35x, 644x ...), OMAP 243x, OMAP 3, and TUSB 6010. - Analog Devices parts using this IP include Blackfin BF54x, - BF525 and BF527. - Allwinner SoCs using this IP include A10, A13, A20, ... If you do not know what this is, please say N. @@ -107,11 +104,6 @@ config USB_MUSB_DSPS depends on ARCH_OMAP2PLUS || COMPILE_TEST depends on OF_IRQ -config USB_MUSB_BLACKFIN - tristate "Blackfin" - depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523) - depends on NOP_USB_XCEIV - config USB_MUSB_UX500 tristate "Ux500 platforms" depends on ARCH_U8500 || COMPILE_TEST @@ -149,7 +141,7 @@ config USB_UX500_DMA config USB_INVENTRA_DMA bool 'Inventra' - depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN + depends on USB_MUSB_OMAP2PLUS help Enable DMA transfers using Mentor's engine. diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile index 79d4d5439164..3a88c79e650c 100644 --- a/drivers/usb/musb/Makefile +++ b/drivers/usb/musb/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o obj-$(CONFIG_USB_MUSB_TUSB6010) += tusb6010.o obj-$(CONFIG_USB_MUSB_DAVINCI) += davinci.o obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o -obj-$(CONFIG_USB_MUSB_BLACKFIN) += blackfin.o obj-$(CONFIG_USB_MUSB_UX500) += ux500.o obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c deleted file mode 100644 index 0a98dcd66d19..000000000000 --- a/drivers/usb/musb/blackfin.c +++ /dev/null @@ -1,623 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * MUSB OTG controller driver for Blackfin Processors - * - * Copyright 2006-2008 Analog Devices Inc. - * - * Enter bugs at http://blackfin.uclinux.org/ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "musb_core.h" -#include "musbhsdma.h" -#include "blackfin.h" - -struct bfin_glue { - struct device *dev; - struct platform_device *musb; - struct platform_device *phy; -}; -#define glue_to_musb(g) platform_get_drvdata(g->musb) - -static u32 bfin_fifo_offset(u8 epnum) -{ - return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8); -} - -static u8 bfin_readb(const void __iomem *addr, unsigned offset) -{ - return (u8)(bfin_read16(addr + offset)); -} - -static u16 bfin_readw(const void __iomem *addr, unsigned offset) -{ - return bfin_read16(addr + offset); -} - -static u32 bfin_readl(const void __iomem *addr, unsigned offset) -{ - return (u32)(bfin_read16(addr + offset)); -} - -static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data) -{ - bfin_write16(addr + offset, (u16)data); -} - -static void bfin_writew(void __iomem *addr, unsigned offset, u16 data) -{ - bfin_write16(addr + offset, data); -} - -static void bfin_writel(void __iomem *addr, unsigned offset, u32 data) -{ - bfin_write16(addr + offset, (u16)data); -} - -/* - * Load an endpoint's FIFO - */ -static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) -{ - struct musb *musb = hw_ep->musb; - void __iomem *fifo = hw_ep->fifo; - void __iomem *epio = hw_ep->regs; - u8 epnum = hw_ep->epnum; - - prefetch((u8 *)src); - - musb_writew(epio, MUSB_TXCOUNT, len); - - dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n", - hw_ep->epnum, fifo, len, src, epio); - - dump_fifo_data(src, len); - - if (!ANOMALY_05000380 && epnum != 0) { - u16 dma_reg; - - flush_dcache_range((unsigned long)src, - (unsigned long)(src + len)); - - /* Setup DMA address register */ - dma_reg = (u32)src; - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); - SSYNC(); - - dma_reg = (u32)src >> 16; - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); - SSYNC(); - - /* Setup DMA count register */ - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); - SSYNC(); - - /* Enable the DMA */ - dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION; - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); - SSYNC(); - - /* Wait for complete */ - while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum))) - cpu_relax(); - - /* acknowledge dma interrupt */ - bfin_write_USB_DMA_INTERRUPT(1 << epnum); - SSYNC(); - - /* Reset DMA */ - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); - SSYNC(); - } else { - SSYNC(); - - if (unlikely((unsigned long)src & 0x01)) - outsw_8((unsigned long)fifo, src, (len + 1) >> 1); - else - outsw((unsigned long)fifo, src, (len + 1) >> 1); - } -} -/* - * Unload an endpoint's FIFO - */ -static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) -{ - struct musb *musb = hw_ep->musb; - void __iomem *fifo = hw_ep->fifo; - u8 epnum = hw_ep->epnum; - - if (ANOMALY_05000467 && epnum != 0) { - u16 dma_reg; - - invalidate_dcache_range((unsigned long)dst, - (unsigned long)(dst + len)); - - /* Setup DMA address register */ - dma_reg = (u32)dst; - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); - SSYNC(); - - dma_reg = (u32)dst >> 16; - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); - SSYNC(); - - /* Setup DMA count register */ - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); - SSYNC(); - - /* Enable the DMA */ - dma_reg = (epnum << 4) | DMA_ENA | INT_ENA; - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); - SSYNC(); - - /* Wait for complete */ - while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum))) - cpu_relax(); - - /* acknowledge dma interrupt */ - bfin_write_USB_DMA_INTERRUPT(1 << epnum); - SSYNC(); - - /* Reset DMA */ - bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); - SSYNC(); - } else { - SSYNC(); - /* Read the last byte of packet with odd size from address fifo + 4 - * to trigger 1 byte access to EP0 FIFO. - */ - if (len == 1) - *dst = (u8)inw((unsigned long)fifo + 4); - else { - if (unlikely((unsigned long)dst & 0x01)) - insw_8((unsigned long)fifo, dst, len >> 1); - else - insw((unsigned long)fifo, dst, len >> 1); - - if (len & 0x01) - *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4); - } - } - dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", - 'R', hw_ep->epnum, fifo, len, dst); - - dump_fifo_data(dst, len); -} - -static irqreturn_t blackfin_interrupt(int irq, void *__hci) -{ - unsigned long flags; - irqreturn_t retval = IRQ_NONE; - struct musb *musb = __hci; - - spin_lock_irqsave(&musb->lock, flags); - - musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); - musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); - musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); - - if (musb->int_usb || musb->int_tx || musb->int_rx) { - musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); - musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); - musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); - retval = musb_interrupt(musb); - } - - /* Start sampling ID pin, when plug is removed from MUSB */ - if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE - || musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) || - (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) { - mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY); - musb->a_wait_bcon = TIMER_DELAY; - } - - spin_unlock_irqrestore(&musb->lock, flags); - - return retval; -} - -static void musb_conn_timer_handler(struct timer_list *t) -{ - struct musb *musb = from_timer(musb, t, dev_timer); - unsigned long flags; - u16 val; - static u8 toggle; - - spin_lock_irqsave(&musb->lock, flags); - switch (musb->xceiv->otg->state) { - case OTG_STATE_A_IDLE: - case OTG_STATE_A_WAIT_BCON: - /* Start a new session */ - val = musb_readw(musb->mregs, MUSB_DEVCTL); - val &= ~MUSB_DEVCTL_SESSION; - musb_writew(musb->mregs, MUSB_DEVCTL, val); - val |= MUSB_DEVCTL_SESSION; - musb_writew(musb->mregs, MUSB_DEVCTL, val); - /* Check if musb is host or peripheral. */ - val = musb_readw(musb->mregs, MUSB_DEVCTL); - - if (!(val & MUSB_DEVCTL_BDEVICE)) { - gpio_set_value(musb->config->gpio_vrsel, 1); - musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; - } else { - gpio_set_value(musb->config->gpio_vrsel, 0); - /* Ignore VBUSERROR and SUSPEND IRQ */ - val = musb_readb(musb->mregs, MUSB_INTRUSBE); - val &= ~MUSB_INTR_VBUSERROR; - musb_writeb(musb->mregs, MUSB_INTRUSBE, val); - - val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR; - musb_writeb(musb->mregs, MUSB_INTRUSB, val); - musb->xceiv->otg->state = OTG_STATE_B_IDLE; - } - mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY); - break; - case OTG_STATE_B_IDLE: - /* - * Start a new session. It seems that MUSB needs taking - * some time to recognize the type of the plug inserted? - */ - val = musb_readw(musb->mregs, MUSB_DEVCTL); - val |= MUSB_DEVCTL_SESSION; - musb_writew(musb->mregs, MUSB_DEVCTL, val); - val = musb_readw(musb->mregs, MUSB_DEVCTL); - - if (!(val & MUSB_DEVCTL_BDEVICE)) { - gpio_set_value(musb->config->gpio_vrsel, 1); - musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; - } else { - gpio_set_value(musb->config->gpio_vrsel, 0); - - /* Ignore VBUSERROR and SUSPEND IRQ */ - val = musb_readb(musb->mregs, MUSB_INTRUSBE); - val &= ~MUSB_INTR_VBUSERROR; - musb_writeb(musb->mregs, MUSB_INTRUSBE, val); - - val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR; - musb_writeb(musb->mregs, MUSB_INTRUSB, val); - - /* Toggle the Soft Conn bit, so that we can response to - * the inserting of either A-plug or B-plug. - */ - if (toggle) { - val = musb_readb(musb->mregs, MUSB_POWER); - val &= ~MUSB_POWER_SOFTCONN; - musb_writeb(musb->mregs, MUSB_POWER, val); - toggle = 0; - } else { - val = musb_readb(musb->mregs, MUSB_POWER); - val |= MUSB_POWER_SOFTCONN; - musb_writeb(musb->mregs, MUSB_POWER, val); - toggle = 1; - } - /* The delay time is set to 1/4 second by default, - * shortening it, if accelerating A-plug detection - * is needed in OTG mode. - */ - mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY / 4); - } - break; - default: - dev_dbg(musb->controller, "%s state not handled\n", - usb_otg_state_string(musb->xceiv->otg->state)); - break; - } - spin_unlock_irqrestore(&musb->lock, flags); - - dev_dbg(musb->controller, "state is %s\n", - usb_otg_state_string(musb->xceiv->otg->state)); -} - -static void bfin_musb_enable(struct musb *musb) -{ - /* REVISIT is this really correct ? */ -} - -static void bfin_musb_disable(struct musb *musb) -{ -} - -static void bfin_musb_set_vbus(struct musb *musb, int is_on) -{ - int value = musb->config->gpio_vrsel_active; - if (!is_on) - value = !value; - gpio_set_value(musb->config->gpio_vrsel, value); - - dev_dbg(musb->controller, "VBUS %s, devctl %02x " - /* otg %3x conf %08x prcm %08x */ "\n", - usb_otg_state_string(musb->xceiv->otg->state), - musb_readb(musb->mregs, MUSB_DEVCTL)); -} - -static int bfin_musb_set_power(struct usb_phy *x, unsigned mA) -{ - return 0; -} - -static int bfin_musb_vbus_status(struct musb *musb) -{ - return 0; -} - -static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode) -{ - return -EIO; -} - -static int bfin_musb_adjust_channel_params(struct dma_channel *channel, - u16 packet_sz, u8 *mode, - dma_addr_t *dma_addr, u32 *len) -{ - struct musb_dma_channel *musb_channel = channel->private_data; - - /* - * Anomaly 05000450 might cause data corruption when using DMA - * MODE 1 transmits with short packet. So to work around this, - * we truncate all MODE 1 transfers down to a multiple of the - * max packet size, and then do the last short packet transfer - * (if there is any) using MODE 0. - */ - if (ANOMALY_05000450) { - if (musb_channel->transmit && *mode == 1) - *len = *len - (*len % packet_sz); - } - - return 0; -} - -static void bfin_musb_reg_init(struct musb *musb) -{ - if (ANOMALY_05000346) { - bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value); - SSYNC(); - } - - if (ANOMALY_05000347) { - bfin_write_USB_APHY_CNTRL(0x0); - SSYNC(); - } - - /* Configure PLL oscillator register */ - bfin_write_USB_PLLOSC_CTRL(0x3080 | - ((480/musb->config->clkin) << 1)); - SSYNC(); - - bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1); - SSYNC(); - - bfin_write_USB_EP_NI0_RXMAXP(64); - SSYNC(); - - bfin_write_USB_EP_NI0_TXMAXP(64); - SSYNC(); - - /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/ - bfin_write_USB_GLOBINTR(0x7); - SSYNC(); - - bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA | - EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA | - EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA | - EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA | - EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA); - SSYNC(); -} - -static int bfin_musb_init(struct musb *musb) -{ - - /* - * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE - * and OTG HOST modes, while rev 1.1 and greater require PE7 to - * be low for DEVICE mode and high for HOST mode. We set it high - * here because we are in host mode - */ - - if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) { - printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n", - musb->config->gpio_vrsel); - return -ENODEV; - } - gpio_direction_output(musb->config->gpio_vrsel, 0); - - musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); - if (IS_ERR_OR_NULL(musb->xceiv)) { - gpio_free(musb->config->gpio_vrsel); - return -EPROBE_DEFER; - } - - bfin_musb_reg_init(musb); - - timer_setup(&musb->dev_timer, musb_conn_timer_handler, 0); - - musb->xceiv->set_power = bfin_musb_set_power; - - musb->isr = blackfin_interrupt; - musb->double_buffer_not_ok = true; - - return 0; -} - -static int bfin_musb_exit(struct musb *musb) -{ - gpio_free(musb->config->gpio_vrsel); - usb_put_phy(musb->xceiv); - - return 0; -} - -static const struct musb_platform_ops bfin_ops = { - .quirks = MUSB_DMA_INVENTRA, - .init = bfin_musb_init, - .exit = bfin_musb_exit, - - .fifo_offset = bfin_fifo_offset, - .readb = bfin_readb, - .writeb = bfin_writeb, - .readw = bfin_readw, - .writew = bfin_writew, - .readl = bfin_readl, - .writel = bfin_writel, - .fifo_mode = 2, - .read_fifo = bfin_read_fifo, - .write_fifo = bfin_write_fifo, -#ifdef CONFIG_USB_INVENTRA_DMA - .dma_init = musbhs_dma_controller_create, - .dma_exit = musbhs_dma_controller_destroy, -#endif - .enable = bfin_musb_enable, - .disable = bfin_musb_disable, - - .set_mode = bfin_musb_set_mode, - - .vbus_status = bfin_musb_vbus_status, - .set_vbus = bfin_musb_set_vbus, - - .adjust_channel_params = bfin_musb_adjust_channel_params, -}; - -static u64 bfin_dmamask = DMA_BIT_MASK(32); - -static int bfin_probe(struct platform_device *pdev) -{ - struct resource musb_resources[2]; - struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); - struct platform_device *musb; - struct bfin_glue *glue; - - int ret = -ENOMEM; - - glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); - if (!glue) - goto err0; - - musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); - if (!musb) - goto err0; - - musb->dev.parent = &pdev->dev; - musb->dev.dma_mask = &bfin_dmamask; - musb->dev.coherent_dma_mask = bfin_dmamask; - - glue->dev = &pdev->dev; - glue->musb = musb; - - pdata->platform_ops = &bfin_ops; - - glue->phy = usb_phy_generic_register(); - if (IS_ERR(glue->phy)) - goto err1; - platform_set_drvdata(pdev, glue); - - memset(musb_resources, 0x00, sizeof(*musb_resources) * - ARRAY_SIZE(musb_resources)); - - musb_resources[0].name = pdev->resource[0].name; - musb_resources[0].start = pdev->resource[0].start; - musb_resources[0].end = pdev->resource[0].end; - musb_resources[0].flags = pdev->resource[0].flags; - - musb_resources[1].name = pdev->resource[1].name; - musb_resources[1].start = pdev->resource[1].start; - musb_resources[1].end = pdev->resource[1].end; - musb_resources[1].flags = pdev->resource[1].flags; - - ret = platform_device_add_resources(musb, musb_resources, - ARRAY_SIZE(musb_resources)); - if (ret) { - dev_err(&pdev->dev, "failed to add resources\n"); - goto err2; - } - - ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); - if (ret) { - dev_err(&pdev->dev, "failed to add platform_data\n"); - goto err2; - } - - ret = platform_device_add(musb); - if (ret) { - dev_err(&pdev->dev, "failed to register musb device\n"); - goto err2; - } - - return 0; - -err2: - usb_phy_generic_unregister(glue->phy); - -err1: - platform_device_put(musb); - -err0: - return ret; -} - -static int bfin_remove(struct platform_device *pdev) -{ - struct bfin_glue *glue = platform_get_drvdata(pdev); - - platform_device_unregister(glue->musb); - usb_phy_generic_unregister(glue->phy); - - return 0; -} - -static int __maybe_unused bfin_suspend(struct device *dev) -{ - struct bfin_glue *glue = dev_get_drvdata(dev); - struct musb *musb = glue_to_musb(glue); - - if (is_host_active(musb)) - /* - * During hibernate gpio_vrsel will change from high to low - * low which will generate wakeup event resume the system - * immediately. Set it to 0 before hibernate to avoid this - * wakeup event. - */ - gpio_set_value(musb->config->gpio_vrsel, 0); - - return 0; -} - -static int __maybe_unused bfin_resume(struct device *dev) -{ - struct bfin_glue *glue = dev_get_drvdata(dev); - struct musb *musb = glue_to_musb(glue); - - bfin_musb_reg_init(musb); - - return 0; -} - -static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume); - -static struct platform_driver bfin_driver = { - .probe = bfin_probe, - .remove = bfin_remove, - .driver = { - .name = "musb-blackfin", - .pm = &bfin_pm_ops, - }, -}; - -MODULE_DESCRIPTION("Blackfin MUSB Glue Layer"); -MODULE_AUTHOR("Bryan Wy "); -MODULE_LICENSE("GPL v2"); -module_platform_driver(bfin_driver); diff --git a/drivers/usb/musb/blackfin.h b/drivers/usb/musb/blackfin.h deleted file mode 100644 index 5b149915b0f8..000000000000 --- a/drivers/usb/musb/blackfin.h +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2007 by Analog Devices, Inc. - */ - -#ifndef __MUSB_BLACKFIN_H__ -#define __MUSB_BLACKFIN_H__ - -/* - * Blackfin specific definitions - */ - -/* Anomalies notes: - * - * 05000450 - USB DMA Mode 1 Short Packet Data Corruption: - * MUSB driver is designed to transfer buffer of N * maxpacket size - * in DMA mode 1 and leave the rest of the data to the next - * transfer in DMA mode 0, so we never transmit a short packet in - * DMA mode 1. - * - * 05000463 - This anomaly doesn't affect this driver since it - * never uses L1 or L2 memory as data destination. - * - * 05000464 - This anomaly doesn't affect this driver since it - * never uses L1 or L2 memory as data source. - * - * 05000465 - The anomaly can be seen when SCLK is over 100 MHz, and there is - * no way to workaround for bulk endpoints. Since the wMaxPackSize - * of bulk is less than or equal to 512, while the fifo size of - * endpoint 5, 6, 7 is 1024, the double buffer mode is enabled - * automatically when these endpoints are used for bulk OUT. - * - * 05000466 - This anomaly doesn't affect this driver since it never mixes - * concurrent DMA and core accesses to the TX endpoint FIFOs. - * - * 05000467 - The workaround for this anomaly will introduce another - * anomaly - 05000465. - */ - -/* The Mentor USB DMA engine on BF52x (silicon v0.0 and v0.1) seems to be - * unstable in host mode. This may be caused by Anomaly 05000380. After - * digging out the root cause, we will change this number accordingly. - * So, need to either use silicon v0.2+ or disable DMA mode in MUSB. - */ -#if ANOMALY_05000380 && defined(CONFIG_BF52x) && \ - !defined(CONFIG_MUSB_PIO_ONLY) -# error "Please use PIO mode in MUSB driver on bf52x chip v0.0 and v0.1" -#endif - -#undef DUMP_FIFO_DATA -#ifdef DUMP_FIFO_DATA -static void dump_fifo_data(u8 *buf, u16 len) -{ - u8 *tmp = buf; - int i; - - for (i = 0; i < len; i++) { - if (!(i % 16) && i) - pr_debug("\n"); - pr_debug("%02x ", *tmp++); - } - pr_debug("\n"); -} -#else -#define dump_fifo_data(buf, len) do {} while (0) -#endif - - -#define USB_DMA_BASE USB_DMA_INTERRUPT -#define USB_DMAx_CTRL 0x04 -#define USB_DMAx_ADDR_LOW 0x08 -#define USB_DMAx_ADDR_HIGH 0x0C -#define USB_DMAx_COUNT_LOW 0x10 -#define USB_DMAx_COUNT_HIGH 0x14 - -#define USB_DMA_REG(ep, reg) (USB_DMA_BASE + 0x20 * ep + reg) - -/* Almost 1 second */ -#define TIMER_DELAY (1 * HZ) - -#endif /* __MUSB_BLACKFIN_H__ */ diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index eef4ad578b31..13486588e561 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -126,7 +126,6 @@ EXPORT_SYMBOL_GPL(musb_get_mode); /*-------------------------------------------------------------------------*/ -#ifndef CONFIG_BLACKFIN static int musb_ulpi_read(struct usb_phy *phy, u32 reg) { void __iomem *addr = phy->io_priv; @@ -208,10 +207,6 @@ out: return ret; } -#else -#define musb_ulpi_read NULL -#define musb_ulpi_write NULL -#endif static struct usb_phy_io_ops musb_ulpi_access = { .read = musb_ulpi_read, @@ -2171,7 +2166,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) * - initializes musb->xceiv, usually by otg_get_phy() * - stops powering VBUS * - * There are various transceiver configurations. Blackfin, + * There are various transceiver configurations. * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses * external/discrete ones in various flavors (twl4030 family, * isp1504, non-OTG, etc) mostly hooking up through ULPI. diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index 385841ee6f46..8a74cb2907f8 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -414,19 +414,6 @@ struct musb { struct usb_gadget_driver *gadget_driver; /* its driver */ struct usb_hcd *hcd; /* the usb hcd */ - /* - * FIXME: Remove this flag. - * - * This is only added to allow Blackfin to work - * with current driver. For some unknown reason - * Blackfin doesn't work with double buffering - * and that's enabled by default. - * - * We added this flag to forcefully disable double - * buffering until we get it working. - */ - unsigned double_buffer_not_ok:1; - const struct musb_hdrc_config *config; int xceiv_old_state; @@ -467,34 +454,6 @@ static inline char *musb_ep_xfertype_string(u8 type) return s; } -#ifdef CONFIG_BLACKFIN -static inline int musb_read_fifosize(struct musb *musb, - struct musb_hw_ep *hw_ep, u8 epnum) -{ - musb->nr_endpoints++; - musb->epmask |= (1 << epnum); - - if (epnum < 5) { - hw_ep->max_packet_sz_tx = 128; - hw_ep->max_packet_sz_rx = 128; - } else { - hw_ep->max_packet_sz_tx = 1024; - hw_ep->max_packet_sz_rx = 1024; - } - hw_ep->is_shared_fifo = false; - - return 0; -} - -static inline void musb_configure_ep0(struct musb *musb) -{ - musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE; - musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE; - musb->endpoints[0].is_shared_fifo = true; -} - -#else - static inline int musb_read_fifosize(struct musb *musb, struct musb_hw_ep *hw_ep, u8 epnum) { @@ -531,8 +490,6 @@ static inline void musb_configure_ep0(struct musb *musb) musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE; musb->endpoints[0].is_shared_fifo = true; } -#endif /* CONFIG_BLACKFIN */ - /***************************** Glue it together *****************************/ diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c index 7cf5a1bbdaff..7dac456f7ebc 100644 --- a/drivers/usb/musb/musb_debugfs.c +++ b/drivers/usb/musb/musb_debugfs.c @@ -70,7 +70,6 @@ static const struct musb_register_map musb_regmap[] = { { "DMA_CNTLch7", 0x274, 16 }, { "DMA_ADDRch7", 0x278, 32 }, { "DMA_COUNTch7", 0x27C, 32 }, -#ifndef CONFIG_BLACKFIN { "ConfigData", MUSB_CONFIGDATA,8 }, { "BabbleCtl", MUSB_BABBLE_CTL,8 }, { "TxFIFOsz", MUSB_TXFIFOSZ, 8 }, @@ -79,7 +78,6 @@ static const struct musb_register_map musb_regmap[] = { { "RxFIFOadd", MUSB_RXFIFOADD, 16 }, { "EPInfo", MUSB_EPINFO, 8 }, { "RAMInfo", MUSB_RAMINFO, 8 }, -#endif { } /* Terminating Entry */ }; diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h index a4241f4d430e..0fc8cd0c2a5c 100644 --- a/drivers/usb/musb/musb_dma.h +++ b/drivers/usb/musb/musb_dma.h @@ -80,17 +80,6 @@ struct musb_hw_ep; #define is_cppi_enabled(musb) 0 #endif -/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1 - * Only allow DMA mode 1 to be used when the USB will actually generate the - * interrupts we expect. - */ -#ifdef CONFIG_BLACKFIN -# undef USE_MODE1 -# if !ANOMALY_05000456 -# define USE_MODE1 -# endif -#endif - /* * DMA channel status ... updated by the dma controller driver whenever that * status changes, and protected by the overall controller spinlock. diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c index 293e5b8da565..e564695c6c8d 100644 --- a/drivers/usb/musb/musb_gadget.c +++ b/drivers/usb/musb/musb_gadget.c @@ -995,15 +995,11 @@ static int musb_gadget_enable(struct usb_ep *ep, /* Set TXMAXP with the FIFO size of the endpoint * to disable double buffering mode. */ - if (musb->double_buffer_not_ok) { - musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); - } else { - if (can_bulk_split(musb, musb_ep->type)) - musb_ep->hb_mult = (hw_ep->max_packet_sz_tx / - musb_ep->packet_sz) - 1; - musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz - | (musb_ep->hb_mult << 11)); - } + if (can_bulk_split(musb, musb_ep->type)) + musb_ep->hb_mult = (hw_ep->max_packet_sz_tx / + musb_ep->packet_sz) - 1; + musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz + | (musb_ep->hb_mult << 11)); csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; if (musb_readw(regs, MUSB_TXCSR) @@ -1038,11 +1034,8 @@ static int musb_gadget_enable(struct usb_ep *ep, /* Set RXMAXP with the FIFO size of the endpoint * to disable double buffering mode. */ - if (musb->double_buffer_not_ok) - musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); - else - musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz - | (musb_ep->hb_mult << 11)); + musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz + | (musb_ep->hb_mult << 11)); /* force shared fifo to OUT-only mode */ if (hw_ep->is_shared_fifo) { @@ -1680,40 +1673,6 @@ static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) return 0; } -#ifdef CONFIG_BLACKFIN -static struct usb_ep *musb_match_ep(struct usb_gadget *g, - struct usb_endpoint_descriptor *desc, - struct usb_ss_ep_comp_descriptor *ep_comp) -{ - struct usb_ep *ep = NULL; - - switch (usb_endpoint_type(desc)) { - case USB_ENDPOINT_XFER_ISOC: - case USB_ENDPOINT_XFER_BULK: - if (usb_endpoint_dir_in(desc)) - ep = gadget_find_ep_by_name(g, "ep5in"); - else - ep = gadget_find_ep_by_name(g, "ep6out"); - break; - case USB_ENDPOINT_XFER_INT: - if (usb_endpoint_dir_in(desc)) - ep = gadget_find_ep_by_name(g, "ep1in"); - else - ep = gadget_find_ep_by_name(g, "ep2out"); - break; - default: - break; - } - - if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp)) - return ep; - - return NULL; -} -#else -#define musb_match_ep NULL -#endif - static int musb_gadget_start(struct usb_gadget *g, struct usb_gadget_driver *driver); static int musb_gadget_stop(struct usb_gadget *g); @@ -1727,7 +1686,6 @@ static const struct usb_gadget_ops musb_gadget_operations = { .pullup = musb_gadget_pullup, .udc_start = musb_gadget_start, .udc_stop = musb_gadget_stop, - .match_ep = musb_match_ep, }; /* ----------------------------------------------------------------------- */ diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index 45ed32c2cba9..3a8451a15f7f 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -574,11 +574,8 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum) /* Set RXMAXP with the FIFO size of the endpoint * to disable double buffer mode. */ - if (musb->double_buffer_not_ok) - musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); - else - musb_writew(ep->regs, MUSB_RXMAXP, - qh->maxpacket | ((qh->hb_mult - 1) << 11)); + musb_writew(ep->regs, MUSB_RXMAXP, + qh->maxpacket | ((qh->hb_mult - 1) << 11)); ep->rx_reinit = 0; } @@ -804,10 +801,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum, /* protocol/endpoint/interval/NAKlimit */ if (epnum) { musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); - if (musb->double_buffer_not_ok) { - musb_writew(epio, MUSB_TXMAXP, - hw_ep->max_packet_sz_tx); - } else if (can_bulk_split(musb, qh->type)) { + if (can_bulk_split(musb, qh->type)) { qh->hb_mult = hw_ep->max_packet_sz_tx / packet_sz; musb_writew(epio, MUSB_TXMAXP, packet_sz diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h index a4beba184798..88466622c89f 100644 --- a/drivers/usb/musb/musb_regs.h +++ b/drivers/usb/musb/musb_regs.h @@ -195,8 +195,6 @@ #define MUSB_HUBADDR_MULTI_TT 0x80 -#ifndef CONFIG_BLACKFIN - /* * Common USB registers */ @@ -416,184 +414,4 @@ static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum) musb->io.busctl_offset(epnum, MUSB_TXHUBPORT)); } -#else /* CONFIG_BLACKFIN */ - -#define USB_BASE USB_FADDR -#define USB_OFFSET(reg) (reg - USB_BASE) - -/* - * Common USB registers - */ -#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */ -#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */ -#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */ -#define MUSB_INTRRX USB_OFFSET(USB_INTRRX) -#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE) -#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE) -#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */ -#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */ -#define MUSB_FRAME USB_OFFSET(USB_FRAME) -#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */ -#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */ - -/* - * Additional Control Registers - */ - -#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */ - -#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */ -#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */ -#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */ -#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */ -#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */ - -/* Offsets to endpoint registers */ -#define MUSB_TXMAXP 0x00 -#define MUSB_TXCSR 0x04 -#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ -#define MUSB_RXMAXP 0x08 -#define MUSB_RXCSR 0x0C -#define MUSB_RXCOUNT 0x10 -#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ -#define MUSB_TXTYPE 0x14 -#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ -#define MUSB_TXINTERVAL 0x18 -#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ -#define MUSB_RXTYPE 0x1C -#define MUSB_RXINTERVAL 0x20 -#define MUSB_TXCOUNT 0x28 - -/* Offsets to endpoint registers in indexed model (using INDEX register) */ -#define MUSB_INDEXED_OFFSET(_epnum, _offset) \ - (0x40 + (_offset)) - -/* Offsets to endpoint registers in flat models */ -#define MUSB_FLAT_OFFSET(_epnum, _offset) \ - (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset)) - -/* Not implemented - HW has separate Tx/Rx FIFO */ -#define MUSB_TXCSR_MODE 0x0000 - -static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size) -{ -} - -static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off) -{ -} - -static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size) -{ -} - -static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off) -{ -} - -static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val) -{ -} - -static inline u8 musb_read_txfifosz(void __iomem *mbase) -{ - return 0; -} - -static inline u16 musb_read_txfifoadd(void __iomem *mbase) -{ - return 0; -} - -static inline u8 musb_read_rxfifosz(void __iomem *mbase) -{ - return 0; -} - -static inline u16 musb_read_rxfifoadd(void __iomem *mbase) -{ - return 0; -} - -static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) -{ - return 0; -} - -static inline u8 musb_read_configdata(void __iomem *mbase) -{ - return 0; -} - -static inline u16 musb_read_hwvers(void __iomem *mbase) -{ - /* - * This register is invisible on Blackfin, actually the MUSB - * RTL version of Blackfin is 1.9, so just hardcode its value. - */ - return MUSB_HWVERS_1900; -} - -static inline void musb_write_rxfunaddr(void __iomem *mbase, u8 epnum, - u8 qh_addr_req) -{ -} - -static inline void musb_write_rxhubaddr(void __iomem *mbase, u8 epnum, - u8 qh_h_addr_reg) -{ -} - -static inline void musb_write_rxhubport(void __iomem *mbase, u8 epnum, - u8 qh_h_port_reg) -{ -} - -static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum, - u8 qh_addr_reg) -{ -} - -static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum, - u8 qh_addr_reg) -{ -} - -static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum, - u8 qh_h_port_reg) -{ -} - -static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum) -{ - return 0; -} - -static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum) -{ - return 0; -} - -static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum) -{ - return 0; -} - -static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum) -{ - return 0; -} - -static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum) -{ - return 0; -} - -static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum) -{ - return 0; -} - -#endif /* CONFIG_BLACKFIN */ - #endif /* __MUSB_REGS_H__ */ diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c index 21fb9e6622f3..4389fc3422bd 100644 --- a/drivers/usb/musb/musbhsdma.c +++ b/drivers/usb/musb/musbhsdma.c @@ -235,11 +235,6 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data) int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); -#ifdef CONFIG_BLACKFIN - /* Clear DMA interrupt flags */ - musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); -#endif - if (!int_hsdma) { musb_dbg(musb, "spurious DMA irq"); diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h index 44f7983df0a1..93665135aff1 100644 --- a/drivers/usb/musb/musbhsdma.h +++ b/drivers/usb/musb/musbhsdma.h @@ -6,8 +6,6 @@ * Copyright (C) 2005-2007 by Texas Instruments */ -#ifndef CONFIG_BLACKFIN - #define MUSB_HSDMA_BASE 0x200 #define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0) #define MUSB_HSDMA_CONTROL 0x4 @@ -34,68 +32,6 @@ musb_writel(mbase, \ MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \ len) -#else - -#define MUSB_HSDMA_BASE 0x400 -#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0) -#define MUSB_HSDMA_CONTROL 0x04 -#define MUSB_HSDMA_ADDR_LOW 0x08 -#define MUSB_HSDMA_ADDR_HIGH 0x0C -#define MUSB_HSDMA_COUNT_LOW 0x10 -#define MUSB_HSDMA_COUNT_HIGH 0x14 - -#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \ - (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset) - -static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel) -{ - u32 addr = musb_readw(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH)); - - addr = addr << 16; - - addr |= musb_readw(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW)); - - return addr; -} - -static inline void musb_write_hsdma_addr(void __iomem *mbase, - u8 bchannel, dma_addr_t dma_addr) -{ - musb_writew(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW), - dma_addr); - musb_writew(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH), - (dma_addr >> 16)); -} - -static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel) -{ - u32 count = musb_readw(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH)); - - count = count << 16; - - count |= musb_readw(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW)); - - return count; -} - -static inline void musb_write_hsdma_count(void __iomem *mbase, - u8 bchannel, u32 len) -{ - musb_writew(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len); - musb_writew(mbase, - MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH), - (len >> 16)); -} - -#endif /* CONFIG_BLACKFIN */ - /* control register (16-bit): */ #define MUSB_HSDMA_ENABLE_SHIFT 0 #define MUSB_HSDMA_TRANSMIT_SHIFT 1 diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h index 5d19e6730475..9eb908a98033 100644 --- a/include/linux/usb/musb.h +++ b/include/linux/usb/musb.h @@ -89,13 +89,6 @@ struct musb_hdrc_config { u8 ram_bits; /* ram address size */ struct musb_hdrc_eps_bits *eps_bits __deprecated; -#ifdef CONFIG_BLACKFIN - /* A GPIO controlling VRSEL in Blackfin */ - unsigned int gpio_vrsel; - unsigned int gpio_vrsel_active; - /* musb CLKIN in Blackfin in MHZ */ - unsigned char clkin; -#endif u32 maximum_speed; }; -- cgit v1.2.3 From a470143fc83924251647143ff042bd2843e296cf Mon Sep 17 00:00:00 2001 From: Sagi Grimberg Date: Wed, 24 Jan 2018 20:24:24 +0200 Subject: net/utils: Introduce inet_addr_is_any Can be useful to check INET_ANY address for both ipv4/ipv6 addresses. Reviewed-by: Bart Van Assche Signed-off-by: Sagi Grimberg Cc: "David S. Miller" Cc: netdev@vger.kernel.org Signed-off-by: Jens Axboe --- include/linux/inet.h | 1 + net/core/utils.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'include/linux') diff --git a/include/linux/inet.h b/include/linux/inet.h index 636ebe87e6f8..97defc1139e9 100644 --- a/include/linux/inet.h +++ b/include/linux/inet.h @@ -59,5 +59,6 @@ extern int in6_pton(const char *src, int srclen, u8 *dst, int delim, const char extern int inet_pton_with_scope(struct net *net, unsigned short af, const char *src, const char *port, struct sockaddr_storage *addr); +extern bool inet_addr_is_any(struct sockaddr *addr); #endif /* _LINUX_INET_H */ diff --git a/net/core/utils.c b/net/core/utils.c index 93066bd0305a..d47863b07a60 100644 --- a/net/core/utils.c +++ b/net/core/utils.c @@ -403,6 +403,29 @@ int inet_pton_with_scope(struct net *net, __kernel_sa_family_t af, } EXPORT_SYMBOL(inet_pton_with_scope); +bool inet_addr_is_any(struct sockaddr *addr) +{ + if (addr->sa_family == AF_INET6) { + struct sockaddr_in6 *in6 = (struct sockaddr_in6 *)addr; + const struct sockaddr_in6 in6_any = + { .sin6_addr = IN6ADDR_ANY_INIT }; + + if (!memcmp(in6->sin6_addr.s6_addr, + in6_any.sin6_addr.s6_addr, 16)) + return true; + } else if (addr->sa_family == AF_INET) { + struct sockaddr_in *in = (struct sockaddr_in *)addr; + + if (in->sin_addr.s_addr == htonl(INADDR_ANY)) + return true; + } else { + pr_warn("unexpected address family %u\n", addr->sa_family); + } + + return false; +} +EXPORT_SYMBOL(inet_addr_is_any); + void inet_proto_csum_replace4(__sum16 *sum, struct sk_buff *skb, __be32 from, __be32 to, bool pseudohdr) { -- cgit v1.2.3 From ede2762d93ff16e0974f7446516b46b1022db213 Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Fri, 23 Mar 2018 19:47:19 +0300 Subject: net: Make NETDEV_XXX commands enum { } This patch is preparation to drop NETDEV_UNREGISTER_FINAL. Since the cmd is used in usnic_ib_netdev_event_to_string() to get cmd name, after plain removing NETDEV_UNREGISTER_FINAL from everywhere, we'd have holes in event2str[] in this function. Instead of that, let's make NETDEV_XXX commands names available for everyone, and to define netdev_cmd_to_name() in the way we won't have to shaffle names after their numbers are changed. Signed-off-by: Kirill Tkhai Signed-off-by: David S. Miller --- drivers/infiniband/hw/usnic/usnic_ib_main.c | 15 +------ include/linux/netdevice.h | 69 +++++++++++++++-------------- net/core/dev.c | 20 +++++++++ 3 files changed, 57 insertions(+), 47 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/usnic/usnic_ib_main.c b/drivers/infiniband/hw/usnic/usnic_ib_main.c index f45e99a938e0..5bf3b20eba25 100644 --- a/drivers/infiniband/hw/usnic/usnic_ib_main.c +++ b/drivers/infiniband/hw/usnic/usnic_ib_main.c @@ -97,20 +97,7 @@ void usnic_ib_log_vf(struct usnic_ib_vf *vf) /* Start of netdev section */ static inline const char *usnic_ib_netdev_event_to_string(unsigned long event) { - const char *event2str[] = {"NETDEV_NONE", "NETDEV_UP", "NETDEV_DOWN", - "NETDEV_REBOOT", "NETDEV_CHANGE", - "NETDEV_REGISTER", "NETDEV_UNREGISTER", "NETDEV_CHANGEMTU", - "NETDEV_CHANGEADDR", "NETDEV_GOING_DOWN", "NETDEV_FEAT_CHANGE", - "NETDEV_BONDING_FAILOVER", "NETDEV_PRE_UP", - "NETDEV_PRE_TYPE_CHANGE", "NETDEV_POST_TYPE_CHANGE", - "NETDEV_POST_INT", "NETDEV_UNREGISTER_FINAL", "NETDEV_RELEASE", - "NETDEV_NOTIFY_PEERS", "NETDEV_JOIN" - }; - - if (event >= ARRAY_SIZE(event2str)) - return "UNKNOWN_NETDEV_EVENT"; - else - return event2str[event]; + return netdev_cmd_to_name(event); } static void usnic_ib_qp_grp_modify_active_to_err(struct usnic_ib_dev *us_ibdev) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 913b1cc882cf..dd5a04c971d5 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -2312,43 +2312,46 @@ struct netdev_lag_lower_state_info { #include -/* netdevice notifier chain. Please remember to update the rtnetlink - * notification exclusion list in rtnetlink_event() when adding new - * types. +/* netdevice notifier chain. Please remember to update netdev_cmd_to_name() + * and the rtnetlink notification exclusion list in rtnetlink_event() when + * adding new types. */ -#define NETDEV_UP 0x0001 /* For now you can't veto a device up/down */ -#define NETDEV_DOWN 0x0002 -#define NETDEV_REBOOT 0x0003 /* Tell a protocol stack a network interface +enum netdev_cmd { + NETDEV_UP = 1, /* For now you can't veto a device up/down */ + NETDEV_DOWN, + NETDEV_REBOOT, /* Tell a protocol stack a network interface detected a hardware crash and restarted - we can use this eg to kick tcp sessions once done */ -#define NETDEV_CHANGE 0x0004 /* Notify device state change */ -#define NETDEV_REGISTER 0x0005 -#define NETDEV_UNREGISTER 0x0006 -#define NETDEV_CHANGEMTU 0x0007 /* notify after mtu change happened */ -#define NETDEV_CHANGEADDR 0x0008 -#define NETDEV_GOING_DOWN 0x0009 -#define NETDEV_CHANGENAME 0x000A -#define NETDEV_FEAT_CHANGE 0x000B -#define NETDEV_BONDING_FAILOVER 0x000C -#define NETDEV_PRE_UP 0x000D -#define NETDEV_PRE_TYPE_CHANGE 0x000E -#define NETDEV_POST_TYPE_CHANGE 0x000F -#define NETDEV_POST_INIT 0x0010 -#define NETDEV_UNREGISTER_FINAL 0x0011 -#define NETDEV_RELEASE 0x0012 -#define NETDEV_NOTIFY_PEERS 0x0013 -#define NETDEV_JOIN 0x0014 -#define NETDEV_CHANGEUPPER 0x0015 -#define NETDEV_RESEND_IGMP 0x0016 -#define NETDEV_PRECHANGEMTU 0x0017 /* notify before mtu change happened */ -#define NETDEV_CHANGEINFODATA 0x0018 -#define NETDEV_BONDING_INFO 0x0019 -#define NETDEV_PRECHANGEUPPER 0x001A -#define NETDEV_CHANGELOWERSTATE 0x001B -#define NETDEV_UDP_TUNNEL_PUSH_INFO 0x001C -#define NETDEV_UDP_TUNNEL_DROP_INFO 0x001D -#define NETDEV_CHANGE_TX_QUEUE_LEN 0x001E + NETDEV_CHANGE, /* Notify device state change */ + NETDEV_REGISTER, + NETDEV_UNREGISTER, + NETDEV_CHANGEMTU, /* notify after mtu change happened */ + NETDEV_CHANGEADDR, + NETDEV_GOING_DOWN, + NETDEV_CHANGENAME, + NETDEV_FEAT_CHANGE, + NETDEV_BONDING_FAILOVER, + NETDEV_PRE_UP, + NETDEV_PRE_TYPE_CHANGE, + NETDEV_POST_TYPE_CHANGE, + NETDEV_POST_INIT, + NETDEV_UNREGISTER_FINAL, + NETDEV_RELEASE, + NETDEV_NOTIFY_PEERS, + NETDEV_JOIN, + NETDEV_CHANGEUPPER, + NETDEV_RESEND_IGMP, + NETDEV_PRECHANGEMTU, /* notify before mtu change happened */ + NETDEV_CHANGEINFODATA, + NETDEV_BONDING_INFO, + NETDEV_PRECHANGEUPPER, + NETDEV_CHANGELOWERSTATE, + NETDEV_UDP_TUNNEL_PUSH_INFO, + NETDEV_UDP_TUNNEL_DROP_INFO, + NETDEV_CHANGE_TX_QUEUE_LEN, +}; +const char *netdev_cmd_to_name(enum netdev_cmd cmd); int register_netdevice_notifier(struct notifier_block *nb); int unregister_netdevice_notifier(struct notifier_block *nb); diff --git a/net/core/dev.c b/net/core/dev.c index f9c28f44286c..055e7ae12759 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -1571,6 +1571,26 @@ static void dev_disable_gro_hw(struct net_device *dev) netdev_WARN(dev, "failed to disable GRO_HW!\n"); } +const char *netdev_cmd_to_name(enum netdev_cmd cmd) +{ +#define N(val) \ + case NETDEV_##val: \ + return "NETDEV_" __stringify(val); + switch (cmd) { + N(UP) N(DOWN) N(REBOOT) N(CHANGE) N(REGISTER) N(UNREGISTER) + N(CHANGEMTU) N(CHANGEADDR) N(GOING_DOWN) N(CHANGENAME) N(FEAT_CHANGE) + N(BONDING_FAILOVER) N(PRE_UP) N(PRE_TYPE_CHANGE) N(POST_TYPE_CHANGE) + N(POST_INIT) N(RELEASE) N(NOTIFY_PEERS) N(JOIN) N(CHANGEUPPER) + N(RESEND_IGMP) N(PRECHANGEMTU) N(CHANGEINFODATA) N(BONDING_INFO) + N(PRECHANGEUPPER) N(CHANGELOWERSTATE) N(UDP_TUNNEL_PUSH_INFO) + N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN) + N(UNREGISTER_FINAL) + }; +#undef N + return "UNKNOWN_NETDEV_EVENT"; +} +EXPORT_SYMBOL_GPL(netdev_cmd_to_name); + static int call_netdevice_notifier(struct notifier_block *nb, unsigned long val, struct net_device *dev) { -- cgit v1.2.3 From 070f2d7e264acd6316fc24092b7f51a18c75ac9c Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Fri, 23 Mar 2018 19:47:39 +0300 Subject: net: Drop NETDEV_UNREGISTER_FINAL Last user is gone after bdf5bd7f2132 "rds: tcp: remove register_netdevice_notifier infrastructure.", so we can remove this netdevice command. This allows to delete rtnl_lock() in netdev_run_todo(), which is hot path for net namespace unregistration. dev_change_net_namespace() and netdev_wait_allrefs() have rcu_barrier() before NETDEV_UNREGISTER_FINAL call, and the source commits say they were introduced to delemit the call with NETDEV_UNREGISTER, but this patch leaves them on the places, since they require additional analysis, whether we need in them for something else. Signed-off-by: Kirill Tkhai Signed-off-by: David S. Miller --- drivers/infiniband/hw/qedr/main.c | 4 ++-- include/linux/netdevice.h | 1 - include/rdma/ib_verbs.h | 4 ++-- net/core/dev.c | 7 ------- 4 files changed, 4 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/qedr/main.c b/drivers/infiniband/hw/qedr/main.c index db4bf97c0e15..eb32abb0099a 100644 --- a/drivers/infiniband/hw/qedr/main.c +++ b/drivers/infiniband/hw/qedr/main.c @@ -90,8 +90,8 @@ static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num) dev_hold(qdev->ndev); /* The HW vendor's device driver must guarantee - * that this function returns NULL before the net device reaches - * NETDEV_UNREGISTER_FINAL state. + * that this function returns NULL before the net device has finished + * NETDEV_UNREGISTER state. */ return qdev->ndev; } diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index dd5a04c971d5..2a2d9cf50aa2 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -2336,7 +2336,6 @@ enum netdev_cmd { NETDEV_PRE_TYPE_CHANGE, NETDEV_POST_TYPE_CHANGE, NETDEV_POST_INIT, - NETDEV_UNREGISTER_FINAL, NETDEV_RELEASE, NETDEV_NOTIFY_PEERS, NETDEV_JOIN, diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index ff3ed435701f..6eb174753acf 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -2122,8 +2122,8 @@ struct ib_device { * net device of device @device at port @port_num or NULL if such * a net device doesn't exist. The vendor driver should call dev_hold * on this net device. The HW vendor's device driver must guarantee - * that this function returns NULL before the net device reaches - * NETDEV_UNREGISTER_FINAL state. + * that this function returns NULL before the net device has finished + * NETDEV_UNREGISTER state. */ struct net_device *(*get_netdev)(struct ib_device *device, u8 port_num); diff --git a/net/core/dev.c b/net/core/dev.c index 055e7ae12759..97a96df4b6da 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -1584,7 +1584,6 @@ const char *netdev_cmd_to_name(enum netdev_cmd cmd) N(RESEND_IGMP) N(PRECHANGEMTU) N(CHANGEINFODATA) N(BONDING_INFO) N(PRECHANGEUPPER) N(CHANGELOWERSTATE) N(UDP_TUNNEL_PUSH_INFO) N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN) - N(UNREGISTER_FINAL) }; #undef N return "UNKNOWN_NETDEV_EVENT"; @@ -8097,7 +8096,6 @@ static void netdev_wait_allrefs(struct net_device *dev) rcu_barrier(); rtnl_lock(); - call_netdevice_notifiers(NETDEV_UNREGISTER_FINAL, dev); if (test_bit(__LINK_STATE_LINKWATCH_PENDING, &dev->state)) { /* We must not have linkwatch events @@ -8169,10 +8167,6 @@ void netdev_run_todo(void) = list_first_entry(&list, struct net_device, todo_list); list_del(&dev->todo_list); - rtnl_lock(); - call_netdevice_notifiers(NETDEV_UNREGISTER_FINAL, dev); - __rtnl_unlock(); - if (unlikely(dev->reg_state != NETREG_UNREGISTERING)) { pr_err("network todo '%s' but state %d\n", dev->name, dev->reg_state); @@ -8614,7 +8608,6 @@ int dev_change_net_namespace(struct net_device *dev, struct net *net, const char */ call_netdevice_notifiers(NETDEV_UNREGISTER, dev); rcu_barrier(); - call_netdevice_notifiers(NETDEV_UNREGISTER_FINAL, dev); new_nsid = peernet2id_alloc(dev_net(dev), net); /* If there is an ifindex conflict assign a new one */ -- cgit v1.2.3 From bc67a0daf8f3bc6fa8fcb68090f3c444de7f951c Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Mon, 26 Mar 2018 15:01:31 +0300 Subject: ipmr: Make vif fib notifiers common The fib-notifiers are tightly coupled with the vif_device which is already common. Move the notifier struct definition and helpers to the common file; Currently they're only used by ipmr. Signed-off-by: Yuval Mintz Signed-off-by: Ido Schimmel Signed-off-by: David S. Miller --- include/linux/mroute.h | 8 ------- include/linux/mroute_base.h | 53 +++++++++++++++++++++++++++++++++++++++++++++ net/ipv4/ipmr.c | 31 +++++--------------------- 3 files changed, 58 insertions(+), 34 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute.h b/include/linux/mroute.h index 7ed82e4f11b3..3f70a04a5879 100644 --- a/include/linux/mroute.h +++ b/include/linux/mroute.h @@ -55,14 +55,6 @@ static inline bool ipmr_rule_default(const struct fib_rule *rule) } #endif -struct vif_entry_notifier_info { - struct fib_notifier_info info; - struct net_device *dev; - vifi_t vif_index; - unsigned short vif_flags; - u32 tb_id; -}; - #define VIFF_STATIC 0x8000 struct mfc_cache_cmp_arg { diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index c2560cb50f1d..23326f5402f3 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -6,6 +6,7 @@ #include #include #include +#include /** * struct vif_device - interface representor for multicast routing @@ -36,6 +37,58 @@ struct vif_device { __be32 local, remote; }; +struct vif_entry_notifier_info { + struct fib_notifier_info info; + struct net_device *dev; + unsigned short vif_index; + unsigned short vif_flags; + u32 tb_id; +}; + +static inline int mr_call_vif_notifier(struct notifier_block *nb, + struct net *net, + unsigned short family, + enum fib_event_type event_type, + struct vif_device *vif, + unsigned short vif_index, u32 tb_id) +{ + struct vif_entry_notifier_info info = { + .info = { + .family = family, + .net = net, + }, + .dev = vif->dev, + .vif_index = vif_index, + .vif_flags = vif->flags, + .tb_id = tb_id, + }; + + return call_fib_notifier(nb, net, event_type, &info.info); +} + +static inline int mr_call_vif_notifiers(struct net *net, + unsigned short family, + enum fib_event_type event_type, + struct vif_device *vif, + unsigned short vif_index, u32 tb_id, + unsigned int *ipmr_seq) +{ + struct vif_entry_notifier_info info = { + .info = { + .family = family, + .net = net, + }, + .dev = vif->dev, + .vif_index = vif_index, + .vif_flags = vif->flags, + .tb_id = tb_id, + }; + + ASSERT_RTNL(); + (*ipmr_seq)++; + return call_fib_notifiers(net, event_type, &info.info); +} + #ifndef MAXVIFS /* This one is nasty; value is defined in uapi using different symbols for * mroute and morute6 but both map into same 32. diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index f6be5db16da2..bb1a0655f8e4 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -650,18 +650,8 @@ static int call_ipmr_vif_entry_notifier(struct notifier_block *nb, struct vif_device *vif, vifi_t vif_index, u32 tb_id) { - struct vif_entry_notifier_info info = { - .info = { - .family = RTNL_FAMILY_IPMR, - .net = net, - }, - .dev = vif->dev, - .vif_index = vif_index, - .vif_flags = vif->flags, - .tb_id = tb_id, - }; - - return call_fib_notifier(nb, net, event_type, &info.info); + return mr_call_vif_notifier(nb, net, RTNL_FAMILY_IPMR, event_type, + vif, vif_index, tb_id); } static int call_ipmr_vif_entry_notifiers(struct net *net, @@ -669,20 +659,9 @@ static int call_ipmr_vif_entry_notifiers(struct net *net, struct vif_device *vif, vifi_t vif_index, u32 tb_id) { - struct vif_entry_notifier_info info = { - .info = { - .family = RTNL_FAMILY_IPMR, - .net = net, - }, - .dev = vif->dev, - .vif_index = vif_index, - .vif_flags = vif->flags, - .tb_id = tb_id, - }; - - ASSERT_RTNL(); - net->ipv4.ipmr_seq++; - return call_fib_notifiers(net, event_type, &info.info); + return mr_call_vif_notifiers(net, RTNL_FAMILY_IPMR, event_type, + vif, vif_index, tb_id, + &net->ipv4.ipmr_seq); } static int call_ipmr_mfc_entry_notifier(struct notifier_block *nb, -- cgit v1.2.3 From 54c4cad97b8fd414909b78d4274a6797baa52b3b Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Mon, 26 Mar 2018 15:01:32 +0300 Subject: ipmr: Make MFC fib notifiers common Like vif notifications, move the notifier struct for MFC as well as its helpers into a common file; Currently they're only used by ipmr. Signed-off-by: Yuval Mintz Signed-off-by: Ido Schimmel Signed-off-by: David S. Miller --- .../net/ethernet/mellanox/mlxsw/spectrum_router.c | 13 ++++--- include/linux/mroute.h | 6 --- include/linux/mroute_base.h | 44 ++++++++++++++++++++++ net/ipv4/ipmr.c | 26 ++----------- 4 files changed, 56 insertions(+), 33 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c index 921bd1075edf..8d067de924cf 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c @@ -5391,7 +5391,9 @@ static int mlxsw_sp_router_fibmr_add(struct mlxsw_sp *mlxsw_sp, if (IS_ERR(vr)) return PTR_ERR(vr); - return mlxsw_sp_mr_route4_add(vr->mr4_table, men_info->mfc, replace); + return mlxsw_sp_mr_route4_add(vr->mr4_table, + (struct mfc_cache *) men_info->mfc, + replace); } static void mlxsw_sp_router_fibmr_del(struct mlxsw_sp *mlxsw_sp, @@ -5406,7 +5408,8 @@ static void mlxsw_sp_router_fibmr_del(struct mlxsw_sp *mlxsw_sp, if (WARN_ON(!vr)) return; - mlxsw_sp_mr_route4_del(vr->mr4_table, men_info->mfc); + mlxsw_sp_mr_route4_del(vr->mr4_table, + (struct mfc_cache *) men_info->mfc); mlxsw_sp_vr_put(mlxsw_sp, vr); } @@ -5682,11 +5685,11 @@ static void mlxsw_sp_router_fibmr_event_work(struct work_struct *work) replace); if (err) mlxsw_sp_router_fib_abort(mlxsw_sp); - ipmr_cache_put(fib_work->men_info.mfc); + ipmr_cache_put((struct mfc_cache *) fib_work->men_info.mfc); break; case FIB_EVENT_ENTRY_DEL: mlxsw_sp_router_fibmr_del(mlxsw_sp, &fib_work->men_info); - ipmr_cache_put(fib_work->men_info.mfc); + ipmr_cache_put((struct mfc_cache *) fib_work->men_info.mfc); break; case FIB_EVENT_VIF_ADD: err = mlxsw_sp_router_fibmr_vif_add(mlxsw_sp, @@ -5766,7 +5769,7 @@ mlxsw_sp_router_fibmr_event(struct mlxsw_sp_fib_event_work *fib_work, case FIB_EVENT_ENTRY_ADD: /* fall through */ case FIB_EVENT_ENTRY_DEL: memcpy(&fib_work->men_info, info, sizeof(fib_work->men_info)); - ipmr_cache_hold(fib_work->men_info.mfc); + ipmr_cache_hold((struct mfc_cache *) fib_work->men_info.mfc); break; case FIB_EVENT_VIF_ADD: /* fall through */ case FIB_EVENT_VIF_DEL: diff --git a/include/linux/mroute.h b/include/linux/mroute.h index 3f70a04a5879..c855d80b51f7 100644 --- a/include/linux/mroute.h +++ b/include/linux/mroute.h @@ -80,12 +80,6 @@ struct mfc_cache { }; }; -struct mfc_entry_notifier_info { - struct fib_notifier_info info; - struct mfc_cache *mfc; - u32 tb_id; -}; - struct rtmsg; int ipmr_get_route(struct net *net, struct sk_buff *skb, __be32 saddr, __be32 daddr, diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 23326f5402f3..2c594686c05e 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -152,6 +152,50 @@ struct mr_mfc { struct rcu_head rcu; }; +struct mfc_entry_notifier_info { + struct fib_notifier_info info; + struct mr_mfc *mfc; + u32 tb_id; +}; + +static inline int mr_call_mfc_notifier(struct notifier_block *nb, + struct net *net, + unsigned short family, + enum fib_event_type event_type, + struct mr_mfc *mfc, u32 tb_id) +{ + struct mfc_entry_notifier_info info = { + .info = { + .family = family, + .net = net, + }, + .mfc = mfc, + .tb_id = tb_id + }; + + return call_fib_notifier(nb, net, event_type, &info.info); +} + +static inline int mr_call_mfc_notifiers(struct net *net, + unsigned short family, + enum fib_event_type event_type, + struct mr_mfc *mfc, u32 tb_id, + unsigned int *ipmr_seq) +{ + struct mfc_entry_notifier_info info = { + .info = { + .family = family, + .net = net, + }, + .mfc = mfc, + .tb_id = tb_id + }; + + ASSERT_RTNL(); + (*ipmr_seq)++; + return call_fib_notifiers(net, event_type, &info.info); +} + struct mr_table; /** diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index bb1a0655f8e4..470956d2d8ad 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -669,34 +669,16 @@ static int call_ipmr_mfc_entry_notifier(struct notifier_block *nb, enum fib_event_type event_type, struct mfc_cache *mfc, u32 tb_id) { - struct mfc_entry_notifier_info info = { - .info = { - .family = RTNL_FAMILY_IPMR, - .net = net, - }, - .mfc = mfc, - .tb_id = tb_id - }; - - return call_fib_notifier(nb, net, event_type, &info.info); + return mr_call_mfc_notifier(nb, net, RTNL_FAMILY_IPMR, + event_type, &mfc->_c, tb_id); } static int call_ipmr_mfc_entry_notifiers(struct net *net, enum fib_event_type event_type, struct mfc_cache *mfc, u32 tb_id) { - struct mfc_entry_notifier_info info = { - .info = { - .family = RTNL_FAMILY_IPMR, - .net = net, - }, - .mfc = mfc, - .tb_id = tb_id - }; - - ASSERT_RTNL(); - net->ipv4.ipmr_seq++; - return call_fib_notifiers(net, event_type, &info.info); + return mr_call_mfc_notifiers(net, RTNL_FAMILY_IPMR, event_type, + &mfc->_c, tb_id, &net->ipv4.ipmr_seq); } /** -- cgit v1.2.3 From cdc9f9443b5c3a61c7cec807965054ee1fd29acf Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Mon, 26 Mar 2018 15:01:33 +0300 Subject: ipmr: Make ipmr_dump() common Since all the primitive elements used for the notification done by ipmr are now common [mr_table, mr_mfc, vif_device] we can refactor the logic for dumping them to a common file. Signed-off-by: Yuval Mintz Signed-off-by: Ido Schimmel Signed-off-by: David S. Miller --- include/linux/mroute_base.h | 18 +++++++++++++++ net/ipv4/ipmr.c | 53 ++------------------------------------------- net/ipv4/ipmr_base.c | 42 +++++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 51 deletions(-) (limited to 'include/linux') diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 2c594686c05e..289eb5aa7b5d 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -277,6 +277,13 @@ int mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb, u32 portid, u32 seq, struct mr_mfc *c, int cmd, int flags), spinlock_t *lock); + +int mr_dump(struct net *net, struct notifier_block *nb, unsigned short family, + int (*rules_dump)(struct net *net, + struct notifier_block *nb), + struct mr_table *(*mr_iter)(struct net *net, + struct mr_table *mrt), + rwlock_t *mrt_lock); #else static inline void vif_device_init(struct vif_device *v, struct net_device *dev, @@ -333,6 +340,17 @@ mr_rtm_dumproute(struct sk_buff *skb, struct netlink_callback *cb, { return -EINVAL; } + +static inline int mr_dump(struct net *net, struct notifier_block *nb, + unsigned short family, + int (*rules_dump)(struct net *net, + struct notifier_block *nb), + struct mr_table *(*mr_iter)(struct net *net, + struct mr_table *mrt), + rwlock_t *mrt_lock) +{ + return -EINVAL; +} #endif static inline void *mr_mfc_find(struct mr_table *mrt, void *hasharg) diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 470956d2d8ad..24c340021aba 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -644,16 +644,6 @@ static struct net_device *ipmr_reg_vif(struct net *net, struct mr_table *mrt) } #endif -static int call_ipmr_vif_entry_notifier(struct notifier_block *nb, - struct net *net, - enum fib_event_type event_type, - struct vif_device *vif, - vifi_t vif_index, u32 tb_id) -{ - return mr_call_vif_notifier(nb, net, RTNL_FAMILY_IPMR, event_type, - vif, vif_index, tb_id); -} - static int call_ipmr_vif_entry_notifiers(struct net *net, enum fib_event_type event_type, struct vif_device *vif, @@ -664,15 +654,6 @@ static int call_ipmr_vif_entry_notifiers(struct net *net, &net->ipv4.ipmr_seq); } -static int call_ipmr_mfc_entry_notifier(struct notifier_block *nb, - struct net *net, - enum fib_event_type event_type, - struct mfc_cache *mfc, u32 tb_id) -{ - return mr_call_mfc_notifier(nb, net, RTNL_FAMILY_IPMR, - event_type, &mfc->_c, tb_id); -} - static int call_ipmr_mfc_entry_notifiers(struct net *net, enum fib_event_type event_type, struct mfc_cache *mfc, u32 tb_id) @@ -2950,38 +2931,8 @@ static unsigned int ipmr_seq_read(struct net *net) static int ipmr_dump(struct net *net, struct notifier_block *nb) { - struct mr_table *mrt; - int err; - - err = ipmr_rules_dump(net, nb); - if (err) - return err; - - ipmr_for_each_table(mrt, net) { - struct vif_device *v = &mrt->vif_table[0]; - struct mr_mfc *mfc; - int vifi; - - /* Notifiy on table VIF entries */ - read_lock(&mrt_lock); - for (vifi = 0; vifi < mrt->maxvif; vifi++, v++) { - if (!v->dev) - continue; - - call_ipmr_vif_entry_notifier(nb, net, FIB_EVENT_VIF_ADD, - v, vifi, mrt->id); - } - read_unlock(&mrt_lock); - - /* Notify on table MFC entries */ - list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) - call_ipmr_mfc_entry_notifier(nb, net, - FIB_EVENT_ENTRY_ADD, - (struct mfc_cache *)mfc, - mrt->id); - } - - return 0; + return mr_dump(net, nb, RTNL_FAMILY_IPMR, ipmr_rules_dump, + ipmr_mr_table_iter, &mrt_lock); } static const struct fib_notifier_ops ipmr_notifier_ops_template = { diff --git a/net/ipv4/ipmr_base.c b/net/ipv4/ipmr_base.c index 8ba55bfda817..4fe97723b53f 100644 --- a/net/ipv4/ipmr_base.c +++ b/net/ipv4/ipmr_base.c @@ -321,3 +321,45 @@ done: return skb->len; } EXPORT_SYMBOL(mr_rtm_dumproute); + +int mr_dump(struct net *net, struct notifier_block *nb, unsigned short family, + int (*rules_dump)(struct net *net, + struct notifier_block *nb), + struct mr_table *(*mr_iter)(struct net *net, + struct mr_table *mrt), + rwlock_t *mrt_lock) +{ + struct mr_table *mrt; + int err; + + err = rules_dump(net, nb); + if (err) + return err; + + for (mrt = mr_iter(net, NULL); mrt; mrt = mr_iter(net, mrt)) { + struct vif_device *v = &mrt->vif_table[0]; + struct mr_mfc *mfc; + int vifi; + + /* Notifiy on table VIF entries */ + read_lock(mrt_lock); + for (vifi = 0; vifi < mrt->maxvif; vifi++, v++) { + if (!v->dev) + continue; + + mr_call_vif_notifier(nb, net, family, + FIB_EVENT_VIF_ADD, + v, vifi, mrt->id); + } + read_unlock(mrt_lock); + + /* Notify on table MFC entries */ + list_for_each_entry_rcu(mfc, &mrt->mfc_cache_list, list) + mr_call_mfc_notifier(nb, net, family, + FIB_EVENT_ENTRY_ADD, + mfc, mrt->id); + } + + return 0; +} +EXPORT_SYMBOL(mr_dump); -- cgit v1.2.3 From d3c07e5b9939a055fa017f200e535ae947eb22ab Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Mon, 26 Mar 2018 15:01:35 +0300 Subject: ip6mr: Add API for default_rule fib Add the ability to discern whether a given FIB rule notification relates to the default rule inserted when registering ip6mr or a different one. Would later be used by drivers wishing to offload ipv6 multicast routes but unable to offload rules other than the default one. Signed-off-by: Yuval Mintz Signed-off-by: Ido Schimmel Signed-off-by: David S. Miller --- include/linux/mroute6.h | 10 ++++++++++ net/ipv6/ip6mr.c | 7 +++++++ 2 files changed, 17 insertions(+) (limited to 'include/linux') diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h index 1ac38e6819f5..c4a45859f586 100644 --- a/include/linux/mroute6.h +++ b/include/linux/mroute6.h @@ -8,6 +8,7 @@ #include #include #include +#include #ifdef CONFIG_IPV6_MROUTE static inline int ip6_mroute_opt(int opt) @@ -63,6 +64,15 @@ static inline void ip6_mr_cleanup(void) } #endif +#ifdef CONFIG_IPV6_MROUTE_MULTIPLE_TABLES +bool ip6mr_rule_default(const struct fib_rule *rule); +#else +static inline bool ip6mr_rule_default(const struct fib_rule *rule) +{ + return true; +} +#endif + #define VIFF_STATIC 0x8000 struct mfc6_cache_cmp_arg { diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index 0be2f333e168..a187c523a95f 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -268,6 +268,13 @@ static unsigned int ip6mr_rules_seq_read(struct net *net) { return fib_rules_seq_read(net, RTNL_FAMILY_IP6MR); } + +bool ip6mr_rule_default(const struct fib_rule *rule) +{ + return fib_rule_matchall(rule) && rule->action == FR_ACT_TO_TBL && + rule->table == RT6_TABLE_DFLT && !rule->l3mdev; +} +EXPORT_SYMBOL(ip6mr_rule_default); #else #define ip6mr_for_each_table(mrt, net) \ for (mrt = net->ipv6.mrt6; mrt; mrt = NULL) -- cgit v1.2.3 From 8c13af2a219c6498071b30ea558438c74267ae4d Mon Sep 17 00:00:00 2001 From: Yuval Mintz Date: Mon, 26 Mar 2018 15:01:36 +0300 Subject: ip6mr: Add refcounting to mfc Since ipmr and ip6mr are using the same mr_mfc struct at their core, we can now refactor the ipmr_cache_{hold,put} logic and apply refcounting to both ipmr and ip6mr. Signed-off-by: Yuval Mintz Signed-off-by: Ido Schimmel Signed-off-by: David S. Miller --- drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c | 6 +++--- drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c | 6 +++--- include/linux/mroute.h | 19 ------------------- include/linux/mroute_base.h | 13 +++++++++++++ net/ipv4/ipmr.c | 8 ++++---- net/ipv6/ip6mr.c | 6 ++++-- 6 files changed, 27 insertions(+), 31 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c index 978a3c70653a..51b104ae2eec 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_mr.c @@ -360,7 +360,7 @@ mlxsw_sp_mr_route4_create(struct mlxsw_sp_mr_table *mr_table, /* Find min_mtu and link iVIF and eVIFs */ mr_route->min_mtu = ETH_MAX_MTU; - ipmr_cache_hold(mfc); + mr_cache_hold(&mfc->_c); mr_route->mfc4 = mfc; mr_route->mr_table = mr_table; for (i = 0; i < MAXVIFS; i++) { @@ -380,7 +380,7 @@ mlxsw_sp_mr_route4_create(struct mlxsw_sp_mr_table *mr_table, mr_route->route_action = mlxsw_sp_mr_route_action(mr_route); return mr_route; err: - ipmr_cache_put(mfc); + mr_cache_put(&mfc->_c); list_for_each_entry_safe(rve, tmp, &mr_route->evif_list, route_node) mlxsw_sp_mr_route_evif_unlink(rve); kfree(mr_route); @@ -393,7 +393,7 @@ static void mlxsw_sp_mr_route4_destroy(struct mlxsw_sp_mr_table *mr_table, struct mlxsw_sp_mr_route_vif_entry *rve, *tmp; mlxsw_sp_mr_route_ivif_unlink(mr_route); - ipmr_cache_put(mr_route->mfc4); + mr_cache_put((struct mr_mfc *)mr_route->mfc4); list_for_each_entry_safe(rve, tmp, &mr_route->evif_list, route_node) mlxsw_sp_mr_route_evif_unlink(rve); kfree(mr_route); diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c index 8d067de924cf..be241c708bb9 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c @@ -5685,11 +5685,11 @@ static void mlxsw_sp_router_fibmr_event_work(struct work_struct *work) replace); if (err) mlxsw_sp_router_fib_abort(mlxsw_sp); - ipmr_cache_put((struct mfc_cache *) fib_work->men_info.mfc); + mr_cache_put(fib_work->men_info.mfc); break; case FIB_EVENT_ENTRY_DEL: mlxsw_sp_router_fibmr_del(mlxsw_sp, &fib_work->men_info); - ipmr_cache_put((struct mfc_cache *) fib_work->men_info.mfc); + mr_cache_put(fib_work->men_info.mfc); break; case FIB_EVENT_VIF_ADD: err = mlxsw_sp_router_fibmr_vif_add(mlxsw_sp, @@ -5769,7 +5769,7 @@ mlxsw_sp_router_fibmr_event(struct mlxsw_sp_fib_event_work *fib_work, case FIB_EVENT_ENTRY_ADD: /* fall through */ case FIB_EVENT_ENTRY_DEL: memcpy(&fib_work->men_info, info, sizeof(fib_work->men_info)); - ipmr_cache_hold((struct mfc_cache *) fib_work->men_info.mfc); + mr_cache_hold(fib_work->men_info.mfc); break; case FIB_EVENT_VIF_ADD: /* fall through */ case FIB_EVENT_VIF_DEL: diff --git a/include/linux/mroute.h b/include/linux/mroute.h index c855d80b51f7..9a36fad9e068 100644 --- a/include/linux/mroute.h +++ b/include/linux/mroute.h @@ -84,23 +84,4 @@ struct rtmsg; int ipmr_get_route(struct net *net, struct sk_buff *skb, __be32 saddr, __be32 daddr, struct rtmsg *rtm, u32 portid); - -#ifdef CONFIG_IP_MROUTE -void ipmr_cache_free(struct mfc_cache *mfc_cache); -#else -static inline void ipmr_cache_free(struct mfc_cache *mfc_cache) -{ -} -#endif - -static inline void ipmr_cache_put(struct mfc_cache *c) -{ - if (refcount_dec_and_test(&c->_c.mfc_un.res.refcount)) - ipmr_cache_free(c); -} -static inline void ipmr_cache_hold(struct mfc_cache *c) -{ - refcount_inc(&c->_c.mfc_un.res.refcount); -} - #endif diff --git a/include/linux/mroute_base.h b/include/linux/mroute_base.h index 289eb5aa7b5d..d617fe45543e 100644 --- a/include/linux/mroute_base.h +++ b/include/linux/mroute_base.h @@ -125,6 +125,7 @@ enum { * @refcount: reference count for this entry * @list: global entry list * @rcu: used for entry destruction + * @free: Operation used for freeing an entry under RCU */ struct mr_mfc { struct rhlist_head mnode; @@ -150,8 +151,20 @@ struct mr_mfc { } mfc_un; struct list_head list; struct rcu_head rcu; + void (*free)(struct rcu_head *head); }; +static inline void mr_cache_put(struct mr_mfc *c) +{ + if (refcount_dec_and_test(&c->mfc_un.res.refcount)) + call_rcu(&c->rcu, c->free); +} + +static inline void mr_cache_hold(struct mr_mfc *c) +{ + refcount_inc(&c->mfc_un.res.refcount); +} + struct mfc_entry_notifier_info { struct fib_notifier_info info; struct mr_mfc *mfc; diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c index 24c340021aba..e79211a8537c 100644 --- a/net/ipv4/ipmr.c +++ b/net/ipv4/ipmr.c @@ -732,11 +732,10 @@ static void ipmr_cache_free_rcu(struct rcu_head *head) kmem_cache_free(mrt_cachep, (struct mfc_cache *)c); } -void ipmr_cache_free(struct mfc_cache *c) +static void ipmr_cache_free(struct mfc_cache *c) { call_rcu(&c->_c.rcu, ipmr_cache_free_rcu); } -EXPORT_SYMBOL(ipmr_cache_free); /* Destroy an unresolved cache entry, killing queued skbs * and reporting error to netlink readers. @@ -987,6 +986,7 @@ static struct mfc_cache *ipmr_cache_alloc(void) if (c) { c->_c.mfc_un.res.last_assert = jiffies - MFC_ASSERT_THRESH - 1; c->_c.mfc_un.res.minvif = MAXVIFS; + c->_c.free = ipmr_cache_free_rcu; refcount_set(&c->_c.mfc_un.res.refcount, 1); } return c; @@ -1206,7 +1206,7 @@ static int ipmr_mfc_delete(struct mr_table *mrt, struct mfcctl *mfc, int parent) list_del_rcu(&c->_c.list); call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_DEL, c, mrt->id); mroute_netlink_event(mrt, c, RTM_DELROUTE); - ipmr_cache_put(c); + mr_cache_put(&c->_c); return 0; } @@ -1318,7 +1318,7 @@ static void mroute_clean_tables(struct mr_table *mrt, bool all) call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_DEL, cache, mrt->id); mroute_netlink_event(mrt, cache, RTM_DELROUTE); - ipmr_cache_put(cache); + mr_cache_put(c); } if (atomic_read(&mrt->cache_resolve_queue_len) != 0) { diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index a187c523a95f..1c8fa29d155a 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -989,6 +989,8 @@ static struct mfc6_cache *ip6mr_cache_alloc(void) return NULL; c->_c.mfc_un.res.last_assert = jiffies - MFC_ASSERT_THRESH - 1; c->_c.mfc_un.res.minvif = MAXMIFS; + c->_c.free = ip6mr_cache_free_rcu; + refcount_set(&c->_c.mfc_un.res.refcount, 1); return c; } @@ -1227,7 +1229,7 @@ static int ip6mr_mfc_delete(struct mr_table *mrt, struct mf6cctl *mfc, call_ip6mr_mfc_entry_notifiers(read_pnet(&mrt->net), FIB_EVENT_ENTRY_DEL, c, mrt->id); mr6_netlink_event(mrt, c, RTM_DELROUTE); - ip6mr_cache_free(c); + mr_cache_put(&c->_c); return 0; } @@ -1516,7 +1518,7 @@ static void mroute_clean_tables(struct mr_table *mrt, bool all) rhltable_remove(&mrt->mfc_hash, &c->mnode, ip6mr_rht_params); list_del_rcu(&c->list); mr6_netlink_event(mrt, (struct mfc6_cache *)c, RTM_DELROUTE); - ip6mr_cache_free((struct mfc6_cache *)c); + mr_cache_put(c); } if (atomic_read(&mrt->cache_resolve_queue_len) != 0) { -- cgit v1.2.3 From 2fcb12df7d2fa5a004fc3e7f589e58a08f7ed8c9 Mon Sep 17 00:00:00 2001 From: Inbar Karmy Date: Thu, 17 Aug 2017 16:39:47 +0300 Subject: net/mlx5e: Expose PFC stall prevention counters Add the needed capability bit and counters to device spec description. Expose the following two counters in ethtool: tx_pause_storm_warning_events: when the device is stalled for a period longer than a pre-configured watermark, the counter increase, allowing the debug utility an insight into current device status. tx_pause_storm_error_events: when the device is stalled for a period longer than a pre-configured timeout, the pause transmission is disabled, and the counter increase. Signed-off-by: Inbar Karmy Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/en_stats.c | 19 ++++++++++++++- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 3 +++ include/linux/mlx5/device.h | 4 ++++ include/linux/mlx5/mlx5_ifc.h | 28 +++++++++++++++++++--- 4 files changed, 50 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 5f0f3493d747..2553c58dcf1c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -754,7 +754,15 @@ static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) }, }; +static const struct counter_desc pport_pfc_stall_stats_desc[] = { + { "tx_pause_storm_warning_events ", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) }, + { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) }, +}; + #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc) +#define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \ + MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \ + MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv) { @@ -790,7 +798,8 @@ static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv) { return (mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * - NUM_PPORT_PER_PRIO_PFC_COUNTERS; + NUM_PPORT_PER_PRIO_PFC_COUNTERS + + NUM_PPORT_PFC_STALL_COUNTERS(priv); } static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv, @@ -818,6 +827,10 @@ static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv, } } + for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) + strcpy(data + (idx++) * ETH_GSTRING_LEN, + pport_pfc_stall_stats_desc[i].format); + return idx; } @@ -845,6 +858,10 @@ static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv, } } + for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++) + data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0], + pport_pfc_stall_stats_desc, i); + return idx; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c index 9d11e92fb541..d7bb10ab2173 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -183,6 +183,9 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) return err; } + if (MLX5_CAP_GEN(dev, debug)) + mlx5_core_get_caps(dev, MLX5_CAP_DEBUG); + if (MLX5_CAP_GEN(dev, pcam_reg)) mlx5_get_pcam_reg(dev); diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index e5258ee4e38b..4b5939c78cdd 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1013,6 +1013,7 @@ enum mlx5_cap_type { MLX5_CAP_RESERVED, MLX5_CAP_VECTOR_CALC, MLX5_CAP_QOS, + MLX5_CAP_DEBUG, /* NUM OF CAP Types */ MLX5_CAP_NUM }; @@ -1140,6 +1141,9 @@ enum mlx5_qcam_feature_groups { #define MLX5_CAP_QOS(mdev, cap)\ MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap) +#define MLX5_CAP_DEBUG(mdev, cap)\ + MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap) + #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 14ad84afe8ba..c7d50eccff9e 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -593,6 +593,16 @@ struct mlx5_ifc_qos_cap_bits { u8 reserved_at_100[0x700]; }; +struct mlx5_ifc_debug_cap_bits { + u8 reserved_at_0[0x20]; + + u8 reserved_at_20[0x2]; + u8 stall_detect[0x1]; + u8 reserved_at_23[0x1d]; + + u8 reserved_at_40[0x7c0]; +}; + struct mlx5_ifc_per_protocol_networking_offload_caps_bits { u8 csum_cap[0x1]; u8 vlan_cap[0x1]; @@ -855,7 +865,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 out_of_seq_cnt[0x1]; u8 vport_counters[0x1]; u8 retransmission_q_counters[0x1]; - u8 reserved_at_183[0x1]; + u8 debug[0x1]; u8 modify_rq_counter_set_id[0x1]; u8 rq_delay_drop[0x1]; u8 max_qp_cnt[0xa]; @@ -1572,7 +1582,17 @@ struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { u8 rx_pause_transition_low[0x20]; - u8 reserved_at_3c0[0x400]; + u8 reserved_at_3c0[0x40]; + + u8 device_stall_minor_watermark_cnt_high[0x20]; + + u8 device_stall_minor_watermark_cnt_low[0x20]; + + u8 device_stall_critical_watermark_cnt_high[0x20]; + + u8 device_stall_critical_watermark_cnt_low[0x20]; + + u8 reserved_at_480[0x340]; }; struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { @@ -7874,8 +7894,10 @@ struct mlx5_ifc_peir_reg_bits { }; struct mlx5_ifc_pcam_enhanced_features_bits { - u8 reserved_at_0[0x7b]; + u8 reserved_at_0[0x76]; + u8 pfcc_mask[0x1]; + u8 reserved_at_77[0x4]; u8 rx_buffer_fullness_counters[0x1]; u8 ptys_connector_type[0x1]; u8 reserved_at_7d[0x1]; -- cgit v1.2.3 From 2afa609f5c970185a8cae73f6a4caadf97fbea54 Mon Sep 17 00:00:00 2001 From: Inbar Karmy Date: Mon, 20 Nov 2017 18:06:20 +0200 Subject: net/mlx5e: PFC stall prevention support Implement set/get functions to configure PFC stall prevention timeout by tunables api through ethtool. By default the stall prevention timeout is configured to 8 sec. Timeout range is: 80-8000 msec. Enabling stall prevention with the auto timeout will set the timeout to 100 msec. Signed-off-by: Inbar Karmy Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/en_ethtool.c | 57 +++++++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/port.c | 64 +++++++++++++++++++--- include/linux/mlx5/mlx5_ifc.h | 17 ++++-- include/linux/mlx5/port.h | 6 ++ 4 files changed, 132 insertions(+), 12 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index cc8048f68f11..62061fd23143 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -1066,6 +1066,57 @@ static int mlx5e_get_rxnfc(struct net_device *netdev, return err; } +#define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 +#define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 +#define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 +#define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 +#define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ + max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ + (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) + +static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, + u16 *pfc_prevention_tout) +{ + struct mlx5e_priv *priv = netdev_priv(netdev); + struct mlx5_core_dev *mdev = priv->mdev; + + if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || + !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) + return -EOPNOTSUPP; + + return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); +} + +static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, + u16 pfc_preven) +{ + struct mlx5e_priv *priv = netdev_priv(netdev); + struct mlx5_core_dev *mdev = priv->mdev; + u16 critical_tout; + u16 minor; + + if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || + !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) + return -EOPNOTSUPP; + + critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? + MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : + pfc_preven; + + if (critical_tout != PFC_STORM_PREVENTION_DISABLE && + (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || + critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { + netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", + __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, + MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); + return -EINVAL; + } + + minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); + return mlx5_set_port_stall_watermark(mdev, critical_tout, + minor); +} + static int mlx5e_get_tunable(struct net_device *dev, const struct ethtool_tunable *tuna, void *data) @@ -1077,6 +1128,9 @@ static int mlx5e_get_tunable(struct net_device *dev, case ETHTOOL_TX_COPYBREAK: *(u32 *)data = priv->channels.params.tx_max_inline; break; + case ETHTOOL_PFC_PREVENTION_TOUT: + err = mlx5e_get_pfc_prevention_tout(dev, data); + break; default: err = -EINVAL; break; @@ -1118,6 +1172,9 @@ static int mlx5e_set_tunable(struct net_device *dev, break; mlx5e_switch_priv_channels(priv, &new_channels, NULL); + break; + case ETHTOOL_PFC_PREVENTION_TOUT: + err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); break; default: err = -EINVAL; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index c37d00cd472a..fa9d0760dd36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -483,6 +483,17 @@ int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, } EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt); +static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out, + u32 out_size) +{ + u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; + + MLX5_SET(pfcc_reg, in, local_port, 1); + + return mlx5_core_access_reg(dev, in, sizeof(in), out, + out_size, MLX5_REG_PFCC, 0, 0); +} + int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause) { u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; @@ -500,13 +511,10 @@ EXPORT_SYMBOL_GPL(mlx5_set_port_pause); int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 *rx_pause, u32 *tx_pause) { - u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; int err; - MLX5_SET(pfcc_reg, in, local_port, 1); - err = mlx5_core_access_reg(dev, in, sizeof(in), out, - sizeof(out), MLX5_REG_PFCC, 0, 0); + err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); if (err) return err; @@ -520,6 +528,49 @@ int mlx5_query_port_pause(struct mlx5_core_dev *dev, } EXPORT_SYMBOL_GPL(mlx5_query_port_pause); +int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, + u16 stall_critical_watermark, + u16 stall_minor_watermark) +{ + u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; + u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; + + MLX5_SET(pfcc_reg, in, local_port, 1); + MLX5_SET(pfcc_reg, in, pptx_mask_n, 1); + MLX5_SET(pfcc_reg, in, pprx_mask_n, 1); + MLX5_SET(pfcc_reg, in, ppan_mask_n, 1); + MLX5_SET(pfcc_reg, in, critical_stall_mask, 1); + MLX5_SET(pfcc_reg, in, minor_stall_mask, 1); + MLX5_SET(pfcc_reg, in, device_stall_critical_watermark, + stall_critical_watermark); + MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark); + + return mlx5_core_access_reg(dev, in, sizeof(in), out, + sizeof(out), MLX5_REG_PFCC, 0, 1); +} + +int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, + u16 *stall_critical_watermark, + u16 *stall_minor_watermark) +{ + u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; + int err; + + err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); + if (err) + return err; + + if (stall_critical_watermark) + *stall_critical_watermark = MLX5_GET(pfcc_reg, out, + device_stall_critical_watermark); + + if (stall_minor_watermark) + *stall_minor_watermark = MLX5_GET(pfcc_reg, out, + device_stall_minor_watermark); + + return 0; +} + int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx) { u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; @@ -538,13 +589,10 @@ EXPORT_SYMBOL_GPL(mlx5_set_port_pfc); int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx) { - u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0}; u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; int err; - MLX5_SET(pfcc_reg, in, local_port, 1); - err = mlx5_core_access_reg(dev, in, sizeof(in), out, - sizeof(out), MLX5_REG_PFCC, 0, 0); + err = mlx5_query_pfcc_reg(dev, out, sizeof(out)); if (err) return err; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index c7d50eccff9e..f3200a9696d6 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -7833,7 +7833,11 @@ struct mlx5_ifc_pifr_reg_bits { struct mlx5_ifc_pfcc_reg_bits { u8 reserved_at_0[0x8]; u8 local_port[0x8]; - u8 reserved_at_10[0x10]; + u8 reserved_at_10[0xb]; + u8 ppan_mask_n[0x1]; + u8 minor_stall_mask[0x1]; + u8 critical_stall_mask[0x1]; + u8 reserved_at_1e[0x2]; u8 ppan[0x4]; u8 reserved_at_24[0x4]; @@ -7843,17 +7847,22 @@ struct mlx5_ifc_pfcc_reg_bits { u8 pptx[0x1]; u8 aptx[0x1]; - u8 reserved_at_42[0x6]; + u8 pptx_mask_n[0x1]; + u8 reserved_at_43[0x5]; u8 pfctx[0x8]; u8 reserved_at_50[0x10]; u8 pprx[0x1]; u8 aprx[0x1]; - u8 reserved_at_62[0x6]; + u8 pprx_mask_n[0x1]; + u8 reserved_at_63[0x5]; u8 pfcrx[0x8]; u8 reserved_at_70[0x10]; - u8 reserved_at_80[0x80]; + u8 device_stall_minor_watermark[0x10]; + u8 device_stall_critical_watermark[0x10]; + + u8 reserved_at_a0[0x60]; }; struct mlx5_ifc_pelc_reg_bits { diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h index 035f0d4dc9fe..34aed6032f86 100644 --- a/include/linux/mlx5/port.h +++ b/include/linux/mlx5/port.h @@ -151,6 +151,12 @@ int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx); +int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, + u16 stall_critical_watermark, + u16 stall_minor_watermark); +int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, + u16 *stall_critical_watermark, u16 *stall_minor_watermark); + int mlx5_max_tc(struct mlx5_core_dev *mdev); int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc); -- cgit v1.2.3 From 61c5b5c9178288a4caa3e39095aafb391c5100f6 Mon Sep 17 00:00:00 2001 From: Moshe Shemesh Date: Sun, 7 Jan 2018 16:45:27 +0200 Subject: net/mlx5: Add support for QUERY_VNIC_ENV command Add support for new FW command QUERY_VNIC_ENV. The command is used by the driver to query vnic diagnostic statistics from FW. Signed-off-by: Moshe Shemesh Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/cmd.c | 2 ++ include/linux/mlx5/mlx5_ifc.h | 50 ++++++++++++++++++++++++++- 2 files changed, 51 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c index e9a1fbcc4adf..fe5428667ad1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c @@ -359,6 +359,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT: case MLX5_CMD_OP_QUERY_HCA_VPORT_GID: case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY: + case MLX5_CMD_OP_QUERY_VNIC_ENV: case MLX5_CMD_OP_QUERY_VPORT_COUNTER: case MLX5_CMD_OP_ALLOC_Q_COUNTER: case MLX5_CMD_OP_QUERY_Q_COUNTER: @@ -501,6 +502,7 @@ const char *mlx5_command_str(int command) MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT); MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID); MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY); + MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV); MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER); MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index f3200a9696d6..52e373dd2679 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -143,6 +143,7 @@ enum { MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, + MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, @@ -875,7 +876,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 vhca_group_manager[0x1]; u8 ib_virt[0x1]; u8 eth_virt[0x1]; - u8 reserved_at_1a4[0x1]; + u8 vnic_env_queue_counters[0x1]; u8 ets[0x1]; u8 nic_flow_table[0x1]; u8 eswitch_flow_table[0x1]; @@ -2386,6 +2387,24 @@ struct mlx5_ifc_xrc_srqc_bits { u8 reserved_at_180[0x80]; }; +struct mlx5_ifc_vnic_diagnostic_statistics_bits { + u8 counter_error_queues[0x20]; + + u8 total_error_queues[0x20]; + + u8 send_queue_priority_update_flow[0x20]; + + u8 reserved_at_60[0x20]; + + u8 nic_receive_steering_discard[0x40]; + + u8 receive_discard_vport_down[0x40]; + + u8 transmit_discard_vport_down[0x40]; + + u8 reserved_at_140[0xec0]; +}; + struct mlx5_ifc_traffic_counter_bits { u8 packets[0x40]; @@ -3661,6 +3680,35 @@ struct mlx5_ifc_query_vport_state_in_bits { u8 reserved_at_60[0x20]; }; +struct mlx5_ifc_query_vnic_env_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 reserved_at_40[0x40]; + + struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; +}; + +enum { + MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, +}; + +struct mlx5_ifc_query_vnic_env_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 other_vport[0x1]; + u8 reserved_at_41[0xf]; + u8 vport_number[0x10]; + + u8 reserved_at_60[0x20]; +}; + struct mlx5_ifc_query_vport_counter_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; -- cgit v1.2.3 From 5c298143be17f5100656b9c140af672c644116d9 Mon Sep 17 00:00:00 2001 From: Moshe Shemesh Date: Tue, 26 Dec 2017 16:46:29 +0200 Subject: net/mlx5e: Add vnic steering drop statistics Added the following packets drop counter: Rx steering missed dropped packets - counts packets which were dropped due to miss on NIC rx steering rules. This counter will be shown on ethtool as a new counter called rx_steer_missed_packets. Signed-off-by: Moshe Shemesh Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/en_stats.c | 65 ++++++++++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en_stats.h | 5 ++ include/linux/mlx5/mlx5_ifc.h | 3 +- 3 files changed, 72 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index 2553c58dcf1c..552510c03ef2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -211,6 +211,65 @@ static void mlx5e_grp_q_update_stats(struct mlx5e_priv *priv) qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer); } +#define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c) +static const struct counter_desc vnic_env_stats_desc[] = { + { "rx_steer_missed_packets", + VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) }, +}; + +#define NUM_VNIC_ENV_COUNTERS ARRAY_SIZE(vnic_env_stats_desc) + +static int mlx5e_grp_vnic_env_get_num_stats(struct mlx5e_priv *priv) +{ + return MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard) ? + NUM_VNIC_ENV_COUNTERS : 0; +} + +static int mlx5e_grp_vnic_env_fill_strings(struct mlx5e_priv *priv, u8 *data, + int idx) +{ + int i; + + if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) + return idx; + + for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) + strcpy(data + (idx++) * ETH_GSTRING_LEN, + vnic_env_stats_desc[i].format); + return idx; +} + +static int mlx5e_grp_vnic_env_fill_stats(struct mlx5e_priv *priv, u64 *data, + int idx) +{ + int i; + + if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) + return idx; + + for (i = 0; i < NUM_VNIC_ENV_COUNTERS; i++) + data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out, + vnic_env_stats_desc, i); + return idx; +} + +static void mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) +{ + u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out; + int outlen = MLX5_ST_SZ_BYTES(query_vnic_env_out); + u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0}; + struct mlx5_core_dev *mdev = priv->mdev; + + if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) + return; + + MLX5_SET(query_vnic_env_in, in, opcode, + MLX5_CMD_OP_QUERY_VNIC_ENV); + MLX5_SET(query_vnic_env_in, in, op_mod, 0); + MLX5_SET(query_vnic_env_in, in, other_vport, 0); + mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); +} + #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c) static const struct counter_desc vport_stats_desc[] = { { "rx_vport_unicast_packets", @@ -1111,6 +1170,12 @@ const struct mlx5e_stats_grp mlx5e_stats_grps[] = { .update_stats_mask = MLX5E_NDO_UPDATE_STATS, .update_stats = mlx5e_grp_q_update_stats, }, + { + .get_num_stats = mlx5e_grp_vnic_env_get_num_stats, + .fill_strings = mlx5e_grp_vnic_env_fill_strings, + .fill_stats = mlx5e_grp_vnic_env_fill_stats, + .update_stats = mlx5e_grp_vnic_env_update_stats, + }, { .get_num_stats = mlx5e_grp_vport_get_num_stats, .fill_strings = mlx5e_grp_vport_fill_strings, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h index 0b3320a2b072..847388ff8ca8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -99,6 +99,10 @@ struct mlx5e_qcounter_stats { u32 rx_out_of_buffer; }; +struct mlx5e_vnic_env_stats { + __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)]; +}; + #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \ vstats->query_vport_out, c) @@ -201,6 +205,7 @@ struct mlx5e_ch_stats { struct mlx5e_stats { struct mlx5e_sw_stats sw; struct mlx5e_qcounter_stats qcnt; + struct mlx5e_vnic_env_stats vnic; struct mlx5e_vport_stats vport; struct mlx5e_pport_stats pport; struct rtnl_link_stats64 vf_vport; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 52e373dd2679..9202113f552c 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1008,7 +1008,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_330[0xb]; u8 log_max_xrcd[0x5]; - u8 reserved_at_340[0x8]; + u8 nic_receive_steering_discard[0x1]; + u8 reserved_at_341[0x7]; u8 log_max_flow_counter_bulk[0x8]; u8 max_flow_counter_15_0[0x10]; -- cgit v1.2.3 From aaabd0783b1cf46569f5fc1c60d79709815497fc Mon Sep 17 00:00:00 2001 From: Moshe Shemesh Date: Sun, 14 Jan 2018 00:56:25 +0200 Subject: net/mlx5: Add packet dropped while vport down statistics Added the following packets dropped while vport down statistics: Rx dropped while vport down - counts packets which were steered by e-switch to a vport, but dropped since the vport was down. This counter will be shown on ip link tool as part of the vport rx_dropped counter. Tx dropped while vport down - counts packets which were transmitted by a vport, but dropped due to vport logical link down. This counter will be shown on ip link tool as part of the vport tx_dropped counter. The counters are read from FW by command QUERY_VNIC_ENV. Signed-off-by: Moshe Shemesh Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/eswitch.c | 31 +++++++++++++++++++---- drivers/net/ethernet/mellanox/mlx5/core/vport.c | 26 +++++++++++++++++++ include/linux/mlx5/mlx5_ifc.h | 4 ++- include/linux/mlx5/vport.h | 3 +++ 4 files changed, 58 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c index 77b7272eaaa8..332bc56306bf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -2096,17 +2096,19 @@ unlock: return err; } -static void mlx5_eswitch_query_vport_drop_stats(struct mlx5_core_dev *dev, - int vport_idx, - struct mlx5_vport_drop_stats *stats) +static int mlx5_eswitch_query_vport_drop_stats(struct mlx5_core_dev *dev, + int vport_idx, + struct mlx5_vport_drop_stats *stats) { struct mlx5_eswitch *esw = dev->priv.eswitch; struct mlx5_vport *vport = &esw->vports[vport_idx]; + u64 rx_discard_vport_down, tx_discard_vport_down; u64 bytes = 0; u16 idx = 0; + int err = 0; if (!vport->enabled || esw->mode != SRIOV_LEGACY) - return; + return 0; if (vport->egress.drop_counter) { idx = vport->egress.drop_counter->id; @@ -2117,6 +2119,23 @@ static void mlx5_eswitch_query_vport_drop_stats(struct mlx5_core_dev *dev, idx = vport->ingress.drop_counter->id; mlx5_fc_query(dev, idx, &stats->tx_dropped, &bytes); } + + if (!MLX5_CAP_GEN(dev, receive_discard_vport_down) && + !MLX5_CAP_GEN(dev, transmit_discard_vport_down)) + return 0; + + err = mlx5_query_vport_down_stats(dev, vport_idx, + &rx_discard_vport_down, + &tx_discard_vport_down); + if (err) + return err; + + if (MLX5_CAP_GEN(dev, receive_discard_vport_down)) + stats->rx_dropped += rx_discard_vport_down; + if (MLX5_CAP_GEN(dev, transmit_discard_vport_down)) + stats->tx_dropped += tx_discard_vport_down; + + return 0; } int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, @@ -2180,7 +2199,9 @@ int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, vf_stats->broadcast = MLX5_GET_CTR(out, received_eth_broadcast.packets); - mlx5_eswitch_query_vport_drop_stats(esw->dev, vport, &stats); + err = mlx5_eswitch_query_vport_drop_stats(esw->dev, vport, &stats); + if (err) + goto free_out; vf_stats->rx_dropped = stats.rx_dropped; vf_stats->tx_dropped = stats.tx_dropped; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/ethernet/mellanox/mlx5/core/vport.c index dfe36cf6fbea..177e076b8d17 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -1070,6 +1070,32 @@ free: } EXPORT_SYMBOL_GPL(mlx5_core_query_vport_counter); +int mlx5_query_vport_down_stats(struct mlx5_core_dev *mdev, u16 vport, + u64 *rx_discard_vport_down, + u64 *tx_discard_vport_down) +{ + u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {0}; + u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0}; + int err; + + MLX5_SET(query_vnic_env_in, in, opcode, + MLX5_CMD_OP_QUERY_VNIC_ENV); + MLX5_SET(query_vnic_env_in, in, op_mod, 0); + MLX5_SET(query_vnic_env_in, in, vport_number, vport); + if (vport) + MLX5_SET(query_vnic_env_in, in, other_vport, 1); + + err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); + if (err) + return err; + + *rx_discard_vport_down = MLX5_GET64(query_vnic_env_out, out, + vport_env.receive_discard_vport_down); + *tx_discard_vport_down = MLX5_GET64(query_vnic_env_out, out, + vport_env.transmit_discard_vport_down); + return 0; +} + int mlx5_core_modify_hca_vport_context(struct mlx5_core_dev *dev, u8 other_vport, u8 port_num, int vf, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 9202113f552c..1f3483d40055 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1009,7 +1009,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_max_xrcd[0x5]; u8 nic_receive_steering_discard[0x1]; - u8 reserved_at_341[0x7]; + u8 receive_discard_vport_down[0x1]; + u8 transmit_discard_vport_down[0x1]; + u8 reserved_at_343[0x5]; u8 log_max_flow_counter_bulk[0x8]; u8 max_flow_counter_15_0[0x10]; diff --git a/include/linux/mlx5/vport.h b/include/linux/mlx5/vport.h index 64e193e87394..9208cb8809ac 100644 --- a/include/linux/mlx5/vport.h +++ b/include/linux/mlx5/vport.h @@ -107,6 +107,9 @@ int mlx5_modify_nic_vport_vlans(struct mlx5_core_dev *dev, int mlx5_nic_vport_enable_roce(struct mlx5_core_dev *mdev); int mlx5_nic_vport_disable_roce(struct mlx5_core_dev *mdev); +int mlx5_query_vport_down_stats(struct mlx5_core_dev *mdev, u16 vport, + u64 *rx_discard_vport_down, + u64 *tx_discard_vport_down); int mlx5_core_query_vport_counter(struct mlx5_core_dev *dev, u8 other_vport, int vf, u8 port_num, void *out, size_t out_sz); -- cgit v1.2.3 From 0c06897a9ac7e2db9ad2df15bc6511e8ab88378f Mon Sep 17 00:00:00 2001 From: Or Gerlitz Date: Sun, 28 Jan 2018 20:14:20 +0200 Subject: net/mlx5: Add core support for vlan push/pop steering action Newer NICs (ConnectX-5 and onward) can apply vlan pop or push as an action taking place during flow steering. Add the core bits for that. Signed-off-by: Or Gerlitz Reviewed-by: Mark Bloch Signed-off-by: Saeed Mahameed --- .../net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h | 2 ++ drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 3 --- drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c | 10 +++++++++- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 4 +++- include/linux/mlx5/fs.h | 7 +++++++ include/linux/mlx5/mlx5_ifc.h | 16 ++++++++++++++-- 6 files changed, 35 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h b/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h index a6ba57fbb414..09f178a3fcab 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h @@ -136,6 +136,8 @@ TRACE_EVENT(mlx5_fs_del_fg, {MLX5_FLOW_CONTEXT_ACTION_ENCAP, "ENCAP"},\ {MLX5_FLOW_CONTEXT_ACTION_DECAP, "DECAP"},\ {MLX5_FLOW_CONTEXT_ACTION_MOD_HDR, "MOD_HDR"},\ + {MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH, "VLAN_PUSH"},\ + {MLX5_FLOW_CONTEXT_ACTION_VLAN_POP, "VLAN_POP"},\ {MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"} TRACE_EVENT(mlx5_fs_set_fte, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 98d2177d0806..a435eb7971c6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -227,9 +227,6 @@ enum { SET_VLAN_INSERT = BIT(1) }; -#define MLX5_FLOW_CONTEXT_ACTION_VLAN_POP 0x4000 -#define MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH 0x8000 - struct mlx5_esw_flow_attr { struct mlx5_eswitch_rep *in_rep; struct mlx5_eswitch_rep *out_rep; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c index 645f83cac34d..ef5afd7c9325 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c @@ -317,7 +317,7 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, fte->dests_size * MLX5_ST_SZ_BYTES(dest_format_struct); u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {0}; struct mlx5_flow_rule *dst; - void *in_flow_context; + void *in_flow_context, *vlan; void *in_match_value; void *in_dests; u32 *in; @@ -340,11 +340,19 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, in_flow_context = MLX5_ADDR_OF(set_fte_in, in, flow_context); MLX5_SET(flow_context, in_flow_context, group_id, group_id); + MLX5_SET(flow_context, in_flow_context, flow_tag, fte->action.flow_tag); MLX5_SET(flow_context, in_flow_context, action, fte->action.action); MLX5_SET(flow_context, in_flow_context, encap_id, fte->action.encap_id); MLX5_SET(flow_context, in_flow_context, modify_header_id, fte->action.modify_id); + + vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan); + + MLX5_SET(vlan, vlan, ethtype, fte->action.vlan.ethtype); + MLX5_SET(vlan, vlan, vid, fte->action.vlan.vid); + MLX5_SET(vlan, vlan, prio, fte->action.vlan.prio); + in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context, match_value); memcpy(in_match_value, &fte->val, sizeof(fte->val)); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index 3ba07c7096ef..de51e7c39bc8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -1439,7 +1439,9 @@ static bool check_conflicting_actions(u32 action1, u32 action2) if (xored_actions & (MLX5_FLOW_CONTEXT_ACTION_DROP | MLX5_FLOW_CONTEXT_ACTION_ENCAP | MLX5_FLOW_CONTEXT_ACTION_DECAP | - MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) + MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | + MLX5_FLOW_CONTEXT_ACTION_VLAN_POP | + MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)) return true; return false; diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h index b957e52434f8..47aecc4fa8c2 100644 --- a/include/linux/mlx5/fs.h +++ b/include/linux/mlx5/fs.h @@ -142,6 +142,12 @@ struct mlx5_flow_group * mlx5_create_flow_group(struct mlx5_flow_table *ft, u32 *in); void mlx5_destroy_flow_group(struct mlx5_flow_group *fg); +struct mlx5_fs_vlan { + u16 ethtype; + u16 vid; + u8 prio; +}; + struct mlx5_flow_act { u32 action; bool has_flow_tag; @@ -149,6 +155,7 @@ struct mlx5_flow_act { u32 encap_id; u32 modify_id; uintptr_t esp_id; + struct mlx5_fs_vlan vlan; }; #define MLX5_DECLARE_FLOW_ACT(name) \ diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 1f3483d40055..c19e611d2782 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -314,7 +314,10 @@ struct mlx5_ifc_flow_table_prop_layout_bits { u8 flow_table_modify[0x1]; u8 encap[0x1]; u8 decap[0x1]; - u8 reserved_at_9[0x17]; + u8 reserved_at_9[0x1]; + u8 pop_vlan[0x1]; + u8 push_vlan[0x1]; + u8 reserved_at_c[0x14]; u8 reserved_at_20[0x2]; u8 log_max_ft_size[0x6]; @@ -2311,10 +2314,19 @@ enum { MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, + MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, + MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, +}; + +struct mlx5_ifc_vlan_bits { + u8 ethtype[0x10]; + u8 prio[0x3]; + u8 cfi[0x1]; + u8 vid[0xc]; }; struct mlx5_ifc_flow_context_bits { - u8 reserved_at_0[0x20]; + struct mlx5_ifc_vlan_bits push_vlan; u8 group_id[0x20]; -- cgit v1.2.3 From fc5d1073cae299de4517755a910df4f12a6a438f Mon Sep 17 00:00:00 2001 From: David Rientjes Date: Mon, 26 Mar 2018 23:27:21 -0700 Subject: x86/mm/32: Remove unused node_memmap_size_bytes() & CONFIG_NEED_NODE_MEMMAP_SIZE logic node_memmap_size_bytes() has been unused since the v3.9 kernel, so remove it. Signed-off-by: David Rientjes Cc: Dave Hansen Cc: Laura Abbott Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-mm@kvack.org Fixes: f03574f2d5b2 ("x86-32, mm: Rip out x86_32 NUMA remapping code") Link: http://lkml.kernel.org/r/alpine.DEB.2.20.1803262325540.256524@chino.kir.corp.google.com Signed-off-by: Ingo Molnar --- arch/x86/Kconfig | 4 ---- arch/x86/mm/numa_32.c | 11 ----------- include/linux/mmzone.h | 5 ----- mm/sparse.c | 22 ---------------------- 4 files changed, 42 deletions(-) (limited to 'include/linux') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 18233e459bff..739aff253d17 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1608,10 +1608,6 @@ config ARCH_HAVE_MEMORY_PRESENT def_bool y depends on X86_32 && DISCONTIGMEM -config NEED_NODE_MEMMAP_SIZE - def_bool y - depends on X86_32 && (DISCONTIGMEM || SPARSEMEM) - config ARCH_FLATMEM_ENABLE def_bool y depends on X86_32 && !NUMA diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c index aca6295350f3..e8a4a09e20f1 100644 --- a/arch/x86/mm/numa_32.c +++ b/arch/x86/mm/numa_32.c @@ -60,17 +60,6 @@ void memory_present(int nid, unsigned long start, unsigned long end) } printk(KERN_CONT "\n"); } - -unsigned long node_memmap_size_bytes(int nid, unsigned long start_pfn, - unsigned long end_pfn) -{ - unsigned long nr_pages = end_pfn - start_pfn; - - if (!nr_pages) - return 0; - - return (nr_pages + 1) * sizeof(struct page); -} #endif extern unsigned long highend_pfn, highstart_pfn; diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index 7522a6987595..a2db4576e499 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -816,10 +816,6 @@ int local_memory_node(int node_id); static inline int local_memory_node(int node_id) { return node_id; }; #endif -#ifdef CONFIG_NEED_NODE_MEMMAP_SIZE -unsigned long __init node_memmap_size_bytes(int, unsigned long, unsigned long); -#endif - /* * zone_idx() returns 0 for the ZONE_DMA zone, 1 for the ZONE_NORMAL zone, etc. */ @@ -1289,7 +1285,6 @@ struct mminit_pfnnid_cache { #endif void memory_present(int nid, unsigned long start, unsigned long end); -unsigned long __init node_memmap_size_bytes(int, unsigned long, unsigned long); /* * If it is possible to have holes within a MAX_ORDER_NR_PAGES, then we diff --git a/mm/sparse.c b/mm/sparse.c index 7af5e7a92528..79b26f98d793 100644 --- a/mm/sparse.c +++ b/mm/sparse.c @@ -235,28 +235,6 @@ void __init memory_present(int nid, unsigned long start, unsigned long end) } } -/* - * Only used by the i386 NUMA architecures, but relatively - * generic code. - */ -unsigned long __init node_memmap_size_bytes(int nid, unsigned long start_pfn, - unsigned long end_pfn) -{ - unsigned long pfn; - unsigned long nr_pages = 0; - - mminit_validate_memmodel_limits(&start_pfn, &end_pfn); - for (pfn = start_pfn; pfn < end_pfn; pfn += PAGES_PER_SECTION) { - if (nid != early_pfn_to_nid(pfn)) - continue; - - if (pfn_present(pfn)) - nr_pages += PAGES_PER_SECTION; - } - - return nr_pages * sizeof(struct page); -} - /* * Subtle, we encode the real pfn into the mem_map such that * the identity pfn - section_mem_map will return the actual -- cgit v1.2.3 From 5b644aa012f67fd211138a067b9f351f30bdcc60 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Wed, 14 Mar 2018 13:10:42 +0100 Subject: mtd: partitions: add of_match_table parser matching for the "ofpart" type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to properly support compatibility strings as described in the bindings/mtd/partition.txt "ofpart" type should be treated as an indication for looking into OF. MTD should check "compatible" property and search for a matching parser rather than blindly trying the one supporting "fixed-partitions". It also means that existing "fixed-partitions" parser should get renamed to use a more meaningful name. This commit achievies that aim by introducing a new mtd_part_of_parse(). It works by looking for a matching parser for every string in the "compatibility" property (starting with the most specific one). Please note that driver-specified parsers still take a precedence. It's assumed that driver providing a parser type has a good reason for that (e.g. having platform data with device-specific info). Also doing otherwise could break existing setups. The same applies to using default parsers (including "cmdlinepart") as some overwrite DT data with cmdline argument. Partition parsers can now provide an of_match_table to enable flash<-->parser matching via device tree as documented in the mtd/partition.txt. This support is currently limited to built-in parsers as it uses request_module() and friends. This should be sufficient for most cases though as compiling parsers as modules isn't a common choice. Signed-off-by: Brian Norris Signed-off-by: Rafał Miłecki Tested-by: Peter Rosin Reviewed-by: Richard Weinberger Signed-off-by: Boris Brezillon --- drivers/mtd/mtdpart.c | 116 +++++++++++++++++++++++++++++++++++++---- include/linux/mtd/partitions.h | 1 + 2 files changed, 108 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 85fea8ea3423..2b7bb834ff40 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "mtdcore.h" @@ -845,6 +846,92 @@ static int mtd_part_do_parse(struct mtd_part_parser *parser, return ret; } +/** + * mtd_part_get_compatible_parser - find MTD parser by a compatible string + * + * @compat: compatible string describing partitions in a device tree + * + * MTD parsers can specify supported partitions by providing a table of + * compatibility strings. This function finds a parser that advertises support + * for a passed value of "compatible". + */ +static struct mtd_part_parser *mtd_part_get_compatible_parser(const char *compat) +{ + struct mtd_part_parser *p, *ret = NULL; + + spin_lock(&part_parser_lock); + + list_for_each_entry(p, &part_parsers, list) { + const struct of_device_id *matches; + + matches = p->of_match_table; + if (!matches) + continue; + + for (; matches->compatible[0]; matches++) { + if (!strcmp(matches->compatible, compat) && + try_module_get(p->owner)) { + ret = p; + break; + } + } + + if (ret) + break; + } + + spin_unlock(&part_parser_lock); + + return ret; +} + +static int mtd_part_of_parse(struct mtd_info *master, + struct mtd_partitions *pparts) +{ + struct mtd_part_parser *parser; + struct device_node *np; + struct property *prop; + const char *compat; + const char *fixed = "ofpart"; + int ret, err = 0; + + np = of_get_child_by_name(mtd_get_of_node(master), "partitions"); + of_property_for_each_string(np, "compatible", prop, compat) { + parser = mtd_part_get_compatible_parser(compat); + if (!parser) + continue; + ret = mtd_part_do_parse(parser, master, pparts, NULL); + if (ret > 0) { + of_node_put(np); + return ret; + } + mtd_part_parser_put(parser); + if (ret < 0 && !err) + err = ret; + } + of_node_put(np); + + /* + * For backward compatibility we have to try the "ofpart" + * parser. It supports old DT format with partitions specified as a + * direct subnodes of a flash device DT node without any compatibility + * specified we could match. + */ + parser = mtd_part_parser_get(fixed); + if (!parser && !request_module("%s", fixed)) + parser = mtd_part_parser_get(fixed); + if (parser) { + ret = mtd_part_do_parse(parser, master, pparts, NULL); + if (ret > 0) + return ret; + mtd_part_parser_put(parser); + if (ret < 0 && !err) + err = ret; + } + + return err; +} + /** * parse_mtd_partitions - parse MTD partitions * @master: the master partition (describes whole MTD device) @@ -877,19 +964,30 @@ int parse_mtd_partitions(struct mtd_info *master, const char *const *types, types = default_mtd_part_types; for ( ; *types; types++) { - pr_debug("%s: parsing partitions %s\n", master->name, *types); - parser = mtd_part_parser_get(*types); - if (!parser && !request_module("%s", *types)) + /* + * ofpart is a special type that means OF partitioning info + * should be used. It requires a bit different logic so it is + * handled in a separated function. + */ + if (!strcmp(*types, "ofpart")) { + ret = mtd_part_of_parse(master, pparts); + } else { + pr_debug("%s: parsing partitions %s\n", master->name, + *types); parser = mtd_part_parser_get(*types); - pr_debug("%s: got parser %s\n", master->name, - parser ? parser->name : NULL); - if (!parser) - continue; - ret = mtd_part_do_parse(parser, master, pparts, data); + if (!parser && !request_module("%s", *types)) + parser = mtd_part_parser_get(*types); + pr_debug("%s: got parser %s\n", master->name, + parser ? parser->name : NULL); + if (!parser) + continue; + ret = mtd_part_do_parse(parser, master, pparts, data); + if (ret <= 0) + mtd_part_parser_put(parser); + } /* Found partitions! */ if (ret > 0) return 0; - mtd_part_parser_put(parser); /* * Stash the first error we see; only report it if no parser * succeeds diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index c4beb70dacbd..11cb0c50cd84 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -77,6 +77,7 @@ struct mtd_part_parser { struct list_head list; struct module *owner; const char *name; + const struct of_device_id *of_match_table; int (*parse_fn)(struct mtd_info *, const struct mtd_partition **, struct mtd_part_parser_data *); void (*cleanup)(const struct mtd_partition *pparts, int nr_parts); -- cgit v1.2.3 From 6691dffab0ab6301bb7b489b1dcf9f5efdef202f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 28 Feb 2018 14:08:57 +0100 Subject: reset: add support for non-DT systems The reset framework only supports device-tree. There are some platforms however, which need to use it even in legacy, board-file based mode. An example of such architecture is the DaVinci family of SoCs which supports both device tree and legacy boot modes and we don't want to introduce any regressions. We're currently working on converting the platform from its hand-crafted clock API to using the common clock framework. Part of the overhaul will be representing the chip's power sleep controller's reset lines using the reset framework. This changeset extends the core reset code with a new reset lookup entry structure. It contains data allowing the reset core to associate reset lines with devices by comparing the dev_id and con_id strings. It also provides a function allowing drivers to register lookup entries with the framework. The new lookup function is only called as a fallback in case the of_node field is NULL and doesn't change anything for current users. Tested with a dummy reset driver with several lookup entries. An example lookup table registration from a driver can be found below: static struct reset_control_lookup foobar_reset_lookup[] = { RESET_LOOKUP("foo.0", "foo", 15), RESET_LOOKUP("bar.0", NULL, 5), }; foobar_probe() { ... reset_controller_add_lookup(&rcdev, foobar_reset_lookup, ARRAY_SIZE(foobar_reset_lookup)); ... } Cc: Sekhar Nori Cc: Kevin Hilman Cc: David Lechner Signed-off-by: Bartosz Golaszewski Signed-off-by: Philipp Zabel --- drivers/reset/core.c | 72 +++++++++++++++++++++++++++++++++++++++- include/linux/reset-controller.h | 28 ++++++++++++++++ 2 files changed, 99 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/drivers/reset/core.c b/drivers/reset/core.c index da4292e9de97..06fa4907afc4 100644 --- a/drivers/reset/core.c +++ b/drivers/reset/core.c @@ -23,6 +23,9 @@ static DEFINE_MUTEX(reset_list_mutex); static LIST_HEAD(reset_controller_list); +static DEFINE_MUTEX(reset_lookup_mutex); +static LIST_HEAD(reset_lookup_list); + /** * struct reset_control - a reset control * @rcdev: a pointer to the reset controller device @@ -148,6 +151,36 @@ int devm_reset_controller_register(struct device *dev, } EXPORT_SYMBOL_GPL(devm_reset_controller_register); +/** + * reset_controller_add_lookup - register a set of lookup entries + * @rcdev: initialized reset controller device owning the reset line + * @lookup: array of reset lookup entries + * @num_entries: number of entries in the lookup array + */ +void reset_controller_add_lookup(struct reset_controller_dev *rcdev, + struct reset_control_lookup *lookup, + unsigned int num_entries) +{ + struct reset_control_lookup *entry; + unsigned int i; + + mutex_lock(&reset_lookup_mutex); + for (i = 0; i < num_entries; i++) { + entry = &lookup[i]; + + if (!entry->dev_id) { + pr_warn("%s(): reset lookup entry has no dev_id, skipping\n", + __func__); + continue; + } + + entry->rcdev = rcdev; + list_add_tail(&entry->list, &reset_lookup_list); + } + mutex_unlock(&reset_lookup_mutex); +} +EXPORT_SYMBOL_GPL(reset_controller_add_lookup); + static inline struct reset_control_array * rstc_to_array(struct reset_control *rstc) { return container_of(rstc, struct reset_control_array, base); @@ -493,6 +526,43 @@ struct reset_control *__of_reset_control_get(struct device_node *node, } EXPORT_SYMBOL_GPL(__of_reset_control_get); +static struct reset_control * +__reset_control_get_from_lookup(struct device *dev, const char *con_id, + bool shared, bool optional) +{ + const struct reset_control_lookup *lookup; + const char *dev_id = dev_name(dev); + struct reset_control *rstc = NULL; + + if (!dev) + return ERR_PTR(-EINVAL); + + mutex_lock(&reset_lookup_mutex); + + list_for_each_entry(lookup, &reset_lookup_list, list) { + if (strcmp(lookup->dev_id, dev_id)) + continue; + + if ((!con_id && !lookup->con_id) || + ((con_id && lookup->con_id) && + !strcmp(con_id, lookup->con_id))) { + mutex_lock(&reset_list_mutex); + rstc = __reset_control_get_internal(lookup->rcdev, + lookup->index, + shared); + mutex_unlock(&reset_list_mutex); + break; + } + } + + mutex_unlock(&reset_lookup_mutex); + + if (!rstc) + return optional ? NULL : ERR_PTR(-ENOENT); + + return rstc; +} + struct reset_control *__reset_control_get(struct device *dev, const char *id, int index, bool shared, bool optional) { @@ -500,7 +570,7 @@ struct reset_control *__reset_control_get(struct device *dev, const char *id, return __of_reset_control_get(dev->of_node, id, index, shared, optional); - return optional ? NULL : ERR_PTR(-EINVAL); + return __reset_control_get_from_lookup(dev, id, shared, optional); } EXPORT_SYMBOL_GPL(__reset_control_get); diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h index adb88f8cefbc..25698f6c1fae 100644 --- a/include/linux/reset-controller.h +++ b/include/linux/reset-controller.h @@ -26,6 +26,30 @@ struct module; struct device_node; struct of_phandle_args; +/** + * struct reset_control_lookup - represents a single lookup entry + * + * @list: internal list of all reset lookup entries + * @rcdev: reset controller device controlling this reset line + * @index: ID of the reset controller in the reset controller device + * @dev_id: name of the device associated with this reset line + * @con_id name of the reset line (can be NULL) + */ +struct reset_control_lookup { + struct list_head list; + struct reset_controller_dev *rcdev; + unsigned int index; + const char *dev_id; + const char *con_id; +}; + +#define RESET_LOOKUP(_dev_id, _con_id, _index) \ + { \ + .dev_id = _dev_id, \ + .con_id = _con_id, \ + .index = _index, \ + } + /** * struct reset_controller_dev - reset controller entity that might * provide multiple reset controls @@ -58,4 +82,8 @@ struct device; int devm_reset_controller_register(struct device *dev, struct reset_controller_dev *rcdev); +void reset_controller_add_lookup(struct reset_controller_dev *rcdev, + struct reset_control_lookup *lookup, + unsigned int num_entries); + #endif -- cgit v1.2.3 From e2749bb998701e21cdb8b34486b82fc1c051ab41 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Fri, 23 Mar 2018 14:04:48 +0100 Subject: reset: modify the way reset lookup works for board files Commit 7af1bb19f1d7 ("reset: add support for non-DT systems") introduced reset control lookup mechanism for boards that still use board files. The routine used to register lookup entries takes the corresponding reset_controlled_dev structure as argument. It's been determined however that for the first user of this new interface - davinci psc driver - it will be easier to register the lookup entries using the reset controller device name. This patch changes the way lookup entries are added. Signed-off-by: Bartosz Golaszewski [p.zabel@pengutronix.de: added missing ERR_PTR] Signed-off-by: Philipp Zabel --- drivers/reset/core.c | 38 +++++++++++++++++++++++++++++++------- include/linux/reset-controller.h | 14 ++++++++------ 2 files changed, 39 insertions(+), 13 deletions(-) (limited to 'include/linux') diff --git a/drivers/reset/core.c b/drivers/reset/core.c index 06fa4907afc4..6488292e129c 100644 --- a/drivers/reset/core.c +++ b/drivers/reset/core.c @@ -153,12 +153,10 @@ EXPORT_SYMBOL_GPL(devm_reset_controller_register); /** * reset_controller_add_lookup - register a set of lookup entries - * @rcdev: initialized reset controller device owning the reset line * @lookup: array of reset lookup entries * @num_entries: number of entries in the lookup array */ -void reset_controller_add_lookup(struct reset_controller_dev *rcdev, - struct reset_control_lookup *lookup, +void reset_controller_add_lookup(struct reset_control_lookup *lookup, unsigned int num_entries) { struct reset_control_lookup *entry; @@ -168,13 +166,12 @@ void reset_controller_add_lookup(struct reset_controller_dev *rcdev, for (i = 0; i < num_entries; i++) { entry = &lookup[i]; - if (!entry->dev_id) { - pr_warn("%s(): reset lookup entry has no dev_id, skipping\n", + if (!entry->dev_id || !entry->provider) { + pr_warn("%s(): reset lookup entry badly specified, skipping\n", __func__); continue; } - entry->rcdev = rcdev; list_add_tail(&entry->list, &reset_lookup_list); } mutex_unlock(&reset_lookup_mutex); @@ -526,11 +523,30 @@ struct reset_control *__of_reset_control_get(struct device_node *node, } EXPORT_SYMBOL_GPL(__of_reset_control_get); +static struct reset_controller_dev * +__reset_controller_by_name(const char *name) +{ + struct reset_controller_dev *rcdev; + + lockdep_assert_held(&reset_list_mutex); + + list_for_each_entry(rcdev, &reset_controller_list, list) { + if (!rcdev->dev) + continue; + + if (!strcmp(name, dev_name(rcdev->dev))) + return rcdev; + } + + return NULL; +} + static struct reset_control * __reset_control_get_from_lookup(struct device *dev, const char *con_id, bool shared, bool optional) { const struct reset_control_lookup *lookup; + struct reset_controller_dev *rcdev; const char *dev_id = dev_name(dev); struct reset_control *rstc = NULL; @@ -547,7 +563,15 @@ __reset_control_get_from_lookup(struct device *dev, const char *con_id, ((con_id && lookup->con_id) && !strcmp(con_id, lookup->con_id))) { mutex_lock(&reset_list_mutex); - rstc = __reset_control_get_internal(lookup->rcdev, + rcdev = __reset_controller_by_name(lookup->provider); + if (!rcdev) { + mutex_unlock(&reset_list_mutex); + mutex_unlock(&reset_lookup_mutex); + /* Reset provider may not be ready yet. */ + return ERR_PTR(-EPROBE_DEFER); + } + + rstc = __reset_control_get_internal(rcdev, lookup->index, shared); mutex_unlock(&reset_list_mutex); diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h index 25698f6c1fae..9326d671b6e6 100644 --- a/include/linux/reset-controller.h +++ b/include/linux/reset-controller.h @@ -30,24 +30,25 @@ struct of_phandle_args; * struct reset_control_lookup - represents a single lookup entry * * @list: internal list of all reset lookup entries - * @rcdev: reset controller device controlling this reset line + * @provider: name of the reset controller device controlling this reset line * @index: ID of the reset controller in the reset controller device * @dev_id: name of the device associated with this reset line * @con_id name of the reset line (can be NULL) */ struct reset_control_lookup { struct list_head list; - struct reset_controller_dev *rcdev; + const char *provider; unsigned int index; const char *dev_id; const char *con_id; }; -#define RESET_LOOKUP(_dev_id, _con_id, _index) \ +#define RESET_LOOKUP(_provider, _index, _dev_id, _con_id) \ { \ + .provider = _provider, \ + .index = _index, \ .dev_id = _dev_id, \ .con_id = _con_id, \ - .index = _index, \ } /** @@ -57,6 +58,7 @@ struct reset_control_lookup { * @owner: kernel module of the reset controller driver * @list: internal list of reset controller devices * @reset_control_head: head of internal list of requested reset controls + * @dev: corresponding driver model device struct * @of_node: corresponding device tree node as phandle target * @of_reset_n_cells: number of cells in reset line specifiers * @of_xlate: translation function to translate from specifier as found in the @@ -68,6 +70,7 @@ struct reset_controller_dev { struct module *owner; struct list_head list; struct list_head reset_control_head; + struct device *dev; struct device_node *of_node; int of_reset_n_cells; int (*of_xlate)(struct reset_controller_dev *rcdev, @@ -82,8 +85,7 @@ struct device; int devm_reset_controller_register(struct device *dev, struct reset_controller_dev *rcdev); -void reset_controller_add_lookup(struct reset_controller_dev *rcdev, - struct reset_control_lookup *lookup, +void reset_controller_add_lookup(struct reset_control_lookup *lookup, unsigned int num_entries); #endif -- cgit v1.2.3 From 3af345258617e0412059c1ab6462495947f73e89 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 20 Mar 2018 20:07:59 +0200 Subject: firmware/dmi_scan: Uninline dmi_get_bios_year() helper Uninline dmi_get_bios_year() which, in particular, allows us to optimize it in the future. While doing this, convert the function to return an error code when BIOS date is not present or not parsable, or CONFIG_DMI=n. Additionally, during the move, add a bit of documentation. Suggested-by: Bjorn Helgaas Suggested-by: Rafael J. Wysocki Signed-off-by: Andy Shevchenko Reviewed-by: Jean Delvare Reviewed-by: Rafael J. Wysocki Acked-by: Thomas Gleixner Cc: Bjorn Helgaas Cc: Linus Torvalds Cc: Lukas Wunner Cc: Peter Zijlstra Cc: Rafael J . Wysocki Cc: linux-acpi@vger.kernel.org Cc: linux-pci@vger.kernel.org Fixes: 492a1abd61e4 ("dmi: Introduce the dmi_get_bios_year() helper function") Signed-off-by: Ingo Molnar --- drivers/firmware/dmi_scan.c | 20 ++++++++++++++++++++ include/linux/dmi.h | 11 ++--------- 2 files changed, 22 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/drivers/firmware/dmi_scan.c b/drivers/firmware/dmi_scan.c index e763e1484331..e35c5e04c46a 100644 --- a/drivers/firmware/dmi_scan.c +++ b/drivers/firmware/dmi_scan.c @@ -1004,6 +1004,26 @@ out: } EXPORT_SYMBOL(dmi_get_date); +/** + * dmi_get_bios_year - get a year out of DMI_BIOS_DATE field + * + * Returns year on success, -ENXIO if DMI is not selected, + * or a different negative error code if DMI field is not present + * or not parseable. + */ +int dmi_get_bios_year(void) +{ + bool exists; + int year; + + exists = dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL); + if (!exists) + return -ENODATA; + + return year ? year : -ERANGE; +} +EXPORT_SYMBOL(dmi_get_bios_year); + /** * dmi_walk - Walk the DMI table and get called back for every record * @decode: Callback function diff --git a/include/linux/dmi.h b/include/linux/dmi.h index 0bade156e908..6a86d8db16d9 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -106,6 +106,7 @@ extern void dmi_scan_machine(void); extern void dmi_memdev_walk(void); extern void dmi_set_dump_stack_arch_desc(void); extern bool dmi_get_date(int field, int *yearp, int *monthp, int *dayp); +extern int dmi_get_bios_year(void); extern int dmi_name_in_vendors(const char *str); extern int dmi_name_in_serial(const char *str); extern int dmi_available; @@ -133,6 +134,7 @@ static inline bool dmi_get_date(int field, int *yearp, int *monthp, int *dayp) *dayp = 0; return false; } +static inline int dmi_get_bios_year(void) { return -ENXIO; } static inline int dmi_name_in_vendors(const char *s) { return 0; } static inline int dmi_name_in_serial(const char *s) { return 0; } #define dmi_available 0 @@ -147,13 +149,4 @@ static inline const struct dmi_system_id * #endif -static inline int dmi_get_bios_year(void) -{ - int year; - - dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL); - - return year; -} - #endif /* __DMI_H__ */ -- cgit v1.2.3 From 726cb3ba49692bdae6caff457755e7cdb432efa4 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 23 Mar 2018 09:34:52 -0700 Subject: gpiolib: Support 'gpio-reserved-ranges' property Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Add support for a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Non-DT platforms can add support by directly updating the chip->valid_mask. Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd Tested-by: Timur Tabi Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/gpio/gpiolib-of.c | 24 +++++++++++++++++++++++ drivers/gpio/gpiolib.c | 46 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/gpio/driver.h | 16 ++++++++++++++++ 3 files changed, 86 insertions(+) (limited to 'include/linux') diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 84e5a9df2344..ed81d9a6316f 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -511,6 +511,28 @@ void of_mm_gpiochip_remove(struct of_mm_gpio_chip *mm_gc) } EXPORT_SYMBOL(of_mm_gpiochip_remove); +static void of_gpiochip_init_valid_mask(struct gpio_chip *chip) +{ + int len, i; + u32 start, count; + struct device_node *np = chip->of_node; + + len = of_property_count_u32_elems(np, "gpio-reserved-ranges"); + if (len < 0 || len % 2 != 0) + return; + + for (i = 0; i < len; i += 2) { + of_property_read_u32_index(np, "gpio-reserved-ranges", + i, &start); + of_property_read_u32_index(np, "gpio-reserved-ranges", + i + 1, &count); + if (start >= chip->ngpio || start + count >= chip->ngpio) + continue; + + bitmap_clear(chip->valid_mask, start, count); + } +}; + #ifdef CONFIG_PINCTRL static int of_gpiochip_add_pin_range(struct gpio_chip *chip) { @@ -615,6 +637,8 @@ int of_gpiochip_add(struct gpio_chip *chip) if (chip->of_gpio_n_cells > MAX_PHANDLE_ARGS) return -EINVAL; + of_gpiochip_init_valid_mask(chip); + status = of_gpiochip_add_pin_range(chip); if (status) return status; diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index db3788d17ba0..fecbb553e8a4 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -351,6 +351,43 @@ static unsigned long *gpiochip_allocate_mask(struct gpio_chip *chip) return p; } +static int gpiochip_init_valid_mask(struct gpio_chip *gpiochip) +{ +#ifdef CONFIG_OF_GPIO + int size; + struct device_node *np = gpiochip->of_node; + + size = of_property_count_u32_elems(np, "gpio-reserved-ranges"); + if (size > 0 && size % 2 == 0) + gpiochip->need_valid_mask = true; +#endif + + if (!gpiochip->need_valid_mask) + return 0; + + gpiochip->valid_mask = gpiochip_allocate_mask(gpiochip); + if (!gpiochip->valid_mask) + return -ENOMEM; + + return 0; +} + +static void gpiochip_free_valid_mask(struct gpio_chip *gpiochip) +{ + kfree(gpiochip->valid_mask); + gpiochip->valid_mask = NULL; +} + +bool gpiochip_line_is_valid(const struct gpio_chip *gpiochip, + unsigned int offset) +{ + /* No mask means all valid */ + if (likely(!gpiochip->valid_mask)) + return true; + return test_bit(offset, gpiochip->valid_mask); +} +EXPORT_SYMBOL_GPL(gpiochip_line_is_valid); + /* * GPIO line handle management */ @@ -1275,6 +1312,10 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, if (status) goto err_remove_from_list; + status = gpiochip_init_valid_mask(chip); + if (status) + goto err_remove_irqchip_mask; + status = gpiochip_add_irqchip(chip, lock_key, request_key); if (status) goto err_remove_chip; @@ -1304,6 +1345,8 @@ err_remove_chip: acpi_gpiochip_remove(chip); gpiochip_free_hogs(chip); of_gpiochip_remove(chip); + gpiochip_free_valid_mask(chip); +err_remove_irqchip_mask: gpiochip_irqchip_free_valid_mask(chip); err_remove_from_list: spin_lock_irqsave(&gpio_lock, flags); @@ -1360,6 +1403,7 @@ void gpiochip_remove(struct gpio_chip *chip) acpi_gpiochip_remove(chip); gpiochip_remove_pin_ranges(chip); of_gpiochip_remove(chip); + gpiochip_free_valid_mask(chip); /* * We accept no more calls into the driver from this point, so * NULL the driver data pointer @@ -1536,6 +1580,8 @@ static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip) bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, unsigned int offset) { + if (!gpiochip_line_is_valid(gpiochip, offset)) + return false; /* No mask means all valid */ if (likely(!gpiochip->irq.valid_mask)) return true; diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 1ba9a331ec51..5382b5183b7e 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -288,6 +288,21 @@ struct gpio_chip { struct gpio_irq_chip irq; #endif + /** + * @need_valid_mask: + * + * If set core allocates @valid_mask with all bits set to one. + */ + bool need_valid_mask; + + /** + * @valid_mask: + * + * If not %NULL holds bitmask of GPIOs which are valid to be used + * from the chip. + */ + unsigned long *valid_mask; + #if defined(CONFIG_OF_GPIO) /* * If CONFIG_OF is enabled, then all GPIO controllers described in the @@ -384,6 +399,7 @@ bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset); /* Sleep persistence inquiry for drivers */ bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset); +bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset); /* get driver data */ void *gpiochip_get_data(struct gpio_chip *chip); -- cgit v1.2.3 From 4420bf21fb6c0306e36ad58ade1e741fba57ce65 Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Tue, 27 Mar 2018 18:02:23 +0300 Subject: net: Rename net_sem to pernet_ops_rwsem net_sem is some undefined area name, so it will be better to make the area more defined. Rename it to pernet_ops_rwsem for better readability and better intelligibility. Signed-off-by: Kirill Tkhai Signed-off-by: David S. Miller --- include/linux/rtnetlink.h | 2 +- include/net/net_namespace.h | 12 +++++++----- net/core/net_namespace.c | 40 ++++++++++++++++++++-------------------- net/core/rtnetlink.c | 4 ++-- 4 files changed, 30 insertions(+), 28 deletions(-) (limited to 'include/linux') diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 562a175c35a9..c7d1e4689325 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -36,7 +36,7 @@ extern int rtnl_is_locked(void); extern int rtnl_lock_killable(void); extern wait_queue_head_t netdev_unregistering_wq; -extern struct rw_semaphore net_sem; +extern struct rw_semaphore pernet_ops_rwsem; #ifdef CONFIG_PROVE_LOCKING extern bool lockdep_rtnl_is_held(void); diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h index 37bcf8382b61..922e8b6fb422 100644 --- a/include/net/net_namespace.h +++ b/include/net/net_namespace.h @@ -60,9 +60,10 @@ struct net { struct list_head list; /* list of network namespaces */ struct list_head exit_list; /* To linked to call pernet exit - * methods on dead net (net_sem - * read locked), or to unregister - * pernet ops (net_sem wr locked). + * methods on dead net ( + * pernet_ops_rwsem read locked), + * or to unregister pernet ops + * (pernet_ops_rwsem write locked). */ struct llist_node cleanup_list; /* namespaces on death row */ @@ -95,8 +96,9 @@ struct net { /* core fib_rules */ struct list_head rules_ops; - struct list_head fib_notifier_ops; /* protected by net_sem */ - + struct list_head fib_notifier_ops; /* Populated by + * register_pernet_subsys() + */ struct net_device *loopback_dev; /* The loopback */ struct netns_core core; struct netns_mib mib; diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c index eef17ad29dea..9e8ee4640451 100644 --- a/net/core/net_namespace.c +++ b/net/core/net_namespace.c @@ -41,10 +41,10 @@ EXPORT_SYMBOL(init_net); static bool init_net_initialized; /* - * net_sem: protects: pernet_list, net_generic_ids, + * pernet_ops_rwsem: protects: pernet_list, net_generic_ids, * init_net_initialized and first_device pointer. */ -DECLARE_RWSEM(net_sem); +DECLARE_RWSEM(pernet_ops_rwsem); #define MIN_PERNET_OPS_ID \ ((sizeof(struct net_generic) + sizeof(void *) - 1) / sizeof(void *)) @@ -72,7 +72,7 @@ static int net_assign_generic(struct net *net, unsigned int id, void *data) BUG_ON(id < MIN_PERNET_OPS_ID); old_ng = rcu_dereference_protected(net->gen, - lockdep_is_held(&net_sem)); + lockdep_is_held(&pernet_ops_rwsem)); if (old_ng->s.len > id) { old_ng->ptr[id] = data; return 0; @@ -289,7 +289,7 @@ struct net *get_net_ns_by_id(struct net *net, int id) */ static __net_init int setup_net(struct net *net, struct user_namespace *user_ns) { - /* Must be called with net_sem held */ + /* Must be called with pernet_ops_rwsem held */ const struct pernet_operations *ops, *saved_ops; int error = 0; LIST_HEAD(net_exit_list); @@ -422,13 +422,13 @@ struct net *copy_net_ns(unsigned long flags, net->ucounts = ucounts; get_user_ns(user_ns); - rv = down_read_killable(&net_sem); + rv = down_read_killable(&pernet_ops_rwsem); if (rv < 0) goto put_userns; rv = setup_net(net, user_ns); - up_read(&net_sem); + up_read(&pernet_ops_rwsem); if (rv < 0) { put_userns: @@ -480,7 +480,7 @@ static void cleanup_net(struct work_struct *work) /* Atomically snapshot the list of namespaces to cleanup */ net_kill_list = llist_del_all(&cleanup_list); - down_read(&net_sem); + down_read(&pernet_ops_rwsem); /* Don't let anyone else find us. */ rtnl_lock(); @@ -519,7 +519,7 @@ static void cleanup_net(struct work_struct *work) list_for_each_entry_reverse(ops, &pernet_list, list) ops_free_list(ops, &net_exit_list); - up_read(&net_sem); + up_read(&pernet_ops_rwsem); /* Ensure there are no outstanding rcu callbacks using this * network namespace. @@ -546,8 +546,8 @@ static void cleanup_net(struct work_struct *work) */ void net_ns_barrier(void) { - down_write(&net_sem); - up_write(&net_sem); + down_write(&pernet_ops_rwsem); + up_write(&pernet_ops_rwsem); } EXPORT_SYMBOL(net_ns_barrier); @@ -869,12 +869,12 @@ static int __init net_ns_init(void) rcu_assign_pointer(init_net.gen, ng); - down_write(&net_sem); + down_write(&pernet_ops_rwsem); if (setup_net(&init_net, &init_user_ns)) panic("Could not setup the initial network namespace"); init_net_initialized = true; - up_write(&net_sem); + up_write(&pernet_ops_rwsem); register_pernet_subsys(&net_ns_ops); @@ -1013,9 +1013,9 @@ static void unregister_pernet_operations(struct pernet_operations *ops) int register_pernet_subsys(struct pernet_operations *ops) { int error; - down_write(&net_sem); + down_write(&pernet_ops_rwsem); error = register_pernet_operations(first_device, ops); - up_write(&net_sem); + up_write(&pernet_ops_rwsem); return error; } EXPORT_SYMBOL_GPL(register_pernet_subsys); @@ -1031,9 +1031,9 @@ EXPORT_SYMBOL_GPL(register_pernet_subsys); */ void unregister_pernet_subsys(struct pernet_operations *ops) { - down_write(&net_sem); + down_write(&pernet_ops_rwsem); unregister_pernet_operations(ops); - up_write(&net_sem); + up_write(&pernet_ops_rwsem); } EXPORT_SYMBOL_GPL(unregister_pernet_subsys); @@ -1059,11 +1059,11 @@ EXPORT_SYMBOL_GPL(unregister_pernet_subsys); int register_pernet_device(struct pernet_operations *ops) { int error; - down_write(&net_sem); + down_write(&pernet_ops_rwsem); error = register_pernet_operations(&pernet_list, ops); if (!error && (first_device == &pernet_list)) first_device = &ops->list; - up_write(&net_sem); + up_write(&pernet_ops_rwsem); return error; } EXPORT_SYMBOL_GPL(register_pernet_device); @@ -1079,11 +1079,11 @@ EXPORT_SYMBOL_GPL(register_pernet_device); */ void unregister_pernet_device(struct pernet_operations *ops) { - down_write(&net_sem); + down_write(&pernet_ops_rwsem); if (&ops->list == first_device) first_device = first_device->next; unregister_pernet_operations(ops); - up_write(&net_sem); + up_write(&pernet_ops_rwsem); } EXPORT_SYMBOL_GPL(unregister_pernet_device); diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 31438b63d4b4..73011a60434c 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -460,11 +460,11 @@ static void rtnl_lock_unregistering_all(void) void rtnl_link_unregister(struct rtnl_link_ops *ops) { /* Close the race with cleanup_net() */ - down_write(&net_sem); + down_write(&pernet_ops_rwsem); rtnl_lock_unregistering_all(); __rtnl_link_unregister(ops); rtnl_unlock(); - up_write(&net_sem); + up_write(&pernet_ops_rwsem); } EXPORT_SYMBOL_GPL(rtnl_link_unregister); -- cgit v1.2.3 From c8d75a980fab886a9c716567e6b47cc414ad84ee Mon Sep 17 00:00:00 2001 From: Majd Dibbiny Date: Thu, 22 Mar 2018 15:34:04 +0200 Subject: IB/mlx5: Respect new UMR capabilities In some firmware configuration, UMR usage from Virtual Functions is restricted. This information is published to the driver using new capability bits. Avoid using UMRs in these cases and use the Firmware slow-path flow to create mkeys and populate them with Virtual to Physical address translation. Older drivers that do not have this patch, will end up using memory keys that aren't populated with Virtual to Physical address translation that is done part of the UMR work. Reviewed-by: Mark Bloch Signed-off-by: Majd Dibbiny Signed-off-by: Leon Romanovsky Tested-by: Laurence Oberman Signed-off-by: Jason Gunthorpe --- drivers/infiniband/hw/mlx5/mr.c | 35 ++++++++++++++++++++++++++++++----- drivers/infiniband/hw/mlx5/qp.c | 21 ++++++++++++++++++--- include/linux/mlx5/mlx5_ifc.h | 6 +++++- 3 files changed, 53 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c index bcf5e22cf743..60683090d138 100644 --- a/drivers/infiniband/hw/mlx5/mr.c +++ b/drivers/infiniband/hw/mlx5/mr.c @@ -51,6 +51,21 @@ static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); static int mr_cache_max_order(struct mlx5_ib_dev *dev); static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); +static bool umr_can_modify_entity_size(struct mlx5_ib_dev *dev) +{ + return !MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled); +} + +static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev) +{ + return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled); +} + +static bool use_umr(struct mlx5_ib_dev *dev, int order) +{ + return order <= mr_cache_max_order(dev) && + umr_can_modify_entity_size(dev); +} static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) { @@ -956,7 +971,10 @@ static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages, { struct mlx5_ib_dev *dev = mr->dev; struct ib_umem *umem = mr->umem; + if (flags & MLX5_IB_UPD_XLT_INDIRECT) { + if (!umr_can_use_indirect_mkey(dev)) + return -EPERM; mlx5_odp_populate_klm(xlt, idx, npages, mr, flags); return npages; } @@ -1003,6 +1021,10 @@ int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, gfp_t gfp; bool use_emergency_page = false; + if ((flags & MLX5_IB_UPD_XLT_INDIRECT) && + !umr_can_use_indirect_mkey(dev)) + return -EPERM; + /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, * so we need to align the offset and length accordingly */ @@ -1211,13 +1233,13 @@ struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, { struct mlx5_ib_dev *dev = to_mdev(pd->device); struct mlx5_ib_mr *mr = NULL; + bool populate_mtts = false; struct ib_umem *umem; int page_shift; int npages; int ncont; int order; int err; - bool use_umr = true; if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM)) return ERR_PTR(-EOPNOTSUPP); @@ -1244,26 +1266,29 @@ struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, if (err < 0) return ERR_PTR(err); - if (order <= mr_cache_max_order(dev)) { + if (use_umr(dev, order)) { mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont, page_shift, order, access_flags); if (PTR_ERR(mr) == -EAGAIN) { mlx5_ib_dbg(dev, "cache empty for order %d\n", order); mr = NULL; } + populate_mtts = false; } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { if (access_flags & IB_ACCESS_ON_DEMAND) { err = -EINVAL; pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n"); goto error; } - use_umr = false; + populate_mtts = true; } if (!mr) { + if (!umr_can_modify_entity_size(dev)) + populate_mtts = true; mutex_lock(&dev->slow_path_mutex); mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, - page_shift, access_flags, !use_umr); + page_shift, access_flags, populate_mtts); mutex_unlock(&dev->slow_path_mutex); } @@ -1281,7 +1306,7 @@ struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, update_odp_mr(mr); #endif - if (use_umr) { + if (!populate_mtts) { int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE; if (access_flags & IB_ACCESS_ON_DEMAND) diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index 2fb3d9a400d3..c152c6f35101 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -3697,8 +3697,19 @@ static __be64 get_umr_update_pd_mask(void) return cpu_to_be64(result); } -static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, - struct ib_send_wr *wr, int atomic) +static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) +{ + if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && + MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || + (mask & MLX5_MKEY_MASK_A && + MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) + return -EPERM; + return 0; +} + +static int set_reg_umr_segment(struct mlx5_ib_dev *dev, + struct mlx5_wqe_umr_ctrl_seg *umr, + struct ib_send_wr *wr, int atomic) { struct mlx5_umr_wr *umrwr = umr_wr(wr); @@ -3730,6 +3741,8 @@ static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, if (!wr->num_sge) umr->flags |= MLX5_UMR_INLINE; + + return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); } static u8 get_umr_flags(int acc) @@ -4552,7 +4565,9 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, } qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); - set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); + err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); + if (unlikely(err)) + goto out; seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; if (unlikely((seg == qend))) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index c63bbdc35503..64963fd2cd9b 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -916,7 +916,11 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_202[0x1]; u8 ipoib_enhanced_offloads[0x1]; u8 ipoib_basic_offloads[0x1]; - u8 reserved_at_205[0x5]; + u8 reserved_at_205[0x1]; + u8 repeated_block_disabled[0x1]; + u8 umr_modify_entity_size_disabled[0x1]; + u8 umr_modify_atomic_disabled[0x1]; + u8 umr_indirect_mkey_disabled[0x1]; u8 umr_fence[0x2]; u8 reserved_at_20c[0x3]; u8 drain_sigerr[0x1]; -- cgit v1.2.3 From 2816077127230ef52cc7497903e71def45747611 Mon Sep 17 00:00:00 2001 From: Eran Ben Elisha Date: Tue, 26 Dec 2017 15:17:05 +0200 Subject: mlx5_{ib,core}: Add query SQ state helper function Move query SQ state function from mlx5_ib to mlx5_core in order to have it in shared code. It will be used in a downstream patch from mlx5e. Signed-off-by: Eran Ben Elisha Signed-off-by: Saeed Mahameed --- drivers/infiniband/hw/mlx5/qp.c | 14 +----------- drivers/net/ethernet/mellanox/mlx5/core/transobj.c | 25 ++++++++++++++++++++++ include/linux/mlx5/transobj.h | 1 + 3 files changed, 27 insertions(+), 13 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index 85c612ac547a..0d0b0b8dad98 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -4739,26 +4739,14 @@ static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, struct mlx5_ib_sq *sq, u8 *sq_state) { - void *out; - void *sqc; - int inlen; int err; - inlen = MLX5_ST_SZ_BYTES(query_sq_out); - out = kvzalloc(inlen, GFP_KERNEL); - if (!out) - return -ENOMEM; - - err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); + err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); if (err) goto out; - - sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); - *sq_state = MLX5_GET(sqc, sqc, state); sq->state = *sq_state; out: - kvfree(out); return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/transobj.c b/drivers/net/ethernet/mellanox/mlx5/core/transobj.c index 9e38343a951f..c64957b5ef47 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/transobj.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/transobj.c @@ -157,6 +157,31 @@ int mlx5_core_query_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *out) } EXPORT_SYMBOL(mlx5_core_query_sq); +int mlx5_core_query_sq_state(struct mlx5_core_dev *dev, u32 sqn, u8 *state) +{ + void *out; + void *sqc; + int inlen; + int err; + + inlen = MLX5_ST_SZ_BYTES(query_sq_out); + out = kvzalloc(inlen, GFP_KERNEL); + if (!out) + return -ENOMEM; + + err = mlx5_core_query_sq(dev, sqn, out); + if (err) + goto out; + + sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); + *state = MLX5_GET(sqc, sqc, state); + +out: + kvfree(out); + return err; +} +EXPORT_SYMBOL_GPL(mlx5_core_query_sq_state); + int mlx5_core_create_tir(struct mlx5_core_dev *dev, u32 *in, int inlen, u32 *tirn) { diff --git a/include/linux/mlx5/transobj.h b/include/linux/mlx5/transobj.h index 7e8f281f8c00..80d7aa8b2831 100644 --- a/include/linux/mlx5/transobj.h +++ b/include/linux/mlx5/transobj.h @@ -47,6 +47,7 @@ int mlx5_core_create_sq(struct mlx5_core_dev *dev, u32 *in, int inlen, int mlx5_core_modify_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *in, int inlen); void mlx5_core_destroy_sq(struct mlx5_core_dev *dev, u32 sqn); int mlx5_core_query_sq(struct mlx5_core_dev *dev, u32 sqn, u32 *out); +int mlx5_core_query_sq_state(struct mlx5_core_dev *dev, u32 sqn, u8 *state); int mlx5_core_create_tir(struct mlx5_core_dev *dev, u32 *in, int inlen, u32 *tirn); int mlx5_core_modify_tir(struct mlx5_core_dev *dev, u32 tirn, u32 *in, -- cgit v1.2.3 From 1acae6b030164217b9c6a52245eade730057152b Mon Sep 17 00:00:00 2001 From: Eran Ben Elisha Date: Sun, 31 Dec 2017 12:55:26 +0200 Subject: mlx5: Move dump error CQE function out of mlx5_ib for code sharing Move mlx5_ib dump error CQE implementation to mlx5 CQ header file in order to use it in a downstream patch from mlx5e. In addition, use print_hex_dump instead of manual dumping of the buffer. Signed-off-by: Eran Ben Elisha Signed-off-by: Saeed Mahameed --- drivers/infiniband/hw/mlx5/cq.c | 8 +------- include/linux/mlx5/cq.h | 6 ++++++ 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c index 94a27d89a303..77d257ec899b 100644 --- a/drivers/infiniband/hw/mlx5/cq.c +++ b/drivers/infiniband/hw/mlx5/cq.c @@ -267,14 +267,8 @@ static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe, static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe) { - __be32 *p = (__be32 *)cqe; - int i; - mlx5_ib_warn(dev, "dump error cqe\n"); - for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4) - pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]), - be32_to_cpu(p[1]), be32_to_cpu(p[2]), - be32_to_cpu(p[3])); + mlx5_dump_err_cqe(dev->mdev, cqe); } static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev, diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h index 445ad194e0fe..0ef6138eca49 100644 --- a/include/linux/mlx5/cq.h +++ b/include/linux/mlx5/cq.h @@ -193,6 +193,12 @@ int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, u16 cq_period, u16 cq_max_count); +static inline void mlx5_dump_err_cqe(struct mlx5_core_dev *dev, + struct mlx5_err_cqe *err_cqe) +{ + print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, + sizeof(*err_cqe), false); +} int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); -- cgit v1.2.3 From 3cdb741efa02c5053a738d5816b70de11c4d6364 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 27 Mar 2018 08:53:01 -0700 Subject: regulator: qcom: smd: Add pm8998 and pmi8998 regulators Add the pm8998 and pmi8998 regulators as used in the MSM8998 platform. Signed-off-by: Bjorn Andersson Signed-off-by: Mark Brown --- .../bindings/regulator/qcom,smd-rpm-regulator.txt | 48 ++++++++ drivers/regulator/qcom_smd-regulator.c | 121 +++++++++++++++++++++ include/linux/soc/qcom/smd-rpm.h | 1 + 3 files changed, 170 insertions(+) (limited to 'include/linux') diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt index 4e3dfb5b5f16..58a1d97972f5 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt @@ -23,7 +23,9 @@ Regulator nodes are identified by their compatible: "qcom,rpm-pm8916-regulators" "qcom,rpm-pm8941-regulators" "qcom,rpm-pm8994-regulators" + "qcom,rpm-pm8998-regulators" "qcom,rpm-pma8084-regulators" + "qcom,rpm-pmi8998-regulators" - vdd_s1-supply: - vdd_s2-supply: @@ -119,6 +121,38 @@ Regulator nodes are identified by their compatible: Definition: reference to regulator supplying the input pin, as described in the data sheet +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_s5-supply: +- vdd_s6-supply: +- vdd_s7-supply: +- vdd_s8-supply: +- vdd_s9-supply: +- vdd_s10-supply: +- vdd_s11-supply: +- vdd_s12-supply: +- vdd_s13-supply: +- vdd_l1_l27-supply: +- vdd_l20_l24-supply: +- vdd_l26-supply: +- vdd_l2_l8_l17-supply: +- vdd_l3_l11-supply: +- vdd_l4_l5-supply: +- vdd_l6-supply: +- vdd_l7_l12_l14_l15-supply: +- vdd_l9-supply: +- vdd_l10_l23_l25-supply: +- vdd_l13_l19_l21-supply: +- vdd_l16_l28-supply: +- vdd_l18_l22-supply: +- vdd_lvs1_lvs2-supply: + Usage: optional (pmi8998 only) + Value type: + Definition: reference to regulator supplying the input pin, as + described in the data sheet + - vdd_s1-supply: - vdd_s2-supply: - vdd_s3-supply: @@ -148,6 +182,12 @@ Regulator nodes are identified by their compatible: Definition: reference to regulator supplying the input pin, as described in the data sheet +- vdd_bob-supply: + Usage: optional (pmi8998 only) + Value type: + Definition: reference to regulator supplying the input pin, as + described in the data sheet + The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each of the pmics below. @@ -169,11 +209,19 @@ pm8994: l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2 +pm8998: + s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2, l3, l4, + l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, + l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2 + pma8084: s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1 +pmi8998: + bob + The content of each sub-node is defined by the standard binding for regulators - see regulator.txt. diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index 940fe1b78411..ef51db5f0d9b 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -165,6 +165,15 @@ static const struct regulator_ops rpm_switch_ops = { .is_enabled = rpm_reg_is_enabled, }; +static const struct regulator_ops rpm_bob_ops = { + .enable = rpm_reg_enable, + .disable = rpm_reg_disable, + .is_enabled = rpm_reg_is_enabled, + + .get_voltage = rpm_reg_get_voltage, + .set_voltage = rpm_reg_set_voltage, +}; + static const struct regulator_desc pma8084_hfsmps = { .linear_ranges = (struct regulator_linear_range[]) { REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), @@ -355,6 +364,64 @@ static const struct regulator_desc pm8994_lnldo = { .ops = &rpm_smps_ldo_ops_fixed, }; +static const struct regulator_desc pm8998_ftsmps = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000), + }, + .n_linear_ranges = 1, + .n_voltages = 259, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_hfsmps = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 216, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_nldo = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_pldo = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_pldo_lv = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_switch = { + .ops = &rpm_switch_ops, +}; + +static const struct regulator_desc pmi8998_bob = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000), + }, + .n_linear_ranges = 1, + .n_voltages = 84, + .ops = &rpm_bob_ops, +}; + struct rpm_regulator_data { const char *name; u32 type; @@ -544,12 +611,66 @@ static const struct rpm_regulator_data rpm_pm8994_regulators[] = { {} }; +static const struct rpm_regulator_data rpm_pm8998_regulators[] = { + { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" }, + { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" }, + { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" }, + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" }, + { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" }, + { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" }, + { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" }, + { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" }, + { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" }, + { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" }, + { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" }, + { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" }, + { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" }, + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" }, + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" }, + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" }, + { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" }, + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" }, + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" }, + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" }, + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" }, + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" }, + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" }, + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" }, + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" }, + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" }, + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" }, + { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" }, + { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" }, + { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" }, + { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" }, + { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" }, + { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" }, + { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" }, + { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" }, + { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" }, + { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" }, + { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" }, + { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" }, + {} +}; + +static const struct rpm_regulator_data rpm_pmi8998_regulators[] = { + { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" }, + {} +}; + static const struct of_device_id rpm_of_match[] = { { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, + { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators }, { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, + { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators }, {} }; MODULE_DEVICE_TABLE(of, rpm_of_match); diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 9f5c6e53f3a5..9e4fdd861a51 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -10,6 +10,7 @@ struct qcom_smd_rpm; /* * Constants used for addressing resources in the RPM. */ +#define QCOM_SMD_RPM_BOBB 0x62626f62 #define QCOM_SMD_RPM_BOOST 0x61747362 #define QCOM_SMD_RPM_BUS_CLK 0x316b6c63 #define QCOM_SMD_RPM_BUS_MASTER 0x73616d62 -- cgit v1.2.3 From f23f5bece686a76598335141a091934f7eb0998c Mon Sep 17 00:00:00 2001 From: Keith Busch Date: Tue, 27 Mar 2018 09:39:06 -0600 Subject: blk-mq: Allow PCI vector offset for mapping queues The PCI interrupt vectors intended to be associated with a queue may not start at 0; a driver may allocate pre_vectors for special use. This patch adds an offset parameter so blk-mq may find the intended affinity mask and updates all drivers using this API accordingly. Cc: Don Brace Cc: Cc: Signed-off-by: Keith Busch Reviewed-by: Ming Lei Signed-off-by: Jens Axboe --- block/blk-mq-pci.c | 6 ++++-- drivers/nvme/host/pci.c | 2 +- drivers/scsi/qla2xxx/qla_os.c | 2 +- drivers/scsi/smartpqi/smartpqi_init.c | 2 +- include/linux/blk-mq-pci.h | 3 ++- 5 files changed, 9 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/block/blk-mq-pci.c b/block/blk-mq-pci.c index 76944e3271bf..e233996bb76f 100644 --- a/block/blk-mq-pci.c +++ b/block/blk-mq-pci.c @@ -21,6 +21,7 @@ * blk_mq_pci_map_queues - provide a default queue mapping for PCI device * @set: tagset to provide the mapping for * @pdev: PCI device associated with @set. + * @offset: Offset to use for the pci irq vector * * This function assumes the PCI device @pdev has at least as many available * interrupt vectors as @set has queues. It will then query the vector @@ -28,13 +29,14 @@ * that maps a queue to the CPUs that have irq affinity for the corresponding * vector. */ -int blk_mq_pci_map_queues(struct blk_mq_tag_set *set, struct pci_dev *pdev) +int blk_mq_pci_map_queues(struct blk_mq_tag_set *set, struct pci_dev *pdev, + int offset) { const struct cpumask *mask; unsigned int queue, cpu; for (queue = 0; queue < set->nr_hw_queues; queue++) { - mask = pci_irq_get_affinity(pdev, queue); + mask = pci_irq_get_affinity(pdev, queue + offset); if (!mask) goto fallback; diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index cef5ce851a92..e3b9efca0571 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -414,7 +414,7 @@ static int nvme_pci_map_queues(struct blk_mq_tag_set *set) { struct nvme_dev *dev = set->driver_data; - return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); + return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 0); } /** diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 12ee6e02d146..2c705f3dd265 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -6805,7 +6805,7 @@ static int qla2xxx_map_queues(struct Scsi_Host *shost) if (USER_CTRL_IRQ(vha->hw)) rc = blk_mq_map_queues(&shost->tag_set); else - rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev); + rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0); return rc; } diff --git a/drivers/scsi/smartpqi/smartpqi_init.c b/drivers/scsi/smartpqi/smartpqi_init.c index b2880c7709e6..10c94011c8a8 100644 --- a/drivers/scsi/smartpqi/smartpqi_init.c +++ b/drivers/scsi/smartpqi/smartpqi_init.c @@ -5348,7 +5348,7 @@ static int pqi_map_queues(struct Scsi_Host *shost) { struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost); - return blk_mq_pci_map_queues(&shost->tag_set, ctrl_info->pci_dev); + return blk_mq_pci_map_queues(&shost->tag_set, ctrl_info->pci_dev, 0); } static int pqi_getpciinfo_ioctl(struct pqi_ctrl_info *ctrl_info, diff --git a/include/linux/blk-mq-pci.h b/include/linux/blk-mq-pci.h index 6338551e0fb9..9f4c17f0d2d8 100644 --- a/include/linux/blk-mq-pci.h +++ b/include/linux/blk-mq-pci.h @@ -5,6 +5,7 @@ struct blk_mq_tag_set; struct pci_dev; -int blk_mq_pci_map_queues(struct blk_mq_tag_set *set, struct pci_dev *pdev); +int blk_mq_pci_map_queues(struct blk_mq_tag_set *set, struct pci_dev *pdev, + int offset); #endif /* _LINUX_BLK_MQ_PCI_H */ -- cgit v1.2.3 From 0e11f6443f522f89509495b13ef1f3745640144d Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 21 Feb 2018 07:54:49 -0800 Subject: fs: move I_DIRTY_INODE to fs.h And use it in a few more places rather than opencoding the values. Signed-off-by: Christoph Hellwig Signed-off-by: Al Viro --- fs/ext4/inode.c | 4 ++-- fs/fs-writeback.c | 9 +++------ fs/gfs2/super.c | 2 +- include/linux/fs.h | 3 ++- 4 files changed, 8 insertions(+), 10 deletions(-) (limited to 'include/linux') diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index c94780075b04..6d2a18991fcb 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -5032,12 +5032,12 @@ static int other_inode_match(struct inode * inode, unsigned long ino, if ((inode->i_ino != ino) || (inode->i_state & (I_FREEING | I_WILL_FREE | I_NEW | - I_DIRTY_SYNC | I_DIRTY_DATASYNC)) || + I_DIRTY_INODE)) || ((inode->i_state & I_DIRTY_TIME) == 0)) return 0; spin_lock(&inode->i_lock); if (((inode->i_state & (I_FREEING | I_WILL_FREE | I_NEW | - I_DIRTY_SYNC | I_DIRTY_DATASYNC)) == 0) && + I_DIRTY_INODE)) == 0) && (inode->i_state & I_DIRTY_TIME)) { struct ext4_inode_info *ei = EXT4_I(inode); diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c index d4d04fee568a..1280f915079b 100644 --- a/fs/fs-writeback.c +++ b/fs/fs-writeback.c @@ -1343,7 +1343,7 @@ __writeback_single_inode(struct inode *inode, struct writeback_control *wbc) dirty = inode->i_state & I_DIRTY; if (inode->i_state & I_DIRTY_TIME) { - if ((dirty & (I_DIRTY_SYNC | I_DIRTY_DATASYNC)) || + if ((dirty & I_DIRTY_INODE) || wbc->sync_mode == WB_SYNC_ALL || unlikely(inode->i_state & I_DIRTY_TIME_EXPIRED) || unlikely(time_after(jiffies, @@ -2112,7 +2112,6 @@ static noinline void block_dump___mark_inode_dirty(struct inode *inode) */ void __mark_inode_dirty(struct inode *inode, int flags) { -#define I_DIRTY_INODE (I_DIRTY_SYNC | I_DIRTY_DATASYNC) struct super_block *sb = inode->i_sb; int dirtytime; @@ -2122,7 +2121,7 @@ void __mark_inode_dirty(struct inode *inode, int flags) * Don't do this for I_DIRTY_PAGES - that doesn't actually * dirty the inode itself */ - if (flags & (I_DIRTY_SYNC | I_DIRTY_DATASYNC | I_DIRTY_TIME)) { + if (flags & (I_DIRTY_INODE | I_DIRTY_TIME)) { trace_writeback_dirty_inode_start(inode, flags); if (sb->s_op->dirty_inode) @@ -2197,7 +2196,7 @@ void __mark_inode_dirty(struct inode *inode, int flags) if (dirtytime) inode->dirtied_time_when = jiffies; - if (inode->i_state & (I_DIRTY_INODE | I_DIRTY_PAGES)) + if (inode->i_state & I_DIRTY) dirty_list = &wb->b_dirty; else dirty_list = &wb->b_dirty_time; @@ -2221,8 +2220,6 @@ void __mark_inode_dirty(struct inode *inode, int flags) } out_unlock_inode: spin_unlock(&inode->i_lock); - -#undef I_DIRTY_INODE } EXPORT_SYMBOL(__mark_inode_dirty); diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c index 620be0521866..cf5c7f3080d2 100644 --- a/fs/gfs2/super.c +++ b/fs/gfs2/super.c @@ -800,7 +800,7 @@ static void gfs2_dirty_inode(struct inode *inode, int flags) int need_endtrans = 0; int ret; - if (!(flags & (I_DIRTY_DATASYNC|I_DIRTY_SYNC))) + if (!(flags & I_DIRTY_INODE)) return; if (unlikely(test_bit(SDF_SHUTDOWN, &sdp->sd_flags))) return; diff --git a/include/linux/fs.h b/include/linux/fs.h index d7b2caadb292..00da24bc0350 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2014,7 +2014,8 @@ static inline void init_sync_kiocb(struct kiocb *kiocb, struct file *filp) #define I_WB_SWITCH (1 << 13) #define I_OVL_INUSE (1 << 14) -#define I_DIRTY (I_DIRTY_SYNC | I_DIRTY_DATASYNC | I_DIRTY_PAGES) +#define I_DIRTY_INODE (I_DIRTY_SYNC | I_DIRTY_DATASYNC) +#define I_DIRTY (I_DIRTY_INODE | I_DIRTY_PAGES) #define I_DIRTY_ALL (I_DIRTY | I_DIRTY_TIME) extern void __mark_inode_dirty(struct inode *, int); -- cgit v1.2.3 From e89f5b37015309a8bdf0b21d08007580b92f92a4 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 28 Mar 2018 15:35:35 +0200 Subject: dma-mapping: Don't clear GFP_ZERO in dma_alloc_attrs Revert the clearing of __GFP_ZERO in dma_alloc_attrs and move it to dma_direct_alloc for now. While most common architectures always zero dma cohereny allocations (and x86 did so since day one) this is not documented and at least arc and s390 do not zero without the explicit __GFP_ZERO argument. Fixes: 57bf5a8963f8 ("dma-mapping: clear harmful GFP_* flags in common code") Reported-by: Evgeniy Didin Reported-by: Sebastian Ott Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Gleixner Tested-by: Evgeniy Didin Cc: iommu@lists.linux-foundation.org Link: https://lkml.kernel.org/r/20180328133535.17302-2-hch@lst.de --- include/linux/dma-mapping.h | 8 ++------ lib/dma-direct.c | 3 +++ 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index eb9eab4ecd6d..12fedcba9a9a 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -518,12 +518,8 @@ static inline void *dma_alloc_attrs(struct device *dev, size_t size, if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) return cpu_addr; - /* - * Let the implementation decide on the zone to allocate from, and - * decide on the way of zeroing the memory given that the memory - * returned should always be zeroed. - */ - flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM | __GFP_ZERO); + /* let the implementation decide on the zone to allocate from: */ + flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); if (!arch_dma_alloc_attrs(&dev, &flag)) return NULL; diff --git a/lib/dma-direct.c b/lib/dma-direct.c index 1277d293d4da..c0bba30fef0a 100644 --- a/lib/dma-direct.c +++ b/lib/dma-direct.c @@ -59,6 +59,9 @@ void *dma_direct_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, struct page *page = NULL; void *ret; + /* we always manually zero the memory once we are done: */ + gfp &= ~__GFP_ZERO; + /* GFP_DMA32 and GFP_DMA are no ops without the corresponding zones: */ if (dev->coherent_dma_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS)) gfp |= GFP_DMA; -- cgit v1.2.3 From 9ea393d8d8377b6da8ee25c6a114ec24c0687c7c Mon Sep 17 00:00:00 2001 From: Alexander Shishkin Date: Wed, 28 Mar 2018 18:43:57 +0300 Subject: stm class: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate This adds SPDX GPL-2.0 header to to stm core files and removes the GPLv2 boilerplate text. Signed-off-by: Alexander Shishkin --- drivers/hwtracing/stm/console.c | 10 +--------- drivers/hwtracing/stm/core.c | 10 +--------- drivers/hwtracing/stm/dummy_stm.c | 10 +--------- drivers/hwtracing/stm/heartbeat.c | 10 +--------- drivers/hwtracing/stm/policy.c | 10 +--------- drivers/hwtracing/stm/stm.h | 10 +--------- include/linux/stm.h | 10 +--------- include/uapi/linux/stm.h | 9 --------- 8 files changed, 7 insertions(+), 72 deletions(-) (limited to 'include/linux') diff --git a/drivers/hwtracing/stm/console.c b/drivers/hwtracing/stm/console.c index c9d9a8d2ff52..a00f65e21747 100644 --- a/drivers/hwtracing/stm/console.c +++ b/drivers/hwtracing/stm/console.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Simple kernel console driver for STM devices * Copyright (c) 2014, Intel Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * * STM console will send kernel messages over STM devices to a trace host. */ diff --git a/drivers/hwtracing/stm/core.c b/drivers/hwtracing/stm/core.c index f129869e05a9..05386b76465e 100644 --- a/drivers/hwtracing/stm/core.c +++ b/drivers/hwtracing/stm/core.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * System Trace Module (STM) infrastructure * Copyright (c) 2014, Intel Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * * STM class implements generic infrastructure for System Trace Module devices * as defined in MIPI STPv2 specification. */ diff --git a/drivers/hwtracing/stm/dummy_stm.c b/drivers/hwtracing/stm/dummy_stm.c index c5f94ca31c4d..63288020ea5b 100644 --- a/drivers/hwtracing/stm/dummy_stm.c +++ b/drivers/hwtracing/stm/dummy_stm.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * A dummy STM device for stm/stm_source class testing. * Copyright (c) 2014, Intel Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * * STM class implements generic infrastructure for System Trace Module devices * as defined in MIPI STPv2 specification. */ diff --git a/drivers/hwtracing/stm/heartbeat.c b/drivers/hwtracing/stm/heartbeat.c index 3da7b673aab2..7db42395e131 100644 --- a/drivers/hwtracing/stm/heartbeat.c +++ b/drivers/hwtracing/stm/heartbeat.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Simple heartbeat STM source driver * Copyright (c) 2016, Intel Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * * Heartbeat STM source will send repetitive messages over STM devices to a * trace host. */ diff --git a/drivers/hwtracing/stm/policy.c b/drivers/hwtracing/stm/policy.c index 33e9a1b6ea7c..3fd07e275b34 100644 --- a/drivers/hwtracing/stm/policy.c +++ b/drivers/hwtracing/stm/policy.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * System Trace Module (STM) master/channel allocation policy management * Copyright (c) 2014, Intel Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * * A master/channel allocation policy allows mapping string identifiers to * master and channel ranges, where allocation can be done. */ diff --git a/drivers/hwtracing/stm/stm.h b/drivers/hwtracing/stm/stm.h index 4e8c6926260f..923571adc6f4 100644 --- a/drivers/hwtracing/stm/stm.h +++ b/drivers/hwtracing/stm/stm.h @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * System Trace Module (STM) infrastructure * Copyright (c) 2014, Intel Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * * STM class implements generic infrastructure for System Trace Module devices * as defined in MIPI STPv2 specification. */ diff --git a/include/linux/stm.h b/include/linux/stm.h index 210ff2292361..c6f577ab6f21 100644 --- a/include/linux/stm.h +++ b/include/linux/stm.h @@ -1,15 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * System Trace Module (STM) infrastructure apis * Copyright (C) 2014 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. */ #ifndef _STM_H_ diff --git a/include/uapi/linux/stm.h b/include/uapi/linux/stm.h index dbffdc23d804..29c89be72275 100644 --- a/include/uapi/linux/stm.h +++ b/include/uapi/linux/stm.h @@ -3,15 +3,6 @@ * System Trace Module (STM) userspace interfaces * Copyright (c) 2014, Intel Corporation. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * * STM class implements generic infrastructure for System Trace Module devices * as defined in MIPI STPv2 specification. */ -- cgit v1.2.3 From 8ecd2953d0a1b78748b36f5bed6f233f5bd6d6ea Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Wed, 28 Mar 2018 18:41:25 +1100 Subject: ipc/shm: fix up for struct file no longer being available in shm.h Stephen Rothewell wrote: > After merging the userns tree, today's linux-next build (powerpc > ppc64_defconfig) produced this warning: > > In file included from include/linux/sched.h:16:0, > from arch/powerpc/lib/xor_vmx_glue.c:14: > include/linux/shm.h:17:35: error: 'struct file' declared inside parameter list will not be visible outside of this definition or declaration [-Werror] > bool is_file_shm_hugepages(struct file *file); > ^~~~ > > and many, many more (most warnings, but some errors - arch/powerpc is > mostly built with -Werror) I dug through this and I discovered that the error was caused by the removal of struct shmid_kernel from shm.h when building on powerpc. Except for observing the existence of "struct file *shm_file" in struct shmid_kernel I have no clue why the structure move would cause such a failure. I suspect shm.h always needed the forward declaration and someting had been confusing gcc into not issuing the warning. --EWB Fixes: a2e102cd3cdd ("shm: Move struct shmid_kernel into ipc/shm.c") Signed-off-by: Stephen Rothwell Signed-off-by: Eric W. Biederman --- include/linux/shm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux') diff --git a/include/linux/shm.h b/include/linux/shm.h index 3a8eae3ca33c..d8e69aed3d32 100644 --- a/include/linux/shm.h +++ b/include/linux/shm.h @@ -7,6 +7,8 @@ #include #include +struct file; + #ifdef CONFIG_SYSVIPC struct sysv_shm { struct list_head shm_clist; -- cgit v1.2.3 From 5a485803221777013944cbd1a7cd5c62efba3ffa Mon Sep 17 00:00:00 2001 From: Vitaly Kuznetsov Date: Tue, 20 Mar 2018 15:02:05 +0100 Subject: x86/hyper-v: move hyperv.h out of uapi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit hyperv.h is not part of uapi, there are no (known) users outside of kernel. We are making changes to this file to match current Hyper-V Hypervisor Top-Level Functional Specification (TLFS, see: https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs) and we don't want to maintain backwards compatibility. Move the file renaming to hyperv-tlfs.h to avoid confusing it with mshyperv.h. In future, all definitions from TLFS should go to it and all kernel objects should go to mshyperv.h or include/linux/hyperv.h. Signed-off-by: Vitaly Kuznetsov Acked-by: Thomas Gleixner Signed-off-by: Radim Krčmář --- MAINTAINERS | 2 +- arch/x86/hyperv/hv_init.c | 2 +- arch/x86/include/asm/hyperv-tlfs.h | 432 +++++++++++++++++++++++++++++++++++ arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/mshyperv.h | 2 +- arch/x86/include/uapi/asm/hyperv.h | 425 ---------------------------------- arch/x86/include/uapi/asm/kvm_para.h | 1 - arch/x86/kernel/cpu/mshyperv.c | 2 +- drivers/hv/connection.c | 1 - drivers/hv/hv.c | 1 - drivers/hv/hyperv_vmbus.h | 1 + drivers/hv/vmbus_drv.c | 1 - include/linux/hyperv.h | 1 - 13 files changed, 438 insertions(+), 434 deletions(-) create mode 100644 arch/x86/include/asm/hyperv-tlfs.h delete mode 100644 arch/x86/include/uapi/asm/hyperv.h (limited to 'include/linux') diff --git a/MAINTAINERS b/MAINTAINERS index 4623caf8d72d..80befd9f4775 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6531,7 +6531,7 @@ S: Maintained F: Documentation/networking/netvsc.txt F: arch/x86/include/asm/mshyperv.h F: arch/x86/include/asm/trace/hyperv.h -F: arch/x86/include/uapi/asm/hyperv.h +F: arch/x86/include/asm/hyperv-tlfs.h F: arch/x86/kernel/cpu/mshyperv.c F: arch/x86/hyperv F: drivers/hid/hid-hyperv.c diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c index 2edc49e7409b..4b82bc206929 100644 --- a/arch/x86/hyperv/hv_init.c +++ b/arch/x86/hyperv/hv_init.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h new file mode 100644 index 000000000000..77d6e8b10ea9 --- /dev/null +++ b/arch/x86/include/asm/hyperv-tlfs.h @@ -0,0 +1,432 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +/* + * This file contains definitions from Hyper-V Hypervisor Top-Level Functional + * Specification (TLFS): + * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs + */ + +#ifndef _ASM_X86_HYPERV_TLFS_H +#define _ASM_X86_HYPERV_TLFS_H + +#include + +/* + * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent + * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). + */ +#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 +#define HYPERV_CPUID_INTERFACE 0x40000001 +#define HYPERV_CPUID_VERSION 0x40000002 +#define HYPERV_CPUID_FEATURES 0x40000003 +#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 +#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 + +#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 +#define HYPERV_CPUID_MIN 0x40000005 +#define HYPERV_CPUID_MAX 0x4000ffff + +/* + * Feature identification. EAX indicates which features are available + * to the partition based upon the current partition privileges. + */ + +/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ +#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) +/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ +#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) +/* Partition reference TSC MSR is available */ +#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) + +/* A partition's reference time stamp counter (TSC) page */ +#define HV_X64_MSR_REFERENCE_TSC 0x40000021 + +/* + * There is a single feature flag that signifies if the partition has access + * to MSRs with local APIC and TSC frequencies. + */ +#define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11) + +/* AccessReenlightenmentControls privilege */ +#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) + +/* + * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM + * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available + */ +#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) +/* + * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through + * HV_X64_MSR_STIMER3_COUNT) available + */ +#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) +/* + * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) + * are available + */ +#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) +/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ +#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) +/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ +#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) +/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ +#define HV_X64_MSR_RESET_AVAILABLE (1 << 7) + /* + * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, + * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, + * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available + */ +#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) + +/* Frequency MSRs available */ +#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8) + +/* Crash MSR available */ +#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10) + +/* + * Feature identification: EBX indicates which flags were specified at + * partition creation. The format is the same as the partition creation + * flag structure defined in section Partition Creation Flags. + */ +#define HV_X64_CREATE_PARTITIONS (1 << 0) +#define HV_X64_ACCESS_PARTITION_ID (1 << 1) +#define HV_X64_ACCESS_MEMORY_POOL (1 << 2) +#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) +#define HV_X64_POST_MESSAGES (1 << 4) +#define HV_X64_SIGNAL_EVENTS (1 << 5) +#define HV_X64_CREATE_PORT (1 << 6) +#define HV_X64_CONNECT_PORT (1 << 7) +#define HV_X64_ACCESS_STATS (1 << 8) +#define HV_X64_DEBUGGING (1 << 11) +#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) +#define HV_X64_CONFIGURE_PROFILER (1 << 13) + +/* + * Feature identification. EDX indicates which miscellaneous features + * are available to the partition. + */ +/* The MWAIT instruction is available (per section MONITOR / MWAIT) */ +#define HV_X64_MWAIT_AVAILABLE (1 << 0) +/* Guest debugging support is available */ +#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) +/* Performance Monitor support is available*/ +#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) +/* Support for physical CPU dynamic partitioning events is available*/ +#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) +/* + * Support for passing hypercall input parameter block via XMM + * registers is available + */ +#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) +/* Support for a virtual guest idle state is available */ +#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) +/* Guest crash data handler available */ +#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) + +/* + * Implementation recommendations. Indicates which behaviors the hypervisor + * recommends the OS implement for optimal performance. + */ + /* + * Recommend using hypercall for address space switches rather + * than MOV to CR3 instruction + */ +#define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0) +/* Recommend using hypercall for local TLB flushes rather + * than INVLPG or MOV to CR3 instructions */ +#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) +/* + * Recommend using hypercall for remote TLB flushes rather + * than inter-processor interrupts + */ +#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) +/* + * Recommend using MSRs for accessing APIC registers + * EOI, ICR and TPR rather than their memory-mapped counterparts + */ +#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) +/* Recommend using the hypervisor-provided MSR to initiate a system RESET */ +#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) +/* + * Recommend using relaxed timing for this partition. If used, + * the VM should disable any watchdog timeouts that rely on the + * timely delivery of external interrupts + */ +#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) + +/* + * Virtual APIC support + */ +#define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9) + +/* Recommend using the newer ExProcessorMasks interface */ +#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11) + +/* + * Crash notification flag. + */ +#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63) + +/* MSR used to identify the guest OS. */ +#define HV_X64_MSR_GUEST_OS_ID 0x40000000 + +/* MSR used to setup pages used to communicate with the hypervisor. */ +#define HV_X64_MSR_HYPERCALL 0x40000001 + +/* MSR used to provide vcpu index */ +#define HV_X64_MSR_VP_INDEX 0x40000002 + +/* MSR used to reset the guest OS. */ +#define HV_X64_MSR_RESET 0x40000003 + +/* MSR used to provide vcpu runtime in 100ns units */ +#define HV_X64_MSR_VP_RUNTIME 0x40000010 + +/* MSR used to read the per-partition time reference counter */ +#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 + +/* MSR used to retrieve the TSC frequency */ +#define HV_X64_MSR_TSC_FREQUENCY 0x40000022 + +/* MSR used to retrieve the local APIC timer frequency */ +#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 + +/* Define the virtual APIC registers */ +#define HV_X64_MSR_EOI 0x40000070 +#define HV_X64_MSR_ICR 0x40000071 +#define HV_X64_MSR_TPR 0x40000072 +#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 + +/* Define synthetic interrupt controller model specific registers. */ +#define HV_X64_MSR_SCONTROL 0x40000080 +#define HV_X64_MSR_SVERSION 0x40000081 +#define HV_X64_MSR_SIEFP 0x40000082 +#define HV_X64_MSR_SIMP 0x40000083 +#define HV_X64_MSR_EOM 0x40000084 +#define HV_X64_MSR_SINT0 0x40000090 +#define HV_X64_MSR_SINT1 0x40000091 +#define HV_X64_MSR_SINT2 0x40000092 +#define HV_X64_MSR_SINT3 0x40000093 +#define HV_X64_MSR_SINT4 0x40000094 +#define HV_X64_MSR_SINT5 0x40000095 +#define HV_X64_MSR_SINT6 0x40000096 +#define HV_X64_MSR_SINT7 0x40000097 +#define HV_X64_MSR_SINT8 0x40000098 +#define HV_X64_MSR_SINT9 0x40000099 +#define HV_X64_MSR_SINT10 0x4000009A +#define HV_X64_MSR_SINT11 0x4000009B +#define HV_X64_MSR_SINT12 0x4000009C +#define HV_X64_MSR_SINT13 0x4000009D +#define HV_X64_MSR_SINT14 0x4000009E +#define HV_X64_MSR_SINT15 0x4000009F + +/* + * Synthetic Timer MSRs. Four timers per vcpu. + */ +#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 +#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 +#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 +#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 +#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 +#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 +#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 +#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 + +/* Hyper-V guest crash notification MSR's */ +#define HV_X64_MSR_CRASH_P0 0x40000100 +#define HV_X64_MSR_CRASH_P1 0x40000101 +#define HV_X64_MSR_CRASH_P2 0x40000102 +#define HV_X64_MSR_CRASH_P3 0x40000103 +#define HV_X64_MSR_CRASH_P4 0x40000104 +#define HV_X64_MSR_CRASH_CTL 0x40000105 +#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) +#define HV_X64_MSR_CRASH_PARAMS \ + (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) + +/* TSC emulation after migration */ +#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 + +struct hv_reenlightenment_control { + __u64 vector:8; + __u64 reserved1:8; + __u64 enabled:1; + __u64 reserved2:15; + __u64 target_vp:32; +}; + +#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 +#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 + +struct hv_tsc_emulation_control { + __u64 enabled:1; + __u64 reserved:63; +}; + +struct hv_tsc_emulation_status { + __u64 inprogress:1; + __u64 reserved:63; +}; + +#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 +#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 +#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ + (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) + +/* Declare the various hypercall operations. */ +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 +#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 +#define HVCALL_POST_MESSAGE 0x005c +#define HVCALL_SIGNAL_EVENT 0x005d + +#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001 +#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12 +#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \ + (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) + +#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 +#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 + +#define HV_PROCESSOR_POWER_STATE_C0 0 +#define HV_PROCESSOR_POWER_STATE_C1 1 +#define HV_PROCESSOR_POWER_STATE_C2 2 +#define HV_PROCESSOR_POWER_STATE_C3 3 + +#define HV_FLUSH_ALL_PROCESSORS BIT(0) +#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) +#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) +#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) + +enum HV_GENERIC_SET_FORMAT { + HV_GENERIC_SET_SPARCE_4K, + HV_GENERIC_SET_ALL, +}; + +/* hypercall status code */ +#define HV_STATUS_SUCCESS 0 +#define HV_STATUS_INVALID_HYPERCALL_CODE 2 +#define HV_STATUS_INVALID_HYPERCALL_INPUT 3 +#define HV_STATUS_INVALID_ALIGNMENT 4 +#define HV_STATUS_INVALID_PARAMETER 5 +#define HV_STATUS_INSUFFICIENT_MEMORY 11 +#define HV_STATUS_INVALID_PORT_ID 17 +#define HV_STATUS_INVALID_CONNECTION_ID 18 +#define HV_STATUS_INSUFFICIENT_BUFFERS 19 + +typedef struct _HV_REFERENCE_TSC_PAGE { + __u32 tsc_sequence; + __u32 res1; + __u64 tsc_scale; + __s64 tsc_offset; +} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; + +/* Define the number of synthetic interrupt sources. */ +#define HV_SYNIC_SINT_COUNT (16) +/* Define the expected SynIC version. */ +#define HV_SYNIC_VERSION_1 (0x1) +/* Valid SynIC vectors are 16-255. */ +#define HV_SYNIC_FIRST_VALID_VECTOR (16) + +#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) +#define HV_SYNIC_SIMP_ENABLE (1ULL << 0) +#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) +#define HV_SYNIC_SINT_MASKED (1ULL << 16) +#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) +#define HV_SYNIC_SINT_VECTOR_MASK (0xFF) + +#define HV_SYNIC_STIMER_COUNT (4) + +/* Define synthetic interrupt controller message constants. */ +#define HV_MESSAGE_SIZE (256) +#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) +#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) + +/* Define hypervisor message types. */ +enum hv_message_type { + HVMSG_NONE = 0x00000000, + + /* Memory access messages. */ + HVMSG_UNMAPPED_GPA = 0x80000000, + HVMSG_GPA_INTERCEPT = 0x80000001, + + /* Timer notification messages. */ + HVMSG_TIMER_EXPIRED = 0x80000010, + + /* Error messages. */ + HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, + HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, + HVMSG_UNSUPPORTED_FEATURE = 0x80000022, + + /* Trace buffer complete messages. */ + HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, + + /* Platform-specific processor intercept messages. */ + HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, + HVMSG_X64_MSR_INTERCEPT = 0x80010001, + HVMSG_X64_CPUID_INTERCEPT = 0x80010002, + HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, + HVMSG_X64_APIC_EOI = 0x80010004, + HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 +}; + +/* Define synthetic interrupt controller message flags. */ +union hv_message_flags { + __u8 asu8; + struct { + __u8 msg_pending:1; + __u8 reserved:7; + }; +}; + +/* Define port identifier type. */ +union hv_port_id { + __u32 asu32; + struct { + __u32 id:24; + __u32 reserved:8; + } u; +}; + +/* Define synthetic interrupt controller message header. */ +struct hv_message_header { + __u32 message_type; + __u8 payload_size; + union hv_message_flags message_flags; + __u8 reserved[2]; + union { + __u64 sender; + union hv_port_id port; + }; +}; + +/* Define synthetic interrupt controller message format. */ +struct hv_message { + struct hv_message_header header; + union { + __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; + } u; +}; + +/* Define the synthetic interrupt message page layout. */ +struct hv_message_page { + struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; +}; + +/* Define timer message payload structure. */ +struct hv_timer_message_payload { + __u32 timer_index; + __u32 reserved; + __u64 expiration_time; /* When the timer expired */ + __u64 delivery_time; /* When the message was delivered */ +}; + +#define HV_STIMER_ENABLE (1ULL << 0) +#define HV_STIMER_PERIODIC (1ULL << 1) +#define HV_STIMER_LAZY (1ULL << 2) +#define HV_STIMER_AUTOENABLE (1ULL << 3) +#define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F) + +#endif diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 38b4080b29c2..74b5b3e518df 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -34,6 +34,7 @@ #include #include #include +#include #define KVM_MAX_VCPUS 288 #define KVM_SOFT_MAX_VCPUS 240 diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h index 25283f7eb299..044323a59354 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include /* diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h deleted file mode 100644 index 6285cf817347..000000000000 --- a/arch/x86/include/uapi/asm/hyperv.h +++ /dev/null @@ -1,425 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_X86_HYPERV_H -#define _ASM_X86_HYPERV_H - -#include - -/* - * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent - * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). - */ -#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 -#define HYPERV_CPUID_INTERFACE 0x40000001 -#define HYPERV_CPUID_VERSION 0x40000002 -#define HYPERV_CPUID_FEATURES 0x40000003 -#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 -#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 - -#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 -#define HYPERV_CPUID_MIN 0x40000005 -#define HYPERV_CPUID_MAX 0x4000ffff - -/* - * Feature identification. EAX indicates which features are available - * to the partition based upon the current partition privileges. - */ - -/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ -#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) -/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ -#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) -/* Partition reference TSC MSR is available */ -#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) - -/* A partition's reference time stamp counter (TSC) page */ -#define HV_X64_MSR_REFERENCE_TSC 0x40000021 - -/* - * There is a single feature flag that signifies if the partition has access - * to MSRs with local APIC and TSC frequencies. - */ -#define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11) - -/* AccessReenlightenmentControls privilege */ -#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) - -/* - * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM - * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available - */ -#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) -/* - * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through - * HV_X64_MSR_STIMER3_COUNT) available - */ -#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) -/* - * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) - * are available - */ -#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) -/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ -#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) -/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ -#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) -/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ -#define HV_X64_MSR_RESET_AVAILABLE (1 << 7) - /* - * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, - * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, - * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available - */ -#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) - -/* Frequency MSRs available */ -#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8) - -/* Crash MSR available */ -#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10) - -/* - * Feature identification: EBX indicates which flags were specified at - * partition creation. The format is the same as the partition creation - * flag structure defined in section Partition Creation Flags. - */ -#define HV_X64_CREATE_PARTITIONS (1 << 0) -#define HV_X64_ACCESS_PARTITION_ID (1 << 1) -#define HV_X64_ACCESS_MEMORY_POOL (1 << 2) -#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) -#define HV_X64_POST_MESSAGES (1 << 4) -#define HV_X64_SIGNAL_EVENTS (1 << 5) -#define HV_X64_CREATE_PORT (1 << 6) -#define HV_X64_CONNECT_PORT (1 << 7) -#define HV_X64_ACCESS_STATS (1 << 8) -#define HV_X64_DEBUGGING (1 << 11) -#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) -#define HV_X64_CONFIGURE_PROFILER (1 << 13) - -/* - * Feature identification. EDX indicates which miscellaneous features - * are available to the partition. - */ -/* The MWAIT instruction is available (per section MONITOR / MWAIT) */ -#define HV_X64_MWAIT_AVAILABLE (1 << 0) -/* Guest debugging support is available */ -#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) -/* Performance Monitor support is available*/ -#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) -/* Support for physical CPU dynamic partitioning events is available*/ -#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) -/* - * Support for passing hypercall input parameter block via XMM - * registers is available - */ -#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) -/* Support for a virtual guest idle state is available */ -#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) -/* Guest crash data handler available */ -#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) - -/* - * Implementation recommendations. Indicates which behaviors the hypervisor - * recommends the OS implement for optimal performance. - */ - /* - * Recommend using hypercall for address space switches rather - * than MOV to CR3 instruction - */ -#define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0) -/* Recommend using hypercall for local TLB flushes rather - * than INVLPG or MOV to CR3 instructions */ -#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) -/* - * Recommend using hypercall for remote TLB flushes rather - * than inter-processor interrupts - */ -#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) -/* - * Recommend using MSRs for accessing APIC registers - * EOI, ICR and TPR rather than their memory-mapped counterparts - */ -#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) -/* Recommend using the hypervisor-provided MSR to initiate a system RESET */ -#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) -/* - * Recommend using relaxed timing for this partition. If used, - * the VM should disable any watchdog timeouts that rely on the - * timely delivery of external interrupts - */ -#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) - -/* - * Virtual APIC support - */ -#define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9) - -/* Recommend using the newer ExProcessorMasks interface */ -#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11) - -/* - * Crash notification flag. - */ -#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63) - -/* MSR used to identify the guest OS. */ -#define HV_X64_MSR_GUEST_OS_ID 0x40000000 - -/* MSR used to setup pages used to communicate with the hypervisor. */ -#define HV_X64_MSR_HYPERCALL 0x40000001 - -/* MSR used to provide vcpu index */ -#define HV_X64_MSR_VP_INDEX 0x40000002 - -/* MSR used to reset the guest OS. */ -#define HV_X64_MSR_RESET 0x40000003 - -/* MSR used to provide vcpu runtime in 100ns units */ -#define HV_X64_MSR_VP_RUNTIME 0x40000010 - -/* MSR used to read the per-partition time reference counter */ -#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 - -/* MSR used to retrieve the TSC frequency */ -#define HV_X64_MSR_TSC_FREQUENCY 0x40000022 - -/* MSR used to retrieve the local APIC timer frequency */ -#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 - -/* Define the virtual APIC registers */ -#define HV_X64_MSR_EOI 0x40000070 -#define HV_X64_MSR_ICR 0x40000071 -#define HV_X64_MSR_TPR 0x40000072 -#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 - -/* Define synthetic interrupt controller model specific registers. */ -#define HV_X64_MSR_SCONTROL 0x40000080 -#define HV_X64_MSR_SVERSION 0x40000081 -#define HV_X64_MSR_SIEFP 0x40000082 -#define HV_X64_MSR_SIMP 0x40000083 -#define HV_X64_MSR_EOM 0x40000084 -#define HV_X64_MSR_SINT0 0x40000090 -#define HV_X64_MSR_SINT1 0x40000091 -#define HV_X64_MSR_SINT2 0x40000092 -#define HV_X64_MSR_SINT3 0x40000093 -#define HV_X64_MSR_SINT4 0x40000094 -#define HV_X64_MSR_SINT5 0x40000095 -#define HV_X64_MSR_SINT6 0x40000096 -#define HV_X64_MSR_SINT7 0x40000097 -#define HV_X64_MSR_SINT8 0x40000098 -#define HV_X64_MSR_SINT9 0x40000099 -#define HV_X64_MSR_SINT10 0x4000009A -#define HV_X64_MSR_SINT11 0x4000009B -#define HV_X64_MSR_SINT12 0x4000009C -#define HV_X64_MSR_SINT13 0x4000009D -#define HV_X64_MSR_SINT14 0x4000009E -#define HV_X64_MSR_SINT15 0x4000009F - -/* - * Synthetic Timer MSRs. Four timers per vcpu. - */ -#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 -#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 -#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 -#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 -#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 -#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 -#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 -#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 - -/* Hyper-V guest crash notification MSR's */ -#define HV_X64_MSR_CRASH_P0 0x40000100 -#define HV_X64_MSR_CRASH_P1 0x40000101 -#define HV_X64_MSR_CRASH_P2 0x40000102 -#define HV_X64_MSR_CRASH_P3 0x40000103 -#define HV_X64_MSR_CRASH_P4 0x40000104 -#define HV_X64_MSR_CRASH_CTL 0x40000105 -#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) -#define HV_X64_MSR_CRASH_PARAMS \ - (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) - -/* TSC emulation after migration */ -#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 - -struct hv_reenlightenment_control { - __u64 vector:8; - __u64 reserved1:8; - __u64 enabled:1; - __u64 reserved2:15; - __u64 target_vp:32; -}; - -#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 -#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 - -struct hv_tsc_emulation_control { - __u64 enabled:1; - __u64 reserved:63; -}; - -struct hv_tsc_emulation_status { - __u64 inprogress:1; - __u64 reserved:63; -}; - -#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 -#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 -#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ - (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) - -/* Declare the various hypercall operations. */ -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 -#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 -#define HVCALL_POST_MESSAGE 0x005c -#define HVCALL_SIGNAL_EVENT 0x005d - -#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001 -#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12 -#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \ - (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) - -#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 -#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 - -#define HV_PROCESSOR_POWER_STATE_C0 0 -#define HV_PROCESSOR_POWER_STATE_C1 1 -#define HV_PROCESSOR_POWER_STATE_C2 2 -#define HV_PROCESSOR_POWER_STATE_C3 3 - -#define HV_FLUSH_ALL_PROCESSORS BIT(0) -#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) -#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) -#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) - -enum HV_GENERIC_SET_FORMAT { - HV_GENERIC_SET_SPARCE_4K, - HV_GENERIC_SET_ALL, -}; - -/* hypercall status code */ -#define HV_STATUS_SUCCESS 0 -#define HV_STATUS_INVALID_HYPERCALL_CODE 2 -#define HV_STATUS_INVALID_HYPERCALL_INPUT 3 -#define HV_STATUS_INVALID_ALIGNMENT 4 -#define HV_STATUS_INVALID_PARAMETER 5 -#define HV_STATUS_INSUFFICIENT_MEMORY 11 -#define HV_STATUS_INVALID_PORT_ID 17 -#define HV_STATUS_INVALID_CONNECTION_ID 18 -#define HV_STATUS_INSUFFICIENT_BUFFERS 19 - -typedef struct _HV_REFERENCE_TSC_PAGE { - __u32 tsc_sequence; - __u32 res1; - __u64 tsc_scale; - __s64 tsc_offset; -} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; - -/* Define the number of synthetic interrupt sources. */ -#define HV_SYNIC_SINT_COUNT (16) -/* Define the expected SynIC version. */ -#define HV_SYNIC_VERSION_1 (0x1) -/* Valid SynIC vectors are 16-255. */ -#define HV_SYNIC_FIRST_VALID_VECTOR (16) - -#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) -#define HV_SYNIC_SIMP_ENABLE (1ULL << 0) -#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) -#define HV_SYNIC_SINT_MASKED (1ULL << 16) -#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) -#define HV_SYNIC_SINT_VECTOR_MASK (0xFF) - -#define HV_SYNIC_STIMER_COUNT (4) - -/* Define synthetic interrupt controller message constants. */ -#define HV_MESSAGE_SIZE (256) -#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) -#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) - -/* Define hypervisor message types. */ -enum hv_message_type { - HVMSG_NONE = 0x00000000, - - /* Memory access messages. */ - HVMSG_UNMAPPED_GPA = 0x80000000, - HVMSG_GPA_INTERCEPT = 0x80000001, - - /* Timer notification messages. */ - HVMSG_TIMER_EXPIRED = 0x80000010, - - /* Error messages. */ - HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, - HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, - HVMSG_UNSUPPORTED_FEATURE = 0x80000022, - - /* Trace buffer complete messages. */ - HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, - - /* Platform-specific processor intercept messages. */ - HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, - HVMSG_X64_MSR_INTERCEPT = 0x80010001, - HVMSG_X64_CPUID_INTERCEPT = 0x80010002, - HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, - HVMSG_X64_APIC_EOI = 0x80010004, - HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 -}; - -/* Define synthetic interrupt controller message flags. */ -union hv_message_flags { - __u8 asu8; - struct { - __u8 msg_pending:1; - __u8 reserved:7; - }; -}; - -/* Define port identifier type. */ -union hv_port_id { - __u32 asu32; - struct { - __u32 id:24; - __u32 reserved:8; - } u; -}; - -/* Define synthetic interrupt controller message header. */ -struct hv_message_header { - __u32 message_type; - __u8 payload_size; - union hv_message_flags message_flags; - __u8 reserved[2]; - union { - __u64 sender; - union hv_port_id port; - }; -}; - -/* Define synthetic interrupt controller message format. */ -struct hv_message { - struct hv_message_header header; - union { - __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; - } u; -}; - -/* Define the synthetic interrupt message page layout. */ -struct hv_message_page { - struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; -}; - -/* Define timer message payload structure. */ -struct hv_timer_message_payload { - __u32 timer_index; - __u32 reserved; - __u64 expiration_time; /* When the timer expired */ - __u64 delivery_time; /* When the message was delivered */ -}; - -#define HV_STIMER_ENABLE (1ULL << 0) -#define HV_STIMER_PERIODIC (1ULL << 1) -#define HV_STIMER_LAZY (1ULL << 2) -#define HV_STIMER_AUTOENABLE (1ULL << 3) -#define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F) - -#endif diff --git a/arch/x86/include/uapi/asm/kvm_para.h b/arch/x86/include/uapi/asm/kvm_para.h index 68a41b6ba3da..4c851ebb3ceb 100644 --- a/arch/x86/include/uapi/asm/kvm_para.h +++ b/arch/x86/include/uapi/asm/kvm_para.h @@ -3,7 +3,6 @@ #define _UAPI_ASM_X86_KVM_PARA_H #include -#include /* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx. It * should be used to determine that a VM is running under KVM. diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 9340f41ce8d3..04f760432a17 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/hv/connection.c b/drivers/hv/connection.c index 447371f4de56..72855182b191 100644 --- a/drivers/hv/connection.c +++ b/drivers/hv/connection.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include "hyperv_vmbus.h" diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c index fe96aab9e794..45f3694bbb76 100644 --- a/drivers/hv/hv.c +++ b/drivers/hv/hv.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include "hyperv_vmbus.h" diff --git a/drivers/hv/hyperv_vmbus.h b/drivers/hv/hyperv_vmbus.h index 22300ec7b556..500f805a6ef2 100644 --- a/drivers/hv/hyperv_vmbus.h +++ b/drivers/hv/hyperv_vmbus.h @@ -27,6 +27,7 @@ #include #include +#include #include #include #include diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index bc65c4d79c1f..b10fe26c4891 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -36,7 +36,6 @@ #include #include -#include #include #include #include diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 93bd6fcd6e62..eed8b33b0173 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -26,7 +26,6 @@ #define _HYPERV_H #include -#include #include #include -- cgit v1.2.3 From cf14f27f82af78e713f8a57c477cf9233faf8b30 Mon Sep 17 00:00:00 2001 From: Alexei Starovoitov Date: Wed, 28 Mar 2018 12:05:36 -0700 Subject: macro: introduce COUNT_ARGS() macro move COUNT_ARGS() macro from apparmor to generic header and extend it to count till twelve. COUNT() was an alternative name for this logic, but it's used for different purpose in many other places. Similarly for CONCATENATE() macro. Suggested-by: Linus Torvalds Signed-off-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/kernel.h | 7 +++++++ security/apparmor/include/path.h | 7 +------ 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 3fd291503576..293fa0677fba 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -919,6 +919,13 @@ static inline void ftrace_dump(enum ftrace_dump_mode oops_dump_mode) { } #define swap(a, b) \ do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) +/* This counts to 12. Any more, it will return 13th argument. */ +#define __COUNT_ARGS(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _n, X...) _n +#define COUNT_ARGS(X...) __COUNT_ARGS(, ##X, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __CONCAT(a, b) a ## b +#define CONCATENATE(a, b) __CONCAT(a, b) + /** * container_of - cast a member of a structure out to the containing structure * @ptr: the pointer to the member. diff --git a/security/apparmor/include/path.h b/security/apparmor/include/path.h index 05fb3305671e..e042b994f2b8 100644 --- a/security/apparmor/include/path.h +++ b/security/apparmor/include/path.h @@ -43,15 +43,10 @@ struct aa_buffers { DECLARE_PER_CPU(struct aa_buffers, aa_buffers); -#define COUNT_ARGS(X...) COUNT_ARGS_HELPER(, ##X, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) -#define COUNT_ARGS_HELPER(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, n, X...) n -#define CONCAT(X, Y) X ## Y -#define CONCAT_AFTER(X, Y) CONCAT(X, Y) - #define ASSIGN(FN, X, N) ((X) = FN(N)) #define EVAL1(FN, X) ASSIGN(FN, X, 0) /*X = FN(0)*/ #define EVAL2(FN, X, Y...) do { ASSIGN(FN, X, 1); EVAL1(FN, Y); } while (0) -#define EVAL(FN, X...) CONCAT_AFTER(EVAL, COUNT_ARGS(X))(FN, X) +#define EVAL(FN, X...) CONCATENATE(EVAL, COUNT_ARGS(X))(FN, X) #define for_each_cpu_buffer(I) for ((I) = 0; (I) < MAX_PATH_BUFFERS; (I)++) -- cgit v1.2.3 From c4f6699dfcb8558d138fe838f741b2c10f416cf9 Mon Sep 17 00:00:00 2001 From: Alexei Starovoitov Date: Wed, 28 Mar 2018 12:05:37 -0700 Subject: bpf: introduce BPF_RAW_TRACEPOINT Introduce BPF_PROG_TYPE_RAW_TRACEPOINT bpf program type to access kernel internal arguments of the tracepoints in their raw form. >From bpf program point of view the access to the arguments look like: struct bpf_raw_tracepoint_args { __u64 args[0]; }; int bpf_prog(struct bpf_raw_tracepoint_args *ctx) { // program can read args[N] where N depends on tracepoint // and statically verified at program load+attach time } kprobe+bpf infrastructure allows programs access function arguments. This feature allows programs access raw tracepoint arguments. Similar to proposed 'dynamic ftrace events' there are no abi guarantees to what the tracepoints arguments are and what their meaning is. The program needs to type cast args properly and use bpf_probe_read() helper to access struct fields when argument is a pointer. For every tracepoint __bpf_trace_##call function is prepared. In assembler it looks like: (gdb) disassemble __bpf_trace_xdp_exception Dump of assembler code for function __bpf_trace_xdp_exception: 0xffffffff81132080 <+0>: mov %ecx,%ecx 0xffffffff81132082 <+2>: jmpq 0xffffffff811231f0 where TRACE_EVENT(xdp_exception, TP_PROTO(const struct net_device *dev, const struct bpf_prog *xdp, u32 act), The above assembler snippet is casting 32-bit 'act' field into 'u64' to pass into bpf_trace_run3(), while 'dev' and 'xdp' args are passed as-is. All of ~500 of __bpf_trace_*() functions are only 5-10 byte long and in total this approach adds 7k bytes to .text. This approach gives the lowest possible overhead while calling trace_xdp_exception() from kernel C code and transitioning into bpf land. Since tracepoint+bpf are used at speeds of 1M+ events per second this is valuable optimization. The new BPF_RAW_TRACEPOINT_OPEN sys_bpf command is introduced that returns anon_inode FD of 'bpf-raw-tracepoint' object. The user space looks like: // load bpf prog with BPF_PROG_TYPE_RAW_TRACEPOINT type prog_fd = bpf_prog_load(...); // receive anon_inode fd for given bpf_raw_tracepoint with prog attached raw_tp_fd = bpf_raw_tracepoint_open("xdp_exception", prog_fd); Ctrl-C of tracing daemon or cmdline tool that uses this feature will automatically detach bpf program, unload it and unregister tracepoint probe. On the kernel side the __bpf_raw_tp_map section of pointers to tracepoint definition and to __bpf_trace_*() probe function is used to find a tracepoint with "xdp_exception" name and corresponding __bpf_trace_xdp_exception() probe function which are passed to tracepoint_probe_register() to connect probe with tracepoint. Addition of bpf_raw_tracepoint doesn't interfere with ftrace and perf tracepoint mechanisms. perf_event_open() can be used in parallel on the same tracepoint. Multiple bpf_raw_tracepoint_open("xdp_exception", prog_fd) are permitted. Each with its own bpf program. The kernel will execute all tracepoint probes and all attached bpf programs. In the future bpf_raw_tracepoints can be extended with query/introspection logic. __bpf_raw_tp_map section logic was contributed by Steven Rostedt Signed-off-by: Alexei Starovoitov Signed-off-by: Steven Rostedt (VMware) Acked-by: Steven Rostedt (VMware) Signed-off-by: Daniel Borkmann --- include/asm-generic/vmlinux.lds.h | 10 +++ include/linux/bpf_types.h | 1 + include/linux/trace_events.h | 42 +++++++++ include/linux/tracepoint-defs.h | 6 ++ include/trace/bpf_probe.h | 92 +++++++++++++++++++ include/trace/define_trace.h | 1 + include/uapi/linux/bpf.h | 11 +++ kernel/bpf/syscall.c | 78 ++++++++++++++++ kernel/trace/bpf_trace.c | 183 ++++++++++++++++++++++++++++++++++++++ 9 files changed, 424 insertions(+) create mode 100644 include/trace/bpf_probe.h (limited to 'include/linux') diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 1ab0e520d6fc..8add3493a202 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -178,6 +178,15 @@ #define TRACE_SYSCALLS() #endif +#ifdef CONFIG_BPF_EVENTS +#define BPF_RAW_TP() STRUCT_ALIGN(); \ + VMLINUX_SYMBOL(__start__bpf_raw_tp) = .; \ + KEEP(*(__bpf_raw_tp_map)) \ + VMLINUX_SYMBOL(__stop__bpf_raw_tp) = .; +#else +#define BPF_RAW_TP() +#endif + #ifdef CONFIG_SERIAL_EARLYCON #define EARLYCON_TABLE() STRUCT_ALIGN(); \ VMLINUX_SYMBOL(__earlycon_table) = .; \ @@ -249,6 +258,7 @@ LIKELY_PROFILE() \ BRANCH_PROFILE() \ TRACE_PRINTKS() \ + BPF_RAW_TP() \ TRACEPOINT_STR() /* diff --git a/include/linux/bpf_types.h b/include/linux/bpf_types.h index 5e2e8a49fb21..6d7243bfb0ff 100644 --- a/include/linux/bpf_types.h +++ b/include/linux/bpf_types.h @@ -19,6 +19,7 @@ BPF_PROG_TYPE(BPF_PROG_TYPE_SK_MSG, sk_msg) BPF_PROG_TYPE(BPF_PROG_TYPE_KPROBE, kprobe) BPF_PROG_TYPE(BPF_PROG_TYPE_TRACEPOINT, tracepoint) BPF_PROG_TYPE(BPF_PROG_TYPE_PERF_EVENT, perf_event) +BPF_PROG_TYPE(BPF_PROG_TYPE_RAW_TRACEPOINT, raw_tracepoint) #endif #ifdef CONFIG_CGROUP_BPF BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_DEVICE, cg_dev) diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h index 8a1442c4e513..b0357cd198b0 100644 --- a/include/linux/trace_events.h +++ b/include/linux/trace_events.h @@ -468,6 +468,9 @@ unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx); int perf_event_attach_bpf_prog(struct perf_event *event, struct bpf_prog *prog); void perf_event_detach_bpf_prog(struct perf_event *event); int perf_event_query_prog_array(struct perf_event *event, void __user *info); +int bpf_probe_register(struct bpf_raw_event_map *btp, struct bpf_prog *prog); +int bpf_probe_unregister(struct bpf_raw_event_map *btp, struct bpf_prog *prog); +struct bpf_raw_event_map *bpf_find_raw_tracepoint(const char *name); #else static inline unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx) { @@ -487,6 +490,18 @@ perf_event_query_prog_array(struct perf_event *event, void __user *info) { return -EOPNOTSUPP; } +static inline int bpf_probe_register(struct bpf_raw_event_map *btp, struct bpf_prog *p) +{ + return -EOPNOTSUPP; +} +static inline int bpf_probe_unregister(struct bpf_raw_event_map *btp, struct bpf_prog *p) +{ + return -EOPNOTSUPP; +} +static inline struct bpf_raw_event_map *bpf_find_raw_tracepoint(const char *name) +{ + return NULL; +} #endif enum { @@ -546,6 +561,33 @@ extern void ftrace_profile_free_filter(struct perf_event *event); void perf_trace_buf_update(void *record, u16 type); void *perf_trace_buf_alloc(int size, struct pt_regs **regs, int *rctxp); +void bpf_trace_run1(struct bpf_prog *prog, u64 arg1); +void bpf_trace_run2(struct bpf_prog *prog, u64 arg1, u64 arg2); +void bpf_trace_run3(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3); +void bpf_trace_run4(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4); +void bpf_trace_run5(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5); +void bpf_trace_run6(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5, u64 arg6); +void bpf_trace_run7(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7); +void bpf_trace_run8(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7, + u64 arg8); +void bpf_trace_run9(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7, + u64 arg8, u64 arg9); +void bpf_trace_run10(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7, + u64 arg8, u64 arg9, u64 arg10); +void bpf_trace_run11(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7, + u64 arg8, u64 arg9, u64 arg10, u64 arg11); +void bpf_trace_run12(struct bpf_prog *prog, u64 arg1, u64 arg2, + u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7, + u64 arg8, u64 arg9, u64 arg10, u64 arg11, u64 arg12); void perf_trace_run_bpf_submit(void *raw_data, int size, int rctx, struct trace_event_call *call, u64 count, struct pt_regs *regs, struct hlist_head *head, diff --git a/include/linux/tracepoint-defs.h b/include/linux/tracepoint-defs.h index 64ed7064f1fa..22c5a46e9693 100644 --- a/include/linux/tracepoint-defs.h +++ b/include/linux/tracepoint-defs.h @@ -35,4 +35,10 @@ struct tracepoint { struct tracepoint_func __rcu *funcs; }; +struct bpf_raw_event_map { + struct tracepoint *tp; + void *bpf_func; + u32 num_args; +} __aligned(32); + #endif diff --git a/include/trace/bpf_probe.h b/include/trace/bpf_probe.h new file mode 100644 index 000000000000..505dae0bed80 --- /dev/null +++ b/include/trace/bpf_probe.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#undef TRACE_SYSTEM_VAR + +#ifdef CONFIG_BPF_EVENTS + +#undef __entry +#define __entry entry + +#undef __get_dynamic_array +#define __get_dynamic_array(field) \ + ((void *)__entry + (__entry->__data_loc_##field & 0xffff)) + +#undef __get_dynamic_array_len +#define __get_dynamic_array_len(field) \ + ((__entry->__data_loc_##field >> 16) & 0xffff) + +#undef __get_str +#define __get_str(field) ((char *)__get_dynamic_array(field)) + +#undef __get_bitmask +#define __get_bitmask(field) (char *)__get_dynamic_array(field) + +#undef __perf_count +#define __perf_count(c) (c) + +#undef __perf_task +#define __perf_task(t) (t) + +/* cast any integer, pointer, or small struct to u64 */ +#define UINTTYPE(size) \ + __typeof__(__builtin_choose_expr(size == 1, (u8)1, \ + __builtin_choose_expr(size == 2, (u16)2, \ + __builtin_choose_expr(size == 4, (u32)3, \ + __builtin_choose_expr(size == 8, (u64)4, \ + (void)5))))) +#define __CAST_TO_U64(x) ({ \ + typeof(x) __src = (x); \ + UINTTYPE(sizeof(x)) __dst; \ + memcpy(&__dst, &__src, sizeof(__dst)); \ + (u64)__dst; }) + +#define __CAST1(a,...) __CAST_TO_U64(a) +#define __CAST2(a,...) __CAST_TO_U64(a), __CAST1(__VA_ARGS__) +#define __CAST3(a,...) __CAST_TO_U64(a), __CAST2(__VA_ARGS__) +#define __CAST4(a,...) __CAST_TO_U64(a), __CAST3(__VA_ARGS__) +#define __CAST5(a,...) __CAST_TO_U64(a), __CAST4(__VA_ARGS__) +#define __CAST6(a,...) __CAST_TO_U64(a), __CAST5(__VA_ARGS__) +#define __CAST7(a,...) __CAST_TO_U64(a), __CAST6(__VA_ARGS__) +#define __CAST8(a,...) __CAST_TO_U64(a), __CAST7(__VA_ARGS__) +#define __CAST9(a,...) __CAST_TO_U64(a), __CAST8(__VA_ARGS__) +#define __CAST10(a,...) __CAST_TO_U64(a), __CAST9(__VA_ARGS__) +#define __CAST11(a,...) __CAST_TO_U64(a), __CAST10(__VA_ARGS__) +#define __CAST12(a,...) __CAST_TO_U64(a), __CAST11(__VA_ARGS__) +/* tracepoints with more than 12 arguments will hit build error */ +#define CAST_TO_U64(...) CONCATENATE(__CAST, COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__) + +#undef DECLARE_EVENT_CLASS +#define DECLARE_EVENT_CLASS(call, proto, args, tstruct, assign, print) \ +static notrace void \ +__bpf_trace_##call(void *__data, proto) \ +{ \ + struct bpf_prog *prog = __data; \ + CONCATENATE(bpf_trace_run, COUNT_ARGS(args))(prog, CAST_TO_U64(args)); \ +} + +/* + * This part is compiled out, it is only here as a build time check + * to make sure that if the tracepoint handling changes, the + * bpf probe will fail to compile unless it too is updated. + */ +#undef DEFINE_EVENT +#define DEFINE_EVENT(template, call, proto, args) \ +static inline void bpf_test_probe_##call(void) \ +{ \ + check_trace_callback_type_##call(__bpf_trace_##template); \ +} \ +static struct bpf_raw_event_map __used \ + __attribute__((section("__bpf_raw_tp_map"))) \ +__bpf_trace_tp_map_##call = { \ + .tp = &__tracepoint_##call, \ + .bpf_func = (void *)__bpf_trace_##template, \ + .num_args = COUNT_ARGS(args), \ +}; + + +#undef DEFINE_EVENT_PRINT +#define DEFINE_EVENT_PRINT(template, name, proto, args, print) \ + DEFINE_EVENT(template, name, PARAMS(proto), PARAMS(args)) + +#include TRACE_INCLUDE(TRACE_INCLUDE_FILE) +#endif /* CONFIG_BPF_EVENTS */ diff --git a/include/trace/define_trace.h b/include/trace/define_trace.h index d9e3d4aa3f6e..cb30c5532144 100644 --- a/include/trace/define_trace.h +++ b/include/trace/define_trace.h @@ -95,6 +95,7 @@ #ifdef TRACEPOINTS_ENABLED #include #include +#include #endif #undef TRACE_EVENT diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 18b7c510c511..1878201c2d77 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -94,6 +94,7 @@ enum bpf_cmd { BPF_MAP_GET_FD_BY_ID, BPF_OBJ_GET_INFO_BY_FD, BPF_PROG_QUERY, + BPF_RAW_TRACEPOINT_OPEN, }; enum bpf_map_type { @@ -134,6 +135,7 @@ enum bpf_prog_type { BPF_PROG_TYPE_SK_SKB, BPF_PROG_TYPE_CGROUP_DEVICE, BPF_PROG_TYPE_SK_MSG, + BPF_PROG_TYPE_RAW_TRACEPOINT, }; enum bpf_attach_type { @@ -344,6 +346,11 @@ union bpf_attr { __aligned_u64 prog_ids; __u32 prog_cnt; } query; + + struct { + __u64 name; + __u32 prog_fd; + } raw_tracepoint; } __attribute__((aligned(8))); /* BPF helper function descriptions: @@ -1152,4 +1159,8 @@ struct bpf_cgroup_dev_ctx { __u32 minor; }; +struct bpf_raw_tracepoint_args { + __u64 args[0]; +}; + #endif /* _UAPI__LINUX_BPF_H__ */ diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c index 77d45bd9f507..95ca2523fa6e 100644 --- a/kernel/bpf/syscall.c +++ b/kernel/bpf/syscall.c @@ -1315,6 +1315,81 @@ static int bpf_obj_get(const union bpf_attr *attr) attr->file_flags); } +struct bpf_raw_tracepoint { + struct bpf_raw_event_map *btp; + struct bpf_prog *prog; +}; + +static int bpf_raw_tracepoint_release(struct inode *inode, struct file *filp) +{ + struct bpf_raw_tracepoint *raw_tp = filp->private_data; + + if (raw_tp->prog) { + bpf_probe_unregister(raw_tp->btp, raw_tp->prog); + bpf_prog_put(raw_tp->prog); + } + kfree(raw_tp); + return 0; +} + +static const struct file_operations bpf_raw_tp_fops = { + .release = bpf_raw_tracepoint_release, + .read = bpf_dummy_read, + .write = bpf_dummy_write, +}; + +#define BPF_RAW_TRACEPOINT_OPEN_LAST_FIELD raw_tracepoint.prog_fd + +static int bpf_raw_tracepoint_open(const union bpf_attr *attr) +{ + struct bpf_raw_tracepoint *raw_tp; + struct bpf_raw_event_map *btp; + struct bpf_prog *prog; + char tp_name[128]; + int tp_fd, err; + + if (strncpy_from_user(tp_name, u64_to_user_ptr(attr->raw_tracepoint.name), + sizeof(tp_name) - 1) < 0) + return -EFAULT; + tp_name[sizeof(tp_name) - 1] = 0; + + btp = bpf_find_raw_tracepoint(tp_name); + if (!btp) + return -ENOENT; + + raw_tp = kzalloc(sizeof(*raw_tp), GFP_USER); + if (!raw_tp) + return -ENOMEM; + raw_tp->btp = btp; + + prog = bpf_prog_get_type(attr->raw_tracepoint.prog_fd, + BPF_PROG_TYPE_RAW_TRACEPOINT); + if (IS_ERR(prog)) { + err = PTR_ERR(prog); + goto out_free_tp; + } + + err = bpf_probe_register(raw_tp->btp, prog); + if (err) + goto out_put_prog; + + raw_tp->prog = prog; + tp_fd = anon_inode_getfd("bpf-raw-tracepoint", &bpf_raw_tp_fops, raw_tp, + O_CLOEXEC); + if (tp_fd < 0) { + bpf_probe_unregister(raw_tp->btp, prog); + err = tp_fd; + goto out_put_prog; + } + return tp_fd; + +out_put_prog: + bpf_prog_put(prog); +out_free_tp: + kfree(raw_tp); + return err; +} + #ifdef CONFIG_CGROUP_BPF #define BPF_PROG_ATTACH_LAST_FIELD attach_flags @@ -1925,6 +2000,9 @@ SYSCALL_DEFINE3(bpf, int, cmd, union bpf_attr __user *, uattr, unsigned int, siz case BPF_OBJ_GET_INFO_BY_FD: err = bpf_obj_get_info_by_fd(&attr, uattr); break; + case BPF_RAW_TRACEPOINT_OPEN: + err = bpf_raw_tracepoint_open(&attr); + break; default: err = -EINVAL; break; diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 7f9691c86b6e..463e72d18c4c 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -735,6 +735,86 @@ static const struct bpf_func_proto *pe_prog_func_proto(enum bpf_func_id func_id) } } +/* + * bpf_raw_tp_regs are separate from bpf_pt_regs used from skb/xdp + * to avoid potential recursive reuse issue when/if tracepoints are added + * inside bpf_*_event_output and/or bpf_get_stack_id + */ +static DEFINE_PER_CPU(struct pt_regs, bpf_raw_tp_regs); +BPF_CALL_5(bpf_perf_event_output_raw_tp, struct bpf_raw_tracepoint_args *, args, + struct bpf_map *, map, u64, flags, void *, data, u64, size) +{ + struct pt_regs *regs = this_cpu_ptr(&bpf_raw_tp_regs); + + perf_fetch_caller_regs(regs); + return ____bpf_perf_event_output(regs, map, flags, data, size); +} + +static const struct bpf_func_proto bpf_perf_event_output_proto_raw_tp = { + .func = bpf_perf_event_output_raw_tp, + .gpl_only = true, + .ret_type = RET_INTEGER, + .arg1_type = ARG_PTR_TO_CTX, + .arg2_type = ARG_CONST_MAP_PTR, + .arg3_type = ARG_ANYTHING, + .arg4_type = ARG_PTR_TO_MEM, + .arg5_type = ARG_CONST_SIZE_OR_ZERO, +}; + +BPF_CALL_3(bpf_get_stackid_raw_tp, struct bpf_raw_tracepoint_args *, args, + struct bpf_map *, map, u64, flags) +{ + struct pt_regs *regs = this_cpu_ptr(&bpf_raw_tp_regs); + + perf_fetch_caller_regs(regs); + /* similar to bpf_perf_event_output_tp, but pt_regs fetched differently */ + return bpf_get_stackid((unsigned long) regs, (unsigned long) map, + flags, 0, 0); +} + +static const struct bpf_func_proto bpf_get_stackid_proto_raw_tp = { + .func = bpf_get_stackid_raw_tp, + .gpl_only = true, + .ret_type = RET_INTEGER, + .arg1_type = ARG_PTR_TO_CTX, + .arg2_type = ARG_CONST_MAP_PTR, + .arg3_type = ARG_ANYTHING, +}; + +static const struct bpf_func_proto *raw_tp_prog_func_proto(enum bpf_func_id func_id) +{ + switch (func_id) { + case BPF_FUNC_perf_event_output: + return &bpf_perf_event_output_proto_raw_tp; + case BPF_FUNC_get_stackid: + return &bpf_get_stackid_proto_raw_tp; + default: + return tracing_func_proto(func_id); + } +} + +static bool raw_tp_prog_is_valid_access(int off, int size, + enum bpf_access_type type, + struct bpf_insn_access_aux *info) +{ + /* largest tracepoint in the kernel has 12 args */ + if (off < 0 || off >= sizeof(__u64) * 12) + return false; + if (type != BPF_READ) + return false; + if (off % size != 0) + return false; + return true; +} + +const struct bpf_verifier_ops raw_tracepoint_verifier_ops = { + .get_func_proto = raw_tp_prog_func_proto, + .is_valid_access = raw_tp_prog_is_valid_access, +}; + +const struct bpf_prog_ops raw_tracepoint_prog_ops = { +}; + static bool pe_prog_is_valid_access(int off, int size, enum bpf_access_type type, struct bpf_insn_access_aux *info) { @@ -908,3 +988,106 @@ int perf_event_query_prog_array(struct perf_event *event, void __user *info) return ret; } + +extern struct bpf_raw_event_map __start__bpf_raw_tp[]; +extern struct bpf_raw_event_map __stop__bpf_raw_tp[]; + +struct bpf_raw_event_map *bpf_find_raw_tracepoint(const char *name) +{ + struct bpf_raw_event_map *btp = __start__bpf_raw_tp; + + for (; btp < __stop__bpf_raw_tp; btp++) { + if (!strcmp(btp->tp->name, name)) + return btp; + } + return NULL; +} + +static __always_inline +void __bpf_trace_run(struct bpf_prog *prog, u64 *args) +{ + rcu_read_lock(); + preempt_disable(); + (void) BPF_PROG_RUN(prog, args); + preempt_enable(); + rcu_read_unlock(); +} + +#define UNPACK(...) __VA_ARGS__ +#define REPEAT_1(FN, DL, X, ...) FN(X) +#define REPEAT_2(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_1(FN, DL, __VA_ARGS__) +#define REPEAT_3(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_2(FN, DL, __VA_ARGS__) +#define REPEAT_4(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_3(FN, DL, __VA_ARGS__) +#define REPEAT_5(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_4(FN, DL, __VA_ARGS__) +#define REPEAT_6(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_5(FN, DL, __VA_ARGS__) +#define REPEAT_7(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_6(FN, DL, __VA_ARGS__) +#define REPEAT_8(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_7(FN, DL, __VA_ARGS__) +#define REPEAT_9(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_8(FN, DL, __VA_ARGS__) +#define REPEAT_10(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_9(FN, DL, __VA_ARGS__) +#define REPEAT_11(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_10(FN, DL, __VA_ARGS__) +#define REPEAT_12(FN, DL, X, ...) FN(X) UNPACK DL REPEAT_11(FN, DL, __VA_ARGS__) +#define REPEAT(X, FN, DL, ...) REPEAT_##X(FN, DL, __VA_ARGS__) + +#define SARG(X) u64 arg##X +#define COPY(X) args[X] = arg##X + +#define __DL_COM (,) +#define __DL_SEM (;) + +#define __SEQ_0_11 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 + +#define BPF_TRACE_DEFN_x(x) \ + void bpf_trace_run##x(struct bpf_prog *prog, \ + REPEAT(x, SARG, __DL_COM, __SEQ_0_11)) \ + { \ + u64 args[x]; \ + REPEAT(x, COPY, __DL_SEM, __SEQ_0_11); \ + __bpf_trace_run(prog, args); \ + } \ + EXPORT_SYMBOL_GPL(bpf_trace_run##x) +BPF_TRACE_DEFN_x(1); +BPF_TRACE_DEFN_x(2); +BPF_TRACE_DEFN_x(3); +BPF_TRACE_DEFN_x(4); +BPF_TRACE_DEFN_x(5); +BPF_TRACE_DEFN_x(6); +BPF_TRACE_DEFN_x(7); +BPF_TRACE_DEFN_x(8); +BPF_TRACE_DEFN_x(9); +BPF_TRACE_DEFN_x(10); +BPF_TRACE_DEFN_x(11); +BPF_TRACE_DEFN_x(12); + +static int __bpf_probe_register(struct bpf_raw_event_map *btp, struct bpf_prog *prog) +{ + struct tracepoint *tp = btp->tp; + + /* + * check that program doesn't access arguments beyond what's + * available in this tracepoint + */ + if (prog->aux->max_ctx_offset > btp->num_args * sizeof(u64)) + return -EINVAL; + + return tracepoint_probe_register(tp, (void *)btp->bpf_func, prog); +} + +int bpf_probe_register(struct bpf_raw_event_map *btp, struct bpf_prog *prog) +{ + int err; + + mutex_lock(&bpf_event_mutex); + err = __bpf_probe_register(btp, prog); + mutex_unlock(&bpf_event_mutex); + return err; +} + +int bpf_probe_unregister(struct bpf_raw_event_map *btp, struct bpf_prog *prog) +{ + int err; + + mutex_lock(&bpf_event_mutex); + err = tracepoint_probe_unregister(btp->tp, (void *)btp->bpf_func, prog); + mutex_unlock(&bpf_event_mutex); + return err; +} -- cgit v1.2.3 From e59ac634908f4ea90066e6db7dd7ae8ca02815ff Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Wed, 28 Mar 2018 17:48:33 -0700 Subject: bpf: add parenthesis around argument of BPF_LDST_BYTES() BPF_LDST_BYTES() does not put it's argument in parenthesis when referencing it. This makes it impossible to pass pointers obtained by address-of operator (e.g. BPF_LDST_BYTES(&insn)). Add the parenthesis. Signed-off-by: Jakub Kicinski Reviewed-by: Quentin Monnet Signed-off-by: Alexei Starovoitov --- include/linux/filter.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/filter.h b/include/linux/filter.h index 109d05ccea9a..c2f167db8bd5 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -372,7 +372,7 @@ struct xdp_rxq_info; #define BPF_LDST_BYTES(insn) \ ({ \ - const int __size = bpf_size_to_bytes(BPF_SIZE(insn->code)); \ + const int __size = bpf_size_to_bytes(BPF_SIZE((insn)->code)); \ WARN_ON(__size < 0); \ __size; \ }) -- cgit v1.2.3 From 64bdff698092aa6be28c3b248f887022eec77902 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Wed, 14 Mar 2018 12:27:21 +0100 Subject: PM: cpuidle/suspend: Add s2idle usage and time state attributes Add a new attribute group called "s2idle" under the sysfs directory of each cpuidle state that supports the ->enter_s2idle callback and put two new attributes, "usage" and "time", into that group to represent the number of times the given state was requested for suspend-to-idle and the total time spent in suspend-to-idle after requesting that state, respectively. That will allow diagnostic information related to suspend-to-idle to be collected without enabling advanced debug features and analyzing dmesg output. Signed-off-by: Rafael J. Wysocki --- Documentation/ABI/testing/sysfs-devices-system-cpu | 25 ++++++++++ drivers/cpuidle/cpuidle.c | 9 ++++ drivers/cpuidle/sysfs.c | 54 ++++++++++++++++++++++ include/linux/cpuidle.h | 4 ++ 4 files changed, 92 insertions(+) (limited to 'include/linux') diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 4ed63b6cfb15..025b7cf3768d 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -198,6 +198,31 @@ Description: time (in microseconds) this cpu should spend in this idle state to make the transition worth the effort. +What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/s2idle/ +Date: March 2018 +KernelVersion: v4.17 +Contact: Linux power management list +Description: + Idle state usage statistics related to suspend-to-idle. + + This attribute group is only present for states that can be + used in suspend-to-idle with suspended timekeeping. + +What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/s2idle/time +Date: March 2018 +KernelVersion: v4.17 +Contact: Linux power management list +Description: + Total time spent by the CPU in suspend-to-idle (with scheduler + tick suspended) after requesting this state. + +What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/s2idle/usage +Date: March 2018 +KernelVersion: v4.17 +Contact: Linux power management list +Description: + Total number of times this state has been requested by the CPU + while entering suspend-to-idle. What: /sys/devices/system/cpu/cpu#/cpufreq/* Date: pre-git history diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c index 68a16827f45f..0003e9a02637 100644 --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -131,6 +131,10 @@ int cpuidle_find_deepest_state(struct cpuidle_driver *drv, static void enter_s2idle_proper(struct cpuidle_driver *drv, struct cpuidle_device *dev, int index) { + ktime_t time_start, time_end; + + time_start = ns_to_ktime(local_clock()); + /* * trace_suspend_resume() called by tick_freeze() for the last CPU * executing it contains RCU usage regarded as invalid in the idle @@ -152,6 +156,11 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv, */ RCU_NONIDLE(tick_unfreeze()); start_critical_timings(); + + time_end = ns_to_ktime(local_clock()); + + dev->states_usage[index].s2idle_time += ktime_us_delta(time_end, time_start); + dev->states_usage[index].s2idle_usage++; } /** diff --git a/drivers/cpuidle/sysfs.c b/drivers/cpuidle/sysfs.c index ae948b1da93a..e754c7aae7f7 100644 --- a/drivers/cpuidle/sysfs.c +++ b/drivers/cpuidle/sysfs.c @@ -330,6 +330,58 @@ struct cpuidle_state_kobj { struct kobject kobj; }; +#ifdef CONFIG_SUSPEND +#define define_show_state_s2idle_ull_function(_name) \ +static ssize_t show_state_s2idle_##_name(struct cpuidle_state *state, \ + struct cpuidle_state_usage *state_usage, \ + char *buf) \ +{ \ + return sprintf(buf, "%llu\n", state_usage->s2idle_##_name);\ +} + +define_show_state_s2idle_ull_function(usage); +define_show_state_s2idle_ull_function(time); + +#define define_one_state_s2idle_ro(_name, show) \ +static struct cpuidle_state_attr attr_s2idle_##_name = \ + __ATTR(_name, 0444, show, NULL) + +define_one_state_s2idle_ro(usage, show_state_s2idle_usage); +define_one_state_s2idle_ro(time, show_state_s2idle_time); + +static struct attribute *cpuidle_state_s2idle_attrs[] = { + &attr_s2idle_usage.attr, + &attr_s2idle_time.attr, + NULL +}; + +static const struct attribute_group cpuidle_state_s2idle_group = { + .name = "s2idle", + .attrs = cpuidle_state_s2idle_attrs, +}; + +static void cpuidle_add_s2idle_attr_group(struct cpuidle_state_kobj *kobj) +{ + int ret; + + if (!kobj->state->enter_s2idle) + return; + + ret = sysfs_create_group(&kobj->kobj, &cpuidle_state_s2idle_group); + if (ret) + pr_debug("%s: sysfs attribute group not created\n", __func__); +} + +static void cpuidle_remove_s2idle_attr_group(struct cpuidle_state_kobj *kobj) +{ + if (kobj->state->enter_s2idle) + sysfs_remove_group(&kobj->kobj, &cpuidle_state_s2idle_group); +} +#else +static inline void cpuidle_add_s2idle_attr_group(struct cpuidle_state_kobj *kobj) { } +static inline void cpuidle_remove_s2idle_attr_group(struct cpuidle_state_kobj *kobj) { } +#endif /* CONFIG_SUSPEND */ + #define kobj_to_state_obj(k) container_of(k, struct cpuidle_state_kobj, kobj) #define kobj_to_state(k) (kobj_to_state_obj(k)->state) #define kobj_to_state_usage(k) (kobj_to_state_obj(k)->state_usage) @@ -383,6 +435,7 @@ static struct kobj_type ktype_state_cpuidle = { static inline void cpuidle_free_state_kobj(struct cpuidle_device *device, int i) { + cpuidle_remove_s2idle_attr_group(device->kobjs[i]); kobject_put(&device->kobjs[i]->kobj); wait_for_completion(&device->kobjs[i]->kobj_unregister); kfree(device->kobjs[i]); @@ -417,6 +470,7 @@ static int cpuidle_add_state_sysfs(struct cpuidle_device *device) kfree(kobj); goto error_state; } + cpuidle_add_s2idle_attr_group(kobj); kobject_uevent(&kobj->kobj, KOBJ_ADD); device->kobjs[i] = kobj; } diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h index 0b3fc229086c..a806e94c482f 100644 --- a/include/linux/cpuidle.h +++ b/include/linux/cpuidle.h @@ -33,6 +33,10 @@ struct cpuidle_state_usage { unsigned long long disable; unsigned long long usage; unsigned long long time; /* in US */ +#ifdef CONFIG_SUSPEND + unsigned long long s2idle_usage; + unsigned long long s2idle_time; /* in US */ +#endif }; struct cpuidle_state { -- cgit v1.2.3 From 6ed70cf342de03c7b11cd4eb032705faeb29d284 Mon Sep 17 00:00:00 2001 From: Alexander Shishkin Date: Thu, 29 Mar 2018 15:06:48 +0300 Subject: perf/x86/pt, coresight: Clean up address filter structure This is a cosmetic patch that deals with the address filter structure's ambiguous fields 'filter' and 'range'. The former stands to mean that the filter's *action* should be to filter the traces to its address range if it's set or stop tracing if it's unset. This is confusing and hard on the eyes, so this patch replaces it with 'action' enum. The 'range' field is completely redundant (meaning that the filter is an address range as opposed to a single address trigger), as we can use zero size to mean the same thing. Signed-off-by: Alexander Shishkin Acked-by: Mathieu Poirier Acked-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: Will Deacon Link: http://lkml.kernel.org/r/20180329120648.11902-1-alexander.shishkin@linux.intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/pt.c | 13 ++++-- drivers/hwtracing/coresight/coresight-etm-perf.c | 59 +++++++++++------------- include/linux/perf_event.h | 14 ++++-- kernel/events/core.c | 26 +++++++---- 4 files changed, 63 insertions(+), 49 deletions(-) (limited to 'include/linux') diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 81fd41d5a0d9..3b993942a0e4 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1186,8 +1186,12 @@ static int pt_event_addr_filters_validate(struct list_head *filters) int range = 0; list_for_each_entry(filter, filters, entry) { - /* PT doesn't support single address triggers */ - if (!filter->range || !filter->size) + /* + * PT doesn't support single address triggers and + * 'start' filters. + */ + if (!filter->size || + filter->action == PERF_ADDR_FILTER_ACTION_START) return -EOPNOTSUPP; if (!filter->inode) { @@ -1227,7 +1231,10 @@ static void pt_event_addr_filters_sync(struct perf_event *event) filters->filter[range].msr_a = msr_a; filters->filter[range].msr_b = msr_b; - filters->filter[range].config = filter->filter ? 1 : 2; + if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER) + filters->filter[range].config = 1; + else + filters->filter[range].config = 2; range++; } diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 8a0ad77574e7..4e5ed6597f2f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -393,35 +393,26 @@ static int etm_addr_filters_validate(struct list_head *filters) if (++index > ETM_ADDR_CMP_MAX) return -EOPNOTSUPP; + /* filter::size==0 means single address trigger */ + if (filter->size) { + /* + * The existing code relies on START/STOP filters + * being address filters. + */ + if (filter->action == PERF_ADDR_FILTER_ACTION_START || + filter->action == PERF_ADDR_FILTER_ACTION_STOP) + return -EOPNOTSUPP; + + range = true; + } else + address = true; + /* - * As taken from the struct perf_addr_filter documentation: - * @range: 1: range, 0: address - * * At this time we don't allow range and start/stop filtering * to cohabitate, they have to be mutually exclusive. */ - if ((filter->range == 1) && address) + if (range && address) return -EOPNOTSUPP; - - if ((filter->range == 0) && range) - return -EOPNOTSUPP; - - /* - * For range filtering, the second address in the address - * range comparator needs to be higher than the first. - * Invalid otherwise. - */ - if (filter->range && filter->size == 0) - return -EINVAL; - - /* - * Everything checks out with this filter, record what we've - * received before moving on to the next one. - */ - if (filter->range) - range = true; - else - address = true; } return 0; @@ -441,18 +432,20 @@ static void etm_addr_filters_sync(struct perf_event *event) stop = start + filter->size; etm_filter = &filters->etm_filter[i]; - if (filter->range == 1) { + switch (filter->action) { + case PERF_ADDR_FILTER_ACTION_FILTER: etm_filter->start_addr = start; etm_filter->stop_addr = stop; etm_filter->type = ETM_ADDR_TYPE_RANGE; - } else { - if (filter->filter == 1) { - etm_filter->start_addr = start; - etm_filter->type = ETM_ADDR_TYPE_START; - } else { - etm_filter->stop_addr = stop; - etm_filter->type = ETM_ADDR_TYPE_STOP; - } + break; + case PERF_ADDR_FILTER_ACTION_START: + etm_filter->start_addr = start; + etm_filter->type = ETM_ADDR_TYPE_START; + break; + case PERF_ADDR_FILTER_ACTION_STOP: + etm_filter->stop_addr = stop; + etm_filter->type = ETM_ADDR_TYPE_STOP; + break; } i++; } diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index ff39ab011376..e71e99eb9a4e 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -449,14 +449,19 @@ struct pmu { int (*filter_match) (struct perf_event *event); /* optional */ }; +enum perf_addr_filter_action_t { + PERF_ADDR_FILTER_ACTION_STOP = 0, + PERF_ADDR_FILTER_ACTION_START, + PERF_ADDR_FILTER_ACTION_FILTER, +}; + /** * struct perf_addr_filter - address range filter definition * @entry: event's filter list linkage * @inode: object file's inode for file-based filters * @offset: filter range offset - * @size: filter range size - * @range: 1: range, 0: address - * @filter: 1: filter/start, 0: stop + * @size: filter range size (size==0 means single address trigger) + * @action: filter/start/stop * * This is a hardware-agnostic filter configuration as specified by the user. */ @@ -465,8 +470,7 @@ struct perf_addr_filter { struct inode *inode; unsigned long offset; unsigned long size; - unsigned int range : 1, - filter : 1; + enum perf_addr_filter_action_t action; }; /** diff --git a/kernel/events/core.c b/kernel/events/core.c index 7517b4fb3ef4..fc1c330c6bd6 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -8803,7 +8803,8 @@ restart: * * for kernel addresses: [/] * * for object files: [/]@ * - * if is not specified, the range is treated as a single address. + * if is not specified or is zero, the range is treated as a single + * address; not valid for ACTION=="filter". */ enum { IF_ACT_NONE = -1, @@ -8853,6 +8854,11 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, return -ENOMEM; while ((start = strsep(&fstr, " ,\n")) != NULL) { + static const enum perf_addr_filter_action_t actions[] = { + [IF_ACT_FILTER] = PERF_ADDR_FILTER_ACTION_FILTER, + [IF_ACT_START] = PERF_ADDR_FILTER_ACTION_START, + [IF_ACT_STOP] = PERF_ADDR_FILTER_ACTION_STOP, + }; ret = -EINVAL; if (!*start) @@ -8869,12 +8875,11 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, switch (token) { case IF_ACT_FILTER: case IF_ACT_START: - filter->filter = 1; - case IF_ACT_STOP: if (state != IF_STATE_ACTION) goto fail; + filter->action = actions[token]; state = IF_STATE_SOURCE; break; @@ -8887,15 +8892,12 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, if (state != IF_STATE_SOURCE) goto fail; - if (token == IF_SRC_FILE || token == IF_SRC_KERNEL) - filter->range = 1; - *args[0].to = 0; ret = kstrtoul(args[0].from, 0, &filter->offset); if (ret) goto fail; - if (filter->range) { + if (token == IF_SRC_KERNEL || token == IF_SRC_FILE) { *args[1].to = 0; ret = kstrtoul(args[1].from, 0, &filter->size); if (ret) @@ -8903,7 +8905,7 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, } if (token == IF_SRC_FILE || token == IF_SRC_FILEADDR) { - int fpos = filter->range ? 2 : 1; + int fpos = token == IF_SRC_FILE ? 2 : 1; filename = match_strdup(&args[fpos]); if (!filename) { @@ -8929,6 +8931,14 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr, if (kernel && event->attr.exclude_kernel) goto fail; + /* + * ACTION "filter" must have a non-zero length region + * specified. + */ + if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER && + !filter->size) + goto fail; + if (!kernel) { if (!filename) goto fail; -- cgit v1.2.3 From f0b07bb151b098d291fd1fd71ef7a2df56fb124a Mon Sep 17 00:00:00 2001 From: Kirill Tkhai Date: Thu, 29 Mar 2018 19:20:32 +0300 Subject: net: Introduce net_rwsem to protect net_namespace_list rtnl_lock() is used everywhere, and contention is very high. When someone wants to iterate over alive net namespaces, he/she has no a possibility to do that without exclusive lock. But the exclusive rtnl_lock() in such places is overkill, and it just increases the contention. Yes, there is already for_each_net_rcu() in kernel, but it requires rcu_read_lock(), and this can't be sleepable. Also, sometimes it may be need really prevent net_namespace_list growth, so for_each_net_rcu() is not fit there. This patch introduces new rw_semaphore, which will be used instead of rtnl_mutex to protect net_namespace_list. It is sleepable and allows not-exclusive iterations over net namespaces list. It allows to stop using rtnl_lock() in several places (what is made in next patches) and makes less the time, we keep rtnl_mutex. Here we just add new lock, while the explanation of we can remove rtnl_lock() there are in next patches. Fine grained locks generally are better, then one big lock, so let's do that with net_namespace_list, while the situation allows that. Signed-off-by: Kirill Tkhai Signed-off-by: David S. Miller --- drivers/infiniband/core/roce_gid_mgmt.c | 2 ++ include/linux/rtnetlink.h | 1 + include/net/net_namespace.h | 1 + net/core/dev.c | 5 +++++ net/core/fib_notifier.c | 2 ++ net/core/net_namespace.c | 18 +++++++++++++----- net/core/rtnetlink.c | 5 +++++ net/netfilter/nf_conntrack_core.c | 2 ++ net/openvswitch/datapath.c | 2 ++ net/wireless/wext-core.c | 2 ++ security/selinux/include/xfrm.h | 2 ++ 11 files changed, 37 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/core/roce_gid_mgmt.c b/drivers/infiniband/core/roce_gid_mgmt.c index 5a52ec77940a..cc2966380c0c 100644 --- a/drivers/infiniband/core/roce_gid_mgmt.c +++ b/drivers/infiniband/core/roce_gid_mgmt.c @@ -403,10 +403,12 @@ static void enum_all_gids_of_dev_cb(struct ib_device *ib_dev, * our feet */ rtnl_lock(); + down_read(&net_rwsem); for_each_net(net) for_each_netdev(net, ndev) if (is_eth_port_of_netdev(ib_dev, port, rdma_ndev, ndev)) add_netdev_ips(ib_dev, port, rdma_ndev, ndev); + up_read(&net_rwsem); rtnl_unlock(); } diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index c7d1e4689325..5225832bd6ff 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -37,6 +37,7 @@ extern int rtnl_lock_killable(void); extern wait_queue_head_t netdev_unregistering_wq; extern struct rw_semaphore pernet_ops_rwsem; +extern struct rw_semaphore net_rwsem; #ifdef CONFIG_PROVE_LOCKING extern bool lockdep_rtnl_is_held(void); diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h index 1ab4f920f109..47e35cce3b64 100644 --- a/include/net/net_namespace.h +++ b/include/net/net_namespace.h @@ -291,6 +291,7 @@ static inline struct net *read_pnet(const possible_net_t *pnet) #endif } +/* Protected by net_rwsem */ #define for_each_net(VAR) \ list_for_each_entry(VAR, &net_namespace_list, list) diff --git a/net/core/dev.c b/net/core/dev.c index e13807b5c84d..eca5458b2753 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -1629,6 +1629,7 @@ int register_netdevice_notifier(struct notifier_block *nb) goto unlock; if (dev_boot_phase) goto unlock; + down_read(&net_rwsem); for_each_net(net) { for_each_netdev(net, dev) { err = call_netdevice_notifier(nb, NETDEV_REGISTER, dev); @@ -1642,6 +1643,7 @@ int register_netdevice_notifier(struct notifier_block *nb) call_netdevice_notifier(nb, NETDEV_UP, dev); } } + up_read(&net_rwsem); unlock: rtnl_unlock(); @@ -1664,6 +1666,7 @@ rollback: } outroll: + up_read(&net_rwsem); raw_notifier_chain_unregister(&netdev_chain, nb); goto unlock; } @@ -1694,6 +1697,7 @@ int unregister_netdevice_notifier(struct notifier_block *nb) if (err) goto unlock; + down_read(&net_rwsem); for_each_net(net) { for_each_netdev(net, dev) { if (dev->flags & IFF_UP) { @@ -1704,6 +1708,7 @@ int unregister_netdevice_notifier(struct notifier_block *nb) call_netdevice_notifier(nb, NETDEV_UNREGISTER, dev); } } + up_read(&net_rwsem); unlock: rtnl_unlock(); return err; diff --git a/net/core/fib_notifier.c b/net/core/fib_notifier.c index 0c048bdeb016..614b985c92a4 100644 --- a/net/core/fib_notifier.c +++ b/net/core/fib_notifier.c @@ -33,6 +33,7 @@ static unsigned int fib_seq_sum(void) struct net *net; rtnl_lock(); + down_read(&net_rwsem); for_each_net(net) { rcu_read_lock(); list_for_each_entry_rcu(ops, &net->fib_notifier_ops, list) { @@ -43,6 +44,7 @@ static unsigned int fib_seq_sum(void) } rcu_read_unlock(); } + up_read(&net_rwsem); rtnl_unlock(); return fib_seq; diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c index b5796d17a302..7fdf321d4997 100644 --- a/net/core/net_namespace.c +++ b/net/core/net_namespace.c @@ -33,6 +33,10 @@ static struct list_head *first_device = &pernet_list; LIST_HEAD(net_namespace_list); EXPORT_SYMBOL_GPL(net_namespace_list); +/* Protects net_namespace_list. Nests iside rtnl_lock() */ +DECLARE_RWSEM(net_rwsem); +EXPORT_SYMBOL_GPL(net_rwsem); + struct net init_net = { .count = REFCOUNT_INIT(1), .dev_base_head = LIST_HEAD_INIT(init_net.dev_base_head), @@ -309,9 +313,9 @@ static __net_init int setup_net(struct net *net, struct user_namespace *user_ns) if (error < 0) goto out_undo; } - rtnl_lock(); + down_write(&net_rwsem); list_add_tail_rcu(&net->list, &net_namespace_list); - rtnl_unlock(); + up_write(&net_rwsem); out: return error; @@ -450,7 +454,7 @@ static void unhash_nsid(struct net *net, struct net *last) * and this work is the only process, that may delete * a net from net_namespace_list. So, when the below * is executing, the list may only grow. Thus, we do not - * use for_each_net_rcu() or rtnl_lock(). + * use for_each_net_rcu() or net_rwsem. */ for_each_net(tmp) { int id; @@ -485,7 +489,7 @@ static void cleanup_net(struct work_struct *work) down_read(&pernet_ops_rwsem); /* Don't let anyone else find us. */ - rtnl_lock(); + down_write(&net_rwsem); llist_for_each_entry(net, net_kill_list, cleanup_list) list_del_rcu(&net->list); /* Cache last net. After we unlock rtnl, no one new net @@ -499,7 +503,7 @@ static void cleanup_net(struct work_struct *work) * useless anyway, as netns_ids are destroyed there. */ last = list_last_entry(&net_namespace_list, struct net, list); - rtnl_unlock(); + up_write(&net_rwsem); llist_for_each_entry(net, net_kill_list, cleanup_list) { unhash_nsid(net, last); @@ -900,6 +904,9 @@ static int __register_pernet_operations(struct list_head *list, list_add_tail(&ops->list, list); if (ops->init || (ops->id && ops->size)) { + /* We held write locked pernet_ops_rwsem, and parallel + * setup_net() and cleanup_net() are not possible. + */ for_each_net(net) { error = ops_init(ops, net); if (error) @@ -923,6 +930,7 @@ static void __unregister_pernet_operations(struct pernet_operations *ops) LIST_HEAD(net_exit_list); list_del(&ops->list); + /* See comment in __register_pernet_operations() */ for_each_net(net) list_add_tail(&net->exit_list, &net_exit_list); ops_exit_list(ops, &net_exit_list); diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 2d3949789cef..e86b28482ca7 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -418,9 +418,11 @@ void __rtnl_link_unregister(struct rtnl_link_ops *ops) { struct net *net; + down_read(&net_rwsem); for_each_net(net) { __rtnl_kill_links(net, ops); } + up_read(&net_rwsem); list_del(&ops->list); } EXPORT_SYMBOL_GPL(__rtnl_link_unregister); @@ -438,6 +440,9 @@ static void rtnl_lock_unregistering_all(void) for (;;) { unregistering = false; rtnl_lock(); + /* We held write locked pernet_ops_rwsem, and parallel + * setup_net() and cleanup_net() are not possible. + */ for_each_net(net) { if (net->dev_unreg_count > 0) { unregistering = true; diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index 705198de671d..370f9b7f051b 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c @@ -1764,12 +1764,14 @@ nf_ct_iterate_destroy(int (*iter)(struct nf_conn *i, void *data), void *data) struct net *net; rtnl_lock(); + down_read(&net_rwsem); for_each_net(net) { if (atomic_read(&net->ct.count) == 0) continue; __nf_ct_unconfirmed_destroy(net); nf_queue_nf_hook_drop(net); } + up_read(&net_rwsem); rtnl_unlock(); /* Need to wait for netns cleanup worker to finish, if its diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c index ef38e5aecd28..9746ee30a99b 100644 --- a/net/openvswitch/datapath.c +++ b/net/openvswitch/datapath.c @@ -2364,8 +2364,10 @@ static void __net_exit ovs_exit_net(struct net *dnet) __dp_destroy(dp); rtnl_lock(); + down_read(&net_rwsem); for_each_net(net) list_vports_from_net(net, dnet, &head); + up_read(&net_rwsem); rtnl_unlock(); /* Detach all vports from given namespace. */ diff --git a/net/wireless/wext-core.c b/net/wireless/wext-core.c index 9efbfc753347..544d7b62d7ca 100644 --- a/net/wireless/wext-core.c +++ b/net/wireless/wext-core.c @@ -349,11 +349,13 @@ void wireless_nlevent_flush(void) ASSERT_RTNL(); + down_read(&net_rwsem); for_each_net(net) { while ((skb = skb_dequeue(&net->wext_nlevents))) rtnl_notify(skb, net, 0, RTNLGRP_LINK, NULL, GFP_KERNEL); } + up_read(&net_rwsem); } EXPORT_SYMBOL_GPL(wireless_nlevent_flush); diff --git a/security/selinux/include/xfrm.h b/security/selinux/include/xfrm.h index 1f173a7a4daa..31d66431be1e 100644 --- a/security/selinux/include/xfrm.h +++ b/security/selinux/include/xfrm.h @@ -48,8 +48,10 @@ static inline void selinux_xfrm_notify_policyload(void) struct net *net; rtnl_lock(); + down_read(&net_rwsem); for_each_net(net) rt_genid_bump_all(net); + up_read(&net_rwsem); rtnl_unlock(); } #else -- cgit v1.2.3 From 50bc60cb155c813157fdca5b3b05194cd325d3e9 Mon Sep 17 00:00:00 2001 From: Michal Kalderon Date: Wed, 28 Mar 2018 11:42:16 +0300 Subject: qed*: Utilize FW 8.33.11.0 This FW contains several fixes and features RDMA Features - SRQ support - XRC support - Memory window support - RDMA low latency queue support - RDMA bonding support RDMA bug fixes - RDMA remote invalidate during retransmit fix - iWARP MPA connect interop issue with RTR fix - iWARP Legacy DPM support - Fix MPA reject flow - iWARP error handling - RQ WQE validation checks MISC - Fix some HSI types endianity - New Restriction: vlan insertion in core_tx_bd_data can't be set for LB packets ETH - HW QoS offload support - Fix vlan, dcb and sriov flow of VF sending a packet with inband VLAN tag instead of default VLAN - Allow GRE version 1 offloads in RX flow - Allow VXLAN steering iSCSI / FcoE - Fix bd availability checking flow - Support 256th sge proerly in iscsi/fcoe retransmit - Performance improvement - Fix handle iSCSI command arrival with AHS and with immediate - Fix ipv6 traffic class configuration DEBUG - Update debug utilities Signed-off-by: Michal Kalderon Signed-off-by: Tomer Tayar Signed-off-by: Manish Rangankar Signed-off-by: Ariel Elior Acked-by: Jason Gunthorpe Signed-off-by: David S. Miller --- drivers/infiniband/hw/qedr/qedr_hsi_rdma.h | 4 +- drivers/infiniband/hw/qedr/verbs.c | 4 +- drivers/net/ethernet/qlogic/qed/qed_debug.c | 415 +++-- drivers/net/ethernet/qlogic/qed/qed_dev.c | 4 +- drivers/net/ethernet/qlogic/qed/qed_hsi.h | 1892 ++++++++++---------- .../net/ethernet/qlogic/qed/qed_init_fw_funcs.c | 103 +- drivers/net/ethernet/qlogic/qed/qed_iwarp.c | 7 - drivers/net/ethernet/qlogic/qed/qed_l2.c | 2 +- drivers/net/ethernet/qlogic/qed/qed_ll2.c | 13 - include/linux/qed/common_hsi.h | 2 +- include/linux/qed/eth_common.h | 2 +- include/linux/qed/iscsi_common.h | 4 +- include/linux/qed/rdma_common.h | 2 + include/linux/qed/roce_common.h | 3 + 14 files changed, 1310 insertions(+), 1147 deletions(-) (limited to 'include/linux') diff --git a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h index 78b49002fbd2..b816c80df50b 100644 --- a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h +++ b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h @@ -45,7 +45,7 @@ struct rdma_cqe_responder { __le32 imm_data_or_inv_r_Key; __le32 length; __le32 imm_data_hi; - __le16 rq_cons; + __le16 rq_cons_or_srq_id; u8 flags; #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0 @@ -115,6 +115,7 @@ enum rdma_cqe_requester_status_enum { RDMA_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR, RDMA_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR, RDMA_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR, + RDMA_CQE_REQ_STS_XRC_VOILATION_ERR, MAX_RDMA_CQE_REQUESTER_STATUS_ENUM }; @@ -136,6 +137,7 @@ enum rdma_cqe_type { RDMA_CQE_TYPE_REQUESTER, RDMA_CQE_TYPE_RESPONDER_RQ, RDMA_CQE_TYPE_RESPONDER_SRQ, + RDMA_CQE_TYPE_RESPONDER_XRC_SRQ, RDMA_CQE_TYPE_INVALID, MAX_RDMA_CQE_TYPE }; diff --git a/drivers/infiniband/hw/qedr/verbs.c b/drivers/infiniband/hw/qedr/verbs.c index 875b17272d65..7d51ef47667f 100644 --- a/drivers/infiniband/hw/qedr/verbs.c +++ b/drivers/infiniband/hw/qedr/verbs.c @@ -3695,7 +3695,7 @@ static int process_resp_flush(struct qedr_qp *qp, struct qedr_cq *cq, static void try_consume_resp_cqe(struct qedr_cq *cq, struct qedr_qp *qp, struct rdma_cqe_responder *resp, int *update) { - if (le16_to_cpu(resp->rq_cons) == qp->rq.wqe_cons) { + if (le16_to_cpu(resp->rq_cons_or_srq_id) == qp->rq.wqe_cons) { consume_cqe(cq); *update |= 1; } @@ -3710,7 +3710,7 @@ static int qedr_poll_cq_resp(struct qedr_dev *dev, struct qedr_qp *qp, if (resp->status == RDMA_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR) { cnt = process_resp_flush(qp, cq, num_entries, wc, - resp->rq_cons); + resp->rq_cons_or_srq_id); try_consume_resp_cqe(cq, qp, resp, update); } else { cnt = process_resp_one(dev, qp, cq, wc, resp); diff --git a/drivers/net/ethernet/qlogic/qed/qed_debug.c b/drivers/net/ethernet/qlogic/qed/qed_debug.c index fdf37abee3d3..4926c5532fba 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_debug.c +++ b/drivers/net/ethernet/qlogic/qed/qed_debug.c @@ -265,6 +265,7 @@ struct grc_param_defs { u32 min; u32 max; bool is_preset; + bool is_persistent; u32 exclude_all_preset_val; u32 crash_preset_val; }; @@ -1520,129 +1521,129 @@ static struct platform_defs s_platform_defs[] = { static struct grc_param_defs s_grc_param_defs[] = { /* DBG_GRC_PARAM_DUMP_TSTORM */ - {{1, 1, 1}, 0, 1, false, 1, 1}, + {{1, 1, 1}, 0, 1, false, false, 1, 1}, /* DBG_GRC_PARAM_DUMP_MSTORM */ - {{1, 1, 1}, 0, 1, false, 1, 1}, + {{1, 1, 1}, 0, 1, false, false, 1, 1}, /* DBG_GRC_PARAM_DUMP_USTORM */ - {{1, 1, 1}, 0, 1, false, 1, 1}, + {{1, 1, 1}, 0, 1, false, false, 1, 1}, /* DBG_GRC_PARAM_DUMP_XSTORM */ - {{1, 1, 1}, 0, 1, false, 1, 1}, + {{1, 1, 1}, 0, 1, false, false, 1, 1}, /* DBG_GRC_PARAM_DUMP_YSTORM */ - {{1, 1, 1}, 0, 1, false, 1, 1}, + {{1, 1, 1}, 0, 1, false, false, 1, 1}, /* DBG_GRC_PARAM_DUMP_PSTORM */ - {{1, 1, 1}, 0, 1, false, 1, 1}, + {{1, 1, 1}, 0, 1, false, false, 1, 1}, /* DBG_GRC_PARAM_DUMP_REGS */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_RAM */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_PBUF */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_IOR */ - {{0, 0, 0}, 0, 1, false, 0, 1}, + {{0, 0, 0}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_VFC */ - {{0, 0, 0}, 0, 1, false, 0, 1}, + {{0, 0, 0}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_CM_CTX */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_ILT */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_RSS */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_CAU */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_QM */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_MCP */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, - /* DBG_GRC_PARAM_RESERVED */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + /* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */ + {{1, 1, 1}, 1, 0xffffffff, false, true, 0, 1}, /* DBG_GRC_PARAM_DUMP_CFC */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_IGU */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_BRB */ - {{0, 0, 0}, 0, 1, false, 0, 1}, + {{0, 0, 0}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_BTB */ - {{0, 0, 0}, 0, 1, false, 0, 1}, + {{0, 0, 0}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_BMB */ - {{0, 0, 0}, 0, 1, false, 0, 1}, + {{0, 0, 0}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_NIG */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_MULD */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_PRS */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_DMAE */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_TM */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_SDM */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_DIF */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_STATIC */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_UNSTALL */ - {{0, 0, 0}, 0, 1, false, 0, 0}, + {{0, 0, 0}, 0, 1, false, false, 0, 0}, /* DBG_GRC_PARAM_NUM_LCIDS */ - {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, MAX_LCIDS, - MAX_LCIDS}, + {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, false, + MAX_LCIDS, MAX_LCIDS}, /* DBG_GRC_PARAM_NUM_LTIDS */ - {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, MAX_LTIDS, - MAX_LTIDS}, + {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, false, + MAX_LTIDS, MAX_LTIDS}, /* DBG_GRC_PARAM_EXCLUDE_ALL */ - {{0, 0, 0}, 0, 1, true, 0, 0}, + {{0, 0, 0}, 0, 1, true, false, 0, 0}, /* DBG_GRC_PARAM_CRASH */ - {{0, 0, 0}, 0, 1, true, 0, 0}, + {{0, 0, 0}, 0, 1, true, false, 0, 0}, /* DBG_GRC_PARAM_PARITY_SAFE */ - {{0, 0, 0}, 0, 1, false, 1, 0}, + {{0, 0, 0}, 0, 1, false, false, 1, 0}, /* DBG_GRC_PARAM_DUMP_CM */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_DUMP_PHY */ - {{1, 1, 1}, 0, 1, false, 0, 1}, + {{1, 1, 1}, 0, 1, false, false, 0, 1}, /* DBG_GRC_PARAM_NO_MCP */ - {{0, 0, 0}, 0, 1, false, 0, 0}, + {{0, 0, 0}, 0, 1, false, false, 0, 0}, /* DBG_GRC_PARAM_NO_FW_VER */ - {{0, 0, 0}, 0, 1, false, 0, 0} + {{0, 0, 0}, 0, 1, false, false, 0, 0} }; static struct rss_mem_defs s_rss_mem_defs[] = { @@ -4731,8 +4732,13 @@ static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, offset += qed_dump_section_hdr(dump_buf + offset, dump, "mcp_trace_meta", 1); - /* Read trace meta info (trace_meta_size_bytes is dword-aligned) */ - if (mcp_access) { + /* If MCP Trace meta size parameter was set, use it. + * Otherwise, read trace meta. + * trace_meta_size_bytes is dword-aligned. + */ + trace_meta_size_bytes = + qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_MCP_TRACE_META_SIZE); + if ((!trace_meta_size_bytes || dump) && mcp_access) { status = qed_mcp_trace_get_meta_info(p_hwfn, p_ptt, trace_data_size_bytes, @@ -5063,8 +5069,9 @@ void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn) u32 i; for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) - dev_data->grc.param_val[i] = - s_grc_param_defs[i].default_val[dev_data->chip_id]; + if (!s_grc_param_defs[i].is_persistent) + dev_data->grc.param_val[i] = + s_grc_param_defs[i].default_val[dev_data->chip_id]; } enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, @@ -6071,10 +6078,14 @@ static const struct igu_fifo_addr_data s_igu_fifo_addr_data[] = { /******************************** Variables **********************************/ -/* MCP Trace meta data - used in case the dump doesn't contain the meta data - * (e.g. due to no NVRAM access). +/* MCP Trace meta data array - used in case the dump doesn't contain the + * meta data (e.g. due to no NVRAM access). */ -static struct user_dbg_array s_mcp_trace_meta = { NULL, 0 }; +static struct user_dbg_array s_mcp_trace_meta_arr = { NULL, 0 }; + +/* Parsed MCP Trace meta data info, based on MCP trace meta array */ +static struct mcp_trace_meta s_mcp_trace_meta; +static bool s_mcp_trace_meta_valid; /* Temporary buffer, used for print size calculations */ static char s_temp_buf[MAX_MSG_LEN]; @@ -6104,6 +6115,9 @@ static u32 qed_read_from_cyclic_buf(void *buf, val_ptr = (u8 *)&val; + /* Assume running on a LITTLE ENDIAN and the buffer is network order + * (BIG ENDIAN), as high order bytes are placed in lower memory address. + */ for (i = 0; i < num_bytes_to_read; i++) { val_ptr[i] = bytes_buf[*offset]; *offset = qed_cyclic_add(*offset, 1, buf_size); @@ -6185,7 +6199,7 @@ static u32 qed_read_param(u32 *dump_buf, offset += 4; } - return offset / 4; + return (u32)offset / 4; } /* Reads a section header from the specified buffer. @@ -6503,6 +6517,8 @@ static void qed_mcp_trace_free_meta(struct qed_hwfn *p_hwfn, { u32 i; + s_mcp_trace_meta_valid = false; + /* Release modules */ if (meta->modules) { for (i = 0; i < meta->modules_num; i++) @@ -6529,6 +6545,10 @@ static enum dbg_status qed_mcp_trace_alloc_meta(struct qed_hwfn *p_hwfn, u8 *meta_buf_bytes = (u8 *)meta_buf; u32 offset = 0, signature, i; + /* Free the previous meta before loading a new one. */ + if (s_mcp_trace_meta_valid) + qed_mcp_trace_free_meta(p_hwfn, meta); + memset(meta, 0, sizeof(*meta)); /* Read first signature */ @@ -6594,31 +6614,153 @@ static enum dbg_status qed_mcp_trace_alloc_meta(struct qed_hwfn *p_hwfn, format_len, format_ptr->format_str); } + s_mcp_trace_meta_valid = true; return DBG_STATUS_OK; } +/* Parses an MCP trace buffer. If result_buf is not NULL, the MCP Trace results + * are printed to it. The parsing status is returned. + * Arguments: + * trace_buf - MCP trace cyclic buffer + * trace_buf_size - MCP trace cyclic buffer size in bytes + * data_offset - offset in bytes of the data to parse in the MCP trace cyclic + * buffer. + * data_size - size in bytes of data to parse. + * parsed_buf - destination buffer for parsed data. + * parsed_bytes - size of parsed data in bytes. + */ +static enum dbg_status qed_parse_mcp_trace_buf(u8 *trace_buf, + u32 trace_buf_size, + u32 data_offset, + u32 data_size, + char *parsed_buf, + u32 *parsed_bytes) +{ + u32 param_mask, param_shift; + enum dbg_status status; + + *parsed_bytes = 0; + + if (!s_mcp_trace_meta_valid) + return DBG_STATUS_MCP_TRACE_BAD_DATA; + + status = DBG_STATUS_OK; + + while (data_size) { + struct mcp_trace_format *format_ptr; + u8 format_level, format_module; + u32 params[3] = { 0, 0, 0 }; + u32 header, format_idx, i; + + if (data_size < MFW_TRACE_ENTRY_SIZE) + return DBG_STATUS_MCP_TRACE_BAD_DATA; + + header = qed_read_from_cyclic_buf(trace_buf, + &data_offset, + trace_buf_size, + MFW_TRACE_ENTRY_SIZE); + data_size -= MFW_TRACE_ENTRY_SIZE; + format_idx = header & MFW_TRACE_EVENTID_MASK; + + /* Skip message if its index doesn't exist in the meta data */ + if (format_idx > s_mcp_trace_meta.formats_num) { + u8 format_size = + (u8)((header & MFW_TRACE_PRM_SIZE_MASK) >> + MFW_TRACE_PRM_SIZE_SHIFT); + + if (data_size < format_size) + return DBG_STATUS_MCP_TRACE_BAD_DATA; + + data_offset = qed_cyclic_add(data_offset, + format_size, + trace_buf_size); + data_size -= format_size; + continue; + } + + format_ptr = &s_mcp_trace_meta.formats[format_idx]; + + for (i = 0, + param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK, + param_shift = MCP_TRACE_FORMAT_P1_SIZE_SHIFT; + i < MCP_TRACE_FORMAT_MAX_PARAMS; + i++, + param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH, + param_shift += MCP_TRACE_FORMAT_PARAM_WIDTH) { + /* Extract param size (0..3) */ + u8 param_size = (u8)((format_ptr->data & param_mask) >> + param_shift); + + /* If the param size is zero, there are no other + * parameters. + */ + if (!param_size) + break; + + /* Size is encoded using 2 bits, where 3 is used to + * encode 4. + */ + if (param_size == 3) + param_size = 4; + + if (data_size < param_size) + return DBG_STATUS_MCP_TRACE_BAD_DATA; + + params[i] = qed_read_from_cyclic_buf(trace_buf, + &data_offset, + trace_buf_size, + param_size); + data_size -= param_size; + } + + format_level = (u8)((format_ptr->data & + MCP_TRACE_FORMAT_LEVEL_MASK) >> + MCP_TRACE_FORMAT_LEVEL_SHIFT); + format_module = (u8)((format_ptr->data & + MCP_TRACE_FORMAT_MODULE_MASK) >> + MCP_TRACE_FORMAT_MODULE_SHIFT); + if (format_level >= ARRAY_SIZE(s_mcp_trace_level_str)) + return DBG_STATUS_MCP_TRACE_BAD_DATA; + + /* Print current message to results buffer */ + *parsed_bytes += + sprintf(qed_get_buf_ptr(parsed_buf, *parsed_bytes), + "%s %-8s: ", + s_mcp_trace_level_str[format_level], + s_mcp_trace_meta.modules[format_module]); + *parsed_bytes += + sprintf(qed_get_buf_ptr(parsed_buf, *parsed_bytes), + format_ptr->format_str, + params[0], params[1], params[2]); + } + + /* Add string NULL terminator */ + (*parsed_bytes)++; + + return status; +} + /* Parses an MCP Trace dump buffer. * If result_buf is not NULL, the MCP Trace results are printed to it. * In any case, the required results buffer size is assigned to - * parsed_results_bytes. + * parsed_bytes. * The parsing status is returned. */ static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn, u32 *dump_buf, - char *results_buf, - u32 *parsed_results_bytes) + char *parsed_buf, + u32 *parsed_bytes) { - u32 end_offset, bytes_left, trace_data_dwords, trace_meta_dwords; - u32 param_mask, param_shift, param_num_val, num_section_params; const char *section_name, *param_name, *param_str_val; - u32 offset, results_offset = 0; - struct mcp_trace_meta meta; + u32 data_size, trace_data_dwords, trace_meta_dwords; + u32 offset, results_offset, parsed_buf_bytes; + u32 param_num_val, num_section_params; struct mcp_trace *trace; enum dbg_status status; const u32 *meta_buf; u8 *trace_buf; - *parsed_results_bytes = 0; + *parsed_bytes = 0; /* Read global_params section */ dump_buf += qed_read_section_hdr(dump_buf, @@ -6629,7 +6771,7 @@ static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn, /* Print global params */ dump_buf += qed_print_section_params(dump_buf, num_section_params, - results_buf, &results_offset); + parsed_buf, &results_offset); /* Read trace_data section */ dump_buf += qed_read_section_hdr(dump_buf, @@ -6646,8 +6788,7 @@ static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn, trace = (struct mcp_trace *)dump_buf; trace_buf = (u8 *)dump_buf + sizeof(*trace); offset = trace->trace_oldest; - end_offset = trace->trace_prod; - bytes_left = qed_cyclic_sub(end_offset, offset, trace->size); + data_size = qed_cyclic_sub(trace->trace_prod, offset, trace->size); dump_buf += trace_data_dwords; /* Read meta_data section */ @@ -6664,126 +6805,33 @@ static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn, /* Choose meta data buffer */ if (!trace_meta_dwords) { /* Dump doesn't include meta data */ - if (!s_mcp_trace_meta.ptr) + if (!s_mcp_trace_meta_arr.ptr) return DBG_STATUS_MCP_TRACE_NO_META; - meta_buf = s_mcp_trace_meta.ptr; + meta_buf = s_mcp_trace_meta_arr.ptr; } else { /* Dump includes meta data */ meta_buf = dump_buf; } /* Allocate meta data memory */ - status = qed_mcp_trace_alloc_meta(p_hwfn, meta_buf, &meta); + status = qed_mcp_trace_alloc_meta(p_hwfn, meta_buf, &s_mcp_trace_meta); if (status != DBG_STATUS_OK) - goto free_mem; - - /* Ignore the level and modules masks - just print everything that is - * already in the buffer. - */ - while (bytes_left) { - struct mcp_trace_format *format_ptr; - u8 format_level, format_module; - u32 params[3] = { 0, 0, 0 }; - u32 header, format_idx, i; - - if (bytes_left < MFW_TRACE_ENTRY_SIZE) { - status = DBG_STATUS_MCP_TRACE_BAD_DATA; - goto free_mem; - } - - header = qed_read_from_cyclic_buf(trace_buf, - &offset, - trace->size, - MFW_TRACE_ENTRY_SIZE); - bytes_left -= MFW_TRACE_ENTRY_SIZE; - format_idx = header & MFW_TRACE_EVENTID_MASK; - - /* Skip message if its index doesn't exist in the meta data */ - if (format_idx > meta.formats_num) { - u8 format_size = - (u8)((header & - MFW_TRACE_PRM_SIZE_MASK) >> - MFW_TRACE_PRM_SIZE_SHIFT); - - if (bytes_left < format_size) { - status = DBG_STATUS_MCP_TRACE_BAD_DATA; - goto free_mem; - } - - offset = qed_cyclic_add(offset, - format_size, trace->size); - bytes_left -= format_size; - continue; - } - - format_ptr = &meta.formats[format_idx]; - - for (i = 0, - param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK, param_shift = - MCP_TRACE_FORMAT_P1_SIZE_SHIFT; - i < MCP_TRACE_FORMAT_MAX_PARAMS; - i++, param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH, - param_shift += MCP_TRACE_FORMAT_PARAM_WIDTH) { - /* Extract param size (0..3) */ - u8 param_size = - (u8)((format_ptr->data & - param_mask) >> param_shift); - - /* If the param size is zero, there are no other - * parameters. - */ - if (!param_size) - break; - - /* Size is encoded using 2 bits, where 3 is used to - * encode 4. - */ - if (param_size == 3) - param_size = 4; - - if (bytes_left < param_size) { - status = DBG_STATUS_MCP_TRACE_BAD_DATA; - goto free_mem; - } - - params[i] = qed_read_from_cyclic_buf(trace_buf, - &offset, - trace->size, - param_size); - - bytes_left -= param_size; - } + return status; - format_level = - (u8)((format_ptr->data & - MCP_TRACE_FORMAT_LEVEL_MASK) >> - MCP_TRACE_FORMAT_LEVEL_SHIFT); - format_module = - (u8)((format_ptr->data & - MCP_TRACE_FORMAT_MODULE_MASK) >> - MCP_TRACE_FORMAT_MODULE_SHIFT); - if (format_level >= ARRAY_SIZE(s_mcp_trace_level_str)) { - status = DBG_STATUS_MCP_TRACE_BAD_DATA; - goto free_mem; - } + status = qed_parse_mcp_trace_buf(trace_buf, + trace->size, + offset, + data_size, + parsed_buf ? + parsed_buf + results_offset : + NULL, + &parsed_buf_bytes); + if (status != DBG_STATUS_OK) + return status; - /* Print current message to results buffer */ - results_offset += - sprintf(qed_get_buf_ptr(results_buf, - results_offset), "%s %-8s: ", - s_mcp_trace_level_str[format_level], - meta.modules[format_module]); - results_offset += - sprintf(qed_get_buf_ptr(results_buf, - results_offset), - format_ptr->format_str, params[0], params[1], - params[2]); - } + *parsed_bytes = results_offset + parsed_buf_bytes; -free_mem: - *parsed_results_bytes = results_offset + 1; - qed_mcp_trace_free_meta(p_hwfn, &meta); - return status; + return DBG_STATUS_OK; } /* Parses a Reg FIFO dump buffer. @@ -7291,8 +7339,8 @@ enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size) { - s_mcp_trace_meta.ptr = data; - s_mcp_trace_meta.size_in_dwords = size; + s_mcp_trace_meta_arr.ptr = data; + s_mcp_trace_meta_arr.size_in_dwords = size; } enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, @@ -7316,6 +7364,19 @@ enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, results_buf, &parsed_buf_size); } +enum dbg_status qed_print_mcp_trace_line(u8 *dump_buf, + u32 num_dumped_bytes, + char *results_buf) +{ + u32 parsed_bytes; + + return qed_parse_mcp_trace_buf(dump_buf, + num_dumped_bytes, + 0, + num_dumped_bytes, + results_buf, &parsed_bytes); +} + enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, u32 *dump_buf, u32 num_dumped_dwords, @@ -7891,6 +7952,7 @@ int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) } } + qed_set_debug_engine(cdev, org_engine); /* mcp_trace */ rc = qed_dbg_mcp_trace(cdev, (u8 *)buffer + offset + REGDUMP_HEADER_SIZE, &feature_size); @@ -7903,8 +7965,6 @@ int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) DP_ERR(cdev, "qed_dbg_mcp_trace failed. rc = %d\n", rc); } - qed_set_debug_engine(cdev, org_engine); - return 0; } @@ -7929,9 +7989,10 @@ int qed_dbg_all_data_size(struct qed_dev *cdev) REGDUMP_HEADER_SIZE + qed_dbg_fw_asserts_size(cdev); } + qed_set_debug_engine(cdev, org_engine); + /* Engine common */ regs_len += REGDUMP_HEADER_SIZE + qed_dbg_mcp_trace_size(cdev); - qed_set_debug_engine(cdev, org_engine); return regs_len; } diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c index cdb3eec0f68c..de5527c0c1c7 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dev.c +++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c @@ -407,6 +407,7 @@ static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); /* init pq params */ + qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + qm_info->num_vports; qm_info->qm_pq_params[pq_idx].tc_id = tc; @@ -727,8 +728,9 @@ static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) pq = &(qm_info->qm_pq_params[i]); DP_VERBOSE(p_hwfn, NETIF_MSG_HW, - "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", + "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", qm_info->start_pq + i, + pq->port_id, pq->vport_id, pq->tc_id, pq->wrr_group, pq->rl_valid); } diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h b/drivers/net/ethernet/qlogic/qed/qed_hsi.h index de873d770575..2c6a679166e1 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h +++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h @@ -612,7 +612,7 @@ struct e4_xstorm_core_conn_ag_ctx { __le16 reserved16; __le16 tx_bd_cons; __le16 tx_bd_or_spq_prod; - __le16 word5; + __le16 updated_qm_pq_id; __le16 conn_dpi; u8 byte3; u8 byte4; @@ -1005,7 +1005,9 @@ enum fw_flow_ctrl_mode { enum gft_profile_type { GFT_PROFILE_TYPE_4_TUPLE, GFT_PROFILE_TYPE_L4_DST_PORT, - GFT_PROFILE_TYPE_IP_DST_PORT, + GFT_PROFILE_TYPE_IP_DST_ADDR, + GFT_PROFILE_TYPE_IP_SRC_ADDR, + GFT_PROFILE_TYPE_TUNNEL_TYPE, MAX_GFT_PROFILE_TYPE }; @@ -1133,7 +1135,7 @@ struct protocol_dcb_data { u8 dcb_priority; u8 dcb_tc; u8 dscp_val; - u8 reserved0; + u8 dcb_dont_add_vlan0; }; /* Update tunnel configuration */ @@ -1932,7 +1934,7 @@ enum bin_dbg_buffer_type { /* Attention bit mapping */ struct dbg_attn_bit_mapping { - __le16 data; + u16 data; #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 @@ -1941,11 +1943,12 @@ struct dbg_attn_bit_mapping { /* Attention block per-type data */ struct dbg_attn_block_type_data { - __le16 names_offset; - __le16 reserved1; + u16 names_offset; + u16 reserved1; u8 num_regs; u8 reserved2; - __le16 regs_offset; + u16 regs_offset; + }; /* Block attentions */ @@ -1955,15 +1958,15 @@ struct dbg_attn_block { /* Attention register result */ struct dbg_attn_reg_result { - __le32 data; + u32 data; #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 - __le16 block_attn_offset; - __le16 reserved; - __le32 sts_val; - __le32 mask_val; + u16 block_attn_offset; + u16 reserved; + u32 sts_val; + u32 mask_val; }; /* Attention block result */ @@ -1974,13 +1977,13 @@ struct dbg_attn_block_result { #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 - __le16 names_offset; + u16 names_offset; struct dbg_attn_reg_result reg_results[15]; }; /* Mode header */ struct dbg_mode_hdr { - __le16 data; + u16 data; #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF @@ -1990,14 +1993,14 @@ struct dbg_mode_hdr { /* Attention register */ struct dbg_attn_reg { struct dbg_mode_hdr mode; - __le16 block_attn_offset; - __le32 data; + u16 block_attn_offset; + u32 data; #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 - __le32 sts_clr_address; - __le32 mask_address; + u32 sts_clr_address; + u32 mask_address; }; /* Attention types */ @@ -2011,14 +2014,14 @@ enum dbg_attn_type { struct dbg_bus_block { u8 num_of_lines; u8 has_latency_events; - __le16 lines_offset; + u16 lines_offset; }; /* Debug Bus block user data */ struct dbg_bus_block_user_data { u8 num_of_lines; u8 has_latency_events; - __le16 names_offset; + u16 names_offset; }; /* Block Debug line data */ @@ -2042,12 +2045,12 @@ struct dbg_dump_cond_hdr { /* Memory data for registers dump */ struct dbg_dump_mem { - __le32 dword0; + u32 dword0; #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 - __le32 dword1; + u32 dword1; #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF #define DBG_DUMP_MEM_LENGTH_SHIFT 0 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 @@ -2058,7 +2061,7 @@ struct dbg_dump_mem { /* Register data for registers dump */ struct dbg_dump_reg { - __le32 data; + u32 data; #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF #define DBG_DUMP_REG_ADDRESS_SHIFT 0 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 @@ -2069,7 +2072,7 @@ struct dbg_dump_reg { /* Split header for registers dump */ struct dbg_dump_split_hdr { - __le32 hdr; + u32 hdr; #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF @@ -2079,33 +2082,33 @@ struct dbg_dump_split_hdr { /* Condition header for idle check */ struct dbg_idle_chk_cond_hdr { struct dbg_mode_hdr mode; /* Mode header */ - __le16 data_size; /* size in dwords of the data following this header */ + u16 data_size; /* size in dwords of the data following this header */ }; /* Idle Check condition register */ struct dbg_idle_chk_cond_reg { - __le32 data; + u32 data; #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 - __le16 num_entries; + u16 num_entries; u8 entry_size; u8 start_entry; }; /* Idle Check info register */ struct dbg_idle_chk_info_reg { - __le32 data; + u32 data; #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 - __le16 size; /* register size in dwords */ + u16 size; /* register size in dwords */ struct dbg_mode_hdr mode; /* Mode header */ }; @@ -2117,8 +2120,8 @@ union dbg_idle_chk_reg { /* Idle Check result header */ struct dbg_idle_chk_result_hdr { - __le16 rule_id; /* Failing rule index */ - __le16 mem_entry_id; /* Failing memory entry index */ + u16 rule_id; /* Failing rule index */ + u16 mem_entry_id; /* Failing memory entry index */ u8 num_dumped_cond_regs; /* number of dumped condition registers */ u8 num_dumped_info_regs; /* number of dumped condition registers */ u8 severity; /* from dbg_idle_chk_severity_types enum */ @@ -2133,29 +2136,29 @@ struct dbg_idle_chk_result_reg_hdr { #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 u8 start_entry; /* index of the first checked entry */ - __le16 size; /* register size in dwords */ + u16 size; /* register size in dwords */ }; /* Idle Check rule */ struct dbg_idle_chk_rule { - __le16 rule_id; /* Idle Check rule ID */ + u16 rule_id; /* Idle Check rule ID */ u8 severity; /* value from dbg_idle_chk_severity_types enum */ u8 cond_id; /* Condition ID */ u8 num_cond_regs; /* number of condition registers */ u8 num_info_regs; /* number of info registers */ u8 num_imms; /* number of immediates in the condition */ u8 reserved1; - __le16 reg_offset; /* offset of this rules registers in the idle check - * register array (in dbg_idle_chk_reg units). - */ - __le16 imm_offset; /* offset of this rules immediate values in the - * immediate values array (in dwords). - */ + u16 reg_offset; /* offset of this rules registers in the idle check + * register array (in dbg_idle_chk_reg units). + */ + u16 imm_offset; /* offset of this rules immediate values in the + * immediate values array (in dwords). + */ }; /* Idle Check rule parsing data */ struct dbg_idle_chk_rule_parsing_data { - __le32 data; + u32 data; #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF @@ -2175,7 +2178,7 @@ enum dbg_idle_chk_severity_types { /* Debug Bus block data */ struct dbg_bus_block_data { - __le16 data; + u16 data; #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF @@ -2238,15 +2241,15 @@ struct dbg_bus_trigger_state_data { /* Debug Bus memory address */ struct dbg_bus_mem_addr { - __le32 lo; - __le32 hi; + u32 lo; + u32 hi; }; /* Debug Bus PCI buffer data */ struct dbg_bus_pci_buf_data { struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */ struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */ - __le32 size; /* PCI buffer size in bytes */ + u32 size; /* PCI buffer size in bytes */ }; /* Debug Bus Storm EID range filter params */ @@ -2276,15 +2279,15 @@ struct dbg_bus_storm_data { u8 eid_range_not_mask; u8 cid_filter_en; union dbg_bus_storm_eid_params eid_filter_params; - __le32 cid; + u32 cid; }; /* Debug Bus data */ struct dbg_bus_data { - __le32 app_version; + u32 app_version; u8 state; u8 hw_dwords; - __le16 hw_id_mask; + u16 hw_id_mask; u8 num_enabled_blocks; u8 num_enabled_storms; u8 target; @@ -2295,7 +2298,7 @@ struct dbg_bus_data { u8 adding_filter; u8 filter_pre_trigger; u8 filter_post_trigger; - __le16 reserved; + u16 reserved; u8 trigger_en; struct dbg_bus_trigger_state_data trigger_states[3]; u8 next_trigger_state; @@ -2391,8 +2394,8 @@ enum dbg_bus_targets { struct dbg_grc_data { u8 params_initialized; u8 reserved1; - __le16 reserved2; - __le32 param_val[48]; + u16 reserved2; + u32 param_val[48]; }; /* Debug GRC params */ @@ -2414,7 +2417,7 @@ enum dbg_grc_params { DBG_GRC_PARAM_DUMP_CAU, DBG_GRC_PARAM_DUMP_QM, DBG_GRC_PARAM_DUMP_MCP, - DBG_GRC_PARAM_RESERVED, + DBG_GRC_PARAM_MCP_TRACE_META_SIZE, DBG_GRC_PARAM_DUMP_CFC, DBG_GRC_PARAM_DUMP_IGU, DBG_GRC_PARAM_DUMP_BRB, @@ -2526,10 +2529,10 @@ enum dbg_storms { /* Idle Check data */ struct idle_chk_data { - __le32 buf_size; + u32 buf_size; u8 buf_size_set; u8 reserved1; - __le16 reserved2; + u16 reserved2; }; /* Debug Tools data (per HW function) */ @@ -2543,7 +2546,7 @@ struct dbg_tools_data { u8 platform_id; u8 initialized; u8 use_dmae; - __le32 num_regs_read; + u32 num_regs_read; }; /********************************/ @@ -2555,10 +2558,10 @@ struct dbg_tools_data { /* BRB RAM init requirements */ struct init_brb_ram_req { - __le32 guranteed_per_tc; - __le32 headroom_per_tc; - __le32 min_pkt_size; - __le32 max_ports_per_engine; + u32 guranteed_per_tc; + u32 headroom_per_tc; + u32 min_pkt_size; + u32 max_ports_per_engine; u8 num_active_tcs[MAX_NUM_PORTS]; }; @@ -2566,21 +2569,21 @@ struct init_brb_ram_req { struct init_ets_tc_req { u8 use_sp; u8 use_wfq; - __le16 weight; + u16 weight; }; /* ETS init requirements */ struct init_ets_req { - __le32 mtu; + u32 mtu; struct init_ets_tc_req tc_req[NUM_OF_TCS]; }; /* NIG LB RL init requirements */ struct init_nig_lb_rl_req { - __le16 lb_mac_rate; - __le16 lb_rate; - __le32 mtu; - __le16 tc_rate[NUM_OF_PHYS_TCS]; + u16 lb_mac_rate; + u16 lb_rate; + u32 mtu; + u16 tc_rate[NUM_OF_PHYS_TCS]; }; /* NIG TC mapping for each priority */ @@ -2598,9 +2601,9 @@ struct init_nig_pri_tc_map_req { struct init_qm_port_params { u8 active; u8 active_phys_tcs; - __le16 num_pbf_cmd_lines; - __le16 num_btb_blocks; - __le16 reserved; + u16 num_pbf_cmd_lines; + u16 num_btb_blocks; + u16 reserved; }; /* QM per-PQ init parameters */ @@ -2609,13 +2612,16 @@ struct init_qm_pq_params { u8 tc_id; u8 wrr_group; u8 rl_valid; + u8 port_id; + u8 reserved0; + u16 reserved1; }; /* QM per-vport init parameters */ struct init_qm_vport_params { - __le32 vport_rl; - __le16 vport_wfq; - __le16 first_tx_pq_id[NUM_OF_TCS]; + u32 vport_rl; + u16 vport_wfq; + u16 first_tx_pq_id[NUM_OF_TCS]; }; /**************************************/ @@ -2639,8 +2645,8 @@ enum chip_ids { }; struct fw_asserts_ram_section { - __le16 section_ram_line_offset; - __le16 section_ram_line_size; + u16 section_ram_line_offset; + u16 section_ram_line_size; u8 list_dword_offset; u8 list_element_dword_size; u8 list_num_elements; @@ -2713,8 +2719,8 @@ enum init_split_types { /* Binary buffer header */ struct bin_buffer_hdr { - __le32 offset; - __le32 length; + u32 offset; + u32 length; }; /* Binary init buffer types */ @@ -2729,7 +2735,7 @@ enum bin_init_buffer_type { /* init array header: raw */ struct init_array_raw_hdr { - __le32 data; + u32 data; #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF @@ -2738,7 +2744,7 @@ struct init_array_raw_hdr { /* init array header: standard */ struct init_array_standard_hdr { - __le32 data; + u32 data; #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF @@ -2747,7 +2753,7 @@ struct init_array_standard_hdr { /* init array header: zipped */ struct init_array_zipped_hdr { - __le32 data; + u32 data; #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF @@ -2756,7 +2762,7 @@ struct init_array_zipped_hdr { /* init array header: pattern */ struct init_array_pattern_hdr { - __le32 data; + u32 data; #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF @@ -2783,41 +2789,41 @@ enum init_array_types { /* init operation: callback */ struct init_callback_op { - __le32 op_data; + u32 op_data; #define INIT_CALLBACK_OP_OP_MASK 0xF #define INIT_CALLBACK_OP_OP_SHIFT 0 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 - __le16 callback_id; - __le16 block_id; + u16 callback_id; + u16 block_id; }; /* init operation: delay */ struct init_delay_op { - __le32 op_data; + u32 op_data; #define INIT_DELAY_OP_OP_MASK 0xF #define INIT_DELAY_OP_OP_SHIFT 0 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF #define INIT_DELAY_OP_RESERVED_SHIFT 4 - __le32 delay; + u32 delay; }; /* init operation: if_mode */ struct init_if_mode_op { - __le32 op_data; + u32 op_data; #define INIT_IF_MODE_OP_OP_MASK 0xF #define INIT_IF_MODE_OP_OP_SHIFT 0 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 - __le16 reserved2; - __le16 modes_buf_offset; + u16 reserved2; + u16 modes_buf_offset; }; /* init operation: if_phase */ struct init_if_phase_op { - __le32 op_data; + u32 op_data; #define INIT_IF_PHASE_OP_OP_MASK 0xF #define INIT_IF_PHASE_OP_OP_SHIFT 0 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 @@ -2826,7 +2832,7 @@ struct init_if_phase_op { #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 - __le32 phase_data; + u32 phase_data; #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF @@ -2845,31 +2851,31 @@ enum init_mode_ops { /* init operation: raw */ struct init_raw_op { - __le32 op_data; + u32 op_data; #define INIT_RAW_OP_OP_MASK 0xF #define INIT_RAW_OP_OP_SHIFT 0 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF #define INIT_RAW_OP_PARAM1_SHIFT 4 - __le32 param2; + u32 param2; }; /* init array params */ struct init_op_array_params { - __le16 size; - __le16 offset; + u16 size; + u16 offset; }; /* Write init operation arguments */ union init_write_args { - __le32 inline_val; - __le32 zeros_count; - __le32 array_offset; + u32 inline_val; + u32 zeros_count; + u32 array_offset; struct init_op_array_params runtime; }; /* init operation: write */ struct init_write_op { - __le32 data; + u32 data; #define INIT_WRITE_OP_OP_MASK 0xF #define INIT_WRITE_OP_OP_SHIFT 0 #define INIT_WRITE_OP_SOURCE_MASK 0x7 @@ -2885,7 +2891,7 @@ struct init_write_op { /* init operation: read */ struct init_read_op { - __le32 op_data; + u32 op_data; #define INIT_READ_OP_OP_MASK 0xF #define INIT_READ_OP_OP_SHIFT 0 #define INIT_READ_OP_POLL_TYPE_MASK 0xF @@ -2894,7 +2900,7 @@ struct init_read_op { #define INIT_READ_OP_RESERVED_SHIFT 8 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF #define INIT_READ_OP_ADDRESS_SHIFT 9 - __le32 expected_val; + u32 expected_val; }; /* Init operations union */ @@ -2939,11 +2945,11 @@ enum init_source_types { /* Internal RAM Offsets macro data */ struct iro { - __le32 base; - __le16 m1; - __le16 m2; - __le16 m3; - __le16 size; + u32 base; + u16 m1; + u16 m2; + u16 m3; + u16 size; }; /***************************** Public Functions *******************************/ @@ -3383,6 +3389,19 @@ enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, u32 num_dumped_dwords, char *results_buf); +/** + * @brief print_mcp_trace_line - Prints MCP Trace results for a single line + * + * @param dump_buf - mcp trace dump buffer, starting from the header. + * @param num_dumped_bytes - number of bytes that were dumped. + * @param results_buf - buffer for printing the mcp trace results. + * + * @return error if the parsing fails, ok otherwise. + */ +enum dbg_status qed_print_mcp_trace_line(u8 *dump_buf, + u32 num_dumped_bytes, + char *results_buf); + /** * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size * for reg_fifo results (in bytes). @@ -4005,6 +4024,9 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool eth_geneve_enable, bool ip_geneve_enable); +void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, + struct qed_ptt *p_ptt, bool enable); + /** * @brief qed_gft_disable - Disable GFT * @@ -4348,8 +4370,8 @@ static const struct iro iro_arr[51] = { {0x80, 0x8, 0x0, 0x0, 0x4}, {0x84, 0x8, 0x0, 0x0, 0x2}, {0x4c48, 0x0, 0x0, 0x0, 0x78}, - {0x3e18, 0x0, 0x0, 0x0, 0x78}, - {0x2b58, 0x0, 0x0, 0x0, 0x78}, + {0x3e38, 0x0, 0x0, 0x0, 0x78}, + {0x2b78, 0x0, 0x0, 0x0, 0x78}, {0x4c40, 0x0, 0x0, 0x0, 0x78}, {0x4998, 0x0, 0x0, 0x0, 0x78}, {0x7f50, 0x0, 0x0, 0x0, 0x78}, @@ -4364,7 +4386,7 @@ static const struct iro iro_arr[51] = { {0x4ba8, 0x80, 0x0, 0x0, 0x20}, {0x8158, 0x40, 0x0, 0x0, 0x30}, {0xe770, 0x60, 0x0, 0x0, 0x60}, - {0x2cf0, 0x80, 0x0, 0x0, 0x38}, + {0x2d10, 0x80, 0x0, 0x0, 0x38}, {0xf2b8, 0x78, 0x0, 0x0, 0x78}, {0x1f8, 0x4, 0x0, 0x0, 0x4}, {0xaf20, 0x0, 0x0, 0x0, 0xf0}, @@ -4384,10 +4406,10 @@ static const struct iro iro_arr[51] = { {0x10300, 0x18, 0x0, 0x0, 0x10}, {0xde48, 0x48, 0x0, 0x0, 0x38}, {0x10768, 0x20, 0x0, 0x0, 0x20}, - {0x2d28, 0x80, 0x0, 0x0, 0x10}, + {0x2d48, 0x80, 0x0, 0x0, 0x10}, {0x5048, 0x10, 0x0, 0x0, 0x10}, {0xc9b8, 0x30, 0x0, 0x0, 0x10}, - {0xeee0, 0x10, 0x0, 0x0, 0x10}, + {0xed90, 0x10, 0x0, 0x0, 0x10}, {0xa3a0, 0x10, 0x0, 0x0, 0x10}, {0x13108, 0x8, 0x0, 0x0, 0x8}, }; @@ -5151,7 +5173,7 @@ struct e4_xstorm_eth_conn_ag_ctx { __le16 edpm_num_bds; __le16 tx_bd_cons; __le16 tx_bd_prod; - __le16 tx_class; + __le16 updated_qm_pq_id; __le16 conn_dpi; u8 byte3; u8 byte4; @@ -5674,7 +5696,6 @@ struct eth_vport_rx_mode { #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 - __le16 reserved2[3]; }; /* Command for setting tpa parameters */ @@ -5712,7 +5733,6 @@ struct eth_vport_tx_mode { #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 - __le16 reserved2[3]; }; /* GFT filter update action type */ @@ -5805,7 +5825,8 @@ struct rx_queue_update_ramrod_data { u8 complete_cqe_flg; u8 complete_event_flg; u8 vport_id; - u8 reserved[4]; + u8 set_default_rss_queue; + u8 reserved[3]; u8 reserved1; u8 reserved2; u8 reserved3; @@ -5843,7 +5864,7 @@ struct rx_update_gft_filter_data { u8 flow_id_valid; u8 filter_action; u8 assert_on_error; - u8 reserved; + u8 inner_vlan_removal_en; }; /* Ramrod data for rx queue start ramrod */ @@ -5927,7 +5948,7 @@ struct vport_start_ramrod_data { u8 zero_placement_offset; u8 ctl_frame_mac_check_en; u8 ctl_frame_ethtype_check_en; - u8 reserved[5]; + u8 reserved[1]; }; /* Ramrod data for vport stop ramrod */ @@ -5992,6 +6013,7 @@ struct vport_update_ramrod_data { struct eth_vport_rx_mode rx_mode; struct eth_vport_tx_mode tx_mode; + __le32 reserved[3]; struct eth_vport_tpa_param tpa_param; struct vport_update_ramrod_mcast approx_mcast; struct eth_vport_rss_config rss_config; @@ -6213,7 +6235,7 @@ struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart { __le16 edpm_num_bds; __le16 tx_bd_cons; __le16 tx_bd_prod; - __le16 tx_class; + __le16 updated_qm_pq_id; __le16 conn_dpi; u8 byte3; u8 byte4; @@ -6479,7 +6501,7 @@ struct e4_xstorm_eth_hw_conn_ag_ctx { __le16 edpm_num_bds; __le16 tx_bd_cons; __le16 tx_bd_prod; - __le16 tx_class; + __le16 updated_qm_pq_id; __le16 conn_dpi; }; @@ -6703,8 +6725,8 @@ struct e4_ystorm_rdma_task_ag_ctx { #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 -#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 -#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 +#define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 +#define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 u8 flags1; #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 @@ -6759,8 +6781,8 @@ struct e4_mstorm_rdma_task_ag_ctx { #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 -#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 -#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 +#define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 +#define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 u8 flags1; #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 @@ -6814,7 +6836,7 @@ struct ustorm_rdma_task_st_ctx { struct e4_ustorm_rdma_task_ag_ctx { u8 reserved; - u8 byte1; + u8 state; __le16 icid; u8 flags0; #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF @@ -6830,8 +6852,8 @@ struct e4_ustorm_rdma_task_ag_ctx { #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 -#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 -#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 +#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3 +#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 u8 flags2; @@ -6841,8 +6863,8 @@ struct e4_ustorm_rdma_task_ag_ctx { #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 -#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 -#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 +#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1 +#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 @@ -6864,10 +6886,17 @@ struct e4_ustorm_rdma_task_ag_ctx { #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 __le32 dif_err_intervals; __le32 dif_error_1st_interval; - __le32 reg2; + __le32 sq_cons; __le32 dif_runt_value; - __le32 reg4; + __le32 sge_index; __le32 reg5; + u8 byte2; + u8 byte3; + __le16 word1; + __le16 word2; + __le16 word3; + __le32 reg6; + __le32 reg7; }; /* RDMA task context */ @@ -6970,7 +6999,9 @@ struct rdma_init_func_hdr { u8 vf_id; u8 vf_valid; u8 relaxed_ordering; - u8 reserved[2]; + __le16 first_reg_srq_id; + __le32 reg_srq_base_addr; + __le32 reserved; }; /* rdma function init ramrod data */ @@ -7077,13 +7108,23 @@ struct rdma_srq_context { /* rdma create qp requester ramrod data */ struct rdma_srq_create_ramrod_data { + u8 flags; +#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1 +#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0 +#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 +#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1 +#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F +#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2 + u8 reserved2; + __le16 xrc_domain; + __le32 xrc_srq_cq_cid; struct regpair pbl_base_addr; __le16 pages_in_srq_pbl; __le16 pd_id; struct rdma_srq_id srq_id; __le16 page_size; - __le16 reserved1; - __le32 reserved2; + __le16 reserved3; + __le32 reserved4; struct regpair producers_addr; }; @@ -7108,214 +7149,366 @@ enum rdma_tid_type { MAX_RDMA_TID_TYPE }; -struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part { +struct rdma_xrc_srq_context { + struct regpair temp[9]; +}; + +struct e4_tstorm_rdma_task_ag_ctx { + u8 byte0; + u8 byte1; + __le16 word0; + u8 flags0; +#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF +#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 + u8 flags1; +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 + u8 flags2; +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 + u8 flags3; +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 + u8 flags4; +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 +#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 + u8 byte2; + __le16 word1; + __le32 reg0; + u8 byte3; + u8 byte4; + __le16 word2; + __le16 word3; + __le16 word4; + __le32 reg1; + __le32 reg2; +}; + +struct e4_ustorm_rdma_conn_ag_ctx { + u8 reserved; + u8 byte1; + u8 flags0; +#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 +#define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1 +#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 +#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 + u8 flags1; +#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 + u8 flags2; +#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 + u8 flags3; +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 +#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 + u8 byte2; + u8 byte3; + __le16 conn_dpi; + __le16 word1; + __le32 cq_cons; + __le32 cq_se_prod; + __le32 cq_prod; + __le32 reg3; + __le16 int_timeout; + __le16 word3; +}; + +struct e4_xstorm_roce_conn_ag_ctx { u8 reserved0; u8 state; u8 flags0; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7 u8 flags1; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 u8 flags2; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6 u8 flags3; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 u8 flags4; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6 u8 flags5; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6 u8 flags6; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6 u8 flags7; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7 u8 flags8; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7 u8 flags9; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7 u8 flags10; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7 u8 flags11; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7 u8 flags12; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7 u8 flags13; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 u8 flags14; -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 -#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 +#define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4 +#define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 +#define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3 +#define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6 u8 byte2; __le16 physical_q0; __le16 word1; @@ -7333,128 +7526,93 @@ struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part { __le32 reg2; __le32 snd_nxt_psn; __le32 reg4; + __le32 reg5; + __le32 reg6; }; -struct e4_mstorm_rdma_conn_ag_ctx { - u8 byte0; - u8 byte1; - u8 flags0; -#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 -#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 - u8 flags1; -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 -#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 - __le16 word0; - __le16 word1; - __le32 reg0; - __le32 reg1; -}; - -struct e4_tstorm_rdma_conn_ag_ctx { +struct e4_tstorm_roce_conn_ag_ctx { u8 reserved0; u8 byte1; u8 flags0; -#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 +#define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6 u8 flags1; -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 -#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 -#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 +#define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2 +#define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 +#define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 u8 flags2; -#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6 u8 flags3; -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 -#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4 +#define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6 +#define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 u8 flags4; -#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 -#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 +#define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7 u8 flags5; -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 -#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 +#define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 __le32 reg0; __le32 reg1; __le32 reg2; @@ -7476,427 +7634,6 @@ struct e4_tstorm_rdma_conn_ag_ctx { __le32 reg10; }; -struct e4_tstorm_rdma_task_ag_ctx { - u8 byte0; - u8 byte1; - __le16 word0; - u8 flags0; -#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF -#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 - u8 flags1; -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 - u8 flags2; -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 - u8 flags3; -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 - u8 flags4; -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 -#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 - u8 byte2; - __le16 word1; - __le32 reg0; - u8 byte3; - u8 byte4; - __le16 word2; - __le16 word3; - __le16 word4; - __le32 reg1; - __le32 reg2; -}; - -struct e4_ustorm_rdma_conn_ag_ctx { - u8 reserved; - u8 byte1; - u8 flags0; -#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 -#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 -#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 -#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 - u8 flags1; -#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 - u8 flags2; -#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 - u8 flags3; -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 -#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 - u8 byte2; - u8 byte3; - __le16 conn_dpi; - __le16 word1; - __le32 cq_cons; - __le32 cq_se_prod; - __le32 cq_prod; - __le32 reg3; - __le16 int_timeout; - __le16 word3; -}; - -struct e4_xstorm_rdma_conn_ag_ctx { - u8 reserved0; - u8 state; - u8 flags0; -#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 - u8 flags1; -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 - u8 flags2; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 - u8 flags3; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 - u8 flags4; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 - u8 flags5; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 - u8 flags6; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 - u8 flags7; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 - u8 flags8; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 - u8 flags9; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 - u8 flags10; -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 - u8 flags11; -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 - u8 flags12; -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 - u8 flags13; -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 - u8 flags14; -#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 -#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 -#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 -#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 - u8 byte2; - __le16 physical_q0; - __le16 word1; - __le16 word2; - __le16 word3; - __le16 word4; - __le16 word5; - __le16 conn_dpi; - u8 byte3; - u8 byte4; - u8 byte5; - u8 byte6; - __le32 reg0; - __le32 reg1; - __le32 reg2; - __le32 snd_nxt_psn; - __le32 reg4; - __le32 reg5; - __le32 reg6; -}; - -struct e4_ystorm_rdma_conn_ag_ctx { - u8 byte0; - u8 byte1; - u8 flags0; -#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 -#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 - u8 flags1; -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 -#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 - u8 byte2; - u8 byte3; - __le16 word0; - __le32 reg0; - __le32 reg1; - __le16 word1; - __le16 word2; - __le16 word3; - __le16 word4; - __le32 reg2; - __le32 reg3; -}; - /* The roce storm context of Ystorm */ struct ystorm_roce_conn_st_ctx { struct regpair temp[2]; @@ -7933,15 +7670,15 @@ struct e4_roce_conn_context { struct regpair ystorm_st_padding[2]; struct pstorm_roce_conn_st_ctx pstorm_st_context; struct xstorm_roce_conn_st_ctx xstorm_st_context; - struct regpair xstorm_st_padding[2]; - struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context; - struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context; + struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context; + struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context; struct timers_context timer_context; struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context; struct tstorm_roce_conn_st_ctx tstorm_st_context; + struct regpair tstorm_st_padding[2]; struct mstorm_roce_conn_st_ctx mstorm_st_context; + struct regpair mstorm_st_padding[2]; struct ustorm_roce_conn_st_ctx ustorm_st_context; - struct regpair ustorm_st_padding[2]; }; /* roce create qp requester ramrod data */ @@ -7955,8 +7692,8 @@ struct roce_create_qp_req_ramrod_data { #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 -#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1 -#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7 +#define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 +#define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF @@ -7982,18 +7719,18 @@ struct roce_create_qp_req_ramrod_data { __le16 udp_src_port; __le32 src_gid[4]; __le32 dst_gid[4]; + __le32 cq_cid; struct regpair qp_handle_for_cqe; struct regpair qp_handle_for_async; u8 stats_counter_id; u8 reserved3[7]; - __le32 cq_cid; __le16 regular_latency_phy_queue; __le16 dpi; }; /* roce create qp responder ramrod data */ struct roce_create_qp_resp_ramrod_data { - __le16 flags; + __le32 flags; #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 @@ -8012,6 +7749,11 @@ struct roce_create_qp_resp_ramrod_data { #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 +#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 +#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 +#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF +#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17 + __le16 xrc_domain; u8 max_ird; u8 traffic_class; u8 hop_limit; @@ -8037,7 +7779,7 @@ struct roce_create_qp_resp_ramrod_data { struct regpair qp_handle_for_cqe; struct regpair qp_handle_for_async; __le16 low_latency_phy_queue; - u8 reserved2[6]; + u8 reserved2[2]; __le32 cq_cid; __le16 regular_latency_phy_queue; __le16 dpi; @@ -8237,15 +7979,279 @@ struct roce_query_qp_resp_ramrod_data { struct regpair output_params_addr; }; -/* ROCE ramrod command IDs */ -enum roce_ramrod_cmd_id { - ROCE_RAMROD_CREATE_QP = 11, - ROCE_RAMROD_MODIFY_QP, - ROCE_RAMROD_QUERY_QP, - ROCE_RAMROD_DESTROY_QP, - ROCE_RAMROD_CREATE_UD_QP, - ROCE_RAMROD_DESTROY_UD_QP, - MAX_ROCE_RAMROD_CMD_ID +/* ROCE ramrod command IDs */ +enum roce_ramrod_cmd_id { + ROCE_RAMROD_CREATE_QP = 11, + ROCE_RAMROD_MODIFY_QP, + ROCE_RAMROD_QUERY_QP, + ROCE_RAMROD_DESTROY_QP, + ROCE_RAMROD_CREATE_UD_QP, + ROCE_RAMROD_DESTROY_UD_QP, + MAX_ROCE_RAMROD_CMD_ID +}; + +struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part { + u8 reserved0; + u8 state; + u8 flags0; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 + u8 flags1; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 + u8 flags2; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 + u8 flags3; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 + u8 flags4; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 + u8 flags5; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 + u8 flags6; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 + u8 flags7; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 + u8 flags8; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 + u8 flags9; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 + u8 flags10; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 + u8 flags11; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 + u8 flags12; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 + u8 flags13; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 + u8 flags14; +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 +#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 + u8 byte2; + __le16 physical_q0; + __le16 word1; + __le16 word2; + __le16 word3; + __le16 word4; + __le16 word5; + __le16 conn_dpi; + u8 byte3; + u8 byte4; + u8 byte5; + u8 byte6; + __le32 reg0; + __le32 reg1; + __le32 reg2; + __le32 snd_nxt_psn; + __le32 reg4; +}; + +struct e4_mstorm_roce_conn_ag_ctx { + u8 byte0; + u8 byte1; + u8 flags0; +#define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 +#define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 + u8 flags1; +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 +#define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 + __le16 word0; + __le16 word1; + __le32 reg0; + __le32 reg1; }; struct e4_mstorm_roce_req_conn_ag_ctx { @@ -8341,8 +8347,8 @@ struct e4_tstorm_roce_req_conn_ag_ctx { #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 u8 flags1; -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 @@ -8350,8 +8356,8 @@ struct e4_tstorm_roce_req_conn_ag_ctx { #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 u8 flags2; -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 @@ -8365,8 +8371,8 @@ struct e4_tstorm_roce_req_conn_ag_ctx { #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 @@ -8374,8 +8380,8 @@ struct e4_tstorm_roce_req_conn_ag_ctx { u8 flags4; #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 -#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1 +#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 @@ -8421,7 +8427,7 @@ struct e4_tstorm_roce_req_conn_ag_ctx { u8 byte5; __le16 snd_sq_cons; __le16 conn_dpi; - __le16 word3; + __le16 force_comp_cons; __le32 reg9; __le32 reg10; }; @@ -8445,8 +8451,8 @@ struct e4_tstorm_roce_resp_conn_ag_ctx { #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 u8 flags1; -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 @@ -8454,8 +8460,8 @@ struct e4_tstorm_roce_resp_conn_ag_ctx { #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 u8 flags2; -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 @@ -8469,8 +8475,8 @@ struct e4_tstorm_roce_resp_conn_ag_ctx { #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 @@ -8478,8 +8484,8 @@ struct e4_tstorm_roce_resp_conn_ag_ctx { u8 flags4; #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 -#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 +#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 @@ -8724,10 +8730,10 @@ struct e4_xstorm_roce_req_conn_ag_ctx { #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 u8 flags4; -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 @@ -8774,10 +8780,10 @@ struct e4_xstorm_roce_req_conn_ag_ctx { #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 -#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1 +#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7 u8 flags9; #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 @@ -8882,9 +8888,9 @@ struct e4_xstorm_roce_req_conn_ag_ctx { __le16 sq_cmp_cons; __le16 sq_cons; __le16 sq_prod; - __le16 word5; + __le16 dif_error_first_sq_cons; __le16 conn_dpi; - u8 byte3; + u8 dif_error_sge_index; u8 byte4; u8 byte5; u8 byte6; @@ -8892,7 +8898,7 @@ struct e4_xstorm_roce_req_conn_ag_ctx { __le32 ssn; __le32 snd_una_psn; __le32 snd_nxt_psn; - __le32 reg4; + __le32 dif_error_offset; __le32 orq_cons_th; __le32 orq_cons; }; @@ -9128,6 +9134,50 @@ struct e4_xstorm_roce_resp_conn_ag_ctx { __le32 msn_and_syndrome; }; +struct e4_ystorm_roce_conn_ag_ctx { + u8 byte0; + u8 byte1; + u8 flags0; +#define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 +#define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 + u8 flags1; +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 +#define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 + u8 byte2; + u8 byte3; + __le16 word0; + __le32 reg0; + __le32 reg1; + __le16 word1; + __le16 word2; + __le16 word3; + __le16 word4; + __le32 reg2; + __le32 reg3; +}; + struct e4_ystorm_roce_req_conn_ag_ctx { u8 byte0; u8 byte1; @@ -9236,7 +9286,7 @@ struct pstorm_iwarp_conn_st_ctx { /* The iwarp storm context of Xstorm */ struct xstorm_iwarp_conn_st_ctx { - __le32 reserved[44]; + __le32 reserved[48]; }; struct e4_xstorm_iwarp_conn_ag_ctx { @@ -9377,8 +9427,8 @@ struct e4_xstorm_iwarp_conn_ag_ctx { #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 -#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 -#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 +#define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1 +#define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 @@ -9447,8 +9497,8 @@ struct e4_xstorm_iwarp_conn_ag_ctx { #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 -#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 -#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 +#define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3 +#define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6 u8 byte2; __le16 physical_q0; __le16 physical_q1; @@ -9466,7 +9516,7 @@ struct e4_xstorm_iwarp_conn_ag_ctx { __le32 reg2; __le32 more_to_send_seq; __le32 reg4; - __le32 rewinded_snd_max; + __le32 rewinded_snd_max_or_term_opcode; __le32 rd_msn; __le16 irq_prod_via_msdm; __le16 irq_cons; @@ -9476,8 +9526,8 @@ struct e4_xstorm_iwarp_conn_ag_ctx { __le32 orq_cons; __le32 orq_cons_th; u8 byte7; - u8 max_ord; u8 wqe_data_pad_bytes; + u8 max_ord; u8 former_hq_prod; u8 irq_prod_via_msem; u8 byte12; @@ -9506,8 +9556,8 @@ struct e4_tstorm_iwarp_conn_ag_ctx { #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 -#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 -#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 +#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1 +#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 @@ -9622,7 +9672,6 @@ struct e4_iwarp_conn_context { struct pstorm_iwarp_conn_st_ctx pstorm_st_context; struct regpair pstorm_st_padding[2]; struct xstorm_iwarp_conn_st_ctx xstorm_st_context; - struct regpair xstorm_st_padding[2]; struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context; struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context; struct timers_context timer_context; @@ -9648,8 +9697,10 @@ struct iwarp_create_qp_ramrod_data { #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 -#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3 -#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6 +#define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1 +#define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6 +#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1 +#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7 u8 reserved1; __le16 pd; __le16 sq_num_pages; @@ -9698,6 +9749,7 @@ enum iwarp_eqe_sync_opcode { IWARP_EVENT_TYPE_QUERY_QP, IWARP_EVENT_TYPE_MODIFY_QP, IWARP_EVENT_TYPE_DESTROY_QP, + IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD, MAX_IWARP_EQE_SYNC_OPCODE }; @@ -9722,6 +9774,8 @@ enum iwarp_fw_return_code { IWARP_EXCEPTION_DETECTED_LLP_RESET, IWARP_EXCEPTION_DETECTED_IRQ_FULL, IWARP_EXCEPTION_DETECTED_RQ_EMPTY, + IWARP_EXCEPTION_DETECTED_SRQ_EMPTY, + IWARP_EXCEPTION_DETECTED_SRQ_LIMIT, IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT, IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR, IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW, @@ -9766,10 +9820,13 @@ struct iwarp_modify_qp_ramrod_data { #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 -#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF -#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5 - __le32 reserved3[3]; - __le32 reserved4[8]; +#define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 +#define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5 +#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF +#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6 + __le16 physical_q0; + __le16 physical_q1; + __le32 reserved1[10]; }; /* MPA params for Enhanced mode */ @@ -9853,6 +9910,7 @@ enum iwarp_ramrod_cmd_id { IWARP_RAMROD_CMD_ID_QUERY_QP, IWARP_RAMROD_CMD_ID_MODIFY_QP, IWARP_RAMROD_CMD_ID_DESTROY_QP, + IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD, MAX_IWARP_RAMROD_CMD_ID }; @@ -11205,7 +11263,7 @@ struct e4_tstorm_iscsi_conn_ag_ctx { #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 __le32 reg0; __le32 reg1; - __le32 reg2; + __le32 rx_tcp_checksum_err_cnt; __le32 reg3; __le32 reg4; __le32 reg5; diff --git a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c index 18fb5062a83d..1365da7c8900 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c +++ b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c @@ -467,12 +467,11 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn, u16 *p_first_tx_pq_id; ext_voq = qed_get_ext_voq(p_hwfn, - p_params->port_id, + pq_params[i].port_id, tc_id, p_params->max_phys_tcs_per_port); is_vf_pq = (i >= p_params->num_pf_pqs); - rl_valid = pq_params[i].rl_valid && - pq_params[i].vport_id < max_qm_global_rls; + rl_valid = pq_params[i].rl_valid > 0; /* Update first Tx PQ of VPORT/TC */ vport_id_in_pf = pq_params[i].vport_id - p_params->start_vport; @@ -494,10 +493,11 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn, } /* Check RL ID */ - if (pq_params[i].rl_valid && pq_params[i].vport_id >= - max_qm_global_rls) + if (rl_valid && pq_params[i].vport_id >= max_qm_global_rls) { DP_NOTICE(p_hwfn, "Invalid VPORT ID for rate limiter configuration\n"); + rl_valid = false; + } /* Prepare PQ map entry */ QM_INIT_TX_PQ_MAP(p_hwfn, @@ -528,7 +528,7 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn, pq_info = PQ_INFO_ELEMENT(*p_first_tx_pq_id, p_params->pf_id, tc_id, - p_params->port_id, + pq_params[i].port_id, rl_valid ? 1 : 0, rl_valid ? pq_params[i].vport_id : 0); @@ -603,6 +603,7 @@ static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn, * Return -1 on error. */ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn, + struct qed_qm_pf_rt_init_params *p_params) { u16 num_tx_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs; @@ -619,7 +620,7 @@ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn, for (i = 0; i < num_tx_pqs; i++) { ext_voq = qed_get_ext_voq(p_hwfn, - p_params->port_id, + pq_params[i].port_id, pq_params[i].tc_id, p_params->max_phys_tcs_per_port); crd_reg_offset = @@ -1020,7 +1021,8 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, *__p_var = (*__p_var & ~BIT(__offset)) | \ ((enable) ? BIT(__offset) : 0); \ } while (0) -#define PRS_ETH_TUNN_FIC_FORMAT -188897008 +#define PRS_ETH_TUNN_OUTPUT_FORMAT -188897008 +#define PRS_ETH_OUTPUT_FORMAT -46832 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 dest_port) @@ -1046,11 +1048,15 @@ void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, shift = PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT; SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable); qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) - qed_wr(p_hwfn, - p_ptt, - PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { + reg_val = + qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); + } /* Update NIG register */ reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE); @@ -1077,11 +1083,15 @@ void qed_set_gre_enable(struct qed_hwfn *p_hwfn, shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT; SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable); qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) - qed_wr(p_hwfn, - p_ptt, - PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { + reg_val = + qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); + } /* Update NIG register */ reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE); @@ -1126,11 +1136,15 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT; SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_geneve_enable); qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); - if (reg_val) - qed_wr(p_hwfn, - p_ptt, - PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, - (u32)PRS_ETH_TUNN_FIC_FORMAT); + if (reg_val) { + reg_val = + qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); + + /* Update output only if tunnel blocks not included. */ + if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) + qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); + } /* Update NIG register */ qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE, @@ -1152,6 +1166,38 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, ip_geneve_enable ? 1 : 0); } +#define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET 4 +#define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT -927094512 + +void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, + struct qed_ptt *p_ptt, bool enable) +{ + u32 reg_val, cfg_mask; + + /* read PRS config register */ + reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO); + + /* set VXLAN_NO_L2_ENABLE mask */ + cfg_mask = BIT(PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET); + + if (enable) { + /* set VXLAN_NO_L2_ENABLE flag */ + reg_val |= cfg_mask; + + /* update PRS FIC register */ + qed_wr(p_hwfn, + p_ptt, + PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, + (u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT); + } else { + /* clear VXLAN_NO_L2_ENABLE flag */ + reg_val &= ~cfg_mask; + } + + /* write PRS config register */ + qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val); +} + #define T_ETH_PACKET_ACTION_GFT_EVENTID 23 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272 #define T_ETH_PACKET_MATCH_RFS_EVENTID 25 @@ -1268,6 +1314,10 @@ void qed_gft_config(struct qed_hwfn *p_hwfn, ram_line_lo = 0; ram_line_hi = 0; + /* Tunnel type */ + SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1); + SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1); + if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) { SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1); SET_FIELD(ram_line_hi, GFT_RAM_LINE_SRC_IP, 1); @@ -1279,9 +1329,14 @@ void qed_gft_config(struct qed_hwfn *p_hwfn, SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1); SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1); SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1); - } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_PORT) { + } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_ADDR) { SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1); SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1); + } else if (profile_type == GFT_PROFILE_TYPE_IP_SRC_ADDR) { + SET_FIELD(ram_line_hi, GFT_RAM_LINE_SRC_IP, 1); + SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1); + } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) { + SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1); } qed_wr(p_hwfn, diff --git a/drivers/net/ethernet/qlogic/qed/qed_iwarp.c b/drivers/net/ethernet/qlogic/qed/qed_iwarp.c index 69051e98aff9..2a2b1018ed1d 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_iwarp.c +++ b/drivers/net/ethernet/qlogic/qed/qed_iwarp.c @@ -2375,13 +2375,6 @@ qed_iwarp_ll2_comp_syn_pkt(void *cxt, struct qed_ll2_comp_rx_data *data) memset(&tx_pkt, 0, sizeof(tx_pkt)); tx_pkt.num_of_bds = 1; - tx_pkt.vlan = data->vlan; - - if (GET_FIELD(data->parse_flags, - PARSING_AND_ERR_FLAGS_TAG8021QEXIST)) - SET_FIELD(tx_pkt.bd_flags, - CORE_TX_BD_DATA_VLAN_INSERTION, 1); - tx_pkt.l4_hdr_offset_w = (data->length.packet_length) >> 2; tx_pkt.tx_dest = QED_LL2_TX_DEST_LB; tx_pkt.first_frag = buf->data_phys_addr + diff --git a/drivers/net/ethernet/qlogic/qed/qed_l2.c b/drivers/net/ethernet/qlogic/qed/qed_l2.c index 893ef08a4b39..e874504e8b28 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_l2.c +++ b/drivers/net/ethernet/qlogic/qed/qed_l2.c @@ -1974,7 +1974,7 @@ qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode) if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE) return GFT_PROFILE_TYPE_4_TUPLE; if (mode == QED_FILTER_CONFIG_MODE_IP_DEST) - return GFT_PROFILE_TYPE_IP_DST_PORT; + return GFT_PROFILE_TYPE_IP_DST_ADDR; return GFT_PROFILE_TYPE_L4_DST_PORT; } diff --git a/drivers/net/ethernet/qlogic/qed/qed_ll2.c b/drivers/net/ethernet/qlogic/qed/qed_ll2.c index c4f14fdc4e77..74fc626b1ec1 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_ll2.c +++ b/drivers/net/ethernet/qlogic/qed/qed_ll2.c @@ -591,16 +591,6 @@ static void qed_ll2_rxq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle) } } -static u8 qed_ll2_convert_rx_parse_to_tx_flags(u16 parse_flags) -{ - u8 bd_flags = 0; - - if (GET_FIELD(parse_flags, PARSING_AND_ERR_FLAGS_TAG8021QEXIST)) - SET_FIELD(bd_flags, CORE_TX_BD_DATA_VLAN_INSERTION, 1); - - return bd_flags; -} - static int qed_ll2_lb_rxq_handler(struct qed_hwfn *p_hwfn, struct qed_ll2_info *p_ll2_conn) { @@ -744,7 +734,6 @@ qed_ooo_submit_tx_buffers(struct qed_hwfn *p_hwfn, struct qed_ooo_buffer *p_buffer; u16 l4_hdr_offset_w; dma_addr_t first_frag; - u16 parse_flags; u8 bd_flags; int rc; @@ -756,8 +745,6 @@ qed_ooo_submit_tx_buffers(struct qed_hwfn *p_hwfn, first_frag = p_buffer->rx_buffer_phys_addr + p_buffer->placement_offset; - parse_flags = p_buffer->parse_flags; - bd_flags = qed_ll2_convert_rx_parse_to_tx_flags(parse_flags); SET_FIELD(bd_flags, CORE_TX_BD_DATA_FORCE_VLAN_MODE, 1); SET_FIELD(bd_flags, CORE_TX_BD_DATA_L4_PROTOCOL, 1); diff --git a/include/linux/qed/common_hsi.h b/include/linux/qed/common_hsi.h index 2b3b350e07b7..13c8ab171437 100644 --- a/include/linux/qed/common_hsi.h +++ b/include/linux/qed/common_hsi.h @@ -110,7 +110,7 @@ #define FW_MAJOR_VERSION 8 #define FW_MINOR_VERSION 33 -#define FW_REVISION_VERSION 1 +#define FW_REVISION_VERSION 11 #define FW_ENGINEERING_VERSION 0 /***********************/ diff --git a/include/linux/qed/eth_common.h b/include/linux/qed/eth_common.h index 9db02856623b..d9416ad5ef59 100644 --- a/include/linux/qed/eth_common.h +++ b/include/linux/qed/eth_common.h @@ -105,7 +105,7 @@ #define ETH_CTL_FRAME_ETH_TYPE_NUM 4 /* GFS constants */ -#define ETH_GFT_TRASH_CAN_VPORT 0x1FF +#define ETH_GFT_TRASHCAN_VPORT 0x1FF /* GFT drop flow vport number */ /* Destination port mode */ enum dest_port_mode { diff --git a/include/linux/qed/iscsi_common.h b/include/linux/qed/iscsi_common.h index 4cc9b37b8d95..938df614cb6a 100644 --- a/include/linux/qed/iscsi_common.h +++ b/include/linux/qed/iscsi_common.h @@ -753,8 +753,8 @@ struct e4_ystorm_iscsi_task_ag_ctx { #define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5 #define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1 #define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6 -#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1 -#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7 +#define E4_YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_MASK 0x1 /* bit3 */ +#define E4_YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_SHIFT 7 u8 flags1; #define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3 #define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0 diff --git a/include/linux/qed/rdma_common.h b/include/linux/qed/rdma_common.h index c1a446ebe362..480a57eb36cc 100644 --- a/include/linux/qed/rdma_common.h +++ b/include/linux/qed/rdma_common.h @@ -51,6 +51,8 @@ #define RDMA_MAX_CQS (64 * 1024) #define RDMA_MAX_TIDS (128 * 1024 - 1) #define RDMA_MAX_PDS (64 * 1024) +#define RDMA_MAX_XRC_SRQS (1024) +#define RDMA_MAX_SRQS (32 * 1024) #define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS #define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2 diff --git a/include/linux/qed/roce_common.h b/include/linux/qed/roce_common.h index e15e0da71240..193bcef302e1 100644 --- a/include/linux/qed/roce_common.h +++ b/include/linux/qed/roce_common.h @@ -59,6 +59,9 @@ enum roce_async_events_type { ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR, ROCE_ASYNC_EVENT_SRQ_EMPTY, ROCE_ASYNC_EVENT_DESTROY_QP_DONE, + ROCE_ASYNC_EVENT_XRC_DOMAIN_ERR, + ROCE_ASYNC_EVENT_INVALID_XRCETH_ERR, + ROCE_ASYNC_EVENT_XRC_SRQ_CATASTROPHIC_ERR, MAX_ROCE_ASYNC_EVENTS_TYPE }; -- cgit v1.2.3 From 3a69cae80cdd1b5c8b23137cba2a80ecfec4cef5 Mon Sep 17 00:00:00 2001 From: Sudarsana Reddy Kalluru Date: Wed, 28 Mar 2018 05:14:22 -0700 Subject: qed: Adapter flash update support. This patch adds the required driver support for updating the flash or non volatile memory of the adapter. At highlevel, flash upgrade comprises of reading the flash images from the input file, validating the images and writing them to the respective paritions. Signed-off-by: Sudarsana Reddy Kalluru Signed-off-by: Ariel Elior Signed-off-by: David S. Miller --- drivers/net/ethernet/qlogic/qed/qed_main.c | 338 +++++++++++++++++++++++++++++ include/linux/qed/qed_if.h | 19 ++ 2 files changed, 357 insertions(+) (limited to 'include/linux') diff --git a/drivers/net/ethernet/qlogic/qed/qed_main.c b/drivers/net/ethernet/qlogic/qed/qed_main.c index 27832885a87f..9854aa9139af 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_main.c +++ b/drivers/net/ethernet/qlogic/qed/qed_main.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -1553,6 +1554,342 @@ static int qed_drain(struct qed_dev *cdev) return 0; } +static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev, + struct qed_nvm_image_att *nvm_image, + u32 *crc) +{ + u8 *buf = NULL; + int rc, j; + u32 val; + + /* Allocate a buffer for holding the nvram image */ + buf = kzalloc(nvm_image->length, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + /* Read image into buffer */ + rc = qed_mcp_nvm_read(cdev, nvm_image->start_addr, + buf, nvm_image->length); + if (rc) { + DP_ERR(cdev, "Failed reading image from nvm\n"); + goto out; + } + + /* Convert the buffer into big-endian format (excluding the + * closing 4 bytes of CRC). + */ + for (j = 0; j < nvm_image->length - 4; j += 4) { + val = cpu_to_be32(*(u32 *)&buf[j]); + *(u32 *)&buf[j] = val; + } + + /* Calc CRC for the "actual" image buffer, i.e. not including + * the last 4 CRC bytes. + */ + *crc = (~cpu_to_be32(crc32(0xffffffff, buf, nvm_image->length - 4))); + +out: + kfree(buf); + + return rc; +} + +/* Binary file format - + * /----------------------------------------------------------------------\ + * 0B | 0x4 [command index] | + * 4B | image_type | Options | Number of register settings | + * 8B | Value | + * 12B | Mask | + * 16B | Offset | + * \----------------------------------------------------------------------/ + * There can be several Value-Mask-Offset sets as specified by 'Number of...'. + * Options - 0'b - Calculate & Update CRC for image + */ +static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data, + bool *check_resp) +{ + struct qed_nvm_image_att nvm_image; + struct qed_hwfn *p_hwfn; + bool is_crc = false; + u32 image_type; + int rc = 0, i; + u16 len; + + *data += 4; + image_type = **data; + p_hwfn = QED_LEADING_HWFN(cdev); + for (i = 0; i < p_hwfn->nvm_info.num_images; i++) + if (image_type == p_hwfn->nvm_info.image_att[i].image_type) + break; + if (i == p_hwfn->nvm_info.num_images) { + DP_ERR(cdev, "Failed to find nvram image of type %08x\n", + image_type); + return -ENOENT; + } + + nvm_image.start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr; + nvm_image.length = p_hwfn->nvm_info.image_att[i].len; + + DP_VERBOSE(cdev, NETIF_MSG_DRV, + "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n", + **data, image_type, nvm_image.start_addr, + nvm_image.start_addr + nvm_image.length - 1); + (*data)++; + is_crc = !!(**data & BIT(0)); + (*data)++; + len = *((u16 *)*data); + *data += 2; + if (is_crc) { + u32 crc = 0; + + rc = qed_nvm_flash_image_access_crc(cdev, &nvm_image, &crc); + if (rc) { + DP_ERR(cdev, "Failed calculating CRC, rc = %d\n", rc); + goto exit; + } + + rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, + (nvm_image.start_addr + + nvm_image.length - 4), (u8 *)&crc, 4); + if (rc) + DP_ERR(cdev, "Failed writing to %08x, rc = %d\n", + nvm_image.start_addr + nvm_image.length - 4, rc); + goto exit; + } + + /* Iterate over the values for setting */ + while (len) { + u32 offset, mask, value, cur_value; + u8 buf[4]; + + value = *((u32 *)*data); + *data += 4; + mask = *((u32 *)*data); + *data += 4; + offset = *((u32 *)*data); + *data += 4; + + rc = qed_mcp_nvm_read(cdev, nvm_image.start_addr + offset, buf, + 4); + if (rc) { + DP_ERR(cdev, "Failed reading from %08x\n", + nvm_image.start_addr + offset); + goto exit; + } + + cur_value = le32_to_cpu(*((__le32 *)buf)); + DP_VERBOSE(cdev, NETIF_MSG_DRV, + "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n", + nvm_image.start_addr + offset, cur_value, + (cur_value & ~mask) | (value & mask), value, mask); + value = (value & mask) | (cur_value & ~mask); + rc = qed_mcp_nvm_write(cdev, QED_NVM_WRITE_NVRAM, + nvm_image.start_addr + offset, + (u8 *)&value, 4); + if (rc) { + DP_ERR(cdev, "Failed writing to %08x\n", + nvm_image.start_addr + offset); + goto exit; + } + + len--; + } +exit: + return rc; +} + +/* Binary file format - + * /----------------------------------------------------------------------\ + * 0B | 0x3 [command index] | + * 4B | b'0: check_response? | b'1-31 reserved | + * 8B | File-type | reserved | + * \----------------------------------------------------------------------/ + * Start a new file of the provided type + */ +static int qed_nvm_flash_image_file_start(struct qed_dev *cdev, + const u8 **data, bool *check_resp) +{ + int rc; + + *data += 4; + *check_resp = !!(**data & BIT(0)); + *data += 4; + + DP_VERBOSE(cdev, NETIF_MSG_DRV, + "About to start a new file of type %02x\n", **data); + rc = qed_mcp_nvm_put_file_begin(cdev, **data); + *data += 4; + + return rc; +} + +/* Binary file format - + * /----------------------------------------------------------------------\ + * 0B | 0x2 [command index] | + * 4B | Length in bytes | + * 8B | b'0: check_response? | b'1-31 reserved | + * 12B | Offset in bytes | + * 16B | Data ... | + * \----------------------------------------------------------------------/ + * Write data as part of a file that was previously started. Data should be + * of length equal to that provided in the message + */ +static int qed_nvm_flash_image_file_data(struct qed_dev *cdev, + const u8 **data, bool *check_resp) +{ + u32 offset, len; + int rc; + + *data += 4; + len = *((u32 *)(*data)); + *data += 4; + *check_resp = !!(**data & BIT(0)); + *data += 4; + offset = *((u32 *)(*data)); + *data += 4; + + DP_VERBOSE(cdev, NETIF_MSG_DRV, + "About to write File-data: %08x bytes to offset %08x\n", + len, offset); + + rc = qed_mcp_nvm_write(cdev, QED_PUT_FILE_DATA, offset, + (char *)(*data), len); + *data += len; + + return rc; +} + +/* Binary file format [General header] - + * /----------------------------------------------------------------------\ + * 0B | QED_NVM_SIGNATURE | + * 4B | Length in bytes | + * 8B | Highest command in this batchfile | Reserved | + * \----------------------------------------------------------------------/ + */ +static int qed_nvm_flash_image_validate(struct qed_dev *cdev, + const struct firmware *image, + const u8 **data) +{ + u32 signature, len; + + /* Check minimum size */ + if (image->size < 12) { + DP_ERR(cdev, "Image is too short [%08x]\n", (u32)image->size); + return -EINVAL; + } + + /* Check signature */ + signature = *((u32 *)(*data)); + if (signature != QED_NVM_SIGNATURE) { + DP_ERR(cdev, "Wrong signature '%08x'\n", signature); + return -EINVAL; + } + + *data += 4; + /* Validate internal size equals the image-size */ + len = *((u32 *)(*data)); + if (len != image->size) { + DP_ERR(cdev, "Size mismatch: internal = %08x image = %08x\n", + len, (u32)image->size); + return -EINVAL; + } + + *data += 4; + /* Make sure driver familiar with all commands necessary for this */ + if (*((u16 *)(*data)) >= QED_NVM_FLASH_CMD_NVM_MAX) { + DP_ERR(cdev, "File contains unsupported commands [Need %04x]\n", + *((u16 *)(*data))); + return -EINVAL; + } + + *data += 4; + + return 0; +} + +static int qed_nvm_flash(struct qed_dev *cdev, const char *name) +{ + const struct firmware *image; + const u8 *data, *data_end; + u32 cmd_type; + int rc; + + rc = request_firmware(&image, name, &cdev->pdev->dev); + if (rc) { + DP_ERR(cdev, "Failed to find '%s'\n", name); + return rc; + } + + DP_VERBOSE(cdev, NETIF_MSG_DRV, + "Flashing '%s' - firmware's data at %p, size is %08x\n", + name, image->data, (u32)image->size); + data = image->data; + data_end = data + image->size; + + rc = qed_nvm_flash_image_validate(cdev, image, &data); + if (rc) + goto exit; + + while (data < data_end) { + bool check_resp = false; + + /* Parse the actual command */ + cmd_type = *((u32 *)data); + switch (cmd_type) { + case QED_NVM_FLASH_CMD_FILE_DATA: + rc = qed_nvm_flash_image_file_data(cdev, &data, + &check_resp); + break; + case QED_NVM_FLASH_CMD_FILE_START: + rc = qed_nvm_flash_image_file_start(cdev, &data, + &check_resp); + break; + case QED_NVM_FLASH_CMD_NVM_CHANGE: + rc = qed_nvm_flash_image_access(cdev, &data, + &check_resp); + break; + default: + DP_ERR(cdev, "Unknown command %08x\n", cmd_type); + rc = -EINVAL; + goto exit; + } + + if (rc) { + DP_ERR(cdev, "Command %08x failed\n", cmd_type); + goto exit; + } + + /* Check response if needed */ + if (check_resp) { + u32 mcp_response = 0; + + if (qed_mcp_nvm_resp(cdev, (u8 *)&mcp_response)) { + DP_ERR(cdev, "Failed getting MCP response\n"); + rc = -EINVAL; + goto exit; + } + + switch (mcp_response & FW_MSG_CODE_MASK) { + case FW_MSG_CODE_OK: + case FW_MSG_CODE_NVM_OK: + case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK: + case FW_MSG_CODE_PHY_OK: + break; + default: + DP_ERR(cdev, "MFW returns error: %08x\n", + mcp_response); + rc = -EINVAL; + goto exit; + } + } + } + +exit: + release_firmware(image); + + return rc; +} + static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, u8 *buf, u16 len) { @@ -1719,6 +2056,7 @@ const struct qed_common_ops qed_common_ops_pass = { .dbg_all_data_size = &qed_dbg_all_data_size, .chain_alloc = &qed_chain_alloc, .chain_free = &qed_chain_free, + .nvm_flash = &qed_nvm_flash, .nvm_get_image = &qed_nvm_get_image, .set_coalesce = &qed_set_coalesce, .set_led = &qed_set_led, diff --git a/include/linux/qed/qed_if.h b/include/linux/qed/qed_if.h index 15e398c7230e..b5b2bc9eacca 100644 --- a/include/linux/qed/qed_if.h +++ b/include/linux/qed/qed_if.h @@ -483,6 +483,15 @@ struct qed_int_info { u8 used_cnt; }; +#define QED_NVM_SIGNATURE 0x12435687 + +enum qed_nvm_flash_cmd { + QED_NVM_FLASH_CMD_FILE_DATA = 0x2, + QED_NVM_FLASH_CMD_FILE_START = 0x3, + QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4, + QED_NVM_FLASH_CMD_NVM_MAX, +}; + struct qed_common_cb_ops { void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); void (*link_update)(void *dev, @@ -657,6 +666,16 @@ struct qed_common_ops { void (*chain_free)(struct qed_dev *cdev, struct qed_chain *p_chain); +/** + * @brief nvm_flash - Flash nvm data. + * + * @param cdev + * @param name - file containing the data + * + * @return 0 on success, error otherwise. + */ + int (*nvm_flash)(struct qed_dev *cdev, const char *name); + /** * @brief nvm_get_image - reads an entire image from nvram * -- cgit v1.2.3 From 903ddaf49329076862d65f7284d825759ff67bd6 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Wed, 7 Mar 2018 12:47:04 -0500 Subject: take out orphan externs (empty_string/slash_string) Signed-off-by: Al Viro --- include/linux/dcache.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/dcache.h b/include/linux/dcache.h index 82a99d366aec..c84ffbfc5098 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h @@ -56,9 +56,7 @@ struct qstr { #define QSTR_INIT(n,l) { { { .len = l } }, .name = n } -extern const char empty_string[]; extern const struct qstr empty_name; -extern const char slash_string[]; extern const struct qstr slash_name; struct dentry_stat_t { -- cgit v1.2.3 From 8934ce2fd08171e8605f7fada91ee7619fe17ab8 Mon Sep 17 00:00:00 2001 From: John Fastabend Date: Wed, 28 Mar 2018 12:49:15 -0700 Subject: bpf: sockmap redirect ingress support Add support for the BPF_F_INGRESS flag in sk_msg redirect helper. To do this add a scatterlist ring for receiving socks to check before calling into regular recvmsg call path. Additionally, because the poll wakeup logic only checked the skb recv queue we need to add a hook in TCP stack (similar to write side) so that we have a way to wake up polling socks when a scatterlist is redirected to that sock. After this all that is needed is for the redirect helper to push the scatterlist into the psock receive queue. Signed-off-by: John Fastabend Signed-off-by: Daniel Borkmann --- include/linux/filter.h | 1 + include/net/sock.h | 1 + kernel/bpf/sockmap.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++++- net/core/filter.c | 2 +- net/ipv4/tcp.c | 10 ++- 5 files changed, 207 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/filter.h b/include/linux/filter.h index c2f167db8bd5..961cc5d53956 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -521,6 +521,7 @@ struct sk_msg_buff { __u32 key; __u32 flags; struct bpf_map *map; + struct list_head list; }; /* Compute the linear packet data range [data, data_end) which diff --git a/include/net/sock.h b/include/net/sock.h index 709311132d4c..b8ff435fa96e 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1085,6 +1085,7 @@ struct proto { #endif bool (*stream_memory_free)(const struct sock *sk); + bool (*stream_memory_read)(const struct sock *sk); /* Memory pressure */ void (*enter_memory_pressure)(struct sock *sk); void (*leave_memory_pressure)(struct sock *sk); diff --git a/kernel/bpf/sockmap.c b/kernel/bpf/sockmap.c index 69c5bccabd22..402e15466e9f 100644 --- a/kernel/bpf/sockmap.c +++ b/kernel/bpf/sockmap.c @@ -41,6 +41,8 @@ #include #include #include +#include +#include #define SOCK_CREATE_FLAG_MASK \ (BPF_F_NUMA_NODE | BPF_F_RDONLY | BPF_F_WRONLY) @@ -82,6 +84,7 @@ struct smap_psock { int sg_size; int eval; struct sk_msg_buff *cork; + struct list_head ingress; struct strparser strp; struct bpf_prog *bpf_tx_msg; @@ -103,6 +106,8 @@ struct smap_psock { }; static void smap_release_sock(struct smap_psock *psock, struct sock *sock); +static int bpf_tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, + int nonblock, int flags, int *addr_len); static int bpf_tcp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size); static int bpf_tcp_sendpage(struct sock *sk, struct page *page, int offset, size_t size, int flags); @@ -112,6 +117,21 @@ static inline struct smap_psock *smap_psock_sk(const struct sock *sk) return rcu_dereference_sk_user_data(sk); } +static bool bpf_tcp_stream_read(const struct sock *sk) +{ + struct smap_psock *psock; + bool empty = true; + + rcu_read_lock(); + psock = smap_psock_sk(sk); + if (unlikely(!psock)) + goto out; + empty = list_empty(&psock->ingress); +out: + rcu_read_unlock(); + return !empty; +} + static struct proto tcp_bpf_proto; static int bpf_tcp_init(struct sock *sk) { @@ -135,6 +155,8 @@ static int bpf_tcp_init(struct sock *sk) if (psock->bpf_tx_msg) { tcp_bpf_proto.sendmsg = bpf_tcp_sendmsg; tcp_bpf_proto.sendpage = bpf_tcp_sendpage; + tcp_bpf_proto.recvmsg = bpf_tcp_recvmsg; + tcp_bpf_proto.stream_memory_read = bpf_tcp_stream_read; } sk->sk_prot = &tcp_bpf_proto; @@ -170,6 +192,7 @@ static void bpf_tcp_close(struct sock *sk, long timeout) { void (*close_fun)(struct sock *sk, long timeout); struct smap_psock_map_entry *e, *tmp; + struct sk_msg_buff *md, *mtmp; struct smap_psock *psock; struct sock *osk; @@ -188,6 +211,12 @@ static void bpf_tcp_close(struct sock *sk, long timeout) close_fun = psock->save_close; write_lock_bh(&sk->sk_callback_lock); + list_for_each_entry_safe(md, mtmp, &psock->ingress, list) { + list_del(&md->list); + free_start_sg(psock->sock, md); + kfree(md); + } + list_for_each_entry_safe(e, tmp, &psock->maps, list) { osk = cmpxchg(e->entry, sk, NULL); if (osk == sk) { @@ -468,6 +497,72 @@ verdict: return _rc; } +static int bpf_tcp_ingress(struct sock *sk, int apply_bytes, + struct smap_psock *psock, + struct sk_msg_buff *md, int flags) +{ + bool apply = apply_bytes; + size_t size, copied = 0; + struct sk_msg_buff *r; + int err = 0, i; + + r = kzalloc(sizeof(struct sk_msg_buff), __GFP_NOWARN | GFP_KERNEL); + if (unlikely(!r)) + return -ENOMEM; + + lock_sock(sk); + r->sg_start = md->sg_start; + i = md->sg_start; + + do { + r->sg_data[i] = md->sg_data[i]; + + size = (apply && apply_bytes < md->sg_data[i].length) ? + apply_bytes : md->sg_data[i].length; + + if (!sk_wmem_schedule(sk, size)) { + if (!copied) + err = -ENOMEM; + break; + } + + sk_mem_charge(sk, size); + r->sg_data[i].length = size; + md->sg_data[i].length -= size; + md->sg_data[i].offset += size; + copied += size; + + if (md->sg_data[i].length) { + get_page(sg_page(&r->sg_data[i])); + r->sg_end = (i + 1) == MAX_SKB_FRAGS ? 0 : i + 1; + } else { + i++; + if (i == MAX_SKB_FRAGS) + i = 0; + r->sg_end = i; + } + + if (apply) { + apply_bytes -= size; + if (!apply_bytes) + break; + } + } while (i != md->sg_end); + + md->sg_start = i; + + if (!err) { + list_add_tail(&r->list, &psock->ingress); + sk->sk_data_ready(sk); + } else { + free_start_sg(sk, r); + kfree(r); + } + + release_sock(sk); + return err; +} + static int bpf_tcp_sendmsg_do_redirect(struct sock *sk, int send, struct sk_msg_buff *md, int flags) @@ -475,6 +570,7 @@ static int bpf_tcp_sendmsg_do_redirect(struct sock *sk, int send, struct smap_psock *psock; struct scatterlist *sg; int i, err, free = 0; + bool ingress = !!(md->flags & BPF_F_INGRESS); sg = md->sg_data; @@ -487,9 +583,14 @@ static int bpf_tcp_sendmsg_do_redirect(struct sock *sk, int send, goto out_rcu; rcu_read_unlock(); - lock_sock(sk); - err = bpf_tcp_push(sk, send, md, flags, false); - release_sock(sk); + + if (ingress) { + err = bpf_tcp_ingress(sk, send, psock, md, flags); + } else { + lock_sock(sk); + err = bpf_tcp_push(sk, send, md, flags, false); + release_sock(sk); + } smap_release_sock(psock, sk); if (unlikely(err)) goto out; @@ -623,6 +724,89 @@ out_err: return err; } +static int bpf_tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, + int nonblock, int flags, int *addr_len) +{ + struct iov_iter *iter = &msg->msg_iter; + struct smap_psock *psock; + int copied = 0; + + if (unlikely(flags & MSG_ERRQUEUE)) + return inet_recv_error(sk, msg, len, addr_len); + + rcu_read_lock(); + psock = smap_psock_sk(sk); + if (unlikely(!psock)) + goto out; + + if (unlikely(!refcount_inc_not_zero(&psock->refcnt))) + goto out; + rcu_read_unlock(); + + if (!skb_queue_empty(&sk->sk_receive_queue)) + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); + + lock_sock(sk); + while (copied != len) { + struct scatterlist *sg; + struct sk_msg_buff *md; + int i; + + md = list_first_entry_or_null(&psock->ingress, + struct sk_msg_buff, list); + if (unlikely(!md)) + break; + i = md->sg_start; + do { + struct page *page; + int n, copy; + + sg = &md->sg_data[i]; + copy = sg->length; + page = sg_page(sg); + + if (copied + copy > len) + copy = len - copied; + + n = copy_page_to_iter(page, sg->offset, copy, iter); + if (n != copy) { + md->sg_start = i; + release_sock(sk); + smap_release_sock(psock, sk); + return -EFAULT; + } + + copied += copy; + sg->offset += copy; + sg->length -= copy; + sk_mem_uncharge(sk, copy); + + if (!sg->length) { + i++; + if (i == MAX_SKB_FRAGS) + i = 0; + put_page(page); + } + if (copied == len) + break; + } while (i != md->sg_end); + md->sg_start = i; + + if (!sg->length && md->sg_start == md->sg_end) { + list_del(&md->list); + kfree(md); + } + } + + release_sock(sk); + smap_release_sock(psock, sk); + return copied; +out: + rcu_read_unlock(); + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); +} + + static int bpf_tcp_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) { int flags = msg->msg_flags | MSG_NO_SHARED_FRAGS; @@ -1107,6 +1291,7 @@ static void sock_map_remove_complete(struct bpf_stab *stab) static void smap_gc_work(struct work_struct *w) { struct smap_psock_map_entry *e, *tmp; + struct sk_msg_buff *md, *mtmp; struct smap_psock *psock; psock = container_of(w, struct smap_psock, gc_work); @@ -1131,6 +1316,12 @@ static void smap_gc_work(struct work_struct *w) kfree(psock->cork); } + list_for_each_entry_safe(md, mtmp, &psock->ingress, list) { + list_del(&md->list); + free_start_sg(psock->sock, md); + kfree(md); + } + list_for_each_entry_safe(e, tmp, &psock->maps, list) { list_del(&e->list); kfree(e); @@ -1160,6 +1351,7 @@ static struct smap_psock *smap_init_psock(struct sock *sock, INIT_WORK(&psock->tx_work, smap_tx_work); INIT_WORK(&psock->gc_work, smap_gc_work); INIT_LIST_HEAD(&psock->maps); + INIT_LIST_HEAD(&psock->ingress); refcount_set(&psock->refcnt, 1); rcu_assign_sk_user_data(sock, psock); diff --git a/net/core/filter.c b/net/core/filter.c index afd825534ac4..a5a995e5b380 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -1894,7 +1894,7 @@ BPF_CALL_4(bpf_msg_redirect_map, struct sk_msg_buff *, msg, struct bpf_map *, map, u32, key, u64, flags) { /* If user passes invalid input drop the packet. */ - if (unlikely(flags)) + if (unlikely(flags & ~(BPF_F_INGRESS))) return SK_DROP; msg->key = key; diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 0c31be306572..bccc4c270087 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -485,6 +485,14 @@ static void tcp_tx_timestamp(struct sock *sk, u16 tsflags) } } +static inline bool tcp_stream_is_readable(const struct tcp_sock *tp, + int target, struct sock *sk) +{ + return (tp->rcv_nxt - tp->copied_seq >= target) || + (sk->sk_prot->stream_memory_read ? + sk->sk_prot->stream_memory_read(sk) : false); +} + /* * Wait for a TCP event. * @@ -554,7 +562,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) tp->urg_data) target++; - if (tp->rcv_nxt - tp->copied_seq >= target) + if (tcp_stream_is_readable(tp, target, sk)) mask |= EPOLLIN | EPOLLRDNORM; if (!(sk->sk_shutdown & SEND_SHUTDOWN)) { -- cgit v1.2.3 From fa246693a111fab32bd51d20f07a347e42773ee9 Mon Sep 17 00:00:00 2001 From: John Fastabend Date: Wed, 28 Mar 2018 12:49:25 -0700 Subject: bpf: sockmap, BPF_F_INGRESS flag for BPF_SK_SKB_STREAM_VERDICT: Add support for the BPF_F_INGRESS flag in skb redirect helper. To do this convert skb into a scatterlist and push into ingress queue. This is the same logic that is used in the sk_msg redirect helper so it should feel familiar. Signed-off-by: John Fastabend Signed-off-by: Daniel Borkmann --- include/linux/filter.h | 1 + kernel/bpf/sockmap.c | 94 ++++++++++++++++++++++++++++++++++++++++---------- net/core/filter.c | 2 +- 3 files changed, 78 insertions(+), 19 deletions(-) (limited to 'include/linux') diff --git a/include/linux/filter.h b/include/linux/filter.h index 961cc5d53956..897ff3d95968 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -521,6 +521,7 @@ struct sk_msg_buff { __u32 key; __u32 flags; struct bpf_map *map; + struct sk_buff *skb; struct list_head list; }; diff --git a/kernel/bpf/sockmap.c b/kernel/bpf/sockmap.c index 402e15466e9f..9192fdbcbccc 100644 --- a/kernel/bpf/sockmap.c +++ b/kernel/bpf/sockmap.c @@ -785,7 +785,8 @@ static int bpf_tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, i++; if (i == MAX_SKB_FRAGS) i = 0; - put_page(page); + if (!md->skb) + put_page(page); } if (copied == len) break; @@ -794,6 +795,8 @@ static int bpf_tcp_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, if (!sg->length && md->sg_start == md->sg_end) { list_del(&md->list); + if (md->skb) + consume_skb(md->skb); kfree(md); } } @@ -1045,27 +1048,72 @@ static int smap_verdict_func(struct smap_psock *psock, struct sk_buff *skb) __SK_DROP; } +static int smap_do_ingress(struct smap_psock *psock, struct sk_buff *skb) +{ + struct sock *sk = psock->sock; + int copied = 0, num_sg; + struct sk_msg_buff *r; + + r = kzalloc(sizeof(struct sk_msg_buff), __GFP_NOWARN | GFP_ATOMIC); + if (unlikely(!r)) + return -EAGAIN; + + if (!sk_rmem_schedule(sk, skb, skb->len)) { + kfree(r); + return -EAGAIN; + } + + sg_init_table(r->sg_data, MAX_SKB_FRAGS); + num_sg = skb_to_sgvec(skb, r->sg_data, 0, skb->len); + if (unlikely(num_sg < 0)) { + kfree(r); + return num_sg; + } + sk_mem_charge(sk, skb->len); + copied = skb->len; + r->sg_start = 0; + r->sg_end = num_sg == MAX_SKB_FRAGS ? 0 : num_sg; + r->skb = skb; + list_add_tail(&r->list, &psock->ingress); + sk->sk_data_ready(sk); + return copied; +} + static void smap_do_verdict(struct smap_psock *psock, struct sk_buff *skb) { + struct smap_psock *peer; struct sock *sk; + __u32 in; int rc; rc = smap_verdict_func(psock, skb); switch (rc) { case __SK_REDIRECT: sk = do_sk_redirect_map(skb); - if (likely(sk)) { - struct smap_psock *peer = smap_psock_sk(sk); - - if (likely(peer && - test_bit(SMAP_TX_RUNNING, &peer->state) && - !sock_flag(sk, SOCK_DEAD) && - sock_writeable(sk))) { - skb_set_owner_w(skb, sk); - skb_queue_tail(&peer->rxqueue, skb); - schedule_work(&peer->tx_work); - break; - } + if (!sk) { + kfree_skb(skb); + break; + } + + peer = smap_psock_sk(sk); + in = (TCP_SKB_CB(skb)->bpf.flags) & BPF_F_INGRESS; + + if (unlikely(!peer || sock_flag(sk, SOCK_DEAD) || + !test_bit(SMAP_TX_RUNNING, &peer->state))) { + kfree_skb(skb); + break; + } + + if (!in && sock_writeable(sk)) { + skb_set_owner_w(skb, sk); + skb_queue_tail(&peer->rxqueue, skb); + schedule_work(&peer->tx_work); + break; + } else if (in && + atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) { + skb_queue_tail(&peer->rxqueue, skb); + schedule_work(&peer->tx_work); + break; } /* Fall through and free skb otherwise */ case __SK_DROP: @@ -1127,15 +1175,23 @@ static void smap_tx_work(struct work_struct *w) } while ((skb = skb_dequeue(&psock->rxqueue))) { + __u32 flags; + rem = skb->len; off = 0; start: + flags = (TCP_SKB_CB(skb)->bpf.flags) & BPF_F_INGRESS; do { - if (likely(psock->sock->sk_socket)) - n = skb_send_sock_locked(psock->sock, - skb, off, rem); - else + if (likely(psock->sock->sk_socket)) { + if (flags) + n = smap_do_ingress(psock, skb); + else + n = skb_send_sock_locked(psock->sock, + skb, off, rem); + } else { n = -EINVAL; + } + if (n <= 0) { if (n == -EAGAIN) { /* Retry when space is available */ @@ -1153,7 +1209,9 @@ start: rem -= n; off += n; } while (rem); - kfree_skb(skb); + + if (!flags) + kfree_skb(skb); } out: release_sock(psock->sock); diff --git a/net/core/filter.c b/net/core/filter.c index a5a995e5b380..e989bf313195 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -1855,7 +1855,7 @@ BPF_CALL_4(bpf_sk_redirect_map, struct sk_buff *, skb, struct tcp_skb_cb *tcb = TCP_SKB_CB(skb); /* If user passes invalid input drop the packet. */ - if (unlikely(flags)) + if (unlikely(flags & ~(BPF_F_INGRESS))) return SK_DROP; tcb->bpf.key = key; -- cgit v1.2.3 From c6ac3f35d46b3c9999838dd13e7e113674f22ffa Mon Sep 17 00:00:00 2001 From: Matias Bjørling Date: Fri, 30 Mar 2018 00:05:01 +0200 Subject: lightnvm: flatten nvm_id_group into nvm_id MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are no groups in the 2.0 specification, make sure that the nvm_id structure is flattened before 2.0 data structures are added. Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 25 +++++----- drivers/nvme/host/lightnvm.c | 106 +++++++++++++++++++++---------------------- include/linux/lightnvm.h | 53 +++++++++++----------- 3 files changed, 89 insertions(+), 95 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index 5f1988df1593..db4a1b8f1561 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -851,33 +851,32 @@ EXPORT_SYMBOL(nvm_get_tgt_bb_tbl); static int nvm_core_init(struct nvm_dev *dev) { struct nvm_id *id = &dev->identity; - struct nvm_id_group *grp = &id->grp; struct nvm_geo *geo = &dev->geo; int ret; memcpy(&geo->ppaf, &id->ppaf, sizeof(struct nvm_addr_format)); - if (grp->mtype != 0) { + if (id->mtype != 0) { pr_err("nvm: memory type not supported\n"); return -EINVAL; } /* Whole device values */ - geo->nr_chnls = grp->num_ch; - geo->nr_luns = grp->num_lun; + geo->nr_chnls = id->num_ch; + geo->nr_luns = id->num_lun; /* Generic device geometry values */ - geo->ws_min = grp->ws_min; - geo->ws_opt = grp->ws_opt; - geo->ws_seq = grp->ws_seq; - geo->ws_per_chk = grp->ws_per_chk; - geo->nr_chks = grp->num_chk; - geo->sec_size = grp->csecs; - geo->oob_size = grp->sos; - geo->mccap = grp->mccap; + geo->ws_min = id->ws_min; + geo->ws_opt = id->ws_opt; + geo->ws_seq = id->ws_seq; + geo->ws_per_chk = id->ws_per_chk; + geo->nr_chks = id->num_chk; + geo->sec_size = id->csecs; + geo->oob_size = id->sos; + geo->mccap = id->mccap; geo->max_rq_size = dev->ops->max_phys_sect * geo->sec_size; - geo->sec_per_chk = grp->clba; + geo->sec_per_chk = id->clba; geo->sec_per_lun = geo->sec_per_chk * geo->nr_chks; geo->all_luns = geo->nr_luns * geo->nr_chnls; diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index 60db3f1b59da..6412551ecc65 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -203,57 +203,55 @@ static inline void _nvme_nvm_check_size(void) static int init_grp(struct nvm_id *nvm_id, struct nvme_nvm_id12 *id12) { struct nvme_nvm_id12_grp *src; - struct nvm_id_group *grp; int sec_per_pg, sec_per_pl, pg_per_blk; if (id12->cgrps != 1) return -EINVAL; src = &id12->grp; - grp = &nvm_id->grp; - grp->mtype = src->mtype; - grp->fmtype = src->fmtype; + nvm_id->mtype = src->mtype; + nvm_id->fmtype = src->fmtype; - grp->num_ch = src->num_ch; - grp->num_lun = src->num_lun; + nvm_id->num_ch = src->num_ch; + nvm_id->num_lun = src->num_lun; - grp->num_chk = le16_to_cpu(src->num_chk); - grp->csecs = le16_to_cpu(src->csecs); - grp->sos = le16_to_cpu(src->sos); + nvm_id->num_chk = le16_to_cpu(src->num_chk); + nvm_id->csecs = le16_to_cpu(src->csecs); + nvm_id->sos = le16_to_cpu(src->sos); pg_per_blk = le16_to_cpu(src->num_pg); - sec_per_pg = le16_to_cpu(src->fpg_sz) / grp->csecs; + sec_per_pg = le16_to_cpu(src->fpg_sz) / nvm_id->csecs; sec_per_pl = sec_per_pg * src->num_pln; - grp->clba = sec_per_pl * pg_per_blk; - grp->ws_per_chk = pg_per_blk; - - grp->mpos = le32_to_cpu(src->mpos); - grp->cpar = le16_to_cpu(src->cpar); - grp->mccap = le32_to_cpu(src->mccap); - - grp->ws_opt = grp->ws_min = sec_per_pg; - grp->ws_seq = NVM_IO_SNGL_ACCESS; - - if (grp->mpos & 0x020202) { - grp->ws_seq = NVM_IO_DUAL_ACCESS; - grp->ws_opt <<= 1; - } else if (grp->mpos & 0x040404) { - grp->ws_seq = NVM_IO_QUAD_ACCESS; - grp->ws_opt <<= 2; + nvm_id->clba = sec_per_pl * pg_per_blk; + nvm_id->ws_per_chk = pg_per_blk; + + nvm_id->mpos = le32_to_cpu(src->mpos); + nvm_id->cpar = le16_to_cpu(src->cpar); + nvm_id->mccap = le32_to_cpu(src->mccap); + + nvm_id->ws_opt = nvm_id->ws_min = sec_per_pg; + nvm_id->ws_seq = NVM_IO_SNGL_ACCESS; + + if (nvm_id->mpos & 0x020202) { + nvm_id->ws_seq = NVM_IO_DUAL_ACCESS; + nvm_id->ws_opt <<= 1; + } else if (nvm_id->mpos & 0x040404) { + nvm_id->ws_seq = NVM_IO_QUAD_ACCESS; + nvm_id->ws_opt <<= 2; } - grp->trdt = le32_to_cpu(src->trdt); - grp->trdm = le32_to_cpu(src->trdm); - grp->tprt = le32_to_cpu(src->tprt); - grp->tprm = le32_to_cpu(src->tprm); - grp->tbet = le32_to_cpu(src->tbet); - grp->tbem = le32_to_cpu(src->tbem); + nvm_id->trdt = le32_to_cpu(src->trdt); + nvm_id->trdm = le32_to_cpu(src->trdm); + nvm_id->tprt = le32_to_cpu(src->tprt); + nvm_id->tprm = le32_to_cpu(src->tprm); + nvm_id->tbet = le32_to_cpu(src->tbet); + nvm_id->tbem = le32_to_cpu(src->tbem); /* 1.2 compatibility */ - grp->num_pln = src->num_pln; - grp->num_pg = le16_to_cpu(src->num_pg); - grp->fpg_sz = le16_to_cpu(src->fpg_sz); + nvm_id->num_pln = src->num_pln; + nvm_id->num_pg = le16_to_cpu(src->num_pg); + nvm_id->fpg_sz = le16_to_cpu(src->fpg_sz); return 0; } @@ -740,14 +738,12 @@ static ssize_t nvm_dev_attr_show(struct device *dev, struct nvme_ns *ns = nvme_get_ns_from_dev(dev); struct nvm_dev *ndev = ns->ndev; struct nvm_id *id; - struct nvm_id_group *grp; struct attribute *attr; if (!ndev) return 0; id = &ndev->identity; - grp = &id->grp; attr = &dattr->attr; if (strcmp(attr->name, "version") == 0) { @@ -771,41 +767,41 @@ static ssize_t nvm_dev_attr_show(struct device *dev, id->ppaf.pg_offset, id->ppaf.pg_len, id->ppaf.sect_offset, id->ppaf.sect_len); } else if (strcmp(attr->name, "media_type") == 0) { /* u8 */ - return scnprintf(page, PAGE_SIZE, "%u\n", grp->mtype); + return scnprintf(page, PAGE_SIZE, "%u\n", id->mtype); } else if (strcmp(attr->name, "flash_media_type") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->fmtype); + return scnprintf(page, PAGE_SIZE, "%u\n", id->fmtype); } else if (strcmp(attr->name, "num_channels") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_ch); + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_ch); } else if (strcmp(attr->name, "num_luns") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_lun); + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_lun); } else if (strcmp(attr->name, "num_planes") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_pln); + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_pln); } else if (strcmp(attr->name, "num_blocks") == 0) { /* u16 */ - return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_chk); + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_chk); } else if (strcmp(attr->name, "num_pages") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->num_pg); + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_pg); } else if (strcmp(attr->name, "page_size") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->fpg_sz); + return scnprintf(page, PAGE_SIZE, "%u\n", id->fpg_sz); } else if (strcmp(attr->name, "hw_sector_size") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->csecs); + return scnprintf(page, PAGE_SIZE, "%u\n", id->csecs); } else if (strcmp(attr->name, "oob_sector_size") == 0) {/* u32 */ - return scnprintf(page, PAGE_SIZE, "%u\n", grp->sos); + return scnprintf(page, PAGE_SIZE, "%u\n", id->sos); } else if (strcmp(attr->name, "read_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->trdt); + return scnprintf(page, PAGE_SIZE, "%u\n", id->trdt); } else if (strcmp(attr->name, "read_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->trdm); + return scnprintf(page, PAGE_SIZE, "%u\n", id->trdm); } else if (strcmp(attr->name, "prog_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->tprt); + return scnprintf(page, PAGE_SIZE, "%u\n", id->tprt); } else if (strcmp(attr->name, "prog_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->tprm); + return scnprintf(page, PAGE_SIZE, "%u\n", id->tprm); } else if (strcmp(attr->name, "erase_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->tbet); + return scnprintf(page, PAGE_SIZE, "%u\n", id->tbet); } else if (strcmp(attr->name, "erase_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", grp->tbem); + return scnprintf(page, PAGE_SIZE, "%u\n", id->tbem); } else if (strcmp(attr->name, "multiplane_modes") == 0) { - return scnprintf(page, PAGE_SIZE, "0x%08x\n", grp->mpos); + return scnprintf(page, PAGE_SIZE, "0x%08x\n", id->mpos); } else if (strcmp(attr->name, "media_capabilities") == 0) { - return scnprintf(page, PAGE_SIZE, "0x%08x\n", grp->mccap); + return scnprintf(page, PAGE_SIZE, "0x%08x\n", id->mccap); } else if (strcmp(attr->name, "max_phys_secs") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", ndev->ops->max_phys_sect); diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index 7f4b60abdf27..94b704a8d83d 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -154,9 +154,29 @@ struct nvm_id_lp_tbl { struct nvm_id_lp_mlc mlc; }; -struct nvm_id_group { - u8 mtype; - u8 fmtype; +struct nvm_addr_format { + u8 ch_offset; + u8 ch_len; + u8 lun_offset; + u8 lun_len; + u8 pln_offset; + u8 pln_len; + u8 blk_offset; + u8 blk_len; + u8 pg_offset; + u8 pg_len; + u8 sect_offset; + u8 sect_len; +}; + +struct nvm_id { + u8 ver_id; + u8 vmnt; + u32 cap; + u32 dom; + + struct nvm_addr_format ppaf; + u8 num_ch; u8 num_lun; u16 num_chk; @@ -180,33 +200,12 @@ struct nvm_id_group { u16 cpar; /* 1.2 compatibility */ + u8 mtype; + u8 fmtype; + u8 num_pln; u16 num_pg; u16 fpg_sz; -}; - -struct nvm_addr_format { - u8 ch_offset; - u8 ch_len; - u8 lun_offset; - u8 lun_len; - u8 pln_offset; - u8 pln_len; - u8 blk_offset; - u8 blk_len; - u8 pg_offset; - u8 pg_len; - u8 sect_offset; - u8 sect_len; -}; - -struct nvm_id { - u8 ver_id; - u8 vmnt; - u32 cap; - u32 dom; - struct nvm_addr_format ppaf; - struct nvm_id_group grp; } __packed; struct nvm_target { -- cgit v1.2.3 From 62771fe0aa28b5d329f3e53a2e0f805f73433752 Mon Sep 17 00:00:00 2001 From: Matias Bjørling Date: Fri, 30 Mar 2018 00:05:02 +0200 Subject: lightnvm: add 2.0 geometry identification MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement the geometry data structures for 2.0 and enable a drive to be identified as one, including exposing the appropriate 2.0 sysfs entries. Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 8 +- drivers/nvme/host/lightnvm.c | 338 ++++++++++++++++++++++++++++++++++++------- include/linux/lightnvm.h | 11 +- 3 files changed, 299 insertions(+), 58 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index db4a1b8f1561..521f520a1bb4 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -931,11 +931,9 @@ static int nvm_init(struct nvm_dev *dev) goto err; } - pr_debug("nvm: ver:%x nvm_vendor:%x\n", - dev->identity.ver_id, dev->identity.vmnt); - - if (dev->identity.ver_id != 1) { - pr_err("nvm: device not supported by kernel."); + if (dev->identity.ver_id != 1 && dev->identity.ver_id != 2) { + pr_err("nvm: device ver_id %d not supported by kernel.\n", + dev->identity.ver_id); goto err; } diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index 6412551ecc65..8b243af8a949 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -184,6 +184,58 @@ struct nvme_nvm_bb_tbl { __u8 blk[0]; }; +struct nvme_nvm_id20_addrf { + __u8 grp_len; + __u8 pu_len; + __u8 chk_len; + __u8 lba_len; + __u8 resv[4]; +}; + +struct nvme_nvm_id20 { + __u8 mjr; + __u8 mnr; + __u8 resv[6]; + + struct nvme_nvm_id20_addrf lbaf; + + __le32 mccap; + __u8 resv2[12]; + + __u8 wit; + __u8 resv3[31]; + + /* Geometry */ + __le16 num_grp; + __le16 num_pu; + __le32 num_chk; + __le32 clba; + __u8 resv4[52]; + + /* Write data requirements */ + __le32 ws_min; + __le32 ws_opt; + __le32 mw_cunits; + __le32 maxoc; + __le32 maxocpu; + __u8 resv5[44]; + + /* Performance related metrics */ + __le32 trdt; + __le32 trdm; + __le32 twrt; + __le32 twrm; + __le32 tcrst; + __le32 tcrsm; + __u8 resv6[40]; + + /* Reserved area */ + __u8 resv7[2816]; + + /* Vendor specific */ + __u8 vs[1024]; +}; + /* * Check we didn't inadvertently grow the command struct */ @@ -198,6 +250,8 @@ static inline void _nvme_nvm_check_size(void) BUILD_BUG_ON(sizeof(struct nvme_nvm_id12_addrf) != 16); BUILD_BUG_ON(sizeof(struct nvme_nvm_id12) != NVME_IDENTIFY_DATA_SIZE); BUILD_BUG_ON(sizeof(struct nvme_nvm_bb_tbl) != 64); + BUILD_BUG_ON(sizeof(struct nvme_nvm_id20_addrf) != 8); + BUILD_BUG_ON(sizeof(struct nvme_nvm_id20) != NVME_IDENTIFY_DATA_SIZE); } static int init_grp(struct nvm_id *nvm_id, struct nvme_nvm_id12 *id12) @@ -256,6 +310,49 @@ static int init_grp(struct nvm_id *nvm_id, struct nvme_nvm_id12 *id12) return 0; } +static int nvme_nvm_setup_12(struct nvm_dev *nvmdev, struct nvm_id *nvm_id, + struct nvme_nvm_id12 *id) +{ + nvm_id->ver_id = id->ver_id; + nvm_id->vmnt = id->vmnt; + nvm_id->cap = le32_to_cpu(id->cap); + nvm_id->dom = le32_to_cpu(id->dom); + memcpy(&nvm_id->ppaf, &id->ppaf, + sizeof(struct nvm_addr_format)); + + return init_grp(nvm_id, id); +} + +static int nvme_nvm_setup_20(struct nvm_dev *nvmdev, struct nvm_id *nvm_id, + struct nvme_nvm_id20 *id) +{ + nvm_id->ver_id = id->mjr; + + nvm_id->num_ch = le16_to_cpu(id->num_grp); + nvm_id->num_lun = le16_to_cpu(id->num_pu); + nvm_id->num_chk = le32_to_cpu(id->num_chk); + nvm_id->clba = le32_to_cpu(id->clba); + + nvm_id->ws_min = le32_to_cpu(id->ws_min); + nvm_id->ws_opt = le32_to_cpu(id->ws_opt); + nvm_id->mw_cunits = le32_to_cpu(id->mw_cunits); + + nvm_id->trdt = le32_to_cpu(id->trdt); + nvm_id->trdm = le32_to_cpu(id->trdm); + nvm_id->tprt = le32_to_cpu(id->twrt); + nvm_id->tprm = le32_to_cpu(id->twrm); + nvm_id->tbet = le32_to_cpu(id->tcrst); + nvm_id->tbem = le32_to_cpu(id->tcrsm); + + /* calculated values */ + nvm_id->ws_per_chk = nvm_id->clba / nvm_id->ws_min; + + /* 1.2 compatibility */ + nvm_id->ws_seq = NVM_IO_SNGL_ACCESS; + + return 0; +} + static int nvme_nvm_identity(struct nvm_dev *nvmdev, struct nvm_id *nvm_id) { struct nvme_ns *ns = nvmdev->q->queuedata; @@ -277,14 +374,24 @@ static int nvme_nvm_identity(struct nvm_dev *nvmdev, struct nvm_id *nvm_id) goto out; } - nvm_id->ver_id = id->ver_id; - nvm_id->vmnt = id->vmnt; - nvm_id->cap = le32_to_cpu(id->cap); - nvm_id->dom = le32_to_cpu(id->dom); - memcpy(&nvm_id->ppaf, &id->ppaf, - sizeof(struct nvm_addr_format)); - - ret = init_grp(nvm_id, id); + /* + * The 1.2 and 2.0 specifications share the first byte in their geometry + * command to make it possible to know what version a device implements. + */ + switch (id->ver_id) { + case 1: + ret = nvme_nvm_setup_12(nvmdev, nvm_id, id); + break; + case 2: + ret = nvme_nvm_setup_20(nvmdev, nvm_id, + (struct nvme_nvm_id20 *)id); + break; + default: + dev_err(ns->ctrl->device, + "OCSSD revision not supported (%d)\n", + nvm_id->ver_id); + ret = -EINVAL; + } out: kfree(id); return ret; @@ -733,7 +840,7 @@ void nvme_nvm_unregister(struct nvme_ns *ns) } static ssize_t nvm_dev_attr_show(struct device *dev, - struct device_attribute *dattr, char *page) + struct device_attribute *dattr, char *page) { struct nvme_ns *ns = nvme_get_ns_from_dev(dev); struct nvm_dev *ndev = ns->ndev; @@ -748,10 +855,36 @@ static ssize_t nvm_dev_attr_show(struct device *dev, if (strcmp(attr->name, "version") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", id->ver_id); - } else if (strcmp(attr->name, "vendor_opcode") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->vmnt); } else if (strcmp(attr->name, "capabilities") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", id->cap); + } else if (strcmp(attr->name, "read_typ") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->trdt); + } else if (strcmp(attr->name, "read_max") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->trdm); + } else { + return scnprintf(page, + PAGE_SIZE, + "Unhandled attr(%s) in `nvm_dev_attr_show`\n", + attr->name); + } +} + +static ssize_t nvm_dev_attr_show_12(struct device *dev, + struct device_attribute *dattr, char *page) +{ + struct nvme_ns *ns = nvme_get_ns_from_dev(dev); + struct nvm_dev *ndev = ns->ndev; + struct nvm_id *id; + struct attribute *attr; + + if (!ndev) + return 0; + + id = &ndev->identity; + attr = &dattr->attr; + + if (strcmp(attr->name, "vendor_opcode") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->vmnt); } else if (strcmp(attr->name, "device_mode") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", id->dom); /* kept for compatibility */ @@ -786,10 +919,6 @@ static ssize_t nvm_dev_attr_show(struct device *dev, return scnprintf(page, PAGE_SIZE, "%u\n", id->csecs); } else if (strcmp(attr->name, "oob_sector_size") == 0) {/* u32 */ return scnprintf(page, PAGE_SIZE, "%u\n", id->sos); - } else if (strcmp(attr->name, "read_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->trdt); - } else if (strcmp(attr->name, "read_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->trdm); } else if (strcmp(attr->name, "prog_typ") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", id->tprt); } else if (strcmp(attr->name, "prog_max") == 0) { @@ -808,48 +937,99 @@ static ssize_t nvm_dev_attr_show(struct device *dev, } else { return scnprintf(page, PAGE_SIZE, - "Unhandled attr(%s) in `nvm_dev_attr_show`\n", + "Unhandled attr(%s) in `nvm_dev_attr_show_12`\n", attr->name); } } -#define NVM_DEV_ATTR_RO(_name) \ +static ssize_t nvm_dev_attr_show_20(struct device *dev, + struct device_attribute *dattr, char *page) +{ + struct nvme_ns *ns = nvme_get_ns_from_dev(dev); + struct nvm_dev *ndev = ns->ndev; + struct nvm_id *id; + struct attribute *attr; + + if (!ndev) + return 0; + + id = &ndev->identity; + attr = &dattr->attr; + + if (strcmp(attr->name, "groups") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_ch); + } else if (strcmp(attr->name, "punits") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_lun); + } else if (strcmp(attr->name, "chunks") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->num_chk); + } else if (strcmp(attr->name, "clba") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->clba); + } else if (strcmp(attr->name, "ws_min") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->ws_min); + } else if (strcmp(attr->name, "ws_opt") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->ws_opt); + } else if (strcmp(attr->name, "mw_cunits") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->mw_cunits); + } else if (strcmp(attr->name, "write_typ") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->tprt); + } else if (strcmp(attr->name, "write_max") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->tprm); + } else if (strcmp(attr->name, "reset_typ") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->tbet); + } else if (strcmp(attr->name, "reset_max") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", id->tbem); + } else { + return scnprintf(page, + PAGE_SIZE, + "Unhandled attr(%s) in `nvm_dev_attr_show_20`\n", + attr->name); + } +} + +#define NVM_DEV_ATTR_RO(_name) \ DEVICE_ATTR(_name, S_IRUGO, nvm_dev_attr_show, NULL) +#define NVM_DEV_ATTR_12_RO(_name) \ + DEVICE_ATTR(_name, S_IRUGO, nvm_dev_attr_show_12, NULL) +#define NVM_DEV_ATTR_20_RO(_name) \ + DEVICE_ATTR(_name, S_IRUGO, nvm_dev_attr_show_20, NULL) +/* general attributes */ static NVM_DEV_ATTR_RO(version); -static NVM_DEV_ATTR_RO(vendor_opcode); static NVM_DEV_ATTR_RO(capabilities); -static NVM_DEV_ATTR_RO(device_mode); -static NVM_DEV_ATTR_RO(ppa_format); -static NVM_DEV_ATTR_RO(media_manager); - -static NVM_DEV_ATTR_RO(media_type); -static NVM_DEV_ATTR_RO(flash_media_type); -static NVM_DEV_ATTR_RO(num_channels); -static NVM_DEV_ATTR_RO(num_luns); -static NVM_DEV_ATTR_RO(num_planes); -static NVM_DEV_ATTR_RO(num_blocks); -static NVM_DEV_ATTR_RO(num_pages); -static NVM_DEV_ATTR_RO(page_size); -static NVM_DEV_ATTR_RO(hw_sector_size); -static NVM_DEV_ATTR_RO(oob_sector_size); + static NVM_DEV_ATTR_RO(read_typ); static NVM_DEV_ATTR_RO(read_max); -static NVM_DEV_ATTR_RO(prog_typ); -static NVM_DEV_ATTR_RO(prog_max); -static NVM_DEV_ATTR_RO(erase_typ); -static NVM_DEV_ATTR_RO(erase_max); -static NVM_DEV_ATTR_RO(multiplane_modes); -static NVM_DEV_ATTR_RO(media_capabilities); -static NVM_DEV_ATTR_RO(max_phys_secs); - -static struct attribute *nvm_dev_attrs[] = { + +/* 1.2 values */ +static NVM_DEV_ATTR_12_RO(vendor_opcode); +static NVM_DEV_ATTR_12_RO(device_mode); +static NVM_DEV_ATTR_12_RO(ppa_format); +static NVM_DEV_ATTR_12_RO(media_manager); +static NVM_DEV_ATTR_12_RO(media_type); +static NVM_DEV_ATTR_12_RO(flash_media_type); +static NVM_DEV_ATTR_12_RO(num_channels); +static NVM_DEV_ATTR_12_RO(num_luns); +static NVM_DEV_ATTR_12_RO(num_planes); +static NVM_DEV_ATTR_12_RO(num_blocks); +static NVM_DEV_ATTR_12_RO(num_pages); +static NVM_DEV_ATTR_12_RO(page_size); +static NVM_DEV_ATTR_12_RO(hw_sector_size); +static NVM_DEV_ATTR_12_RO(oob_sector_size); +static NVM_DEV_ATTR_12_RO(prog_typ); +static NVM_DEV_ATTR_12_RO(prog_max); +static NVM_DEV_ATTR_12_RO(erase_typ); +static NVM_DEV_ATTR_12_RO(erase_max); +static NVM_DEV_ATTR_12_RO(multiplane_modes); +static NVM_DEV_ATTR_12_RO(media_capabilities); +static NVM_DEV_ATTR_12_RO(max_phys_secs); + +static struct attribute *nvm_dev_attrs_12[] = { &dev_attr_version.attr, - &dev_attr_vendor_opcode.attr, &dev_attr_capabilities.attr, + + &dev_attr_vendor_opcode.attr, &dev_attr_device_mode.attr, &dev_attr_media_manager.attr, - &dev_attr_ppa_format.attr, &dev_attr_media_type.attr, &dev_attr_flash_media_type.attr, @@ -870,22 +1050,82 @@ static struct attribute *nvm_dev_attrs[] = { &dev_attr_multiplane_modes.attr, &dev_attr_media_capabilities.attr, &dev_attr_max_phys_secs.attr, + NULL, }; -static const struct attribute_group nvm_dev_attr_group = { +static const struct attribute_group nvm_dev_attr_group_12 = { .name = "lightnvm", - .attrs = nvm_dev_attrs, + .attrs = nvm_dev_attrs_12, +}; + +/* 2.0 values */ +static NVM_DEV_ATTR_20_RO(groups); +static NVM_DEV_ATTR_20_RO(punits); +static NVM_DEV_ATTR_20_RO(chunks); +static NVM_DEV_ATTR_20_RO(clba); +static NVM_DEV_ATTR_20_RO(ws_min); +static NVM_DEV_ATTR_20_RO(ws_opt); +static NVM_DEV_ATTR_20_RO(mw_cunits); +static NVM_DEV_ATTR_20_RO(write_typ); +static NVM_DEV_ATTR_20_RO(write_max); +static NVM_DEV_ATTR_20_RO(reset_typ); +static NVM_DEV_ATTR_20_RO(reset_max); + +static struct attribute *nvm_dev_attrs_20[] = { + &dev_attr_version.attr, + &dev_attr_capabilities.attr, + + &dev_attr_groups.attr, + &dev_attr_punits.attr, + &dev_attr_chunks.attr, + &dev_attr_clba.attr, + &dev_attr_ws_min.attr, + &dev_attr_ws_opt.attr, + &dev_attr_mw_cunits.attr, + + &dev_attr_read_typ.attr, + &dev_attr_read_max.attr, + &dev_attr_write_typ.attr, + &dev_attr_write_max.attr, + &dev_attr_reset_typ.attr, + &dev_attr_reset_max.attr, + + NULL, +}; + +static const struct attribute_group nvm_dev_attr_group_20 = { + .name = "lightnvm", + .attrs = nvm_dev_attrs_20, }; int nvme_nvm_register_sysfs(struct nvme_ns *ns) { - return sysfs_create_group(&disk_to_dev(ns->disk)->kobj, - &nvm_dev_attr_group); + if (!ns->ndev) + return -EINVAL; + + switch (ns->ndev->identity.ver_id) { + case 1: + return sysfs_create_group(&disk_to_dev(ns->disk)->kobj, + &nvm_dev_attr_group_12); + case 2: + return sysfs_create_group(&disk_to_dev(ns->disk)->kobj, + &nvm_dev_attr_group_20); + } + + return -EINVAL; } void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) { - sysfs_remove_group(&disk_to_dev(ns->disk)->kobj, - &nvm_dev_attr_group); + switch (ns->ndev->identity.ver_id) { + case 1: + sysfs_remove_group(&disk_to_dev(ns->disk)->kobj, + &nvm_dev_attr_group_12); + break; + case 2: + sysfs_remove_group(&disk_to_dev(ns->disk)->kobj, + &nvm_dev_attr_group_20); + break; + } } diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index 94b704a8d83d..b717c000b712 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -184,10 +184,9 @@ struct nvm_id { u16 csecs; u16 sos; - u16 ws_min; - u16 ws_opt; - u16 ws_seq; - u16 ws_per_chk; + u32 ws_min; + u32 ws_opt; + u32 mw_cunits; u32 trdt; u32 trdm; @@ -199,6 +198,10 @@ struct nvm_id { u32 mccap; u16 cpar; + /* calculated values */ + u16 ws_seq; + u16 ws_per_chk; + /* 1.2 compatibility */ u8 mtype; u8 fmtype; -- cgit v1.2.3 From af569398c390810fca773c903a85b71dfd870bb0 Mon Sep 17 00:00:00 2001 From: Matias Bjørling Date: Fri, 30 Mar 2018 00:05:03 +0200 Subject: lightnvm: remove max_rq_size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The field is no longer used. Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 1 - include/linux/lightnvm.h | 2 -- 2 files changed, 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index 521f520a1bb4..a59ad29600c3 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -874,7 +874,6 @@ static int nvm_core_init(struct nvm_dev *dev) geo->sec_size = id->csecs; geo->oob_size = id->sos; geo->mccap = id->mccap; - geo->max_rq_size = dev->ops->max_phys_sect * geo->sec_size; geo->sec_per_chk = id->clba; geo->sec_per_lun = geo->sec_per_chk * geo->nr_chks; diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index b717c000b712..67b4fa8e4906 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -295,8 +295,6 @@ struct nvm_geo { int ws_seq; int ws_per_chk; - int max_rq_size; - int op; struct nvm_addr_format ppaf; -- cgit v1.2.3 From 89a09c5643e01f5e5d3c5f2e720053473a60a90b Mon Sep 17 00:00:00 2001 From: Matias Bjørling Date: Fri, 30 Mar 2018 00:05:04 +0200 Subject: lightnvm: remove nvm_dev_ops->max_phys_sect MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The value of max_phys_sect is always static. Instead of defining it in the nvm_dev_ops structure, declare it as a global value. Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 28 +++++++--------------------- drivers/lightnvm/pblk-init.c | 9 ++++----- drivers/lightnvm/pblk-recovery.c | 8 ++------ drivers/nvme/host/lightnvm.c | 5 +---- include/linux/lightnvm.h | 5 ++--- 5 files changed, 16 insertions(+), 39 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index a59ad29600c3..9704db219866 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -407,7 +407,8 @@ static int nvm_create_tgt(struct nvm_dev *dev, struct nvm_ioctl_create *create) tdisk->private_data = targetdata; tqueue->queuedata = targetdata; - blk_queue_max_hw_sectors(tqueue, 8 * dev->ops->max_phys_sect); + blk_queue_max_hw_sectors(tqueue, + (dev->geo.sec_size >> 9) * NVM_MAX_VLBA); set_capacity(tdisk, tt->capacity(targetdata)); add_disk(tdisk); @@ -719,7 +720,7 @@ int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *tgt_dev, struct ppa_addr *ppas, struct nvm_rq rqd; int ret; - if (nr_ppas > dev->ops->max_phys_sect) { + if (nr_ppas > NVM_MAX_VLBA) { pr_err("nvm: unable to update all blocks atomically\n"); return -EINVAL; } @@ -740,14 +741,6 @@ int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *tgt_dev, struct ppa_addr *ppas, } EXPORT_SYMBOL(nvm_set_tgt_bb_tbl); -int nvm_max_phys_sects(struct nvm_tgt_dev *tgt_dev) -{ - struct nvm_dev *dev = tgt_dev->parent; - - return dev->ops->max_phys_sect; -} -EXPORT_SYMBOL(nvm_max_phys_sects); - int nvm_submit_io(struct nvm_tgt_dev *tgt_dev, struct nvm_rq *rqd) { struct nvm_dev *dev = tgt_dev->parent; @@ -965,17 +958,10 @@ int nvm_register(struct nvm_dev *dev) if (!dev->q || !dev->ops) return -EINVAL; - if (dev->ops->max_phys_sect > 256) { - pr_info("nvm: max sectors supported is 256.\n"); - return -EINVAL; - } - - if (dev->ops->max_phys_sect > 1) { - dev->dma_pool = dev->ops->create_dma_pool(dev, "ppalist"); - if (!dev->dma_pool) { - pr_err("nvm: could not create dma pool\n"); - return -ENOMEM; - } + dev->dma_pool = dev->ops->create_dma_pool(dev, "ppalist"); + if (!dev->dma_pool) { + pr_err("nvm: could not create dma pool\n"); + return -ENOMEM; } ret = nvm_init(dev); diff --git a/drivers/lightnvm/pblk-init.c b/drivers/lightnvm/pblk-init.c index 141036bd6afa..43b835678f48 100644 --- a/drivers/lightnvm/pblk-init.c +++ b/drivers/lightnvm/pblk-init.c @@ -260,8 +260,7 @@ static int pblk_core_init(struct pblk *pblk) return -ENOMEM; /* Internal bios can be at most the sectors signaled by the device. */ - pblk->page_bio_pool = mempool_create_page_pool(nvm_max_phys_sects(dev), - 0); + pblk->page_bio_pool = mempool_create_page_pool(NVM_MAX_VLBA, 0); if (!pblk->page_bio_pool) goto free_global_caches; @@ -716,12 +715,12 @@ static int pblk_lines_init(struct pblk *pblk) pblk->min_write_pgs = geo->sec_per_pl * (geo->sec_size / PAGE_SIZE); max_write_ppas = pblk->min_write_pgs * geo->all_luns; - pblk->max_write_pgs = (max_write_ppas < nvm_max_phys_sects(dev)) ? - max_write_ppas : nvm_max_phys_sects(dev); + pblk->max_write_pgs = min_t(int, max_write_ppas, NVM_MAX_VLBA); pblk_set_sec_per_write(pblk, pblk->min_write_pgs); if (pblk->max_write_pgs > PBLK_MAX_REQ_ADDRS) { - pr_err("pblk: cannot support device max_phys_sect\n"); + pr_err("pblk: vector list too big(%u > %u)\n", + pblk->max_write_pgs, PBLK_MAX_REQ_ADDRS); return -EINVAL; } diff --git a/drivers/lightnvm/pblk-recovery.c b/drivers/lightnvm/pblk-recovery.c index e75a1af2eebe..aaab9a5c17cc 100644 --- a/drivers/lightnvm/pblk-recovery.c +++ b/drivers/lightnvm/pblk-recovery.c @@ -21,17 +21,15 @@ void pblk_submit_rec(struct work_struct *work) struct pblk_rec_ctx *recovery = container_of(work, struct pblk_rec_ctx, ws_rec); struct pblk *pblk = recovery->pblk; - struct nvm_tgt_dev *dev = pblk->dev; struct nvm_rq *rqd = recovery->rqd; struct pblk_c_ctx *c_ctx = nvm_rq_to_pdu(rqd); - int max_secs = nvm_max_phys_sects(dev); struct bio *bio; unsigned int nr_rec_secs; unsigned int pgs_read; int ret; nr_rec_secs = bitmap_weight((unsigned long int *)&rqd->ppa_status, - max_secs); + NVM_MAX_VLBA); bio = bio_alloc(GFP_KERNEL, nr_rec_secs); @@ -74,8 +72,6 @@ int pblk_recov_setup_rq(struct pblk *pblk, struct pblk_c_ctx *c_ctx, struct pblk_rec_ctx *recovery, u64 *comp_bits, unsigned int comp) { - struct nvm_tgt_dev *dev = pblk->dev; - int max_secs = nvm_max_phys_sects(dev); struct nvm_rq *rec_rqd; struct pblk_c_ctx *rec_ctx; int nr_entries = c_ctx->nr_valid + c_ctx->nr_padded; @@ -86,7 +82,7 @@ int pblk_recov_setup_rq(struct pblk *pblk, struct pblk_c_ctx *c_ctx, /* Copy completion bitmap, but exclude the first X completed entries */ bitmap_shift_right((unsigned long int *)&rec_rqd->ppa_status, (unsigned long int *)comp_bits, - comp, max_secs); + comp, NVM_MAX_VLBA); /* Save the context for the entries that need to be re-written and * update current context with the completed entries. diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index 8b243af8a949..e38d835b15b5 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -612,8 +612,6 @@ static struct nvm_dev_ops nvme_nvm_dev_ops = { .destroy_dma_pool = nvme_nvm_destroy_dma_pool, .dev_dma_alloc = nvme_nvm_dev_dma_alloc, .dev_dma_free = nvme_nvm_dev_dma_free, - - .max_phys_sect = 64, }; static int nvme_nvm_submit_user_cmd(struct request_queue *q, @@ -932,8 +930,7 @@ static ssize_t nvm_dev_attr_show_12(struct device *dev, } else if (strcmp(attr->name, "media_capabilities") == 0) { return scnprintf(page, PAGE_SIZE, "0x%08x\n", id->mccap); } else if (strcmp(attr->name, "max_phys_secs") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", - ndev->ops->max_phys_sect); + return scnprintf(page, PAGE_SIZE, "%u\n", NVM_MAX_VLBA); } else { return scnprintf(page, PAGE_SIZE, diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index 67b4fa8e4906..e55b10573c99 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -73,8 +73,6 @@ struct nvm_dev_ops { nvm_destroy_dma_pool_fn *destroy_dma_pool; nvm_dev_dma_alloc_fn *dev_dma_alloc; nvm_dev_dma_free_fn *dev_dma_free; - - unsigned int max_phys_sect; }; #ifdef CONFIG_NVM @@ -228,6 +226,8 @@ struct nvm_target { #define NVM_VERSION_MINOR 0 #define NVM_VERSION_PATCH 0 +#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */ + struct nvm_rq; typedef void (nvm_end_io_fn)(struct nvm_rq *); @@ -436,7 +436,6 @@ extern void nvm_unregister(struct nvm_dev *); extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *, int, int); -extern int nvm_max_phys_sects(struct nvm_tgt_dev *); extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *); extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *); extern void nvm_end_io(struct nvm_rq *); -- cgit v1.2.3 From e46f4e4822bdecf9bcbc2e71b2a3ae7f37464a2d Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:10 +0200 Subject: lightnvm: simplify geometry structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, the device geometry is stored redundantly in the nvm_id and nvm_geo structures at a device level. Moreover, when instantiating targets on a specific number of LUNs, these structures are replicated and manually modified to fit the instance channel and LUN partitioning. Instead, create a generic geometry around nvm_geo, which can be used by (i) the underlying device to describe the geometry of the whole device, and (ii) instances to describe their geometry independently. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 70 +++----- drivers/lightnvm/pblk-core.c | 16 +- drivers/lightnvm/pblk-gc.c | 2 +- drivers/lightnvm/pblk-init.c | 117 +++++++------- drivers/lightnvm/pblk-read.c | 2 +- drivers/lightnvm/pblk-recovery.c | 14 +- drivers/lightnvm/pblk-rl.c | 2 +- drivers/lightnvm/pblk-sysfs.c | 35 ++-- drivers/lightnvm/pblk-write.c | 2 +- drivers/lightnvm/pblk.h | 83 ++++------ drivers/nvme/host/lightnvm.c | 337 +++++++++++++++++++++++---------------- include/linux/lightnvm.h | 196 +++++++++++------------ 12 files changed, 451 insertions(+), 425 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index c4f12b1ae8b8..9dec936ac1dc 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -155,7 +155,7 @@ static struct nvm_tgt_dev *nvm_create_tgt_dev(struct nvm_dev *dev, int blun = lun_begin % dev->geo.nr_luns; int lunid = 0; int lun_balanced = 1; - int prev_nr_luns; + int sec_per_lun, prev_nr_luns; int i, j; nr_chnls = (nr_chnls_mod == 0) ? nr_chnls : nr_chnls + 1; @@ -215,18 +215,23 @@ static struct nvm_tgt_dev *nvm_create_tgt_dev(struct nvm_dev *dev, if (!tgt_dev) goto err_ch; + /* Inherit device geometry from parent */ memcpy(&tgt_dev->geo, &dev->geo, sizeof(struct nvm_geo)); + /* Target device only owns a portion of the physical device */ tgt_dev->geo.nr_chnls = nr_chnls; - tgt_dev->geo.all_luns = nr_luns; tgt_dev->geo.nr_luns = (lun_balanced) ? prev_nr_luns : -1; + tgt_dev->geo.all_luns = nr_luns; + tgt_dev->geo.all_chunks = nr_luns * dev->geo.nr_chks; + tgt_dev->geo.op = op; - tgt_dev->total_secs = nr_luns * tgt_dev->geo.sec_per_lun; + + sec_per_lun = dev->geo.clba * dev->geo.nr_chks; + tgt_dev->geo.total_secs = nr_luns * sec_per_lun; + tgt_dev->q = dev->q; tgt_dev->map = dev_map; tgt_dev->luns = luns; - memcpy(&tgt_dev->identity, &dev->identity, sizeof(struct nvm_id)); - tgt_dev->parent = dev; return tgt_dev; @@ -296,8 +301,6 @@ static int __nvm_config_simple(struct nvm_dev *dev, static int __nvm_config_extended(struct nvm_dev *dev, struct nvm_ioctl_create_extended *e) { - struct nvm_geo *geo = &dev->geo; - if (e->lun_begin == 0xFFFF && e->lun_end == 0xFFFF) { e->lun_begin = 0; e->lun_end = dev->geo.all_luns - 1; @@ -311,7 +314,7 @@ static int __nvm_config_extended(struct nvm_dev *dev, return -EINVAL; } - return nvm_config_check_luns(geo, e->lun_begin, e->lun_end); + return nvm_config_check_luns(&dev->geo, e->lun_begin, e->lun_end); } static int nvm_create_tgt(struct nvm_dev *dev, struct nvm_ioctl_create *create) @@ -406,7 +409,7 @@ static int nvm_create_tgt(struct nvm_dev *dev, struct nvm_ioctl_create *create) tqueue->queuedata = targetdata; blk_queue_max_hw_sectors(tqueue, - (dev->geo.sec_size >> 9) * NVM_MAX_VLBA); + (dev->geo.csecs >> 9) * NVM_MAX_VLBA); set_capacity(tdisk, tt->capacity(targetdata)); add_disk(tdisk); @@ -841,40 +844,9 @@ EXPORT_SYMBOL(nvm_get_tgt_bb_tbl); static int nvm_core_init(struct nvm_dev *dev) { - struct nvm_id *id = &dev->identity; struct nvm_geo *geo = &dev->geo; int ret; - memcpy(&geo->ppaf, &id->ppaf, sizeof(struct nvm_addr_format)); - - if (id->mtype != 0) { - pr_err("nvm: memory type not supported\n"); - return -EINVAL; - } - - /* Whole device values */ - geo->nr_chnls = id->num_ch; - geo->nr_luns = id->num_lun; - - /* Generic device geometry values */ - geo->ws_min = id->ws_min; - geo->ws_opt = id->ws_opt; - geo->ws_seq = id->ws_seq; - geo->ws_per_chk = id->ws_per_chk; - geo->nr_chks = id->num_chk; - geo->mccap = id->mccap; - - geo->sec_per_chk = id->clba; - geo->sec_per_lun = geo->sec_per_chk * geo->nr_chks; - geo->all_luns = geo->nr_luns * geo->nr_chnls; - - /* 1.2 spec device geometry values */ - geo->plane_mode = 1 << geo->ws_seq; - geo->nr_planes = geo->ws_opt / geo->ws_min; - geo->sec_per_pg = geo->ws_min; - geo->sec_per_pl = geo->sec_per_pg * geo->nr_planes; - - dev->total_secs = geo->all_luns * geo->sec_per_lun; dev->lun_map = kcalloc(BITS_TO_LONGS(geo->all_luns), sizeof(unsigned long), GFP_KERNEL); if (!dev->lun_map) @@ -913,16 +885,14 @@ static int nvm_init(struct nvm_dev *dev) struct nvm_geo *geo = &dev->geo; int ret = -EINVAL; - if (dev->ops->identity(dev, &dev->identity)) { + if (dev->ops->identity(dev)) { pr_err("nvm: device could not be identified\n"); goto err; } - if (dev->identity.ver_id != 1 && dev->identity.ver_id != 2) { - pr_err("nvm: device ver_id %d not supported by kernel.\n", - dev->identity.ver_id); - goto err; - } + pr_debug("nvm: ver:%u nvm_vendor:%x\n", + geo->ver_id, + geo->vmnt); ret = nvm_core_init(dev); if (ret) { @@ -930,10 +900,10 @@ static int nvm_init(struct nvm_dev *dev) goto err; } - pr_info("nvm: registered %s [%u/%u/%u/%u/%u/%u]\n", - dev->name, geo->sec_per_pg, geo->nr_planes, - geo->ws_per_chk, geo->nr_chks, - geo->all_luns, geo->nr_chnls); + pr_info("nvm: registered %s [%u/%u/%u/%u/%u]\n", + dev->name, geo->ws_min, geo->ws_opt, + geo->nr_chks, geo->all_luns, + geo->nr_chnls); return 0; err: pr_err("nvm: failed to initialize nvm\n"); diff --git a/drivers/lightnvm/pblk-core.c b/drivers/lightnvm/pblk-core.c index 5c363ccde0e3..52c0c3e5ec6e 100644 --- a/drivers/lightnvm/pblk-core.c +++ b/drivers/lightnvm/pblk-core.c @@ -613,7 +613,7 @@ next_rq: memset(&rqd, 0, sizeof(struct nvm_rq)); rq_ppas = pblk_calc_secs(pblk, left_ppas, 0); - rq_len = rq_ppas * geo->sec_size; + rq_len = rq_ppas * geo->csecs; bio = pblk_bio_map_addr(pblk, emeta_buf, rq_ppas, rq_len, l_mg->emeta_alloc_type, GFP_KERNEL); @@ -722,7 +722,7 @@ u64 pblk_line_smeta_start(struct pblk *pblk, struct pblk_line *line) if (bit >= lm->blk_per_line) return -1; - return bit * geo->sec_per_pl; + return bit * geo->ws_opt; } static int pblk_line_submit_smeta_io(struct pblk *pblk, struct pblk_line *line, @@ -1034,17 +1034,17 @@ static int pblk_line_init_bb(struct pblk *pblk, struct pblk_line *line, /* Capture bad block information on line mapping bitmaps */ while ((bit = find_next_bit(line->blk_bitmap, lm->blk_per_line, bit + 1)) < lm->blk_per_line) { - off = bit * geo->sec_per_pl; + off = bit * geo->ws_opt; bitmap_shift_left(l_mg->bb_aux, l_mg->bb_template, off, lm->sec_per_line); bitmap_or(line->map_bitmap, line->map_bitmap, l_mg->bb_aux, lm->sec_per_line); - line->sec_in_line -= geo->sec_per_chk; + line->sec_in_line -= geo->clba; } /* Mark smeta metadata sectors as bad sectors */ bit = find_first_zero_bit(line->blk_bitmap, lm->blk_per_line); - off = bit * geo->sec_per_pl; + off = bit * geo->ws_opt; bitmap_set(line->map_bitmap, off, lm->smeta_sec); line->sec_in_line -= lm->smeta_sec; line->smeta_ssec = off; @@ -1063,10 +1063,10 @@ static int pblk_line_init_bb(struct pblk *pblk, struct pblk_line *line, emeta_secs = lm->emeta_sec[0]; off = lm->sec_per_line; while (emeta_secs) { - off -= geo->sec_per_pl; + off -= geo->ws_opt; if (!test_bit(off, line->invalid_bitmap)) { - bitmap_set(line->invalid_bitmap, off, geo->sec_per_pl); - emeta_secs -= geo->sec_per_pl; + bitmap_set(line->invalid_bitmap, off, geo->ws_opt); + emeta_secs -= geo->ws_opt; } } diff --git a/drivers/lightnvm/pblk-gc.c b/drivers/lightnvm/pblk-gc.c index 31f17d6f14ee..7143b0f740fb 100644 --- a/drivers/lightnvm/pblk-gc.c +++ b/drivers/lightnvm/pblk-gc.c @@ -88,7 +88,7 @@ static void pblk_gc_line_ws(struct work_struct *work) up(&gc->gc_sem); - gc_rq->data = vmalloc(gc_rq->nr_secs * geo->sec_size); + gc_rq->data = vmalloc(gc_rq->nr_secs * geo->csecs); if (!gc_rq->data) { pr_err("pblk: could not GC line:%d (%d/%d)\n", line->id, *line->vsc, gc_rq->nr_secs); diff --git a/drivers/lightnvm/pblk-init.c b/drivers/lightnvm/pblk-init.c index 8f1d622801df..2fca27d0a9b5 100644 --- a/drivers/lightnvm/pblk-init.c +++ b/drivers/lightnvm/pblk-init.c @@ -179,7 +179,7 @@ static int pblk_rwb_init(struct pblk *pblk) return -ENOMEM; power_size = get_count_order(nr_entries); - power_seg_sz = get_count_order(geo->sec_size); + power_seg_sz = get_count_order(geo->csecs); return pblk_rb_init(&pblk->rwb, entries, power_size, power_seg_sz); } @@ -187,18 +187,10 @@ static int pblk_rwb_init(struct pblk *pblk) /* Minimum pages needed within a lun */ #define ADDR_POOL_SIZE 64 -static int pblk_set_ppaf(struct pblk *pblk) +static int pblk_set_addrf_12(struct nvm_geo *geo, struct nvm_addrf_12 *dst) { - struct nvm_tgt_dev *dev = pblk->dev; - struct nvm_geo *geo = &dev->geo; - struct nvm_addr_format ppaf = geo->ppaf; - int mod, power_len; - - div_u64_rem(geo->sec_per_chk, pblk->min_write_pgs, &mod); - if (mod) { - pr_err("pblk: bad configuration of sectors/pages\n"); - return -EINVAL; - } + struct nvm_addrf_12 *src = (struct nvm_addrf_12 *)&geo->addrf; + int power_len; /* Re-calculate channel and lun format to adapt to configuration */ power_len = get_count_order(geo->nr_chnls); @@ -206,34 +198,50 @@ static int pblk_set_ppaf(struct pblk *pblk) pr_err("pblk: supports only power-of-two channel config.\n"); return -EINVAL; } - ppaf.ch_len = power_len; + dst->ch_len = power_len; power_len = get_count_order(geo->nr_luns); if (1 << power_len != geo->nr_luns) { pr_err("pblk: supports only power-of-two LUN config.\n"); return -EINVAL; } - ppaf.lun_len = power_len; - - pblk->ppaf.sec_offset = 0; - pblk->ppaf.pln_offset = ppaf.sect_len; - pblk->ppaf.ch_offset = pblk->ppaf.pln_offset + ppaf.pln_len; - pblk->ppaf.lun_offset = pblk->ppaf.ch_offset + ppaf.ch_len; - pblk->ppaf.pg_offset = pblk->ppaf.lun_offset + ppaf.lun_len; - pblk->ppaf.blk_offset = pblk->ppaf.pg_offset + ppaf.pg_len; - pblk->ppaf.sec_mask = (1ULL << ppaf.sect_len) - 1; - pblk->ppaf.pln_mask = ((1ULL << ppaf.pln_len) - 1) << - pblk->ppaf.pln_offset; - pblk->ppaf.ch_mask = ((1ULL << ppaf.ch_len) - 1) << - pblk->ppaf.ch_offset; - pblk->ppaf.lun_mask = ((1ULL << ppaf.lun_len) - 1) << - pblk->ppaf.lun_offset; - pblk->ppaf.pg_mask = ((1ULL << ppaf.pg_len) - 1) << - pblk->ppaf.pg_offset; - pblk->ppaf.blk_mask = ((1ULL << ppaf.blk_len) - 1) << - pblk->ppaf.blk_offset; - - pblk->ppaf_bitsize = pblk->ppaf.blk_offset + ppaf.blk_len; + dst->lun_len = power_len; + + dst->blk_len = src->blk_len; + dst->pg_len = src->pg_len; + dst->pln_len = src->pln_len; + dst->sect_len = src->sect_len; + + dst->sect_offset = 0; + dst->pln_offset = dst->sect_len; + dst->ch_offset = dst->pln_offset + dst->pln_len; + dst->lun_offset = dst->ch_offset + dst->ch_len; + dst->pg_offset = dst->lun_offset + dst->lun_len; + dst->blk_offset = dst->pg_offset + dst->pg_len; + + dst->sec_mask = ((1ULL << dst->sect_len) - 1) << dst->sect_offset; + dst->pln_mask = ((1ULL << dst->pln_len) - 1) << dst->pln_offset; + dst->ch_mask = ((1ULL << dst->ch_len) - 1) << dst->ch_offset; + dst->lun_mask = ((1ULL << dst->lun_len) - 1) << dst->lun_offset; + dst->pg_mask = ((1ULL << dst->pg_len) - 1) << dst->pg_offset; + dst->blk_mask = ((1ULL << dst->blk_len) - 1) << dst->blk_offset; + + return dst->blk_offset + src->blk_len; +} + +static int pblk_set_ppaf(struct pblk *pblk) +{ + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + int mod; + + div_u64_rem(geo->clba, pblk->min_write_pgs, &mod); + if (mod) { + pr_err("pblk: bad configuration of sectors/pages\n"); + return -EINVAL; + } + + pblk->ppaf_bitsize = pblk_set_addrf_12(geo, (void *)&pblk->ppaf); return 0; } @@ -303,10 +311,9 @@ static int pblk_core_init(struct pblk *pblk) atomic64_set(&pblk->nr_flush, 0); pblk->nr_flush_rst = 0; - pblk->pgs_in_buffer = NVM_MEM_PAGE_WRITE * geo->sec_per_pg * - geo->nr_planes * geo->all_luns; + pblk->pgs_in_buffer = geo->mw_cunits * geo->all_luns; - pblk->min_write_pgs = geo->sec_per_pl * (geo->sec_size / PAGE_SIZE); + pblk->min_write_pgs = geo->ws_opt * (geo->csecs / PAGE_SIZE); max_write_ppas = pblk->min_write_pgs * geo->all_luns; pblk->max_write_pgs = min_t(int, max_write_ppas, NVM_MAX_VLBA); pblk_set_sec_per_write(pblk, pblk->min_write_pgs); @@ -583,18 +590,18 @@ static unsigned int calc_emeta_len(struct pblk *pblk) /* Round to sector size so that lba_list starts on its own sector */ lm->emeta_sec[1] = DIV_ROUND_UP( sizeof(struct line_emeta) + lm->blk_bitmap_len + - sizeof(struct wa_counters), geo->sec_size); - lm->emeta_len[1] = lm->emeta_sec[1] * geo->sec_size; + sizeof(struct wa_counters), geo->csecs); + lm->emeta_len[1] = lm->emeta_sec[1] * geo->csecs; /* Round to sector size so that vsc_list starts on its own sector */ lm->dsec_per_line = lm->sec_per_line - lm->emeta_sec[0]; lm->emeta_sec[2] = DIV_ROUND_UP(lm->dsec_per_line * sizeof(u64), - geo->sec_size); - lm->emeta_len[2] = lm->emeta_sec[2] * geo->sec_size; + geo->csecs); + lm->emeta_len[2] = lm->emeta_sec[2] * geo->csecs; lm->emeta_sec[3] = DIV_ROUND_UP(l_mg->nr_lines * sizeof(u32), - geo->sec_size); - lm->emeta_len[3] = lm->emeta_sec[3] * geo->sec_size; + geo->csecs); + lm->emeta_len[3] = lm->emeta_sec[3] * geo->csecs; lm->vsc_list_len = l_mg->nr_lines * sizeof(u32); @@ -625,13 +632,13 @@ static void pblk_set_provision(struct pblk *pblk, long nr_free_blks) * on user capacity consider only provisioned blocks */ pblk->rl.total_blocks = nr_free_blks; - pblk->rl.nr_secs = nr_free_blks * geo->sec_per_chk; + pblk->rl.nr_secs = nr_free_blks * geo->clba; /* Consider sectors used for metadata */ sec_meta = (lm->smeta_sec + lm->emeta_sec[0]) * l_mg->nr_free_lines; - blk_meta = DIV_ROUND_UP(sec_meta, geo->sec_per_chk); + blk_meta = DIV_ROUND_UP(sec_meta, geo->clba); - pblk->capacity = (provisioned - blk_meta) * geo->sec_per_chk; + pblk->capacity = (provisioned - blk_meta) * geo->clba; atomic_set(&pblk->rl.free_blocks, nr_free_blks); atomic_set(&pblk->rl.free_user_blocks, nr_free_blks); @@ -783,7 +790,7 @@ static int pblk_line_meta_init(struct pblk *pblk) unsigned int smeta_len, emeta_len; int i; - lm->sec_per_line = geo->sec_per_chk * geo->all_luns; + lm->sec_per_line = geo->clba * geo->all_luns; lm->blk_per_line = geo->all_luns; lm->blk_bitmap_len = BITS_TO_LONGS(geo->all_luns) * sizeof(long); lm->sec_bitmap_len = BITS_TO_LONGS(lm->sec_per_line) * sizeof(long); @@ -797,8 +804,8 @@ static int pblk_line_meta_init(struct pblk *pblk) */ i = 1; add_smeta_page: - lm->smeta_sec = i * geo->sec_per_pl; - lm->smeta_len = lm->smeta_sec * geo->sec_size; + lm->smeta_sec = i * geo->ws_opt; + lm->smeta_len = lm->smeta_sec * geo->csecs; smeta_len = sizeof(struct line_smeta) + lm->lun_bitmap_len; if (smeta_len > lm->smeta_len) { @@ -811,8 +818,8 @@ add_smeta_page: */ i = 1; add_emeta_page: - lm->emeta_sec[0] = i * geo->sec_per_pl; - lm->emeta_len[0] = lm->emeta_sec[0] * geo->sec_size; + lm->emeta_sec[0] = i * geo->ws_opt; + lm->emeta_len[0] = lm->emeta_sec[0] * geo->csecs; emeta_len = calc_emeta_len(pblk); if (emeta_len > lm->emeta_len[0]) { @@ -825,7 +832,7 @@ add_emeta_page: lm->min_blk_line = 1; if (geo->all_luns > 1) lm->min_blk_line += DIV_ROUND_UP(lm->smeta_sec + - lm->emeta_sec[0], geo->sec_per_chk); + lm->emeta_sec[0], geo->clba); if (lm->min_blk_line > lm->blk_per_line) { pr_err("pblk: config. not supported. Min. LUN in line:%d\n", @@ -1009,9 +1016,9 @@ static void *pblk_init(struct nvm_tgt_dev *dev, struct gendisk *tdisk, struct pblk *pblk; int ret; - if (dev->identity.dom & NVM_RSP_L2P) { + if (dev->geo.dom & NVM_RSP_L2P) { pr_err("pblk: host-side L2P table not supported. (%x)\n", - dev->identity.dom); + dev->geo.dom); return ERR_PTR(-EINVAL); } @@ -1093,7 +1100,7 @@ static void *pblk_init(struct nvm_tgt_dev *dev, struct gendisk *tdisk, blk_queue_write_cache(tqueue, true, false); - tqueue->limits.discard_granularity = geo->sec_per_chk * geo->sec_size; + tqueue->limits.discard_granularity = geo->clba * geo->csecs; tqueue->limits.discard_alignment = 0; blk_queue_max_discard_sectors(tqueue, UINT_MAX >> 9); blk_queue_flag_set(QUEUE_FLAG_DISCARD, tqueue); diff --git a/drivers/lightnvm/pblk-read.c b/drivers/lightnvm/pblk-read.c index 2f761283f43e..9eee10f69df0 100644 --- a/drivers/lightnvm/pblk-read.c +++ b/drivers/lightnvm/pblk-read.c @@ -563,7 +563,7 @@ int pblk_submit_read_gc(struct pblk *pblk, struct pblk_gc_rq *gc_rq) if (!(gc_rq->secs_to_gc)) goto out; - data_len = (gc_rq->secs_to_gc) * geo->sec_size; + data_len = (gc_rq->secs_to_gc) * geo->csecs; bio = pblk_bio_map_addr(pblk, gc_rq->data, gc_rq->secs_to_gc, data_len, PBLK_VMALLOC_META, GFP_KERNEL); if (IS_ERR(bio)) { diff --git a/drivers/lightnvm/pblk-recovery.c b/drivers/lightnvm/pblk-recovery.c index aaab9a5c17cc..26356429dc72 100644 --- a/drivers/lightnvm/pblk-recovery.c +++ b/drivers/lightnvm/pblk-recovery.c @@ -184,7 +184,7 @@ static int pblk_calc_sec_in_line(struct pblk *pblk, struct pblk_line *line) int nr_bb = bitmap_weight(line->blk_bitmap, lm->blk_per_line); return lm->sec_per_line - lm->smeta_sec - lm->emeta_sec[0] - - nr_bb * geo->sec_per_chk; + nr_bb * geo->clba; } struct pblk_recov_alloc { @@ -232,7 +232,7 @@ next_read_rq: rq_ppas = pblk_calc_secs(pblk, left_ppas, 0); if (!rq_ppas) rq_ppas = pblk->min_write_pgs; - rq_len = rq_ppas * geo->sec_size; + rq_len = rq_ppas * geo->csecs; bio = bio_map_kern(dev->q, data, rq_len, GFP_KERNEL); if (IS_ERR(bio)) @@ -351,7 +351,7 @@ static int pblk_recov_pad_oob(struct pblk *pblk, struct pblk_line *line, if (!pad_rq) return -ENOMEM; - data = vzalloc(pblk->max_write_pgs * geo->sec_size); + data = vzalloc(pblk->max_write_pgs * geo->csecs); if (!data) { ret = -ENOMEM; goto free_rq; @@ -368,7 +368,7 @@ next_pad_rq: goto fail_free_pad; } - rq_len = rq_ppas * geo->sec_size; + rq_len = rq_ppas * geo->csecs; meta_list = nvm_dev_dma_alloc(dev->parent, GFP_KERNEL, &dma_meta_list); if (!meta_list) { @@ -509,7 +509,7 @@ next_rq: rq_ppas = pblk_calc_secs(pblk, left_ppas, 0); if (!rq_ppas) rq_ppas = pblk->min_write_pgs; - rq_len = rq_ppas * geo->sec_size; + rq_len = rq_ppas * geo->csecs; bio = bio_map_kern(dev->q, data, rq_len, GFP_KERNEL); if (IS_ERR(bio)) @@ -640,7 +640,7 @@ next_rq: rq_ppas = pblk_calc_secs(pblk, left_ppas, 0); if (!rq_ppas) rq_ppas = pblk->min_write_pgs; - rq_len = rq_ppas * geo->sec_size; + rq_len = rq_ppas * geo->csecs; bio = bio_map_kern(dev->q, data, rq_len, GFP_KERNEL); if (IS_ERR(bio)) @@ -745,7 +745,7 @@ static int pblk_recov_l2p_from_oob(struct pblk *pblk, struct pblk_line *line) ppa_list = (void *)(meta_list) + pblk_dma_meta_size; dma_ppa_list = dma_meta_list + pblk_dma_meta_size; - data = kcalloc(pblk->max_write_pgs, geo->sec_size, GFP_KERNEL); + data = kcalloc(pblk->max_write_pgs, geo->csecs, GFP_KERNEL); if (!data) { ret = -ENOMEM; goto free_meta_list; diff --git a/drivers/lightnvm/pblk-rl.c b/drivers/lightnvm/pblk-rl.c index 0d457b162f23..883a7113b19d 100644 --- a/drivers/lightnvm/pblk-rl.c +++ b/drivers/lightnvm/pblk-rl.c @@ -200,7 +200,7 @@ void pblk_rl_init(struct pblk_rl *rl, int budget) /* Consider sectors used for metadata */ sec_meta = (lm->smeta_sec + lm->emeta_sec[0]) * l_mg->nr_free_lines; - blk_meta = DIV_ROUND_UP(sec_meta, geo->sec_per_chk); + blk_meta = DIV_ROUND_UP(sec_meta, geo->clba); rl->high = pblk->op_blks - blk_meta - lm->blk_per_line; rl->high_pw = get_count_order(rl->high); diff --git a/drivers/lightnvm/pblk-sysfs.c b/drivers/lightnvm/pblk-sysfs.c index c2cf6c939752..2474ef4366fa 100644 --- a/drivers/lightnvm/pblk-sysfs.c +++ b/drivers/lightnvm/pblk-sysfs.c @@ -113,26 +113,31 @@ static ssize_t pblk_sysfs_ppaf(struct pblk *pblk, char *page) { struct nvm_tgt_dev *dev = pblk->dev; struct nvm_geo *geo = &dev->geo; + struct nvm_addrf_12 *ppaf; + struct nvm_addrf_12 *geo_ppaf; ssize_t sz = 0; - sz = snprintf(page, PAGE_SIZE - sz, + ppaf = (struct nvm_addrf_12 *)&pblk->ppaf; + geo_ppaf = (struct nvm_addrf_12 *)&geo->addrf; + + sz = snprintf(page, PAGE_SIZE, "g:(b:%d)blk:%d/%d,pg:%d/%d,lun:%d/%d,ch:%d/%d,pl:%d/%d,sec:%d/%d\n", - pblk->ppaf_bitsize, - pblk->ppaf.blk_offset, geo->ppaf.blk_len, - pblk->ppaf.pg_offset, geo->ppaf.pg_len, - pblk->ppaf.lun_offset, geo->ppaf.lun_len, - pblk->ppaf.ch_offset, geo->ppaf.ch_len, - pblk->ppaf.pln_offset, geo->ppaf.pln_len, - pblk->ppaf.sec_offset, geo->ppaf.sect_len); + pblk->ppaf_bitsize, + ppaf->blk_offset, ppaf->blk_len, + ppaf->pg_offset, ppaf->pg_len, + ppaf->lun_offset, ppaf->lun_len, + ppaf->ch_offset, ppaf->ch_len, + ppaf->pln_offset, ppaf->pln_len, + ppaf->sect_offset, ppaf->sect_len); sz += snprintf(page + sz, PAGE_SIZE - sz, "d:blk:%d/%d,pg:%d/%d,lun:%d/%d,ch:%d/%d,pl:%d/%d,sec:%d/%d\n", - geo->ppaf.blk_offset, geo->ppaf.blk_len, - geo->ppaf.pg_offset, geo->ppaf.pg_len, - geo->ppaf.lun_offset, geo->ppaf.lun_len, - geo->ppaf.ch_offset, geo->ppaf.ch_len, - geo->ppaf.pln_offset, geo->ppaf.pln_len, - geo->ppaf.sect_offset, geo->ppaf.sect_len); + geo_ppaf->blk_offset, geo_ppaf->blk_len, + geo_ppaf->pg_offset, geo_ppaf->pg_len, + geo_ppaf->lun_offset, geo_ppaf->lun_len, + geo_ppaf->ch_offset, geo_ppaf->ch_len, + geo_ppaf->pln_offset, geo_ppaf->pln_len, + geo_ppaf->sect_offset, geo_ppaf->sect_len); return sz; } @@ -288,7 +293,7 @@ static ssize_t pblk_sysfs_lines_info(struct pblk *pblk, char *page) "blk_line:%d, sec_line:%d, sec_blk:%d\n", lm->blk_per_line, lm->sec_per_line, - geo->sec_per_chk); + geo->clba); return sz; } diff --git a/drivers/lightnvm/pblk-write.c b/drivers/lightnvm/pblk-write.c index aae86ed60b98..3e6f1ebd743a 100644 --- a/drivers/lightnvm/pblk-write.c +++ b/drivers/lightnvm/pblk-write.c @@ -333,7 +333,7 @@ int pblk_submit_meta_io(struct pblk *pblk, struct pblk_line *meta_line) m_ctx = nvm_rq_to_pdu(rqd); m_ctx->private = meta_line; - rq_len = rq_ppas * geo->sec_size; + rq_len = rq_ppas * geo->csecs; data = ((void *)emeta->buf) + emeta->mem; bio = pblk_bio_map_addr(pblk, data, rq_ppas, rq_len, diff --git a/drivers/lightnvm/pblk.h b/drivers/lightnvm/pblk.h index f0309d8172c0..898c4e49f77d 100644 --- a/drivers/lightnvm/pblk.h +++ b/drivers/lightnvm/pblk.h @@ -551,21 +551,6 @@ struct pblk_line_meta { unsigned int meta_distance; /* Distance between data and metadata */ }; -struct pblk_addr_format { - u64 ch_mask; - u64 lun_mask; - u64 pln_mask; - u64 blk_mask; - u64 pg_mask; - u64 sec_mask; - u8 ch_offset; - u8 lun_offset; - u8 pln_offset; - u8 blk_offset; - u8 pg_offset; - u8 sec_offset; -}; - enum { PBLK_STATE_RUNNING = 0, PBLK_STATE_STOPPING = 1, @@ -585,8 +570,8 @@ struct pblk { struct pblk_line_mgmt l_mg; /* Line management */ struct pblk_line_meta lm; /* Line metadata */ + struct nvm_addrf ppaf; int ppaf_bitsize; - struct pblk_addr_format ppaf; struct pblk_rb rwb; @@ -941,14 +926,12 @@ static inline int pblk_line_vsc(struct pblk_line *line) return le32_to_cpu(*line->vsc); } -#define NVM_MEM_PAGE_WRITE (8) - static inline int pblk_pad_distance(struct pblk *pblk) { struct nvm_tgt_dev *dev = pblk->dev; struct nvm_geo *geo = &dev->geo; - return NVM_MEM_PAGE_WRITE * geo->all_luns * geo->sec_per_pl; + return geo->mw_cunits * geo->all_luns * geo->ws_opt; } static inline int pblk_ppa_to_line(struct ppa_addr p) @@ -964,15 +947,16 @@ static inline int pblk_ppa_to_pos(struct nvm_geo *geo, struct ppa_addr p) static inline struct ppa_addr addr_to_gen_ppa(struct pblk *pblk, u64 paddr, u64 line_id) { + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&pblk->ppaf; struct ppa_addr ppa; ppa.ppa = 0; ppa.g.blk = line_id; - ppa.g.pg = (paddr & pblk->ppaf.pg_mask) >> pblk->ppaf.pg_offset; - ppa.g.lun = (paddr & pblk->ppaf.lun_mask) >> pblk->ppaf.lun_offset; - ppa.g.ch = (paddr & pblk->ppaf.ch_mask) >> pblk->ppaf.ch_offset; - ppa.g.pl = (paddr & pblk->ppaf.pln_mask) >> pblk->ppaf.pln_offset; - ppa.g.sec = (paddr & pblk->ppaf.sec_mask) >> pblk->ppaf.sec_offset; + ppa.g.pg = (paddr & ppaf->pg_mask) >> ppaf->pg_offset; + ppa.g.lun = (paddr & ppaf->lun_mask) >> ppaf->lun_offset; + ppa.g.ch = (paddr & ppaf->ch_mask) >> ppaf->ch_offset; + ppa.g.pl = (paddr & ppaf->pln_mask) >> ppaf->pln_offset; + ppa.g.sec = (paddr & ppaf->sec_mask) >> ppaf->sect_offset; return ppa; } @@ -980,13 +964,14 @@ static inline struct ppa_addr addr_to_gen_ppa(struct pblk *pblk, u64 paddr, static inline u64 pblk_dev_ppa_to_line_addr(struct pblk *pblk, struct ppa_addr p) { + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&pblk->ppaf; u64 paddr; - paddr = (u64)p.g.pg << pblk->ppaf.pg_offset; - paddr |= (u64)p.g.lun << pblk->ppaf.lun_offset; - paddr |= (u64)p.g.ch << pblk->ppaf.ch_offset; - paddr |= (u64)p.g.pl << pblk->ppaf.pln_offset; - paddr |= (u64)p.g.sec << pblk->ppaf.sec_offset; + paddr = (u64)p.g.ch << ppaf->ch_offset; + paddr |= (u64)p.g.lun << ppaf->lun_offset; + paddr |= (u64)p.g.pg << ppaf->pg_offset; + paddr |= (u64)p.g.pl << ppaf->pln_offset; + paddr |= (u64)p.g.sec << ppaf->sect_offset; return paddr; } @@ -1003,18 +988,14 @@ static inline struct ppa_addr pblk_ppa32_to_ppa64(struct pblk *pblk, u32 ppa32) ppa64.c.line = ppa32 & ((~0U) >> 1); ppa64.c.is_cached = 1; } else { - ppa64.g.blk = (ppa32 & pblk->ppaf.blk_mask) >> - pblk->ppaf.blk_offset; - ppa64.g.pg = (ppa32 & pblk->ppaf.pg_mask) >> - pblk->ppaf.pg_offset; - ppa64.g.lun = (ppa32 & pblk->ppaf.lun_mask) >> - pblk->ppaf.lun_offset; - ppa64.g.ch = (ppa32 & pblk->ppaf.ch_mask) >> - pblk->ppaf.ch_offset; - ppa64.g.pl = (ppa32 & pblk->ppaf.pln_mask) >> - pblk->ppaf.pln_offset; - ppa64.g.sec = (ppa32 & pblk->ppaf.sec_mask) >> - pblk->ppaf.sec_offset; + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&pblk->ppaf; + + ppa64.g.ch = (ppa32 & ppaf->ch_mask) >> ppaf->ch_offset; + ppa64.g.lun = (ppa32 & ppaf->lun_mask) >> ppaf->lun_offset; + ppa64.g.blk = (ppa32 & ppaf->blk_mask) >> ppaf->blk_offset; + ppa64.g.pg = (ppa32 & ppaf->pg_mask) >> ppaf->pg_offset; + ppa64.g.pl = (ppa32 & ppaf->pln_mask) >> ppaf->pln_offset; + ppa64.g.sec = (ppa32 & ppaf->sec_mask) >> ppaf->sect_offset; } return ppa64; @@ -1030,12 +1011,14 @@ static inline u32 pblk_ppa64_to_ppa32(struct pblk *pblk, struct ppa_addr ppa64) ppa32 |= ppa64.c.line; ppa32 |= 1U << 31; } else { - ppa32 |= ppa64.g.blk << pblk->ppaf.blk_offset; - ppa32 |= ppa64.g.pg << pblk->ppaf.pg_offset; - ppa32 |= ppa64.g.lun << pblk->ppaf.lun_offset; - ppa32 |= ppa64.g.ch << pblk->ppaf.ch_offset; - ppa32 |= ppa64.g.pl << pblk->ppaf.pln_offset; - ppa32 |= ppa64.g.sec << pblk->ppaf.sec_offset; + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&pblk->ppaf; + + ppa32 |= ppa64.g.ch << ppaf->ch_offset; + ppa32 |= ppa64.g.lun << ppaf->lun_offset; + ppa32 |= ppa64.g.blk << ppaf->blk_offset; + ppa32 |= ppa64.g.pg << ppaf->pg_offset; + ppa32 |= ppa64.g.pl << ppaf->pln_offset; + ppa32 |= ppa64.g.sec << ppaf->sect_offset; } return ppa32; @@ -1229,10 +1212,10 @@ static inline int pblk_boundary_ppa_checks(struct nvm_tgt_dev *tgt_dev, if (!ppa->c.is_cached && ppa->g.ch < geo->nr_chnls && ppa->g.lun < geo->nr_luns && - ppa->g.pl < geo->nr_planes && + ppa->g.pl < geo->num_pln && ppa->g.blk < geo->nr_chks && - ppa->g.pg < geo->ws_per_chk && - ppa->g.sec < geo->sec_per_pg) + ppa->g.pg < geo->num_pg && + ppa->g.sec < geo->ws_min) continue; print_ppa(ppa, "boundary", i); diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index 839c0b96466a..29c8f44eb25b 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -152,8 +152,8 @@ struct nvme_nvm_id12_addrf { __u8 blk_len; __u8 pg_offset; __u8 pg_len; - __u8 sect_offset; - __u8 sect_len; + __u8 sec_offset; + __u8 sec_len; __u8 res[4]; } __packed; @@ -254,106 +254,160 @@ static inline void _nvme_nvm_check_size(void) BUILD_BUG_ON(sizeof(struct nvme_nvm_id20) != NVME_IDENTIFY_DATA_SIZE); } -static int init_grp(struct nvm_id *nvm_id, struct nvme_nvm_id12 *id12) +static void nvme_nvm_set_addr_12(struct nvm_addrf_12 *dst, + struct nvme_nvm_id12_addrf *src) +{ + dst->ch_len = src->ch_len; + dst->lun_len = src->lun_len; + dst->blk_len = src->blk_len; + dst->pg_len = src->pg_len; + dst->pln_len = src->pln_len; + dst->sect_len = src->sec_len; + + dst->ch_offset = src->ch_offset; + dst->lun_offset = src->lun_offset; + dst->blk_offset = src->blk_offset; + dst->pg_offset = src->pg_offset; + dst->pln_offset = src->pln_offset; + dst->sect_offset = src->sec_offset; + + dst->ch_mask = ((1ULL << dst->ch_len) - 1) << dst->ch_offset; + dst->lun_mask = ((1ULL << dst->lun_len) - 1) << dst->lun_offset; + dst->blk_mask = ((1ULL << dst->blk_len) - 1) << dst->blk_offset; + dst->pg_mask = ((1ULL << dst->pg_len) - 1) << dst->pg_offset; + dst->pln_mask = ((1ULL << dst->pln_len) - 1) << dst->pln_offset; + dst->sec_mask = ((1ULL << dst->sect_len) - 1) << dst->sect_offset; +} + +static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, + struct nvm_geo *geo) { struct nvme_nvm_id12_grp *src; int sec_per_pg, sec_per_pl, pg_per_blk; - if (id12->cgrps != 1) + if (id->cgrps != 1) + return -EINVAL; + + src = &id->grp; + + if (src->mtype != 0) { + pr_err("nvm: memory type not supported\n"); return -EINVAL; + } - src = &id12->grp; + geo->ver_id = id->ver_id; - nvm_id->mtype = src->mtype; - nvm_id->fmtype = src->fmtype; + geo->nr_chnls = src->num_ch; + geo->nr_luns = src->num_lun; + geo->all_luns = geo->nr_chnls * geo->nr_luns; - nvm_id->num_ch = src->num_ch; - nvm_id->num_lun = src->num_lun; + geo->nr_chks = le16_to_cpu(src->num_chk); - nvm_id->num_chk = le16_to_cpu(src->num_chk); - nvm_id->csecs = le16_to_cpu(src->csecs); - nvm_id->sos = le16_to_cpu(src->sos); + geo->csecs = le16_to_cpu(src->csecs); + geo->sos = le16_to_cpu(src->sos); pg_per_blk = le16_to_cpu(src->num_pg); - sec_per_pg = le16_to_cpu(src->fpg_sz) / nvm_id->csecs; + sec_per_pg = le16_to_cpu(src->fpg_sz) / geo->csecs; sec_per_pl = sec_per_pg * src->num_pln; - nvm_id->clba = sec_per_pl * pg_per_blk; - nvm_id->ws_per_chk = pg_per_blk; - - nvm_id->mpos = le32_to_cpu(src->mpos); - nvm_id->cpar = le16_to_cpu(src->cpar); - nvm_id->mccap = le32_to_cpu(src->mccap); - - nvm_id->ws_opt = nvm_id->ws_min = sec_per_pg; - nvm_id->ws_seq = NVM_IO_SNGL_ACCESS; - - if (nvm_id->mpos & 0x020202) { - nvm_id->ws_seq = NVM_IO_DUAL_ACCESS; - nvm_id->ws_opt <<= 1; - } else if (nvm_id->mpos & 0x040404) { - nvm_id->ws_seq = NVM_IO_QUAD_ACCESS; - nvm_id->ws_opt <<= 2; - } + geo->clba = sec_per_pl * pg_per_blk; + + geo->all_chunks = geo->all_luns * geo->nr_chks; + geo->total_secs = geo->clba * geo->all_chunks; + + geo->ws_min = sec_per_pg; + geo->ws_opt = sec_per_pg; + geo->mw_cunits = geo->ws_opt << 3; /* default to MLC safe values */ - nvm_id->trdt = le32_to_cpu(src->trdt); - nvm_id->trdm = le32_to_cpu(src->trdm); - nvm_id->tprt = le32_to_cpu(src->tprt); - nvm_id->tprm = le32_to_cpu(src->tprm); - nvm_id->tbet = le32_to_cpu(src->tbet); - nvm_id->tbem = le32_to_cpu(src->tbem); + geo->mccap = le32_to_cpu(src->mccap); + + geo->trdt = le32_to_cpu(src->trdt); + geo->trdm = le32_to_cpu(src->trdm); + geo->tprt = le32_to_cpu(src->tprt); + geo->tprm = le32_to_cpu(src->tprm); + geo->tbet = le32_to_cpu(src->tbet); + geo->tbem = le32_to_cpu(src->tbem); /* 1.2 compatibility */ - nvm_id->num_pln = src->num_pln; - nvm_id->num_pg = le16_to_cpu(src->num_pg); - nvm_id->fpg_sz = le16_to_cpu(src->fpg_sz); + geo->vmnt = id->vmnt; + geo->cap = le32_to_cpu(id->cap); + geo->dom = le32_to_cpu(id->dom); + + geo->mtype = src->mtype; + geo->fmtype = src->fmtype; + + geo->cpar = le16_to_cpu(src->cpar); + geo->mpos = le32_to_cpu(src->mpos); + + geo->plane_mode = NVM_PLANE_SINGLE; + + if (geo->mpos & 0x020202) { + geo->plane_mode = NVM_PLANE_DOUBLE; + geo->ws_opt <<= 1; + } else if (geo->mpos & 0x040404) { + geo->plane_mode = NVM_PLANE_QUAD; + geo->ws_opt <<= 2; + } + + geo->num_pln = src->num_pln; + geo->num_pg = le16_to_cpu(src->num_pg); + geo->fpg_sz = le16_to_cpu(src->fpg_sz); + + nvme_nvm_set_addr_12((struct nvm_addrf_12 *)&geo->addrf, &id->ppaf); return 0; } -static int nvme_nvm_setup_12(struct nvm_dev *nvmdev, struct nvm_id *nvm_id, - struct nvme_nvm_id12 *id) +static void nvme_nvm_set_addr_20(struct nvm_addrf *dst, + struct nvme_nvm_id20_addrf *src) { - nvm_id->ver_id = id->ver_id; - nvm_id->vmnt = id->vmnt; - nvm_id->cap = le32_to_cpu(id->cap); - nvm_id->dom = le32_to_cpu(id->dom); - memcpy(&nvm_id->ppaf, &id->ppaf, - sizeof(struct nvm_addr_format)); - - return init_grp(nvm_id, id); + dst->ch_len = src->grp_len; + dst->lun_len = src->pu_len; + dst->chk_len = src->chk_len; + dst->sec_len = src->lba_len; + + dst->sec_offset = 0; + dst->chk_offset = dst->sec_len; + dst->lun_offset = dst->chk_offset + dst->chk_len; + dst->ch_offset = dst->lun_offset + dst->lun_len; + + dst->ch_mask = ((1ULL << dst->ch_len) - 1) << dst->ch_offset; + dst->lun_mask = ((1ULL << dst->lun_len) - 1) << dst->lun_offset; + dst->chk_mask = ((1ULL << dst->chk_len) - 1) << dst->chk_offset; + dst->sec_mask = ((1ULL << dst->sec_len) - 1) << dst->sec_offset; } -static int nvme_nvm_setup_20(struct nvm_dev *nvmdev, struct nvm_id *nvm_id, - struct nvme_nvm_id20 *id) +static int nvme_nvm_setup_20(struct nvme_nvm_id20 *id, + struct nvm_geo *geo) { - nvm_id->ver_id = id->mjr; + geo->ver_id = id->mjr; - nvm_id->num_ch = le16_to_cpu(id->num_grp); - nvm_id->num_lun = le16_to_cpu(id->num_pu); - nvm_id->num_chk = le32_to_cpu(id->num_chk); - nvm_id->clba = le32_to_cpu(id->clba); + geo->nr_chnls = le16_to_cpu(id->num_grp); + geo->nr_luns = le16_to_cpu(id->num_pu); + geo->all_luns = geo->nr_chnls * geo->nr_luns; - nvm_id->ws_min = le32_to_cpu(id->ws_min); - nvm_id->ws_opt = le32_to_cpu(id->ws_opt); - nvm_id->mw_cunits = le32_to_cpu(id->mw_cunits); + geo->nr_chks = le32_to_cpu(id->num_chk); + geo->clba = le32_to_cpu(id->clba); - nvm_id->trdt = le32_to_cpu(id->trdt); - nvm_id->trdm = le32_to_cpu(id->trdm); - nvm_id->tprt = le32_to_cpu(id->twrt); - nvm_id->tprm = le32_to_cpu(id->twrm); - nvm_id->tbet = le32_to_cpu(id->tcrst); - nvm_id->tbem = le32_to_cpu(id->tcrsm); + geo->all_chunks = geo->all_luns * geo->nr_chks; + geo->total_secs = geo->clba * geo->all_chunks; - /* calculated values */ - nvm_id->ws_per_chk = nvm_id->clba / nvm_id->ws_min; + geo->ws_min = le32_to_cpu(id->ws_min); + geo->ws_opt = le32_to_cpu(id->ws_opt); + geo->mw_cunits = le32_to_cpu(id->mw_cunits); - /* 1.2 compatibility */ - nvm_id->ws_seq = NVM_IO_SNGL_ACCESS; + geo->trdt = le32_to_cpu(id->trdt); + geo->trdm = le32_to_cpu(id->trdm); + geo->tprt = le32_to_cpu(id->twrt); + geo->tprm = le32_to_cpu(id->twrm); + geo->tbet = le32_to_cpu(id->tcrst); + geo->tbem = le32_to_cpu(id->tcrsm); + + nvme_nvm_set_addr_20(&geo->addrf, &id->lbaf); return 0; } -static int nvme_nvm_identity(struct nvm_dev *nvmdev, struct nvm_id *nvm_id) +static int nvme_nvm_identity(struct nvm_dev *nvmdev) { struct nvme_ns *ns = nvmdev->q->queuedata; struct nvme_nvm_id12 *id; @@ -380,18 +434,18 @@ static int nvme_nvm_identity(struct nvm_dev *nvmdev, struct nvm_id *nvm_id) */ switch (id->ver_id) { case 1: - ret = nvme_nvm_setup_12(nvmdev, nvm_id, id); + ret = nvme_nvm_setup_12(id, &nvmdev->geo); break; case 2: - ret = nvme_nvm_setup_20(nvmdev, nvm_id, - (struct nvme_nvm_id20 *)id); + ret = nvme_nvm_setup_20((struct nvme_nvm_id20 *)id, + &nvmdev->geo); break; default: - dev_err(ns->ctrl->device, - "OCSSD revision not supported (%d)\n", - nvm_id->ver_id); + dev_err(ns->ctrl->device, "OCSSD revision not supported (%d)\n", + id->ver_id); ret = -EINVAL; } + out: kfree(id); return ret; @@ -406,7 +460,7 @@ static int nvme_nvm_get_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr ppa, struct nvme_ctrl *ctrl = ns->ctrl; struct nvme_nvm_command c = {}; struct nvme_nvm_bb_tbl *bb_tbl; - int nr_blks = geo->nr_chks * geo->plane_mode; + int nr_blks = geo->nr_chks * geo->num_pln; int tblsz = sizeof(struct nvme_nvm_bb_tbl) + nr_blks; int ret = 0; @@ -447,7 +501,7 @@ static int nvme_nvm_get_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr ppa, goto out; } - memcpy(blks, bb_tbl->blk, geo->nr_chks * geo->plane_mode); + memcpy(blks, bb_tbl->blk, geo->nr_chks * geo->num_pln); out: kfree(bb_tbl); return ret; @@ -815,9 +869,10 @@ int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg) void nvme_nvm_update_nvm_info(struct nvme_ns *ns) { struct nvm_dev *ndev = ns->ndev; + struct nvm_geo *geo = &ndev->geo; - ndev->identity.csecs = ndev->geo.sec_size = 1 << ns->lba_shift; - ndev->identity.sos = ndev->geo.oob_size = ns->ms; + geo->csecs = 1 << ns->lba_shift; + geo->sos = ns->ms; } int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node) @@ -850,23 +905,22 @@ static ssize_t nvm_dev_attr_show(struct device *dev, { struct nvme_ns *ns = nvme_get_ns_from_dev(dev); struct nvm_dev *ndev = ns->ndev; - struct nvm_id *id; + struct nvm_geo *geo = &ndev->geo; struct attribute *attr; if (!ndev) return 0; - id = &ndev->identity; attr = &dattr->attr; if (strcmp(attr->name, "version") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->ver_id); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->ver_id); } else if (strcmp(attr->name, "capabilities") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->cap); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->cap); } else if (strcmp(attr->name, "read_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->trdt); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->trdt); } else if (strcmp(attr->name, "read_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->trdm); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->trdm); } else { return scnprintf(page, PAGE_SIZE, @@ -875,75 +929,78 @@ static ssize_t nvm_dev_attr_show(struct device *dev, } } +static ssize_t nvm_dev_attr_show_ppaf(struct nvm_addrf_12 *ppaf, char *page) +{ + return scnprintf(page, PAGE_SIZE, + "0x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", + ppaf->ch_offset, ppaf->ch_len, + ppaf->lun_offset, ppaf->lun_len, + ppaf->pln_offset, ppaf->pln_len, + ppaf->blk_offset, ppaf->blk_len, + ppaf->pg_offset, ppaf->pg_len, + ppaf->sect_offset, ppaf->sect_len); +} + static ssize_t nvm_dev_attr_show_12(struct device *dev, struct device_attribute *dattr, char *page) { struct nvme_ns *ns = nvme_get_ns_from_dev(dev); struct nvm_dev *ndev = ns->ndev; - struct nvm_id *id; + struct nvm_geo *geo = &ndev->geo; struct attribute *attr; if (!ndev) return 0; - id = &ndev->identity; attr = &dattr->attr; if (strcmp(attr->name, "vendor_opcode") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->vmnt); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->vmnt); } else if (strcmp(attr->name, "device_mode") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->dom); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->dom); /* kept for compatibility */ } else if (strcmp(attr->name, "media_manager") == 0) { return scnprintf(page, PAGE_SIZE, "%s\n", "gennvm"); } else if (strcmp(attr->name, "ppa_format") == 0) { - return scnprintf(page, PAGE_SIZE, - "0x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", - id->ppaf.ch_offset, id->ppaf.ch_len, - id->ppaf.lun_offset, id->ppaf.lun_len, - id->ppaf.pln_offset, id->ppaf.pln_len, - id->ppaf.blk_offset, id->ppaf.blk_len, - id->ppaf.pg_offset, id->ppaf.pg_len, - id->ppaf.sect_offset, id->ppaf.sect_len); + return nvm_dev_attr_show_ppaf((void *)&geo->addrf, page); } else if (strcmp(attr->name, "media_type") == 0) { /* u8 */ - return scnprintf(page, PAGE_SIZE, "%u\n", id->mtype); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->mtype); } else if (strcmp(attr->name, "flash_media_type") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->fmtype); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->fmtype); } else if (strcmp(attr->name, "num_channels") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_ch); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chnls); } else if (strcmp(attr->name, "num_luns") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_lun); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_luns); } else if (strcmp(attr->name, "num_planes") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_pln); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_pln); } else if (strcmp(attr->name, "num_blocks") == 0) { /* u16 */ - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_chk); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chks); } else if (strcmp(attr->name, "num_pages") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_pg); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_pg); } else if (strcmp(attr->name, "page_size") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->fpg_sz); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->fpg_sz); } else if (strcmp(attr->name, "hw_sector_size") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->csecs); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->csecs); } else if (strcmp(attr->name, "oob_sector_size") == 0) {/* u32 */ - return scnprintf(page, PAGE_SIZE, "%u\n", id->sos); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->sos); } else if (strcmp(attr->name, "prog_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tprt); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tprt); } else if (strcmp(attr->name, "prog_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tprm); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tprm); } else if (strcmp(attr->name, "erase_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tbet); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tbet); } else if (strcmp(attr->name, "erase_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tbem); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tbem); } else if (strcmp(attr->name, "multiplane_modes") == 0) { - return scnprintf(page, PAGE_SIZE, "0x%08x\n", id->mpos); + return scnprintf(page, PAGE_SIZE, "0x%08x\n", geo->mpos); } else if (strcmp(attr->name, "media_capabilities") == 0) { - return scnprintf(page, PAGE_SIZE, "0x%08x\n", id->mccap); + return scnprintf(page, PAGE_SIZE, "0x%08x\n", geo->mccap); } else if (strcmp(attr->name, "max_phys_secs") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", NVM_MAX_VLBA); } else { - return scnprintf(page, - PAGE_SIZE, - "Unhandled attr(%s) in `nvm_dev_attr_show_12`\n", - attr->name); + return scnprintf(page, PAGE_SIZE, + "Unhandled attr(%s) in `nvm_dev_attr_show_12`\n", + attr->name); } } @@ -952,42 +1009,40 @@ static ssize_t nvm_dev_attr_show_20(struct device *dev, { struct nvme_ns *ns = nvme_get_ns_from_dev(dev); struct nvm_dev *ndev = ns->ndev; - struct nvm_id *id; + struct nvm_geo *geo = &ndev->geo; struct attribute *attr; if (!ndev) return 0; - id = &ndev->identity; attr = &dattr->attr; if (strcmp(attr->name, "groups") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_ch); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chnls); } else if (strcmp(attr->name, "punits") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_lun); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_luns); } else if (strcmp(attr->name, "chunks") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->num_chk); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chks); } else if (strcmp(attr->name, "clba") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->clba); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->clba); } else if (strcmp(attr->name, "ws_min") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->ws_min); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->ws_min); } else if (strcmp(attr->name, "ws_opt") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->ws_opt); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->ws_opt); } else if (strcmp(attr->name, "mw_cunits") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->mw_cunits); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->mw_cunits); } else if (strcmp(attr->name, "write_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tprt); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tprt); } else if (strcmp(attr->name, "write_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tprm); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tprm); } else if (strcmp(attr->name, "reset_typ") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tbet); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tbet); } else if (strcmp(attr->name, "reset_max") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", id->tbem); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->tbem); } else { - return scnprintf(page, - PAGE_SIZE, - "Unhandled attr(%s) in `nvm_dev_attr_show_20`\n", - attr->name); + return scnprintf(page, PAGE_SIZE, + "Unhandled attr(%s) in `nvm_dev_attr_show_20`\n", + attr->name); } } @@ -1106,10 +1161,13 @@ static const struct attribute_group nvm_dev_attr_group_20 = { int nvme_nvm_register_sysfs(struct nvme_ns *ns) { - if (!ns->ndev) + struct nvm_dev *ndev = ns->ndev; + struct nvm_geo *geo = &ndev->geo; + + if (!ndev) return -EINVAL; - switch (ns->ndev->identity.ver_id) { + switch (geo->ver_id) { case 1: return sysfs_create_group(&disk_to_dev(ns->disk)->kobj, &nvm_dev_attr_group_12); @@ -1123,7 +1181,10 @@ int nvme_nvm_register_sysfs(struct nvme_ns *ns) void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) { - switch (ns->ndev->identity.ver_id) { + struct nvm_dev *ndev = ns->ndev; + struct nvm_geo *geo = &ndev->geo; + + switch (geo->ver_id) { case 1: sysfs_remove_group(&disk_to_dev(ns->disk)->kobj, &nvm_dev_attr_group_12); diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index e55b10573c99..6e650563b379 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -50,7 +50,7 @@ struct nvm_id; struct nvm_dev; struct nvm_tgt_dev; -typedef int (nvm_id_fn)(struct nvm_dev *, struct nvm_id *); +typedef int (nvm_id_fn)(struct nvm_dev *); typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *); typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int); typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *); @@ -152,62 +152,48 @@ struct nvm_id_lp_tbl { struct nvm_id_lp_mlc mlc; }; -struct nvm_addr_format { - u8 ch_offset; +struct nvm_addrf_12 { u8 ch_len; - u8 lun_offset; u8 lun_len; - u8 pln_offset; - u8 pln_len; - u8 blk_offset; u8 blk_len; - u8 pg_offset; u8 pg_len; - u8 sect_offset; + u8 pln_len; u8 sect_len; -}; - -struct nvm_id { - u8 ver_id; - u8 vmnt; - u32 cap; - u32 dom; - struct nvm_addr_format ppaf; - - u8 num_ch; - u8 num_lun; - u16 num_chk; - u16 clba; - u16 csecs; - u16 sos; - - u32 ws_min; - u32 ws_opt; - u32 mw_cunits; - - u32 trdt; - u32 trdm; - u32 tprt; - u32 tprm; - u32 tbet; - u32 tbem; - u32 mpos; - u32 mccap; - u16 cpar; + u8 ch_offset; + u8 lun_offset; + u8 blk_offset; + u8 pg_offset; + u8 pln_offset; + u8 sect_offset; - /* calculated values */ - u16 ws_seq; - u16 ws_per_chk; + u64 ch_mask; + u64 lun_mask; + u64 blk_mask; + u64 pg_mask; + u64 pln_mask; + u64 sec_mask; +}; - /* 1.2 compatibility */ - u8 mtype; - u8 fmtype; +struct nvm_addrf { + u8 ch_len; + u8 lun_len; + u8 chk_len; + u8 sec_len; + u8 rsv_len[2]; - u8 num_pln; - u16 num_pg; - u16 fpg_sz; -} __packed; + u8 ch_offset; + u8 lun_offset; + u8 chk_offset; + u8 sec_offset; + u8 rsv_off[2]; + + u64 ch_mask; + u64 lun_mask; + u64 chk_mask; + u64 sec_mask; + u64 rsv_mask[2]; +}; struct nvm_target { struct list_head list; @@ -274,36 +260,63 @@ enum { NVM_BLK_ST_BAD = 0x8, /* Bad block */ }; - -/* Device generic information */ +/* Instance geometry */ struct nvm_geo { - /* generic geometry */ + /* device reported version */ + u8 ver_id; + + /* instance specific geometry */ int nr_chnls; - int all_luns; /* across channels */ - int nr_luns; /* per channel */ - int nr_chks; /* per lun */ + int nr_luns; /* per channel */ - int sec_size; - int oob_size; - int mccap; + /* calculated values */ + int all_luns; /* across channels */ + int all_chunks; /* across channels */ + + int op; /* over-provision in instance */ + + sector_t total_secs; /* across channels */ + + /* chunk geometry */ + u32 nr_chks; /* chunks per lun */ + u32 clba; /* sectors per chunk */ + u16 csecs; /* sector size */ + u16 sos; /* out-of-band area size */ - int sec_per_chk; - int sec_per_lun; + /* device write constrains */ + u32 ws_min; /* minimum write size */ + u32 ws_opt; /* optimal write size */ + u32 mw_cunits; /* distance required for successful read */ - int ws_min; - int ws_opt; - int ws_seq; - int ws_per_chk; + /* device capabilities */ + u32 mccap; - int op; + /* device timings */ + u32 trdt; /* Avg. Tread (ns) */ + u32 trdm; /* Max Tread (ns) */ + u32 tprt; /* Avg. Tprog (ns) */ + u32 tprm; /* Max Tprog (ns) */ + u32 tbet; /* Avg. Terase (ns) */ + u32 tbem; /* Max Terase (ns) */ - struct nvm_addr_format ppaf; + /* generic address format */ + struct nvm_addrf addrf; - /* Legacy 1.2 specific geometry */ - int plane_mode; /* drive device in single, double or quad mode */ - int nr_planes; - int sec_per_pg; /* only sectors for a single page */ - int sec_per_pl; /* all sectors across planes */ + /* 1.2 compatibility */ + u8 vmnt; + u32 cap; + u32 dom; + + u8 mtype; + u8 fmtype; + + u16 cpar; + u32 mpos; + + u8 num_pln; + u8 plane_mode; + u16 num_pg; + u16 fpg_sz; }; /* sub-device structure */ @@ -314,9 +327,6 @@ struct nvm_tgt_dev { /* Base ppas for target LUNs */ struct ppa_addr *luns; - sector_t total_secs; - - struct nvm_id identity; struct request_queue *q; struct nvm_dev *parent; @@ -331,13 +341,9 @@ struct nvm_dev { /* Device information */ struct nvm_geo geo; - unsigned long total_secs; - unsigned long *lun_map; void *dma_pool; - struct nvm_id identity; - /* Backend device */ struct request_queue *q; char name[DISK_NAME_LEN]; @@ -357,14 +363,15 @@ static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev, struct ppa_addr r) { struct nvm_geo *geo = &tgt_dev->geo; + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf; struct ppa_addr l; - l.ppa = ((u64)r.g.blk) << geo->ppaf.blk_offset; - l.ppa |= ((u64)r.g.pg) << geo->ppaf.pg_offset; - l.ppa |= ((u64)r.g.sec) << geo->ppaf.sect_offset; - l.ppa |= ((u64)r.g.pl) << geo->ppaf.pln_offset; - l.ppa |= ((u64)r.g.lun) << geo->ppaf.lun_offset; - l.ppa |= ((u64)r.g.ch) << geo->ppaf.ch_offset; + l.ppa = ((u64)r.g.ch) << ppaf->ch_offset; + l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset; + l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset; + l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset; + l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset; + l.ppa |= ((u64)r.g.sec) << ppaf->sect_offset; return l; } @@ -373,24 +380,17 @@ static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev, struct ppa_addr r) { struct nvm_geo *geo = &tgt_dev->geo; + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf; struct ppa_addr l; l.ppa = 0; - /* - * (r.ppa << X offset) & X len bitmask. X eq. blk, pg, etc. - */ - l.g.blk = (r.ppa >> geo->ppaf.blk_offset) & - (((1 << geo->ppaf.blk_len) - 1)); - l.g.pg |= (r.ppa >> geo->ppaf.pg_offset) & - (((1 << geo->ppaf.pg_len) - 1)); - l.g.sec |= (r.ppa >> geo->ppaf.sect_offset) & - (((1 << geo->ppaf.sect_len) - 1)); - l.g.pl |= (r.ppa >> geo->ppaf.pln_offset) & - (((1 << geo->ppaf.pln_len) - 1)); - l.g.lun |= (r.ppa >> geo->ppaf.lun_offset) & - (((1 << geo->ppaf.lun_len) - 1)); - l.g.ch |= (r.ppa >> geo->ppaf.ch_offset) & - (((1 << geo->ppaf.ch_len) - 1)); + + l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset; + l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset; + l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset; + l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset; + l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset; + l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sect_offset; return l; } -- cgit v1.2.3 From 3cb98f84d368b3bbe07a2d5bf938e31f74567620 Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:11 +0200 Subject: lightnvm: add minor version to generic geometry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Separate the version between major and minor on the generic geometry and represent it through sysfs in the 2.0 path. The 1.2 path only shows the major version to preserve the existing user space interface. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 4 ++-- drivers/nvme/host/lightnvm.c | 25 ++++++++++++++++++++----- include/linux/lightnvm.h | 3 ++- 3 files changed, 24 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index 9dec936ac1dc..103e0ad9622c 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -890,8 +890,8 @@ static int nvm_init(struct nvm_dev *dev) goto err; } - pr_debug("nvm: ver:%u nvm_vendor:%x\n", - geo->ver_id, + pr_debug("nvm: ver:%u.%u nvm_vendor:%x\n", + geo->major_ver_id, geo->minor_ver_id, geo->vmnt); ret = nvm_core_init(dev); diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index 29c8f44eb25b..de4105544956 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -295,7 +295,9 @@ static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, return -EINVAL; } - geo->ver_id = id->ver_id; + /* 1.2 spec. only reports a single version id - unfold */ + geo->major_ver_id = id->ver_id; + geo->minor_ver_id = 2; geo->nr_chnls = src->num_ch; geo->nr_luns = src->num_lun; @@ -379,7 +381,14 @@ static void nvme_nvm_set_addr_20(struct nvm_addrf *dst, static int nvme_nvm_setup_20(struct nvme_nvm_id20 *id, struct nvm_geo *geo) { - geo->ver_id = id->mjr; + geo->major_ver_id = id->mjr; + geo->minor_ver_id = id->mnr; + + if (!(geo->major_ver_id == 2 && geo->minor_ver_id == 0)) { + pr_err("nvm: OCSSD version not supported (v%d.%d)\n", + geo->major_ver_id, geo->minor_ver_id); + return -EINVAL; + } geo->nr_chnls = le16_to_cpu(id->num_grp); geo->nr_luns = le16_to_cpu(id->num_pu); @@ -914,7 +923,13 @@ static ssize_t nvm_dev_attr_show(struct device *dev, attr = &dattr->attr; if (strcmp(attr->name, "version") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", geo->ver_id); + if (geo->major_ver_id == 1) + return scnprintf(page, PAGE_SIZE, "%u\n", + geo->major_ver_id); + else + return scnprintf(page, PAGE_SIZE, "%u.%u\n", + geo->major_ver_id, + geo->minor_ver_id); } else if (strcmp(attr->name, "capabilities") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", geo->cap); } else if (strcmp(attr->name, "read_typ") == 0) { @@ -1167,7 +1182,7 @@ int nvme_nvm_register_sysfs(struct nvme_ns *ns) if (!ndev) return -EINVAL; - switch (geo->ver_id) { + switch (geo->major_ver_id) { case 1: return sysfs_create_group(&disk_to_dev(ns->disk)->kobj, &nvm_dev_attr_group_12); @@ -1184,7 +1199,7 @@ void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) struct nvm_dev *ndev = ns->ndev; struct nvm_geo *geo = &ndev->geo; - switch (geo->ver_id) { + switch (geo->major_ver_id) { case 1: sysfs_remove_group(&disk_to_dev(ns->disk)->kobj, &nvm_dev_attr_group_12); diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index 6e650563b379..7ed8b92d6744 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -263,7 +263,8 @@ enum { /* Instance geometry */ struct nvm_geo { /* device reported version */ - u8 ver_id; + u8 major_ver_id; + u8 minor_ver_id; /* instance specific geometry */ int nr_chnls; -- cgit v1.2.3 From f1d4e8121f3fc25f9be94c6de6b8f5f788ad0265 Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:12 +0200 Subject: lightnvm: add shorten OCSSD version in geo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create a shorten version to use in the generic geometry. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/nvme/host/lightnvm.c | 6 ++++++ include/linux/lightnvm.h | 8 ++++++++ 2 files changed, 14 insertions(+) (limited to 'include/linux') diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index de4105544956..f7f7769e7588 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -299,6 +299,9 @@ static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, geo->major_ver_id = id->ver_id; geo->minor_ver_id = 2; + /* Set compacted version for upper layers */ + geo->version = NVM_OCSSD_SPEC_12; + geo->nr_chnls = src->num_ch; geo->nr_luns = src->num_lun; geo->all_luns = geo->nr_chnls * geo->nr_luns; @@ -384,6 +387,9 @@ static int nvme_nvm_setup_20(struct nvme_nvm_id20 *id, geo->major_ver_id = id->mjr; geo->minor_ver_id = id->mnr; + /* Set compacted version for upper layers */ + geo->version = NVM_OCSSD_SPEC_20; + if (!(geo->major_ver_id == 2 && geo->minor_ver_id == 0)) { pr_err("nvm: OCSSD version not supported (v%d.%d)\n", geo->major_ver_id, geo->minor_ver_id); diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index 7ed8b92d6744..a073c0c76260 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -23,6 +23,11 @@ enum { #define NVM_LUN_BITS (8) #define NVM_CH_BITS (7) +enum { + NVM_OCSSD_SPEC_12 = 12, + NVM_OCSSD_SPEC_20 = 20, +}; + struct ppa_addr { /* Generic structure for all addresses */ union { @@ -266,6 +271,9 @@ struct nvm_geo { u8 major_ver_id; u8 minor_ver_id; + /* kernel short version */ + u8 version; + /* instance specific geometry */ int nr_chnls; int nr_luns; /* per channel */ -- cgit v1.2.3 From 3f48021bad73696421e2725c856b9b3aec7f567c Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:13 +0200 Subject: lightnvm: complete geo structure with maxoc* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Complete the generic geometry structure with the maxoc and maxocpu felds, present in the 2.0 spec. Also, expose them through sysfs. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/nvme/host/lightnvm.c | 17 +++++++++++++++++ include/linux/lightnvm.h | 2 ++ 2 files changed, 19 insertions(+) (limited to 'include/linux') diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index f7f7769e7588..41b38ebdb1f3 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -323,6 +323,13 @@ static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, geo->ws_opt = sec_per_pg; geo->mw_cunits = geo->ws_opt << 3; /* default to MLC safe values */ + /* Do not impose values for maximum number of open blocks as it is + * unspecified in 1.2. Users of 1.2 must be aware of this and eventually + * specify these values through a quirk if restrictions apply. + */ + geo->maxoc = geo->all_luns * geo->nr_chks; + geo->maxocpu = geo->nr_chks; + geo->mccap = le32_to_cpu(src->mccap); geo->trdt = le32_to_cpu(src->trdt); @@ -409,6 +416,8 @@ static int nvme_nvm_setup_20(struct nvme_nvm_id20 *id, geo->ws_min = le32_to_cpu(id->ws_min); geo->ws_opt = le32_to_cpu(id->ws_opt); geo->mw_cunits = le32_to_cpu(id->mw_cunits); + geo->maxoc = le32_to_cpu(id->maxoc); + geo->maxocpu = le32_to_cpu(id->maxocpu); geo->trdt = le32_to_cpu(id->trdt); geo->trdm = le32_to_cpu(id->trdm); @@ -1050,6 +1059,10 @@ static ssize_t nvm_dev_attr_show_20(struct device *dev, return scnprintf(page, PAGE_SIZE, "%u\n", geo->ws_min); } else if (strcmp(attr->name, "ws_opt") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", geo->ws_opt); + } else if (strcmp(attr->name, "maxoc") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", geo->maxoc); + } else if (strcmp(attr->name, "maxocpu") == 0) { + return scnprintf(page, PAGE_SIZE, "%u\n", geo->maxocpu); } else if (strcmp(attr->name, "mw_cunits") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", geo->mw_cunits); } else if (strcmp(attr->name, "write_typ") == 0) { @@ -1147,6 +1160,8 @@ static NVM_DEV_ATTR_20_RO(chunks); static NVM_DEV_ATTR_20_RO(clba); static NVM_DEV_ATTR_20_RO(ws_min); static NVM_DEV_ATTR_20_RO(ws_opt); +static NVM_DEV_ATTR_20_RO(maxoc); +static NVM_DEV_ATTR_20_RO(maxocpu); static NVM_DEV_ATTR_20_RO(mw_cunits); static NVM_DEV_ATTR_20_RO(write_typ); static NVM_DEV_ATTR_20_RO(write_max); @@ -1163,6 +1178,8 @@ static struct attribute *nvm_dev_attrs_20[] = { &dev_attr_clba.attr, &dev_attr_ws_min.attr, &dev_attr_ws_opt.attr, + &dev_attr_maxoc.attr, + &dev_attr_maxocpu.attr, &dev_attr_mw_cunits.attr, &dev_attr_read_typ.attr, diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index a073c0c76260..870959a58fef 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -296,6 +296,8 @@ struct nvm_geo { u32 ws_min; /* minimum write size */ u32 ws_opt; /* optimal write size */ u32 mw_cunits; /* distance required for successful read */ + u32 maxoc; /* maximum open chunks */ + u32 maxocpu; /* maximum open chunks per parallel unit */ /* device capabilities */ u32 mccap; -- cgit v1.2.3 From a40afad90b9a253b282183eb9365f1cc14aeff77 Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:14 +0200 Subject: lightnvm: normalize geometry nomenclature MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Normalize nomenclature for naming channels, luns, chunks, planes and sectors as well as derivations in order to improve readability. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 89 +++++++++++++++++++++---------------------- drivers/lightnvm/pblk-core.c | 4 +- drivers/lightnvm/pblk-init.c | 30 +++++++-------- drivers/lightnvm/pblk-sysfs.c | 4 +- drivers/lightnvm/pblk.h | 20 +++++----- drivers/nvme/host/lightnvm.c | 54 +++++++++++++------------- include/linux/lightnvm.h | 16 ++++---- 7 files changed, 108 insertions(+), 109 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index 103e0ad9622c..94b3b423840b 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -36,13 +36,13 @@ static DECLARE_RWSEM(nvm_lock); /* Map between virtual and physical channel and lun */ struct nvm_ch_map { int ch_off; - int nr_luns; + int num_lun; int *lun_offs; }; struct nvm_dev_map { struct nvm_ch_map *chnls; - int nr_chnls; + int num_ch; }; static struct nvm_target *nvm_find_target(struct nvm_dev *dev, const char *name) @@ -114,15 +114,15 @@ static void nvm_remove_tgt_dev(struct nvm_tgt_dev *tgt_dev, int clear) struct nvm_dev_map *dev_map = tgt_dev->map; int i, j; - for (i = 0; i < dev_map->nr_chnls; i++) { + for (i = 0; i < dev_map->num_ch; i++) { struct nvm_ch_map *ch_map = &dev_map->chnls[i]; int *lun_offs = ch_map->lun_offs; int ch = i + ch_map->ch_off; if (clear) { - for (j = 0; j < ch_map->nr_luns; j++) { + for (j = 0; j < ch_map->num_lun; j++) { int lun = j + lun_offs[j]; - int lunid = (ch * dev->geo.nr_luns) + lun; + int lunid = (ch * dev->geo.num_lun) + lun; WARN_ON(!test_and_clear_bit(lunid, dev->lun_map)); @@ -147,47 +147,46 @@ static struct nvm_tgt_dev *nvm_create_tgt_dev(struct nvm_dev *dev, struct nvm_dev_map *dev_rmap = dev->rmap; struct nvm_dev_map *dev_map; struct ppa_addr *luns; - int nr_luns = lun_end - lun_begin + 1; - int luns_left = nr_luns; - int nr_chnls = nr_luns / dev->geo.nr_luns; - int nr_chnls_mod = nr_luns % dev->geo.nr_luns; - int bch = lun_begin / dev->geo.nr_luns; - int blun = lun_begin % dev->geo.nr_luns; + int num_lun = lun_end - lun_begin + 1; + int luns_left = num_lun; + int num_ch = num_lun / dev->geo.num_lun; + int num_ch_mod = num_lun % dev->geo.num_lun; + int bch = lun_begin / dev->geo.num_lun; + int blun = lun_begin % dev->geo.num_lun; int lunid = 0; int lun_balanced = 1; - int sec_per_lun, prev_nr_luns; + int sec_per_lun, prev_num_lun; int i, j; - nr_chnls = (nr_chnls_mod == 0) ? nr_chnls : nr_chnls + 1; + num_ch = (num_ch_mod == 0) ? num_ch : num_ch + 1; dev_map = kmalloc(sizeof(struct nvm_dev_map), GFP_KERNEL); if (!dev_map) goto err_dev; - dev_map->chnls = kcalloc(nr_chnls, sizeof(struct nvm_ch_map), - GFP_KERNEL); + dev_map->chnls = kcalloc(num_ch, sizeof(struct nvm_ch_map), GFP_KERNEL); if (!dev_map->chnls) goto err_chnls; - luns = kcalloc(nr_luns, sizeof(struct ppa_addr), GFP_KERNEL); + luns = kcalloc(num_lun, sizeof(struct ppa_addr), GFP_KERNEL); if (!luns) goto err_luns; - prev_nr_luns = (luns_left > dev->geo.nr_luns) ? - dev->geo.nr_luns : luns_left; - for (i = 0; i < nr_chnls; i++) { + prev_num_lun = (luns_left > dev->geo.num_lun) ? + dev->geo.num_lun : luns_left; + for (i = 0; i < num_ch; i++) { struct nvm_ch_map *ch_rmap = &dev_rmap->chnls[i + bch]; int *lun_roffs = ch_rmap->lun_offs; struct nvm_ch_map *ch_map = &dev_map->chnls[i]; int *lun_offs; - int luns_in_chnl = (luns_left > dev->geo.nr_luns) ? - dev->geo.nr_luns : luns_left; + int luns_in_chnl = (luns_left > dev->geo.num_lun) ? + dev->geo.num_lun : luns_left; - if (lun_balanced && prev_nr_luns != luns_in_chnl) + if (lun_balanced && prev_num_lun != luns_in_chnl) lun_balanced = 0; ch_map->ch_off = ch_rmap->ch_off = bch; - ch_map->nr_luns = luns_in_chnl; + ch_map->num_lun = luns_in_chnl; lun_offs = kcalloc(luns_in_chnl, sizeof(int), GFP_KERNEL); if (!lun_offs) @@ -209,7 +208,7 @@ static struct nvm_tgt_dev *nvm_create_tgt_dev(struct nvm_dev *dev, luns_left -= luns_in_chnl; } - dev_map->nr_chnls = nr_chnls; + dev_map->num_ch = num_ch; tgt_dev = kmalloc(sizeof(struct nvm_tgt_dev), GFP_KERNEL); if (!tgt_dev) @@ -219,15 +218,15 @@ static struct nvm_tgt_dev *nvm_create_tgt_dev(struct nvm_dev *dev, memcpy(&tgt_dev->geo, &dev->geo, sizeof(struct nvm_geo)); /* Target device only owns a portion of the physical device */ - tgt_dev->geo.nr_chnls = nr_chnls; - tgt_dev->geo.nr_luns = (lun_balanced) ? prev_nr_luns : -1; - tgt_dev->geo.all_luns = nr_luns; - tgt_dev->geo.all_chunks = nr_luns * dev->geo.nr_chks; + tgt_dev->geo.num_ch = num_ch; + tgt_dev->geo.num_lun = (lun_balanced) ? prev_num_lun : -1; + tgt_dev->geo.all_luns = num_lun; + tgt_dev->geo.all_chunks = num_lun * dev->geo.num_chk; tgt_dev->geo.op = op; - sec_per_lun = dev->geo.clba * dev->geo.nr_chks; - tgt_dev->geo.total_secs = nr_luns * sec_per_lun; + sec_per_lun = dev->geo.clba * dev->geo.num_chk; + tgt_dev->geo.total_secs = num_lun * sec_per_lun; tgt_dev->q = dev->q; tgt_dev->map = dev_map; @@ -505,20 +504,20 @@ static int nvm_register_map(struct nvm_dev *dev) if (!rmap) goto err_rmap; - rmap->chnls = kcalloc(dev->geo.nr_chnls, sizeof(struct nvm_ch_map), + rmap->chnls = kcalloc(dev->geo.num_ch, sizeof(struct nvm_ch_map), GFP_KERNEL); if (!rmap->chnls) goto err_chnls; - for (i = 0; i < dev->geo.nr_chnls; i++) { + for (i = 0; i < dev->geo.num_ch; i++) { struct nvm_ch_map *ch_rmap; int *lun_roffs; - int luns_in_chnl = dev->geo.nr_luns; + int luns_in_chnl = dev->geo.num_lun; ch_rmap = &rmap->chnls[i]; ch_rmap->ch_off = -1; - ch_rmap->nr_luns = luns_in_chnl; + ch_rmap->num_lun = luns_in_chnl; lun_roffs = kcalloc(luns_in_chnl, sizeof(int), GFP_KERNEL); if (!lun_roffs) @@ -547,7 +546,7 @@ static void nvm_unregister_map(struct nvm_dev *dev) struct nvm_dev_map *rmap = dev->rmap; int i; - for (i = 0; i < dev->geo.nr_chnls; i++) + for (i = 0; i < dev->geo.num_ch; i++) kfree(rmap->chnls[i].lun_offs); kfree(rmap->chnls); @@ -676,7 +675,7 @@ static int nvm_set_rqd_ppalist(struct nvm_tgt_dev *tgt_dev, struct nvm_rq *rqd, int i, plane_cnt, pl_idx; struct ppa_addr ppa; - if (geo->plane_mode == NVM_PLANE_SINGLE && nr_ppas == 1) { + if (geo->pln_mode == NVM_PLANE_SINGLE && nr_ppas == 1) { rqd->nr_ppas = nr_ppas; rqd->ppa_addr = ppas[0]; @@ -690,7 +689,7 @@ static int nvm_set_rqd_ppalist(struct nvm_tgt_dev *tgt_dev, struct nvm_rq *rqd, return -ENOMEM; } - plane_cnt = geo->plane_mode; + plane_cnt = geo->pln_mode; rqd->nr_ppas *= plane_cnt; for (i = 0; i < nr_ppas; i++) { @@ -808,15 +807,15 @@ int nvm_bb_tbl_fold(struct nvm_dev *dev, u8 *blks, int nr_blks) struct nvm_geo *geo = &dev->geo; int blk, offset, pl, blktype; - if (nr_blks != geo->nr_chks * geo->plane_mode) + if (nr_blks != geo->num_chk * geo->pln_mode) return -EINVAL; - for (blk = 0; blk < geo->nr_chks; blk++) { - offset = blk * geo->plane_mode; + for (blk = 0; blk < geo->num_chk; blk++) { + offset = blk * geo->pln_mode; blktype = blks[offset]; /* Bad blocks on any planes take precedence over other types */ - for (pl = 0; pl < geo->plane_mode; pl++) { + for (pl = 0; pl < geo->pln_mode; pl++) { if (blks[offset + pl] & (NVM_BLK_T_BAD|NVM_BLK_T_GRWN_BAD)) { blktype = blks[offset + pl]; @@ -827,7 +826,7 @@ int nvm_bb_tbl_fold(struct nvm_dev *dev, u8 *blks, int nr_blks) blks[blk] = blktype; } - return geo->nr_chks; + return geo->num_chk; } EXPORT_SYMBOL(nvm_bb_tbl_fold); @@ -901,9 +900,9 @@ static int nvm_init(struct nvm_dev *dev) } pr_info("nvm: registered %s [%u/%u/%u/%u/%u]\n", - dev->name, geo->ws_min, geo->ws_opt, - geo->nr_chks, geo->all_luns, - geo->nr_chnls); + dev->name, dev->geo.ws_min, dev->geo.ws_opt, + dev->geo.num_chk, dev->geo.all_luns, + dev->geo.num_ch); return 0; err: pr_err("nvm: failed to initialize nvm\n"); diff --git a/drivers/lightnvm/pblk-core.c b/drivers/lightnvm/pblk-core.c index 52c0c3e5ec6e..64c87dd4f1cd 100644 --- a/drivers/lightnvm/pblk-core.c +++ b/drivers/lightnvm/pblk-core.c @@ -1742,10 +1742,10 @@ void pblk_up_rq(struct pblk *pblk, struct ppa_addr *ppa_list, int nr_ppas, struct nvm_tgt_dev *dev = pblk->dev; struct nvm_geo *geo = &dev->geo; struct pblk_lun *rlun; - int nr_luns = geo->all_luns; + int num_lun = geo->all_luns; int bit = -1; - while ((bit = find_next_bit(lun_bitmap, nr_luns, bit + 1)) < nr_luns) { + while ((bit = find_next_bit(lun_bitmap, num_lun, bit + 1)) < num_lun) { rlun = &pblk->luns[bit]; up(&rlun->wr_sem); } diff --git a/drivers/lightnvm/pblk-init.c b/drivers/lightnvm/pblk-init.c index 2fca27d0a9b5..4656d1ff81a6 100644 --- a/drivers/lightnvm/pblk-init.c +++ b/drivers/lightnvm/pblk-init.c @@ -193,15 +193,15 @@ static int pblk_set_addrf_12(struct nvm_geo *geo, struct nvm_addrf_12 *dst) int power_len; /* Re-calculate channel and lun format to adapt to configuration */ - power_len = get_count_order(geo->nr_chnls); - if (1 << power_len != geo->nr_chnls) { + power_len = get_count_order(geo->num_ch); + if (1 << power_len != geo->num_ch) { pr_err("pblk: supports only power-of-two channel config.\n"); return -EINVAL; } dst->ch_len = power_len; - power_len = get_count_order(geo->nr_luns); - if (1 << power_len != geo->nr_luns) { + power_len = get_count_order(geo->num_lun); + if (1 << power_len != geo->num_lun) { pr_err("pblk: supports only power-of-two LUN config.\n"); return -EINVAL; } @@ -210,16 +210,16 @@ static int pblk_set_addrf_12(struct nvm_geo *geo, struct nvm_addrf_12 *dst) dst->blk_len = src->blk_len; dst->pg_len = src->pg_len; dst->pln_len = src->pln_len; - dst->sect_len = src->sect_len; + dst->sec_len = src->sec_len; - dst->sect_offset = 0; - dst->pln_offset = dst->sect_len; + dst->sec_offset = 0; + dst->pln_offset = dst->sec_len; dst->ch_offset = dst->pln_offset + dst->pln_len; dst->lun_offset = dst->ch_offset + dst->ch_len; dst->pg_offset = dst->lun_offset + dst->lun_len; dst->blk_offset = dst->pg_offset + dst->pg_len; - dst->sec_mask = ((1ULL << dst->sect_len) - 1) << dst->sect_offset; + dst->sec_mask = ((1ULL << dst->sec_len) - 1) << dst->sec_offset; dst->pln_mask = ((1ULL << dst->pln_len) - 1) << dst->pln_offset; dst->ch_mask = ((1ULL << dst->ch_len) - 1) << dst->ch_offset; dst->lun_mask = ((1ULL << dst->lun_len) - 1) << dst->lun_offset; @@ -503,7 +503,7 @@ static void *pblk_bb_get_log(struct pblk *pblk) int i, nr_blks, blk_per_lun; int ret; - blk_per_lun = geo->nr_chks * geo->plane_mode; + blk_per_lun = geo->num_chk * geo->pln_mode; nr_blks = blk_per_lun * geo->all_luns; log = kmalloc(nr_blks, GFP_KERNEL); @@ -530,7 +530,7 @@ static int pblk_bb_line(struct pblk *pblk, struct pblk_line *line, struct nvm_tgt_dev *dev = pblk->dev; struct nvm_geo *geo = &dev->geo; int i, bb_cnt = 0; - int blk_per_lun = geo->nr_chks * geo->plane_mode; + int blk_per_lun = geo->num_chk * geo->pln_mode; for (i = 0; i < blk_per_line; i++) { struct pblk_lun *rlun = &pblk->luns[i]; @@ -554,7 +554,7 @@ static int pblk_luns_init(struct pblk *pblk) int i; /* TODO: Implement unbalanced LUN support */ - if (geo->nr_luns < 0) { + if (geo->num_lun < 0) { pr_err("pblk: unbalanced LUN config.\n"); return -EINVAL; } @@ -566,9 +566,9 @@ static int pblk_luns_init(struct pblk *pblk) for (i = 0; i < geo->all_luns; i++) { /* Stripe across channels */ - int ch = i % geo->nr_chnls; - int lun_raw = i / geo->nr_chnls; - int lunid = lun_raw + ch * geo->nr_luns; + int ch = i % geo->num_ch; + int lun_raw = i / geo->num_ch; + int lunid = lun_raw + ch * geo->num_lun; rlun = &pblk->luns[i]; rlun->bppa = dev->luns[lunid]; @@ -672,7 +672,7 @@ static int pblk_line_mg_init(struct pblk *pblk) struct pblk_line_meta *lm = &pblk->lm; int i, bb_distance; - l_mg->nr_lines = geo->nr_chks; + l_mg->nr_lines = geo->num_chk; l_mg->log_line = l_mg->data_line = NULL; l_mg->l_seq_nr = l_mg->d_seq_nr = 0; l_mg->nr_free_lines = 0; diff --git a/drivers/lightnvm/pblk-sysfs.c b/drivers/lightnvm/pblk-sysfs.c index 2474ef4366fa..3e9364f60b44 100644 --- a/drivers/lightnvm/pblk-sysfs.c +++ b/drivers/lightnvm/pblk-sysfs.c @@ -128,7 +128,7 @@ static ssize_t pblk_sysfs_ppaf(struct pblk *pblk, char *page) ppaf->lun_offset, ppaf->lun_len, ppaf->ch_offset, ppaf->ch_len, ppaf->pln_offset, ppaf->pln_len, - ppaf->sect_offset, ppaf->sect_len); + ppaf->sec_offset, ppaf->sec_len); sz += snprintf(page + sz, PAGE_SIZE - sz, "d:blk:%d/%d,pg:%d/%d,lun:%d/%d,ch:%d/%d,pl:%d/%d,sec:%d/%d\n", @@ -137,7 +137,7 @@ static ssize_t pblk_sysfs_ppaf(struct pblk *pblk, char *page) geo_ppaf->lun_offset, geo_ppaf->lun_len, geo_ppaf->ch_offset, geo_ppaf->ch_len, geo_ppaf->pln_offset, geo_ppaf->pln_len, - geo_ppaf->sect_offset, geo_ppaf->sect_len); + geo_ppaf->sec_offset, geo_ppaf->sec_len); return sz; } diff --git a/drivers/lightnvm/pblk.h b/drivers/lightnvm/pblk.h index 898c4e49f77d..dcdad255ccb5 100644 --- a/drivers/lightnvm/pblk.h +++ b/drivers/lightnvm/pblk.h @@ -941,7 +941,7 @@ static inline int pblk_ppa_to_line(struct ppa_addr p) static inline int pblk_ppa_to_pos(struct nvm_geo *geo, struct ppa_addr p) { - return p.g.lun * geo->nr_chnls + p.g.ch; + return p.g.lun * geo->num_ch + p.g.ch; } static inline struct ppa_addr addr_to_gen_ppa(struct pblk *pblk, u64 paddr, @@ -956,7 +956,7 @@ static inline struct ppa_addr addr_to_gen_ppa(struct pblk *pblk, u64 paddr, ppa.g.lun = (paddr & ppaf->lun_mask) >> ppaf->lun_offset; ppa.g.ch = (paddr & ppaf->ch_mask) >> ppaf->ch_offset; ppa.g.pl = (paddr & ppaf->pln_mask) >> ppaf->pln_offset; - ppa.g.sec = (paddr & ppaf->sec_mask) >> ppaf->sect_offset; + ppa.g.sec = (paddr & ppaf->sec_mask) >> ppaf->sec_offset; return ppa; } @@ -971,7 +971,7 @@ static inline u64 pblk_dev_ppa_to_line_addr(struct pblk *pblk, paddr |= (u64)p.g.lun << ppaf->lun_offset; paddr |= (u64)p.g.pg << ppaf->pg_offset; paddr |= (u64)p.g.pl << ppaf->pln_offset; - paddr |= (u64)p.g.sec << ppaf->sect_offset; + paddr |= (u64)p.g.sec << ppaf->sec_offset; return paddr; } @@ -995,7 +995,7 @@ static inline struct ppa_addr pblk_ppa32_to_ppa64(struct pblk *pblk, u32 ppa32) ppa64.g.blk = (ppa32 & ppaf->blk_mask) >> ppaf->blk_offset; ppa64.g.pg = (ppa32 & ppaf->pg_mask) >> ppaf->pg_offset; ppa64.g.pl = (ppa32 & ppaf->pln_mask) >> ppaf->pln_offset; - ppa64.g.sec = (ppa32 & ppaf->sec_mask) >> ppaf->sect_offset; + ppa64.g.sec = (ppa32 & ppaf->sec_mask) >> ppaf->sec_offset; } return ppa64; @@ -1018,7 +1018,7 @@ static inline u32 pblk_ppa64_to_ppa32(struct pblk *pblk, struct ppa_addr ppa64) ppa32 |= ppa64.g.blk << ppaf->blk_offset; ppa32 |= ppa64.g.pg << ppaf->pg_offset; ppa32 |= ppa64.g.pl << ppaf->pln_offset; - ppa32 |= ppa64.g.sec << ppaf->sect_offset; + ppa32 |= ppa64.g.sec << ppaf->sec_offset; } return ppa32; @@ -1136,7 +1136,7 @@ static inline int pblk_set_progr_mode(struct pblk *pblk, int type) struct nvm_geo *geo = &dev->geo; int flags; - flags = geo->plane_mode >> 1; + flags = geo->pln_mode >> 1; if (type == PBLK_WRITE) flags |= NVM_IO_SCRAMBLE_ENABLE; @@ -1157,7 +1157,7 @@ static inline int pblk_set_read_mode(struct pblk *pblk, int type) flags = NVM_IO_SUSPEND | NVM_IO_SCRAMBLE_ENABLE; if (type == PBLK_READ_SEQUENTIAL) - flags |= geo->plane_mode >> 1; + flags |= geo->pln_mode >> 1; return flags; } @@ -1210,10 +1210,10 @@ static inline int pblk_boundary_ppa_checks(struct nvm_tgt_dev *tgt_dev, ppa = &ppas[i]; if (!ppa->c.is_cached && - ppa->g.ch < geo->nr_chnls && - ppa->g.lun < geo->nr_luns && + ppa->g.ch < geo->num_ch && + ppa->g.lun < geo->num_lun && ppa->g.pl < geo->num_pln && - ppa->g.blk < geo->nr_chks && + ppa->g.blk < geo->num_chk && ppa->g.pg < geo->num_pg && ppa->g.sec < geo->ws_min) continue; diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index 41b38ebdb1f3..08f0f6b5bc06 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -262,21 +262,21 @@ static void nvme_nvm_set_addr_12(struct nvm_addrf_12 *dst, dst->blk_len = src->blk_len; dst->pg_len = src->pg_len; dst->pln_len = src->pln_len; - dst->sect_len = src->sec_len; + dst->sec_len = src->sec_len; dst->ch_offset = src->ch_offset; dst->lun_offset = src->lun_offset; dst->blk_offset = src->blk_offset; dst->pg_offset = src->pg_offset; dst->pln_offset = src->pln_offset; - dst->sect_offset = src->sec_offset; + dst->sec_offset = src->sec_offset; dst->ch_mask = ((1ULL << dst->ch_len) - 1) << dst->ch_offset; dst->lun_mask = ((1ULL << dst->lun_len) - 1) << dst->lun_offset; dst->blk_mask = ((1ULL << dst->blk_len) - 1) << dst->blk_offset; dst->pg_mask = ((1ULL << dst->pg_len) - 1) << dst->pg_offset; dst->pln_mask = ((1ULL << dst->pln_len) - 1) << dst->pln_offset; - dst->sec_mask = ((1ULL << dst->sect_len) - 1) << dst->sect_offset; + dst->sec_mask = ((1ULL << dst->sec_len) - 1) << dst->sec_offset; } static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, @@ -302,11 +302,11 @@ static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, /* Set compacted version for upper layers */ geo->version = NVM_OCSSD_SPEC_12; - geo->nr_chnls = src->num_ch; - geo->nr_luns = src->num_lun; - geo->all_luns = geo->nr_chnls * geo->nr_luns; + geo->num_ch = src->num_ch; + geo->num_lun = src->num_lun; + geo->all_luns = geo->num_ch * geo->num_lun; - geo->nr_chks = le16_to_cpu(src->num_chk); + geo->num_chk = le16_to_cpu(src->num_chk); geo->csecs = le16_to_cpu(src->csecs); geo->sos = le16_to_cpu(src->sos); @@ -316,7 +316,7 @@ static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, sec_per_pl = sec_per_pg * src->num_pln; geo->clba = sec_per_pl * pg_per_blk; - geo->all_chunks = geo->all_luns * geo->nr_chks; + geo->all_chunks = geo->all_luns * geo->num_chk; geo->total_secs = geo->clba * geo->all_chunks; geo->ws_min = sec_per_pg; @@ -327,8 +327,8 @@ static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, * unspecified in 1.2. Users of 1.2 must be aware of this and eventually * specify these values through a quirk if restrictions apply. */ - geo->maxoc = geo->all_luns * geo->nr_chks; - geo->maxocpu = geo->nr_chks; + geo->maxoc = geo->all_luns * geo->num_chk; + geo->maxocpu = geo->num_chk; geo->mccap = le32_to_cpu(src->mccap); @@ -350,13 +350,13 @@ static int nvme_nvm_setup_12(struct nvme_nvm_id12 *id, geo->cpar = le16_to_cpu(src->cpar); geo->mpos = le32_to_cpu(src->mpos); - geo->plane_mode = NVM_PLANE_SINGLE; + geo->pln_mode = NVM_PLANE_SINGLE; if (geo->mpos & 0x020202) { - geo->plane_mode = NVM_PLANE_DOUBLE; + geo->pln_mode = NVM_PLANE_DOUBLE; geo->ws_opt <<= 1; } else if (geo->mpos & 0x040404) { - geo->plane_mode = NVM_PLANE_QUAD; + geo->pln_mode = NVM_PLANE_QUAD; geo->ws_opt <<= 2; } @@ -403,14 +403,14 @@ static int nvme_nvm_setup_20(struct nvme_nvm_id20 *id, return -EINVAL; } - geo->nr_chnls = le16_to_cpu(id->num_grp); - geo->nr_luns = le16_to_cpu(id->num_pu); - geo->all_luns = geo->nr_chnls * geo->nr_luns; + geo->num_ch = le16_to_cpu(id->num_grp); + geo->num_lun = le16_to_cpu(id->num_pu); + geo->all_luns = geo->num_ch * geo->num_lun; - geo->nr_chks = le32_to_cpu(id->num_chk); + geo->num_chk = le32_to_cpu(id->num_chk); geo->clba = le32_to_cpu(id->clba); - geo->all_chunks = geo->all_luns * geo->nr_chks; + geo->all_chunks = geo->all_luns * geo->num_chk; geo->total_secs = geo->clba * geo->all_chunks; geo->ws_min = le32_to_cpu(id->ws_min); @@ -484,7 +484,7 @@ static int nvme_nvm_get_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr ppa, struct nvme_ctrl *ctrl = ns->ctrl; struct nvme_nvm_command c = {}; struct nvme_nvm_bb_tbl *bb_tbl; - int nr_blks = geo->nr_chks * geo->num_pln; + int nr_blks = geo->num_chk * geo->num_pln; int tblsz = sizeof(struct nvme_nvm_bb_tbl) + nr_blks; int ret = 0; @@ -525,7 +525,7 @@ static int nvme_nvm_get_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr ppa, goto out; } - memcpy(blks, bb_tbl->blk, geo->nr_chks * geo->num_pln); + memcpy(blks, bb_tbl->blk, geo->num_chk * geo->num_pln); out: kfree(bb_tbl); return ret; @@ -968,7 +968,7 @@ static ssize_t nvm_dev_attr_show_ppaf(struct nvm_addrf_12 *ppaf, char *page) ppaf->pln_offset, ppaf->pln_len, ppaf->blk_offset, ppaf->blk_len, ppaf->pg_offset, ppaf->pg_len, - ppaf->sect_offset, ppaf->sect_len); + ppaf->sec_offset, ppaf->sec_len); } static ssize_t nvm_dev_attr_show_12(struct device *dev, @@ -998,13 +998,13 @@ static ssize_t nvm_dev_attr_show_12(struct device *dev, } else if (strcmp(attr->name, "flash_media_type") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", geo->fmtype); } else if (strcmp(attr->name, "num_channels") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chnls); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_ch); } else if (strcmp(attr->name, "num_luns") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_luns); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_lun); } else if (strcmp(attr->name, "num_planes") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_pln); } else if (strcmp(attr->name, "num_blocks") == 0) { /* u16 */ - return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chks); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_chk); } else if (strcmp(attr->name, "num_pages") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_pg); } else if (strcmp(attr->name, "page_size") == 0) { @@ -1048,11 +1048,11 @@ static ssize_t nvm_dev_attr_show_20(struct device *dev, attr = &dattr->attr; if (strcmp(attr->name, "groups") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chnls); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_ch); } else if (strcmp(attr->name, "punits") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_luns); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_lun); } else if (strcmp(attr->name, "chunks") == 0) { - return scnprintf(page, PAGE_SIZE, "%u\n", geo->nr_chks); + return scnprintf(page, PAGE_SIZE, "%u\n", geo->num_chk); } else if (strcmp(attr->name, "clba") == 0) { return scnprintf(page, PAGE_SIZE, "%u\n", geo->clba); } else if (strcmp(attr->name, "ws_min") == 0) { diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index 870959a58fef..00295d9f9522 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -163,14 +163,14 @@ struct nvm_addrf_12 { u8 blk_len; u8 pg_len; u8 pln_len; - u8 sect_len; + u8 sec_len; u8 ch_offset; u8 lun_offset; u8 blk_offset; u8 pg_offset; u8 pln_offset; - u8 sect_offset; + u8 sec_offset; u64 ch_mask; u64 lun_mask; @@ -275,8 +275,8 @@ struct nvm_geo { u8 version; /* instance specific geometry */ - int nr_chnls; - int nr_luns; /* per channel */ + int num_ch; + int num_lun; /* per channel */ /* calculated values */ int all_luns; /* across channels */ @@ -287,7 +287,7 @@ struct nvm_geo { sector_t total_secs; /* across channels */ /* chunk geometry */ - u32 nr_chks; /* chunks per lun */ + u32 num_chk; /* chunks per lun */ u32 clba; /* sectors per chunk */ u16 csecs; /* sector size */ u16 sos; /* out-of-band area size */ @@ -325,7 +325,7 @@ struct nvm_geo { u32 mpos; u8 num_pln; - u8 plane_mode; + u8 pln_mode; u16 num_pg; u16 fpg_sz; }; @@ -382,7 +382,7 @@ static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev, l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset; l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset; l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset; - l.ppa |= ((u64)r.g.sec) << ppaf->sect_offset; + l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset; return l; } @@ -401,7 +401,7 @@ static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev, l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset; l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset; l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset; - l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sect_offset; + l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset; return l; } -- cgit v1.2.3 From 694715137482b10d5be83b1dadf9a3cdee2ce1bc Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:15 +0200 Subject: lightnvm: add support for 2.0 address format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for 2.0 address format. Also, align address bits for 1.2 and 2.0 to be able to operate on channel and luns without requiring a format conversion. Use a generic address format for this purpose. Also, convert the generic operations to the generic format in pblk. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 20 ++++----- drivers/lightnvm/pblk-core.c | 10 ++--- drivers/lightnvm/pblk-map.c | 4 +- drivers/lightnvm/pblk-sysfs.c | 4 +- drivers/lightnvm/pblk.h | 4 +- include/linux/lightnvm.h | 101 +++++++++++++++++++++++++++++++----------- 6 files changed, 95 insertions(+), 48 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index 94b3b423840b..63d948cc6dec 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -194,8 +194,8 @@ static struct nvm_tgt_dev *nvm_create_tgt_dev(struct nvm_dev *dev, for (j = 0; j < luns_in_chnl; j++) { luns[lunid].ppa = 0; - luns[lunid].g.ch = i; - luns[lunid++].g.lun = j; + luns[lunid].a.ch = i; + luns[lunid++].a.lun = j; lun_offs[j] = blun; lun_roffs[j + blun] = blun; @@ -556,22 +556,22 @@ static void nvm_unregister_map(struct nvm_dev *dev) static void nvm_map_to_dev(struct nvm_tgt_dev *tgt_dev, struct ppa_addr *p) { struct nvm_dev_map *dev_map = tgt_dev->map; - struct nvm_ch_map *ch_map = &dev_map->chnls[p->g.ch]; - int lun_off = ch_map->lun_offs[p->g.lun]; + struct nvm_ch_map *ch_map = &dev_map->chnls[p->a.ch]; + int lun_off = ch_map->lun_offs[p->a.lun]; - p->g.ch += ch_map->ch_off; - p->g.lun += lun_off; + p->a.ch += ch_map->ch_off; + p->a.lun += lun_off; } static void nvm_map_to_tgt(struct nvm_tgt_dev *tgt_dev, struct ppa_addr *p) { struct nvm_dev *dev = tgt_dev->parent; struct nvm_dev_map *dev_rmap = dev->rmap; - struct nvm_ch_map *ch_rmap = &dev_rmap->chnls[p->g.ch]; - int lun_roff = ch_rmap->lun_offs[p->g.lun]; + struct nvm_ch_map *ch_rmap = &dev_rmap->chnls[p->a.ch]; + int lun_roff = ch_rmap->lun_offs[p->a.lun]; - p->g.ch -= ch_rmap->ch_off; - p->g.lun -= lun_roff; + p->a.ch -= ch_rmap->ch_off; + p->a.lun -= lun_roff; } static void nvm_ppa_tgt_to_dev(struct nvm_tgt_dev *tgt_dev, diff --git a/drivers/lightnvm/pblk-core.c b/drivers/lightnvm/pblk-core.c index 64c87dd4f1cd..c3eb135fce07 100644 --- a/drivers/lightnvm/pblk-core.c +++ b/drivers/lightnvm/pblk-core.c @@ -885,7 +885,7 @@ int pblk_line_erase(struct pblk *pblk, struct pblk_line *line) } ppa = pblk->luns[bit].bppa; /* set ch and lun */ - ppa.g.blk = line->id; + ppa.a.blk = line->id; atomic_dec(&line->left_eblks); WARN_ON(test_and_set_bit(bit, line->erase_bitmap)); @@ -1683,8 +1683,8 @@ static void __pblk_down_page(struct pblk *pblk, struct ppa_addr *ppa_list, int i; for (i = 1; i < nr_ppas; i++) - WARN_ON(ppa_list[0].g.lun != ppa_list[i].g.lun || - ppa_list[0].g.ch != ppa_list[i].g.ch); + WARN_ON(ppa_list[0].a.lun != ppa_list[i].a.lun || + ppa_list[0].a.ch != ppa_list[i].a.ch); #endif ret = down_timeout(&rlun->wr_sem, msecs_to_jiffies(30000)); @@ -1728,8 +1728,8 @@ void pblk_up_page(struct pblk *pblk, struct ppa_addr *ppa_list, int nr_ppas) int i; for (i = 1; i < nr_ppas; i++) - WARN_ON(ppa_list[0].g.lun != ppa_list[i].g.lun || - ppa_list[0].g.ch != ppa_list[i].g.ch); + WARN_ON(ppa_list[0].a.lun != ppa_list[i].a.lun || + ppa_list[0].a.ch != ppa_list[i].a.ch); #endif rlun = &pblk->luns[pos]; diff --git a/drivers/lightnvm/pblk-map.c b/drivers/lightnvm/pblk-map.c index 04e08d76ea5f..20dbaa89c9df 100644 --- a/drivers/lightnvm/pblk-map.c +++ b/drivers/lightnvm/pblk-map.c @@ -127,7 +127,7 @@ void pblk_map_erase_rq(struct pblk *pblk, struct nvm_rq *rqd, atomic_dec(&e_line->left_eblks); *erase_ppa = rqd->ppa_list[i]; - erase_ppa->g.blk = e_line->id; + erase_ppa->a.blk = e_line->id; spin_unlock(&e_line->lock); @@ -168,6 +168,6 @@ retry: set_bit(bit, e_line->erase_bitmap); atomic_dec(&e_line->left_eblks); *erase_ppa = pblk->luns[bit].bppa; /* set ch and lun */ - erase_ppa->g.blk = e_line->id; + erase_ppa->a.blk = e_line->id; } } diff --git a/drivers/lightnvm/pblk-sysfs.c b/drivers/lightnvm/pblk-sysfs.c index 3e9364f60b44..2489ea0edfa0 100644 --- a/drivers/lightnvm/pblk-sysfs.c +++ b/drivers/lightnvm/pblk-sysfs.c @@ -39,8 +39,8 @@ static ssize_t pblk_sysfs_luns_show(struct pblk *pblk, char *page) sz += snprintf(page + sz, PAGE_SIZE - sz, "pblk: pos:%d, ch:%d, lun:%d - %d\n", i, - rlun->bppa.g.ch, - rlun->bppa.g.lun, + rlun->bppa.a.ch, + rlun->bppa.a.lun, active); } diff --git a/drivers/lightnvm/pblk.h b/drivers/lightnvm/pblk.h index dcdad255ccb5..6607c41b23c0 100644 --- a/drivers/lightnvm/pblk.h +++ b/drivers/lightnvm/pblk.h @@ -936,12 +936,12 @@ static inline int pblk_pad_distance(struct pblk *pblk) static inline int pblk_ppa_to_line(struct ppa_addr p) { - return p.g.blk; + return p.a.blk; } static inline int pblk_ppa_to_pos(struct nvm_geo *geo, struct ppa_addr p) { - return p.g.lun * geo->num_ch + p.g.ch; + return p.a.lun * geo->num_ch + p.a.ch; } static inline struct ppa_addr addr_to_gen_ppa(struct pblk *pblk, u64 paddr, diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index 00295d9f9522..f2549b4b8626 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -16,12 +16,21 @@ enum { NVM_IOTYPE_GC = 1, }; -#define NVM_BLK_BITS (16) -#define NVM_PG_BITS (16) -#define NVM_SEC_BITS (8) -#define NVM_PL_BITS (8) -#define NVM_LUN_BITS (8) -#define NVM_CH_BITS (7) +/* common format */ +#define NVM_GEN_CH_BITS (8) +#define NVM_GEN_LUN_BITS (8) +#define NVM_GEN_BLK_BITS (16) +#define NVM_GEN_RESERVED (32) + +/* 1.2 format */ +#define NVM_12_PG_BITS (16) +#define NVM_12_PL_BITS (4) +#define NVM_12_SEC_BITS (4) +#define NVM_12_RESERVED (8) + +/* 2.0 format */ +#define NVM_20_SEC_BITS (24) +#define NVM_20_RESERVED (8) enum { NVM_OCSSD_SPEC_12 = 12, @@ -31,16 +40,34 @@ enum { struct ppa_addr { /* Generic structure for all addresses */ union { + /* generic device format */ struct { - u64 blk : NVM_BLK_BITS; - u64 pg : NVM_PG_BITS; - u64 sec : NVM_SEC_BITS; - u64 pl : NVM_PL_BITS; - u64 lun : NVM_LUN_BITS; - u64 ch : NVM_CH_BITS; - u64 reserved : 1; + u64 ch : NVM_GEN_CH_BITS; + u64 lun : NVM_GEN_LUN_BITS; + u64 blk : NVM_GEN_BLK_BITS; + u64 reserved : NVM_GEN_RESERVED; + } a; + + /* 1.2 device format */ + struct { + u64 ch : NVM_GEN_CH_BITS; + u64 lun : NVM_GEN_LUN_BITS; + u64 blk : NVM_GEN_BLK_BITS; + u64 pg : NVM_12_PG_BITS; + u64 pl : NVM_12_PL_BITS; + u64 sec : NVM_12_SEC_BITS; + u64 reserved : NVM_12_RESERVED; } g; + /* 2.0 device format */ + struct { + u64 grp : NVM_GEN_CH_BITS; + u64 pu : NVM_GEN_LUN_BITS; + u64 chk : NVM_GEN_BLK_BITS; + u64 sec : NVM_20_SEC_BITS; + u64 reserved : NVM_20_RESERVED; + } m; + struct { u64 line : 63; u64 is_cached : 1; @@ -374,15 +401,25 @@ static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev, struct ppa_addr r) { struct nvm_geo *geo = &tgt_dev->geo; - struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf; struct ppa_addr l; - l.ppa = ((u64)r.g.ch) << ppaf->ch_offset; - l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset; - l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset; - l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset; - l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset; - l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset; + if (geo->version == NVM_OCSSD_SPEC_12) { + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf; + + l.ppa = ((u64)r.g.ch) << ppaf->ch_offset; + l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset; + l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset; + l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset; + l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset; + l.ppa |= ((u64)r.g.sec) << ppaf->sec_offset; + } else { + struct nvm_addrf *lbaf = &geo->addrf; + + l.ppa = ((u64)r.m.grp) << lbaf->ch_offset; + l.ppa |= ((u64)r.m.pu) << lbaf->lun_offset; + l.ppa |= ((u64)r.m.chk) << lbaf->chk_offset; + l.ppa |= ((u64)r.m.sec) << lbaf->sec_offset; + } return l; } @@ -391,17 +428,27 @@ static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev, struct ppa_addr r) { struct nvm_geo *geo = &tgt_dev->geo; - struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf; struct ppa_addr l; l.ppa = 0; - l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset; - l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset; - l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset; - l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset; - l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset; - l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset; + if (geo->version == NVM_OCSSD_SPEC_12) { + struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf; + + l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset; + l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset; + l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset; + l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset; + l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset; + l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sec_offset; + } else { + struct nvm_addrf *lbaf = &geo->addrf; + + l.m.grp = (r.ppa & lbaf->ch_mask) >> lbaf->ch_offset; + l.m.pu = (r.ppa & lbaf->lun_mask) >> lbaf->lun_offset; + l.m.chk = (r.ppa & lbaf->chk_mask) >> lbaf->chk_offset; + l.m.sec = (r.ppa & lbaf->sec_mask) >> lbaf->sec_offset; + } return l; } -- cgit v1.2.3 From 7100d50a7e58a6884368001e2b1a32b7169c072c Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:16 +0200 Subject: lightnvm: make address conversions depend on generic device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On address conversions, use the generic device, instead of the target device. This allows to use conversions outside of the target's realm. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 4 ++-- include/linux/lightnvm.h | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index 63d948cc6dec..77901bf17416 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -581,7 +581,7 @@ static void nvm_ppa_tgt_to_dev(struct nvm_tgt_dev *tgt_dev, for (i = 0; i < nr_ppas; i++) { nvm_map_to_dev(tgt_dev, &ppa_list[i]); - ppa_list[i] = generic_to_dev_addr(tgt_dev, ppa_list[i]); + ppa_list[i] = generic_to_dev_addr(tgt_dev->parent, ppa_list[i]); } } @@ -591,7 +591,7 @@ static void nvm_ppa_dev_to_tgt(struct nvm_tgt_dev *tgt_dev, int i; for (i = 0; i < nr_ppas; i++) { - ppa_list[i] = dev_to_generic_addr(tgt_dev, ppa_list[i]); + ppa_list[i] = dev_to_generic_addr(tgt_dev->parent, ppa_list[i]); nvm_map_to_tgt(tgt_dev, &ppa_list[i]); } } diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index f2549b4b8626..f3b273e543c3 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -397,10 +397,10 @@ struct nvm_dev { struct list_head targets; }; -static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev, +static inline struct ppa_addr generic_to_dev_addr(struct nvm_dev *dev, struct ppa_addr r) { - struct nvm_geo *geo = &tgt_dev->geo; + struct nvm_geo *geo = &dev->geo; struct ppa_addr l; if (geo->version == NVM_OCSSD_SPEC_12) { @@ -424,10 +424,10 @@ static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev, return l; } -static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev, +static inline struct ppa_addr dev_to_generic_addr(struct nvm_dev *dev, struct ppa_addr r) { - struct nvm_geo *geo = &tgt_dev->geo; + struct nvm_geo *geo = &dev->geo; struct ppa_addr l; l.ppa = 0; -- cgit v1.2.3 From a294c199455187d124b0760fa8f86c13cdaa4b25 Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:17 +0200 Subject: lightnvm: implement get log report chunk helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 2.0 spec provides a report chunk log page that can be retrieved using the stangard nvme get log page. This replaces the dedicated get/put bad block table in 1.2. This patch implements the helper functions to allow targets retrieve the chunk metadata using get log page. It makes nvme_get_log_ext available outside of nvme core so that we can use it form lightnvm. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/core.c | 11 +++++++ drivers/nvme/host/core.c | 4 +-- drivers/nvme/host/lightnvm.c | 74 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/lightnvm.h | 24 ++++++++++++++ 4 files changed, 111 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/core.c b/drivers/lightnvm/core.c index 77901bf17416..63171cdce270 100644 --- a/drivers/lightnvm/core.c +++ b/drivers/lightnvm/core.c @@ -712,6 +712,17 @@ static void nvm_free_rqd_ppalist(struct nvm_tgt_dev *tgt_dev, nvm_dev_dma_free(tgt_dev->parent, rqd->ppa_list, rqd->dma_ppa_list); } +int nvm_get_chunk_meta(struct nvm_tgt_dev *tgt_dev, struct nvm_chk_meta *meta, + struct ppa_addr ppa, int nchks) +{ + struct nvm_dev *dev = tgt_dev->parent; + + nvm_ppa_tgt_to_dev(tgt_dev, &ppa, 1); + + return dev->ops->get_chk_meta(tgt_dev->parent, meta, + (sector_t)ppa.ppa, nchks); +} +EXPORT_SYMBOL(nvm_get_chunk_meta); int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *tgt_dev, struct ppa_addr *ppas, int nr_ppas, int type) diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index e7ec2fb5c59a..f81e3b323366 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -2219,8 +2219,8 @@ out_unlock: } int nvme_get_log_ext(struct nvme_ctrl *ctrl, struct nvme_ns *ns, - u8 log_page, void *log, - size_t size, size_t offset) + u8 log_page, void *log, + size_t size, size_t offset) { struct nvme_command c = { }; unsigned long dwlen = size / 4 - 1; diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index 08f0f6b5bc06..ffd64a83c8c3 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -35,6 +35,10 @@ enum nvme_nvm_admin_opcode { nvme_nvm_admin_set_bb_tbl = 0xf1, }; +enum nvme_nvm_log_page { + NVME_NVM_LOG_REPORT_CHUNK = 0xca, +}; + struct nvme_nvm_ph_rw { __u8 opcode; __u8 flags; @@ -236,6 +240,16 @@ struct nvme_nvm_id20 { __u8 vs[1024]; }; +struct nvme_nvm_chk_meta { + __u8 state; + __u8 type; + __u8 wi; + __u8 rsvd[5]; + __le64 slba; + __le64 cnlb; + __le64 wp; +}; + /* * Check we didn't inadvertently grow the command struct */ @@ -252,6 +266,9 @@ static inline void _nvme_nvm_check_size(void) BUILD_BUG_ON(sizeof(struct nvme_nvm_bb_tbl) != 64); BUILD_BUG_ON(sizeof(struct nvme_nvm_id20_addrf) != 8); BUILD_BUG_ON(sizeof(struct nvme_nvm_id20) != NVME_IDENTIFY_DATA_SIZE); + BUILD_BUG_ON(sizeof(struct nvme_nvm_chk_meta) != 32); + BUILD_BUG_ON(sizeof(struct nvme_nvm_chk_meta) != + sizeof(struct nvm_chk_meta)); } static void nvme_nvm_set_addr_12(struct nvm_addrf_12 *dst, @@ -552,6 +569,61 @@ static int nvme_nvm_set_bb_tbl(struct nvm_dev *nvmdev, struct ppa_addr *ppas, return ret; } +/* + * Expect the lba in device format + */ +static int nvme_nvm_get_chk_meta(struct nvm_dev *ndev, + struct nvm_chk_meta *meta, + sector_t slba, int nchks) +{ + struct nvm_geo *geo = &ndev->geo; + struct nvme_ns *ns = ndev->q->queuedata; + struct nvme_ctrl *ctrl = ns->ctrl; + struct nvme_nvm_chk_meta *dev_meta = (struct nvme_nvm_chk_meta *)meta; + struct ppa_addr ppa; + size_t left = nchks * sizeof(struct nvme_nvm_chk_meta); + size_t log_pos, offset, len; + int ret, i; + + /* Normalize lba address space to obtain log offset */ + ppa.ppa = slba; + ppa = dev_to_generic_addr(ndev, ppa); + + log_pos = ppa.m.chk; + log_pos += ppa.m.pu * geo->num_chk; + log_pos += ppa.m.grp * geo->num_lun * geo->num_chk; + + offset = log_pos * sizeof(struct nvme_nvm_chk_meta); + + while (left) { + len = min_t(unsigned int, left, ctrl->max_hw_sectors << 9); + + ret = nvme_get_log_ext(ctrl, ns, NVME_NVM_LOG_REPORT_CHUNK, + dev_meta, len, offset); + if (ret) { + dev_err(ctrl->device, "Get REPORT CHUNK log error\n"); + break; + } + + for (i = 0; i < len; i += sizeof(struct nvme_nvm_chk_meta)) { + meta->state = dev_meta->state; + meta->type = dev_meta->type; + meta->wi = dev_meta->wi; + meta->slba = le64_to_cpu(dev_meta->slba); + meta->cnlb = le64_to_cpu(dev_meta->cnlb); + meta->wp = le64_to_cpu(dev_meta->wp); + + meta++; + dev_meta++; + } + + offset += len; + left -= len; + } + + return ret; +} + static inline void nvme_nvm_rqtocmd(struct nvm_rq *rqd, struct nvme_ns *ns, struct nvme_nvm_command *c) { @@ -683,6 +755,8 @@ static struct nvm_dev_ops nvme_nvm_dev_ops = { .get_bb_tbl = nvme_nvm_get_bb_tbl, .set_bb_tbl = nvme_nvm_set_bb_tbl, + .get_chk_meta = nvme_nvm_get_chk_meta, + .submit_io = nvme_nvm_submit_io, .submit_io_sync = nvme_nvm_submit_io_sync, diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index f3b273e543c3..da45efa09bb2 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -81,10 +81,13 @@ struct nvm_rq; struct nvm_id; struct nvm_dev; struct nvm_tgt_dev; +struct nvm_chk_meta; typedef int (nvm_id_fn)(struct nvm_dev *); typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *); typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int); +typedef int (nvm_get_chk_meta_fn)(struct nvm_dev *, struct nvm_chk_meta *, + sector_t, int); typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *); typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *); typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *); @@ -98,6 +101,8 @@ struct nvm_dev_ops { nvm_op_bb_tbl_fn *get_bb_tbl; nvm_op_set_bb_fn *set_bb_tbl; + nvm_get_chk_meta_fn *get_chk_meta; + nvm_submit_io_fn *submit_io; nvm_submit_io_sync_fn *submit_io_sync; @@ -227,6 +232,20 @@ struct nvm_addrf { u64 rsv_mask[2]; }; +/* + * Note: The structure size is linked to nvme_nvm_chk_meta such that the same + * buffer can be used when converting from little endian to cpu addressing. + */ +struct nvm_chk_meta { + u8 state; + u8 type; + u8 wi; + u8 rsvd[5]; + u64 slba; + u64 cnlb; + u64 wp; +}; + struct nvm_target { struct list_head list; struct nvm_tgt_dev *dev; @@ -492,6 +511,11 @@ extern struct nvm_dev *nvm_alloc_dev(int); extern int nvm_register(struct nvm_dev *); extern void nvm_unregister(struct nvm_dev *); + +extern int nvm_get_chunk_meta(struct nvm_tgt_dev *tgt_dev, + struct nvm_chk_meta *meta, struct ppa_addr ppa, + int nchks); + extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *, int, int); extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *); -- cgit v1.2.3 From 32ef9412c1142c64b372b83d3740f234f4226317 Mon Sep 17 00:00:00 2001 From: Javier González Date: Fri, 30 Mar 2018 00:05:20 +0200 Subject: lightnvm: pblk: implement get log report chunk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In preparation of pblk supporting 2.0, implement the get log report chunk in pblk. Also, define the chunk states as given in the 2.0 spec. Signed-off-by: Javier González Signed-off-by: Matias Bjørling Signed-off-by: Jens Axboe --- drivers/lightnvm/pblk-core.c | 138 +++++++++++++++++++++++---- drivers/lightnvm/pblk-init.c | 222 ++++++++++++++++++++++++++++++------------- drivers/lightnvm/pblk.h | 7 ++ include/linux/lightnvm.h | 13 +++ 4 files changed, 298 insertions(+), 82 deletions(-) (limited to 'include/linux') diff --git a/drivers/lightnvm/pblk-core.c b/drivers/lightnvm/pblk-core.c index c3eb135fce07..94d5d97c9d8a 100644 --- a/drivers/lightnvm/pblk-core.c +++ b/drivers/lightnvm/pblk-core.c @@ -44,11 +44,12 @@ static void pblk_line_mark_bb(struct work_struct *work) } static void pblk_mark_bb(struct pblk *pblk, struct pblk_line *line, - struct ppa_addr *ppa) + struct ppa_addr ppa_addr) { struct nvm_tgt_dev *dev = pblk->dev; struct nvm_geo *geo = &dev->geo; - int pos = pblk_ppa_to_pos(geo, *ppa); + struct ppa_addr *ppa; + int pos = pblk_ppa_to_pos(geo, ppa_addr); pr_debug("pblk: erase failed: line:%d, pos:%d\n", line->id, pos); atomic_long_inc(&pblk->erase_failed); @@ -58,26 +59,38 @@ static void pblk_mark_bb(struct pblk *pblk, struct pblk_line *line, pr_err("pblk: attempted to erase bb: line:%d, pos:%d\n", line->id, pos); + /* Not necessary to mark bad blocks on 2.0 spec. */ + if (geo->version == NVM_OCSSD_SPEC_20) + return; + + ppa = kmalloc(sizeof(struct ppa_addr), GFP_ATOMIC); + if (!ppa) + return; + + *ppa = ppa_addr; pblk_gen_run_ws(pblk, NULL, ppa, pblk_line_mark_bb, GFP_ATOMIC, pblk->bb_wq); } static void __pblk_end_io_erase(struct pblk *pblk, struct nvm_rq *rqd) { + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + struct nvm_chk_meta *chunk; struct pblk_line *line; + int pos; line = &pblk->lines[pblk_ppa_to_line(rqd->ppa_addr)]; + pos = pblk_ppa_to_pos(geo, rqd->ppa_addr); + chunk = &line->chks[pos]; + atomic_dec(&line->left_seblks); if (rqd->error) { - struct ppa_addr *ppa; - - ppa = kmalloc(sizeof(struct ppa_addr), GFP_ATOMIC); - if (!ppa) - return; - - *ppa = rqd->ppa_addr; - pblk_mark_bb(pblk, line, ppa); + chunk->state = NVM_CHK_ST_OFFLINE; + pblk_mark_bb(pblk, line, rqd->ppa_addr); + } else { + chunk->state = NVM_CHK_ST_FREE; } atomic_dec(&pblk->inflight_io); @@ -92,6 +105,49 @@ static void pblk_end_io_erase(struct nvm_rq *rqd) mempool_free(rqd, pblk->e_rq_pool); } +/* + * Get information for all chunks from the device. + * + * The caller is responsible for freeing the returned structure + */ +struct nvm_chk_meta *pblk_chunk_get_info(struct pblk *pblk) +{ + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + struct nvm_chk_meta *meta; + struct ppa_addr ppa; + unsigned long len; + int ret; + + ppa.ppa = 0; + + len = geo->all_chunks * sizeof(*meta); + meta = kzalloc(len, GFP_KERNEL); + if (!meta) + return ERR_PTR(-ENOMEM); + + ret = nvm_get_chunk_meta(dev, meta, ppa, geo->all_chunks); + if (ret) { + kfree(meta); + return ERR_PTR(-EIO); + } + + return meta; +} + +struct nvm_chk_meta *pblk_chunk_get_off(struct pblk *pblk, + struct nvm_chk_meta *meta, + struct ppa_addr ppa) +{ + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + int ch_off = ppa.m.grp * geo->num_chk * geo->num_lun; + int lun_off = ppa.m.pu * geo->num_chk; + int chk_off = ppa.m.chk; + + return meta + ch_off + lun_off + chk_off; +} + void __pblk_map_invalidate(struct pblk *pblk, struct pblk_line *line, u64 paddr) { @@ -1091,10 +1147,34 @@ static int pblk_line_init_bb(struct pblk *pblk, struct pblk_line *line, return 1; } +static int pblk_prepare_new_line(struct pblk *pblk, struct pblk_line *line) +{ + struct pblk_line_meta *lm = &pblk->lm; + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + int blk_to_erase = atomic_read(&line->blk_in_line); + int i; + + for (i = 0; i < lm->blk_per_line; i++) { + struct pblk_lun *rlun = &pblk->luns[i]; + int pos = pblk_ppa_to_pos(geo, rlun->bppa); + int state = line->chks[pos].state; + + /* Free chunks should not be erased */ + if (state & NVM_CHK_ST_FREE) { + set_bit(pblk_ppa_to_pos(geo, rlun->bppa), + line->erase_bitmap); + blk_to_erase--; + } + } + + return blk_to_erase; +} + static int pblk_line_prepare(struct pblk *pblk, struct pblk_line *line) { struct pblk_line_meta *lm = &pblk->lm; - int blk_in_line = atomic_read(&line->blk_in_line); + int blk_to_erase; line->map_bitmap = kzalloc(lm->sec_bitmap_len, GFP_ATOMIC); if (!line->map_bitmap) @@ -1107,7 +1187,21 @@ static int pblk_line_prepare(struct pblk *pblk, struct pblk_line *line) return -ENOMEM; } + /* Bad blocks do not need to be erased */ + bitmap_copy(line->erase_bitmap, line->blk_bitmap, lm->blk_per_line); + spin_lock(&line->lock); + + /* If we have not written to this line, we need to mark up free chunks + * as already erased + */ + if (line->state == PBLK_LINESTATE_NEW) { + blk_to_erase = pblk_prepare_new_line(pblk, line); + line->state = PBLK_LINESTATE_FREE; + } else { + blk_to_erase = atomic_read(&line->blk_in_line); + } + if (line->state != PBLK_LINESTATE_FREE) { kfree(line->map_bitmap); kfree(line->invalid_bitmap); @@ -1119,15 +1213,12 @@ static int pblk_line_prepare(struct pblk *pblk, struct pblk_line *line) line->state = PBLK_LINESTATE_OPEN; - atomic_set(&line->left_eblks, blk_in_line); - atomic_set(&line->left_seblks, blk_in_line); + atomic_set(&line->left_eblks, blk_to_erase); + atomic_set(&line->left_seblks, blk_to_erase); line->meta_distance = lm->meta_distance; spin_unlock(&line->lock); - /* Bad blocks do not need to be erased */ - bitmap_copy(line->erase_bitmap, line->blk_bitmap, lm->blk_per_line); - kref_init(&line->ref); return 0; @@ -1583,12 +1674,14 @@ static void pblk_line_should_sync_meta(struct pblk *pblk) void pblk_line_close(struct pblk *pblk, struct pblk_line *line) { + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + struct pblk_line_meta *lm = &pblk->lm; struct pblk_line_mgmt *l_mg = &pblk->l_mg; struct list_head *move_list; + int i; #ifdef CONFIG_NVM_DEBUG - struct pblk_line_meta *lm = &pblk->lm; - WARN(!bitmap_full(line->map_bitmap, lm->sec_per_line), "pblk: corrupt closed line %d\n", line->id); #endif @@ -1610,6 +1703,15 @@ void pblk_line_close(struct pblk *pblk, struct pblk_line *line) line->smeta = NULL; line->emeta = NULL; + for (i = 0; i < lm->blk_per_line; i++) { + struct pblk_lun *rlun = &pblk->luns[i]; + int pos = pblk_ppa_to_pos(geo, rlun->bppa); + int state = line->chks[pos].state; + + if (!(state & NVM_CHK_ST_OFFLINE)) + state = NVM_CHK_ST_CLOSED; + } + spin_unlock(&line->lock); spin_unlock(&l_mg->gc_lock); } diff --git a/drivers/lightnvm/pblk-init.c b/drivers/lightnvm/pblk-init.c index 5b381700ef30..27b4974930b4 100644 --- a/drivers/lightnvm/pblk-init.c +++ b/drivers/lightnvm/pblk-init.c @@ -451,6 +451,7 @@ static void pblk_line_meta_free(struct pblk_line *line) { kfree(line->blk_bitmap); kfree(line->erase_bitmap); + kfree(line->chks); } static void pblk_lines_free(struct pblk *pblk) @@ -495,55 +496,44 @@ static int pblk_bb_get_tbl(struct nvm_tgt_dev *dev, struct pblk_lun *rlun, return 0; } -static void *pblk_bb_get_log(struct pblk *pblk) +static void *pblk_bb_get_meta(struct pblk *pblk) { struct nvm_tgt_dev *dev = pblk->dev; struct nvm_geo *geo = &dev->geo; - u8 *log; + u8 *meta; int i, nr_blks, blk_per_lun; int ret; blk_per_lun = geo->num_chk * geo->pln_mode; nr_blks = blk_per_lun * geo->all_luns; - log = kmalloc(nr_blks, GFP_KERNEL); - if (!log) + meta = kmalloc(nr_blks, GFP_KERNEL); + if (!meta) return ERR_PTR(-ENOMEM); for (i = 0; i < geo->all_luns; i++) { struct pblk_lun *rlun = &pblk->luns[i]; - u8 *log_pos = log + i * blk_per_lun; + u8 *meta_pos = meta + i * blk_per_lun; - ret = pblk_bb_get_tbl(dev, rlun, log_pos, blk_per_lun); + ret = pblk_bb_get_tbl(dev, rlun, meta_pos, blk_per_lun); if (ret) { - kfree(log); + kfree(meta); return ERR_PTR(-EIO); } } - return log; + return meta; } -static int pblk_bb_line(struct pblk *pblk, struct pblk_line *line, - u8 *bb_log, int blk_per_line) +static void *pblk_chunk_get_meta(struct pblk *pblk) { struct nvm_tgt_dev *dev = pblk->dev; struct nvm_geo *geo = &dev->geo; - int i, bb_cnt = 0; - int blk_per_lun = geo->num_chk * geo->pln_mode; - for (i = 0; i < blk_per_line; i++) { - struct pblk_lun *rlun = &pblk->luns[i]; - u8 *lun_bb_log = bb_log + i * blk_per_lun; - - if (lun_bb_log[line->id] == NVM_BLK_T_FREE) - continue; - - set_bit(pblk_ppa_to_pos(geo, rlun->bppa), line->blk_bitmap); - bb_cnt++; - } - - return bb_cnt; + if (geo->version == NVM_OCSSD_SPEC_12) + return pblk_bb_get_meta(pblk); + else + return pblk_chunk_get_info(pblk); } static int pblk_luns_init(struct pblk *pblk) @@ -644,8 +634,131 @@ static void pblk_set_provision(struct pblk *pblk, long nr_free_blks) atomic_set(&pblk->rl.free_user_blocks, nr_free_blks); } -static int pblk_setup_line_meta(struct pblk *pblk, struct pblk_line *line, - void *chunk_log, long *nr_bad_blks) +static int pblk_setup_line_meta_12(struct pblk *pblk, struct pblk_line *line, + void *chunk_meta) +{ + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + struct pblk_line_meta *lm = &pblk->lm; + int i, chk_per_lun, nr_bad_chks = 0; + + chk_per_lun = geo->num_chk * geo->pln_mode; + + for (i = 0; i < lm->blk_per_line; i++) { + struct pblk_lun *rlun = &pblk->luns[i]; + struct nvm_chk_meta *chunk; + int pos = pblk_ppa_to_pos(geo, rlun->bppa); + u8 *lun_bb_meta = chunk_meta + pos * chk_per_lun; + + chunk = &line->chks[pos]; + + /* + * In 1.2 spec. chunk state is not persisted by the device. Thus + * some of the values are reset each time pblk is instantiated. + */ + if (lun_bb_meta[line->id] == NVM_BLK_T_FREE) + chunk->state = NVM_CHK_ST_FREE; + else + chunk->state = NVM_CHK_ST_OFFLINE; + + chunk->type = NVM_CHK_TP_W_SEQ; + chunk->wi = 0; + chunk->slba = -1; + chunk->cnlb = geo->clba; + chunk->wp = 0; + + if (!(chunk->state & NVM_CHK_ST_OFFLINE)) + continue; + + set_bit(pos, line->blk_bitmap); + nr_bad_chks++; + } + + return nr_bad_chks; +} + +static int pblk_setup_line_meta_20(struct pblk *pblk, struct pblk_line *line, + struct nvm_chk_meta *meta) +{ + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + struct pblk_line_meta *lm = &pblk->lm; + int i, nr_bad_chks = 0; + + for (i = 0; i < lm->blk_per_line; i++) { + struct pblk_lun *rlun = &pblk->luns[i]; + struct nvm_chk_meta *chunk; + struct nvm_chk_meta *chunk_meta; + struct ppa_addr ppa; + int pos; + + ppa = rlun->bppa; + pos = pblk_ppa_to_pos(geo, ppa); + chunk = &line->chks[pos]; + + ppa.m.chk = line->id; + chunk_meta = pblk_chunk_get_off(pblk, meta, ppa); + + chunk->state = chunk_meta->state; + chunk->type = chunk_meta->type; + chunk->wi = chunk_meta->wi; + chunk->slba = chunk_meta->slba; + chunk->cnlb = chunk_meta->cnlb; + chunk->wp = chunk_meta->wp; + + if (!(chunk->state & NVM_CHK_ST_OFFLINE)) + continue; + + if (chunk->type & NVM_CHK_TP_SZ_SPEC) { + WARN_ONCE(1, "pblk: custom-sized chunks unsupported\n"); + continue; + } + + set_bit(pos, line->blk_bitmap); + nr_bad_chks++; + } + + return nr_bad_chks; +} + +static long pblk_setup_line_meta(struct pblk *pblk, struct pblk_line *line, + void *chunk_meta, int line_id) +{ + struct nvm_tgt_dev *dev = pblk->dev; + struct nvm_geo *geo = &dev->geo; + struct pblk_line_mgmt *l_mg = &pblk->l_mg; + struct pblk_line_meta *lm = &pblk->lm; + long nr_bad_chks, chk_in_line; + + line->pblk = pblk; + line->id = line_id; + line->type = PBLK_LINETYPE_FREE; + line->state = PBLK_LINESTATE_NEW; + line->gc_group = PBLK_LINEGC_NONE; + line->vsc = &l_mg->vsc_list[line_id]; + spin_lock_init(&line->lock); + + if (geo->version == NVM_OCSSD_SPEC_12) + nr_bad_chks = pblk_setup_line_meta_12(pblk, line, chunk_meta); + else + nr_bad_chks = pblk_setup_line_meta_20(pblk, line, chunk_meta); + + chk_in_line = lm->blk_per_line - nr_bad_chks; + if (nr_bad_chks < 0 || nr_bad_chks > lm->blk_per_line || + chk_in_line < lm->min_blk_line) { + line->state = PBLK_LINESTATE_BAD; + list_add_tail(&line->list, &l_mg->bad_list); + return 0; + } + + atomic_set(&line->blk_in_line, chk_in_line); + list_add_tail(&line->list, &l_mg->free_list); + l_mg->nr_free_lines++; + + return chk_in_line; +} + +static int pblk_alloc_line_meta(struct pblk *pblk, struct pblk_line *line) { struct pblk_line_meta *lm = &pblk->lm; @@ -659,7 +772,13 @@ static int pblk_setup_line_meta(struct pblk *pblk, struct pblk_line *line, return -ENOMEM; } - *nr_bad_blks = pblk_bb_line(pblk, line, chunk_log, lm->blk_per_line); + line->chks = kmalloc(lm->blk_per_line * sizeof(struct nvm_chk_meta), + GFP_KERNEL); + if (!line->chks) { + kfree(line->erase_bitmap); + kfree(line->blk_bitmap); + return -ENOMEM; + } return 0; } @@ -846,10 +965,9 @@ add_emeta_page: static int pblk_lines_init(struct pblk *pblk) { struct pblk_line_mgmt *l_mg = &pblk->l_mg; - struct pblk_line_meta *lm = &pblk->lm; struct pblk_line *line; - void *chunk_log; - long nr_bad_blks = 0, nr_free_blks = 0; + void *chunk_meta; + long nr_free_chks = 0; int i, ret; ret = pblk_line_meta_init(pblk); @@ -864,11 +982,9 @@ static int pblk_lines_init(struct pblk *pblk) if (ret) goto fail_free_meta; - chunk_log = pblk_bb_get_log(pblk); - if (IS_ERR(chunk_log)) { - pr_err("pblk: could not get bad block log (%lu)\n", - PTR_ERR(chunk_log)); - ret = PTR_ERR(chunk_log); + chunk_meta = pblk_chunk_get_meta(pblk); + if (IS_ERR(chunk_meta)) { + ret = PTR_ERR(chunk_meta); goto fail_free_luns; } @@ -876,52 +992,30 @@ static int pblk_lines_init(struct pblk *pblk) GFP_KERNEL); if (!pblk->lines) { ret = -ENOMEM; - goto fail_free_chunk_log; + goto fail_free_chunk_meta; } for (i = 0; i < l_mg->nr_lines; i++) { - int chk_in_line; - line = &pblk->lines[i]; - line->pblk = pblk; - line->id = i; - line->type = PBLK_LINETYPE_FREE; - line->state = PBLK_LINESTATE_FREE; - line->gc_group = PBLK_LINEGC_NONE; - line->vsc = &l_mg->vsc_list[i]; - spin_lock_init(&line->lock); - - ret = pblk_setup_line_meta(pblk, line, chunk_log, &nr_bad_blks); + ret = pblk_alloc_line_meta(pblk, line); if (ret) goto fail_free_lines; - chk_in_line = lm->blk_per_line - nr_bad_blks; - if (nr_bad_blks < 0 || nr_bad_blks > lm->blk_per_line || - chk_in_line < lm->min_blk_line) { - line->state = PBLK_LINESTATE_BAD; - list_add_tail(&line->list, &l_mg->bad_list); - continue; - } - - nr_free_blks += chk_in_line; - atomic_set(&line->blk_in_line, chk_in_line); - - l_mg->nr_free_lines++; - list_add_tail(&line->list, &l_mg->free_list); + nr_free_chks += pblk_setup_line_meta(pblk, line, chunk_meta, i); } - pblk_set_provision(pblk, nr_free_blks); + pblk_set_provision(pblk, nr_free_chks); - kfree(chunk_log); + kfree(chunk_meta); return 0; fail_free_lines: while (--i >= 0) pblk_line_meta_free(&pblk->lines[i]); kfree(pblk->lines); -fail_free_chunk_log: - kfree(chunk_log); +fail_free_chunk_meta: + kfree(chunk_meta); fail_free_luns: kfree(pblk->luns); fail_free_meta: diff --git a/drivers/lightnvm/pblk.h b/drivers/lightnvm/pblk.h index 40aee9e48af4..39e47e3d6f23 100644 --- a/drivers/lightnvm/pblk.h +++ b/drivers/lightnvm/pblk.h @@ -297,6 +297,7 @@ enum { PBLK_LINETYPE_DATA = 2, /* Line state */ + PBLK_LINESTATE_NEW = 9, PBLK_LINESTATE_FREE = 10, PBLK_LINESTATE_OPEN = 11, PBLK_LINESTATE_CLOSED = 12, @@ -426,6 +427,8 @@ struct pblk_line { unsigned long *lun_bitmap; /* Bitmap for LUNs mapped in line */ + struct nvm_chk_meta *chks; /* Chunks forming line */ + struct pblk_smeta *smeta; /* Start metadata */ struct pblk_emeta *emeta; /* End medatada */ @@ -729,6 +732,10 @@ void pblk_set_sec_per_write(struct pblk *pblk, int sec_per_write); int pblk_setup_w_rec_rq(struct pblk *pblk, struct nvm_rq *rqd, struct pblk_c_ctx *c_ctx); void pblk_discard(struct pblk *pblk, struct bio *bio); +struct nvm_chk_meta *pblk_chunk_get_info(struct pblk *pblk); +struct nvm_chk_meta *pblk_chunk_get_off(struct pblk *pblk, + struct nvm_chk_meta *lp, + struct ppa_addr ppa); void pblk_log_write_err(struct pblk *pblk, struct nvm_rq *rqd); void pblk_log_read_err(struct pblk *pblk, struct nvm_rq *rqd); int pblk_submit_io(struct pblk *pblk, struct nvm_rq *rqd); diff --git a/include/linux/lightnvm.h b/include/linux/lightnvm.h index da45efa09bb2..6e0859b9d4d2 100644 --- a/include/linux/lightnvm.h +++ b/include/linux/lightnvm.h @@ -232,6 +232,19 @@ struct nvm_addrf { u64 rsv_mask[2]; }; +enum { + /* Chunk states */ + NVM_CHK_ST_FREE = 1 << 0, + NVM_CHK_ST_CLOSED = 1 << 1, + NVM_CHK_ST_OPEN = 1 << 2, + NVM_CHK_ST_OFFLINE = 1 << 3, + + /* Chunk types */ + NVM_CHK_TP_W_SEQ = 1 << 0, + NVM_CHK_TP_W_RAN = 1 << 1, + NVM_CHK_TP_SZ_SPEC = 1 << 4, +}; + /* * Note: The structure size is linked to nvme_nvm_chk_meta such that the same * buffer can be used when converting from little endian to cpu addressing. -- cgit v1.2.3 From b575454fa330aab2d65cf17812ca8e1f405ae80d Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Wed, 14 Feb 2018 01:08:15 +1000 Subject: mm: make memblock_alloc_base_nid() non-static This will be used by powerpc to allocate per-cpu stacks and other data structures node-local where possible. Signed-off-by: Nicholas Piggin [mpe: Drop stray change to memblock_alloc_range() as noticed by akpm] Signed-off-by: Michael Ellerman --- include/linux/memblock.h | 3 +++ mm/memblock.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/memblock.h b/include/linux/memblock.h index 8be5077efb5f..4e1e3d0b002a 100644 --- a/include/linux/memblock.h +++ b/include/linux/memblock.h @@ -319,6 +319,9 @@ static inline bool memblock_bottom_up(void) phys_addr_t __init memblock_alloc_range(phys_addr_t size, phys_addr_t align, phys_addr_t start, phys_addr_t end, ulong flags); +phys_addr_t memblock_alloc_base_nid(phys_addr_t size, + phys_addr_t align, phys_addr_t max_addr, + int nid, ulong flags); phys_addr_t memblock_alloc_base(phys_addr_t size, phys_addr_t align, phys_addr_t max_addr); phys_addr_t __memblock_alloc_base(phys_addr_t size, phys_addr_t align, diff --git a/mm/memblock.c b/mm/memblock.c index 5a9ca2a1751b..cea2af494da0 100644 --- a/mm/memblock.c +++ b/mm/memblock.c @@ -1190,7 +1190,7 @@ phys_addr_t __init memblock_alloc_range(phys_addr_t size, phys_addr_t align, flags); } -static phys_addr_t __init memblock_alloc_base_nid(phys_addr_t size, +phys_addr_t __init memblock_alloc_base_nid(phys_addr_t size, phys_addr_t align, phys_addr_t max_addr, int nid, ulong flags) { -- cgit v1.2.3 From 9daae9bd47cff82a2a06aca23c458d6c79d09d52 Mon Sep 17 00:00:00 2001 From: Gal Pressman Date: Wed, 28 Mar 2018 17:46:54 +0300 Subject: net: Call add/kill vid ndo on vlan filter feature toggling NETIF_F_HW_VLAN_[CS]TAG_FILTER features require more than just a bit flip in dev->features in order to keep the driver in a consistent state. These features notify the driver of each added/removed vlan, but toggling of vlan-filter does not notify the driver accordingly for each of the existing vlans. This patch implements a similar solution to NETIF_F_RX_UDP_TUNNEL_PORT behavior (which notifies the driver about UDP ports in the same manner that vids are reported). Each toggling of the features propagates to the 8021q module, which iterates over the vlans and call add/kill ndo accordingly. Signed-off-by: Gal Pressman Reviewed-by: Tariq Toukan Signed-off-by: David S. Miller --- include/linux/if_vlan.h | 24 +++++++++++ include/linux/netdevice.h | 4 ++ net/8021q/vlan.c | 21 ++++++++++ net/8021q/vlan.h | 3 ++ net/8021q/vlan_core.c | 101 ++++++++++++++++++++++++++++++++++------------ net/core/dev.c | 20 +++++++++ 6 files changed, 148 insertions(+), 25 deletions(-) (limited to 'include/linux') diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index c4a1cff9c768..24d1976c1e61 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -83,6 +83,30 @@ static inline bool is_vlan_dev(const struct net_device *dev) #define skb_vlan_tag_get_id(__skb) ((__skb)->vlan_tci & VLAN_VID_MASK) #define skb_vlan_tag_get_prio(__skb) ((__skb)->vlan_tci & VLAN_PRIO_MASK) +static inline int vlan_get_rx_ctag_filter_info(struct net_device *dev) +{ + ASSERT_RTNL(); + return notifier_to_errno(call_netdevice_notifiers(NETDEV_CVLAN_FILTER_PUSH_INFO, dev)); +} + +static inline void vlan_drop_rx_ctag_filter_info(struct net_device *dev) +{ + ASSERT_RTNL(); + call_netdevice_notifiers(NETDEV_CVLAN_FILTER_DROP_INFO, dev); +} + +static inline int vlan_get_rx_stag_filter_info(struct net_device *dev) +{ + ASSERT_RTNL(); + return notifier_to_errno(call_netdevice_notifiers(NETDEV_SVLAN_FILTER_PUSH_INFO, dev)); +} + +static inline void vlan_drop_rx_stag_filter_info(struct net_device *dev) +{ + ASSERT_RTNL(); + call_netdevice_notifiers(NETDEV_SVLAN_FILTER_DROP_INFO, dev); +} + /** * struct vlan_pcpu_stats - VLAN percpu rx/tx stats * @rx_packets: number of received packets diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 2a2d9cf50aa2..da44dab492e3 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -2349,6 +2349,10 @@ enum netdev_cmd { NETDEV_UDP_TUNNEL_PUSH_INFO, NETDEV_UDP_TUNNEL_DROP_INFO, NETDEV_CHANGE_TX_QUEUE_LEN, + NETDEV_CVLAN_FILTER_PUSH_INFO, + NETDEV_CVLAN_FILTER_DROP_INFO, + NETDEV_SVLAN_FILTER_PUSH_INFO, + NETDEV_SVLAN_FILTER_DROP_INFO, }; const char *netdev_cmd_to_name(enum netdev_cmd cmd); diff --git a/net/8021q/vlan.c b/net/8021q/vlan.c index bad01b14a4ad..5505ee6ebdbe 100644 --- a/net/8021q/vlan.c +++ b/net/8021q/vlan.c @@ -360,6 +360,7 @@ static int vlan_device_event(struct notifier_block *unused, unsigned long event, struct vlan_dev_priv *vlan; bool last = false; LIST_HEAD(list); + int err; if (is_vlan_dev(dev)) { int err = __vlan_device_event(dev, event); @@ -489,6 +490,26 @@ static int vlan_device_event(struct notifier_block *unused, unsigned long event, vlan_group_for_each_dev(grp, i, vlandev) call_netdevice_notifiers(event, vlandev); break; + + case NETDEV_CVLAN_FILTER_PUSH_INFO: + err = vlan_filter_push_vids(vlan_info, htons(ETH_P_8021Q)); + if (err) + return notifier_from_errno(err); + break; + + case NETDEV_CVLAN_FILTER_DROP_INFO: + vlan_filter_drop_vids(vlan_info, htons(ETH_P_8021Q)); + break; + + case NETDEV_SVLAN_FILTER_PUSH_INFO: + err = vlan_filter_push_vids(vlan_info, htons(ETH_P_8021AD)); + if (err) + return notifier_from_errno(err); + break; + + case NETDEV_SVLAN_FILTER_DROP_INFO: + vlan_filter_drop_vids(vlan_info, htons(ETH_P_8021AD)); + break; } out: diff --git a/net/8021q/vlan.h b/net/8021q/vlan.h index a8ba51030b75..e23aac3e4d37 100644 --- a/net/8021q/vlan.h +++ b/net/8021q/vlan.h @@ -97,6 +97,9 @@ static inline struct net_device *vlan_find_dev(struct net_device *real_dev, if (((dev) = __vlan_group_get_device((grp), (i) / VLAN_N_VID, \ (i) % VLAN_N_VID))) +int vlan_filter_push_vids(struct vlan_info *vlan_info, __be16 proto); +void vlan_filter_drop_vids(struct vlan_info *vlan_info, __be16 proto); + /* found in vlan_dev.c */ void vlan_dev_set_ingress_priority(const struct net_device *dev, u32 skb_prio, u16 vlan_prio); diff --git a/net/8021q/vlan_core.c b/net/8021q/vlan_core.c index 45c9bf5ff3a0..c8d7abdc0463 100644 --- a/net/8021q/vlan_core.c +++ b/net/8021q/vlan_core.c @@ -165,13 +165,12 @@ struct vlan_vid_info { int refcount; }; -static bool vlan_hw_filter_capable(const struct net_device *dev, - const struct vlan_vid_info *vid_info) +bool vlan_hw_filter_capable(const struct net_device *dev, __be16 proto) { - if (vid_info->proto == htons(ETH_P_8021Q) && + if (proto == htons(ETH_P_8021Q) && dev->features & NETIF_F_HW_VLAN_CTAG_FILTER) return true; - if (vid_info->proto == htons(ETH_P_8021AD) && + if (proto == htons(ETH_P_8021AD) && dev->features & NETIF_F_HW_VLAN_STAG_FILTER) return true; return false; @@ -202,11 +201,73 @@ static struct vlan_vid_info *vlan_vid_info_alloc(__be16 proto, u16 vid) return vid_info; } +static int vlan_add_rx_filter_info(struct net_device *dev, __be16 proto, u16 vid) +{ + if (!vlan_hw_filter_capable(dev, proto)) + return 0; + + if (netif_device_present(dev)) + return dev->netdev_ops->ndo_vlan_rx_add_vid(dev, proto, vid); + else + return -ENODEV; +} + +static int vlan_kill_rx_filter_info(struct net_device *dev, __be16 proto, u16 vid) +{ + if (!vlan_hw_filter_capable(dev, proto)) + return 0; + + if (netif_device_present(dev)) + return dev->netdev_ops->ndo_vlan_rx_kill_vid(dev, proto, vid); + else + return -ENODEV; +} + +int vlan_filter_push_vids(struct vlan_info *vlan_info, __be16 proto) +{ + struct net_device *real_dev = vlan_info->real_dev; + struct vlan_vid_info *vlan_vid_info; + int err; + + list_for_each_entry(vlan_vid_info, &vlan_info->vid_list, list) { + if (vlan_vid_info->proto == proto) { + err = vlan_add_rx_filter_info(real_dev, proto, + vlan_vid_info->vid); + if (err) + goto unwind; + } + } + + return 0; + +unwind: + list_for_each_entry_continue_reverse(vlan_vid_info, + &vlan_info->vid_list, list) { + if (vlan_vid_info->proto == proto) + vlan_kill_rx_filter_info(real_dev, proto, + vlan_vid_info->vid); + } + + return err; +} +EXPORT_SYMBOL(vlan_filter_push_vids); + +void vlan_filter_drop_vids(struct vlan_info *vlan_info, __be16 proto) +{ + struct vlan_vid_info *vlan_vid_info; + + list_for_each_entry(vlan_vid_info, &vlan_info->vid_list, list) + if (vlan_vid_info->proto == proto) + vlan_kill_rx_filter_info(vlan_info->real_dev, + vlan_vid_info->proto, + vlan_vid_info->vid); +} +EXPORT_SYMBOL(vlan_filter_drop_vids); + static int __vlan_vid_add(struct vlan_info *vlan_info, __be16 proto, u16 vid, struct vlan_vid_info **pvid_info) { struct net_device *dev = vlan_info->real_dev; - const struct net_device_ops *ops = dev->netdev_ops; struct vlan_vid_info *vid_info; int err; @@ -214,16 +275,12 @@ static int __vlan_vid_add(struct vlan_info *vlan_info, __be16 proto, u16 vid, if (!vid_info) return -ENOMEM; - if (vlan_hw_filter_capable(dev, vid_info)) { - if (netif_device_present(dev)) - err = ops->ndo_vlan_rx_add_vid(dev, proto, vid); - else - err = -ENODEV; - if (err) { - kfree(vid_info); - return err; - } + err = vlan_add_rx_filter_info(dev, proto, vid); + if (err) { + kfree(vid_info); + return err; } + list_add(&vid_info->list, &vlan_info->vid_list); vlan_info->nr_vids++; *pvid_info = vid_info; @@ -270,21 +327,15 @@ static void __vlan_vid_del(struct vlan_info *vlan_info, struct vlan_vid_info *vid_info) { struct net_device *dev = vlan_info->real_dev; - const struct net_device_ops *ops = dev->netdev_ops; __be16 proto = vid_info->proto; u16 vid = vid_info->vid; int err; - if (vlan_hw_filter_capable(dev, vid_info)) { - if (netif_device_present(dev)) - err = ops->ndo_vlan_rx_kill_vid(dev, proto, vid); - else - err = -ENODEV; - if (err) { - pr_warn("failed to kill vid %04x/%d for device %s\n", - proto, vid, dev->name); - } - } + err = vlan_kill_rx_filter_info(dev, proto, vid); + if (err) + pr_warn("failed to kill vid %04x/%d for device %s\n", + proto, vid, dev->name); + list_del(&vid_info->list); kfree(vid_info); vlan_info->nr_vids--; diff --git a/net/core/dev.c b/net/core/dev.c index eca5458b2753..1ddb6b9c58a8 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -1584,6 +1584,8 @@ const char *netdev_cmd_to_name(enum netdev_cmd cmd) N(RESEND_IGMP) N(PRECHANGEMTU) N(CHANGEINFODATA) N(BONDING_INFO) N(PRECHANGEUPPER) N(CHANGELOWERSTATE) N(UDP_TUNNEL_PUSH_INFO) N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN) + N(CVLAN_FILTER_PUSH_INFO) N(CVLAN_FILTER_DROP_INFO) + N(SVLAN_FILTER_PUSH_INFO) N(SVLAN_FILTER_DROP_INFO) }; #undef N return "UNKNOWN_NETDEV_EVENT"; @@ -7665,6 +7667,24 @@ sync_lower: } } + if (diff & NETIF_F_HW_VLAN_CTAG_FILTER) { + if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { + dev->features = features; + err |= vlan_get_rx_ctag_filter_info(dev); + } else { + vlan_drop_rx_ctag_filter_info(dev); + } + } + + if (diff & NETIF_F_HW_VLAN_STAG_FILTER) { + if (features & NETIF_F_HW_VLAN_STAG_FILTER) { + dev->features = features; + err |= vlan_get_rx_stag_filter_info(dev); + } else { + vlan_drop_rx_stag_filter_info(dev); + } + } + dev->features = features; } -- cgit v1.2.3 From c6ab3008b6a6ecda22e92f96a1b9cc6b0d0b0a4e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 28 Mar 2018 15:44:15 -0700 Subject: net: phy: phylink: Provide PHY interface to mac_link_{up, down} In preparation for having DSA transition entirely to PHYLINK, we need to pass a PHY interface type to the mac_link_{up,down} callbacks because we may have to make decisions on that (e.g: turn on/off RGMII interfaces etc.). We do not pass an entire phylink_link_state because not all parameters (pause, duplex etc.) are defined when the link is down, only link and interface are. Update mvneta accordingly since it currently implements phylink_mac_ops. Acked-by: Russell King Signed-off-by: Florian Fainelli Acked-by: Russell King Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvneta.c | 4 +++- drivers/net/phy/phylink.c | 4 +++- include/linux/phylink.h | 14 +++++++++++--- 3 files changed, 17 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index eaa4bb80f1c9..cd09bde55596 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -3396,7 +3396,8 @@ static void mvneta_set_eee(struct mvneta_port *pp, bool enable) mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); } -static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode) +static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode, + phy_interface_t interface) { struct mvneta_port *pp = netdev_priv(ndev); u32 val; @@ -3415,6 +3416,7 @@ static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode) } static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode, + phy_interface_t interface, struct phy_device *phy) { struct mvneta_port *pp = netdev_priv(ndev); diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 51a011a349fe..9b1e4721ea3a 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -470,10 +470,12 @@ static void phylink_resolve(struct work_struct *w) if (link_state.link != netif_carrier_ok(ndev)) { if (!link_state.link) { netif_carrier_off(ndev); - pl->ops->mac_link_down(ndev, pl->link_an_mode); + pl->ops->mac_link_down(ndev, pl->link_an_mode, + pl->phy_state.interface); netdev_info(ndev, "Link is Down\n"); } else { pl->ops->mac_link_up(ndev, pl->link_an_mode, + pl->phy_state.interface, pl->phydev); netif_carrier_on(ndev); diff --git a/include/linux/phylink.h b/include/linux/phylink.h index bd137c273d38..e95cc12030fa 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -73,8 +73,10 @@ struct phylink_mac_ops { void (*mac_config)(struct net_device *ndev, unsigned int mode, const struct phylink_link_state *state); void (*mac_an_restart)(struct net_device *ndev); - void (*mac_link_down)(struct net_device *ndev, unsigned int mode); + void (*mac_link_down)(struct net_device *ndev, unsigned int mode, + phy_interface_t interface); void (*mac_link_up)(struct net_device *ndev, unsigned int mode, + phy_interface_t interface, struct phy_device *phy); }; @@ -161,25 +163,31 @@ void mac_an_restart(struct net_device *ndev); * mac_link_down() - take the link down * @ndev: a pointer to a &struct net_device for the MAC. * @mode: link autonegotiation mode + * @interface: link &typedef phy_interface_t mode * * If @mode is not an in-band negotiation mode (as defined by * phylink_autoneg_inband()), force the link down and disable any - * Energy Efficient Ethernet MAC configuration. + * Energy Efficient Ethernet MAC configuration. Interface type + * selection must be done in mac_config(). */ -void mac_link_down(struct net_device *ndev, unsigned int mode); +void mac_link_down(struct net_device *ndev, unsigned int mode, + phy_interface_t interface); /** * mac_link_up() - allow the link to come up * @ndev: a pointer to a &struct net_device for the MAC. * @mode: link autonegotiation mode + * @interface: link &typedef phy_interface_t mode * @phy: any attached phy * * If @mode is not an in-band negotiation mode (as defined by * phylink_autoneg_inband()), allow the link to come up. If @phy * is non-%NULL, configure Energy Efficient Ethernet by calling * phy_init_eee() and perform appropriate MAC configuration for EEE. + * Interface type selection must be done in mac_config(). */ void mac_link_up(struct net_device *ndev, unsigned int mode, + phy_interface_t interface, struct phy_device *phy); #endif -- cgit v1.2.3 From e679c9c1dbfdba07b2a979a076cca74b773be8ce Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 28 Mar 2018 15:44:16 -0700 Subject: sfp/phylink: move module EEPROM ethtool access into netdev core ethtool Provide a pointer to the SFP bus in struct net_device, so that the ethtool module EEPROM methods can access the SFP directly, rather than needing every user to provide a hook for it. Reviewed-by: Andrew Lunn Signed-off-by: Russell King Signed-off-by: Florian Fainelli Reviewed-by: Andrew Lunn Signed-off-by: Russell King Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/ethernet/marvell/mvneta.c | 18 ------------------ drivers/net/phy/phylink.c | 28 ---------------------------- drivers/net/phy/sfp-bus.c | 6 ++---- include/linux/netdevice.h | 3 +++ include/linux/phylink.h | 3 --- net/core/ethtool.c | 7 +++++++ 6 files changed, 12 insertions(+), 53 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index cd09bde55596..25ced96750bf 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -4075,22 +4075,6 @@ static int mvneta_ethtool_set_wol(struct net_device *dev, return ret; } -static int mvneta_ethtool_get_module_info(struct net_device *dev, - struct ethtool_modinfo *modinfo) -{ - struct mvneta_port *pp = netdev_priv(dev); - - return phylink_ethtool_get_module_info(pp->phylink, modinfo); -} - -static int mvneta_ethtool_get_module_eeprom(struct net_device *dev, - struct ethtool_eeprom *ee, u8 *buf) -{ - struct mvneta_port *pp = netdev_priv(dev); - - return phylink_ethtool_get_module_eeprom(pp->phylink, ee, buf); -} - static int mvneta_ethtool_get_eee(struct net_device *dev, struct ethtool_eee *eee) { @@ -4165,8 +4149,6 @@ static const struct ethtool_ops mvneta_eth_tool_ops = { .set_link_ksettings = mvneta_ethtool_set_link_ksettings, .get_wol = mvneta_ethtool_get_wol, .set_wol = mvneta_ethtool_set_wol, - .get_module_info = mvneta_ethtool_get_module_info, - .get_module_eeprom = mvneta_ethtool_get_module_eeprom, .get_eee = mvneta_ethtool_get_eee, .set_eee = mvneta_ethtool_set_eee, }; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 9b1e4721ea3a..c582b2d7546c 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1250,34 +1250,6 @@ int phylink_ethtool_set_pauseparam(struct phylink *pl, } EXPORT_SYMBOL_GPL(phylink_ethtool_set_pauseparam); -int phylink_ethtool_get_module_info(struct phylink *pl, - struct ethtool_modinfo *modinfo) -{ - int ret = -EOPNOTSUPP; - - WARN_ON(!lockdep_rtnl_is_held()); - - if (pl->sfp_bus) - ret = sfp_get_module_info(pl->sfp_bus, modinfo); - - return ret; -} -EXPORT_SYMBOL_GPL(phylink_ethtool_get_module_info); - -int phylink_ethtool_get_module_eeprom(struct phylink *pl, - struct ethtool_eeprom *ee, u8 *buf) -{ - int ret = -EOPNOTSUPP; - - WARN_ON(!lockdep_rtnl_is_held()); - - if (pl->sfp_bus) - ret = sfp_get_module_eeprom(pl->sfp_bus, ee, buf); - - return ret; -} -EXPORT_SYMBOL_GPL(phylink_ethtool_get_module_eeprom); - /** * phylink_ethtool_get_eee_err() - read the energy efficient ethernet error * counter diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c index 3d4ff5d0d2a6..0381da78d228 100644 --- a/drivers/net/phy/sfp-bus.c +++ b/drivers/net/phy/sfp-bus.c @@ -342,6 +342,7 @@ static int sfp_register_bus(struct sfp_bus *bus) } if (bus->started) bus->socket_ops->start(bus->sfp); + bus->netdev->sfp_bus = bus; bus->registered = true; return 0; } @@ -356,6 +357,7 @@ static void sfp_unregister_bus(struct sfp_bus *bus) if (bus->phydev && ops && ops->disconnect_phy) ops->disconnect_phy(bus->upstream); } + bus->netdev->sfp_bus = NULL; bus->registered = false; } @@ -371,8 +373,6 @@ static void sfp_unregister_bus(struct sfp_bus *bus) */ int sfp_get_module_info(struct sfp_bus *bus, struct ethtool_modinfo *modinfo) { - if (!bus->registered) - return -ENOIOCTLCMD; return bus->socket_ops->module_info(bus->sfp, modinfo); } EXPORT_SYMBOL_GPL(sfp_get_module_info); @@ -391,8 +391,6 @@ EXPORT_SYMBOL_GPL(sfp_get_module_info); int sfp_get_module_eeprom(struct sfp_bus *bus, struct ethtool_eeprom *ee, u8 *data) { - if (!bus->registered) - return -ENOIOCTLCMD; return bus->socket_ops->module_eeprom(bus->sfp, ee, data); } EXPORT_SYMBOL_GPL(sfp_get_module_eeprom); diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index da44dab492e3..cf44503ea81a 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -58,6 +58,7 @@ struct device; struct phy_device; struct dsa_port; +struct sfp_bus; /* 802.11 specific */ struct wireless_dev; /* 802.15.4 specific */ @@ -1662,6 +1663,7 @@ enum netdev_priv_flags { * @priomap: XXX: need comments on this one * @phydev: Physical device may attach itself * for hardware timestamping + * @sfp_bus: attached &struct sfp_bus structure. * * @qdisc_tx_busylock: lockdep class annotating Qdisc->busylock spinlock * @qdisc_running_key: lockdep class annotating Qdisc->running seqcount @@ -1945,6 +1947,7 @@ struct net_device { struct netprio_map __rcu *priomap; #endif struct phy_device *phydev; + struct sfp_bus *sfp_bus; struct lock_class_key *qdisc_tx_busylock; struct lock_class_key *qdisc_running_key; bool proto_down; diff --git a/include/linux/phylink.h b/include/linux/phylink.h index e95cc12030fa..50eeae025f1e 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -219,9 +219,6 @@ void phylink_ethtool_get_pauseparam(struct phylink *, struct ethtool_pauseparam *); int phylink_ethtool_set_pauseparam(struct phylink *, struct ethtool_pauseparam *); -int phylink_ethtool_get_module_info(struct phylink *, struct ethtool_modinfo *); -int phylink_ethtool_get_module_eeprom(struct phylink *, - struct ethtool_eeprom *, u8 *); int phylink_get_eee_err(struct phylink *); int phylink_ethtool_get_eee(struct phylink *, struct ethtool_eee *); int phylink_ethtool_set_eee(struct phylink *, struct ethtool_eee *); diff --git a/net/core/ethtool.c b/net/core/ethtool.c index bb6e498c6e3d..eb55252ca1fb 100644 --- a/net/core/ethtool.c +++ b/net/core/ethtool.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -2245,6 +2246,9 @@ static int __ethtool_get_module_info(struct net_device *dev, const struct ethtool_ops *ops = dev->ethtool_ops; struct phy_device *phydev = dev->phydev; + if (dev->sfp_bus) + return sfp_get_module_info(dev->sfp_bus, modinfo); + if (phydev && phydev->drv && phydev->drv->module_info) return phydev->drv->module_info(phydev, modinfo); @@ -2279,6 +2283,9 @@ static int __ethtool_get_module_eeprom(struct net_device *dev, const struct ethtool_ops *ops = dev->ethtool_ops; struct phy_device *phydev = dev->phydev; + if (dev->sfp_bus) + return sfp_get_module_eeprom(dev->sfp_bus, ee, data); + if (phydev && phydev->drv && phydev->drv->module_eeprom) return phydev->drv->module_eeprom(phydev, ee, data); -- cgit v1.2.3 From 9217e566bdee4583d0a9ea4879c8f5e004886eac Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 29 Mar 2018 07:29:48 +0200 Subject: of_net: Implement of_get_nvmem_mac_address helper It's common practice to store MAC addresses for network interfaces into nvmem devices. However the code to actually do this in the kernel lacks, so this patch adds of_get_nvmem_mac_address() for drivers to obtain the address from an nvmem cell provider. This is particulary useful on devices where the ethernet interface cannot be configured by the bootloader, for example because it's in an FPGA. Signed-off-by: Mike Looijmans Reviewed-by: Florian Fainelli Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/ethernet.txt | 2 ++ drivers/of/of_net.c | 40 ++++++++++++++++++++++ include/linux/of_net.h | 6 ++++ 3 files changed, 48 insertions(+) (limited to 'include/linux') diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt index 2974e63ba311..cfc376bc977a 100644 --- a/Documentation/devicetree/bindings/net/ethernet.txt +++ b/Documentation/devicetree/bindings/net/ethernet.txt @@ -10,6 +10,8 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. the boot program; should be used in cases where the MAC address assigned to the device by the boot program is different from the "local-mac-address" property; +- nvmem-cells: phandle, reference to an nvmem node for the MAC address; +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used; - max-speed: number, specifies maximum speed in Mbit/s supported by the device; - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than the maximum frame size (there's contradiction in the Devicetree diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c index d820f3edd431..53189d4022a6 100644 --- a/drivers/of/of_net.c +++ b/drivers/of/of_net.c @@ -7,6 +7,7 @@ */ #include #include +#include #include #include #include @@ -80,3 +81,42 @@ const void *of_get_mac_address(struct device_node *np) return of_get_mac_addr(np, "address"); } EXPORT_SYMBOL(of_get_mac_address); + +/** + * Obtain the MAC address from an nvmem provider named 'mac-address' through + * device tree. + * On success, copies the new address into memory pointed to by addr and + * returns 0. Returns a negative error code otherwise. + * @np: Device tree node containing the nvmem-cells phandle + * @addr: Pointer to receive the MAC address using ether_addr_copy() + */ +int of_get_nvmem_mac_address(struct device_node *np, void *addr) +{ + struct nvmem_cell *cell; + const void *mac; + size_t len; + int ret; + + cell = of_nvmem_cell_get(np, "mac-address"); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + mac = nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(mac)) + return PTR_ERR(mac); + + if (len < ETH_ALEN || !is_valid_ether_addr(mac)) { + ret = -EINVAL; + } else { + ether_addr_copy(addr, mac); + ret = 0; + } + + kfree(mac); + + return ret; +} +EXPORT_SYMBOL(of_get_nvmem_mac_address); diff --git a/include/linux/of_net.h b/include/linux/of_net.h index 9cd72aab76fe..90d81ee9e6a0 100644 --- a/include/linux/of_net.h +++ b/include/linux/of_net.h @@ -13,6 +13,7 @@ struct net_device; extern int of_get_phy_mode(struct device_node *np); extern const void *of_get_mac_address(struct device_node *np); +extern int of_get_nvmem_mac_address(struct device_node *np, void *addr); extern struct net_device *of_find_net_device_by_node(struct device_node *np); #else static inline int of_get_phy_mode(struct device_node *np) @@ -25,6 +26,11 @@ static inline const void *of_get_mac_address(struct device_node *np) return NULL; } +static inline int of_get_nvmem_mac_address(struct device_node *np, void *addr) +{ + return -ENODEV; +} + static inline struct net_device *of_find_net_device_by_node(struct device_node *np) { return NULL; -- cgit v1.2.3 From c769accdf3d8a103940bea2979b65556718567e9 Mon Sep 17 00:00:00 2001 From: Toshiaki Makita Date: Thu, 29 Mar 2018 19:05:30 +0900 Subject: vlan: Fix vlan insertion for packets without ethernet header In some situation vlan packets do not have ethernet headers. One example is packets from tun devices. Users can specify vlan protocol in tun_pi field instead of IP protocol. When we have a vlan device with reorder_hdr disabled on top of the tun device, such packets from tun devices are untagged in skb_vlan_untag() and vlan headers will be inserted back in vlan_insert_inner_tag(). vlan_insert_inner_tag() however did not expect packets without ethernet headers, so in such a case size argument for memmove() underflowed. We don't need to copy headers for packets which do not have preceding headers of vlan headers, so skip memmove() in that case. Also don't write vlan protocol in skb->data when it does not have enough room for it. Fixes: cbe7128c4b92 ("vlan: Fix out of order vlan headers with reorder header off") Signed-off-by: Toshiaki Makita Signed-off-by: David S. Miller --- include/linux/if_vlan.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index c4a1cff9c768..7d30892da064 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -323,13 +323,24 @@ static inline int __vlan_insert_inner_tag(struct sk_buff *skb, skb_push(skb, VLAN_HLEN); /* Move the mac header sans proto to the beginning of the new header. */ - memmove(skb->data, skb->data + VLAN_HLEN, mac_len - ETH_TLEN); + if (likely(mac_len > ETH_TLEN)) + memmove(skb->data, skb->data + VLAN_HLEN, mac_len - ETH_TLEN); skb->mac_header -= VLAN_HLEN; veth = (struct vlan_ethhdr *)(skb->data + mac_len - ETH_HLEN); /* first, the ethernet type */ - veth->h_vlan_proto = vlan_proto; + if (likely(mac_len >= ETH_TLEN)) { + /* h_vlan_encapsulated_proto should already be populated, and + * skb->data has space for h_vlan_proto + */ + veth->h_vlan_proto = vlan_proto; + } else { + /* h_vlan_encapsulated_proto should not be populated, and + * skb->data has no space for h_vlan_proto + */ + veth->h_vlan_encapsulated_proto = skb->protocol; + } /* now, the TCI */ veth->h_vlan_TCI = htons(vlan_tci); -- cgit v1.2.3 From f97c3dc3c0e8d23a5c4357d182afeef4c67f5c33 Mon Sep 17 00:00:00 2001 From: Tal Gilboa Date: Thu, 29 Mar 2018 13:53:52 +0300 Subject: net/dim: Fix int overflow When calculating difference between samples, the values are multiplied by 100. Large values may cause int overflow when multiplied (usually on first iteration). Fixed by forcing 100 to be of type unsigned long. Fixes: 4c4dbb4a7363 ("net/mlx5e: Move dynamic interrupt coalescing code to include/linux") Signed-off-by: Tal Gilboa Reviewed-by: Andy Gospodarek Signed-off-by: David S. Miller --- include/linux/net_dim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/net_dim.h b/include/linux/net_dim.h index bebeaad897cc..29ed8fd6379a 100644 --- a/include/linux/net_dim.h +++ b/include/linux/net_dim.h @@ -231,7 +231,7 @@ static inline void net_dim_exit_parking(struct net_dim *dim) } #define IS_SIGNIFICANT_DIFF(val, ref) \ - (((100 * abs((val) - (ref))) / (ref)) > 10) /* more than 10% difference */ + (((100UL * abs((val) - (ref))) / (ref)) > 10) /* more than 10% difference */ static inline int net_dim_stats_compare(struct net_dim_stats *curr, struct net_dim_stats *prev) -- cgit v1.2.3 From 9def051018c08e65c532822749e857eb4b2e12e7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 21 Mar 2018 19:01:40 +0200 Subject: crypto: Deduplicate le32_to_cpu_array() and cpu_to_le32_array() Deduplicate le32_to_cpu_array() and cpu_to_le32_array() by moving them to the generic header. No functional change implied. Signed-off-by: Andy Shevchenko Signed-off-by: Herbert Xu --- crypto/md4.c | 17 ----------------- crypto/md5.c | 17 ----------------- include/linux/byteorder/generic.h | 17 +++++++++++++++++ 3 files changed, 17 insertions(+), 34 deletions(-) (limited to 'include/linux') diff --git a/crypto/md4.c b/crypto/md4.c index 3515af425cc9..810fefb0a007 100644 --- a/crypto/md4.c +++ b/crypto/md4.c @@ -64,23 +64,6 @@ static inline u32 H(u32 x, u32 y, u32 z) #define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (u32)0x5A827999,s)) #define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (u32)0x6ED9EBA1,s)) -/* XXX: this stuff can be optimized */ -static inline void le32_to_cpu_array(u32 *buf, unsigned int words) -{ - while (words--) { - __le32_to_cpus(buf); - buf++; - } -} - -static inline void cpu_to_le32_array(u32 *buf, unsigned int words) -{ - while (words--) { - __cpu_to_le32s(buf); - buf++; - } -} - static void md4_transform(u32 *hash, u32 const *in) { u32 a, b, c, d; diff --git a/crypto/md5.c b/crypto/md5.c index f7ae1a48225b..f776ef43d621 100644 --- a/crypto/md5.c +++ b/crypto/md5.c @@ -32,23 +32,6 @@ const u8 md5_zero_message_hash[MD5_DIGEST_SIZE] = { }; EXPORT_SYMBOL_GPL(md5_zero_message_hash); -/* XXX: this stuff can be optimized */ -static inline void le32_to_cpu_array(u32 *buf, unsigned int words) -{ - while (words--) { - __le32_to_cpus(buf); - buf++; - } -} - -static inline void cpu_to_le32_array(u32 *buf, unsigned int words) -{ - while (words--) { - __cpu_to_le32s(buf); - buf++; - } -} - #define F1(x, y, z) (z ^ (x & (y ^ z))) #define F2(x, y, z) F1(z, x, y) #define F3(x, y, z) (x ^ y ^ z) diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h index 451aaa0786ae..4b13e0a3e15b 100644 --- a/include/linux/byteorder/generic.h +++ b/include/linux/byteorder/generic.h @@ -156,6 +156,23 @@ static inline void le64_add_cpu(__le64 *var, u64 val) *var = cpu_to_le64(le64_to_cpu(*var) + val); } +/* XXX: this stuff can be optimized */ +static inline void le32_to_cpu_array(u32 *buf, unsigned int words) +{ + while (words--) { + __le32_to_cpus(buf); + buf++; + } +} + +static inline void cpu_to_le32_array(u32 *buf, unsigned int words) +{ + while (words--) { + __cpu_to_le32s(buf); + buf++; + } +} + static inline void be16_add_cpu(__be16 *var, u16 val) { *var = cpu_to_be16(be16_to_cpu(*var) + val); -- cgit v1.2.3 From f44c77630d26ca2c2a60b20c47dd9ce07c4361b3 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 7 Mar 2018 15:26:44 -0800 Subject: fs, dax: prepare for dax-specific address_space_operations In preparation for the dax implementation to start associating dax pages to inodes via page->mapping, we need to provide a 'struct address_space_operations' instance for dax. Define some generic VFS aops helpers for dax. These noop implementations are there in the dax case to prevent the VFS from falling back to operations with page-cache assumptions, dax_writeback_mapping_range() may not be referenced in the FS_DAX=n case. Cc: Jeff Moyer Cc: Ross Zwisler Suggested-by: Matthew Wilcox Suggested-by: Jan Kara Suggested-by: Christoph Hellwig Reviewed-by: Christoph Hellwig Reviewed-by: Jan Kara Suggested-by: Dave Chinner Signed-off-by: Dan Williams --- fs/libfs.c | 39 +++++++++++++++++++++++++++++++++++++++ include/linux/dax.h | 12 +++++++++--- include/linux/fs.h | 4 ++++ 3 files changed, 52 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/fs/libfs.c b/fs/libfs.c index 7ff3cb904acd..0fb590d79f30 100644 --- a/fs/libfs.c +++ b/fs/libfs.c @@ -1060,6 +1060,45 @@ int noop_fsync(struct file *file, loff_t start, loff_t end, int datasync) } EXPORT_SYMBOL(noop_fsync); +int noop_set_page_dirty(struct page *page) +{ + /* + * Unlike __set_page_dirty_no_writeback that handles dirty page + * tracking in the page object, dax does all dirty tracking in + * the inode address_space in response to mkwrite faults. In the + * dax case we only need to worry about potentially dirty CPU + * caches, not dirty page cache pages to write back. + * + * This callback is defined to prevent fallback to + * __set_page_dirty_buffers() in set_page_dirty(). + */ + return 0; +} +EXPORT_SYMBOL_GPL(noop_set_page_dirty); + +void noop_invalidatepage(struct page *page, unsigned int offset, + unsigned int length) +{ + /* + * There is no page cache to invalidate in the dax case, however + * we need this callback defined to prevent falling back to + * block_invalidatepage() in do_invalidatepage(). + */ +} +EXPORT_SYMBOL_GPL(noop_invalidatepage); + +ssize_t noop_direct_IO(struct kiocb *iocb, struct iov_iter *iter) +{ + /* + * iomap based filesystems support direct I/O without need for + * this callback. However, it still needs to be set in + * inode->a_ops so that open/fcntl know that direct I/O is + * generally supported. + */ + return -EINVAL; +} +EXPORT_SYMBOL_GPL(noop_direct_IO); + /* Because kfree isn't assignment-compatible with void(void*) ;-/ */ void kfree_link(void *p) { diff --git a/include/linux/dax.h b/include/linux/dax.h index 0185ecdae135..ae27a7efe7ab 100644 --- a/include/linux/dax.h +++ b/include/linux/dax.h @@ -38,6 +38,7 @@ static inline void put_dax(struct dax_device *dax_dev) } #endif +struct writeback_control; int bdev_dax_pgoff(struct block_device *, sector_t, size_t, pgoff_t *pgoff); #if IS_ENABLED(CONFIG_FS_DAX) int __bdev_dax_supported(struct super_block *sb, int blocksize); @@ -57,6 +58,8 @@ static inline void fs_put_dax(struct dax_device *dax_dev) } struct dax_device *fs_dax_get_by_bdev(struct block_device *bdev); +int dax_writeback_mapping_range(struct address_space *mapping, + struct block_device *bdev, struct writeback_control *wbc); #else static inline int bdev_dax_supported(struct super_block *sb, int blocksize) { @@ -76,6 +79,12 @@ static inline struct dax_device *fs_dax_get_by_bdev(struct block_device *bdev) { return NULL; } + +static inline int dax_writeback_mapping_range(struct address_space *mapping, + struct block_device *bdev, struct writeback_control *wbc) +{ + return -EOPNOTSUPP; +} #endif int dax_read_lock(void); @@ -121,7 +130,4 @@ static inline bool dax_mapping(struct address_space *mapping) return mapping->host && IS_DAX(mapping->host); } -struct writeback_control; -int dax_writeback_mapping_range(struct address_space *mapping, - struct block_device *bdev, struct writeback_control *wbc); #endif diff --git a/include/linux/fs.h b/include/linux/fs.h index 79c413985305..44f7f7080faa 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -3129,6 +3129,10 @@ extern int simple_rmdir(struct inode *, struct dentry *); extern int simple_rename(struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); extern int noop_fsync(struct file *, loff_t, loff_t, int); +extern int noop_set_page_dirty(struct page *page); +extern void noop_invalidatepage(struct page *page, unsigned int offset, + unsigned int length); +extern ssize_t noop_direct_IO(struct kiocb *iocb, struct iov_iter *iter); extern int simple_empty(struct dentry *); extern int simple_readpage(struct file *file, struct page *page); extern int simple_write_begin(struct file *file, struct address_space *mapping, -- cgit v1.2.3 From f385178679b6561d2e717567d12e07c7f927ee59 Mon Sep 17 00:00:00 2001 From: Prashant Bhole Date: Fri, 30 Mar 2018 09:20:59 +0900 Subject: lib/scatterlist: add sg_init_marker() helper sg_init_marker initializes sg_magic in the sg table and calls sg_mark_end() on the last entry of the table. This can be useful to avoid memset in sg_init_table() when scatterlist is already zeroed out For example: when scatterlist is embedded inside other struct and that container struct is zeroed out Suggested-by: Daniel Borkmann Signed-off-by: Prashant Bhole Acked-by: John Fastabend Signed-off-by: Daniel Borkmann --- include/linux/scatterlist.h | 18 ++++++++++++++++++ lib/scatterlist.c | 9 +-------- 2 files changed, 19 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h index 22b2131bcdcd..aa5d4eb725f5 100644 --- a/include/linux/scatterlist.h +++ b/include/linux/scatterlist.h @@ -248,6 +248,24 @@ static inline void *sg_virt(struct scatterlist *sg) return page_address(sg_page(sg)) + sg->offset; } +/** + * sg_init_marker - Initialize markers in sg table + * @sgl: The SG table + * @nents: Number of entries in table + * + **/ +static inline void sg_init_marker(struct scatterlist *sgl, + unsigned int nents) +{ +#ifdef CONFIG_DEBUG_SG + unsigned int i; + + for (i = 0; i < nents; i++) + sgl[i].sg_magic = SG_MAGIC; +#endif + sg_mark_end(&sgl[nents - 1]); +} + int sg_nents(struct scatterlist *sg); int sg_nents_for_len(struct scatterlist *sg, u64 len); struct scatterlist *sg_next(struct scatterlist *); diff --git a/lib/scatterlist.c b/lib/scatterlist.c index 53728d391d3a..06dad7a072fd 100644 --- a/lib/scatterlist.c +++ b/lib/scatterlist.c @@ -132,14 +132,7 @@ EXPORT_SYMBOL(sg_last); void sg_init_table(struct scatterlist *sgl, unsigned int nents) { memset(sgl, 0, sizeof(*sgl) * nents); -#ifdef CONFIG_DEBUG_SG - { - unsigned int i; - for (i = 0; i < nents; i++) - sgl[i].sg_magic = SG_MAGIC; - } -#endif - sg_mark_end(&sgl[nents - 1]); + sg_init_marker(sgl, nents); } EXPORT_SYMBOL(sg_init_table); -- cgit v1.2.3 From 02bfeb484230dfd073148a17253aeb1717ce769c Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 9 Mar 2018 11:21:25 -0600 Subject: PCI/portdrv: Simplify PCIe feature permission checking Some PCIe features (AER, DPC, hotplug, PME) can be managed by either the platform firmware or the OS, so the host bridge driver may have to request permission from the platform before using them. On ACPI systems, this is done by negotiate_os_control() in acpi_pci_root_add(). The PCIe port driver later uses pcie_port_platform_notify() and pcie_port_acpi_setup() to figure out whether it can use these features. But all we need is a single bit for each service, so these interfaces are needlessly complicated. Simplify this by adding bits in the struct pci_host_bridge to show when the OS has permission to use each feature: + unsigned int native_aer:1; /* OS may use PCIe AER */ + unsigned int native_hotplug:1; /* OS may use PCIe hotplug */ + unsigned int native_pme:1; /* OS may use PCIe PME */ These are set when we create a host bridge, and the host bridge driver can clear the bits corresponding to any feature the platform doesn't want us to use. Signed-off-by: Bjorn Helgaas Reviewed-by: Rafael J. Wysocki --- drivers/acpi/pci_root.c | 13 +++++++++++-- drivers/pci/pcie/Makefile | 1 - drivers/pci/pcie/portdrv.h | 11 ----------- drivers/pci/pcie/portdrv_core.c | 42 +++++++++++++++++++++++++---------------- drivers/pci/probe.c | 10 ++++++++++ include/linux/pci.h | 3 +++ 6 files changed, 50 insertions(+), 30 deletions(-) (limited to 'include/linux') diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 6fc204a52493..63b2cb775324 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -871,6 +871,7 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, struct acpi_device *device = root->device; int node = acpi_get_node(device->handle); struct pci_bus *bus; + struct pci_host_bridge *host_bridge; info->root = root; info->bridge = device; @@ -895,9 +896,17 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, if (!bus) goto out_release_info; + host_bridge = to_pci_host_bridge(bus->bridge); + if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)) + host_bridge->native_hotplug = 0; + if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL)) + host_bridge->native_aer = 0; + if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL)) + host_bridge->native_pme = 0; + pci_scan_child_bus(bus); - pci_set_host_bridge_release(to_pci_host_bridge(bus->bridge), - acpi_pci_root_release_info, info); + pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info, + info); if (node != NUMA_NO_NODE) dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); return bus; diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index e01c10c97b95..11fb633b866c 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_PCIEASPM) += aspm.o pcieportdrv-y := portdrv_core.o portdrv_pci.o -pcieportdrv-$(CONFIG_ACPI) += portdrv_acpi.o obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 7bfd75f9197b..ed84e767085f 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -123,15 +123,4 @@ static inline bool pcie_pme_no_msi(void) { return false; } static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {} #endif /* !CONFIG_PCIE_PME */ -#ifdef CONFIG_ACPI -void pcie_port_acpi_setup(struct pci_dev *port, int *mask); - -static inline void pcie_port_platform_notify(struct pci_dev *port, int *mask) -{ - pcie_port_acpi_setup(port, mask); -} -#else /* !CONFIG_ACPI */ -static inline void pcie_port_platform_notify(struct pci_dev *port, int *mask){} -#endif /* !CONFIG_ACPI */ - #endif /* _PORTDRV_H_ */ diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index bf851da97947..5c25761cd05e 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -206,19 +206,20 @@ legacy_irq: */ static int get_port_device_capability(struct pci_dev *dev) { + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); + bool native; int services = 0; - int cap_mask = 0; - cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP; - if (pci_aer_available()) - cap_mask |= PCIE_PORT_SERVICE_AER | PCIE_PORT_SERVICE_DPC; - - if (pcie_ports_auto) - pcie_port_platform_notify(dev, &cap_mask); + /* + * If the user specified "pcie_ports=native", use the PCIe services + * regardless of whether the platform has given us permission. On + * ACPI systems, this means we ignore _OSC. + */ + native = !pcie_ports_auto; - /* Hot-Plug Capable */ - if ((cap_mask & PCIE_PORT_SERVICE_HP) && dev->is_hotplug_bridge) { + if (dev->is_hotplug_bridge && (native || host->native_hotplug)) { services |= PCIE_PORT_SERVICE_HP; + /* * Disable hot-plug interrupts in case they have been enabled * by the BIOS and the hot-plug service driver is not loaded. @@ -226,20 +227,27 @@ static int get_port_device_capability(struct pci_dev *dev) pcie_capability_clear_word(dev, PCI_EXP_SLTCTL, PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE); } - /* AER capable */ - if ((cap_mask & PCIE_PORT_SERVICE_AER) - && pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) { + + if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR) && + pci_aer_available() && (native || host->native_aer)) { services |= PCIE_PORT_SERVICE_AER; + /* * Disable AER on this port in case it's been enabled by the * BIOS (the AER service driver will enable it when necessary). */ pci_disable_pcie_error_reporting(dev); } - /* Root ports are capable of generating PME too */ - if ((cap_mask & PCIE_PORT_SERVICE_PME) - && pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { + + /* + * Root ports are capable of generating PME too. Root Complex + * Event Collectors can also generate PMEs, but we don't handle + * those yet. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && + (native || host->native_pme)) { services |= PCIE_PORT_SERVICE_PME; + /* * Disable PME interrupt on this port in case it's been enabled * by the BIOS (the PME service driver will enable it when @@ -247,7 +255,9 @@ static int get_port_device_capability(struct pci_dev *dev) */ pcie_pme_interrupt_enable(dev, false); } - if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC)) + + if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) && + pci_aer_available()) services |= PCIE_PORT_SERVICE_DPC; return services; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index ef5377438a1e..a00de697a970 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -540,6 +540,16 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) INIT_LIST_HEAD(&bridge->windows); bridge->dev.release = pci_release_host_bridge_dev; + /* + * We assume we can manage these PCIe features. Some systems may + * reserve these for use by the platform itself, e.g., an ACPI BIOS + * may implement its own AER handling and use _OSC to prevent the + * OS from interfering. + */ + bridge->native_aer = 1; + bridge->native_hotplug = 1; + bridge->native_pme = 1; + return bridge; } EXPORT_SYMBOL(pci_alloc_host_bridge); diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1beda008..a04b7abc6b7a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -469,6 +469,9 @@ struct pci_host_bridge { struct msi_controller *msi; unsigned int ignore_reset_delay:1; /* For entire hierarchy */ unsigned int no_ext_tags:1; /* No Extended Tags */ + unsigned int native_aer:1; /* OS may use PCIe AER */ + unsigned int native_hotplug:1; /* OS may use PCIe hotplug */ + unsigned int native_pme:1; /* OS may use PCIe PME */ /* Resource alignment requirements */ resource_size_t (*align_resource)(struct pci_dev *dev, const struct resource *res, -- cgit v1.2.3 From 842b447f0074b93e9f7db60039fdc72ec14bef9a Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 9 Mar 2018 11:21:29 -0600 Subject: PCI/portdrv: Encapsulate pcie_ports_auto inside the port driver "pcie_ports_auto" is only used inside the PCIe port driver itself, so move it from include/linux/pci.h to portdrv.h so it's not visible to the whole kernel. Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/portdrv.h | 2 ++ include/linux/pci.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 86368f9341d7..62e28b5afa51 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -12,6 +12,8 @@ #include +extern bool pcie_ports_auto; + /* Service Type */ #define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */ #define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT) diff --git a/include/linux/pci.h b/include/linux/pci.h index a04b7abc6b7a..dc70a3ce8dc5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1449,10 +1449,8 @@ static inline int pci_irqd_intx_xlate(struct irq_domain *d, #ifdef CONFIG_PCIEPORTBUS extern bool pcie_ports_disabled; -extern bool pcie_ports_auto; #else #define pcie_ports_disabled true -#define pcie_ports_auto false #endif #ifdef CONFIG_PCIEASPM -- cgit v1.2.3 From ad32eb2df801548a4b55802384fbbfbc04d76bfa Mon Sep 17 00:00:00 2001 From: Bjørn Mork Date: Sun, 18 Mar 2018 13:58:06 +0100 Subject: PCI: Always define the of_node helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simply move these inline functions outside the ifdef instead of duplicating them as stubs in the !OF case. The struct device of_node field does not depend on OF. This also fixes the missing stubbed pci_bus_to_OF_node(). Signed-off-by: Bjørn Mork Signed-off-by: Bjorn Helgaas --- include/linux/pci.h | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'include/linux') diff --git a/include/linux/pci.h b/include/linux/pci.h index 024a1beda008..d0396da9160e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2182,24 +2182,11 @@ int pci_parse_request_of_pci_ranges(struct device *dev, /* Arch may override this (weak) */ struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); -static inline struct device_node * -pci_device_to_OF_node(const struct pci_dev *pdev) -{ - return pdev ? pdev->dev.of_node : NULL; -} - -static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) -{ - return bus ? bus->dev.of_node : NULL; -} - #else /* CONFIG_OF */ static inline void pci_set_of_node(struct pci_dev *dev) { } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { } static inline void pci_release_bus_of_node(struct pci_bus *bus) { } -static inline struct device_node * -pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } static inline struct irq_domain * pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } static inline int pci_parse_request_of_pci_ranges(struct device *dev, @@ -2210,6 +2197,17 @@ static inline int pci_parse_request_of_pci_ranges(struct device *dev, } #endif /* CONFIG_OF */ +static inline struct device_node * +pci_device_to_OF_node(const struct pci_dev *pdev) +{ + return pdev ? pdev->dev.of_node : NULL; +} + +static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) +{ + return bus ? bus->dev.of_node : NULL; +} + #ifdef CONFIG_ACPI struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); -- cgit v1.2.3 From b2d3907c234618c20239127f2c234b4e92adf5ef Mon Sep 17 00:00:00 2001 From: Saeed Mahameed Date: Tue, 13 Feb 2018 17:07:02 -0800 Subject: net/mlx5: Eliminate query xsrq dead code 1. This function is not used anywhere in mlx5 driver 2. It has a memcpy statement that makes no sense and produces build warning with gcc8 drivers/net/ethernet/mellanox/mlx5/core/transobj.c: In function 'mlx5_core_query_xsrq': drivers/net/ethernet/mellanox/mlx5/core/transobj.c:347:3: error: 'memcpy' source argument is the same as destination [-Werror=restrict] Fixes: 01949d0109ee ("net/mlx5_core: Enable XRCs and SRQs when using ISSI > 0") Reported-by: Arnd Bergmann Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/transobj.c | 21 --------------------- include/linux/mlx5/transobj.h | 1 - 2 files changed, 22 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/transobj.c b/drivers/net/ethernet/mellanox/mlx5/core/transobj.c index c64957b5ef47..dae1c5c5d27c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/transobj.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/transobj.c @@ -354,27 +354,6 @@ int mlx5_core_destroy_xsrq(struct mlx5_core_dev *dev, u32 xsrqn) return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } -int mlx5_core_query_xsrq(struct mlx5_core_dev *dev, u32 xsrqn, u32 *out) -{ - u32 in[MLX5_ST_SZ_DW(query_xrc_srq_in)] = {0}; - void *srqc; - void *xrc_srqc; - int err; - - MLX5_SET(query_xrc_srq_in, in, opcode, MLX5_CMD_OP_QUERY_XRC_SRQ); - MLX5_SET(query_xrc_srq_in, in, xrc_srqn, xsrqn); - err = mlx5_cmd_exec(dev, in, sizeof(in), out, - MLX5_ST_SZ_BYTES(query_xrc_srq_out)); - if (!err) { - xrc_srqc = MLX5_ADDR_OF(query_xrc_srq_out, out, - xrc_srq_context_entry); - srqc = MLX5_ADDR_OF(query_srq_out, out, srq_context_entry); - memcpy(srqc, xrc_srqc, MLX5_ST_SZ_BYTES(srqc)); - } - - return err; -} - int mlx5_core_arm_xsrq(struct mlx5_core_dev *dev, u32 xsrqn, u16 lwm) { u32 in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0}; diff --git a/include/linux/mlx5/transobj.h b/include/linux/mlx5/transobj.h index 80d7aa8b2831..83a33a1873a6 100644 --- a/include/linux/mlx5/transobj.h +++ b/include/linux/mlx5/transobj.h @@ -67,7 +67,6 @@ int mlx5_core_arm_rmp(struct mlx5_core_dev *dev, u32 rmpn, u16 lwm); int mlx5_core_create_xsrq(struct mlx5_core_dev *dev, u32 *in, int inlen, u32 *rmpn); int mlx5_core_destroy_xsrq(struct mlx5_core_dev *dev, u32 rmpn); -int mlx5_core_query_xsrq(struct mlx5_core_dev *dev, u32 rmpn, u32 *out); int mlx5_core_arm_xsrq(struct mlx5_core_dev *dev, u32 rmpn, u16 lwm); int mlx5_core_create_rqt(struct mlx5_core_dev *dev, u32 *in, int inlen, -- cgit v1.2.3 From 619a8f2a42f1031cdbd74435b6a9191eb4913139 Mon Sep 17 00:00:00 2001 From: Tariq Toukan Date: Wed, 7 Feb 2018 14:41:25 +0200 Subject: net/mlx5e: Use linear SKB in Striding RQ Current Striding RQ HW feature utilizes the RX buffers so that there is no wasted room between the strides. This maximises the memory utilization. This prevents the use of build_skb() (which requires headroom and tailroom), and demands to memcpy the packets headers into the skb linear part. In this patch, whenever a set of conditions holds, we apply an RQ configuration that allows combining the use of linear SKB on top of a Striding RQ. To use build_skb() with Striding RQ, the following must hold: 1. packet does not cross a page boundary. 2. there is enough headroom and tailroom surrounding the packet. We can satisfy 1 and 2 by configuring: stride size = MTU + headroom + tailoom. This is possible only when: a. (MTU - headroom - tailoom) does not exceed PAGE_SIZE. b. HW LRO is turned off. Using linear SKB has many advantages: - Saves a memcpy of the headers. - No page-boundary checks in datapath. - No filler CQEs. - Significantly smaller CQ. - SKB data continuously resides in linear part, and not split to small amount (linear part) and large amount (fragment). This saves datapath cycles in driver and improves utilization of SKB fragments in GRO. - The fragments of a resulting GRO SKB follow the IP forwarding assumption of equal-size fragments. Some implementation details: HW writes the packets to the beginning of a stride, i.e. does not keep headroom. To overcome this we make sure we can extend backwards and use the last bytes of stride i-1. Extra care is needed for stride 0 as it has no preceding stride. We make sure headroom bytes are available by shifting the buffer pointer passed to HW by headroom bytes. This configuration now becomes default, whenever capable. Of course, this implies turning LRO off. Performance testing: ConnectX-5, single core, single RX ring, default MTU. UDP packet rate, early drop in TC layer: -------------------------------------------- | pkt size | before | after | ratio | -------------------------------------------- | 1500byte | 4.65 Mpps | 5.96 Mpps | 1.28x | | 500byte | 5.23 Mpps | 5.97 Mpps | 1.14x | | 64byte | 5.94 Mpps | 5.96 Mpps | 1.00x | -------------------------------------------- TCP streams: ~20% gain Signed-off-by: Tariq Toukan Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 10 +++ drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 76 +++++++++++++--- drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 102 ++++++++++++++++------ include/linux/mlx5/device.h | 3 + include/linux/mlx5/mlx5_ifc.h | 7 +- 5 files changed, 153 insertions(+), 45 deletions(-) (limited to 'include/linux') diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index c1d3a29388bd..d26dd4bc89f4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -473,6 +473,9 @@ struct mlx5e_page_cache { struct mlx5e_rq; typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); +typedef struct sk_buff * +(*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, + u16 cqe_bcnt, u32 head_offset, u32 page_idx); typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); @@ -491,6 +494,7 @@ struct mlx5e_rq { } wqe; struct { struct mlx5e_mpw_info *info; + mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; u16 num_strides; u8 log_stride_sz; bool umr_in_progress; @@ -834,6 +838,12 @@ bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); +struct sk_buff * +mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, + u16 cqe_bcnt, u32 head_offset, u32 page_idx); +struct sk_buff * +mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, + u16 cqe_bcnt, u32 head_offset, u32 page_idx); void mlx5e_update_stats(struct mlx5e_priv *priv); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 42dc350c5ab1..bba2fa0aa15f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -91,9 +91,14 @@ bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params) { - u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); + if (!params->xdp_prog) { + u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); + u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN; - return hw_mtu; + return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu); + } + + return PAGE_SIZE; } static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params) @@ -103,6 +108,26 @@ static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params) return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz); } +static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, + struct mlx5e_params *params) +{ + u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params); + s8 signed_log_num_strides_param; + u8 log_num_strides; + + if (params->lro_en || frag_sz > PAGE_SIZE) + return false; + + if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) + return true; + + log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz); + signed_log_num_strides_param = + (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE; + + return signed_log_num_strides_param >= 0; +} + static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params) { if (params->log_rq_mtu_frames < @@ -115,6 +140,9 @@ static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params) static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params) { + if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) + return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params)); + return MLX5E_MPWQE_STRIDE_SZ(mdev, MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); } @@ -126,7 +154,8 @@ static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, mlx5e_mpwqe_get_log_stride_size(mdev, params); } -static u16 mlx5e_get_rq_headroom(struct mlx5e_params *params) +static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, + struct mlx5e_params *params) { u16 linear_rq_headroom = params->xdp_prog ? XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM; @@ -136,6 +165,9 @@ static u16 mlx5e_get_rq_headroom(struct mlx5e_params *params) if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST) return linear_rq_headroom; + if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) + return linear_rq_headroom; + return 0; } @@ -151,12 +183,14 @@ void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, break; default: /* MLX5_WQ_TYPE_LINKED_LIST */ /* Extra room needed for build_skb */ - params->lro_wqe_sz -= mlx5e_get_rq_headroom(params) + + params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); } mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, + params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? + BIT(mlx5e_mpwqe_get_log_rq_size(params)) : BIT(params->log_rq_mtu_frames), BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)), MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); @@ -400,11 +434,10 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, goto err_rq_wq_destroy; rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; - rq->buff.headroom = mlx5e_get_rq_headroom(params); + rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params); switch (rq->wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: - rq->post_wqes = mlx5e_post_rx_mpwqes; rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; @@ -422,6 +455,10 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, goto err_rq_wq_destroy; } + rq->mpwqe.skb_from_cqe_mpwrq = + mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ? + mlx5e_skb_from_cqe_mpwrq_linear : + mlx5e_skb_from_cqe_mpwrq_nonlinear; rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params); rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params)); @@ -484,7 +521,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT; - wqe->data.addr = cpu_to_be64(dma_offset); + wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom); } wqe->data.byte_count = cpu_to_be32(byte_count); @@ -1834,9 +1871,11 @@ static void mlx5e_build_rq_param(struct mlx5e_priv *priv, switch (params->rq_wq_type) { case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: MLX5_SET(wq, wq, log_wqe_num_of_strides, - mlx5e_mpwqe_get_log_num_strides(mdev, params) - 9); + mlx5e_mpwqe_get_log_num_strides(mdev, params) - + MLX5_MPWQE_LOG_NUM_STRIDES_BASE); MLX5_SET(wq, wq, log_wqe_stride_size, - mlx5e_mpwqe_get_log_stride_size(mdev, params) - 6); + mlx5e_mpwqe_get_log_stride_size(mdev, params) - + MLX5_MPWQE_LOG_STRIDE_SZ_BASE); MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params)); break; @@ -3193,20 +3232,28 @@ typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); static int set_feature_lro(struct net_device *netdev, bool enable) { struct mlx5e_priv *priv = netdev_priv(netdev); + struct mlx5_core_dev *mdev = priv->mdev; struct mlx5e_channels new_channels = {}; + struct mlx5e_params *old_params; int err = 0; bool reset; mutex_lock(&priv->state_lock); - reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST); - reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state); + old_params = &priv->channels.params; + reset = test_bit(MLX5E_STATE_OPENED, &priv->state); - new_channels.params = priv->channels.params; + new_channels.params = *old_params; new_channels.params.lro_en = enable; + if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) { + if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) == + mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params)) + reset = false; + } + if (!reset) { - priv->channels.params = new_channels.params; + *old_params = new_channels.params; err = mlx5e_modify_tirs_lro(priv); goto out; } @@ -4121,7 +4168,8 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */ if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) - params->lro_en = !slow_pci_heuristic(mdev); + if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) + params->lro_en = !slow_pci_heuristic(mdev); params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); /* CQ moderation params */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 539dbe9382ee..07db8a58d0a2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -836,6 +836,24 @@ static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, } } +static inline +struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va, + u32 frag_size, u16 headroom, + u32 cqe_bcnt) +{ + struct sk_buff *skb = build_skb(va, frag_size); + + if (unlikely(!skb)) { + rq->stats.buff_alloc_err++; + return NULL; + } + + skb_reserve(skb, headroom); + skb_put(skb, cqe_bcnt); + + return skb; +} + static inline struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) @@ -867,18 +885,13 @@ struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, if (consumed) return NULL; /* page/packet was consumed by XDP */ - skb = build_skb(va, frag_size); - if (unlikely(!skb)) { - rq->stats.buff_alloc_err++; + skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt); + if (unlikely(!skb)) return NULL; - } /* queue up for recycling/reuse */ page_ref_inc(di->page); - skb_reserve(skb, rx_headroom); - skb_put(skb, cqe_bcnt); - return skb; } @@ -967,20 +980,24 @@ wq_ll_pop: } #endif -static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, - struct mlx5_cqe64 *cqe, - struct mlx5e_mpw_info *wi, - u32 cqe_bcnt, - struct sk_buff *skb) +struct sk_buff * +mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, + u16 cqe_bcnt, u32 head_offset, u32 page_idx) { - u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); - u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; - u32 head_offset = wqe_offset & (PAGE_SIZE - 1); - u32 page_idx = wqe_offset >> PAGE_SHIFT; - u32 head_page_idx = page_idx; u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); u32 frag_offset = head_offset + headlen; u16 byte_cnt = cqe_bcnt - headlen; + u32 head_page_idx = page_idx; + struct sk_buff *skb; + + skb = napi_alloc_skb(rq->cq.napi, + ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long))); + if (unlikely(!skb)) { + rq->stats.buff_alloc_err++; + return NULL; + } + + prefetchw(skb->data); if (unlikely(frag_offset >= PAGE_SIZE)) { page_idx++; @@ -1003,6 +1020,35 @@ static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, /* skb linear part was allocated with headlen and aligned to long */ skb->tail += headlen; skb->len += headlen; + + return skb; +} + +struct sk_buff * +mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, + u16 cqe_bcnt, u32 head_offset, u32 page_idx) +{ + struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; + u16 rx_headroom = rq->buff.headroom; + struct sk_buff *skb; + void *va, *data; + u32 frag_size; + + va = page_address(di->page) + head_offset; + data = va + rx_headroom; + frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); + + dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset, + frag_size, DMA_FROM_DEVICE); + prefetch(data); + skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt); + if (unlikely(!skb)) + return NULL; + + /* queue up for recycling/reuse */ + wi->skbs_frags[page_idx]++; + + return skb; } void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) @@ -1010,7 +1056,11 @@ void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); u16 wqe_id = be16_to_cpu(cqe->wqe_id); struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; - struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); + u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); + u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; + u32 head_offset = wqe_offset & (PAGE_SIZE - 1); + u32 page_idx = wqe_offset >> PAGE_SHIFT; + struct mlx5e_rx_wqe *wqe; struct sk_buff *skb; u16 cqe_bcnt; @@ -1026,18 +1076,13 @@ void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) goto mpwrq_cqe_out; } - skb = napi_alloc_skb(rq->cq.napi, - ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, - sizeof(long))); - if (unlikely(!skb)) { - rq->stats.buff_alloc_err++; - goto mpwrq_cqe_out; - } - - prefetchw(skb->data); cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); - mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); + skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset, + page_idx); + if (unlikely(!skb)) + goto mpwrq_cqe_out; + mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); napi_gro_receive(rq->cq.napi, skb); @@ -1045,6 +1090,7 @@ mpwrq_cqe_out: if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) return; + wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); mlx5e_free_rx_mpwqe(rq, wi); mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); } diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 4b5939c78cdd..12758595459b 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -782,6 +782,9 @@ static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) return (u64)lo | ((u64)hi << 32); } +#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9) +#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6) + struct mpwrq_cqe_bc { __be16 filler_consumed_strides; __be16 byte_cnt; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index c19e611d2782..d25011f84815 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1038,7 +1038,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_398[0x3]; u8 log_max_tis_per_sq[0x5]; - u8 reserved_at_3a0[0x3]; + u8 ext_stride_num_range[0x1]; + u8 reserved_at_3a1[0x2]; u8 log_max_stride_sz_rq[0x5]; u8 reserved_at_3a8[0x3]; u8 log_min_stride_sz_rq[0x5]; @@ -1205,9 +1206,9 @@ struct mlx5_ifc_wq_bits { u8 log_hairpin_num_packets[0x5]; u8 reserved_at_128[0x3]; u8 log_hairpin_data_sz[0x5]; - u8 reserved_at_130[0x5]; - u8 log_wqe_num_of_strides[0x3]; + u8 reserved_at_130[0x4]; + u8 log_wqe_num_of_strides[0x4]; u8 two_byte_shift_en[0x1]; u8 reserved_at_139[0x4]; u8 log_wqe_stride_size[0x3]; -- cgit v1.2.3 From 5e43f899b03a3492ce5fc44e8900becb04dae9c0 Mon Sep 17 00:00:00 2001 From: Andrey Ignatov Date: Fri, 30 Mar 2018 15:08:00 -0700 Subject: bpf: Check attach type at prog load time == The problem == There are use-cases when a program of some type can be attached to multiple attach points and those attach points must have different permissions to access context or to call helpers. E.g. context structure may have fields for both IPv4 and IPv6 but it doesn't make sense to read from / write to IPv6 field when attach point is somewhere in IPv4 stack. Same applies to BPF-helpers: it may make sense to call some helper from some attach point, but not from other for same prog type. == The solution == Introduce `expected_attach_type` field in in `struct bpf_attr` for `BPF_PROG_LOAD` command. If scenario described in "The problem" section is the case for some prog type, the field will be checked twice: 1) At load time prog type is checked to see if attach type for it must be known to validate program permissions correctly. Prog will be rejected with EINVAL if it's the case and `expected_attach_type` is not specified or has invalid value. 2) At attach time `attach_type` is compared with `expected_attach_type`, if prog type requires to have one, and, if they differ, attach will be rejected with EINVAL. The `expected_attach_type` is now available as part of `struct bpf_prog` in both `bpf_verifier_ops->is_valid_access()` and `bpf_verifier_ops->get_func_proto()` () and can be used to check context accesses and calls to helpers correspondingly. Initially the idea was discussed by Alexei Starovoitov and Daniel Borkmann here: https://marc.info/?l=linux-netdev&m=152107378717201&w=2 Signed-off-by: Andrey Ignatov Signed-off-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/bpf.h | 5 ++++- include/linux/filter.h | 1 + include/uapi/linux/bpf.h | 5 +++++ kernel/bpf/cgroup.c | 3 ++- kernel/bpf/syscall.c | 31 ++++++++++++++++++++++++++++++- kernel/bpf/verifier.c | 6 +++--- kernel/trace/bpf_trace.c | 27 ++++++++++++++++++--------- net/core/filter.c | 39 +++++++++++++++++++++++++-------------- 8 files changed, 88 insertions(+), 29 deletions(-) (limited to 'include/linux') diff --git a/include/linux/bpf.h b/include/linux/bpf.h index 819229c80eca..95a7abd0ee92 100644 --- a/include/linux/bpf.h +++ b/include/linux/bpf.h @@ -208,12 +208,15 @@ struct bpf_prog_ops { struct bpf_verifier_ops { /* return eBPF function prototype for verification */ - const struct bpf_func_proto *(*get_func_proto)(enum bpf_func_id func_id); + const struct bpf_func_proto * + (*get_func_proto)(enum bpf_func_id func_id, + const struct bpf_prog *prog); /* return true if 'size' wide access at offset 'off' within bpf_context * with 'type' (read or write) is allowed */ bool (*is_valid_access)(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info); int (*gen_prologue)(struct bpf_insn *insn, bool direct_write, const struct bpf_prog *prog); diff --git a/include/linux/filter.h b/include/linux/filter.h index 897ff3d95968..13c044e4832d 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -469,6 +469,7 @@ struct bpf_prog { is_func:1, /* program is a bpf function */ kprobe_override:1; /* Do we override a kprobe? */ enum bpf_prog_type type; /* Type of BPF program */ + enum bpf_attach_type expected_attach_type; /* For some prog types */ u32 len; /* Number of filter blocks */ u32 jited_len; /* Size of jited insns in bytes */ u8 tag[BPF_TAG_SIZE]; diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 1878201c2d77..102718624d1e 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -296,6 +296,11 @@ union bpf_attr { __u32 prog_flags; char prog_name[BPF_OBJ_NAME_LEN]; __u32 prog_ifindex; /* ifindex of netdev to prep for */ + /* For some prog types expected attach type must be known at + * load time to verify attach type specific parts of prog + * (context accesses, allowed helpers, etc). + */ + __u32 expected_attach_type; }; struct { /* anonymous struct used by BPF_OBJ_* commands */ diff --git a/kernel/bpf/cgroup.c b/kernel/bpf/cgroup.c index c1c0b60d3f2f..8730b24ed540 100644 --- a/kernel/bpf/cgroup.c +++ b/kernel/bpf/cgroup.c @@ -545,7 +545,7 @@ int __cgroup_bpf_check_dev_permission(short dev_type, u32 major, u32 minor, EXPORT_SYMBOL(__cgroup_bpf_check_dev_permission); static const struct bpf_func_proto * -cgroup_dev_func_proto(enum bpf_func_id func_id) +cgroup_dev_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_map_lookup_elem: @@ -566,6 +566,7 @@ cgroup_dev_func_proto(enum bpf_func_id func_id) static bool cgroup_dev_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { const int size_default = sizeof(__u32); diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c index 95ca2523fa6e..9d3b572d4dec 100644 --- a/kernel/bpf/syscall.c +++ b/kernel/bpf/syscall.c @@ -1171,8 +1171,27 @@ struct bpf_prog *bpf_prog_get_type_dev(u32 ufd, enum bpf_prog_type type, } EXPORT_SYMBOL_GPL(bpf_prog_get_type_dev); +static int +bpf_prog_load_check_attach_type(enum bpf_prog_type prog_type, + enum bpf_attach_type expected_attach_type) +{ + /* There are currently no prog types that require specifying + * attach_type at load time. + */ + return 0; +} + +static int bpf_prog_attach_check_attach_type(const struct bpf_prog *prog, + enum bpf_attach_type attach_type) +{ + /* There are currently no prog types that require specifying + * attach_type at load time. + */ + return 0; +} + /* last field in 'union bpf_attr' used by this command */ -#define BPF_PROG_LOAD_LAST_FIELD prog_ifindex +#define BPF_PROG_LOAD_LAST_FIELD expected_attach_type static int bpf_prog_load(union bpf_attr *attr) { @@ -1209,11 +1228,16 @@ static int bpf_prog_load(union bpf_attr *attr) !capable(CAP_SYS_ADMIN)) return -EPERM; + if (bpf_prog_load_check_attach_type(type, attr->expected_attach_type)) + return -EINVAL; + /* plain bpf_prog allocation */ prog = bpf_prog_alloc(bpf_prog_size(attr->insn_cnt), GFP_USER); if (!prog) return -ENOMEM; + prog->expected_attach_type = attr->expected_attach_type; + prog->aux->offload_requested = !!attr->prog_ifindex; err = security_bpf_prog_alloc(prog->aux); @@ -1474,6 +1498,11 @@ static int bpf_prog_attach(const union bpf_attr *attr) if (IS_ERR(prog)) return PTR_ERR(prog); + if (bpf_prog_attach_check_attach_type(prog, attr->attach_type)) { + bpf_prog_put(prog); + return -EINVAL; + } + cgrp = cgroup_get_from_fd(attr->target_fd); if (IS_ERR(cgrp)) { bpf_prog_put(prog); diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index 8acd2207e412..10024323031d 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -1323,7 +1323,7 @@ static int check_ctx_access(struct bpf_verifier_env *env, int insn_idx, int off, }; if (env->ops->is_valid_access && - env->ops->is_valid_access(off, size, t, &info)) { + env->ops->is_valid_access(off, size, t, env->prog, &info)) { /* A non zero info.ctx_field_size indicates that this field is a * candidate for later verifier transformation to load the whole * field and then apply a mask when accessed with a narrower @@ -2349,7 +2349,7 @@ static int check_helper_call(struct bpf_verifier_env *env, int func_id, int insn } if (env->ops->get_func_proto) - fn = env->ops->get_func_proto(func_id); + fn = env->ops->get_func_proto(func_id, env->prog); if (!fn) { verbose(env, "unknown func %s#%d\n", func_id_name(func_id), func_id); @@ -5572,7 +5572,7 @@ static int fixup_bpf_calls(struct bpf_verifier_env *env) insn = new_prog->insnsi + i + delta; } patch_call_imm: - fn = env->ops->get_func_proto(insn->imm); + fn = env->ops->get_func_proto(insn->imm, env->prog); /* all functions that have prototype and verifier allowed * programs to call them, must be real in-kernel functions */ diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 463e72d18c4c..d88e96d4e12c 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -524,7 +524,8 @@ static const struct bpf_func_proto bpf_probe_read_str_proto = { .arg3_type = ARG_ANYTHING, }; -static const struct bpf_func_proto *tracing_func_proto(enum bpf_func_id func_id) +static const struct bpf_func_proto * +tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_map_lookup_elem: @@ -568,7 +569,8 @@ static const struct bpf_func_proto *tracing_func_proto(enum bpf_func_id func_id) } } -static const struct bpf_func_proto *kprobe_prog_func_proto(enum bpf_func_id func_id) +static const struct bpf_func_proto * +kprobe_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_perf_event_output: @@ -582,12 +584,13 @@ static const struct bpf_func_proto *kprobe_prog_func_proto(enum bpf_func_id func return &bpf_override_return_proto; #endif default: - return tracing_func_proto(func_id); + return tracing_func_proto(func_id, prog); } } /* bpf+kprobe programs can access fields of 'struct pt_regs' */ static bool kprobe_prog_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { if (off < 0 || off >= sizeof(struct pt_regs)) @@ -661,7 +664,8 @@ static const struct bpf_func_proto bpf_get_stackid_proto_tp = { .arg3_type = ARG_ANYTHING, }; -static const struct bpf_func_proto *tp_prog_func_proto(enum bpf_func_id func_id) +static const struct bpf_func_proto * +tp_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_perf_event_output: @@ -669,11 +673,12 @@ static const struct bpf_func_proto *tp_prog_func_proto(enum bpf_func_id func_id) case BPF_FUNC_get_stackid: return &bpf_get_stackid_proto_tp; default: - return tracing_func_proto(func_id); + return tracing_func_proto(func_id, prog); } } static bool tp_prog_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { if (off < sizeof(void *) || off >= PERF_MAX_TRACE_SIZE) @@ -721,7 +726,8 @@ static const struct bpf_func_proto bpf_perf_prog_read_value_proto = { .arg3_type = ARG_CONST_SIZE, }; -static const struct bpf_func_proto *pe_prog_func_proto(enum bpf_func_id func_id) +static const struct bpf_func_proto * +pe_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_perf_event_output: @@ -731,7 +737,7 @@ static const struct bpf_func_proto *pe_prog_func_proto(enum bpf_func_id func_id) case BPF_FUNC_perf_prog_read_value: return &bpf_perf_prog_read_value_proto; default: - return tracing_func_proto(func_id); + return tracing_func_proto(func_id, prog); } } @@ -781,7 +787,8 @@ static const struct bpf_func_proto bpf_get_stackid_proto_raw_tp = { .arg3_type = ARG_ANYTHING, }; -static const struct bpf_func_proto *raw_tp_prog_func_proto(enum bpf_func_id func_id) +static const struct bpf_func_proto * +raw_tp_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_perf_event_output: @@ -789,12 +796,13 @@ static const struct bpf_func_proto *raw_tp_prog_func_proto(enum bpf_func_id func case BPF_FUNC_get_stackid: return &bpf_get_stackid_proto_raw_tp; default: - return tracing_func_proto(func_id); + return tracing_func_proto(func_id, prog); } } static bool raw_tp_prog_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { /* largest tracepoint in the kernel has 12 args */ @@ -816,6 +824,7 @@ const struct bpf_prog_ops raw_tracepoint_prog_ops = { }; static bool pe_prog_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { const int size_u64 = sizeof(u64); diff --git a/net/core/filter.c b/net/core/filter.c index e989bf313195..7790fd128614 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -3685,7 +3685,7 @@ bpf_base_func_proto(enum bpf_func_id func_id) } static const struct bpf_func_proto * -sock_filter_func_proto(enum bpf_func_id func_id) +sock_filter_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { /* inet and inet6 sockets are created in a process @@ -3699,7 +3699,7 @@ sock_filter_func_proto(enum bpf_func_id func_id) } static const struct bpf_func_proto * -sk_filter_func_proto(enum bpf_func_id func_id) +sk_filter_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_skb_load_bytes: @@ -3714,7 +3714,7 @@ sk_filter_func_proto(enum bpf_func_id func_id) } static const struct bpf_func_proto * -tc_cls_act_func_proto(enum bpf_func_id func_id) +tc_cls_act_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_skb_store_bytes: @@ -3781,7 +3781,7 @@ tc_cls_act_func_proto(enum bpf_func_id func_id) } static const struct bpf_func_proto * -xdp_func_proto(enum bpf_func_id func_id) +xdp_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_perf_event_output: @@ -3804,7 +3804,7 @@ xdp_func_proto(enum bpf_func_id func_id) } static const struct bpf_func_proto * -lwt_inout_func_proto(enum bpf_func_id func_id) +lwt_inout_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_skb_load_bytes: @@ -3831,7 +3831,7 @@ lwt_inout_func_proto(enum bpf_func_id func_id) } static const struct bpf_func_proto * - sock_ops_func_proto(enum bpf_func_id func_id) +sock_ops_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_setsockopt: @@ -3847,7 +3847,8 @@ static const struct bpf_func_proto * } } -static const struct bpf_func_proto *sk_msg_func_proto(enum bpf_func_id func_id) +static const struct bpf_func_proto * +sk_msg_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_msg_redirect_map: @@ -3863,7 +3864,8 @@ static const struct bpf_func_proto *sk_msg_func_proto(enum bpf_func_id func_id) } } -static const struct bpf_func_proto *sk_skb_func_proto(enum bpf_func_id func_id) +static const struct bpf_func_proto * +sk_skb_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_skb_store_bytes: @@ -3888,7 +3890,7 @@ static const struct bpf_func_proto *sk_skb_func_proto(enum bpf_func_id func_id) } static const struct bpf_func_proto * -lwt_xmit_func_proto(enum bpf_func_id func_id) +lwt_xmit_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_skb_get_tunnel_key: @@ -3918,11 +3920,12 @@ lwt_xmit_func_proto(enum bpf_func_id func_id) case BPF_FUNC_set_hash_invalid: return &bpf_set_hash_invalid_proto; default: - return lwt_inout_func_proto(func_id); + return lwt_inout_func_proto(func_id, prog); } } static bool bpf_skb_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { const int size_default = sizeof(__u32); @@ -3966,6 +3969,7 @@ static bool bpf_skb_is_valid_access(int off, int size, enum bpf_access_type type static bool sk_filter_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { switch (off) { @@ -3986,11 +3990,12 @@ static bool sk_filter_is_valid_access(int off, int size, } } - return bpf_skb_is_valid_access(off, size, type, info); + return bpf_skb_is_valid_access(off, size, type, prog, info); } static bool lwt_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { switch (off) { @@ -4020,11 +4025,12 @@ static bool lwt_is_valid_access(int off, int size, break; } - return bpf_skb_is_valid_access(off, size, type, info); + return bpf_skb_is_valid_access(off, size, type, prog, info); } static bool sock_filter_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { if (type == BPF_WRITE) { @@ -4096,6 +4102,7 @@ static int tc_cls_act_prologue(struct bpf_insn *insn_buf, bool direct_write, static bool tc_cls_act_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { if (type == BPF_WRITE) { @@ -4125,7 +4132,7 @@ static bool tc_cls_act_is_valid_access(int off, int size, return false; } - return bpf_skb_is_valid_access(off, size, type, info); + return bpf_skb_is_valid_access(off, size, type, prog, info); } static bool __is_valid_xdp_access(int off, int size) @@ -4142,6 +4149,7 @@ static bool __is_valid_xdp_access(int off, int size) static bool xdp_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { if (type == BPF_WRITE) @@ -4174,6 +4182,7 @@ EXPORT_SYMBOL_GPL(bpf_warn_invalid_xdp_action); static bool sock_ops_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { const int size_default = sizeof(__u32); @@ -4220,6 +4229,7 @@ static int sk_skb_prologue(struct bpf_insn *insn_buf, bool direct_write, static bool sk_skb_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { switch (off) { @@ -4249,11 +4259,12 @@ static bool sk_skb_is_valid_access(int off, int size, break; } - return bpf_skb_is_valid_access(off, size, type, info); + return bpf_skb_is_valid_access(off, size, type, prog, info); } static bool sk_msg_is_valid_access(int off, int size, enum bpf_access_type type, + const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { if (type == BPF_WRITE) -- cgit v1.2.3 From 4fbac77d2d092b475dda9eea66da674369665427 Mon Sep 17 00:00:00 2001 From: Andrey Ignatov Date: Fri, 30 Mar 2018 15:08:02 -0700 Subject: bpf: Hooks for sys_bind == The problem == There is a use-case when all processes inside a cgroup should use one single IP address on a host that has multiple IP configured. Those processes should use the IP for both ingress and egress, for TCP and UDP traffic. So TCP/UDP servers should be bound to that IP to accept incoming connections on it, and TCP/UDP clients should make outgoing connections from that IP. It should not require changing application code since it's often not possible. Currently it's solved by intercepting glibc wrappers around syscalls such as `bind(2)` and `connect(2)`. It's done by a shared library that is preloaded for every process in a cgroup so that whenever TCP/UDP server calls `bind(2)`, the library replaces IP in sockaddr before passing arguments to syscall. When application calls `connect(2)` the library transparently binds the local end of connection to that IP (`bind(2)` with `IP_BIND_ADDRESS_NO_PORT` to avoid performance penalty). Shared library approach is fragile though, e.g.: * some applications clear env vars (incl. `LD_PRELOAD`); * `/etc/ld.so.preload` doesn't help since some applications are linked with option `-z nodefaultlib`; * other applications don't use glibc and there is nothing to intercept. == The solution == The patch provides much more reliable in-kernel solution for the 1st part of the problem: binding TCP/UDP servers on desired IP. It does not depend on application environment and implementation details (whether glibc is used or not). It adds new eBPF program type `BPF_PROG_TYPE_CGROUP_SOCK_ADDR` and attach types `BPF_CGROUP_INET4_BIND` and `BPF_CGROUP_INET6_BIND` (similar to already existing `BPF_CGROUP_INET_SOCK_CREATE`). The new program type is intended to be used with sockets (`struct sock`) in a cgroup and provided by user `struct sockaddr`. Pointers to both of them are parts of the context passed to programs of newly added types. The new attach types provides hooks in `bind(2)` system call for both IPv4 and IPv6 so that one can write a program to override IP addresses and ports user program tries to bind to and apply such a program for whole cgroup. == Implementation notes == [1] Separate attach types for `AF_INET` and `AF_INET6` are added intentionally to prevent reading/writing to offsets that don't make sense for corresponding socket family. E.g. if user passes `sockaddr_in` it doesn't make sense to read from / write to `user_ip6[]` context fields. [2] The write access to `struct bpf_sock_addr_kern` is implemented using special field as an additional "register". There are just two registers in `sock_addr_convert_ctx_access`: `src` with value to write and `dst` with pointer to context that can't be changed not to break later instructions. But the fields, allowed to write to, are not available directly and to access them address of corresponding pointer has to be loaded first. To get additional register the 1st not used by `src` and `dst` one is taken, its content is saved to `bpf_sock_addr_kern.tmp_reg`, then the register is used to load address of pointer field, and finally the register's content is restored from the temporary field after writing `src` value. Signed-off-by: Andrey Ignatov Signed-off-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/bpf-cgroup.h | 21 ++++ include/linux/bpf_types.h | 1 + include/linux/filter.h | 10 ++ include/uapi/linux/bpf.h | 23 +++++ kernel/bpf/cgroup.c | 36 +++++++ kernel/bpf/syscall.c | 36 +++++-- kernel/bpf/verifier.c | 1 + net/core/filter.c | 232 +++++++++++++++++++++++++++++++++++++++++++++ net/ipv4/af_inet.c | 7 ++ net/ipv6/af_inet6.c | 7 ++ 10 files changed, 366 insertions(+), 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/bpf-cgroup.h b/include/linux/bpf-cgroup.h index 8a4566691c8f..67dc4a6471ad 100644 --- a/include/linux/bpf-cgroup.h +++ b/include/linux/bpf-cgroup.h @@ -6,6 +6,7 @@ #include struct sock; +struct sockaddr; struct cgroup; struct sk_buff; struct bpf_sock_ops_kern; @@ -63,6 +64,10 @@ int __cgroup_bpf_run_filter_skb(struct sock *sk, int __cgroup_bpf_run_filter_sk(struct sock *sk, enum bpf_attach_type type); +int __cgroup_bpf_run_filter_sock_addr(struct sock *sk, + struct sockaddr *uaddr, + enum bpf_attach_type type); + int __cgroup_bpf_run_filter_sock_ops(struct sock *sk, struct bpf_sock_ops_kern *sock_ops, enum bpf_attach_type type); @@ -103,6 +108,20 @@ int __cgroup_bpf_check_dev_permission(short dev_type, u32 major, u32 minor, __ret; \ }) +#define BPF_CGROUP_RUN_SA_PROG(sk, uaddr, type) \ +({ \ + int __ret = 0; \ + if (cgroup_bpf_enabled) \ + __ret = __cgroup_bpf_run_filter_sock_addr(sk, uaddr, type); \ + __ret; \ +}) + +#define BPF_CGROUP_RUN_PROG_INET4_BIND(sk, uaddr) \ + BPF_CGROUP_RUN_SA_PROG(sk, uaddr, BPF_CGROUP_INET4_BIND) + +#define BPF_CGROUP_RUN_PROG_INET6_BIND(sk, uaddr) \ + BPF_CGROUP_RUN_SA_PROG(sk, uaddr, BPF_CGROUP_INET6_BIND) + #define BPF_CGROUP_RUN_PROG_SOCK_OPS(sock_ops) \ ({ \ int __ret = 0; \ @@ -135,6 +154,8 @@ static inline int cgroup_bpf_inherit(struct cgroup *cgrp) { return 0; } #define BPF_CGROUP_RUN_PROG_INET_INGRESS(sk,skb) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET_EGRESS(sk,skb) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET4_BIND(sk, uaddr) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET6_BIND(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_SOCK_OPS(sock_ops) ({ 0; }) #define BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type,major,minor,access) ({ 0; }) diff --git a/include/linux/bpf_types.h b/include/linux/bpf_types.h index 6d7243bfb0ff..2b28fcf6f6ae 100644 --- a/include/linux/bpf_types.h +++ b/include/linux/bpf_types.h @@ -8,6 +8,7 @@ BPF_PROG_TYPE(BPF_PROG_TYPE_SCHED_ACT, tc_cls_act) BPF_PROG_TYPE(BPF_PROG_TYPE_XDP, xdp) BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SKB, cg_skb) BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCK, cg_sock) +BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCK_ADDR, cg_sock_addr) BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_IN, lwt_inout) BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_OUT, lwt_inout) BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_XMIT, lwt_xmit) diff --git a/include/linux/filter.h b/include/linux/filter.h index 13c044e4832d..fc4e8f91b03d 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -1021,6 +1021,16 @@ static inline int bpf_tell_extensions(void) return SKF_AD_MAX; } +struct bpf_sock_addr_kern { + struct sock *sk; + struct sockaddr *uaddr; + /* Temporary "register" to make indirect stores to nested structures + * defined above. We need three registers to make such a store, but + * only two (src and dst) are available at convert_ctx_access time + */ + u64 tmp_reg; +}; + struct bpf_sock_ops_kern { struct sock *sk; u32 op; diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 102718624d1e..ce3e69e3c793 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -136,6 +136,7 @@ enum bpf_prog_type { BPF_PROG_TYPE_CGROUP_DEVICE, BPF_PROG_TYPE_SK_MSG, BPF_PROG_TYPE_RAW_TRACEPOINT, + BPF_PROG_TYPE_CGROUP_SOCK_ADDR, }; enum bpf_attach_type { @@ -147,6 +148,8 @@ enum bpf_attach_type { BPF_SK_SKB_STREAM_VERDICT, BPF_CGROUP_DEVICE, BPF_SK_MSG_VERDICT, + BPF_CGROUP_INET4_BIND, + BPF_CGROUP_INET6_BIND, __MAX_BPF_ATTACH_TYPE }; @@ -1010,6 +1013,26 @@ struct bpf_map_info { __u64 netns_ino; } __attribute__((aligned(8))); +/* User bpf_sock_addr struct to access socket fields and sockaddr struct passed + * by user and intended to be used by socket (e.g. to bind to, depends on + * attach attach type). + */ +struct bpf_sock_addr { + __u32 user_family; /* Allows 4-byte read, but no write. */ + __u32 user_ip4; /* Allows 1,2,4-byte read and 4-byte write. + * Stored in network byte order. + */ + __u32 user_ip6[4]; /* Allows 1,2,4-byte read an 4-byte write. + * Stored in network byte order. + */ + __u32 user_port; /* Allows 4-byte read and write. + * Stored in network byte order + */ + __u32 family; /* Allows 4-byte read, but no write */ + __u32 type; /* Allows 4-byte read, but no write */ + __u32 protocol; /* Allows 4-byte read, but no write */ +}; + /* User bpf_sock_ops struct to access socket values and specify request ops * and their replies. * Some of this fields are in network (bigendian) byte order and may need diff --git a/kernel/bpf/cgroup.c b/kernel/bpf/cgroup.c index 8730b24ed540..43171a0bb02b 100644 --- a/kernel/bpf/cgroup.c +++ b/kernel/bpf/cgroup.c @@ -494,6 +494,42 @@ int __cgroup_bpf_run_filter_sk(struct sock *sk, } EXPORT_SYMBOL(__cgroup_bpf_run_filter_sk); +/** + * __cgroup_bpf_run_filter_sock_addr() - Run a program on a sock and + * provided by user sockaddr + * @sk: sock struct that will use sockaddr + * @uaddr: sockaddr struct provided by user + * @type: The type of program to be exectuted + * + * socket is expected to be of type INET or INET6. + * + * This function will return %-EPERM if an attached program is found and + * returned value != 1 during execution. In all other cases, 0 is returned. + */ +int __cgroup_bpf_run_filter_sock_addr(struct sock *sk, + struct sockaddr *uaddr, + enum bpf_attach_type type) +{ + struct bpf_sock_addr_kern ctx = { + .sk = sk, + .uaddr = uaddr, + }; + struct cgroup *cgrp; + int ret; + + /* Check socket family since not all sockets represent network + * endpoint (e.g. AF_UNIX). + */ + if (sk->sk_family != AF_INET && sk->sk_family != AF_INET6) + return 0; + + cgrp = sock_cgroup_ptr(&sk->sk_cgrp_data); + ret = BPF_PROG_RUN_ARRAY(cgrp->bpf.effective[type], &ctx, BPF_PROG_RUN); + + return ret == 1 ? 0 : -EPERM; +} +EXPORT_SYMBOL(__cgroup_bpf_run_filter_sock_addr); + /** * __cgroup_bpf_run_filter_sock_ops() - Run a program on a sock * @sk: socket to get cgroup from diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c index 9d3b572d4dec..2cad66a4cacb 100644 --- a/kernel/bpf/syscall.c +++ b/kernel/bpf/syscall.c @@ -1175,19 +1175,29 @@ static int bpf_prog_load_check_attach_type(enum bpf_prog_type prog_type, enum bpf_attach_type expected_attach_type) { - /* There are currently no prog types that require specifying - * attach_type at load time. - */ - return 0; + switch (prog_type) { + case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: + switch (expected_attach_type) { + case BPF_CGROUP_INET4_BIND: + case BPF_CGROUP_INET6_BIND: + return 0; + default: + return -EINVAL; + } + default: + return 0; + } } static int bpf_prog_attach_check_attach_type(const struct bpf_prog *prog, enum bpf_attach_type attach_type) { - /* There are currently no prog types that require specifying - * attach_type at load time. - */ - return 0; + switch (prog->type) { + case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: + return attach_type == prog->expected_attach_type ? 0 : -EINVAL; + default: + return 0; + } } /* last field in 'union bpf_attr' used by this command */ @@ -1479,6 +1489,10 @@ static int bpf_prog_attach(const union bpf_attr *attr) case BPF_CGROUP_INET_SOCK_CREATE: ptype = BPF_PROG_TYPE_CGROUP_SOCK; break; + case BPF_CGROUP_INET4_BIND: + case BPF_CGROUP_INET6_BIND: + ptype = BPF_PROG_TYPE_CGROUP_SOCK_ADDR; + break; case BPF_CGROUP_SOCK_OPS: ptype = BPF_PROG_TYPE_SOCK_OPS; break; @@ -1541,6 +1555,10 @@ static int bpf_prog_detach(const union bpf_attr *attr) case BPF_CGROUP_INET_SOCK_CREATE: ptype = BPF_PROG_TYPE_CGROUP_SOCK; break; + case BPF_CGROUP_INET4_BIND: + case BPF_CGROUP_INET6_BIND: + ptype = BPF_PROG_TYPE_CGROUP_SOCK_ADDR; + break; case BPF_CGROUP_SOCK_OPS: ptype = BPF_PROG_TYPE_SOCK_OPS; break; @@ -1590,6 +1608,8 @@ static int bpf_prog_query(const union bpf_attr *attr, case BPF_CGROUP_INET_INGRESS: case BPF_CGROUP_INET_EGRESS: case BPF_CGROUP_INET_SOCK_CREATE: + case BPF_CGROUP_INET4_BIND: + case BPF_CGROUP_INET6_BIND: case BPF_CGROUP_SOCK_OPS: case BPF_CGROUP_DEVICE: break; diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index 10024323031d..5dd1dcb902bf 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -3887,6 +3887,7 @@ static int check_return_code(struct bpf_verifier_env *env) switch (env->prog->type) { case BPF_PROG_TYPE_CGROUP_SKB: case BPF_PROG_TYPE_CGROUP_SOCK: + case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: case BPF_PROG_TYPE_SOCK_OPS: case BPF_PROG_TYPE_CGROUP_DEVICE: break; diff --git a/net/core/filter.c b/net/core/filter.c index 7790fd128614..c08e5b121558 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -3698,6 +3698,20 @@ sock_filter_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) } } +static const struct bpf_func_proto * +sock_addr_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) +{ + switch (func_id) { + /* inet and inet6 sockets are created in a process + * context so there is always a valid uid/gid + */ + case BPF_FUNC_get_current_uid_gid: + return &bpf_get_current_uid_gid_proto; + default: + return bpf_base_func_proto(func_id); + } +} + static const struct bpf_func_proto * sk_filter_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { @@ -4180,6 +4194,69 @@ void bpf_warn_invalid_xdp_action(u32 act) } EXPORT_SYMBOL_GPL(bpf_warn_invalid_xdp_action); +static bool sock_addr_is_valid_access(int off, int size, + enum bpf_access_type type, + const struct bpf_prog *prog, + struct bpf_insn_access_aux *info) +{ + const int size_default = sizeof(__u32); + + if (off < 0 || off >= sizeof(struct bpf_sock_addr)) + return false; + if (off % size != 0) + return false; + + /* Disallow access to IPv6 fields from IPv4 contex and vise + * versa. + */ + switch (off) { + case bpf_ctx_range(struct bpf_sock_addr, user_ip4): + switch (prog->expected_attach_type) { + case BPF_CGROUP_INET4_BIND: + break; + default: + return false; + } + break; + case bpf_ctx_range_till(struct bpf_sock_addr, user_ip6[0], user_ip6[3]): + switch (prog->expected_attach_type) { + case BPF_CGROUP_INET6_BIND: + break; + default: + return false; + } + break; + } + + switch (off) { + case bpf_ctx_range(struct bpf_sock_addr, user_ip4): + case bpf_ctx_range_till(struct bpf_sock_addr, user_ip6[0], user_ip6[3]): + /* Only narrow read access allowed for now. */ + if (type == BPF_READ) { + bpf_ctx_record_field_size(info, size_default); + if (!bpf_ctx_narrow_access_ok(off, size, size_default)) + return false; + } else { + if (size != size_default) + return false; + } + break; + case bpf_ctx_range(struct bpf_sock_addr, user_port): + if (size != size_default) + return false; + break; + default: + if (type == BPF_READ) { + if (size != size_default) + return false; + } else { + return false; + } + } + + return true; +} + static bool sock_ops_is_valid_access(int off, int size, enum bpf_access_type type, const struct bpf_prog *prog, @@ -4724,6 +4801,152 @@ static u32 xdp_convert_ctx_access(enum bpf_access_type type, return insn - insn_buf; } +/* SOCK_ADDR_LOAD_NESTED_FIELD() loads Nested Field S.F.NF where S is type of + * context Structure, F is Field in context structure that contains a pointer + * to Nested Structure of type NS that has the field NF. + * + * SIZE encodes the load size (BPF_B, BPF_H, etc). It's up to caller to make + * sure that SIZE is not greater than actual size of S.F.NF. + * + * If offset OFF is provided, the load happens from that offset relative to + * offset of NF. + */ +#define SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF(S, NS, F, NF, SIZE, OFF) \ + do { \ + *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(S, F), si->dst_reg, \ + si->src_reg, offsetof(S, F)); \ + *insn++ = BPF_LDX_MEM( \ + SIZE, si->dst_reg, si->dst_reg, \ + bpf_target_off(NS, NF, FIELD_SIZEOF(NS, NF), \ + target_size) \ + + OFF); \ + } while (0) + +#define SOCK_ADDR_LOAD_NESTED_FIELD(S, NS, F, NF) \ + SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF(S, NS, F, NF, \ + BPF_FIELD_SIZEOF(NS, NF), 0) + +/* SOCK_ADDR_STORE_NESTED_FIELD_OFF() has semantic similar to + * SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF() but for store operation. + * + * It doesn't support SIZE argument though since narrow stores are not + * supported for now. + * + * In addition it uses Temporary Field TF (member of struct S) as the 3rd + * "register" since two registers available in convert_ctx_access are not + * enough: we can't override neither SRC, since it contains value to store, nor + * DST since it contains pointer to context that may be used by later + * instructions. But we need a temporary place to save pointer to nested + * structure whose field we want to store to. + */ +#define SOCK_ADDR_STORE_NESTED_FIELD_OFF(S, NS, F, NF, OFF, TF) \ + do { \ + int tmp_reg = BPF_REG_9; \ + if (si->src_reg == tmp_reg || si->dst_reg == tmp_reg) \ + --tmp_reg; \ + if (si->src_reg == tmp_reg || si->dst_reg == tmp_reg) \ + --tmp_reg; \ + *insn++ = BPF_STX_MEM(BPF_DW, si->dst_reg, tmp_reg, \ + offsetof(S, TF)); \ + *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(S, F), tmp_reg, \ + si->dst_reg, offsetof(S, F)); \ + *insn++ = BPF_STX_MEM( \ + BPF_FIELD_SIZEOF(NS, NF), tmp_reg, si->src_reg, \ + bpf_target_off(NS, NF, FIELD_SIZEOF(NS, NF), \ + target_size) \ + + OFF); \ + *insn++ = BPF_LDX_MEM(BPF_DW, tmp_reg, si->dst_reg, \ + offsetof(S, TF)); \ + } while (0) + +#define SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD_SIZE_OFF(S, NS, F, NF, SIZE, OFF, \ + TF) \ + do { \ + if (type == BPF_WRITE) { \ + SOCK_ADDR_STORE_NESTED_FIELD_OFF(S, NS, F, NF, OFF, \ + TF); \ + } else { \ + SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF( \ + S, NS, F, NF, SIZE, OFF); \ + } \ + } while (0) + +#define SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD(S, NS, F, NF, TF) \ + SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD_SIZE_OFF( \ + S, NS, F, NF, BPF_FIELD_SIZEOF(NS, NF), 0, TF) + +static u32 sock_addr_convert_ctx_access(enum bpf_access_type type, + const struct bpf_insn *si, + struct bpf_insn *insn_buf, + struct bpf_prog *prog, u32 *target_size) +{ + struct bpf_insn *insn = insn_buf; + int off; + + switch (si->off) { + case offsetof(struct bpf_sock_addr, user_family): + SOCK_ADDR_LOAD_NESTED_FIELD(struct bpf_sock_addr_kern, + struct sockaddr, uaddr, sa_family); + break; + + case offsetof(struct bpf_sock_addr, user_ip4): + SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD_SIZE_OFF( + struct bpf_sock_addr_kern, struct sockaddr_in, uaddr, + sin_addr, BPF_SIZE(si->code), 0, tmp_reg); + break; + + case bpf_ctx_range_till(struct bpf_sock_addr, user_ip6[0], user_ip6[3]): + off = si->off; + off -= offsetof(struct bpf_sock_addr, user_ip6[0]); + SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD_SIZE_OFF( + struct bpf_sock_addr_kern, struct sockaddr_in6, uaddr, + sin6_addr.s6_addr32[0], BPF_SIZE(si->code), off, + tmp_reg); + break; + + case offsetof(struct bpf_sock_addr, user_port): + /* To get port we need to know sa_family first and then treat + * sockaddr as either sockaddr_in or sockaddr_in6. + * Though we can simplify since port field has same offset and + * size in both structures. + * Here we check this invariant and use just one of the + * structures if it's true. + */ + BUILD_BUG_ON(offsetof(struct sockaddr_in, sin_port) != + offsetof(struct sockaddr_in6, sin6_port)); + BUILD_BUG_ON(FIELD_SIZEOF(struct sockaddr_in, sin_port) != + FIELD_SIZEOF(struct sockaddr_in6, sin6_port)); + SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD(struct bpf_sock_addr_kern, + struct sockaddr_in6, uaddr, + sin6_port, tmp_reg); + break; + + case offsetof(struct bpf_sock_addr, family): + SOCK_ADDR_LOAD_NESTED_FIELD(struct bpf_sock_addr_kern, + struct sock, sk, sk_family); + break; + + case offsetof(struct bpf_sock_addr, type): + SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF( + struct bpf_sock_addr_kern, struct sock, sk, + __sk_flags_offset, BPF_W, 0); + *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_TYPE_MASK); + *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, SK_FL_TYPE_SHIFT); + break; + + case offsetof(struct bpf_sock_addr, protocol): + SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF( + struct bpf_sock_addr_kern, struct sock, sk, + __sk_flags_offset, BPF_W, 0); + *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_PROTO_MASK); + *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, + SK_FL_PROTO_SHIFT); + break; + } + + return insn - insn_buf; +} + static u32 sock_ops_convert_ctx_access(enum bpf_access_type type, const struct bpf_insn *si, struct bpf_insn *insn_buf, @@ -5181,6 +5404,15 @@ const struct bpf_verifier_ops cg_sock_verifier_ops = { const struct bpf_prog_ops cg_sock_prog_ops = { }; +const struct bpf_verifier_ops cg_sock_addr_verifier_ops = { + .get_func_proto = sock_addr_func_proto, + .is_valid_access = sock_addr_is_valid_access, + .convert_ctx_access = sock_addr_convert_ctx_access, +}; + +const struct bpf_prog_ops cg_sock_addr_prog_ops = { +}; + const struct bpf_verifier_ops sock_ops_verifier_ops = { .get_func_proto = sock_ops_func_proto, .is_valid_access = sock_ops_is_valid_access, diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index e8c7fad8c329..2dec266507dc 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -450,6 +450,13 @@ int inet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) if (addr_len < sizeof(struct sockaddr_in)) goto out; + /* BPF prog is run before any checks are done so that if the prog + * changes context in a wrong way it will be caught. + */ + err = BPF_CGROUP_RUN_PROG_INET4_BIND(sk, uaddr); + if (err) + goto out; + if (addr->sin_family != AF_INET) { /* Compatibility games : accept AF_UNSPEC (mapped to AF_INET) * only if s_addr is INADDR_ANY. diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index dbbe04018813..fa24e3f06ac6 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -295,6 +295,13 @@ int inet6_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) if (addr_len < SIN6_LEN_RFC2133) return -EINVAL; + /* BPF prog is run before any checks are done so that if the prog + * changes context in a wrong way it will be caught. + */ + err = BPF_CGROUP_RUN_PROG_INET6_BIND(sk, uaddr); + if (err) + return err; + if (addr->sin6_family != AF_INET6) return -EAFNOSUPPORT; -- cgit v1.2.3 From d74bad4e74ee373787a9ae24197c17b7cdc428d5 Mon Sep 17 00:00:00 2001 From: Andrey Ignatov Date: Fri, 30 Mar 2018 15:08:05 -0700 Subject: bpf: Hooks for sys_connect == The problem == See description of the problem in the initial patch of this patch set. == The solution == The patch provides much more reliable in-kernel solution for the 2nd part of the problem: making outgoing connecttion from desired IP. It adds new attach types `BPF_CGROUP_INET4_CONNECT` and `BPF_CGROUP_INET6_CONNECT` for program type `BPF_PROG_TYPE_CGROUP_SOCK_ADDR` that can be used to override both source and destination of a connection at connect(2) time. Local end of connection can be bound to desired IP using newly introduced BPF-helper `bpf_bind()`. It allows to bind to only IP though, and doesn't support binding to port, i.e. leverages `IP_BIND_ADDRESS_NO_PORT` socket option. There are two reasons for this: * looking for a free port is expensive and can affect performance significantly; * there is no use-case for port. As for remote end (`struct sockaddr *` passed by user), both parts of it can be overridden, remote IP and remote port. It's useful if an application inside cgroup wants to connect to another application inside same cgroup or to itself, but knows nothing about IP assigned to the cgroup. Support is added for IPv4 and IPv6, for TCP and UDP. IPv4 and IPv6 have separate attach types for same reason as sys_bind hooks, i.e. to prevent reading from / writing to e.g. user_ip6 fields when user passes sockaddr_in since it'd be out-of-bound. == Implementation notes == The patch introduces new field in `struct proto`: `pre_connect` that is a pointer to a function with same signature as `connect` but is called before it. The reason is in some cases BPF hooks should be called way before control is passed to `sk->sk_prot->connect`. Specifically `inet_dgram_connect` autobinds socket before calling `sk->sk_prot->connect` and there is no way to call `bpf_bind()` from hooks from e.g. `ip4_datagram_connect` or `ip6_datagram_connect` since it'd cause double-bind. On the other hand `proto.pre_connect` provides a flexible way to add BPF hooks for connect only for necessary `proto` and call them at desired time before `connect`. Since `bpf_bind()` is allowed to bind only to IP and autobind in `inet_dgram_connect` binds only port there is no chance of double-bind. bpf_bind() sets `force_bind_address_no_port` to bind to only IP despite of value of `bind_address_no_port` socket field. bpf_bind() sets `with_lock` to `false` when calling to __inet_bind() and __inet6_bind() since all call-sites, where bpf_bind() is called, already hold socket lock. Signed-off-by: Andrey Ignatov Signed-off-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/bpf-cgroup.h | 31 +++++++++++++++++++++++++ include/net/addrconf.h | 7 ++++++ include/net/sock.h | 3 +++ include/net/udp.h | 1 + include/uapi/linux/bpf.h | 12 +++++++++- kernel/bpf/syscall.c | 8 +++++++ net/core/filter.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ net/ipv4/af_inet.c | 13 +++++++++++ net/ipv4/tcp_ipv4.c | 16 +++++++++++++ net/ipv4/udp.c | 14 ++++++++++++ net/ipv6/af_inet6.c | 5 ++++ net/ipv6/tcp_ipv6.c | 16 +++++++++++++ net/ipv6/udp.c | 20 ++++++++++++++++ 13 files changed, 202 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/bpf-cgroup.h b/include/linux/bpf-cgroup.h index 67dc4a6471ad..c6ab295e6dcb 100644 --- a/include/linux/bpf-cgroup.h +++ b/include/linux/bpf-cgroup.h @@ -116,12 +116,38 @@ int __cgroup_bpf_check_dev_permission(short dev_type, u32 major, u32 minor, __ret; \ }) +#define BPF_CGROUP_RUN_SA_PROG_LOCK(sk, uaddr, type) \ +({ \ + int __ret = 0; \ + if (cgroup_bpf_enabled) { \ + lock_sock(sk); \ + __ret = __cgroup_bpf_run_filter_sock_addr(sk, uaddr, type); \ + release_sock(sk); \ + } \ + __ret; \ +}) + #define BPF_CGROUP_RUN_PROG_INET4_BIND(sk, uaddr) \ BPF_CGROUP_RUN_SA_PROG(sk, uaddr, BPF_CGROUP_INET4_BIND) #define BPF_CGROUP_RUN_PROG_INET6_BIND(sk, uaddr) \ BPF_CGROUP_RUN_SA_PROG(sk, uaddr, BPF_CGROUP_INET6_BIND) +#define BPF_CGROUP_PRE_CONNECT_ENABLED(sk) (cgroup_bpf_enabled && \ + sk->sk_prot->pre_connect) + +#define BPF_CGROUP_RUN_PROG_INET4_CONNECT(sk, uaddr) \ + BPF_CGROUP_RUN_SA_PROG(sk, uaddr, BPF_CGROUP_INET4_CONNECT) + +#define BPF_CGROUP_RUN_PROG_INET6_CONNECT(sk, uaddr) \ + BPF_CGROUP_RUN_SA_PROG(sk, uaddr, BPF_CGROUP_INET6_CONNECT) + +#define BPF_CGROUP_RUN_PROG_INET4_CONNECT_LOCK(sk, uaddr) \ + BPF_CGROUP_RUN_SA_PROG_LOCK(sk, uaddr, BPF_CGROUP_INET4_CONNECT) + +#define BPF_CGROUP_RUN_PROG_INET6_CONNECT_LOCK(sk, uaddr) \ + BPF_CGROUP_RUN_SA_PROG_LOCK(sk, uaddr, BPF_CGROUP_INET6_CONNECT) + #define BPF_CGROUP_RUN_PROG_SOCK_OPS(sock_ops) \ ({ \ int __ret = 0; \ @@ -151,11 +177,16 @@ struct cgroup_bpf {}; static inline void cgroup_bpf_put(struct cgroup *cgrp) {} static inline int cgroup_bpf_inherit(struct cgroup *cgrp) { return 0; } +#define BPF_CGROUP_PRE_CONNECT_ENABLED(sk) (0) #define BPF_CGROUP_RUN_PROG_INET_INGRESS(sk,skb) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET_EGRESS(sk,skb) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET4_BIND(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET6_BIND(sk, uaddr) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET4_CONNECT(sk, uaddr) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET4_CONNECT_LOCK(sk, uaddr) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET6_CONNECT(sk, uaddr) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET6_CONNECT_LOCK(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_SOCK_OPS(sock_ops) ({ 0; }) #define BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type,major,minor,access) ({ 0; }) diff --git a/include/net/addrconf.h b/include/net/addrconf.h index 132e5b95167a..378d601258be 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -231,6 +231,13 @@ struct ipv6_stub { }; extern const struct ipv6_stub *ipv6_stub __read_mostly; +/* A stub used by bpf helpers. Similarly ugly as ipv6_stub */ +struct ipv6_bpf_stub { + int (*inet6_bind)(struct sock *sk, struct sockaddr *uaddr, int addr_len, + bool force_bind_address_no_port, bool with_lock); +}; +extern const struct ipv6_bpf_stub *ipv6_bpf_stub __read_mostly; + /* * identify MLD packets for MLD filter exceptions */ diff --git a/include/net/sock.h b/include/net/sock.h index b8ff435fa96e..49bd2c1796b0 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1026,6 +1026,9 @@ static inline void sk_prot_clear_nulls(struct sock *sk, int size) struct proto { void (*close)(struct sock *sk, long timeout); + int (*pre_connect)(struct sock *sk, + struct sockaddr *uaddr, + int addr_len); int (*connect)(struct sock *sk, struct sockaddr *uaddr, int addr_len); diff --git a/include/net/udp.h b/include/net/udp.h index 850a8e581cce..0676b272f6ac 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -273,6 +273,7 @@ void udp4_hwcsum(struct sk_buff *skb, __be32 src, __be32 dst); int udp_rcv(struct sk_buff *skb); int udp_ioctl(struct sock *sk, int cmd, unsigned long arg); int udp_init_sock(struct sock *sk); +int udp_pre_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len); int __udp_disconnect(struct sock *sk, int flags); int udp_disconnect(struct sock *sk, int flags); __poll_t udp_poll(struct file *file, struct socket *sock, poll_table *wait); diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index ce3e69e3c793..77afaf1ba556 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -150,6 +150,8 @@ enum bpf_attach_type { BPF_SK_MSG_VERDICT, BPF_CGROUP_INET4_BIND, BPF_CGROUP_INET6_BIND, + BPF_CGROUP_INET4_CONNECT, + BPF_CGROUP_INET6_CONNECT, __MAX_BPF_ATTACH_TYPE }; @@ -744,6 +746,13 @@ union bpf_attr { * @flags: reserved for future use * Return: SK_PASS * + * int bpf_bind(ctx, addr, addr_len) + * Bind socket to address. Only binding to IP is supported, no port can be + * set in addr. + * @ctx: pointer to context of type bpf_sock_addr + * @addr: pointer to struct sockaddr to bind socket to + * @addr_len: length of sockaddr structure + * Return: 0 on success or negative error code */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -809,7 +818,8 @@ union bpf_attr { FN(msg_redirect_map), \ FN(msg_apply_bytes), \ FN(msg_cork_bytes), \ - FN(msg_pull_data), + FN(msg_pull_data), \ + FN(bind), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c index 2cad66a4cacb..cf1b29bc0ab8 100644 --- a/kernel/bpf/syscall.c +++ b/kernel/bpf/syscall.c @@ -1180,6 +1180,8 @@ bpf_prog_load_check_attach_type(enum bpf_prog_type prog_type, switch (expected_attach_type) { case BPF_CGROUP_INET4_BIND: case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET4_CONNECT: + case BPF_CGROUP_INET6_CONNECT: return 0; default: return -EINVAL; @@ -1491,6 +1493,8 @@ static int bpf_prog_attach(const union bpf_attr *attr) break; case BPF_CGROUP_INET4_BIND: case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET4_CONNECT: + case BPF_CGROUP_INET6_CONNECT: ptype = BPF_PROG_TYPE_CGROUP_SOCK_ADDR; break; case BPF_CGROUP_SOCK_OPS: @@ -1557,6 +1561,8 @@ static int bpf_prog_detach(const union bpf_attr *attr) break; case BPF_CGROUP_INET4_BIND: case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET4_CONNECT: + case BPF_CGROUP_INET6_CONNECT: ptype = BPF_PROG_TYPE_CGROUP_SOCK_ADDR; break; case BPF_CGROUP_SOCK_OPS: @@ -1610,6 +1616,8 @@ static int bpf_prog_query(const union bpf_attr *attr, case BPF_CGROUP_INET_SOCK_CREATE: case BPF_CGROUP_INET4_BIND: case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET4_CONNECT: + case BPF_CGROUP_INET6_CONNECT: case BPF_CGROUP_SOCK_OPS: case BPF_CGROUP_DEVICE: break; diff --git a/net/core/filter.c b/net/core/filter.c index c08e5b121558..bdb9cadd4d27 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -3656,6 +3657,52 @@ static const struct bpf_func_proto bpf_sock_ops_cb_flags_set_proto = { .arg2_type = ARG_ANYTHING, }; +const struct ipv6_bpf_stub *ipv6_bpf_stub __read_mostly; +EXPORT_SYMBOL_GPL(ipv6_bpf_stub); + +BPF_CALL_3(bpf_bind, struct bpf_sock_addr_kern *, ctx, struct sockaddr *, addr, + int, addr_len) +{ +#ifdef CONFIG_INET + struct sock *sk = ctx->sk; + int err; + + /* Binding to port can be expensive so it's prohibited in the helper. + * Only binding to IP is supported. + */ + err = -EINVAL; + if (addr->sa_family == AF_INET) { + if (addr_len < sizeof(struct sockaddr_in)) + return err; + if (((struct sockaddr_in *)addr)->sin_port != htons(0)) + return err; + return __inet_bind(sk, addr, addr_len, true, false); +#if IS_ENABLED(CONFIG_IPV6) + } else if (addr->sa_family == AF_INET6) { + if (addr_len < SIN6_LEN_RFC2133) + return err; + if (((struct sockaddr_in6 *)addr)->sin6_port != htons(0)) + return err; + /* ipv6_bpf_stub cannot be NULL, since it's called from + * bpf_cgroup_inet6_connect hook and ipv6 is already loaded + */ + return ipv6_bpf_stub->inet6_bind(sk, addr, addr_len, true, false); +#endif /* CONFIG_IPV6 */ + } +#endif /* CONFIG_INET */ + + return -EAFNOSUPPORT; +} + +static const struct bpf_func_proto bpf_bind_proto = { + .func = bpf_bind, + .gpl_only = false, + .ret_type = RET_INTEGER, + .arg1_type = ARG_PTR_TO_CTX, + .arg2_type = ARG_PTR_TO_MEM, + .arg3_type = ARG_CONST_SIZE, +}; + static const struct bpf_func_proto * bpf_base_func_proto(enum bpf_func_id func_id) { @@ -3707,6 +3754,14 @@ sock_addr_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) */ case BPF_FUNC_get_current_uid_gid: return &bpf_get_current_uid_gid_proto; + case BPF_FUNC_bind: + switch (prog->expected_attach_type) { + case BPF_CGROUP_INET4_CONNECT: + case BPF_CGROUP_INET6_CONNECT: + return &bpf_bind_proto; + default: + return NULL; + } default: return bpf_base_func_proto(func_id); } @@ -4213,6 +4268,7 @@ static bool sock_addr_is_valid_access(int off, int size, case bpf_ctx_range(struct bpf_sock_addr, user_ip4): switch (prog->expected_attach_type) { case BPF_CGROUP_INET4_BIND: + case BPF_CGROUP_INET4_CONNECT: break; default: return false; @@ -4221,6 +4277,7 @@ static bool sock_addr_is_valid_access(int off, int size, case bpf_ctx_range_till(struct bpf_sock_addr, user_ip6[0], user_ip6[3]): switch (prog->expected_attach_type) { case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET6_CONNECT: break; default: return false; diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index e203a39d6988..488fe26ac8e5 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -547,12 +547,19 @@ int inet_dgram_connect(struct socket *sock, struct sockaddr *uaddr, int addr_len, int flags) { struct sock *sk = sock->sk; + int err; if (addr_len < sizeof(uaddr->sa_family)) return -EINVAL; if (uaddr->sa_family == AF_UNSPEC) return sk->sk_prot->disconnect(sk, flags); + if (BPF_CGROUP_PRE_CONNECT_ENABLED(sk)) { + err = sk->sk_prot->pre_connect(sk, uaddr, addr_len); + if (err) + return err; + } + if (!inet_sk(sk)->inet_num && inet_autobind(sk)) return -EAGAIN; return sk->sk_prot->connect(sk, uaddr, addr_len); @@ -633,6 +640,12 @@ int __inet_stream_connect(struct socket *sock, struct sockaddr *uaddr, if (sk->sk_state != TCP_CLOSE) goto out; + if (BPF_CGROUP_PRE_CONNECT_ENABLED(sk)) { + err = sk->sk_prot->pre_connect(sk, uaddr, addr_len); + if (err) + goto out; + } + err = sk->sk_prot->connect(sk, uaddr, addr_len); if (err < 0) goto out; diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index 2c6aec2643e8..3c11d992d784 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -140,6 +140,21 @@ int tcp_twsk_unique(struct sock *sk, struct sock *sktw, void *twp) } EXPORT_SYMBOL_GPL(tcp_twsk_unique); +static int tcp_v4_pre_connect(struct sock *sk, struct sockaddr *uaddr, + int addr_len) +{ + /* This check is replicated from tcp_v4_connect() and intended to + * prevent BPF program called below from accessing bytes that are out + * of the bound specified by user in addr_len. + */ + if (addr_len < sizeof(struct sockaddr_in)) + return -EINVAL; + + sock_owned_by_me(sk); + + return BPF_CGROUP_RUN_PROG_INET4_CONNECT(sk, uaddr); +} + /* This will initiate an outgoing connection. */ int tcp_v4_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len) { @@ -2409,6 +2424,7 @@ struct proto tcp_prot = { .name = "TCP", .owner = THIS_MODULE, .close = tcp_close, + .pre_connect = tcp_v4_pre_connect, .connect = tcp_v4_connect, .disconnect = tcp_disconnect, .accept = inet_csk_accept, diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c index 908fc02fb4f8..9c6c77fec963 100644 --- a/net/ipv4/udp.c +++ b/net/ipv4/udp.c @@ -1658,6 +1658,19 @@ csum_copy_err: goto try_again; } +int udp_pre_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len) +{ + /* This check is replicated from __ip4_datagram_connect() and + * intended to prevent BPF program called below from accessing bytes + * that are out of the bound specified by user in addr_len. + */ + if (addr_len < sizeof(struct sockaddr_in)) + return -EINVAL; + + return BPF_CGROUP_RUN_PROG_INET4_CONNECT_LOCK(sk, uaddr); +} +EXPORT_SYMBOL(udp_pre_connect); + int __udp_disconnect(struct sock *sk, int flags) { struct inet_sock *inet = inet_sk(sk); @@ -2530,6 +2543,7 @@ struct proto udp_prot = { .name = "UDP", .owner = THIS_MODULE, .close = udp_lib_close, + .pre_connect = udp_pre_connect, .connect = ip4_datagram_connect, .disconnect = udp_disconnect, .ioctl = udp_ioctl, diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index 13110bee5c14..566cec0e0a44 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -887,6 +887,10 @@ static const struct ipv6_stub ipv6_stub_impl = { .nd_tbl = &nd_tbl, }; +static const struct ipv6_bpf_stub ipv6_bpf_stub_impl = { + .inet6_bind = __inet6_bind, +}; + static int __init inet6_init(void) { struct list_head *r; @@ -1043,6 +1047,7 @@ static int __init inet6_init(void) /* ensure that ipv6 stubs are visible only after ipv6 is ready */ wmb(); ipv6_stub = &ipv6_stub_impl; + ipv6_bpf_stub = &ipv6_bpf_stub_impl; out: return err; diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index 5425d7b100ee..6469b741cf5a 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -117,6 +117,21 @@ static u32 tcp_v6_init_ts_off(const struct net *net, const struct sk_buff *skb) ipv6_hdr(skb)->saddr.s6_addr32); } +static int tcp_v6_pre_connect(struct sock *sk, struct sockaddr *uaddr, + int addr_len) +{ + /* This check is replicated from tcp_v6_connect() and intended to + * prevent BPF program called below from accessing bytes that are out + * of the bound specified by user in addr_len. + */ + if (addr_len < SIN6_LEN_RFC2133) + return -EINVAL; + + sock_owned_by_me(sk); + + return BPF_CGROUP_RUN_PROG_INET6_CONNECT(sk, uaddr); +} + static int tcp_v6_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len) { @@ -1925,6 +1940,7 @@ struct proto tcpv6_prot = { .name = "TCPv6", .owner = THIS_MODULE, .close = tcp_close, + .pre_connect = tcp_v6_pre_connect, .connect = tcp_v6_connect, .disconnect = tcp_disconnect, .accept = inet_csk_accept, diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index ad30f5e31969..6861ed479469 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -957,6 +957,25 @@ static void udp_v6_flush_pending_frames(struct sock *sk) } } +static int udpv6_pre_connect(struct sock *sk, struct sockaddr *uaddr, + int addr_len) +{ + /* The following checks are replicated from __ip6_datagram_connect() + * and intended to prevent BPF program called below from accessing + * bytes that are out of the bound specified by user in addr_len. + */ + if (uaddr->sa_family == AF_INET) { + if (__ipv6_only_sock(sk)) + return -EAFNOSUPPORT; + return udp_pre_connect(sk, uaddr, addr_len); + } + + if (addr_len < SIN6_LEN_RFC2133) + return -EINVAL; + + return BPF_CGROUP_RUN_PROG_INET6_CONNECT_LOCK(sk, uaddr); +} + /** * udp6_hwcsum_outgoing - handle outgoing HW checksumming * @sk: socket we are sending on @@ -1512,6 +1531,7 @@ struct proto udpv6_prot = { .name = "UDPv6", .owner = THIS_MODULE, .close = udp_lib_close, + .pre_connect = udpv6_pre_connect, .connect = ip6_datagram_connect, .disconnect = udp_disconnect, .ioctl = udp_ioctl, -- cgit v1.2.3 From aac3fc320d9404f2665a8b1249dc3170d5fa3caf Mon Sep 17 00:00:00 2001 From: Andrey Ignatov Date: Fri, 30 Mar 2018 15:08:07 -0700 Subject: bpf: Post-hooks for sys_bind "Post-hooks" are hooks that are called right before returning from sys_bind. At this time IP and port are already allocated and no further changes to `struct sock` can happen before returning from sys_bind but BPF program has a chance to inspect the socket and change sys_bind result. Specifically it can e.g. inspect what port was allocated and if it doesn't satisfy some policy, BPF program can force sys_bind to fail and return EPERM to user. Another example of usage is recording the IP:port pair to some map to use it in later calls to sys_connect. E.g. if some TCP server inside cgroup was bound to some IP:port_n, it can be recorded to a map. And later when some TCP client inside same cgroup is trying to connect to 127.0.0.1:port_n, BPF hook for sys_connect can override the destination and connect application to IP:port_n instead of 127.0.0.1:port_n. That helps forcing all applications inside a cgroup to use desired IP and not break those applications if they e.g. use localhost to communicate between each other. == Implementation details == Post-hooks are implemented as two new attach types `BPF_CGROUP_INET4_POST_BIND` and `BPF_CGROUP_INET6_POST_BIND` for existing prog type `BPF_PROG_TYPE_CGROUP_SOCK`. Separate attach types for IPv4 and IPv6 are introduced to avoid access to IPv6 field in `struct sock` from `inet_bind()` and to IPv4 field from `inet6_bind()` since those fields might not make sense in such cases. Signed-off-by: Andrey Ignatov Signed-off-by: Alexei Starovoitov Signed-off-by: Daniel Borkmann --- include/linux/bpf-cgroup.h | 16 +++++-- include/uapi/linux/bpf.h | 11 +++++ kernel/bpf/syscall.c | 43 +++++++++++++++++ net/core/filter.c | 116 +++++++++++++++++++++++++++++++++++++++------ net/ipv4/af_inet.c | 18 ++++--- net/ipv6/af_inet6.c | 21 +++++--- 6 files changed, 195 insertions(+), 30 deletions(-) (limited to 'include/linux') diff --git a/include/linux/bpf-cgroup.h b/include/linux/bpf-cgroup.h index c6ab295e6dcb..30d15e64b993 100644 --- a/include/linux/bpf-cgroup.h +++ b/include/linux/bpf-cgroup.h @@ -98,16 +98,24 @@ int __cgroup_bpf_check_dev_permission(short dev_type, u32 major, u32 minor, __ret; \ }) -#define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) \ +#define BPF_CGROUP_RUN_SK_PROG(sk, type) \ ({ \ int __ret = 0; \ if (cgroup_bpf_enabled) { \ - __ret = __cgroup_bpf_run_filter_sk(sk, \ - BPF_CGROUP_INET_SOCK_CREATE); \ + __ret = __cgroup_bpf_run_filter_sk(sk, type); \ } \ __ret; \ }) +#define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) \ + BPF_CGROUP_RUN_SK_PROG(sk, BPF_CGROUP_INET_SOCK_CREATE) + +#define BPF_CGROUP_RUN_PROG_INET4_POST_BIND(sk) \ + BPF_CGROUP_RUN_SK_PROG(sk, BPF_CGROUP_INET4_POST_BIND) + +#define BPF_CGROUP_RUN_PROG_INET6_POST_BIND(sk) \ + BPF_CGROUP_RUN_SK_PROG(sk, BPF_CGROUP_INET6_POST_BIND) + #define BPF_CGROUP_RUN_SA_PROG(sk, uaddr, type) \ ({ \ int __ret = 0; \ @@ -183,6 +191,8 @@ static inline int cgroup_bpf_inherit(struct cgroup *cgrp) { return 0; } #define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET4_BIND(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET6_BIND(sk, uaddr) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET4_POST_BIND(sk) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_INET6_POST_BIND(sk) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET4_CONNECT(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET4_CONNECT_LOCK(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET6_CONNECT(sk, uaddr) ({ 0; }) diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 77afaf1ba556..c5ec89732a8d 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -152,6 +152,8 @@ enum bpf_attach_type { BPF_CGROUP_INET6_BIND, BPF_CGROUP_INET4_CONNECT, BPF_CGROUP_INET6_CONNECT, + BPF_CGROUP_INET4_POST_BIND, + BPF_CGROUP_INET6_POST_BIND, __MAX_BPF_ATTACH_TYPE }; @@ -948,6 +950,15 @@ struct bpf_sock { __u32 protocol; __u32 mark; __u32 priority; + __u32 src_ip4; /* Allows 1,2,4-byte read. + * Stored in network byte order. + */ + __u32 src_ip6[4]; /* Allows 1,2,4-byte read. + * Stored in network byte order. + */ + __u32 src_port; /* Allows 4-byte read. + * Stored in host byte order + */ }; #define XDP_PACKET_HEADROOM 256 diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c index cf1b29bc0ab8..0244973ee544 100644 --- a/kernel/bpf/syscall.c +++ b/kernel/bpf/syscall.c @@ -1171,11 +1171,46 @@ struct bpf_prog *bpf_prog_get_type_dev(u32 ufd, enum bpf_prog_type type, } EXPORT_SYMBOL_GPL(bpf_prog_get_type_dev); +/* Initially all BPF programs could be loaded w/o specifying + * expected_attach_type. Later for some of them specifying expected_attach_type + * at load time became required so that program could be validated properly. + * Programs of types that are allowed to be loaded both w/ and w/o (for + * backward compatibility) expected_attach_type, should have the default attach + * type assigned to expected_attach_type for the latter case, so that it can be + * validated later at attach time. + * + * bpf_prog_load_fixup_attach_type() sets expected_attach_type in @attr if + * prog type requires it but has some attach types that have to be backward + * compatible. + */ +static void bpf_prog_load_fixup_attach_type(union bpf_attr *attr) +{ + switch (attr->prog_type) { + case BPF_PROG_TYPE_CGROUP_SOCK: + /* Unfortunately BPF_ATTACH_TYPE_UNSPEC enumeration doesn't + * exist so checking for non-zero is the way to go here. + */ + if (!attr->expected_attach_type) + attr->expected_attach_type = + BPF_CGROUP_INET_SOCK_CREATE; + break; + } +} + static int bpf_prog_load_check_attach_type(enum bpf_prog_type prog_type, enum bpf_attach_type expected_attach_type) { switch (prog_type) { + case BPF_PROG_TYPE_CGROUP_SOCK: + switch (expected_attach_type) { + case BPF_CGROUP_INET_SOCK_CREATE: + case BPF_CGROUP_INET4_POST_BIND: + case BPF_CGROUP_INET6_POST_BIND: + return 0; + default: + return -EINVAL; + } case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: switch (expected_attach_type) { case BPF_CGROUP_INET4_BIND: @@ -1195,6 +1230,7 @@ static int bpf_prog_attach_check_attach_type(const struct bpf_prog *prog, enum bpf_attach_type attach_type) { switch (prog->type) { + case BPF_PROG_TYPE_CGROUP_SOCK: case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: return attach_type == prog->expected_attach_type ? 0 : -EINVAL; default: @@ -1240,6 +1276,7 @@ static int bpf_prog_load(union bpf_attr *attr) !capable(CAP_SYS_ADMIN)) return -EPERM; + bpf_prog_load_fixup_attach_type(attr); if (bpf_prog_load_check_attach_type(type, attr->expected_attach_type)) return -EINVAL; @@ -1489,6 +1526,8 @@ static int bpf_prog_attach(const union bpf_attr *attr) ptype = BPF_PROG_TYPE_CGROUP_SKB; break; case BPF_CGROUP_INET_SOCK_CREATE: + case BPF_CGROUP_INET4_POST_BIND: + case BPF_CGROUP_INET6_POST_BIND: ptype = BPF_PROG_TYPE_CGROUP_SOCK; break; case BPF_CGROUP_INET4_BIND: @@ -1557,6 +1596,8 @@ static int bpf_prog_detach(const union bpf_attr *attr) ptype = BPF_PROG_TYPE_CGROUP_SKB; break; case BPF_CGROUP_INET_SOCK_CREATE: + case BPF_CGROUP_INET4_POST_BIND: + case BPF_CGROUP_INET6_POST_BIND: ptype = BPF_PROG_TYPE_CGROUP_SOCK; break; case BPF_CGROUP_INET4_BIND: @@ -1616,6 +1657,8 @@ static int bpf_prog_query(const union bpf_attr *attr, case BPF_CGROUP_INET_SOCK_CREATE: case BPF_CGROUP_INET4_BIND: case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET4_POST_BIND: + case BPF_CGROUP_INET6_POST_BIND: case BPF_CGROUP_INET4_CONNECT: case BPF_CGROUP_INET6_CONNECT: case BPF_CGROUP_SOCK_OPS: diff --git a/net/core/filter.c b/net/core/filter.c index bdb9cadd4d27..d31aff93270d 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -4097,30 +4097,80 @@ static bool lwt_is_valid_access(int off, int size, return bpf_skb_is_valid_access(off, size, type, prog, info); } -static bool sock_filter_is_valid_access(int off, int size, - enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info) + +/* Attach type specific accesses */ +static bool __sock_filter_check_attach_type(int off, + enum bpf_access_type access_type, + enum bpf_attach_type attach_type) { - if (type == BPF_WRITE) { - switch (off) { - case offsetof(struct bpf_sock, bound_dev_if): - case offsetof(struct bpf_sock, mark): - case offsetof(struct bpf_sock, priority): - break; + switch (off) { + case offsetof(struct bpf_sock, bound_dev_if): + case offsetof(struct bpf_sock, mark): + case offsetof(struct bpf_sock, priority): + switch (attach_type) { + case BPF_CGROUP_INET_SOCK_CREATE: + goto full_access; + default: + return false; + } + case bpf_ctx_range(struct bpf_sock, src_ip4): + switch (attach_type) { + case BPF_CGROUP_INET4_POST_BIND: + goto read_only; + default: + return false; + } + case bpf_ctx_range_till(struct bpf_sock, src_ip6[0], src_ip6[3]): + switch (attach_type) { + case BPF_CGROUP_INET6_POST_BIND: + goto read_only; + default: + return false; + } + case bpf_ctx_range(struct bpf_sock, src_port): + switch (attach_type) { + case BPF_CGROUP_INET4_POST_BIND: + case BPF_CGROUP_INET6_POST_BIND: + goto read_only; default: return false; } } +read_only: + return access_type == BPF_READ; +full_access: + return true; +} + +static bool __sock_filter_check_size(int off, int size, + struct bpf_insn_access_aux *info) +{ + const int size_default = sizeof(__u32); - if (off < 0 || off + size > sizeof(struct bpf_sock)) + switch (off) { + case bpf_ctx_range(struct bpf_sock, src_ip4): + case bpf_ctx_range_till(struct bpf_sock, src_ip6[0], src_ip6[3]): + bpf_ctx_record_field_size(info, size_default); + return bpf_ctx_narrow_access_ok(off, size, size_default); + } + + return size == size_default; +} + +static bool sock_filter_is_valid_access(int off, int size, + enum bpf_access_type type, + const struct bpf_prog *prog, + struct bpf_insn_access_aux *info) +{ + if (off < 0 || off >= sizeof(struct bpf_sock)) return false; - /* The verifier guarantees that size > 0. */ if (off % size != 0) return false; - if (size != sizeof(__u32)) + if (!__sock_filter_check_attach_type(off, type, + prog->expected_attach_type)) + return false; + if (!__sock_filter_check_size(off, size, info)) return false; - return true; } @@ -4728,6 +4778,7 @@ static u32 sock_filter_convert_ctx_access(enum bpf_access_type type, struct bpf_prog *prog, u32 *target_size) { struct bpf_insn *insn = insn_buf; + int off; switch (si->off) { case offsetof(struct bpf_sock, bound_dev_if): @@ -4783,6 +4834,43 @@ static u32 sock_filter_convert_ctx_access(enum bpf_access_type type, *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_PROTO_MASK); *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, SK_FL_PROTO_SHIFT); break; + + case offsetof(struct bpf_sock, src_ip4): + *insn++ = BPF_LDX_MEM( + BPF_SIZE(si->code), si->dst_reg, si->src_reg, + bpf_target_off(struct sock_common, skc_rcv_saddr, + FIELD_SIZEOF(struct sock_common, + skc_rcv_saddr), + target_size)); + break; + + case bpf_ctx_range_till(struct bpf_sock, src_ip6[0], src_ip6[3]): +#if IS_ENABLED(CONFIG_IPV6) + off = si->off; + off -= offsetof(struct bpf_sock, src_ip6[0]); + *insn++ = BPF_LDX_MEM( + BPF_SIZE(si->code), si->dst_reg, si->src_reg, + bpf_target_off( + struct sock_common, + skc_v6_rcv_saddr.s6_addr32[0], + FIELD_SIZEOF(struct sock_common, + skc_v6_rcv_saddr.s6_addr32[0]), + target_size) + off); +#else + (void)off; + *insn++ = BPF_MOV32_IMM(si->dst_reg, 0); +#endif + break; + + case offsetof(struct bpf_sock, src_port): + *insn++ = BPF_LDX_MEM( + BPF_FIELD_SIZEOF(struct sock_common, skc_num), + si->dst_reg, si->src_reg, + bpf_target_off(struct sock_common, skc_num, + FIELD_SIZEOF(struct sock_common, + skc_num), + target_size)); + break; } return insn - insn_buf; diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 488fe26ac8e5..142d4c35b493 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -519,12 +519,18 @@ int __inet_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, inet->inet_saddr = 0; /* Use device */ /* Make sure we are allowed to bind here. */ - if ((snum || !(inet->bind_address_no_port || - force_bind_address_no_port)) && - sk->sk_prot->get_port(sk, snum)) { - inet->inet_saddr = inet->inet_rcv_saddr = 0; - err = -EADDRINUSE; - goto out_release_sock; + if (snum || !(inet->bind_address_no_port || + force_bind_address_no_port)) { + if (sk->sk_prot->get_port(sk, snum)) { + inet->inet_saddr = inet->inet_rcv_saddr = 0; + err = -EADDRINUSE; + goto out_release_sock; + } + err = BPF_CGROUP_RUN_PROG_INET4_POST_BIND(sk); + if (err) { + inet->inet_saddr = inet->inet_rcv_saddr = 0; + goto out_release_sock; + } } if (inet->inet_rcv_saddr) diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index 566cec0e0a44..41f50472679d 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -412,13 +412,20 @@ int __inet6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, sk->sk_ipv6only = 1; /* Make sure we are allowed to bind here. */ - if ((snum || !(inet->bind_address_no_port || - force_bind_address_no_port)) && - sk->sk_prot->get_port(sk, snum)) { - sk->sk_ipv6only = saved_ipv6only; - inet_reset_saddr(sk); - err = -EADDRINUSE; - goto out; + if (snum || !(inet->bind_address_no_port || + force_bind_address_no_port)) { + if (sk->sk_prot->get_port(sk, snum)) { + sk->sk_ipv6only = saved_ipv6only; + inet_reset_saddr(sk); + err = -EADDRINUSE; + goto out; + } + err = BPF_CGROUP_RUN_PROG_INET6_POST_BIND(sk); + if (err) { + sk->sk_ipv6only = saved_ipv6only; + inet_reset_saddr(sk); + goto out; + } } if (addr_type != IPV6_ADDR_ANY) -- cgit v1.2.3 From df0ce17331e2501dbffc060041dfc6c5f85227b5 Mon Sep 17 00:00:00 2001 From: Sargun Dhillon Date: Thu, 29 Mar 2018 01:28:23 +0000 Subject: security: convert security hooks to use hlist This changes security_hook_heads to use hlist_heads instead of the circular doubly-linked list heads. This should cut down the size of the struct by about half. In addition, it allows mutation of the hooks at the tail of the callback list without having to modify the head. The longer-term purpose of this is to enable making the heads read only. Signed-off-by: Sargun Dhillon Reviewed-by: Tetsuo Handa Acked-by: Casey Schaufler Signed-off-by: James Morris --- include/linux/lsm_hooks.h | 428 +++++++++++++------------- scripts/gcc-plugins/randomize_layout_plugin.c | 4 +- security/security.c | 22 +- 3 files changed, 227 insertions(+), 227 deletions(-) (limited to 'include/linux') diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index e0ac011d07a5..ac491137b10a 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -1731,230 +1731,230 @@ union security_list_options { }; struct security_hook_heads { - struct list_head binder_set_context_mgr; - struct list_head binder_transaction; - struct list_head binder_transfer_binder; - struct list_head binder_transfer_file; - struct list_head ptrace_access_check; - struct list_head ptrace_traceme; - struct list_head capget; - struct list_head capset; - struct list_head capable; - struct list_head quotactl; - struct list_head quota_on; - struct list_head syslog; - struct list_head settime; - struct list_head vm_enough_memory; - struct list_head bprm_set_creds; - struct list_head bprm_check_security; - struct list_head bprm_committing_creds; - struct list_head bprm_committed_creds; - struct list_head sb_alloc_security; - struct list_head sb_free_security; - struct list_head sb_copy_data; - struct list_head sb_remount; - struct list_head sb_kern_mount; - struct list_head sb_show_options; - struct list_head sb_statfs; - struct list_head sb_mount; - struct list_head sb_umount; - struct list_head sb_pivotroot; - struct list_head sb_set_mnt_opts; - struct list_head sb_clone_mnt_opts; - struct list_head sb_parse_opts_str; - struct list_head dentry_init_security; - struct list_head dentry_create_files_as; + struct hlist_head binder_set_context_mgr; + struct hlist_head binder_transaction; + struct hlist_head binder_transfer_binder; + struct hlist_head binder_transfer_file; + struct hlist_head ptrace_access_check; + struct hlist_head ptrace_traceme; + struct hlist_head capget; + struct hlist_head capset; + struct hlist_head capable; + struct hlist_head quotactl; + struct hlist_head quota_on; + struct hlist_head syslog; + struct hlist_head settime; + struct hlist_head vm_enough_memory; + struct hlist_head bprm_set_creds; + struct hlist_head bprm_check_security; + struct hlist_head bprm_committing_creds; + struct hlist_head bprm_committed_creds; + struct hlist_head sb_alloc_security; + struct hlist_head sb_free_security; + struct hlist_head sb_copy_data; + struct hlist_head sb_remount; + struct hlist_head sb_kern_mount; + struct hlist_head sb_show_options; + struct hlist_head sb_statfs; + struct hlist_head sb_mount; + struct hlist_head sb_umount; + struct hlist_head sb_pivotroot; + struct hlist_head sb_set_mnt_opts; + struct hlist_head sb_clone_mnt_opts; + struct hlist_head sb_parse_opts_str; + struct hlist_head dentry_init_security; + struct hlist_head dentry_create_files_as; #ifdef CONFIG_SECURITY_PATH - struct list_head path_unlink; - struct list_head path_mkdir; - struct list_head path_rmdir; - struct list_head path_mknod; - struct list_head path_truncate; - struct list_head path_symlink; - struct list_head path_link; - struct list_head path_rename; - struct list_head path_chmod; - struct list_head path_chown; - struct list_head path_chroot; + struct hlist_head path_unlink; + struct hlist_head path_mkdir; + struct hlist_head path_rmdir; + struct hlist_head path_mknod; + struct hlist_head path_truncate; + struct hlist_head path_symlink; + struct hlist_head path_link; + struct hlist_head path_rename; + struct hlist_head path_chmod; + struct hlist_head path_chown; + struct hlist_head path_chroot; #endif - struct list_head inode_alloc_security; - struct list_head inode_free_security; - struct list_head inode_init_security; - struct list_head inode_create; - struct list_head inode_link; - struct list_head inode_unlink; - struct list_head inode_symlink; - struct list_head inode_mkdir; - struct list_head inode_rmdir; - struct list_head inode_mknod; - struct list_head inode_rename; - struct list_head inode_readlink; - struct list_head inode_follow_link; - struct list_head inode_permission; - struct list_head inode_setattr; - struct list_head inode_getattr; - struct list_head inode_setxattr; - struct list_head inode_post_setxattr; - struct list_head inode_getxattr; - struct list_head inode_listxattr; - struct list_head inode_removexattr; - struct list_head inode_need_killpriv; - struct list_head inode_killpriv; - struct list_head inode_getsecurity; - struct list_head inode_setsecurity; - struct list_head inode_listsecurity; - struct list_head inode_getsecid; - struct list_head inode_copy_up; - struct list_head inode_copy_up_xattr; - struct list_head file_permission; - struct list_head file_alloc_security; - struct list_head file_free_security; - struct list_head file_ioctl; - struct list_head mmap_addr; - struct list_head mmap_file; - struct list_head file_mprotect; - struct list_head file_lock; - struct list_head file_fcntl; - struct list_head file_set_fowner; - struct list_head file_send_sigiotask; - struct list_head file_receive; - struct list_head file_open; - struct list_head task_alloc; - struct list_head task_free; - struct list_head cred_alloc_blank; - struct list_head cred_free; - struct list_head cred_prepare; - struct list_head cred_transfer; - struct list_head kernel_act_as; - struct list_head kernel_create_files_as; - struct list_head kernel_read_file; - struct list_head kernel_post_read_file; - struct list_head kernel_module_request; - struct list_head task_fix_setuid; - struct list_head task_setpgid; - struct list_head task_getpgid; - struct list_head task_getsid; - struct list_head task_getsecid; - struct list_head task_setnice; - struct list_head task_setioprio; - struct list_head task_getioprio; - struct list_head task_prlimit; - struct list_head task_setrlimit; - struct list_head task_setscheduler; - struct list_head task_getscheduler; - struct list_head task_movememory; - struct list_head task_kill; - struct list_head task_prctl; - struct list_head task_to_inode; - struct list_head ipc_permission; - struct list_head ipc_getsecid; - struct list_head msg_msg_alloc_security; - struct list_head msg_msg_free_security; - struct list_head msg_queue_alloc_security; - struct list_head msg_queue_free_security; - struct list_head msg_queue_associate; - struct list_head msg_queue_msgctl; - struct list_head msg_queue_msgsnd; - struct list_head msg_queue_msgrcv; - struct list_head shm_alloc_security; - struct list_head shm_free_security; - struct list_head shm_associate; - struct list_head shm_shmctl; - struct list_head shm_shmat; - struct list_head sem_alloc_security; - struct list_head sem_free_security; - struct list_head sem_associate; - struct list_head sem_semctl; - struct list_head sem_semop; - struct list_head netlink_send; - struct list_head d_instantiate; - struct list_head getprocattr; - struct list_head setprocattr; - struct list_head ismaclabel; - struct list_head secid_to_secctx; - struct list_head secctx_to_secid; - struct list_head release_secctx; - struct list_head inode_invalidate_secctx; - struct list_head inode_notifysecctx; - struct list_head inode_setsecctx; - struct list_head inode_getsecctx; + struct hlist_head inode_alloc_security; + struct hlist_head inode_free_security; + struct hlist_head inode_init_security; + struct hlist_head inode_create; + struct hlist_head inode_link; + struct hlist_head inode_unlink; + struct hlist_head inode_symlink; + struct hlist_head inode_mkdir; + struct hlist_head inode_rmdir; + struct hlist_head inode_mknod; + struct hlist_head inode_rename; + struct hlist_head inode_readlink; + struct hlist_head inode_follow_link; + struct hlist_head inode_permission; + struct hlist_head inode_setattr; + struct hlist_head inode_getattr; + struct hlist_head inode_setxattr; + struct hlist_head inode_post_setxattr; + struct hlist_head inode_getxattr; + struct hlist_head inode_listxattr; + struct hlist_head inode_removexattr; + struct hlist_head inode_need_killpriv; + struct hlist_head inode_killpriv; + struct hlist_head inode_getsecurity; + struct hlist_head inode_setsecurity; + struct hlist_head inode_listsecurity; + struct hlist_head inode_getsecid; + struct hlist_head inode_copy_up; + struct hlist_head inode_copy_up_xattr; + struct hlist_head file_permission; + struct hlist_head file_alloc_security; + struct hlist_head file_free_security; + struct hlist_head file_ioctl; + struct hlist_head mmap_addr; + struct hlist_head mmap_file; + struct hlist_head file_mprotect; + struct hlist_head file_lock; + struct hlist_head file_fcntl; + struct hlist_head file_set_fowner; + struct hlist_head file_send_sigiotask; + struct hlist_head file_receive; + struct hlist_head file_open; + struct hlist_head task_alloc; + struct hlist_head task_free; + struct hlist_head cred_alloc_blank; + struct hlist_head cred_free; + struct hlist_head cred_prepare; + struct hlist_head cred_transfer; + struct hlist_head kernel_act_as; + struct hlist_head kernel_create_files_as; + struct hlist_head kernel_read_file; + struct hlist_head kernel_post_read_file; + struct hlist_head kernel_module_request; + struct hlist_head task_fix_setuid; + struct hlist_head task_setpgid; + struct hlist_head task_getpgid; + struct hlist_head task_getsid; + struct hlist_head task_getsecid; + struct hlist_head task_setnice; + struct hlist_head task_setioprio; + struct hlist_head task_getioprio; + struct hlist_head task_prlimit; + struct hlist_head task_setrlimit; + struct hlist_head task_setscheduler; + struct hlist_head task_getscheduler; + struct hlist_head task_movememory; + struct hlist_head task_kill; + struct hlist_head task_prctl; + struct hlist_head task_to_inode; + struct hlist_head ipc_permission; + struct hlist_head ipc_getsecid; + struct hlist_head msg_msg_alloc_security; + struct hlist_head msg_msg_free_security; + struct hlist_head msg_queue_alloc_security; + struct hlist_head msg_queue_free_security; + struct hlist_head msg_queue_associate; + struct hlist_head msg_queue_msgctl; + struct hlist_head msg_queue_msgsnd; + struct hlist_head msg_queue_msgrcv; + struct hlist_head shm_alloc_security; + struct hlist_head shm_free_security; + struct hlist_head shm_associate; + struct hlist_head shm_shmctl; + struct hlist_head shm_shmat; + struct hlist_head sem_alloc_security; + struct hlist_head sem_free_security; + struct hlist_head sem_associate; + struct hlist_head sem_semctl; + struct hlist_head sem_semop; + struct hlist_head netlink_send; + struct hlist_head d_instantiate; + struct hlist_head getprocattr; + struct hlist_head setprocattr; + struct hlist_head ismaclabel; + struct hlist_head secid_to_secctx; + struct hlist_head secctx_to_secid; + struct hlist_head release_secctx; + struct hlist_head inode_invalidate_secctx; + struct hlist_head inode_notifysecctx; + struct hlist_head inode_setsecctx; + struct hlist_head inode_getsecctx; #ifdef CONFIG_SECURITY_NETWORK - struct list_head unix_stream_connect; - struct list_head unix_may_send; - struct list_head socket_create; - struct list_head socket_post_create; - struct list_head socket_bind; - struct list_head socket_connect; - struct list_head socket_listen; - struct list_head socket_accept; - struct list_head socket_sendmsg; - struct list_head socket_recvmsg; - struct list_head socket_getsockname; - struct list_head socket_getpeername; - struct list_head socket_getsockopt; - struct list_head socket_setsockopt; - struct list_head socket_shutdown; - struct list_head socket_sock_rcv_skb; - struct list_head socket_getpeersec_stream; - struct list_head socket_getpeersec_dgram; - struct list_head sk_alloc_security; - struct list_head sk_free_security; - struct list_head sk_clone_security; - struct list_head sk_getsecid; - struct list_head sock_graft; - struct list_head inet_conn_request; - struct list_head inet_csk_clone; - struct list_head inet_conn_established; - struct list_head secmark_relabel_packet; - struct list_head secmark_refcount_inc; - struct list_head secmark_refcount_dec; - struct list_head req_classify_flow; - struct list_head tun_dev_alloc_security; - struct list_head tun_dev_free_security; - struct list_head tun_dev_create; - struct list_head tun_dev_attach_queue; - struct list_head tun_dev_attach; - struct list_head tun_dev_open; + struct hlist_head unix_stream_connect; + struct hlist_head unix_may_send; + struct hlist_head socket_create; + struct hlist_head socket_post_create; + struct hlist_head socket_bind; + struct hlist_head socket_connect; + struct hlist_head socket_listen; + struct hlist_head socket_accept; + struct hlist_head socket_sendmsg; + struct hlist_head socket_recvmsg; + struct hlist_head socket_getsockname; + struct hlist_head socket_getpeername; + struct hlist_head socket_getsockopt; + struct hlist_head socket_setsockopt; + struct hlist_head socket_shutdown; + struct hlist_head socket_sock_rcv_skb; + struct hlist_head socket_getpeersec_stream; + struct hlist_head socket_getpeersec_dgram; + struct hlist_head sk_alloc_security; + struct hlist_head sk_free_security; + struct hlist_head sk_clone_security; + struct hlist_head sk_getsecid; + struct hlist_head sock_graft; + struct hlist_head inet_conn_request; + struct hlist_head inet_csk_clone; + struct hlist_head inet_conn_established; + struct hlist_head secmark_relabel_packet; + struct hlist_head secmark_refcount_inc; + struct hlist_head secmark_refcount_dec; + struct hlist_head req_classify_flow; + struct hlist_head tun_dev_alloc_security; + struct hlist_head tun_dev_free_security; + struct hlist_head tun_dev_create; + struct hlist_head tun_dev_attach_queue; + struct hlist_head tun_dev_attach; + struct hlist_head tun_dev_open; #endif /* CONFIG_SECURITY_NETWORK */ #ifdef CONFIG_SECURITY_INFINIBAND - struct list_head ib_pkey_access; - struct list_head ib_endport_manage_subnet; - struct list_head ib_alloc_security; - struct list_head ib_free_security; + struct hlist_head ib_pkey_access; + struct hlist_head ib_endport_manage_subnet; + struct hlist_head ib_alloc_security; + struct hlist_head ib_free_security; #endif /* CONFIG_SECURITY_INFINIBAND */ #ifdef CONFIG_SECURITY_NETWORK_XFRM - struct list_head xfrm_policy_alloc_security; - struct list_head xfrm_policy_clone_security; - struct list_head xfrm_policy_free_security; - struct list_head xfrm_policy_delete_security; - struct list_head xfrm_state_alloc; - struct list_head xfrm_state_alloc_acquire; - struct list_head xfrm_state_free_security; - struct list_head xfrm_state_delete_security; - struct list_head xfrm_policy_lookup; - struct list_head xfrm_state_pol_flow_match; - struct list_head xfrm_decode_session; + struct hlist_head xfrm_policy_alloc_security; + struct hlist_head xfrm_policy_clone_security; + struct hlist_head xfrm_policy_free_security; + struct hlist_head xfrm_policy_delete_security; + struct hlist_head xfrm_state_alloc; + struct hlist_head xfrm_state_alloc_acquire; + struct hlist_head xfrm_state_free_security; + struct hlist_head xfrm_state_delete_security; + struct hlist_head xfrm_policy_lookup; + struct hlist_head xfrm_state_pol_flow_match; + struct hlist_head xfrm_decode_session; #endif /* CONFIG_SECURITY_NETWORK_XFRM */ #ifdef CONFIG_KEYS - struct list_head key_alloc; - struct list_head key_free; - struct list_head key_permission; - struct list_head key_getsecurity; + struct hlist_head key_alloc; + struct hlist_head key_free; + struct hlist_head key_permission; + struct hlist_head key_getsecurity; #endif /* CONFIG_KEYS */ #ifdef CONFIG_AUDIT - struct list_head audit_rule_init; - struct list_head audit_rule_known; - struct list_head audit_rule_match; - struct list_head audit_rule_free; + struct hlist_head audit_rule_init; + struct hlist_head audit_rule_known; + struct hlist_head audit_rule_match; + struct hlist_head audit_rule_free; #endif /* CONFIG_AUDIT */ #ifdef CONFIG_BPF_SYSCALL - struct list_head bpf; - struct list_head bpf_map; - struct list_head bpf_prog; - struct list_head bpf_map_alloc_security; - struct list_head bpf_map_free_security; - struct list_head bpf_prog_alloc_security; - struct list_head bpf_prog_free_security; + struct hlist_head bpf; + struct hlist_head bpf_map; + struct hlist_head bpf_prog; + struct hlist_head bpf_map_alloc_security; + struct hlist_head bpf_map_free_security; + struct hlist_head bpf_prog_alloc_security; + struct hlist_head bpf_prog_free_security; #endif /* CONFIG_BPF_SYSCALL */ } __randomize_layout; @@ -1963,8 +1963,8 @@ struct security_hook_heads { * For use with generic list macros for common operations. */ struct security_hook_list { - struct list_head list; - struct list_head *head; + struct hlist_node list; + struct hlist_head *head; union security_list_options hook; char *lsm; } __randomize_layout; @@ -2003,7 +2003,7 @@ static inline void security_delete_hooks(struct security_hook_list *hooks, int i; for (i = 0; i < count; i++) - list_del_rcu(&hooks[i].list); + hlist_del_rcu(&hooks[i].list); } #endif /* CONFIG_SECURITY_SELINUX_DISABLE */ diff --git a/scripts/gcc-plugins/randomize_layout_plugin.c b/scripts/gcc-plugins/randomize_layout_plugin.c index c4a345c3715b..6d5bbd31db7f 100644 --- a/scripts/gcc-plugins/randomize_layout_plugin.c +++ b/scripts/gcc-plugins/randomize_layout_plugin.c @@ -52,8 +52,8 @@ static const struct whitelist_entry whitelist[] = { { "net/unix/af_unix.c", "unix_skb_parms", "char" }, /* big_key payload.data struct splashing */ { "security/keys/big_key.c", "path", "void *" }, - /* walk struct security_hook_heads as an array of struct list_head */ - { "security/security.c", "list_head", "security_hook_heads" }, + /* walk struct security_hook_heads as an array of struct hlist_head */ + { "security/security.c", "hlist_head", "security_hook_heads" }, { } }; diff --git a/security/security.c b/security/security.c index 14c291910d25..dd246a38b3f0 100644 --- a/security/security.c +++ b/security/security.c @@ -61,11 +61,11 @@ static void __init do_security_initcalls(void) int __init security_init(void) { int i; - struct list_head *list = (struct list_head *) &security_hook_heads; + struct hlist_head *list = (struct hlist_head *) &security_hook_heads; - for (i = 0; i < sizeof(security_hook_heads) / sizeof(struct list_head); + for (i = 0; i < sizeof(security_hook_heads) / sizeof(struct hlist_head); i++) - INIT_LIST_HEAD(&list[i]); + INIT_HLIST_HEAD(&list[i]); pr_info("Security Framework initialized\n"); /* @@ -163,7 +163,7 @@ void __init security_add_hooks(struct security_hook_list *hooks, int count, for (i = 0; i < count; i++) { hooks[i].lsm = lsm; - list_add_tail_rcu(&hooks[i].list, hooks[i].head); + hlist_add_tail_rcu(&hooks[i].list, hooks[i].head); } if (lsm_append(lsm, &lsm_names) < 0) panic("%s - Cannot get early memory.\n", __func__); @@ -201,7 +201,7 @@ EXPORT_SYMBOL(unregister_lsm_notifier); do { \ struct security_hook_list *P; \ \ - list_for_each_entry(P, &security_hook_heads.FUNC, list) \ + hlist_for_each_entry(P, &security_hook_heads.FUNC, list) \ P->hook.FUNC(__VA_ARGS__); \ } while (0) @@ -210,7 +210,7 @@ EXPORT_SYMBOL(unregister_lsm_notifier); do { \ struct security_hook_list *P; \ \ - list_for_each_entry(P, &security_hook_heads.FUNC, list) { \ + hlist_for_each_entry(P, &security_hook_heads.FUNC, list) { \ RC = P->hook.FUNC(__VA_ARGS__); \ if (RC != 0) \ break; \ @@ -317,7 +317,7 @@ int security_vm_enough_memory_mm(struct mm_struct *mm, long pages) * agree that it should be set it will. If any module * thinks it should not be set it won't. */ - list_for_each_entry(hp, &security_hook_heads.vm_enough_memory, list) { + hlist_for_each_entry(hp, &security_hook_heads.vm_enough_memory, list) { rc = hp->hook.vm_enough_memory(mm, pages); if (rc <= 0) { cap_sys_admin = 0; @@ -805,7 +805,7 @@ int security_inode_getsecurity(struct inode *inode, const char *name, void **buf /* * Only one module will provide an attribute with a given name. */ - list_for_each_entry(hp, &security_hook_heads.inode_getsecurity, list) { + hlist_for_each_entry(hp, &security_hook_heads.inode_getsecurity, list) { rc = hp->hook.inode_getsecurity(inode, name, buffer, alloc); if (rc != -EOPNOTSUPP) return rc; @@ -823,7 +823,7 @@ int security_inode_setsecurity(struct inode *inode, const char *name, const void /* * Only one module will provide an attribute with a given name. */ - list_for_each_entry(hp, &security_hook_heads.inode_setsecurity, list) { + hlist_for_each_entry(hp, &security_hook_heads.inode_setsecurity, list) { rc = hp->hook.inode_setsecurity(inode, name, value, size, flags); if (rc != -EOPNOTSUPP) @@ -1126,7 +1126,7 @@ int security_task_prctl(int option, unsigned long arg2, unsigned long arg3, int rc = -ENOSYS; struct security_hook_list *hp; - list_for_each_entry(hp, &security_hook_heads.task_prctl, list) { + hlist_for_each_entry(hp, &security_hook_heads.task_prctl, list) { thisrc = hp->hook.task_prctl(option, arg2, arg3, arg4, arg5); if (thisrc != -ENOSYS) { rc = thisrc; @@ -1629,7 +1629,7 @@ int security_xfrm_state_pol_flow_match(struct xfrm_state *x, * For speed optimization, we explicitly break the loop rather than * using the macro */ - list_for_each_entry(hp, &security_hook_heads.xfrm_state_pol_flow_match, + hlist_for_each_entry(hp, &security_hook_heads.xfrm_state_pol_flow_match, list) { rc = hp->hook.xfrm_state_pol_flow_match(x, xp, fl); break; -- cgit v1.2.3 From a95b37e20db9a2b05354eec009b2188523a21c8e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 27 Mar 2018 21:52:50 +0900 Subject: kbuild: get out of Since commit 28128c61e08e ("kconfig.h: Include compiler types to avoid missed struct attributes"), pulls in kernel-space headers to unrelated places. Commit 0f9da844d877 ("MIPS: boot: Define __ASSEMBLY__ for its.S build") suppress the build error by defining __ASSEMBLY__, but ITS (i.e. DTS) is not assembly, and should not include in the first place. Looking at arch/s390/tools/Makefile, host programs gen_facilities and gen_opcode_table now pull in as well. The motivation for that commit was to define necessary attributes before any struct is defined. Obviously, this happens only in C. It is enough to include only when compiling C files, and only when compiling kernel space. Move the include to c_flags. Signed-off-by: Masahiro Yamada --- include/linux/kconfig.h | 3 --- scripts/Makefile.lib | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h index dcde9471897d..cc8fa109cfa3 100644 --- a/include/linux/kconfig.h +++ b/include/linux/kconfig.h @@ -70,7 +70,4 @@ */ #define IS_ENABLED(option) __or(IS_BUILTIN(option), IS_MODULE(option)) -/* Make sure we always have all types and struct attributes defined. */ -#include - #endif /* __LINUX_KCONFIG_H */ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 194ae707167d..e3215b7652ee 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -152,6 +152,7 @@ __cpp_flags = $(call flags,_cpp_flags) endif c_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \ + -include $(srctree)/include/linux/compiler_types.h \ $(__c_flags) $(modkern_cflags) \ $(basename_flags) $(modname_flags) -- cgit v1.2.3 From 619e6f340cec7c5d1449a2951dae5af0990bd0f5 Mon Sep 17 00:00:00 2001 From: Mathieu Malaterre Date: Fri, 30 Mar 2018 17:39:31 -0500 Subject: PCI/IOV: Add missing prototypes for powerpc pcibios interfaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing prototypes for: resource_size_t pcibios_default_alignment(void); int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); int pcibios_sriov_disable(struct pci_dev *pdev); This fixes the following warnings treated as errors when using W=1: arch/powerpc/kernel/pci-common.c:236:17: error: no previous prototype for ‘pcibios_default_alignment’ [-Werror=missing-prototypes] arch/powerpc/kernel/pci-common.c:253:5: error: no previous prototype for ‘pcibios_sriov_enable’ [-Werror=missing-prototypes] arch/powerpc/kernel/pci-common.c:261:5: error: no previous prototype for ‘pcibios_sriov_disable’ [-Werror=missing-prototypes] Also, commit 978d2d683123 ("PCI: Add pcibios_iov_resource_alignment() interface") added a new function but the prototype was located in the main header instead of the CONFIG_PCI_IOV specific section. Move this function next to the newly added ones. Signed-off-by: Mathieu Malaterre Signed-off-by: Bjorn Helgaas --- include/linux/pci.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/pci.h b/include/linux/pci.h index 562875d34b98..df17288fc1f6 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1295,7 +1295,6 @@ unsigned char pci_bus_max_busnr(struct pci_bus *bus); void pci_setup_bridge(struct pci_bus *bus); resource_size_t pcibios_window_alignment(struct pci_bus *bus, unsigned long type); -resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) @@ -1923,6 +1922,7 @@ void pcibios_release_device(struct pci_dev *dev); void pcibios_penalize_isa_irq(int irq, int active); int pcibios_alloc_irq(struct pci_dev *dev); void pcibios_free_irq(struct pci_dev *dev); +resource_size_t pcibios_default_alignment(void); #ifdef CONFIG_HIBERNATE_CALLBACKS extern struct dev_pm_ops pcibios_pm_ops; @@ -1955,6 +1955,11 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); int pci_sriov_get_totalvfs(struct pci_dev *dev); resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); + +/* Arch may override these (weak) */ +int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); +int pcibios_sriov_disable(struct pci_dev *pdev); +resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); #else static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) { -- cgit v1.2.3 From e5d672a0780d9e7118caad4c171ec88b8299398d Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Sat, 31 Mar 2018 12:58:56 -0700 Subject: rhashtable: reorganize struct rhashtable layout While under frags DDOS I noticed unfortunate false sharing between @nelems and @params.automatic_shrinking Move @nelems at the end of struct rhashtable so that first cache line is shared between all cpus, because almost never dirtied. Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller --- include/linux/rhashtable.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/rhashtable.h b/include/linux/rhashtable.h index 668a21f04b09..1f8ad121eb43 100644 --- a/include/linux/rhashtable.h +++ b/include/linux/rhashtable.h @@ -152,25 +152,25 @@ struct rhashtable_params { /** * struct rhashtable - Hash table handle * @tbl: Bucket table - * @nelems: Number of elements in table * @key_len: Key length for hashfn - * @p: Configuration parameters * @max_elems: Maximum number of elements in table + * @p: Configuration parameters * @rhlist: True if this is an rhltable * @run_work: Deferred worker to expand/shrink asynchronously * @mutex: Mutex to protect current/future table swapping * @lock: Spin lock to protect walker list + * @nelems: Number of elements in table */ struct rhashtable { struct bucket_table __rcu *tbl; - atomic_t nelems; unsigned int key_len; - struct rhashtable_params p; unsigned int max_elems; + struct rhashtable_params p; bool rhlist; struct work_struct run_work; struct mutex mutex; spinlock_t lock; + atomic_t nelems; }; /** -- cgit v1.2.3 From bf66337140c64c27fa37222b7abca7e49d63fb57 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Sat, 31 Mar 2018 12:58:58 -0700 Subject: inet: frags: get rid of ipfrag_skb_cb/FRAG_CB ip_defrag uses skb->cb[] to store the fragment offset, and unfortunately this integer is currently in a different cache line than skb->next, meaning that we use two cache lines per skb when finding the insertion point. By aliasing skb->ip_defrag_offset and skb->dev, we pack all the fields in a single cache line and save precious memory bandwidth. Note that after the fast path added by Changli Gao in commit d6bebca92c66 ("fragment: add fast path for in-order fragments") this change wont help the fast path, since we still need to access prev->len (2nd cache line), but will show great benefits when slow path is entered, since we perform a linear scan of a potentially long list. Also, note that this potential long list is an attack vector, we might consider also using an rb-tree there eventually. Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller --- include/linux/skbuff.h | 1 + net/ipv4/ip_fragment.c | 35 ++++++++++++++--------------------- 2 files changed, 15 insertions(+), 21 deletions(-) (limited to 'include/linux') diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 47082f54ec1f..9065477ed255 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -672,6 +672,7 @@ struct sk_buff { * UDP receive path is one user. */ unsigned long dev_scratch; + int ip_defrag_offset; }; }; struct rb_node rbnode; /* used in netem & tcp stack */ diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c index fb185d9a5cc7..994fa70a910f 100644 --- a/net/ipv4/ip_fragment.c +++ b/net/ipv4/ip_fragment.c @@ -57,14 +57,6 @@ */ static const char ip_frag_cache_name[] = "ip4-frags"; -struct ipfrag_skb_cb -{ - struct inet_skb_parm h; - int offset; -}; - -#define FRAG_CB(skb) ((struct ipfrag_skb_cb *)((skb)->cb)) - /* Describe an entry in the "incomplete datagrams" queue. */ struct ipq { struct inet_frag_queue q; @@ -353,13 +345,13 @@ static int ip_frag_queue(struct ipq *qp, struct sk_buff *skb) * this fragment, right? */ prev = qp->q.fragments_tail; - if (!prev || FRAG_CB(prev)->offset < offset) { + if (!prev || prev->ip_defrag_offset < offset) { next = NULL; goto found; } prev = NULL; for (next = qp->q.fragments; next != NULL; next = next->next) { - if (FRAG_CB(next)->offset >= offset) + if (next->ip_defrag_offset >= offset) break; /* bingo! */ prev = next; } @@ -370,7 +362,7 @@ found: * any overlaps are eliminated. */ if (prev) { - int i = (FRAG_CB(prev)->offset + prev->len) - offset; + int i = (prev->ip_defrag_offset + prev->len) - offset; if (i > 0) { offset += i; @@ -387,8 +379,8 @@ found: err = -ENOMEM; - while (next && FRAG_CB(next)->offset < end) { - int i = end - FRAG_CB(next)->offset; /* overlap is 'i' bytes */ + while (next && next->ip_defrag_offset < end) { + int i = end - next->ip_defrag_offset; /* overlap is 'i' bytes */ if (i < next->len) { /* Eat head of the next overlapped fragment @@ -396,7 +388,7 @@ found: */ if (!pskb_pull(next, i)) goto err; - FRAG_CB(next)->offset += i; + next->ip_defrag_offset += i; qp->q.meat -= i; if (next->ip_summed != CHECKSUM_UNNECESSARY) next->ip_summed = CHECKSUM_NONE; @@ -420,7 +412,13 @@ found: } } - FRAG_CB(skb)->offset = offset; + /* Note : skb->ip_defrag_offset and skb->dev share the same location */ + dev = skb->dev; + if (dev) + qp->iif = dev->ifindex; + /* Makes sure compiler wont do silly aliasing games */ + barrier(); + skb->ip_defrag_offset = offset; /* Insert this fragment in the chain of fragments. */ skb->next = next; @@ -431,11 +429,6 @@ found: else qp->q.fragments = skb; - dev = skb->dev; - if (dev) { - qp->iif = dev->ifindex; - skb->dev = NULL; - } qp->q.stamp = skb->tstamp; qp->q.meat += skb->len; qp->ecn |= ecn; @@ -511,7 +504,7 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, } WARN_ON(!head); - WARN_ON(FRAG_CB(head)->offset != 0); + WARN_ON(head->ip_defrag_offset != 0); /* Allocate a new buffer for the datagram. */ ihlen = ip_hdrlen(head); -- cgit v1.2.3 From e0be6bea2583486ec4ed98e36437d82ea8190811 Mon Sep 17 00:00:00 2001 From: Atul Gupta Date: Sat, 31 Mar 2018 21:41:53 +0530 Subject: ethtool: enable Inline TLS in HW Ethtool option enables TLS record offload on HW, user configures the feature for netdev capable of Inline TLS. This allows user to define custom sk_prot for Inline TLS sock Signed-off-by: Atul Gupta Signed-off-by: David S. Miller --- include/linux/netdev_features.h | 2 ++ net/core/ethtool.c | 1 + 2 files changed, 3 insertions(+) (limited to 'include/linux') diff --git a/include/linux/netdev_features.h b/include/linux/netdev_features.h index db84c516bcfb..35b79f47a13d 100644 --- a/include/linux/netdev_features.h +++ b/include/linux/netdev_features.h @@ -79,6 +79,7 @@ enum { NETIF_F_RX_UDP_TUNNEL_PORT_BIT, /* Offload of RX port for UDP tunnels */ NETIF_F_GRO_HW_BIT, /* Hardware Generic receive offload */ + NETIF_F_HW_TLS_RECORD_BIT, /* Offload TLS record */ /* * Add your fresh new feature above and remember to update @@ -145,6 +146,7 @@ enum { #define NETIF_F_HW_ESP __NETIF_F(HW_ESP) #define NETIF_F_HW_ESP_TX_CSUM __NETIF_F(HW_ESP_TX_CSUM) #define NETIF_F_RX_UDP_TUNNEL_PORT __NETIF_F(RX_UDP_TUNNEL_PORT) +#define NETIF_F_HW_TLS_RECORD __NETIF_F(HW_TLS_RECORD) #define for_each_netdev_feature(mask_addr, bit) \ for_each_set_bit(bit, (unsigned long *)mask_addr, NETDEV_FEATURE_COUNT) diff --git a/net/core/ethtool.c b/net/core/ethtool.c index eb55252ca1fb..03416e6dd5d7 100644 --- a/net/core/ethtool.c +++ b/net/core/ethtool.c @@ -108,6 +108,7 @@ static const char netdev_features_strings[NETDEV_FEATURE_COUNT][ETH_GSTRING_LEN] [NETIF_F_HW_ESP_BIT] = "esp-hw-offload", [NETIF_F_HW_ESP_TX_CSUM_BIT] = "esp-tx-csum-hw-offload", [NETIF_F_RX_UDP_TUNNEL_PORT_BIT] = "rx-udp_tunnel-port-offload", + [NETIF_F_HW_TLS_RECORD_BIT] = "tls-hw-record", }; static const char -- cgit v1.2.3 From dccbf08005df800f5c8e948ab6132ed5536134bc Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Sat, 17 Feb 2018 09:29:58 +0100 Subject: libceph, ceph: change ceph_calc_file_object_mapping() signature - make it void - xlen (object extent length) out parameter should be u32 because only a single stripe unit is mapped at a time Signed-off-by: Ilya Dryomov Reviewed-by: Alex Elder --- fs/ceph/addr.c | 16 ++++++---------- fs/ceph/ioctl.c | 11 +++-------- include/linux/ceph/osdmap.h | 7 +++---- net/ceph/osd_client.c | 10 ++++------ net/ceph/osdmap.c | 6 ++---- 5 files changed, 18 insertions(+), 32 deletions(-) (limited to 'include/linux') diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c index b4336b42ce3b..c0fe1b6f47ac 100644 --- a/fs/ceph/addr.c +++ b/fs/ceph/addr.c @@ -945,19 +945,15 @@ get_more_pages: if (locked_pages == 0) { u64 objnum; u64 objoff; + u32 xlen; /* prepare async write request */ offset = (u64)page_offset(page); - len = wsize; - - rc = ceph_calc_file_object_mapping(&ci->i_layout, - offset, len, - &objnum, &objoff, - &len); - if (rc < 0) { - unlock_page(page); - break; - } + ceph_calc_file_object_mapping(&ci->i_layout, + offset, wsize, + &objnum, &objoff, + &xlen); + len = xlen; num_ops = 1; strip_unit_end = page->index + diff --git a/fs/ceph/ioctl.c b/fs/ceph/ioctl.c index 851aa69ec8f0..b855d24a895a 100644 --- a/fs/ceph/ioctl.c +++ b/fs/ceph/ioctl.c @@ -185,7 +185,7 @@ static long ceph_ioctl_get_dataloc(struct file *file, void __user *arg) &ceph_sb_to_client(inode->i_sb)->client->osdc; struct ceph_object_locator oloc; CEPH_DEFINE_OID_ONSTACK(oid); - u64 len = 1, olen; + u32 xlen; u64 tmp; struct ceph_pg pgid; int r; @@ -195,13 +195,8 @@ static long ceph_ioctl_get_dataloc(struct file *file, void __user *arg) return -EFAULT; down_read(&osdc->lock); - r = ceph_calc_file_object_mapping(&ci->i_layout, dl.file_offset, len, - &dl.object_no, &dl.object_offset, - &olen); - if (r < 0) { - up_read(&osdc->lock); - return -EIO; - } + ceph_calc_file_object_mapping(&ci->i_layout, dl.file_offset, 1, + &dl.object_no, &dl.object_offset, &xlen); dl.file_offset -= dl.object_offset; dl.object_size = ci->i_layout.object_size; dl.block_size = ci->i_layout.stripe_unit; diff --git a/include/linux/ceph/osdmap.h b/include/linux/ceph/osdmap.h index d41fad99c0fa..92314035dac1 100644 --- a/include/linux/ceph/osdmap.h +++ b/include/linux/ceph/osdmap.h @@ -280,10 +280,9 @@ bool ceph_osds_changed(const struct ceph_osds *old_acting, const struct ceph_osds *new_acting, bool any_change); -/* calculate mapping of a file extent to an object */ -extern int ceph_calc_file_object_mapping(struct ceph_file_layout *layout, - u64 off, u64 len, - u64 *bno, u64 *oxoff, u64 *oxlen); +void ceph_calc_file_object_mapping(struct ceph_file_layout *l, + u64 off, u64 len, + u64 *objno, u64 *objoff, u32 *xlen); int __ceph_object_locator_to_pg(struct ceph_pg_pool_info *pi, const struct ceph_object_id *oid, diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c index 2814dba5902d..4b0485458d26 100644 --- a/net/ceph/osd_client.c +++ b/net/ceph/osd_client.c @@ -103,13 +103,12 @@ static int calc_layout(struct ceph_file_layout *layout, u64 off, u64 *plen, u64 *objnum, u64 *objoff, u64 *objlen) { u64 orig_len = *plen; - int r; + u32 xlen; /* object extent? */ - r = ceph_calc_file_object_mapping(layout, off, orig_len, objnum, - objoff, objlen); - if (r < 0) - return r; + ceph_calc_file_object_mapping(layout, off, orig_len, objnum, + objoff, &xlen); + *objlen = xlen; if (*objlen < orig_len) { *plen = *objlen; dout(" skipping last %llu, final file extent %llu~%llu\n", @@ -117,7 +116,6 @@ static int calc_layout(struct ceph_file_layout *layout, u64 off, u64 *plen, } dout("calc_layout objnum=%llx %llu~%llu\n", *objnum, *objoff, *objlen); - return 0; } diff --git a/net/ceph/osdmap.c b/net/ceph/osdmap.c index 3faa9e701518..e3ebbe2ecdad 100644 --- a/net/ceph/osdmap.c +++ b/net/ceph/osdmap.c @@ -2153,9 +2153,9 @@ bool ceph_osds_changed(const struct ceph_osds *old_acting, * objno | 0 | 1 | 2 | 3 | 4 * objsetno | 0 | 1 */ -int ceph_calc_file_object_mapping(struct ceph_file_layout *l, +void ceph_calc_file_object_mapping(struct ceph_file_layout *l, u64 off, u64 len, - u64 *objno, u64 *objoff, u64 *xlen) + u64 *objno, u64 *objoff, u32 *xlen) { u32 stripes_per_object = l->object_size / l->stripe_unit; u64 blockno; /* which su in the file (i.e. globally) */ @@ -2173,8 +2173,6 @@ int ceph_calc_file_object_mapping(struct ceph_file_layout *l, *objno = objsetno * l->stripe_count + stripepos; *objoff = objsetpos * l->stripe_unit + blockoff; *xlen = min_t(u64, len, l->stripe_unit - blockoff); - - return 0; } EXPORT_SYMBOL(ceph_calc_file_object_mapping); -- cgit v1.2.3 From 5359a17d2706b86da2af83027343d5eb256f7670 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Sat, 20 Jan 2018 10:30:10 +0100 Subject: libceph, rbd: new bio handling code (aka don't clone bios) The reason we clone bios is to be able to give each object request (and consequently each ceph_osd_data/ceph_msg_data item) its own pointer to a (list of) bio(s). The messenger then initializes its cursor with cloned bio's ->bi_iter, so it knows where to start reading from/writing to. That's all the cloned bios are used for: to determine each object request's starting position in the provided data buffer. Introduce ceph_bio_iter to do exactly that -- store position within bio list (i.e. pointer to bio) + position within that bio (i.e. bvec_iter). Signed-off-by: Ilya Dryomov --- drivers/block/rbd.c | 67 +++++++++++++++----------- include/linux/ceph/messenger.h | 59 +++++++++++++++++++---- include/linux/ceph/osd_client.h | 11 +++-- net/ceph/messenger.c | 101 ++++++++++++++-------------------------- net/ceph/osd_client.c | 13 ++++-- 5 files changed, 139 insertions(+), 112 deletions(-) (limited to 'include/linux') diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c index 883f17d6deeb..8eaebf609611 100644 --- a/drivers/block/rbd.c +++ b/drivers/block/rbd.c @@ -218,7 +218,7 @@ typedef void (*rbd_obj_callback_t)(struct rbd_obj_request *); enum obj_request_type { OBJ_REQUEST_NODATA = 1, - OBJ_REQUEST_BIO, + OBJ_REQUEST_BIO, /* pointer into provided bio (list) */ OBJ_REQUEST_PAGES, }; @@ -270,7 +270,7 @@ struct rbd_obj_request { enum obj_request_type type; union { - struct bio *bio_list; + struct ceph_bio_iter bio_pos; struct { struct page **pages; u32 page_count; @@ -1255,6 +1255,27 @@ static u64 rbd_segment_length(struct rbd_device *rbd_dev, return length; } +static void zero_bvec(struct bio_vec *bv) +{ + void *buf; + unsigned long flags; + + buf = bvec_kmap_irq(bv, &flags); + memset(buf, 0, bv->bv_len); + flush_dcache_page(bv->bv_page); + bvec_kunmap_irq(buf, &flags); +} + +static void zero_bios(struct ceph_bio_iter *bio_pos, u32 off, u32 bytes) +{ + struct ceph_bio_iter it = *bio_pos; + + ceph_bio_iter_advance(&it, off); + ceph_bio_iter_advance_step(&it, bytes, ({ + zero_bvec(&bv); + })); +} + /* * bio helpers */ @@ -1719,13 +1740,14 @@ rbd_img_obj_request_read_callback(struct rbd_obj_request *obj_request) rbd_assert(obj_request->type != OBJ_REQUEST_NODATA); if (obj_request->result == -ENOENT) { if (obj_request->type == OBJ_REQUEST_BIO) - zero_bio_chain(obj_request->bio_list, 0); + zero_bios(&obj_request->bio_pos, 0, length); else zero_pages(obj_request->pages, 0, length); obj_request->result = 0; } else if (xferred < length && !obj_request->result) { if (obj_request->type == OBJ_REQUEST_BIO) - zero_bio_chain(obj_request->bio_list, xferred); + zero_bios(&obj_request->bio_pos, xferred, + length - xferred); else zero_pages(obj_request->pages, xferred, length); } @@ -2036,11 +2058,8 @@ static void rbd_obj_request_destroy(struct kref *kref) rbd_assert(obj_request_type_valid(obj_request->type)); switch (obj_request->type) { case OBJ_REQUEST_NODATA: - break; /* Nothing to do */ case OBJ_REQUEST_BIO: - if (obj_request->bio_list) - bio_chain_put(obj_request->bio_list); - break; + break; /* Nothing to do */ case OBJ_REQUEST_PAGES: /* img_data requests don't own their page array */ if (obj_request->pages && @@ -2368,7 +2387,7 @@ static void rbd_img_obj_request_fill(struct rbd_obj_request *obj_request, if (obj_request->type == OBJ_REQUEST_BIO) osd_req_op_extent_osd_data_bio(osd_request, num_ops, - obj_request->bio_list, length); + &obj_request->bio_pos, length); else if (obj_request->type == OBJ_REQUEST_PAGES) osd_req_op_extent_osd_data_pages(osd_request, num_ops, obj_request->pages, length, @@ -2396,8 +2415,7 @@ static int rbd_img_request_fill(struct rbd_img_request *img_request, struct rbd_device *rbd_dev = img_request->rbd_dev; struct rbd_obj_request *obj_request = NULL; struct rbd_obj_request *next_obj_request; - struct bio *bio_list = NULL; - unsigned int bio_offset = 0; + struct ceph_bio_iter bio_it; struct page **pages = NULL; enum obj_operation_type op_type; u64 img_offset; @@ -2412,9 +2430,9 @@ static int rbd_img_request_fill(struct rbd_img_request *img_request, op_type = rbd_img_request_op_type(img_request); if (type == OBJ_REQUEST_BIO) { - bio_list = data_desc; + bio_it = *(struct ceph_bio_iter *)data_desc; rbd_assert(img_offset == - bio_list->bi_iter.bi_sector << SECTOR_SHIFT); + bio_it.iter.bi_sector << SECTOR_SHIFT); } else if (type == OBJ_REQUEST_PAGES) { pages = data_desc; } @@ -2440,17 +2458,8 @@ static int rbd_img_request_fill(struct rbd_img_request *img_request, rbd_img_obj_request_add(img_request, obj_request); if (type == OBJ_REQUEST_BIO) { - unsigned int clone_size; - - rbd_assert(length <= (u64)UINT_MAX); - clone_size = (unsigned int)length; - obj_request->bio_list = - bio_chain_clone_range(&bio_list, - &bio_offset, - clone_size, - GFP_NOIO); - if (!obj_request->bio_list) - goto out_unwind; + obj_request->bio_pos = bio_it; + ceph_bio_iter_advance(&bio_it, length); } else if (type == OBJ_REQUEST_PAGES) { unsigned int page_count; @@ -2980,7 +2989,7 @@ static void rbd_img_parent_read(struct rbd_obj_request *obj_request) if (obj_request->type == OBJ_REQUEST_BIO) result = rbd_img_request_fill(img_request, OBJ_REQUEST_BIO, - obj_request->bio_list); + &obj_request->bio_pos); else result = rbd_img_request_fill(img_request, OBJ_REQUEST_PAGES, obj_request->pages); @@ -4093,9 +4102,13 @@ static void rbd_queue_workfn(struct work_struct *work) if (op_type == OBJ_OP_DISCARD) result = rbd_img_request_fill(img_request, OBJ_REQUEST_NODATA, NULL); - else + else { + struct ceph_bio_iter bio_it = { .bio = rq->bio, + .iter = rq->bio->bi_iter }; + result = rbd_img_request_fill(img_request, OBJ_REQUEST_BIO, - rq->bio); + &bio_it); + } if (result) goto err_img_request; diff --git a/include/linux/ceph/messenger.h b/include/linux/ceph/messenger.h index ead9d85f1c11..d7b9605fd51d 100644 --- a/include/linux/ceph/messenger.h +++ b/include/linux/ceph/messenger.h @@ -93,14 +93,60 @@ static __inline__ bool ceph_msg_data_type_valid(enum ceph_msg_data_type type) } } +#ifdef CONFIG_BLOCK + +struct ceph_bio_iter { + struct bio *bio; + struct bvec_iter iter; +}; + +#define __ceph_bio_iter_advance_step(it, n, STEP) do { \ + unsigned int __n = (n), __cur_n; \ + \ + while (__n) { \ + BUG_ON(!(it)->iter.bi_size); \ + __cur_n = min((it)->iter.bi_size, __n); \ + (void)(STEP); \ + bio_advance_iter((it)->bio, &(it)->iter, __cur_n); \ + if (!(it)->iter.bi_size && (it)->bio->bi_next) { \ + dout("__ceph_bio_iter_advance_step next bio\n"); \ + (it)->bio = (it)->bio->bi_next; \ + (it)->iter = (it)->bio->bi_iter; \ + } \ + __n -= __cur_n; \ + } \ +} while (0) + +/* + * Advance @it by @n bytes. + */ +#define ceph_bio_iter_advance(it, n) \ + __ceph_bio_iter_advance_step(it, n, 0) + +/* + * Advance @it by @n bytes, executing BVEC_STEP for each bio_vec. + */ +#define ceph_bio_iter_advance_step(it, n, BVEC_STEP) \ + __ceph_bio_iter_advance_step(it, n, ({ \ + struct bio_vec bv; \ + struct bvec_iter __cur_iter; \ + \ + __cur_iter = (it)->iter; \ + __cur_iter.bi_size = __cur_n; \ + __bio_for_each_segment(bv, (it)->bio, __cur_iter, __cur_iter) \ + (void)(BVEC_STEP); \ + })) + +#endif /* CONFIG_BLOCK */ + struct ceph_msg_data { struct list_head links; /* ceph_msg->data */ enum ceph_msg_data_type type; union { #ifdef CONFIG_BLOCK struct { - struct bio *bio; - size_t bio_length; + struct ceph_bio_iter bio_pos; + u32 bio_length; }; #endif /* CONFIG_BLOCK */ struct { @@ -122,10 +168,7 @@ struct ceph_msg_data_cursor { bool need_crc; /* crc update needed */ union { #ifdef CONFIG_BLOCK - struct { /* bio */ - struct bio *bio; /* bio from list */ - struct bvec_iter bvec_iter; - }; + struct ceph_bio_iter bio_iter; #endif /* CONFIG_BLOCK */ struct { /* pages */ unsigned int page_offset; /* offset in page */ @@ -290,8 +333,8 @@ extern void ceph_msg_data_add_pages(struct ceph_msg *msg, struct page **pages, extern void ceph_msg_data_add_pagelist(struct ceph_msg *msg, struct ceph_pagelist *pagelist); #ifdef CONFIG_BLOCK -extern void ceph_msg_data_add_bio(struct ceph_msg *msg, struct bio *bio, - size_t length); +void ceph_msg_data_add_bio(struct ceph_msg *msg, struct ceph_bio_iter *bio_pos, + u32 length); #endif /* CONFIG_BLOCK */ extern struct ceph_msg *ceph_msg_new(int type, int front_len, gfp_t flags, diff --git a/include/linux/ceph/osd_client.h b/include/linux/ceph/osd_client.h index 52fb37d1c2a5..315691490cb0 100644 --- a/include/linux/ceph/osd_client.h +++ b/include/linux/ceph/osd_client.h @@ -72,8 +72,8 @@ struct ceph_osd_data { struct ceph_pagelist *pagelist; #ifdef CONFIG_BLOCK struct { - struct bio *bio; /* list of bios */ - size_t bio_length; /* total in list */ + struct ceph_bio_iter bio_pos; + u32 bio_length; }; #endif /* CONFIG_BLOCK */ }; @@ -405,9 +405,10 @@ extern void osd_req_op_extent_osd_data_pagelist(struct ceph_osd_request *, unsigned int which, struct ceph_pagelist *pagelist); #ifdef CONFIG_BLOCK -extern void osd_req_op_extent_osd_data_bio(struct ceph_osd_request *, - unsigned int which, - struct bio *bio, size_t bio_length); +void osd_req_op_extent_osd_data_bio(struct ceph_osd_request *osd_req, + unsigned int which, + struct ceph_bio_iter *bio_pos, + u32 bio_length); #endif /* CONFIG_BLOCK */ extern void osd_req_op_cls_request_data_pagelist(struct ceph_osd_request *, diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 8a4d3758030b..b9fa8b869c08 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -839,90 +839,57 @@ static void ceph_msg_data_bio_cursor_init(struct ceph_msg_data_cursor *cursor, size_t length) { struct ceph_msg_data *data = cursor->data; - struct bio *bio; + struct ceph_bio_iter *it = &cursor->bio_iter; - BUG_ON(data->type != CEPH_MSG_DATA_BIO); + cursor->resid = min_t(size_t, length, data->bio_length); + *it = data->bio_pos; + if (cursor->resid < it->iter.bi_size) + it->iter.bi_size = cursor->resid; - bio = data->bio; - BUG_ON(!bio); - - cursor->resid = min(length, data->bio_length); - cursor->bio = bio; - cursor->bvec_iter = bio->bi_iter; - cursor->last_piece = - cursor->resid <= bio_iter_len(bio, cursor->bvec_iter); + BUG_ON(cursor->resid < bio_iter_len(it->bio, it->iter)); + cursor->last_piece = cursor->resid == bio_iter_len(it->bio, it->iter); } static struct page *ceph_msg_data_bio_next(struct ceph_msg_data_cursor *cursor, size_t *page_offset, size_t *length) { - struct ceph_msg_data *data = cursor->data; - struct bio *bio; - struct bio_vec bio_vec; - - BUG_ON(data->type != CEPH_MSG_DATA_BIO); - - bio = cursor->bio; - BUG_ON(!bio); + struct bio_vec bv = bio_iter_iovec(cursor->bio_iter.bio, + cursor->bio_iter.iter); - bio_vec = bio_iter_iovec(bio, cursor->bvec_iter); - - *page_offset = (size_t) bio_vec.bv_offset; - BUG_ON(*page_offset >= PAGE_SIZE); - if (cursor->last_piece) /* pagelist offset is always 0 */ - *length = cursor->resid; - else - *length = (size_t) bio_vec.bv_len; - BUG_ON(*length > cursor->resid); - BUG_ON(*page_offset + *length > PAGE_SIZE); - - return bio_vec.bv_page; + *page_offset = bv.bv_offset; + *length = bv.bv_len; + return bv.bv_page; } static bool ceph_msg_data_bio_advance(struct ceph_msg_data_cursor *cursor, size_t bytes) { - struct bio *bio; - struct bio_vec bio_vec; - - BUG_ON(cursor->data->type != CEPH_MSG_DATA_BIO); - - bio = cursor->bio; - BUG_ON(!bio); - - bio_vec = bio_iter_iovec(bio, cursor->bvec_iter); + struct ceph_bio_iter *it = &cursor->bio_iter; - /* Advance the cursor offset */ - - BUG_ON(cursor->resid < bytes); + BUG_ON(bytes > cursor->resid); + BUG_ON(bytes > bio_iter_len(it->bio, it->iter)); cursor->resid -= bytes; + bio_advance_iter(it->bio, &it->iter, bytes); - bio_advance_iter(bio, &cursor->bvec_iter, bytes); + if (!cursor->resid) { + BUG_ON(!cursor->last_piece); + return false; /* no more data */ + } - if (bytes < bio_vec.bv_len) + if (!bytes || (it->iter.bi_size && it->iter.bi_bvec_done)) return false; /* more bytes to process in this segment */ - /* Move on to the next segment, and possibly the next bio */ - - if (!cursor->bvec_iter.bi_size) { - bio = bio->bi_next; - cursor->bio = bio; - if (bio) - cursor->bvec_iter = bio->bi_iter; - else - memset(&cursor->bvec_iter, 0, - sizeof(cursor->bvec_iter)); - } - - if (!cursor->last_piece) { - BUG_ON(!cursor->resid); - BUG_ON(!bio); - /* A short read is OK, so use <= rather than == */ - if (cursor->resid <= bio_iter_len(bio, cursor->bvec_iter)) - cursor->last_piece = true; + if (!it->iter.bi_size) { + it->bio = it->bio->bi_next; + it->iter = it->bio->bi_iter; + if (cursor->resid < it->iter.bi_size) + it->iter.bi_size = cursor->resid; } + BUG_ON(cursor->last_piece); + BUG_ON(cursor->resid < bio_iter_len(it->bio, it->iter)); + cursor->last_piece = cursor->resid == bio_iter_len(it->bio, it->iter); return true; } #endif /* CONFIG_BLOCK */ @@ -1163,9 +1130,11 @@ static struct page *ceph_msg_data_next(struct ceph_msg_data_cursor *cursor, page = NULL; break; } + BUG_ON(!page); BUG_ON(*page_offset + *length > PAGE_SIZE); BUG_ON(!*length); + BUG_ON(*length > cursor->resid); if (last_piece) *last_piece = cursor->last_piece; @@ -3262,16 +3231,14 @@ void ceph_msg_data_add_pagelist(struct ceph_msg *msg, EXPORT_SYMBOL(ceph_msg_data_add_pagelist); #ifdef CONFIG_BLOCK -void ceph_msg_data_add_bio(struct ceph_msg *msg, struct bio *bio, - size_t length) +void ceph_msg_data_add_bio(struct ceph_msg *msg, struct ceph_bio_iter *bio_pos, + u32 length) { struct ceph_msg_data *data; - BUG_ON(!bio); - data = ceph_msg_data_create(CEPH_MSG_DATA_BIO); BUG_ON(!data); - data->bio = bio; + data->bio_pos = *bio_pos; data->bio_length = length; list_add_tail(&data->links, &msg->data); diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c index 4b0485458d26..339d8773ebe8 100644 --- a/net/ceph/osd_client.c +++ b/net/ceph/osd_client.c @@ -146,10 +146,11 @@ static void ceph_osd_data_pagelist_init(struct ceph_osd_data *osd_data, #ifdef CONFIG_BLOCK static void ceph_osd_data_bio_init(struct ceph_osd_data *osd_data, - struct bio *bio, size_t bio_length) + struct ceph_bio_iter *bio_pos, + u32 bio_length) { osd_data->type = CEPH_OSD_DATA_TYPE_BIO; - osd_data->bio = bio; + osd_data->bio_pos = *bio_pos; osd_data->bio_length = bio_length; } #endif /* CONFIG_BLOCK */ @@ -216,12 +217,14 @@ EXPORT_SYMBOL(osd_req_op_extent_osd_data_pagelist); #ifdef CONFIG_BLOCK void osd_req_op_extent_osd_data_bio(struct ceph_osd_request *osd_req, - unsigned int which, struct bio *bio, size_t bio_length) + unsigned int which, + struct ceph_bio_iter *bio_pos, + u32 bio_length) { struct ceph_osd_data *osd_data; osd_data = osd_req_op_data(osd_req, which, extent, osd_data); - ceph_osd_data_bio_init(osd_data, bio, bio_length); + ceph_osd_data_bio_init(osd_data, bio_pos, bio_length); } EXPORT_SYMBOL(osd_req_op_extent_osd_data_bio); #endif /* CONFIG_BLOCK */ @@ -826,7 +829,7 @@ static void ceph_osdc_msg_data_add(struct ceph_msg *msg, ceph_msg_data_add_pagelist(msg, osd_data->pagelist); #ifdef CONFIG_BLOCK } else if (osd_data->type == CEPH_OSD_DATA_TYPE_BIO) { - ceph_msg_data_add_bio(msg, osd_data->bio, length); + ceph_msg_data_add_bio(msg, &osd_data->bio_pos, length); #endif } else { BUG_ON(osd_data->type != CEPH_OSD_DATA_TYPE_NONE); -- cgit v1.2.3 From b9e281c2b38804984d619e1d9efc4b9020bcb291 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Sat, 20 Jan 2018 10:30:11 +0100 Subject: libceph: introduce BVECS data type In preparation for rbd "fancy" striping, introduce ceph_bvec_iter for working with bio_vec array data buffers. The wrappers are trivial, but make it look similar to ceph_bio_iter. Signed-off-by: Ilya Dryomov --- include/linux/ceph/messenger.h | 42 +++++++++++++++++++++++ include/linux/ceph/osd_client.h | 8 +++++ net/ceph/messenger.c | 75 +++++++++++++++++++++++++++++++++++++++++ net/ceph/osd_client.c | 39 +++++++++++++++++++++ 4 files changed, 164 insertions(+) (limited to 'include/linux') diff --git a/include/linux/ceph/messenger.h b/include/linux/ceph/messenger.h index d7b9605fd51d..c7dfcb8a1fb2 100644 --- a/include/linux/ceph/messenger.h +++ b/include/linux/ceph/messenger.h @@ -76,6 +76,7 @@ enum ceph_msg_data_type { #ifdef CONFIG_BLOCK CEPH_MSG_DATA_BIO, /* data source/destination is a bio list */ #endif /* CONFIG_BLOCK */ + CEPH_MSG_DATA_BVECS, /* data source/destination is a bio_vec array */ }; static __inline__ bool ceph_msg_data_type_valid(enum ceph_msg_data_type type) @@ -87,6 +88,7 @@ static __inline__ bool ceph_msg_data_type_valid(enum ceph_msg_data_type type) #ifdef CONFIG_BLOCK case CEPH_MSG_DATA_BIO: #endif /* CONFIG_BLOCK */ + case CEPH_MSG_DATA_BVECS: return true; default: return false; @@ -139,6 +141,42 @@ struct ceph_bio_iter { #endif /* CONFIG_BLOCK */ +struct ceph_bvec_iter { + struct bio_vec *bvecs; + struct bvec_iter iter; +}; + +#define __ceph_bvec_iter_advance_step(it, n, STEP) do { \ + BUG_ON((n) > (it)->iter.bi_size); \ + (void)(STEP); \ + bvec_iter_advance((it)->bvecs, &(it)->iter, (n)); \ +} while (0) + +/* + * Advance @it by @n bytes. + */ +#define ceph_bvec_iter_advance(it, n) \ + __ceph_bvec_iter_advance_step(it, n, 0) + +/* + * Advance @it by @n bytes, executing BVEC_STEP for each bio_vec. + */ +#define ceph_bvec_iter_advance_step(it, n, BVEC_STEP) \ + __ceph_bvec_iter_advance_step(it, n, ({ \ + struct bio_vec bv; \ + struct bvec_iter __cur_iter; \ + \ + __cur_iter = (it)->iter; \ + __cur_iter.bi_size = (n); \ + for_each_bvec(bv, (it)->bvecs, __cur_iter, __cur_iter) \ + (void)(BVEC_STEP); \ + })) + +#define ceph_bvec_iter_shorten(it, n) do { \ + BUG_ON((n) > (it)->iter.bi_size); \ + (it)->iter.bi_size = (n); \ +} while (0) + struct ceph_msg_data { struct list_head links; /* ceph_msg->data */ enum ceph_msg_data_type type; @@ -149,6 +187,7 @@ struct ceph_msg_data { u32 bio_length; }; #endif /* CONFIG_BLOCK */ + struct ceph_bvec_iter bvec_pos; struct { struct page **pages; /* NOT OWNER. */ size_t length; /* total # bytes */ @@ -170,6 +209,7 @@ struct ceph_msg_data_cursor { #ifdef CONFIG_BLOCK struct ceph_bio_iter bio_iter; #endif /* CONFIG_BLOCK */ + struct bvec_iter bvec_iter; struct { /* pages */ unsigned int page_offset; /* offset in page */ unsigned short page_index; /* index in array */ @@ -336,6 +376,8 @@ extern void ceph_msg_data_add_pagelist(struct ceph_msg *msg, void ceph_msg_data_add_bio(struct ceph_msg *msg, struct ceph_bio_iter *bio_pos, u32 length); #endif /* CONFIG_BLOCK */ +void ceph_msg_data_add_bvecs(struct ceph_msg *msg, + struct ceph_bvec_iter *bvec_pos); extern struct ceph_msg *ceph_msg_new(int type, int front_len, gfp_t flags, bool can_fail); diff --git a/include/linux/ceph/osd_client.h b/include/linux/ceph/osd_client.h index 315691490cb0..528ccc943cee 100644 --- a/include/linux/ceph/osd_client.h +++ b/include/linux/ceph/osd_client.h @@ -57,6 +57,7 @@ enum ceph_osd_data_type { #ifdef CONFIG_BLOCK CEPH_OSD_DATA_TYPE_BIO, #endif /* CONFIG_BLOCK */ + CEPH_OSD_DATA_TYPE_BVECS, }; struct ceph_osd_data { @@ -76,6 +77,7 @@ struct ceph_osd_data { u32 bio_length; }; #endif /* CONFIG_BLOCK */ + struct ceph_bvec_iter bvec_pos; }; }; @@ -410,6 +412,9 @@ void osd_req_op_extent_osd_data_bio(struct ceph_osd_request *osd_req, struct ceph_bio_iter *bio_pos, u32 bio_length); #endif /* CONFIG_BLOCK */ +void osd_req_op_extent_osd_data_bvec_pos(struct ceph_osd_request *osd_req, + unsigned int which, + struct ceph_bvec_iter *bvec_pos); extern void osd_req_op_cls_request_data_pagelist(struct ceph_osd_request *, unsigned int which, @@ -419,6 +424,9 @@ extern void osd_req_op_cls_request_data_pages(struct ceph_osd_request *, struct page **pages, u64 length, u32 alignment, bool pages_from_pool, bool own_pages); +void osd_req_op_cls_request_data_bvecs(struct ceph_osd_request *osd_req, + unsigned int which, + struct bio_vec *bvecs, u32 bytes); extern void osd_req_op_cls_response_data_pages(struct ceph_osd_request *, unsigned int which, struct page **pages, u64 length, diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index b9fa8b869c08..91a57857cf11 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -894,6 +894,58 @@ static bool ceph_msg_data_bio_advance(struct ceph_msg_data_cursor *cursor, } #endif /* CONFIG_BLOCK */ +static void ceph_msg_data_bvecs_cursor_init(struct ceph_msg_data_cursor *cursor, + size_t length) +{ + struct ceph_msg_data *data = cursor->data; + struct bio_vec *bvecs = data->bvec_pos.bvecs; + + cursor->resid = min_t(size_t, length, data->bvec_pos.iter.bi_size); + cursor->bvec_iter = data->bvec_pos.iter; + cursor->bvec_iter.bi_size = cursor->resid; + + BUG_ON(cursor->resid < bvec_iter_len(bvecs, cursor->bvec_iter)); + cursor->last_piece = + cursor->resid == bvec_iter_len(bvecs, cursor->bvec_iter); +} + +static struct page *ceph_msg_data_bvecs_next(struct ceph_msg_data_cursor *cursor, + size_t *page_offset, + size_t *length) +{ + struct bio_vec bv = bvec_iter_bvec(cursor->data->bvec_pos.bvecs, + cursor->bvec_iter); + + *page_offset = bv.bv_offset; + *length = bv.bv_len; + return bv.bv_page; +} + +static bool ceph_msg_data_bvecs_advance(struct ceph_msg_data_cursor *cursor, + size_t bytes) +{ + struct bio_vec *bvecs = cursor->data->bvec_pos.bvecs; + + BUG_ON(bytes > cursor->resid); + BUG_ON(bytes > bvec_iter_len(bvecs, cursor->bvec_iter)); + cursor->resid -= bytes; + bvec_iter_advance(bvecs, &cursor->bvec_iter, bytes); + + if (!cursor->resid) { + BUG_ON(!cursor->last_piece); + return false; /* no more data */ + } + + if (!bytes || cursor->bvec_iter.bi_bvec_done) + return false; /* more bytes to process in this segment */ + + BUG_ON(cursor->last_piece); + BUG_ON(cursor->resid < bvec_iter_len(bvecs, cursor->bvec_iter)); + cursor->last_piece = + cursor->resid == bvec_iter_len(bvecs, cursor->bvec_iter); + return true; +} + /* * For a page array, a piece comes from the first page in the array * that has not already been fully consumed. @@ -1077,6 +1129,9 @@ static void __ceph_msg_data_cursor_init(struct ceph_msg_data_cursor *cursor) ceph_msg_data_bio_cursor_init(cursor, length); break; #endif /* CONFIG_BLOCK */ + case CEPH_MSG_DATA_BVECS: + ceph_msg_data_bvecs_cursor_init(cursor, length); + break; case CEPH_MSG_DATA_NONE: default: /* BUG(); */ @@ -1125,6 +1180,9 @@ static struct page *ceph_msg_data_next(struct ceph_msg_data_cursor *cursor, page = ceph_msg_data_bio_next(cursor, page_offset, length); break; #endif /* CONFIG_BLOCK */ + case CEPH_MSG_DATA_BVECS: + page = ceph_msg_data_bvecs_next(cursor, page_offset, length); + break; case CEPH_MSG_DATA_NONE: default: page = NULL; @@ -1163,6 +1221,9 @@ static void ceph_msg_data_advance(struct ceph_msg_data_cursor *cursor, new_piece = ceph_msg_data_bio_advance(cursor, bytes); break; #endif /* CONFIG_BLOCK */ + case CEPH_MSG_DATA_BVECS: + new_piece = ceph_msg_data_bvecs_advance(cursor, bytes); + break; case CEPH_MSG_DATA_NONE: default: BUG(); @@ -3247,6 +3308,20 @@ void ceph_msg_data_add_bio(struct ceph_msg *msg, struct ceph_bio_iter *bio_pos, EXPORT_SYMBOL(ceph_msg_data_add_bio); #endif /* CONFIG_BLOCK */ +void ceph_msg_data_add_bvecs(struct ceph_msg *msg, + struct ceph_bvec_iter *bvec_pos) +{ + struct ceph_msg_data *data; + + data = ceph_msg_data_create(CEPH_MSG_DATA_BVECS); + BUG_ON(!data); + data->bvec_pos = *bvec_pos; + + list_add_tail(&data->links, &msg->data); + msg->data_length += bvec_pos->iter.bi_size; +} +EXPORT_SYMBOL(ceph_msg_data_add_bvecs); + /* * construct a new message with given type, size * the new msg has a ref count of 1. diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c index 339d8773ebe8..407be0533c18 100644 --- a/net/ceph/osd_client.c +++ b/net/ceph/osd_client.c @@ -155,6 +155,13 @@ static void ceph_osd_data_bio_init(struct ceph_osd_data *osd_data, } #endif /* CONFIG_BLOCK */ +static void ceph_osd_data_bvecs_init(struct ceph_osd_data *osd_data, + struct ceph_bvec_iter *bvec_pos) +{ + osd_data->type = CEPH_OSD_DATA_TYPE_BVECS; + osd_data->bvec_pos = *bvec_pos; +} + #define osd_req_op_data(oreq, whch, typ, fld) \ ({ \ struct ceph_osd_request *__oreq = (oreq); \ @@ -229,6 +236,17 @@ void osd_req_op_extent_osd_data_bio(struct ceph_osd_request *osd_req, EXPORT_SYMBOL(osd_req_op_extent_osd_data_bio); #endif /* CONFIG_BLOCK */ +void osd_req_op_extent_osd_data_bvec_pos(struct ceph_osd_request *osd_req, + unsigned int which, + struct ceph_bvec_iter *bvec_pos) +{ + struct ceph_osd_data *osd_data; + + osd_data = osd_req_op_data(osd_req, which, extent, osd_data); + ceph_osd_data_bvecs_init(osd_data, bvec_pos); +} +EXPORT_SYMBOL(osd_req_op_extent_osd_data_bvec_pos); + static void osd_req_op_cls_request_info_pagelist( struct ceph_osd_request *osd_req, unsigned int which, struct ceph_pagelist *pagelist) @@ -266,6 +284,23 @@ void osd_req_op_cls_request_data_pages(struct ceph_osd_request *osd_req, } EXPORT_SYMBOL(osd_req_op_cls_request_data_pages); +void osd_req_op_cls_request_data_bvecs(struct ceph_osd_request *osd_req, + unsigned int which, + struct bio_vec *bvecs, u32 bytes) +{ + struct ceph_osd_data *osd_data; + struct ceph_bvec_iter it = { + .bvecs = bvecs, + .iter = { .bi_size = bytes }, + }; + + osd_data = osd_req_op_data(osd_req, which, cls, request_data); + ceph_osd_data_bvecs_init(osd_data, &it); + osd_req->r_ops[which].cls.indata_len += bytes; + osd_req->r_ops[which].indata_len += bytes; +} +EXPORT_SYMBOL(osd_req_op_cls_request_data_bvecs); + void osd_req_op_cls_response_data_pages(struct ceph_osd_request *osd_req, unsigned int which, struct page **pages, u64 length, u32 alignment, bool pages_from_pool, bool own_pages) @@ -291,6 +326,8 @@ static u64 ceph_osd_data_length(struct ceph_osd_data *osd_data) case CEPH_OSD_DATA_TYPE_BIO: return (u64)osd_data->bio_length; #endif /* CONFIG_BLOCK */ + case CEPH_OSD_DATA_TYPE_BVECS: + return osd_data->bvec_pos.iter.bi_size; default: WARN(true, "unrecognized data type %d\n", (int)osd_data->type); return 0; @@ -831,6 +868,8 @@ static void ceph_osdc_msg_data_add(struct ceph_msg *msg, } else if (osd_data->type == CEPH_OSD_DATA_TYPE_BIO) { ceph_msg_data_add_bio(msg, &osd_data->bio_pos, length); #endif + } else if (osd_data->type == CEPH_OSD_DATA_TYPE_BVECS) { + ceph_msg_data_add_bvecs(msg, &osd_data->bvec_pos); } else { BUG_ON(osd_data->type != CEPH_OSD_DATA_TYPE_NONE); } -- cgit v1.2.3 From ed0811d2d243c4195580a9671266031907c02ca7 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Fri, 2 Feb 2018 15:23:22 +0100 Subject: libceph: striping framework implementation Signed-off-by: Ilya Dryomov --- include/linux/ceph/striper.h | 65 +++++++++++++ net/ceph/Makefile | 1 + net/ceph/striper.c | 226 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+) create mode 100644 include/linux/ceph/striper.h create mode 100644 net/ceph/striper.c (limited to 'include/linux') diff --git a/include/linux/ceph/striper.h b/include/linux/ceph/striper.h new file mode 100644 index 000000000000..74134ee5fdc8 --- /dev/null +++ b/include/linux/ceph/striper.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_CEPH_STRIPER_H +#define _LINUX_CEPH_STRIPER_H + +#include +#include + +struct ceph_file_layout; + +struct ceph_object_extent { + struct list_head oe_item; + u64 oe_objno; + u64 oe_off; + u64 oe_len; +}; + +static inline void ceph_object_extent_init(struct ceph_object_extent *ex) +{ + INIT_LIST_HEAD(&ex->oe_item); +} + +/* + * Called for each mapped stripe unit. + * + * @bytes: number of bytes mapped, i.e. the minimum of the full length + * requested (file extent length) or the remainder of the stripe + * unit within an object + */ +typedef void (*ceph_object_extent_fn_t)(struct ceph_object_extent *ex, + u32 bytes, void *arg); + +int ceph_file_to_extents(struct ceph_file_layout *l, u64 off, u64 len, + struct list_head *object_extents, + struct ceph_object_extent *alloc_fn(void *arg), + void *alloc_arg, + ceph_object_extent_fn_t action_fn, + void *action_arg); +int ceph_iterate_extents(struct ceph_file_layout *l, u64 off, u64 len, + struct list_head *object_extents, + ceph_object_extent_fn_t action_fn, + void *action_arg); + +struct ceph_file_extent { + u64 fe_off; + u64 fe_len; +}; + +static inline u64 ceph_file_extents_bytes(struct ceph_file_extent *file_extents, + u32 num_file_extents) +{ + u64 bytes = 0; + u32 i; + + for (i = 0; i < num_file_extents; i++) + bytes += file_extents[i].fe_len; + + return bytes; +} + +int ceph_extent_to_file(struct ceph_file_layout *l, + u64 objno, u64 objoff, u64 objlen, + struct ceph_file_extent **file_extents, + u32 *num_file_extents); + +#endif diff --git a/net/ceph/Makefile b/net/ceph/Makefile index b4bded4b5396..12bf49772d24 100644 --- a/net/ceph/Makefile +++ b/net/ceph/Makefile @@ -8,6 +8,7 @@ libceph-y := ceph_common.o messenger.o msgpool.o buffer.o pagelist.o \ mon_client.o \ cls_lock_client.o \ osd_client.o osdmap.o crush/crush.o crush/mapper.o crush/hash.o \ + striper.o \ debugfs.o \ auth.o auth_none.o \ crypto.o armor.o \ diff --git a/net/ceph/striper.c b/net/ceph/striper.c new file mode 100644 index 000000000000..bc1e4de30df9 --- /dev/null +++ b/net/ceph/striper.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include + +#include +#include + +#include +#include +#include + +/* + * Return the last extent with given objno (@object_extents is sorted + * by objno). If not found, return NULL and set @add_pos so that the + * new extent can be added with list_add(add_pos, new_ex). + */ +static struct ceph_object_extent * +lookup_last(struct list_head *object_extents, u64 objno, + struct list_head **add_pos) +{ + struct list_head *pos; + + list_for_each_prev(pos, object_extents) { + struct ceph_object_extent *ex = + list_entry(pos, typeof(*ex), oe_item); + + if (ex->oe_objno == objno) + return ex; + + if (ex->oe_objno < objno) + break; + } + + *add_pos = pos; + return NULL; +} + +static struct ceph_object_extent * +lookup_containing(struct list_head *object_extents, u64 objno, + u64 objoff, u32 xlen) +{ + struct ceph_object_extent *ex; + + list_for_each_entry(ex, object_extents, oe_item) { + if (ex->oe_objno == objno && + ex->oe_off <= objoff && + ex->oe_off + ex->oe_len >= objoff + xlen) /* paranoia */ + return ex; + + if (ex->oe_objno > objno) + break; + } + + return NULL; +} + +/* + * Map a file extent to a sorted list of object extents. + * + * We want only one (or as few as possible) object extents per object. + * Adjacent object extents will be merged together, each returned object + * extent may reverse map to multiple different file extents. + * + * Call @alloc_fn for each new object extent and @action_fn for each + * mapped stripe unit, whether it was merged into an already allocated + * object extent or started a new object extent. + * + * Newly allocated object extents are added to @object_extents. + * To keep @object_extents sorted, successive calls to this function + * must map successive file extents (i.e. the list of file extents that + * are mapped using the same @object_extents must be sorted). + * + * The caller is responsible for @object_extents. + */ +int ceph_file_to_extents(struct ceph_file_layout *l, u64 off, u64 len, + struct list_head *object_extents, + struct ceph_object_extent *alloc_fn(void *arg), + void *alloc_arg, + ceph_object_extent_fn_t action_fn, + void *action_arg) +{ + struct ceph_object_extent *last_ex, *ex; + + while (len) { + struct list_head *add_pos = NULL; + u64 objno, objoff; + u32 xlen; + + ceph_calc_file_object_mapping(l, off, len, &objno, &objoff, + &xlen); + + last_ex = lookup_last(object_extents, objno, &add_pos); + if (!last_ex || last_ex->oe_off + last_ex->oe_len != objoff) { + ex = alloc_fn(alloc_arg); + if (!ex) + return -ENOMEM; + + ex->oe_objno = objno; + ex->oe_off = objoff; + ex->oe_len = xlen; + if (action_fn) + action_fn(ex, xlen, action_arg); + + if (!last_ex) + list_add(&ex->oe_item, add_pos); + else + list_add(&ex->oe_item, &last_ex->oe_item); + } else { + last_ex->oe_len += xlen; + if (action_fn) + action_fn(last_ex, xlen, action_arg); + } + + off += xlen; + len -= xlen; + } + + for (last_ex = list_first_entry(object_extents, typeof(*ex), oe_item), + ex = list_next_entry(last_ex, oe_item); + &ex->oe_item != object_extents; + last_ex = ex, ex = list_next_entry(ex, oe_item)) { + if (last_ex->oe_objno > ex->oe_objno || + (last_ex->oe_objno == ex->oe_objno && + last_ex->oe_off + last_ex->oe_len >= ex->oe_off)) { + WARN(1, "%s: object_extents list not sorted!\n", + __func__); + return -EINVAL; + } + } + + return 0; +} +EXPORT_SYMBOL(ceph_file_to_extents); + +/* + * A stripped down, non-allocating version of ceph_file_to_extents(), + * for when @object_extents is already populated. + */ +int ceph_iterate_extents(struct ceph_file_layout *l, u64 off, u64 len, + struct list_head *object_extents, + ceph_object_extent_fn_t action_fn, + void *action_arg) +{ + while (len) { + struct ceph_object_extent *ex; + u64 objno, objoff; + u32 xlen; + + ceph_calc_file_object_mapping(l, off, len, &objno, &objoff, + &xlen); + + ex = lookup_containing(object_extents, objno, objoff, xlen); + if (!ex) { + WARN(1, "%s: objno %llu %llu~%u not found!\n", + __func__, objno, objoff, xlen); + return -EINVAL; + } + + action_fn(ex, xlen, action_arg); + + off += xlen; + len -= xlen; + } + + return 0; +} +EXPORT_SYMBOL(ceph_iterate_extents); + +/* + * Reverse map an object extent to a sorted list of file extents. + * + * On success, the caller is responsible for: + * + * kfree(file_extents) + */ +int ceph_extent_to_file(struct ceph_file_layout *l, + u64 objno, u64 objoff, u64 objlen, + struct ceph_file_extent **file_extents, + u32 *num_file_extents) +{ + u32 stripes_per_object = l->object_size / l->stripe_unit; + u64 blockno; /* which su */ + u32 blockoff; /* offset into su */ + u64 stripeno; /* which stripe */ + u32 stripepos; /* which su in the stripe, + which object in the object set */ + u64 objsetno; /* which object set */ + u32 i = 0; + + if (!objlen) { + *file_extents = NULL; + *num_file_extents = 0; + return 0; + } + + *num_file_extents = DIV_ROUND_UP_ULL(objoff + objlen, l->stripe_unit) - + DIV_ROUND_DOWN_ULL(objoff, l->stripe_unit); + *file_extents = kmalloc_array(*num_file_extents, sizeof(**file_extents), + GFP_NOIO); + if (!*file_extents) + return -ENOMEM; + + div_u64_rem(objoff, l->stripe_unit, &blockoff); + while (objlen) { + u64 off, len; + + objsetno = div_u64_rem(objno, l->stripe_count, &stripepos); + stripeno = div_u64(objoff, l->stripe_unit) + + objsetno * stripes_per_object; + blockno = stripeno * l->stripe_count + stripepos; + off = blockno * l->stripe_unit + blockoff; + len = min_t(u64, objlen, l->stripe_unit - blockoff); + + (*file_extents)[i].fe_off = off; + (*file_extents)[i].fe_len = len; + + blockoff = 0; + objoff += len; + objlen -= len; + i++; + } + + BUG_ON(i != *num_file_extents); + return 0; +} +EXPORT_SYMBOL(ceph_extent_to_file); -- cgit v1.2.3 From 08c1ac508b6dc20ac866e7cdb7279245437c7d26 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Sat, 17 Feb 2018 10:41:20 +0100 Subject: libceph, ceph: move ceph_calc_file_object_mapping() to striper.c ceph_calc_file_object_mapping() has nothing to do with osdmaps. Signed-off-by: Ilya Dryomov --- fs/ceph/addr.c | 1 + fs/ceph/ioctl.c | 2 +- include/linux/ceph/osdmap.h | 5 ----- include/linux/ceph/striper.h | 4 ++++ net/ceph/osd_client.c | 1 + net/ceph/osdmap.c | 37 ------------------------------------- net/ceph/striper.c | 37 ++++++++++++++++++++++++++++++++++++- 7 files changed, 43 insertions(+), 44 deletions(-) (limited to 'include/linux') diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c index c0fe1b6f47ac..c3557a9ea73d 100644 --- a/fs/ceph/addr.c +++ b/fs/ceph/addr.c @@ -15,6 +15,7 @@ #include "mds_client.h" #include "cache.h" #include +#include /* * Ceph address space ops. diff --git a/fs/ceph/ioctl.c b/fs/ceph/ioctl.c index b855d24a895a..c90f03beb15d 100644 --- a/fs/ceph/ioctl.c +++ b/fs/ceph/ioctl.c @@ -5,7 +5,7 @@ #include "super.h" #include "mds_client.h" #include "ioctl.h" - +#include /* * ioctls diff --git a/include/linux/ceph/osdmap.h b/include/linux/ceph/osdmap.h index 92314035dac1..e71fb222c7c3 100644 --- a/include/linux/ceph/osdmap.h +++ b/include/linux/ceph/osdmap.h @@ -5,7 +5,6 @@ #include #include #include -#include #include /* @@ -280,10 +279,6 @@ bool ceph_osds_changed(const struct ceph_osds *old_acting, const struct ceph_osds *new_acting, bool any_change); -void ceph_calc_file_object_mapping(struct ceph_file_layout *l, - u64 off, u64 len, - u64 *objno, u64 *objoff, u32 *xlen); - int __ceph_object_locator_to_pg(struct ceph_pg_pool_info *pi, const struct ceph_object_id *oid, const struct ceph_object_locator *oloc, diff --git a/include/linux/ceph/striper.h b/include/linux/ceph/striper.h index 74134ee5fdc8..cbd0d24b7148 100644 --- a/include/linux/ceph/striper.h +++ b/include/linux/ceph/striper.h @@ -7,6 +7,10 @@ struct ceph_file_layout; +void ceph_calc_file_object_mapping(struct ceph_file_layout *l, + u64 off, u64 len, + u64 *objno, u64 *objoff, u32 *xlen); + struct ceph_object_extent { struct list_head oe_item; u64 oe_objno; diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c index 407be0533c18..4a3af96dc057 100644 --- a/net/ceph/osd_client.c +++ b/net/ceph/osd_client.c @@ -20,6 +20,7 @@ #include #include #include +#include #define OSD_OPREPLY_FRONT_LEN 512 diff --git a/net/ceph/osdmap.c b/net/ceph/osdmap.c index e3ebbe2ecdad..9645ffd6acfb 100644 --- a/net/ceph/osdmap.c +++ b/net/ceph/osdmap.c @@ -4,7 +4,6 @@ #include #include -#include #include #include @@ -2140,42 +2139,6 @@ bool ceph_osds_changed(const struct ceph_osds *old_acting, return false; } -/* - * Map a file extent to a stripe unit within an object. - * Fill in objno, offset into object, and object extent length (i.e. the - * number of bytes mapped, less than or equal to @l->stripe_unit). - * - * Example for stripe_count = 3, stripes_per_object = 4: - * - * blockno | 0 3 6 9 | 1 4 7 10 | 2 5 8 11 | 12 15 18 21 | 13 16 19 - * stripeno | 0 1 2 3 | 0 1 2 3 | 0 1 2 3 | 4 5 6 7 | 4 5 6 - * stripepos | 0 | 1 | 2 | 0 | 1 - * objno | 0 | 1 | 2 | 3 | 4 - * objsetno | 0 | 1 - */ -void ceph_calc_file_object_mapping(struct ceph_file_layout *l, - u64 off, u64 len, - u64 *objno, u64 *objoff, u32 *xlen) -{ - u32 stripes_per_object = l->object_size / l->stripe_unit; - u64 blockno; /* which su in the file (i.e. globally) */ - u32 blockoff; /* offset into su */ - u64 stripeno; /* which stripe */ - u32 stripepos; /* which su in the stripe, - which object in the object set */ - u64 objsetno; /* which object set */ - u32 objsetpos; /* which stripe in the object set */ - - blockno = div_u64_rem(off, l->stripe_unit, &blockoff); - stripeno = div_u64_rem(blockno, l->stripe_count, &stripepos); - objsetno = div_u64_rem(stripeno, stripes_per_object, &objsetpos); - - *objno = objsetno * l->stripe_count + stripepos; - *objoff = objsetpos * l->stripe_unit + blockoff; - *xlen = min_t(u64, len, l->stripe_unit - blockoff); -} -EXPORT_SYMBOL(ceph_calc_file_object_mapping); - /* * Map an object into a PG. * diff --git a/net/ceph/striper.c b/net/ceph/striper.c index bc1e4de30df9..c36462dc86b7 100644 --- a/net/ceph/striper.c +++ b/net/ceph/striper.c @@ -5,10 +5,45 @@ #include #include -#include #include #include +/* + * Map a file extent to a stripe unit within an object. + * Fill in objno, offset into object, and object extent length (i.e. the + * number of bytes mapped, less than or equal to @l->stripe_unit). + * + * Example for stripe_count = 3, stripes_per_object = 4: + * + * blockno | 0 3 6 9 | 1 4 7 10 | 2 5 8 11 | 12 15 18 21 | 13 16 19 + * stripeno | 0 1 2 3 | 0 1 2 3 | 0 1 2 3 | 4 5 6 7 | 4 5 6 + * stripepos | 0 | 1 | 2 | 0 | 1 + * objno | 0 | 1 | 2 | 3 | 4 + * objsetno | 0 | 1 + */ +void ceph_calc_file_object_mapping(struct ceph_file_layout *l, + u64 off, u64 len, + u64 *objno, u64 *objoff, u32 *xlen) +{ + u32 stripes_per_object = l->object_size / l->stripe_unit; + u64 blockno; /* which su in the file (i.e. globally) */ + u32 blockoff; /* offset into su */ + u64 stripeno; /* which stripe */ + u32 stripepos; /* which su in the stripe, + which object in the object set */ + u64 objsetno; /* which object set */ + u32 objsetpos; /* which stripe in the object set */ + + blockno = div_u64_rem(off, l->stripe_unit, &blockoff); + stripeno = div_u64_rem(blockno, l->stripe_count, &stripepos); + objsetno = div_u64_rem(stripeno, stripes_per_object, &objsetpos); + + *objno = objsetno * l->stripe_count + stripepos; + *objoff = objsetpos * l->stripe_unit + blockoff; + *xlen = min_t(u64, len, l->stripe_unit - blockoff); +} +EXPORT_SYMBOL(ceph_calc_file_object_mapping); + /* * Return the last extent with given objno (@object_extents is sorted * by objno). If not found, return NULL and set @add_pos so that the -- cgit v1.2.3 From bb48bd4dc45f9ee1e44d8e9fcb01023e0d0ba80d Mon Sep 17 00:00:00 2001 From: Chengguang Xu Date: Tue, 13 Mar 2018 10:42:44 +0800 Subject: ceph: optimize memory usage In current code, regular file and directory use same struct ceph_file_info to store fs specific data so the struct has to include some fields which are only used for directory (e.g., readdir related info), when having plenty of regular files, it will lead to memory waste. This patch introduces dedicated ceph_dir_file_info cache for readdir related thins. So that regular file does not include those unused fields anymore. Signed-off-by: Chengguang Xu Reviewed-by: "Yan, Zheng" Signed-off-by: Ilya Dryomov --- fs/ceph/dir.c | 185 ++++++++++++++++++++++--------------------- fs/ceph/file.c | 88 ++++++++++++++------ fs/ceph/super.c | 8 ++ fs/ceph/super.h | 4 + include/linux/ceph/libceph.h | 1 + 5 files changed, 169 insertions(+), 117 deletions(-) (limited to 'include/linux') diff --git a/fs/ceph/dir.c b/fs/ceph/dir.c index 1aa3bfc9ef35..16405e0774a6 100644 --- a/fs/ceph/dir.c +++ b/fs/ceph/dir.c @@ -102,18 +102,18 @@ static int fpos_cmp(loff_t l, loff_t r) * regardless of what dir changes take place on the * server. */ -static int note_last_dentry(struct ceph_file_info *fi, const char *name, +static int note_last_dentry(struct ceph_dir_file_info *dfi, const char *name, int len, unsigned next_offset) { char *buf = kmalloc(len+1, GFP_KERNEL); if (!buf) return -ENOMEM; - kfree(fi->last_name); - fi->last_name = buf; - memcpy(fi->last_name, name, len); - fi->last_name[len] = 0; - fi->next_offset = next_offset; - dout("note_last_dentry '%s'\n", fi->last_name); + kfree(dfi->last_name); + dfi->last_name = buf; + memcpy(dfi->last_name, name, len); + dfi->last_name[len] = 0; + dfi->next_offset = next_offset; + dout("note_last_dentry '%s'\n", dfi->last_name); return 0; } @@ -175,7 +175,7 @@ __dcache_find_get_entry(struct dentry *parent, u64 idx, static int __dcache_readdir(struct file *file, struct dir_context *ctx, int shared_gen) { - struct ceph_file_info *fi = file->private_data; + struct ceph_dir_file_info *dfi = file->private_data; struct dentry *parent = file->f_path.dentry; struct inode *dir = d_inode(parent); struct dentry *dentry, *last = NULL; @@ -222,7 +222,7 @@ static int __dcache_readdir(struct file *file, struct dir_context *ctx, bool emit_dentry = false; dentry = __dcache_find_get_entry(parent, idx++, &cache_ctl); if (!dentry) { - fi->flags |= CEPH_F_ATEND; + dfi->file_info.flags |= CEPH_F_ATEND; err = 0; break; } @@ -273,33 +273,33 @@ out: if (last) { int ret; di = ceph_dentry(last); - ret = note_last_dentry(fi, last->d_name.name, last->d_name.len, + ret = note_last_dentry(dfi, last->d_name.name, last->d_name.len, fpos_off(di->offset) + 1); if (ret < 0) err = ret; dput(last); /* last_name no longer match cache index */ - if (fi->readdir_cache_idx >= 0) { - fi->readdir_cache_idx = -1; - fi->dir_release_count = 0; + if (dfi->readdir_cache_idx >= 0) { + dfi->readdir_cache_idx = -1; + dfi->dir_release_count = 0; } } return err; } -static bool need_send_readdir(struct ceph_file_info *fi, loff_t pos) +static bool need_send_readdir(struct ceph_dir_file_info *dfi, loff_t pos) { - if (!fi->last_readdir) + if (!dfi->last_readdir) return true; if (is_hash_order(pos)) - return !ceph_frag_contains_value(fi->frag, fpos_hash(pos)); + return !ceph_frag_contains_value(dfi->frag, fpos_hash(pos)); else - return fi->frag != fpos_frag(pos); + return dfi->frag != fpos_frag(pos); } static int ceph_readdir(struct file *file, struct dir_context *ctx) { - struct ceph_file_info *fi = file->private_data; + struct ceph_dir_file_info *dfi = file->private_data; struct inode *inode = file_inode(file); struct ceph_inode_info *ci = ceph_inode(inode); struct ceph_fs_client *fsc = ceph_inode_to_client(inode); @@ -310,7 +310,7 @@ static int ceph_readdir(struct file *file, struct dir_context *ctx) struct ceph_mds_reply_info_parsed *rinfo; dout("readdir %p file %p pos %llx\n", inode, file, ctx->pos); - if (fi->flags & CEPH_F_ATEND) + if (dfi->file_info.flags & CEPH_F_ATEND) return 0; /* always start with . and .. */ @@ -351,15 +351,15 @@ static int ceph_readdir(struct file *file, struct dir_context *ctx) /* proceed with a normal readdir */ more: /* do we have the correct frag content buffered? */ - if (need_send_readdir(fi, ctx->pos)) { + if (need_send_readdir(dfi, ctx->pos)) { struct ceph_mds_request *req; int op = ceph_snap(inode) == CEPH_SNAPDIR ? CEPH_MDS_OP_LSSNAP : CEPH_MDS_OP_READDIR; /* discard old result, if any */ - if (fi->last_readdir) { - ceph_mdsc_put_request(fi->last_readdir); - fi->last_readdir = NULL; + if (dfi->last_readdir) { + ceph_mdsc_put_request(dfi->last_readdir); + dfi->last_readdir = NULL; } if (is_hash_order(ctx->pos)) { @@ -373,7 +373,7 @@ more: } dout("readdir fetching %llx.%llx frag %x offset '%s'\n", - ceph_vinop(inode), frag, fi->last_name); + ceph_vinop(inode), frag, dfi->last_name); req = ceph_mdsc_create_request(mdsc, op, USE_AUTH_MDS); if (IS_ERR(req)) return PTR_ERR(req); @@ -389,8 +389,8 @@ more: __set_bit(CEPH_MDS_R_DIRECT_IS_HASH, &req->r_req_flags); req->r_inode_drop = CEPH_CAP_FILE_EXCL; } - if (fi->last_name) { - req->r_path2 = kstrdup(fi->last_name, GFP_KERNEL); + if (dfi->last_name) { + req->r_path2 = kstrdup(dfi->last_name, GFP_KERNEL); if (!req->r_path2) { ceph_mdsc_put_request(req); return -ENOMEM; @@ -400,10 +400,10 @@ more: cpu_to_le32(fpos_hash(ctx->pos)); } - req->r_dir_release_cnt = fi->dir_release_count; - req->r_dir_ordered_cnt = fi->dir_ordered_count; - req->r_readdir_cache_idx = fi->readdir_cache_idx; - req->r_readdir_offset = fi->next_offset; + req->r_dir_release_cnt = dfi->dir_release_count; + req->r_dir_ordered_cnt = dfi->dir_ordered_count; + req->r_readdir_cache_idx = dfi->readdir_cache_idx; + req->r_readdir_offset = dfi->next_offset; req->r_args.readdir.frag = cpu_to_le32(frag); req->r_args.readdir.flags = cpu_to_le16(CEPH_READDIR_REPLY_BITFLAGS); @@ -427,35 +427,35 @@ more: if (le32_to_cpu(rinfo->dir_dir->frag) != frag) { frag = le32_to_cpu(rinfo->dir_dir->frag); if (!rinfo->hash_order) { - fi->next_offset = req->r_readdir_offset; + dfi->next_offset = req->r_readdir_offset; /* adjust ctx->pos to beginning of frag */ ctx->pos = ceph_make_fpos(frag, - fi->next_offset, + dfi->next_offset, false); } } - fi->frag = frag; - fi->last_readdir = req; + dfi->frag = frag; + dfi->last_readdir = req; if (test_bit(CEPH_MDS_R_DID_PREPOPULATE, &req->r_req_flags)) { - fi->readdir_cache_idx = req->r_readdir_cache_idx; - if (fi->readdir_cache_idx < 0) { + dfi->readdir_cache_idx = req->r_readdir_cache_idx; + if (dfi->readdir_cache_idx < 0) { /* preclude from marking dir ordered */ - fi->dir_ordered_count = 0; + dfi->dir_ordered_count = 0; } else if (ceph_frag_is_leftmost(frag) && - fi->next_offset == 2) { + dfi->next_offset == 2) { /* note dir version at start of readdir so * we can tell if any dentries get dropped */ - fi->dir_release_count = req->r_dir_release_cnt; - fi->dir_ordered_count = req->r_dir_ordered_cnt; + dfi->dir_release_count = req->r_dir_release_cnt; + dfi->dir_ordered_count = req->r_dir_ordered_cnt; } } else { dout("readdir !did_prepopulate\n"); /* disable readdir cache */ - fi->readdir_cache_idx = -1; + dfi->readdir_cache_idx = -1; /* preclude from marking dir complete */ - fi->dir_release_count = 0; + dfi->dir_release_count = 0; } /* note next offset and last dentry name */ @@ -464,19 +464,19 @@ more: rinfo->dir_entries + (rinfo->dir_nr-1); unsigned next_offset = req->r_reply_info.dir_end ? 2 : (fpos_off(rde->offset) + 1); - err = note_last_dentry(fi, rde->name, rde->name_len, + err = note_last_dentry(dfi, rde->name, rde->name_len, next_offset); if (err) return err; } else if (req->r_reply_info.dir_end) { - fi->next_offset = 2; + dfi->next_offset = 2; /* keep last name */ } } - rinfo = &fi->last_readdir->r_reply_info; + rinfo = &dfi->last_readdir->r_reply_info; dout("readdir frag %x num %d pos %llx chunk first %llx\n", - fi->frag, rinfo->dir_nr, ctx->pos, + dfi->frag, rinfo->dir_nr, ctx->pos, rinfo->dir_nr ? rinfo->dir_entries[0].offset : 0LL); i = 0; @@ -520,52 +520,55 @@ more: ctx->pos++; } - ceph_mdsc_put_request(fi->last_readdir); - fi->last_readdir = NULL; + ceph_mdsc_put_request(dfi->last_readdir); + dfi->last_readdir = NULL; - if (fi->next_offset > 2) { - frag = fi->frag; + if (dfi->next_offset > 2) { + frag = dfi->frag; goto more; } /* more frags? */ - if (!ceph_frag_is_rightmost(fi->frag)) { - frag = ceph_frag_next(fi->frag); + if (!ceph_frag_is_rightmost(dfi->frag)) { + frag = ceph_frag_next(dfi->frag); if (is_hash_order(ctx->pos)) { loff_t new_pos = ceph_make_fpos(ceph_frag_value(frag), - fi->next_offset, true); + dfi->next_offset, true); if (new_pos > ctx->pos) ctx->pos = new_pos; /* keep last_name */ } else { - ctx->pos = ceph_make_fpos(frag, fi->next_offset, false); - kfree(fi->last_name); - fi->last_name = NULL; + ctx->pos = ceph_make_fpos(frag, dfi->next_offset, + false); + kfree(dfi->last_name); + dfi->last_name = NULL; } dout("readdir next frag is %x\n", frag); goto more; } - fi->flags |= CEPH_F_ATEND; + dfi->file_info.flags |= CEPH_F_ATEND; /* * if dir_release_count still matches the dir, no dentries * were released during the whole readdir, and we should have * the complete dir contents in our cache. */ - if (atomic64_read(&ci->i_release_count) == fi->dir_release_count) { + if (atomic64_read(&ci->i_release_count) == + dfi->dir_release_count) { spin_lock(&ci->i_ceph_lock); - if (fi->dir_ordered_count == atomic64_read(&ci->i_ordered_count)) { + if (dfi->dir_ordered_count == + atomic64_read(&ci->i_ordered_count)) { dout(" marking %p complete and ordered\n", inode); /* use i_size to track number of entries in * readdir cache */ - BUG_ON(fi->readdir_cache_idx < 0); - i_size_write(inode, fi->readdir_cache_idx * + BUG_ON(dfi->readdir_cache_idx < 0); + i_size_write(inode, dfi->readdir_cache_idx * sizeof(struct dentry*)); } else { dout(" marking %p complete\n", inode); } - __ceph_dir_set_complete(ci, fi->dir_release_count, - fi->dir_ordered_count); + __ceph_dir_set_complete(ci, dfi->dir_release_count, + dfi->dir_ordered_count); spin_unlock(&ci->i_ceph_lock); } @@ -573,25 +576,25 @@ more: return 0; } -static void reset_readdir(struct ceph_file_info *fi) +static void reset_readdir(struct ceph_dir_file_info *dfi) { - if (fi->last_readdir) { - ceph_mdsc_put_request(fi->last_readdir); - fi->last_readdir = NULL; + if (dfi->last_readdir) { + ceph_mdsc_put_request(dfi->last_readdir); + dfi->last_readdir = NULL; } - kfree(fi->last_name); - fi->last_name = NULL; - fi->dir_release_count = 0; - fi->readdir_cache_idx = -1; - fi->next_offset = 2; /* compensate for . and .. */ - fi->flags &= ~CEPH_F_ATEND; + kfree(dfi->last_name); + dfi->last_name = NULL; + dfi->dir_release_count = 0; + dfi->readdir_cache_idx = -1; + dfi->next_offset = 2; /* compensate for . and .. */ + dfi->file_info.flags &= ~CEPH_F_ATEND; } /* * discard buffered readdir content on seekdir(0), or seek to new frag, * or seek prior to current chunk */ -static bool need_reset_readdir(struct ceph_file_info *fi, loff_t new_pos) +static bool need_reset_readdir(struct ceph_dir_file_info *dfi, loff_t new_pos) { struct ceph_mds_reply_info_parsed *rinfo; loff_t chunk_offset; @@ -600,10 +603,10 @@ static bool need_reset_readdir(struct ceph_file_info *fi, loff_t new_pos) if (is_hash_order(new_pos)) { /* no need to reset last_name for a forward seek when * dentries are sotred in hash order */ - } else if (fi->frag != fpos_frag(new_pos)) { + } else if (dfi->frag != fpos_frag(new_pos)) { return true; } - rinfo = fi->last_readdir ? &fi->last_readdir->r_reply_info : NULL; + rinfo = dfi->last_readdir ? &dfi->last_readdir->r_reply_info : NULL; if (!rinfo || !rinfo->dir_nr) return true; chunk_offset = rinfo->dir_entries[0].offset; @@ -613,7 +616,7 @@ static bool need_reset_readdir(struct ceph_file_info *fi, loff_t new_pos) static loff_t ceph_dir_llseek(struct file *file, loff_t offset, int whence) { - struct ceph_file_info *fi = file->private_data; + struct ceph_dir_file_info *dfi = file->private_data; struct inode *inode = file->f_mapping->host; loff_t retval; @@ -631,20 +634,20 @@ static loff_t ceph_dir_llseek(struct file *file, loff_t offset, int whence) } if (offset >= 0) { - if (need_reset_readdir(fi, offset)) { + if (need_reset_readdir(dfi, offset)) { dout("dir_llseek dropping %p content\n", file); - reset_readdir(fi); + reset_readdir(dfi); } else if (is_hash_order(offset) && offset > file->f_pos) { /* for hash offset, we don't know if a forward seek * is within same frag */ - fi->dir_release_count = 0; - fi->readdir_cache_idx = -1; + dfi->dir_release_count = 0; + dfi->readdir_cache_idx = -1; } if (offset != file->f_pos) { file->f_pos = offset; file->f_version = 0; - fi->flags &= ~CEPH_F_ATEND; + dfi->file_info.flags &= ~CEPH_F_ATEND; } retval = offset; } @@ -1352,7 +1355,7 @@ static void ceph_d_prune(struct dentry *dentry) static ssize_t ceph_read_dir(struct file *file, char __user *buf, size_t size, loff_t *ppos) { - struct ceph_file_info *fi = file->private_data; + struct ceph_dir_file_info *dfi = file->private_data; struct inode *inode = file_inode(file); struct ceph_inode_info *ci = ceph_inode(inode); int left; @@ -1361,12 +1364,12 @@ static ssize_t ceph_read_dir(struct file *file, char __user *buf, size_t size, if (!ceph_test_mount_opt(ceph_sb_to_client(inode->i_sb), DIRSTAT)) return -EISDIR; - if (!fi->dir_info) { - fi->dir_info = kmalloc(bufsize, GFP_KERNEL); - if (!fi->dir_info) + if (!dfi->dir_info) { + dfi->dir_info = kmalloc(bufsize, GFP_KERNEL); + if (!dfi->dir_info) return -ENOMEM; - fi->dir_info_len = - snprintf(fi->dir_info, bufsize, + dfi->dir_info_len = + snprintf(dfi->dir_info, bufsize, "entries: %20lld\n" " files: %20lld\n" " subdirs: %20lld\n" @@ -1386,10 +1389,10 @@ static ssize_t ceph_read_dir(struct file *file, char __user *buf, size_t size, (long)ci->i_rctime.tv_nsec); } - if (*ppos >= fi->dir_info_len) + if (*ppos >= dfi->dir_info_len) return 0; - size = min_t(unsigned, size, fi->dir_info_len-*ppos); - left = copy_to_user(buf, fi->dir_info + *ppos, size); + size = min_t(unsigned, size, dfi->dir_info_len-*ppos); + left = copy_to_user(buf, dfi->dir_info + *ppos, size); if (left == size) return -EFAULT; *ppos += (size - left); diff --git a/fs/ceph/file.c b/fs/ceph/file.c index a1f0aee29c27..4a92acba1e9c 100644 --- a/fs/ceph/file.c +++ b/fs/ceph/file.c @@ -161,13 +161,50 @@ out: return req; } +static int ceph_init_file_info(struct inode *inode, struct file *file, + int fmode, bool isdir) +{ + struct ceph_file_info *fi; + + dout("%s %p %p 0%o (%s)\n", __func__, inode, file, + inode->i_mode, isdir ? "dir" : "regular"); + BUG_ON(inode->i_fop->release != ceph_release); + + if (isdir) { + struct ceph_dir_file_info *dfi = + kmem_cache_zalloc(ceph_dir_file_cachep, GFP_KERNEL); + if (!dfi) { + ceph_put_fmode(ceph_inode(inode), fmode); /* clean up */ + return -ENOMEM; + } + + file->private_data = dfi; + fi = &dfi->file_info; + dfi->next_offset = 2; + dfi->readdir_cache_idx = -1; + } else { + fi = kmem_cache_zalloc(ceph_file_cachep, GFP_KERNEL); + if (!fi) { + ceph_put_fmode(ceph_inode(inode), fmode); /* clean up */ + return -ENOMEM; + } + + file->private_data = fi; + } + + fi->fmode = fmode; + spin_lock_init(&fi->rw_contexts_lock); + INIT_LIST_HEAD(&fi->rw_contexts); + + return 0; +} + /* * initialize private struct file data. * if we fail, clean up by dropping fmode reference on the ceph_inode */ static int ceph_init_file(struct inode *inode, struct file *file, int fmode) { - struct ceph_file_info *fi; int ret = 0; switch (inode->i_mode & S_IFMT) { @@ -175,22 +212,10 @@ static int ceph_init_file(struct inode *inode, struct file *file, int fmode) ceph_fscache_register_inode_cookie(inode); ceph_fscache_file_set_cookie(inode, file); case S_IFDIR: - dout("init_file %p %p 0%o (regular)\n", inode, file, - inode->i_mode); - fi = kmem_cache_zalloc(ceph_file_cachep, GFP_KERNEL); - if (!fi) { - ceph_put_fmode(ceph_inode(inode), fmode); /* clean up */ - return -ENOMEM; - } - fi->fmode = fmode; - - spin_lock_init(&fi->rw_contexts_lock); - INIT_LIST_HEAD(&fi->rw_contexts); - - fi->next_offset = 2; - fi->readdir_cache_idx = -1; - file->private_data = fi; - BUG_ON(inode->i_fop->release != ceph_release); + ret = ceph_init_file_info(inode, file, fmode, + S_ISDIR(inode->i_mode)); + if (ret) + return ret; break; case S_IFLNK: @@ -462,16 +487,27 @@ out_acl: int ceph_release(struct inode *inode, struct file *file) { struct ceph_inode_info *ci = ceph_inode(inode); - struct ceph_file_info *fi = file->private_data; - dout("release inode %p file %p\n", inode, file); - ceph_put_fmode(ci, fi->fmode); - if (fi->last_readdir) - ceph_mdsc_put_request(fi->last_readdir); - kfree(fi->last_name); - kfree(fi->dir_info); - WARN_ON(!list_empty(&fi->rw_contexts)); - kmem_cache_free(ceph_file_cachep, fi); + if (S_ISDIR(inode->i_mode)) { + struct ceph_dir_file_info *dfi = file->private_data; + dout("release inode %p dir file %p\n", inode, file); + WARN_ON(!list_empty(&dfi->file_info.rw_contexts)); + + ceph_put_fmode(ci, dfi->file_info.fmode); + + if (dfi->last_readdir) + ceph_mdsc_put_request(dfi->last_readdir); + kfree(dfi->last_name); + kfree(dfi->dir_info); + kmem_cache_free(ceph_dir_file_cachep, dfi); + } else { + struct ceph_file_info *fi = file->private_data; + dout("release inode %p regular file %p\n", inode, file); + WARN_ON(!list_empty(&fi->rw_contexts)); + + ceph_put_fmode(ci, fi->fmode); + kmem_cache_free(ceph_file_cachep, fi); + } /* wake up anyone waiting for caps on this inode */ wake_up_all(&ci->i_cap_wq); diff --git a/fs/ceph/super.c b/fs/ceph/super.c index 9bf9e54259dd..0fc03c456c50 100644 --- a/fs/ceph/super.c +++ b/fs/ceph/super.c @@ -679,6 +679,7 @@ struct kmem_cache *ceph_cap_cachep; struct kmem_cache *ceph_cap_flush_cachep; struct kmem_cache *ceph_dentry_cachep; struct kmem_cache *ceph_file_cachep; +struct kmem_cache *ceph_dir_file_cachep; static void ceph_inode_init_once(void *foo) { @@ -715,6 +716,10 @@ static int __init init_caches(void) if (!ceph_file_cachep) goto bad_file; + ceph_dir_file_cachep = KMEM_CACHE(ceph_dir_file_info, SLAB_MEM_SPREAD); + if (!ceph_dir_file_cachep) + goto bad_dir_file; + error = ceph_fscache_register(); if (error) goto bad_fscache; @@ -722,6 +727,8 @@ static int __init init_caches(void) return 0; bad_fscache: + kmem_cache_destroy(ceph_dir_file_cachep); +bad_dir_file: kmem_cache_destroy(ceph_file_cachep); bad_file: kmem_cache_destroy(ceph_dentry_cachep); @@ -747,6 +754,7 @@ static void destroy_caches(void) kmem_cache_destroy(ceph_cap_flush_cachep); kmem_cache_destroy(ceph_dentry_cachep); kmem_cache_destroy(ceph_file_cachep); + kmem_cache_destroy(ceph_dir_file_cachep); ceph_fscache_unregister(); } diff --git a/fs/ceph/super.h b/fs/ceph/super.h index 1c2086e0fec2..ff49433014e9 100644 --- a/fs/ceph/super.h +++ b/fs/ceph/super.h @@ -671,6 +671,10 @@ struct ceph_file_info { spinlock_t rw_contexts_lock; struct list_head rw_contexts; +}; + +struct ceph_dir_file_info { + struct ceph_file_info file_info; /* readdir: position within the dir */ u32 frag; diff --git a/include/linux/ceph/libceph.h b/include/linux/ceph/libceph.h index c2ec44cf5098..49c93b9308d7 100644 --- a/include/linux/ceph/libceph.h +++ b/include/linux/ceph/libceph.h @@ -262,6 +262,7 @@ extern struct kmem_cache *ceph_cap_cachep; extern struct kmem_cache *ceph_cap_flush_cachep; extern struct kmem_cache *ceph_dentry_cachep; extern struct kmem_cache *ceph_file_cachep; +extern struct kmem_cache *ceph_dir_file_cachep; /* ceph_common.c */ extern bool libceph_compatible(void *data); -- cgit v1.2.3 From fb18a57568c2b84cd611e242c0f6fa97b45e4907 Mon Sep 17 00:00:00 2001 From: Luis Henriques Date: Fri, 5 Jan 2018 10:47:18 +0000 Subject: ceph: quota: add initial infrastructure to support cephfs quotas This patch adds the infrastructure required to support cephfs quotas as it is currently implemented in the ceph fuse client. Cephfs quotas can be set on any directory, and can restrict the number of bytes or the number of files stored beneath that point in the directory hierarchy. Quotas are set using the extended attributes 'ceph.quota.max_files' and 'ceph.quota.max_bytes', and can be removed by setting these attributes to '0'. Link: http://tracker.ceph.com/issues/22372 Signed-off-by: Luis Henriques Reviewed-by: "Yan, Zheng" Signed-off-by: Ilya Dryomov --- Documentation/filesystems/ceph.txt | 12 +++++++ fs/ceph/Makefile | 2 +- fs/ceph/inode.c | 6 ++++ fs/ceph/mds_client.c | 23 ++++++++++++++ fs/ceph/mds_client.h | 2 ++ fs/ceph/quota.c | 65 ++++++++++++++++++++++++++++++++++++++ fs/ceph/super.h | 8 +++++ fs/ceph/xattr.c | 44 ++++++++++++++++++++++++++ include/linux/ceph/ceph_features.h | 1 + include/linux/ceph/ceph_fs.h | 17 ++++++++++ net/ceph/ceph_common.c | 1 + 11 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 fs/ceph/quota.c (limited to 'include/linux') diff --git a/Documentation/filesystems/ceph.txt b/Documentation/filesystems/ceph.txt index 0b302a11718a..094772481263 100644 --- a/Documentation/filesystems/ceph.txt +++ b/Documentation/filesystems/ceph.txt @@ -62,6 +62,18 @@ subdirectories, and a summation of all nested file sizes. This makes the identification of large disk space consumers relatively quick, as no 'du' or similar recursive scan of the file system is required. +Finally, Ceph also allows quotas to be set on any directory in the system. +The quota can restrict the number of bytes or the number of files stored +beneath that point in the directory hierarchy. Quotas can be set using +extended attributes 'ceph.quota.max_files' and 'ceph.quota.max_bytes', eg: + + setfattr -n ceph.quota.max_bytes -v 100000000 /some/dir + getfattr -n ceph.quota.max_bytes /some/dir + +A limitation of the current quotas implementation is that it relies on the +cooperation of the client mounting the file system to stop writers when a +limit is reached. A modified or adversarial client cannot be prevented +from writing as much data as it needs. Mount Syntax ============ diff --git a/fs/ceph/Makefile b/fs/ceph/Makefile index 174f5709e508..a699e320393f 100644 --- a/fs/ceph/Makefile +++ b/fs/ceph/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_CEPH_FS) += ceph.o ceph-y := super.o inode.o dir.o file.o locks.o addr.o ioctl.o \ - export.o caps.o snap.o xattr.o \ + export.o caps.o snap.o xattr.o quota.o \ mds_client.o mdsmap.o strings.o ceph_frag.o \ debugfs.o diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c index be5f12d0d637..2c6f8be4ed63 100644 --- a/fs/ceph/inode.c +++ b/fs/ceph/inode.c @@ -441,6 +441,9 @@ struct inode *ceph_alloc_inode(struct super_block *sb) atomic64_set(&ci->i_complete_seq[1], 0); ci->i_symlink = NULL; + ci->i_max_bytes = 0; + ci->i_max_files = 0; + memset(&ci->i_dir_layout, 0, sizeof(ci->i_dir_layout)); RCU_INIT_POINTER(ci->i_layout.pool_ns, NULL); @@ -790,6 +793,9 @@ static int fill_inode(struct inode *inode, struct page *locked_page, inode->i_rdev = le32_to_cpu(info->rdev); inode->i_blkbits = fls(le32_to_cpu(info->layout.fl_stripe_unit)) - 1; + ci->i_max_bytes = iinfo->max_bytes; + ci->i_max_files = iinfo->max_files; + if ((new_version || (new_issued & CEPH_CAP_AUTH_SHARED)) && (issued & CEPH_CAP_AUTH_EXCL) == 0) { inode->i_mode = le32_to_cpu(info->mode); diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c index 537048b4a4d5..1c9877c1149f 100644 --- a/fs/ceph/mds_client.c +++ b/fs/ceph/mds_client.c @@ -100,6 +100,26 @@ static int parse_reply_info_in(void **p, void *end, } else info->inline_version = CEPH_INLINE_NONE; + if (features & CEPH_FEATURE_MDS_QUOTA) { + u8 struct_v, struct_compat; + u32 struct_len; + + /* + * both struct_v and struct_compat are expected to be >= 1 + */ + ceph_decode_8_safe(p, end, struct_v, bad); + ceph_decode_8_safe(p, end, struct_compat, bad); + if (!struct_v || !struct_compat) + goto bad; + ceph_decode_32_safe(p, end, struct_len, bad); + ceph_decode_need(p, end, struct_len, bad); + ceph_decode_64_safe(p, end, info->max_bytes, bad); + ceph_decode_64_safe(p, end, info->max_files, bad); + } else { + info->max_bytes = 0; + info->max_files = 0; + } + info->pool_ns_len = 0; info->pool_ns_data = NULL; if (features & CEPH_FEATURE_FS_FILE_LAYOUT_V2) { @@ -4082,6 +4102,9 @@ static void dispatch(struct ceph_connection *con, struct ceph_msg *msg) case CEPH_MSG_CLIENT_LEASE: handle_lease(mdsc, s, msg); break; + case CEPH_MSG_CLIENT_QUOTA: + ceph_handle_quota(mdsc, s, msg); + break; default: pr_err("received unknown message type %d %s\n", type, diff --git a/fs/ceph/mds_client.h b/fs/ceph/mds_client.h index 71e3b783ee6f..2a67c8b01ae6 100644 --- a/fs/ceph/mds_client.h +++ b/fs/ceph/mds_client.h @@ -49,6 +49,8 @@ struct ceph_mds_reply_info_in { char *inline_data; u32 pool_ns_len; char *pool_ns_data; + u64 max_bytes; + u64 max_files; }; struct ceph_mds_reply_dir_entry { diff --git a/fs/ceph/quota.c b/fs/ceph/quota.c new file mode 100644 index 000000000000..1b69d8365ec2 --- /dev/null +++ b/fs/ceph/quota.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * quota.c - CephFS quota + * + * Copyright (C) 2017-2018 SUSE + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "super.h" +#include "mds_client.h" + +void ceph_handle_quota(struct ceph_mds_client *mdsc, + struct ceph_mds_session *session, + struct ceph_msg *msg) +{ + struct super_block *sb = mdsc->fsc->sb; + struct ceph_mds_quota *h = msg->front.iov_base; + struct ceph_vino vino; + struct inode *inode; + struct ceph_inode_info *ci; + + if (msg->front.iov_len != sizeof(*h)) { + pr_err("%s corrupt message mds%d len %d\n", __func__, + session->s_mds, (int)msg->front.iov_len); + ceph_msg_dump(msg); + return; + } + + /* increment msg sequence number */ + mutex_lock(&session->s_mutex); + session->s_seq++; + mutex_unlock(&session->s_mutex); + + /* lookup inode */ + vino.ino = le64_to_cpu(h->ino); + vino.snap = CEPH_NOSNAP; + inode = ceph_find_inode(sb, vino); + if (!inode) { + pr_warn("Failed to find inode %llu\n", vino.ino); + return; + } + ci = ceph_inode(inode); + + spin_lock(&ci->i_ceph_lock); + ci->i_rbytes = le64_to_cpu(h->rbytes); + ci->i_rfiles = le64_to_cpu(h->rfiles); + ci->i_rsubdirs = le64_to_cpu(h->rsubdirs); + ci->i_max_bytes = le64_to_cpu(h->max_bytes); + ci->i_max_files = le64_to_cpu(h->max_files); + spin_unlock(&ci->i_ceph_lock); + + iput(inode); +} diff --git a/fs/ceph/super.h b/fs/ceph/super.h index ff49433014e9..0c95a929bab7 100644 --- a/fs/ceph/super.h +++ b/fs/ceph/super.h @@ -310,6 +310,9 @@ struct ceph_inode_info { u64 i_rbytes, i_rfiles, i_rsubdirs; u64 i_files, i_subdirs; + /* quotas */ + u64 i_max_bytes, i_max_files; + struct rb_root i_fragtree; int i_fragtree_nsplits; struct mutex i_fragtree_mutex; @@ -1070,4 +1073,9 @@ extern int ceph_locks_to_pagelist(struct ceph_filelock *flocks, extern int ceph_fs_debugfs_init(struct ceph_fs_client *client); extern void ceph_fs_debugfs_cleanup(struct ceph_fs_client *client); +/* quota.c */ +extern void ceph_handle_quota(struct ceph_mds_client *mdsc, + struct ceph_mds_session *session, + struct ceph_msg *msg); + #endif /* _FS_CEPH_SUPER_H */ diff --git a/fs/ceph/xattr.c b/fs/ceph/xattr.c index e1c4e0b12b4c..7e72348639e4 100644 --- a/fs/ceph/xattr.c +++ b/fs/ceph/xattr.c @@ -224,6 +224,31 @@ static size_t ceph_vxattrcb_dir_rctime(struct ceph_inode_info *ci, char *val, (long)ci->i_rctime.tv_nsec); } +/* quotas */ + +static bool ceph_vxattrcb_quota_exists(struct ceph_inode_info *ci) +{ + return (ci->i_max_files || ci->i_max_bytes); +} + +static size_t ceph_vxattrcb_quota(struct ceph_inode_info *ci, char *val, + size_t size) +{ + return snprintf(val, size, "max_bytes=%llu max_files=%llu", + ci->i_max_bytes, ci->i_max_files); +} + +static size_t ceph_vxattrcb_quota_max_bytes(struct ceph_inode_info *ci, + char *val, size_t size) +{ + return snprintf(val, size, "%llu", ci->i_max_bytes); +} + +static size_t ceph_vxattrcb_quota_max_files(struct ceph_inode_info *ci, + char *val, size_t size) +{ + return snprintf(val, size, "%llu", ci->i_max_files); +} #define CEPH_XATTR_NAME(_type, _name) XATTR_CEPH_PREFIX #_type "." #_name #define CEPH_XATTR_NAME2(_type, _name, _name2) \ @@ -247,6 +272,15 @@ static size_t ceph_vxattrcb_dir_rctime(struct ceph_inode_info *ci, char *val, .hidden = true, \ .exists_cb = ceph_vxattrcb_layout_exists, \ } +#define XATTR_QUOTA_FIELD(_type, _name) \ + { \ + .name = CEPH_XATTR_NAME(_type, _name), \ + .name_size = sizeof(CEPH_XATTR_NAME(_type, _name)), \ + .getxattr_cb = ceph_vxattrcb_ ## _type ## _ ## _name, \ + .readonly = false, \ + .hidden = true, \ + .exists_cb = ceph_vxattrcb_quota_exists, \ + } static struct ceph_vxattr ceph_dir_vxattrs[] = { { @@ -270,6 +304,16 @@ static struct ceph_vxattr ceph_dir_vxattrs[] = { XATTR_NAME_CEPH(dir, rsubdirs), XATTR_NAME_CEPH(dir, rbytes), XATTR_NAME_CEPH(dir, rctime), + { + .name = "ceph.quota", + .name_size = sizeof("ceph.quota"), + .getxattr_cb = ceph_vxattrcb_quota, + .readonly = false, + .hidden = true, + .exists_cb = ceph_vxattrcb_quota_exists, + }, + XATTR_QUOTA_FIELD(quota, max_bytes), + XATTR_QUOTA_FIELD(quota, max_files), { .name = NULL, 0 } /* Required table terminator */ }; static size_t ceph_dir_vxattrs_name_size; /* total size of all names */ diff --git a/include/linux/ceph/ceph_features.h b/include/linux/ceph/ceph_features.h index 59042d5ac520..3901927cf6a0 100644 --- a/include/linux/ceph/ceph_features.h +++ b/include/linux/ceph/ceph_features.h @@ -204,6 +204,7 @@ DEFINE_CEPH_FEATURE_DEPRECATED(63, 1, RESERVED_BROKEN, LUMINOUS) // client-facin CEPH_FEATURE_OSD_PRIMARY_AFFINITY | \ CEPH_FEATURE_MSGR_KEEPALIVE2 | \ CEPH_FEATURE_OSD_POOLRESEND | \ + CEPH_FEATURE_MDS_QUOTA | \ CEPH_FEATURE_CRUSH_V4 | \ CEPH_FEATURE_NEW_OSDOP_ENCODING | \ CEPH_FEATURE_SERVER_JEWEL | \ diff --git a/include/linux/ceph/ceph_fs.h b/include/linux/ceph/ceph_fs.h index 88dd51381aaf..7ecfc88314d8 100644 --- a/include/linux/ceph/ceph_fs.h +++ b/include/linux/ceph/ceph_fs.h @@ -134,6 +134,7 @@ struct ceph_dir_layout { #define CEPH_MSG_CLIENT_LEASE 0x311 #define CEPH_MSG_CLIENT_SNAP 0x312 #define CEPH_MSG_CLIENT_CAPRELEASE 0x313 +#define CEPH_MSG_CLIENT_QUOTA 0x314 /* pool ops */ #define CEPH_MSG_POOLOP_REPLY 48 @@ -807,4 +808,20 @@ struct ceph_mds_snap_realm { } __attribute__ ((packed)); /* followed by my snap list, then prior parent snap list */ +/* + * quotas + */ +struct ceph_mds_quota { + __le64 ino; /* ino */ + struct ceph_timespec rctime; + __le64 rbytes; /* dir stats */ + __le64 rfiles; + __le64 rsubdirs; + __u8 struct_v; /* compat */ + __u8 struct_compat; + __le32 struct_len; + __le64 max_bytes; /* quota max. bytes */ + __le64 max_files; /* quota max. files */ +} __attribute__ ((packed)); + #endif diff --git a/net/ceph/ceph_common.c b/net/ceph/ceph_common.c index c15e2699090c..ffbcc7f5e740 100644 --- a/net/ceph/ceph_common.c +++ b/net/ceph/ceph_common.c @@ -80,6 +80,7 @@ const char *ceph_msg_type_name(int type) case CEPH_MSG_CLIENT_REPLY: return "client_reply"; case CEPH_MSG_CLIENT_CAPS: return "client_caps"; case CEPH_MSG_CLIENT_CAPRELEASE: return "client_cap_release"; + case CEPH_MSG_CLIENT_QUOTA: return "client_quota"; case CEPH_MSG_CLIENT_SNAP: return "client_snap"; case CEPH_MSG_CLIENT_LEASE: return "client_lease"; case CEPH_MSG_POOLOP_REPLY: return "poolop_reply"; -- cgit v1.2.3 From 8ea229511e06f9635ecc338dcbe0db41a73623f0 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Mon, 2 Apr 2018 16:26:25 +0530 Subject: thermal: Add cooling device's statistics in sysfs This extends the sysfs interface for thermal cooling devices and exposes some pretty useful statistics. These statistics have proven to be quite useful specially while doing benchmarks related to the task scheduler, where we want to make sure that nothing has disrupted the test, specially the cooling device which may have put constraints on the CPUs. The information exposed here tells us to what extent the CPUs were constrained by the thermal framework. The write-only "reset" file is used to reset the statistics. The read-only "time_in_state_ms" file shows the time (in msec) spent by the device in the respective cooling states, and it prints one line per cooling state. The read-only "total_trans" file shows single positive integer value showing the total number of cooling state transitions the device has gone through since the time the cooling device is registered or the time when statistics were reset last. The read-only "trans_table" file shows a two dimensional matrix, where an entry (row i, column j) represents the number of transitions from State_i to State_j. This is how the directory structure looks like for a single cooling device: $ ls -R /sys/class/thermal/cooling_device0/ /sys/class/thermal/cooling_device0/: cur_state max_state power stats subsystem type uevent /sys/class/thermal/cooling_device0/power: autosuspend_delay_ms runtime_active_time runtime_suspended_time control runtime_status /sys/class/thermal/cooling_device0/stats: reset time_in_state_ms total_trans trans_table This is tested on ARM 64-bit Hisilicon hikey620 board running Ubuntu and ARM 64-bit Hisilicon hikey960 board running Android. Signed-off-by: Viresh Kumar Signed-off-by: Zhang Rui --- Documentation/thermal/sysfs-api.txt | 31 +++++ drivers/thermal/Kconfig | 7 ++ drivers/thermal/thermal_core.c | 3 +- drivers/thermal/thermal_core.h | 10 ++ drivers/thermal/thermal_helpers.c | 5 +- drivers/thermal/thermal_sysfs.c | 225 ++++++++++++++++++++++++++++++++++++ include/linux/thermal.h | 1 + 7 files changed, 280 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt index bb9a0a53e76b..911399730c1c 100644 --- a/Documentation/thermal/sysfs-api.txt +++ b/Documentation/thermal/sysfs-api.txt @@ -255,6 +255,7 @@ temperature) and throttle appropriate devices. 2. sysfs attributes structure RO read only value +WO write only value RW read/write value Thermal sysfs attributes will be represented under /sys/class/thermal. @@ -286,6 +287,11 @@ Thermal cooling device sys I/F, created once it's registered: |---type: Type of the cooling device(processor/fan/...) |---max_state: Maximum cooling state of the cooling device |---cur_state: Current cooling state of the cooling device + |---stats: Directory containing cooling device's statistics + |---stats/reset: Writing any value resets the statistics + |---stats/time_in_state_ms: Time (msec) spent in various cooling states + |---stats/total_trans: Total number of times cooling state is changed + |---stats/trans_table: Cooing state transition table Then next two dynamic attributes are created/removed in pairs. They represent @@ -490,6 +496,31 @@ cur_state - cur_state == max_state means the maximum cooling. RW, Required +stats/reset + Writing any value resets the cooling device's statistics. + WO, Required + +stats/time_in_state_ms: + The amount of time spent by the cooling device in various cooling + states. The output will have "